repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
wujique/stm32f407 | 4,899 | Utilities/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s | ;/*
; * FreeRTOS Kernel V10.0.0
; * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software. If you wish to use our Amazon
; * FreeRTOS name, please do so in a fair use way that does not cause confusion.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * http://www.FreeRTOS.org
; * http://aws.amazon.com/freertos
; *
; * 1 tab == 4 spaces!
; */
INCLUDE FreeRTOSConfig.h
INCLUDE portmacro.h
EXTERN vTaskSwitchContext
EXTERN ulPortYieldRequired
EXTERN ulPortInterruptNesting
EXTERN vApplicationIRQHandler
PUBLIC FreeRTOS_SWI_Handler
PUBLIC FreeRTOS_IRQ_Handler
PUBLIC vPortRestoreTaskContext
SYS_MODE EQU 0x1f
SVC_MODE EQU 0x13
IRQ_MODE EQU 0x12
SECTION .text:CODE:ROOT(2)
ARM
INCLUDE portASM.h
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; SVC handler is used to yield a task.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_SWI_Handler
PRESERVE8
; Save the context of the current task and select a new task to run.
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vPortRestoreTaskContext is used to start the scheduler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortRestoreTaskContext
PRESERVE8
; Switch to system mode
CPS #SYS_MODE
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; IRQ interrupt handler used when individual priorities cannot be masked
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_IRQ_Handler
PRESERVE8
; Return to the interrupted instruction.
SUB lr, lr, #4
; Push the return address and SPSR
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
; Change to supervisor mode to allow reentry.
CPS #SVC_MODE
; Push used registers.
PUSH {r0-r4, r12}
; Increment nesting count. r3 holds the address of ulPortInterruptNesting
; for future use. r1 holds the original ulPortInterruptNesting value for
; future use.
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use.
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
PUSH {r0-r4, lr}
; Call the port part specific handler.
LDR r0, =vApplicationIRQHandler
BLX r0
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
; Write to the EOI register.
LDR r4, =configEOI_ADDRESS
STR r0, [r4]
; Restore the old nesting count
STR r1, [r3]
; A context switch is never performed if the nesting count is not 0.
CMP r1, #0
BNE exit_without_switch
; Did the interrupt request a context switch? r1 holds the address of
; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
; use.
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch
; No context switch. Restore used registers, LR_irq and SPSR before
; returning.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit
; A context switch is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
; Restore used registers, LR-irq and SPSR before saving the context
; to the task stack.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
; Call the function that selects the new task to execute.
; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
; instructions, or 8 byte aligned stack allocated data. LR does not need
; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
LDR r0, =vTaskSwitchContext
BLX r0
; Restore the context of, and branch to, the task selected to execute next.
portRESTORE_CONTEXT
END
|
wujique/stm32f407 | 4,381 | Utilities/FreeRTOS/Source/portable/IAR/RX100/port_asm.s | /*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include "PriorityDefinitions.h"
PUBLIC _prvStartFirstTask
PUBLIC ___interrupt_27
EXTERN _pxCurrentTCB
EXTERN _vTaskSwitchContext
RSEG CODE:CODE(4)
_prvStartFirstTask:
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
SETPSW U
/* Obtain the location of the stack associated with which ever task
pxCurrentTCB is currently pointing to. */
MOV.L #_pxCurrentTCB, R15
MOV.L [R15], R15
MOV.L [R15], R0
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15
/* R1 to R15 - R0 is not included as it is the SP. */
POPM R1-R15
/* This pops the remaining registers. */
RTE
NOP
NOP
/*-----------------------------------------------------------*/
/* The software interrupt - overwrite the default 'weak' definition. */
___interrupt_27:
/* Re-enable interrupts. */
SETPSW I
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
PUSH.L R15
/* Read the user stack pointer. */
MVFC USP, R15
/* Move the address down to the data being moved. */
SUB #12, R15
MVTC R15, USP
/* Copy the data across, R15, then PC, then PSW. */
MOV.L [ R0 ], [ R15 ]
MOV.L 4[ R0 ], 4[ R15 ]
MOV.L 8[ R0 ], 8[ R15 ]
/* Move the interrupt stack pointer to its new correct position. */
ADD #12, R0
/* All the rest of the registers are saved directly to the user stack. */
SETPSW U
/* Save the rest of the general registers (R15 has been saved already). */
PUSHM R1-R14
/* Save the accumulator. */
MVFACHI R15
PUSH.L R15
/* Middle word. */
MVFACMI R15
/* Shifted left as it is restored to the low order word. */
SHLL #16, R15
PUSH.L R15
/* Save the stack pointer to the TCB. */
MOV.L #_pxCurrentTCB, R15
MOV.L [ R15 ], R15
MOV.L R0, [ R15 ]
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
/* Select the next task to run. */
BSR.A _vTaskSwitchContext
/* Reset the interrupt mask as no more data structure access is required. */
MVTIPL #configKERNEL_INTERRUPT_PRIORITY
/* Load the stack pointer of the task that is now selected as the Running
state task from its TCB. */
MOV.L #_pxCurrentTCB,R15
MOV.L [ R15 ], R15
MOV.L [ R15 ], R0
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
POP R15
MVTACLO R15
POP R15
MVTACHI R15
POPM R1-R15
RTE
NOP
NOP
/*-----------------------------------------------------------*/
END
|
wujique/stm32f407 | 5,300 | Utilities/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s | /*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC vPortEnableVFP
PUBLIC vPortRestoreContextOfFirstTask
PUBLIC xPortRaisePrivilege
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
isb
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r2, [r3]
/* Is the task using the FPU context? If so, push high vfp registers. */
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
/* Save the core registers. */
mrs r1, control
stmdb r0!, {r1, r4-r11, r14}
/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
dsb
isb
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r0, r3}
/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r0, [r1]
/* Move onto the second item in the TCB... */
add r1, r1, #4
/* Region Base Address register. */
ldr r2, =0xe000ed9c
/* Read 4 sets of MPU registers. */
ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. */
stmia r2!, {r4-r11}
/* Pop the registers that are not automatically saved on exception entry. */
ldmia r0!, {r3-r11, r14}
msr control, r3
/* Is the task using the FPU context? If so, pop the high vfp registers
too. */
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
bx r14
/*-----------------------------------------------------------*/
vPortSVCHandler:
#ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
#else
mrs r0, psp
#endif
b vPortSVCHandler_C
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Clear the bit that indicates the FPU is in use in case the FPU was used
before the scheduler was started - which would otherwise result in the
unnecessary leaving of space in the SVC stack for lazy saving of FPU
registers. */
mov r0, #0
msr control, r0
/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
svc 0
/*-----------------------------------------------------------*/
vPortRestoreContextOfFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Restore the context. */
ldr r3, =pxCurrentTCB
ldr r1, [r3]
/* The first item in the TCB is the task top of stack. */
ldr r0, [r1]
/* Move onto the second item in the TCB... */
add r1, r1, #4
/* Region Base Address register. */
ldr r2, =0xe000ed9c
/* Read 4 sets of MPU registers. */
ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. */
stmia r2!, {r4-r11}
/* Pop the registers that are not automatically saved on exception entry. */
ldmia r0!, {r3-r11, r14}
msr control, r3
/* Restore the task stack pointer. */
msr psp, r0
mov r0, #0
msr basepri, r0
bx r14
/*-----------------------------------------------------------*/
vPortEnableVFP
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
/*-----------------------------------------------------------*/
xPortRaisePrivilege
mrs r0, control
/* Is the task running privileged? */
tst r0, #1
itte ne
/* CONTROL[0]!=0, return false. */
movne r0, #0
/* Switch to privileged. */
svcne 2 /* 2 == portSVC_RAISE_PRIVILEGE */
/* CONTROL[0]==0, return true. */
moveq r0, #1
bx lr
END
|
wujique/stm32f407 | 4,267 | Utilities/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s | /*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN vPortYieldFromISR
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC vSetMSP
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC ulSetInterruptMaskFromISR
PUBLIC vClearInterruptMaskFromISR
/*-----------------------------------------------------------*/
vSetMSP
msr msp, r0
bx lr
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
ldr r2, [r3]
subs r0, r0, #32 /* Make space for the remaining low registers. */
str r0, [r2] /* Save the new top of stack. */
stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
mov r4, r8 /* Store the high registers. */
mov r5, r9
mov r6, r10
mov r7, r11
stmia r0!, {r4-r7}
push {r3, r14}
cpsid i
bl vTaskSwitchContext
cpsie i
pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
ldr r1, [r2]
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
adds r0, r0, #16 /* Move to the high registers. */
ldmia r0!, {r4-r7} /* Pop the high registers. */
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
msr psp, r0 /* Remember the new top of stack for the task. */
subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */
ldmia r0!, {r4-r7} /* Pop low registers. */
bx r3
/*-----------------------------------------------------------*/
vPortSVCHandler;
/* This function is no longer used, but retained for backward
compatibility. */
bx lr
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
table offset register that can be used to locate the initial stack value.
Not all M0 parts have the application vector table at address 0. */
ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
ldr r1, [r3]
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
movs r0, #2 /* Switch to the psp stack. */
msr CONTROL, r0
isb
pop {r0-r5} /* Pop the registers that are saved automatically. */
mov lr, r5 /* lr is now in r5. */
pop {r3} /* The return address is now in r3. */
pop {r2} /* Pop and discard the XPSR. */
cpsie i /* The first task has its context and interrupts can be enabled. */
bx r3 /* Jump to the user defined task code. */
/*-----------------------------------------------------------*/
ulSetInterruptMaskFromISR
mrs r0, PRIMASK
cpsid i
bx lr
/*-----------------------------------------------------------*/
vClearInterruptMaskFromISR
msr PRIMASK, r0
bx lr
END
|
wujique/stm32f407 | 5,176 | Utilities/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s | ;/*
; * FreeRTOS Kernel V10.0.0
; * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software. If you wish to use our Amazon
; * FreeRTOS name, please do so in a fair use way that does not cause confusion.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * http://www.FreeRTOS.org
; * http://aws.amazon.com/freertos
; *
; * 1 tab == 4 spaces!
; */
INCLUDE FreeRTOSConfig.h
INCLUDE portmacro.h
EXTERN vApplicationIRQHandler
EXTERN vTaskSwitchContext
EXTERN ulPortYieldRequired
EXTERN ulPortInterruptNesting
PUBLIC FreeRTOS_SWI_Handler
PUBLIC FreeRTOS_IRQ_Handler
PUBLIC vPortRestoreTaskContext
SYS_MODE EQU 0x1f
SVC_MODE EQU 0x13
IRQ_MODE EQU 0x12
SECTION .text:CODE:ROOT(2)
ARM
INCLUDE portASM.h
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; SVC handler is used to yield a task.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_SWI_Handler
PRESERVE8
; Save the context of the current task and select a new task to run.
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vPortRestoreTaskContext is used to start the scheduler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortRestoreTaskContext
; Switch to system mode
CPS #SYS_MODE
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; PL390 GIC interrupt handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_IRQ_Handler
; Return to the interrupted instruction.
SUB lr, lr, #4
; Push the return address and SPSR
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
; Change to supervisor mode to allow reentry.
CPS #SVC_MODE
; Push used registers.
PUSH {r0-r4, r12}
; Increment nesting count. r3 holds the address of ulPortInterruptNesting
; for future use. r1 holds the original ulPortInterruptNesting value for
; future use.
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
; Read value from the interrupt acknowledge register, which is stored in r0
; for future parameter and interrupt clearing use.
LDR r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS
LDR r0, [r2]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned?
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
; Call the interrupt handler. r4 is pushed to maintain alignment.
PUSH {r0-r4, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
; Write the value read from ICCIAR to ICCEOIR
LDR r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS
STR r0, [r4]
; Restore the old nesting count
STR r1, [r3]
; A context switch is never performed if the nesting count is not 0
CMP r1, #0
BNE exit_without_switch
; Did the interrupt request a context switch? r1 holds the address of
; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
; use.
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch
; No context switch. Restore used registers, LR_irq and SPSR before
; returning.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit
; A context switch is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
; Restore used registers, LR-irq and SPSR before saving the context
; to the task stack.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
; Call the function that selects the new task to execute.
; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
; instructions, or 8 byte aligned stack allocated data. LR does not need
; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
LDR r0, =vTaskSwitchContext
BLX r0
; Restore the context of, and branch to, the task selected to execute next.
portRESTORE_CONTEXT
END
|
wujique/stm32f407 | 5,199 | Utilities/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s | /*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include "PriorityDefinitions.h"
PUBLIC _prvStartFirstTask
PUBLIC ___interrupt_27
EXTERN _pxCurrentTCB
EXTERN _vTaskSwitchContext
RSEG CODE:CODE(4)
_prvStartFirstTask:
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
SETPSW U
/* Obtain the location of the stack associated with which ever task
pxCurrentTCB is currently pointing to. */
MOV.L #_pxCurrentTCB, R15
MOV.L [R15], R15
MOV.L [R15], R0
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A0
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A0
POP R15
/* Accumulator guard. */
MVTACGU R15, A0
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A1
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A1
POP R15
/* Accumulator guard. */
MVTACGU R15, A1
POP R15
/* Floating point status word. */
MVTC R15, FPSW
/* R1 to R15 - R0 is not included as it is the SP. */
POPM R1-R15
/* This pops the remaining registers. */
RTE
NOP
NOP
/*-----------------------------------------------------------*/
/* The software interrupt - overwrite the default 'weak' definition. */
___interrupt_27:
/* Re-enable interrupts. */
SETPSW I
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
PUSH.L R15
/* Read the user stack pointer. */
MVFC USP, R15
/* Move the address down to the data being moved. */
SUB #12, R15
MVTC R15, USP
/* Copy the data across, R15, then PC, then PSW. */
MOV.L [ R0 ], [ R15 ]
MOV.L 4[ R0 ], 4[ R15 ]
MOV.L 8[ R0 ], 8[ R15 ]
/* Move the interrupt stack pointer to its new correct position. */
ADD #12, R0
/* All the rest of the registers are saved directly to the user stack. */
SETPSW U
/* Save the rest of the general registers (R15 has been saved already). */
PUSHM R1-R14
/* Save the FPSW and accumulator. */
MVFC FPSW, R15
PUSH.L R15
MVFACGU #0, A1, R15
PUSH.L R15
MVFACHI #0, A1, R15
PUSH.L R15
/* Low order word. */
MVFACLO #0, A1, R15
PUSH.L R15
MVFACGU #0, A0, R15
PUSH.L R15
MVFACHI #0, A0, R15
PUSH.L R15
/* Low order word. */
MVFACLO #0, A0, R15
PUSH.L R15
/* Save the stack pointer to the TCB. */
MOV.L #_pxCurrentTCB, R15
MOV.L [ R15 ], R15
MOV.L R0, [ R15 ]
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
/* Select the next task to run. */
BSR.A _vTaskSwitchContext
/* Reset the interrupt mask as no more data structure access is required. */
MVTIPL #configKERNEL_INTERRUPT_PRIORITY
/* Load the stack pointer of the task that is now selected as the Running
state task from its TCB. */
MOV.L #_pxCurrentTCB,R15
MOV.L [ R15 ], R15
MOV.L [ R15 ], R0
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A0
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A0
POP R15
/* Accumulator guard. */
MVTACGU R15, A0
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A1
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A1
POP R15
/* Accumulator guard. */
MVTACGU R15, A1
POP R15
MVTC R15, FPSW
POPM R1-R15
RTE
NOP
NOP
/*-----------------------------------------------------------*/
END
|
wujique/stm32f407 | 2,924 | Utilities/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s | /*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
isb
ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
ldr r2, [r3]
stmdb r0!, {r4-r11} /* Save the remaining registers. */
str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
stmdb sp!, {r3, r14}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
dsb
isb
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r3, r14}
ldr r1, [r3]
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
ldmia r0!, {r4-r11} /* Pop the registers. */
msr psp, r0
isb
bx r14
/*-----------------------------------------------------------*/
vPortSVCHandler:
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
orr r14, r14, #13
bx r14
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Call SVC to start the first task, ensuring interrupts are enabled. */
cpsie i
cpsie f
dsb
isb
svc 0
END
|
wujique/stm32f407 | 3,850 | Utilities/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s | /*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC vPortEnableVFP
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
isb
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r2, [r3]
/* Is the task using the FPU context? If so, push high vfp registers. */
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
/* Save the core registers. */
stmdb r0!, {r4-r11, r14}
/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
cpsid i
msr basepri, r0
dsb
isb
cpsie i
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r0, r3}
/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
/* Is the task using the FPU context? If so, pop the high vfp registers
too. */
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
#if WORKAROUND_PMU_CM001 == 1
push { r14 }
pop { pc }
#endif
#endif
bx r14
/*-----------------------------------------------------------*/
vPortSVCHandler:
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
bx r14
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Clear the bit that indicates the FPU is in use in case the FPU was used
before the scheduler was started - which would otherwise result in the
unnecessary leaving of space in the SVC stack for lazy saving of FPU
registers. */
mov r0, #0
msr control, r0
/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
svc 0
/*-----------------------------------------------------------*/
vPortEnableVFP:
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
END
|
WukLab/LegoOS | 1,486 | arch/x86/boot/pmjump.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* The final jump to protected-mode
*/
#include <asm/boot.h>
#include <asm/segment.h>
#include <asm/processor-flags.h>
#include <lego/linkage.h>
.text
.code16
/*
* void protected_mode_jump(u32 entrypoint, u32 bootparams);
*/
GLOBAL(protected_mode_jump)
movl %edx, %esi # Pointer to boot_params table
xorl %ebx, %ebx
movw %cs, %bx
shll $4, %ebx
addl %ebx, 2f
jmp 1f # Short jump to serialize on 386/486
1:
movw $__BOOT_DS, %cx
movw $__BOOT_TSS, %di
movl %cr0, %edx
orb $X86_CR0_PE, %dl # Protected mode
movl %edx, %cr0
# Transition to 32-bit mode
.byte 0x66, 0xea # ljmpl opcode
2: .long in_pm32 # offset
.word __BOOT_CS # segment
ENDPROC(protected_mode_jump)
.code32
.section ".text32","ax"
GLOBAL(in_pm32)
# Set up data segments for flat 32-bit mode
movl %ecx, %ds
movl %ecx, %es
movl %ecx, %fs
movl %ecx, %gs
movl %ecx, %ss
# The 32-bit code sets up its own stack, but this way we do have
# a valid stack if some debugging hack wants to use it.
addl %ebx, %esp
# Set up TR to make Intel VT happy
ltr %di
# Clear registers to allow for future extensions to the
# 32-bit boot protocol
xorl %ecx, %ecx
xorl %edx, %edx
xorl %ebx, %ebx
xorl %ebp, %ebp
xorl %edi, %edi
# Set up LDTR to make Intel VT happy
lldt %cx
#
# Jump to protected-mode kernel, 0x100000
# which is the compressed/head_$(BITS).o
#
jmp *%eax
ENDPROC(in_pm32)
|
WukLab/LegoOS | 1,228 | arch/x86/boot/bioscall.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* "Glove box" for BIOS calls. Avoids the constant problems with BIOSes
* touching registers they shouldn't be.
*/
.code16
.section ".inittext","ax"
.globl intcall
.type intcall, @function
intcall:
/* Self-modify the INT instruction. Ugly, but works. */
cmpb %al, 3f
je 1f
movb %al, 3f
jmp 1f /* Synchronize pipeline */
1:
/* Save state */
pushfl
pushw %fs
pushw %gs
pushal
/* Copy input state to stack frame */
subw $44, %sp
movw %dx, %si
movw %sp, %di
movw $11, %cx
rep; movsd
/* Pop full state from the stack */
popal
popw %gs
popw %fs
popw %es
popw %ds
popfl
/* Actual INT */
.byte 0xcd /* INT opcode */
3: .byte 0
/* Push full state to the stack */
pushfl
pushw %ds
pushw %es
pushw %fs
pushw %gs
pushal
/* Re-establish C environment invariants */
cld
movzwl %sp, %esp
movw %cs, %ax
movw %ax, %ds
movw %ax, %es
/* Copy output state from stack frame */
movw 68(%esp), %di /* Original %cx == 3rd argument */
andw %di, %di
jz 4f
movw %sp, %si
movw $11, %cx
rep; movsd
4: addw $44, %sp
/* Restore state and return */
popal
popw %gs
popw %fs
popfl
retl
.size intcall, .-intcall
|
WukLab/LegoOS | 8,204 | arch/x86/boot/header.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This is the entry point of 16-bit setup kernel. It will do the necessary
* sanitary checking and initilization, then jumps to main() of setup.
*
* To fit with GRUB2+linux+x86 boot protocol, we have to have these stuff here.
* With this promise, we can install LegoOS image into /boot/ and add an entry
* to GRUB2 config file, then GRUB2 can boot LegoOS just like booting a linux.
* Besides, GRUB2 can pass command line parameters, initrd ptr and so on to us.
*/
#include "boot.h"
#include <asm/boot.h>
#include <asm/setup.h>
#include <asm/bootparam.h>
BOOTSEG = 0x07c0 # bootsect segment
SYSSEG = 0x1000 # system segment (obsolete)
#ifndef SVGA_MODE
#define SVGA_MODE ASK_VGA
#endif
#ifndef ROOT_RDONLY
#define ROOT_RDONLY 1
#endif
.code16
.section ".bstext", "ax"
.global bootsect_start
bootsect_start:
# Normalize the start address
ljmp $BOOTSEG, $start2
start2:
movw %cs, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
xorw %sp, %sp
sti
cld
movw $bugger_off_msg, %si
msg_loop:
lodsb
andb %al, %al
jz bs_die
movb $0xe, %ah
movw $7, %bx
int $0x10
jmp msg_loop
bs_die:
# Allow the user to press a key, then reboot
xorw %ax, %ax
int $0x16
int $0x19
# int 0x19 should never return.
# In case, invoke BIOS reset vector
ljmp $0xf000,$0xfff0
.section ".bsdata", "a"
bugger_off_msg:
.ascii "Use a boot loader.\r\n"
.ascii "\n"
.ascii "Remove disk and press any key to reboot...\r\n"
.byte 0
/*
* Kernel attributes; used by setup. (Still in the first 512-byte sector)
* Part 1 of the bootparam.header, from the old boot sector.
*/
.section ".header", "a"
.globl sentinel
sentinel: .byte 0xff, 0xff /* Used to detect broken loaders */
.globl hdr
hdr:
setup_sects: .byte 0 /* Filled in by build.c */
root_flags: .word ROOT_RDONLY
syssize: .long 0 /* Filled in by build.c */
ram_size: .word 0 /* Obsolete */
vid_mode: .word SVGA_MODE
root_dev: .word 0 /* Filled in by build.c */
boot_flag: .word 0xAA55
/*
* The second sector.
* offset 512, entry point
*/
.globl _start
_start:
# Explicitly enter this as bytes, or the assembler
# tries to generate a 3-byte jump here, which causes
# everything else to push off to the wrong offset.
.byte 0xeb # short (2-byte) jump
.byte start_of_setup-1f
1:
# Part 2 of the bootparam.header
.ascii "HdrS" # header signature
.word 0x020a # header version number
.globl realmode_swtch
realmode_swtch: .word 0, 0 # default_switch, SETUPSEG
start_sys_seg: .word SYSSEG # obsolete and meaningless, but just
# in case something decided to "use" it
.word kernel_version-512 # pointing to kernel version string
# above section of header is compatible
# with loadlin-1.5 (header v1.5). Don't
# change it.
type_of_loader: .byte 0 # 0 means ancient bootloader, newer
# bootloaders know to change this.
# See Documentation/x86/boot.txt for
# assigned ids
# flags, unused bits must be zero (RFU) bit within loadflags
loadflags:
.byte LOADED_HIGH # The kernel is to be loaded high
setup_move_size: .word 0x8000 # size to move, when setup is not
# loaded at 0x90000. We will move setup
# to 0x90000 then just before jumping
# into the kernel. However, only the
# loader knows how much data behind
# us also needs to be loaded.
code32_start: # here loaders can put a different
# start address for 32-bit code.
.long 0x100000 # 0x100000 = default for big kernel
ramdisk_image: .long 0 # address of loaded ramdisk image
# Here the loader puts the 32-bit
# address where it loaded the image.
# This only will be read by the kernel.
ramdisk_size: .long 0 # its size in bytes
bootsect_kludge:
.long 0 # obsolete
heap_end_ptr: .word __end+STACK_SIZE-512
# (Header version 0x0201 or later)
# space from here (exclusive) down to
# end of setup code can be used by setup
# for local heap purposes.
ext_loader_ver:
.byte 0 # Extended boot loader version
ext_loader_type:
.byte 0 # Extended boot loader type
cmd_line_ptr: .long 0 # (Header version 0x0202 or later)
# If nonzero, a 32-bit pointer
# to the kernel command line.
# The command line should be
# located between the start of
# setup and the end of low
# memory (0xa0000), or it may
# get overwritten before it
# gets read. If this field is
# used, there is no longer
# anything magical about the
# 0x90000 segment; the setup
# can be located anywhere in
# low memory 0x10000 or higher.
initrd_addr_max: .long 0x7fffffff
# (Header version 0x0203 or later)
# The highest safe address for
# the contents of an initrd
# The current kernel allows up to 4 GB,
# but leave it at 2 GB to avoid
# possible bootloader bugs.
kernel_alignment: .long CONFIG_PHYSICAL_ALIGN #physical addr alignment
#required for protected mode
#kernel
relocatable_kernel: .byte 0
#define MIN_KERNEL_ALIGN_LG2 21
min_alignment: .byte MIN_KERNEL_ALIGN_LG2 # minimum alignment
xloadflags:
#ifdef CONFIG_X86_64
# define XLF0 1 /* 64-bit kernel */
#else
# define XLF0 0
#endif
.word XLF0
cmdline_size: .long COMMAND_LINE_SIZE-1 #length of the command line,
#added with boot protocol
#version 2.06
hardware_subarch: .long 0 # subarchitecture, added with 2.07
# default to 0 for normal x86 PC
hardware_subarch_data: .quad 0
#define ZO_input_data 0
#define ZO_z_input_len 0
payload_offset: .long ZO_input_data
payload_length: .long ZO_z_input_len
setup_data: .quad 0 # 64-bit physical pointer to
# single linked list of
# struct setup_data
pref_address: .quad 0x100000 # preferred load addr
#define VO__text 0
#define VO__end 1
#define INIT_SIZE (VO__end - VO__text)
init_size: .long INIT_SIZE # kernel initialization size
handover_offset: .long 0 # Filled in by build.c
# End of part 2 header ###########################################
/*
* Assume we are loaded by GRUB2. The related code how grub will load
* LegoOS is in [grub-core/loader/i386/pc/linux.c] of grub source code tree.
*
* Normally,
* gs = fs = es = ds = ss = Segment
* cs = Segment + 0x20
* ip = 0
*
* where Segment is a safe value chosed by GRUB2, which is not necessary be
* the historical 0x9000.
*/
.section ".entrytext", "ax"
start_of_setup:
movw %ds, %ax
movw %ax, %es
cld
movw %ss, %dx
cmpw %ax, %dx # %ds == %ss?
movw %sp, %dx
je 2f # -> assume %sp is reasonably set
# Invalid %ss, make up a new stack
movw $__end, %dx
testb $CAN_USE_HEAP, loadflags
jz 1f
movw heap_end_ptr, %dx
1:
addw $STACK_SIZE, %dx
jnc 2f
xorw %dx, %dx # Avoid wraparound
2:
# Now %dx should point to the end of our stack space
andw $~3, %dx # dword align (might as well...)
jnz 3f
movw $0xfffc, %dx # Make sure we're not zero
3:
movw %ax, %ss # %ss = %ds = %es for sure
movzwl %dx, %esp # Clear upper half of %esp
sti # Now we should have a working stack
# We will have entered with %cs = %ds+0x20, normalize %cs so
# it is on par with the other segments.
pushw %ds
pushw $1f
lretw
1:
# Check the signature of the setup image
cmpl $0x5a5aaa55, setup_sig
jne setup_bad_signature
# zero the bss
movw $__bss_start, %di
movw $__end+3, %cx
xorl %eax, %eax
subw %di, %cx
shrw $2, %cx
rep; stosl
# Jump to C code, should never return
calll main
setup_bad_signature:
movw $setup_msg_sig, %si
setup_print:
lodsb
andb %al, %al
jz die
movb $0xe, %ah
movw $7, %bx
int $0x10
jmp setup_print
.globl die
.type die, @function
die:
hlt
jmp die
.size die, .-die
.section ".entrydata", "a"
setup_msg_sig:
.ascii "No setup signature found\r\n"
.ascii "\n"
.ascii "Press any key to reboot...\r\n"
.byte 0
|
WukLab/LegoOS | 3,573 | arch/x86/lib/memmove_64.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <lego/linkage.h>
#include <asm/alternative-asm.h>
#include <asm/processor-features.h>
#undef memmove
/*
* Implement memmove(). This can handle overlap between src and dst.
*
* Input:
* rdi: dest
* rsi: src
* rdx: count
*
* Output:
* rax: dest
*/
.weak memmove
ENTRY(memmove)
ENTRY(__memmove)
/* Handle more 32 bytes in loop */
mov %rdi, %rax
cmp $0x20, %rdx
jb 1f
/* Decide forward/backward copy mode */
cmp %rdi, %rsi
jge .Lmemmove_begin_forward
mov %rsi, %r8
add %rdx, %r8
cmp %rdi, %r8
jg 2f
.Lmemmove_begin_forward:
ALTERNATIVE "", "movq %rdx, %rcx; rep movsb; retq", X86_FEATURE_ERMS
/*
* movsq instruction have many startup latency
* so we handle small size by general register.
*/
cmp $680, %rdx
jb 3f
/*
* movsq instruction is only good for aligned case.
*/
cmpb %dil, %sil
je 4f
3:
sub $0x20, %rdx
/*
* We gobble 32 bytes forward in each loop.
*/
5:
sub $0x20, %rdx
movq 0*8(%rsi), %r11
movq 1*8(%rsi), %r10
movq 2*8(%rsi), %r9
movq 3*8(%rsi), %r8
leaq 4*8(%rsi), %rsi
movq %r11, 0*8(%rdi)
movq %r10, 1*8(%rdi)
movq %r9, 2*8(%rdi)
movq %r8, 3*8(%rdi)
leaq 4*8(%rdi), %rdi
jae 5b
addq $0x20, %rdx
jmp 1f
/*
* Handle data forward by movsq.
*/
.p2align 4
4:
movq %rdx, %rcx
movq -8(%rsi, %rdx), %r11
lea -8(%rdi, %rdx), %r10
shrq $3, %rcx
rep movsq
movq %r11, (%r10)
jmp 13f
.Lmemmove_end_forward:
/*
* Handle data backward by movsq.
*/
.p2align 4
7:
movq %rdx, %rcx
movq (%rsi), %r11
movq %rdi, %r10
leaq -8(%rsi, %rdx), %rsi
leaq -8(%rdi, %rdx), %rdi
shrq $3, %rcx
std
rep movsq
cld
movq %r11, (%r10)
jmp 13f
/*
* Start to prepare for backward copy.
*/
.p2align 4
2:
cmp $680, %rdx
jb 6f
cmp %dil, %sil
je 7b
6:
/*
* Calculate copy position to tail.
*/
addq %rdx, %rsi
addq %rdx, %rdi
subq $0x20, %rdx
/*
* We gobble 32 bytes backward in each loop.
*/
8:
subq $0x20, %rdx
movq -1*8(%rsi), %r11
movq -2*8(%rsi), %r10
movq -3*8(%rsi), %r9
movq -4*8(%rsi), %r8
leaq -4*8(%rsi), %rsi
movq %r11, -1*8(%rdi)
movq %r10, -2*8(%rdi)
movq %r9, -3*8(%rdi)
movq %r8, -4*8(%rdi)
leaq -4*8(%rdi), %rdi
jae 8b
/*
* Calculate copy position to head.
*/
addq $0x20, %rdx
subq %rdx, %rsi
subq %rdx, %rdi
1:
cmpq $16, %rdx
jb 9f
/*
* Move data from 16 bytes to 31 bytes.
*/
movq 0*8(%rsi), %r11
movq 1*8(%rsi), %r10
movq -2*8(%rsi, %rdx), %r9
movq -1*8(%rsi, %rdx), %r8
movq %r11, 0*8(%rdi)
movq %r10, 1*8(%rdi)
movq %r9, -2*8(%rdi, %rdx)
movq %r8, -1*8(%rdi, %rdx)
jmp 13f
.p2align 4
9:
cmpq $8, %rdx
jb 10f
/*
* Move data from 8 bytes to 15 bytes.
*/
movq 0*8(%rsi), %r11
movq -1*8(%rsi, %rdx), %r10
movq %r11, 0*8(%rdi)
movq %r10, -1*8(%rdi, %rdx)
jmp 13f
10:
cmpq $4, %rdx
jb 11f
/*
* Move data from 4 bytes to 7 bytes.
*/
movl (%rsi), %r11d
movl -4(%rsi, %rdx), %r10d
movl %r11d, (%rdi)
movl %r10d, -4(%rdi, %rdx)
jmp 13f
11:
cmp $2, %rdx
jb 12f
/*
* Move data from 2 bytes to 3 bytes.
*/
movw (%rsi), %r11w
movw -2(%rsi, %rdx), %r10w
movw %r11w, (%rdi)
movw %r10w, -2(%rdi, %rdx)
jmp 13f
12:
cmp $1, %rdx
jb 13f
/*
* Move data for 1 byte.
*/
movb (%rsi), %r11b
movb %r11b, (%rdi)
13:
retq
ENDPROC(__memmove)
ENDPROC(memmove)
|
WukLab/LegoOS | 8,797 | arch/x86/lib/uaccess.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <lego/errno.h>
#include <lego/linkage.h>
#include <asm/asm.h>
#include <asm/percpu.h>
#include <asm/extable.h>
#include <asm/thread_info.h>
#include <asm/alternative-asm.h>
#include <asm/processor-features.h>
#include <generated/asm-offsets.h>
/* Standard copy_to_user with segment limit checking */
ENTRY(_copy_to_user)
mov PER_CPU_VAR(current_task), %rax
movq %rdi,%rcx
addq %rdx,%rcx
jc bad_to_user
cmpq TASK_addr_limit(%rax),%rcx
ja bad_to_user
ALTERNATIVE_2 "jmp copy_user_generic_unrolled", \
"jmp copy_user_generic_string", \
X86_FEATURE_REP_GOOD, \
"jmp copy_user_enhanced_fast_string", \
X86_FEATURE_ERMS
ENDPROC(_copy_to_user)
/* Standard copy_from_user with segment limit checking */
ENTRY(_copy_from_user)
mov PER_CPU_VAR(current_task), %rax
movq %rsi,%rcx
addq %rdx,%rcx
jc bad_from_user
cmpq TASK_addr_limit(%rax),%rcx
ja bad_from_user
ALTERNATIVE_2 "jmp copy_user_generic_unrolled", \
"jmp copy_user_generic_string", \
X86_FEATURE_REP_GOOD, \
"jmp copy_user_enhanced_fast_string", \
X86_FEATURE_ERMS
ENDPROC(_copy_from_user)
.section .fixup,"ax"
/* must zero dest */
ENTRY(bad_from_user)
bad_from_user:
movl %edx,%ecx
xorl %eax,%eax
rep
stosb
bad_to_user:
movl %edx,%eax
ret
ENDPROC(bad_from_user)
.previous
/*
* copy_user_generic_unrolled - memory copy with exception handling.
* This version is for CPUs like P4 that don't have efficient micro
* code for rep movsq
*
* Input:
* rdi destination
* rsi source
* rdx count
*
* Output:
* eax uncopied bytes or 0 if successful.
*/
ENTRY(copy_user_generic_unrolled)
ASM_STAC
cmpl $8,%edx
jb 20f /* less then 8 bytes, go to byte copy loop */
ALIGN_DESTINATION
movl %edx,%ecx
andl $63,%edx
shrl $6,%ecx
jz 17f
1: movq (%rsi),%r8
2: movq 1*8(%rsi),%r9
3: movq 2*8(%rsi),%r10
4: movq 3*8(%rsi),%r11
5: movq %r8,(%rdi)
6: movq %r9,1*8(%rdi)
7: movq %r10,2*8(%rdi)
8: movq %r11,3*8(%rdi)
9: movq 4*8(%rsi),%r8
10: movq 5*8(%rsi),%r9
11: movq 6*8(%rsi),%r10
12: movq 7*8(%rsi),%r11
13: movq %r8,4*8(%rdi)
14: movq %r9,5*8(%rdi)
15: movq %r10,6*8(%rdi)
16: movq %r11,7*8(%rdi)
leaq 64(%rsi),%rsi
leaq 64(%rdi),%rdi
decl %ecx
jnz 1b
17: movl %edx,%ecx
andl $7,%edx
shrl $3,%ecx
jz 20f
18: movq (%rsi),%r8
19: movq %r8,(%rdi)
leaq 8(%rsi),%rsi
leaq 8(%rdi),%rdi
decl %ecx
jnz 18b
20: andl %edx,%edx
jz 23f
movl %edx,%ecx
21: movb (%rsi),%al
22: movb %al,(%rdi)
incq %rsi
incq %rdi
decl %ecx
jnz 21b
23: xor %eax,%eax
ASM_CLAC
ret
.section .fixup,"ax"
30: shll $6,%ecx
addl %ecx,%edx
jmp 60f
40: leal (%rdx,%rcx,8),%edx
jmp 60f
50: movl %ecx,%edx
60: jmp copy_user_handle_tail /* ecx is zerorest also */
.previous
_ASM_EXTABLE(1b,30b)
_ASM_EXTABLE(2b,30b)
_ASM_EXTABLE(3b,30b)
_ASM_EXTABLE(4b,30b)
_ASM_EXTABLE(5b,30b)
_ASM_EXTABLE(6b,30b)
_ASM_EXTABLE(7b,30b)
_ASM_EXTABLE(8b,30b)
_ASM_EXTABLE(9b,30b)
_ASM_EXTABLE(10b,30b)
_ASM_EXTABLE(11b,30b)
_ASM_EXTABLE(12b,30b)
_ASM_EXTABLE(13b,30b)
_ASM_EXTABLE(14b,30b)
_ASM_EXTABLE(15b,30b)
_ASM_EXTABLE(16b,30b)
_ASM_EXTABLE(18b,40b)
_ASM_EXTABLE(19b,40b)
_ASM_EXTABLE(21b,50b)
_ASM_EXTABLE(22b,50b)
ENDPROC(copy_user_generic_unrolled)
/* Some CPUs run faster using the string copy instructions.
* This is also a lot simpler. Use them when possible.
*
* Only 4GB of copy is supported. This shouldn't be a problem
* because the kernel normally only writes from/to page sized chunks
* even if user space passed a longer buffer.
* And more would be dangerous because both Intel and AMD have
* errata with rep movsq > 4GB. If someone feels the need to fix
* this please consider this.
*
* Input:
* rdi destination
* rsi source
* rdx count
*
* Output:
* eax uncopied bytes or 0 if successful.
*/
ENTRY(copy_user_generic_string)
ASM_STAC
cmpl $8,%edx
jb 2f /* less than 8 bytes, go to byte copy loop */
ALIGN_DESTINATION
movl %edx,%ecx
shrl $3,%ecx
andl $7,%edx
1: rep
movsq
2: movl %edx,%ecx
3: rep
movsb
xorl %eax,%eax
ASM_CLAC
ret
.section .fixup,"ax"
11: leal (%rdx,%rcx,8),%ecx
12: movl %ecx,%edx /* ecx is zerorest also */
jmp copy_user_handle_tail
.previous
_ASM_EXTABLE(1b,11b)
_ASM_EXTABLE(3b,12b)
ENDPROC(copy_user_generic_string)
/*
* Some CPUs are adding enhanced REP MOVSB/STOSB instructions.
* It's recommended to use enhanced REP MOVSB/STOSB if it's enabled.
*
* Input:
* rdi destination
* rsi source
* rdx count
*
* Output:
* eax uncopied bytes or 0 if successful.
*/
ENTRY(copy_user_enhanced_fast_string)
ASM_STAC
movl %edx,%ecx
1: rep
movsb
xorl %eax,%eax
ASM_CLAC
ret
.section .fixup,"ax"
12: movl %ecx,%edx /* ecx is zerorest also */
jmp copy_user_handle_tail
.previous
_ASM_EXTABLE(1b,12b)
ENDPROC(copy_user_enhanced_fast_string)
/*
* copy_user_nocache - Uncached memory copy with exception handling
* This will force destination out of cache for more performance.
*
* Note: Cached memory copy is used when destination or size is not
* naturally aligned. That is:
* - Require 8-byte alignment when size is 8 bytes or larger.
* - Require 4-byte alignment when size is 4 bytes.
*/
ENTRY(__copy_user_nocache)
ASM_STAC
/* If size is less than 8 bytes, go to 4-byte copy */
cmpl $8,%edx
jb .L_4b_nocache_copy_entry
/* If destination is not 8-byte aligned, "cache" copy to align it */
ALIGN_DESTINATION
/* Set 4x8-byte copy count and remainder */
movl %edx,%ecx
andl $63,%edx
shrl $6,%ecx
jz .L_8b_nocache_copy_entry /* jump if count is 0 */
/* Perform 4x8-byte nocache loop-copy */
.L_4x8b_nocache_copy_loop:
1: movq (%rsi),%r8
2: movq 1*8(%rsi),%r9
3: movq 2*8(%rsi),%r10
4: movq 3*8(%rsi),%r11
5: movnti %r8,(%rdi)
6: movnti %r9,1*8(%rdi)
7: movnti %r10,2*8(%rdi)
8: movnti %r11,3*8(%rdi)
9: movq 4*8(%rsi),%r8
10: movq 5*8(%rsi),%r9
11: movq 6*8(%rsi),%r10
12: movq 7*8(%rsi),%r11
13: movnti %r8,4*8(%rdi)
14: movnti %r9,5*8(%rdi)
15: movnti %r10,6*8(%rdi)
16: movnti %r11,7*8(%rdi)
leaq 64(%rsi),%rsi
leaq 64(%rdi),%rdi
decl %ecx
jnz .L_4x8b_nocache_copy_loop
/* Set 8-byte copy count and remainder */
.L_8b_nocache_copy_entry:
movl %edx,%ecx
andl $7,%edx
shrl $3,%ecx
jz .L_4b_nocache_copy_entry /* jump if count is 0 */
/* Perform 8-byte nocache loop-copy */
.L_8b_nocache_copy_loop:
20: movq (%rsi),%r8
21: movnti %r8,(%rdi)
leaq 8(%rsi),%rsi
leaq 8(%rdi),%rdi
decl %ecx
jnz .L_8b_nocache_copy_loop
/* If no byte left, we're done */
.L_4b_nocache_copy_entry:
andl %edx,%edx
jz .L_finish_copy
/* If destination is not 4-byte aligned, go to byte copy: */
movl %edi,%ecx
andl $3,%ecx
jnz .L_1b_cache_copy_entry
/* Set 4-byte copy count (1 or 0) and remainder */
movl %edx,%ecx
andl $3,%edx
shrl $2,%ecx
jz .L_1b_cache_copy_entry /* jump if count is 0 */
/* Perform 4-byte nocache copy: */
30: movl (%rsi),%r8d
31: movnti %r8d,(%rdi)
leaq 4(%rsi),%rsi
leaq 4(%rdi),%rdi
/* If no bytes left, we're done: */
andl %edx,%edx
jz .L_finish_copy
/* Perform byte "cache" loop-copy for the remainder */
.L_1b_cache_copy_entry:
movl %edx,%ecx
.L_1b_cache_copy_loop:
40: movb (%rsi),%al
41: movb %al,(%rdi)
incq %rsi
incq %rdi
decl %ecx
jnz .L_1b_cache_copy_loop
/* Finished copying; fence the prior stores */
.L_finish_copy:
xorl %eax,%eax
ASM_CLAC
sfence
ret
.section .fixup,"ax"
.L_fixup_4x8b_copy:
shll $6,%ecx
addl %ecx,%edx
jmp .L_fixup_handle_tail
.L_fixup_8b_copy:
lea (%rdx,%rcx,8),%rdx
jmp .L_fixup_handle_tail
.L_fixup_4b_copy:
lea (%rdx,%rcx,4),%rdx
jmp .L_fixup_handle_tail
.L_fixup_1b_copy:
movl %ecx,%edx
.L_fixup_handle_tail:
sfence
jmp copy_user_handle_tail
.previous
_ASM_EXTABLE(1b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(2b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(3b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(4b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(5b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(6b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(7b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(8b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(9b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(10b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(11b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(12b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(13b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(14b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(15b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(16b,.L_fixup_4x8b_copy)
_ASM_EXTABLE(20b,.L_fixup_8b_copy)
_ASM_EXTABLE(21b,.L_fixup_8b_copy)
_ASM_EXTABLE(30b,.L_fixup_4b_copy)
_ASM_EXTABLE(31b,.L_fixup_4b_copy)
_ASM_EXTABLE(40b,.L_fixup_1b_copy)
_ASM_EXTABLE(41b,.L_fixup_1b_copy)
ENDPROC(__copy_user_nocache)
|
WukLab/LegoOS | 3,805 | arch/x86/lib/rwsem.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/*
* x86 semaphore implementation.
*
* (C) Copyright 1999 Linus Torvalds
*
* Portions Copyright 1999 Red Hat, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* rw semaphores implemented November 1999 by Benjamin LaHaise <bcrl@kvack.org>
*/
#include <lego/linkage.h>
#include <asm/frame.h>
#include <asm/alternative-asm.h>
#define __ASM_HALF_REG(reg) __ASM_SEL(reg, e##reg)
#define __ASM_HALF_SIZE(inst) __ASM_SEL(inst##w, inst##l)
#ifdef CONFIG_X86_32
/*
* The semaphore operations have a special calling sequence that
* allow us to do a simpler in-line version of them. These routines
* need to convert that sequence back into the C sequence when
* there is contention on the semaphore.
*
* %eax contains the semaphore pointer on entry. Save the C-clobbered
* registers (%eax, %edx and %ecx) except %eax which is either a return
* value or just gets clobbered. Same is true for %edx so make sure GCC
* reloads it after the slow path, by making it hold a temporary, for
* example see ____down_write().
*/
#define save_common_regs \
pushl %ecx
#define restore_common_regs \
popl %ecx
/* Avoid uglifying the argument copying x86-64 needs to do. */
.macro movq src, dst
.endm
#else
/*
* x86-64 rwsem wrappers
*
* This interfaces the inline asm code to the slow-path
* C routines. We need to save the call-clobbered regs
* that the asm does not mark as clobbered, and move the
* argument from %rax to %rdi.
*
* NOTE! We don't need to save %rax, because the functions
* will always return the semaphore pointer in %rax (which
* is also the input argument to these helpers)
*
* The following can clobber %rdx because the asm clobbers it:
* call_rwsem_down_write_failed
* call_rwsem_wake
* but %rdi, %rsi, %rcx, %r8-r11 always need saving.
*/
#define save_common_regs \
pushq %rdi; \
pushq %rsi; \
pushq %rcx; \
pushq %r8; \
pushq %r9; \
pushq %r10; \
pushq %r11
#define restore_common_regs \
popq %r11; \
popq %r10; \
popq %r9; \
popq %r8; \
popq %rcx; \
popq %rsi; \
popq %rdi
#endif
/* Fix up special calling conventions */
ENTRY(call_rwsem_down_read_failed)
FRAME_BEGIN
save_common_regs
__ASM_SIZE(push,) %__ASM_REG(dx)
movq %rax,%rdi
call rwsem_down_read_failed
__ASM_SIZE(pop,) %__ASM_REG(dx)
restore_common_regs
FRAME_END
ret
ENDPROC(call_rwsem_down_read_failed)
ENTRY(call_rwsem_down_write_failed)
FRAME_BEGIN
save_common_regs
movq %rax,%rdi
call rwsem_down_write_failed
restore_common_regs
FRAME_END
ret
ENDPROC(call_rwsem_down_write_failed)
ENTRY(call_rwsem_down_write_failed_killable)
FRAME_BEGIN
save_common_regs
movq %rax,%rdi
call rwsem_down_write_failed_killable
restore_common_regs
FRAME_END
ret
ENDPROC(call_rwsem_down_write_failed_killable)
ENTRY(call_rwsem_wake)
FRAME_BEGIN
/* do nothing if still outstanding active readers */
__ASM_HALF_SIZE(dec) %__ASM_HALF_REG(dx)
jnz 1f
save_common_regs
movq %rax,%rdi
call rwsem_wake
restore_common_regs
1: FRAME_END
ret
ENDPROC(call_rwsem_wake)
ENTRY(call_rwsem_downgrade_wake)
FRAME_BEGIN
save_common_regs
__ASM_SIZE(push,) %__ASM_REG(dx)
movq %rax,%rdi
call rwsem_downgrade_wake
__ASM_SIZE(pop,) %__ASM_REG(dx)
restore_common_regs
FRAME_END
ret
ENDPROC(call_rwsem_downgrade_wake)
|
WukLab/LegoOS | 2,943 | arch/x86/lib/memset_64.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <lego/linkage.h>
#include <asm/alternative-asm.h>
#include <asm/processor-features.h>
.weak memset
/*
* ISO C memset - set a memory block to a byte value. This function uses fast
* string to get better performance than the original function. The code is
* simpler and shorter than the original function as well.
*
* rdi destination
* rsi value (char)
* rdx count (bytes)
*
* rax original destination
*/
ENTRY(memset)
ENTRY(__memset)
/*
* Some CPUs support enhanced REP MOVSB/STOSB feature. It is recommended
* to use it when possible. If not available, use fast string instructions.
*
* Otherwise, use original memset function.
*/
ALTERNATIVE_2 "jmp memset_orig", "", X86_FEATURE_REP_GOOD, \
"jmp memset_erms", X86_FEATURE_ERMS
movq %rdi,%r9
movq %rdx,%rcx
andl $7,%edx
shrq $3,%rcx
/* expand byte value */
movzbl %sil,%esi
movabs $0x0101010101010101,%rax
imulq %rsi,%rax
rep stosq
movl %edx,%ecx
rep stosb
movq %r9,%rax
ret
ENDPROC(memset)
ENDPROC(__memset)
/*
* ISO C memset - set a memory block to a byte value. This function uses
* enhanced rep stosb to override the fast string function.
* The code is simpler and shorter than the fast string function as well.
*
* rdi destination
* rsi value (char)
* rdx count (bytes)
*
* rax original destination
*/
ENTRY(memset_erms)
movq %rdi,%r9
movb %sil,%al
movq %rdx,%rcx
rep stosb
movq %r9,%rax
ret
ENDPROC(memset_erms)
ENTRY(memset_orig)
movq %rdi,%r10
/* expand byte value */
movzbl %sil,%ecx
movabs $0x0101010101010101,%rax
imulq %rcx,%rax
/* align dst */
movl %edi,%r9d
andl $7,%r9d
jnz .Lbad_alignment
.Lafter_bad_alignment:
movq %rdx,%rcx
shrq $6,%rcx
jz .Lhandle_tail
.p2align 4
.Lloop_64:
decq %rcx
movq %rax,(%rdi)
movq %rax,8(%rdi)
movq %rax,16(%rdi)
movq %rax,24(%rdi)
movq %rax,32(%rdi)
movq %rax,40(%rdi)
movq %rax,48(%rdi)
movq %rax,56(%rdi)
leaq 64(%rdi),%rdi
jnz .Lloop_64
/* Handle tail in loops. The loops should be faster than hard
to predict jump tables. */
.p2align 4
.Lhandle_tail:
movl %edx,%ecx
andl $63&(~7),%ecx
jz .Lhandle_7
shrl $3,%ecx
.p2align 4
.Lloop_8:
decl %ecx
movq %rax,(%rdi)
leaq 8(%rdi),%rdi
jnz .Lloop_8
.Lhandle_7:
andl $7,%edx
jz .Lende
.p2align 4
.Lloop_1:
decl %edx
movb %al,(%rdi)
leaq 1(%rdi),%rdi
jnz .Lloop_1
.Lende:
movq %r10,%rax
ret
.Lbad_alignment:
cmpq $7,%rdx
jbe .Lhandle_7
movq %rax,(%rdi) /* unaligned store */
movq $8,%r8
subq %r9,%r8
addq %r8,%rdi
subq %r8,%rdx
jmp .Lafter_bad_alignment
.Lfinal:
ENDPROC(memset_orig)
|
WukLab/LegoOS | 2,831 | arch/x86/lib/getuser.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/*
* __get_user functions.
*
* (C) Copyright 1998 Linus Torvalds
* (C) Copyright 2005 Andi Kleen
* (C) Copyright 2008 Glauber Costa
*
* These functions have a non-standard call interface
* to make them more efficient, especially as they
* return an error value in addition to the "real"
* return value.
*/
/*
* __get_user_X
*
* Inputs: %[r|e]ax contains the address.
*
* Outputs: %[r|e]ax is error code (0 or -EFAULT)
* %[r|e]dx contains zero-extended value
* %ecx contains the high half for 32-bit __get_user_8
*
*
* These functions should not modify any other registers,
* as they get called from within inline assembly.
*/
#include <lego/errno.h>
#include <lego/linkage.h>
#include <asm/percpu.h>
#include <asm/asm.h>
#include <asm/extable.h>
#include <asm/thread_info.h>
#include <generated/asm-offsets.h>
.text
ENTRY(__get_user_1)
mov PER_CPU_VAR(current_task), %_ASM_DX
cmp TASK_addr_limit(%_ASM_DX),%_ASM_AX
jae bad_get_user
ASM_STAC
1: movzbl (%_ASM_AX),%edx
xor %eax,%eax
ASM_CLAC
ret
ENDPROC(__get_user_1)
ENTRY(__get_user_2)
add $1,%_ASM_AX
jc bad_get_user
mov PER_CPU_VAR(current_task), %_ASM_DX
cmp TASK_addr_limit(%_ASM_DX),%_ASM_AX
jae bad_get_user
ASM_STAC
2: movzwl -1(%_ASM_AX),%edx
xor %eax,%eax
ASM_CLAC
ret
ENDPROC(__get_user_2)
ENTRY(__get_user_4)
add $3,%_ASM_AX
jc bad_get_user
mov PER_CPU_VAR(current_task), %_ASM_DX
cmp TASK_addr_limit(%_ASM_DX),%_ASM_AX
jae bad_get_user
ASM_STAC
3: movl -3(%_ASM_AX),%edx
xor %eax,%eax
ASM_CLAC
ret
ENDPROC(__get_user_4)
ENTRY(__get_user_8)
#ifdef CONFIG_X86_64
add $7,%_ASM_AX
jc bad_get_user
mov PER_CPU_VAR(current_task), %_ASM_DX
cmp TASK_addr_limit(%_ASM_DX),%_ASM_AX
jae bad_get_user
ASM_STAC
4: movq -7(%_ASM_AX),%rdx
xor %eax,%eax
ASM_CLAC
ret
#else
add $7,%_ASM_AX
jc bad_get_user_8
mov PER_CPU_VAR(current_task), %_ASM_DX
cmp TASK_addr_limit(%_ASM_DX),%_ASM_AX
jae bad_get_user_8
ASM_STAC
4: movl -7(%_ASM_AX),%edx
5: movl -3(%_ASM_AX),%ecx
xor %eax,%eax
ASM_CLAC
ret
#endif
ENDPROC(__get_user_8)
bad_get_user:
xor %edx,%edx
mov $(-EFAULT),%_ASM_AX
ASM_CLAC
ret
END(bad_get_user)
#ifdef CONFIG_X86_32
bad_get_user_8:
xor %edx,%edx
xor %ecx,%ecx
mov $(-EFAULT),%_ASM_AX
ASM_CLAC
ret
END(bad_get_user_8)
#endif
_ASM_EXTABLE(1b,bad_get_user)
_ASM_EXTABLE(2b,bad_get_user)
_ASM_EXTABLE(3b,bad_get_user)
#ifdef CONFIG_X86_64
_ASM_EXTABLE(4b,bad_get_user)
#else
_ASM_EXTABLE(4b,bad_get_user_8)
_ASM_EXTABLE(5b,bad_get_user_8)
#endif
|
WukLab/LegoOS | 1,944 | arch/x86/lib/putuser.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <lego/errno.h>
#include <lego/linkage.h>
#include <asm/percpu.h>
#include <asm/asm.h>
#include <asm/extable.h>
#include <asm/thread_info.h>
#include <generated/asm-offsets.h>
/*
* __put_user_X
*
* Inputs: %eax[:%edx] contains the data
* %ecx contains the address
*
* Outputs: %eax is error code (0 or -EFAULT)
*
* These functions should not modify any other registers,
* as they get called from within inline assembly.
*/
#define ENTER mov PER_CPU_VAR(current_task), %_ASM_BX
#define EXIT ASM_CLAC ; \
ret
.text
ENTRY(__put_user_1)
ENTER
cmp TASK_addr_limit(%_ASM_BX),%_ASM_CX
jae bad_put_user
ASM_STAC
1: movb %al,(%_ASM_CX)
xor %eax,%eax
EXIT
ENDPROC(__put_user_1)
ENTRY(__put_user_2)
ENTER
mov TASK_addr_limit(%_ASM_BX),%_ASM_BX
sub $1,%_ASM_BX
cmp %_ASM_BX,%_ASM_CX
jae bad_put_user
ASM_STAC
2: movw %ax,(%_ASM_CX)
xor %eax,%eax
EXIT
ENDPROC(__put_user_2)
ENTRY(__put_user_4)
ENTER
mov TASK_addr_limit(%_ASM_BX),%_ASM_BX
sub $3,%_ASM_BX
cmp %_ASM_BX,%_ASM_CX
jae bad_put_user
ASM_STAC
3: movl %eax,(%_ASM_CX)
xor %eax,%eax
EXIT
ENDPROC(__put_user_4)
ENTRY(__put_user_8)
ENTER
mov TASK_addr_limit(%_ASM_BX),%_ASM_BX
sub $7,%_ASM_BX
cmp %_ASM_BX,%_ASM_CX
jae bad_put_user
ASM_STAC
4: mov %_ASM_AX,(%_ASM_CX)
#ifdef CONFIG_X86_32
5: movl %edx,4(%_ASM_CX)
#endif
xor %eax,%eax
EXIT
ENDPROC(__put_user_8)
bad_put_user:
movl $-EFAULT,%eax
EXIT
END(bad_put_user)
_ASM_EXTABLE(1b,bad_put_user)
_ASM_EXTABLE(2b,bad_put_user)
_ASM_EXTABLE(3b,bad_put_user)
_ASM_EXTABLE(4b,bad_put_user)
#ifdef CONFIG_X86_32
_ASM_EXTABLE(5b,bad_put_user)
#endif
|
WukLab/LegoOS | 3,633 | arch/x86/lib/memcpy_64.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <lego/linkage.h>
#include <asm/alternative-asm.h>
#include <asm/processor-features.h>
/*
* We build a jump to memcpy_orig by default which gets NOPped out on
* the majority of x86 CPUs which set REP_GOOD. In addition, CPUs which
* have the enhanced REP MOVSB/STOSB feature (ERMS), change those NOPs
* to a jmp to memcpy_erms which does the REP; MOVSB mem copy.
*/
.weak memcpy
/*
* memcpy - Copy a memory block.
*
* Input:
* rdi destination
* rsi source
* rdx count
*
* Output:
* rax original destination
*/
ENTRY(__memcpy)
ENTRY(memcpy)
ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \
"jmp memcpy_erms", X86_FEATURE_ERMS
movq %rdi, %rax
movq %rdx, %rcx
shrq $3, %rcx
andl $7, %edx
rep movsq
movl %edx, %ecx
rep movsb
ret
ENDPROC(memcpy)
ENDPROC(__memcpy)
/*
* memcpy_erms() - enhanced fast string memcpy. This is faster and
* simpler than memcpy. Use memcpy_erms when possible.
*/
ENTRY(memcpy_erms)
movq %rdi, %rax
movq %rdx, %rcx
rep movsb
ret
ENDPROC(memcpy_erms)
ENTRY(memcpy_orig)
movq %rdi, %rax
cmpq $0x20, %rdx
jb .Lhandle_tail
/*
* We check whether memory false dependence could occur,
* then jump to corresponding copy mode.
*/
cmp %dil, %sil
jl .Lcopy_backward
subq $0x20, %rdx
.Lcopy_forward_loop:
subq $0x20, %rdx
/*
* Move in blocks of 4x8 bytes:
*/
movq 0*8(%rsi), %r8
movq 1*8(%rsi), %r9
movq 2*8(%rsi), %r10
movq 3*8(%rsi), %r11
leaq 4*8(%rsi), %rsi
movq %r8, 0*8(%rdi)
movq %r9, 1*8(%rdi)
movq %r10, 2*8(%rdi)
movq %r11, 3*8(%rdi)
leaq 4*8(%rdi), %rdi
jae .Lcopy_forward_loop
addl $0x20, %edx
jmp .Lhandle_tail
.Lcopy_backward:
/*
* Calculate copy position to tail.
*/
addq %rdx, %rsi
addq %rdx, %rdi
subq $0x20, %rdx
/*
* At most 3 ALU operations in one cycle,
* so append NOPS in the same 16 bytes trunk.
*/
.p2align 4
.Lcopy_backward_loop:
subq $0x20, %rdx
movq -1*8(%rsi), %r8
movq -2*8(%rsi), %r9
movq -3*8(%rsi), %r10
movq -4*8(%rsi), %r11
leaq -4*8(%rsi), %rsi
movq %r8, -1*8(%rdi)
movq %r9, -2*8(%rdi)
movq %r10, -3*8(%rdi)
movq %r11, -4*8(%rdi)
leaq -4*8(%rdi), %rdi
jae .Lcopy_backward_loop
/*
* Calculate copy position to head.
*/
addl $0x20, %edx
subq %rdx, %rsi
subq %rdx, %rdi
.Lhandle_tail:
cmpl $16, %edx
jb .Lless_16bytes
/*
* Move data from 16 bytes to 31 bytes.
*/
movq 0*8(%rsi), %r8
movq 1*8(%rsi), %r9
movq -2*8(%rsi, %rdx), %r10
movq -1*8(%rsi, %rdx), %r11
movq %r8, 0*8(%rdi)
movq %r9, 1*8(%rdi)
movq %r10, -2*8(%rdi, %rdx)
movq %r11, -1*8(%rdi, %rdx)
retq
.p2align 4
.Lless_16bytes:
cmpl $8, %edx
jb .Lless_8bytes
/*
* Move data from 8 bytes to 15 bytes.
*/
movq 0*8(%rsi), %r8
movq -1*8(%rsi, %rdx), %r9
movq %r8, 0*8(%rdi)
movq %r9, -1*8(%rdi, %rdx)
retq
.p2align 4
.Lless_8bytes:
cmpl $4, %edx
jb .Lless_3bytes
/*
* Move data from 4 bytes to 7 bytes.
*/
movl (%rsi), %ecx
movl -4(%rsi, %rdx), %r8d
movl %ecx, (%rdi)
movl %r8d, -4(%rdi, %rdx)
retq
.p2align 4
.Lless_3bytes:
subl $1, %edx
jb .Lend
/*
* Move data from 1 bytes to 3 bytes.
*/
movzbl (%rsi), %ecx
jz .Lstore_1byte
movzbq 1(%rsi), %r8
movzbq (%rsi, %rdx), %r9
movb %r8b, 1(%rdi)
movb %r9b, (%rdi, %rdx)
.Lstore_1byte:
movb %cl, (%rdi)
.Lend:
retq
ENDPROC(memcpy_orig)
|
WukLab/LegoOS | 16,110 | arch/x86/entry/entry_64.S | /*
* entry.S contains the system-call and fault low-level handling routines.
*
* A note on terminology:
* - iret frame: Architecture defined interrupt frame from SS to RIP
* at the top of the kernel process stack.
*
* Some macro usage:
* - ENTRY/END: Define functions in the symbol table.
* - IDT_ENTRY: Define exception entry points.
* - INTERRUPT: Define interrupt entry points
*/
#include <asm/asm.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/percpu.h>
#include <asm/segment.h>
#include <asm/extable.h>
#include <asm/alternative-asm.h>
#include <asm/irq_vectors.h>
#include <asm/thread_info.h>
#include <asm/processor-flags.h>
#include <asm/processor-features-flags.h>
#include <lego/errno.h>
#include <lego/linkage.h>
#include <generated/asm-offsets.h>
#include "abi.h"
ENTRY(ignore_sysret)
mov $-ENOSYS, %eax
sysret
END(ignore_sysret)
#define SWAPGS swapgs
/*
* 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
*
* This is the only entry point used for 64-bit system calls. The
* hardware interface is reasonably well designed and the register to
* argument mapping Linux uses fits well with the registers that are
* available when SYSCALL is used.
*
* SYSCALL instructions can be found inlined in libc implementations as
* well as some other programs and libraries. There are also a handful
* of SYSCALL instructions in the vDSO used, for example, as a
* clock_gettimeofday fallback.
*
* 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
* then loads new ss, cs, and rip from previously programmed MSRs.
* rflags gets masked by a value from another MSR (so CLD and CLAC
* are not needed). SYSCALL does not save anything on the stack
* and does not change rsp.
*
* Registers on entry:
* rax system call number
* rcx return address
* r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
* rdi arg0
* rsi arg1
* rdx arg2
* r10 arg3 (needs to be moved to rcx to conform to C ABI)
* r8 arg4
* r9 arg5
* (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
*
* Only called from user space.
*
* When user can change pt_regs->foo always force IRET. That is because
* it deals with uncanonical addresses better. SYSRET has trouble
* with them due to bugs in both AMD and Intel CPUs.
*/
/* Interrupts are off on entry */
ENTRY(entry_SYSCALL_64)
SWAPGS
/*
* SYSCALL does not change rsp for us!
* Save the previous rsp and load the top of kernel stack.
* It must be the top of kernel stack, since we came here
* from *userspace*.
*/
movq %rsp, PER_CPU_VAR(rsp_scratch)
movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
/*
* Construct struct pt_regs on stack
*
* In any syscall handler, you can use
* current_pt_regs()
* to get these registers.
*/
pushq $__USER_DS /* pt_regs->ss */
pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
pushq %r11 /* pt_regs->flags */
pushq $__USER_CS /* pt_regs->cs */
pushq %rcx /* pt_regs->ip */
pushq %rax /* pt_regs->orig_ax */
pushq %rdi /* pt_regs->di */
pushq %rsi /* pt_regs->si */
pushq %rdx /* pt_regs->dx */
pushq %rcx /* pt_regs->cx */
pushq $-ENOSYS /* pt_regs->ax */
pushq %r8 /* pt_regs->r8 */
pushq %r9 /* pt_regs->r9 */
pushq %r10 /* pt_regs->r10 */
pushq %r11 /* pt_regs->r11 */
sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 */
/*
* TODO:
* Lego uses the SYSCALL slowpath compared with Linux
* This may have performance issues.
*/
entry_SYSCALL64_slow_path:
/* IRQs are off. */
SAVE_EXTRA_REGS
movq %rsp, %rdi
call do_syscall_64 /* return with IRQs disabled */
return_from_SYSCALL_64:
RESTORE_EXTRA_REGS
/*
* Try to use SYSRET instead of IRET if we're returning to
* a completely clean 64-bit userspace context.
*/
movq RCX(%rsp), %rcx
movq RIP(%rsp), %r11
cmpq %rcx, %r11 /* RCX == RIP */
jne opportunistic_sysret_failed
/*
* On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
* in kernel space. This essentially lets the user take over
* the kernel, since userspace controls RSP.
*
* If width of "canonical tail" ever becomes variable, this will need
* to be updated to remain correct on both old and new CPUs.
*/
.ifne __VIRTUAL_MASK_SHIFT - 47
.error "virtual address width changed -- SYSRET checks need update"
.endif
/* Change top 16 bits to be the sign-extension of 47th bit */
shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
/* If this changed %rcx, it was not canonical */
cmpq %rcx, %r11
jne opportunistic_sysret_failed
cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
jne opportunistic_sysret_failed
movq R11(%rsp), %r11
cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
jne opportunistic_sysret_failed
/*
* SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
* restore RF properly. If the slowpath sets it for whatever reason, we
* need to restore it correctly.
*
* SYSRET can restore TF, but unlike IRET, restoring TF results in a
* trap from userspace immediately after SYSRET. This would cause an
* infinite loop whenever #DB happens with register state that satisfies
* the opportunistic SYSRET conditions. For example, single-stepping
* this user code:
*
* movq $stuck_here, %rcx
* pushfq
* popq %r11
* stuck_here:
*
* would never get past 'stuck_here'.
*/
testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
jnz opportunistic_sysret_failed
/* nothing to check for RSP */
cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
jne opportunistic_sysret_failed
/*
* We win! This label is here just for ease of understanding
* perf profiles. Nothing jumps here.
*/
syscall_return_via_sysret:
/* rcx and r11 are already restored (see code above) */
RESTORE_C_REGS_EXCEPT_RCX_R11
movq RSP(%rsp), %rsp
SWAPGS
sysretq
opportunistic_sysret_failed:
SWAPGS
jmp restore_c_regs_and_iret
END(entry_SYSCALL_64)
/*
* Reload gs selector with exception handling
* edi: new selector
*/
ENTRY(native_load_gs_index)
pushfq
cli
SWAPGS
.Lgs_change:
movl %edi, %gs
2:
SWAPGS
popfq
ret
END(native_load_gs_index)
_ASM_EXTABLE(.Lgs_change, bad_gs)
.section .fixup, "ax"
/* running with kernelgs */
bad_gs:
SWAPGS /* switch back to user gs */
.macro ZAP_GS
/* This can't be a string because the preprocessor needs to see it. */
movl $__USER_DS, %eax
movl %eax, %gs
.endm
ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
xorl %eax, %eax
movl %eax, %gs
jmp 2b
.previous
/*
* IDT_ENTRY - Intel Reserved Vector Handler
* Corresponding to Intel's software developer manual, e.g. page fault.
*/
.macro IDT_ENTRY sym do_sym has_error_code:req
ENTRY(\sym)
.ifeq \has_error_code
pushq $-1 /* ORIG_RAX: no syscall to restart */
.endif
/*
* Save all registers in pt_regs
*/
ALLOC_PT_GPREGS_ON_STACK
call error_entry
/* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
movq %rsp, %rdi /* pt_regs pointer */
.if \has_error_code
movq ORIG_RAX(%rsp), %rsi /* get error code */
movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
.else
xorl %esi, %esi /* no error code */
.endif
call \do_sym
jmp error_exit
END(\sym)
.endm
/*
* Save all registers in pt_regs, and switch gs if needed.
* Return: EBX=0: came from user mode; EBX=1: otherwise
*/
ENTRY(error_entry)
cld
SAVE_C_REGS 8 /* offset 8 due to [call error_entry] pushes */
SAVE_EXTRA_REGS 8
xorl %ebx, %ebx
testb $3, CS+8(%rsp)
jz .Lerror_kernelspace
/*
* We entered from user mode or we're pretending to have entered
* from user mode due to an IRET fault.
*/
SWAPGS
.Lerror_entry_from_usermode_after_swapgs:
ret
.Lerror_entry_done:
ret
/*
* There are two places in the kernel that can potentially fault with
* usergs. Handle them here. B stepping K8s sometimes report a
* truncated RIP for IRET exceptions returning to compat mode. Check
* for these here too.
*/
.Lerror_kernelspace:
incl %ebx
leaq native_irq_return_iret(%rip), %rcx
cmpq %rcx, RIP+8(%rsp)
je .Lerror_bad_iret
movl %ecx, %eax /* zero extend */
cmpq %rax, RIP+8(%rsp)
je .Lbstep_iret
cmpq $.Lgs_change, RIP+8(%rsp)
jne .Lerror_entry_done
/*
* hack: .Lgs_change can fail with user gsbase. If this happens, fix up
* gsbase and proceed. We'll fix up the exception and land in
* .Lgs_change's error handler with kernel gsbase.
*/
SWAPGS
jmp .Lerror_entry_done
.Lbstep_iret:
/* Fix truncated RIP */
movq %rcx, RIP+8(%rsp)
/* fall through */
.Lerror_bad_iret:
/*
* We came from an IRET to user mode, so we have user gsbase.
* Switch to kernel gsbase:
*/
SWAPGS
/*
* Pretend that the exception came from user mode: set up pt_regs
* as if we faulted immediately after IRET and clear EBX so that
* error_exit knows that we will be returning to user mode.
*/
mov %rsp, %rdi
call fixup_bad_iret
mov %rax, %rsp
decl %ebx
jmp .Lerror_entry_from_usermode_after_swapgs
END(error_entry)
/*
* On entry, EBX is a "return to kernel mode" flag:
* 1: already in kernel mode, don't need SWAPGS
* 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
*/
ENTRY(error_exit)
movl %ebx, %eax
cli
testl %eax, %eax
jnz retint_kernel
jmp retint_user
END(error_exit)
IDT_ENTRY divide_error do_divide_error has_error_code=0
IDT_ENTRY debug do_debug has_error_code=0
IDT_ENTRY nmi do_nmi has_error_code=0
IDT_ENTRY int3 do_int3 has_error_code=0
IDT_ENTRY overflow do_overflow has_error_code=0
IDT_ENTRY bounds do_bounds has_error_code=0
IDT_ENTRY invalid_op do_invalid_op has_error_code=0
IDT_ENTRY device_not_available do_device_not_available has_error_code=0
IDT_ENTRY double_fault do_double_fault has_error_code=1
IDT_ENTRY coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
IDT_ENTRY stack_segment do_stack_segment has_error_code=1
IDT_ENTRY general_protection do_general_protection has_error_code=1
IDT_ENTRY invalid_TSS do_invalid_TSS has_error_code=1
IDT_ENTRY page_fault do_page_fault has_error_code=1
IDT_ENTRY segment_not_present do_segment_not_present has_error_code=1
IDT_ENTRY spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
IDT_ENTRY coprocessor_error do_coprocessor_error has_error_code=0
IDT_ENTRY alignment_check do_alignment_check has_error_code=1
IDT_ENTRY machine_check do_machine_check has_error_code=0
IDT_ENTRY simd_exception do_simd_exception has_error_code=0
IDT_ENTRY virtualization_exception do_virtualization_exception has_error_code=0
/*
* Interrupt entry/exit.
* Interrupt entry points save only callee clobbered registers in fast path.
* Entry runs with interrupts off.
*
* When called, 0(%rsp): ~(interrupt number)
*/
.macro interrupt func
cld
ALLOC_PT_GPREGS_ON_STACK
SAVE_C_REGS
SAVE_EXTRA_REGS
testb $3, CS(%rsp)
jz 1f
/*
* IRQ from user mode.
* Switch to kernel gsbase.
*/
SWAPGS
1:
/*
* TODO:
* This is the point where we can switch to interrupt stack!
* Since Intel supports different stacks! e.g. NMI, Interrupt
*
* But for now Lego only the stack of the current thread
* No switching
*/
movq %rsp, %rdi /* pt_regs pointer */
pushq %rdi
call \func /* %rdi points to pt_regs */
.endm
/*
* The interrupt stubs push (~vector+0x80) onto the stack
* and then jump to common_interrupt.
*/
.align 64
ENTRY(common_interrupt)
/* Adjust vector to [-256, -1] range */
addq $-0x80, (%rsp)
interrupt do_IRQ
/* 0(%rsp): old RSP */
ret_from_intr:
cli
/* Restore saved previous stack */
popq %rsp
testb $3, CS(%rsp)
jz retint_kernel
/* Interrupt came from user space */
retint_user:
movq %rsp, %rdi
call prepare_exit_to_usermode
SWAPGS
jmp restore_regs_and_iret
/* Returning to kernel space */
retint_kernel:
#ifdef CONFIG_PREEMPT
/* Interrupts are off */
/* Check if we need preemption */
bt $9, EFLAGS(%rsp) /* was interrupt off? */
jnc 1f
0: cmpl $0, PER_CPU_VAR(__preempt_count) /* was preemption disabled? */
jnz 1f
GET_THREAD_INFO(%rcx)
bt $TIF_NEED_RESCHED, TI_flags(%rcx) /* was need_resched set? */
jnc 1f
call preempt_schedule_irq /* Do preemption */
jmp 0b
1:
#endif
/*
* At this label, code paths which return to kernel and to user,
* which come from interrupts/exception and from syscalls, merge.
*/
GLOBAL(restore_regs_and_iret)
RESTORE_EXTRA_REGS
restore_c_regs_and_iret:
RESTORE_C_REGS
REMOVE_PT_GPREGS_FROM_STACK 8
.global native_irq_return_iret
native_irq_return_iret:
/*
* The iretq could re-enable interrupts:
*/
/*
* This may fault. Non-paranoid faults on return to userspace are
* handled by fixup_bad_iret. These include #SS, #GP, and #NP.
* Double-faults due to espfix64 are handled in do_double_fault.
* Other faults here are fatal.
*/
iretq
END(common_interrupt)
/**
* irq_entries_start - [0x20...FIRST_SYSTEM_VECTOR] handler
*
* IDT has 0xff vectors:
* [0x0...0x1f] are Intel reserved vectors.
* [0x20...FIRST_SYSTEM_VECTOR] handlers are the below handler array
* [FIRST_SYSTEM_VECTOR...0xff] are filled of special system vectors,
* the holes inside this small range are filled of spurious_interrupt().
*
* Check arch/x86/kernel/irqinit.c for the god damn details.
*
* Build the entry stubs with some assembler magic.
* We pack 1 stub into every 8-byte block.
*/
.align 8
ENTRY(irq_entries_start)
vector=FIRST_EXTERNAL_VECTOR
.rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
/* Note: always in signed byte range */
pushq $(~vector+0x80)
vector=vector+1
jmp common_interrupt
.align 8
.endr
END(irq_entries_start)
/*
* APIC interrupts
*
* These are system interrupt handlers.
* Thus, always come from kernel mode.
* Lay between [FIRST_SYSTEM_VECTOR...0xff]
*/
.macro apicinterrupt num do_sym smp__sym
ENTRY(\smp__sym)
pushq $~(\num)
interrupt \do_sym
jmp ret_from_intr
END(\smp__sym)
.endm
apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp__reschedule_interrupt
apicinterrupt REBOOT_VECTOR reboot_interrupt smp__reboot_interrupt
apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp__apic_timer_interrupt
apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp__x86_platform_ipi
apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp__call_function_single_interrupt
apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp__call_function_interrupt
apicinterrupt ERROR_APIC_VECTOR error_interrupt smp__error_interrupt
apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp__spurious_interrupt
/*
* %rdi: prev task
* %rsi: next task
*/
ENTRY(__switch_to_asm)
/*
* Save callee-saved registers
* This must match the order in inactive_task_frame
*
* Note that ret_addr is already pushed:
* 1) context_switch(), where switch_to() was called
* 2) ret_from_fork(), which is placed by fork()
*/
pushq %rbp
pushq %rbx
pushq %r12
pushq %r13
pushq %r14
pushq %r15
/* Switch stack */
movq %rsp, TASK_threadsp(%rdi)
movq TASK_threadsp(%rsi), %rsp
/* restore callee-saved registers */
popq %r15
popq %r14
popq %r13
popq %r12
popq %rbx
popq %rbp
/*
* Note:
* This is a *JUMP* to __switch_to() function!
*/
jmp __switch_to
END(__switch_to_asm)
/*
* A newly forked process directly context switches into this address.
*
* rax: prev task we switched from
* rbx: kernel thread func (NULL for user thread)
* r12: kernel thread arg
*/
ENTRY(ret_from_fork)
movq %rax, %rdi
call schedule_tail /* rdi: 'prev' task parameter */
testq %rbx, %rbx /* from kernel_thread? */
jnz 1f /* kernel threads are uncommon */
2:
movq %rsp, %rdi
call syscall_return_slowpath /* return with IRQs disabled */
SWAPGS /* switch to user gs.base */
jmp restore_regs_and_iret
1:
/* kernel thread */
movq %r12, %rdi
call *%rbx
/*
* A kernel thread is allowed to return here after successfully
* calling do_execve(). Exit to userspace to complete the execve()
* syscall:
*/
movq $0, RAX(%rsp)
jmp 2b
END(ret_from_fork)
|
WukLab/LegoOS | 5,929 | arch/x86/entry/entry_64_compat.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <asm/asm.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/percpu.h>
#include <asm/segment.h>
#include <asm/extable.h>
#include <asm/irq_vectors.h>
#include <asm/thread_info.h>
#include <asm/alternative-asm.h>
#include <asm/processor-flags.h>
#include <asm/processor-features-flags.h>
#include <lego/errno.h>
#include <lego/linkage.h>
#include <generated/asm-offsets.h>
#include "abi.h"
/*
* 32-bit SYSENTER entry.
*
* 32-bit system calls through the vDSO's __kernel_vsyscall enter here
* on 64-bit kernels running on Intel CPUs.
*
* The SYSENTER instruction, in principle, should *only* occur in the
* vDSO. In practice, a small number of Android devices were shipped
* with a copy of Bionic that inlined a SYSENTER instruction. This
* never happened in any of Google's Bionic versions -- it only happened
* in a narrow range of Intel-provided versions.
*
* SYSENTER loads SS, RSP, CS, and RIP from previously programmed MSRs.
* IF and VM in RFLAGS are cleared (IOW: interrupts are off).
* SYSENTER does not save anything on the stack,
* and does not save old RIP (!!!), RSP, or RFLAGS.
*
* Arguments:
* eax system call number
* ebx arg1
* ecx arg2
* edx arg3
* esi arg4
* edi arg5
* ebp user stack
* 0(%ebp) arg6
*/
ENTRY(entry_SYSENTER_compat)
/* Interrupts are off on entry. */
swapgs
call do_fast_syscall_32
GLOBAL(__end_entry_SYSENTER_compat)
ENDPROC(entry_SYSENTER_compat)
/*
* 32-bit SYSCALL entry.
*
* 32-bit system calls through the vDSO's __kernel_vsyscall enter here
* on 64-bit kernels running on AMD CPUs.
*
* The SYSCALL instruction, in principle, should *only* occur in the
* vDSO. In practice, it appears that this really is the case.
* As evidence:
*
* - The calling convention for SYSCALL has changed several times without
* anyone noticing.
*
* - Prior to the in-kernel X86_BUG_SYSRET_SS_ATTRS fixup, anything
* user task that did SYSCALL without immediately reloading SS
* would randomly crash.
*
* - Most programmers do not directly target AMD CPUs, and the 32-bit
* SYSCALL instruction does not exist on Intel CPUs. Even on AMD
* CPUs, Linux disables the SYSCALL instruction on 32-bit kernels
* because the SYSCALL instruction in legacy/native 32-bit mode (as
* opposed to compat mode) is sufficiently poorly designed as to be
* essentially unusable.
*
* 32-bit SYSCALL saves RIP to RCX, clears RFLAGS.RF, then saves
* RFLAGS to R11, then loads new SS, CS, and RIP from previously
* programmed MSRs. RFLAGS gets masked by a value from another MSR
* (so CLD and CLAC are not needed). SYSCALL does not save anything on
* the stack and does not change RSP.
*
* Note: RFLAGS saving+masking-with-MSR happens only in Long mode
* (in legacy 32-bit mode, IF, RF and VM bits are cleared and that's it).
* Don't get confused: RFLAGS saving+masking depends on Long Mode Active bit
* (EFER.LMA=1), NOT on bitness of userspace where SYSCALL executes
* or target CS descriptor's L bit (SYSCALL does not read segment descriptors).
*
* Arguments:
* eax system call number
* ecx return address
* ebx arg1
* ebp arg2 (note: not saved in the stack frame, should not be touched)
* edx arg3
* esi arg4
* edi arg5
* esp user stack
* 0(%esp) arg6
*/
ENTRY(entry_SYSCALL_compat)
/* Interrupts are off on entry. */
swapgs
call do_fast_syscall_32
END(entry_SYSCALL_compat)
/*
* 32-bit legacy system call entry.
*
* 32-bit x86 Linux system calls traditionally used the INT $0x80
* instruction. INT $0x80 lands here.
*
* This entry point can be used by 32-bit and 64-bit programs to perform
* 32-bit system calls. Instances of INT $0x80 can be found inline in
* various programs and libraries. It is also used by the vDSO's
* __kernel_vsyscall fallback for hardware that doesn't support a faster
* entry method. Restarted 32-bit system calls also fall back to INT
* $0x80 regardless of what instruction was originally used to do the
* system call.
*
* This is considered a slow path. It is not used by most libc
* implementations on modern hardware except during process startup.
*
* Arguments:
* eax system call number
* ebx arg1
* ecx arg2
* edx arg3
* esi arg4
* edi arg5
* ebp arg6
*/
ENTRY(entry_INT80_compat)
/*
* Interrupts are off on entry.
*/
ASM_CLAC /* Do this early to minimize exposure */
swapgs
/*
* User tracing code (ptrace or signal handlers) might assume that
* the saved RAX contains a 32-bit number when we're invoking a 32-bit
* syscall. Just in case the high bits are nonzero, zero-extend
* the syscall number. (This could almost certainly be deleted
* with no ill effects.)
*/
movl %eax, %eax
/* Construct struct pt_regs on stack (iret frame is already on stack) */
pushq %rax /* pt_regs->orig_ax */
pushq %rdi /* pt_regs->di */
pushq %rsi /* pt_regs->si */
pushq %rdx /* pt_regs->dx */
pushq %rcx /* pt_regs->cx */
pushq $-ENOSYS /* pt_regs->ax */
pushq $0 /* pt_regs->r8 = 0 */
pushq $0 /* pt_regs->r9 = 0 */
pushq $0 /* pt_regs->r10 = 0 */
pushq $0 /* pt_regs->r11 = 0 */
pushq %rbx /* pt_regs->rbx */
pushq %rbp /* pt_regs->rbp */
pushq %r12 /* pt_regs->r12 */
pushq %r13 /* pt_regs->r13 */
pushq %r14 /* pt_regs->r14 */
pushq %r15 /* pt_regs->r15 */
cld
movq %rsp, %rdi
call do_int80_syscall_32
.Lsyscall_32_done:
swapgs
jmp restore_regs_and_iret
END(entry_INT80_compat)
|
WukLab/LegoOS | 5,894 | arch/x86/kernel/vmImage.lds.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* vmImage.lds.S: ld script for the x86 kernel.
*/
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/percpu.h>
#include <lego/compiler.h>
#include <lego/vmImage.lds.h>
/* in case the preprocessor is a 32bit one */
#undef i386
OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT)
#ifdef CONFIG_X86_64
ENTRY(startup_64)
OUTPUT_ARCH(i386:x86-64)
# define LOAD_OFFSET __START_KERNEL_map
#else
ENTRY(startup_32)
OUTPUT_ARCH(i386)
# define LOAD_OFFSET __PAGE_OFFSET
#endif
#define PT_LOAD 1
PHDRS {
text PT_LOAD FLAGS(5); /* R_E */
data PT_LOAD FLAGS(6); /* RW_ */
percpu PT_LOAD FLAGS(6); /* RW_ */
init PT_LOAD FLAGS(7); /* RWE */
}
SECTIONS {
. = LOAD_OFFSET + CONFIG_PHYSICAL_START;
#ifdef CONFIG_X86_64
phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET);
#else
phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET);
#endif
.text : AT(ADDR(.text) - LOAD_OFFSET) {
__text = .;
/* Bootstrapping code */
*(.head.text)
. = ALIGN(L1_CACHE_BYTES);
/* Whole story */
__stext = .;
*(.text*)
SCHED_TEXT
FIXUP_TEXT
/* End of text section */
__etext = .;
} :text = 0x9090
EXCEPTION_TABLE(16) :text = 0x9090
. = ALIGN(PAGE_SIZE);
.rodata : AT(ADDR(.rodata) - LOAD_OFFSET) {
__srodata = .;
*(.rodata*)
__erodata = .;
}
. = ALIGN(PAGE_SIZE);
.data : AT(ADDR(.data) - LOAD_OFFSET) {
__sdata = .;
/*
* the init task, which needs to be aligned
* with THREAD_SIZE (16KB in 64bit)
*/
. = ALIGN(THREAD_SIZE);
*(.data..init_task)
. = ALIGN(PAGE_SIZE);
*(.data..page_aligned)
. = ALIGN(L1_CACHE_BYTES);
*(.data..read_mostly)
. = ALIGN(L1_CACHE_BYTES);
*(.data..cacheline_aligned)
/* Normal data */
. = ALIGN(L1_CACHE_BYTES);
*(.data)
/* variables inside WARN_ONCE etc. */
. = ALIGN(L1_CACHE_BYTES);
*(.data..unlikely)
__edata = .;
} :data
/* Init code and data - will be freed after init */
. = ALIGN(PAGE_SIZE);
.init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) {
__sinit = .;
}
/*
* percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the
* output PHDR, so the next output section - .init.text - should
* start another segment - init.
*/
PERCPU_VADDR(L1_CACHE_BYTES, 0, :percpu)
ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START,
"per-CPU data too large - increase CONFIG_PHYSICAL_START")
. = ALIGN(PAGE_SIZE);
.init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
__sinittext = .;
*(.init.text)
__einittext = .;
} :init
. = ALIGN(L1_CACHE_BYTES);
.init.data : AT(ADDR(.init.data) - LOAD_OFFSET) {
__sinitdata = .;
*(.init.data)
__einitdata = .;
}
. = ALIGN(L1_CACHE_BYTES);
.init.rodata : AT(ADDR(.init.rodata) - LOAD_OFFSET) {
__sinitrodata = .;
*(.init.rodata)
__einitrodata = .;
}
/*
* Kernel parameter setup functions
* __setup(str, fn);
*/
. = ALIGN(L1_CACHE_BYTES);
.init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
__sinitsetup = .;
*(.init.setup)
__einitsetup = .;
}
. = ALIGN(L1_CACHE_BYTES);
.init.trampoline : AT(ADDR(.init.trampoline) - LOAD_OFFSET) {
__sinittrampoline = .;
*(.init.trampoline)
__einittrampoline = .;
}
. = ALIGN(L1_CACHE_BYTES);
.x86_cpu_vendor.init : AT(ADDR(.x86_cpu_vendor.init) - LOAD_OFFSET) {
__x86_cpu_vendor_start = .;
*(.x86_cpu_vendor.init)
__x86_cpu_vendor_end = .;
}
. = ALIGN(L1_CACHE_BYTES);
.profile.point : AT(ADDR(.profile.point) - LOAD_OFFSET) {
__sprofilepoint = .;
*(.profile.point)
__eprofilepoint = .;
}
/*
* struct alt_inst entries. From the header (alternative.h):
* "Alternative instructions for different CPU types or capabilities"
* Think locking instructions on spinlocks.
*/
. = ALIGN(L1_CACHE_BYTES);
.altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) {
__alt_instructions = .;
*(.altinstructions)
__alt_instructions_end = .;
}
/*
* And here are the replacement instructions. The linker sticks
* them as binary blobs. The .altinstructions has enough data to
* get the address and the length of them to patch the kernel safely.
*/
.altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) {
__alt_replacement = .;
*(.altinstr_replacement)
__alt_replacement_end = .;
}
. = ALIGN(L1_CACHE_BYTES);
.apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) {
__apicdrivers = .;
*(.apicdrivers)
__apicdrivers_end = .;
}
/* XXX: remove me later */
#ifdef CONFIG_COMP_MEMORY
. = ALIGN(PAGE_SIZE);
.ramfs : AT(ADDR(.ramfs) - LOAD_OFFSET) {
__ramfs_start = .;
*(.ramfs)
__ramfs_end = .;
}
#endif
__einit = .;
/* Checked during boot-time */
.signature : AT(ADDR(.signature) - LOAD_OFFSET) {
kernel_signature = .;
LONG(0x5a5aaa55)
}
/* Real-content ends here */
/* BSS */
. = ALIGN(PAGE_SIZE);
.bss : AT(ADDR(.bss) - LOAD_OFFSET) {
__bss_start = .;
*(.bss..page_aligned)
*(.bss*)
. = ALIGN(PAGE_SIZE);
__bss_end = .;
}
/*
* Boot-time early brk-like allocator
* Use RESERVE_BRK() to reserve this area at compile time
* Use extend_brk() to allocate brk at run time
*/
. = ALIGN(PAGE_SIZE);
.brk : AT(ADDR(.brk) - LOAD_OFFSET) {
__brk_start = .;
. += 64 * 1024;
*(.brk_reservation) /* areas brk users have reserved */
__brk_limit = .;
}
. = ALIGN(PAGE_SIZE);
__end = .;
}
/*
* Per-cpu symbols which need to be offset from __per_cpu_load
* for the boot processor.
*
* Used by head.S
*/
#define INIT_PER_CPU(x) \
INIT_PER_CPU_VAR(x) = x + __per_cpu_load
INIT_PER_CPU(per_cpu_head_start);
INIT_PER_CPU(cpu_gdt_page);
|
WukLab/LegoOS | 11,934 | arch/x86/kernel/head_64.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <asm/msr.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/percpu.h>
#include <asm/pgtable.h>
#include <asm/segment.h>
#include <asm/irq_vectors.h>
#include <asm/processor-flags.h>
#include <lego/linkage.h>
#include <lego/compiler.h>
#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
L4_START_KERNEL = pgd_index(__START_KERNEL_map)
L3_START_KERNEL = pud_index(__START_KERNEL_map)
#define pa(x) ((x) - __START_KERNEL_map)
.text
.section ".head.text","ax"
.code64
ENTRY(startup_64)
/*
* At this point the CPU runs in 64-bit mode CS.L = 1 CS.D = 0,
* and an identity mapped page table is loaded. These identity
* mapped page tables map [0, 4GB).
*
* %rsi holds a physical pointer to bootparam structure
*/
leaq __text(%rip), %rbp
subq $__text - __START_KERNEL_map, %rbp
/*
* If not relocatable, %rbp = 0
* Fixup the physical addresses in the page table
*/
addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
addq %rbp, level3_kernel_pgt + (510*8)(%rip)
addq %rbp, level3_kernel_pgt + (511*8)(%rip)
addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
/*
* Set up the identity mapping for the switchover. These
* entries should *NOT* have the global bit set! This also
* creates a bunch of nonsense entries but that is fine --
* it avoids problems around wraparound.
*/
leaq __text(%rip), %rdi
leaq early_level4_pgt(%rip), %rbx
movq %rdi, %rax
shrq $PGDIR_SHIFT, %rax
leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
movq %rdx, 0(%rbx,%rax,8)
movq %rdx, 8(%rbx,%rax,8)
addq $4096, %rdx
movq %rdi, %rax
shrq $PUD_SHIFT, %rax
andl $(PTRS_PER_PUD-1), %eax
movq %rdx, 4096(%rbx,%rax,8)
incl %eax
andl $(PTRS_PER_PUD-1), %eax
movq %rdx, 4096(%rbx,%rax,8)
addq $8192, %rbx
movq %rdi, %rax
shrq $PMD_SHIFT, %rdi
addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
leaq (__end - 1)(%rip), %rcx
shrq $PMD_SHIFT, %rcx
subq %rdi, %rcx
incl %ecx
1:
andq $(PTRS_PER_PMD - 1), %rdi
movq %rax, (%rbx,%rdi,8)
incq %rdi
addq $PMD_SIZE, %rax
decl %ecx
jnz 1b
/*
* Fixup the kernel text+data virtual addresses. Note that
* we might write invalid pmds, when the kernel is relocated
* cleanup_highmap() fixes this up along with the mappings
* beyond _end.
*/
leaq level2_kernel_pgt(%rip), %rdi
leaq 4096(%rdi), %r8
/* See if it is a valid page table entry */
1: testb $1, 0(%rdi)
jz 2f
addq %rbp, 0(%rdi)
/* Go to the next page */
2: addq $8, %rdi
cmp %r8, %rdi
jne 1b
/* Fixup phys_base */
addq %rbp, phys_base(%rip)
movq $(early_level4_pgt - __START_KERNEL_map), %rax
jmp 1f
/*
* This is triky.
* Since the above code won't be too big, so the align
* actually means the *absolute* offset from the beginning.
*
* Hence the trampoline code can jump to:
* CONFIG_PHYSICAL_START + SECONDARY_STARTUP_64_ALIGN
* directly...
*/
.align SECONDARY_STARTUP_64_ALIGN
ENTRY(secondary_startup_64)
/*
* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
* and someone has loaded a mapped page table.
*
* %rsi holds a physical pointer to real_mode_data.
*
* We come here either from startup_64 (using physical addresses)
* or from trampoline.S (using virtual addresses).
*
* Using virtual addresses from trampoline.S removes the need
* to have any identity mapped pages in the kernel page table
* after the boot processor executes this code.
*/
movq $(init_level4_pgt - __START_KERNEL_map), %rax
1:
/*
* Enable PAE mode and PGE
*
* PAE: must be set before entering IA-32e mode.
* PGE: global pages are not flushed from the TLB on a
* task switch or a write to register CR3.
*/
movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
movq %rcx, %cr4
/* Setup early boot stage 4 level pagetables. */
addq phys_base(%rip), %rax
movq %rax, %cr3
/* Ensure I am executing from virtual addresses */
movq $1f, %rax
jmp *%rax
1:
/* Check if nx is implemented */
movl $0x80000001, %eax
cpuid
movl %edx,%edi
/* Setup EFER (Extended Feature Enable Register) */
movl $MSR_EFER, %ecx
rdmsr
btsl $_EFER_SCE, %eax /* Enable System Call */
btl $20,%edi /* No Execute supported? */
jnc 1f
btsl $_EFER_NX, %eax
btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
1: wrmsr /* Make changes effective */
/* Setup cr0 */
#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
X86_CR0_PG)
movl $CR0_STATE, %eax
/* Make changes effective */
movq %rax, %cr0
/* Setup a boot time stack */
movq initial_stack(%rip), %rsp
/* zero EFLAGS after setting rsp */
pushq $0
popfq
/*
* We must switch to a new descriptor in kernel space for the GDT
* because soon the kernel won't have access anymore to the userspace
* addresses where we're currently running on. We have to do that here
* because in 32bit we couldn't load a 64bit linear address.
*/
lgdt early_gdt_descr(%rip)
/* set up data segments */
xorl %eax,%eax
movl %eax,%ds
movl %eax,%ss
movl %eax,%es
/*
* We don't really need to load %fs or %gs, but load them anyway
* to kill any stale realmode selectors. This allows execution
* under VT hardware.
*/
movl %eax,%fs
movl %eax,%gs
/* Set up %gs for per-cpu data structure */
movl $MSR_GS_BASE, %ecx
movl initial_gs(%rip),%eax
movl initial_gs+4(%rip),%edx
wrmsr
/*
* rsi is pointer to real mode structure with interesting info.
* pass it to C
*/
movq %rsi, %rdi
/*
* Finally jump to run C code and to be on real kernel address
* Since we are running on identity-mapped space we have to jump
* to the full 64bit address, this is only possible as indirect
* jump. In addition we need to ensure %cs is set so we make this
* a far return.
*
* Note: do not change to far jump indirect with 64bit offset.
*
* Intel64 does support 64bit offset.
* Software Developer Manual Vol 2: states:
* FF /5 JMP m16:16 Jump far, absolute indirect,
* address given in m16:16
* FF /5 JMP m16:32 Jump far, absolute indirect,
* address given in m16:32.
* REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
* address given in m16:64.
*/
movq initial_code(%rip),%rax
pushq $0 # fake return address to stop unwinder
pushq $__KERNEL_CS # set correct cs
pushq %rax # target address in negative space
lretq
.data
.balign 8
/*
* initial_code, initial_stack, initial_gs differ
* for BSP and secondary CPUs. They will be replaced by do_cpu_up()
* before booting secondary CPUs.
*/
GLOBAL(initial_code)
.quad x86_64_start_kernel
GLOBAL(initial_stack)
.quad init_thread_union+THREAD_SIZE-8
.word 0
/*
* Make the per-cpu variable work on BSP before
* initilizing per-cpu setup.
*
* This is not a real variable, it is symbol defined
* and exported by linker script.
*/
GLOBAL(initial_gs)
.quad INIT_PER_CPU_VAR(per_cpu_head_start)
.section ".init.text"
ENTRY(early_idt_handler_array)
# 104(%rsp) %rflags
# 96(%rsp) %cs
# 88(%rsp) %rip
# 80(%rsp) error code
i = 0
.rept NUM_EXCEPTION_VECTORS
.ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1
pushq $0 # Dummy error code, to make stack frame uniform
.endif
pushq $i # 72(%rsp) Vector number
jmp early_idt_handler_common
i = i + 1
.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
.endr
ENDPROC(early_idt_handler_array)
early_idt_handler_common:
/*
* The stack is the hardware frame, an error code or zero, and the
* vector number.
*/
cld
incl early_recursion_flag(%rip)
/* The vector number is currently in the pt_regs->di slot. */
pushq %rsi /* pt_regs->si */
movq 8(%rsp), %rsi /* RSI = vector number */
movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
pushq %rdx /* pt_regs->dx */
pushq %rcx /* pt_regs->cx */
pushq %rax /* pt_regs->ax */
pushq %r8 /* pt_regs->r8 */
pushq %r9 /* pt_regs->r9 */
pushq %r10 /* pt_regs->r10 */
pushq %r11 /* pt_regs->r11 */
pushq %rbx /* pt_regs->bx */
pushq %rbp /* pt_regs->bp */
pushq %r12 /* pt_regs->r12 */
pushq %r13 /* pt_regs->r13 */
pushq %r14 /* pt_regs->r14 */
pushq %r15 /* pt_regs->r15 */
cmpq $14, %rsi /* Page fault? */
jnz 10f
movq %cr2, %rdi
call early_make_pgtable
andl %eax,%eax
jz 20f /* All good */
10:
movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
call early_fixup_exception
20:
decl early_recursion_flag(%rip)
jmp restore_regs_and_iret
ENDPROC(early_idt_handler_common)
.balign 4
GLOBAL(early_recursion_flag)
.long 0
#define NEXT_PAGE(name) \
.balign PAGE_SIZE; \
GLOBAL(name)
/* Automate the creation of 1 to 1 mapping pmd entries */
#define PMDS(START, PERM, COUNT) \
i = 0 ; \
.rept (COUNT) ; \
.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
i = i + 1 ; \
.endr
.section ".init.data","aw",%progbits
NEXT_PAGE(early_level4_pgt)
.fill 511,8,0
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
NEXT_PAGE(early_dynamic_pgts)
.fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
.data
NEXT_PAGE(init_level4_pgt)
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
.org init_level4_pgt + L4_PAGE_OFFSET*8, 0
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
.org init_level4_pgt + L4_START_KERNEL*8, 0
/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
NEXT_PAGE(level3_ident_pgt)
.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
.fill 511, 8, 0
NEXT_PAGE(level2_ident_pgt)
/* Since I easily can, map the first 1G.
* Don't set NX because code runs from these pages.
*/
PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
/*
* 0-510: .fill L3_START_KERNEL
* 511: 0xffffffff80000000 - 0xffffffffbffffff
* 522: 0xffffffffc0000000 - 0xfffffffffffffff
*
* 511, which is level2_kernel_pgt, is for kernel code+data+bss
* 522, which is level2_fixmap_pgt, is for fixmap + early_ioremap
*
* Check early_ioremap_init() for more explanations.
*/
NEXT_PAGE(level3_kernel_pgt)
.fill L3_START_KERNEL,8,0
/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
NEXT_PAGE(level2_kernel_pgt)
/*
* 512 MB kernel mapping. We spend a full page on this pagetable
* anyway.
*
* The kernel code+data+bss must not be bigger than that.
*
* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
* If you want to increase this then increase MODULES_VADDR
* too.)
*/
PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
KERNEL_IMAGE_SIZE/PMD_SIZE)
/*
* We will have a bm_pte[] array for early_ioremap, which will
* be initilized in early_ioremap_init(), so here we do not
* need to allocate the L1 pgtable for it. But for the permanent
* fixmap entries, we need to provide a L1 pgtable, which will
* be the level1_fixmap_pgt.
*
* Also because the FIXADDR_TOP starts from vsyscall, which is
* 0xfffffffff600000, thus we need to fill the level1_fixmap_pgt
* into the right slot (507)
*/
NEXT_PAGE(level2_fixmap_pgt)
.fill 506,8,0
.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
.fill 5,8,0
NEXT_PAGE(level1_fixmap_pgt)
.fill 512,8,0
#undef PMDS
.data
.align 16
.globl early_gdt_descr
early_gdt_descr:
.word GDT_ENTRIES*8-1
.quad INIT_PER_CPU_VAR(cpu_gdt_page)
ENTRY(phys_base)
/* This must match the first entry in level2_kernel_pgt */
.quad 0x0000000000000000
.bss
NEXT_PAGE(empty_zero_page)
.skip PAGE_SIZE
|
WukLab/LegoOS | 3,848 | arch/x86/boot/compressed/head_64.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* Note that:
* %esi points to the bootparam structure.
*/
#include <asm/msr.h>
#include <asm/boot.h>
#include <asm/segment.h>
#include <asm/processor-flags.h>
#include <lego/linkage.h>
#define NR_PGTABLE 6
.text
.code32
.section ".head.text","ax"
GLOBAL(startup_32)
cld
cli
/*
* Get the address where we are loaded
* well, it is 0x100000 that we are talking about.
*/
call 1f
1: popl %ebp
subl $1b, %ebp
/* Setup a mini stack */
movl $boot_stack_end, %eax
addl %ebp, %eax
movl %eax, %esp
/*
* Load new GDT with the 64bit segments using 32bit descriptor.
* These descriptors has .L = 1, indicates that these segments
* contains native 64-bit code.
*/
leal gdt(%ebp), %eax
movl %eax, gdt+2(%ebp)
lgdt gdt(%ebp)
/*
* Enable PAE mode
* Note: If CR0.PG = 0, paging is not used. In this case,
* CR4.PAE and IA32_EFER.LME are ignored by the processor.
*/
movl %cr4, %eax
orl $X86_CR4_PAE, %eax
movl %eax, %cr4
/*
* Build early 4GB boot pagetable
* Identity mapping, using 2MB page size.
*
* Level 4: entry 0
* Level 3: entry 0~3
* Level 2: entry 0~511, need 4 full level-2 pgtables
*/
/* Clear pagetables */
leal pgtable(%ebp), %edi
xorl %eax, %eax
movl $((NR_PGTABLE * 4096) / 4), %ecx
rep
stosl
/* Build Level 4 */
leal pgtable + 0(%ebp), %edi
leal 0x1007(%edi), %eax
movl %eax, 0(%edi)
/* Build Level 3 */
leal pgtable + 0x1000(%ebp), %edi
leal 0x1007(%edi), %eax
movl $4, %ecx
1: movl %eax, 0x00(%edi)
addl $0x00001000, %eax
addl $8, %edi
decl %ecx
jnz 1b
/* Build Level 2 */
leal pgtable + 0x2000(%ebp), %edi
movl $0x00000183, %eax
movl $2048, %ecx
1: movl %eax, 0(%edi)
addl $0x00200000, %eax
addl $8, %edi
decl %ecx
jnz 1b
/* Enable the boot page tables */
leal pgtable(%ebp), %eax
movl %eax, %cr3
/*
* Set IA32_EFER.LME = 1
* Enable Long mode in EFER (Extended Feature Enable Register)
*/
movl $MSR_EFER, %ecx
rdmsr
btsl $_EFER_LME, %eax
wrmsr
/* After gdt is loaded */
xorl %eax, %eax
lldt %ax
movl $__BOOT_TSS, %eax
ltr %ax
/*
* Setup for the jump to 64bit mode
*
* When the jump is performend we will be in long mode but
* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
* We place all of the values on our mini stack so lret can
* used to perform that far jump.
*/
pushl $__KERNEL_CS
leal startup_64(%ebp), %eax
pushl %eax
/* Enter paged protected Mode, activating Long Mode */
movl $(X86_CR0_PG | X86_CR0_PE), %eax
movl %eax, %cr0
/* Jump from 32bit compatibility mode into 64bit mode. */
lret
ENDPROC(startup_32)
.code64
.org 0x200
ENTRY(startup_64)
/* Setup data segments. */
xorl %eax, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %ss
movl %eax, %fs
movl %eax, %gs
/* Save real-mode bootparam ptr */
pushq %rsi
/* Copy kernel to CONFIG_PHYSICAL_START */
movq $_ekernel, %rcx
subq $_kernel, %rcx
shrq $3, %rcx
incq %rcx
leaq _kernel(%rbp), %rsi
movq $CONFIG_PHYSICAL_START, %rdi
rep
movsq
/* Restore real-mode bootparam ptr */
popq %rsi
/*
* Jump to kernel
* arch/x86/kernel/head_64.S
*/
movq $CONFIG_PHYSICAL_START, %rax
jmpq *%rax
.data
gdt:
.word gdt_end - gdt
.long gdt
.word 0 /* 0 */
.quad 0x0000000000000000 /* NULL descriptor 1 */
.quad 0x00af9a000000ffff /* __KERNEL_CS 2 */
.quad 0x00cf92000000ffff /* __KERNEL_DS 3 */
.quad 0x0080890000000000 /* TS descriptor 4 */
.quad 0x0000000000000000 /* TS continued 5 */
gdt_end:
.bss
.balign 4
boot_heap:
.fill 0x1000, 1, 0
boot_stack:
.fill 0x1000, 1, 0
boot_stack_end:
.section ".pgtable","a",@nobits
.balign 4096
pgtable:
.fill NR_PGTABLE * 4096, 1, 0
|
WukLab/LegoOS | 4,496 | arch/x86/realmode/rm/trampoline.S | /*
* Copyright (c) 2016-2020 Wuklab, Purdue University. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/*
* Trampoline code used to boot secondary CPUs.
* Invoked by BSP by sending APIC INIT to this CPU.
*
* This file actually is a combination of:
* arch/x86/boot/pmjump.S: (16bit->32bit transition)
* arch/x86/boot/compressed/head_64.S: (32bit->64bit transition)
*
* At last it will jump to [arch/x86/kernel/head_64.S] to enter kernel.
*/
#include <lego/linkage.h>
#include <asm/msr.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/segment.h>
#include <asm/processor-flags.h>
#define NR_PGTABLE 6
.section ".text","ax"
.code16
ENTRY(_start)
cli
wbinvd
xorl %eax, %eax
mov %cs, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %ss
# PA already changed by previous CPU?
movl pa_changed, %ebx
testl %ebx, %ebx
jnz 1f
# No, we are the FIRST secondary cpu
shll $4, %eax
addl %eax, pa_tr_gdt
addl %eax, 2f
movl $1, pa_changed
1:
# Setup stack
movl $rm_stack_end, %esp
# Load idt with 0,0
lidtl tr_idt_desc
lgdtl tr_gdt_desc
xorl %edx, %edx
movw $__KERNEL_DS, %dx # Data segment descriptor
# Enable protected mode
movl $X86_CR0_PE, %eax # protected mode (PE) bit
movl %eax, %cr0 # into protected mode
# Transition to 32-bit mode
.byte 0x66, 0xea # ljmpl opcode
2: .long startup_32 # offset
.word __KERNEL32_CS # segment
.section ".text32","ax"
.code32
.balign 4
ENTRY(startup_32)
movl %edx, %ss
movl %edx, %ds
movl %edx, %es
movl %edx, %fs
movl %edx, %gs
# Get the address where we are loaded
call 1f
1: popl %ebp
subl $1b, %ebp
# Setup mini stack
leal rm_stack_end(%ebp), %esp
# Enable PAE mode
movl %cr4, %eax
orl $X86_CR4_PAE, %eax
movl %eax, %cr4
/*
* Build early 4GB boot pagetable
* Identity mapping, using 2MB page size.
*
* Level 4: entry 0
* Level 3: entry 0~3
* Level 2: entry 0~511, need 4 full level-2 pgtables
*/
/* Clear pagetables */
leal pgtable(%ebp), %edi
xorl %eax, %eax
movl $((NR_PGTABLE * 4096) / 4), %ecx
rep
stosl
/* Build Level 4 */
leal pgtable + 0(%ebp), %edi
leal 0x1007(%edi), %eax
movl %eax, 0(%edi)
/* Build Level 3 */
leal pgtable + 0x1000(%ebp), %edi
leal 0x1007(%edi), %eax
movl $4, %ecx
1: movl %eax, 0x00(%edi)
addl $0x00001000, %eax
addl $8, %edi
decl %ecx
jnz 1b
/* Build Level 2 */
leal pgtable + 0x2000(%ebp), %edi
movl $0x00000183, %eax
movl $2048, %ecx
1: movl %eax, 0(%edi)
addl $0x00200000, %eax
addl $8, %edi
decl %ecx
jnz 1b
/* Enable the boot page tables */
leal pgtable(%ebp), %eax
movl %eax, %cr3
/*
* Set IA32_EFER.LME = 1
* Enable Long mode in EFER (Extended Feature Enable Register)
*/
movl $MSR_EFER, %ecx
rdmsr
btsl $_EFER_LME, %eax
wrmsr
# Enable paging and in turn activate Long Mode
movl $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax
movl %eax, %cr0
/*
* Setup for the jump to 64bit mode
*
* When the jump is performend we will be in long mode but
* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
* We place all of the values on our mini stack so lret can
* used to perform that far jump.
*/
pushl $__KERNEL_CS
leal startup_64(%ebp), %eax
pushl %eax
# Transition to 64-bit mode
lret
.code64
.section ".text64","ax"
.balign 4
ENTRY(startup_64)
cld
/* Setup data segments. */
xorl %eax, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %ss
movl %eax, %fs
movl %eax, %gs
/*
* Jump to kernel
* arch/x86/kernel/head_64.S
*/
movq $(CONFIG_PHYSICAL_START + SECONDARY_STARTUP_64_ALIGN), %rax
jmpq *%rax
# DATA Section
.data
# Duplicate the global descriptor table
# so the kernel can live anywhere
.balign 16
tr_gdt_desc:
.short tr_gdt_end - tr_gdt # gdt limit
pa_tr_gdt:
.long tr_gdt # gdt address
.balign 16
tr_gdt:
.quad 0
.quad 0x00cf9b000000ffff # __KERNEL32_CS
.quad 0x00af9b000000ffff # __KERNEL_CS
.quad 0x00cf93000000ffff # __KERNEL_DS
tr_gdt_end:
.balign 16
tr_idt_desc: .fill 1, 6, 0 # IDT 0,0
.balign 8
pa_changed:
.long 0
# BSS Section
.bss
.balign 16
rm_stack:
.space 128
rm_stack_end:
.align PAGE_SIZE
pgtable:
.space NR_PGTABLE * PAGE_SIZE
|
Wunkolo/OakSim | 1,077 | SampleCode.s | .macro PADGROUP name=""
.balign 16,0xAB
.ascii "\name"
.balign 16,'='
.endm
.arm @ Emit 32-bit ARM code
#.thumb @ Emit 16-bit THUMB code, note now "IntegerDivide" collapses
PADGROUP "Square"
square:
mov r3, r0
mul r0, r3, r0
bx lr
PADGROUP "IntegerDivide"
IntegerDivide:
mov r1, #0
adds r0, r0, r0
.rept 32 @ repeat 32 times
adcs r1, r2, r1, lsl #1
subcc r1, r1, r2
adcs r0, r0, r0
.endr
mov pc, lr
PADGROUP "Mul50Int"
Mul50Int:
mov r3, #50
mul r0, r3, r0
bx lr
PADGROUP "Mul50Float"
Mul50Float:
vmov s14, r0
vldr.32 s15, .L1
vmul.f32 s15, s14, s15
vmov r0, s15
bx lr
.L1:
.float 50.0
PADGROUP "Mul50Double"
Mul50Double:
vmov d6, r0, r4
vldr.64 d7, .L2
vmul.f64 d7, d6, d7
vmov r0, r1, d7
bx lr
.L2:
.double 50.0s
PADGROUP "Data"
Data:
# Values
.float 1.0, 0.5, inf @floats
.double 1.0, 0.5, inf @doubles
# Strings
PADGROUP "Strings"
.string "Arm assembly right in your browser!"
.ascii "test\000"
.space 64,'^'
.asciiz "YO"
# Rept
PADGROUP "Rept"
.rept 12 @ x12 1.0-floats
.float 1.0
.endr |
wurlyfox/c1 | 481,764 | src/psx/r3000a.s |
.text
.macro copy_w_seq_unr src, dst, from=0, to=0x100, step=4
addiu \src, \step
sw \src, \from(\dst)
.if \to-\from
copy_w_seq_unr \src, \dst, "(\from+step)", \to, \step
.endif
.endm
# save all regs to scratch memory
.macro ssave
sw $s0, 0x1F800000
sw $s1, 0x1F800004
sw $s2, 0x1F800008
sw $s3, 0x1F80000C
sw $s4, 0x1F800010
sw $s5, 0x1F800014
sw $s6, 0x1F800018
sw $s7, 0x1F80001C
sw $t8, 0x1F800020
sw $t9, 0x1F800024
sw $k0, 0x1F800028
sw $k1, 0x1F80002C
sw $gp, 0x1F800030
sw $sp, 0x1F800034
sw $fp, 0x1F800038
sw $ra, 0x1F80003C
.endm
# reload all regs from scratch memory
.macro sload
lw $s0, 0x1F800000
lw $s1, 0x1F800004
lw $s2, 0x1F800008
lw $s3, 0x1F80000C
lw $s4, 0x1F800010
lw $s5, 0x1F800014
lw $s6, 0x1F800018
lw $s7, 0x1F80001C
lw $t8, 0x1F800020
lw $t9, 0x1F800024
lw $k0, 0x1F800028
lw $k1, 0x1F80002C
lw $gp, 0x1F800030
lw $sp, 0x1F800034
lw $ra, 0x1F80003C
lw $fp, 0x1F800038
.endm
#
# inline version of sin
#
# this is simply a lookup into a precomputed table
#
# said table stores only the first 90 degrees of a sine curve
# since sin(a) = sin(pi - a) for pi/2 <= a <= pi, 0 <= pi - a <= pi/2
# sin(a) = -sin(a - pi) for pi <= a <= 3pi/2, 0 <= a - pi <= pi/2
# sin(a) = -sin(2pi - a) for 3pi/2 <= a <= 2pi, 0 <= 2pi - a <= pi/2
#
# thus, for angle values that fall into the 2nd, 3rd, or 4th quadrants
# it is necessary to compute the corresponding angle in the 1st quadrant
# such that yields a result for sin with the same absolute value
# and ultimately the same value, if negated in the case that pi < a < 2pi
# and then use this angle to index the table, negating the result accordingly
#
# angles are 12 bit values such that
#
# rad = (ang / 0x1000) * 2pi
# deg = (ang / 0x1000) * 360
#
# where ang is the angle value, and rad and deg are the corresponding values
# in radians and degrees, respectively
#
# name - unique label used to differentiate multiple inline usages
# st - register with pointer to sine table
# r1 - register with output value
# r2 - register with input angle
#
.macro msin name st r1 r2
sin_\name\()_test_1:
slti \r1, \r2, 0x800
beqz \r1, sin_\name\()_gteq180
sin_\name\()_test_2:
slti \r1, \r2, 0x400
beqz \r1, sin_\name\()_bt_90_180
sin_\name\()_lt90:
sll \r1, \r2, 1
addu \r1, \st, \r1
bgez $zero, sin_\name\()_ret
lh \r1, 0(\r1) # \r1 = sin_table[ang]
nop
sin_\name\()_bt_90_180:
subu \r1, \st, \r1
bgez $zero, sin_\name\()_ret
lh \r1, 0x1000(\r1) # \r1 = sin_table[0x800-ang] (180 - ang)
nop
sin_\name\()_gteq180:
sin_\name\()_test_3:
slti \r1, \r2, 0xC00
beqz \r1, sin_\name\()_bt_270_360
sin_\name\()_bt_180_270:
sll \r1, \r2, 1
addu \r1, \st, \r1
lh \r1, -0x1000(\r1)
bgez $zero, sin_\name\()_ret
negu \r1, \r1 # \r1 = -sin_table[ang-0x800] (ang - 180)
sin_\name\()_bt_270_360:
subu \r1, \st, \r1
lh \r1, 0x2000(\r1)
bgez $zero, sin_\name\()_ret
negu \r1, \r1 # \r1 = -sin_table[0x1000-ang] (360 - ang)
sin_\name\()_ret:
.endm
#
# inline version of cos
#
# this is simply a lookup into the precomputed sine table, as is the inlined sin
#
# since cos(a) = sin(a + pi/2)
# and sin(b) = sin(pi - b) for pi/2 <= b <= pi, 0 <= pi - b <= pi/2
# sin(b) = -sin(b - pi) for pi <= b <= 3pi/2, 0 <= b - pi <= pi/2
# sin(b) = -sin(2pi - b) for 3pi/2 <= b <= 2pi, 0 <= 2pi - b <= pi/2
# sin(b) = sin(b) for 0 <= b <= pi/2, 0 <= b <= pi/2
# then b = a + pi/2 => cos(a) = sin(b) and
# cos(a) = sin(pi - b) for pi/2 <= b <= pi, 0 <= pi - b <= pi/2
# = sin(pi/2 - a) for 0 <= a <= pi/2, 0 <= pi/2 - a <= pi/2
# cos(a) = -sin(b - pi) for pi <= b <= 3pi/2, 0 <= b - pi <= pi/2
# = -sin(a - pi/2) for pi/2 <= a <= pi, 0 <= a - pi/2 <= pi/2
# cos(a) = -sin(2pi - b) for 3pi/2 <= b <= 2pi, 0 <= 2pi - b <= pi/2
# = -sin(3pi/2 - a) for pi <= a <= 3pi/2, 0 <= 3pi/2 - a <= pi/2
# cos(a) = sin(b) for 0 <= b <= pi/2, 0 <= b <= pi/2
# = sin(b - 2pi) for 2pi <= b <= 5pi/2, 0 <= b - 2pi <= pi/2
# = sin(a - 3pi/2) for 3pi/2 <= a <= 2pi, 0 <= a - 3pi/2 <= pi/2
# thus
# cos(a) = sin(pi/2 - a) for 0 <= a <= pi/2, 0 <= pi/2 - a <= pi/2
# cos(a) = -sin(a - pi/2) for pi/2 <= a <= pi, 0 <= a - pi/2 <= pi/2
# cos(a) = -sin(3pi/2 - a) for pi <= a <= 3pi/2, 0 <= 3pi/2 - a <= pi/2
# cos(a) = sin(a - 3pi/2) for 3pi/2 <= a <= 2pi, 0 <= a - 3pi/2 <= pi/2
#
# the function is identical to the inline sin function, except for the adjusted offsets
# and negations
#
# name - unique label used to differentiate multiple inline usages
# st - register with pointer to sine table
# r1 - register with output value
# r2 - register with input angle
#
.macro mcos name st r1 r2
cos_\name\()_test_1:
slti \r1, \r2, 0x800
beqz \r1, cos_\name\()_gteq180
cos_\name\()_test_2:
slti \r1, \r2, 0x400
beqz \r1, cos_\name\()_bt_90_180
cos_\name\()_lt90:
sll \r1, \r2, 1
subu \r1, \st, \r1
bgez $zero, cos_\name\()_ret
lh \r1, 0x800(\r1) # \r1 = sin_table[0x400-ang] (90 - ang)
nop
cos_\name\()_bt_90_180:
addu \r1, \st, \r1
lh \r1, -0x800(\r1) # \r1 = -sin_table[ang-0x400] (ang - 90)
bgez $zero, sin_\name\()_ret
negu \r1, \r1
cos_\name\()_gteq180:
cos_\name\()_test_3:
slti \r1, \r2, 0xC00
beqz \r1, cos_\name\()_bt_270_360
cos_\name\()_bt_180_270:
sll \r1, \r2, 1
subu \r1, \st, \r1
lh \r1, 0x1800(\r1)
bgez $zero, cos_\name\()_ret
negu \r1, \r1 # \r1 = -sin_table[0xC00-ang] (270 - ang)
cos_\name\()_bt_270_360:
addu \r1, \st, \r1
lh \r1, -0x1800(\r1) # \r1 = sin_table[ang-0xC00] (ang - 270)
cos_\name\()_ret:
.endm
/*
note for slst decoding routines:
Perhaps the name 'node' is misleading for the 16 bit structures which make up the slst deltas,
as the structures are neither part of a tree nor include the pointers of a linked list.
The slst deltas were initially assumed to be a BSP tree of sorts before their format was
cracked, and in initial pseudocode attempts the structures are referred to as nodes.
The name has since stuck.
*/
#
# apply changes to a poly id list for a forward change in path progress
# using an slst delta item
#
# a0 = slst delta item
# a1 = source poly id list
# a2 = destination poly id list
#
RSlstDecodeForward:
slst_delta = $a0 # slst delta item
src = $t6 # source list iterator (pointer-based)
src_len = $gp # source list length
dst = $s1 # destination list iterator (pointer-based)
# dst_len = n/a # (unused) destination list length
isrc = $v1 # source list iterator (index-based)
idst = $v0 # destination list iterator (index-based)
add = $t7 # iterator/pointer to current add node
rem = $s0 # iterator/pointer to current rem node
swap = $fp # iterator/pointer to current swap node
add_start = $sp # pointer to the first add node (or 1 short after the last rem node)
add_idx = $t0 # index in dst list at which to begin adding poly ids for the current add node
rem_idx = $t1 # index in src list at which to begin removing poly ids for the current rem node
add_len = $t2 # remaining number of poly ids to add for the current add node
rem_len = $t3 # remaining number of poly ids to remove for the current rem node
add_count = $t4 # number of poly ids added thus far for the current add node
rem_count = $t5 # number of poly ids removed thus far for the current rem node
add_node = $s7 # current add node
rem_node = $t8 # current rem node
swap_l = $s4 # pointer to left poly id for the current swap
swap_r = $s3 # pointer to right poly id for the current swap
null = $s6 # null index
tmp1 = $at
tmp2 = $a3
tmp3 = $t9
ssave
move idst, $zero # initialize dst index
move rem_count, $zero # initialize rem node [poly id] count
addiu rem, slst_delta, 8 # initialize rem node iterator
lhu tmp1, 4(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add add_start, slst_delta, tmp1 # compute absolute address of add nodes
move add, add_start # initialize add node iterator
lhu tmp1, 6(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add swap, slst_delta, tmp1 # compute absolute address of swap nodes
addiu src, $a1, 4 # initialize src list iterator
lhu src_len, 0($a1) # get length of src list
addiu dst, $a2, 4 # initialize dst list iterator
rem_next_1:
lhu tmp1, 0(rem) # get first rem node
addiu rem, 2 # increment rem node iterator
slt tmp3, rem, add_start
beqz tmp3, rem_next_null_1 # skip next 2 blocks if rem node iterator at end of rem nodes
move rem_len, $zero # set default rem node poly id count
rem_next_valid_1a:
move rem_node, tmp1
beq rem_node, null, rem_next_null_1 # skip next block if rem node is null
rem_next_valid_1b:
andi rem_idx, rem_node, 0xFFF # get rem index
andi rem_len, rem_node, 0xF000
srl rem_len, 12 # get rem length
bgez $zero, rem_next_inc_1 # skip the null case
addiu rem_len, 1 # (length is minimum of 1)
rem_next_null_1:
sll rem_idx, null, 8 # set rem idx to -255
rem_next_inc_1:
blez rem_len, add_next_1 # skip incrementing rem node iterator if rem node is null
nop
rem_next_valid_inc_1:
lhu rem_node, 0(rem) # grab next rem node
addiu rem, 2 # increment rem node iterator (to be dereferenced in next iteration)
add_next_1:
lhu tmp1, 0(add) # get first add node
addiu add, 2 # increment add node iterator
slt tmp3, add, swap
beqz tmp3, add_next_null_1 # skip next 2 blocks if add node iterator at end of add nodes
move add_len, $zero # set default add node poly id count
add_next_valid_1a:
move add_node, tmp1
beq add_node, null, add_next_null_1 # skip next block if add node is null
add_next_valid_1b:
andi add_idx, add_node, 0xFFF # get add index
andi add_len, add_node, 0xF000
srl add_len, 12 # get add length
bgez $zero, add_next_inc_1 # skip the null case
addiu add_len, 1 # (length is minimum of 1)
add_next_null_1:
sll add_idx, null, 8 # set add idx to -255
add_next_inc_1:
blez add_len, add_rem_loop_init_1 # skip incrementing add node iterator if add node is null
nop
add_next_valid_inc_1:
lhu add_node, 0(add) # get next add node
addiu add, 2 # increment add node iterator (to be derefernced in next iteration)
add_rem_loop_init_1:
move isrc, $zero # initialize src index
add_rem_loop_1:
rem_test_1:
slt tmp1, isrc, src_len
slt tmp2, $zero, rem_len
and tmp1, tmp2
beqz tmp1, add_test_1 # skip removal if isrc >= src_len || rem_len <= 0
rem_test_2:
addi tmp1, rem_idx, -1
sub tmp1, isrc
bnez tmp1, add_test_1 # skip removal if ((rem_idx-1)-isrc) == 0
nop
rem_do_1:
addi rem_len, -1 # decrement rem length
addiu rem_count, 1 # add to number of ids removed
addiu isrc, 1 # increment src iterator (index-based)
addiu src, 2 # increment src iterator (pointer-based) ['skip' the poly id]
blez rem_len, rem_next_2 # goto rem_next_2 if rem length is <= 0
nop
rem_polyid_next_inc_1:
lhu rem_node, 0(rem) # get next rem node (it will be a poly id)
addiu rem, 2 # increment rem node iterator
rem_intrlv_1:
srl tmp1, rem_node, 15 # shift down the interleave bit
bgez $zero, add_rem_loop_test_1 # goto bottom of loop (end current iteration, test for next)
add rem_idx, tmp1 # and add it to the rem index
rem_next_2:
lhu tmp1, 0(rem) # get next rem node
addiu rem, 2 # increment rem node iterator
slt tmp3, rem, add_start
beqz tmp3, rem_next_null_2 # skip next 2 blocks if rem node iterator at end of rem nodes
move rem_len, $zero # set default rem node poly id count
rem_next_valid_2a:
move rem_node, tmp1
beq rem_node, null, rem_next_null_2 # skip incrementing rem node iterator if current was rem node null
rem_next_valid_2b:
andi rem_idx, rem_node, 0xFFF # get rem index
andi rem_len, rem_node, 0xF000
srl rem_len, 12 # get rem length
bgez $zero, rem_next_inc_2 # skip the null case
addiu rem_len, 1 # (length is minimum of 1)
rem_next_null_2:
sll rem_idx, null, 8 # set rem index to -255
rem_next_inc_2:
blez rem_len, add_rem_loop_test_1 # skip incrementing and go to bottom of loop if current rem node was null
nop
rem_next_valid_inc_2:
lhu rem_node, 0(rem) # get next rem node
addiu rem, 2 # increment rem node iterator
bgez $zero, add_rem_loop_test_1 # goto bottom of loop (end current iteration, test for next)
nop
add_test_1:
blez add_len, copy_test_1 # skip addition if add_len <= 0
add_test_2:
add tmp1, add_idx, rem_count
sub tmp1, isrc
bnez tmp1, copy_test_1 # skip addition if (add_idx-rem_count)-isrc != 0
add_do_1:
andi tmp1, add_node, 0x7FFF # clear polyid interleave bit
sh tmp1, 0(dst) # put polyid in dst list
addiu dst, 2 # increment dst iterator (pointer-based), thus resulting in an append
addiu idst, 1 # increment dst iterator (index-based)
addi add_len, -1 # decrement add length
blez add_len, add_next_2 # skip next 2 blocks if add_len <= 0
nop
add_polyid_next_inc_1:
lhu add_node, 0(add) # get next add node (it will be a poly id)
addiu add, 2 # increment add node iterator
add_intrlv_1:
srl tmp1, add_node, 15 # shift down the interleave bit
bgez $zero, add_rem_loop_test_1 # goto bottom of loop (end current iteration, test for next)
add add_idx, tmp1 # and add it to the add index
add_next_2:
lhu tmp1, 0(add) # get next add node
addiu add, 2 # increment add node iterator
slt tmp3, add, swap
beqz tmp3, add_next_null_2 # skip next 2 blocks if add node iterator at end of add nodes
move add_len, $zero # set default add node poly id count
add_next_valid_2a:
move add_node, tmp1
beq add_node, null, add_next_null_2 # skip incrementing add node iterator if current add node was null
add_next_valid_2b:
andi add_idx, add_node, 0xFFF # get add index
andi add_len, add_node, 0xF000
srl add_len, 12 # get add length
bgez $zero, add_next_inc_2 # skip the null case
addiu add_len, 1 # (length is minimum of 1)
add_next_null_2:
sll add_idx, null, 8 # set add index to -255
add_next_inc_2:
blez add_len, add_rem_loop_test_1 # skip incrementing and go straight to bottom of loop if current add node was null
nop
add_next_valid_inc_2:
lhu add_node, 0(add) # get next add node
addiu add, 2 # increment add node iterator
bgez $zero, add_rem_loop_test_1 # goto bottom of loop (end current iteration, test for next)
nop
copy_test_1:
slt tmp1, isrc, src_len
beqz tmp1, add_rem_loop_test_1 # skip copying/goto bottom of loop if isrc < src_len
copy_test_2:
sub tmp1, rem_idx, isrc
addi tmp1, -1 # (rem_idx-isrc)-1
add tmp2, add_idx, rem_count
sub tmp2, isrc # (add_idx+rem_count)-isrc
slt tmp3, tmp1, tmp2
bnez tmp3, copy_test_2_minr_1 # tmp1 = min((rem_idx-isrc)-1,(add_idx+rem_count)-isrc)
nop
copy_test_2_minl_1:
move tmp1, tmp2
copy_test_2_minr_1:
sub tmp2, src_len, isrc
addi tmp2, -1 # (src_len-isrc)-1
slt tmp3, tmp1, tmp2 # tmp1 = min((rem_idx-isrc)-1,(add_idx+rem_count)-isrc,(src_len-isrc)-1)
bnez tmp3, copy_test_2_minr_2
nop
copy_test_2_minl_2:
move tmp1, tmp2
copy_test_2_minr_2: # note: tmp1 = number of polyids to copy
slti tmp2, tmp1, 2
beqz tmp2, umemcpy16 # goto do an optimized memcpy of polyids if tmp1 < 2
nop
copy_do:
lhu tmp1, 0(src) # get next src poly id
addiu src, 2 # increment src iterator (pointer-based)
sh tmp1, 0(dst) # and append it to dst
addiu dst, 2 # ...incrementing the dst iterator (pointer-based)
addiu idst, 1 # increment src iterator (index-based)
addiu isrc, 1 # increment dst iterator (index-based)
add_rem_loop_test_1:
slt tmp1, isrc, src_len
slt tmp2, $zero, add_len
or tmp1, tmp2
slt tmp2, $zero, rem_len
or tmp1, tmp2
bnez tmp1, add_rem_loop_1 # continue looping if isrc < src_len || add_len > 0 || rem_len > 0
nop
swap_preloop_1:
swap2 = $t6
end = $t7
lhu tmp1, 6(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add swap2, slst_delta, tmp1 # compute absolute address of swap nodes
lhu tmp1, 0(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add end, slst_delta, tmp1 # compute absolute address of end of swap nodes/slst delta
swap_loop_1:
slt tmp2, swap2, end
beqz tmp2, ret_decode_1 # return (end loop) if swap node iterator at end of swap nodes
nop
swap_next_1:
lhu tmp1, 0(swap2) # get next swap node
addiu swap2, 2 # increment swap node iterator
beq tmp1, null, ret_decode_1 # return if swap node is null
swap_next_valid_1:
andi tmp2, tmp1, 0x8000
beqz tmp2, swap_parse_fmtbc_1 # goto parse format b or c if bit 16 is set
swap_parse_fmta_1: # else parse the format a swap node
andi swap_r, tmp1, 0x7800
srl swap_r, 11
bgez $zero, swap_do_1 # goto do the swap
andi swap_l, tmp1, 0x7FF
swap_parse_fmtbc_1: # parse format b or c
andi tmp2, tmp1, 0xC000
li tmp3, 0x4000
bne tmp2, tmp3, swap_parse_fmtb_1 # goto parse format b if bit 15 is clear
swap_parse_fmtc_1: # else parse the format c swap node
andi swap_r, tmp1, 0x1F
addiu swap_r, 0x10
andi tmp2, tmp1, 0x3FE0
srl tmp2, 5
bgez $zero, swap_do_1 # goto do the swap
addu swap_l, tmp2
swap_parse_fmtb_1: # parse format b
andi swap_l, tmp1, 0xFFF
lhu tmp1, 0(swap2)
addiu swap2, 2 # get and parse additional hword for format b node
andi swap_r, tmp1, 0xFFF
swap_do_1: # do the swap
move tmp3, swap_l # save current swap_l; it will need to be restored
addiu swap_r, 1 # swap_r is relative index of minimum 1
addu swap_r, swap_l # swap_r is relative to swap_l, so add for absolute index
sll swap_r, 1
sll swap_l, 1 # convert indices to offsets
addiu tmp1, $a2, 4 # recompute start address of dst nodes
addu swap_l, tmp1
addu swap_r, tmp1 # convert to dst node pointers
lhu tmp1, 0(swap_l)
lhu tmp2, 0(swap_r)
sh tmp1, 0(swap_r)
sh tmp2, 0(swap_l) # swap
bgez $zero, swap_loop_1 # continue
move swap_l, tmp3 # restore the saved swap_l
ret_decode_1:
sh idst, 0($a2) # write length to the destination list
sload
jr $ra # return
nop
#
# apply changes to a poly id list for a backward change in path progress
# using an slst delta item
#
# a0 = slst delta item
# a1 = source poly id list
# a2 = destination poly id list
#
RSlstDecodeBackward:
slst_delta = $a0 # slst delta item
src = $t6 # source list iterator (pointer-based)
src_len = $gp # source list length
dst = $s1 # destination list iterator (pointer-based)
# dst_len = ? # destination list length
isrc = $v1 # source list iterator (index-based)
idst = $v0 # destination list iterator (index-based)
add = $t7 # iterator/pointer to current add node
rem = $s0 # iterator/pointer to current rem node
swap = $t7 # iterator/pointer to current swap node
swap_start = $t6 # pointer to the first swap node (or 1 short after the last add node)
add_idx = $t0 # index in dst list at which to begin adding poly ids for the current add node
rem_idx = $t1 # index in src list at which to begin removing poly ids for the current rem node
add_len = $t2 # remaining number of poly ids to add for the current add node
rem_len = $t3 # remaining number of poly ids to remove for the current rem node
add_count = $t4 # number of poly ids added thus far for the current add node
rem_count = $t5 # number of poly ids removed thus far for the current rem node
add_node = $s7 # current add node
rem_node = $t8 # current rem node
swap_l = $s4 # pointer to left poly id for the current swap
swap_r = $s3 # pointer to right poly id for the current swap
null = $s6 # null index
tmp1 = $at
tmp2 = $a3
tmp3 = $t9
swap = $t7
start = $t6
ssave
lhu tmp1, 0(slst_delta)
nop
addi tmp1, -1
sll tmp1, 1
addiu tmp1, 4
add swap, slst_delta, tmp1 # compute absolute address of last swap node
lhu tmp1, 6(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add swap_start, slst_delta, tmp1 # compute absolute address of start of swap nodes
swap_loop_2:
slt tmp2, swap, swap_start
bnez tmp2, ret_decode_2 # break loop if swap node iterator at start of swap nodes
nop
swap_next_2:
lhu tmp1, 0(swap) # get next swap node
addiu swap, -2 # decrement swap node iterator
beq tmp1, null, swap_loop_2 # skip if swap node is null
swap_next_valid_2:
andi tmp2, tmp1, 0x8000
beqz tmp2, swap_parse_fmtbc_2 # goto parse format b or c if bit 16 is not set
swap_parse_fmta_2: # else parse the format a swap node
andi swap_r, tmp1, 0x7800
srl swap_r, 11
bgez $zero, swap_do_2 # goto do the swap
andi swap_l, tmp1, 0x7FF
swap_parse_fmtbc_2: # parse format b or c
andi tmp2, tmp1, 0xC000
li tmp3, 0x4000
bne tmp2, tmp3, swap_parse_fmtb_2 # goto parse format b if bit 15 is clear
swap_test_next_fmtb_2: # else...
lhu tmp2, 0(swap) # peek at the next (previous memory-wise) swap node
nop
andi tmp3, tmp2, 0x8000
beqz tmp3, swap_parse_next_fmtb_2 # goto parse it if its a format b (or c?)
swap_parse_fmtc_2a: # else parse the cur node as a format c
nop
andi swap_l, tmp2, 0x7FF # extract bits for the left relative index
bgez $zero, swap_parse_fmtc_2b # goto do the remainder of the parse
nop
swap_parse_next_fmtb_2:
lhu tmp2, -2(swap)
nop
andi swap_l, tmp2, 0xFFF # extract bits [from next format b node] as left relative index
swap_parse_fmtc_2b:
andi swap_r, tmp1, 0x1F
addiu swap_r, 0x10
andi tmp2, tmp1, 0x3FE0
srl tmp2, 5
bgez $zero, swap_do_2 # goto do the swap
addu swap_l, tmp2 # add tmp2 to swap_l [left relative index from either cur format c or next format b]
swap_parse_fmtb_2: # parse format b
andi swap_r, tmp1, 0xFFF
lhu tmp1, 0(swap2)
addiu swap2, -2 # get and parse additional hword for format b node
andi swap_l, tmp1, 0xFFF
swap_do_2: # do the swap
addiu swap_r, 1 # swap_r is relative index of minimum 1
addu swap_r, swap_l # swap_r is relative to swap_l, so add for absolute index
sll swap_r, 1
sll swap_l, 1 # convert indices to offsets
addiu tmp1, $a1, 4 # recompute start address of dst nodes
addu swap_l, tmp1
addu swap_r, tmp1 # convert to dst node pointers
lhu tmp1, 0(swap_l)
lhu tmp2, 0(swap_r)
sh tmp1, 0(swap_r)
sh tmp2, 0(swap_l) # swap
bgez $zero, swap_loop_2 # continue
addrem_init_2:
move idst, $zero # initialize dst index
move add_count, $zero # initialize add node [poly id] count
move rem_count, $zero # initialize rem node [poly id] count
addiu add, slst_delta, 8 # initialize add node iterator
lhu tmp1, 4(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add swap, slst_delta, tmp1 # compute absolute address of swap nodes
move rem, swap # initialize rem node iterator
lhu tmp1, 6(slst_delta)
nop
sll tmp1, 1
addiu tmp1, 4
add add_start, slst_delta, tmp1 # compute absolute address of start of add nodes
addiu src, $a1, 4 # initialize src list iterator
lhu src_len, 0($a1) # get length of src list
addiu dst, $a2, 4 # initialize dst list iterator
rem_next_3:
lhu tmp1, 0(rem) # get first rem node
addiu rem, 2 # increment rem node iterator
slt tmp3, rem, add_start
beqz tmp3, rem_next_null_3 # skip next 2 blocks if rem node iterator at end of rem nodes
move rem_len, $zero # set default rem node poly id count
rem_next_valid_3a:
move rem_node, tmp1
beq rem_node, null, rem_next_null_3 # skip next block if rem node is null
rem_next_valid_3b:
andi rem_idx, rem_node, 0xFFF # get rem index
andi rem_len, rem_node, 0xF000
srl rem_len, 12 # get rem length
bgez $zero, rem_next_inc_3 # skip the null case
addiu rem_len, 1 # (length is minimum of 1)
rem_next_null_3:
sll rem_idx, null, 8 # set rem idx to -255
rem_next_inc_3:
blez rem_len, add_next_3 # skip incrementing rem node iterator if rem node is null
nop
rem_next_valid_inc_3:
lhu rem_node, 0(rem) # grab next rem node
addiu rem, 2 # increment rem node iterator (to be dereferenced in next iteration)
add_next_3:
lhu tmp1, 0(add) # get first add node
addiu add, 2 # increment add node iterator
slt tmp3, add, swap
beqz tmp3, add_next_null_3 # skip next 2 blocks if add node iterator at end of add nodes
move add_len, $zero # set default add node poly id count
add_next_valid_3a:
move add_node, tmp1
beq add_node, null, add_next_null_3 # skip next block if add node is null
add_next_valid_3b:
andi add_idx, add_node, 0xFFF # get add index
andi add_len, add_node, 0xF000
srl add_len, 12 # get add length
bgez $zero, add_next_inc_3 # skip the null case
addiu add_len, 1 # (length is minimum of 1)
add_next_null_3:
sll add_idx, null, 8 # set add idx to -255
add_next_inc_3:
blez add_len, add_rem_loop_init_2 # skip incrementing add node iterator if add node is null
nop
add_next_valid_inc_3:
lhu add_node, 0(add) # get next add node
addiu add, 2 # increment add node iterator (to be derefernced in next iteration)
add_rem_loop_init_2:
move isrc, $zero # initialize src index
add_rem_loop_3:
rem_test_3:
slt tmp1, isrc, src_len
slt tmp2, $zero, rem_len
and tmp1, tmp2
beqz tmp1, add_test_3 # skip removal if isrc >= src_len || rem_len <= 0
rem_test_4:
addi tmp1, rem_idx, rem_count
sub tmp1, isrc
bnez tmp1, add_test_3 # skip removal if ((rem_idx+rem_count)-isrc) == 0
nop
rem_do_2:
addi rem_len, -1 # decrement rem length
addiu rem_count, 1 # add to number of ids removed
addiu isrc, 1 # increment src iterator (index-based)
addiu src, 2 # increment src iterator (pointer-based) ['skip' the poly id]
blez rem_len, rem_next_4 # skip next 2 blocks if rem length is <= 0
nop
rem_polyid_next_inc_3:
lhu rem_node, 0(rem) # get next rem node (it will be a poly id)
addiu rem, 2 # increment rem node iterator
rem_intrlv_3:
srl tmp1, rem_node, 15 # shift down the interleave bit
bgez $zero, add_rem_loop_test_2 # goto bottom of loop (end current iteration, test for next)
add rem_idx, tmp1 # and add it to the rem index
rem_next_4:
lhu tmp1, 0(rem) # get next rem node
addiu rem, 2 # increment rem node iterator
slt tmp3, rem, add_start
beqz tmp3, rem_next_null_4 # skip next 2 blocks if rem node iterator at end of rem nodes
move rem_len, $zero # set default rem node poly id count
rem_next_valid_4a:
move rem_node, tmp1
beq rem_node, null, rem_next_null_4 # skip incrementing rem node iterator if current was rem node null
rem_next_valid_4b:
andi rem_idx, rem_node, 0xFFF # get rem index
andi rem_len, rem_node, 0xF000
srl rem_len, 12 # get rem length
bgez $zero, rem_next_inc_4 # skip the null case
addiu rem_len, 1 # (length is minimum of 1)
rem_next_null_4:
sll rem_idx, null, 8 # set rem index to -255
rem_next_inc_4:
blez rem_len, add_rem_loop_test_2 # skip incrementing and go to bottom of loop if current rem node was null
nop
rem_next_valid_inc_4:
lhu rem_node, 0(rem) # get next rem node
addiu rem, 2 # increment rem node iterator
bgez $zero, add_rem_loop_test_2 # goto bottom of loop (end current iteration, test for next)
nop
add_test_3:
blez add_len, copy_test_3 # skip addition if add_len <= 0
add_test_4:
add tmp1, add_idx, rem_count
sub tmp1, add_count
addiu tmp1, -1
sub tmp1, isrc
bnez tmp1, copy_test_4 # skip addition if (add_idx+rem_count)-add_count-1-isrc != 0
add_do_3:
andi tmp1, add_node, 0x7FFF # clear polyid interleave bit
sh tmp1, 0(dst) # put polyid in dst list
addiu dst, 2 # increment dst iterator (pointer-based), thus resulting in an append
addiu idst, 1 # increment dst iterator (index-based)
addi add_len, -1 # decrement add length
addiu add_count, 1 # increment add count
blez add_len, add_next_4 # skip next 2 blocks if add_len <= 0
nop
add_polyid_next_inc_3:
lhu add_node, 0(add) # get next add node (it will be a poly id)
addiu add, 2 # increment add node iterator
add_intrlv_3:
srl tmp1, add_node, 15 # shift down the interleave bit
bgez $zero, add_rem_loop_test_2 # goto bottom of loop (end current iteration, test for next)
add add_idx, tmp1 # and add it to the add index
add_next_4:
lhu tmp1, 0(add) # get next add node
addiu add, 2 # increment add node iterator
slt tmp3, add, swap
beqz tmp3, add_next_null_4 # skip next 2 blocks if add node iterator at end of add nodes
move add_len, $zero # set default add node poly id count
add_next_valid_4a:
move add_node, tmp1
beq add_node, null, add_next_null_4 # skip incrementing add node iterator if current add node was null
add_next_valid_4b:
andi add_idx, add_node, 0xFFF # get add index
andi add_len, add_node, 0xF000
srl add_len, 12 # get add length
bgez $zero, add_next_inc_4 # skip the null case
addiu add_len, 1 # (length is minimum of 1)
add_next_null_4:
sll add_idx, null, 8 # set add index to -255
add_next_inc_4:
blez add_len, add_rem_loop_test_2 # skip incrementing and go straight to bottom of loop if current add node was null
nop
add_next_valid_inc_4:
lhu add_node, 0(add) # get next add node
addiu add, 2 # increment add node iterator
bgez $zero, add_rem_loop_test_2 # goto bottom of loop (end current iteration, test for next)
nop
copy_test_3:
slt tmp1, isrc, src_len
beqz tmp1, add_rem_loop_test_2 # skip copying/goto bottom of loop if isrc < src_len
copy_test_4:
add tmp1, rem_idx, rem_count
sub tmp1, isrc # ((rem_idx+rem_count)-isrc)
add tmp2, add_idx, rem_count
sub tmp2, add_count
addi tmp2, -1
sub tmp2, isrc # ((add_idx+add_count)+rem_count-1-isrc)
slt tmp3, tmp1, tmp2
bnez tmp3, copy_test_4_minr_1 # tmp1 = min((rem_idx+rem_count)-isrc,(add_idx+add_count)+rem_count-1-isrc)
nop
copy_test_4_minl_1:
move tmp1, tmp2
copy_test_4_minr_1:
sub tmp2, src_len, isrc
addi tmp2, -1 # (src_len-isrc)-1
slt tmp3, tmp1, tmp2 # tmp1 = min((rem_idx+rem_count)-isrc,(add_idx+add_count)+rem_count-1-isrc,(src_len-isrc)-1)
bnez tmp3, copy_test_4_minr_2
nop
copy_test_4_minl_2:
move tmp1, tmp2
copy_test_4_minr_2:
slti tmp2, tmp1, 2
beqz tmp2, umemcpy16 # goto do an optimized memcpy of polyids if tmp1 (count) >= 2
nop
copy_do_2: # copy a single poly id from src to dst
lhu tmp1, 0(src) # get next src poly id
addiu src, 2 # increment src iterator (pointer-based)
sh tmp1, 0(dst) # and append it to dst
addiu dst, 2 # ...incrementing the dst iterator (pointer-based)
addiu idst, 1 # increment src iterator (index-based)
addiu isrc, 1 # increment dst iterator (index-based)
add_rem_loop_test_2:
slt tmp1, isrc, src_len
slt tmp2, $zero, add_len
or tmp1, tmp2
slt tmp2, $zero, rem_len
or tmp1, tmp2
bnez tmp1, add_rem_loop_2 # continue looping if isrc < src_len || add_len > 0 || rem_len > 0
nop
ret_decode_2:
sh idst, 0($a2) # write length to the destination list
sload
jr $ra # return
nop
#
# partial loop-unrolled hword memcpy
#
# at = count
# t6 = src (hword pointer)
# s1 = dst (hword pointer)
#
umemcpy16:
src = $t6
dst = $s1
umemcpy16_test_1:
add $v0, $at
add $v1, $at
slti $s2, $at, 5
bnez $s2, umemcpy16_lteq5 # if count (at+1) <= 5, goto count-specific hword copy
umemcpy16_test_2:
andi $s2, src, 3
beqz $s2, umemcpy16_test_asrc # if src is word-aligned
umemcpy16_test_msrc:
andi $s3, dst, 3
beqz $s3, umemcpy16_msrc # if dst is word-aligned (and src is not)
umemcpy16_misal:
nop # src and dst are non-word-aligned
lhu $s2, 0(src)
addiu src, 2
sh $s2, 0(dst)
addiu dst, 2 # copy an hword so that src and dst are moved to a multiple of 4
bgez $zero, umemcpy16_loop
addiu $at, -1
jr $ra
nop
# ---------------------------------------------------------------------------
umemcpy16_test_asrc:
bnez $s3, umemcpy16_mdst # if dst is non-word-aligned
nop
umemcpy16_loop:
umemcpy16_test_3:
sltiu $s2, $at, 4
bnez $s2, umemcpy16_lteq5 # if count < 4, goto count-specific hword copy
umemcpy16_test_4:
sltiu $s2, $at, 9
beqz $s2, umemcpy16_gteq9 # if count >= 9, goto count-specific hword copy
umemcpy16_bt_4_8: # count is between 4 and 8
andi $s5, $at, 3
subu $at, $s5 # floor count to nearest multiple of 4 (4=>4, 5=>4, 6=>4, 7=>4, 8=>8)
li $s4, umemcpy16_gteq9_inc
sll $s2, $at, 2
subu $s4, $s2
jr $s4 # jump to one of the 2 jump dests below, to copy either the next 4 or 8 hwords
nop
# ---------------------------------------------------------------------------
umemcpy16_gteq9:
addiu $s5, $at, -8 # decrement count by 8
li $at, 8 # temporarily replace count with the increment amount
lw $s3, 0xC(src) # jump dest # copy the next 8 hwords/4 words
lw $s2, 8(src) # ...
sw $s3, 0xC(dst)
sw $s2, 8(dst)
lw $s3, 4(src) # jump dest
lw $s2, 0(src)
sw $s3, 4(dst)
sw $s2, 0(dst) # ...
umemcpy16_gteq9_inc:
addu src, $at
addu src, $at # increment src by 16 bytes/8 hwords
addu dst, $at
addu dst, $at # increment dst by 16 bytes/8 hwords
bgez $zero, umemcpy16_loop # continue
move $at, $s5 # restore the decremented count
umemcpy16_mdst: # dst is misaligned...
umemcpy16_mdst_test_1:
sltiu $s2, $at, 4
bnez $s2, umemcpy16_lteq5 # if count < 4, goto count-specific hword copy
umemcpy16_mdst_test_2:
sltiu $s2, $at, 9
beqz $s2, umemcpy16_mdst_copy # if count >= 9, goto count-specific hword copy for misaligned dst
umemcpy16_mdst_bt_4_8: # count is between 4 and 8
andi $s5, $at, 3 # s5 = count % 4; this will be the remaining count after the below copy, and will be restored
subu $at, $s5 # temporarily floor count to nearest multiple of 4
li $s4, umemcpy16_mdst_copy
sll $s3, $at, 2
addu $s3, $at
sll $s3, 1
subu $s4, $s3 # get address of the jump dest below, to copy the next 4 or 8 hwords ((uint32_t*)umemcpy16_mdst_copy - count*3)
addu $a3, $at, $at
addu $a3, dst, $a3
lhu $s2, 0($a3) # load the 5th or 9th hword from dst
jr $s4 # jump
nop
# ---------------------------------------------------------------------------
umemcpy16_mdst_copy:
addiu $s5, $at, -8 # decrement count by 8 to get remaining count (when count >= 9)
li $at, 8
addu $a3, $at, $at
addu $a3, dst, $a3
lhu $s2, 0($a3) # load 9th hword from dst *((uint16_t*)dst+8)
lw $t9, 0xC(src) # jump dst # load 8th and 7th hword from src *((uint32_t*)src+3)
sll $s3, $s2, 16 # shift 9th hword from dst to upper hword
srl $a3, $t9, 16 # shift 8th hword from src to lower hword
or $s3, $a3 # or the values
sw $s3, 0xE(dst) # store as 9th and 8th hwords of dst
lw $s2, 8(src) # load 6th and 5th hword from src
sll $s3, $t9, 16 # shift 7th hword from src to upper hword
srl $a3, $s2, 16 # shift 6th hword from src to lower hword
or $s3, $a3 # or the values (count=$at is 4 if this is the jump dst)
sw $s3, 0xA(dst) # store as 7th and 6th hwords of dst
lw $t9, 4(src) # jump dst # load 4th and 3rd hword from src
sll $s3, $s2, 16 # shift 5th hword from src to upper hword
srl $a3, $t9, 16 # shift 4th hword from src to lower hword
or $s3, $a3 # or the values
sw $s3, 6(dst) # store as 5th and 4th hwords of dst
lw $s2, 0(src) # load 2nd and 1st hword from src
sll $s3, $t9, 16 # shift 3rd hword from src to upper hword
srl $a3, $s2, 16 # shift 2nd hword from src to lower hword
or $s3, $a3 # or the values
sw $s3, 2(dst) # store as 3rd and 2nd hwords of dst
umemcpy16_mdst_inc:
sh $s2, 0(dst) # store 1st hword from src as 1st hword of dst
addu src, $at
addu src, $at # increment src by count*sizeof(uint16_t) bytes (8 or 16)
addu dst, $at
addu dst, $at # increment dst by count*sizeof(uint16_t) bytes (8 or 16)
bgez $zero, umemcpy16_loop # continue
move $at, $s5 # restore the remaining count
umemcpy16_msrc: # src is misaligned...
umemcpy16_msrc_test_1:
sltiu $s2, $at, 4 # if count < 4, goto count-specific hword copy
bnez $s2, loc_80033ED4
umemcpy16_msrc_test_2:
sltiu $s2, $at, 9
beqz $s2, loc_80033E58 # if count >= 9, goto count-specific hword copy for misaligned src
umemcpy16_msrc_bt_4_8: # count is between 4 and 8
andi $s5, $at, 3 # s5 = count % 4; this will be the remaining count after the below copy, and will be restored
subu $at, $s5 # temporarily floor count to nearest multiple of 4
li $s4, umemcpy16_msrc_copy
sll $s3, $at, 2
addu $s3, $at
sll $s3, 1
subu $s4, $s3 # get address of the jump dest below, to copy the next 4 or 8 hwords ((uint32_t*)umemcpy16_msrc_copy - count*3)
addu $a3, $at, $at
addu $a3, src, $a3
lhu $s2, -2($a3) # load the 4th or 8th hword from src
jr $s4 # jump
nop
# ---------------------------------------------------------------------------
umemcpy16_msrc_copy:
addiu $s5, $at, -8 # decrement count by 8 to get remaining count (when count >= 9)
li $at, 8 # jump dst
addu $a3, $at, $at
addu $a3, src, $a3
lhu $s2, -2($a3) # load 8th hword from src *((uint16_t*)src+7)
lw $t9, 0xA(src) # load 7th and 6th hword from src
sll $s3, $s2, 16 # shift 8th hword from src to upper hword
srl $a3, $t9, 16 # shift 7th hword from src to lower hword
or $s3, $a3 # or the values
sw $s3, 0xC(dst) # store as 8th and 7th hwords of dst
lw $s2, 6(src) # load 5th and 4th hword from src
sll $s3, $t9, 16 # shift 6th hword from src to upper hword
srl $a3, $s2, 16 # shift 5th hword from src to lower hword
or $s3, $a3 # jump dst # or the values
sw $s3, 8(dst) # store as 6th and 5th hwords of dst
lw $t9, 2(src) # load 3rd and 2nd hword from src
sll $s3, $s2, 16 # shift 4th hword from src to upper hword
srl $a3, $t9, 16 # shift 3rd hword from src to lower hword
or $s3, $a3 # or the values
sw $s3, 4(dst) # store as 4th and 3rd hwords of dst
lw $s2, -2(src) # load 1st hword from src and the hword before src
sll $s3, $t9, 16 # shift 2nd hword from src to upper hword
srl $a3, $s2, 16 # shift 1st hword from src to lower hword
or $s3, $a3 # or the values
sw $s3, 0(dst) # store as 2nd and 1st hwords of dst
umemcpy16_msrc_inc:
addu src, $at
addu src, $at # increment src by count*sizeof(uint16_t) bytes (8 or 16)
addu dst, $at
addu dst, $at # increment dst by count*sizeof(uint16_t) bytes (8 or 16)
bgez $zero, umemcpy16_loop # continue
move $at, $s5 # restore the remaining count
umemcpy16_lteq5:
lhu $s2, 0(src)
li $s4, umemcpy_lteq5_copy
sll $s3, $at, 5
addu $s4, $s3 # calc address for the appropriate 32 byte section
sll $s3, $at, 1
addu src, $s3
jr $s4 # jump
addu dst, $s3
umemcpy16_lteq5_copy: # below sections copy 0,1,2,3,4, and >=5 hwords, respectively, and then return
jr $ra
nop
# ---------------------------------------------------------------------------
.word 0, 0, 0, 0, 0, 0
# ---------------------------------------------------------------------------
jr $ra
sh $s2, -2(dst)
# ---------------------------------------------------------------------------
.word 0, 0, 0, 0, 0, 0
# ---------------------------------------------------------------------------
lhu $s3, -2(src)
sh $s2, -4(dst)
jr $ra
sh $s3, -2(dst)
# ---------------------------------------------------------------------------
.word 0, 0, 0, 0
# ---------------------------------------------------------------------------
lhu $s3, -4(src)
sh $s2, -6(dst)
lhu $s2, -2(src)
sh $s3, -4(dst)
jr $ra
sh $s2, -2(src)
# ---------------------------------------------------------------------------
.word 0, 0
# ---------------------------------------------------------------------------
lhu $s3, -6(src)
sh $s2, -8(dst)
lhu $s2, -4(src)
sh $s3, -6(dst)
lhu $s3, -2(src)
sh $s2, -4(dst)
jr $ra
sh $s3, -2(src)
addi $at, -1
umemcpy16_eq5:
umemcpy16_eq5_loop:
lhu $a3, 0(src)
addiu $t6, 2
sh $a3, 0(dst)
addiu $s1, 2
bnez $at, umemcpy16_eq5_loop
addi $at, -1
umemcpy16_ret:
jr $ra
nop
#
# reset the ot with an incrementing sequence of tags
#
# a0 = base address of sequence
# a1 = length of ot in words
#
RGpuResetOT:
li t0, 0xFFFFFF
and $at, $a0, $t0
srl $a1, 6
addui $a1, -1
ot_copy_loop:
copy_w_seq_unr $at, $a0, 0, 0x100
beqz $a1, ret_ot_copy
addiu $a0, 0x100
bgez $zero, ot_copy_loop
addi $a1, -1
ret_ot_copy:
jr $ra
#
# increment the total number of ticks elapsed
#
# this is an event handler/callback function
# which is triggered for each root counter tick
#
RIncTickCount:
li $v1, ticks_elapsed
lw $v0, 0($v1)
nop
addiu $v0, 1
jr $ra
sw $v0, 0($v1)
# ---------------------------------------------------------------------------
ticks_elapsed: .word 0
#
# compute the squared magnitude of 2 values (v1^2 + v2^2)
#
# a0 = first value (n bit fractional fixed point)
# a1 = second value (n bit fractional fixed point)
# output = result (2n - 13 bit fractional fixed point; use n=13 for no change)
#
RSqrMagnitude2:
# abs values are computed before squaring; possibly to keep from multiplying negative numbers
sqr_mag_2_abs_val1_test:
bgez $a0, sqr_mag_2_val1_gt0
nop
sqr_mag_2_val1_lt0:
negu $a0, $a0
sqr_mag_2_val1_gt0:
sqr_mag_2_abs_val2_test:
bgez $a1, sqr_mag_2_val2_gt0
nop
sqr_mag_2_val2_lt0:
negu $a1, $a1
sqr_mag_2_val2_gt0:
# ---
sqr_mag_2:
mult $a0, $a0
mflo $a2 # get lower word of the result of $a0*$a0 (a 64-bit value)
mfhi $a3 # get upper word of the result of $a0*$a0 (a 64 bit value)
nop
nop
mult $a1, $a1
mflo $t0 # get lower word of the result of $a1*$a1 (a 64-bit value)
mfhi $t1 # get upper word of the result of $a1*$a1 (a 64-bit value)
addu $v0, $a2, $t0 # compute sum of lower words of both results
sltu $v1, $v0, $a2 # set a carry bit if result overflows (i.e. $a2 + $t0 < $a2 implies a carry)
addu $v1, $a3 # add carry bit to upper word of first result
addu $v1, $t1 # add upper words of second result and first result
srl $v0, 13 # select upper 19 bits of sum of lower words as lower 19 bits
sll $v1, 19 # select lower 13 bits of sum of upper words as upper 13 bits
jr $ra # return
or $v0, $v1 # or the selected bits
#
# compute the squared magnitude of 3 values (v1^2 + v2^2 + v3^2)
#
# a0 = first value (n bit fractional fixed point)
# a1 = second value (n bit fractional fixed point)
# a2 = third value (n bit fractional fixed point)
# output = result (2n - 20 bit fractional fixed point; use n=20 for no change, n=10 for integer result)
#
RSqrMagnitude3:
# abs values are computed before squaring; possibly to keep from multiplying negative numbers
sqr_mag_3_abs_val1_test:
bgez $a0, sqr_mag_3_val1_gt0
nop
sqr_mag_3_val1_lt0:
negu $a0, $a0
sqr_mag_3_val1_gt0:
sqr_mag_3_abs_val2_test:
bgez $a1, sqr_mag_3_val2_gt0
nop
sqr_mag_3_val2_lt0:
negu $a1, $a1
sqr_mag_3_val2_gt0:
sqr_mag_3_abs_val3_test:
bgez $a2, sqr_mag_3_val3_gt0
nop
sqr_mag_3_val3_lt0:
negu $a2, $a2
sqr_mag_3_val3_gt0:
# --
sqr_mag_3:
mult $a0, $a0
mflo $a3 # get lower word of the result of $a0*$a0 (a 64-bit value)
mfhi $t0 # get upper word of the result of $a0*$a0 (a 64-bit value)
nop
nop
mult $a1, $a1
mflo $t1 # get lower word of the result of $a1*$a1 (a 64-bit value)
mfhi $t2 # get upper word of the result of $a1*$a1 (a 64-bit value)
nop
nop
mult $a2, $a2
mflo $a0 # get lower word of the result of $a2*$a2 (a 64-bit value)
mfhi $a1 # get upper word of the result of $a2*$a2 (a 64-bit value)
addu $v0, $a3, $t1 # compute sum of lower words of first two results
sltu $v1, $v0, $a3 # set a carry bit if result overflows (i.e. $a3 + $t1 < $a3 implies a carry)
addu $v1, $t0 # add carry bit to upper word of first result
addu $v1, $t2 # add upper words of first and second result
addu $a2, $v0, $a0 # add sum of lower words of first two results to lower word of third result
sltu $a3, $a2, $v0 # set a carry bit if result overflows (i.e. $v0 + $a0 < $v0 implies a carry)
addu $a3, $v1 # add carry bit to sum of upper words of first and second result
addu $a3, $a1 # add upper word of third result to sum of upper words of first and second result
srl $a2, 20 # select upper 12 bits of sum of lower words as lower 12 bits
sll $a3, 12 # select lower 20 bits of sum of upper words as upper 20 bits
jr $ra # return
or $v0, $a3, $a2 # or the selected bits
#
# translate, rotate, and perspective transform an array of tgeo polys for a given
# svtx frame, and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# by default, polys are phong shaded given the texinfo rgb value and current
# light matrix, color matrix, and back color set in the GTE. if the is_flat_shaded
# flag of the texinfo is set, this behavior is overridden.
#
# the flag argument enables 3/2 the sum of min and max transformed poly vert z values
# to be used instead of the sum of all 3 verts, when computing average for the ot index
#
# a0 = svtx_frame = (in) svtx vertex animation frame item
# a1 = ot = (in) ot
# a2 = polys = (in) array of tgeo polygons
# a3 = header = (in) tgeo header item
# 0x10($sp) = cull_mask = (in) bitmask xor'ed with projected poly normal value which rejects when < 0
# 0x14($sp) = far = (in) far value
# 0x18($sp) = prims_tail = (inout) pointer to current tail pointer of primitive buffer
# 0x1C($sp) = regions = (in) table of precomputed uv coordinate rects/'regions'
# 0x20($sp) = flag = (in) see above
#
RGteTransformSvtx:
arg_0 = 0
arg_10 = 0x10
arg_14 = 0x14
arg_18 = 0x18
arg_1C = 0x1C
arg_20 = 0x20
poly = $a2
prim = $a3
verts = $t3
regions = $s7
poly_idx = $t5
flag = $t7
ssave
lw cull_mask, arg_10($sp) # get mask value for backface culling
lw $t1, arg_14($sp) # get far value argument
lw $t2, arg_18($sp) # get argument value which is a pointer to prims_tail
lw regions, arg_1C($sp)
lw flag, arg_20($sp)
sll $t1, 2 # multiply far value as an index by sizeof(void*) to convert to an ot offset
li $t9, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t8, 0x60 # '`' # load mask for selecting semi-trans mode
lui $gp, 0x600 # load len for POLY_G3
lw $at, 8($a0) # $at = frame->x
lw $v0, 0xC($a0) # $v0 = frame->y
lw $v1, 0x10($a0) # $v1 = frame->z
addiu $at, -128 # $at = frame->x - 128
addiu $v0, -128 # $v0 = frame->y - 128
addiu $v1, -128 # $v1 = frame->z - 128
addiu verts, $a0, 0x38 # verts = &frame->vertices
addiu texinfos, $a3, 0x14 # texinfos = &header->texinfos
lw i_poly, 0($a3) # i_poly = header->poly_count
# note: i_poly is a reverse/'count-remaining' type iterator,
prim = $a3 # but the 'poly' pointer itself is a forward iterator
lw prim, 0($t2) # get pointer to a new prim
transform_svtx_loop:
lw $sp, 0(poly) # get cur poly word 1
lw $fp, 4(poly) # get cur poly word 2
nop
andi $ra, $sp, 0xFFFF # get offset of vert 1 from lower hword of cur poly word 1
addu $s0, verts, $ra # get pointer to vert 1
srl $ra, $sp, 16 # get offset of vert 2 from upper hword of cur poly word 1
addu $s1, $t3, $ra # get pointer to vert 2
andi $ra, $fp, 0xFFFF # get offset of vert 3 from lower hword of cur poly word 2
addu $s2, $t3, $ra # get pointer to vert 3
srl $ra, $fp, 16 # get flag and texinfo offset from upper hword of cur poly word 2
andi $t2, $ra, 0x8000 # select is_flat_shaded bit
andi $ra, 0x7FFF # select texinfo offset
sll $ra, 2 # multiply texinfo offset by 4, as it is stored / 4
addu $t6, texinfos, $ra # get a pointer to the texinfo
lhu $s6, 0($s0) # get vert 1 xy from first hword
# $s6 = (vert1->y << 8) | vert1->x
lhu $s3, 2($s0) # get vert 1 z and normal x from second hword
# $s3 = (vert1->normal_x << 8) | vert1->z
srl $fp, $s6, 8 # $fp = vert1->y
addu $fp, $v0 # $fp = vert1->y + (frame->y - 128)
sll $fp, 18 # $fp = ((vert1->y + (frame->y - 128))*4) << 16
andi $sp, $s6, 0xFF # $fp = vert1->x
addu $sp, $at # $fp = vert1->x + (frame->x - 128)
sll $sp, 2 # $fp = (vert1->x + (frame->x - 128))*4
andi $sp, 0xFFFF
or $fp, $sp # $fp = (((vert1->y + (frame->y - 128))*4) << 16) | ((vert1->x + (frame->x - 128))*4)
mtc2 $fp, $0 # set GTE VXY0 to $fp
andi $sp, $s3, 0xFF # $sp = vert1->z
addu $sp, $v1 # $sp = vert1->z + (frame->z - 128)
sll $sp, 2 # $sp = (vert1->z + (frame->z - 128))*4
mtc2 $sp, $1 # set GTE VZ0 to $sp
# GTE V0 = [(vert1->x + (frame->x - 128))*4]
# [(vert1->y + (frame->y - 128))*4]
# [(vert1->z + (frame->z - 128))*4]
lhu $s6, 0($s1) # repeat for vert 2...
lhu $s4, 2($s1)
srl $fp, $s6, 8
addu $fp, $v0
sll $fp, 18
andi $sp, $s6, 0xFF
addu $sp, $at
sll $sp, 2
andi $sp, 0xFFFF
or $fp, $sp
mtc2 $fp, $2 # set GTE VXY1 to $fp
andi $sp, $s4, 0xFF
addu $sp, $v1
sll $sp, 2
mtc2 $sp, $3 # set GTE VZ1 to $sp
# GTE V1 = [(vert2->x + (frame->x - 128))*4]
# [(vert2->y + (frame->y - 128))*4]
# [(vert2->z + (frame->z - 128))*4]
lhu $s6, 0($s2) # repeat for vert 3...
lhu $s5, 2($s2)
srl $fp, $s6, 8
addu $fp, $v0
sll $fp, 18
andi $sp, $s6, 0xFF
addu $sp, $at
sll $sp, 2
andi $sp, 0xFFFF
or $fp, $sp
mtc2 $fp, $4 # set GTE VXY2 to $fp
andi $sp, $s5, 0xFF
addu $sp, $v1
sll $sp, 2
mtc2 $sp, $5 # set GTE VZ2 to $sp
# GTE V2 = [(vert3->x + (frame->x - 128))*4]
# [(vert3->y + (frame->y - 128))*4]
# [(vert3->z + (frame->z - 128))*4]
lw $a0, 0($t6) # get texinfo word 1
cop2 0x280030 # translate, rotate, and perspective transform verts
cfc2 $sp, $31 # get GTE flag
mtc2 $a0, $6 # set GTE RGB = texinfo rgb value
bltz $sp, loc_80034A98 # skip this poly if transformation resulted in limiting
transform_svtx_test_backface_cull:
srl $s6, $a0, 24 # shift down upper byte of texinfo word 1
andi $sp, $s6, 0x10 # select the 'skip backface culling' flag bit
bnez $sp, loc_800347CC # if set then skip backface culling
nop
transform_svtx_backface_cull:
cop2 0x1400006 # do GTE normal clipping
# GTE MAC0 = SX0*SY1+SX1*SY2+SX2*SY0-SX0*SY2-SX1*SY0-SX2*SY1
mfc2 $sp, $24 # move the results (MAC0) to $sp
nop
beqz $sp, transform_svtx_continue # skip poly if value is 0
xor $sp, cull_mask
bltz $sp, transform_svtx_continue # or if value ^ cull_mask is < 0
nop
transform_svtx_test_flat_shaded:
beqz $t2, transform_svtx_phong_shaded # skip to next block if is_flat_shaded bit is clear (shading is phong)
nop
transform_svtx_flat_shaded: # else poly is flat shaded
mtc2 $a0, $20 # set GTE RGB0 = texinfo rgb value
mtc2 $a0, $21 # set GTE RGB1 = texinfo rgb value
mtc2 $a0, $22 # set GTE RGB2 = texinfo rgb value
bgez $zero, transform_svtx_test_textured # skip past phong shaded case
nop
transform_svtx_phong_shaded:
lhu $s0, 4($s0) # get vert 1 normal y and z from third hword
# $s0 = vert1->normal_z << 16 | vert1->normal_y
lhu $s1, 4($s1) # get vert 2 normal y and z from third hword
lhu $s2, 4($s2) # get vert 3 normal y and z from third hword
andi $sp, $s3, 0xFF00 # select vert 1 normal x, multiplied by 256
sll $fp, $s0, 24 # shift up vert 1 normal y, multiplied by 256, to the upper hword
or $sp, $fp # or the values
mtc2 $sp, $0 # set GTE VXY0 = ((vert1->normal_y*256) << 16) | (vert1->normal_x*256)
andi $sp, $s0, 0xFF00 # select vert 1 normal z, multiplied by 256
mtc2 $sp, $1 # set GTE VZ0 = (vert1->normal_z*256)
andi $sp, $s4, 0xFF00 # repeat for vert 2...
sll $fp, $s1, 24
or $sp, $fp
mtc2 $sp, $2 # set GTE VXY1 = ((vert2->normal_y*256) << 16) | (vert2->normal_x*256)
andi $sp, $s1, 0xFF00
mtc2 $sp, $3 # set GTE VZ1 = (vert2->normal_z*256)
andi $sp, $s5, 0xFF00
sll $fp, $s2, 24
or $sp, $fp
mtc2 $sp, $4 # set GTE VXY2 = ((vert3->normal_y*256) << 16) | (vert3->normal_x*256)
andi $sp, $s2, 0xFF00
mtc2 $sp, $5 # set GTE VZ2 = (vert3->normal_z*256)
nop
cop2 0x118043F # use light matrix, color matrix, back color, RGB,
# and V, as a normal vector, to compute vertex colors
# (output is GTE RGB0, RGB1, RGB2)
transform_svtx_test_textured:
andi $sp, $s6, 0x80 # test bit 32 of texinfo word 1 (is_textured)
beqz $sp, loc_800349D8 # if not set then goto non-textured poly case
nop
transform_svtx_textured:
create_poly_gt3_4:
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
mfc2 $sp, $20 # get the result GTE RGB0
swc2 $21, 0x10(prim) # store result RGB1 as rgb value for vert 2 in the prim
swc2 $22, 0x1C(prim) # store result RGB2 as rgb value for vert 3 in the prim
and $sp, $t9 # select the lower 3 bytes (rgb value) of result GTE RGB0
lui $fp, 0x3400 # load code constant for POLY_GT3 primitives
or $sp, $fp # or with the result rgb value in the lower 3 bytes
and $fp, $s6, $t8 # select semi-transparency bits from texinfo word 1
beq $fp, $t8, create_poly_gt3_5 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
lw $s0, 8($t6) # get third word of texinfo
lui $ra, 0x200
or $sp, $ra # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_5:
sw $sp, 4(prim) # store primitive code and RGB value for vert 1
lw $sp, 4($t6) # get resolved tpage/tpageinfo pointer from texinfo (word 2 is a pointer to the tpageinfo)
srl $s2, $s0, 20 # shift down bits 21 and 22 of texinfo word 3 (color mode)
lw $s1, 0($sp) # load the resolved tpage/tpageinfo
srl $sp, $s0, 22 # shift down bits 23-32 of texinfo word 3 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s3, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
andi $s2, 3 # get bits 21 and 22 from texinfo word 3 (color mode)
sll $sp, $s2, 7 # shift to bits 8 and 9
andi $ra, $s1, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $ra # or with color mode bits 8 and 9
srl $ra, $s0, 18
andi $ra, 3 # get bits 19 and 20 from texinfo word 3 (segment), as bits 1 and 2
or $sp, $ra # or with color mode, tpage y index, and tpage x index
andi $ra, $s6, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $ra # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s0, 0x1F # get bits 1-5 from texinfo word 3 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s1, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s0, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 3 (offs_x) as bits 4-8
srlv $fp, $s2 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s2, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s3, 16 # shift down xy value for the second region point
addu $fp, $s2 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $s6, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s0, 0x1FC0 # get bits 7-13 from texinfo word 3 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s1, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s3, 0xFFFF # select xy value for first region point
addu $fp, $s2 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s2 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
transform_svtx_test_flag_1:
mfc2 $sp, $17 # get calculated vert 1 z from transformation
mfc2 $fp, $18 # get calculated vert 2 z from transformation
beqz $t7, transform_svtx_flag_false_1
mfc2 $ra, $19 # get calculated vert 3 z from transformation
transform_svtx_flag_true_1: # when flag is true, compute 3/2 of the sum of min and max
transform_svtx_test_z_max1_1: # vert z values instead of the sum of all vert z values, as the basis for the ot index
slt $s6, $sp, $fp
beqz $s6, transform_svtx_test_z_max3_1 # skip to test vert 3 z as a max if vert 1 z > vert 2 z
transform_svtx_z_max1_1:
move $s4, $sp # and set max vert z as vert 1 z
transform_svtx_z_max2_1:
move $s4, $fp # else set max vert z as vert 2 z
transform_svtx_test_z_max3_1:
slt $s6, $s4, $ra
beqz $s6, transform_svtx_test_z_min1_1 # skip to testing min vert z if vert 3 z <= max vert z
nop
transform_svtx_z_max3_1:
move $s4, $ra # else set max vert z as vert 3 z
transform_svtx_test_z_min1_1:
slt $s6, $fp, $sp
beqz $s6, transform_svtx_test_z_min3_1 # skip to test vert 3 z as a min if vert 1 z < vert 2 z
transform_svtx_z_min1_1:
move $sp, $sp # and set min vert z as vert 1 z
transform_svtx_z_min2_1:
move $sp, $fp # else set min vert z as vert 2 z
transform_svtx_test_z_min3_1:
slt $s6, $ra, $sp
beqz $s6, transform_svtx_z_mmax_avg_1 # skip to computing avg if vert 3 z >= min vert z
nop
transform_svtx_z_min3_1:
move $sp, $ra # else set min vert z as vert 3 z
transform_svtx_z_mmax_avg_1:
addu $sp, $s4 # $sp = min z + max z
srl $fp, $sp, 1 # $fp = (min z + max z) / 2
bgez $zero, add_poly_gt3_2
addu $sp, $fp # $sp = (min z + max z) * 3/2
# this should scale up correctly; if all vert zs are equal to value v
# then min z + max z = 2v, and 2v*3/2 = 3v = z1 + z2 + z3
transform_svtx_flag_false_1:
addu $sp, $fp
addu $sp, $ra # just use sum of transformed vert zs in the false case
add_poly_gt3_2:
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $t1, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
addu $t6, $a1, $sp # get pointer to ot entry at that offset
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $t9 # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
bgez $zero, transform_svtx_loop # loop
addiu prim, 0x28 # add sizeof(POLY_GT3) for next free location in primmem
create_poly_g3_2:
swc2 $12, 8(prim)
swc2 $13, 0x10(prim)
swc2 $14, 0x18(prim) # store transformed yx values for each vertex in a new POLY_G3 primitive
mfc2 $sp, $20 # get the result GTE RGB0
swc2 $21, 0xC(prim) # store result RGB1 as rgb value for vert 2 in the prim
swc2 $22, 0x14(prim) # store result RGB2 as rgb value for vert 3 in the prim
and $sp, $t9 # select the lower 3 bytes (rgb value) of result GTE RGB0
lui $ra, 0x3000 # load primitive code constant for POLY_G3
or $sp, $ra # or with the RGB values
sw $s3, 4(prim) # store primitive code and RGB values for vert 1
mfc2 $sp, $17 # get calculated vert 1 z from transformation
mfc2 $fp, $18 # get calculated vert 2 z from transformation
beqz $t7, transform_svtx_flag_false_2
mfc2 $ra, $19 # get calculated vert 3 z from transformation
transform_svtx_flag_true_2: # when flag is true, compute 3/2 of the sum of min and max
transform_svtx_test_z_max1_2: # vert z values instead of the sum of all vert z values, as the basis for the ot index
slt $s6, $sp, $fp
beqz $s6, transform_svtx_test_z_max3_2 # skip to test vert 3 z as a max if vert 1 z > vert 2 z
transform_svtx_z_max1_2:
move $s4, $sp # and set max vert z as vert 1 z
transform_svtx_z_max2_2:
move $s4, $fp # else set max vert z as vert 2 z
transform_svtx_test_z_max3_2:
slt $s6, $s4, $ra
beqz $s6, transform_svtx_test_z_min1_2 # skip to testing min vert z if vert 3 z <= max vert z
nop
transform_svtx_z_max3_2:
move $s4, $ra # else set max vert z as vert 3 z
transform_svtx_test_z_min1_2:
slt $s6, $fp, $sp
beqz $s6, transform_svtx_test_z_min3_2 # skip to test vert 3 z as a min if vert 1 z < vert 2 z
transform_svtx_z_min1_2:
move $sp, $sp # and set min vert z as vert 1 z
transform_svtx_z_min2_2:
move $sp, $fp # else set min vert z as vert 2 z
transform_svtx_test_z_min3_2:
slt $s6, $ra, $sp
beqz $s6, transform_svtx_z_mmax_avg_2 # skip to computing avg if vert 3 z >= min vert z
nop
transform_svtx_z_min3_2:
move $sp, $ra # else set min vert z as vert 3 z
transform_svtx_z_mmax_avg_2:
addu $sp, $s4 # $sp = min z + max z
srl $fp, $sp, 1 # $fp = (min z + max z) / 2
bgez $zero, transform_svtx_2
addu $sp, $fp # $sp = (min z + max z) * 3/2
# this should scale up correctly; if all vert zs are equal to value v
# then min z + max z = 2v, and 2v*3/2 = 3v = z1 + z2 + z3
transform_svtx_flag_false_2: # false case
addu $sp, $fp
addu $sp, $ra # just use sum of transformed vert zs
transform_svtx_2:
srl $sp, 3 # compute sum over 32 (average over 10.666), multiplied by sizeof(void*); this is an index
sub $sp, $t1, $sp # get distance from far value offset
bgez $sp,
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
add_poly_g3_lim_ot_offset_2:
move $sp, $zero
add_poly_g3_2:
addu $t6, $a1, $sp # get pointer to ot entry at that offset
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $t9 # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
or $sp, $gp # or len for POLY_G3 with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_svtx_continue:
addiu $t5, -1 # decrement poly count
bnez $t5, transform_svtx_loop # continue looping while poly count > 0
addiu $a2, 8 # also increment to next poly ($a2 += sizeof(tgeo_polygon))
lw $sp, 0x1F800034 # restore the original $sp
nop
lw $at, arg_18($sp) # get argument which is a pointer to prims_tail
nop
sw prim, 0($at) # store the new prims_tail
sload
jr $ra
nop
#
# translate, rotate, and perspective transform an array of tgeo polys for a given
# cvtx frame, and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# prims created by this routine are gouraud shaded rather than phong shaded (like
# the svtx routine)
#
# svtx vertices (whose transform routine does phong shading) include x, y, and z
# bytes for vertex normals;
# for cvtx vertices, these bytes are replaced by r, g, and b values for gouraud
# shading. this rgb value is, also, interpolated according to the following:
#
# texinfo word 1 = tssnxxxx aaaaaaaa bbbbbbbb cccccccc
# a bits (signed) = t1
# b bits (signed) = t2
# c bits (signed) = t3
# ri = (t1 > 0 ? ((127-abs(t1))*0 + ( abs(t1)* r)) * 32:
# : ((128-abs(t1))*255 + ((abs(t1)-1)* r)) * 32) >> shamt;
# gi = (t2 > 0 ? ((127-abs(t2))*0 + ( abs(t2)* g)) * 32:
# : ((128-abs(t2))*255 + ((abs(t2)-1)* g)) * 32) >> shamt;
# bi = (t3 > 0 ? ((127-abs(t3))*0 + ( abs(t3)* b)) * 32:
# : ((128-abs(t3))*255 + ((abs(t3)-1)* b)) * 32) >> shamt;
#
# where (r,g,b) is the vertex rgb value,
# (t1,t2,t3) are t values from the poly texinfo
# shamt is value of the argument with that name
# (ri,gi,bi) is the interpolated vertex rgb value,
#
# a0 = cvtx_frame = (in) cvtx vertex animation frame item
# a1 = ot = (in) ot
# a2 = polys = (in) array of tgeo polygons
# a3 = header = (in) tgeo header item
# 0x10($sp) = cull_mask = (in) bitmask xor'ed with projected poly normal value which rejects when < 0
# 0x14($sp) = far = (in) far value
# 0x18($sp) = prims_tail = (inout) pointer to current tail pointer of primitive buffer
# 0x1C($sp) = regions = (in) table of precomputed uv coordinate rects/'regions'
# 0x20($sp) = shamt = (in) see above
#
RGteTransformCvtx:
arg_0 = 0
arg_10 = 0x10
arg_14 = 0x14
arg_18 = 0x18
arg_1C = 0x1C
arg_20 = 0x20
poly = $a2
prim = $a3
verts = $t3
regions = $s7
poly_idx = $t5
ssave
lw cull_mask, arg_10($sp) # get mask value for backface culling
lw $t1, arg_14($sp) # get far value argument
lw $t2, arg_18($sp) # get argument value which is a pointer to prims_tail
lw regions, arg_1C($sp)
lw $fp, arg_20($sp) # get shamt argument
# --- RGteTransformSvtx diff --- #
# create a mask that can be used to select the lower [8-shamt] bits of each of the lower 3 bytes of a word
# (each of the byte values in a word can be shifted right by shamt, simultaneously, by shifting the whole
# word right by shamt. this has the consequence that the lower shamt bits of each byte (except for the
# first) 'overflow' into the upper shamt bits of the bytes to the right. said mask can be used to
# deselect the overflowing bits after such a shift.)
li $at, 0x1F8000E0
sw $fp, 0xC($at) # preserve shamt argument $fp in scratch
li $ra, 0xFF
srlv $fp, $ra, $fp # $fp = 0xFF >> shamt
sll $ra, $fp, 8
or $fp, $ra, $fp # $fp = ((0xFF >> shamt) << 8) | (0xFF >> shamt)
sll $ra, 8
or $fp, $ra, $fp # $fp = ((0xFF >> shamt) << 16) | ((0xFF >> shamt) << 8) | (0xFF >> shamt)
sw $fp, 0x10($at) # preserve mask $fp in scratch
cfc2 $sp, $21
cfc2 $fp, $22
cfc2 $ra, $23 # $sp,$fp,$ra = current GTE far color
sw $sp, 0($at)
sw $fp, 4($at)
sw $ra, 8($at) # save current GTE far color in scratch
# ------------------------------- #
sll $t1, 2 # multiply far value as an index by sizeof(void*) to convert to an ot offset
li $t9, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t8, 0x60 # '`' # load mask for selecting semi-trans mode
lui $gp, 0x600 # load len for POLY_G3
lw $at, 8($a0) # $at = frame->x
lw $v0, 0xC($a0) # $v0 = frame->y
lw $v1, 0x10($a0) # $v1 = frame->z
addiu $at, -128 # $at = frame->x - 128
addiu $v0, -128 # $v0 = frame->y - 128
addiu $v1, -128 # $v1 = frame->z - 128
addiu verts, $a0, 0x38 # verts = &frame->vertices
addiu texinfos, $a3, 0x14 # texinfos = &header->texinfos
lw i_poly, 0($a3) # i_poly = header->poly_count
# note: i_poly is a reverse/'count-remaining' type iterator,
prim = $a3 # but the 'poly' pointer itself is a forward iterator
lw prim, 0($t2) # get pointer to a new prim
transform_cvtx_loop:
# --- RGteTransformSvtx diff --- #
move $t7, 0 # reset ot offset adjust
# ------------------------------ #
lw $sp, 0(poly) # get cur poly word 1
lw $fp, 4(poly) # get cur poly word 2
nop
andi $ra, $sp, 0xFFFF # get offset of vert 1 from lower hword of cur poly word 1
addu $s0, verts, $ra # get pointer to vert 1
srl $ra, $sp, 16 # get offset of vert 2 from upper hword of cur poly word 1
addu $s1, $t3, $ra # get pointer to vert 2
andi $ra, $fp, 0xFFFF # get offset of vert 3 from lower hword of cur poly word 2
addu $s2, $t3, $ra # get pointer to vert 3
srl $ra, $fp, 16 # get flag and texinfo offset from upper hword of cur poly word 2
andi $t2, $ra, 0x8000 # select is_flat_shaded bit
andi $ra, 0x7FFF # select texinfo offset
sll $ra, 2 # multiply texinfo offset by 4, as it is stored / 4
addu $t6, texinfos, $ra # get a pointer to the texinfo
lhu $s6, 0($s0) # get vert 1 xy from first hword
# $s6 = (vert1->y << 8) | vert1->x
lhu $s3, 2($s0) # get vert 1 z and normal x from second hword
# $s3 = (vert1->normal_x << 8) | vert1->z
srl $fp, $s6, 8 # $fp = vert1->y
addu $fp, $v0 # $fp = vert1->y + (frame->y - 128)
sll $fp, 18 # $fp = ((vert1->y + (frame->y - 128))*4) << 16
andi $sp, $s6, 0xFF # $fp = vert1->x
addu $sp, $at # $fp = vert1->x + (frame->x - 128)
sll $sp, 2 # $fp = (vert1->x + (frame->x - 128))*4
andi $sp, 0xFFFF
or $fp, $sp # $fp = (((vert1->y + (frame->y - 128))*4) << 16) | ((vert1->x + (frame->x - 128))*4)
mtc2 $fp, $0 # set GTE VXY0 to $fp
andi $sp, $s3, 0xFF # $sp = vert1->z
addu $sp, $v1 # $sp = vert1->z + (frame->z - 128)
sll $sp, 2 # $sp = (vert1->z + (frame->z - 128))*4
mtc2 $sp, $1 # set GTE VZ0 to $sp
# GTE V0 = [(vert1->x + (frame->x - 128))*4]
# [(vert1->y + (frame->y - 128))*4]
# [(vert1->z + (frame->z - 128))*4]
lhu $s6, 0($s1) # repeat for vert 2...
lhu $s4, 2($s1)
srl $fp, $s6, 8
addu $fp, $v0
sll $fp, 18
andi $sp, $s6, 0xFF
addu $sp, $at
sll $sp, 2
andi $sp, 0xFFFF
or $fp, $sp
mtc2 $fp, $2 # set GTE VXY1 to $fp
andi $sp, $s4, 0xFF
addu $sp, $v1
sll $sp, 2
mtc2 $sp, $3 # set GTE VZ1 to $sp
# GTE V1 = [(vert2->x + (frame->x - 128))*4]
# [(vert2->y + (frame->y - 128))*4]
# [(vert2->z + (frame->z - 128))*4]
lhu $s6, 0($s2) # repeat for vert 3...
lhu $s5, 2($s2)
srl $fp, $s6, 8
addu $fp, $v0
sll $fp, 18
andi $sp, $s6, 0xFF
addu $sp, $at
sll $sp, 2
andi $sp, 0xFFFF
or $fp, $sp
mtc2 $fp, $4 # set GTE VXY2 to $fp
andi $sp, $s5, 0xFF
addu $sp, $v1
sll $sp, 2
mtc2 $sp, $5 # set GTE VZ2 to $sp
# GTE V2 = [(vert3->x + (frame->x - 128))*4]
# [(vert3->y + (frame->y - 128))*4]
# [(vert3->z + (frame->z - 128))*4]
lw $a0, 0($t6) # get texinfo word 1
nop
cop2 0x280030 # translate, rotate, and perspective transform verts
cfc2 $sp, $31 # get GTE flag
nop # (diff: here the RGB value is set in RGteSvtxTransform)
bltz $sp, transform_cvtx_continue # skip this poly if transformation resulted in limiting
transform_cvtx_test_backface_cull_mode:
srl $s6, $a0, 24 # shift down upper byte of texinfo word 1
andi $sp, $s6, 0x10 # select the 'backface culling mode' flag bit
bnez $sp, transform_cvtx_skip_backface_cull_mode_1 # if set then goto do backface culling mode 1
nop
transform_cvtx_backface_cull_mode_0: # else do backface culling mode 0
cop2 0x1400006 # do GTE normal clipping
# GTE MAC0 = SX0*SY1+SX1*SY2+SX2*SY0-SX0*SY2-SX1*SY0-SX2*SY1
mfc2 $sp, $24 # move the results (MAC0) to $sp
nop
beqz $sp, transform_cvtx_continue # skip poly if value is 0
xor $sp, cull_mask
bltz $sp, transform_cvtx_continue # or if value ^ cull_mask is < 0
nop
# no flat-shaded test
transform_cvtx:
lhu $s0, 4($s0) # get vert 1 g and b from third hword
# $s0 = vert1->normal_z << 16 | vert1->normal_y
lhu $s1, 4($s1) # get vert 2 g and b from third hword
lhu $s2, 4($s2) # get vert 3 g and b from third hword
# --- RGteTransformSvtx diff --- #
transform_cvtx_test_t1_lt128: # map and interpolate with vert t1 value: 0 to 127 => 127 to 0, 128 to 255 => 0 to 127
andi $sp, $a0, 0xFF # get t1 value from texinfo word 1
sltiu $fp, $sp, 128
beqz $fp, transform_cvtx_unk_gteq128
nop
transform_cvtx_t1_lt128:
ctc2 $zero, $21
ctc2 $zero, $22
ctc2 $zero, $23 # set GTE far color to (0,0,0)
li $fp, 127
bgez $zero, loc_80034D50
subu $sp, $fp, $sp # $sp = 127 - $sp
transform_cvtx_t1_gteq128:
li $fp, 0xFF0
ctc2 $fp, $21
ctc2 $fp, $22
ctc2 $fp, $23 # set GTE far color to (0xFF0,0xFF0,0xFF0)
addiu $sp, -128 # $sp = $sp - 128 (i.e. $sp = $sp + 128 for $sp signed and < 0)
transform_cvtx_t1:
sll $sp, 5 # multiply by 2, and shift left by 4 (so that 127 => 0xFE0 approx= 0xFF0)
mtc2 $sp, $8 # set GTE IR0 = (2*(abs(127-t1)-abs(t1/128))) << 4
srl $s3, 8 # shift down vert 1 r
srl $s4, 8 # shift down vert 2 r
srl $s5, 8 # shift down vert 3 r
sll $fp, $s4, 8
or $sp, $s3, $fp
sll $fp, $s5, 16
or $sp, $fp # set $sp = (v3.r << 16) | (v2.r << 8) | (v1.r)
mtc2 $sp, $6 # set GTE RGB = $sp
nop
nop
cop2 0x780010 # interpolate between RGB (r values) and the far color (upper/lower limits), using t=IR0
nop
nop
mfc2 $sp, $22 # get the interpolated r values
nop
nop
andi $s3, $sp, 0xFF # get component 1 of the interpolated value
srl $s4, $sp, 8
andi $s4, 0xFF # get component 2 of the interpolated value
srl $s5, $sp, 16
andi $s5, 0xFF # get component 3 of the interpolated value
srl $sp, $a0, 8 # shift down the t2 value from texinfo word 1
transform_cvtx_test_t2_lt128: # map and interpolate with vert t2 value: 0 to 127 => 127 to 0, 128 to 255 => 0 to 127
andi $sp, 0xFF # select t2 value from texinfo word 1
sltiu $fp, $sp, 128
beqz $fp, transform_cvtx_t2_gteq128 # go to >= to 128 case if >= 128
nop
transform_cvtx_t2_lt128: # else
ctc2 $zero, $21
ctc2 $zero, $22
ctc2 $zero, $23 # set GTE far color to (0,0,0)
li $fp, 127
bgez $zero, transform_cvtx_t2 # skip over >= 128 case
subu $sp, $fp, $sp # $sp = 127 - $sp
transform_cvtx_t2_gteq128:
li $fp, 0xFF0
ctc2 $fp, $21
ctc2 $fp, $22
ctc2 $fp, $23 # set GTE far color to (0xFF0,0xFF0,0xFF0)
addiu $sp, -128 # $sp = $sp - 128
transform_cvtx_t2:
sll $sp, 5 # multiply $sp by 2, and shift left by 4 (so that 128 => 0xFF0)
mtc2 $sp, $8 # set GTE IR0 = (2*(abs(127-t2)-abs(t2/128))) << 4
andi $sp, $s0, 0xFF
andi $fp, $s1, 0xFF
sll $fp, 8
andi $ra, $s2, 0xFF
sll $ra, 16
or $sp, $fp
or $sp, $ra # set $sp = (v3.g << 16) | (v2.g << 8) | (v1.g)
mtc2 $sp, $6 # set GTE RGB = $sp
nop
nop
cop2 0x780010 # interpolate between RGB (g values) and the far color (upper/lower limits), using t=IR0
nop
nop
srl $sp, $s0, 8 # shift down v1.b value
andi $fp, $s1, 0xFF00 # select v2.b shifted left 8
andi $ra, $s2, 0xFF00 # select v3.b shifted left 8
sll $ra, 8 # shift the selected v3.b value left by an additional 8
or $sp, $fp
or $sp, $ra # or the values to get $sp = (v3.b << 16) | (v2.b << 8) | (v1.b)
mtc2 $sp, $6 # set GTE RGB = $sp
mfc2 $s0, $22 # get the interpolated g values
nop
nop
andi $s1, $s0, 0xFF00 # select result g2 value shifted left 8 (so that it is in upper byte of lower hword)
srl $s2, $s0, 8
andi $s2, 0xFF00 # select result g3 value shifted left 8 (so that it is in upper byte of lower hword)
sll $s0, 8
andi $s0, 0xFF00 # select result g1 value shifted left 8 (so that it is in upper byte of lower hword)
or $s3, $s0 # or result g1 value in upper byte with result r1 value in lower byte
or $s4, $s1 # or result g2 value in upper byte with result r2 value in lower byte
or $s5, $s2 # or result g3 value in upper byte with result r3 value in lower byte
transform_cvtx_test_t3_lt128: # map and interpolate with vert t2 value: 0 to 127 => 127 to 0, 128 to 255 => 0 to 127
srl $sp, $a0, 16 # shift down t3 value from texinfo word 1
andi $sp, 0xFF # select t3 value from texinfo word 1
sltiu $fp, $sp, 128
beqz $fp, transform_cvtx_t3_gteq128 # go to >= to 128 case if >= 128
nop
transform_cvtx_t3_lt128: # else
ctc2 $zero, $21
ctc2 $zero, $22
ctc2 $zero, $23 # set GTE far color to (0,0,0)
li $fp, 127
bgez $zero, transform_cvtx_t3 # skip over >= 128 case
subu $sp, $fp, $sp # $sp = 127 - $sp
transform_cvtx_t3_gteq128:
li $fp, 0xFF0
ctc2 $fp, $21
ctc2 $fp, $22
ctc2 $fp, $23 # set GTE far color to (0xFF0,0xFF0,0xFF0)
addiu $sp, -128 # $sp = $sp - 128
transform_cvtx_t3:
sll $sp, 5 # multiply $sp by 2, and shift left by 4 (so that 128 => 0xFF0)
mtc2 $sp, $8 # set GTE IR0 = (2*(abs(127-t3)-abs(t3/128))) << 4
nop
nop
cop2 0x780010 # interpolate between RGB (b values) and the far color (upper/lower limits), using t=IR0
nop
nop
mfc2 $sp, $22 # get the interpolated b values
nop
nop
andi $s0, $sp, 0xFF # select result b1 value
sll $s0, 16 # shift it left 16 to lower byte of upper hword
andi $s1, $sp, 0xFF00 # select result b2 value, shifted left 8
sll $s1, 8 # shift it left 8 to lower byte of upper hword
lui $fp, 0xFF # load mask for selecting b3 value
and $s2, $sp, $fp # select result b3 value, shifted left 16
or $s3, $s0 # or result b1 value in lower byte of upper hword with result r1 and g1 values in lower hword
or $s4, $s1 # or result b2 value in lower byte of upper hword with result r2 and g2 values in lower hword
or $s5, $s2 # or result b3 value in lower byte of upper hword with result r3 and g3 values in lower hword
# ------------------------------ #
transform_cvtx_test_textured:
andi $sp, $s6, 0x80 # test bit 32 of texinfo word 1 (is_textured)
beqz $sp, transform_cvtx_nontextured # if not set then goto non-textured poly case
nop
transform_cvtx_textured:
create_poly_gt3_8:
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
# --- RGteTransformSvtx diff --- #
create_poly_gt3_test_shamt:
li $sp, 0x1F8000EC # get pointer to preserved values in scratch
lw $fp, 0($sp) # restore shamt argument from scratch
nop
beqz $fp, create_poly_gt3_9 # skip nonzero case if shamt is zero
create_poly_gt3_shamt_neq0:
srlv $s3, $fp # shift result b1 | g1 | r1 value right by shamt
srlv $s4, $fp # shift result b2 | g2 | r2 value right by shamt
lw $sp, 4($sp) # restore mask argument from scratch
srlv $s5, $fp # shift result b3 | g3 | r3 value right by shamt
and $s3, $sp
and $s4, $sp
and $s5, $sp # apply mask to each shifted result
# ------------------------------ #
create_poly_gt3_9:
lui $fp, 0x3400 # load code constant for POLY_GT3 primitives
or $s3, $fp # or with the result rgb value in the lower 3 bytes
and $fp, $s6, $t8 # select semi-transparency bits from texinfo word 1
beq $fp, $t8, create_poly_gt3_10 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
lw $s0, 8($t6) # get third word of texinfo
lui $sp, 0x200
or $s3, $sp # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_10:
sw $s3, 4(prim) # store primitive code and RGB value for vert 1
sw $s4, 0x10(prim) # store RGB value for vert 2
sw $s5, 0x1C(prim) # store RGB value for vert 3
lw $sp, 4($t6) # get resolved tpage/tpageinfo pointer from texinfo (word 2 is a pointer to the tpageinfo)
srl $s2, $s0, 20 # shift down bits 21 and 22 of texinfo word 3 (color mode)
lw $s1, 0($sp) # load the resolved tpage/tpageinfo
srl $sp, $s0, 22 # shift down bits 23-32 of texinfo word 3 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s3, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
andi $s2, 3 # get bits 21 and 22 from texinfo word 3 (color mode)
sll $sp, $s2, 7 # shift to bits 8 and 9
andi $ra, $s1, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $ra # or with color mode bits 8 and 9
srl $ra, $s0, 18
andi $ra, 3 # get bits 19 and 20 from texinfo word 3 (segment), as bits 1 and 2
or $sp, $ra # or with color mode, tpage y index, and tpage x index
andi $ra, $s6, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $ra # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s0, 0x1F # get bits 1-5 from texinfo word 3 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s1, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s0, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 3 (offs_x) as bits 4-8
srlv $fp, $s2 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s2, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s3, 16 # shift down xy value for the second region point
addu $fp, $s2 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $s6, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s0, 0x1FC0 # get bits 7-13 from texinfo word 3 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s1, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s3, 0xFFFF # select xy value for first region point
addu $fp, $s2 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s2 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
mfc2 $sp, $17 # get calculated vert 1 z from transformation
mfc2 $fp, $18 # get calculated vert 2 z from transformation
mfc2 $ra, $19 # get calculated vert 3 z from transformation
addu $sp, $fp
addu $sp, $ra # compute sum of transformed vert zs
add_poly_gt3_8:
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
add $sp, $t7 # add value of ot offset adjust (argument)
sub $sp, $t1, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
addu $t6, $a1, $sp # get pointer to ot entry at that offset
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $t9 # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
bgez $zero, transform_cvtx_loop # loop
addiu prim, 0x28 # add sizeof(POLY_GT3) for next free location in primmem
create_poly_g3_8:
swc2 $12, 8(prim)
swc2 $13, 0x10(prim)
swc2 $14, 0x18(prim) # store transformed yx values for each vertex in a new POLY_G3 primitive
# --- RGteTransformSvtx diff --- #
create_poly_g3_test_shamt:
li $sp, 0x1F8000EC # get pointer to preserved values in scratch
lw $fp, 0($sp) # restore shamt argument from scratch
nop
beqz $fp, create_poly_g3_9 # skip nonzero case if shamt is zero
create_poly_g3_shamt_neq0:
srlv $s3, $fp # shift result r3 | r2 | r1 value right by shamt
srlv $s4, $fp # shift result g3 | g2 | g1 value right by shamt
lw $sp, 4($sp) # restore mask argument from scratch
srlv $s5, $fp # shift result b3 | b2 | b1 value right by shamt
and $s3, $sp
and $s4, $sp
and $s5, $sp # apply mask to each shifted result
# ------------------------------ #
create_poly_g3_9:
sw $s3, 4(prim) # store primitive code and RGB values for vert 1
sw $s4, 0xC(prim) # store result RGB1 as rgb value for vert 2 in the prim
sw $s5, 0x14(prim) # store result RGB2 as rgb value for vert 3 in the prim
and $sp, $t9 # select the lower 3 bytes (rgb value) of result GTE RGB0
lui $ra, 0x3000 # load primitive code constant for POLY_G3
or $sp, $ra # or with the RGB values
mfc2 $sp, $17 # get calculated vert 1 z from transformation
mfc2 $fp, $18 # get calculated vert 2 z from transformation
mfc2 $ra, $19 # get calculated vert 3 z from transformation
addu $sp, $fp
addu $sp, $ra # compute sum of transformed vert zs
add_poly_g3_8:
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
# --- RGteTransformSvtx diff --- #
add $sp, $t7 # add value of ot offset adjust (set for bf culling mode 1)
# ------------------------------ #
sub $sp, $t1, $sp # get distance from far value offset
bgez $sp, add_poly_g3_9
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
add_poly_g3_lim_ot_offset_4:
move $sp, $zero
add_poly_g3_9:
addu $t6, $a1, $sp # get pointer to ot entry at that offset
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $t9 # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
or $sp, $gp # or len for POLY_G3 with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_cvtx_continue:
addiu $t5, -1 # decrement poly count
bnez $t5, transform_cvtx_loop # continue looping while poly count > 0
addiu $a2, 8 # also increment to next poly ($a2 += sizeof(tgeo_polygon))
# --- RGteTransformSvtx diff --- #
li $at, 0x1F8000E0
lw $sp, 0($at)
lw $fp, 4($at)
lw $ra, 8($at) # get the previous GTE far color from scratch
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # restore the previous GTE far color
# ------------------------------ #
lw $sp, 0x1F800034 # restore the original $sp
nop
lw $at, arg_18($sp) # get argument which is a pointer to prims_tail
nop
sw prim, 0($at) # store the new prims_tail
sload
jr $ra
nop
# --- RGteTransformSvtx diff --- #
transform_cvtx_backface_cull_mode_1: # do backface culling mode 1
cop2 0x1400006 # do GTE normal clipping
# GTE MAC0 = SX0*SY1+SX1*SY2+SX2*SY0-SX0*SY2-SX1*SY0-SX2*SY1
mfc2 $sp, $24 # move the results (MAC0) to $sp
nop
beqz $sp, transform_cvtx_bc1_shift_ot_offset # goto change the ot offset if value is 0
xor $sp, cull_mask
bltz $sp, transform_cvtx_bc1_shift_ot_offset # or if value ^ cull_mask is < 0
nop
bgez $zero, cvtx_transform # else go to transform
nop
transform_cvtx_bc1_shift_ot_offset:
li $sp, 0xFFFFFFDF
and $s6, $sp # clear semi-transparency mode bit 1
bgez $zero, transform_cvtx # goto transform
li $t7, 0x30 # set offset to move (eventual) prim forward in the ot, by 12 entries
nop
# ------------------------------ #
#
# project a 3 dimensional local bound to 2 dimensions (screen coordinates)
# and return a 2d bound with the x and y extents
#
# a0 (in) = local bound
# a1 (in) = col (centering offset for collision)
# a2 (in) = trans
# a3 (in) = cam_trans
# scratch[0x48] (out) = xy extents p1.x
# scratch[0x4C] (out) = xy extents p1.y
# scratch[0x50] (out) = xy extents p2.x
# scratch[0x54] (out) = xy extents p2.y
#
RGteProjectBound:
sw $ra, 0x1F800000 # save return address in scratch
lw $t2, 0($a2)
lw $t3, 4($a2)
lw $t4, 8($a2) # $t2-$t4 = trans
lw $t5, 0($a1)
lw $t6, 4($a1)
lw $t7, 8($a1) # $t5-$t7 = col
lw $at, 0($a0)
lw $v0, 4($a0)
lw $v1, 8($a0) # $at,$v0,$v1 = bound.p1
lw $a2, 0xC($a0)
lw $a1, 0x10($a0)
lw $a0, 0x14($a0) # $a2-$a0 = bound.p2
lw $t1, 0($a3)
lw $t0, 4($a3)
lw $a3, 8($a3) # $t1,$t0,$a3 = cam_trans
addu $at, $t2
addu $v0, $t3
addu $v1, $t4 # $at,$v0,$v1 = bound.p1 + trans
addu $a2, $t2
addu $a1, $t3
addu $a0, $t4 # $a2-$a0 = bound.p2 + trans
subu $t5, $t1
subu $t6, $t0
subu $t7, $a3 # $t5-$t7 = col - cam_trans
addu $t2, $at, $t5
addu $t3, $v0, $t6
addu $t4, $v1, $t7 # $t2-$t4 = bound.p1 + trans + (col - cam_trans)
addu $t5, $a2, $t5
addu $t6, $a1, $t6
addu $t7, $a0, $t7 # $t5-$t7 = bound.p2 + trans + (col - cam_trans)
sra $t2, 8
sra $t3, 8
sra $t4, 8 # $t2-$t4 = (bound.p1 + trans + (col - cam_trans)) >> 8
sra $t5, 8
sra $t6, 8
sra $t7, 8 # $t5-$t7 = (bound.p2 + trans + (col - cam_trans)) >> 8
# b.p1 = $t2-$t4, b.p2 = $t5-$t7
andi $t2, 0xFFFF # $t2 = (b.p1.x&0xFFFF)
andi $t5, 0xFFFF # $t5 = (b.p2.x&0xFFFF)
sll $t3, 16 # $t3 = (b.p1.y<<16)
sll $t6, 16 # $t6 = (b.p2.y<<16)
andi $t4, 0xFFFF # $t4 = (b.p1.z&0xFFFF)
andi $t7, 0xFFFF # $t7 = (b.p2.z&0xFFFF)
or $at, $t2, $t3 # $at = (b.p1.y<<16) | (b.p1.x&0xFFFF)
or $v0, $t2, $t6 # $v0 = (b.p2.y<<16) | (b.p1.x&0xFFFF)
mtc2 $at, $0 # VX0 = b.p1.x, VY0 = b.p1.y
mtc2 $at, $2 # VX1 = b.p1.x, VY1 = b.p1.y
mtc2 $v0, $4 # VX2 = b.p1.x, VY2 = b.p2.y
mtc2 $t4, $1 # VZ0 = b.p1.z
mtc2 $t7, $3 # VZ1 = b.p2.z
mtc2 $t4, $5 # VZ2 = b.p1.z
nop # or VX0 = b.p1.x, VY0 = b.p1.y, VZ0 = b.p1.z (upper left front)
nop # VX1 = b.p1.x, VY1 = b.p1.y, VZ1 = b.p2.z (upper left back)
cop2 0x280030 # trans, rot, and perspective transform verts
nop # VX2 = b.p1.x, VY2 = b.p2.y, VZ2 = b.p1.z (lower left front)
mfc2 $at, $12
mfc2 $v0, $13
mfc2 $v1, $14 # $at,$v0,$v1 = transformed vert xys
lui $a1, 0x8000 # initial x_max = MIN_INT
lui $a3, 0x8000 # initial y_max = MIN_INT
nor $a0, $a1, $zero # initial x_min = MAX_INT
nor $a2, $a3, $zero # initial x_max = MAX_INT
jal sub_80035370 # find x and y extents of the transformed verts
nop # (the results will be in $a0-$a3=x_min,x_max,y_min,y_max)
or $at, $t2, $t6 # $at = (b.p2.y<<16) | (b.p1.x&0xFFFF)
or $v0, $t5, $t3 # $v0 = (b.p1.y<<16) | (b.p2.x&0xFFFF)
mtc2 $at, $0 # VX0 = b.p1.x, VY0 = b.p2.y
mtc2 $v0, $2 # VX1 = b.p2.x, VY1 = b.p1.y
mtc2 $v0, $4 # VX2 = b.p2.x, VY2 = b.p1.y
mtc2 $t7, $1 # VZ0 = b.p2.z
mtc2 $t4, $3 # VZ1 = b.p1.z
mtc2 $t7, $5 # VZ2 = b.p2.z
nop # or VX0 = b.p1.x, VY0 = b.p2.y, VZ0 = b.p2.z (lower left back)
nop # VX1 = b.p2.x, VY1 = b.p1.y, VZ1 = b.p1.z (upper right front)
cop2 0x280030 # trans, rot, and perspective transform verts
nop # VX2 = b.p2.x, VY2 = b.p1.y, VZ2 = b.p2.z (lower right back)
mfc2 $at, $12
mfc2 $v0, $13
mfc2 $v1, $14 # $at,$v0,$v1 = transformed vert xys
jal sub_80035370 # find x and y extents of the 6 verts computed thus far
nop # using extents found for the first 3 ($a0-$a3)
# and the next 3 transformed verts ($at,$v0,$v1)
or $at, $t5, $t6 # $at = (b.p2.y<<16) | (b.p2.x&0xFFFF)
mtc2 $at, $2 # VX0 = b.p2.x, VY0 = b.p2.y
mtc2 $at, $4 # VX1 = b.p2.x, VY0 = b.p2.y
mtc2 $t4, $3 # VZ0 = b.p1.z
mtc2 $t7, $5 # VZ1 = b.p2.z
nop # or VX0 = b.p2.x, VY0 = b.p2.y, VZ0 = b.p1.z (lower right front)
nop # VX1 = b.p2.x, VY1 = b.p2.y, VZ1 = b.p2.z (lower right back)
cop2 0x280030 # trans, rot, and perspective transform verts
nop # (V0 and V1 are the remaining 2 corners of the bound/rect)
mfc2 $v0, $13 # $v0,$v1 = transformed vert xys
mfc2 $v1, $14
jal sub_800353B0 # find xy extents of the 8 verts (bound corners) computed
nop # using extents found for the first 6
# and the last 2 transformed verts ($v0,$v1)
li $at, 0x1F800048 # get a pointer to scratch[0x48] for storing the extents
sw $a0, 0($at)
sw $a2, 4($at)
sw $a1, 8($at)
sw $a3, 0xC($at) # store the extents in scratch memory
lw $ra, 0x1F800000 # restore return address from scratch
move $v0, $zero # return 0
jr $ra
nop
#
# find the x and y extents of set of 3 vertices/points
#
# at (in) = v1.y(16)|v1.x(16)
# v0 (in) = v2.y(16)|v2.x(16)
# v1 (in) = v3.y(16)|v3.x(16)
# a0 (out) = x_min
# a1 (out) = x_max
# a2 (out) = y_min
# a3 (out) = y_max
#
sub_80035370:
sll $t1, $at, 16
sra $t1, 16 # extract v1.x; shift up the sign bit
slt $t0, $t1, $a0 # minimize with respect to a0
beqz $t0, loc_80035370_max_x1 # ...
slt $t0, $a1, $t1 # start maximizing with respect to a1
sub_80035370_minl_x1:
move $a0, $t1 # if (v1.x < x_min) { x_min = v1.x; }
sub_80035370_max_x1:
beqz $t0, sub_80035370_min_y1
sra $t0, $at, 16 # extract v1.y
sub_80035370_maxl_x1:
move $a1, $t1 # if (v1.x > x_max) { x_max = v1.x; }
sub_80035370_min_y1:
slt $t1, $t0, $a2
beqz $t1, sub_80035370_max_y1
slt $t1, $a3, $t0
sub_80035370_minl_y1:
move $a2, $t0 # if (v1.y < y_min) { y_min = v1.y; }
sub_80035370_max_y1:
beqz $t1, sub_800353B0
nop
move $a3, $t0 # if (v1.y > y_max) { y_max = v1.y; }
# continues into the following function for the remaining 2 points...
#
# find the x and y extents of a set of 2 vertices/points (*v2 and v3)
#
# v0 (in) = v2.y(16)|v2.x(16)
# v1 (in) = v3.y(16)|v3.x(16)
# a0 (out) = x_min
# a1 (out) = x_max
# a2 (out) = y_min
#
# a3 (out) = y_max
#
sub_800353B0:
sll $t1, $v0, 16
sra $t1, 16 # extract v2.x; shift up the sign bit
slt $t0, $t1, $a0 # minimize with respect to a0
beqz $t0, sub_800353B0_max_x2 # ...
slt $t0, $a1, $t1 # start maximizing with respect to a1
sub_800353B0_minl_x2:
move $a0, $t1 # if (v2.x < x_min) { x_min = v2.x; }
sub_800353B0_max_x2:
beqz $t0, sub_800353B0_min_y2
sra $t0, $v0, 16 # extract v2.y
sub_800353B0_maxl_x2:
move $a1, $t1 # if (v2.x > x_max) { x_max = v2.x; }
sub_800353B0_min_y2:
slt $t1, $t0, $a2
beqz $t1, sub_800353B0_max_y2
slt $t1, $a3, $t0
sub_800353B0_minl_y2:
move $a2, $t0 # if (v2.y < y_min) { y_min = v2.y; }
sub_800353B0_max_y2:
beqz $t1, sub_800353B0_min_x3
nop
move $a3, $t0 # if (v2.y > y_max) { y_max = v2.y; }
sub_800353B0_min_x3:
sll $t1, $v1, 16
sra $t1, 16 # extract v3.x; shift up the sign bit
slt $t0, $t1, $a0 # minimize with respect to a0
beqz $t0, sub_800353B0_max_x3 # ...
slt $t0, $a1, $t1 # start maximizing with respect to a1
sub_800353B0_minl_x3:
move $a0, $t1 # if (v3.x < x_min) { x_min = v3.x; }
sub_800353B0_max_x3:
beqz $t0, sub_800353B0_min_y3
sra $t0, $v1, 16 # extract v3.y
sub_800353B0_maxl_x3:
move $a1, $t1 # if (v3.x > x_max) { x_max = v3.x; }
sub_800353B0_min_y3:
slt $t1, $t0, $a2
beqz $t1, sub_800353B0_max_y3
slt $t1, $a3, $t0
sub_800353B0_minl_y3:
move $a2, $t0 # if (v3.y < y_min) { y_min = v3.y; }
sub_800353B0_max_y3:
beqz $t1, sub_800353B0_ret
nop
move $a3, $t0 # if (v3.y > y_max) { y_max = v3.y; }
sub_800353B0_ret:
jr $ra
nop
#
# note on [texinfo] offset calculations for animated textures:
# each world transform routine does the following to calculate an offset from the base texinfo
# for a given polygon that has animated texture bits set (anim_len != 0):
#
# b = base offset, h = anim_phase, c = anim_counter, p = anim_period, m = anim_mask
# offs = (h+(c>>p))&((m<<1)|1)
# texinfo = (texinfo*)&texinfo_data[b+offs]
#
# when m is a power of 2 minus 1, the calculation for offs is equivalent to
#
# offs = (h+(c>>p)) % ((m+1)*2)
#
# in this case the animation offset will be an increasing sequence that repeats every
# (m+1)*2 frames. the sequence will otherwise still repeat but will not be strictly
# increasing.
#
# following are the possible sequences for values of m, as (h+(c>>p)) increases by 1:
#
# m= 1: 0, 1, 2, 3...
# m= 2: 0, 1, 0, 1, 4, 5, 4, 5...
# m= 3: 0, 1, 2, 3, 4, 5, 6, 7...
# m= 4: 0, 1, 0, 1, 0, 1, 0, 1, 8, 9, 8, 9, 8, 9, 8, 9...
# m= 5: 0, 1, 2, 3, 0, 1, 2, 3, 8, 9,10,11, 8, 9,10,11...
# m= 6: 0, 1, 0, 1, 4, 5, 4, 5, 8, 9, 8, 9,12,13,12,13...
# m= 7: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15...
# m= 8: 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,16,17,16,17,16,17,16,17,16,17,16,17,16,17,16,17...
# m= 9: 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3,16,17,18,19,16,17,18,19,16,17,18,19,16,17,18,19...
# m=10: 0, 1, 0, 1, 4, 5, 4, 5, 0, 1, 0, 1, 4, 5, 4, 5,16,17,16,17,20,21,20,21,16,17,16,17,20,21,20,21...
# m=11: 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7,16,17,18,19,20,21,22,23,16,17,18,19,20,21,22,23...
# m=12: 0, 1, 0, 1, 0, 1, 0, 1, 8, 9, 8, 9, 8, 9, 8, 9,16,17,16,17,16,17,16,17,24,25,24,25,24,25,24,25...
# m=13: 0, 1, 2, 3, 0, 1, 2, 3, 8, 9,10,11, 8, 9,10,11,16,17,18,19,16,17,18,19,24,25,26,27,24,25,26,27...
# m=14: 0, 1, 0, 1, 4, 5, 4, 5, 8, 9, 8, 9,12,13,12,13,16,17,16,17,20,21,20,21,24,25,24,25,28,29,28,29...
# m=15: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31...
#
#
# translate, rotate, and perspective transform polys of the worlds in scratch memory
# and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# a0 = poly_ids = (in) poly id list [only the polys with ids in this list are processed]
# a1 = ot = (in) ot
# a2 = far = (in) far value
# a3 = anim_counter = (in) counter for animated textures
# arg_10 = prims_tail = (out) pointer to tail pointer of primitive buffer, post-operation
# arg_14 = regions = (in) table of precomputed uv coordinate rects/'regions'
#
RGteTransformWorlds:
poly_ids = $a0
ot = $a1
min_ot_offset = $v1
scratch_worlds = $t0
p_poly_id = $t2
prim = $t3
world_idx = $t4
i_poly_id = $t5
regions = $s6
polys = $s7
verts = $t8
texinfos = $t9
tmp1 = $sp
tmp2 = $fp
tmp3 = $ra
ssave
lw $t7, arg_10($sp)
lw regions, arg_14($sp)
lw prim, 0($t7) # get pointer to primitive memory
li $sp, 0x1F8000E0
sw $a3, arg_0($sp) # save texture anim phase in scratch memory
li $gp, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t7, 0x60 # load mask for selecting semi-trans bits from first word of texinfos
li scratch_worlds, 0x1F800100
lw i_poly_id, 0(poly_ids) # get poly id count; start poly id iterator at end of poly id list
addiu p_poly_id, poly_ids, 2
addu p_poly_id, i_poly_id
addu p_poly_id, i_poly_id # get pointer to the current poly id
li world_idx, 0xFFFF
lui $a0, 0x200 # load code bits for semi-trans primitives
lhu $at, 0(p_poly_id) # get poly id
sll $a2, 2 # multiply far value by sizeof(void*); it will be used as an ot offset
li min_ot_offset, 0x1FFC # initialize with max ot offset
transform_worlds_loop_1:
addiu p_poly_id, -2 # decrement poly id iterator (pointer-based)
srl tmp2, $at, 12 # shift down world index bits
beq tmp2, world_idx, loc_80035510 # skip loading world if already loaded (same world idx)
andi $at, 0xFFF # clear world index bits (poly_idx = poly_id & 0xFFF)
load_world_1:
move world_idx, tmp2 # save world index for above check in next iteration
sll tmp3, world_idx, 6 # world_idx * sizeof(gfx_world)
addu $v0, tmp3, scratch_worlds # get pointer to the world
lw tmp1, 4($v0) # get world trans x
lw tmp2, 8($v0) # get world trans y
lw tmp3, 0xC($v0) # get world trans z
ctc2 tmp1, $5 # set GTE TRX to world trans x
ctc2 tmp2, $6 # set GTE TRY to world trans y
ctc2 tmp3, $7 # set GTE TRZ to world trans z
tpages = $a3
lw polys, 0x14($v0) # get pointer to world polys
lw verts, 0x18($v0) # get pointer to world verts
lw texinfos, 0x1C($v0) # get pointer to world texinfos
addiu tpages, $v0, 0x20 # get pointer to resolved world tpages
transform_poly_1:
sll $at, 3 # get poly offset (poly_offset = poly_idx*sizeof(wgeo_polygon))
addu $t1, polys, $at # get pointer to poly
lw $at, 0($t1)
lw $t1, 4($t1) # get poly data
sll $v0, $at, 12 # shift up bits 1-20 of first word to bits 13-32
andi $sp, $t1, 0xFF # select rightmost byte of second word
or $v0, $sp # or the 2 values and save for further below
srl $s0, $t1, 17 # shift down leftmost 12 bits of word 2 (vert 1 idx)
andi $s0, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s0, verts # get pointer to vert 1
srl $s1, $t1, 5 # shift down bits 9-24 of word 2 (vert 2 idx)
andi $s1, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s1, verts # get pointer to vert 2
srl $s2, $at, 17 # shift down leftmost 12 bits of word 1 (vert 3 idx)
andi $s2, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s2, verts # get pointer to vert 3
lw $s3, 0($s0)
lw $s0, 4($s0)
lw $s4, 0($s1)
lw $s1, 4($s1)
lw $s5, 0($s2)
lw $s2, 4($s2) # get data for each vert (s0-s5 = v1 word2, v1 word1, v2 word2, v2 word1...)
li $at, 0xFFF8FFF8 # load mask for selecting y and x values
and $sp, $s0, $at
and $fp, $s1, $at
and $ra, $s2, $at # use the mask to select yx values from second word of each vert
mtc2 $sp, $0
mtc2 $fp, $2
mtc2 $ra, $4 # set GTE VXY0, VXY1, VXY2
li $at, 0x70006 # load mask for selecting z values
srl $sp, $s3, 24 # (vert 1) shift down upper 8 bits of 1st word to lower 8 bits
sll $sp, 3 # and shift up to multiple of 8, to bits 11-4
and $s0, $at # use mask to select bits from second word
sll $t1, $s0, 10 # shift bits 1 and 2 up to 12 and 13
or $sp, $t1 # or with bits 11-4
srl $t1, $s0, 3 # shift bits 17-19 down to 14-16
or $sp, $t1 # final value sp is z value for vert 1
srl $fp, $s4, 24 # repeat for vert 2...
sll $fp, 3
and $s1, $at
sll $t1, $s1, 10
or $fp, $t1
srl $t1, $s1, 3
or $fp, $t1 # fp is z value for vert 2
srl $ra, $s5, 24 # and vert 3 ...
sll $ra, 3
and $s2, $at
sll $t1, $s2, 10
or $ra, $t1
srl $t1, $s2, 3
or $ra, $t1 # ra is z value for vert 3
mtc2 $sp, $1
mtc2 $fp, $3
mtc2 $ra, $5 # set GTE VZ0, VZ1, VZ2
srl $fp, $v0, 20 # shift down bits 21-32 from the or'ed values above
nop # ...these are bits 9-20 from the first word of the poly data (texinfo/rgbinfo offset divided by 4)
cop2 0x280030 # trans, rot, and perspective transform verts
sll $fp, 2 # multiply offset by 4 (it is stored divided by 4)
addu $t6, texinfos, $fp # get pointer to texinfo
lw $t1, 0($t6) # get first word of texinfo
lui $s2, 0x3400 # load code constant for POLY_GT3 primitives
srl $t1, 24
andi $sp, $t1, 0x80 # get is_textured flag from texinfo word 1
beqz $sp, create_poly_g3_1 # goto create gouraud shaded poly if non-textured
create_poly_gt3_1:
and $s3, $gp # select ... values from lower 3 bytes of first word for vert 1
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
and $fp, $t1, $t7 # select semi-transparency bits from texinfo word 1
beq $fp, $t7, create_poly_gt3_2 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
create_poly_gt3_steq3_1:
or $s3, $s2 # or the primitive code constant (with RGB values)
create_poly_gt3_stlt3_1:
or $s3, $a0 # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_2:
sw $s3, 4(prim) # store primitive code and RGB values for vert 1
sw $s4, 0x10(prim) # store RGB values for vert 2
sw $s5, 0x1C(prim) # store RGB values for vert 3
srl $ra, $v0, 15 # select bits 18-20 from the or'ed values above (bits 6-8 from the first word
andi $ra, 0x1C # of the poly data, index of resolved tpage), as a multiple of sizeof(uint32_t)
addu $at, $ra, tpages # get pointer to resolved tpage
andi $ra, $v0, 0x1E # select bits 2-5 (?) from the or'ed values above (bits 2-5 from the second word)
beqz $ra, create_poly_gt3_3 # if zero then skip adding offsets for an animated texture
create_poly_gt3_animtex_1: # else the value is the 'animation frame index mask'
srl $sp, $v0, 5 # shift down bits 6-8 from the or'ed values above (bits 6-8 from the second word)
li $fp, 0x1F8000E0
lw $fp, 0($fp) # restore the saved anim_counter argument
andi $sp, 7 # select bits 6-8 from the or'ed values above (anim_period)
srlv $fp, $sp # shift the saved anim_counter value right by this amount
srl $sp, $v0, 12
andi $sp, 0x1F # select bits 1-5 from the or'ed values above (anim_phase)
addu $sp, $fp, $sp # add as an offset to the shifted anim_counter value
ori $fp, $ra, 1 # add 1 to the anim_mask value
and $sp, $fp # and with the anim_phase + shifted anim_counter value (*see note above)
sll $sp, 2 # multiply by sizeof(texinfo)/2
addu $t6, $sp, $t6 # add as an offset to the texinfo pointer
create_poly_gt3_3:
lw $s3, 4($t6) # get second word of texinfo
lw $s4, 0($at) # get resolved tpage (a bitfield)
srl $sp, $s3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s0, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
srl $s5, $s3, 20
andi $s5, 3 # get bits 21 and 22 from texinfo word 2 (color mode)
sll $sp, $s5, 7 # shift to bits 8 and 9
andi $fp, $s4, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $fp # or with color mode bits 8 and 9
srl $fp, $s3, 18
andi $fp, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $sp, $fp # or with color mode, tpage y index, and tpage x index
andi $fp, $t1, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $fp # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s4, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s3, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8
srlv $fp, $s5 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s5, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s0, 16 # shift down xy value for the second region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $t1, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s4, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s0, 0xFFFF # select xy value for first region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s5 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_gt3_1 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_gt3_minl_1:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_gt3_1 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_gt3_lim_ot_offset_1:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_gt3_1:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0(prim) # store it as the tag for the POLY_GT3 prim
addiu prim, 0x28 # '(' # add sizeof(POLY_GT3) for next free location in primmem
bgez $zero, transform_worlds_loop_test_1 # loop
nop
create_poly_g3_1:
swc2 $12, 8($t3)
swc2 $13, 0x10($t3)
swc2 $14, 0x18($t3) # store transformed yx values for each vertex in a new POLY_G3 primitive
lui $s2, 0x3000 # load primitive code constant for POLY_G3
or $s3, $s2 # or with the RGB values
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0xC($t3) # store RGB values for vert 2
sw $s5, 0x14($t3) # store RGB values for vert 3
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_g3_1 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_g3_minl_1:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_g3_1 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_g3_lim_ot_offset_1:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_g3_1:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x600 # load len for the POLY_G3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_worlds_loop_test_1:
addiu i_poly_id, -1 # decrement poly_id iterator (index-based)
bnez i_poly_id transform_worlds_loop_1 # continue while nonzero
lhu $at, 0(p_poly_id) # get the next poly id
nop
transform_worlds_end_1:
lw $sp, 0x1F800034
nop
lw $at, arg_10($sp)
nop
sw prim, 0($at) # store the new prims_tail
sload
#
# translate, rotate, and perspective transform polys of the worlds in scratch memory
# and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# this variant interpolates vertex colors with the current far color, for the given far value
#
# a0 = poly_ids = (in) poly id list [only the polys with ids in this list are processed]
# a1 = ot = (in) ot
# a2 = far = (in) far value
# a3 = anim_phase = (in) phase for animated textures
# arg_10 = prims_tail = (out) pointer to tail pointer of primitive buffer, post-operation
# arg_14 = regions = (in) pointer to table of precomputed uv coordinate rects/'regions'
#
RGteTransformWorldsFog:
poly_ids = $a0
min_ot_offset = $v1
scratch_worlds = $t0
p_poly_id = $t2
prim = $t3
world_idx = $t4
i_poly_id = $t5
regions = $s6
polys = $s7
verts = $t8
texinfos = $t9
tmp1 = $sp
tmp2 = $fp
tmp3 = $ra
ssave
lw $t7, arg_10($sp)
lw regions, arg_14($sp)
lw prim, 0($t7) # get pointer to primitive memory
li $sp, 0x1F8000E0
sw $a3, arg_0($sp)
li $gp, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t7, 0x60
li scratch_worlds, 0x1F800100
lw i_poly_id, 0(poly_ids) # get poly id count; start poly id iterator at end of poly id list
addiu p_poly_id, poly_ids, 2
addu p_poly_id, i_poly_id
addu p_poly_id, i_poly_id # get pointer to the current poly id
li world_idx, 0xFFFF
lhu $at, 0(p_poly_id) # get poly id
sll $a2, 2 # multiply far value by sizeof(void*); it will be used as an ot offset
li min_ot_offset, 0x1FFC # initialize with max ot offset
transform_worlds_loop_2:
addiu p_poly_id, -2 # decrement poly id iterator (pointer-based)
srl tmp2, $at, 12 # shift down world index bits
beq tmp2, world_idx, loc_80035510 # skip loading world if already loaded (same world idx)
andi $at, 0xFFF # clear world index bits (poly_idx = poly_id & 0xFFF)
load_world_2:
move world_idx, tmp2 # save world index for above check in next iteration
sll tmp3, world_idx, 6 # world_idx * sizeof(gfx_world)
addu $v0, tmp3, scratch_worlds # get pointer to the world
lw tmp1, 4($v0) # get world trans x
lw tmp2, 8($v0) # get world trans y
lw tmp3, 0xC($v0) # get world trans z
ctc2 tmp1, $5 # set GTE TRX to world trans x
ctc2 tmp2, $6 # set GTE TRY to world trans y
ctc2 tmp3, $7 # set GTE TRZ to world trans z
lw $a3, 0($v0)
lw polys, 0x14($v0) # get pointer to world polys
lw verts, 0x18($v0) # get pointer to world verts
lw texinfos, 0x1C($v0) # get pointer to world texinfos
srl $a0, $a3, 16 # select z dist shamt from world tag
andi $a3, 0xFFFF # select far value from world tag
transform_poly_2:
sll $at, 3 # get poly offset (poly_offset = poly_idx*sizeof(wgeo_polygon))
addu $t1, polys, $at # get pointer to poly
lw $at, 0($t1)
lw $t1, 4($t1) # get poly data
sll $v0, $at, 12 # shift up bits 1-20 of first word to bits 13-32
andi $sp, $t1, 0xFF # select rightmost byte of second word
or $v0, $sp # or the 2 values and save for further below
srl $s0, $t1, 17 # shift down leftmost 12 bits of word 2 (vert 1 idx)
andi $s0, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s0, verts # get pointer to vert 1
srl $s1, $t1, 5 # shift down bits 9-24 of word 2 (vert 2 idx)
andi $s1, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s1, verts # get pointer to vert 2
srl $s2, $at, 17 # shift down leftmost 12 bits of word 1 (vert 3 idx)
andi $s2, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s2, verts # get pointer to vert 3
lw $s3, 0($s0)
lw $s0, 4($s0)
lw $s4, 0($s1)
lw $s1, 4($s1)
lw $s5, 0($s2)
lw $s2, 4($s2) # get data for each vert (s0-s5 = v1 word2, v1 word1, v2 word2, v2 word1...)
li $at, 0xFFF8FFF8 # load mask for selecting y and x values
and $sp, $s0, $at
and $fp, $s1, $at
and $ra, $s2, $at # use the mask to select yx values from second word of each vert
mtc2 $sp, $0
mtc2 $fp, $2
mtc2 $ra, $4 # set GTE VXY0, VXY1, VXY2
li $at, 0x70006 # load mask for selecting z values
srl $sp, $s3, 24 # (vert 1) shift down upper 8 bits of 1st word to lower 8 bits
sll $sp, 3 # and shift up to multiple of 8, to bits 11-4
and $s0, $at # use mask to select bits from second word
sll $t1, $s0, 10 # shift bits 1 and 2 up to 12 and 13
or $sp, $t1 # or with bits 11-4
srl $t1, $s0, 3 # shift bits 17-19 down to 14-16
or $sp, $t1 # final value sp is z value for vert 1
srl $fp, $s4, 24 # repeat for vert 2...
sll $fp, 3
and $s1, $at
sll $t1, $s1, 10
or $fp, $t1
srl $t1, $s1, 3
or $fp, $t1 # fp is z value for vert 2
srl $ra, $s5, 24 # and vert 3 ...
sll $ra, 3
and $s2, $at
sll $t1, $s2, 10
or $ra, $t1
srl $t1, $s2, 3
or $ra, $t1 # ra is z value for vert 3
mtc2 $sp, $1
mtc2 $fp, $3
mtc2 $ra, $5 # set GTE VZ0, VZ1, VZ2
srl $fp, $v0, 20 # shift down bits 21-32 from the or'ed values above
# nop # ...these are bits 9-20 from the first word of the poly data (texinfo/rgbinfo offset divided by 4)
cop2 0x280030 # trans, rot, and perspective transform verts
sll $fp, 2 # multiply offset by 4 (it is stored divided by 4)
addu $t6, texinfos, $fp # get pointer to texinfo
lw $t1, 0($t6) # get first word of texinfo
lui $s2, 0x3400 # load code constant for POLY_GT3 primitives
srl $t1, 24
andi $sp, $t1, 0x80 # get is_textured flag from texinfo word 1
beqz $sp, create_poly_g3_2 # goto create gouraud shaded poly if non-textured
create_poly_gt3_4:
and $s3, $gp # select rgb value for vert 1 from lower 3 bytes of first word
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
create_poly_gt3_rgb1_1:
mfc2 $sp, $17 # get transformed z value for vert 1
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
slt $fp, $a3, $sp
beqz $fp, create_poly_gt3_rgb2_1 # skip rgb interp for transformed vert 1 if z <= the passed far value
create_poly_gt3_rgb1_2:
subu $fp, $sp, $a3 # calc z dist of transformed vert 1 from passed far value
sllv $fp, $a0 # shift left by z dist shamt
mtc2 $fp, $8 # set GTE IR0 to the shifted value
nop # (IR0 is the t value used for interpolation)
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s3, $22 # get the interpolated rgb value
create_poly_gt3_rgb2_1: # repeat for vert 2...
mfc2 $ra, $18 # get transformed z value for vert 2
nop
addu $s1, $sp, $ra # get sum of transformed vert 1 z and transofmred vert 2 z
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
slt $fp, $a3, $ra
beqz $fp, create_poly_gt3_rgb2_2 # skip rgb interp for transformed vert 2 if z >= the passed far value
create_poly_gt3_rgb2_2:
subu $fp, $ra, $a3 # calc z dist of transformed vert 2 from passed far value
sllv $fp, $a0 # shift left by z dist shamt
mtc2 $fp, $8 # set GTE IR0 to the shifted value
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s4, $22 # get the interpolated rgb value
create_poly_gt3_rgb3_1: # repeat for vert 3...
mfc2 $sp, $19
nop
addu $s1, $sp # get sum of z values for transformed vert 1, vert 2, and vert 3
mtc2 $s5, $6
slt $fp, $a3, $sp
beqz $fp, loc_80035B1C
create_poly_gt3_rgb3_2:
subu $fp, $sp, $a3
sllv $fp, $a0
mtc2 $fp, $8
nop
cop2 0x780010
nop
mfc2 $s5, $22 # get the interpolated rgb value
create_poly_gt3_st_2:
srl $s1, 5 # compute sum of z values over 32 (average over 10.666); this is an index
srl $s1, 2 # multiply by sizeof(void*)
and $fp, $t1, $t7 # select semi-transparency bits from texinfo word 1
beq $fp, $t7, create_poly_gt3_5 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
create_poly_gt3_steq3_2:
or $s3, $s2 # or the primitive code constant (with RGB values)
create_poly_gt3_stlt3_2:
lui $fp, 0x200 # load code bits for semi-trans primitives
or $s3, $fp # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_5:
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0x10($t3) # store RGB values for vert 2
sw $s5, 0x1C($t3) # store RGB values for vert 3
srl $ra, $v0, 15 # select bits 18-20 from the or'ed values above (bits 6-8 from the first word
andi $ra, 0x1C # of the poly data, index of resolved tpage), as a multiple of sizeof(uint32_t)
addu $at, $ra, tpages # get pointer to resolved tpage
andi $ra, $v0, 0x1E # select bits 2-5 (?) from the or'ed values above (bits 2-5 from the second word)
beqz $ra, create_poly_gt3_6 # if zero then skip adding offsets for an animated texture
create_poly_gt3_animtex_2: # else the value is the 'animation frame index mask'
srl $sp, $v0, 5 # shift down bits 6-8 from the or'ed values above (bits 6-8 from the second word)
li $fp, 0x1F8000E0
lw $fp, 0($fp) # restore the saved anim_counter argument
andi $sp, 7 # select bits 6-8 from the or'ed values above (anim_period)
srlv $fp, $sp # shift the saved anim_counter value right by this amount
srl $sp, $v0, 12
andi $sp, 0x1F # select bits 1-5 from the or'ed values above (anim_phase)
addu $sp, $fp, $sp # add as an offset to the shifted anim_counter value
ori $fp, $ra, 1 # add 1 to the anim_mask value
and $sp, $fp # and with the anim_phase + shifted anim_counter value (*see note above)
sll $sp, 2 # multiply by sizeof(texinfo)/2
addu $t6, $sp, $t6 # add as an offset to the texinfo pointer
create_poly_gt3_6:
lw $s3, 4($t6) # get second word of texinfo
lw $s4, 0($at) # get resolved tpage (a bitfield)
srl $sp, $s3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s0, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
srl $s5, $s3, 20
andi $s5, 3 # get bits 21 and 22 from texinfo word 2 (color mode)
sll $sp, $s5, 7 # shift to bits 8 and 9
andi $fp, $s4, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $fp # or with color mode bits 8 and 9
srl $fp, $s3, 18
andi $fp, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $sp, $fp # or with color mode, tpage y index, and tpage x index
andi $fp, $t1, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $fp # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s4, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s3, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8 (the value is stored / 8)
srlv $fp, $s5 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s5, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s0, 16 # shift down xy value for the second region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $t1, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s4, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s0, 0xFFFF # select xy value for first region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s5 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
sub $sp, $a2, $s1 # get distance of z value average/ot offset from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_gt3_1 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_gt3_minl_2:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_gt3_2 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_gt3_lim_ot_offset_2:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_gt3_2:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_GT3 prim
addiu prim, 0x28 # '(' # add sizeof(POLY_GT3) for next free location in primmem
bgez $zero, transform_worlds_loop_test_2 # loop
nop
create_poly_g3_2:
swc2 $12, 8($t3)
swc2 $13, 0x10($t3)
swc2 $14, 0x18($t3) # store transformed yx values for each vertex in a new POLY_G3 primitive
create_poly_g3_rgb1_1:
mfc2 $sp, $17 # get transformed z value for vert 1
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
slt $fp, $a3, $sp
beqz $fp, create_poly_g3_rgb2_1 # skip rgb interp for transformed vert 1 if z >= the passed far value
create_poly_g3_rgb1_2:
subu $fp, $sp, $a3 # calc z dist of transformed vert 1 from passed far value
sllv $fp, $a0 # shift left by z dist shamt
mtc2 $fp, $8 # set GTE IR0 to the shifted value
nop # (IR0 is the t value used for interpolation)
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s3, $22 # get the interpolated rgb value
create_poly_g3_rgb2_1: # repeat for vert 2...
mfc2 $ra, $18 # get transformed z value for vert 2
nop
addu $s1, $sp, $ra # get sum of transformed vert 1 z and transofmred vert 2 z
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
slt $fp, $a3, $ra
beqz $fp, create_poly_g3_rgb2_2 # skip rgb interp for transformed vert 2 if z >= the passed far value
create_poly_g3_rgb2_2:
subu $fp, $ra, $a3 # calc z dist of transformed vert 2 from passed far value
sllv $fp, $a0 # shift left by z dist shamt
mtc2 $fp, $8 # set GTE IR0 to the shifted value
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s4, $22 # get the interpolated rgb value
create_poly_g3_rgb3_1: # repeat for vert 3...
mfc2 $sp, $19
nop
addu $s1, $sp # get sum of z values for transformed vert 1, vert 2, and vert 3
mtc2 $s5, $6
slt $fp, $a3, $sp
beqz $fp, loc_80035B1C
create_poly_g3_rgb3_2:
subu $fp, $sp, $a3
sllv $fp, $a0
mtc2 $fp, $8
nop
cop2 0x780010
nop
mfc2 $s5, $22 # get the interpolated rgb value
create_poly_g3_2:
srl $s1, 5 # compute sum of z values over 32 (average over 10.666); this is an index
srl $s1, 2 # multiply by sizeof(void*)
and $s3, $gp
lui $s2, 0x3000 # load primitive code constant for POLY_G3
or $s3, $s2 # or with the RGB value for vert 1
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0xC($t3) # store RGB values for vert 2
sw $s5, 0x14($t3) # store RGB values for vert 3
sub $sp, $a2, $sp # get distance of z value average/ot offset from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_g3_2 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_g3_minl_2:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_g3_1 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_g3_lim_ot_offset_2:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_g3_2:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x600 # load len for the POLY_G3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_worlds_loop_test_2:
addiu i_poly_id, -1 # decrement poly_id iterator (index-based)
bnez i_poly_id transform_worlds_loop_1 # continue while nonzero
lhu $at, 0(p_poly_id) # get the next poly id
nop
transform_worlds_end_2:
lw $sp, 0x1F800034
nop
lw $at, arg_10($sp)
nop
sw prim, 0($at) # store the new prims_tail
sload
#
# translate, rotate, and perspective transform polys of the worlds in scratch memory
# and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# this variant adjusts the y position of verts via a positional vertex shader
# the y offset for a vertex is determined by the value at index ((y+x)/8)%16
# in the array of precomputed offsets in scratch memory, where x and y are
# the [model] coordinates of the untransformed vertex
#
# it is used to create a ripple effect for polygons which represent water
#
# a0 = poly_ids = (in) poly id list [only the polys with ids in this list are processed]
# a1 = ot = (in) ot
# a2 = far = (in) far value
# a3 = anim_phase = (in) phase for animated textures
# arg_10 = prims_tail = (out) pointer to tail pointer of primitive buffer, post-operation
# arg_14 = regions = (in) pointer to table of precomputed uv coordinate rects/'regions'
#
RGteTransformWorldsRipple:
poly_ids = $a0
ot = $a1
min_ot_offset = $v1
scratch_worlds = $t0
p_poly_id = $t2
prim = $t3
world_idx = $t4
i_poly_id = $t5
regions = $s6
polys = $s7
verts = $t8
texinfos = $t9
tmp1 = $sp
tmp2 = $fp
tmp3 = $ra
ssave
lw $t7, arg_10($sp)
lw regions, arg_14($sp)
lw prim, 0($t7) # get pointer to primitive memory
li $sp, 0x1F8000E0
sw $a3, arg_0($sp) # save pointer to prims pointer (out param) in scratch memory
li $gp, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t7, 0x60
li scratch_worlds, 0x1F800100
lw i_poly_id, 0(poly_ids) # get poly id count; start poly id iterator at end of poly id list
addiu p_poly_id, poly_ids, 2
addu p_poly_id, i_poly_id
addu p_poly_id, i_poly_id # get pointer to the current poly id
li world_idx, 0xFFFF
lui $a0, 0x200 # load code bits for textured primitives
lhu $at, 0(p_poly_id) # get poly id
sll $a2, 2 # multiply far value by sizeof(void*); it will be used as an ot offset
li min_ot_offset, 0x1FFC # initialize with max ot offset
transform_worlds_loop_3:
addiu p_poly_id, -2 # decrement poly id iterator (pointer-based)
srl tmp2, $at, 12 # shift down world index bits
beq tmp2, world_idx, transform_poly_3 # skip loading world if already loaded (same world idx)
andi $at, 0xFFF # clear world index bits (poly_idx = poly_id & 0xFFF)
load_world_3:
move world_idx, tmp2 # save world index for above check in next iteration
sll tmp3, world_idx, 6 # world_idx * sizeof(gfx_world)
addu $v0, tmp3, scratch_worlds # get pointer to the world
lw tmp1, 4($v0) # get world trans x
lw tmp2, 8($v0) # get world trans y
lw tmp3, 0xC($v0) # get world trans z
ctc2 tmp1, $5 # set GTE TRX to world trans x
ctc2 tmp2, $6 # set GTE TRY to world trans y
ctc2 tmp3, $7 # set GTE TRZ to world trans z
tpages = $a3
lw polys, 0x14($v0) # get pointer to world polys
lw verts, 0x18($v0) # get pointer to world verts
lw texinfos, 0x1C($v0) # get pointer to world texinfos
addiu tpages, $v0, 0x20 # get pointer to resolved world tpages
transform_poly_3:
sll $at, 3 # get poly offset (poly_offset = poly_idx*sizeof(wgeo_polygon))
addu $t1, polys, $at # get pointer to poly
lw $at, 0($t1)
lw $t1, 4($t1) # get poly data
sll $v0, $at, 12 # shift up bits 1-20 of first word to bits 13-32
andi $sp, $t1, 0xFF # select rightmost byte of second word
or $v0, $sp # or the 2 values and save for further below
srl $s0, $t1, 17 # shift down leftmost 12 bits of word 2 (vert 1 idx)
andi $s0, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s0, verts # get pointer to vert 1
srl $s1, $t1, 5 # shift down bits 9-24 of word 2 (vert 2 idx)
andi $s1, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s1, verts # get pointer to vert 2
srl $s2, $at, 17 # shift down leftmost 12 bits of word 1 (vert 3 idx)
andi $s2, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s2, verts # get pointer to vert 3
lw $s3, 0($s0)
lw $s0, 4($s0)
lw $s4, 0($s1)
lw $s1, 4($s1)
lw $s5, 0($s2)
lw $s2, 4($s2) # get data for each vert (s0-s5 = v1 word2, v1 word1, v2 word2, v2 word1...)
li $at, 0xFFF8FFF8 # load mask for selecting y and x values
transform_poly_test_v1fx_1:
li $ra, 0x1F800048 # load pointer to value array in scratch memory
andi $sp, $s0, 1 # get bit 1 of vert 1 word 2 (fx)
beqz $sp, transform_poly_test_v2fx_1 # if fx bit is clear then skip fx for vert 1
and $sp, $s0, $at # use mask to select yx values for vert 1 from second word
transform_poly_v1fx_1: # compute adjusted yx values for vert 1
srl $fp, $sp, 19 # shift down the y value
andi $t1, $sp, 0xFFF8
srl $t1, 3 # ...and the x value
addu $fp, $t1 # add y and x value (divided by 8)
andi $fp, 0xF
sll $fp, 2 # fp = (((y+x)/8)%16) * sizeof(int32_t)
addu $t1, $fp, $ra
lw $fp, 0($t1) # get value at index ((y+x)/8)%16 in the scratch array
nop
sra $t1, $sp, 16 # shift down y value again, this time as a multiple of 8
addu $t1, $fp # add the scratch array value
sll $t1, 16 # shift to the upper hword
sll $fp, $s0, 16
srl $fp, 16 # select x value and cast to 32 bit int (shift up sign bit)
or $sp, $fp, $t1 # or with the y value in upper hword
transform_poly_test_v2fx_1:
mtc2 $sp, $0 # set GTE VXY0 to (possibly adjusted) yx value
andi $sp, $s1, 1 # repeat for vert 2...
beqz $sp, transform_poly_test_v3fx_1
transform_poly_v2fx_1:
and $sp, $s1, $at
srl $fp, $sp, 19
andi $t1, $sp, 0xFFF8
srl $t1, 3
addu $fp, $t1
andi $fp, 0xF
sll $fp, 2
addu $t1, $fp, $ra
lw $fp, 0($t1)
nop
sra $t1, $sp, 16
addu $t1, $fp
sll $t1, 16
sll $fp, $s1, 16
srl $fp, 16
or $sp, $fp, $t1
transform_poly_test_v3fx_1:
mtc2 $sp, $2 # set GTE VXY1 to (possibly adjusted) yx value
andi $sp, $s2, 1 # repeat for vert 3...
beqz $sp, transform_poly_3b
transform_poly_v3fx_1:
and $sp, $s2, $at
srl $fp, $sp, 19
andi $t1, $sp, 0xFFF8
srl $t1, 3
addu $fp, $t1
andi $fp, 0xF
sll $fp, 2
addu $t1, $fp, $ra
lw $fp, 0($t1)
nop
sra $t1, $sp, 16
addu $t1, $fp
sll $t1, 16
sll $fp, $s2, 16
srl $fp, 16
or $sp, $fp, $t1
transform_poly_3b:
mtc2 $sp, $4 # set GTE VXY2 to (possibly adjusted) yx value
li $at, 0x70006 # load mask for selecting z values
srl $sp, $s3, 24 # (vert 1) shift down upper 8 bits of 1st word to lower 8 bits
sll $sp, 3 # and shift up to multiple of 8, to bits 11-4
and $s0, $at # use mask to select bits from second word
sll $t1, $s0, 10 # shift bits 1 and 2 up to 12 and 13
or $sp, $t1 # or with bits 11-4
srl $t1, $s0, 3 # shift bits 17-19 down to 14-16
or $sp, $t1 # final value sp is z value for vert 1
srl $fp, $s4, 24 # repeat for vert 2...
sll $fp, 3
and $s1, $at
sll $t1, $s1, 10
or $fp, $t1
srl $t1, $s1, 3
or $fp, $t1 # fp is z value for vert 2
srl $ra, $s5, 24 # and vert 3 ...
sll $ra, 3
and $s2, $at
sll $t1, $s2, 10
or $ra, $t1
srl $t1, $s2, 3
or $ra, $t1 # ra is z value for vert 3
mtc2 $sp, $1
mtc2 $fp, $3
mtc2 $ra, $5 # set GTE VZ0, VZ1, VZ2
srl $fp, $v0, 20 # shift down bits 21-32 from the or'ed values above
nop # ...these are bits 9-20 from the first word of the poly data (texinfo/rgbinfo offset divided by 4)
cop2 0x280030 # trans, rot, and perspective transform verts
sll $fp, 2 # multiply offset by 4 (it is stored divided by 4)
addu $t6, texinfos, $fp # get pointer to texinfo
lw $t1, 0($t6) # get first word of texinfo
lui $s2, 0x3400 # load code constant for POLY_GT3 primitives
srl $t1, 24
andi $sp, $t1, 0x80 # get is_textured flag from texinfo word 1
beqz $sp, create_poly_g3_3 # goto create gouraud shaded poly if non-textured
create_poly_gt3_7:
and $s3, $gp # select ... values from lower 3 bytes of first word for vert 1
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
and $fp, $t1, $t7 # select semi-transparency bits from texinfo word 1
beq $fp, $t7, create_poly_gt3_8 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
create_poly_gt3_steq3_3:
or $s3, $s2 # or the primitive code constant (with RGB values)
create_poly_gt3_stlt3_3:
or $s3, $a0 # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_8:
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0x10($t3) # store RGB values for vert 2
sw $s5, 0x1C($t3) # store RGB values for vert 3
srl $ra, $v0, 15 # select bits 18-20 from the or'ed values above (bits 6-8 from the first word
andi $ra, 0x1C # of the poly data, index of resolved tpage), as a multiple of sizeof(uint32_t)
addu $at, $ra, tpages # get pointer to resolved tpage
andi $ra, $v0, 0x1E # select bits 2-5 (?) from the or'ed values above (bits 2-5 from the second word)
beqz $ra, create_poly_gt3_9 # if zero then skip adding offsets for an animated texture
create_poly_gt3_animtex_3: # else the value is the 'animation frame index mask'
srl $sp, $v0, 5 # shift down bits 6-8 from the or'ed values above (bits 6-8 from the second word)
li $fp, 0x1F8000E0
lw $fp, 0($fp) # restore the saved anim_counter argument
andi $sp, 7 # select bits 6-8 from the or'ed values above (anim_period)
srlv $fp, $sp # shift the saved anim_counter value right by this amount
srl $sp, $v0, 12
andi $sp, 0x1F # select bits 1-5 from the or'ed values above (anim_phase)
addu $sp, $fp, $sp # add as an offset to the shifted anim_counter value
ori $fp, $ra, 1 # add 1 to the anim_mask value
and $sp, $fp # and with the anim_phase + shifted anim_counter value (*see note above)
sll $sp, 2 # multiply by sizeof(texinfo)/2
addu $t6, $sp, $t6 # add as an offset to the texinfo pointer
create_poly_gt3_9:
lw $s3, 4($t6) # get second word of texinfo
lw $s4, 0($at) # get resolved tpage (a bitfield)
srl $sp, $s3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s0, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
srl $s5, $s3, 20
andi $s5, 3 # get bits 21 and 22 from texinfo word 2 (color mode)
sll $sp, $s5, 7 # shift to bits 8 and 9
andi $fp, $s4, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $fp # or with color mode bits 8 and 9
srl $fp, $s3, 18
andi $fp, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $sp, $fp # or with color mode, tpage y index, and tpage x index
andi $fp, $t1, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $fp # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s4, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s3, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8
srlv $fp, $s5 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s5, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s0, 16 # shift down xy value for the second region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $t1, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s4, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s0, 0xFFFF # select xy value for first region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s5 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_gt3_3 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_gt3_minl_3:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_gt3_3 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_gt3_lim_ot_offset_3:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_gt3_3:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_GT3 prim
addiu prim, 0x28 # '(' # add sizeof(POLY_GT3) for next free location in primmem
bgez $zero, transform_worlds_loop_test_3 # loop
nop
create_poly_g3_3:
swc2 $12, 8($t3)
swc2 $13, 0x10($t3)
swc2 $14, 0x18($t3) # store transformed yx values for each vertex in a new POLY_G3 primitive
lui $s2, 0x3000 # load primitive code constant for POLY_G3
or $s3, $s2 # or with the RGB values
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0xC($t3) # store RGB values for vert 2
sw $s5, 0x14($t3) # store RGB values for vert 3
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_g3_3 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_g3_minl_3:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_g3_3 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_g3_lim_ot_offset_3:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_g3_3:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x600 # load len for the POLY_G3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_worlds_loop_test_3:
addiu i_poly_id, -1 # decrement poly_id iterator (index-based)
bnez i_poly_id transform_worlds_loop_3 # continue while nonzero
lhu $at, 0(p_poly_id) # get the next poly id
nop
transform_worlds_end_3:
lw $sp, 0x1F800034
nop
lw $at, arg_10($sp)
nop
sw prim, 0($at) # store the new prims_tail
sload
#
# translate, rotate, and perspective transform polys of the worlds in scratch memory
# and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# this variant interpolates vertex colors depending on fx bit
# - fx bit = 0 => use far color scratch values 1-3, IR0 scratch value 4
# - fx bit = 1 => use far color scratch values 5-7, IR0 scratch value 8
#
# it is used to create a lightning effect
#
RGteTransformWorldsLightning:
poly_ids = $a0
ot = $a1
min_ot_offset = $v1
scratch_worlds = $t0
p_poly_id = $t2
prim = $t3
world_idx = $t4
i_poly_id = $t5
regions = $s6
polys = $s7
verts = $t8
texinfos = $t9
tmp1 = $sp
tmp2 = $fp
tmp3 = $ra
ssave
lw $t7, arg_10($sp)
lw regions, arg_14($sp)
lw prim, 0($t7) # get pointer to primitive memory
li $sp, 0x1F8000E0
sw $a3, arg_0($sp) # save pointer to prims pointer (out param) in scratch memory
li $gp, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t7, 0x60
li scratch_worlds, 0x1F800100
lw i_poly_id, 0(poly_ids) # get poly id count; start poly id iterator at end of poly id list
addiu p_poly_id, poly_ids, 2
addu p_poly_id, i_poly_id
addu p_poly_id, i_poly_id # get pointer to the current poly id
li world_idx, 0xFFFF
lui $a0, 0x200 # load code bits for textured primitives
lhu $at, 0(p_poly_id) # get poly id
sll $a2, 2 # multiply far value by sizeof(void*); it will be used as an ot offset
li min_ot_offset, 0x1FFC # initialize with max ot offset
transform_worlds_loop_4:
addiu p_poly_id, -2 # decrement poly id iterator (pointer-based)
srl tmp2, $at, 12 # shift down world index bits
beq tmp2, world_idx, transform_poly_4 # skip loading world if already loaded (same world idx)
andi $at, 0xFFF # clear world index bits (poly_idx = poly_id & 0xFFF)
load_world_4:
move world_idx, tmp2 # save world index for above check in next iteration
sll tmp3, world_idx, 6 # world_idx * sizeof(gfx_world)
addu $v0, tmp3, scratch_worlds # get pointer to the world
lw tmp1, 4($v0) # get world trans x
lw tmp2, 8($v0) # get world trans y
lw tmp3, 0xC($v0) # get world trans z
ctc2 tmp1, $5 # set GTE TRX to world trans x
ctc2 tmp2, $6 # set GTE TRY to world trans y
ctc2 tmp3, $7 # set GTE TRZ to world trans z
tpages = $a3
lw polys, 0x14($v0) # get pointer to world polys
lw verts, 0x18($v0) # get pointer to world verts
lw texinfos, 0x1C($v0) # get pointer to world texinfos
addiu tpages, $v0, 0x20 # get pointer to resolved world tpages
transform_poly_4:
sll $at, 3 # get poly offset (poly_offset = poly_idx*sizeof(wgeo_polygon))
addu $t1, polys, $at # get pointer to poly
lw $at, 0($t1)
lw $t1, 4($t1) # get poly data
sll $v0, $at, 12 # shift up bits 1-20 of first word to bits 13-32
andi $sp, $t1, 0xFF # select rightmost byte of second word
or $v0, $sp # or the 2 values and save for further below
srl $s0, $t1, 17 # shift down leftmost 12 bits of word 2 (vert 1 idx)
andi $s0, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s0, verts # get pointer to vert 1
srl $s1, $t1, 5 # shift down bits 9-24 of word 2 (vert 2 idx)
andi $s1, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s1, verts # get pointer to vert 2
srl $s2, $at, 17 # shift down leftmost 12 bits of word 1 (vert 3 idx)
andi $s2, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s2, verts # get pointer to vert 3
lw $s3, 0($s0)
lw $s0, 4($s0)
lw $s4, 0($s1)
lw $s1, 4($s1)
lw $s5, 0($s2)
lw $s2, 4($s2) # get data for each vert (s0-s5 = v1 word2, v1 word1, v2 word2, v2 word1...)
li $t1, 0x1F800048 # get pointer to scratch values
lw $ra, 0xC($t1) # load 4th value in scratch
andi $sp, $s0, 1 # get bit 1 of vert 1 word 2 (fx)
andi $fp, $s1, 1 # get fx bit for vert 2
sll $fp, 1 # shift up to bit 2
or $sp, $fp # or with vert 1 fx bit 1
andi $fp, $s2, 1 # get fx bit for vert 3
sll $fp, 2 # shift up to bit 3
or $at, $sp, $fp # or with the other 2 fx bits
or $fp, $at, $ra # or with the 4th scratch value
# fp = scratch.values[3] | (v1_fx | (v2_fx << 1) | (v3_fx << 2))
beqz $fp, transform_poly_4b # skip rgb interpolation if no fx bits are set or scratch value is 0
mtc2 $ra, $8 # set GTE IR0 to the 4th scratch value
lw $sp, 0($t1)
lw $fp, 4($t1)
lw $ra, 8($t1) # get the first 3 scratch values, an RGB far color
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch far color
li $ra, transform_poly_fx_000_1 # get start of the next code block
sll $sp, $at, 7 # multiply index calculated from fx bits by 32 instructions (128 bytes)
addu $ra, $sp # add to address of the next code block
jr $ra # jump to the corresponding 32 instruction code section
nor $fp, $gp, $zero # get mask for selecting upper byte
# ---------------------------------------------------------------------------
transform_poly_fx_000_1: # interpolate RGBs for all 3 verts with far color scratch values 1-3, IR0 scratch value 4
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
nop
cop2 0x780010 # interpolate between RGB and the far color
and $s3, $fp # select the upper byte (?) of vert 1 word 1
mfc2 $sp, $22 # get the interpolated rgb value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
and $s4, $fp # select upper byte of vert 2 word 1
mfc2 $sp, $22 # get the interpolated rgb value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated rgb value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s5, $sp # or the values
nop # results are in $s3, $s4, and $s5
nop
nop # when an fx bit is clear the corresponding vert RGB is interpolated
nop # with the far color from scratch values 1-3
nop # and IR0 from the 4th scratch value
nop # when an fx bit is set the corresponding vert RGB is interpolated
nop # with the far color from scratch values 5-7
nop # and IR0 from the 8th scratch value
nop
nop
# ---------------------------------------------------------------------------
transform_poly_fx_001_1: # interpolate RGBs for verts 2&3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGB for vert 1 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
nop
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or the values
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s3, $sp # or with the upper byte of vert 1 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_010_1:
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or the values
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s4, $sp # or with the upper byte of vert 2 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_011_1: # interpolate RGB for vert 3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGBs for verts 1&2 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
nop
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or with the upper byte of vert 3 word 1
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s4, $sp # or with the upper byte of vert 2 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_100_1: # interpolate RGBs for verts 2&3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGB for vert 1 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s4, $fp # select upper byte of vert 2 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or the values
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s5, $sp # or with the upper byte of vert 3 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_101_1: # interpolate RGB for vert 2 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGBs for verts 1&3 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
nop
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s5, $sp # or with the upper byte of vert 3 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_110_1: # interpolate RGB for vert 3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGBs for verts 1&2 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_4b # skip past the other 32 instruction code sections
or $s5, $sp # or with the upper byte of vert 3 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_111_1: # interpolate RGBs for all verts with far color scratch values 5-7, IR0 scratch value 8
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
nop
cop2 0x780010 # interpolate between RGB and the far color
and $s3, $fp # select upper byte of vert 1 word 1
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
and $s4, $fp # select upper byte of vert 2 word 1
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or with the upper byte of vert 3 word 1
transform_poly_4b:
li $at, 0xFFF8FFF8 # load mask for selecting y and x values
and $sp, $s0, $at
and $fp, $s1, $at
and $ra, $s2, $at # use the mask to select yx values from second word of each vert
mtc2 $sp, $0
mtc2 $fp, $2
mtc2 $ra, $4 # set GTE VXY0, VXY1, VXY2
li $at, 0x70006 # load mask for selecting z values
srl $sp, $s3, 24 # (vert 1) shift down upper 8 bits of 1st word to lower 8 bits
sll $sp, 3 # and shift up to multiple of 8, to bits 11-4
and $s0, $at # use mask to select bits from second word
sll $t1, $s0, 10 # shift bits 1 and 2 up to 12 and 13
or $sp, $t1 # or with bits 11-4
srl $t1, $s0, 3 # shift bits 17-19 down to 14-16
or $sp, $t1 # final value sp is z value for vert 1
srl $fp, $s4, 24 # repeat for vert 2...
sll $fp, 3
and $s1, $at
sll $t1, $s1, 10
or $fp, $t1
srl $t1, $s1, 3
or $fp, $t1 # fp is z value for vert 2
srl $ra, $s5, 24 # and vert 3 ...
sll $ra, 3
and $s2, $at
sll $t1, $s2, 10
or $ra, $t1
srl $t1, $s2, 3
or $ra, $t1 # ra is z value for vert 3
mtc2 $sp, $1
mtc2 $fp, $3
mtc2 $ra, $5 # set GTE VZ0, VZ1, VZ2
srl $fp, $v0, 20 # shift down bits 21-32 from the or'ed values above
nop # ...these are bits 9-20 from the first word of the poly data (texinfo/rgbinfo offset divided by 4)
cop2 0x280030 # trans, rot, and perspective transform verts
sll $fp, 2 # multiply offset by 4 (it is stored divided by 4)
addu $t6, texinfos, $fp # get pointer to texinfo
lw $t1, 0($t6) # get first word of texinfo
lui $s2, 0x3400 # load code constant for POLY_GT3 primitives
srl $t1, 24
andi $sp, $t1, 0x80 # get is_textured flag from texinfo word 1
beqz $sp, create_poly_g3_4 # goto create gouraud shaded poly if non-textured
create_poly_gt3_10:
and $s3, $gp # select ... values from lower 3 bytes of first word for vert 1
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
and $fp, $t1, $t7 # select semi-transparency bits from texinfo word 1
beq $fp, $t7, create_poly_gt3_11 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
create_poly_gt3_steq3_4:
or $s3, $s2 # or the primitive code constant (with RGB values)
create_poly_gt3_stlt3_4:
or $s3, $a0 # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_11:
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0x10($t3) # store RGB values for vert 2
sw $s5, 0x1C($t3) # store RGB values for vert 3
srl $ra, $v0, 15 # select bits 18-20 from the or'ed values above (bits 6-8 from the first word
andi $ra, 0x1C # of the poly data, index of resolved tpage), as a multiple of sizeof(uint32_t)
addu $at, $ra, tpages # get pointer to resolved tpage
andi $ra, $v0, 0x1E # select bits 2-5 (?) from the or'ed values above (bits 2-5 from the second word)
beqz $ra, create_poly_gt3_12 # if zero then skip adding offsets for an animated texture
create_poly_gt3_animtex_4: # else the value is the 'animation frame index mask'
srl $sp, $v0, 5 # shift down bits 6-8 from the or'ed values above (bits 6-8 from the second word)
li $fp, 0x1F8000E0
lw $fp, 0($fp) # restore the saved anim_counter argument
andi $sp, 7 # select bits 6-8 from the or'ed values above (anim_period)
srlv $fp, $sp # shift the saved anim_counter value right by this amount
srl $sp, $v0, 12
andi $sp, 0x1F # select bits 1-5 from the or'ed values above (anim_phase)
addu $sp, $fp, $sp # add as an offset to the shifted anim_counter value
ori $fp, $ra, 1 # add 1 to the anim_mask value
and $sp, $fp # and with the anim_phase + shifted anim_counter value (*see note above)
sll $sp, 2 # multiply by sizeof(texinfo)/2
addu $t6, $sp, $t6 # add as an offset to the texinfo pointer
create_poly_gt3_12:
lw $s3, 4($t6) # get second word of texinfo
lw $s4, 0($at) # get resolved tpage (a bitfield)
srl $sp, $s3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s0, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
srl $s5, $s3, 20
andi $s5, 3 # get bits 21 and 22 from texinfo word 2 (color mode)
sll $sp, $s5, 7 # shift to bits 8 and 9
andi $fp, $s4, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $fp # or with color mode bits 8 and 9
srl $fp, $s3, 18
andi $fp, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $sp, $fp # or with color mode, tpage y index, and tpage x index
andi $fp, $t1, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $fp # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s4, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s3, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8
srlv $fp, $s5 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s5, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s0, 16 # shift down xy value for the second region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $t1, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s4, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s0, 0xFFFF # select xy value for first region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s5 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_gt3_4 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_gt3_minl_4:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_gt3_4 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_gt3_lim_ot_offset_4:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_gt3_4:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_GT3 prim
addiu prim, 0x28 # '(' # add sizeof(POLY_GT3) for next free location in primmem
bgez $zero, transform_worlds_loop_test_4 # loop
nop
create_poly_g3_4:
swc2 $12, 8($t3)
swc2 $13, 0x10($t3)
swc2 $14, 0x18($t3) # store transformed yx values for each vertex in a new POLY_G3 primitive
lui $s2, 0x3000 # load primitive code constant for POLY_G3
or $s3, $s2 # or with the RGB values
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0xC($t3) # store RGB values for vert 2
sw $s5, 0x14($t3) # store RGB values for vert 3
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_g3_4 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_g3_minl_4:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_g3_4 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_g3_lim_ot_offset_4:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_g3_4:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x600 # load len for the POLY_G3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_worlds_loop_test_4:
addiu i_poly_id, -1 # decrement poly_id iterator (index-based)
bnez i_poly_id transform_worlds_loop_4 # continue while nonzero
lhu $at, 0(p_poly_id) # get the next poly id
nop
transform_worlds_end_4:
lw $sp, 0x1F800034
nop
lw $at, arg_10($sp)
nop
sw prim, 0($at) # store the new prims_tail
sload
#
# translate, rotate, and perspective transform polys of the worlds in scratch memory
# and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# this variant does up to 2 interpolations of vertex colors:
# vertex colors are first interpolated depending on fx bit
# - fx bit = 0 => use far color scratch values 1-3, IR0 scratch value 4
# - fx bit = 1 => use far color scratch values 5-7, IR0 scratch value 8
#
# if a transformed vertex z is less than the far value
# the result color for that vert is then interpolated
# with far color scratch values 39-41 and IR0 = (transformed vert z - far) << amt
#
# it is used to create a darkness effect
#
RGteTransformWorldsDark:
poly_ids = $a0
ot = $a1
min_ot_offset = $v1
scratch_worlds = $t0
p_poly_id = $t2
prim = $t3
world_idx = $t4
i_poly_id = $t5
regions = $s6
polys = $s7
verts = $t8
texinfos = $t9
tmp1 = $sp
tmp2 = $fp
tmp3 = $ra
ssave
lw $t7, arg_10($sp)
lw regions, arg_14($sp)
lw $at, arg_18($sp) # load far value argument
lw $ra, arg_1C($sp) # get shamt argument
lw prim, 0($t7) # get pointer to primitive memory
li $sp, 0x1F8000E0
sw $a3, arg_0($sp) # save pointer to prims pointer (out param) in scratch memory
cfc2 $s3, $21
cfc2 $s4, $22
cfc2 $s5, $23 # $s3-$s5 = current GTE FC (far color)
sw $s3, arg_4($sp)
sw $s4, arg_8($sp)
sw $s5, arg_C($sp) # store current far color on stack
li $gp, 0xFFFFFF # load mask for selecting lower 3 bytes
li $t7, 0x60
li scratch_worlds, 0x1F800100
lw i_poly_id, 0(poly_ids) # get poly id count; start poly id iterator at end of poly id list
addiu p_poly_id, poly_ids, 2
addu p_poly_id, i_poly_id
addu p_poly_id, i_poly_id # get pointer to the current poly id
li world_idx, 0xFFFF
move $a3, $at # preserve far value argument
move $a0, $ra # preserve shamt argument
lhu $at, 0(p_poly_id) # get poly id
sll $a2, 2 # multiply far value by sizeof(void*); it will be used as an ot offset
li min_ot_offset, 0x1FFC # initialize with max ot offset
transform_worlds_loop_5:
addiu p_poly_id, -2 # decrement poly id iterator (pointer-based)
srl tmp2, $at, 12 # shift down world index bits
beq tmp2, world_idx, transform_poly_5 # skip loading world if already loaded (same world idx)
andi $at, 0xFFF # clear world index bits (poly_idx = poly_id & 0xFFF)
load_world_5:
move world_idx, tmp2 # save world index for above check in next iteration
sll tmp3, world_idx, 6 # world_idx * sizeof(gfx_world)
addu $v0, tmp3, scratch_worlds # get pointer to the world
lw tmp1, 4($v0) # get world trans x
lw tmp2, 8($v0) # get world trans y
lw tmp3, 0xC($v0) # get world trans z
ctc2 tmp1, $5 # set GTE TRX to world trans x
ctc2 tmp2, $6 # set GTE TRY to world trans y
ctc2 tmp3, $7 # set GTE TRZ to world trans z
tpages = $a3
lw polys, 0x14($v0) # get pointer to world polys
lw verts, 0x18($v0) # get pointer to world verts
lw texinfos, 0x1C($v0) # get pointer to world texinfos
transform_poly_5:
sll $at, 3 # get poly offset (poly_offset = poly_idx*sizeof(wgeo_polygon))
addu $t1, polys, $at # get pointer to poly
lw $at, 0($t1)
lw $t1, 4($t1) # get poly data
sll $v0, $at, 12 # shift up bits 1-20 of first word to bits 13-32
andi $sp, $t1, 0xFF # select rightmost byte of second word
or $v0, $sp # or the 2 values and save for further below
srl $s0, $t1, 17 # shift down leftmost 12 bits of word 2 (vert 1 idx)
andi $s0, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s0, verts # get pointer to vert 1
srl $s1, $t1, 5 # shift down bits 9-24 of word 2 (vert 2 idx)
andi $s1, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s1, verts # get pointer to vert 2
srl $s2, $at, 17 # shift down leftmost 12 bits of word 1 (vert 3 idx)
andi $s2, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s2, verts # get pointer to vert 3
lw $s3, 0($s0)
lw $s0, 4($s0)
lw $s4, 0($s1)
lw $s1, 4($s1)
lw $s5, 0($s2)
lw $s2, 4($s2) # get data for each vert (s0-s5 = v1 word2, v1 word1, v2 word2, v2 word1...)
li $t1, 0x1F800048 # get pointer to scratch values
lw $sp, 0($t1)
lw $fp, 4($t1)
lw $ra, 8($t1) # get the first 3 scratch values, an RGB far color
lwc2 $8, 0xC($1) # set GTE IR0 to the 4th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE FC (far color) to the scratch far color
andi $sp, $s0, 1 # get bit 1 of vert 1 word 2 (fx)
andi $ra, $s1, 1 # get fx bit for vert 2
sll $ra, 1 # shift up to bit 2
or $sp, $ra # or with vert 1 fx bit 1
andi $ra, $s2, 1 # get fx bit for vert 3
sll $ra, 2 # shift up to bit 3
or $sp, $ra # or with the other 2 fx bits
# sp = (v1_fx | (v2_fx << 1) | (v3_fx << 2))
li $ra, transform_poly_fx_000_2 # get start of the next code block
sll $sp, $at, 7 # multiply index calculated from fx bits by 32 instructions (128 bytes)
addu $ra, $sp # add to address of the next code block
jr $ra # jump to the corresponding 32 instruction code section
nor $fp, $gp, $zero # get mask for selecting upper byte
# ---------------------------------------------------------------------------
transform_poly_fx_000_2: # interpolate RGBs for all 3 verts with far color scratch values 1-3, IR0 scratch value 4
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
nop
cop2 0x780010 # interpolate between RGB and the far color
and $s3, $fp # select the upper byte (?) of vert 1 word 1
mfc2 $sp, $22 # get the interpolated rgb value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
and $s4, $fp # select upper byte of vert 2 word 1
mfc2 $sp, $22 # get the interpolated rgb value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated rgb value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s5, $sp # or the values
nop # results are in $s3, $s4, and $s5
nop
nop # when an fx bit is clear the corresponding vert RGB is interpolated
nop # with the far color from scratch values 1-3
nop # and IR0 from the 4th scratch value
nop # when an fx bit is set the corresponding vert RGB is interpolated
nop # with the far color from scratch values 5-7
nop # and IR0 from the 8th scratch value
nop
nop
# ---------------------------------------------------------------------------
transform_poly_fx_001_2: # interpolate RGBs for verts 2&3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGB for vert 1 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
nop
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or the values
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s3, $sp # or with the upper byte of vert 1 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_010_2:
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or the values
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s4, $sp # or with the upper byte of vert 2 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_011_2: # interpolate RGB for vert 3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGBs for verts 1&2 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
nop
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or with the upper byte of vert 3 word 1
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s4, $sp # or with the upper byte of vert 2 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_100_2: # interpolate RGBs for verts 2&3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGB for vert 1 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s4, $fp # select upper byte of vert 2 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or the values
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s5, $sp # or with the upper byte of vert 3 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_101_2: # interpolate RGB for vert 2 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGBs for verts 1&3 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
nop
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s5, $sp # or with the upper byte of vert 3 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_110_2: # interpolate RGB for vert 3 with far color scratch values 1-3, IR0 scratch value 4
# interpolate RGBs for verts 1&2 with far color scratch values 5-7, IR0 scratch value 8
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
and $s3, $fp # select upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
and $s4, $fp # select upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
and $s5, $fp # select upper byte of vert 3 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
nop
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
bgez $zero, transform_poly_5b # skip past the other 32 instruction code sections
or $s5, $sp # or with the upper byte of vert 3 word 1
# ---------------------------------------------------------------------------
transform_poly_fx_111_2: # interpolate RGBs for all verts with far color scratch values 5-7, IR0 scratch value 8
lw $sp, 0x10($t1)
lw $fp, 0x14($t1)
lw $ra, 0x18($t1) # load the far color from scratch values 5-7
lwc2 $8, 0x1C($t1) # set GTE IR0 to the 8th scratch value
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE far color to the scratch values 5-7
nor $fp, $gp, $zero # recompute mask for selecting upper byte
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
nop
nop
cop2 0x780010 # interpolate between RGB and the far color
and $s3, $fp # select upper byte of vert 1 word 1
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 1 rgb value
or $s3, $sp # or with the upper byte of vert 1 word 1
cop2 0x780010 # interpolate between RGB and the far color
and $s4, $fp # select upper byte of vert 2 word 1
mfc2 $sp, $22 # get the interpolated RGB value
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 2 rgb value
or $s4, $sp # or with the upper byte of vert 2 word 1
cop2 0x780010 # interpolate between RGB and new far color using new IR0
nop
mfc2 $sp, $22 # get the interpolated RGB value
and $s5, $fp # select upper byte of vert 3 word 1
and $sp, $gp # select lower 3 bytes (RGB) of the interpolated vert 3 rgb value
or $s5, $sp # or with the upper byte of vert 3 word 1
transform_poly_5b:
lw $sp, 0x9C($t1)
lw $fp, 0xA0($t1)
lw $ra, 0xA4($t1) # $sp-$ra = scratch values 39-41
ctc2 $sp, $21
ctc2 $fp, $22
ctc2 $ra, $23 # set GTE FC (far color) to scratch values 39-41
li $at, 0xFFF8FFF8 # load mask for selecting y and x values
and $sp, $s0, $at
and $fp, $s1, $at
and $ra, $s2, $at # use the mask to select yx values from second word of each vert
mtc2 $sp, $0
mtc2 $fp, $2
mtc2 $ra, $4 # set GTE VXY0, VXY1, VXY2
li $at, 0x70006 # load mask for selecting z values
srl $sp, $s3, 24 # (vert 1) shift down upper 8 bits of 1st word to lower 8 bits
sll $sp, 3 # and shift up to multiple of 8, to bits 11-4
and $s0, $at # use mask to select bits from second word
sll $t1, $s0, 10 # shift bits 1 and 2 up to 12 and 13
or $sp, $t1 # or with bits 11-4
srl $t1, $s0, 3 # shift bits 17-19 down to 14-16
or $sp, $t1 # final value sp is z value for vert 1
srl $fp, $s4, 24 # repeat for vert 2...
sll $fp, 3
and $s1, $at
sll $t1, $s1, 10
or $fp, $t1
srl $t1, $s1, 3
or $fp, $t1 # fp is z value for vert 2
srl $ra, $s5, 24 # and vert 3 ...
sll $ra, 3
and $s2, $at
sll $t1, $s2, 10
or $ra, $t1
srl $t1, $s2, 3
or $ra, $t1 # ra is z value for vert 3
mtc2 $sp, $1
mtc2 $fp, $3
mtc2 $ra, $5 # set GTE VZ0, VZ1, VZ2
srl $fp, $v0, 20 # shift down bits 21-32 from the or'ed values above
cop2 0x280030 # trans, rot, and perspective transform verts
sll $fp, 2 # multiply offset by 4 (it is stored divided by 4)
addu $t6, texinfos, $fp # get pointer to texinfo
lw $t1, 0($t6) # get first word of texinfo
lui $s2, 0x3400 # load code constant for POLY_GT3 primitives
srl $t1, 24
andi $sp, $t1, 0x80 # get is_textured flag from texinfo word 1
beqz $sp, create_poly_g3_5 # goto create gouraud shaded poly if non-textured
nop
create_poly_gt3_13:
and $s3, $gp # select ... values from lower 3 bytes of first word for vert 1
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
create_poly_gt3_interp2_1_1:
mfc2 $sp, $17 # get transformed z value for vert 1
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
create_poly_gt3_test_z1_ltfar:
slt $fp, $a3, $sp
beqz $fp, create_poly_gt3_interp2_2 # skip second interpolation for vert 1 if transformed z value is greater than or equal to far value
create_poly_gt3_z1_gteqfar:
subu $fp, $sp, $a3
sllv $fp, $a0
mtc2 $fp, $8 # set GTE IR0 = (transformed vert1 z - far value) << amt
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s3, $22 # get the interpolated value
create_poly_gt3_interp2_2_1:
mfc2 $ra, $18 # get transformed z value for vert 2
nop
addu $s1, $sp, $ra # add to transformed z value for vert 1
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
create_poly_gt3_test_z2_ltfar:
slt $fp, $a3, $ra
beqz $fp, create_poly_gt3_interp2_3 # skip second interpolation for vert 2 if transformed z value is greater than or equal to far value
create_poly_gt3_z2_gteqfar:
subu $fp, $ra, $a3
sllv $fp, $a0
mtc2 $fp, $8 # set GTE IR0 = (transformed vert2 z - far value) << amt
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s4, $22 # get the interpolated value
create_poly_gt3_interp2_3_1:
mfc2 $sp, $19 # get transformed z value for vert 3
nop
addu $s1, $sp # add to sum of transformed z values for vert 1 and 2
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
create_poly_gt3_test_z3_ltfar:
slt $fp, $a3, $sp
beqz $fp, create_poly_gt3_interp2_3 # skip second interpolation for vert 3 if transformed z value is greater than or equal to far value
create_poly_gt3_z3_gteqfar:
subu $fp, $sp, $a3
sllv $fp, $a0
mtc2 $fp, $8 # set GTE IR0 = (transformed vert3 z - far value) << amt
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s5, $22 # get the interpolated value
create_poly_gt3_14:
srl $sp, 5 # compute transformed z values sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
and $s3, $gp # select rgb bits for vert 1 result of second interpolation
and $fp, $t1, $t7 # select semi-transparency bits from texinfo word 1
beq $fp, $t7, create_poly_gt3_14 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
create_poly_gt3_steq3_5:
or $s3, $s2 # or the primitive code constant (with RGB values)
create_poly_gt3_stlt3_5:
lui $fp, 0x200 # load code bits for semi-trans primitives
or $s3, $fp # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_14:
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0x10($t3) # store RGB values for vert 2
sw $s5, 0x1C($t3) # store RGB values for vert 3
srl $ra, $v0, 15 # select bits 18-20 from the or'ed values above (bits 6-8 from the first word
andi $ra, 0x1C # of the poly data, index of resolved tpage), as a multiple of sizeof(uint32_t)
sll $sp, $t4, 6
addu $sp, $t0
addiu $sp, 0x20
addu $at, $ra, $sp # get pointer to resolved tpage
andi $ra, $v0, 0x1E # select bits 2-5 (?) from the or'ed values above (bits 2-5 from the second word)
beqz $ra, create_poly_gt3_15 # if zero then skip adding offsets for an animated texture
create_poly_gt3_animtex_5: # else the value is the 'animation frame index mask'
srl $sp, $v0, 5 # shift down bits 6-8 from the or'ed values above (bits 6-8 from the second word)
li $fp, 0x1F8000E0
lw $fp, 0($fp) # restore the saved anim_counter argument
andi $sp, 7 # select bits 6-8 from the or'ed values above (anim_period)
srlv $fp, $sp # shift the saved anim_counter value right by this amount
srl $sp, $v0, 12
andi $sp, 0x1F # select bits 1-5 from the or'ed values above (anim_phase)
addu $sp, $fp, $sp # add as an offset to the shifted anim_counter value
ori $fp, $ra, 1 # add 1 to the anim_mask value
and $sp, $fp # and with the anim_phase + shifted anim_counter value (*see note above)
sll $sp, 2 # multiply by sizeof(texinfo)/2
addu $t6, $sp, $t6 # add as an offset to the texinfo pointer
create_poly_gt3_15:
lw $s3, 4($t6) # get second word of texinfo
lw $s4, 0($at) # get resolved tpage (a bitfield)
srl $sp, $s3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, regions, $sp # get a pointer to the region
lw $s0, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
srl $s5, $s3, 20
andi $s5, 3 # get bits 21 and 22 from texinfo word 2 (color mode)
sll $sp, $s5, 7 # shift to bits 8 and 9
andi $fp, $s4, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $fp # or with color mode bits 8 and 9
srl $fp, $s3, 18
andi $fp, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $sp, $fp # or with color mode, tpage y index, and tpage x index
andi $fp, $t1, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $fp # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s4, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s3, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8
srlv $fp, $s5 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s5, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s0, 16 # shift down xy value for the second region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $t1, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s4, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s0, 0xFFFF # select xy value for first region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s5 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_gt3_4 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_gt3_minl_5:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_gt3_4 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_gt3_lim_ot_offset_5:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_gt3_5:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_GT3 prim
addiu prim, 0x28 # '(' # add sizeof(POLY_GT3) for next free location in primmem
bgez $zero, transform_worlds_loop_test_5 # loop
nop
create_poly_g3_5:
swc2 $12, 8($t3)
swc2 $13, 0x10($t3)
swc2 $14, 0x18($t3) # store transformed yx values for each vertex in a new POLY_G3 primitive
create_poly_g3_interp2_1:
mfc2 $sp, $17 # get transformed z value for vert 1
mtc2 $s3, $6 # set GTE RGB to vert 1 rgb value
create_poly_g3_test_z1_ltfar:
slt $fp, $a3, $sp
beqz $fp, create_poly_g3_interp2_2 # skip second interpolation for vert 1 if transformed z value is greater than or equal to far value
create_poly_g3_z1_gteqfar:
subu $fp, $sp, $a3
sllv $fp, $a0
mtc2 $fp, $8 # set GTE IR0 = (transformed vert1 z - far value) << amt
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s3, $22 # get the interpolated value
create_poly_g3_interp2_2:
mfc2 $ra, $18 # get transformed z value for vert 2
nop
addu $s1, $sp, $ra # add to transformed z value for vert 1
mtc2 $s4, $6 # set GTE RGB to vert 2 rgb value
create_poly_g3_test_z2_ltfar:
slt $fp, $a3, $ra
beqz $fp, create_poly_g3_interp2_3 # skip second interpolation for vert 2 if transformed z value is greater than or equal to far value
create_poly_g3_z2_gteqfar:
subu $fp, $ra, $a3
sllv $fp, $a0
mtc2 $fp, $8 # set GTE IR0 = (transformed vert2 z - far value) << amt
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s4, $22 # get the interpolated value
create_poly_g3_interp2_3:
mfc2 $sp, $19 # get transformed z value for vert 3
nop
addu $s1, $sp # add to sum of transformed z values for vert 1 and 2
mtc2 $s5, $6 # set GTE RGB to vert 3 rgb value
create_poly_g3_test_z3_ltfar:
slt $fp, $a3, $sp
beqz $fp, create_poly_g3_5b # skip second interpolation for vert 3 if transformed z value is greater than or equal to far value
create_poly_g3_z3_gteqfar:
subu $fp, $sp, $a3
sllv $fp, $a0
mtc2 $fp, $8 # set GTE IR0 = (transformed vert3 z - far value) << amt
nop
cop2 0x780010 # interpolate between RGB and the far color
nop
mfc2 $s5, $22 # get the interpolated value
create_poly_g3_5b:
srl $sp, 5 # compute transformed z values sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
and $s3, $gp # select rgb bits for vert 1 result of second interpolation
lui $s2, 0x3000 # load primitive code constant for POLY_G3
or $s3, $s2 # or with the RGB values
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0xC($t3) # store RGB values for vert 2
sw $s5, 0x14($t3) # store RGB values for vert 3
sub $sp, $a2, $sp # get distance of transformed z values average from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_g3_5 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_g3_minl_5:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_g3_5 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_g3_lim_ot_offset_5:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_g3_5:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x600 # load len for the POLY_G3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_worlds_loop_test_5:
addiu i_poly_id, -1 # decrement poly_id iterator (index-based)
bnez i_poly_id transform_worlds_loop_5 # continue while nonzero
lhu $at, 0(p_poly_id) # get the next poly id
nop
transform_worlds_end_5:
lw $sp, 0x1F800034
nop
lw $at, arg_10($sp)
nop
sw prim, 0($at) # store the new prims_tail
sload
#
# translate, rotate, and perspective transform polys of the worlds in scratch memory
# and populate the ot with corresponding (POLY_GT3/POLY_G3) primitives
#
# this variant interpolates vertex colors according to the following formulas:
# sum = (abs(v.x + world->trans.x - dark2_illum.x)
# + abs(v.y + world->trans.y - dark2_illum.y)
# + abs(v.z + world->trans.z - dark2_illum.z))
# sum2 = sum + (sum >> dark2_shamt_add) - (sum >> dark2_shamt_sub)
# + v.fx ? dark2_amb_fx1 : dark2_amb_fx0
# IR0 = limit(sum2,0,4096)
# RGB = v.color
# (where the interpolated RGB for a vertex is given by RGB+IR0*(FC-RGB))
#
# it is used to create a darkness effect
#
RGteTransformWorldsDark2:
poly_ids = $a0
min_ot_offset = $v1
scratch_worlds = $t0
p_poly_id = $t2
prim = $t3
world_idx = $t4
i_poly_id = $t5
polys = $s7
verts = $t8
texinfos = $t9
tmp1 = $sp
tmp2 = $fp
tmp3 = $ra
ssave
lw $t7, arg_10($sp)
lw $fp, arg_14($sp) # get regions argument
lw prim, 0($t7) # get pointer to primitive memory
lui $gp, 0x1F80 # pointer to start of scratch memory
sw $a3, 0x1F8000E0 # store a3 argument in scratch
sw $fp, 0x1F8000E4 # store regions argument in scratch
li $t7, 0x60
lw i_poly_id, 0(poly_ids) # get poly id count; start poly id iterator at end of poly id list
addiu p_poly_id, poly_ids, 2
addu p_poly_id, i_poly_id
addu p_poly_id, i_poly_id # get pointer to the current poly id
li world_idx, 0xFFFF
lhu $at, 0(p_poly_id) # get poly id
sll $a2, 2 # multiply far value by sizeof(void*); it will be used as an ot offset
li min_ot_offset, 0x1FFC # initialize with max ot offset
transform_worlds_loop_6:
addiu p_poly_id, -2 # decrement poly id iterator (pointer-based)
srl tmp2, $at, 12 # shift down world index bits
beq tmp2, world_idx, loc_80035510 # skip loading world if already loaded (same world idx)
andi $at, 0xFFF # clear world index bits (poly_idx = poly_id & 0xFFF)
load_world_6:
move world_idx, tmp2 # save world index for above check in next iteration
sll tmp3, world_idx, 6 # world_idx * sizeof(gfx_world)
li $v0, 0x1F800100
addu $v0, tmp3 # get pointer to the world
lw tmp1, 4($v0) # get world trans x
lw tmp2, 8($v0) # get world trans y
lw tmp3, 0xC($v0) # get world trans z
ctc2 tmp1, $5 # set GTE TRX to world trans x
ctc2 tmp2, $6 # set GTE TRY to world trans y
ctc2 tmp3, $7 # set GTE TRZ to world trans z
lw polys, 0x14($v0) # get pointer to world polys
lw verts, 0x18($v0) # get pointer to world verts
lw texinfos, 0x1C($v0) # get pointer to world texinfos
addiu tpages, $v0, 0x20 # get pointer to resolved world tpages
transform_poly_6:
sll $at, 3 # get poly offset (poly_offset = poly_idx*sizeof(wgeo_polygon))
addu $t1, polys, $at # get pointer to poly
lw $at, 0($t1)
lw $t1, 4($t1) # get poly data
sll $v0, $at, 12 # shift up bits 1-20 of first word to bits 13-32
andi $sp, $t1, 0xFF # select rightmost byte of second word
or $v0, $sp # or the 2 values and save for further below
srl $s0, $t1, 17 # shift down leftmost 12 bits of word 2 (vert 1 idx)
andi $s0, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s0, verts # get pointer to vert 1
srl $s1, $t1, 5 # shift down bits 9-24 of word 2 (vert 2 idx)
andi $s1, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s1, verts # get pointer to vert 2
srl $s2, $at, 17 # shift down leftmost 12 bits of word 1 (vert 3 idx)
andi $s2, 0x7FF8 # select those bits, as a multiple of sizeof(wgeo_vertex)
addu $s2, verts # get pointer to vert 3
lw $s3, 0($s0)
lw $s0, 4($s0)
lw $s4, 0($s1)
lw $s1, 4($s1)
lw $s5, 0($s2)
lw $s2, 4($s2) # get data for each vert (s0-s5 = v1 word2, v1 word1, v2 word2, v2 word1...)
li $at, 0xFFF8FFF8 # load mask for selecting y and x values
and $sp, $s0, $at
and $fp, $s1, $at
and $ra, $s2, $at # use the mask to select yx values from second word of each vert
mtc2 $sp, $0
mtc2 $fp, $2
mtc2 $ra, $4 # set GTE VXY0, VXY1, VXY2
li $t1, 0x1F800300 # get a pointer to scratch ?
sll $at, $t4, 4 # multiply world_idx by sizeof(?)
addu $t1, $at # get a pointer to the location for this world in scratch
lw $t6, 0($t1) # get x location
sll $at, $sp, 16
sra $at, 16 # select vert 1 x
addu $t6, $at # add to x location
lw $at, 0x48($gp) # get x center of illumination
nop
subu $at, $t6, $at # subtract it from sum of vert 1 x and x location
transform_poly_6_abs_v1xs:
transform_poly_6_test_v1xs_lt0:
bgez $at, transform_poly_6_v1xs_gteq0 # and get absolute value
nop
transform_poly_6_v1xs_lt0:
negu $at, $at
transform_poly_6_v1xs_gteq0:
move $a0, $at # save the result (i.e. abs(v1->x + world->trans.x - dark2_illum.x))
lw $t6, 4($t1) # get second word of structure
sra $at, $sp, 16 # select vert 1 y
addu $t6, $at # add to second word of structure
lw $at, 0x4C($gp) # get blue value for far_color1
nop
subu $at, $t6, $at # subtract it from sum of vert 1 y and structure second word
transform_poly_6_abs_v1ys:
transform_poly_6_test_v1ys_lt0
bgez $at, transform_poly_6_v1ys_gteq0 # and get absolute value
nop
transform_poly_6_v1ys_lt0:
negu $at, $at
transform_poly_6_v1ys_gteq0:
addu $a0, $at # add the result to result for v1->x
# i.e. $a0 = abs(v1->x + world->trans.x - dark2_illum.x)
# + abs(v1->y + world->trans.y - dark2_illum.y)
lw $t6, 0($t1) # get first word of structure
sll $at, $fp, 16
sra $at, 16 # select vert 2 x
addu $t6, $at # add to first word of structure
lw $at, 0x48($gp) # get green value for far_color1
nop
subu $at, $t6, $at # subtract it from sum of vert 2 x and structure first word
transform_poly_6_abs_v2xs:
transform_poly_6_test_v2xs_lt0:
bgez $at, transform_poly_6_v2xs_gteq0 # and get absolute value
nop
transform_poly_6_v2xs_lt0:
negu $at, $at
transform_poly_6_v2xs_gteq0:
move $t0, $at # save the result (i.e. abs(v2->x + world->trans.x - dark2_illum.x))
lw $t6, 4($t1) # get second word of structure
sra $at, $fp, 16 # select vert 2 y
addu $t6, $at # add to second word of structure
lw $at, 0x4C($gp) # get blue value for far_color1
nop
subu $at, $t6, $at # subtract it from sum of vert 2 y and structure second word
transform_poly_6_abs_v2ys:
transform_poly_6_test_v2ys_lt0:
bgez $at, transform_poly_6_v2ys_gteq0 # and get absolute value
nop
transform_poly_6_v2ys_lt0:
negu $at, $at
transform_poly_6_v2ys_gteq0:
addu $t0, $at # add the result to result for v2->x
# i.e. $t0 = abs(v2->x + world->trans.x - dark2_illum.x)
# + abs(v2->y + world->trans.y - dark2_illum.y)
lw $t6, 0($t1) # get first word of structure
sll $at, $ra, 16
sra $at, 16 # select vert 3 x
addu $t6, $at # add to first word of structure
lw $at, 0x48($gp) # get green value for far_color1
nop
subu $at, $t6, $at # subtract it from sum of vert 3 x and structure first word
transform_poly_6_abs_v3xs:
transform_poly_6_test_v3xs_lt0
bgez $at, transform_poly_6_v3xs_gteq0 # and get absolute value
nop
transform_poly_6_v3xs_lt0:
negu $at, $at
transform_poly_6_v3xs_gteq0:
move $s6, $at # save the result (i.e. abs(v3->x + world->trans.x - dark2_illum.x))
lw $t6, 4($t1) # get second word of structure
sra $at, $ra, 16 # select vert 3 y
addu $t6, $at # add to second word of structure
lw $at, 0x4C($gp) # get blue value for far_color1
nop
subu $at, $t6, $at # subtract it from sum of vert 3 y and structure second word
transform_poly_6_abs_v3ys:
transform_poly_6_test_v3ys_lt0:
bgez $at, transform_poly_6_v3ys_gteq0 # and get absolute value
nop
transform_poly_6_v3ys_lt0:
negu $at, $at
transform_poly_6_v3ys_gteq0:
addu $s6, $at # add the result to result for v3->x
# i.e. $t0 = abs(v3->x + world->trans.x - dark2_illum.x)
# + abs(v3->y + world->trans.y - dark2_illum.y)
li $at, 0x70006 # load mask for selecting z values
srl $sp, $s3, 24 # (vert 1) shift down upper 8 bits of 1st word to lower 8 bits
sll $sp, 3 # and shift up to multiple of 8, to bits 11-4
and $s0, $at # use mask to select bits from second word
sll $t1, $s0, 10 # shift bits 1 and 2 up to 12 and 13
or $sp, $t1 # or with bits 11-4
srl $t1, $s0, 3 # shift bits 17-19 down to 14-16
or $sp, $t1 # final value sp is z value for vert 1
srl $fp, $s4, 24 # repeat for vert 2...
sll $fp, 3
and $s1, $at
sll $t1, $s1, 10
or $fp, $t1
srl $t1, $s1, 3
or $fp, $t1 # fp is z value for vert 2
srl $ra, $s5, 24 # and vert 3 ...
sll $ra, 3
and $s2, $at
sll $t1, $s2, 10
or $ra, $t1
srl $t1, $s2, 3
or $ra, $t1 # ra is z value for vert 3
mtc2 $sp, $1
mtc2 $fp, $3
mtc2 $ra, $5 # set GTE VZ0, VZ1, VZ2
li $t1, 0x1F800300 # get pointer to scratch ?
sll $at, $t4, 4 # multiply world_idx by sizeof(?)
addu $t1, $at # recompute pointer to the 16 byte structure? for this world in scratch
lw $t6, 8($t1) # get third word of structure
sll $at, $sp, 16
sra $at, 16 # select vert 1 z
addu $t6, $at # add to third word of structure
lw $at, 0x50($gp) # get t1 value global
nop
subu $at, $t6, $at # subtract it from sum of vert 1 z and structure third word
transform_poly_6_abs_v1zs:
transform_poly_6_test_v1zs_lt0:
bgez $at, transform_poly_6_v1zs_gteq0 # and get absolute value
nop
transform_poly_6_v1zs_lt0:
negu $at, $at
transform_poly_6_v1zs_gteq0:
addu $a0, $at # add the result to result for v1
# i.e. sum1 = abs(v1->x + world->trans.x - dark2_illum.x)
# + abs(v1->y + world->trans.y - dark2_illum.y)
# + abs(v1->z + world->trans.z - dark2_illum.z)
lw $t6, 0x54($gp) # load dark2_shamt_add
lw $at, 0x58($gp) # load dark2_shamt_sub
srlv $sp, $a0, $t6
addu $t6, $a0, $sp # set $t6 = sum1+(sum1>>dark2_shamt_add)
srlv $sp, $a0, $at
subu $a0, $t6, $sp # set $a0 = sum1+(sum1>>dark2_shamt_add)-(sum1>>dark2_shamt_sub)
transform_poly_test_v1fx_3:
andi $at, $s0, 1 # select bit 1 of vert 1 word 2 (fx bit)
beqz $at, transform_poly_v1fx_false_3 # if false then load dark2_amb_fx_0
lw $t6, 0x5C($gp)
nop
transform_poly_v1fx_true_3:
lw $t6, 0x60($gp) # else load dark2_amb_fx_1
transform_poly_v1fx_false_3:
nop
addu $a0, $t6 # set $a0 = sum1+(sum1>>dark2_shamt_add)-(sum1>>dark2_shamt_sub)+[dark2_amb_fx0 or dark2_amb_fx1]
transform_poly_v1fx_test_sum_lt4096:
slti $sp, $a0, 0x1000
bnez $sp, transform_poly_v1fx_sum_lt4096 # skip upper limiting if sum is less than 4096
nop
transform_poly_v1fx_sum_gteq4096:
bgez $zero, loc_80037934 # skip lower limiting
li $a0, 0xFFF # upper limit at 4095
transform_poly_v1fx_sum_lt4096:
transform_poly_v1fx_test_sum_gteq0:
bgez $a0, loc_80037934 # skip lower limiting if sum is greater than or equal to 0
nop
transform_poly_v1fx_sum_lt0:
move $a0, $zero # lower limit at 0
transform_poly_v1fx:
mtc2 $a0, $8 # set GTE IR0 = limit(sum1+(sum1>>dark2_shamt_add)-(sum1>>dark2_shamt_sub)+[dark2_amb_fx0 or dark2_amb_fx1],0,4095)
mtc2 $s3, $6 # set GTE RGB = vert 1 rgb
nop
nop
cop2 0x780010 # interpolate between RGB and the far color (for t = IR0)
nop
nop
mfc2 $s3, $22 # get the interpolated value
lw $t6, 8($t1) # get world trans z
sll $at, $fp, 16
sra $at, 16 # select vert 2 z
addu $t6, $at # add to world trans z
lw $at, 0x50($gp) # get center of illum z
nop
subu $at, $t6, $at # subtract it from sum of vert 2 z and world trans z
transform_poly_6_abs_v2zs:
transform_poly_6_test_v2zs_lt0
bgez $at, transform_poly_6_v2zs_gteq0 # and get absolute value
nop
transform_poly_6_v2zs_lt0:
negu $at, $at
transform_poly_6_v2zs_gteq0:
addu $t0, $at # add the result to result for v2
# i.e. sum2 = abs(v2->x + world->trans.x - dark2_illum.x)
# + abs(v2->y + world->trans.y - dark2_illum.y)
# + abs(v2->z + world->trans.z - dark2_illum.z)
lw $t6, 0x54($gp) # load dark2_shamt_add
lw $at, 0x58($gp) # load dark2_shamt_sub
srlv $sp, $t0, $t6
addu $t6, $t0, $sp # set $t6 = sum2+(sum2>>dark2_shamt_add)
srlv $sp, $t0, $at
subu $t0, $t6, $sp # set $t0 = sum2+(sum2>>dark2_shamt_add)-(sum2>>dark2_shamt_sub)
transform_poly_test_v2fx_3:
andi $at, $s1, 1 # select bit 1 of vert 2 word 2 (fx bit)
beqz $at, transform_poly_v2fx_false_3 # if false then load dark2_amb_fx0
lw $t6, 0x5C($gp)
nop
transform_poly_v2fx_true_3:
lw $t6, 0x60($gp) # else load dark2_amb_fx1
transform_poly_v2fx_false_3:
nop
addu $t0, $t6 # set $t0 = sum2+(sum2>>dark2_shamt_add)-(sum2>>dark2_shamt_sub)+[dark2_amb_fx0 or dark2_amb_fx1]
transform_poly_v2fx_test_sum_lt4096:
slti $sp, $t0, 0x1000
bnez $sp, transform_poly_v2fx_sum_lt4096 # skip upper limiting if sum is less than 4096
nop
transform_poly_v2fx_sum_gteq4096:
bgez $zero, transform_poly_v2fx # skip lower limiting
li $t0, 0xFFF # upper limit at 4095
transform_poly_v2fx_sum_lt4096:
transform_poly_v2fx_test_sum_gteq0:
bgez $t0, transform_poly_v2fx # skip lower limiting if sum is greater than or equal to 0
nop
transform_poly_v2fx_sum_lt0:
move $t0, $zero # lower limit at 0
transform_poly_v2fx:
mtc2 $t0, $8 # set GTE IR0 = limit(sum2+(sum2>>dark2_shamt_add)-(sum2>>dark2_shamt_sub)+[dark2_amb_fx0 or dark2_amb_fx1],0,4095)
mtc2 $s4, $6 # set GTE RGB = vert 2 rgb
nop
nop
cop2 0x780010 # interpolate between RGB and the far color (for t = IR0)
nop
nop
mfc2 $s4, $22 # get the interpolated value
lw $t6, 8($t1) # get third word of structure
sll $at, $ra, 16
sra $at, 16 # select vert 3 z
addu $t6, $at # add to third word of structure
lw $at, 0x50($gp) # get t1 value global
nop
subu $at, $t6, $at # subtract it from sum of vert 3 z and structure third word
transform_poly_6_abs_v3zs:
transform_poly_6_test_v3zs_lt0
bgez $at, transform_poly_6_v3zs_gteq0 # and get absolute value
nop
transform_poly_6_v3zs_lt0:
negu $at, $at
transform_poly_6_v3zs_gteq0:
addu $s6, $at # add the result to result for v3
# i.e. sum3 = abs(v3->x + world->trans.x - dark2_illum.x)
# + abs(v3->y + world->trans.y - dark2_illum.y)
# + abs(v3->z + world->trans.z - dark2_illum.z)
lw $t6, 0x54($gp) # load dark2_shamt_add
lw $at, 0x58($gp) # load dark2_shamt_sub
srlv $sp, $s6, $t6
addu $t6, $s6, $sp # set $t6 = sum3+(sum3>>dark2_shamt_add)
srlv $sp, $s6, $at
subu $s6, $t6, $sp # set $s6 = sum3+(sum3>>dark2_shamt_add)-(sum3>>dark2_shamt_sub)
transform_poly_test_v3fx_3:
andi $at, $s1, 1 # select bit 1 of vert 2 word 2 (fx bit)
beqz $at, transform_poly_v3fx_false_3 # if false then load dark2_amb_fx0
lw $t6, 0x5C($gp)
nop
transform_poly_v3fx_true_3:
lw $t6, 0x60($gp) # else load dark2_amb_fx1
transform_poly_v3fx_false_3:
nop
addu $s6, $t6 # set $s6 = sum3+(sum3>>dark2_shamt_add)-(sum3>>dark2_shamt_sub)+[dark2_amb_fx0 or dark2_amb_fx1]
transform_poly_v3fx_test_sum_lt4096:
slti $sp, $s6, 0x1000
bnez $sp, transform_poly_v3fx_sum_lt4096 # skip upper limiting if sum is less than 4096
nop
transform_poly_v3fx_sum_gteq4096:
bgez $zero, transform_poly_v3fx # skip lower limiting
li $s6, 0xFFF # upper limit at 4095
transform_poly_v3fx_sum_lt4096:
transform_poly_v3fx_test_sum_gteq0:
bgez $s6, transform_poly_v3fx # skip lower limiting if sum is greater than or equal to 0
nop
transform_poly_v3fx_sum_lt0:
move $s6, $zero # lower limit at 0
transform_poly_v3fx:
mtc2 $s6, $8 # set GTE IR0 = limit(sum3+(sum3>>dark2_shamt_add)-(sum3>>dark2_shamt_sub)+[dark2_amb_fx0 or dark2_amb_fx1],0,4095)
mtc2 $s5, $6 # set GTE RGB = vert 2 rgb
nop
nop
cop2 0x780010 # interpolate between RGB and the far color (for t = IR0)
nop
nop
mfc2 $s5, $22 # get the interpolated value
srl $fp, $v0, 20 # shift down bits 21-32 from the or'ed values above
# # ...these are bits 9-20 from the first word of the poly data (texinfo/rgbinfo offset divided by 4)
cop2 0x280030 # trans, rot, and perspective transform verts
sll $fp, 2 # multiply offset by 4 (it is stored divided by 4)
addu $t6, texinfos, $fp # get pointer to texinfo
lw $t1, 0($t6) # get first word of texinfo
lui $s2, 0x3400 # load code constant for POLY_GT3 primitives
srl $t1, 24
li $fp, 0xFFFFFF # load mask for selecting lower 3 bytes
andi $sp, $t1, 0x80 # get is_textured flag from texinfo word 1
beqz $sp, create_poly_g3_6 # goto create gouraud shaded poly if non-textured
create_poly_gt3_16:
and $s3, $gp # select rgb value for vert 1 from lower 3 bytes of interpolation result
swc2 $12, 8(prim)
swc2 $13, 0x14(prim)
swc2 $14, 0x20(prim) # store transformed yx values for each vertex in a new POLY_GT3 primitive
and $fp, $t1, $t7 # select semi-transparency bits from texinfo word 1
beq $fp, $t7, create_poly_gt3_17 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
create_poly_gt3_steq3_6:
or $s3, $s2 # or the primitive code constant (with RGB values)
create_poly_gt3_stlt3_6:
or $s3, $ra # set code bits for a semi-trans primitive if semi-trans bits < 3
create_poly_gt3_17:
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0x10($t3) # store RGB values for vert 2
sw $s5, 0x1C($t3) # store RGB values for vert 3
srl $ra, $v0, 15 # select bits 18-20 from the or'ed values above (bits 6-8 from the first word
andi $ra, 0x1C # of the poly data, index of resolved tpage), as a multiple of sizeof(uint32_t)
addu $at, $ra, tpages # get pointer to resolved tpage
andi $ra, $v0, 0x1E # select bits 2-5 (?) from the or'ed values above (bits 2-5 from the second word)
beqz $ra, create_poly_gt3_18 # if zero then skip adding offsets for an animated texture
create_poly_gt3_animtex_6: # else the value is the 'animation frame index mask'
srl $sp, $v0, 5 # shift down bits 6-8 from the or'ed values above (bits 6-8 from the second word)
li $fp, 0x1F8000E0
lw $fp, 0($fp) # restore the saved anim_counter argument
andi $sp, 7 # select bits 6-8 from the or'ed values above (anim_period)
srlv $fp, $sp # shift the saved anim_counter value right by this amount
srl $sp, $v0, 12
andi $sp, 0x1F # select bits 1-5 from the or'ed values above (anim_phase)
addu $sp, $fp, $sp # add as an offset to the shifted anim_counter value
ori $fp, $ra, 1 # add 1 to the anim_mask value
and $sp, $fp # and with the anim_phase + shifted anim_counter value (*see note above)
sll $sp, 2 # multiply by sizeof(texinfo)/2
addu $t6, $sp, $t6 # add as an offset to the texinfo pointer
create_poly_gt3_18:
lw $s3, 4($t6) # get second word of texinfo
lw $s4, 0($at) # get resolved tpage (a bitfield)
lw $fp, 0xE4($gp) # restore regions pointer from scratch memory
srl $sp, $s3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $sp, 3 # multiply index by sizeof(quad8)
addu $t6, $fp, $sp # get a pointer to the region
lw $s0, 0($t6) # get xy for first and second region points
lhu $t6, 4($t6) # get xy for third region point (fourth is unused for a 3 point polygon)
srl $s5, $s3, 20
andi $s5, 3 # get bits 21 and 22 from texinfo word 2 (color mode)
sll $sp, $s5, 7 # shift to bits 8 and 9
andi $fp, $s4, 0x1C # get bits 3 and 4-5 from resolved tpage (tpage y index, tpage x index)
or $sp, $fp # or with color mode bits 8 and 9
srl $fp, $s3, 18
andi $fp, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $sp, $fp # or with color mode, tpage y index, and tpage x index
andi $fp, $t1, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $sp, $fp # or with color mode, tpage y index, tpage x index, and segment
sll $sp, 16 # shift or'ed values to the upper halfword
andi $fp, $s3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $fp, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $ra, $s4, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $fp, $ra # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $ra, $fp, 8 # shift y_offs to upper byte of lower halfword
srl $fp, $s3, 10
andi $fp, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8 (the value is stored / 8)
srlv $fp, $s5 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $s5, $fp, $ra # or with the value with y_offs in upper byte
srl $fp, $s0, 16 # shift down xy value for the second region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $ra, $sp, $fp # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $sp, $t1, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $fp, $s3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $sp, $fp # or the values
srl $fp, $s4, 4
andi $fp, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $sp, $fp # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $sp, 16 # shift clut id to upper halfword
andi $fp, $s0, 0xFFFF # select xy value for first region point
addu $fp, $s5 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $fp, $sp, $fp # or with the value with clut id in upper halfword
addu $t6, $s5 # add xy value for the third region point to the or'ed x_offs/y_offs value
sw $fp, 0xC(prim) # store clut id and uv for vert 1 in the POLY_GT3 prim
sw $ra, 0x18(prim) # store tpage id and uv for vert 2 in the POLY_GT3 prim
sh $t6, 0x24(prim) # store uv for vert 3 in the POLY_GT3 prim
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $sp, 5 # compute sum over 32 (average over 10.666); this is an index
sll $sp, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_gt3_6 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_gt3_minl_6:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_gt3_6 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_gt3_lim_ot_offset_6:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_gt3_6:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x900 # load len for the POLY_GT3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_GT3 prim
addiu prim, 0x28 # '(' # add sizeof(POLY_GT3) for next free location in primmem
bgez $zero, transform_worlds_loop_test_6 # loop
nop
create_poly_g3_2:
swc2 $12, 8($t3)
swc2 $13, 0x10($t3)
swc2 $14, 0x18($t3) # store transformed yx values for each vertex in a new POLY_G3 primitive
lui $s2, 0x3000 # load primitive code constant for POLY_G3
or $s3, $s2 # or with the RGB value for vert 1
and $s3, $gp
sw $s3, 4($t3) # store primitive code and RGB values for vert 1
sw $s4, 0xC($t3) # store RGB values for vert 2
sw $s5, 0x14($t3) # store RGB values for vert 3
mfc2 $sp, $17
mfc2 $fp, $18
mfc2 $ra, $19 # get calculated vert z values from transformation
addu $sp, $fp
addu $sp, $ra
srl $s1, 5 # compute sum of z values over 32 (average over 10.666); this is an index
srl $s1, 2 # multiply by sizeof(void*)
sub $sp, $a2, $sp # get distance of z value average/ot offset from far value offset
andi $sp, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $fp, $sp, min_ot_offset
beqz $fp, add_poly_g3_2 # skip below 2 blocks if no less than the min ot offset seen thus far
addu $t6, $a1, min_ot_offset # get pointer to ot entry at minimum offset
add_poly_g3_minl_6:
move min_ot_offset, $sp # record as new minimum ot offset
bgez min_ot_offset, add_poly_g3_6 # skip limiting to 0 if already greater than or equal to
addu $t6, $a1, min_ot_offset # get pointer to ot entry at new minimum offset
add_poly_g3_lim_ot_offset_6:
move min_ot_offset, $zero # limit to 0
addu $t6, $a1, min_ot_offset # get pointer to ot entry at limited minimum offset
add_poly_g3_6:
lw $sp, 0($t6) # get ot entry currently at min offset
and $fp, prim, $gp # select lower 3 bytes of prim pointer
sw $fp, 0($t6) # replace entry at min offset with the selected bytes
lui $ra, 0x600 # load len for the POLY_G3
or $sp, $ra # or with the replaced entry (thereby forming a link)
sw $sp, 0($t3) # store it as the tag for the POLY_G3 prim
addiu prim, 0x1C # add sizeof(POLY_G3) for next free location in primmem
transform_worlds_loop_test_6:
addiu i_poly_id, -1 # decrement poly_id iterator (index-based)
bnez i_poly_id transform_worlds_loop_6 # continue while nonzero
lhu $at, 0(p_poly_id) # get the next poly id
nop
transform_worlds_end_6:
lw $sp, 0x1F800034
nop
lw $at, arg_10($sp)
nop
sw prim, 0($at) # store the new prims_tail
sload
jr $ra
nop
#
# query the octree of a zone
#
# a0 (in, zone_dimensions*) = zone dimensions item
# a1 (in, bound*) = test bound
# a2 (in, zone_query*) = query (incl results)
#
# returns the number of query results
#
RZoneQueryOctree:
query = $a2
level = $fp
zone_w = $s0
zone_h = $s1
zone_d = $s2
rect_w = $s0
rect_h = $s1
rect_d = $s2
rect_x = $t5
rect_y = $t6
rect_z = $t7
nodes_w = $t2
nodes_h = $t3
nodes_d = $t4
max_depth_x = $s3
max_depth_y = $s4
max_depth_z = $s5
ssave
lw $s6, 0($a1)
lw $t0, 4($a1)
lw $t1, 8($a1) # $s6,$t0,$t1 = bound.p1
lw $t2, 0xC($a1)
lw $t3, 0x10($a1)
lw $t4, 0x14($a1) # $t2-$t4 = bound.p2
lw rect_x, 0($a0)
lw rect_y, 4($a0)
lw rect_z, 8($a0) # rect.loc = dim.loc
lw zone_w, 0xC($a0)
lw zone_h, 0x10($a0)
lw zone_d, 0x14($a0) # zone_rect.dim = dim.dim
lhu $v1, 0x1C($a0) # $v1 = dim.octree.root
lhu max_depth_x, 0x1E($a0) # max_depth_x = dim.octree.max_depth_x
lhu max_depth_y, 0x20($a0) # max_depth_y = dim.octree.max_depth_y
lhu max_depth_z, 0x22($a0) # max_depth_z = dim.octree.max_depth_z
sh $zero, 0(query)
sh zone_w, 2(query) # query->result_rect.w = dim.dim.w
sh zone_h, 4(query) # query->result_rect.h = dim.dim.h
sh zone_d, 6(query) # query->result_rect.d = dim.dim.d
addiu $a2, 8
sh $zero, 0(query)
sh max_depth_x, 2(query) # query->result_rect.max_depth_x = max_depth_x
sh max_depth_y, 4(query) # query->result_rect.max_depth_y = max_depth_y
sh max_depth_z, 6(query) # query->result_rect.max_depth_z = max_depth_z
addiu $a2, 8
sll rect_x, 8
sll rect_y, 8
sll rect_z, 8 # rect.loc = dim.loc << 8 (dim.loc as 12 bit fractional fixed point)
sll rect_w, 8
sll rect_h, 8
sll rect_d, 8 # rect.dim = dim.dim << 8 (dim.dim as 12 bit fractional fixed point)
subu rect_x, $s6
subu rect_y, $t0
subu rect_z, $t1 # rect.loc = (dim.loc >> 8) - bound.p1 [(0,0) is the upper left of the zone, positive values = outside, negative values = inside]
subu nodes_w, $s6
subu nodes_h, $t0
subu nodes_d, $t1 # nodes_dim = bound.p2 - bound.p1
addiu result_count, 2 # first 2 words
bgez $zero, query_octree_test
move level, $zero # start at level 0
query_octree_ret:
move $v0, $a3 # return count of query results
sload
jr $ra
nop
# ---------------------------------------------------------------------------
query_octree_test:
query_octree_test_empty:
move $ra, $v1
andi $a1, $ra, 0xFFFF # $a1 = dim.octree.root & 0xFFFF
beqz $a1, query_octree_empty # if node is 0 then empty; goto empty
query_octree_test_leaf:
andi $at, $a1, 1 # test bit 1
bnez $at, query_octree_leaf # if set then node is leaf; goto leaf case
query_octree_nonleaf:
slt $v0, level, max_depth_x # $v0 = level < max_depth_x
slt $v1, level, max_depth_y
sll $v1, 1 # $v1 = (level < max_depth_y)<<1
or $v0, $v1 # $v0 = ((level < max_depth_y) << 1) | (level < max_depth_x)
slt $v1, level, max_depth_z
sll $v1, 2 # $v1 = ((level < max_depth_z) << 2)
or $v0, $v1 # $v0 = ((level < max_depth_z) << 2) | ((level < max_depth_y) << 1) | (level < max_depth_x)
addiu $v0, -1 # map values 1-8 => 0-7 ($v0 cannot be 0 before this line)
li $at, query_octree_jumptable
sll $v0, 3 # multiply index $v0 by 8 bytes, (i.e. 2 instructions)
addu $at, $v0 # add to jumptable start address to get pointer to corresponding branch instruction
jr $at # jump to the branch instruction
addu $a1, $a0 # add nonleaf node value to zone dim item pointer to get pointer to node's children
# ---------------------------------------------------------------------------
query_octree_nonleaf_jumptable:
bgez $zero, query_octree_nonleaf_001
nop
bgez $zero, query_octree_nonleaf_010
nop
bgez $zero, query_octree_nonleaf_011
nop
bgez $zero, query_octree_nonleaf_100
nop
bgez $zero, query_octree_nonleaf_101
nop
bgez $zero, query_octree_nonleaf_110
nop
bgez $zero, query_octree_nonleaf_111
nop
query_octree_ret_prev:
query_octree_empty:
li $v0, query_octree_empty_jumptable_1
sll $at, level, 3 # multiply level by 8 bytes, (i.e. 2 instructions)
addu $v0, $at # add to jumptable start address to get pointer to corresponding branch instruction
srl $at, $ra, 24 # shift down upper byte of $ra to restore previous iterator value, multiplied by 8
jr $v0 # jump to the branch instruction
addiu level, -1 # subtract 1 from the level [of recursion], as the current level is being exited
query_octree_empty_jumptable_1:
bgez $zero, query_octree_ret # return
nop
bgez $zero, query_octree_empty_2
move $ra, $s7 # restore parent iterator and node at level 1
bgez $zero, query_octree_empty_2
move $ra, $t8 # restore parent iterator and node at level 2
bgez $zero, query_octree_empty_2
move $ra, $t9 # restore parent iterator and node at level 3
bgez $zero, query_octree_empty_2
move $ra, $gp # restore parent iterator and node at level 4
bgez $zero, query_octree_empty_2
move $ra, $sp # restore parent iterator and node at level 5
bgez $zero, query_octree_empty_2
move $ra, $s6 # restore parent iterator and node at level 6
move $ra, $t0 # restore parent iterator and node at level 7
query_octree_empty_2:
li $v0, query_octree_empty_jumptable_2
addu $at, $v0 # add restored iterator value multiplied by 8 bytes/2 instructions to below
# jumptable start address to get a pointer to the branch instruction
# which will restore control to the next test in succession to
# the one for the previous iterator value
jr $at # ...and jump
andi $a1, $ra, 0xFFFF # ensure that only the lower hword of the node is selected (node is only hword in size)
# ---------------------------------------------------------------------------
query_octree_empty_jumptable_2:
bgez $zero, query_octree_nonleaf_test_2_001
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_001_end
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_4_010
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_010_end
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_6_100
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_100_end
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_8_011
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_8_011
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_9_011
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_10_011
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_12_101
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_12_101
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_13_101
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_14_101
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_16_110
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_16_110
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_17_110
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_18_110
addu $a1, $a0
bgez $zero, query_octree_nonleaf_test_20_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_20_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_21_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_22_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_23_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_24_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_25_111
addu $a1, $a0
bgez $zero, query_octree_nonleaf_res_26_111
addu $a1, $a0
query_octree_recurse:
li $at, query_octree_recurse_jumptable
sll $v0, level, 3 # calculate offset of instructions which will save parent iterator and node
# for current level and jump to next level
addu $at, $v0 # get pointer to the instructions
jr $at # jump
addiu level, 1 # increment level
# ---------------------------------------------------------------------------
query_octree_recurse_jumptable:
bgez $zero, query_octree_test # query at next level
move $s7, $ra # save parent iterator and node for level 0
bgez $zero, query_octree_test # ...
move $t8, $ra # save parent iterator and node for level 1
bgez $zero, query_octree_test # ...
move $t9, $ra # save parent iterator and node for level 2
bgez $zero, query_octree_test # ...
move $gp, $ra # save parent iterator and node for level 3
bgez $zero, query_octree_test # ...
move $sp, $ra # save parent iterator and node for level 4
bgez $zero, query_octree_test
move $s6, $ra # save parent iterator and node for level 5
bgez $zero, query_octree_test
move $t0, $ra # save parent iterator and node for level 6
query_octree_recurse_limit:
break 1 # break at level 7
bgez $zero, query_octree_recurse_limit
query_octree_nonleaf_001: # rect = relative rect of the current bound from the test bound
query_octree_nonleaf_test_1_001: # change current rect to rect for left child
srl rect_w, 1 # halve the width
addu $at, rect_w, rect_x # get x location of the right face (i.e. mid-plane of the now parent rect)
slt $at, $zero
bnez $at, query_octree_nonleaf_test_2_001: # if negative, left face of test bound (and test bound itself),
# cannot intersect with current (left) rect; so skip recursion in left half
query_octree_nonleaf_1_001: # else recurse in left half:
li $v1, 0 # set current iterator value * 8 (this is test 1-1=0, 0*8=0)
lhu $at, 0($a1) # get left child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_2_001:
addu rect_x, rect_w # change current rect to rect for right child;
slt $at, nodes_w, rect_x # compare x location of left face with width of test bound
bnez $at, query_octree_nonleaf_001_end # if greater than width of test bound, right face of test bound (and test bound itself),
# cannot intersect with current (right) rect; so skip recursion in right half
query_octree_nonleaf_2_001: # else recurse in right half:
lui $v1, 0x800 # set current iterator value * 8 (this is test 2-1=1, 1*8=8)
lhu $at, 2($a1) # get right child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_001_end:
subu rect_x, rect_w # restore parent rect location
bgez $zero, query_octree_ret_prev # return to previous level
sll rect_w, 1 # restore parent rect dimensions
query_octree_nonleaf_010:
query_octree_nonleaf_test_3_010:
srl rect_h, 1 # change current rect to rect for top child; halve the height
addu $at, rect_y, rect_h # get y location of bottom face (i.e. mid-plane of the now parent rect)
slt $at, $zero
bnez $at, query_octree_nonleaf_test_4_010 # if negative, top face of test bound (and test bound itself),
# cannot intersect with current (top) rect; so skip recursion in top half
query_octree_nonleaf_3_010: # else recurse in top half:
lui $v1, 0x1000 # set current iterator value * 8 (this is test 3-1=2, 2*8=0x10)
lhu $at, 0($a1) # get top child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_4_010:
addu rect_y, rect_h # change current rect to rect for bottom child
slt $at, nodes_h, $t6 # compare y location of top face with height of test bound
bnez $at, query_octree_nonleaf_010_end # if greater than height of test bound, bottom face of test bound (and test bound itself),
# cannot intersect with current (bottom) rect; so skip recursion in bottom half
query_octree_nonleaf_4_010: # else recurse in bottom half:
lui $v1, 0x1800 # set current iterator value * 8 (this is test 4-1=3, 3*8=0x18)
lhu $at, 2($a1) # get bottom child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_010_end:
subu rect_y, rect_h # restore parent rect location
bgez $zero, loc_80037F0C # return to previous level
sll rect_h, 1 # restore parent rect dimensions
query_octree_nonleaf_100:
query_octree_nonleaf_test_5_100:
srl rect_d, 1 # change current rect to rect for front child; halve the depth
addu $at, rect_z, rect_d # get z location of back face (i.e. mid-plane of the now parent rect)
slt $at, $zero
bnez $at, query_octree_nonleaf_test_6_100 # if negative, front face of test bound (and test bound itself),
# cannot intersect with current (front) rect; so skip recursion in front half
query_octree_nonleaf_5_100: # else recurse in front half:
lui $v1, 0x2000 # set current iterator value * 8 (this is test 5-1=4, 4*8=0x20)
lhu $at, 0($a1) # get front child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_6_100:
addu rect_z, rect_d # change current rect to rect for back child
slt $at, nodes_d, rect_z # compare z location of front face with depth of test bound
bnez $at, query_octree_nonleaf_100_end # if greater than depth of test bound, back face of test bound (and test bound itself),
# cannot intersect with current (back) rect; so skip recursion in back half
query_octree_nonleaf_6_100: # else recurse in back half:
lui $v1, 0x2800 # set current iterator value * 8 (this is test 6-1=5, 5*8=0x28)
lhu $at, 2($a1) # get back child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_100_end:
subu rect_z, rect_d # restore parent rect location
bgez $zero, loc_80037F0C # return to previous level
sll rect_d, 1 # restore parent rect dimensions
query_octree_nonleaf_011:
query_octree_nonleaf_test_l_011:
srl rect_w, 1
srl rect_h, 1 # change cur rect to rect for upper-left child; halve width and height
addu $at, rect_x, rect_w # get x location of mid-yz-plane of parent rect
slt $v0, $at, $zero
bnez $v0, query_octree_nonleaf_test_r_011 # if negative, left face of test bound (and test bound itself)
# cannot intersect with left half of parent rect; so skip the next block
slt $at, nodes_w, $at # (also compare x loc of mid-yz-plane of parent rect with width of test bound)
query_octree_nonleaf_l_011: # else set a bit indicating potential intersection with left half of parent rect
lui $v1, 1
or $ra, $v1
query_octree_nonleaf_test_r_011:
bnez $at, query_octree_nonleaf_test_9_011 # if x loc of mid-yz-plane of parent rect greater than width of test bound,
# right face of test bound (and test bound itself)
# cannot intersect with right half of parent rect; so skip the next block
addu $at, rect_y, rect_h # (also get y location of mid-xz-plane of parent rect)
query_octree_nonleaf_r_011: # else set a bit indicating potential intersection with right half of parent rect
lui $v1, 2
or $ra, $v1
query_octree_nonleaf_test_t_011:
slt $v0, $at, $zero # test location of mid-yz-plane of parent rect
bnez $v0, query_octree_nonleaf_test_b_011 # if negative, bottom face of test bound (and test bound itself)
# cannot intersect with bottom half of parent rect; so skip the next block
slt $at, nodes_h, $at # (also compare y loc of mid-xz-plane of parent rect with height of test bound)
query_octree_nonleaf_t_011: # else set a bit indicating potential intersection with top half of parent rect
lui $v1, 4
or $ra, $v1
query_octree_nonleaf_test_b_011:
bnez $at, query_octree_nonleaf_test_7_011 # if y loc of mid-xz-plane of parent rect greater than height of test bound,
# bottom face of test bound (and test bound itself)
# cannot intersect with bottom half of parent rect; so skip the next block
lui $at, 5 # (also load mask for testing bits 1 and 3, i.e. potential intersection with upper-left quadrant)
query_octress_nonleaf_b_011: # else set a bit indicating potential intersection with bottom half of parent rect
lui $v1, 8
or $ra, $v1
query_octree_nonleaf_test_7_011:
and $v0, $at, $ra # using bitfield and mask, test for potential intersection with upper-left quadrant of parent rect
bne $at, $v0, query_octree_nonleaf_test_8_011 # if no intersection, skip recursion in upper-left quadrant
query_octree_nonleaf_7_011: # else recurse in upper-left quadrant
lui $v1, 0x3000 # set current iterator value * 8 (this is test 7-1=6, 6*8=0x30)
lhu $at, 0($a1) # get upper-left child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_8_011:
lui $at, 9 # load mask for testing bits 1 and 4, i.e. potential intersection with lower-left quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_9_011 # if no intersection, skip recursion in lower-left quadrant
query_octree_nonleaf_8_011: # else recurse in lower-left quadrant
lui $v1, 0x3800 # set current iterator value * 8 (this is test 8-1=7, 7*8=0x38)
lhu $at, 2($a1) # get lower-left child node
addu rect_y, rect_h # change cur rect to rect for lower-left child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_8_011:
subu rect_y, rect_h # restore upper-left rect location
query_octree_nonleaf_test_9_011:
lui $at, 6 # load mask for testing bits 2 and 3, i.e. potential intersection with upper-right quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_10_011 # if no intersection, skip recursion in upper-right quadrant
query_octree_nonleaf_9_011: # else recurse in upper-right quadrant
lui $v1, 0x4000 # set current iterator value * 8 (this is test 9-1=8, 8*8=0x40)
lhu $at, 4($a1) # get upper-right child node
addu rect_x, rect_w # change cur rect to rect for upper-right child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_9_011:
subu rect_x, rect_w # restore upper-left rect location
query_octree_nonleaf_test_10_011:
lui $at, 0xA # load mask for testing bits 2 and 4, i.e. potential intersection with lower-right quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_010_end # if no intersection, skip recursion in lower-right quadrant
query_octree_nonleaf_10_011: # else recurse in lower-right quadrant
lui $v1, 0x4800 # set current iterator value * 8 (this is test 10-1=9, 9*8=0x48)
lhu $at, 6($a1) # get lower-right child node
addu rect_x, rect_w
addu rect_y, rect_h # change cur rect to rect for lower-right child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_10_011:
subu rect_x, rect_w
subu rect_y, rect_h # restore upper-left rect location
query_octree_nonleaf_011_end:
sll rect_w, 1 # restore parent rect width
bgez $zero, query_octree_ret_prev # return to previous level
sll rect_h, 1 # restore parent rect height
query_octree_nonleaf_101:
query_octree_nonleaf_test_l_101:
srl rect_w, 1
srl rect_d, 1 # change cur rect to rect for front-left child; halve width and depth
addu $at, rect_x, rect_w # get x location of mid-yz-plane of parent rect
slt $v0, $at, $zero
bnez $v0, query_octree_nonleaf_test_r_101 # if negative, left face of test bound (and test bound itself)
# cannot intersect with left half of parent rect; so skip the next block
slt $at, nodes_w, $at # (also compare x loc of mid-yz-plane of parent rect with width of test bound)
query_octree_nonleaf_l_101: # else set a bit indicating potential intersection with left half of parent rect
lui $v1, 1
or $ra, $v1
query_octree_nonleaf_test_r_101:
bnez $at, query_octree_nonleaf_test_f_101 # if x loc of mid-yz-plane of parent rect greater than width of test bound,
# right face of test bound (and test bound itself)
# cannot intersect with right half of parent rect; so skip the next block
addu $at, rect_z, rect_d # (also get z location of mid-xy-plane of parent rect)
query_octree_nonleaf_r_101: # else set a bit indicating potential intersection with right half of parent rect
lui $v1, 2
or $ra, $v1
query_octree_nonleaf_test_f_101:
slt $v0, $at, $zero # test location of mid-xy-plane of parent rect
bnez $v0, query_octree_nonleaf_test_bk_101 # if negative, front face of test bound (and test bound itself)
# cannot intersect with front half of parent rect; so skip the next block
slt $at, nodes_d, $at # (also compare z loc of mid-xy-plane of parent rect with depth of test bound)
query_octree_nonleaf_f_101: # else set a bit indicating potential intersection with front half of parent rect
lui $v1, 0x10
or $ra, $v1
query_octree_nonleaf_test_bk_101:
bnez $at, query_octree_nonleaf_test_11_101 # if z loc of mid-xy-plane of parent rect greater than depth of test bound,
# back face of test bound (and test bound itself)
# cannot intersect with back half of parent rect; so skip the next block
lui $at, 0x11 # (also load mask for testing bits 1 and 5, i.e. potential intersection with front-left quadrant)
query_octress_nonleaf_bk_101: # else set a bit indicating potential intersection with back half of parent rect
lui $v1, 0x20
or $ra, $v1
query_octree_nonleaf_test_11_101:
and $v0, $at, $ra # using bitfield and mask, test for potential intersection with front-left quadrant of parent rect
bne $at, $v0, query_octree_nonleaf_test_12_101 # if no intersection, skip recursion in front-left quadrant
query_octree_nonleaf_11_101: # else recurse in front-left quadrant
lui $v1, 0x5000 # set current iterator value * 8 (this is test 11-1=10, 10*8=0x50)
lhu $at, 0($a1) # get front-left child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_12_101:
lui $at, 0x21 # load mask for testing bits 1 and 6, i.e. potential intersection with back-left quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_13_101 # if no intersection, skip recursion in back-left quadrant
query_octree_nonleaf_12_101: # else recurse in back-left quadrant
lui $v1, 0x5800 # set current iterator value * 8 (this is test 12-1=11, 11*8=0x58)
lhu $at, 2($a1) # get back-left child node
addu rect_z, rect_d # change cur rect to rect for back-left child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_12_101:
subu rect_z, rect_d # restore front-left rect location
query_octree_nonleaf_test_13_101:
lui $at, 0x12 # load mask for testing bits 2 and 5, i.e. potential intersection with front-right quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_14_101 # if no intersection, skip recursion in front-right quadrant
query_octree_nonleaf_13_101: # else recurse in front-right quadrant
lui $v1, 0x6000 # set current iterator value * 8 (this is test 13-1=12, 12*8=0x60)
lhu $at, 4($a1) # get front-right child node
addu rect_x, rect_w # change cur rect to rect for front-right child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_13_101:
subu rect_x, rect_w # restore front-left rect location
query_octree_nonleaf_test_14_101:
lui $at, 0x22 # load mask for testing bits 2 and 6, i.e. potential intersection with back-right quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_101_end # if no intersection, skip recursion in back-right quadrant
query_octree_nonleaf_14_101: # else recurse in back-right quadrant
lui $v1, 0x6800 # set current iterator value * 8 (this is test 14-1=13, 13*8=0x68)
lhu $at, 6($a1) # get back-right child node
addu rect_x, rect_w
addu rect_z, rect_d # change cur rect to rect for back-right child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_14_101:
subu rect_x, rect_w
subu rect_z, rect_d # restore upper-left rect location
query_octree_nonleaf_101_end:
sll rect_w, 1 # restore parent rect width
bgez $zero, query_octree_ret_prev # return to previous level
sll rect_d, 1 # restore parent rect depth
query_octree_nonleaf_110:
query_octree_nonleaf_test_t_110:
srl rect_h, 1
srl rect_d, 1 # change cur rect to rect for front-top child; halve height and depth
addu $at, rect_y, rect_h # get y location of mid-xz-plane of parent rect
slt $v0, $at, $zero
bnez $v0, query_octree_nonleaf_test_b_110 # if negative, top face of test bound (and test bound itself)
# cannot intersect with top half of parent rect; so skip the next block
slt $at, nodes_w, $at # (also compare y loc of mid-xz-plane of parent rect with height of test bound)
query_octree_nonleaf_t_110: # else set a bit indicating potential intersection with top half of parent rect
lui $v1, 4
or $ra, $v1
query_octree_nonleaf_test_b_110:
bnez $at, query_octree_nonleaf_test_f_110 # if y loc of mid-xz-plane of parent rect greater than height of test bound,
# bottom face of test bound (and test bound itself)
# cannot intersect with bottom half of parent rect; so skip the next block
addu $at, rect_z, rect_d # (also get z location of mid-xy-plane of parent rect)
query_octree_nonleaf_b_110: # else set a bit indicating potential intersection with bottom half of parent rect
lui $v1, 8
or $ra, $v1
query_octree_nonleaf_test_f_110:
slt $v0, $at, $zero # test location of mid-xy-plane of parent rect
bnez $v0, query_octree_nonleaf_test_bk_110 # if negative, front face of test bound (and test bound itself)
# cannot intersect with front half of parent rect; so skip the next block
slt $at, nodes_d, $at # (also compare z loc of mid-xy-plane of parent rect with depth of test bound)
query_octree_nonleaf_f_110: # else set a bit indicating potential intersection with front half of parent rect
lui $v1, 0x10
or $ra, $v1
query_octree_nonleaf_test_bk_110:
bnez $at, query_octree_nonleaf_test_15_110 # if z loc of mid-xy-plane of parent rect greater than depth of test bound,
# back face of test bound (and test bound itself)
# cannot intersect with back half of parent rect; so skip the next block
lui $at, 0x14 # (also load mask for testing bits 3 and 5, i.e. potential intersection with front-top quadrant)
query_octress_nonleaf_bk_110: # else set a bit indicating potential intersection with back half of parent rect
lui $v1, 0x20
or $ra, $v1
query_octree_nonleaf_test_15_110:
and $v0, $at, $ra # using bitfield and mask, test for potential intersection with front-top quadrant of parent rect
bne $at, $v0, query_octree_nonleaf_test_16_110 # if no intersection, skip recursion in front-top quadrant
query_octree_nonleaf_15_110: # else recurse in front-top quadrant
lui $v1, 0x7000 # set current iterator value * 8 (this is test 15-1=14, 14*8=0x70)
lhu $at, 0($a1) # get front-top child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_16_110:
lui $at, 0x24 # load mask for testing bits 3 and 6, i.e. potential intersection with back-top quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_17_110 # if no intersection, skip recursion in back-top quadrant
query_octree_nonleaf_16_110: # else recurse in back-top quadrant
lui $v1, 0x7800 # set current iterator value * 8 (this is test 16-1=15, 15*8=0x78)
lhu $at, 2($a1) # get back-top child node
addu rect_z, rect_d # change cur rect to rect for back-top child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_16_110:
subu rect_z, rect_d # restore front-top rect location
query_octree_nonleaf_test_17_110:
lui $at, 0x18 # load mask for testing bits 4 and 5, i.e. potential intersection with front-bottom quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_18_110 # if no intersection, skip recursion in front-bottom quadrant
query_octree_nonleaf_17_110: # else recurse in front-bottom quadrant
lui $v1, 0x8000 # set current iterator value * 8 (this is test 17-1=16, 16*8=0x80)
lhu $at, 4($a1) # get front-bottom child node
addu rect_y, rect_h # change cur rect to rect for front-bottom child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_17_110:
subu rect_y, rect_h # restore front-top rect location
query_octree_nonleaf_test_18_110:
lui $at, 0x28 # load mask for testing bits 4 and 6, i.e. potential intersection with back-bottom quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_110_end # if no intersection, skip recursion in back-bottom quadrant
query_octree_nonleaf_18_110: # else recurse in back-bottom quadrant
lui $v1, 0x8800 # set current iterator value * 8 (this is test 18-1=17, 17*8=0x88)
lhu $at, 6($a1) # get back-bottom child node
addu rect_y, rect_h
addu rect_z, rect_d # change cur rect to rect for back-bottom child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_18_110:
subu rect_y, rect_h
subu rect_z, rect_d # restore front-top rect location
query_octree_nonleaf_110_end:
sll rect_h, 1 # restore parent rect height
bgez $zero, query_octree_ret_prev # return to previous level
sll rect_d, 1 # restore parent rect depth
query_octree_nonleaf_111:
srl rect_w, 1
srl rect_h, 1
srl rect_d, 1 # change cur rect to rect for upper-left-front child; halve width, height, and depth
addu $at, rect_x, rect_w # get x location of mid-yz-plane of parent rect
slt $v0, $at, $zero
bnez $v0, query_octree_nonleaf_test_r_111 # if negative, left face of test bound (and test bound itself)
# cannot intersect with left half of parent rect; so skip the next block
slt $at, nodes_w, $at # (also compare x loc of mid-yz-plane of parent rect with width of test bound)
query_octree_nonleaf_l_111: # else set a bit indicating potential intersection with left half of parent rect
lui $v1, 1
or $ra, $v1
query_octree_nonleaf_test_r_111:
bnez $at, query_octree_nonleaf_test_f_111 # if x loc of mid-yz-plane of parent rect greater than width of test bound,
# right face of test bound (and test bound itself)
# cannot intersect with right half of parent rect; so skip the next block
addu $at, rect_y, rect_h # (also get y location of mid-xz-plane of parent rect)
query_octree_nonleaf_r_111: # else set a bit indicating potential intersection with right half of parent rect
lui $v1, 2
or $ra, $v1
query_octree_nonleaf_test_t_111:
slt $v0, $at, $zero # test y location of mid-xz-plane of parent rect
bnez $v0, query_octree_nonleaf_test_b_111 # if negative, top face of test bound (and test bound itself)
# cannot intersect with top half of parent rect; so skip the next block
slt $at, nodes_h, $at # (also compare y loc of mid-xz-plane of parent rect with height of test bound)
query_octree_nonleaf_t_110: # else set a bit indicating potential intersection with top half of parent rect
lui $v1, 4
or $ra, $v1
query_octree_nonleaf_test_b_111:
bnez $at, query_octree_nonleaf_test_f_111 # if y loc of mid-xz-plane of parent rect greater than height of test bound,
# bottom face of test bound (and test bound itself)
# cannot intersect with bottom half of parent rect; so skip the next block
addu $at, rect_z, rect_d # (also get z location of mid-xy-plane of parent rect)
query_octree_nonleaf_b_111: # else set a bit indicating potential intersection with bottom half of parent rect
lui $v1, 8
or $ra, $v1
query_octree_nonleaf_test_f_111:
slt $v0, $at, $zero # test z location of mid-xy-plane of parent rect
bnez $v0, query_octree_nonleaf_test_bk_111 # if negative, front face of test bound (and test bound itself)
# cannot intersect with front half of parent rect; so skip the next block
slt $at, nodes_d, $at # (also compare z loc of mid-xy-plane of parent rect with depth of test bound)
query_octree_nonleaf_b_111: # else set a bit indicating potential intersection with front half of parent rect
lui $v1, 0x10
or $ra, $v1
query_octree_nonleaf_test_bk_111:
bnez $at, query_octree_nonleaf_test_15_111 # if z loc of mid-xy-plane of parent rect greater than depth of test bound,
# back face of test bound (and test bound itself)
# cannot intersect with back half of parent rect; so skip the next block
lui $at, 0x15 # (also load mask for testing bits 1, 3, and 5,
# i.e. potential intersection with upper-left-front octant)
query_octress_nonleaf_bk_111: # else set a bit indicating potential intersection with back half of parent rect
lui $v1, 0x20
or $ra, $v1
query_octree_nonleaf_test_19_111:
and $v0, $at, $ra # using bitfield and mask, test for potential intersection
# with upper-left-front octant of parent rect
bne $at, $v0, query_octree_nonleaf_test_20_111 # if no intersection, skip recursion in upper-left-front octant
query_octree_nonleaf_19_111: # else recurse in upper-left-front octant
lui $v1, 0x9000 # set current iterator value * 8 (this is test 19-1=18, 18*8=0x90)
lhu $at, 0($a1) # get upper-left-front child node
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_test_20_111:
lui $at, 0x25 # load mask for testing bits 1, 3, and 6, i.e. potential intersection
# with upper-left-back quadrant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_21_111 # if no intersection, skip recursion in upper-left-back octant
query_octree_nonleaf_20_111: # else recurse in upper-left-back
lui $v1, 0x9800 # set current iterator value * 8 (this is test 20-1=19, 19*8=0x98)
lhu $at, 2($a1) # get upper-left-back child node
addu rect_z, rect_d # change cur rect to rect for upper-left-back child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_20_111:
subu rect_z, rect_d # restore upper-left-front rect location
query_octree_nonleaf_test_21_111:
lui $at, 0x19 # load mask for testing bits 1, 4, and 5, i.e. potential intersection
# with lower-left-front octant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_22_111 # if no intersection, skip recursion in lower-left-front octant
query_octree_nonleaf_21_111: # else recurse in lower-left-front octant
lui $v1, 0xA000 # set current iterator value * 8 (this is test 21-1=20, 20*8=0xA0)
lhu $at, 4($a1) # get lower-left-front child node
addu rect_y, rect_h # change cur rect to rect for lower-left-front child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_21_111:
subu rect_y, rect_h # restore upper-left-front rect location
query_octree_nonleaf_test_22_111:
lui $at, 0x29 # load mask for testing bits 1, 4, and 6 i.e. potential intersection
# with lower-left-back octant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_23_111 # if no intersection, skip recursion in lower-left-back octant
query_octree_nonleaf_22_111: # else recurse in lower-left-back octant
lui $v1, 0xA800 # set current iterator value * 8 (this is test 22-1=21, 21*8=0xA8)
lhu $at, 6($a1) # get lower-left-back child node
addu rect_y, rect_h
addu rect_z, rect_d # change cur rect to rect for lower-left-back child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_22_111:
subu rect_y, rect_h
subu rect_z, rect_d # restore upper-left-front rect location
query_octree_nonleaf_test_23_111:
lui $at, 0x16 # load mask for testing bits 2, 3, and 5 i.e. potential intersection
# with upper-right-front octant of parent rect
bne $at, $v0, query_octree_nonleaf_test_24_111 # if no intersection, skip recursion in upper-right-front octant
query_octree_nonleaf_23_111: # else recurse in upper-right-front octant
lui $v1, 0xB000 # set current iterator value * 8 (this is test 23-1=22, 22*8=0xB0)
lhu $at, 8($a1) # get upper-right-front child node
addu rect_x, rect_w # change cur rect to rect for upper-right-front child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_23_111:
subu rect_x, rect_w # restore upper-left-front rect location
query_octree_nonleaf_test_24_111:
lui $at, 0x26 # load mask for testing bits 2, 3, and 6, i.e. potential intersection
# with upper-right-back octant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_25_111 # if no intersection, skip recursion in upper-right-back octant
query_octree_nonleaf_24_111: # else recurse in upper-right-back
lui $v1, 0xB800 # set current iterator value * 8 (this is test 24-1=23, 19*8=0xB8)
lhu $at, 0xA($a1) # get upper-right-back child node
addu rect_x, rect_W
addu rect_z, rect_d # change cur rect to rect for upper-right-back child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_24_111:
subu rect_x, rect_w
subu rect_z, rect_d # restore upper-left-front rect location
query_octree_nonleaf_test_25_111:
lui $at, 0x1A # load mask for testing bits 2, 4, and 5, i.e. potential intersection
# with lower-right-front octant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_test_26_111 # if no intersection, skip recursion in lower-right-front octant
query_octree_nonleaf_25_111: # else recurse in lower-right-front octant
lui $v1, 0xC000 # set current iterator value * 8 (this is test 25-1=24, 24*8=0xC0)
lhu $at, 0xC($a1) # get lower-right-front child node
addu rect_x, rect_w
addu rect_y, rect_h # change cur rect to rect for lower-right-front child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_25_111:
subu rect_x, rect_w
subu rect_y, rect_h # restore upper-left-front rect location
query_octree_nonleaf_test_26_111:
lui $at, 0x2A # load mask for testing bits 2, 4, and 6 i.e. potential intersection
# with lower-right-back octant of parent rect
and $v0, $at, $ra # apply mask
bne $at, $v0, query_octree_nonleaf_111_end # if no intersection, skip recursion in lower-right-back octant
query_octree_nonleaf_26_111: # else recurse in lower-right-back octant
lui $v1, 0xC800 # set current iterator value * 8 (this is test 26-1=25, 25*8=0xC8)
lhu $at, 0xE($a1) # get lower-right-back child node
addu rect_x, rect_w
addu rect_y, rect_h
addu rect_z, rect_d # change cur rect to rect for lower-right-back child [of parent rect]
bgez $zero, query_octree_recurse # recurse
or $v1, $at # store iterator value * 8 in upper byte of $v1, with child node
query_octree_nonleaf_res_26_111:
subu rect_x, rect_w
subu rect_y, rect_h
subu rect_z, rect_d # restore parent rect location
query_octree_nonleaf_111_end:
sll rect_w, 1 # restore parent rect width
sll rect_h, 1 # restore parent rect height
bgez $zero, query_octree_ret_prev # return to previous level
sll rect_d, 1 # restore parent rect depth
query_octree_leaf:
query_octree_leaf_test_1:
slti $at, $a3, 512 # test count of query results
beqz $at, query_octree_ret_prev # if too high, return to previous level
query_octree_leaf_1: # else pack the leaf node, current level, and rect location,
# into a new zone_query_result, and append to results array
sll $at, $a1, 2 # shift up type and subtype bits of node
andi $at, 0xFFF8 # select as bits 4-7 and 8-16, respectively
or $at, level # or with current level in bits 1-3
srl $v0, $t5, 4 # shift out lower 4 bits of cur rect x location
sll $v0, 16 # shift remaining 12 bits to upper hword
or $at, $v0 # or with type, subtype, and current level bits in lower hword
srl $v0, $t7, 4 # shift out lower 4 bits of cur rect z location
sll $v0, 16 # shift remaining 12 bits to upper hword
srl $v1, $t6, 4 # shift out lower 4 bits of cur rect y location
andi $v1, 0xFFFF # select only lower hword of result
or $v0, $v1 # or with shifted rect z location in upper hword
sw $at, 0($a2) # store (append) the shifted rect x location, type, subtype, and
# current level bits as the first word of a new query result
sw $v0, 4($a2) # store (append) shifted rect z and y location as the second word
# of the new query result
addiu $a3, 1 # increment query result count
bgez $zero, query_octree_ret_prev # return to the previous level
addiu $a2, 8 # increment query result iterator (pointer-based)
#
# Plot walls in the wall bitmap for wall nodes returned by a query.
#
# a0 = query
# a1 = zone_loc or zone_dim
# a2 = flags
# a3 = test_y1_t1
# gp (arg_10) = test_y1
# sp (arg_14) = test_y2
# fp (arg_18) = trans_x
# t3 (arg_1C) = trans_z
#
RPlotQueryWalls:
result = $a0
level = $t0
nbound_p1_x = $t6
nbound_p1_y = $t7
nbound_p1_z = $s0
nbound_p2_x = $s1
nbound_p2_y = $s2
nbound_p2_z = $s3
zone_w = $s4
zone_h = $s5
zone_d = $s6
max_depth_x = $s7
max_depth_y = $t8
max_depth_z = $t9
test_y1 = $gp
test_y2 = $sp
trans_x = $fp
trans_z = $t3
ssave
lw test_y1, arg_10($sp)
lw trans_x, arg_18($sp)
lw trans_z, arg_1C($sp)
lw test_y2, arg_14($sp)
lw $t5, 8($a1)
lw $t4, 4($a1)
lw $a1, 0($a1) # $a1,$t4,$t5 = zone_loc
# result is initially equal to query (pointer to query results head)
plot_zone_walls_loop:
plot_zone_walls_result_test:
lw $at, 0(result) # $at = (result->x << 16) | result->is_node
lw $v0, 4(result) # $v0 = (result->z << 16) | result->y
li $v1, 0xFFFF
and $t1, $at, $v1 # $t1 = result->value or result->is_node
beq $t1, $v1, plot_zone_walls_ret # return if result->value is a null node
nop
bnez $t1, loc_80038700 # if (result->is_node) then goto node case
nop
plot_zone_walls_result_is_rect: # else result is a rect; let result_rect = (zone_query_result_rect*)result
srl zone_w, $at, 16
sll zone_w, 8 # zone_w = result_rect->w << 8
andi zone_h, $v0, 0xFFFF
sll zone_h, 8 # zone_h = result_rect->h << 8
srl zone_d, $v0, 16
sll zone_d, 8 # zone_d = result_rect->d << 8
lw $at, 8(result) # $at = (result_rect->max_depth_x << 16) | result_rect->unused
lw $v0, 0xC(result) # $v0 = (result_rect->max_depth_z << 16) | result_rect->max_depth_y
srl max_depth_x, $at, 16 # max_depth_x = result_rect->max_depth_x
andi max_depth_y, $v0, 0xFFFF # max_depth_y = result_rect->max_depth_y
srl max_depth_z, $v0, 16 # max_depth_z = result_rect->max_depth_z
bgez $zero, plot_zone_walls_loop # continue
addiu result, 0x10 # increment result pointer to next result
# ((uint8_t*)result) += sizeof(zone_query_result_rect)
plot_zone_walls_result_is_node:
andi level, $at, 7 # level = result->level
andi $t1, $at, 0xFFF8
srl $t1, 2
ori $t1, 1 # $t1 = (result->node << 1) | 1
srl nbound_p1_x, $at, 16 # nbound.p1.x = result->x
andi nbound_p1_y, $v0, 0xFFFF # nbound.p1.y = result->y
srl nbound_p1_z, $v0, 16 # nbound.p1.z = result->z
sll nbound_p1_x, 16 # shift up sign bit
sra nbound_p1_x, 12 # nbound.p1.x = (result->x << 4)
sll nbound_p1_y, 16
sra nbound_p1_y, 12 # nbound.p1.y = (result->y << 4)
sll nbound_p1_z, 16
sra nbound_p1_z, 12 # nbound.p1.z = (result->z << 4)
addu nbound_p1_x, $a1, nbound_p1_x
addu nbound_p1_y, $t4, nbound_p1_y
addu nbound_p1_z, $t5, nbound_p1_z # n_bound.p1 = (result_loc << 4) + zone_loc
plot_zone_walls_min_lx:
slt $at, max_depth_x, level
bnez $at, plot_zone_walls_rect_x1
# plot_zone_walls_minl_lx:
srlv $at, zone_w, max_depth_x # $at = zone_w >> min(level, max_depth_x)
plot_zone_walls_minr_lx: # ...
srlv $at, zone_w, level # ...
plot_zone_walls_rect_x1:
addu nbound_p2_x, nbound_p1_x, $at # nbound.p2.x = nbound.p1.x + (zone_w >> min(level, max_depth_x))
plot_zone_walls_min_ly:
slt $at, max_depth_y, level
bnez $at, plot_zone_walls_rect_y1
# plot_zone_walls_minl_ly:
srlv $at, zone_h, max_depth_y # $at = zone_h >> min(level, max_depth_y)
plot_zone_walls_minr_ly: # ...
srlv $at, zone_h, level # ...
plot_zone_walls_rect_y1:
addu nbound_p2_y, nbound_p1_y, $at # nbound.p2.y = nbound.p1.y + (zone_h >> min(level, max_depth_y))
plot_zone_walls_min_lz:
slt $at, max_depth_z, level
bnez $at, plot_zone_walls_rect_z1
# plot_zone_walls_minl_lz:
srlv $at, zone_d, max_depth_z # $at = zone_d >> min(level, max_depth_z)
plot_zone_walls_minr_lz:
srlv $at, zone_d, level # ...
plot_zone_walls_rect_z1:
addu nbound_p2_z, nbound_p1_z, $at # nbound.p2.z = nbound.p1.z + (zone_d >> min(level, max_depth_z))
plot_zone_walls_node_parse:
andi $v1, $t1, 0xE
srl $v1, 1 # $v1 = node->type
andi $v0, $t1, 0x3F0
srl $v0, 4 # $v0 = node->subtype
li $at, 3
beq $at, $v1, plot_zone_walls_continue # skip if type is 3
li $at, 4
beq $at, $v1, plot_zone_walls_continue # skip if type is 4
li $at, 1
beq $at, $v1, plot_zone_walls_type_1 # goto type 1 case if type 1
nop
beqz $v0, plot_zone_walls_case_0 # if subtype 0, goto case 0
sltiu $at, $v0, 39 # '''
beqz $at, plot_zone_walls_case_0 # if subtype >= 40, goto case 0
nop
beqz $a2, plot_zone_walls_continue # if a2 != 0, goto case 0; else continue
nop
plot_zone_walls_case_0:
slt $at, test_y1, nbound_p2_y
slt $v0, nbound_p1_y, test_y2
and $at, $v0
bnez $at, plot_zone_walls_do_plot # if test_y1 < nbound.p2.y && nbound.p1.y < test_y2 (intersection), then do plot
nop
bgez $zero, plot_zone_walls_continue # else continue
nop
plot_zone_walls_type_1:
slt $at, $a3, nbound_p2_y
slt $v0, nbound_p1_y, test_y2
and $at, $v0
beqz $at, plot_zone_walls_continue # if test_y1_t1 < nbound.p2.y && nbound.p1.y < test_y2 (intersection),
nop # then fall through to do plot; else continue
plot_zone_walls_do_plot:
li $at, 0x1F8000E0
sw $a2, 0($at)
sw $a3, 4($at) # temporarily preserve $a2 and $a3 (flags, test_y1_t1) in scratch memory
subu nbound_p1_x, trans_x # relativize (w.r.t trans) and scale nbound to bitmap index units
sll nbound_p1_x, 2
sra nbound_p1_x, 13 # nbound.p1.x = ((nbound.p1.x - trans_x) << 2) >> 13
subu nbound_p2_x, trans_x
sll nbound_p2_x, 2
sra nbound_p2_x, 13 # nbound.p2.x = ((nbound.p2.x - trans_x) << 2) >> 13
subu nbound_p1_z, trans_z
sll nbound_p1_z, 2
sra nbound_p1_z, 13 # nbound.p1.z = ((nbound.p1.z - trans_z) << 2) >> 13
subu nbound_p2_z, $t3
sll nbound_p2_z, 2
sra nbound_p2_z, 13 # nbound.p2.z = ((nbound.p2.z - trans_z) << 2) >> 13
plot_zone_walls_do_plot_2: # plot circles along the edges of nbound in 8 bitmap index unit increments
ix = nbound_p1_x
iz = nbound_p1_z
move $t7, nbound_p1_x
move $s2, nbound_p1_z # temporarily preserve current nbound.p1.x, nbound.p1.z in $t7,$s2
plot_zone_walls_test_z1_gtn32:
li $a2, -32
slt $at, $a2, nbound_p1_z
beqz $at, plot_zone_walls_test_x2 # skip loop 1 if nbound.p1.z <= -32
plot_zone_walls_test_z1_lt32:
slti $at, nbound_p1_z, 32
beqz $at, plot_zone_walls_test_x2 # skip loop 1 if nbound.p1.z >= 32
plot_zone_walls_loop_1: # iterate from ix = max(nbound.p1.x, -32[+nbound.p1.x%8]) to min(nbound.p2.x, 32), step by 8
plot_zone_walls_test_ix_gtn32_1:
slt $at, $a2, ix
beqz $at, plot_zone_walls_loop_1_continue # step ix by 8 while it is less than -32 (move it to a valid index)
plot_zone_walls_test_ix_lt32_1:
slti $at, ix, 32
beqz $at, plot_zone_walls_test_x2 # break when ix >= 32
slt $at, ix, nbound_p2_x
beqz $at, plot_zone_walls_test_x2 # or [break] when ix >= nbound_p2_x
move $v1, ix
jal RPlotWall # else plot a wall at (ix, nbound.p1.z)
move $a3, nbound_p1_z
plot_zone_walls_loop_1_continue:
bgez $zero, plot_zone_walls_loop_1 # continue looping
addiu ix, 8 # step iterator ix by 8
plot_zone_walls_test_x2:
move ix, nbound_p2_x
plot_zone_walls_test_x2_gtn32_2:
slt $at, $a2, ix
beqz $at, plot_zone_walls_test_z2
plot_zone_walls_test_x2_lt32_1:
slti $at, ix, 32
beqz $at, plot_zone_walls_test_z2
plot_zone_walls_loop_2: # iterate from iz = max(nbound.p1.z, -32[+nbound.p1.z%8]) to min(nbound.p2.z, 32), step by 8
plot_zone_walls_test_iz_gtn32_1:
slt $at, $a2, iz
beqz $at, plot_zone_walls_loop_2_continue # step iz by 8 while it is less than -32 (move it to a valid index)
plot_zone_walls_test_iz_lt32_1:
slti $at, iz, 32 # ' '
beqz $at, plot_zone_walls_test_z2 # break when iz >= 32
slt $at, iz, nbound_p2_z
beqz $at, plot_zone_walls_test_z2 # or [break] when iz >= nbound_p2_z
move $v1, ix
jal RPlotWall # else plot a wall at (nbound.p1.x, iz)
move $a3, iz
plot_zone_walls_loop_2_continue:
bgez $zero, plot_zone_walls_loop_2 # continue looping
addiu iz, 8 # step iterator iz by 8
plot_zone_walls_test_z2:
move iz, nbound_p2_z
plot_zone_walls_test_z2_gtn32_2:
slt $at, $a2, iz
beqz $at, plot_zone_walls_test_x1
plot_zone_walls_test_z2_lt32_1:
slti $at, iz, 32
beqz $at, plot_zone_walls_test_x1
plot_zone_walls_loop_3: # iterate from ix = min(nbound.p2.x, 32[+nbound.p1.x%8]) to max(nbound.p1.x, -32), step by -8
plot_zone_walls_test_ix_lt32_2:
slti $at, ix, 32
beqz $at, plot_zone_walls_loop_3_continue # step ix by -8 while it is greater than 32 (move it to a valid index)
plot_zone_walls_test_ix_lt32_2:
slt $at, $a2, ix
beqz $at, plot_zone_walls_test_x1 # break when ix <= -32
slt $at, $t7, ix
beqz $at, plot_zone_walls_test_x1 # or [break] when ix <= nbound.p1.x
move $v1, ix
jal RPlotWall # else plot a wall at (ix, nbound.p1.z)
move $a3, iz
plot_zone_walls_loop_3_continue:
bgez $zero, plot_zone_walls_loop_3 # continue looping
addiu ix, -8 # step iterator ix by -8
plot_zone_walls_test_x1:
move ix, $t7 # ix = preserved nbound.p1.x
plot_zone_walls_test_x1_lt32_2:
slti $at, ix, 32
beqz $at, plot_zone_walls_do_plot_3
plot_zone_walls_test_x1_gtn32_1:
slti $at, $a2, ix
beqz $at, plot_zone_walls_do_plot_3
plot_zone_walls_loop_4: # iterate from iz = min(nbound.p2.z, 32[+nbound.p2.z%8]) to max(nbound.p1.z, -32), step by -8
plot_zone_walls_test_iz_lt32_2:
slti $at, iz, 32
beqz $at, plot_zone_walls_loop_4_continue # step iz by -8 while it is greater than 32 (move it to a valid index)
plot_zone_walls_test_iz_gtn32_2:
slt $at, $a2, iz
beqz $at, plot_zone_walls_do_plot_3 # break when iz <= -32
slt $at, $s2, iz # ($s2 = temporarily saved nbound.p1.z)
beqz $at, plot_zone_walls_do_plot_3 # or [break] when iz <= nbound.p1.x
move $v1, ix
jal RPlotWall # else plot a wall at (nbound.p1.x, iz)
move $a3, iz
plot_zone_walls_loop_4_continue:
bgez $zero, plot_zone_walls_loop_2 # continue looping
addiu ix, -8 # step iterator ix by -8
plot_zone_walls_do_plot_3:
li $at, 0x1F8000E0
lw $a2, 0($at)
lw $a3, 4($at) # restore previous flags, test_y1_t1, from scratch memory
plot_zone_walls_continue:
bgez $zero, plot_zone_walls_loop # continue looping
addiu result, 8
plot_zone_walls_ret:
sload
jr $ra
nop
#
# set a 16 unit radius circular region of bits in the wall bitmap
# (functionally identical to PlotWall in solid.c, except for lack of bound check)
#
# v1 = x
# a3 = z
#
RPlotWall:
x = $v1
z = $a3
plot_wall_test_x_1:
bgez x, plot_wall_x_gteq0_1 # goto >= 0 case if x >= 0
plot_wall_x_lt0_1:
addiu $at, z, 32 # $at = z+32
li $v0, 0x1F800180 # get pointer to scratch wall cache
sll $at, 3 # z'th row from center, left set of 32 bits in row
# $at (idx*4) = (((z+32)*2) + 0) * sizeof(uint32_t)
addu $t0, $at, $v0 # $t0 = &scratch.wall_cache[idx]
addiu $v0, x, 32 # $v0 = x+32
li $at, 1
lw $t1, 0($t0) # $t1 = scratch.wall_cache[idx]
bgez $zero, plot_wall_test_cache # goto test bit in the wall cache
sllv $v0, $at, $v0 # $v0 (bit) = 1 << (x+32); mask for (32-abs(x))'th bit
plot_wall_x_gteq0_1:
sll $at, 3
li $v0, 0x1F800180
addiu $at, 4 # z'th row from center, right set of 32 bits in row
# $at (idx*4) = (((z+32)*2) + 1) * sizeof(uint32_t)
addu $t0, $at, $v0 # $t0 = &scratch.wall_cache[idx]
li $at, 1
lw $t1, 0($t0) # $t1 = scratch.wall_cache[idx]
sllv $v0, $at, $v1 # $v0 (bit) = 1 << x; mask for x'th bit
plot_wall_test_cache:
and $at, $v0, $t1 # $at = scratch.wall_cache[idx] & bit
bnez $at, plot_wall_ret # test bit; if set, return, as a wall has already been
# plotted with center at x,z
plot_wall_do: # else, plot circle in wall bitmap with center at x,z:
or $at, $v0, $t1
sw $at, 0($t0) # set bit in the wall cache for future checks
# scratch.wall_cache[idx] |= bit
plot_wall_test_z_1:
bgez z, plot_wall_z_gteq0
move $t1, $zero # $t1 (i, start) = 0
plot_wall_z_lt0:
negu $t1, z # $t1 (i, start) = -z
bgez $zero, plot_wall_test_z_2
li $t2, 32 # $t2 (end) = 32
plot_wall_z_gteq0:
li $at, 32
subu $t2, $at, z # $t2 (end) = 32-z
plot_wall_test_z_2:
bgez z, plot_wall_do_2
nop
plot_wall_z_lt0_2:
move z, $zero # z (i.e. idx) = 0 (else idx = z)
plot_wall_do_2:
li $v0, 0x1F800100 # get pointer to scratch wall bitmap
sll $at, z, 2 # $at = z (idx) * sizeof(uint32_t)
plot_wall_test_x_2:
bgez x, plot_x_gteq0_loop_test #
addu $t0, $at, $v0 # $t0 (wall_bitmap_p) = &wall_bitmap[z];
plot_wall_x_lt0_2:
slt $at, $t1, $t2
beqz $at, plot_wall_ret # return if i < end,
negu $v1, $v1 # x = -x (i.e. abs(x))
plot_wall_x_lt0_loop:
sll $at, $t1, 2 # $at = i * sizeof(uint32_t)
li $v0, 0x1F800380 # get pointer to scratch circle bitmap
addiu $t1, 1 # i++;
addu $at, $v0 # $at = &scratch.circle_bitmap[i];
lw $at, 0($at) # $at (bits) = scratch.circle_bitmap[i];
lw $v0, 0($t0) # $v0 = wall_bitmap[z];
sllv $at, $v1 # $at = bits << x
or $at, $v0 # $at = wall_bitmap[z] | (bits << x);
sw $at, 0($t0) # wall_bitmap[z] = wall_bitmap[z] | (bits << x)
slt $at, $t1, $t2
bnez $at, plot_wall_x_lt0_loop # continue while i < end
addiu $t0, 4 # wall_bitmap_p++; (i.e. z++)
bgez $zero, plot_wall_ret # else return
nop
plot_wall_x_gteq0_loop:
li $v0, 0x1F800380 # get pointer to scratch circle bitmap
addiu $t1, 1 # i++;
addu $at, $v0 # $at = &scratch.circle_bitmap[i];
lw $at, 0($at) # $at (bits) = scratch.circle_bitmap[i];
lw $v0, 0($t0) # $v0 = wall_bitmap[z]
srlv $at, $v1 # $at = bits >> x
or $at, $v0 # $at = wall_bitmap[z] | (bits >> x)
sw $at, 0($t0) # wall_bitmap[z] = wall_bitmap[z] | (bits >> x)
addiu $t0, 4 # wall_bitmap_p++; (i.e. z++)
plot_wall_x_gteq0_loop_test:
slt $at, $t1, $t2
bnez $at, plot_wall_x_gteq0_loop # contine while i < end
sll $at, $t1, 2 # $at = i * sizeof(uint32_t)
plot_wall_ret:
jr $ra
nop
#
# compute the average bottom (top?) face y locations of query result nodes
# of floor type, and non-floor type, respectively, which intersect the input bound
# [and which have a bottom (top?) face below the max_y value]
#
# all nodes of non-type 3 or 4 and of subtype 0 or > 38 which are in the
# intersection contribute to the result(s); otherwise the input callback filter
# function is called with the obj and the node value to determine whether a node
# is selected
#
# the results are stored in the input zone_query_summary
# (which is a substructure of the parent query)
#
# a0 = obj
# a1 = query
# a2 = nodes_bound (input bound queried with)
# a3 = collider_bound (bound to test against query results)
# 0x10($sp) = max_y
# 0x14($sp) = summary
# 0x18($sp) = default_y
# 0x1C($sp) = func
#
RFindFloorY:
result = $t2
level = $gp
nbound_p1_x = $t3
nbound_p1_y = $t4
nbound_p1_z = $t5
cbound_p1_x = $t6
cbound_p1_y = $t7
cbound_p1_z = $s0
cbound_p2_x = $s1
cbound_p2_y = $s2
cbound_p2_z = $s3
zone_w = $s4
zone_h = $s5
zone_d = $s6
max_depth_x = $s7
max_depth_y = $t8
max_depth_z = $t9
max_y = $v1
arg_10 = 0x10
arg_14 = 0x14
arg_18 = 0x18
arg_1C = 0x1C
ssave
li $v0, 0x1F8000EC
sw $a0, 0($v0) # preserve obj (pointer) argument in scratch
lw max_y, arg_10($sp)
lw $t0, arg_14($sp) # get summary results pointer arg
lw $v0, arg_18($sp) # get default y result value arg
lw $t1, arg_1C($sp) # get callback function pointer arg
move result, $a1
lw $sp, 0($a2)
lw $fp, 4($a2)
lw $ra, 8($a2) # $sp,$fp,$ra = nodes_bound.p1
lw cbound_p1_x, 0($a3)
lw cbound_p1_y, 4($a3)
lw cbound_p1_z, 8($a3)
lw cbound_p2_x, 0xC($a3)
lw cbound_p2_y, 0x10($a3)
lw cbound_p2_z, 0x14($a3) # cbound = *collider_bound
li $at, 0x1F8000E0
sw $v0, 0($at) # preserve default y result value arg in scratch
sw $t1, 4($at) # preserve callback function pointer arg in scratch
sw $t0, 8($at) # preserve summary results pointer arg in scratch
type = $t0
count_y2_t0 = $a2
sum_y2_t0 = $a3
# count_tn0 = $at
sum_y2_tn0 = $t1
move sum_y2_t0, $zero # initialize running sum of y2 values for type 0 nodes
move count_t0, $zero # initialize count of type 0 nodes
move sum_y2_tn0, $zero # initialize running sum of y2 values for non-type 0 nodes
move count_tn0, $zero # initialize count of non-type 0 nodes
find_floor_loop:
find_floor_result_test:
lw $a0, 0(result) # $a0 = (result->x << 16) | result->is_node
lw $v0, 4(result) # $v0 = (result->z << 16) | result->y
li $t0, 0xFFFF
and $a1, $a0, $t0 # $a1 = result->value or result->is_node
beq $a1, $t0, find_floor_end # goto end if result->value is null node
nop
bnez $a1, find_floor_result_is_node # if (result->is_node) then goto node case
nop
find_floor_result_is_rect: # else result is a rect; let result_rect = (zone_query_result_rect*)result
srl zone_w, $a0, 16
sll zone_w, 8 # zone_w = result_rect->w << 8
andi zone_h, $v0, 0xFFFF
sll zone_h, 8 # zone_h = result_rect->h << 8
srl zone_d, $v0, 16
sll zone_d, 8 # zone_d = result_rect->d << 8
lw $a0, 8(result) # $a0 = (result_rect->max_depth_x << 16) | result_rect->unused
lw $v0, 0xC(result) # $v0 = (result_rect->max_depth_z << 16) | result_rect->max_depth_y
srl max_depth_x, $a0, 16 # max_depth_x = result_rect->max_depth_x
andi max_depth_y, $v0, 0xFFFF # max_depth_y = result_rect->max_depth_y
srl max_depth_z, $v0, 16 # max_depth_z = result_rect->max_depth_z
bgez $zero, find_floor_loop # continue
addiu result, 0x10 # increment result pointer to next result
find_floor_result_is_node:
andi $a1, $a0, 0xFFF8
srl $a1, 2
ori $a1, 1 # $a1 = (result->node << 1) | 1 [**this is passed to the callback function below]
andi type, $a1, 0xE # type = node->type << 1
andi level, $a0, 7 # level = result->level
srl nbound_p1_x, $a0, 16 # nbound.p1.x = result->x
andi nbound_p1_y, $v0, 0xFFFF # nbound.p1.y = result->y
srl nbound_p1_z, $v0, 16 # nbound.p1.z = result->z
sll nbound_p1_x, 16 # shift up sign bit
sra nbound_p1_x, 12 # nbound.p1.x = (result->x << 4)
sll nbound_p1_y, 16
sra nbound_p1_y, 12 # nbound.p1.y = (result->y << 4)
sll nbound_p1_z, 16
sra nbound_p1_z, 12 # nbound.p1.z = (result->z << 4)
addu nbound_p1_x, $sp, nbound_p1_x
addu nbound_p1_y, $fp, nbound_p1_y
addu nbound_p1_z, $ra, nbound_p1_z # n_bound.p1 = (nodes_bound << 4) + nbound (convert local bound to absolute bound)
find_floor_test_collider_intersects_node: # skip this node if the collider bound is entirely above, left of, or behind the node bound
slt $a0, cbound_p2_x, nbound_p1_x
bnez $a0, find_floor_continue # skip if collider_bound.p2.x < n_bound.p1.x
slt $a0, cbound_p2_y, nbound_p1_y
bnez $a0, find_floor_continue # skip if collider_bound.p2.y < n_bound.p1.y
slt $a0, cbound_p2_z, nbound_p1_z
bnez $a0, find_floor_continue # skip if collider_bound.p2.z < n_bound.p1.z
find_floor_min_lx:
slt $a0, max_depth_x, level
bnez $a0, find_floor_nbound_x2
# find_floor_minl_lx:
srlv $a0, zone_w, max_depth_x # $a0 = zone_w >> min(level, max_depth_x)
find_floor_minr_lx: # ...
srlv $a0, zone_w, level # ...
find_floor_nbound_x2:
nbound_p2_x = nbound_p1_x
addu nbound_p1_x, $a0 # nbound.p2.x = nbound.p1.x + (zone_w >> min(level, max_depth_x))
find_floor_min_ly:
slt $a0, max_depth_y, level
bnez $a0, find_floor_nbound_y2
# find_floor_minl_ly:
srlv $a0, zone_h, max_depth_y # $a0 = zone_h >> min(level, max_depth_y)
find_floor_minr_ly: # ...
srlv $a0, zone_h, level # ...
find_floor_nbound_y2:
nbound_p2_y = nbound_p1_y
addu nbound_p1_y, $a0 # nbound.p2.y = nbound.p1.y + (zone_h >> min(level, max_depth_y))
find_floor_min_lz:
slt $a0, max_depth_z, level
bnez $a0, find_floor_nbound_z2
# find_floor_minl_lz:
srlv $a0, zone_d, max_depth_z # $a0 = zone_d >> min(level, max_depth_z)
find_floor_minr_lz:
srlv $a0, zone_d, level # ...
find_floor_nbound_z2:
nbound_p2_z = nbound_p1_z
addu nbound_p1_z, $a0 # nbound.p2.z = nbound.p1.z + (zone_d >> min(level, max_depth_z))
find_floor_test_collider_intersects_node_2: # skip this node if collider bound is entirely below, to the right, or in front of node bound
slt $a0, nbound_p2_x, cbound_p1_x
bnez $a0, find_floor_continue
slt $a0, nbound_p2_y, cbound_p1_y
bnez $a0, find_floor_continue
slt $a0, nbound_p2_z, cbound_p1_z
bnez $a0, find_floor_continue
find_floor_collider_intersects_node:
li $a0, 6
beq type, $a0, find_floor_case_0 # if type == 3, goto case 0
li $a0, 8
beq type, $a0, find_floor_case_0 # if type == 4, goto case 0
andi $a0, $a1, 0x3F0
beqz $a0, find_floor_case_1 # if subtype == 0, goto case 1
sltiu $a0, 0x270
beqz $a0, find_floor_case_1 # if subtype > 38, goto case 1
nop
find_floor_case_0: # else, type==3 || type==4 || (subtype > 0 && subtype <= 38)
# call callback function pointer in scratch memory
li $a0, 0x1F8000F0
sw $at, 0($a0) # temporarily preserve value of running sum for nonzero type (so $at can be used)
li $at, 0x1F800070 # get pointer to another temp scratch location
sw $v1, 0($at)
sw $a1, 4($at) # note: $a1 = (result->node << 1) | 1; passed as arg 2 to the function below
sw $a2, 8($at) # note: $a2 = count_t0; passed as arg 3 to the function below
sw $a3, 0xC($at) # note: $a3 = sum_y2_t0; passed as arg 4 to the function below
sw $t0, 0x10($at)
sw $t1, 0x14($at)
sw $t2, 0x18($at)
sw $t3, 0x1C($at)
sw $t4, 0x20($at)
sw $t5, 0x24($at)
sw $t6, 0x28($at)
sw $t7, 0x2C($at) # save values of regs that are needed
li $a0, 0x1F8000E4
lw $v0, 0($a0) # restore callback function pointer arg
lw $a0, 8($a0) # restore obj arg as arg 1
jalr $v0 # call the function
nop
li $at, 0x1F800070 # get pointer to temp scratch location
lw $v1, 0($at)
lw $a1, 4($at)
lw $a2, 8($at)
lw $a3, 0xC($at)
lw $t0, 0x10($at)
lw $t1, 0x14($at)
lw $t2, 0x18($at)
lw $t3, 0x1C($at)
lw $t4, 0x20($at)
lw $t5, 0x24($at)
lw $t6, 0x28($at)
lw $t7, 0x2C($at) # restore values of regs saved above
li $a0, 0x1F8000F0 # also get pointer to preserved running sum for nonzero type
lw $at, 0($a0) # restore it
bnez $v0, find_floor_continue # fall through to case 1 if the function returned 0, else continue loop
find_floor_case_1:
find_floor_test_y2:
slt $a0, max_y, nbound_p2_y
bnez $a0, find_floor_continue # continue loop if nbound.p2.y > max_y
find_floor_y2_lt_ty1: # else test the node type...
nop
beqz type, find_floor_y2_lt_ty1_type_0 # goto type 0 case if node type is 0
find_floor_y2_lt_ty1_type_neq0: # else node type != 0
nop
addiu count_tn0, 1 # increment number of type != 0 nodes found that have passed the test
bgez $zero, find_floor_continue # continue
addu $at, nbound_p2_y # also add to running sum of y2 values of such nodes
find_floor_y2_lt_ty1_type_0:
addiu count_t0, 1 # increment number of type 0 nodes found that have passed the test
addu sum_y2_t0, nbound_p2_y # also add to running sum of y2 values of such nodes
find_floor_continue:
bgez $zero, find_floor_loop # loop
addiu result, 8 # increment result pointer to next result
find_floor_end:
li $t2, 0x1F8000E0 # restore args from scratch
lw $t2, 0($t2) # get default value to use when count == 0
li $a0, 0x1F8000E8
lw $a0, 0($a0) # get pointer to summary results part of query
find_floor_test_count_type_0:
beqz count_t0, find_floor_test_count_type_neq0 # skip computing avg y2 for type 0 nodes if count is 0
sw $t2, 4($a0) # ...and instead store default value in summary results
find_floor_avg_y2_type_0:
div $a3, $a2
mflo $v0
sw $v0, 4($a0) # else compute and store avg in summary results (running sum/count = $a3/$a2)
find_floor_test_count_type_neq0:
beqz $t1, loc_80038DAC # skip computing avg y2 for type != 0 nodes if count is 0
sw $t2, 8($a0) # ...and instead store default value in summary results
find_floor_avg_y2_type_neq0:
div $at, $t1
mflo $v0
sw $v0, 8($a0) # else compute and store avg in summary results (running sum/count = $at/$t1)
find_floor_ret:
sload
jr $ra # return
nop
#
# compute the average top face y locations of query result nodes
# of either of the input types
#
# returns the average y
#
# a0 = obj
# a1 = query
# a2 = nodes_bound (input bound queried with)
# a3 = collider_bound (bound to test against query results)
# 0x10($sp) = type_a
# 0x14($sp) = type_b
# 0x18($sp) = default_y
#
RFindCeilY:
result = $a1
nbound_p1_x = $t3
nbound_p1_y = $t4
nbound_p1_z = $t5
cbound_p1_x = $t6
cbound_p1_y = $t7
cbound_p1_z = $s0
cbound_p2_x = $s1
cbound_p2_y = $s2
cbound_p2_z = $s3
zone_w = $s4
zone_h = $s5
zone_d = $s6
max_depth_x = $s7
max_depth_y = $t8
max_depth_z = $t9
type_a = $t0
type_b = $t1
default_y = $t2
arg_10 = 0x10
arg_14 = 0x14
arg_18 = 0x18
ssave
lw type_a, arg_10($sp) # get type_a arg
lw type_b, arg_14($sp) # get type_b arg
lw default_y, arg_18($sp) # get default_y arg
lw $sp, 0($a2)
lw $fp, 4($a2)
lw $ra, 8($a2) # $sp,$fp,$ra = nodes_bound.p1
lw cbound_p1_x, 0($a3)
lw cbound_p1_y, 4($a3)
lw cbound_p1_z, 8($a3)
lw cbound_p2_x, 0xC($a3)
lw cbound_p2_y, 0x10($a3)
lw cbound_p2_z, 0x14($a3) # cbound = *collider_bound
count_y2_t0 = $a2
sum_y2_t0 = $a3
move sum_y2, $zero # initialize running sum of y2 values for found nodes
move count, $zero # initialize count of found nodes
addiu type_a, -1
sll type_a, 1 # shift type_a up as the type bits of a node
addiu type_b, -1
sll type_a, 1 # shift type_b up as the type bits of a node
find_ceil_loop:
find_ceil_result_test:
lw $at, 0(result) # $at = (result->x << 16) | result->is_node
lw $v0, 4(result) # $v0 = (result->z << 16) | result->y
li $gp, 0xFFFF # load lower hword mask
and $v1, $at, $gp # $a1 = result->value or result->is_node
beq $v1, $gp, find_ceil_end # goto end if result->value is null node
nop
bnez $v1, find_ceil_result_is_node # if (result->is_node) then goto node case
nop
find_ceil_result_is_rect: # else result is a rect; let result_rect = (zone_query_result_rect*)result
srl zone_w, $at, 16
sll zone_w, 8 # zone_w = result_rect->w << 8
andi zone_h, $v0, 0xFFFF
sll zone_h, 8 # zone_h = result_rect->h << 8
srl zone_d, $v0, 16
sll zone_d, 8 # zone_d = result_rect->d << 8
lw $at, 8(result) # $at = (result_rect->max_depth_x << 16) | result_rect->unused
lw $v0, 0xC(result) # $v0 = (result_rect->max_depth_z << 16) | result_rect->max_depth_y
srl max_depth_x, $at, 16 # max_depth_x = result_rect->max_depth_x
andi max_depth_y, $v0, 0xFFFF # max_depth_y = result_rect->max_depth_y
srl max_depth_z, $v0, 16 # max_depth_z = result_rect->max_depth_z
bgez $zero, find_ceil_loop # continue
addiu result, 0x10 # increment result pointer to next result
find_ceil_result_is_node:
andi $v1, $at, 0xFFF8
srl $v1, 2
ori $v1, 1 # $v1 = (result->node << 1) | 1
andi $gp, $v1, 0xE # $gp = node->type << 1
find_ceil_test_type_a:
beq $gp, type_a, find_ceil_type_ab # goto find_ceil_type_ab if node is type a
nop
find_ceil_test_type_b:
bne $gp, type_b, find_ceil_continue # continue if node is not type a or b
nop
find_ceil_type_ab:
andi $gp, $at, 7 # level = result->level
srl nbound_p1_x, $a0, 16 # nbound.p1.x = result->x
andi nbound_p1_y, $v0, 0xFFFF # nbound.p1.y = result->y
srl nbound_p1_z, $v0, 16 # nbound.p1.z = result->z
sll nbound_p1_x, 16 # shift up sign bit
sra nbound_p1_x, 12 # nbound.p1.x = (result->x << 4)
sll nbound_p1_y, 16
sra nbound_p1_y, 12 # nbound.p1.y = (result->y << 4)
sll nbound_p1_z, 16
sra nbound_p1_z, 12 # nbound.p1.z = (result->z << 4)
addu nbound_p1_x, $sp, nbound_p1_x
addu nbound_p1_y, $fp, nbound_p1_y
addu nbound_p1_z, $ra, nbound_p1_z # n_bound.p1 = (nodes_bound << 4) + nbound (convert local bound to absolute bound)
move $v0, nbound_p1_y # ***preserve y1 value
find_ceil_test_collider_intersects_node: # skip this node if the collider bound is entirely above, left of, or behind the node bound
slt $at, cbound_p2_x, nbound_p1_x
bnez $at, find_ceil_continue # skip if collider_bound.p2.x < n_bound.p1.x
slt $at, cbound_p2_y, nbound_p1_y
bnez $at, find_ceil_continue # skip if collider_bound.p2.y < n_bound.p1.y
slt $at, cbound_p2_z, nbound_p1_z
bnez $at, find_ceil_continue # skip if collider_bound.p2.z < n_bound.p1.z
find_ceil_min_lx:
slt $at, max_depth_x, level
bnez $at, find_ceil_nbound_x2
# find_ceil_minl_lx:
srlv $at, zone_w, max_depth_x # $a0 = zone_w >> min(level, max_depth_x)
find_ceil_minr_lx: # ...
srlv $at, zone_w, level # ...
find_ceil_nbound_x2:
nbound_p2_x = nbound_p1_x
addu nbound_p1_x, $at # nbound.p2.x = nbound.p1.x + (zone_w >> min(level, max_depth_x))
find_ceil_min_ly:
slt $at, max_depth_y, level
bnez $at, find_ceil_nbound_y2
# find_ceil_minl_ly:
srlv $at, zone_h, max_depth_y # $a0 = zone_h >> min(level, max_depth_y)
find_ceil_minr_ly: # ...
srlv $at, zone_h, level # ...
find_ceil_nbound_y2:
nbound_p2_y = nbound_p1_y
addu nbound_p1_y, $at # nbound.p2.y = nbound.p1.y + (zone_h >> min(level, max_depth_y))
find_ceil_min_lz:
slt $at, max_depth_z, level
bnez $at, find_ceil_nbound_z2
# find_ceil_minl_lz:
srlv $at, zone_d, max_depth_z # $a0 = zone_d >> min(level, max_depth_z)
find_ceil_minr_lz:
srlv $at, zone_d, level # ...
find_ceil_nbound_z2:
nbound_p2_z = nbound_p1_z
addu nbound_p1_z, $at # nbound.p2.z = nbound.p1.z + (zone_d >> min(level, max_depth_z))
find_ceil_test_collider_intersects_node_2: # skip this node if collider bound is entirely below, to the right, or in front of node bound
slt $at, nbound_p2_x, cbound_p1_x
bnez $at, find_ceil_continue
slt $at, nbound_p2_y, cbound_p1_y
bnez $at, find_ceil_continue
slt $at, nbound_p2_z, cbound_p1_z
bnez $at, find_ceil_continue
find_ceil_collider_intersects_node:
addiu count, 1 # increment number of nodes found that have passed the test
addu sum_y1, $v0 # also add to running sum of y1 values of such nodes
find_ceil_continue:
bgez $zero, find_ceil_loop # loop
addiu result, 8 # increment result pointer to next result
find_ceil_end:
find_ceil_test_count:
beqz count, find_ceil_count_eq_0 # skip computing avg y1 for nodes if count is 0
nop
find_ceil_count_gt0:
find_ceil_avg_y1:
div sum_y1, count
mflo $v0 # else compute and return avg (running sum/count)
sload
jr $ra
nop
find_ceil_count_eq_0:
move $v0, default_y # return default y result value
sload
jr $ra
nop
/*
Side note on rotation matrices and euler angle component naming conventions.
In the crash engine, an object's rotation matrix is computed from its
YXY-type euler-angle-based orientation (which is computed by converting
from the default tait bryan angle representation). [note: this excludes
sprites, for which the rotation matrix is computed from the angle as a
ZYX-type (ZXY??) tait-bryan angle]
The rotation matrix for a YXY-type euler angle is given by the following
matrix product:
R = Ry1 * Rx2 * Ry3
such that
Rxi = [ 1, 0, 0] [rotation in yz plane; in y direction; about x axis]
[ 0, ci, -si] (1st column and row are identity)
[ 0, si, ci] ('pitch' or 'flip')
Ryi = [ ci, 0, si] [rotation in xz plane; in x direction; about y axis]
[ 0, 1, 0] (2nd column and row are identity)
[-si, 0, ci] ('yaw' or 'spin')
Rzi = [ ci, -si, 0] [rotation in xy plane; in z direction; about z axis]
[ si, ci, 0] (3rd column and row are identity)
[ 0, 0, 1] ('roll')
...where
si = sin(a_i),
ci = cos(a_i),
and a_i represents the i'th component of the euler angle.
In computing the matrix product we get the following:
Ry1 * Rx2 * Ry3
= [ c1, 0, s1][ 1, 0 0]
[ 0, 1, 0][ 0, c2, -s2] * Ry3
[-s1, 0, c1][ 0, s2, c2]
= [ c1, s1s2, s1c2][ c3, 0, s3]
[ 0, c2, s2][ 0, 1, 0]
[-s1, c1s2, c1c2][-s3 0, c3]
= [ c1c3 - s1c2s3, s1s2, c1s3 + s1c2c3]
[ s2s3, c2, -s2c3]
[-s1c3 - c1c2s3, c1s2, -s1s3 + c1c2c3]
The naming convention currently used for rotation vectors/euler angles,
in order of components/structure field name, is:
'y' = a_2 (offset 0x0)
'x' = a_3 (offset 0x4)
'z' = a_1 (offset 0x8)
This means that (by current conventions):
s1 = sin(a_1) = sin(z), c1 = cos(a_1) = cos(z)
s2 = sin(a_2) = sin(y), c2 = cos(a_2) = cos(y)
s3 = sin(a_3) = sin(x), c3 = cos(a_3) = cos(x)
Therefore, calculations in the below annotations should be validated
using these equalities.
*/
#
# non-inline version of sin
#
# returns a 12 bit fractional fixed point result
#
# a0 = 12-bit angle
#
sin:
li $v1, sin_table
msin sin, $v1, $a0, $v0
jr $ra
#
# non-inline version of cos
#
# returns a 12 bit fractional fixed point result
#
# a0 = 12-bit angle
#
cos:
li $v1, sin_table
mcos cos, $v1, $a0, $v0
jr $ra
#
# Calculate the rotation matrix to use for object geometry transformation
# and color and light matrices to use for phong shading.
#
# The exact calculations are:
#
# GTE R = D(vs*hs)*m_rot*RY(rz)*RX(ry)*RY(rx)*S
# GTE L = RY(-rz)*RX(-ry)*RY(-rx)*lm
# GTE LRGB = cm
# GTE BK = (cc*ci) >> 8 [intensity is 8 bit fractional fixed point?]
#
# where D(v) = diagonal matrix for vector v
# vs = vectors->scale
# hs = header->scale
# rx = vectors->rot.x - vectors->rot.z [conversion from tait-bryan to euler]
# ry = vectors->rot.y
# rz = vectors->rot.z
# RX(a) = x rotation matrix for angle a
# RY(a) = y rotation matrix for angle a
# S = [1, 0, 0]
# [0, -5/8, 0]
# [0, 0, -1]
# lm = colors->light_matrix (possibly the transpose?)
# with first row negated when vectors->scale.x < 0
# cm = colors->color_matrix (possibly the transpose?)
# cc = colors->color (rgb value)
# ci = colors->intensity
#
# for light mat calcs only:
# if scale.x < 0 then rx = -vectors->rot.x - vectors->rot.z
#
# a0 = m_rot: rotation matrix (16-bit)
# a1 = header: tgeo header item
# a2 = vectors: gool vectors
# a3 = colors: gool colors
#
RGteCalcObjectMatrices:
rot_y = $sp
rot_x = $fp
rot_z = $gp
ssave
li $v1, sin_table # load pointer to sin table
lw rot_z, 0x14($a2)
lw rot_x, 0x10($a2)
lw rot_y, 0xC($a2) # rot = *vectors->rot
subu rot_x, rot_z, rot_x # needed for tait-bryan angles
negu rot_x, rot_x # rot.x = vectors->rot.x - vectors=>rot.z
andi rot_z, 0xFFF
andi rot_y, 0xFFF
andi rot_x, 0xFFF # rot = angle12(rot) [limit to 12 bit angle values]
calc_object_light_matrices_sin:
msin z1, $v1, $t5, $gp
msin y1, $v1, $t6, $sp
msin x1, $v1, $t7, $fp
mcos z1, $v1, $t1, $gp
mcos y1, $v1, $t2, $sp
mcos x1, $v1, $t4, $fp
calc_object_light_matrices_start:
# note that results of sin/cos are 12 bit fractional fixed point values
# thus, multiplying 2 of these values will produce a 24 bit fractional
# fixed point value
# therefore it is necessary to shift results of such multiplications
# to the right by 12 to convert back to a 12 bit fractional fixed point value
# the below annotations do not show these shifts as they are considered
# part of the multiplication, and do not show result values direct from
# multiplication as shifted left by 12 (as in most cases they are shifted
# right before any further usage)
mult $t1, $t7 # mres = cos(z)sin(x)
andi $s0, $t7, 0xFFFF # $s0 = (int16_t)sin(x)
andi $t1, 0xFFFF # $t1 = (int16_t)cos(z)
andi $t5, 0xFFFF # $t5 = (int16_t)sin(z)
andi $t6, 0xFFFF # $t6 = (int16_t)sin(y)
andi $t3, $t2, 0xFFFF # $t3 = (int16_t)cos(y)
andi $t4, 0xFFFF # $t4 = (int16_t)cos(x); future annotations assume implicit cast
cos_z = $t1
cos_y = $t3
cos_x = $t4
sin_z = $t5
sin_y = $t6
sin_x = $s0
ctc2 $zero, $1 # set GTE R13R21 = 0
ctc2 $zero, $3 # set GTE R31R32 = 0
mtc2 sin_y, $1 # set GTE VZ0 = sin(y)
sll $at, cos_x, 16
or $at, sin_z
mtc2 $at, $0 # set GTE VXY0 = cos(x) << 16 | sin(z)
# GTE V = [sin(z)]
# [cos(x)]
# [sin(y)]
mflo $fp # $fp = mres = cos(z)sin(x)
ctc2 cos_y, $0 # set GTE R11R12 = cos(y)
ctc2 cos_z, $2 # set GTE R22R23 = cos(z)
ctc2 sin_z, $4 # set GTE R33 = sin(z)
# GTE R = [cos(y), 0, 0]
# [ 0, cos(z), 0]
# [ 0, 0, sin(z)]
sra $fp, 12
mult $fp, $t2 # mres = cos(z)sin(x)cos(y)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
ctc2 cos_x, $0 # set GTE R11R12 = cos(x)
ctc2 sin_y, $2 # set GTE R22R23 = sin(y)
ctc2 sin_x, $4 # set GTE R33 = sin(x)
# GTE R = [cos(x), 0, 0]
# [ 0, sin(y), 0]
# [ 0, 0, sin(x)]
mfc2 $sp, $9 # $sp = rotation result component 1
mflo $t8
sra $t8, 12 # $t8 = mres = cos(z)sin(x)cos(y)
mfc2 $gp, $10 # $gp = rotation result component 2
mfc2 $s1, $11 # $s1 = rotation result component 3
# $sp,$gp,$s1 = [cos(y), 0, 0][sin(z)] = [cos(y)sin(z)]
# [ 0, cos(z), 0][cos(x)] [cos(z)cos(x)]
# [ 0, 0, sin(z)][sin(y)] [sin(z)sin(y)]
mult $sp, $t7 # mres = cos(y)sin(z)sin(x)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
ctc2 sin_x, $0 # set GTE R11R12 = sin(x)
andi $at, $sp, 0xFFFF # $at = (uint16_t)cos(y)sin(z)
ctc2 $at, $2 # set GTE R22R23 = cos(y)sin(z)
ctc2 cos_z, $4 # set GTE R33 = cos(z)
mfc2 $at, $9 # $at = rotation result component 1
mflo $s7 # $s7 = mres = cos(y)sin(z)sin(x)
mfc2 $s2, $10 # $s2 = rotation result component 2
mfc2 $s3, $11 # $s3 = rotation result component 3
# $at,$s2,$s3 = [cos(x), 0, 0][sin(z)] = [cos(x)sin(z)]
# [ 0, sin(y), 0][cos(x)] [sin(y)cos(x)]
# [ 0, 0, sin(x)][sin(y)] [sin(x)sin(y)]
mult $gp, $t2 # mres = cos(z)cos(x)cos(y)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
sra $s7, 12
mfc2 $s4, $9
mfc2 $s5, $10
mfc2 $s6, $11 # $s4,$s5,s6 = rotation result
# $s4,$s5,$s6 = [sin(x), 0, 0][sin(z)] = [sin(x)sin(z)]
# [ 0, cos(y)sin(z), 0][cos(x)] [cos(y)sin(z)cos(x)]
# [ 0, 0, cos(z)][sin(y)] [cos(z)sin(y)]
mflo $t9
sra $t9, 12 # $t9 = mres = cos(z)cos(x)cos(y)
negu $s2, $s2 # $s2 = -sin(y)cos(x)
subu $s7, $gp, $s7 # $s7 = cos(z)cos(x) - cos(y)sin(z)sin(x)
addu $s5, $fp, $s5 # $s5 = cos(z)sin(x) + cos(y)sin(z)cos(x)
addu $t8, $at, $t8
negu $t8, $t8 # $t8 = -cos(x)sin(z) - cos(z)sin(x)cos(y)
subu $t9, $s4 # $t9 = -sin(x)sin(z) + cos(z)cos(x)cos(y)
# $t1 = cos_z
# $t3 = cos_y
# $t4 = cos_x
# $t5 = sin_z
# $t6 = sin_y
lw $t1, 0($a0)
lw $t3, 4($a0)
lw $t4, 8($a0)
lw $t5, 0xC($a0)
lw $t6, 0x10($a0)
ctc2 $t1, $0
ctc2 $t3, $1
ctc2 $t4, $2
ctc2 $t5, $3
ctc2 $t6, $4 # set GTE R = m_rot (matrix passed as argument)
# GTE R = m_rot
lw $t1, 0x18($a2) # $t1 = vectors->scale.x
lw $t3, 4($a1) # $t3 = header->scale.x
mtc2 $s7, $9 # set GTE IR1 = cos(z)cos(x) - cos(y)sin(z)sin(x)
mtc2 $s3, $10 # set GTE IR2 = sin(x)sin(y)
mtc2 $t8, $11 # set GTE IR3 = -cos(x)sin(z) - cos(z)sin(x)cos(y)
# GTE IR1 = [ cos(z)cos(x) - cos(y)sin(z)sin(x)]
# GTE IR2 = [ sin(x)sin(y) ]
# GTE IR3 = [-cos(x)sin(z) - cos(z)sin(x)cos(y)]
mult $t1, $t3 # mres = vectors->scale.x * header->scale.x
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
lw $t1, 0x1C($a2) # $t1 = vectors->scale.y
lw $t3, 8($a1) # $t3 = header->scale.y
mfc2 $s7, $9
mfc2 $s3, $10
mfc2 $t8, $11 # $s7,$s3,$t8 = rotation result
mflo $t4 # $t4 = mres = vectors->scale.x * header->scale.x
# [ cos(z)cos(x) - cos(y)sin(z)sin(x)]
# $s7,$s3,$t8 = m_rot * [ sin(x)sin(y) ]
# [-cos(x)sin(z) - cos(z)sin(x)cos(y)]
mtc2 $s1, $9 # set GTE IR1 = sin(z)sin(y)
mtc2 $t2, $10 # set GTE IR2 = cos(y)
mtc2 $s6, $11 # set GTE IR3 = cos(z)sin(y)
# GTE IR1 = [sin(z)sin(y)]
# GTE IR2 = [ cos(y) ]
# GTE IR3 = [cos(z)sin(y)]
mult $t1, $t3 # mres = vectors->scale.y * header->scale.y
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
lw $t1, 0x20($a2) # $t1 = vectors->scale.z
lw $t3, 0xC($a1) # $t3 = header->scale.z
mfc2 $s1, $9
mfc2 $t2, $10
mfc2 $s6, $11 # $s1,$t2,$t6 = rotation result
# [sin(z)sin(y)]
# $s1,$t2,$s6 = m_rot * [ cos(y) ]
# [cos(z)sin(y)]
sra $t4, 12
mflo $t5 # $t5 = mres = vectors->scale.y * header->scale.y
mtc2 $s5, $9 # set GTE IR1 = cos(z)sin(x) + cos(y)sin(z)cos(x)
mtc2 $s2, $10 # set GTE IR2 = -sin(y)cos(x)
mtc2 $t9, $11 # set GTE IR3 = -sin(x)sin(z) + cos(z)cos(x)cos(y)
# GTE IR1 = [ cos(z)sin(x) + cos(y)sin(z)cos(x)]
# GTE IR2 = [ -sin(y)cos(x) ]
# GTE IR3 = [-sin(x)sin(z) + cos(z)cos(x)cos(y)]
mult $t1, $t3 # mres = vectors->scale.z * header->scale.z
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
sra $t5, 12
mfc2 $s5, $9
mfc2 $s2, $10
mfc2 $t9, $11 # $s5,$s2,$t9 = rotation result
# [ cos(z)sin(x) + cos(y)sin(z)cos(x)]
# $s5,$s2,$t9 = m_rot * [ -sin(y)cos(x) ]
# [-sin(x)sin(z) + cos(z)cos(x)cos(y)]
andi $t4, 0xFFFF # $t4 = (int16_t)(vectors->scale.x * header->scale.x)
andi $t5, 0xFFFF # $t5 = (int16_t)(vectors->scale.y * header->scale.y)
mflo $t6 # ...
sra $t6, 12 # ...
andi $t6, 0xFFFF # $t6 = (int16_t)(vectors->scale.z * header->scale.z)
# [$t4] [(int16_t)(vectors->scale.x * header->scale.x)]
# let scale = [$t5] = [(int16_t)(vectors->scale.y * header->scale.y)]
# [$t6] [(int16_t)(vectors->scale.z * header->scale.z)]
ctc2 $t4, $0 # set GTE R11R12 = scale.x
ctc2 $zero, $1 # set GTE R13R21 = 0
ctc2 $t5, $2 # set GTE R22R23 = scale.y
ctc2 $zero, $3 # set GTE_R31R32 = 0
ctc2 $t6, $4 # set GTE R33 = scale.z
# GTE R = [scale.x, 0, 0]
# [ 0, scale.y, 0]
# [ 0, 0, scale.z]
# [$s7, $s1, $s5] [ cos(z)cos(x) - cos(y)sin(z)sin(x), sin(z)sin(y), cos(z)sin(x) + cos(y)sin(z)cos(x)]
# let m_rot2 = [$s3, $t2, $s2] = m_rot * [ sin(x)sin(y), cos(y), -sin(y)cos(x)]
# [$t8, $s6, $s9] [-cos(x)sin(z) - cos(z)sin(x)cos(y), cos(z)sin(y), -sin(x)sin(z) + cos(z)cos(x)cos(y)]
mtc2 $s3, $9 # set GTE IR1 = m_rot2_21
mtc2 $t2, $10 # set GTE IR2 = m_rot2_22
mtc2 $s2, $11 # set GTE IR3 = m_rot2_23
# GTE IR1 = [m_rot2_21]
# GTE IR2 = [m_rot2_22]
# GTE IR3 = [m_rot2_23]
nop
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
nop
mfc2 $s3, $9
mfc2 $t2, $10
mfc2 $s2, $11 # $s3,$t2,$s2 = rotation result
# $s3,$t2,$s2 = [scale.x, 0, 0][m_rot2_21]
# [ 0, scale.y, 0][m_rot2_22]
# [ 0, 0, scale.z][m_rot2_23]
# let result_y be the current values of $s3,$t2,$s2
mtc2 $t8, $9 # set GTE IR1 = m_rot2_31
mtc2 $s6, $10 # set GTE_IR2 = m_rot2_32
mtc2 $t9, $11 # set GTE_IR3 = m_rot2_33
# GTE IR1 = [m_rot2_31]
# GTE IR2 = [m_rot2_32]
# GTE IR3 = [m_rot2_33]
move $t1, $s3 # $t1 = result_y[0]
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
move $t3, $t2 # $t3 = result_y[1]
mfc2 $t8, $9
mfc2 $s6, $10
mfc2 $t9, $11 # $t8,$s6,$s9 = rotation result
# $t8,$s6,$s9 = [scale.x, 0, 0][m_rot2_31]
# [ 0, scale.y, 0][m_rot2_32]
# [ 0, 0, scale.z][m_rot2_33]
# let result_z be the current values of $t8,$s6,$s9
mtc2 $s7, $9 # set GTE IR1 = m_rot2_11
mtc2 $s1, $10 # set GTE IR2 = m_rot2_12
mtc2 $s5, $11 # set GTE IR3 = m_rot2_13
# GTE IR1 = [m_rot2_11]
# GTE IR2 = [m_rot2_12]
# GTE IR3 = [m_rot2_13]
move $t4, $s2 # $t4 = result_y[2]
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
sll $s3, 2 # $s3 = result_y[0] * 4
mfc2 $s7, $9
mfc2 $s1, $10
mfc2 $s5, $11 # $s7,$s1,$s5 = rotation result
# $s7,$s1,$s5 = [scale.x, 0, 0][m_rot2_11]
# [ 0, scale.y, 0][m_rot2_12]
# [ 0, 0, scale.z][m_rot2_13]
# let result_x be the current values of $s7,$s1,$s5
addu $s3, $t1 # $s3 = (result_y[0] * 4) + result_y[0] = result_y[0]*5
sra $s3, 3 # $s3 = (result_y[0]*5)/8 = result_y[0]*(5/8)
negu $s3, $s3 # $s3 = -(5/8)*result_y[0]
sll $t2, 2
addu $t2, $t3
sra $t2, 3
negu $t2, $t2 # $t2 = -(5/8)*result_y[1]
sll $s2, 2
addu $s2, $t4
sra $s2, 3
negu $s2, $s2 # $s2 = -(5/8)*result_y[2]
negu $t8, $t8 # $t8 = -result_z[0]
negu $s6, $s6 # $s6 = -result_z[1]
negu $t9, $t9 # $t9 = -result_z[2]
andi $at, $s7, 0xFFFF
sll $t1, $s1, 16
or $t1, $at # $t1 = (result_x[1] << 16) | result_x[0]
andi $at, $s5, 0xFFFF
sll $t3, $s3, 16
or $t3, $at # $t3 = ((-(5/8)*result_y[0]) << 16) | result_x[2]
andi $at, $t2, 0xFFFF
sll $t4, $s2, 16
or $t4, $at # $t4 = ((-(5/8)*result_y[2]) << 16) | (-(5/8)*result_y[1])
andi $at, $t8, 0xFFFF
sll $t5, $s6, 16
or $t5, $at # $t5 = (-result_z[1] << 16) | -result_z[0]
ctc2 $t1, $0 # set GTE R11R12 = (result_x[1] << 16) | result_x[0]
ctc2 $t3, $1 # set GTE R13R21 = ((-(5/8)*result_y[0]) << 16) | result_x[2]
ctc2 $t4, $2 # set GTE R22R23 = ((-(5/8)*result_y[2]) << 16) | (-(5/8)*result_y[1])
ctc2 $t5, $3 # set GTE R31R32 = (-result_z[1] << 16) | -result_z[0]
ctc2 $t9, $4 # set GTE R33 = -result_z[2]
# GTE R = [ result_x[0], result_x[1], result_x[2]]
# [-(5/8)*result_y[0], -(5/8)*result_y[1], -(5/8)*result_y[2]]
# [ -result_z[0], -result_z[1], -result_z[2]]
lw $at, 0x18($a2) # $at = vectors.scale.x
lw $fp, 0x14($a2) # $fp = vectors->rot.z
lw $gp, 0x10($a2) # $gp = vectors->rot.x
calc_object_light_matrices_test_scale_x_lt0_1:
slt $a0, $at, $zero
bnez $a0, calc_object_light_matrices_scale_x_lt0_1
calc_object_light_matrices_scale_x_gteq0_1: # $sp = vectors->rot.y
lw $sp, 0xC($a2)
bgez $zero, calc_object_light_matrices_2
subu $gp, $fp, $gp # $gp = vectors->rot.z - vectors->rot.x
calc_object_light_matrices_scale_x_lt0_1:
addu $gp, $fp, $gp # $gp = vectors->rot.z + vectors->rot.x
calc_object_light_matrices_2:
negu $fp, $fp # $fp = -vectors->rot.z
negu $sp, $sp # $sp = -vectors->rot.y
andi $gp, 0xFFF
andi $sp, 0xFFF
andi $fp, 0xFFF # $gp,$sp,$fp = angle12($gp,$sp,$fp)
msin z2, $v1, $t5, $gp
msin y2, $v1, $t6, $sp
msin x2, $v1, $t7, $fp
mcos z2, $v1, $t1, $gp
mcos y2, $v1, $t2, $sp
mcos x2, $v1, $t4, $fp
mult $t1, $t7 # mres = cos(z)sin(x)
andi $s0, $t7, 0xFFFF # $s0 = (int16_t)sin(x)
andi $t1, 0xFFFF # $t1 = (int16_t)cos(z)
andi $t5, 0xFFFF # $t5 = (int16_t)sin(z)
andi $t6, 0xFFFF # $t6 = (int16_t)sin(y)
andi $t3, $t2, 0xFFFF # $t3 = (int16_t)cos(y)
andi $t4, 0xFFFF # $t4 = (int16_t)cos(x);
cos_z = $t1
cos_y = $t3
cos_x = $t4
sin_z = $t5
sin_y = $t6
sin_x = $s0
ctc2 $zero, $9 # set GTE L13L21 = 0
ctc2 $zero, $11 # set GTE L31L32 = 0
mtc2 sin_y, $1 # set GTE VZ0 = sin(y)
sll $at, cos_x, 16
or $at, sin_z
mtc2 $at, $0 # set GTE VXY0 = cos(x) << 16 | sin(z)
# GTE V = [sin(z)]
# [cos(x)]
# [sin(y)]
mflo $fp # $fp = mres = cos(z)sin(x)
ctc2 cos_y, $8 # set GTE L11L12 = cos(y)
ctc2 cos_z, $10 # set GTE L22L23 = cos(z)
ctc2 sin_z, $12 # set GTE L33 = sin(z)
# GTE L = [cos(y), 0, 0]
# [ 0, cos(z), 0]
# [ 0, 0, sin(z)]
sra $fp, 12
mult $fp, $t2 # mres = cos(z)sin(x)cos(y)
cop2 0x4A6012 # multiply V0 by L (MVMVA, llv0)
ctc2 cos_x, $8 # set GTE L11L12 = cos(x)
ctc2 sin_y, $10 # set GTE L22L23 = sin(y)
ctc2 sin_x, $12 # set GTE L33 = sin(x)
# GTE L = [cos(x), 0, 0]
# [ 0, sin(y), 0]
# [ 0, 0, sin(x)]
mfc2 $sp, $9 # $sp = matrix mult result component 1
mflo $t8
sra $t8, 12 # $t8 = mres = cos(z)sin(x)cos(y)
mfc2 $gp, $10 # $gp = matrix mult result component 2
mfc2 $s1, $11 # $s1 = matrix mult result component 3
# $sp,$gp,$s1 = [cos(y), 0, 0][sin(z)] = [cos(y)sin(z)]
# [ 0, cos(z), 0][cos(x)] [cos(z)cos(x)]
# [ 0, 0, sin(z)][sin(y)] [sin(z)sin(y)]
mult $sp, $t7 # mres = cos(y)sin(z)sin(x)
cop2 0x4A6012 # multiply V0 by L (MVMVA, llv0)
ctc2 sin_x, $8 # set GTE L11L12 = sin(x)
andi $at, $sp, 0xFFFF # $at = (uint16_t)cos(y)sin(z)
ctc2 $at, $10 # set GTE L22L23 = cos(y)sin(z)
ctc2 cos_z, $12 # set GTE L33 = cos(z)
# GTE L = [sin(x), 0, 0]
# [ 0, cos(y)sin(z), 0]
# [ 0, 0, cos(z)]
mfc2 $at, $9 # $at = matrix mult result component 1
mflo $s7 # $s7 = mres = cos(y)sin(z)sin(x)
mfc2 $s2, $10 # $s2 = matrix mult result component 2
mfc2 $s3, $11 # $s3 = matrix mult result component 3
# $at,$s2,$s3 = [cos(x), 0, 0][sin(z)] = [cos(x)sin(z)]
# [ 0, sin(y), 0][cos(x)] [sin(y)cos(x)]
# [ 0, 0, sin(x)][sin(y)] [sin(x)sin(y)]
mult $gp, $t2 # mres = cos(z)cos(x)cos(y)
cop2 0x4A6012 # multiply V0 by L (MVMVA, llv0)
sra $s7, 12
mfc2 $s4, $9
mfc2 $s5, $10
mfc2 $s6, $11 # $s4,$s5,s6 = matrix mult result
# $S4,$s5,$s6 = [sin(x), 0, 0][sin(z)] = [ sin(x)sin(z) ]
# [ 0, cos(y)sin(z), 0][cos(x)] [cos(y)sin(z)cos(x)]
# [ 0, 0, cos(z)][sin(y)] [ cos(z)sin(y) ]
mflo $t9
sra $t9, 12 # $t9 = mres = cos(z)cos(x)cos(y)
negu $s2, $s2 # $s2 = -sin(y)cos(x)
subu $s7, $gp, $s7 # $s7 = cos(z)cos(x) - cos(y)sin(z)sin(x)
addu $s5, $fp, $s5 # $s5 = cos(z)sin(x) + cos(y)sin(z)cos(x)
addu $t8, $at, $t8
negu $t8, $t8 # $t8 = -cos(x)sin(z) - cos(z)sin(x)cos(y)
subu $t9, $s4 # $t9 = -sin(x)sin(z) + cos(z)cos(x)cos(y)
# [$s7, $s1, $s5] [ cos(z)cos(x) - cos(y)sin(z)sin(x), sin(z)sin(y), cos(z)sin(x) + cos(y)sin(z)cos(x)]
# let m_lrot = [$s3, $t2, $s2] = [ sin(x)sin(y), cos(y), -sin(y)cos(x)]
# [$t8, $s6, $s9] [-cos(x)sin(z) - cos(z)sin(x)cos(y), cos(z)sin(y), -sin(x)sin(z) + cos(z)cos(x)cos(y)]
# $t1 = cos_z
# $t3 = cos_y
# $t4 = cos_x
# $t5 = sin_z
# $t6 = sin_y
# $s0 = sin_x
andi $at, $s7, 0xFFFF
sll $t1, $s1, 16
or $t1, $at # $t1 = (m_lrot_12 << 16) | m_lrot_11
andi $at, $s5, 0xFFFF
sll $t3, $s3, 16
or $t3, $at # $t3 = (m_lrot_21 << 16) | m_lrot_13
andi $at, $t2, 0xFFFF
sll $t4, $s2, 16
or $t4, $at # $t4 = (m_lrot_23 << 16) | m_lrot_22
andi $at, $t8, 0xFFFF
sll $t5, $s6, 16
or $t5, $at # $t5 = (lrot_32 << 16) | m_lrot_31
ctc2 $t1, $8 # set GTE L11L12 = (lrot_12 << 16) | m_lrot_11
ctc2 $t3, $9 # set GTE L13L21 = (lrot_21 << 16) | m_lrot_13
ctc2 $t4, $10 # set GTE L22L23 = (lrot_23 << 16) | m_lrot_22
ctc2 $t5, $11 # set GTE L31L32 = (lrot_32 << 16) | m_lrot_31
ctc2 $t9, $12 # set GTE L33 = m_lrot_33
# GTE L = m_lrot
lw $t1, 0($a3) # $t1 = (colors->light_mat[0][1] << 16) | colors->light_mat[0][0]
lw $t3, 4($a3) # $t3 = (colors->light_mat[1][0] << 16) | colors->light_mat[0][2]
lw $t4, 8($a3) # $t4 = (colors->light_mat[1][2] << 16) | colors->light_mat[1][1]
lw $t5, 0xC($a3) # $t5 = (colors->light_mat[2][1] << 16) | colors->light_mat[2][0]
lw $t6, 0x10($a3) # $t6 = (colors->color.r << 16) | colors->light_mat[2][2]
lw $t7, 0x14($a3) # $t7 = (colors->color.b << 16) | colors->color.g
lw $s0, 0x18($a3) # $s0 = (colors->color_mat[0][1] << 16) | colors->color_mat[0][0]
lw $s4, 0x1C($a3) # $s4 = (colors->color_mat[1][0] << 16) | colors->color_mat[0][2]
lw $gp, 0x20($a3) # $gp = (colors->color_mat[1][2] << 16) | colors->color_mat[1][1]
lw $sp, 0x24($a3) # $sp = (colors->color_mat[2][1] << 16) | colors->color_mat[2][0]
lw $fp, 0x28($a3) # $fp = (colors->intensity.r << 16) | colors->color_mat[2][2]
lw $v1, 0x2C($a3) # $v1 = (colors->intensity.b << 16) | colors->intensity.g
calc_object_light_matrices_test_scale_x_lt0_2:
sll $s7, $t1, 16 # shift up sign bit
beqz $a0, calc_object_light_matrices_scale_x_gteq0_1
sra $s7, 16 # $s7 = colors->light_mat[0][0]
calc_object_light_matrices_scale_x_lt0_2:
negu $s7, $s7 # $s7 = -colors->light_mat[0][0]
calc_object_light_matrices_scale_x_gteq0_2:
sra $s1, $t1, 16 # $s1 = colors->light_mat[0][1]
sll $s5, $t3, 16 # shift up sign bit
sra $s5, 16 # $s5 = colors->light_mat[0][2]
mtc2 $s7, $9 # set GTE IR1 = $s7
mtc2 $s1, $10 # set GTE IR2 = colors->light_mat[0][1]
mtc2 $s5, $11 # set GTE IR3 = colors->light_mat[0][2]
# GTE IR1 = [[-]colors->light_mat[0][0]]
# GTE IR2 = [ colors->light_mat[0][1] ]
# GTE IR3 = [ colors->light_mat[0][2] ]
sra $v0, $fp, 16 # $v0 = colors->intensity.r
sra $t0, $t6, 16 # $t0 = colors->color.r
mult $v0, $t0 # mres = colors->color.r*colors->intensity.r
cop2 0x4BE012 # multiply IR by L (MVMVA, llir)
sll $v0, $v1, 16 # shift up sign bit? (this is an intensity value?)
sra $v0, 16 # $v0 = colors->intensity.g
sll $t0, $t7, 16 #
sra $t0, 16 # $t0 = colors->color.g
mfc2 $s7, $9
mfc2 $s1, $10
mfc2 $s5, $11 # $s7,$s1,$s5 = results of matrix multiplication
# [[-]colors->light_mat[0][0]]
# $s7,$s1,$s5 = m_lrot * [ colors->light_mat[0][1] ]
# [ colors->light_mat[0][2] ]
mflo $ra
sra $ra, 8 # $ra = mres >> 8 = (colors->color.r*colors->intensity.r) >> 8
ctc2 $ra, $13 # set GTE RBK = (colors->color.r*colors->intensity.r) >> 8
calc_object_light_matrices_test_scale_x_lt0_3:
beqz $a0, calc_object_light_matrices_scale_x_gteq0_3
sra $s3, $t3, 16 # $s3 = colors->light_mat[1][0]
calc_object_light_matrices_scale_x_lt0_3:
negu $s3, $s3 # $s3 = -colors->light_mat[1][0]
calc_object_light_matrices_scale_x_gteq0_3:
sll $t2, $t4, 16
sra $t2, 16 # $t2 = colors->light_mat[1][1]
sra $s2, $t4, 16 # $s2 = colors->light_mat[1][2]
mtc2 $s3, $9 # set GTE IR1 = $s3
mtc2 $t2, $10 # set GTE IR2 = colors->light_mat[1][1]
mtc2 $s2, $11 # set GTE IR3 = colors->light_mat[1][2]
# GTE IR1 = [[-]colors->light_mat[1][0]]
# GTE IR2 = [ colors->light_mat[1][1] ]
# GTE IR3 = [ colors->light_mat[1][2] ]
mult $v0, $t0 # mres = colors->color.g*colors->intensity.g
cop2 0x4BE012 # multiply IR by L (MVMVA, llir)
sra $v0, $v1, 16 # $v0 = colors->intensity.b
sra $t0, $t7, 16 # $t0 = colors->color.b
mfc2 $s3, $9
mfc2 $t2, $10
mfc2 $s2, $11 # $s3,$t2,$s2 = results of matrix multiplication
# [[-]colors->light_mat[1][0]]
# $s3,$t2,$s2 = m_lrot * [ colors->light_mat[1][1] ]
# [ colors->light_mat[1][2] ]
mflo $ra
sra $ra, 8 # $ra = mres >> 8 = (colors->color.g*colors->intensity.g) >> 8
ctc2 $ra, $14 # set GTE GBK = (colors->color.g*colors->intensity.g) >> 8
sll $t8, $t5, 16 # shift up sign bit
calc_object_light_matrices_test_scale_x_lt0_4:
beqz $a0, calc_object_light_matrices_scale_x_gteq0_4
sra $t8, 16 # $t8 = colors->light_mat[2][0]
calc_object_light_matrices_scale_x_lt0_4
negu $t8, $t8 # $t8 = -colors->light_mat[2][0]
calc_object_light_matrices_scale_x_gteq0_4:
sra $s6, $t5, 16 # $s6 = colors->light_mat[2][1]
sll $t9, $t6, 16 # shift up sign bit
sra $t9, 16 # $t9 = colors->light_mat[2][2]
mtc2 $t8, $9 # set GTE IR1 = $t8
mtc2 $s6, $10 # set GTE IR2 = colors->light_mat[2][1]
mtc2 $t9, $11 # set GTE IR3 = colors->light_mat[2][2]
# GTE IR1 = [[-]colors->light_mat[2][0]]
# GTE IR2 = [ colors->light_mat[2][1] ]
# GTE IR3 = [ colors->light_mat[2][2] ]
mult $v0, $t0 # mres -= colors->color.b*colors->intensity.b
cop2 0x4BE012 # multiply IR by L (MVMVA, llir)
nop
mfc2 $t8, $9
mfc2 $s6, $10
mfc2 $t9, $11 # $t8,$s6,$t9 = results of matrix multiplication
# [[-]colors->light_mat[2][0]]
# $t8,$s6,$t9 = m_lrot * [ colors->light_mat[2][1] ]
# [ colors->light_mat[2][2] ]
mflo $ra
sra $ra, 8 # $ra = mres >> 8 = (colors->color.b*colors->intensity.b) >> 8
ctc2 $ra, $15 # set GTE BBK = (colors->color.b*colors->intensity.b) >> 8
# [$s7, $s3, $t8] [[-]colors->light_mat[0][0], [-]colors->light_mat[1][0], [-]colors->light_mat[2][0]]
# let m_lrot2^T = [$s1, $t2, $s6] = m_lrot * [ colors->light_mat[0][1], colors->light_mat[1][1], colors->light_mat[2][1]]
# [$s5, $s2, $s9] [ colors->light_mat[0][2], colors->light_mat[1][2], colors->light_mat[2][2]]
# = m_lrot * (colors->light_mat)^T
#
# so that m_lrot2 = [$s7, $s1, $s5]
# [$s3, $t2, $s2]
# [$t8, $s6, $s9]
#
# then (AB)^T = (B^T)(A^T)
#
# and m_lrot2^T
# = m_lrot * (colors->light_mat)^T
# = (m_lrot^T)^T * (colors->light_mat)^T
# = (colors->light_mat * m_lrot^T) ^ T
# =>
# m_lrot2 = colors->light_mat * m_lrot^T
andi $at, $s7, 0xFFFF
sll $t1, $s1, 16
or $t1, $at
ctc2 $t1, $8 # set GTE L11L12 = (m_lrot2_12 << 16) | m_lrot2_11
andi $at, $s5, 0xFFFF
sll $t1, $s3, 16
or $t1, $at
ctc2 $t1, $9 # set GTE L13L21 = (m_lrot2_21 << 16) | m_lrot2_13
andi $at, $t2, 0xFFFF
sll $t1, $s2, 16
or $t1, $at
ctc2 $t1, $10 # set GTE L22L23 = (m_lrot2_23 << 16) | m_lrot2_22
andi $at, $t8, 0xFFFF
sll $t1, $s6, 16
or $t1, $at
ctc2 $t1, $11 # set GTE L31L32 = (m_lrot2_32 << 16) | m_lrot2_31
ctc2 $t9, $12 # set GTE L33 = m_lrot2_33
# GTE L = m_lrot2 = colors->light_mat * m_lrot^T
lui $at, 0xFFFF
and $t1, $s4, $at # $t1 = ((int16_t)colors->color_mat[1][0] << 16)
andi $t3, $s0, 0xFFFF # $t3 = (int16_t)colors->color_mat[0][0]
or $t1, $t3
ctc2 $t1, $16 # GTE LR1LR2 = ((int16_t)colors->color_mat[1][0] << 16) | (int16_t)colors->color_mat[0][0]
and $t1, $s0, $at
andi $t3, $sp, 0xFFFF
or $t1, $t3
ctc2 $t1, $17 # GTE LR3LG1 = ((int16_t)colors->color_mat[0][1] << 16) | (int16_t)colors->color_mat[2][0]
and $t1, $sp, $at
andi $t3, $gp, 0xFFFF
or $t1, $t3
ctc2 $t1, $18 # GTE LG2LG3 = ((int16_t)colors->color_mat[2][1] << 16) | (int16_t)colors->color_mat[1][1]
and $t1, $gp, $at
andi $t3, $s4, 0xFFFF
or $t1, $t3
ctc2 $t1, $19 # GTE LB1LB2 = ((int16_t)colors->color_mat[1][2] << 16) | (int16_t)colors->color_mat[0][2]
ctc2 $fp, $20 # GTE LB3 = colors->colors_mat[2][2]
# GTE LRGB = (colors->color_mat)^T
sload
jr $ra
nop
#
# identical to the first half of RGteCalcObjectLightMatrices
#
RGteCalcObjectRotMatrix:
rot_y = $sp
rot_x = $fp
rot_z = $gp
ssave
li $v1, sin_table # load pointer to sin table
lw rot_z, 0x14($a2)
lw rot_x, 0x10($a2)
lw rot_y, 0xC($a2) # rot = *vectors->rot
subu rot_x, rot_z, rot_x # needed for tait-bryan angles
negu rot_x, rot_x # rot.x = vectors->rot.x - vectors=>rot.z
andi rot_z, 0xFFF
andi rot_y, 0xFFF
andi rot_x, 0xFFF # rot = angle12(rot) [limit to 12 bit angle values]
calc_object_light_matrices_b_sin:
msin z1, $v1, $t5, $gp
msin y1, $v1, $t6, $sp
msin x1, $v1, $t7, $fp
mcos z1, $v1, $t1, $gp
mcos y1, $v1, $t2, $sp
mcos x1, $v1, $t4, $fp
calc_object_light_matrices_b_start:
# note that results of sin/cos are 12 bit fractional fixed point values
# thus, multiplying 2 of these values will produce a 24 bit fractional
# fixed point value
# therefore it is necessary to shift results of such multiplications
# to the right by 12 to convert back to a 12 bit fractional fixed point value
# the below annotations do not show these shifts as they are considered
# part of the multiplication, and do not show result values direct from
# multiplication as shifted left by 12 (as in most cases they are shifted
# right before any further usage)
mult $t1, $t7 # mres = cos(z)sin(x)
andi $s0, $t7, 0xFFFF # $s0 = (int16_t)sin(x)
andi $t1, 0xFFFF # $t1 = (int16_t)cos(z)
andi $t5, 0xFFFF # $t5 = (int16_t)sin(z)
andi $t6, 0xFFFF # $t6 = (int16_t)sin(y)
andi $t3, $t2, 0xFFFF # $t3 = (int16_t)cos(y)
andi $t4, 0xFFFF # $t4 = (int16_t)cos(x); future annotations assume implicit cast
cos_z = $t1
cos_y = $t3
cos_x = $t4
sin_z = $t5
sin_y = $t6
sin_x = $s0
ctc2 $zero, $1 # set GTE R13R21 = 0
ctc2 $zero, $3 # set GTE R31R32 = 0
mtc2 sin_y, $1 # set GTE VZ0 = sin(y)
sll $at, cos_x, 16
or $at, sin_z
mtc2 $at, $0 # set GTE VXY0 = cos(x) << 16 | sin(z)
# GTE V = [sin(z)]
# [cos(x)]
# [sin(y)]
mflo $fp # $fp = mres = cos(z)sin(x)
ctc2 cos_y, $0 # set GTE R11R12 = cos(y)
ctc2 cos_z, $2 # set GTE R22R23 = cos(z)
ctc2 sin_z, $4 # set GTE R33 = sin(z)
# GTE R = [cos(y), 0, 0]
# [ 0, cos(z), 0]
# [ 0, 0, sin(z)]
sra $fp, 12
mult $fp, $t2 # mres = cos(z)sin(x)cos(y)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
ctc2 cos_x, $0 # set GTE R11R12 = cos(x)
ctc2 sin_y, $2 # set GTE R22R23 = sin(y)
ctc2 sin_x, $4 # set GTE R33 = sin(x)
# GTE R = [cos(x), 0, 0]
# [ 0, sin(y), 0]
# [ 0, 0, sin(x)]
mfc2 $sp, $9 # $sp = rotation result component 1
mflo $t8
sra $t8, 12 # $t8 = mres = cos(z)sin(x)cos(y)
mfc2 $gp, $10 # $gp = rotation result component 2
mfc2 $s1, $11 # $s1 = rotation result component 3
# $sp,$gp,$s1 = [cos(y), 0, 0][sin(z)] = [cos(y)sin(z)]
# [ 0, cos(z), 0][cos(x)] [cos(z)cos(x)]
# [ 0, 0, sin(z)][sin(y)] [sin(z)sin(y)]
mult $sp, $t7 # mres = cos(y)sin(z)sin(x)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
ctc2 sin_x, $0 # set GTE R11R12 = sin(x)
andi $at, $sp, 0xFFFF # $at = (uint16_t)cos(y)sin(z)
ctc2 $at, $2 # set GTE R22R23 = cos(y)sin(z)
ctc2 cos_z, $4 # set GTE R33 = cos(z)
mfc2 $at, $9 # $at = rotation result component 1
mflo $s7 # $s7 = mres = cos(y)sin(z)sin(x)
mfc2 $s2, $10 # $s2 = rotation result component 2
mfc2 $s3, $11 # $s3 = rotation result component 3
# $at,$s2,$s3 = [cos(x), 0, 0][sin(z)] = [cos(x)sin(z)]
# [ 0, sin(y), 0][cos(x)] [sin(y)cos(x)]
# [ 0, 0, sin(x)][sin(y)] [sin(x)sin(y)]
mult $gp, $t2 # mres = cos(z)cos(x)cos(y)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
sra $s7, 12
mfc2 $s4, $9
mfc2 $s5, $10
mfc2 $s6, $11 # $s4,$s5,s6 = rotation result
# $s4,$s5,$s6 = [sin(x), 0, 0][sin(z)] = [sin(x)sin(z)]
# [ 0, cos(y)sin(z), 0][cos(x)] [cos(y)sin(z)cos(x)]
# [ 0, 0, cos(z)][sin(y)] [cos(z)sin(y)]
mflo $t9
sra $t9, 12 # $t9 = mres = cos(z)cos(x)cos(y)
negu $s2, $s2 # $s2 = -sin(y)cos(x)
subu $s7, $gp, $s7 # $s7 = cos(z)cos(x) - cos(y)sin(z)sin(x)
addu $s5, $fp, $s5 # $s5 = cos(z)sin(x) + cos(y)sin(z)cos(x)
addu $t8, $at, $t8
negu $t8, $t8 # $t8 = -cos(x)sin(z) - cos(z)sin(x)cos(y)
subu $t9, $s4 # $t9 = -sin(x)sin(z) + cos(z)cos(x)cos(y)
# $t1 = cos_z
# $t3 = cos_y
# $t4 = cos_x
# $t5 = sin_z
# $t6 = sin_y
lw $t1, 0($a0)
lw $t3, 4($a0)
lw $t4, 8($a0)
lw $t5, 0xC($a0)
lw $t6, 0x10($a0)
ctc2 $t1, $0
ctc2 $t3, $1
ctc2 $t4, $2
ctc2 $t5, $3
ctc2 $t6, $4 # set GTE R = m_rot (matrix passed as argument)
# GTE R = m_rot
lw $t1, 0x18($a2) # $t1 = vectors->scale.x
lw $t3, 4($a1) # $t3 = header->scale.x
mtc2 $s7, $9 # set GTE IR1 = cos(z)cos(x) - cos(y)sin(z)sin(x)
mtc2 $s3, $10 # set GTE IR2 = sin(x)sin(y)
mtc2 $t8, $11 # set GTE IR3 = -cos(x)sin(z) - cos(z)sin(x)cos(y)
# GTE IR1 = [ cos(z)cos(x) - cos(y)sin(z)sin(x)]
# GTE IR2 = [ sin(x)sin(y) ]
# GTE IR3 = [-cos(x)sin(z) - cos(z)sin(x)cos(y)]
mult $t1, $t3 # mres = vectors->scale.x * header->scale.x
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
lw $t1, 0x1C($a2) # $t1 = vectors->scale.y
lw $t3, 8($a1) # $t3 = header->scale.y
mfc2 $s7, $9
mfc2 $s3, $10
mfc2 $t8, $11 # $s7,$s3,$t8 = rotation result
mflo $t4 # $t4 = mres = vectors->scale.x * header->scale.x
# [ cos(z)cos(x) - cos(y)sin(z)sin(x)]
# $s7,$s3,$t8 = m_rot * [ sin(x)sin(y) ]
# [-cos(x)sin(z) - cos(z)sin(x)cos(y)]
mtc2 $s1, $9 # set GTE IR1 = sin(z)sin(y)
mtc2 $t2, $10 # set GTE IR2 = cos(y)
mtc2 $s6, $11 # set GTE IR3 = cos(z)sin(y)
# GTE IR1 = [sin(z)sin(y)]
# GTE IR2 = [ cos(y) ]
# GTE IR3 = [cos(z)sin(y)]
mult $t1, $t3 # mres = vectors->scale.y * header->scale.y
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
lw $t1, 0x20($a2) # $t1 = vectors->scale.z
lw $t3, 0xC($a1) # $t3 = header->scale.z
mfc2 $s1, $9
mfc2 $t2, $10
mfc2 $s6, $11 # $s1,$t2,$t6 = rotation result
# [sin(z)sin(y)]
# $s1,$t2,$s6 = m_rot * [ cos(y) ]
# [cos(z)sin(y)]
sra $t4, 12
mflo $t5 # $t5 = mres = vectors->scale.y * header->scale.y
mtc2 $s5, $9 # set GTE IR1 = cos(z)sin(x) + cos(y)sin(z)cos(x)
mtc2 $s2, $10 # set GTE IR2 = -sin(y)cos(x)
mtc2 $t9, $11 # set GTE IR3 = -sin(x)sin(z) + cos(z)cos(x)cos(y)
# GTE IR1 = [ cos(z)sin(x) + cos(y)sin(z)cos(x)]
# GTE IR2 = [ -sin(y)cos(x) ]
# GTE IR3 = [-sin(x)sin(z) + cos(z)cos(x)cos(y)]
mult $t1, $t3 # mres = vectors->scale.z * header->scale.z
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
sra $t5, 12
mfc2 $s5, $9
mfc2 $s2, $10
mfc2 $t9, $11 # $s5,$s2,$t9 = rotation result
# [ cos(z)sin(x) + cos(y)sin(z)cos(x)]
# $s5,$s2,$t9 = m_rot * [ -sin(y)cos(x) ]
# [-sin(x)sin(z) + cos(z)cos(x)cos(y)]
andi $t4, 0xFFFF # $t4 = (int16_t)(vectors->scale.x * header->scale.x)
andi $t5, 0xFFFF # $t5 = (int16_t)(vectors->scale.y * header->scale.y)
mflo $t6 # ...
sra $t6, 12 # ...
andi $t6, 0xFFFF # $t6 = (int16_t)(vectors->scale.z * header->scale.z)
# [$t4] [(int16_t)(vectors->scale.x * header->scale.x)]
# let scale = [$t5] = [(int16_t)(vectors->scale.y * header->scale.y)]
# [$t6] [(int16_t)(vectors->scale.z * header->scale.z)]
ctc2 $t4, $0 # set GTE R11R12 = scale.x
ctc2 $zero, $1 # set GTE R13R21 = 0
ctc2 $t5, $2 # set GTE R22R23 = scale.y
ctc2 $zero, $3 # set GTE_R31R32 = 0
ctc2 $t6, $4 # set GTE R33 = scale.z
# GTE R = [scale.x, 0, 0]
# [ 0, scale.y, 0]
# [ 0, 0, scale.z]
# [$s7, $s1, $s5] [ cos(z)cos(x) - cos(y)sin(z)sin(x), sin(z)sin(y), cos(z)sin(x) + cos(y)sin(z)cos(x)]
# let m_rot2 = [$s3, $t2, $s2] = m_rot * [ sin(x)sin(y), cos(y), -sin(y)cos(x)]
# [$t8, $s6, $s9] [-cos(x)sin(z) - cos(z)sin(x)cos(y), cos(z)sin(y), -sin(x)sin(z) + cos(z)cos(x)cos(y)]
mtc2 $s3, $9 # set GTE IR1 = m_rot2_21
mtc2 $t2, $10 # set GTE IR2 = m_rot2_22
mtc2 $s2, $11 # set GTE IR3 = m_rot2_23
# GTE IR1 = [m_rot2_21]
# GTE IR2 = [m_rot2_22]
# GTE IR3 = [m_rot2_23]
nop
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
nop
mfc2 $s3, $9
mfc2 $t2, $10
mfc2 $s2, $11 # $s3,$t2,$s2 = rotation result
# $s3,$t2,$s2 = [scale.x, 0, 0][m_rot2_21]
# [ 0, scale.y, 0][m_rot2_22]
# [ 0, 0, scale.z][m_rot2_23]
# let result_y be the current values of $s3,$t2,$s2
mtc2 $t8, $9 # set GTE IR1 = m_rot2_31
mtc2 $s6, $10 # set GTE_IR2 = m_rot2_32
mtc2 $t9, $11 # set GTE_IR3 = m_rot2_33
# GTE IR1 = [m_rot2_31]
# GTE IR2 = [m_rot2_32]
# GTE IR3 = [m_rot2_33]
move $t1, $s3 # $t1 = result_y[0]
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
move $t3, $t2 # $t3 = result_y[1]
mfc2 $t8, $9
mfc2 $s6, $10
mfc2 $t9, $11 # $t8,$s6,$s9 = rotation result
# $t8,$s6,$s9 = [scale.x, 0, 0][m_rot2_31]
# [ 0, scale.y, 0][m_rot2_32]
# [ 0, 0, scale.z][m_rot2_33]
# let result_z be the current values of $t8,$s6,$s9
mtc2 $s7, $9 # set GTE IR1 = m_rot2_11
mtc2 $s1, $10 # set GTE IR2 = m_rot2_12
mtc2 $s5, $11 # set GTE IR3 = m_rot2_13
# GTE IR1 = [m_rot2_11]
# GTE IR2 = [m_rot2_12]
# GTE IR3 = [m_rot2_13]
move $t4, $s2 # $t4 = result_y[2]
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
sll $s3, 2 # $s3 = result_y[0] * 4
mfc2 $s7, $9
mfc2 $s1, $10
mfc2 $s5, $11 # $s7,$s1,$s5 = rotation result
# $s7,$s1,$s5 = [scale.x, 0, 0][m_rot2_11]
# [ 0, scale.y, 0][m_rot2_12]
# [ 0, 0, scale.z][m_rot2_13]
# let result_x be the current values of $s7,$s1,$s5
addu $s3, $t1 # $s3 = (result_y[0] * 4) + result_y[0] = result_y[0]*5
sra $s3, 3 # $s3 = (result_y[0]*5)/8 = result_y[0]*(5/8)
negu $s3, $s3 # $s3 = -(5/8)*result_y[0]
sll $t2, 2
addu $t2, $t3
sra $t2, 3
negu $t2, $t2 # $t2 = -(5/8)*result_y[1]
sll $s2, 2
addu $s2, $t4
sra $s2, 3
negu $s2, $s2 # $s2 = -(5/8)*result_y[2]
negu $t8, $t8 # $t8 = -result_z[0]
negu $s6, $s6 # $s6 = -result_z[1]
negu $t9, $t9 # $t9 = -result_z[2]
andi $at, $s7, 0xFFFF
sll $t1, $s1, 16
or $t1, $at # $t1 = (result_x[1] << 16) | result_x[0]
andi $at, $s5, 0xFFFF
sll $t3, $s3, 16
or $t3, $at # $t3 = ((-(5/8)*result_y[0]) << 16) | result_x[2]
andi $at, $t2, 0xFFFF
sll $t4, $s2, 16
or $t4, $at # $t4 = ((-(5/8)*result_y[2]) << 16) | (-(5/8)*result_y[1])
andi $at, $t8, 0xFFFF
sll $t5, $s6, 16
or $t5, $at # $t5 = (-result_z[1] << 16) | -result_z[0]
ctc2 $t1, $0 # set GTE R11R12 = (result_x[1] << 16) | result_x[0]
ctc2 $t3, $1 # set GTE R13R21 = ((-(5/8)*result_y[0]) << 16) | result_x[2]
ctc2 $t4, $2 # set GTE R22R23 = ((-(5/8)*result_y[2]) << 16) | (-(5/8)*result_y[1])
ctc2 $t5, $3 # set GTE R31R32 = (-result_z[1] << 16) | -result_z[0]
ctc2 $t9, $4 # set GTE R33 = -result_z[2]
sload
jr $ra
nop
#
# Calculate the trans vector and rotation matrix to use
# for sprite geometry transformation
#
# The exact calculations are:
# if flag == 0:
# GTE TR = m_rot*tr
# GTE R = RZ(rz)*RX(ry)*RY(rx)*D(vs)*S*M
#
# where tr = (vectors->trans - cam_vectors->trans) >> 8
# rx = vectors->rot.x - limit(cam_vectors->rot.x, -170, 170)
# ry = vectors->rot.y - limit(cam_vectors->rot.y, -170, 170)
# rz = vectors->rot.z - cam_vectors->rot.z
# if flag == 1:
# [ tx ]
# GTE TR = [ -ty ] >> 8
# [ depth]
# GTE R = RZ(rz)*RX(ry)*RY(rx)*D(vs)*S*M
#
# where tx = vectors->trans.x
# ty = vectors->trans.y
# ry,rx,rz = vectors->rot
#
# where D(v) = diagonal matrix for vector v
# S = [1, 0, 0]
# [0, -5/8, 0]
# [0, 0, -1]
# M = [1, 0, 0] # mask for limiting rotation to xy plane
# [0, 1, 0]
# [0, 0, 0]
# vs = vectors->scale >> shrink
#
# a0 = obj_vectors: sprite (obj) vectors
# a1 = cam_vectors: cam vectors
# a2 = flag
# a3 = shrink: log 2 of shrink amount
# 0x10($sp) = m_rot: rotation matrix
# 0x14($sp) = depth: depth/z location of sprite used when flag == 1
# 0x18($sp) = max_depth: maximum depth (returns 0 if depth is greater than this)
# 0x1C($sp) = not used, value is overwritten
#
RGteCalcSpriteRotMatrix:
arg_10 = 0x10
arg_14 = 0x14
arg_18 = 0x18
arg_1C = 0x1C
calc_sprite_rot_matrix:
ssave
lw $ra, arg_10($sp)
lw $v0, arg_14($sp)
lw $t9, arg_18($sp)
lw $gp, arg_1C($sp)
lw $t0, 0($ra)
lw $t1, 4($ra)
lw $t2, 8($ra)
lw $t3, 0xC($ra)
lw $t4, 0x10($ra)
ctc2 $t0, $0
ctc2 $t1, $1
ctc2 $t2, $2
ctc2 $t3, $3
ctc2 $t4, $4 # set GTE R = m_rot (rot matrix passed as argument)
lw $s0, 0($a0) # $s0 = vectors->trans.x
calc_sprite_rot_matrix_test_flag:
beqz $a2, calc_sprite_rot_matrix_flag_false # goto false section if passed flag is not set
lw $s1, 4($a0) # $s1 = vectors->trans.y
calc_sprite_rot_matrix_flag_true:
sra $s0, 8 # $s0 = (vectors->trans.x >> 8)
negu $s1, $s1
sra $s1, 8 # $s1 = (-vectors->trans.y >> 8)
ctc2 $s0, $5 # set GTE TRX = (vectors->trans.x >> 8)
ctc2 $s1, $6 # set GTE TRY = (-vectors->trans.y >> 8)
bgez $zero, loc_8003A264
ctc2 $v0, $7 # set GTE TRZ = depth (argument)
# GTE TRX = [vectors->trans.x >> 8]
# GTE TRY = [-vectors->trans.y >> 8]
# GTE TRZ = [depth]
calc_sprite_rot_matrix_flag_false:
lw $s2, 8($a0) # $s2 = vectors->trans.z
lw $s3, 0($a1)
lw $s4, 4($a1)
lw $s5, 8($a1) # $s3-$s5 = cam_trans
subu $s0, $s3
subu $s1, $s4
subu $s2, $s5 # $s0-$s2 = vectors->trans - cam_trans
sra $s0, 8
sra $s1, 8
sra $s2, 8 # $s0-$s2 = (vectors->trans - cam_trans) >> 8
mtc2 $s0, $9
mtc2 $s1, $10
mtc2 $s2, $11 # set GTE IR1-3 = $s0-$s2
# GTE IR1-3 = (vectors->trans - cam_trans) >> 8
nop
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
nop
mfc2 $s0, $9
mfc2 $s1, $10
mfc2 $s2, $11 # $s0-$s2 = rotation result (GTE IR1-3)
# $s0-$s2 = R * ((vectors->trans - cam_trans) >> 8)
ctc2 $s0, $5
ctc2 $s1, $6
ctc2 $s2, $7 # set GTE TR = R * ((vectors->trans - cam_trans) >> 8)
# GTE TR = R * ((vectors->trans - cam_trans) >> 8)
calc_sprite_rot_matrix_test_depth:
slt $at, $v0, $s2
beqz $at, calc_sprite_rot_matrix_ret_0 # return 0 if depth >= TRZ
li $at, 12000
slt $at, $s2
bnez $at, calc_sprite_rot_matrix_ret_0 # return 0 if depth >= 12000
slt $at, $t9, $s2
beqz $t9, calc_sprite_rot_matrix_2 # goto next block if depth <= max_depth
nop
bnez $at, calc_sprite_rot_matrix_ret_0 # else return 0
calc_sprite_rot_matrix_2:
lw $fp, 0x10($a0) # $fp = vectors->rot.x
lw $sp, 0xC($a0) # $sp = vectors->rot.y
calc_sprite_rot_matrix_test_flag_2:
bnez $a2, calc_sprite_rot_matrix_flag_true_2
lw $gp, 0x14($a0) # $gp = vectors->rot.z
calc_sprite_rot_matrix_flag_false_2:
lw $s0, 0xC($a1)
lw $s1, 0x10($a1)
lw $s2, 0x14($a1) # $s0-$s2 = cam_rot
sll $s0, 21
sra $s0, 21 # $s0 = (cam_rot.y << 21) >> 21
sll $s1, 21
sra $s1, 21 # $s1 = (cam_rot.x << 21) >> 21
sll $s2, 20
sra $s2, 20 # $s2 = (cam_rot.z << 20) >> 20
negu $s3, $s0 # $s3 = -((cam_rot.y << 21) >> 21)
calc_sprite_rot_matrix_test_camroty_ltn170:
slti $at, $s0, -170 #
bnez $at, calc_sprite_rot_matrix_3 # if cam_rot.y < -170, then skip
li $at, 170 # and set $at = 170
calc_sprite_rot_matrix_test_ncamroty_ltn170:
slti $at, $s3, -170
bnez $at, calc_sprite_rot_matrix_3 # else if cam_rot.y > 170, then skip
li $at, -170 # and set $at = -170
calc_sprite_rot_matrix_camroty_bt_n170_170:
move $at, $s3 # else set $at = -cam_rot.y
calc_sprite_rot_matrix_3:
addu $sp, $at, $sp # $sp = vectors->rot.y - limit(cam_rot.y, -170, 170)]
negu $s3, $s1 # $s3 = -((cam_rot.x << 21) >> 21)
calc_sprite_rot_matrix_test_camrotx_ltn170:
slti $at, $s1, -170
bnez $at, loc_8003A2DC # if cam_rot.x < -170, then skip
li $at, 170 # and set $at = 170
calc_sprite_rot_matrix_test_ncamrotx_ltn170
slti $at, $s3, -170
bnez $at, loc_8003A2DC # if cam_rot.x > 170, then skip
li $at, -170 # and set $at = -170
calc_sprite_rot_matrix_camroty_bt_n170_170
move $at, $s3 # else set $at = -cam_rot.x
calc_sprite_rot_matrix_4:
addu $fp, $at, $fp # $fp = vectors->rot.x - limit(cam_rot.x, -170, 170)
subu $gp, $s2 # $gp = vectors->rot.z - cam_rot.z
calc_sprite_rot_matrix_flag_true_2:
andi $fp, 0xFFF
andi $sp, 0xFFF
andi $gp, 0xFFF # $fp,$gp,$sp = angle12($fp,$gp,$sp)
li $v1, sin_table # load sine table pointer
msin z3, $v1, $t6, $gp
msin y3, $v1, $t5, $sp
msin x3, $v1, $t7, $fp
mcos z3, $v1, $t0, $gp
mcos y3, $v1, $t1, $sp
mcos x3, $v1, $t3, $fp
calc_sprite_rot_matrix_5:
mult $t5, $t7 # mres = sin(y)sin(x)
andi $t4, $t6, 0xFFFF # $t4 = (int16_t)sin(z)
andi $t5, 0xFFFF # $t5 = (int16_t)sin(y)
andi $t7, 0xFFFF # $t7 = (int16_t)sin(x)
andi $t0, 0xFFFF # $t0 = (int16_t)cos(z)
andi $t2, $t1, 0xFFFF # $t2 = (int16_t)cos(y)
andi $t3, 0xFFFF # $t3 = (int16_t)cos(x); future annotations assume implicit cast
cos_z = $t0
cos_y = $t2
cos_x = $t3
sin_z = $t4
sin_y = $t5
sin_x = $t7
ctc2 $zero, $1 # set GTE R13R21 = 0
ctc2 $zero, $3 # set GTE R31R32 = 0
mtc2 cos_z, $1 # set GTE VZ0 = cos(z)
sll $at, cos_x, 16
or $at, sin_x
mtc2 $at, $0 # set GTE VXY0 = cos(x) << 16 | sin(x)
# GTE V = [sin(x)]
# [cos(x)]
# [cos(z)]
mflo $gp # $gp = mres = sin(y)sin(x)
ctc2 $zero, $0 # set GTE R11R12 = 0
ctc2 sin_y, $2 # set GTE R22R23 = sin(y)
ctc2 cos_y, $4 # set GTE R33 = cos(y)
# GTE R = [ 0, 0, 0]
# [ 0, sin(y), 0]
# [ 0, 0, cos(y)]
mult $t6, $t1 # mres = sin(z)cos(y)
sra $gp, 12
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
ctc2 cos_z, $0 # set GTE R11R12 = cos(z)
ctc2 cos_z, $2 # set GTE R22R23 = cos(z)
andi $at, $gp, 0xFFFF # $at = (int16_t)sin(y)sin(x)
ctc2 $at, $4 # set GTE R33 = sin(y)sin(x)
# GTE R = [cos(z), 0, 0]
# [ 0, cos(z), 0]
# [ 0, 0, sin(y)sin(x)]
mflo $s7 # $s7 = mres = sin(z)cos(y)
mfc2 $sp, $10 # $sp = rotation result component 2
mfc2 $s0, $11 # $s0 = rotation result component 3
# $zero,$sp,$s0 = [ 0, 0, 0][sin(x)] = [ 0 ]
# [ 0, sin(y), 0][cos(x)] [sin(y)cos(x)]
# [ 0, 0, cos(y)][cos(z)] [cos(y)cos(z)]
mult $t6, $gp # mres = sin(z)sin(y)sin(x)
sra $s7, 12
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
ctc2 sin_z, $0 # set GTE R11R12 = sin(z)
ctc2 sin_z, $2 # set GTE R22R23 = sin(z)
andi $at, $sp, 0xFFFF # $at = (uint16_t)sin(y)cos(x)
ctc2 $at, $4 # set GTE R33 = sin(y)cos(x)
# GTE R = [sin(z), 0, 0]
# [ 0, sin(z), 0]
# [ 0, 0, sin(y)cos(x)]
mflo $t8 # $t8 = mres = sin(z)sin(y)sin(x)
mfc2 $s1, $9 # $s1 = rotation result component 1
mfc2 $s2, $10 # $s2 = rotation result component 2
mfc2 $s3, $11 # $s3 = rotation result component 3
# $s1,$s2,$s3 = [cos(z), 0, 0][sin(x)] = [ cos(z)sin(x) ]
# [ 0, cos(z), 0][cos(x)] [ cos(z)cos(x) ]
# [ 0, 0, sin(y)sin(x)][cos(z)] [sin(y)sin(x)cos(z)]
mult sin_z, $sp # mres = sin(z)sin(y)cos(x)
cop2 0x486012 # rotate V0 by R (MVMVA, rtv0)
sra $t8, 12
mfc2 $s4, $9
mfc2 $s5, $10
mfc2 $s6, $11 # $s4,$s5,s6 = rotation result
# $s4,$s5,$s6 = [sin(z), 0, 0][sin(x)] = [ sin(z)sin(x) ]
# [ 0, sin(z), 0][cos(x)] [ sin(z)cos(x) ]
# [ 0, 0, sin(y)cos(x)][cos(z)] [sin(y)cos(x)cos(z)]
mflo $at
sra $at, 12 # $at = mres = sin(z)sin(y)cos(x)
subu $s2, $t8 # $s2 = cos(z)cos(x) - sin(z)sin(y)sin(x)
negu $s7, $s7 # $s7 = -sin(z)cos(y)
addu $s1, $at # $s1 = cos(z)sin(x) + sin(z)sin(y)cos(x)
addu $s3, $s5, $s3 # $s3 = sin(z)cos(x) + sin(y)sin(x)cos(z)
subu $s4, $s6 # $s4 = sin(z)sin(x) - sin(y)cos(x)cos(z)
lw $t2, 0x18($a0)
lw $t3, 0x1C($a0)
lw $t4, 0x20($a0) # $t2-$t4 = vectors->scale
srav $t2, $a3
srav $t3, $a3
srav $t4, $a3 # $t2-$t4 = vectors->scale >> shrink
# let scale = (vectors->scale >> shrink)
ctc2 $t2, $0 # set GTE R11R12 = scale.x
ctc2 $zero, $1 # set GTE R13R21 = 0
ctc2 $t3, $2 # set GTE R22R23 = scale.y
ctc2 $zero, $3 # set GTE R31R32 = 0
ctc2 $t4, $4 # set GTE R33 = scale.z
# GTE R = [scale.x, 0, 0]
# [ 0, scale.y, 0]
# [ 0, 0, scale.z]
mtc2 $s3, $9 # set GTE IR1 = sin(z)cos(x) + sin(y)sin(x)cos(z)
mtc2 $s0, $10 # set GTE IR2 = cos(y)cos(z)
mtc2 $s4, $11 # set GTE IR3 = sin(z)sin(x) - sin(y)cos(x)cos(z)
# GTE IR1 = [sin(z)cos(x) + sin(y)sin(x)cos(z)]
# GTE IR2 = [ cos(y)cos(z) ]
# GTE IR3 = [sin(z)sin(x) - sin(y)cos(x)cos(z)]
nop
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
nop
#z,x,y = 1,2,3
mfc2 $s3, $9
mfc2 $s0, $10
mfc2 $s4, $11 # $s3,$s0,$s4 = rotation result
# [sin(z)cos(x) + sin(y)sin(x)cos(z)]
# $s3,$s0,$s4 = scale * [ cos(y)cos(z) ]
# [sin(z)sin(x) - sin(y)cos(x)cos(z)]
# let r1 = $s3,$s0,$s4
mtc2 $s2, $9 # set GTE IR1 = cos(z)cos(x) - sin(z)sin(y)sin(x)
mtc2 $s7, $10 # set GTE IR2 = -sin(z)cos(y)
mtc2 $s1, $11 # set GTE IR3 = cos(z)sin(x) + sin(z)sin(y)cos(x)
# GTE IR1 = [cos(z)cos(x) - sin(z)sin(y)sin(x)]
# GTE IR2 = [ -sin(z)cos(y) ]
# GTE IR3 = [cos(z)sin(x) + sin(z)sin(y)cos(x)]
move $t0, $s3 # $t0 = $s3
cop2 0x49E012 # rotate IR1-3 by R (MVMVA, rtir12)
move $t1, $s0 # $t1 = $s0
mfc2 $s2, $9
mfc2 $s7, $10
mfc2 $s1, $11 # $s2,$s7,$t1 = rotation result
# [cos(z)cos(x) - sin(z)sin(y)sin(x)]
# $s2,$s7,$s1 = scale * [ -sin(z)cos(y) ]
# [cos(z)sin(x) + sin(z)sin(y)cos(x)]
# let r2 = $s2,$s7,$s1
move $t2, $s4 # $t2 = $s4
sll $s3, 2
addu $s3, $t0
sra $s3, 3
negu $s3, $s3 # r1.x = -(5/8)*r1.x
sll $s0, 2
addu $s0, $t1
sra $s0, 3
negu $s0, $s0 # r1.y = (-5/8)*r1.y
sll $s4, 2
addu $s4, $t2
sra $s4, 3
negu $s4, $s4 # r1.z = (-5/8)*r1.z
andi $at, $s2, 0xFFFF # $at = r2.x
sll $t0, $s7, 16 # $t0 = (r2.y << 16)
or $t0, $at # $t0 = (r2.y << 16) | r2.x
andi $at, $s1, 0xFFFF
sll $t1, $s3, 16
or $t1, $at # $t1 = (r1.x << 16) | r2.z
andi $at, $s0, 0xFFFF
sll $t2, $s4, 16
or $t2, $at # $t2 = (r2.z << 16) | r2.y
ctc2 $t0, $0 # set GTE R11R12 = (r2.y << 16) | r2.x
ctc2 $t1, $1 # set GTE R13R21 = (r1.x << 16) | r2.z
ctc2 $t2, $2 # set GTE R22R23 = (r1.z << 16) | r1.y
ctc2 $zero, $3 # set GTE R31R32 = 0
ctc2 $zero, $4 # set GTE R33 = 0
# [cos(z)cos(x) - sin(z)sin(y)sin(x), -sin(z)cos(y), 0] [1, 0, 0]
# GTE R = [sin(z)cos(x) + sin(y)sin(x)cos(z), cos(y)cos(z), 0] * scale * [0, -5/8, 0]
# [ 0, 0, 0] [0, 0, -1]
sload
li $v0, 1 # return 1 (success)
jr $ra
nop
# ---------------------------------------------------------------------------
calc_sprite_rot_matrix_ret_0:
sload
move $v0, $zero # return 0 (fail)
jr $ra
nop
#
# translate, rotate, and perspective transform a 'sprite'
# (an origin-centered square of size*2)
# and populate the ot with the corresponding (POLY_FT4) primitive
#
# a0 = ot = (in) ot
# a1 = p_texinfo = (in) pointer to sprite texinfo
# a2 = tpageinfo = (in) tpage info, resolved from eid
# a3 = size = (in) half length of sprite square
# arg_10 = far = (in) far value
# arg_14 = prims_tail = (inout) pointer to tail pointer of primitive buffer
# arg_18 = regions = (in) pointer to table of precomputed uv coordinate rects/'regions'
#
RGteTransformSprite:
arg_10 = 0x10
arg_14 = 0x14
arg_18 = 0x18
ot = $a0
size = $a3
p_prims_tail = $t1
lw $t0, arg_10($sp)
lw p_prims_tail, arg_14($sp)
lw $t2, arg_18($sp)
sll $t0, 2
negu $at, size
andi $t6, size, 0xFFFF # $t6 = (int16_t)size
andi $t5, $at, 0xFFFF # $t5 = (int16_t)-size
sll $t4, size, 16 # $t4 = ((int16_t)size) << 16
sll $t7, $at, 16 # $t7 = ((int16_t)-size) << 16
or $at, $t5, $t4 # $at = ((int16_t)size) << 16 | (int16_t)-size
or $v0, $t6, $t4 # $v0 = ((int16_t)size) << 16 | (int16_t)size
or $v1, $t5, $t7 # $v1 = ((int16_t)-size) << 16 | (int16_t)-size
or $t7, $t6, $t7 # $t7 = ((int16_t)-size) << 16 | (int16_t)size
transform_sprite_1:
prim = $a3
lw prim, 0(p_prims_tail) # get pointer to primitive memory
lw $t4, 0($a1) # get texinfo word 1
# transform the ul, ll, and lr corners of a square in the xy plane of length 2*size and centered at (0,0)
mtc2 $at, $0 # set GTE VXY0 = ((int16_t)size) << 16 | (int16_t)-size
mtc2 $zero, $1 # set GTE VZ0 = 0
mtc2 $v0, $2 # set GTE VXY1 = ((int16_t)size) << 16 | (int16_t)size
mtc2 $zero, $3 # set GTE VZ1 = 0
mtc2 $v1, $4 # set GTE VXY2 = ((int16_t)-size) << 16 | (int16_t)-size
mtc2 $zero, $5 # set GTE VZ2 = 0
# GTE V0 = [-size]
# [ size]
# [ 0 ]
# GTE V1 = [ size]
# [ size]
# [ 0 ]
# GTE V2 = [-size]
# [-size]
# [ 0 ]
srl $t5, $t4, 24 # shift down semi-transparency bits, etc.
cop2 0x280030 # trans, rot, and perspective transform verts/corners
cfc2 $at, $31 # get GTE flag
nop
bltz $at, transform_sprite_ret # return if transform required limiting
# transform the remaining ur corner of the aformentioned square
mtc2 $t7, $0 # set GTE VXY0 = ((int16_t)-size) << 16 | (int16_t)size
mtc2 $zero, $1 # set GTE VZ0 = 0
# GTE V0 = [ size]
# [-size]
# [ 0 ]
create_poly_ft4_1:
swc2 $12, 8(prim)
swc2 $13, 0x10(prim)
swc2 $14, 0x18(prim) # store yx values for first 3 transformed corners in a new POLY_FT4 primitive
mfc2 $t7, $17
mfc2 $v0, $18
mfc2 $v1, $19 # get transformed z values for first 3 corners
addu $t7, $v0
addu $t7, $v1
srl $t7, 5 # compute sum over 32 (average over 10.666); this is an index
sll $t7, 2 # multiply by sizeof(void*)
cop2 0x180001 # trans, rot, and perspective transform the remaining corner
cfc2 $at, $31 # get GTE flag
nop
bltz $at, transform_sprite_ret # return if transform required limiting
nop
swc2 $14, 0x20(prim) # store yx value for the final transformed corner in the POLY_FT4
li $v1, 0xFFFFFF # load mask for selecting lower 3 bytes
and $at, $t4, $v1 # select RGB values from texinfo word 1
lui $v1, 0x2C00 # load code constant for POLY_FT4 primitives
or $at, $v1 # or the primitive code constant with RGB values
li $v1, 0x60 # '`' # load mask for selecting semi-trans mode
and $v0, $t5, $v1 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
beq $v0, $v1, create_poly_ft4_2 # skip setting code bits for a semi-trans primitive if semi-trans bits == 3
lw $t3, 4($a1) # get texinfo word 2
create_poly_ft4_stlt3_1:
lui $v1, 0x200
or $at, $v1 # set code bits for a semi-trans primitive if semi-trans mode < 3
create_poly_ft4_2:
sw $at, 4(prim) # store primitive code and RGB values
srl $a1, $t3, 20 # shift down bits 21 and 22 from texinfo word 2 (color mode)
srl $at, $t3, 22 # shift down bits 23-32 of texinfo word 2 (region index)
sll $at, 3 # multiply index by sizeof(quad8)
addu $t6, $t2, $at # get a pointer to the region ($t2 = regions)
lw $t2, 0($t6) # get xy for first and second region points
lw $t6, 4($t6) # get xy for third and fourth region points
andi $a1, 3 # select color mode bits
sll $at, $a1, 7 # shift to bits 8 and 9
andi $v1, $a2, 0x1C # get bits 3 and 4-5 from resolved tpage/tpageinfo (tpage y index, tpage x index)
or $at, $v1 # or with color mode bits 8 and 9
srl $v1, $t3, 18
andi $v1, 3 # get bits 19 and 20 from texinfo word 2 (segment), as bits 1 and 2
or $at, $v1 # or with color mode, tpage y index, and tpage x index
andi $v1, $t5, 0x60 # get bits 6 and 7 from texinfo word 1 (semi-trans mode), as bits 6 and 7
or $at, $v1 # or with color mode, tpage y index, tpage x index, and segment
sll $at, 16 # shift or'ed values to the upper hword
andi $v0, $t3, 0x1F # get bits 1-5 from texinfo word 2 (offs_y)
sll $v0, 2 # multiply by 4 (as the value is stored / 4), moving up to bits 3-7
andi $v1, $a2, 0x80 # get bit 8 from resolved tpage (tpage y half)
or $v0, $v1 # or with offs_y bits 3-7
# (i.e. this will add 128 to the y offset if tpage is in the lower row of tpages in the texture window)
sll $v1, $v0, 8 # shift y_offs to upper byte of lower halfword
srl $v0, $t3, 10
andi $v0, 0xF8 # get bits 14-18 from texinfo word 2 (offs_x) as bits 4-8
srlv $v0, $a1 # divide by 2^(color_mode) (as the value is stored * 2^(color_mode))
or $a1, $v0, $v1 # or with the value with y_offs in upper byte
srl $v0, $t2, 16 # shift down xy value for the second region point
addu $v0, $a1 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 2)
or $v1, $at, $v0 # or with the value with color mode, y index (J), x index (I), and segment in upper hword
# this produces tpage id and uv values: ccttJIIXX|xxxxx??0|Yyyyyy00 (where segment is multiplied by 256 to extend the x index)
andi $at, $t5, 0xF # get bits 1-4 from texinfo word 1 (clut x/16, relative to tpage x, color mode 2 (4-bit) only)
andi $v0, $t3, 0x1FC0 # get bits 7-13 from texinfo word 2 (clut y, relative to tpage y)
or $at, $v0 # or the values
srl $v0, $a2, 4
andi $v0, 0xFFF0 # get bits 9-10 and 11-20 from resolved tpage (tpage x index, and tpage y location) as bits 5-6 and 7-16
# note: only bits 14 and 15 should potentially be set in tpage y location, else other bits will override the texinfo bits
or $at, $v0 # or with texinfo clut x/clut y values
# this produces a clut id: 0YYyyyyyyyXXxxxx
sll $at, 16 # shift clut id to upper halfword
andi $v0, $t2, 0xFFFF # select xy value for first region point
addu $v0, $a1 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 1)
or $v0, $at, $v0 # or with the value with clut id in upper halfword
andi $at, $t6, 0xFFFF # select xy value for third region point
addu $at, $a1 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 3)
srl $t6, 16 # shift down xy value for fourth region point
addu $t6, $a1 # add it to the or'ed x_offs/y_offs value (this produces uv for vert 4)
sw $v0, 0xC($a3) # store clut id and uv for vert 1 in the POLY_FT4 prim
sw $v1, 0x14($a3) # store tpage id and uv for vert 2 in the POLY_FT4
sh $at, 0x1C($a3) # store uv for vert 3 in the POLY_FT4
sh $t6, 0x24($a3) # store uv for vert 4 in the POLY_FT4
sub $t7, $t0, $t7 # get distance from far value offset
andi $v1, $t7, 0x1FFC # limit to valid offset in the ot (index < 2048)
slt $t7, $v1, $t7
beqz $t7, add_poly_ft4_1 # skip below 2 blocks if within the valid range
addu $v1, $a0, $v1 # get pointer to ot entry at that offset
add_poly_ft4_lim_ot_offset_1:
addiu $v1, $a0, 0x1FFC # else get pointer to ot entry at last offset
add_poly_ft4_1:
lw $at, 0($v1) # get ot entry currently at min offset
li $a0, 0xFFFFFF
and $v0, prim, $a0 # select lower 3 bytes of prim pointer
sw $v0, 0($v1) # replace entry at min offset with the selected bytes
lui $v1, 0x900 # load len for the POLY_FT4
or $at, $v1 # or with the replaced entry (thereby forming a link)
sw $at, 0(prim) # store it as the tag for the POLY_GT3 prim
addiu $at, prim, 0x28 # '(' # add sizeof(POLY_FT4) for next free location in primmem
sw $at, 0(p_prims_tail) # store the new prims_tail
transform_sprite_ret:
jr $ra # return
nop
|
wurthless-elektroniks/modern-loadfare | 1,752 | ppc/hwinit_delaydbg.s | #
# patch for hwinit that outputs delay programcounter stuff to the POST lines
#
.org 0x0280
hwinit_postcount_code_start:
# stubs - code in cbbpatch.py uses these instead of going to the routines directly
b hwinit_init # +0x00
b hwinit_delay_case # +0x04
b hwinit_done # +0x08
# exit points to be dropped in by cbbpatch
hwinit_register_setup_function:
b hwinit_register_setup_function
hwinit_interpreter_top:
b hwinit_interpreter_top
hwinit_exit:
b hwinit_exit
# ------------------------------------------------------------------------------------------------
hwinit_init:
bl hwinit_register_setup_function
b hwinit_interpreter_top
# ------------------------------------------------------------------------------------------------
hwinit_delay_case:
std %r5,-0xB0(%r1)
std %r6,-0xB8(%r1)
lis %r5,0x8000 # load POST base
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r6,0x88
rldicr %r6,%r6,56,7 # r6 <<= 56
std %r6,0x1010(%r5) # write to POST register
lis %r6,2
mtctr %r6
_wait_loop_1:
bdnz _wait_loop_1
sub %r6,%r16,%r3 # r6 = pc within program
rldicr %r6,%r6,56,7 # r6 <<= 56
std %r6,0x1010(%r5) # write to POST register
lis %r6,2
mtctr %r6
_wait_loop_2:
bdnz _wait_loop_2
sub %r6,%r16,%r3 # r6 = pc within program
rldicr %r6,%r6,48,7 # r6 <<= 48
std %r6,0x1010(%r5) # write to POST register
lis %r6,2
mtctr %r6
_wait_loop_3:
bdnz _wait_loop_3
b hwinit_interpreter_top
# keep scripts happy
mulli %r6,%r6,50
hwinit_done:
# return success and go to epilogue as normal
li %r5,1
b hwinit_exit
|
wurthless-elektroniks/modern-loadfare | 3,132 | ppc/hwinit_postcount_new.s | #
# Newer HWINIT postcounting code, kept separate to avoid breaking builds
#
.text
.equ BASE_POST, 0xA2
.equ BASE_AND, 0x0100
.org 0x0280
hwinit_postcount_code_start:
# stubs - code in cbbpatch.py uses these instead of going to the routines directly
b hwinit_init # +0x00
b hwinit_delay_case # +0x04
b hwinit_done # +0x08
# exit points to be dropped in by cbbpatch
hwinit_register_setup_function:
b hwinit_register_setup_function
hwinit_interpreter_top:
b hwinit_interpreter_top
hwinit_exit:
b hwinit_exit
hwinit_init:
mftb %r6 # read timebase counter
andis. %r6,%r6,BASE_AND
std %r6,-0xA8(%r1) # store in safe space on stack
# base POST must be setup always
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r7,BASE_POST
rldicr %r7,%r7,56,7
std %r7,0x1010(%r5)
bl hwinit_register_setup_function # call normal register setup function at 0x0D5C
# hook to hwinit_toggle_post might not be installed
b hwinit_interpreter_top
# ------------------------------------------------------------------------------------------------
hwinit_delay_case:
# normal hwinit code
mulli %r6,%r6,50
mftb %r8
add %r8,%r8,%r6
_hwinit_delay_loop:
mftb %r7
cmpld %r7,%r8
bgt hwinit_interpreter_top # original instruction is a ble
bl toggle_post
b _hwinit_delay_loop # and keep running the delay
# ------------------------------------------------------------------------------------------------
hwinit_done:
# setup POST register base (0x8000020000060000)
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
# clear POST bits 6/7
li %r7,0x2E
rldicr %r7,%r7,56,7 # r7 <<= 56
std %r7,0x1010(%r5) # write to POST register
# return success and go to epilogue as normal
li %r5,1
b hwinit_exit
toggle_post:
std %r5,-0xB0(%r1)
std %r6,-0xB8(%r1)
std %r7,-0xC0(%r1)
std %r8,-0xC8(%r1)
ld %r6,-0xA8(%r1) # read last poll
mftb %r5 # read timebase counter
andis. %r7,%r5,BASE_AND # check bit (1 << 27)
cmpld %r6,%r7 # has the bit flipped?
beq _toggle_post_exit # if it hasn't, exit
std %r7,-0xA8(%r1) # update last poll state
# setup POST register base (0x8000020000060000)
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r7,BASE_POST # keep POST bit 7 set so SMC can pick up on it
cmpwi %r6,0 # if the bit we checked earlier was 0, leave as-is
beq _toggle_post_send_post
ori %r7,%r7,0x40 # otherwise toggle POST bit 6
_toggle_post_send_post:
rldicr %r7,%r7,56,7 # r7 <<= 56
std %r7,0x1010(%r5) # write to POST register
_toggle_post_exit:
ld %r5,-0xB0(%r1)
ld %r6,-0xB8(%r1)
ld %r7,-0xC0(%r1)
ld %r8,-0xC8(%r1)
blr
hwinit_postcount_code_end:
|
wurthless-elektroniks/modern-loadfare | 4,319 | ppc/hwinit_smc_keepalive.s | #
# hwinit keepalive code using the SMC FIFOs instead of POST bits
#
# hwinit programcounter must be past this point before sending SMC messages
# otherwise we're talking to uninitialized PCI space
.equ HWINIT_MINIMUM_PC_VALUE, 0x0300
# keepalive signal (0xA2, 0xE2) - should blink RoL LEDs and reset watchdogs
.equ SMC_HWINIT_KEEPALIVE_MSGID, 0xA2
# "done" signal
.equ SMC_HWINIT_DONE_MSGID, 0xA8
.equ BASE_AND, 0x0100
.org 0x0280
hwinit_postcount_code_start:
# stubs - code in cbbpatch.py uses these instead of going to the routines directly
b hwinit_init # +0x00
b hwinit_delay_case # +0x04
b hwinit_done # +0x08
# exit points to be dropped in by cbbpatch
hwinit_register_setup_function:
b hwinit_register_setup_function
hwinit_interpreter_top:
b hwinit_interpreter_top
hwinit_exit:
b hwinit_exit
# ------------------------------------------------------------------------------------------------
hwinit_init:
# in contrast to the postcounter code this only reads the timebase counter.
# we can't talk to the SMC until the hwinit program has set up the BARs and sent command 0x12
# so we'll wait until that happens before sending the keepalive messages
mftb %r6 # read timebase counter
andis. %r6,%r6,BASE_AND
std %r6,-0xA8(%r1) # store in safe space on stack
bl hwinit_register_setup_function
b hwinit_interpreter_top
# ------------------------------------------------------------------------------------------------
hwinit_delay_case:
# normal hwinit code
mulli %r6,%r6,50
mftb %r8
add %r8,%r8,%r6
_hwinit_delay_loop:
mftb %r7
cmpld %r7,%r8
bgt hwinit_interpreter_top # original instruction is a ble
bl smc_ipc_tick
b _hwinit_delay_loop # and keep running the delay
hwinit_done:
lis %r5,0x8000 # point r5 at southbridge (0x80000200EA000000)
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0xEA00
lis %r6,0x0400 # set FIFO tx active
stw %r6,0x1084(%r5)
li %r6,SMC_HWINIT_DONE_MSGID # write command to FIFO (SMC will not reply)
rlwinm %r6,24,0,7
stw %r6,0x1080(%r5)
li %r6,0 # release FIFO
stw %r6,0x1084(%r5)
# return success and go to epilogue as normal
li %r5,1
b hwinit_exit
# ------------------------------------------------------------------------------------------------
smc_ipc_tick:
std %r5,-0xB0(%r1)
std %r6,-0xB8(%r1)
std %r7,-0xC0(%r1)
std %r8,-0xC8(%r1)
# check that hwinit interpreter is past a certain point before sending SMC messages.
# during hwinit, %r16 is the program counter and %r3 is the program base.
sub %r5,%r16,%r3
cmpwi %r5,HWINIT_MINIMUM_PC_VALUE
blt _smc_ipc_tick_exit
# otherwise, check timebase against last poll
ld %r6,-0xA8(%r1) # read last poll
mftb %r5 # read timebase counter
andis. %r7,%r5,BASE_AND # check bit
cmpld %r6,%r7 # has the bit flipped?
beq _smc_ipc_tick_exit # if it hasn't, exit
std %r7,-0xA8(%r1) # update last poll state
lis %r5,0x8000 # point r5 at southbridge (0x80000200EA000000)
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0xEA00
lis %r7,0x0400 # r7 = 0x04000000 (sets FIFO active)
stw %r7,0x1084(%r5) # start talking on FIFO
li %r7,SMC_HWINIT_KEEPALIVE_MSGID # prepare keepalive message
cmpwi %r6,0 # if the bit we checked earlier was 0, leave as-is
beq _toggle_post_send_post
ori %r7,%r7,0x40 # otherwise toggle bit 6 (0xA2, 0xE2, 0xA2, etc...)
_toggle_post_send_post:
rlwinm %r7,24,0,7 # SMC command has to be shifted left too
stw %r7,0x1080(%r5) # send SMC command (we don't care if it's acknowledged or not)
li %r7,0 # release FIFO
stw %r7,0x1084(%r5)
_smc_ipc_tick_exit:
ld %r5,-0xB0(%r1)
ld %r6,-0xB8(%r1)
ld %r7,-0xC0(%r1)
ld %r8,-0xC8(%r1)
blr
|
wurthless-elektroniks/RGH1.3 | 3,703 | ppc/hwinit_postcount_unified.s | #
# Unified HWINIT postcounting code
#
.text
.equ BASE_POST, 0xA2
.equ BASE_AND, 0x0100
.org 0x0280
hwinit_postcount_code_start:
# stubs - code in cbbpatch.py uses these instead of going to the routines directly
b hwinit_init # +0x00
b hwinit_toggle_post # +0x04
b hwinit_delay_case # +0x08
b hwinit_done # +0x0C
hwinit_init:
mftb %r6 # read timebase counter
andis. %r6,%r6,BASE_AND
std %r6,-0xA8(%r1) # store in safe space on stack
# base POST must be setup always
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r7,BASE_POST
rldicr %r7,%r7,56,7
std %r7,0x1010(%r5)
bl hwinit_register_setup_function # call normal register setup function at 0x0D5C
# hook to hwinit_toggle_post might not be installed
b hwinit_interpreter_top
# ------------------------------------------------------------------------------------------------
hwinit_toggle_post:
# our hook overwrites these instructions
cmpld %r16,%r4
bge hwinit_success # go to 0xDC4 in case it isn't hooked
# TODO: remove this or find alternative in case it isn't compatible with 6752.
# if this hook is enabled, the mainloop either slows down significantly or destabilizes and crashes.
# doing the post toggles in the delay block is enough to do post toggling on 5772.
bl toggle_post
b hwinit_continue_interpreting
# ------------------------------------------------------------------------------------------------
hwinit_delay_case:
# normal hwinit code
mulli %r6,%r6,50
mftb %r8
add %r8,%r8,%r6
_hwinit_delay_loop:
mftb %r7
cmpld %r7,%r8
bgt hwinit_toggle_post # original instruction is a ble
bl toggle_post
b _hwinit_delay_loop # and keep running the delay
# ------------------------------------------------------------------------------------------------
hwinit_done:
# setup POST register base (0x8000020000060000)
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
# clear POST bits 6/7
li %r7,0x2E
rldicr %r7,%r7,56,7 # r7 <<= 56
std %r7,0x1010(%r5) # write to POST register
# return success and go to epilogue as normal
li %r5,1
b hwinit_exit
toggle_post:
std %r5,-0xB0(%r1)
std %r6,-0xB8(%r1)
std %r7,-0xC0(%r1)
std %r8,-0xC8(%r1)
ld %r6,-0xA8(%r1) # read last poll
mftb %r5 # read timebase counter
andis. %r7,%r5,BASE_AND # check bit (1 << 27)
cmpld %r6,%r7 # has the bit flipped?
beq _toggle_post_exit # if it hasn't, exit
std %r7,-0xA8(%r1) # update last poll state
# setup POST register base (0x8000020000060000)
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r7,BASE_POST # keep POST bit 7 set so SMC can pick up on it
cmpwi %r6,0 # if the bit we checked earlier was 0, leave as-is
beq _toggle_post_send_post
ori %r7,%r7,0x40 # otherwise toggle POST bit 6
_toggle_post_send_post:
rldicr %r7,%r7,56,7 # r7 <<= 56
std %r7,0x1010(%r5) # write to POST register
_toggle_post_exit:
ld %r5,-0xB0(%r1)
ld %r6,-0xB8(%r1)
ld %r7,-0xC0(%r1)
ld %r8,-0xC8(%r1)
blr
hwinit_postcount_code_end:
.org 0x0998
hwinit_interpreter_top:
.org 0x09A0
hwinit_continue_interpreting:
.org 0xD5C
hwinit_register_setup_function:
.org 0xDC4
hwinit_success:
.org 0xDD0
hwinit_exit:
|
wurthless-elektroniks/RGH1.3 | 3,132 | ppc/hwinit_postcount_new.s | #
# Newer HWINIT postcounting code, kept separate to avoid breaking builds
#
.text
.equ BASE_POST, 0xA2
.equ BASE_AND, 0x0100
.org 0x0280
hwinit_postcount_code_start:
# stubs - code in cbbpatch.py uses these instead of going to the routines directly
b hwinit_init # +0x00
b hwinit_delay_case # +0x04
b hwinit_done # +0x08
# exit points to be dropped in by cbbpatch
hwinit_register_setup_function:
b hwinit_register_setup_function
hwinit_interpreter_top:
b hwinit_interpreter_top
hwinit_exit:
b hwinit_exit
hwinit_init:
mftb %r6 # read timebase counter
andis. %r6,%r6,BASE_AND
std %r6,-0xA8(%r1) # store in safe space on stack
# base POST must be setup always
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r7,BASE_POST
rldicr %r7,%r7,56,7
std %r7,0x1010(%r5)
bl hwinit_register_setup_function # call normal register setup function at 0x0D5C
# hook to hwinit_toggle_post might not be installed
b hwinit_interpreter_top
# ------------------------------------------------------------------------------------------------
hwinit_delay_case:
# normal hwinit code
mulli %r6,%r6,50
mftb %r8
add %r8,%r8,%r6
_hwinit_delay_loop:
mftb %r7
cmpld %r7,%r8
bgt hwinit_interpreter_top # original instruction is a ble
bl toggle_post
b _hwinit_delay_loop # and keep running the delay
# ------------------------------------------------------------------------------------------------
hwinit_done:
# setup POST register base (0x8000020000060000)
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
# clear POST bits 6/7
li %r7,0x2E
rldicr %r7,%r7,56,7 # r7 <<= 56
std %r7,0x1010(%r5) # write to POST register
# return success and go to epilogue as normal
li %r5,1
b hwinit_exit
toggle_post:
std %r5,-0xB0(%r1)
std %r6,-0xB8(%r1)
std %r7,-0xC0(%r1)
std %r8,-0xC8(%r1)
ld %r6,-0xA8(%r1) # read last poll
mftb %r5 # read timebase counter
andis. %r7,%r5,BASE_AND # check bit (1 << 27)
cmpld %r6,%r7 # has the bit flipped?
beq _toggle_post_exit # if it hasn't, exit
std %r7,-0xA8(%r1) # update last poll state
# setup POST register base (0x8000020000060000)
lis %r5,0x8000
ori %r5,%r5,0x0200
rldicr %r5,%r5,32,31
oris %r5,%r5,0x0006
li %r7,BASE_POST # keep POST bit 7 set so SMC can pick up on it
cmpwi %r6,0 # if the bit we checked earlier was 0, leave as-is
beq _toggle_post_send_post
ori %r7,%r7,0x40 # otherwise toggle POST bit 6
_toggle_post_send_post:
rldicr %r7,%r7,56,7 # r7 <<= 56
std %r7,0x1010(%r5) # write to POST register
_toggle_post_exit:
ld %r5,-0xB0(%r1)
ld %r6,-0xB8(%r1)
ld %r7,-0xC0(%r1)
ld %r8,-0xC8(%r1)
blr
hwinit_postcount_code_end:
|
wurthless-elektroniks/RGH1.3 | 6,648 | smc/rgh13_xenon.s | ;
; RGH1.3 code for Xenon/Elpis boards
; Actually only really useful for EXT+3
;
.include "xenondefs.inc"
RGH13_POST_6 equ gpio_dbg_led1
RGH13_POST_7 equ gpio_dbg_led2
; TODO: find safe value for this - for now we're leaving it be
RESET_WATCHDOG_TIMEOUT_TICKS equ 0xAF
CBB_HWINIT_POST6_TOGGLE_TIMEOUT equ 254
; define EXT_PLUS_3 so we get faster CB_A timeouts
; (PLL is basically useless on Waternoose)
EXT_PLUS_3 equ 1
; ------------------------------------------------------------------------------------
; the Xenon SMC program is really weird in that it leaves large chunks of memory uninitialized
;
; - 0x07E5: clear 0x2F~0x35
; - 0x0808: clear 0x35~0x67
; - 0x07DE: clear 0xBD~0xC2
; - 0x0801: clear 0xC2~0xE1
;
; 0xBC and upward seem unused so we use that.
; first up, variables that are supposed to get zeroed out on reset
; (0xBD clear loop will be patched to zero them)
VARBASE equ 0B0h
g_holdpowerbutton_counter equ VARBASE+0
g_turboreset_sm_state equ VARBASE+1
g_turboreset_sm_counter equ VARBASE+2
g_ledlightshow_watchdog_state equ VARBASE+3
g_ledlightshow_watchdog_death_counter equ VARBASE+4
; above that are variables that will persist between resets
g_hardreset_sm_init equ VARBASE-3
g_hardreset_sm_state equ VARBASE-2
g_power_up_cause_backup equ VARBASE-1
; ------------------------------------------------------------------------------------
;
; Patchlist
;
; ------------------------------------------------------------------------------------
.org 0x0000
mov dptr,#gpu_reset_deassert_start
mov dptr,#gpu_reset_deassert_end
mov dptr,#mainloop_reorg_start
mov dptr,#mainloop_reorg_end
mov dptr,#memclear_reposition_start
mov dptr,#memclear_reposition_end
mov dptr,#ipc_setled_reroute_start
mov dptr,#ipc_setled_reroute_end
mov dptr,#resetwatchdog_release_cpu_reset_start
mov dptr,#resetwatchdog_release_cpu_reset_end
mov dptr,#resetwatchdog_reload_counter_2_start
mov dptr,#resetwatchdog_reload_counter_2_end
mov dptr,#resetwatchdog_on_success_start
mov dptr,#resetwatchdog_on_success_end
mov dptr,#resetwatchdog_on_timeout_start
mov dptr,#resetwatchdog_on_timeout_end
mov dptr,#powerup_reroute_start
mov dptr,#powerup_reroute_end
mov dptr,#avpack_reroute_1_start
mov dptr,#avpack_reroute_1_end
mov dptr,#avpack_reroute_2_start
mov dptr,#avpack_reroute_2_end
mov dptr,#dbgled_readfcn_stubout_start
mov dptr,#dbgled_readfcn_stubout_end
mov dptr,#port3_ddr_set_all_inputs_1_start
mov dptr,#port3_ddr_set_all_inputs_1_end
mov dptr,#port3_ddr_set_all_inputs_2_start
mov dptr,#port3_ddr_set_all_inputs_2_end
mov dptr,#rgh13_common_code_start
mov dptr,#rgh13_common_code_end
.byte 0 ; end of list
; ------------------------------------------------------------------------------------
;
; Patches
;
; ------------------------------------------------------------------------------------
; 0x0078: function strobes FIFLG.3 several times before bringing GPU out of reset
; so remove that unnecessary behavior
.org 0x0078
gpu_reset_deassert_start:
setb gpio_gpu_rst_n
ret
gpu_reset_deassert_end:
.org 0x7B6
mainloop_reorg_start:
; we drop this reorg in where the debug led statemachine was
; (it's NOP'd out on hacked SMCs)
lcall 0x1CDE ; power event monitor (checks for button presses and acts on them)
lcall 0x1064 ; ???
lcall 0x0F55 ; powerup statemachine
lcall 0x11C4 ; reset watchdog (reboots if GetPowerUpCause isn't received in time)
lcall 0x0FF6 ; reset statemachine (performs actual hardware reset sequence)
lcall 0x0D94 ; powerdown statemachine
lcall rgh13_statemachines_exec ; our custom code below
mainloop_reorg_end:
; 0x07DE - zero out memory starting from 0xB8 instead
; so our work vars get init'd to zero
.org 0x07DE
memclear_reposition_start:
mov r0,#VARBASE
mov r2,#(0xC2-VARBASE)
memclear_reposition_end:
.org 0xB93
ipc_setled_reroute_start:
ljmp ipc_led_anim_has_arrived
ipc_setled_reroute_end:
.org 0x1148
resetwatchdog_release_cpu_reset_start:
lcall cpu_reset_handler
mov 0x3D,#RESET_WATCHDOG_TIMEOUT_TICKS
resetwatchdog_release_cpu_reset_end:
.org 0x115C
resetwatchdog_reload_counter_2_start:
mov 0x3D,#RESET_WATCHDOG_TIMEOUT_TICKS
resetwatchdog_reload_counter_2_end:
.org 0x117C
resetwatchdog_on_success_start:
ljmp on_reset_watchdog_done
resetwatchdog_on_success_end:
.org msftsmc_sysreset_watchdog_exec_state_10
resetwatchdog_on_timeout_start:
lcall on_reset_watchdog_timeout
ljmp 0x1197
resetwatchdog_on_timeout_end:
.org 0x1212
avpack_reroute_1_start:
lcall avpack_detect_reroute
avpack_reroute_1_end:
.org 0x1235
avpack_reroute_2_start:
lcall avpack_detect_reroute
avpack_reroute_2_end:
.org 0x1D72
powerup_reroute_start:
lcall powerup_event_callback
nop
powerup_reroute_end:
; 0x224E: reads dbg leds
; can likely skip this, and use the rest of the function as free space
.org 0x224E
dbgled_readfcn_stubout_start:
ret
; quality of life improvement: if no avpack present, pretend a composite cable
; is plugged in, so the system can boot headless without flashing the four red lights
;
; from https://gamesx.com/wiki/doku.php?id=av:xbox360av
; the avpack mode lines are pulled up by resistors on the motherboard
; and the cables themselves pull the pins low.
; if all avpack bits are 1, nothing's present.
avpack_detect_reroute:
lcall 0x2506 ; query avpack id and other stuff (bits 4~2 will be avpack id)
push acc
anl a,#0b11100
cjne a,#0b11100,_avpack_is_present
pop acc
anl a,#0b11100011
ret
_avpack_is_present:
pop acc
ret
dbgled_readfcn_stubout_end:
; 0x22B8: set pin directions among other things.
; we'll set all pins on port 3 to inputs.
; 0x22C1 - change to ORL DAT_SFR_a5,#0xFF
; 0x22EE - change to MOV DAT_SFR_a5,#0xFF
.org 0x22C1
port3_ddr_set_all_inputs_1_start:
orl gpioddr_port3,#0xFF
port3_ddr_set_all_inputs_1_end:
.org 0x22EE
port3_ddr_set_all_inputs_2_start:
mov gpioddr_port3,#0xFF
port3_ddr_set_all_inputs_2_end:
.org 0x2DAA
rgh13_common_code_start:
cpu_reset_handler:
lcall on_reset_watchdog_deassert_cpu_reset
ljmp msftsmc_deassert_cpu_reset
.include "rgh13.s"
rgh13_common_code_end:
.end |
wurthless-elektroniks/RGH1.3 | 5,715 | smc/rgh13_falcon.s | ;
; RGH1.3 code for Falcons
;
.include "falcondefs.inc"
RGH13_POST_6 equ gpio_gpu_reset_done
RGH13_POST_7 equ gpio_tiltsw_n
; timeout for normal reset watchdog
; default is 137 * 20 * 2 = 5480 ms
RESET_WATCHDOG_TIMEOUT_TICKS equ 137
; ------------------------------------------------------------------------------------
; these variables will be automatically zeroed out on reset
g_holdpowerbutton_counter equ 092h
g_turboreset_sm_state equ 093h
g_turboreset_sm_counter equ 094h
g_ledlightshow_watchdog_state equ 095h
g_ledlightshow_watchdog_death_counter equ 096h
; these variables will persist past a reboot
; see init_memclear_patch_start
g_hardreset_sm_init equ 097h
g_hardreset_sm_state equ 098h
g_power_up_cause_backup equ 099h
; 5772 CB_B starts with about a 320 ms delay between toggles then 166 ms thereafter
; although the first delay can be much shorter.
; other Falcons might take longer...
;
; default value is 14 * 20 = 400 ms (MUST match behavior in CB_B)
CBB_HWINIT_POST6_TOGGLE_TIMEOUT equ 35
; ------------------------------------------------------------------------------------
;
; Patchlist
;
; ------------------------------------------------------------------------------------
.org 0x0000
mov dptr,#mainloop_reorg_start
mov dptr,#mainloop_reorg_end
mov dptr,#init_memclear_patch_start
mov dptr,#init_memclear_patch_end
mov dptr,#ipc_setled_reroute_start
mov dptr,#ipc_setled_reroute_end
mov dptr,#skip_reading_gpu_reset_done_1_start
mov dptr,#skip_reading_gpu_reset_done_1_end
mov dptr,#skip_reading_gpu_reset_done_2_start
mov dptr,#skip_reading_gpu_reset_done_2_end
mov dptr,#resetwatchdog_release_cpu_reset_start
mov dptr,#resetwatchdog_release_cpu_reset_end
mov dptr,#resetwatchdog_reload_counter_2_start
mov dptr,#resetwatchdog_reload_counter_2_end
mov dptr,#resetwatchdog_on_success_start
mov dptr,#resetwatchdog_on_success_end
mov dptr,#resetwatchdog_on_timeout_start
mov dptr,#resetwatchdog_on_timeout_end
mov dptr,#powerup_reroute_start
mov dptr,#powerup_reroute_end
mov dptr,#tiltsw_nullify_start
mov dptr,#tiltsw_nullify_end
mov dptr,#rgh13_common_code_start
mov dptr,#rgh13_common_code_end
.byte 0 ; end of list
; ------------------------------------------------------------------------------------
;
; Patches
;
; ------------------------------------------------------------------------------------
; reorg mainloop to move calls up over the useless statemachine that reads DBG_LED0,
; so we can add a call to our custom RGH1.3 statemachine at the end
.org 0x07C2
mainloop_reorg_start:
lcall 0x1DCE ; power event monitor (checks for button presses and acts on them)
lcall 0x1196 ; no idea what this does
lcall 0x106D ; powerup statemachine
lcall 0x12C6 ; reset watchdog (reboots if GetPowerUpCause isn't received in time)
lcall 0x1112 ; hardware reset statemachine (actually resets hardware)
lcall 0x0EA4 ; powerdown statemachine
lcall rgh13_statemachines_exec ; our custom code below
mainloop_reorg_end:
; should have ended at 0x7D7 or we've overwritten bits of the mainloop
; make room for our hard reset state machine variables
; so they are in a safe space and don't get killed on reboot
.org 0x7EC
init_memclear_patch_start:
mov r2,#0x1A ; stop memory clear at 0x97, so 0x98, 0x99, 0x9A don't get overwritten on reboot
init_memclear_patch_end:
; reroute any power LED changes (via IPC) to custom code below
.org 0xC72
ipc_setled_reroute_start:
ljmp ipc_led_anim_has_arrived
ipc_setled_reroute_end:
; if CPU sends an error code to the SMC, then we need
; to cancel the LED lightshow watchdog to prevent reboots
.org 0xCF0
ipc_displayerror_reroute_start:
lcall ipc_displayerror_has_arrived
nop
ipc_displayerror_reroute_end:
; GPU_RESET_DONE reads in reset watchdog must be patched out to avoid RRoD
; RGH3 does this too
.org 0x11D4
skip_reading_gpu_reset_done_1_start:
sjmp 0x11E8
skip_reading_gpu_reset_done_1_end:
.org 0x11FF
skip_reading_gpu_reset_done_2_start:
sjmp 0x1216
skip_reading_gpu_reset_done_2_end:
.org 0x1271
resetwatchdog_release_cpu_reset_start:
lcall cpu_reset_handler ; 0x1271, 3 bytes
mov 0x3D,#RESET_WATCHDOG_TIMEOUT_TICKS ; 0x1274, 3 bytes
resetwatchdog_release_cpu_reset_end:
.org 0x1282
resetwatchdog_reload_counter_2_start:
mov 0x3D,#RESET_WATCHDOG_TIMEOUT_TICKS
resetwatchdog_reload_counter_2_end:
; reset watchdog patch: GetPowerUpCause arrived
; so jump to custom code to start the LED lightshow watchdog
; (I had problems monitoring g_has_getpowerupcause_arrived)
.org 0x129F
resetwatchdog_on_success_start:
ljmp on_reset_watchdog_done
resetwatchdog_on_success_end:
.org msftsmc_sysreset_watchdog_exec_state_10
resetwatchdog_on_timeout_start:
lcall on_reset_watchdog_timeout
ljmp 0x12BA
resetwatchdog_on_timeout_end:
.org 0x1E62
powerup_reroute_start:
lcall powerup_event_callback
nop ; because we overwrote two CLR opcodes
powerup_reroute_end:
; patch tilt switch read routine so it always returns 0
.org 0x25AA
tiltsw_nullify_start:
clr cy
ret
tiltsw_nullify_end:
.org 0x2D10
rgh13_common_code_start:
.include "rgh13.s"
cpu_reset_handler:
lcall on_reset_watchdog_deassert_cpu_reset
ljmp msftsmc_deassert_cpu_reset
rgh13_common_code_end:
.end
|
wurthless-elektroniks/RGH1.3 | 6,389 | smc/rgh13_jasper.s | ;
; RGH1.3 code for Jasper
;
; horrible hack
ifdef JASPER_FOR_FALCON
JASPER equ 0
; from rgh13_falcon.s, but also seems to work fine without this
RESET_WATCHDOG_TIMEOUT_TICKS equ 137
else
JASPER equ 1
; timeout for normal reset watchdog
; default for jasper is 100 * 20 * 2 = 4000 ms
RESET_WATCHDOG_TIMEOUT_TICKS equ 100
endif
.include "jasperdefs.inc"
RGH13_POST_6 equ gpio_gpu_reset_done
ifdef POST7_TILTSW
RGH13_POST_7 equ gpio_tiltsw_n
endif
ifdef POST7_EXTPWR
RGH13_POST_7 equ gpio_ext_pwr_on_n
endif
ifdef POST7_CHKSTOP
RGH13_POST_7 equ gpio_smc_cpu_chkstop_detect
endif
; ------------------------------------------------------------------------------------
; these variables will be automatically zeroed out on reset
g_holdpowerbutton_counter equ 093h
g_turboreset_sm_state equ 094h
g_turboreset_sm_counter equ 095h
g_ledlightshow_watchdog_state equ 096h
g_ledlightshow_watchdog_death_counter equ 097h
; these variables will persist past a reboot
; see init_memclear_patch_start
g_hardreset_sm_init equ 098h
g_hardreset_sm_state equ 099h
g_power_up_cause_backup equ 09Ah
; 6752 on my test Jasper toggles A2/E2 only once, but the delay is somewhere around 660 ms.
;
; default value is 35 * 20 = 700 ms
CBB_HWINIT_POST6_TOGGLE_TIMEOUT equ 35
; ------------------------------------------------------------------------------------
;
; Patchlist
;
; ------------------------------------------------------------------------------------
.org 0x0000
mov dptr,#mainloop_reorg_start
mov dptr,#mainloop_reorg_end
mov dptr,#init_memclear_patch_start
mov dptr,#init_memclear_patch_end
mov dptr,#ipc_setled_reroute_start
mov dptr,#ipc_setled_reroute_end
mov dptr,#on_reset_done_reroute_start
mov dptr,#on_reset_done_reroute_end
mov dptr,#skip_reading_gpu_reset_done_1_start
mov dptr,#skip_reading_gpu_reset_done_1_end
mov dptr,#skip_reading_gpu_reset_done_2_start
mov dptr,#skip_reading_gpu_reset_done_2_end
mov dptr,#resetwatchdog_reload_counter_1_start
mov dptr,#resetwatchdog_reload_counter_1_end
mov dptr,#resetwatchdog_reload_counter_2_start
mov dptr,#resetwatchdog_reload_counter_2_end
mov dptr,#resetwatchdog_on_success_start
mov dptr,#resetwatchdog_on_success_end
mov dptr,#resetwatchdog_on_timeout_start
mov dptr,#resetwatchdog_on_timeout_end
mov dptr,#powerup_reroute_start
mov dptr,#powerup_reroute_end
if RGH13_POST_7=gpio_tiltsw_n
.include "rgh13_jasper_tiltsw_decls.inc"
endif
if RGH13_POST_7=gpio_ext_pwr_on_n
.include "rgh13_jasper_extpwr_decls.inc"
endif
if RGH13_POST_7=gpio_smc_cpu_chkstop_detect
.include "rgh13_jasper_chkstop_decls.inc"
endif
mov dptr,#rgh13_common_code_start
mov dptr,#rgh13_common_code_end
.byte 0 ; end of list
; ------------------------------------------------------------------------------------
;
; Patches
;
; ------------------------------------------------------------------------------------
; mainloop re-org
.org 0x07C2
mainloop_reorg_start:
; we drop this reorg in where the debug led statemachine was
; (it's NOP'd out on hacked SMCs)
lcall 0x1DE9 ; power event monitor (checks for button presses and acts on them)
lcall 0x119B ; no idea what this does
lcall 0x1072 ; powerup statemachine
lcall 0x12D5 ; reset watchdog (reboots if GetPowerUpCause isn't received in time)
lcall 0x1127 ; reset statemachine (performs actual hardware reset sequence)
lcall 0x0EA9 ; powerdown statemachine
lcall rgh13_statemachines_exec ; our custom code below
; should end at 0x07D7 - if it doesn't, we've broken the build
mainloop_reorg_end:
; make room for our hard reset state machine variables
; so they are in a safe space and don't get killed on reboot
.org 0x7EC
init_memclear_patch_start:
mov r2,#0x1A ; stop memory clear at 0x97, so 0x98, 0x99, 0x9A don't get overwritten on reboot
init_memclear_patch_end:
; reroute any power LED changes (via IPC) to custom code below
.org 0xC77
ipc_setled_reroute_start:
ljmp ipc_led_anim_has_arrived
ipc_setled_reroute_end:
; if CPU sends an error code to the SMC, then we need
; to cancel the LED lightshow watchdog to prevent reboots
.org 0xCF5
ipc_displayerror_reroute_start:
lcall ipc_displayerror_has_arrived
nop
ipc_displayerror_reroute_end:
.org 0x11DB
on_reset_done_reroute_start:
lcall cpu_reset_handler
on_reset_done_reroute_end:
; GPU_RESET_DONE reads in reset watchdog must be patched out to avoid RRoD
; RGH3 does this too
.org 0x11E0
skip_reading_gpu_reset_done_1_start:
sjmp 0x11F5
skip_reading_gpu_reset_done_1_end:
.org 0x1208
skip_reading_gpu_reset_done_2_start:
sjmp 0x1220
skip_reading_gpu_reset_done_2_end:
.org 0x1279
resetwatchdog_reload_counter_1_start:
mov 0x3D,#RESET_WATCHDOG_TIMEOUT_TICKS
resetwatchdog_reload_counter_1_end:
.org 0x1290
resetwatchdog_reload_counter_2_start:
mov 0x3D,#RESET_WATCHDOG_TIMEOUT_TICKS
resetwatchdog_reload_counter_2_end:
; reset watchdog patch: GetPowerUpCause arrived
; so jump to custom code to start the LED lightshow watchdog
; (I had problems monitoring g_has_getpowerupcause_arrived)
.org 0x12AD
resetwatchdog_on_success_start:
ljmp on_reset_watchdog_done
resetwatchdog_on_success_end:
.org 0x12BA
resetwatchdog_on_timeout_start:
lcall on_reset_watchdog_timeout
ljmp 0x12D1
resetwatchdog_on_timeout_end:
.org 0x1E7D
powerup_reroute_start:
lcall powerup_event_callback
nop ; because we overwrote two CLR opcodes
powerup_reroute_end:
if RGH13_POST_7=gpio_tiltsw_n
.include "rgh13_jasper_tiltsw_patches.s"
endif
if RGH13_POST_7=gpio_ext_pwr_on_n
.include "rgh13_jasper_extpwr_patches.s"
endif
if RGH13_POST_7=gpio_smc_cpu_chkstop_detect
.include "rgh13_jasper_chkstop_patches.s"
endif
.org 0x2D73
rgh13_common_code_start:
cpu_reset_handler:
lcall on_reset_watchdog_deassert_cpu_reset
ljmp msftsmc_deassert_cpu_reset
.include "rgh13.s"
rgh13_common_code_end:
.end |
wurthless-elektroniks/RGH1.3 | 17,783 | smc/rgh13.s | ;
; RGH1.3 common turbo SMC code
; Also includes badjasper stuff
;
ifndef JASPER
JASPER equ 0
endif
; ------------------------------------------------------------------------------------
;
; Common definitions/consts
;
; ------------------------------------------------------------------------------------
; amount of time the bootrom has to load and run CB_A.
; if it doesn't in time, we raise RRoD 0022 because this is a major hardware fault.
; default is 50 * 20 = 1000 ms
BOOTROM_TIMEOUT equ 50
; amount of time CB_A has to finish execution and de-assert POST bit 7.
; default value is 16 * 20 = 320 ms
; for EXT+3 it's 8
ifdef EXT_PLUS_3
CBA_POST7_TIMEOUT equ 8
else
CBA_POST7_TIMEOUT equ 16
endif
; amount of time CB_X has to load and run CB_B.
; you may need to adjust this for certain CB_Bs.
; default value is 4 * 20 = 80 ms
ifndef CBX_POST6_TIMEOUT
CBX_POST6_TIMEOUT equ 4
endif
; amount of time CB_B has to make it to HWINIT.
; remember: CB_B is hacked to assert POST bit 7 while HWINIT is running.
; default value is 12 * 20 = 240 ms
ifndef CBB_PRE_HWINIT_POST7_TIMEOUT
CBB_PRE_HWINIT_POST7_TIMEOUT equ 12
endif
; CBB_HWINIT_POST6_TOGGLE_TIMEOUT in rgh13_falcon.s and rgh13_jasper.s
; specifies the period between which POST bit 6 must toggle during HWINIT.
; this can loop over and over, the main reset watchdog will reboot if HWINIT takes too long.
; note the behavior is console-dependent.
; once GetPowerUpCause arrives the CPU has this amount of time to make it to the LED bootanim
; or else we will reboot. this is a workaround for some systems that crash late in the boot,
; primarily jaspers, but falcons are known to do this too.
; default value is 125 * 20 * 2 = 5000 ms, adjust as necessary
LED_LIGHTSHOW_SM_TIMEOUT_TICKS equ 125
; LED blink patterns
;
; assuming the system is lying flat:
; bit 0/4 - top left
; bit 1/5 - top right
; bit 2/6 - bottom left
; bit 3/7 - bottom right
; ggggrrrr
; 32103210
LEDPATTERN_RED equ 0b00000001
; ggggrrrr
; 32103210
LEDPATTERN_RED_RED equ 0b00000011
; ggggrrrr
; 32103210
LEDPATTERN_RED_ORANGE equ 0b00100011
; ggggrrrr
; 32103210
LEDPATTERN_RED_ORANGE_RED equ 0b00100111
; ggggrrrr
; 32103210
LEDPATTERN_RED_ORANGE_ORANGE equ 0b01100111
; ggggrrrr
; 32103210
LEDPATTERN_RED_ORANGE_GREEN equ 0b01100011
; RRoD Classic, but orange so we don't confuse it with a normal system error
LED_ERROR_PATTERN equ 0b11011101
; ------------------------------------------------------------------------------------
rgh13_statemachines_exec:
acall turboreset_sm_exec ; manages POST watchdogs
acall hardreset_sm_exec ; manages hard reset stuff, if necessary
acall led_lightshow_sm_exec ; manages ring of light bootanim watchdog
ljmp holdpowerbutton_sm_exec ; hold powerbutton for 5 seconds to power off
; ------------------------------------------------------------------------------------
;
; Turbo reset
; Monitor POST bits 6/7 during the boot and reboot if we don't like what we see
;
; ------------------------------------------------------------------------------------
on_reset_watchdog_timeout:
; assert /CPU_RST_N now so POST bits drop to 0
; if we don't do this then our POST bit check will fail and we'll get a RRoD
clr gpio_cpu_rst_n
; turn off statemachines that might be running
acall _led_lightshow_sm_go_idle
sjmp _turboreset_sm_disarm
; hook from SMC code lands here
;
; code for reset watchdog state 7 (load counter and go to state 8) varies between falcon/jasper.
; falcon just de-asserts reset immediately and loads the counter.
; jasper does a bit of extra stuff before the counter gets loaded.
on_reset_watchdog_deassert_cpu_reset:
; these POST bits MUST be zero or there's a wiring issue.
; in which case, refuse to let the system run.
jb RGH13_POST_6,_post_bits_not_zero_at_reset
jb RGH13_POST_7,_post_bits_not_zero_at_reset
mov r0,#g_turboreset_sm_state ; enable statemachine
mov @r0,#1
mov r0,#g_turboreset_sm_counter ; with bootrom timeout
mov @r0,#BOOTROM_TIMEOUT
; clear LEDs, they'll have been left on from previous (failed) attempts
mov a,#0
ljmp rol_set_leds
_post_bits_not_zero_at_reset:
mov g_rrod_errorcode_1,#0xFF ; RRoD error code 3333
mov g_rrod_errorcode_2,#0xFF
sjmp _setup_rrod
_turboreset_sm_disarm:
mov r0,#g_turboreset_sm_state
mov @r0,#0
ret
; main turboreset statemachine code here
turboreset_sm_exec:
; short-circuit if reset watchdog statemachine suddenly turned off
; or if the main watchdog requested a reset
jnb g_sysreset_watchdog_should_run,_turboreset_sm_disarm
jb g_requesting_reset,_turboreset_sm_disarm
; also cut the state machine off if RRoD raised
jb g_force_rrod_3,_turboreset_sm_disarm
jb g_force_rrod_4,_turboreset_sm_disarm
jb g_force_rrod_ipc,_turboreset_sm_disarm
; read the state, it's time to start execution
mov r0,#g_turboreset_sm_state
mov a,@r0
;
; state 1 - wait for POST bits 6 and 7 to rise
;
cjne a,#1,_turboreset_sm_exec_state_2
jnb RGH13_POST_6,_turboreset_sm_state_1_timeout
jnb RGH13_POST_7,_turboreset_sm_state_1_timeout
_turboreset_go_state_2:
mov r0,#g_turboreset_sm_state
mov @r0,#2
mov r0,#g_turboreset_sm_counter
mov @r0,#CBA_POST7_TIMEOUT
; flash red on ring of light
mov a,#LEDPATTERN_RED
sjmp _turboreset_set_leds_and_return
_turboreset_sm_state_1_timeout:
; tick timer down
mov r0,#g_turboreset_sm_counter
dec @r0
cjne @r0,#0,_turboreset_do_nothing
; old behavior here was to RRoD 0000/4444
; however POST bus noise and other things caused false positives.
; if the CPU is stuck in a coma, just reboot the whole thing...
ljmp hard_reset
_setup_rrod:
mov g_rrod_set_zero,#0
mov g_rrod_base_error_pattern,#LED_ERROR_PATTERN
mov r0,#g_rol_af_cell
mov @r0,g_rrod_base_error_pattern
setb g_force_rrod_3 ; forces immediate power down
setb g_force_rrod_4
setb g_force_rrod_ipc
setb g_rol_update_pending
clr g_sysreset_watchdog_should_run
mov r0,#g_turboreset_sm_state
mov @r0,#0
_turboreset_do_nothing:
ret
;
; state 2 - POST bit 7 (connected to TILTSW) must fall in time
; (the glitch chip sends the malformed reset pulse during this phase)
;
_turboreset_sm_exec_state_2:
cjne a,#2,_turboreset_sm_exec_state_3
jnb RGH13_POST_7,_turboreset_sm_go_state_3 ; has to fall in time
; tick timer down
mov r0,#g_turboreset_sm_counter
dec @r0
cjne @r0,#0,_turboreset_do_nothing
; we've timed out - call common disarm code below instead of repeating it
acall _turboreset_sm_disarm
; for badjaspers, hard reset always
ifdef HARD_RESET_ON_CBA_FAIL
sjmp hard_reset
else
sjmp _turboreset_reboot_via_sysreset_watchdog
endif
_turboreset_sm_go_state_3:
mov r0,#g_turboreset_sm_state
mov @r0,#3
mov r0,#g_turboreset_sm_counter
mov @r0,#CBX_POST6_TIMEOUT
mov a,#LEDPATTERN_RED_RED
sjmp _turboreset_set_leds_and_return
;
; state 3 - wait for POST bit 6 to fall
; if it doesn't fall in time, CB_X crashed and we need to reboot
;
_turboreset_sm_exec_state_3:
cjne a,#3,_turboreset_sm_exec_state_4
jnb RGH13_POST_6,_turboreset_sm_go_state_4
_turboreset_sm_common_timeout_code:
mov r0,#g_turboreset_sm_counter
dec @r0
cjne @r0,#0,_turboreset_do_nothing
; we've timed out - call common disarm code below instead of repeating it
acall _turboreset_sm_disarm
_turboreset_reboot_via_sysreset_watchdog:
ljmp msftsmc_sysreset_watchdog_exec_state_10
_turboreset_sm_go_state_4:
mov r0,#g_turboreset_sm_state
mov @r0,#4
mov r0,#g_turboreset_sm_counter
mov @r0,#CBB_PRE_HWINIT_POST7_TIMEOUT
mov a,#LEDPATTERN_RED_ORANGE
sjmp _turboreset_set_leds_and_return
;
; state 4 - wait for POST bit 7 to rise again
; and if it doesn't, the CPU crashed before HWINIT
;
_turboreset_sm_exec_state_4:
cjne a,#4,_turboreset_sm_exec_state_5
jb RGH13_POST_7,_turboreset_sm_go_state_5
sjmp _turboreset_sm_common_timeout_code
_turboreset_sm_go_state_5:
mov r0,#g_turboreset_sm_state
mov @r0,#5
mov r0,#g_turboreset_sm_counter
mov @r0,#CBB_HWINIT_POST6_TOGGLE_TIMEOUT
; A2/E2 toggles only once on Jasper so display red/orange/red there
if JASPER == 1
mov a,#LEDPATTERN_RED_ORANGE_RED
else
mov a,#LEDPATTERN_RED_ORANGE
endif
_turboreset_set_leds_and_return:
ljmp rol_set_leds
;
; state 5 and 6 - monitor POST bit 6 toggles.
; this will loop over and over with state 6 until POST bit 7 falls
; and if HWINIT goes into an infinite loop the normal SMC watchdog will reboot
;
_turboreset_sm_exec_state_5:
cjne a,#5,_turboreset_sm_exec_state_6
jnb RGH13_POST_7,_turboreset_sm_go_state_7 ; run as long as POST bit 7 is high
jb RGH13_POST_6,_turboreset_sm_go_state_6 ; state 5 waits for rise
sjmp _turboreset_sm_common_timeout_code
_turboreset_sm_go_state_6:
mov r0,#g_turboreset_sm_state
mov @r0,#6
mov r0,#g_turboreset_sm_counter
mov @r0,#CBB_HWINIT_POST6_TOGGLE_TIMEOUT
mov a,#LEDPATTERN_RED_ORANGE_RED
sjmp _turboreset_set_leds_and_return
_turboreset_sm_exec_state_6:
cjne a,#6,_turboreset_sm_exec_state_7
jnb RGH13_POST_7,_turboreset_sm_go_state_7 ; run as long as POST bit 7 is high
jnb RGH13_POST_6,_turboreset_sm_go_state_5 ; state 6 waits for fall
sjmp _turboreset_sm_common_timeout_code
_turboreset_sm_go_state_7:
mov r0,#g_turboreset_sm_state
mov @r0,#7
; set LEDs red/orange/orange
mov a,#LEDPATTERN_RED_ORANGE_ORANGE
sjmp _turboreset_set_leds_and_return
;
; state 7 - monitor POST bit 7 and go back to state 5/6 if it rises again
; this is mostly intended to catch POST bit 7 sometimes registering as 0 but could
; also catch errors and force a reboot
;
_turboreset_sm_exec_state_7:
cjne a,#7,_turboreset_do_nothing
jnb RGH13_POST_7,_turboreset_do_nothing
jb RGH13_POST_6,_turboreset_sm_go_state_6
sjmp _turboreset_sm_go_state_5
; ------------------------------------------------------------------------------------
;
; Hard reset code, needed for some very uncooperative Jaspers
;
; ------------------------------------------------------------------------------------
hard_reset:
; if power button is held, power off immediately so the user can actually power the console down.
; if we don't do this, the console will bootloop until power is disconnected.
jnb gpio_powersw_n,_hard_reset_power_off
; stash powerup cause because it will get trashed on reboot
mov r0,#g_power_up_cause
mov a,@r0
mov r0,#g_power_up_cause_backup
mov @r0,a
; activate statemachine below
mov r0,#g_hardreset_sm_state ; init first state
mov @r0,#0x43
; and force a hard reset
; (this should NOT clear our work var space!!)
_hard_reset_power_off:
jmp 0x0000
hardreset_init_vars:
mov r0,#g_power_up_cause_backup ; power button by default
mov @r0,0x11
mov r0,#g_hardreset_sm_state ; statemachine off by default
mov @r0,#0
mov r0,#g_hardreset_sm_init ; SM now initialized
mov @r0,#69
_hardreset_do_nothing:
ret
hardreset_sm_exec:
; init work vars if not initialized already
mov r0,#g_hardreset_sm_init
mov a,@r0
cjne a,#69,hardreset_init_vars
; actual state machine execution here
mov r0,#g_hardreset_sm_state
mov a,@r0
cjne a,#0x43,_hardreset_sm_check_case_54
; first state is just to load the next state
; this delays the power-on by 20 or so ms, giving things time to cool down a bit
mov r0,#g_hardreset_sm_state
mov @r0,#0x54
ret
_hardreset_sm_check_case_54:
cjne a,#0x54,_hardreset_do_nothing
; push power button and go to next state
; (callback below will pick up on this)
setb g_powerswitch_pushed
mov r0,#g_hardreset_sm_state
mov @r0,#0x63
ret
powerup_event_callback:
; lcall overwrote these
; these are consistent between falcon/jasper so excuse the hardcoding
; (they are also the same on xenon)
clr 020h.3 ; this is normally set in the IPC poweron/reset command
clr 021h.1 ; "eject button pressed" flag
; if hard reset didn't cause us to get here, stop
mov r0,#g_hardreset_sm_state
cjne @r0,#0x63,_hardreset_do_nothing
; otherwise restore powerup cause and continue
mov @r0,#0 ; turn off hard reset statemachine
mov r0,#g_power_up_cause_backup ; read stashed powerup cause
mov a,@r0
mov r0,#g_power_up_cause ; write it back to restore it
mov @r0,a
ret
; ------------------------------------------------------------------------------------
;
; Ring of light bootanim watchdog
; Reboots system if the bootanim isn't received in time
;
; ------------------------------------------------------------------------------------
; we land in here once the main reset watchdog finishes execution
on_reset_watchdog_done:
; we overwrote this instruction (to turn the watchdog off)
; so do so here
clr g_sysreset_watchdog_should_run
; set RoL pattern red, orange, green
mov a,#LEDPATTERN_RED_ORANGE_GREEN
acall _turboreset_set_leds_and_return
; start LED lightshow watchdog
mov r0,#g_ledlightshow_watchdog_state
mov @r0,#1
led_lightshow_sm_reload_counter_and_exit:
mov r0,#g_ledlightshow_watchdog_death_counter
mov @r0,#LED_LIGHTSHOW_SM_TIMEOUT_TICKS
led_lightshow_sm_do_nothing:
ret
led_lightshow_sm_exec:
; short-circuit if powerdown statemachine starts
; so that we don't power up again by mistake
jb g_powerdown_sm_should_run,_led_lightshow_sm_go_idle
mov r0,#g_ledlightshow_watchdog_state
mov a,@r0
cjne a,#0,_led_lightshow_sm_do_state_1
sjmp _led_lightshow_sm_go_idle
_led_lightshow_sm_do_state_1:
; for all "active" states:
; cut the state machine off if RRoD raised
jb g_force_rrod_3,_led_lightshow_sm_rrod_raised
jb g_force_rrod_4,_led_lightshow_sm_rrod_raised
jb g_force_rrod_ipc,_led_lightshow_sm_rrod_raised
mov r0,#g_ledlightshow_watchdog_state
mov a,@r0
cjne a,#1,_led_lightshow_sm_do_state_2
; tick death counter down
; djnz can't be used here because our vars are in high memory
mov r0,#g_ledlightshow_watchdog_death_counter
dec @r0
cjne @r0,#0,led_lightshow_sm_do_nothing
; timed out - reload counter and go to state 2
mov r0,#g_ledlightshow_watchdog_state
mov @r0,#2
sjmp led_lightshow_sm_reload_counter_and_exit
_led_lightshow_sm_do_state_2:
cjne a,#2,led_lightshow_sm_do_nothing
; tick death counter down
; djnz can't be used here because our vars are in high memory
mov r0,#g_ledlightshow_watchdog_death_counter
dec @r0
cjne @r0,#0,led_lightshow_sm_do_nothing
; reset on timeout
ljmp hard_reset
; IPC hook lands here
ipc_led_anim_has_arrived:
; this setb was overwritten by our ljmp earlier so restore it
setb g_rol_run_bootanim
; REALLY make sure the CPU requested that we play the animation
; (carry should still be set coming into this function)
jnc led_lightshow_sm_do_nothing
; it has, so clear our LED state and let the ring of light run normally
mov a,#0
acall rol_set_leds
; other IPC hook lands here
ipc_displayerror_has_arrived:
; these instructions were trashed by our lcall
; addresses are different between falcon/jasper, but the code is still the same
mov g_rrod_errorcode_1,r2
mov g_rrod_errorcode_2,r3
_led_lightshow_sm_rrod_raised:
; if any RRoD raised, clear LED state
mov a,#0
acall rol_set_leds
_led_lightshow_sm_go_idle:
mov r0,#g_ledlightshow_watchdog_state
mov @r0,#0
ret
;
; Common function to set Ring of Light LEDs
; a - LED states (upper 4 bits green, lower 4 bits red)
;
rol_set_leds:
mov r0,#g_rol_ledstate
mov @r0,a
jz _clear_led_priority_bit
; bits 5/7 must be set for argon sm to display things
; bit 5 is apparently some "high priority" bit and when it is set
; nothing else will display on the ring
mov a,g_rol_flags
orl a,#0b10100000
_rol_set_leds_finish:
mov g_rol_flags,a
; and this bit has to be set too
setb g_rol_update_pending
ret
; clear priority flag when turning LEDs off
_clear_led_priority_bit:
mov a,g_rol_flags
anl a,#0b11011111
sjmp _rol_set_leds_finish
; ------------------------------------------------------------------------------------
;
; Quality of life improvement: force power down if power button held 5 seconds
; (saves people the effort of unplugging their system if it freezes)
;
; ------------------------------------------------------------------------------------
holdpowerbutton_sm_exec:
jnb gpio_psu_12v_enable,_holdpowerbutton_idle ; power must be on (active high)
jnb gpio_powersw_n,_holdpowerbutton_held ; and powerbutton must be held (active low)
_holdpowerbutton_idle:
; 250 * 20 = 5000 ms
mov r0,#g_holdpowerbutton_counter
mov @r0,#250
_holdpowerbutton_done:
ret
_holdpowerbutton_held:
; decrement counter
mov r0,#g_holdpowerbutton_counter
dec @r0
cjne @r0,#0,_holdpowerbutton_done
; when it hits 0, force hard reset to standby mode
ljmp 0x0000
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,284 | Chip/CMSIS/startup/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,214 | Chip/CMSIS/startup/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM12_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM12_IRQHandler
B TIM12_IRQHandler
PUBWEAK TIM13_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM13_IRQHandler
B TIM13_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 13,207 | Chip/CMSIS/startup/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 16,132 | Chip/CMSIS/startup/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,521 | Chip/CMSIS/startup/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,669 | Chip/CMSIS/startup/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 16,119 | Chip/CMSIS/startup/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,581 | Chip/CMSIS/startup/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,079 | Chip/CMSIS/startup/arm/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,346 | Chip/CMSIS/startup/arm/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 13,758 | Chip/CMSIS/startup/arm/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,597 | Chip/CMSIS/startup/arm/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,458 | Chip/CMSIS/startup/arm/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,145 | Chip/CMSIS/startup/arm/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,398 | Chip/CMSIS/startup/arm/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 13,352 | Chip/CMSIS/startup/arm/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wustyuyi/NamelessCotrunQuad_V1.0 | 9,471 | Chip/CMSIS/startup/gcc/startup_stm32f10x_ld.s | /**
******************************************************************************
* @file startup_stm32f10x_ld.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Low Density devices.*/
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,040 | Chip/CMSIS/startup/gcc/startup_stm32f10x_hd_vl.s | /**
******************************************************************************
* @file startup_stm32f10x_hd_vl.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x High Density Value Line Devices vector table for RIDE7
* toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM32100E-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word CEC_IRQHandler
.word TIM12_IRQHandler
.word TIM13_IRQHandler
.word TIM14_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_5_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x High Density Value line devices. */
/*******************************************************************************
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak TIM12_IRQHandler
.thumb_set TIM12_IRQHandler,Default_Handler
.weak TIM13_IRQHandler
.thumb_set TIM13_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 10,659 | Chip/CMSIS/startup/gcc/startup_stm32f10x_md_vl.s | /**
******************************************************************************
* @file startup_stm32f10x_md_vl.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x Medium Density Value Line Devices vector table for RIDE7
* toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word CEC_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x01CC. This is for boot in RAM mode for
STM32F10x Medium Value Line Density devices. */
/*******************************************************************************
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,796 | Chip/CMSIS/startup/gcc/startup_stm32f10x_xl.s | /**
******************************************************************************
* @file startup_stm32f10x_xl.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x XL-Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3210E-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM9_IRQHandler
.word TIM1_UP_TIM10_IRQHandler
.word TIM1_TRG_COM_TIM11_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_TIM12_IRQHandler
.word TIM8_UP_TIM13_IRQHandler
.word TIM8_TRG_COM_TIM14_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FSMC_IRQHandler
.word SDIO_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_5_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x XL Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 9,911 | Chip/CMSIS/startup/gcc/startup_stm32f10x_md.s | /**
******************************************************************************
* @file startup_stm32f10x_md.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F10x Medium Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,695 | Chip/CMSIS/startup/gcc/startup_stm32f10x_hd.s | /**
******************************************************************************
* @file startup_stm32f10x_hd.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3210E-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FSMC_IRQHandler
.word SDIO_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_5_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x High Density devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,604 | Chip/CMSIS/startup/gcc/startup_stm32f10x_cl.s | /**
******************************************************************************
* @file startup_stm32f10x_cl.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR
* address.
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word OTG_FS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ETH_IRQHandler
.word ETH_WKUP_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word OTG_FS_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x Connectivity line Devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 10,179 | Chip/CMSIS/startup/gcc/startup_stm32f10x_ld_vl.s | /**
******************************************************************************
* @file startup_stm32f10x_ld_vl.s
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief STM32F10x Low Density Value Line Devices vector table for RIDE7
* toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word CEC_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x01CC. This is for boot in RAM mode for
STM32F10x Low Density Value Line devices. */
/*******************************************************************************
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,284 | Chip/CMSIS/startup/iar/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,214 | Chip/CMSIS/startup/iar/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM12_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM12_IRQHandler
B TIM12_IRQHandler
PUBWEAK TIM13_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM13_IRQHandler
B TIM13_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 13,207 | Chip/CMSIS/startup/iar/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 16,132 | Chip/CMSIS/startup/iar/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,521 | Chip/CMSIS/startup/iar/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 15,733 | Chip/CMSIS/startup/iar/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 16,119 | Chip/CMSIS/startup/iar/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 12,581 | Chip/CMSIS/startup/iar/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
wustyuyi/NamelessCotrunQuad_V1.0 | 5,710 | Chip/DSP_Lib/TransformFunctions/arm_bitreversal2.S | ;/* ----------------------------------------------------------------------
;* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
;*
;* $Date: 12. March 2014
;* $Revision: V1.4.4
;*
;* Project: CMSIS DSP Library
;* Title: arm_bitreversal2.S
;*
;* Description: This is the arm_bitreversal_32 function done in
;* assembly for maximum speed. This function is called
;* after doing an fft to reorder the output. The function
;* is loop unrolled by 2. arm_bitreversal_16 as well.
;*
;* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions
;* are met:
;* - Redistributions of source code must retain the above copyright
;* notice, this list of conditions and the following disclaimer.
;* - Redistributions in binary form must reproduce the above copyright
;* notice, this list of conditions and the following disclaimer in
;* the documentation and/or other materials provided with the
;* distribution.
;* - Neither the name of ARM LIMITED nor the names of its contributors
;* may be used to endorse or promote products derived from this
;* software without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
;* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;* -------------------------------------------------------------------- */
#if defined(__CC_ARM) // Keil
#define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
#define LABEL
#elif defined(__IASMARM__) // IAR
#define CODESECT SECTION `.text`:CODE
#define PROC
#define LABEL
#define ENDP
#define EXPORT PUBLIC
#elif defined(__CSMC__) /* Cosmic */
#define CODESECT switch .text
#define THUMB
#define EXPORT xdef
#define PROC :
#define LABEL :
#define ENDP
#define arm_bitreversal_32 _arm_bitreversal_32
#elif defined (__GNUC__) // GCC
#define THUMB .thumb
#define CODESECT .section .text
#define EXPORT .global
#define PROC :
#define LABEL :
#define ENDP
#define END
.syntax unified
#endif
CODESECT
THUMB
;/*
;* @brief In-place bit reversal function.
;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
;* @param[in] bitRevLen bit reversal table length
;* @param[in] *pBitRevTab points to bit reversal table.
;* @return none.
;*/
EXPORT arm_bitreversal_32
EXPORT arm_bitreversal_16
#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS)
arm_bitreversal_32 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_32_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
LDR r5,[r2,#4]
LDR r4,[r6,#4]
STR r5,[r6,#4]
STR r4,[r2,#4]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r6}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_16_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
LSRS r2,r2,#1
LSRS r6,r6,#1
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r6}
BX lr
ENDP
#else
arm_bitreversal_32 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8
ADD r9,r0,r9
ADD r2,r0,r2
ADD r12,r0,r12
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
LDR r7,[r9,#4]
LDR r6,[r8,#4]
LDR r5,[r2,#4]
LDR r4,[r12,#4]
STR r6,[r9,#4]
STR r7,[r8,#4]
STR r5,[r12,#4]
STR r4,[r2,#4]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r9}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8,LSR #1
ADD r9,r0,r9,LSR #1
ADD r2,r0,r2,LSR #1
ADD r12,r0,r12,LSR #1
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r9}
BX lr
ENDP
#endif
END
|
wuxx/nanoDAP-HS | 29,171 | test/stm32f405rgt6/led_test/CORE/startup_stm32f40_41xxx.s | ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.4.0
;* @date : 04-August-2014
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 12,079 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 15,346 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 13,758 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 15,597 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 12,458 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 15,145 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 15,398 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP-HS | 13,352 | test/stm32f103c8t6/led_test/Libraries/CMSIS/startup/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/icesugar | 2,656 | src/advanced/picorv32/firmware/custom_ops.S | // This is free and unencumbered software released into the public domain.
//
// Anyone is free to copy, modify, publish, use, compile, sell, or
// distribute this software, either in source code form or as a compiled
// binary, for any purpose, commercial or non-commercial, and by any
// means.
#define regnum_q0 0
#define regnum_q1 1
#define regnum_q2 2
#define regnum_q3 3
#define regnum_x0 0
#define regnum_x1 1
#define regnum_x2 2
#define regnum_x3 3
#define regnum_x4 4
#define regnum_x5 5
#define regnum_x6 6
#define regnum_x7 7
#define regnum_x8 8
#define regnum_x9 9
#define regnum_x10 10
#define regnum_x11 11
#define regnum_x12 12
#define regnum_x13 13
#define regnum_x14 14
#define regnum_x15 15
#define regnum_x16 16
#define regnum_x17 17
#define regnum_x18 18
#define regnum_x19 19
#define regnum_x20 20
#define regnum_x21 21
#define regnum_x22 22
#define regnum_x23 23
#define regnum_x24 24
#define regnum_x25 25
#define regnum_x26 26
#define regnum_x27 27
#define regnum_x28 28
#define regnum_x29 29
#define regnum_x30 30
#define regnum_x31 31
#define regnum_zero 0
#define regnum_ra 1
#define regnum_sp 2
#define regnum_gp 3
#define regnum_tp 4
#define regnum_t0 5
#define regnum_t1 6
#define regnum_t2 7
#define regnum_s0 8
#define regnum_s1 9
#define regnum_a0 10
#define regnum_a1 11
#define regnum_a2 12
#define regnum_a3 13
#define regnum_a4 14
#define regnum_a5 15
#define regnum_a6 16
#define regnum_a7 17
#define regnum_s2 18
#define regnum_s3 19
#define regnum_s4 20
#define regnum_s5 21
#define regnum_s6 22
#define regnum_s7 23
#define regnum_s8 24
#define regnum_s9 25
#define regnum_s10 26
#define regnum_s11 27
#define regnum_t3 28
#define regnum_t4 29
#define regnum_t5 30
#define regnum_t6 31
// x8 is s0 and also fp
#define regnum_fp 8
#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
#define picorv32_getq_insn(_rd, _qs) \
r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
#define picorv32_setq_insn(_qd, _rs) \
r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
#define picorv32_retirq_insn() \
r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
#define picorv32_maskirq_insn(_rd, _rs) \
r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
#define picorv32_waitirq_insn(_rd) \
r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
#define picorv32_timer_insn(_rd, _rs) \
r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
|
wuxx/icesugar | 9,508 | src/advanced/picorv32/firmware/start.S | // This is free and unencumbered software released into the public domain.
//
// Anyone is free to copy, modify, publish, use, compile, sell, or
// distribute this software, either in source code form or as a compiled
// binary, for any purpose, commercial or non-commercial, and by any
// means.
#define ENABLE_QREGS
#define ENABLE_HELLO
#define ENABLE_RVTST
#define ENABLE_SIEVE
#define ENABLE_MULTST
#define ENABLE_STATS
#ifndef ENABLE_QREGS
# undef ENABLE_RVTST
#endif
// Only save registers in IRQ wrapper that are to be saved by the caller in
// the RISC-V ABI, with the excpetion of the stack pointer. The IRQ handler
// will save the rest if necessary. I.e. skip x3, x4, x8, x9, and x18-x27.
#undef ENABLE_FASTIRQ
#include "custom_ops.S"
.section .text
.global irq
.global hello
.global sieve
.global multest
.global hard_mul
.global hard_mulh
.global hard_mulhsu
.global hard_mulhu
.global hard_div
.global hard_divu
.global hard_rem
.global hard_remu
.global stats
reset_vec:
// no more than 16 bytes here !
picorv32_waitirq_insn(zero)
picorv32_maskirq_insn(zero, zero)
j start
/* Interrupt handler
**********************************/
.balign 16
irq_vec:
/* save registers */
#ifdef ENABLE_QREGS
picorv32_setq_insn(q2, x1)
picorv32_setq_insn(q3, x2)
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
picorv32_getq_insn(x2, q0)
sw x2, 0*4(x1)
picorv32_getq_insn(x2, q2)
sw x2, 1*4(x1)
picorv32_getq_insn(x2, q3)
sw x2, 2*4(x1)
#ifdef ENABLE_FASTIRQ
sw x5, 5*4(x1)
sw x6, 6*4(x1)
sw x7, 7*4(x1)
sw x10, 10*4(x1)
sw x11, 11*4(x1)
sw x12, 12*4(x1)
sw x13, 13*4(x1)
sw x14, 14*4(x1)
sw x15, 15*4(x1)
sw x16, 16*4(x1)
sw x17, 17*4(x1)
sw x28, 28*4(x1)
sw x29, 29*4(x1)
sw x30, 30*4(x1)
sw x31, 31*4(x1)
#else
sw x3, 3*4(x1)
sw x4, 4*4(x1)
sw x5, 5*4(x1)
sw x6, 6*4(x1)
sw x7, 7*4(x1)
sw x8, 8*4(x1)
sw x9, 9*4(x1)
sw x10, 10*4(x1)
sw x11, 11*4(x1)
sw x12, 12*4(x1)
sw x13, 13*4(x1)
sw x14, 14*4(x1)
sw x15, 15*4(x1)
sw x16, 16*4(x1)
sw x17, 17*4(x1)
sw x18, 18*4(x1)
sw x19, 19*4(x1)
sw x20, 20*4(x1)
sw x21, 21*4(x1)
sw x22, 22*4(x1)
sw x23, 23*4(x1)
sw x24, 24*4(x1)
sw x25, 25*4(x1)
sw x26, 26*4(x1)
sw x27, 27*4(x1)
sw x28, 28*4(x1)
sw x29, 29*4(x1)
sw x30, 30*4(x1)
sw x31, 31*4(x1)
#endif
#else // ENABLE_QREGS
#ifdef ENABLE_FASTIRQ
sw gp, 0*4+0x200(zero)
sw x1, 1*4+0x200(zero)
sw x2, 2*4+0x200(zero)
sw x5, 5*4+0x200(zero)
sw x6, 6*4+0x200(zero)
sw x7, 7*4+0x200(zero)
sw x10, 10*4+0x200(zero)
sw x11, 11*4+0x200(zero)
sw x12, 12*4+0x200(zero)
sw x13, 13*4+0x200(zero)
sw x14, 14*4+0x200(zero)
sw x15, 15*4+0x200(zero)
sw x16, 16*4+0x200(zero)
sw x17, 17*4+0x200(zero)
sw x28, 28*4+0x200(zero)
sw x29, 29*4+0x200(zero)
sw x30, 30*4+0x200(zero)
sw x31, 31*4+0x200(zero)
#else
sw gp, 0*4+0x200(zero)
sw x1, 1*4+0x200(zero)
sw x2, 2*4+0x200(zero)
sw x3, 3*4+0x200(zero)
sw x4, 4*4+0x200(zero)
sw x5, 5*4+0x200(zero)
sw x6, 6*4+0x200(zero)
sw x7, 7*4+0x200(zero)
sw x8, 8*4+0x200(zero)
sw x9, 9*4+0x200(zero)
sw x10, 10*4+0x200(zero)
sw x11, 11*4+0x200(zero)
sw x12, 12*4+0x200(zero)
sw x13, 13*4+0x200(zero)
sw x14, 14*4+0x200(zero)
sw x15, 15*4+0x200(zero)
sw x16, 16*4+0x200(zero)
sw x17, 17*4+0x200(zero)
sw x18, 18*4+0x200(zero)
sw x19, 19*4+0x200(zero)
sw x20, 20*4+0x200(zero)
sw x21, 21*4+0x200(zero)
sw x22, 22*4+0x200(zero)
sw x23, 23*4+0x200(zero)
sw x24, 24*4+0x200(zero)
sw x25, 25*4+0x200(zero)
sw x26, 26*4+0x200(zero)
sw x27, 27*4+0x200(zero)
sw x28, 28*4+0x200(zero)
sw x29, 29*4+0x200(zero)
sw x30, 30*4+0x200(zero)
sw x31, 31*4+0x200(zero)
#endif
#endif // ENABLE_QREGS
/* call interrupt handler C function */
lui sp, %hi(irq_stack)
addi sp, sp, %lo(irq_stack)
// arg0 = address of regs
lui a0, %hi(irq_regs)
addi a0, a0, %lo(irq_regs)
// arg1 = interrupt type
#ifdef ENABLE_QREGS
picorv32_getq_insn(a1, q1)
#else
addi a1, tp, 0
#endif
// call to C function
jal ra, irq
/* restore registers */
#ifdef ENABLE_QREGS
// new irq_regs address returned from C code in a0
addi x1, a0, 0
lw x2, 0*4(x1)
picorv32_setq_insn(q0, x2)
lw x2, 1*4(x1)
picorv32_setq_insn(q1, x2)
lw x2, 2*4(x1)
picorv32_setq_insn(q2, x2)
#ifdef ENABLE_FASTIRQ
lw x5, 5*4(x1)
lw x6, 6*4(x1)
lw x7, 7*4(x1)
lw x10, 10*4(x1)
lw x11, 11*4(x1)
lw x12, 12*4(x1)
lw x13, 13*4(x1)
lw x14, 14*4(x1)
lw x15, 15*4(x1)
lw x16, 16*4(x1)
lw x17, 17*4(x1)
lw x28, 28*4(x1)
lw x29, 29*4(x1)
lw x30, 30*4(x1)
lw x31, 31*4(x1)
#else
lw x3, 3*4(x1)
lw x4, 4*4(x1)
lw x5, 5*4(x1)
lw x6, 6*4(x1)
lw x7, 7*4(x1)
lw x8, 8*4(x1)
lw x9, 9*4(x1)
lw x10, 10*4(x1)
lw x11, 11*4(x1)
lw x12, 12*4(x1)
lw x13, 13*4(x1)
lw x14, 14*4(x1)
lw x15, 15*4(x1)
lw x16, 16*4(x1)
lw x17, 17*4(x1)
lw x18, 18*4(x1)
lw x19, 19*4(x1)
lw x20, 20*4(x1)
lw x21, 21*4(x1)
lw x22, 22*4(x1)
lw x23, 23*4(x1)
lw x24, 24*4(x1)
lw x25, 25*4(x1)
lw x26, 26*4(x1)
lw x27, 27*4(x1)
lw x28, 28*4(x1)
lw x29, 29*4(x1)
lw x30, 30*4(x1)
lw x31, 31*4(x1)
#endif
picorv32_getq_insn(x1, q1)
picorv32_getq_insn(x2, q2)
#else // ENABLE_QREGS
// new irq_regs address returned from C code in a0
addi a1, zero, 0x200
beq a0, a1, 1f
ebreak
1:
#ifdef ENABLE_FASTIRQ
lw gp, 0*4+0x200(zero)
lw x1, 1*4+0x200(zero)
lw x2, 2*4+0x200(zero)
lw x5, 5*4+0x200(zero)
lw x6, 6*4+0x200(zero)
lw x7, 7*4+0x200(zero)
lw x10, 10*4+0x200(zero)
lw x11, 11*4+0x200(zero)
lw x12, 12*4+0x200(zero)
lw x13, 13*4+0x200(zero)
lw x14, 14*4+0x200(zero)
lw x15, 15*4+0x200(zero)
lw x16, 16*4+0x200(zero)
lw x17, 17*4+0x200(zero)
lw x28, 28*4+0x200(zero)
lw x29, 29*4+0x200(zero)
lw x30, 30*4+0x200(zero)
lw x31, 31*4+0x200(zero)
#else
lw gp, 0*4+0x200(zero)
lw x1, 1*4+0x200(zero)
lw x2, 2*4+0x200(zero)
// do not restore x3 (gp)
lw x4, 4*4+0x200(zero)
lw x5, 5*4+0x200(zero)
lw x6, 6*4+0x200(zero)
lw x7, 7*4+0x200(zero)
lw x8, 8*4+0x200(zero)
lw x9, 9*4+0x200(zero)
lw x10, 10*4+0x200(zero)
lw x11, 11*4+0x200(zero)
lw x12, 12*4+0x200(zero)
lw x13, 13*4+0x200(zero)
lw x14, 14*4+0x200(zero)
lw x15, 15*4+0x200(zero)
lw x16, 16*4+0x200(zero)
lw x17, 17*4+0x200(zero)
lw x18, 18*4+0x200(zero)
lw x19, 19*4+0x200(zero)
lw x20, 20*4+0x200(zero)
lw x21, 21*4+0x200(zero)
lw x22, 22*4+0x200(zero)
lw x23, 23*4+0x200(zero)
lw x24, 24*4+0x200(zero)
lw x25, 25*4+0x200(zero)
lw x26, 26*4+0x200(zero)
lw x27, 27*4+0x200(zero)
lw x28, 28*4+0x200(zero)
lw x29, 29*4+0x200(zero)
lw x30, 30*4+0x200(zero)
lw x31, 31*4+0x200(zero)
#endif
#endif // ENABLE_QREGS
picorv32_retirq_insn()
#ifndef ENABLE_QREGS
.balign 0x200
#endif
irq_regs:
// registers are saved to this memory region during interrupt handling
// the program counter is saved as register 0
.fill 32,4
// stack for the interrupt handler
.fill 128,4
irq_stack:
/* Main program
**********************************/
start:
/* zero-initialize all registers */
addi x1, zero, 0
addi x2, zero, 0
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
#ifdef ENABLE_HELLO
/* set stack pointer */
lui sp,(128*1024)>>12
/* call hello C code */
jal ra,hello
#endif
/* running tests from riscv-tests */
#ifdef ENABLE_RVTST
# define TEST(n) \
.global n; \
addi x1, zero, 1000; \
picorv32_timer_insn(zero, x1); \
jal zero,n; \
.global n ## _ret; \
n ## _ret:
#else
# define TEST(n) \
.global n ## _ret; \
n ## _ret:
#endif
TEST(lui)
TEST(auipc)
TEST(j)
TEST(jal)
TEST(jalr)
TEST(beq)
TEST(bne)
TEST(blt)
TEST(bge)
TEST(bltu)
TEST(bgeu)
TEST(lb)
TEST(lh)
TEST(lw)
TEST(lbu)
TEST(lhu)
TEST(sb)
TEST(sh)
TEST(sw)
TEST(addi)
TEST(slti) // also tests sltiu
TEST(xori)
TEST(ori)
TEST(andi)
TEST(slli)
TEST(srli)
TEST(srai)
TEST(add)
TEST(sub)
TEST(sll)
TEST(slt) // what is with sltu ?
TEST(xor)
TEST(srl)
TEST(sra)
TEST(or)
TEST(and)
TEST(mulh)
TEST(mulhsu)
TEST(mulhu)
TEST(mul)
TEST(div)
TEST(divu)
TEST(rem)
TEST(remu)
TEST(simple)
/* set stack pointer */
lui sp,(128*1024)>>12
/* set gp and tp */
lui gp, %hi(0xdeadbeef)
addi gp, gp, %lo(0xdeadbeef)
addi tp, gp, 0
#ifdef ENABLE_SIEVE
/* call sieve C code */
jal ra,sieve
#endif
#ifdef ENABLE_MULTST
/* call multest C code */
jal ra,multest
#endif
#ifdef ENABLE_STATS
/* call stats C code */
jal ra,stats
#endif
/* print "DONE\n" */
lui a0,0x10000000>>12
addi a1,zero,'D'
addi a2,zero,'O'
addi a3,zero,'N'
addi a4,zero,'E'
addi a5,zero,'\n'
sw a1,0(a0)
sw a2,0(a0)
sw a3,0(a0)
sw a4,0(a0)
sw a5,0(a0)
li a0, 0x20000000
li a1, 123456789
sw a1,0(a0)
/* trap */
ebreak
/* Hard mul functions for multest.c
**********************************/
hard_mul:
mul a0, a0, a1
ret
hard_mulh:
mulh a0, a0, a1
ret
hard_mulhsu:
mulhsu a0, a0, a1
ret
hard_mulhu:
mulhu a0, a0, a1
ret
hard_div:
div a0, a0, a1
ret
hard_divu:
divu a0, a0, a1
ret
hard_rem:
rem a0, a0, a1
ret
hard_remu:
remu a0, a0, a1
ret
|
wuxx/icesugar | 2,431 | src/advanced/picorv32/picosoc/start.s | .section .text
start:
# zero-initialize register file
addi x1, zero, 0
# x2 (sp) is initialized by reset
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
# Update LEDs
li a0, 0x03000000
li a1, 1
sw a1, 0(a0)
# zero initialize entire scratchpad memory
li a0, 0x00000000
setmemloop:
sw a0, 0(a0)
addi a0, a0, 4
blt a0, sp, setmemloop
# Update LEDs
li a0, 0x03000000
li a1, 3
sw a1, 0(a0)
# copy data section
la a0, _sidata
la a1, _sdata
la a2, _edata
bge a1, a2, end_init_data
loop_init_data:
lw a3, 0(a0)
sw a3, 0(a1)
addi a0, a0, 4
addi a1, a1, 4
blt a1, a2, loop_init_data
end_init_data:
# Update LEDs
li a0, 0x03000000
li a1, 7
sw a1, 0(a0)
# zero-init bss section
la a0, _sbss
la a1, _ebss
bge a0, a1, end_init_bss
loop_init_bss:
sw zero, 0(a0)
addi a0, a0, 4
blt a0, a1, loop_init_bss
end_init_bss:
# Update LEDs
li a0, 0x03000000
li a1, 15
sw a1, 0(a0)
# call main
call main
loop:
j loop
.global flashio_worker_begin
.global flashio_worker_end
.balign 4
flashio_worker_begin:
# a0 ... data pointer
# a1 ... data length
# a2 ... optional WREN cmd (0 = disable)
# address of SPI ctrl reg
li t0, 0x02000000
# Set CS high, IO0 is output
li t1, 0x120
sh t1, 0(t0)
# Enable Manual SPI Ctrl
sb zero, 3(t0)
# Send optional WREN cmd
beqz a2, flashio_worker_L1
li t5, 8
andi t2, a2, 0xff
flashio_worker_L4:
srli t4, t2, 7
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
slli t2, t2, 1
andi t2, t2, 0xff
addi t5, t5, -1
bnez t5, flashio_worker_L4
sb t1, 0(t0)
# SPI transfer
flashio_worker_L1:
beqz a1, flashio_worker_L3
li t5, 8
lbu t2, 0(a0)
flashio_worker_L2:
srli t4, t2, 7
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
lbu t4, 0(t0)
andi t4, t4, 2
srli t4, t4, 1
slli t2, t2, 1
or t2, t2, t4
andi t2, t2, 0xff
addi t5, t5, -1
bnez t5, flashio_worker_L2
sb t2, 0(a0)
addi a0, a0, 1
addi a1, a1, -1
j flashio_worker_L1
flashio_worker_L3:
# Back to MEMIO mode
li t1, 0x80
sb t1, 3(t0)
ret
.balign 4
flashio_worker_end:
|
wuxx/icesugar | 2,651 | src/advanced/picorv32/tests/xor.S | # See LICENSE for license details.
#*****************************************************************************
# xor.S
#-----------------------------------------------------------------------------
#
# Test xor instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, xor, 0 );
TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,786 | src/advanced/picorv32/tests/sub.S | # See LICENSE for license details.
#*****************************************************************************
# sub.S
#-----------------------------------------------------------------------------
#
# Test sub instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sub, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sub, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sub, 0xfffffffc, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sub, 0x00008000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, sub, 0x80000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, sub, 0x80008000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 8, sub, 0xffff8001, 0x00000000, 0x00007fff );
TEST_RR_OP( 9, sub, 0x7fffffff, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 10, sub, 0x7fff8000, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 11, sub, 0x7fff8001, 0x80000000, 0x00007fff );
TEST_RR_OP( 12, sub, 0x80007fff, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 13, sub, 0x00000001, 0x00000000, 0xffffffff );
TEST_RR_OP( 14, sub, 0xfffffffe, 0xffffffff, 0x00000001 );
TEST_RR_OP( 15, sub, 0x00000000, 0xffffffff, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
TEST_RR_ZEROSRC12( 36, sub, 0 );
TEST_RR_ZERODEST( 37, sub, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,180 | src/advanced/picorv32/tests/lw.S | # See LICENSE for license details.
#*****************************************************************************
# lw.S
#-----------------------------------------------------------------------------
#
# Test lw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lw, 0x00ff00ff, 0, tdat );
TEST_LD_OP( 3, lw, 0xff00ff00, 4, tdat );
TEST_LD_OP( 4, lw, 0x0ff00ff0, 8, tdat );
TEST_LD_OP( 5, lw, 0xf00ff00f, 12, tdat );
# Test with negative offset
TEST_LD_OP( 6, lw, 0x00ff00ff, -12, tdat4 );
TEST_LD_OP( 7, lw, 0xff00ff00, -8, tdat4 );
TEST_LD_OP( 8, lw, 0x0ff00ff0, -4, tdat4 );
TEST_LD_OP( 9, lw, 0xf00ff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x3, 0x00ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
lw x3, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0xff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
lw x3, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lw, 0x0ff00ff0, 4, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lw, 0xf00ff00f, 4, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lw, 0xff00ff00, 4, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x0ff00ff0, 4, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xf00ff00f, 4, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xff00ff00, 4, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x3, tdat; \
lw x2, 0(x3); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x3, tdat; \
lw x2, 0(x3); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0x00ff00ff
tdat2: .word 0xff00ff00
tdat3: .word 0x0ff00ff0
tdat4: .word 0xf00ff00f
RVTEST_DATA_END
|
wuxx/icesugar | 2,538 | src/advanced/picorv32/tests/bgeu.S | # See LICENSE for license details.
#*****************************************************************************
# bgeu.S
#-----------------------------------------------------------------------------
#
# Test bgeu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 );
TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 24, x1, 3, \
li x1, 1; \
bgeu x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,056 | src/advanced/picorv32/tests/slti.S | # See LICENSE for license details.
#*****************************************************************************
# slti.S
#-----------------------------------------------------------------------------
#
# Test slti instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slti, 0, 0x00000000, 0x000 );
TEST_IMM_OP( 3, slti, 0, 0x00000001, 0x001 );
TEST_IMM_OP( 4, slti, 1, 0x00000003, 0x007 );
TEST_IMM_OP( 5, slti, 0, 0x00000007, 0x003 );
TEST_IMM_OP( 6, slti, 0, 0x00000000, 0x800 );
TEST_IMM_OP( 7, slti, 1, 0x80000000, 0x000 );
TEST_IMM_OP( 8, slti, 1, 0x80000000, 0x800 );
TEST_IMM_OP( 9, slti, 1, 0x00000000, 0x7ff );
TEST_IMM_OP( 10, slti, 0, 0x7fffffff, 0x000 );
TEST_IMM_OP( 11, slti, 0, 0x7fffffff, 0x7ff );
TEST_IMM_OP( 12, slti, 1, 0x80000000, 0x7ff );
TEST_IMM_OP( 13, slti, 0, 0x7fffffff, 0x800 );
TEST_IMM_OP( 14, slti, 0, 0x00000000, 0xfff );
TEST_IMM_OP( 15, slti, 1, 0xffffffff, 0x001 );
TEST_IMM_OP( 16, slti, 0, 0xffffffff, 0xfff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 );
TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 3,372 | src/advanced/picorv32/tests/sll.S | # See LICENSE for license details.
#*****************************************************************************
# sll.S
#-----------------------------------------------------------------------------
#
# Test sll instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sll, 0x00000001, 0x00000001, 0 );
TEST_RR_OP( 3, sll, 0x00000002, 0x00000001, 1 );
TEST_RR_OP( 4, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_OP( 5, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_OP( 6, sll, 0x80000000, 0x00000001, 31 );
TEST_RR_OP( 7, sll, 0xffffffff, 0xffffffff, 0 );
TEST_RR_OP( 8, sll, 0xfffffffe, 0xffffffff, 1 );
TEST_RR_OP( 9, sll, 0xffffff80, 0xffffffff, 7 );
TEST_RR_OP( 10, sll, 0xffffc000, 0xffffffff, 14 );
TEST_RR_OP( 11, sll, 0x80000000, 0xffffffff, 31 );
TEST_RR_OP( 12, sll, 0x21212121, 0x21212121, 0 );
TEST_RR_OP( 13, sll, 0x42424242, 0x21212121, 1 );
TEST_RR_OP( 14, sll, 0x90909080, 0x21212121, 7 );
TEST_RR_OP( 15, sll, 0x48484000, 0x21212121, 14 );
TEST_RR_OP( 16, sll, 0x80000000, 0x21212121, 31 );
# Verify that shifts only use bottom five bits
TEST_RR_OP( 17, sll, 0x21212121, 0x21212121, 0xffffffe0 );
TEST_RR_OP( 18, sll, 0x42424242, 0x21212121, 0xffffffe1 );
TEST_RR_OP( 19, sll, 0x90909080, 0x21212121, 0xffffffe7 );
TEST_RR_OP( 20, sll, 0x48484000, 0x21212121, 0xffffffee );
TEST_RR_OP( 21, sll, 0x00000000, 0x21212120, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sll, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x80000000, 0x00000001, 31 );
TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
TEST_RR_ZEROSRC12( 42, sll, 0 );
TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,185 | src/advanced/picorv32/tests/addi.S | # See LICENSE for license details.
#*****************************************************************************
# addi.S
#-----------------------------------------------------------------------------
#
# Test addi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 );
TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 );
TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 );
TEST_IMM_OP( 5, addi, 0xfffff800, 0x00000000, 0x800 );
TEST_IMM_OP( 6, addi, 0x80000000, 0x80000000, 0x000 );
TEST_IMM_OP( 7, addi, 0x7ffff800, 0x80000000, 0x800 );
TEST_IMM_OP( 8, addi, 0x000007ff, 0x00000000, 0x7ff );
TEST_IMM_OP( 9, addi, 0x7fffffff, 0x7fffffff, 0x000 );
TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff );
TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff );
TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 );
TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff );
TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 );
TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff );
TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 );
TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
TEST_IMM_ZERODEST( 25, addi, 33, 50 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 1,680 | src/advanced/picorv32/tests/andi.S | # See LICENSE for license details.
#*****************************************************************************
# andi.S
#-----------------------------------------------------------------------------
#
# Test andi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,960 | src/advanced/picorv32/tests/mulhu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhu.S
#-----------------------------------------------------------------------------
#
# Test mulhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulhu, 0 );
TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,182 | src/advanced/picorv32/tests/lhu.S | # See LICENSE for license details.
#*****************************************************************************
# lhu.S
#-----------------------------------------------------------------------------
#
# Test lhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lhu, 0x000000ff, 0, tdat );
TEST_LD_OP( 3, lhu, 0x0000ff00, 2, tdat );
TEST_LD_OP( 4, lhu, 0x00000ff0, 4, tdat );
TEST_LD_OP( 5, lhu, 0x0000f00f, 6, tdat );
# Test with negative offset
TEST_LD_OP( 6, lhu, 0x000000ff, -6, tdat4 );
TEST_LD_OP( 7, lhu, 0x0000ff00, -4, tdat4 );
TEST_LD_OP( 8, lhu, 0x00000ff0, -2, tdat4 );
TEST_LD_OP( 9, lhu, 0x0000f00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x3, 0x000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lhu x3, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0x0000ff00, \
la x1, tdat; \
addi x1, x1, -5; \
lhu x3, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x00000ff0, 2, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x0000f00f, 2, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x0000ff00, 2, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x00000ff0, 2, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x0000f00f, 2, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x0000ff00, 2, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x3, tdat; \
lhu x2, 0(x3); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x3, tdat; \
lhu x2, 0(x3); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0x00ff
tdat2: .half 0xff00
tdat3: .half 0x0ff0
tdat4: .half 0xf00f
RVTEST_DATA_END
|
wuxx/icesugar | 2,633 | src/advanced/picorv32/tests/and.S | # See LICENSE for license details.
#*****************************************************************************
# and.S
#-----------------------------------------------------------------------------
#
# Test and instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, and, 0 );
TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,366 | src/advanced/picorv32/tests/bltu.S | # See LICENSE for license details.
#*****************************************************************************
# bltu.S
#-----------------------------------------------------------------------------
#
# Test bltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
bltu x0, x1, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,530 | src/advanced/picorv32/tests/sh.S | # See LICENSE for license details.
#*****************************************************************************
# sh.S
#-----------------------------------------------------------------------------
#
# Test sh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat );
TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat );
TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat );
TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat );
# Test with negative offset
TEST_ST_OP( 6, lh, sh, 0x000000aa, -6, tdat8 );
TEST_ST_OP( 7, lh, sh, 0xffffaa00, -4, tdat8 );
TEST_ST_OP( 8, lh, sh, 0x00000aa0, -2, tdat8 );
TEST_ST_OP( 9, lh, sh, 0xffffa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x3, 0x5678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sh x2, 32(x4); \
lh x3, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0x3098, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -5; \
sh x2, 7(x1); \
la x4, tdat10; \
lh x3, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffbccd, 2, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffbbcc, 4, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffabbc, 6, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffaabb, 8, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffdaab, 10, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
li a0, 0xbeef
la a1, tdat
sh a0, 6(a1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0xbeef
tdat2: .half 0xbeef
tdat3: .half 0xbeef
tdat4: .half 0xbeef
tdat5: .half 0xbeef
tdat6: .half 0xbeef
tdat7: .half 0xbeef
tdat8: .half 0xbeef
tdat9: .half 0xbeef
tdat10: .half 0xbeef
RVTEST_DATA_END
|
wuxx/icesugar | 3,367 | src/advanced/picorv32/tests/srl.S | # See LICENSE for license details.
#*****************************************************************************
# srl.S
#-----------------------------------------------------------------------------
#
# Test srl instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, srl, 0xffff8000, 0xffff8000, 0 );
TEST_RR_OP( 3, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_OP( 4, srl, 0x01ffff00, 0xffff8000, 7 );
TEST_RR_OP( 5, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_RR_OP( 6, srl, 0x0001ffff, 0xffff8001, 15 );
TEST_RR_OP( 7, srl, 0xffffffff, 0xffffffff, 0 );
TEST_RR_OP( 8, srl, 0x7fffffff, 0xffffffff, 1 );
TEST_RR_OP( 9, srl, 0x01ffffff, 0xffffffff, 7 );
TEST_RR_OP( 10, srl, 0x0003ffff, 0xffffffff, 14 );
TEST_RR_OP( 11, srl, 0x00000001, 0xffffffff, 31 );
TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0 );
TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1 );
TEST_RR_OP( 14, srl, 0x00424242, 0x21212121, 7 );
TEST_RR_OP( 15, srl, 0x00008484, 0x21212121, 14 );
TEST_RR_OP( 16, srl, 0x00000000, 0x21212121, 31 );
# Verify that shifts only use bottom five bits
TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffe0 );
TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffe1 );
TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffe7 );
TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffee );
TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
TEST_RR_ZEROSRC12( 42, srl, 0 );
TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,490 | src/advanced/picorv32/tests/sb.S | # See LICENSE for license details.
#*****************************************************************************
# sb.S
#-----------------------------------------------------------------------------
#
# Test sb instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lb, sb, 0xffffffaa, 0, tdat );
TEST_ST_OP( 3, lb, sb, 0x00000000, 1, tdat );
TEST_ST_OP( 4, lh, sb, 0xffffefa0, 2, tdat );
TEST_ST_OP( 5, lb, sb, 0x0000000a, 3, tdat );
# Test with negative offset
TEST_ST_OP( 6, lb, sb, 0xffffffaa, -3, tdat8 );
TEST_ST_OP( 7, lb, sb, 0x00000000, -2, tdat8 );
TEST_ST_OP( 8, lb, sb, 0xffffffa0, -1, tdat8 );
TEST_ST_OP( 9, lb, sb, 0x0000000a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x3, 0x78, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sb x2, 32(x4); \
lb x3, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0xffffff98, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -6; \
sb x2, 7(x1); \
la x4, tdat10; \
lb x3, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffcd, 1, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffcc, 2, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffbc, 3, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffbb, 4, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffab, 5, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
li a0, 0xef
la a1, tdat
sb a0, 3(a1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xef
tdat2: .byte 0xef
tdat3: .byte 0xef
tdat4: .byte 0xef
tdat5: .byte 0xef
tdat6: .byte 0xef
tdat7: .byte 0xef
tdat8: .byte 0xef
tdat9: .byte 0xef
tdat10: .byte 0xef
RVTEST_DATA_END
|
wuxx/icesugar | 2,028 | src/advanced/picorv32/tests/beq.S | # See LICENSE for license details.
#*****************************************************************************
# beq.S
#-----------------------------------------------------------------------------
#
# Test beq instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
beq x0, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,923 | src/advanced/picorv32/tests/mulh.S | # See LICENSE for license details.
#*****************************************************************************
# mulh.S
#-----------------------------------------------------------------------------
#
# Test mulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulh, 0 );
TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 1,669 | src/advanced/picorv32/tests/ori.S | # See LICENSE for license details.
#*****************************************************************************
# ori.S
#-----------------------------------------------------------------------------
#
# Test ori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, ori, 0xffffff0f, 0xff00ff00, 0xf0f );
TEST_IMM_OP( 3, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
TEST_IMM_OP( 5, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffff, 0x00ff00ff, 0xf0f );
TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,174 | src/advanced/picorv32/tests/lbu.S | # See LICENSE for license details.
#*****************************************************************************
# lbu.S
#-----------------------------------------------------------------------------
#
# Test lbu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lbu, 0x000000ff, 0, tdat );
TEST_LD_OP( 3, lbu, 0x00000000, 1, tdat );
TEST_LD_OP( 4, lbu, 0x000000f0, 2, tdat );
TEST_LD_OP( 5, lbu, 0x0000000f, 3, tdat );
# Test with negative offset
TEST_LD_OP( 6, lbu, 0x000000ff, -3, tdat4 );
TEST_LD_OP( 7, lbu, 0x00000000, -2, tdat4 );
TEST_LD_OP( 8, lbu, 0x000000f0, -1, tdat4 );
TEST_LD_OP( 9, lbu, 0x0000000f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x3, 0x000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lbu x3, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0x00000000, \
la x1, tdat; \
addi x1, x1, -6; \
lbu x3, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x000000f0, 1, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x0000000f, 1, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x00000000, 1, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x000000f0, 1, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x0000000f, 1, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x00000000, 1, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x3, tdat; \
lbu x2, 0(x3); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x3, tdat; \
lbu x2, 0(x3); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xff
tdat2: .byte 0x00
tdat3: .byte 0xf0
tdat4: .byte 0x0f
RVTEST_DATA_END
|
wuxx/icesugar | 2,568 | src/advanced/picorv32/tests/sw.S | # See LICENSE for license details.
#*****************************************************************************
# sw.S
#-----------------------------------------------------------------------------
#
# Test sw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lw, sw, 0x00aa00aa, 0, tdat );
TEST_ST_OP( 3, lw, sw, 0xaa00aa00, 4, tdat );
TEST_ST_OP( 4, lw, sw, 0x0aa00aa0, 8, tdat );
TEST_ST_OP( 5, lw, sw, 0xa00aa00a, 12, tdat );
# Test with negative offset
TEST_ST_OP( 6, lw, sw, 0x00aa00aa, -12, tdat8 );
TEST_ST_OP( 7, lw, sw, 0xaa00aa00, -8, tdat8 );
TEST_ST_OP( 8, lw, sw, 0x0aa00aa0, -4, tdat8 );
TEST_ST_OP( 9, lw, sw, 0xa00aa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x3, 0x12345678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sw x2, 32(x4); \
lw x3, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0x58213098, \
la x1, tdat9; \
li x2, 0x58213098; \
addi x1, x1, -3; \
sw x2, 7(x1); \
la x4, tdat10; \
lw x3, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xaabbccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xdaabbccd, 4, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xddaabbcc, 8, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xcddaabbc, 12, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xccddaabb, 16, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xbccddaab, 20, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0xdeadbeef
tdat2: .word 0xdeadbeef
tdat3: .word 0xdeadbeef
tdat4: .word 0xdeadbeef
tdat5: .word 0xdeadbeef
tdat6: .word 0xdeadbeef
tdat7: .word 0xdeadbeef
tdat8: .word 0xdeadbeef
tdat9: .word 0xdeadbeef
tdat10: .word 0xdeadbeef
RVTEST_DATA_END
|
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