code stringlengths 2 1.05M | repo_name stringlengths 5 101 | path stringlengths 4 991 | language stringclasses 3 values | license stringclasses 5 values | size int64 2 1.05M |
|---|---|---|---|---|---|
;
; jcsamss2-64.asm - downsampling (64-bit SSE2)
;
; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
; Copyright 2009 D. R. Commander
;
; Based on
; x86 SIMD extension for IJG JPEG library
; Copyright (C) 1999-2006, MIYASAKA Masaru.
; For conditions of distribution and use, see copyright notice in jsimdext.inc
;
; This file should be assembled with NASM (Netwide Assembler),
; can *not* be assembled with Microsoft's MASM or any compatible
; assembler (including Borland's Turbo Assembler).
; NASM is available from http://nasm.sourceforge.net/ or
; http://sourceforge.net/project/showfiles.php?group_id=6208
;
; [TAB8]
%include "jsimdext.inc"
; --------------------------------------------------------------------------
SECTION SEG_TEXT
BITS 64
;
; Downsample pixel values of a single component.
; This version handles the common case of 2:1 horizontal and 1:1 vertical,
; without smoothing.
;
; GLOBAL(void)
; jsimd_h2v1_downsample_sse2 (JDIMENSION image_width, int max_v_samp_factor,
; JDIMENSION v_samp_factor, JDIMENSION width_blocks,
; JSAMPARRAY input_data, JSAMPARRAY output_data);
;
; r10 = JDIMENSION image_width
; r11 = int max_v_samp_factor
; r12 = JDIMENSION v_samp_factor
; r13 = JDIMENSION width_blocks
; r14 = JSAMPARRAY input_data
; r15 = JSAMPARRAY output_data
align 16
global EXTN(jsimd_h2v1_downsample_sse2) PRIVATE
EXTN(jsimd_h2v1_downsample_sse2):
push rbp
mov rax,rsp
mov rbp,rsp
collect_args
mov ecx, r13d
shl rcx,3 ; imul rcx,DCTSIZE (rcx = output_cols)
jz near .return
mov edx, r10d
; -- expand_right_edge
push rcx
shl rcx,1 ; output_cols * 2
sub rcx,rdx
jle short .expand_end
mov rax, r11
test rax,rax
jle short .expand_end
cld
mov rsi, r14 ; input_data
.expandloop:
push rax
push rcx
mov rdi, JSAMPROW [rsi]
add rdi,rdx
mov al, JSAMPLE [rdi-1]
rep stosb
pop rcx
pop rax
add rsi, byte SIZEOF_JSAMPROW
dec rax
jg short .expandloop
.expand_end:
pop rcx ; output_cols
; -- h2v1_downsample
mov eax, r12d ; rowctr
test eax,eax
jle near .return
mov rdx, 0x00010000 ; bias pattern
movd xmm7,edx
pcmpeqw xmm6,xmm6
pshufd xmm7,xmm7,0x00 ; xmm7={0, 1, 0, 1, 0, 1, 0, 1}
psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..}
mov rsi, r14 ; input_data
mov rdi, r15 ; output_data
.rowloop:
push rcx
push rdi
push rsi
mov rsi, JSAMPROW [rsi] ; inptr
mov rdi, JSAMPROW [rdi] ; outptr
cmp rcx, byte SIZEOF_XMMWORD
jae short .columnloop
.columnloop_r8:
movdqa xmm0, XMMWORD [rsi+0*SIZEOF_XMMWORD]
pxor xmm1,xmm1
mov rcx, SIZEOF_XMMWORD
jmp short .downsample
.columnloop:
movdqa xmm0, XMMWORD [rsi+0*SIZEOF_XMMWORD]
movdqa xmm1, XMMWORD [rsi+1*SIZEOF_XMMWORD]
.downsample:
movdqa xmm2,xmm0
movdqa xmm3,xmm1
pand xmm0,xmm6
psrlw xmm2,BYTE_BIT
pand xmm1,xmm6
psrlw xmm3,BYTE_BIT
paddw xmm0,xmm2
paddw xmm1,xmm3
paddw xmm0,xmm7
paddw xmm1,xmm7
psrlw xmm0,1
psrlw xmm1,1
packuswb xmm0,xmm1
movdqa XMMWORD [rdi+0*SIZEOF_XMMWORD], xmm0
sub rcx, byte SIZEOF_XMMWORD ; outcol
add rsi, byte 2*SIZEOF_XMMWORD ; inptr
add rdi, byte 1*SIZEOF_XMMWORD ; outptr
cmp rcx, byte SIZEOF_XMMWORD
jae short .columnloop
test rcx,rcx
jnz short .columnloop_r8
pop rsi
pop rdi
pop rcx
add rsi, byte SIZEOF_JSAMPROW ; input_data
add rdi, byte SIZEOF_JSAMPROW ; output_data
dec rax ; rowctr
jg near .rowloop
.return:
uncollect_args
pop rbp
ret
; --------------------------------------------------------------------------
;
; Downsample pixel values of a single component.
; This version handles the standard case of 2:1 horizontal and 2:1 vertical,
; without smoothing.
;
; GLOBAL(void)
; jsimd_h2v2_downsample_sse2 (JDIMENSION image_width, int max_v_samp_factor,
; JDIMENSION v_samp_factor, JDIMENSION width_blocks,
; JSAMPARRAY input_data, JSAMPARRAY output_data);
;
; r10 = JDIMENSION image_width
; r11 = int max_v_samp_factor
; r12 = JDIMENSION v_samp_factor
; r13 = JDIMENSION width_blocks
; r14 = JSAMPARRAY input_data
; r15 = JSAMPARRAY output_data
align 16
global EXTN(jsimd_h2v2_downsample_sse2) PRIVATE
EXTN(jsimd_h2v2_downsample_sse2):
push rbp
mov rax,rsp
mov rbp,rsp
collect_args
mov ecx, r13d
shl rcx,3 ; imul rcx,DCTSIZE (rcx = output_cols)
jz near .return
mov edx, r10d
; -- expand_right_edge
push rcx
shl rcx,1 ; output_cols * 2
sub rcx,rdx
jle short .expand_end
mov rax, r11
test rax,rax
jle short .expand_end
cld
mov rsi, r14 ; input_data
.expandloop:
push rax
push rcx
mov rdi, JSAMPROW [rsi]
add rdi,rdx
mov al, JSAMPLE [rdi-1]
rep stosb
pop rcx
pop rax
add rsi, byte SIZEOF_JSAMPROW
dec rax
jg short .expandloop
.expand_end:
pop rcx ; output_cols
; -- h2v2_downsample
mov eax, r12d ; rowctr
test rax,rax
jle near .return
mov rdx, 0x00020001 ; bias pattern
movd xmm7,edx
pcmpeqw xmm6,xmm6
pshufd xmm7,xmm7,0x00 ; xmm7={1, 2, 1, 2, 1, 2, 1, 2}
psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..}
mov rsi, r14 ; input_data
mov rdi, r15 ; output_data
.rowloop:
push rcx
push rdi
push rsi
mov rdx, JSAMPROW [rsi+0*SIZEOF_JSAMPROW] ; inptr0
mov rsi, JSAMPROW [rsi+1*SIZEOF_JSAMPROW] ; inptr1
mov rdi, JSAMPROW [rdi] ; outptr
cmp rcx, byte SIZEOF_XMMWORD
jae short .columnloop
.columnloop_r8:
movdqa xmm0, XMMWORD [rdx+0*SIZEOF_XMMWORD]
movdqa xmm1, XMMWORD [rsi+0*SIZEOF_XMMWORD]
pxor xmm2,xmm2
pxor xmm3,xmm3
mov rcx, SIZEOF_XMMWORD
jmp short .downsample
.columnloop:
movdqa xmm0, XMMWORD [rdx+0*SIZEOF_XMMWORD]
movdqa xmm1, XMMWORD [rsi+0*SIZEOF_XMMWORD]
movdqa xmm2, XMMWORD [rdx+1*SIZEOF_XMMWORD]
movdqa xmm3, XMMWORD [rsi+1*SIZEOF_XMMWORD]
.downsample:
movdqa xmm4,xmm0
movdqa xmm5,xmm1
pand xmm0,xmm6
psrlw xmm4,BYTE_BIT
pand xmm1,xmm6
psrlw xmm5,BYTE_BIT
paddw xmm0,xmm4
paddw xmm1,xmm5
movdqa xmm4,xmm2
movdqa xmm5,xmm3
pand xmm2,xmm6
psrlw xmm4,BYTE_BIT
pand xmm3,xmm6
psrlw xmm5,BYTE_BIT
paddw xmm2,xmm4
paddw xmm3,xmm5
paddw xmm0,xmm1
paddw xmm2,xmm3
paddw xmm0,xmm7
paddw xmm2,xmm7
psrlw xmm0,2
psrlw xmm2,2
packuswb xmm0,xmm2
movdqa XMMWORD [rdi+0*SIZEOF_XMMWORD], xmm0
sub rcx, byte SIZEOF_XMMWORD ; outcol
add rdx, byte 2*SIZEOF_XMMWORD ; inptr0
add rsi, byte 2*SIZEOF_XMMWORD ; inptr1
add rdi, byte 1*SIZEOF_XMMWORD ; outptr
cmp rcx, byte SIZEOF_XMMWORD
jae near .columnloop
test rcx,rcx
jnz near .columnloop_r8
pop rsi
pop rdi
pop rcx
add rsi, byte 2*SIZEOF_JSAMPROW ; input_data
add rdi, byte 1*SIZEOF_JSAMPROW ; output_data
dec rax ; rowctr
jg near .rowloop
.return:
uncollect_args
pop rbp
ret
; For some reason, the OS X linker does not honor the request to align the
; segment unless we do this.
align 16
| Teamxrtc/webrtc-streaming-node | third_party/webrtc/src/chromium/src/third_party/libjpeg_turbo/simd/jcsamss2-64.asm | Assembly | mit | 6,741 |
#include "m328Pdef.inc"
.equ freq = 16000000 ; Hz
.equ target_freq = 100000 ; Hz
.equ cycles_per_us = freq / 1000000 ; 1 us = 10^-6 s
.equ delay_in_cycles = (freq / target_freq)/2
#define ERROR_LED 7
#define SUCCESS_LED 6
#define TX_PIN 2
#define CLK_PIN 4
#define TRIGGER_PIN 0
#define CLK_HI sbi PORTD , CLK_PIN
#define CLK_LO cbi PORTD , CLK_PIN
#define DATA_HI sbi PORTD , TX_PIN
#define DATA_LO cbi PORTD , TX_PIN
#define SUCCESS_LED_ON sbi PORTD, SUCCESS_LED
#define SUCCESS_LED_OFF cbi PORTD, SUCCESS_LED
#define ERROR_LED_ON sbi PORTD, ERROR_LED
#define ERROR_LED_OFF cbi PORTD, ERROR_LED
jmp init ; RESET
jmp onirq ; INT0 - ext IRQ 0
jmp onirq ; INT1 - ext IRQ 1
jmp onirq ; PCINT0 - pin change IRQ
jmp onirq ; PCINT1 - pin change IRQ
jmp onirq ; PCINT2 - pin change IRQ
jmp onirq ; WDT - watchdog IRQ
jmp onirq ; TIMER2_COMPA - timer/counter 2 compare match A
jmp onirq ; TIMER2_COMPB - timer/counter 2 compare match B
jmp onirq ; TIMER2_OVF - timer/counter 2 overflow
jmp onirq ; TIMER1_CAPT - timer/counter 1 capture event
jmp onirq ; TIMER1_COMPA
jmp onirq ; TIMER1_COMPB
jmp onirq ; TIMER1_OVF
jmp onirq ; TIMER0_COMPA
jmp onirq ; TIMER0_COMPB
jmp onirq ; TIMER0_OVF
jmp onirq ; STC - serial transfer complete (SPI)
jmp onirq ; USUART Rx complete
jmp onirq ; USUART Data register empty
jmp onirq ; USUART Tx complete
jmp onirq ; ADC conversion complete
jmp onirq ; EEPROM ready
jmp onirq ; Analog comparator
jmp onirq ; 2-wire interface I2C
jmp onirq ; Store program memory ready
; ========================
; HW init
; ========================
init:
; clear status register
eor r1,r1
out 0x3f,r1
; initialize stack pointer
ldi r28,0xff
ldi r29,0x08
out 0x3e,r29 ; SPH = 0x08
out 0x3d,r28 ; SPL = 0xff
; call main program
again:
call main
call wait_for_button
rjmp again
onirq:
jmp 0x00
; ==========================
; main program starts here
; ==========================
main:
call reset
call wait_for_button
ldi r31 , HIGH(data)
ldi r30 , LOW(data)
ldi r20 , data_end-data
call send_bytes
brcs error
SUCCESS_LED_ON
ret
error:
ERROR_LED_ON
ret
; ====
; reset bus
; =====
reset:
sbi DDRD,CLK_PIN ; set to output
sbi DDRD,TX_PIN ; set to output
sbi DDRD,ERROR_LED ; set to output
sbi DDRD,SUCCESS_LED ; set to output
cbi DDRB,TRIGGER_PIN ; set to input
ERROR_LED_OFF
SUCCESS_LED_OFF
CLK_HI
DATA_HI
ret
; ======
; wait for button press
; ======
wait_for_button:
ldi r18,255
call usleep
wait_released:
sbic PINB , TRIGGER_PIN
rjmp wait_released
wait_pressed:
sbis PINB , TRIGGER_PIN
rjmp wait_pressed
ret
; ====== send bytes
; Assumption: CLK HI , DATA HI when method is entered
; INPUT: r31:r30 (Z register) start address of bytes to transmit
; INPUT: r20 - number of bytes to transmit
; SCRATCHED: r0,r1,r16,r17,r18
; RETURN: Carry clear => transmission successful , Carry set => Transmission failed
; ======
send_bytes:
; generate start sequence
DATA_LO
ldi r18 , 4 ; wait 4 us
call usleep
send_loop: lpm r2 , Z+
call send_byte
; CLK = HI , DATA = LOW
brcs tx_error
dec r20
brne send_loop
rcall send_stop
clc
ret
tx_error:
rcall send_stop
sec
ret
; =======
; send STOP sequence
; =======
send_stop:
DATA_HI
ldi r18, 5 ; wait 5 us
call usleep
ret
; ====================
; Send the byte in r2
; INPUT: r2 - byte to send
; RETURN: Carry clear => byte acknowledged by receiver , Carry set => Byte not acknowledged
; SCRATCHED: r0,r1,r4,r16,r17,r18,r19
; ====================
send_byte:
ldi r19,8 ; number of bits to transmit
bitbang:
CLK_LO
ldi r18, 2 ; wait 2 us
call usleep
lsl r2 ; load bit #7 into carry
brcc transmit0
; transmit 1-bit
DATA_HI
jmp cont
transmit0:
DATA_LO
cont:
ldi r18 , 3 ; wait 3 us while holding clk lo
call usleep
CLK_HI
ldi r18 , 4 ; wait 4 us while holding clk hi
call usleep
dec r19 ; decrement bit counter
brne bitbang ; => more bits to send
; ACK phase starts , CLK is HI here
CLK_LO
DATA_LO
ldi r18 , 5 ; wait 5 us while holding clk lo
call usleep
CLK_HI
ldi r18 , 2 ; wait 2 us while holding clk HIGH
call usleep
call sample_data ; sample data line
brcs ok1 ; carry set => line is HIGH
ldi r18 , 3 ; wait 3 us while holding clk HIGH
call usleep
call sample_data ; sample data line
brcs ok2 ; carry set => data line is HIGH
sec ; no ACK received
ret
ok1:
ldi r18 , 3 ; wait 3 us while holding clk HIGH
call usleep
ok2:
clc
ret
; =========
; sleep for up to 255 micro seconds
;
; >>>> Must NEVER be called with a value less than 2 us (infinite loop) <<<<
; IN: r18 = number of microseconds to sleep
; SCRATCHED: r0,r1,r16,r17,r18
;
; Total execution time:
; +1 cycles for caller having to load the R18 register with time to wait
; +4 cycles for CALL invoking this method
; +5 cycles for calculating cycle count
; +4 cycles for RET
; =========
usleep:
ldi r17 , cycles_per_us ; 1 cycle
mul r18 , r17 ; 1 cycle , result is in r1:r0
movw r27:r26 , r1:r0 ; 1 cycle
sbiw r27:r26,14 ; 2 cycles , adjust for cycles spent invoking this method + preparation
usleep2: sbiw r27:r26,4 ; 2 cycles , subtract 4 cycles per loop iteration
brpl usleep2 ; 2 cycles, 1 cycle if branch not taken
exit:
ret ; 4 cycles
; ======
; Sample status of CLK line and set carry bit accordingly (Carry set = CLK HIGH)
; duration: 7 cycles
; ======
sample_clock:
clc ; 1 cycle , clear carry
cbi DDRD , CLK_PIN ; 2 cycles , switch CLK pin to INPUT
sbic PIND , CLK_PIN ; 1/2 cycles , skip next insn if bit is clear
sec ; 1 cycle
sbi DDRD , CLK_PIN ; 2 cycles , switch CLK pin to OUTPUT
ret ; 4 cycles
; ======
; Sample status of DATA line and set carry bit accordingly (Carry set = DATA HIGH)
; duration: 7 cycles
; ======
sample_data:
clc ; 1 cycle , clear carry
cbi DDRD , TX_PIN ; 2 cycles , switch TX_PIN pin to INPUT
sbic PIND , TX_PIN ; 1/2 cycles , skip next insn if bit is clear
sec ; 1 cycle
sbi DDRD , TX_PIN ; 2 cycles , switch TX_PIN pin to OUTPUT
ret ; 4 cycles
data: .db %11101111,%11001100
data_end: | toby1984/javr | examples/projects/dcf77/src/i2c.asm | Assembly | apache-2.0 | 6,720 |
;******************************************************************************
;*
;* Copyright (c) 2004 - 2006, Intel Corporation
;* All rights reserved. This program and the accompanying materials
;* are licensed and made available under the terms and conditions of the BSD License
;* which accompanies this distribution. The full text of the license may be found at
;* http://opensource.org/licenses/bsd-license.php
;*
;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;*
;******************************************************************************
.586p
.MODEL FLAT, C
EXCPT32_DIVIDE_ERROR EQU 0
EXCPT32_DEBUG EQU 1
EXCPT32_NMI EQU 2
EXCPT32_BREAKPOINT EQU 3
EXCPT32_OVERFLOW EQU 4
EXCPT32_BOUND EQU 5
EXCPT32_INVALID_OPCODE EQU 6
EXCPT32_DOUBLE_FAULT EQU 8
EXCPT32_INVALID_TSS EQU 10
EXCPT32_SEG_NOT_PRESENT EQU 11
EXCPT32_STACK_FAULT EQU 12
EXCPT32_GP_FAULT EQU 13
EXCPT32_PAGE_FAULT EQU 14
EXCPT32_FP_ERROR EQU 16
EXCPT32_ALIGNMENT_CHECK EQU 17
EXCPT32_MACHINE_CHECK EQU 18
EXCPT32_SIMD EQU 19
FXSTOR_FLAG EQU 01000000h ; bit cpuid 24 of feature flags
;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
;; MUST check the CPUID feature flags to see that these instructions are available
;; and fail to init if they are not.
;; fxstor [edi]
FXSTOR_EDI MACRO
db 0fh, 0aeh, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [edi]
ENDM
;; fxrstor [esi]
FXRSTOR_ESI MACRO
db 0fh, 0aeh, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [esi]
ENDM
.DATA
public OrigVector, InterruptEntryStub, StubSize, CommonIdtEntry, FxStorSupport
StubSize dd InterruptEntryStubEnd - InterruptEntryStub
AppEsp dd 11111111h ; ?
DebugEsp dd 22222222h ; ?
ExtraPush dd 33333333h ; ?
ExceptData dd 44444444h ; ?
Eflags dd 55555555h ; ?
OrigVector dd 66666666h ; ?
;; The declarations below define the memory region that will be used for the debug stack.
;; The context record will be built by pushing register values onto this stack.
;; It is imparitive that alignment be carefully managed, since the FXSTOR and
;; FXRSTOR instructions will GP fault if their memory operand is not 16 byte aligned.
;;
;; The stub will switch stacks from the application stack to the debuger stack
;; and pushes the exception number.
;;
;; Then we building the context record on the stack. Since the stack grows down,
;; we push the fields of the context record from the back to the front. There
;; are 132 bytes of stack used prior allocating the 512 bytes of stack to be
;; used as the memory buffer for the fxstor instruction. Therefore address of
;; the buffer used for the FXSTOR instruction is &Eax - 132 - 512, which
;; must be 16 byte aligned.
;;
;; We carefully locate the stack to make this happen.
;;
;; For reference, the context structure looks like this:
;; struct {
;; UINT32 ExceptionData;
;; FX_SAVE_STATE_IA32 FxSaveState; // 512 bytes, must be 16 byte aligned
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
;; UINT32 EFlags;
;; UINT32 Ldtr, Tr;
;; UINT32 Gdtr[2], Idtr[2];
;; UINT32 Eip;
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
;; } SYSTEM_CONTEXT_IA32; // 32 bit system context record
align 16
DebugStackEnd db "DbgStkEnd >>>>>>" ;; 16 byte long string - must be 16 bytes to preserve alignment
dd 1ffdh dup (000000000h) ;; 32K should be enough stack
;; This allocation is coocked to insure
;; that the the buffer for the FXSTORE instruction
;; will be 16 byte aligned also.
;;
ExceptionNumber dd ? ;; first entry will be the vector number pushed by the stub
DebugStackBegin db "<<<< DbgStkBegin" ;; initial debug ESP == DebugStackBegin, set in stub
.CODE
externdef InterruptDistrubutionHub:near
;------------------------------------------------------------------------------
; VOID
; EfiWbinvd (
; VOID
; )
;
; Abstract: Writeback and invalidate cache
;
EfiWbinvd PROC PUBLIC
wbinvd
ret
EfiWbinvd ENDP
;------------------------------------------------------------------------------
; BOOLEAN
; FxStorSupport (
; void
; )
;
; Abstract: Returns TRUE if FxStor instructions are supported
;
FxStorSupport PROC C PUBLIC
;
; cpuid corrupts ebx which must be preserved per the C calling convention
;
push ebx
mov eax, 1
cpuid
mov eax, edx
and eax, FXSTOR_FLAG
shr eax, 24
pop ebx
ret
FxStorSupport ENDP
;------------------------------------------------------------------------------
; DESCRIPTOR *
; GetIdtr (
; void
; )
;
; Abstract: Returns physical address of IDTR
;
GetIdtr PROC C PUBLIC
LOCAL IdtrBuf:FWORD
sidt IdtrBuf
mov eax, DWORD PTR IdtrBuf + 2
ret
GetIdtr ENDP
;------------------------------------------------------------------------------
; BOOLEAN
; WriteInterruptFlag (
; BOOLEAN NewState
; )
;
; Abstract: Programs interrupt flag to the requested state and returns previous
; state.
;
WriteInterruptFlag PROC C PUBLIC State:DWORD
pushfd
pop eax
and eax, 200h
shr eax, 9
mov ecx, State
.IF cl == 0
cli
.ELSE
sti
.ENDIF
ret
WriteInterruptFlag ENDP
;------------------------------------------------------------------------------
; void
; Vect2Desc (
; DESCRIPTOR * DestDesc,
; void (*Vector) (void)
; )
;
; Abstract: Encodes an IDT descriptor with the given physical address
;
Vect2Desc PROC C PUBLIC DestPtr:DWORD, Vector:DWORD
mov eax, Vector
mov ecx, DestPtr
mov word ptr [ecx], ax ; write bits 15..0 of offset
mov dx, cs
mov word ptr [ecx+2], dx ; SYS_CODE_SEL from GDT
mov word ptr [ecx+4], 0e00h OR 8000h ; type = 386 interrupt gate, present
shr eax, 16
mov word ptr [ecx+6], ax ; write bits 31..16 of offset
ret
Vect2Desc ENDP
;------------------------------------------------------------------------------
; InterruptEntryStub
;
; Abstract: This code is not a function, but is a small piece of code that is
; copied and fixed up once for each IDT entry that is hooked.
;
InterruptEntryStub::
mov AppEsp, esp ; save stack top
mov esp, offset DebugStackBegin ; switch to debugger stack
push 0 ; push vector number - will be modified before installed
db 0e9h ; jump rel32
dd 0 ; fixed up to relative address of CommonIdtEntry
InterruptEntryStubEnd:
;------------------------------------------------------------------------------
; CommonIdtEntry
;
; Abstract: This code is not a function, but is the common part for all IDT
; vectors.
;
CommonIdtEntry::
;;
;; At this point, the stub has saved the current application stack esp into AppEsp
;; and switched stacks to the debug stack, where it pushed the vector number
;;
;; The application stack looks like this:
;;
;; ...
;; (last application stack entry)
;; eflags from interrupted task
;; CS from interrupted task
;; EIP from interrupted task
;; Error code <-------------------- Only present for some exeption types
;;
;;
;; The stub switched us to the debug stack and pushed the interrupt number.
;;
;; Next, construct the context record. It will be build on the debug stack by
;; pushing the registers in the correct order so as to create the context structure
;; on the debug stack. The context record must be built from the end back to the
;; beginning because the stack grows down...
;
;; For reference, the context record looks like this:
;;
;; typedef
;; struct {
;; UINT32 ExceptionData;
;; FX_SAVE_STATE_IA32 FxSaveState;
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
;; UINT32 Cr0, Cr2, Cr3, Cr4;
;; UINT32 EFlags;
;; UINT32 Ldtr, Tr;
;; UINT32 Gdtr[2], Idtr[2];
;; UINT32 Eip;
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
;; } SYSTEM_CONTEXT_IA32; // 32 bit system context record
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
pushad
;; Save interrupt state eflags register...
pushfd
pop eax
mov dword ptr Eflags, eax
;; We need to determine if any extra data was pushed by the exception, and if so, save it
;; To do this, we check the exception number pushed by the stub, and cache the
;; result in a variable since we'll need this again.
.IF ExceptionNumber == EXCPT32_DOUBLE_FAULT
mov ExtraPush, 1
.ELSEIF ExceptionNumber == EXCPT32_INVALID_TSS
mov ExtraPush, 1
.ELSEIF ExceptionNumber == EXCPT32_SEG_NOT_PRESENT
mov ExtraPush, 1
.ELSEIF ExceptionNumber == EXCPT32_STACK_FAULT
mov ExtraPush, 1
.ELSEIF ExceptionNumber == EXCPT32_GP_FAULT
mov ExtraPush, 1
.ELSEIF ExceptionNumber == EXCPT32_PAGE_FAULT
mov ExtraPush, 1
.ELSEIF ExceptionNumber == EXCPT32_ALIGNMENT_CHECK
mov ExtraPush, 1
.ELSE
mov ExtraPush, 0
.ENDIF
;; If there's some extra data, save it also, and modify the saved AppEsp to effectively
;; pop this value off the application's stack.
.IF ExtraPush == 1
mov eax, AppEsp
mov ebx, [eax]
mov ExceptData, ebx
add eax, 4
mov AppEsp, eax
.ELSE
mov ExceptData, 0
.ENDIF
;; The "pushad" above pushed the debug stack esp. Since what we're actually doing
;; is building the context record on the debug stack, we need to save the pushed
;; debug ESP, and replace it with the application's last stack entry...
mov eax, [esp + 12]
mov DebugEsp, eax
mov eax, AppEsp
add eax, 12
; application stack has eflags, cs, & eip, so
; last actual application stack entry is
; 12 bytes into the application stack.
mov [esp + 12], eax
;; continue building context record
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
mov eax, ss
push eax
; CS from application is one entry back in application stack
mov eax, AppEsp
movzx eax, word ptr [eax + 4]
push eax
mov eax, ds
push eax
mov eax, es
push eax
mov eax, fs
push eax
mov eax, gs
push eax
;; UINT32 Eip;
; Eip from application is on top of application stack
mov eax, AppEsp
push dword ptr [eax]
;; UINT32 Gdtr[2], Idtr[2];
push 0
push 0
sidt fword ptr [esp]
push 0
push 0
sgdt fword ptr [esp]
;; UINT32 Ldtr, Tr;
xor eax, eax
str ax
push eax
sldt ax
push eax
;; UINT32 EFlags;
;; Eflags from application is two entries back in application stack
mov eax, AppEsp
push dword ptr [eax + 8]
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
;; insure FXSAVE/FXRSTOR is enabled in CR4...
;; ... while we're at it, make sure DE is also enabled...
mov eax, cr4
or eax, 208h
mov cr4, eax
push eax
mov eax, cr3
push eax
mov eax, cr2
push eax
push 0
mov eax, cr0
push eax
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
mov eax, dr7
push eax
;; clear Dr7 while executing debugger itself
xor eax, eax
mov dr7, eax
mov eax, dr6
push eax
;; insure all status bits in dr6 are clear...
xor eax, eax
mov dr6, eax
mov eax, dr3
push eax
mov eax, dr2
push eax
mov eax, dr1
push eax
mov eax, dr0
push eax
;; FX_SAVE_STATE_IA32 FxSaveState;
sub esp, 512
mov edi, esp
; IMPORTANT!! The debug stack has been carefully constructed to
; insure that esp and edi are 16 byte aligned when we get here.
; They MUST be. If they are not, a GP fault will occur.
FXSTOR_EDI
;; UINT32 ExceptionData;
mov eax, ExceptData
push eax
; call to C code which will in turn call registered handler
; pass in the vector number
mov eax, esp
push eax
mov eax, ExceptionNumber
push eax
call InterruptDistrubutionHub
add esp, 8
; restore context...
;; UINT32 ExceptionData;
add esp, 4
;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp
FXRSTOR_ESI
add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
pop eax
mov dr0, eax
pop eax
mov dr1, eax
pop eax
mov dr2, eax
pop eax
mov dr3, eax
;; skip restore of dr6. We cleared dr6 during the context save.
add esp, 4
pop eax
mov dr7, eax
;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
pop eax
mov cr0, eax
add esp, 4
pop eax
mov cr2, eax
pop eax
mov cr3, eax
pop eax
mov cr4, eax
;; UINT32 EFlags;
mov eax, AppEsp
pop dword ptr [eax + 8]
;; UINT32 Ldtr, Tr;
;; UINT32 Gdtr[2], Idtr[2];
;; Best not let anyone mess with these particular registers...
add esp, 24
;; UINT32 Eip;
pop dword ptr [eax]
;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
;; NOTE - modified segment registers could hang the debugger... We
;; could attempt to insulate ourselves against this possibility,
;; but that poses risks as well.
;;
pop gs
pop fs
pop es
pop ds
pop [eax + 4]
pop ss
;; The next stuff to restore is the general purpose registers that were pushed
;; using the "pushad" instruction.
;;
;; The value of ESP as stored in the context record is the application ESP
;; including the 3 entries on the application stack caused by the exception
;; itself. It may have been modified by the debug agent, so we need to
;; determine if we need to relocate the application stack.
mov ebx, [esp + 12] ; move the potentially modified AppEsp into ebx
mov eax, AppEsp
add eax, 12
cmp ebx, eax
je NoAppStackMove
mov eax, AppEsp
mov ecx, [eax] ; EIP
mov [ebx], ecx
mov ecx, [eax + 4] ; CS
mov [ebx + 4], ecx
mov ecx, [eax + 8] ; EFLAGS
mov [ebx + 8], ecx
mov eax, ebx ; modify the saved AppEsp to the new AppEsp
mov AppEsp, eax
NoAppStackMove:
mov eax, DebugEsp ; restore the DebugEsp on the debug stack
; so our "popad" will not cause a stack switch
mov [esp + 12], eax
cmp ExceptionNumber, 068h
jne NoChain
Chain:
;; Restore eflags so when we chain, the flags will be exactly as if we were never here.
;; We gin up the stack to do an iretd so we can get ALL the flags.
mov eax, AppEsp
mov ebx, [eax + 8]
and ebx, NOT 300h ; special handling for IF and TF
push ebx
push cs
push PhonyIretd
iretd
PhonyIretd:
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
popad
;; Switch back to application stack
mov esp, AppEsp
;; Jump to original handler
jmp OrigVector
NoChain:
;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
popad
;; Switch back to application stack
mov esp, AppEsp
;; We're outa here...
iretd
END
| tianocore/edk | Sample/Cpu/DebugSupport/Dxe/ia32/AsmFuncs.asm | Assembly | bsd-3-clause | 19,273 |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; ReadCs.Asm
;
; Abstract:
;
; AsmReadCs function
;
; Notes:
;
;------------------------------------------------------------------------------
.code
;------------------------------------------------------------------------------
; UINT16
; EFIAPI
; AsmReadCs (
; VOID
; );
;------------------------------------------------------------------------------
AsmReadCs PROC
mov eax, cs
ret
AsmReadCs ENDP
END
| tenpoku1000/UEFI_SecureBoot | src/lib/external/BSD/UDK/MdePkg/Library/BaseLib/X64/ReadCs.asm | Assembly | mit | 1,024 |
push 0
push 0
st_ra 0x0
push 1
push 0
sethi 0x0200
st_ra 0x0
push 2
push 0
sethi 0x0400
st_ra 0x0
push 3
push 0
sethi 0x0600
st_ra 0x0
push 0
push 0
sethi 0x0200
ld_ra 0x0
pull_cp 1
push 1
add
st_ra 0x0
push 0
sethi 0x0400
ld_ra 0x0
pull_cp 1
push 2
add
st_ra 0x0
push 0
sethi 0x0600
ld_ra 0x0
pull_cp 1
push 3
add
st_ra 0x0
push 0
ld_ra 0x0
push 4
add
pull 1
push 4
add
st_ra 0x0
halt
| ilebedev/stacktool | tests/emra/RA_MODE/asm_for_rb/RA01.asm | Assembly | mit | 386 |
; Listing generated by Microsoft (R) Optimizing Compiler Version 18.00.30723.0
include listing.inc
INCLUDELIB LIBCMT
INCLUDELIB OLDNAMES
_DATA SEGMENT
$SG3094 DB 0aH, '%d %p %d = %d', 00H
_DATA ENDS
PUBLIC ActionCarrier
PUBLIC sum
PUBLIC difference
PUBLIC product
PUBLIC quotient
PUBLIC modulus
PUBLIC main
EXTRN printf:PROC
pdata SEGMENT
$pdata$ActionCarrier DD imagerel $LN3
DD imagerel $LN3+65
DD imagerel $unwind$ActionCarrier
$pdata$main DD imagerel $LN3
DD imagerel $LN3+132
DD imagerel $unwind$main
pdata ENDS
xdata SEGMENT
$unwind$ActionCarrier DD 011201H
DD 06212H
$unwind$main DD 010401H
DD 06204H
xdata ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
b$ = 32
a$ = 36
main PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 11
$LN3:
sub rsp, 56 ; 00000038H
; Line 12
mov DWORD PTR a$[rsp], 20
mov DWORD PTR b$[rsp], 7
; Line 13
mov r8d, DWORD PTR b$[rsp]
mov edx, DWORD PTR a$[rsp]
lea rcx, OFFSET FLAT:sum
call ActionCarrier
; Line 14
mov r8d, DWORD PTR b$[rsp]
mov edx, DWORD PTR a$[rsp]
lea rcx, OFFSET FLAT:difference
call ActionCarrier
; Line 15
mov r8d, DWORD PTR b$[rsp]
mov edx, DWORD PTR a$[rsp]
lea rcx, OFFSET FLAT:product
call ActionCarrier
; Line 16
mov r8d, DWORD PTR b$[rsp]
mov edx, DWORD PTR a$[rsp]
lea rcx, OFFSET FLAT:quotient
call ActionCarrier
; Line 17
mov r8d, DWORD PTR b$[rsp]
mov edx, DWORD PTR a$[rsp]
lea rcx, OFFSET FLAT:modulus
call ActionCarrier
; Line 18
xor eax, eax
add rsp, 56 ; 00000038H
ret 0
main ENDP
_TEXT ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
a$ = 8
b$ = 16
modulus PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 36
mov DWORD PTR [rsp+16], edx
mov DWORD PTR [rsp+8], ecx
; Line 37
mov eax, DWORD PTR a$[rsp]
cdq
idiv DWORD PTR b$[rsp]
mov eax, edx
; Line 38
ret 0
modulus ENDP
_TEXT ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
a$ = 8
b$ = 16
quotient PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 33
mov DWORD PTR [rsp+16], edx
mov DWORD PTR [rsp+8], ecx
; Line 34
mov eax, DWORD PTR a$[rsp]
cdq
idiv DWORD PTR b$[rsp]
; Line 35
ret 0
quotient ENDP
_TEXT ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
a$ = 8
b$ = 16
product PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 30
mov DWORD PTR [rsp+16], edx
mov DWORD PTR [rsp+8], ecx
; Line 31
mov eax, DWORD PTR a$[rsp]
imul eax, DWORD PTR b$[rsp]
; Line 32
ret 0
product ENDP
_TEXT ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
a$ = 8
b$ = 16
difference PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 27
mov DWORD PTR [rsp+16], edx
mov DWORD PTR [rsp+8], ecx
; Line 28
mov eax, DWORD PTR b$[rsp]
mov ecx, DWORD PTR a$[rsp]
sub ecx, eax
mov eax, ecx
; Line 29
ret 0
difference ENDP
_TEXT ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
a$ = 8
b$ = 16
sum PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 24
mov DWORD PTR [rsp+16], edx
mov DWORD PTR [rsp+8], ecx
; Line 25
mov eax, DWORD PTR b$[rsp]
mov ecx, DWORD PTR a$[rsp]
add ecx, eax
mov eax, ecx
; Line 26
ret 0
sum ENDP
_TEXT ENDS
; Function compile flags: /Odtp
_TEXT SEGMENT
action$ = 64
a$ = 72
b$ = 80
ActionCarrier PROC
; File c:\src\blog posts\function pointers and delegates\function pointer.c
; Line 20
$LN3:
mov DWORD PTR [rsp+24], r8d
mov DWORD PTR [rsp+16], edx
mov QWORD PTR [rsp+8], rcx
sub rsp, 56 ; 00000038H
; Line 21
mov edx, DWORD PTR b$[rsp]
mov ecx, DWORD PTR a$[rsp]
call QWORD PTR action$[rsp]
mov DWORD PTR [rsp+32], eax
mov r9d, DWORD PTR b$[rsp]
mov r8, QWORD PTR action$[rsp]
mov edx, DWORD PTR a$[rsp]
lea rcx, OFFSET FLAT:$SG3094
call printf
; Line 22
add rsp, 56 ; 00000038H
ret 0
ActionCarrier ENDP
_TEXT ENDS
END
| IAmAnubhavSaini/blog-posts | function pointers and delegates/function pointer.asm | Assembly | mit | 3,875 |
list p=18f4550
#include "p18f4550.inc"
CONFIG FOSC = XT_XT
CONFIG PWRT = ON ; Power-up Timer Enable bit (PWRT enabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
org 0x000
goto camote
org 0x008
goto enterrop
org 0x020
camote: bsf TRISB, 1 ;Fuerzo el puerto B1 como entrada
bsf TRISB, 0 ;Fuerzo el puerto B0 como entrada
movlw 0xFC
movwf TRISD ;Puertos D0 y D1 como salidas
bsf INTCON2, 6 ;Interrupción externa 0 en flanco positivo
movlw 0x90
movwf INTCON ;Habilitación de INT0 y GIE
inicio: btfss PORTB, 1
goto nanana
bcf LATD, 1
goto inicio
nanana: bsf LATD, 1
goto inicio
;---Rutina de interrupción----------
enterrop: btfss PORTD, 0
goto nonono
bcf LATD, 0
goto otro
nonono: bsf LATD, 0
otro: bcf INTCON, INT0IF ;Bajamos la banderita
retfie
end
| tocache/picomones | UPC Microcontroladores 2018-1/Ejercicios en MPASM/int0 con negador.X/maincodemon.asm | Assembly | cc0-1.0 | 1,466 |
;****************************************
;* *
;* joystick draw *
;* *
;* Does not work! *
;****************************************
; 10 SYS (49152)
*=$0801
BYTE $0E, $08, $0A, $00, $9E, $20, $28, $34, $39, $31, $35, $32, $29, $00, $00, $00
*=$c000
clear =$e544
jstick =$dc01
ofset =$c200
fire =$c202
inverse =$c204
normal =$c206
mark =$c208
chrout =$ffd2
jsr clear
lda #$ff
sta ofset
lda #16
sta fire
lda #32
sta mark
lda #18
sta inverse
lda #146
sta normal
start lda jstick
eor ofset
cmp #1
beq up
lda inverse
jsr chrout
ldx #0 ; begin pause loop
pause inx
cpx #254
bne pause ; end pause loop
jmp start
up jsr back
lda #145
jmp print
down jsr back
lda #17
jmp print
left jsr back
lda #157
jmp print
print lsr chrout
lda mark
jsr chrout
jmp start
back lda #157 ; subroutine
jsr chrout
rts
end rts
| jacmoe/c64adventures | Asm4Kids/38joystickdraw.asm | Assembly | bsd-2-clause | 1,444 |
macro comment {
Copyright (c) 2017, Davos development team.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
3. Neither the name of Davos nor the names of its contributors may
be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
}
format ELF
section ".text" executable
load_idt:
mov eax, [esp + 4]
lidt [eax]
ret
public load_idt
| daveshep666/davos | source/load_idt.asm | Assembly | bsd-3-clause | 1,651 |
/*
* Scoreboard update function for decoding kernels
* Copyright © <2010>, Intel Corporation.
*
* This program is licensed under the terms and conditions of the
* Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
* http://www.opensource.org/licenses/eclipse-1.0.php.
*
*/
//
// Module name: scoreboard_update.asm
//
// Scoreboard update function for decoding kernels
//
// This module is used by decoding kernels to send message to scoreboard to update the
// "complete" status, thus the dependency of the MB can be cleared.
//
// $Revision: 6 $
// $Date: 10/16/06 5:19p $
//
mov (8) MSGHDRY1<1>:ud 0x00000000:ud // Initialize message header payload with 0
// Compose M0.5:ud information
add (1) MSGHDRY1.10<1>:uw r0.20:ub 0x0200:uw // Message length = 1 DWORD
and (1) MSGHDRY1.11<1>:uw M05_STORE<0;1,0>:uw SB_MASK*4:uw // Retrieve stored value and wrap around scoreboard
or (1) MSGHDRY1.0<1>:ud M05_STORE<0;1,0>:uw 0xc0000000:ud // Set "Completed" bits
#ifndef BSDRESET_ENABLE
#ifdef INTER_KERNEL
mov (1) gREG_WRITE_COMMIT_Y<1>:ud gREG_WRITE_COMMIT_Y<0;1,0>:ud // Make sure Y write is committed
mov (1) gREG_WRITE_COMMIT_UV<1>:ud gREG_WRITE_COMMIT_UV<0;1,0>:ud // Make sure U/V write is committed
#else
mov (1) REG_WRITE_COMMIT_Y<1>:ud REG_WRITE_COMMIT_Y<0;1,0>:ud // Make sure Y write is committed
mov (1) REG_WRITE_COMMIT_UV<1>:ud REG_WRITE_COMMIT_UV<0;1,0>:ud // Make sure U/V write is committed
#endif // INTER_KERNEL
#endif // BSDRESET_ENABLE
send (8) NULLREG MSGHDRY1 null:ud MSG_GW FWDMSGDSC
// End of scoreboard_update
| halleyzhao/libva-intel-driver-fdo | src/shaders/h264/mc/scoreboard_update.asm | Assembly | mit | 1,638 |
;simple sum code
LDA #$05
CLC ;clear carry bit
ADC #$05 | honux77/practice | 6502/easy6502/sum.asm | Assembly | mit | 75 |
; ************************************************************************* ;
; Organizacion del Computador II ;
; ;
; Implementacion de la funcion HSL 2-variacion 1 ;
; hslTOrgb.calcRGB -> pshufd en lugar de shift y pins ;
; ;
; ************************************************************************* ;
extern malloc
extern free
%define PIXEL_SIZE 4h
%define OFFSET_A 0h
%define OFFSET_R 1h
%define OFFSET_G 2h
%define OFFSET_B 3h
lemask: dd 0.0, 360.0, 1.0, 1.0 ; 1 | 1 | 360 | 0
absmask: dd 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF
shuf: db 0x00,0x04,0x08,0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
divS: dd 255.0001, 0.0, 0.0, 0.0 ; 0 | 0 | 0 | 255.0001
divL: dd 510.0, 0.0, 0.0, 0.0
one: dd 1.0 , 0.0, 0.0, 0.0
cEscala: dd 0.0 , 255.0, 255.0, 255.0
cRGB: dd 120.0, 0.0, 0.0, 0.0
cmod2: dd 2.0, 0.0, 0.0, 0.0
c060: dd 60.0, 0.0, 0.0, 0.0
; void ASM_hsl2(uint32_t w, uint32_t h, uint8_t* data, float hh, float ss, float ll)
global ASM_hsl2
ASM_hsl2:
push rbp
mov rbp, rsp
push rbx
push r12
push r13
push r14
push r15
sub rbp, 8
mov edi, edi ;limpio parte alta
mov esi, esi
xor r15, r15
movq xmm8, xmm2 ;xmm8 = ll
pslldq xmm8, 4 ;xmm8 = 0 | 0 | ll | 0
addps xmm8, xmm1 ;xmm8 = 0 | 0 | ll | ss
pslldq xmm8, 4 ;xmm8 = 0 | ll | ss | 0
addps xmm8, xmm0 ;xmm8 = 0 | ll | ss | hh
pslldq xmm8, 4 ;xmm8 = ll | ss | hh | 0
movdqu xmm9, [lemask] ;xmm9 = 1 | 1 | 360 | 0
movdqu xmm6, xmm9 ;xmm6 = 1 | 1 | 360 | 0
movdqu xmm7, xmm6
pslldq xmm7, 8 ;xmm7 = 360 | 0 | 0 | 0
psrldq xmm7, 8 ;xmm7 = 0 | 0 | 360 | 0
psubd xmm6, xmm7 ;xmm6 = 1 | 1 | 0 | 0
mov rbx, rdi ;rbx = w
mov r12, rsi ;r12 = h
mov r13, rdx ;r13 = data
mov rax, r12 ;rax = h
mul rbx ;rax = w * h
mov r9, 4
mul r9
mov r14, rax ;r14 = w * h * 4
mov rdi, 16d
call malloc
mov r12, rax ;r12 = *dst
.ciclo:
mov rsi, r12
lea rdi, [r13 + r15]
call rgbTOhsl3 ;rsi = pixel en hsl ;pixel en registro = l s h a
;call rgbTOhsl
movdqu xmm11, [r12] ;xmm11 = l | s | h | a
;el ultimo "else" se toma como implicito y se buscan las modificaciones hacia los otros casos de ser necesarias,
;primer if
pxor xmm5 , xmm5
pxor xmm15, xmm15
addps xmm11, xmm8 ;xmm11 = l+ll | s+ss | h+hh | a
movdqu xmm4, xmm11 ;xmm4 = l+ll | s+ss | h+hh | a
movdqu xmm13, xmm9 ;xmm13 = 1 | 1 | 360 | 0
cmpleps xmm13, xmm11 ;xmm13 = 1 <= l+ll | 1 <= s+ss | 360 <= h+hh | 0
;h+hh >= 360
movdqu xmm5, xmm13 ;xmm5 = 1 <= l+ll | 1 <= s+ss | 360 <= h+hh | 0
pand xmm5, xmm7 ;xmm7 = 0 | 0 | 360 o 0 | 0
subps xmm11, xmm5 ;xmm11 = l+ll | s+ss | h+hh o h+hh-360| 0
;s+ss >= 1 | l+ll >= 1
movdqu xmm5, xmm4 ;xmm5 = l+ll | s+ss | h+hh | 0
subps xmm5, xmm6 ;xmm5 = l+ll-1 | s+ss-1 | h+hh | 0
pand xmm5, xmm13 ;xmm5 = l+ll-1 o 0 | s+ss-1 o 0 | h+hh o 0 | 0
psrldq xmm5, 8 ;xmm5 = | 0 | 0 | l+ll-1 o 0 | s+ss+1 o 0
pslldq xmm5, 8 ;xmm5 = l+ll-1 o 0 | s+ss-1 o 0 | 0 | 0 |
subps xmm11, xmm5 ;xmm11 = l+ll o 1 | s+ss o 1 | h+hh o h+hh-360 | 0
;segundo if
movdqu xmm14, xmm4 ;xmm14 = l+ll | s+ss | h+hh | 0
cmpltps xmm14, xmm15 ;xmm14 = l+ll < 0 | s+ss < 0 | h+hh < 0 | 0
;h+hh < 360
movdqu xmm5, xmm14 ;xmm5 = l+ll < 0 | s+ss < 0 | h+hh < 0 | 0
pand xmm5, xmm7 ;xmm5 = 0 | 0 | 360 o 0 | 0
addps xmm11, xmm5 ;xmm11 = l+ll o 1 | s+ss o 1 | h+hh o h+hh-360 o h+hh+360| 0
;s+ss < 0 | l+ll < 0
movdqu xmm5, xmm4 ;xmm5 = l+ll | s+ss | h+hh | 0
pand xmm5, xmm14 ;xmm5 = l+ll o 0 | s+ss o 0 | h+hh o 0 | 0 |
psrldq xmm5, 8 ;xmm5 = | 0 | 0 | l+ll o 0 | s+ss o 0
pslldq xmm5, 8 ;xmm5 = l+ll o 0 | s+ss o 0 | 0 | 0 |
subps xmm11, xmm5 ;xmm11 = l+ll o 1 o 0 | s+ss o 1 o 0 | h+hh o h+hh-360 o h+hh+360 | 0
movdqu [r12], xmm11
mov rdi, r12
lea rsi, [r13 + r15]
call hslTOrgb3
add r15, PIXEL_SIZE
cmp r15, r14
jl .ciclo
.final:
add rbp, 8
pop r15
pop r14
pop r13
pop r12
pop rbx
pop rbp
ret
rgbTOhsl3:
push rbp
mov rbp, rsp
push rbx
push r12
push r13
push r14
push r15
sub rbp, 8
xor r14, r14
xor r15, r15
xor rcx, rcx
xor rbx, rbx
xor rax, rax
xor rdx, rdx
mov r12, rdi ;r12 = *dato
mov r13, rsi ;r13 = *dst
mov eax, [r12] ;rax = r-g-b-a
mov r8 , rax ;r8 = r-g-b-a
;repartimos valores
mov dl, al ;rdx = a
shrd rax, r14, 8 ;rbx = r-g-b
mov bl, al ;rbx = b
shrd rax, r14, 8 ;rax = r-g
mov cl, al ;rcx = g
shrd rax, r14, 8 ;rax = r
.calcMax:
mov r15, rbx ;r15 = b (max actual)
cmp r15, rcx ;maxactual < g
jl .maxg
.max2:
cmp r15, rax ;maxactual < r
jl .maxr
jge .calcMin
.maxg:
mov r15, rcx ;maxactual = g
jmp .max2
.maxr:
mov r15, rax ;maxactual = r
jmp .calcMin
.calcMin:
mov r14, rbx ;r14 = b (min actual)
cmp r14, rcx ;minactual > g
jg .ming
.min2:
cmp r14, rax ;minactual > r
jg .minr
jle .calcD
.ming:
mov r14, rcx ;minactual = g
jmp .min2
.minr:
mov r14, rax ;minactual = r
jmp .calcD
.calcD:
xor r8, r8
xor r9, r9
mov r8, rax ;r8 = r
mov r9, rbx ;r9 = b
mov r10, rcx ;r10 = g
mov rcx, r14 ;rcx = minimo
mov rbx, r15 ;rbx = maximo
sub r15, r14 ;r15 = maximo - minimo
.calcH:
xor r11 , r11
pxor xmm0, xmm0
pxor xmm1, xmm1
pxor xmm2, xmm2
pxor xmm4, xmm4
cmp r15, 0 ;if(max == min)
je .Hcaso0
cmp rbx, r8 ;if(max == r)
je .Hcaso1
cmp rbx, r10 ;if(max == g)
je .Hcaso2
cmp rbx, r9 ;if(max == b)
je .Hcaso3
jmp .calcL
.Hcaso0:
xorps xmm0, xmm0
jmp .calcL
.Hcaso1:
movq xmm0, r10 ;xmm0 = g
movq xmm1, r9 ;xmm1 = b
movq xmm2, r15 ;xmm2 = d
mov r11 , 60
movq xmm3, r11 ;xmm3 = 60
mov r11 , 6
movq xmm4, r11 ;xmm4 = 6
cvtdq2ps xmm0, xmm0 ;xmm0 = (float) g
cvtdq2ps xmm1, xmm1 ;xmm0 = (float) b
cvtdq2ps xmm2, xmm2 ;xmm2 = (float) d
cvtdq2ps xmm3, xmm3 ;xmm3 = (float) 60
cvtdq2ps xmm4, xmm4 ;xmm4 = (float) 6
jmp .Hoperar
.Hcaso2:
movq xmm0, r9 ;xmm0 = b
movq xmm1, r8 ;xmm1 = r
movq xmm2, r15 ;xmm2 = d
mov r11 , 60
movq xmm3, r11 ;xmm3 = 60
mov r11 , 2
movq xmm4, r11 ;xmm4 = 2
cvtdq2ps xmm0, xmm0 ;xmm0 = (float) b
cvtdq2ps xmm1, xmm1 ;xmm1 = (float) r
cvtdq2ps xmm2, xmm2 ;xmm2 = (float) d
cvtdq2ps xmm3, xmm3 ;xmm3 = (float) 60
cvtdq2ps xmm4, xmm4 ;xmm4 = (float) 2
jmp .Hoperar
.Hcaso3:
movq xmm0, r8 ;xmm0 = r
movq xmm1, r10 ;xmm1 = g
movq xmm2, r15 ;xmm2 = d
mov r11 , 60
movq xmm3, r11 ;xmm3 = 60
mov r11 , 4
movq xmm4, r11 ;xmm4 = 4
cvtdq2ps xmm0, xmm0 ;xmm0 = (float) r
cvtdq2ps xmm1, xmm1 ;xmm0 = (float) g
cvtdq2ps xmm2, xmm2 ;xmm2 = (float) d
cvtdq2ps xmm3, xmm3 ;xmm3 = (float) 60
cvtdq2ps xmm4, xmm4 ;xmm4 = (float) 4
jmp .Hoperar
.Hoperar: ;(los comentarios de esta funcion son un mero ejemplo del caso 3, es analogo para los otros 2)
subps xmm0, xmm1 ;xmm0 = g-b
divps xmm0, xmm2 ;xmm0 = (g-b)/d
addps xmm0, xmm4 ;xmm0 = ((d-b)/d) + 4
mulps xmm0, xmm3 ;xmm0 = 60 * ( (d-b)/d + 4 )
;ultimo if
mov r8, 360
pxor xmm1, xmm1
pxor xmm2, xmm2
movq xmm1, r8 ;xmm1 = 360
cvtdq2ps xmm1, xmm1
movdqu xmm2, xmm1 ;xmm2 = 360
cmpleps xmm1, xmm0 ;xmm1 = 360 <= h
pand xmm2, xmm1 ;xmm2 = 360 o 0
subps xmm0, xmm2 ;xmm0 = h o h-360
pslldq xmm0, 12
psrldq xmm0, 12
jmp .calcL
.calcL:
pxor xmm1, xmm1
pxor xmm2, xmm2
mov r8, rbx ;r8 = max
add r8, r14 ;r8 = max + min
movq xmm1, r8 ;xmm1 = max + min
cvtdq2ps xmm1, xmm1
divps xmm1, [divL] ;xmm1 = ( max + min ) / 510
pslldq xmm1, 12
psrldq xmm1, 12
.calcS:
pxor xmm2, xmm2 ;xmm2 = 0
pxor xmm11, xmm11 ;xmm11 = 0
cmp rbx, r14
je .terminar
;else
movq xmm2, r15 ;xmm2 = d
cvtdq2ps xmm2, xmm2
mov r8, 1
movq xmm4, r8
cvtdq2ps xmm4, xmm4 ;xmm4 = 1.0
movdqu xmm3, xmm4 ;xmm3 = 1.0
addps xmm3, xmm3 ;xmm3 = 2.0
mulps xmm3, xmm1 ;xmm3 = 2*l
subps xmm3, xmm4 ;xmm3 = 2*l - 1
movdqu xmm12, [absmask]
pand xmm3, xmm12 ; abs(2*l - 1)
subps xmm4, xmm3 ;xmm4 = 1 - abs( 2*l - 1 )
divps xmm2, xmm4 ;xmm4 = d / ( 1 - fabs( 2*l - 1 ) )
divps xmm2, [divS] ;xmm2 = d / ( 1 - fabs( 2*l - 1 ) ) / 255.0001
pslldq xmm2, 12
psrldq xmm2, 12
.terminar:
movq xmm10, rdx
cvtdq2ps xmm10, xmm10
punpckldq xmm0, xmm1 ;xmm1 = 0 | 0 | l | h
punpckldq xmm10, xmm2 ;xmm2 = 0 | 0 | s | a
punpckldq xmm10, xmm0 ;xmm10 = l | s | h | a
movdqu [r13], xmm10
add rbp, 8
pop r15
pop r14
pop r13
pop r12
pop rbx
pop rbp
ret
hslTOrgb3: ; rdi = float *src rsi = uint8_t *dst
push rbp
mov rbp, rsp
push rbx
push r12
push r13
push r14
push r15
sub rbp, 8
mov r12, rdi ; r12 = *src
mov r13, rsi ; r13 = *dst
;separacion de elementos
pxor xmm1, xmm1
pxor xmm2, xmm2
movdqu xmm0, [r12] ;xmm0 = l | s | h | a
punpckldq xmm2, xmm0 ;xmm2 = h | 0 | a | 0
punpckhdq xmm1, xmm0 ;xmm1 = l | 0 | s | 0
;l
psrldq xmm0, 12 ;xmm0 = 0 | 0 | 0 | l
;s
pslldq xmm1, 4 ;xmm1 = 0 | s | 0 | 0
psrldq xmm1, 8 ;xmm1 = 0 | 0 | 0 | s
;h
movdqu xmm3, xmm2 ;xmm3 = h | 0 | a | 0
psrldq xmm2, 12 ;xmm2 = 0 | 0 | 0 | h
;a
pslldq xmm3, 4 ;xmm3 = 0 | a | 0 | 0
psrldq xmm3, 8 ;xmm3 = 0 | 0 | 0 | a
;Cálculo de c, x y m
.calcC:
movdqu xmm15, [one] ;xmm15 = 1
movdqu xmm4 , xmm15 ;xmm4 = 1
movdqu xmm5 , xmm4 ;xmm5 = 1
movdqu xmm10, xmm4 ;xmm5 = 1
addss xmm5, xmm5 ;xmm5 = 2
mulss xmm5, xmm0 ;xmm5 = 2*l
subss xmm5, xmm4 ;xmm5 = 2*l - 1
movdqu xmm11, [absmask] ;xmm11 = 0 yo todos 1s
pand xmm5 , xmm11 ;xmm5 = abs(2*l - 1)
subss xmm4, xmm5 ;xmm4 = 1 - abs(2*l - 1)
mulss xmm4, xmm1 ;xmm4 = ( 1 - abs(2*l - 1) ) * s
.calcX:
mov r8, 60
movq xmm10, r8
cvtdq2ps xmm10, xmm10 ;xmm10 = 60
movdqu xmm11, xmm2 ;xmm11 = h
divss xmm11, xmm10 ;xmm11 = h/60
movdqu xmm5 , xmm15 ;xmm5 = 1
movdqu xmm13, xmm5 ;xmm13 = 1
movdqu xmm12, [cmod2];xmm12 = 2.0
comiss xmm11, xmm12
jb .finloop
.modresta:
subss xmm11, xmm12 ;xmm11 = xmm11 - 60.0
comiss xmm12, xmm11
jbe .modresta
.finloop:
subss xmm11, xmm13 ;xmm11 = mod(h/60 , 2) - 1
movdqu xmm12, [absmask]
pand xmm11, xmm12 ;xmm11 = abs( mod(h/60 , 2) - 1 )
subss xmm13, xmm11 ;xmm13 = 1 - ( abs( mod(h/60 , 2) - 1 ) )
mulss xmm13, xmm4 ;xmm13 = c * ( 1 - ( abs( mod(h/60 , 2) - 1 ) ) )
movdqu xmm5 , xmm13 ;xmm5 = c * ( 1 - ( abs( mod(h/60 , 2) - 1 ) ) )
.calcM:
movdqu xmm10, xmm0 ;xmm10 = l
movdqu xmm11, xmm15 ;xmm11 = 1
addss xmm11, xmm11 ;xmm11 = 2
movdqu xmm12, xmm4 ;xmm12 = c
divss xmm12, xmm11 ;xmm12 = c/2
subss xmm10, xmm12 ;xmm10 = l - c/2
;Cálculo de RGB
.calcRGB:
pxor xmm12, xmm12
movdqu xmm11, [c060]
addss xmm12, xmm11 ;xmm12 = 60
;movd r10d, xmm5 ;r10 = x
pslldq xmm4 , 4 ;xmm4 = 0 | 0 | c | 0
addps xmm4 , xmm5 ;xmm4 = 0 | 0 | c | x
pslldq xmm4, 8
psrldq xmm4, 8
.mayig0:
comiss xmm2, xmm12
jb .men60
addss xmm12, xmm11 ;xmm12 = 120
comiss xmm2, xmm12
jb .men120
addss xmm12, xmm11 ;xmm12 = 180
comiss xmm2, xmm12
jb .men180
addss xmm12, xmm11 ;xmm12 = 240
comiss xmm2, xmm12
jb .men240
addss xmm12, xmm11 ;xmm12 = 300
comiss xmm2, xmm12
jb .men300
addss xmm12, xmm11 ;xmm12 = 360
comiss xmm2, xmm12
jb .men360
.men60:
;pslldq xmm4, 12 ;xmm4 = c | 0 | 0 | 0
;pinsrd xmm4, r10d, 2 ;xmm4 = c | x | 0 | 0
pshufd xmm5, xmm4, 01001111b
jmp .calcEscala
.men120:
pshufd xmm5, xmm4, 00011111b
;pslldq xmm4, 8 ;xmm4 = 0 | c | 0 | 0
;pinsrd xmm4, r10d, 3 ;xmm4 = x | c | 0 | 0
jmp .calcEscala
.men180:
pshufd xmm5, xmm4, 11010011b
;pslldq xmm4, 8 ;xmm4 = 0 | c | 0 | 0
;pinsrd xmm4, r10d, 1 ;xmm4 = 0 | c | x | 0
jmp .calcEscala
.men240:
pshufd xmm5, xmm4, 11000111b
;pslldq xmm4, 4 ;xmm4 = 0 | 0 | c | 0
;pinsrd xmm4, r10d, 2 ;xmm4 = 0 | x | c | 0
jmp .calcEscala
.men300:
pshufd xmm5, xmm4, 00110111b
;pslldq xmm4, 4 ;xmm4 = 0 | 0 | c | 0
;pinsrd xmm4, r10d, 3 ;xmm4 = x | 0 | c | 0
jmp .calcEscala
.men360:
pshufd xmm5, xmm4, 01110011b
;pslldq xmm4, 12 ;xmm4 = c | 0 | 0 | 0
;pinsrd xmm4, r10d, 1 ;xmm4 = c | 0 | x | 0
jmp .calcEscala
;Cálculo de escala
.calcEscala:
movdqu xmm4, xmm5
movdqu xmm12, xmm10 ;xmm12 = 0 | 0 | 0 | m
pslldq xmm12, 4 ;xmm12 = 0 | 0 | m | 0
addps xmm12, xmm10 ;xmm12 = 0 | 0 | m | m
pslldq xmm12, 4 ;xmm12 = 0 | m | m | 0
addps xmm12, xmm10 ;xmm12 = 0 | m | m | m
pslldq xmm12, 4 ;xmm12 = m | m | m | 0
movdqu xmm13, [cEscala] ;xmm13 = 255 | 255 | 255 | 0
addps xmm4, xmm12 ;xmm4 = r+m | g+m | b+m | X
mulps xmm4, xmm13 ;xmm4 = (r+m)*255 | (g+m)*255 | (b+m)*255 | 0
movd r10d, xmm3
pinsrd xmm4, r10d, 0 ;xmm4 = (r+m)*255 | (g+m)*255 | (b+m)*255 | a
cvttps2dq xmm4, xmm4
movdqu xmm10, [shuf] ; Shuffle para pasar dword int a byte int
pshufb xmm4 , xmm10 ; xmm4 = | 0 | 0 | 0 |R|G|B|A|
PEXTRD [r13], xmm4, 00b ; grabo a memoria
.terminar:
add rbp, 8
pop r15
pop r14
pop r13
pop r12
pop rbx
pop rbp
ret
| ilebrero/Orga2-TP2 | src/filters/ASM_hsl2_v1.asm | Assembly | mit | 13,070 |
.data
World: .ascii "____f____"
XCoord: .byte 4
under: .ascii "_"
frog: .ascii "f"
.text
# Call main Frogger repeatedly until has to exit
main:
lui $t0, 0xFFFF
j frogger
bne $v0, $zero, exit
j main
#display a character on the screen
emitchar:
lui $t0, 0xFFFF
lw $t1, 8($t0)
andi $t1, $t1, 0x0001
beq $t1, $zero, emitchar
sw $a0, 12($t0)
li $v0, 11
syscall
jr $ra
#display a string
emitseq:
beq $a0, $a1, seqexit
addi $a0, $a0, 1
j emitchar
#exit
seqexit:
jr $ra
#display the "world" string
emitworld:
addi $ra, $ra, -4($sp)
sw $ra, 0($sp)
jal emitseq
lw $ra, 0($sp)
addi $ra, $ra, 4($sp)
jr $ra
#"move" the player's character
blit_frog:
lw $t6, 0(XCoord)
lw $t7, 0($a0)
add $t7, $t6, $t7
sw under, $t6(World)
sw frog, $t7(World)
jr $ra
#check if the frog is moved, etc.
update_frog:
#is the key pressed q?
addi $s0, $zero, 113
beq $a0, $s0, exit
#is the key pressed l?
addi $s0, $zero, 108
beq $a0, $s0, check_right
#is the key pressed h?
addi $s0, $zero, 104
beq $a0, $s0, check_left
add $v0, $zero, $zero
j exit_frog
#move left?
check_left:
beq $zero, XCoord, no_update
add XCoord, XCoord, $a0
j emitworld
#move right?
check_right:
addi $t0, $zero, 9
beq $t0, XCoord, no_update
add XCoord, XCoord, $a0
j emitworld
#update the world string
update_world:
addi $a0, $a0, -1
addi $a1, $a1, 0
addi $v0, $v0, 0
j emitworld
j exit_frog
#no update needed
no_update:
addi $v0, $zero, 119
#exit move update stuff
exit_frog:
jr $ra
#check for frog movement
teechar:
addi $sp, $sp, -4
sw $ra, 0 ($sp)
jal keyboard
lw $ra, 0 ($sp)
addi $sp, $sp, 4
jr $ra
#frogger main class
frogger:
addi $sp, $sp, -4
sw $ra, 0 ($sp)
jal teechar
jal update_frog
lw $ra, 0 ($sp)
addi $sp, $sp, 4
jr $ra
# get input
keyboard:
lw $t1, 0($t0)
andi $t1, $t1, 0x0001
beq $t1, $zero, keyboard
lw $a0, 4($t0)
jr $ra
#exit game
exit:
li $v0, 10
syscall | vonderborch/CS260 | HW7/ChristianWebber-HW9-1.asm | Assembly | mit | 1,935 |
Map_CB994: dc.w word_CB996-Map_CB994
word_CB996: dc.w $1E ; DATA XREF: ROM:000CB994o
dc.b $D8, $F, $60, 0, $FF, $9C
dc.b $D8, $F, $60, $10, $FF, $BC
dc.b $D8, $F, $60, $20, $FF, $DC
dc.b $D8, $F, $60, $30, $FF, $FC
dc.b $D8, $B, $60, $40, 0, $1C
dc.b $E0, $E, $60, $4C, 0, $34
dc.b $F8, $C, $60, $58, $FF, $84
dc.b $F8, $C, $60, $5C, $FF, $A4
dc.b $F8, $C, $60, $60, $FF, $C4
dc.b $F8, $C, $60, $64, $FF, $E4
dc.b $F8, $C, $60, $68, 0, 4
dc.b $F8, $C, $60, $6C, 0, $24
dc.b $F8, $C, $60, $70, 0, $44
dc.b $F8, 8, $60, $74, 0, $64
dc.b 0, $F, $20, $77, $FF, $84
dc.b 0, $F, $20, $87, $FF, $A4
dc.b 0, $F, $20, $97, $FF, $C4
dc.b 0, $F, $20, $A7, $FF, $E4
dc.b 0, $F, $20, $B7, 0, 4
dc.b 0, $F, $20, $C7, 0, $24
dc.b 0, $F, $20, $D7, 0, $44
dc.b 0, $B, $20, $E7, 0, $64
dc.b $20, $C, $20, $F3, $FF, $84
dc.b $20, $C, $20, $F7, $FF, $A4
dc.b $20, $C, $20, $FB, $FF, $C4
dc.b $20, $C, $20, $FF, $FF, $E4
dc.b $20, $C, $21, 3, 0, 4
dc.b $20, $C, $21, 7, 0, $24
dc.b $20, $C, $21, $B, 0, $44
dc.b $20, 8, $21, $F, 0, $64
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/General/Title/Map - SK Banner.asm | Assembly | apache-2.0 | 1,171 |
dc.w word_35D5E-Map_BPZElephantBlock
dc.w word_35D6C-Map_BPZElephantBlock
word_35D5E: dc.w 2 ; DATA XREF: ROM:00035D5Ao
dc.b $F0, $F, 0, $6E, $FF, $F8
dc.b $F0, $F, 0, $7E, 0, $18
word_35D6C: dc.w 3 ; DATA XREF: ROM:00035D5Ao
dc.b $F0, $F, 0, $6E, $FF, $F8
dc.b $F0, $F, 0, $7E, 0, $18
dc.b $F0, $F, 0, $7E, 0, $38
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/Levels/BPZ/Misc Object Data/Map - Elephant Block.asm | Assembly | apache-2.0 | 361 |
.ORIG x3000
LEA R2, B
AND R0, R0, #0
AND R3, R3, #0
ADD R3, R3, #5
ADD R0, R0, #-5
STW R0, R2, #-1
STW R0, R2, #1
BRzp ERR
AND R3, R3, #0
ERR LDW R1, R2, #1
HALT
A .FILL xDEFA
B .FILL xCEDE
.END | Zaydax/PipelineProcessor | lab3_test_harness/Lab1test/stw.asm | Assembly | mit | 213 |
;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
EXPORT |vp8_sixtap_predict8x4_neon|
ARM
REQUIRE8
PRESERVE8
AREA ||.text||, CODE, READONLY, ALIGN=2
; r0 unsigned char *src_ptr,
; r1 int src_pixels_per_line,
; r2 int xoffset,
; r3 int yoffset,
; r4 unsigned char *dst_ptr,
; stack(r5) int dst_pitch
|vp8_sixtap_predict8x4_neon| PROC
push {r4-r5, lr}
ldr r12, _filter8_coeff_
ldr r4, [sp, #12] ;load parameters from stack
ldr r5, [sp, #16] ;load parameters from stack
cmp r2, #0 ;skip first_pass filter if xoffset=0
beq secondpass_filter8x4_only
add r2, r12, r2, lsl #5 ;calculate filter location
cmp r3, #0 ;skip second_pass filter if yoffset=0
vld1.s32 {q14, q15}, [r2] ;load first_pass filter
beq firstpass_filter8x4_only
sub sp, sp, #32 ;reserve space on stack for temporary storage
vabs.s32 q12, q14
vabs.s32 q13, q15
sub r0, r0, #2 ;move srcptr back to (line-2) and (column-2)
mov lr, sp
sub r0, r0, r1, lsl #1
vdup.8 d0, d24[0] ;first_pass filter (d0-d5)
vdup.8 d1, d24[4]
vdup.8 d2, d25[0]
;First pass: output_height lines x output_width columns (9x8)
vld1.u8 {q3}, [r0], r1 ;load src data
vdup.8 d3, d25[4]
vld1.u8 {q4}, [r0], r1
vdup.8 d4, d26[0]
vld1.u8 {q5}, [r0], r1
vdup.8 d5, d26[4]
vld1.u8 {q6}, [r0], r1
pld [r0]
pld [r0, r1]
pld [r0, r1, lsl #1]
vmull.u8 q7, d6, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q8, d8, d0
vmull.u8 q9, d10, d0
vmull.u8 q10, d12, d0
vext.8 d28, d6, d7, #1 ;construct src_ptr[-1]
vext.8 d29, d8, d9, #1
vext.8 d30, d10, d11, #1
vext.8 d31, d12, d13, #1
vmlsl.u8 q7, d28, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q8, d29, d1
vmlsl.u8 q9, d30, d1
vmlsl.u8 q10, d31, d1
vext.8 d28, d6, d7, #4 ;construct src_ptr[2]
vext.8 d29, d8, d9, #4
vext.8 d30, d10, d11, #4
vext.8 d31, d12, d13, #4
vmlsl.u8 q7, d28, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q8, d29, d4
vmlsl.u8 q9, d30, d4
vmlsl.u8 q10, d31, d4
vext.8 d28, d6, d7, #2 ;construct src_ptr[0]
vext.8 d29, d8, d9, #2
vext.8 d30, d10, d11, #2
vext.8 d31, d12, d13, #2
vmlal.u8 q7, d28, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q8, d29, d2
vmlal.u8 q9, d30, d2
vmlal.u8 q10, d31, d2
vext.8 d28, d6, d7, #5 ;construct src_ptr[3]
vext.8 d29, d8, d9, #5
vext.8 d30, d10, d11, #5
vext.8 d31, d12, d13, #5
vmlal.u8 q7, d28, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q8, d29, d5
vmlal.u8 q9, d30, d5
vmlal.u8 q10, d31, d5
vext.8 d28, d6, d7, #3 ;construct src_ptr[1]
vext.8 d29, d8, d9, #3
vext.8 d30, d10, d11, #3
vext.8 d31, d12, d13, #3
vmull.u8 q3, d28, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q4, d29, d3
vmull.u8 q5, d30, d3
vmull.u8 q6, d31, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vld1.u8 {q3}, [r0], r1 ;load src data
vqrshrun.s16 d22, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d23, q8, #7
vqrshrun.s16 d24, q9, #7
vqrshrun.s16 d25, q10, #7
vld1.u8 {q4}, [r0], r1
vst1.u8 {d22}, [lr]! ;store result
vld1.u8 {q5}, [r0], r1
vst1.u8 {d23}, [lr]!
vld1.u8 {q6}, [r0], r1
vst1.u8 {d24}, [lr]!
vld1.u8 {q7}, [r0], r1
vst1.u8 {d25}, [lr]!
;first_pass filtering on the rest 5-line data
vmull.u8 q8, d6, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q9, d8, d0
vmull.u8 q10, d10, d0
vmull.u8 q11, d12, d0
vmull.u8 q12, d14, d0
vext.8 d27, d6, d7, #1 ;construct src_ptr[-1]
vext.8 d28, d8, d9, #1
vext.8 d29, d10, d11, #1
vext.8 d30, d12, d13, #1
vext.8 d31, d14, d15, #1
vmlsl.u8 q8, d27, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q9, d28, d1
vmlsl.u8 q10, d29, d1
vmlsl.u8 q11, d30, d1
vmlsl.u8 q12, d31, d1
vext.8 d27, d6, d7, #4 ;construct src_ptr[2]
vext.8 d28, d8, d9, #4
vext.8 d29, d10, d11, #4
vext.8 d30, d12, d13, #4
vext.8 d31, d14, d15, #4
vmlsl.u8 q8, d27, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q9, d28, d4
vmlsl.u8 q10, d29, d4
vmlsl.u8 q11, d30, d4
vmlsl.u8 q12, d31, d4
vext.8 d27, d6, d7, #2 ;construct src_ptr[0]
vext.8 d28, d8, d9, #2
vext.8 d29, d10, d11, #2
vext.8 d30, d12, d13, #2
vext.8 d31, d14, d15, #2
vmlal.u8 q8, d27, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q9, d28, d2
vmlal.u8 q10, d29, d2
vmlal.u8 q11, d30, d2
vmlal.u8 q12, d31, d2
vext.8 d27, d6, d7, #5 ;construct src_ptr[3]
vext.8 d28, d8, d9, #5
vext.8 d29, d10, d11, #5
vext.8 d30, d12, d13, #5
vext.8 d31, d14, d15, #5
vmlal.u8 q8, d27, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q9, d28, d5
vmlal.u8 q10, d29, d5
vmlal.u8 q11, d30, d5
vmlal.u8 q12, d31, d5
vext.8 d27, d6, d7, #3 ;construct src_ptr[1]
vext.8 d28, d8, d9, #3
vext.8 d29, d10, d11, #3
vext.8 d30, d12, d13, #3
vext.8 d31, d14, d15, #3
vmull.u8 q3, d27, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q4, d28, d3
vmull.u8 q5, d29, d3
vmull.u8 q6, d30, d3
vmull.u8 q7, d31, d3
vqadd.s16 q8, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q9, q4
vqadd.s16 q10, q5
vqadd.s16 q11, q6
vqadd.s16 q12, q7
vqrshrun.s16 d26, q8, #7 ;shift/round/saturate to u8
vqrshrun.s16 d27, q9, #7
vqrshrun.s16 d28, q10, #7
vqrshrun.s16 d29, q11, #7 ;load intermediate data from stack
vqrshrun.s16 d30, q12, #7
;Second pass: 8x4
;secondpass_filter
add r3, r12, r3, lsl #5
sub lr, lr, #32
vld1.s32 {q5, q6}, [r3] ;load second_pass filter
vld1.u8 {q11}, [lr]!
vabs.s32 q7, q5
vabs.s32 q8, q6
vld1.u8 {q12}, [lr]!
vdup.8 d0, d14[0] ;second_pass filter parameters (d0-d5)
vdup.8 d1, d14[4]
vdup.8 d2, d15[0]
vdup.8 d3, d15[4]
vdup.8 d4, d16[0]
vdup.8 d5, d16[4]
vmull.u8 q3, d22, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q4, d23, d0
vmull.u8 q5, d24, d0
vmull.u8 q6, d25, d0
vmlsl.u8 q3, d23, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q4, d24, d1
vmlsl.u8 q5, d25, d1
vmlsl.u8 q6, d26, d1
vmlsl.u8 q3, d26, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q4, d27, d4
vmlsl.u8 q5, d28, d4
vmlsl.u8 q6, d29, d4
vmlal.u8 q3, d24, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q4, d25, d2
vmlal.u8 q5, d26, d2
vmlal.u8 q6, d27, d2
vmlal.u8 q3, d27, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q4, d28, d5
vmlal.u8 q5, d29, d5
vmlal.u8 q6, d30, d5
vmull.u8 q7, d25, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q8, d26, d3
vmull.u8 q9, d27, d3
vmull.u8 q10, d28, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vqrshrun.s16 d6, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d7, q8, #7
vqrshrun.s16 d8, q9, #7
vqrshrun.s16 d9, q10, #7
vst1.u8 {d6}, [r4], r5 ;store result
vst1.u8 {d7}, [r4], r5
vst1.u8 {d8}, [r4], r5
vst1.u8 {d9}, [r4], r5
add sp, sp, #32
pop {r4-r5,pc}
;--------------------
firstpass_filter8x4_only
vabs.s32 q12, q14
vabs.s32 q13, q15
sub r0, r0, #2 ;move srcptr back to (line-2) and (column-2)
vld1.u8 {q3}, [r0], r1 ;load src data
vdup.8 d0, d24[0] ;first_pass filter (d0-d5)
vld1.u8 {q4}, [r0], r1
vdup.8 d1, d24[4]
vld1.u8 {q5}, [r0], r1
vdup.8 d2, d25[0]
vld1.u8 {q6}, [r0], r1
vdup.8 d3, d25[4]
vdup.8 d4, d26[0]
vdup.8 d5, d26[4]
;First pass: output_height lines x output_width columns (4x8)
pld [r0]
pld [r0, r1]
pld [r0, r1, lsl #1]
vmull.u8 q7, d6, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q8, d8, d0
vmull.u8 q9, d10, d0
vmull.u8 q10, d12, d0
vext.8 d28, d6, d7, #1 ;construct src_ptr[-1]
vext.8 d29, d8, d9, #1
vext.8 d30, d10, d11, #1
vext.8 d31, d12, d13, #1
vmlsl.u8 q7, d28, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q8, d29, d1
vmlsl.u8 q9, d30, d1
vmlsl.u8 q10, d31, d1
vext.8 d28, d6, d7, #4 ;construct src_ptr[2]
vext.8 d29, d8, d9, #4
vext.8 d30, d10, d11, #4
vext.8 d31, d12, d13, #4
vmlsl.u8 q7, d28, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q8, d29, d4
vmlsl.u8 q9, d30, d4
vmlsl.u8 q10, d31, d4
vext.8 d28, d6, d7, #2 ;construct src_ptr[0]
vext.8 d29, d8, d9, #2
vext.8 d30, d10, d11, #2
vext.8 d31, d12, d13, #2
vmlal.u8 q7, d28, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q8, d29, d2
vmlal.u8 q9, d30, d2
vmlal.u8 q10, d31, d2
vext.8 d28, d6, d7, #5 ;construct src_ptr[3]
vext.8 d29, d8, d9, #5
vext.8 d30, d10, d11, #5
vext.8 d31, d12, d13, #5
vmlal.u8 q7, d28, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q8, d29, d5
vmlal.u8 q9, d30, d5
vmlal.u8 q10, d31, d5
vext.8 d28, d6, d7, #3 ;construct src_ptr[1]
vext.8 d29, d8, d9, #3
vext.8 d30, d10, d11, #3
vext.8 d31, d12, d13, #3
vmull.u8 q3, d28, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q4, d29, d3
vmull.u8 q5, d30, d3
vmull.u8 q6, d31, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vqrshrun.s16 d22, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d23, q8, #7
vqrshrun.s16 d24, q9, #7
vqrshrun.s16 d25, q10, #7
vst1.u8 {d22}, [r4], r5 ;store result
vst1.u8 {d23}, [r4], r5
vst1.u8 {d24}, [r4], r5
vst1.u8 {d25}, [r4], r5
pop {r4-r5,pc}
;---------------------
secondpass_filter8x4_only
;Second pass: 8x4
add r3, r12, r3, lsl #5
sub r0, r0, r1, lsl #1
vld1.s32 {q5, q6}, [r3] ;load second_pass filter
vabs.s32 q7, q5
vabs.s32 q8, q6
vld1.u8 {d22}, [r0], r1
vld1.u8 {d23}, [r0], r1
vld1.u8 {d24}, [r0], r1
vdup.8 d0, d14[0] ;second_pass filter parameters (d0-d5)
vld1.u8 {d25}, [r0], r1
vdup.8 d1, d14[4]
vld1.u8 {d26}, [r0], r1
vdup.8 d2, d15[0]
vld1.u8 {d27}, [r0], r1
vdup.8 d3, d15[4]
vld1.u8 {d28}, [r0], r1
vdup.8 d4, d16[0]
vld1.u8 {d29}, [r0], r1
vdup.8 d5, d16[4]
vld1.u8 {d30}, [r0], r1
vmull.u8 q3, d22, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q4, d23, d0
vmull.u8 q5, d24, d0
vmull.u8 q6, d25, d0
vmlsl.u8 q3, d23, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q4, d24, d1
vmlsl.u8 q5, d25, d1
vmlsl.u8 q6, d26, d1
vmlsl.u8 q3, d26, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q4, d27, d4
vmlsl.u8 q5, d28, d4
vmlsl.u8 q6, d29, d4
vmlal.u8 q3, d24, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q4, d25, d2
vmlal.u8 q5, d26, d2
vmlal.u8 q6, d27, d2
vmlal.u8 q3, d27, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q4, d28, d5
vmlal.u8 q5, d29, d5
vmlal.u8 q6, d30, d5
vmull.u8 q7, d25, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q8, d26, d3
vmull.u8 q9, d27, d3
vmull.u8 q10, d28, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vqrshrun.s16 d6, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d7, q8, #7
vqrshrun.s16 d8, q9, #7
vqrshrun.s16 d9, q10, #7
vst1.u8 {d6}, [r4], r5 ;store result
vst1.u8 {d7}, [r4], r5
vst1.u8 {d8}, [r4], r5
vst1.u8 {d9}, [r4], r5
pop {r4-r5,pc}
ENDP
;-----------------
_filter8_coeff_
DCD filter8_coeff
filter8_coeff
DCD 0, 0, 128, 0, 0, 0, 0, 0
DCD 0, -6, 123, 12, -1, 0, 0, 0
DCD 2, -11, 108, 36, -8, 1, 0, 0
DCD 0, -9, 93, 50, -6, 0, 0, 0
DCD 3, -16, 77, 77, -16, 3, 0, 0
DCD 0, -6, 50, 93, -9, 0, 0, 0
DCD 1, -8, 36, 108, -11, 2, 0, 0
DCD 0, -1, 12, 123, -6, 0, 0, 0
END
| allwinner-ics/platform_external_libvpx | vp8/common/arm/neon/sixtappredict8x4_neon.asm | Assembly | bsd-3-clause | 15,863 |
BITS 16
org 100h
jmp START
%INCLUDE "../../../lib/io.asm"
%INCLUDE "../../../lib/string.asm"
;-------------------------------------------------------------------------
START:
MOV AX, 0x0D ; AH: 00, AL: 0D = EGA 16 COLOR
INT 10h ; call BIOS video mode
MOV AH, 0Bh
MOV BX, 00
INT 10h
MOV CX, 0x16
.DO: MOV BX, CX
MOV SI, STR
CALL MOS_IO_PRINT_STRING_C
LOOP .DO
RET
STR: DB "Give life back to music!", 0
| johnnystarr/mos | src/test/io/io_print_string_c/io_print_string_c.asm | Assembly | mit | 455 |
INCLUDE "hardware.inc"
INCLUDE "header.inc"
;--------------------------------------------------------------------------
SECTION "Main",HOME
;------------------------------------
ClearSprites:
push hl
ld b,144
call wait_ly
xor a,a
ld b,$A0
ld hl,$FE00
.loop:
ld [hl+],a
dec b
jr nz,.loop
pop hl
ret
PrepareSprites: ; d = number of sprites in test line
ld b,144
call wait_ly
ld hl,$FE00
.loop:
ld a,d
and a,a
ret z
ld a,48+16
ld [hl+],a
ld a,50
ld [hl+],a
ld a,0
ld [hl+],a
ld [hl+],a
dec d
jr .loop
;--------------------------------------------------------------------------
;- Main() -
;--------------------------------------------------------------------------
Main:
; -------------------------------------------------------
ld a,$0A
ld [$0000],a ; enable ram
ld hl,$A000
ld a,LCDCF_ON|LCDCF_OBJON|LCDCF_OBJ16
ld [rLCDC],a
; -------------------------------------------------------
PERFORM_TEST : MACRO
di
push hl
ld bc,$007F
ld hl,\1
ld de,$FF80
call memcopy
ld b,45
call wait_ly
ld a,50
ld [rLYC],a
ld a,STATF_LYC
ld [rSTAT],a
ld a,IEF_LCDC
ld [rIE],a
xor a,a
ld [rIF],a
pop hl
ei
halt
ENDM
call ClearSprites
ld d,0
.next_spr_number:
push de
push hl
call PrepareSprites
pop hl
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$82
ld [rNR14],a
PERFORM_TEST LCD_INT_HANDLER_0
PERFORM_TEST LCD_INT_HANDLER_1
PERFORM_TEST LCD_INT_HANDLER_2
PERFORM_TEST LCD_INT_HANDLER_3
PERFORM_TEST LCD_INT_HANDLER_4
PERFORM_TEST LCD_INT_HANDLER_5
PERFORM_TEST LCD_INT_HANDLER_6
PERFORM_TEST LCD_INT_HANDLER_7
PERFORM_TEST LCD_INT_HANDLER_8
PERFORM_TEST LCD_INT_HANDLER_9
PERFORM_TEST LCD_INT_HANDLER_10
PERFORM_TEST LCD_INT_HANDLER_11
PERFORM_TEST LCD_INT_HANDLER_12
PERFORM_TEST LCD_INT_HANDLER_13
PERFORM_TEST LCD_INT_HANDLER_14
PERFORM_TEST LCD_INT_HANDLER_15
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$83
ld [rNR14],a
PERFORM_TEST LCD_INT_HANDLER_16
PERFORM_TEST LCD_INT_HANDLER_17
PERFORM_TEST LCD_INT_HANDLER_18
PERFORM_TEST LCD_INT_HANDLER_19
PERFORM_TEST LCD_INT_HANDLER_20
PERFORM_TEST LCD_INT_HANDLER_21
PERFORM_TEST LCD_INT_HANDLER_22
PERFORM_TEST LCD_INT_HANDLER_23
PERFORM_TEST LCD_INT_HANDLER_24
PERFORM_TEST LCD_INT_HANDLER_25
PERFORM_TEST LCD_INT_HANDLER_26
PERFORM_TEST LCD_INT_HANDLER_27
PERFORM_TEST LCD_INT_HANDLER_28
PERFORM_TEST LCD_INT_HANDLER_29
PERFORM_TEST LCD_INT_HANDLER_30
PERFORM_TEST LCD_INT_HANDLER_31
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$82
ld [rNR14],a
pop de
inc d
ld a,16
cp a,d
jp nz,.next_spr_number
; --------------------------------
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$87
ld [rNR14],a
push hl
ld [hl],$12
inc hl
ld [hl],$34
inc hl
ld [hl],$56
inc hl
ld [hl],$78
pop hl
ld a,$00
ld [$0000],a ; disable ram
.endloop:
halt
jr .endloop
; --------------------------------------------------------------
SECTION "functions",ROMX,BANK[1]
LCD_INT_HANDLER_MACRO : MACRO
REPT \1
nop
ENDR
ld a,[rSTAT]
ld [hl+],a
ret
ENDM
LCD_INT_HANDLER_0: LCD_INT_HANDLER_MACRO 0
LCD_INT_HANDLER_1: LCD_INT_HANDLER_MACRO 1
LCD_INT_HANDLER_2: LCD_INT_HANDLER_MACRO 2
LCD_INT_HANDLER_3: LCD_INT_HANDLER_MACRO 3
LCD_INT_HANDLER_4: LCD_INT_HANDLER_MACRO 4
LCD_INT_HANDLER_5: LCD_INT_HANDLER_MACRO 5
LCD_INT_HANDLER_6: LCD_INT_HANDLER_MACRO 6
LCD_INT_HANDLER_7: LCD_INT_HANDLER_MACRO 7
LCD_INT_HANDLER_8: LCD_INT_HANDLER_MACRO 8
LCD_INT_HANDLER_9: LCD_INT_HANDLER_MACRO 9
LCD_INT_HANDLER_10: LCD_INT_HANDLER_MACRO 10
LCD_INT_HANDLER_11: LCD_INT_HANDLER_MACRO 11
LCD_INT_HANDLER_12: LCD_INT_HANDLER_MACRO 12
LCD_INT_HANDLER_13: LCD_INT_HANDLER_MACRO 13
LCD_INT_HANDLER_14: LCD_INT_HANDLER_MACRO 14
LCD_INT_HANDLER_15: LCD_INT_HANDLER_MACRO 15
LCD_INT_HANDLER_16: LCD_INT_HANDLER_MACRO 16
LCD_INT_HANDLER_17: LCD_INT_HANDLER_MACRO 17
LCD_INT_HANDLER_18: LCD_INT_HANDLER_MACRO 18
LCD_INT_HANDLER_19: LCD_INT_HANDLER_MACRO 19
LCD_INT_HANDLER_20: LCD_INT_HANDLER_MACRO 20
LCD_INT_HANDLER_21: LCD_INT_HANDLER_MACRO 21
LCD_INT_HANDLER_22: LCD_INT_HANDLER_MACRO 22
LCD_INT_HANDLER_23: LCD_INT_HANDLER_MACRO 23
LCD_INT_HANDLER_24: LCD_INT_HANDLER_MACRO 24
LCD_INT_HANDLER_25: LCD_INT_HANDLER_MACRO 25
LCD_INT_HANDLER_26: LCD_INT_HANDLER_MACRO 26
LCD_INT_HANDLER_27: LCD_INT_HANDLER_MACRO 27
LCD_INT_HANDLER_28: LCD_INT_HANDLER_MACRO 28
LCD_INT_HANDLER_29: LCD_INT_HANDLER_MACRO 29
LCD_INT_HANDLER_30: LCD_INT_HANDLER_MACRO 30
LCD_INT_HANDLER_31: LCD_INT_HANDLER_MACRO 31
; --------------------------------------------------------------
| AntonioND/gbc-hw-tests | lcd/mode2/mode2_stat_timing_spr_en_dmg_mode_8x16/main.asm | Assembly | mit | 5,036 |
; Listing generated by Microsoft (R) Optimizing Compiler Version 19.00.23506.0
TITLE D:\Projects\TaintAnalysis\AntiTaint\Epilog\src\struct-align.c
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB MSVCRT
INCLUDELIB OLDNAMES
_DATA SEGMENT
$SG5418 DB '%d %d %d', 00H
ORG $+3
$SG5428 DB '%s %d %d %d', 0aH, 00H
_DATA ENDS
PUBLIC ___local_stdio_printf_options
PUBLIC ___local_stdio_scanf_options
PUBLIC __vfprintf_l
PUBLIC _printf
PUBLIC __vfscanf_l
PUBLIC _scanf
PUBLIC _fill
PUBLIC _func
PUBLIC _main
EXTRN __imp____acrt_iob_func:PROC
EXTRN __imp____stdio_common_vfprintf:PROC
EXTRN __imp____stdio_common_vfscanf:PROC
EXTRN _gets:PROC
EXTRN @__security_check_cookie@4:PROC
EXTRN ___security_cookie:DWORD
_DATA SEGMENT
COMM ?_OptionsStorage@?1??__local_stdio_printf_options@@9@9:QWORD ; `__local_stdio_printf_options'::`2'::_OptionsStorage
COMM ?_OptionsStorage@?1??__local_stdio_scanf_options@@9@9:QWORD ; `__local_stdio_scanf_options'::`2'::_OptionsStorage
_DATA ENDS
; Function compile flags: /Odtpy
; File d:\projects\taintanalysis\antitaint\epilog\src\struct-align.c
_TEXT SEGMENT
_main PROC
; 39 : {
push ebp
mov ebp, esp
; 40 : func();
call _func
; 41 : return 0;
xor eax, eax
; 42 : }
pop ebp
ret 0
_main ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File d:\projects\taintanalysis\antitaint\epilog\src\struct-align.c
_TEXT SEGMENT
_s$ = -64 ; size = 32
_buf$ = -12 ; size = 8
__$ArrayPad$ = -4 ; size = 4
_func PROC
; 30 : {
push ebp
mov ebp, esp
and esp, -32 ; ffffffe0H
sub esp, 64 ; 00000040H
mov eax, DWORD PTR ___security_cookie
xor eax, esp
mov DWORD PTR __$ArrayPad$[esp+64], eax
; 31 : struct S s;
; 32 : char buf[8];
; 33 : gets(buf);
lea eax, DWORD PTR _buf$[esp+64]
push eax
call _gets
add esp, 4
; 34 : fill(&s);
lea ecx, DWORD PTR _s$[esp+64]
push ecx
call _fill
add esp, 4
; 35 : printf("%s %d %d %d\n", buf, (int)s.a, (int)s.b, (int)s.c);
mov edx, DWORD PTR _s$[esp+80]
push edx
mov eax, DWORD PTR _s$[esp+76]
push eax
mov ecx, DWORD PTR _s$[esp+72]
push ecx
lea edx, DWORD PTR _buf$[esp+76]
push edx
push OFFSET $SG5428
call _printf
add esp, 20 ; 00000014H
; 36 : }
mov ecx, DWORD PTR __$ArrayPad$[esp+64]
xor ecx, esp
call @__security_check_cookie@4
mov esp, ebp
pop ebp
ret 0
_func ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File d:\projects\taintanalysis\antitaint\epilog\src\struct-align.c
_TEXT SEGMENT
_c$ = -12 ; size = 4
_b$ = -8 ; size = 4
_a$ = -4 ; size = 4
_s$ = 8 ; size = 4
_fill PROC
; 21 : {
push ebp
mov ebp, esp
sub esp, 12 ; 0000000cH
; 22 : int a, b, c;
; 23 : scanf("%d %d %d", &a, &b, &c);
lea eax, DWORD PTR _c$[ebp]
push eax
lea ecx, DWORD PTR _b$[ebp]
push ecx
lea edx, DWORD PTR _a$[ebp]
push edx
push OFFSET $SG5418
call _scanf
add esp, 16 ; 00000010H
; 24 : s->a = a;
mov eax, DWORD PTR _a$[ebp]
cdq
mov ecx, DWORD PTR _s$[ebp]
mov DWORD PTR [ecx], eax
mov DWORD PTR [ecx+4], edx
; 25 : s->b = b;
mov eax, DWORD PTR _b$[ebp]
cdq
mov ecx, DWORD PTR _s$[ebp]
mov DWORD PTR [ecx+8], eax
mov DWORD PTR [ecx+12], edx
; 26 : s->c = c;
mov eax, DWORD PTR _c$[ebp]
cdq
mov ecx, DWORD PTR _s$[ebp]
mov DWORD PTR [ecx+16], eax
mov DWORD PTR [ecx+20], edx
; 27 : }
mov esp, ebp
pop ebp
ret 0
_fill ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT _scanf
_TEXT SEGMENT
__Result$ = -8 ; size = 4
__ArgList$ = -4 ; size = 4
__Format$ = 8 ; size = 4
_scanf PROC ; COMDAT
; 1276 : {
push ebp
mov ebp, esp
sub esp, 8
; 1277 : int _Result;
; 1278 : va_list _ArgList;
; 1279 : __crt_va_start(_ArgList, _Format);
lea eax, DWORD PTR __Format$[ebp+4]
mov DWORD PTR __ArgList$[ebp], eax
; 1280 : _Result = _vfscanf_l(stdin, _Format, NULL, _ArgList);
mov ecx, DWORD PTR __ArgList$[ebp]
push ecx
push 0
mov edx, DWORD PTR __Format$[ebp]
push edx
push 0
call DWORD PTR __imp____acrt_iob_func
add esp, 4
push eax
call __vfscanf_l
add esp, 16 ; 00000010H
mov DWORD PTR __Result$[ebp], eax
; 1281 : __crt_va_end(_ArgList);
mov DWORD PTR __ArgList$[ebp], 0
; 1282 : return _Result;
mov eax, DWORD PTR __Result$[ebp]
; 1283 : }
mov esp, ebp
pop ebp
ret 0
_scanf ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT __vfscanf_l
_TEXT SEGMENT
__Stream$ = 8 ; size = 4
__Format$ = 12 ; size = 4
__Locale$ = 16 ; size = 4
__ArgList$ = 20 ; size = 4
__vfscanf_l PROC ; COMDAT
; 1058 : {
push ebp
mov ebp, esp
; 1059 : return __stdio_common_vfscanf(
mov eax, DWORD PTR __ArgList$[ebp]
push eax
mov ecx, DWORD PTR __Locale$[ebp]
push ecx
mov edx, DWORD PTR __Format$[ebp]
push edx
mov eax, DWORD PTR __Stream$[ebp]
push eax
call ___local_stdio_scanf_options
mov ecx, DWORD PTR [eax+4]
push ecx
mov edx, DWORD PTR [eax]
push edx
call DWORD PTR __imp____stdio_common_vfscanf
add esp, 24 ; 00000018H
; 1060 : _CRT_INTERNAL_LOCAL_SCANF_OPTIONS,
; 1061 : _Stream, _Format, _Locale, _ArgList);
; 1062 : }
pop ebp
ret 0
__vfscanf_l ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT _printf
_TEXT SEGMENT
__Result$ = -8 ; size = 4
__ArgList$ = -4 ; size = 4
__Format$ = 8 ; size = 4
_printf PROC ; COMDAT
; 950 : {
push ebp
mov ebp, esp
sub esp, 8
; 951 : int _Result;
; 952 : va_list _ArgList;
; 953 : __crt_va_start(_ArgList, _Format);
lea eax, DWORD PTR __Format$[ebp+4]
mov DWORD PTR __ArgList$[ebp], eax
; 954 : _Result = _vfprintf_l(stdout, _Format, NULL, _ArgList);
mov ecx, DWORD PTR __ArgList$[ebp]
push ecx
push 0
mov edx, DWORD PTR __Format$[ebp]
push edx
push 1
call DWORD PTR __imp____acrt_iob_func
add esp, 4
push eax
call __vfprintf_l
add esp, 16 ; 00000010H
mov DWORD PTR __Result$[ebp], eax
; 955 : __crt_va_end(_ArgList);
mov DWORD PTR __ArgList$[ebp], 0
; 956 : return _Result;
mov eax, DWORD PTR __Result$[ebp]
; 957 : }
mov esp, ebp
pop ebp
ret 0
_printf ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT __vfprintf_l
_TEXT SEGMENT
__Stream$ = 8 ; size = 4
__Format$ = 12 ; size = 4
__Locale$ = 16 ; size = 4
__ArgList$ = 20 ; size = 4
__vfprintf_l PROC ; COMDAT
; 638 : {
push ebp
mov ebp, esp
; 639 : return __stdio_common_vfprintf(_CRT_INTERNAL_LOCAL_PRINTF_OPTIONS, _Stream, _Format, _Locale, _ArgList);
mov eax, DWORD PTR __ArgList$[ebp]
push eax
mov ecx, DWORD PTR __Locale$[ebp]
push ecx
mov edx, DWORD PTR __Format$[ebp]
push edx
mov eax, DWORD PTR __Stream$[ebp]
push eax
call ___local_stdio_printf_options
mov ecx, DWORD PTR [eax+4]
push ecx
mov edx, DWORD PTR [eax]
push edx
call DWORD PTR __imp____stdio_common_vfprintf
add esp, 24 ; 00000018H
; 640 : }
pop ebp
ret 0
__vfprintf_l ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\corecrt_stdio_config.h
; COMDAT ___local_stdio_scanf_options
_TEXT SEGMENT
___local_stdio_scanf_options PROC ; COMDAT
; 82 : {
push ebp
mov ebp, esp
; 83 : static unsigned __int64 _OptionsStorage;
; 84 : return &_OptionsStorage;
mov eax, OFFSET ?_OptionsStorage@?1??__local_stdio_scanf_options@@9@9 ; `__local_stdio_scanf_options'::`2'::_OptionsStorage
; 85 : }
pop ebp
ret 0
___local_stdio_scanf_options ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\corecrt_stdio_config.h
; COMDAT ___local_stdio_printf_options
_TEXT SEGMENT
___local_stdio_printf_options PROC ; COMDAT
; 73 : {
push ebp
mov ebp, esp
; 74 : static unsigned __int64 _OptionsStorage;
; 75 : return &_OptionsStorage;
mov eax, OFFSET ?_OptionsStorage@?1??__local_stdio_printf_options@@9@9 ; `__local_stdio_printf_options'::`2'::_OptionsStorage
; 76 : }
pop ebp
ret 0
___local_stdio_printf_options ENDP
_TEXT ENDS
END
| Dovgalyuk/AntiTaint | Epilog/asm/MSVC2015/struct-align-omitfp-stackp.asm | Assembly | apache-2.0 | 8,764 |
myloop:
add r1, r1, r25 ; r1 <= 1
add r1, r25, r1 ; r1 <= 2
add r1, r1, r2 ; r1 <= 3
add r1, r1, r3 ; r1 <= 4
add r1, r1, r4 ; r1 <= 5
xor r20, r20, r25 ; toggle lsb of r20.
j myloop ; PC = PC + 4 - 11*4 = -40 (28 hexadecimal) = go to the beginning of the program.
| dpolad/dlx | assembler/assembler.bin/my.asm | Assembly | bsd-2-clause | 285 |
./out/shl.out: ファイル形式 elf32-mist32
セクション .text の逆アセンブル:
00000000 <_start>:
0: 0d 40 00 00 wl16 r0,0x0
4: 0d 60 00 0f wh16 r0,0xf
8: 1c 00 00 00 srspw r0
c: 14 30 00 18 br 6c <check>,#al
00000010 <compare>:
10: 00 c0 01 09 cmp r8,r9
14: 14 41 03 e0 b rret,#eq
00000018 <error>:
18: 0d 40 00 00 wl16 r0,0x0
1c: 0d 60 00 02 wh16 r0,0x2
20: 0e c0 00 20 lil r1,0
24: 10 a0 00 20 st32 r1,r0
28: 0d 40 00 0c wl16 r0,0xc
2c: 0d 60 00 02 wh16 r0,0x2
30: 10 a0 00 40 st32 r2,r0
34: 0d 40 00 08 wl16 r0,0x8
38: 0d 60 00 02 wh16 r0,0x2
3c: 10 a0 00 60 st32 r3,r0
40: 0d 40 00 10 wl16 r0,0x10
44: 0d 60 00 02 wh16 r0,0x2
48: 10 a0 01 00 st32 r8,r0
4c: 0d 40 00 14 wl16 r0,0x14
50: 0d 60 00 02 wh16 r0,0x2
54: 10 a0 01 20 st32 r9,r0
00000058 <finish>:
58: 0d 40 00 04 wl16 r0,0x4
5c: 0d 60 00 02 wh16 r0,0x2
60: 0e c0 00 21 lil r1,1
64: 10 a0 00 20 st32 r1,r0
68: 14 30 00 00 br 68 <finish+0x10>,#al
0000006c <check>:
6c: 0c 40 00 42 xor r2,r2
70: 0c 40 00 63 xor r3,r3
74: 0d 40 01 00 wl16 r8,0x0
78: 0d 60 01 03 wh16 r8,0x3
7c: 10 40 01 08 ld32 r8,r8
80: 0d 40 16 1c wl16 r16,0xbc
84: 0d 60 02 03 wh16 r16,0x3
88: 10 40 02 10 ld32 r16,r16
8c: 0d 40 2d 38 wl16 r9,0x178
90: 0d 60 01 23 wh16 r9,0x3
94: 10 40 01 29 ld32 r9,r9
98: 08 00 01 10 shl r8,r16
9c: 20 70 03 e2 movepc rret,8
a0: 14 30 ff dc br 10 <compare>,#al
a4: 00 10 00 41 add r2,1
a8: 0d 40 01 04 wl16 r8,0x4
ac: 0d 60 01 03 wh16 r8,0x3
b0: 10 40 01 08 ld32 r8,r8
b4: 0d 40 1a 00 wl16 r16,0xc0
b8: 0d 60 02 03 wh16 r16,0x3
bc: 10 40 02 10 ld32 r16,r16
c0: 0d 40 2d 3c wl16 r9,0x17c
c4: 0d 60 01 23 wh16 r9,0x3
c8: 10 40 01 29 ld32 r9,r9
cc: 08 00 01 10 shl r8,r16
d0: 20 70 03 e2 movepc rret,8
d4: 14 30 ff cf br 10 <compare>,#al
d8: 00 10 00 41 add r2,1
dc: 0d 40 01 08 wl16 r8,0x8
e0: 0d 60 01 03 wh16 r8,0x3
e4: 10 40 01 08 ld32 r8,r8
e8: 0d 40 1a 04 wl16 r16,0xc4
ec: 0d 60 02 03 wh16 r16,0x3
f0: 10 40 02 10 ld32 r16,r16
f4: 0d 40 31 20 wl16 r9,0x180
f8: 0d 60 01 23 wh16 r9,0x3
fc: 10 40 01 29 ld32 r9,r9
100: 08 00 01 10 shl r8,r16
104: 20 70 03 e2 movepc rret,8
108: 14 30 ff c2 br 10 <compare>,#al
10c: 00 10 00 41 add r2,1
110: 0d 40 01 0c wl16 r8,0xc
114: 0d 60 01 03 wh16 r8,0x3
118: 10 40 01 08 ld32 r8,r8
11c: 0d 40 1a 08 wl16 r16,0xc8
120: 0d 60 02 03 wh16 r16,0x3
124: 10 40 02 10 ld32 r16,r16
128: 0d 40 31 24 wl16 r9,0x184
12c: 0d 60 01 23 wh16 r9,0x3
130: 10 40 01 29 ld32 r9,r9
134: 08 00 01 10 shl r8,r16
138: 20 70 03 e2 movepc rret,8
13c: 14 30 ff b5 br 10 <compare>,#al
140: 00 10 00 41 add r2,1
144: 0d 40 01 10 wl16 r8,0x10
148: 0d 60 01 03 wh16 r8,0x3
14c: 10 40 01 08 ld32 r8,r8
150: 0d 40 1a 0c wl16 r16,0xcc
154: 0d 60 02 03 wh16 r16,0x3
158: 10 40 02 10 ld32 r16,r16
15c: 0d 40 31 28 wl16 r9,0x188
160: 0d 60 01 23 wh16 r9,0x3
164: 10 40 01 29 ld32 r9,r9
168: 08 00 01 10 shl r8,r16
16c: 20 70 03 e2 movepc rret,8
170: 14 30 ff a8 br 10 <compare>,#al
174: 00 10 00 41 add r2,1
178: 0d 40 01 14 wl16 r8,0x14
17c: 0d 60 01 03 wh16 r8,0x3
180: 10 40 01 08 ld32 r8,r8
184: 0d 40 1a 10 wl16 r16,0xd0
188: 0d 60 02 03 wh16 r16,0x3
18c: 10 40 02 10 ld32 r16,r16
190: 0d 40 31 2c wl16 r9,0x18c
194: 0d 60 01 23 wh16 r9,0x3
198: 10 40 01 29 ld32 r9,r9
19c: 08 00 01 10 shl r8,r16
1a0: 20 70 03 e2 movepc rret,8
1a4: 14 30 ff 9b br 10 <compare>,#al
1a8: 00 10 00 41 add r2,1
1ac: 0d 40 01 18 wl16 r8,0x18
1b0: 0d 60 01 03 wh16 r8,0x3
1b4: 10 40 01 08 ld32 r8,r8
1b8: 0d 40 1a 14 wl16 r16,0xd4
1bc: 0d 60 02 03 wh16 r16,0x3
1c0: 10 40 02 10 ld32 r16,r16
1c4: 0d 40 31 30 wl16 r9,0x190
1c8: 0d 60 01 23 wh16 r9,0x3
1cc: 10 40 01 29 ld32 r9,r9
1d0: 08 00 01 10 shl r8,r16
1d4: 20 70 03 e2 movepc rret,8
1d8: 14 30 ff 8e br 10 <compare>,#al
1dc: 00 10 00 41 add r2,1
1e0: 0d 40 01 1c wl16 r8,0x1c
1e4: 0d 60 01 03 wh16 r8,0x3
1e8: 10 40 01 08 ld32 r8,r8
1ec: 0d 40 1a 18 wl16 r16,0xd8
1f0: 0d 60 02 03 wh16 r16,0x3
1f4: 10 40 02 10 ld32 r16,r16
1f8: 0d 40 31 34 wl16 r9,0x194
1fc: 0d 60 01 23 wh16 r9,0x3
200: 10 40 01 29 ld32 r9,r9
204: 08 00 01 10 shl r8,r16
208: 20 70 03 e2 movepc rret,8
20c: 14 30 ff 81 br 10 <compare>,#al
210: 00 10 00 41 add r2,1
214: 0d 40 05 00 wl16 r8,0x20
218: 0d 60 01 03 wh16 r8,0x3
21c: 10 40 01 08 ld32 r8,r8
220: 0d 40 1a 1c wl16 r16,0xdc
224: 0d 60 02 03 wh16 r16,0x3
228: 10 40 02 10 ld32 r16,r16
22c: 0d 40 31 38 wl16 r9,0x198
230: 0d 60 01 23 wh16 r9,0x3
234: 10 40 01 29 ld32 r9,r9
238: 08 00 01 10 shl r8,r16
23c: 20 70 03 e2 movepc rret,8
240: 14 30 ff 74 br 10 <compare>,#al
244: 00 10 00 41 add r2,1
248: 0d 40 05 04 wl16 r8,0x24
24c: 0d 60 01 03 wh16 r8,0x3
250: 10 40 01 08 ld32 r8,r8
254: 0d 40 1e 00 wl16 r16,0xe0
258: 0d 60 02 03 wh16 r16,0x3
25c: 10 40 02 10 ld32 r16,r16
260: 0d 40 31 3c wl16 r9,0x19c
264: 0d 60 01 23 wh16 r9,0x3
268: 10 40 01 29 ld32 r9,r9
26c: 08 00 01 10 shl r8,r16
270: 20 70 03 e2 movepc rret,8
274: 14 30 ff 67 br 10 <compare>,#al
278: 00 10 00 41 add r2,1
27c: 0d 40 05 08 wl16 r8,0x28
280: 0d 60 01 03 wh16 r8,0x3
284: 10 40 01 08 ld32 r8,r8
288: 0d 40 1e 04 wl16 r16,0xe4
28c: 0d 60 02 03 wh16 r16,0x3
290: 10 40 02 10 ld32 r16,r16
294: 0d 40 35 20 wl16 r9,0x1a0
298: 0d 60 01 23 wh16 r9,0x3
29c: 10 40 01 29 ld32 r9,r9
2a0: 08 00 01 10 shl r8,r16
2a4: 20 70 03 e2 movepc rret,8
2a8: 14 30 ff 5a br 10 <compare>,#al
2ac: 00 10 00 41 add r2,1
2b0: 0d 40 05 0c wl16 r8,0x2c
2b4: 0d 60 01 03 wh16 r8,0x3
2b8: 10 40 01 08 ld32 r8,r8
2bc: 0d 40 1e 08 wl16 r16,0xe8
2c0: 0d 60 02 03 wh16 r16,0x3
2c4: 10 40 02 10 ld32 r16,r16
2c8: 0d 40 35 24 wl16 r9,0x1a4
2cc: 0d 60 01 23 wh16 r9,0x3
2d0: 10 40 01 29 ld32 r9,r9
2d4: 08 00 01 10 shl r8,r16
2d8: 20 70 03 e2 movepc rret,8
2dc: 14 30 ff 4d br 10 <compare>,#al
2e0: 00 10 00 41 add r2,1
2e4: 0d 40 05 10 wl16 r8,0x30
2e8: 0d 60 01 03 wh16 r8,0x3
2ec: 10 40 01 08 ld32 r8,r8
2f0: 0d 40 1e 0c wl16 r16,0xec
2f4: 0d 60 02 03 wh16 r16,0x3
2f8: 10 40 02 10 ld32 r16,r16
2fc: 0d 40 35 28 wl16 r9,0x1a8
300: 0d 60 01 23 wh16 r9,0x3
304: 10 40 01 29 ld32 r9,r9
308: 08 00 01 10 shl r8,r16
30c: 20 70 03 e2 movepc rret,8
310: 14 30 ff 40 br 10 <compare>,#al
314: 00 10 00 41 add r2,1
318: 0d 40 05 14 wl16 r8,0x34
31c: 0d 60 01 03 wh16 r8,0x3
320: 10 40 01 08 ld32 r8,r8
324: 0d 40 1e 10 wl16 r16,0xf0
328: 0d 60 02 03 wh16 r16,0x3
32c: 10 40 02 10 ld32 r16,r16
330: 0d 40 35 2c wl16 r9,0x1ac
334: 0d 60 01 23 wh16 r9,0x3
338: 10 40 01 29 ld32 r9,r9
33c: 08 00 01 10 shl r8,r16
340: 20 70 03 e2 movepc rret,8
344: 14 30 ff 33 br 10 <compare>,#al
348: 00 10 00 41 add r2,1
34c: 0d 40 05 18 wl16 r8,0x38
350: 0d 60 01 03 wh16 r8,0x3
354: 10 40 01 08 ld32 r8,r8
358: 0d 40 1e 14 wl16 r16,0xf4
35c: 0d 60 02 03 wh16 r16,0x3
360: 10 40 02 10 ld32 r16,r16
364: 0d 40 35 30 wl16 r9,0x1b0
368: 0d 60 01 23 wh16 r9,0x3
36c: 10 40 01 29 ld32 r9,r9
370: 08 00 01 10 shl r8,r16
374: 20 70 03 e2 movepc rret,8
378: 14 30 ff 26 br 10 <compare>,#al
37c: 00 10 00 41 add r2,1
380: 0d 40 05 1c wl16 r8,0x3c
384: 0d 60 01 03 wh16 r8,0x3
388: 10 40 01 08 ld32 r8,r8
38c: 0d 40 1e 18 wl16 r16,0xf8
390: 0d 60 02 03 wh16 r16,0x3
394: 10 40 02 10 ld32 r16,r16
398: 0d 40 35 34 wl16 r9,0x1b4
39c: 0d 60 01 23 wh16 r9,0x3
3a0: 10 40 01 29 ld32 r9,r9
3a4: 08 00 01 10 shl r8,r16
3a8: 20 70 03 e2 movepc rret,8
3ac: 14 30 ff 19 br 10 <compare>,#al
3b0: 00 10 00 41 add r2,1
3b4: 0d 40 09 00 wl16 r8,0x40
3b8: 0d 60 01 03 wh16 r8,0x3
3bc: 10 40 01 08 ld32 r8,r8
3c0: 0d 40 1e 1c wl16 r16,0xfc
3c4: 0d 60 02 03 wh16 r16,0x3
3c8: 10 40 02 10 ld32 r16,r16
3cc: 0d 40 35 38 wl16 r9,0x1b8
3d0: 0d 60 01 23 wh16 r9,0x3
3d4: 10 40 01 29 ld32 r9,r9
3d8: 08 00 01 10 shl r8,r16
3dc: 20 70 03 e2 movepc rret,8
3e0: 14 30 ff 0c br 10 <compare>,#al
3e4: 00 10 00 41 add r2,1
3e8: 0d 40 09 04 wl16 r8,0x44
3ec: 0d 60 01 03 wh16 r8,0x3
3f0: 10 40 01 08 ld32 r8,r8
3f4: 0d 40 22 00 wl16 r16,0x100
3f8: 0d 60 02 03 wh16 r16,0x3
3fc: 10 40 02 10 ld32 r16,r16
400: 0d 40 35 3c wl16 r9,0x1bc
404: 0d 60 01 23 wh16 r9,0x3
408: 10 40 01 29 ld32 r9,r9
40c: 08 00 01 10 shl r8,r16
410: 20 70 03 e2 movepc rret,8
414: 14 30 fe ff br 10 <compare>,#al
418: 00 10 00 41 add r2,1
41c: 0d 40 09 08 wl16 r8,0x48
420: 0d 60 01 03 wh16 r8,0x3
424: 10 40 01 08 ld32 r8,r8
428: 0d 40 22 04 wl16 r16,0x104
42c: 0d 60 02 03 wh16 r16,0x3
430: 10 40 02 10 ld32 r16,r16
434: 0d 40 39 20 wl16 r9,0x1c0
438: 0d 60 01 23 wh16 r9,0x3
43c: 10 40 01 29 ld32 r9,r9
440: 08 00 01 10 shl r8,r16
444: 20 70 03 e2 movepc rret,8
448: 14 30 fe f2 br 10 <compare>,#al
44c: 00 10 00 41 add r2,1
450: 0d 40 09 0c wl16 r8,0x4c
454: 0d 60 01 03 wh16 r8,0x3
458: 10 40 01 08 ld32 r8,r8
45c: 0d 40 22 08 wl16 r16,0x108
460: 0d 60 02 03 wh16 r16,0x3
464: 10 40 02 10 ld32 r16,r16
468: 0d 40 39 24 wl16 r9,0x1c4
46c: 0d 60 01 23 wh16 r9,0x3
470: 10 40 01 29 ld32 r9,r9
474: 08 00 01 10 shl r8,r16
478: 20 70 03 e2 movepc rret,8
47c: 14 30 fe e5 br 10 <compare>,#al
480: 00 10 00 41 add r2,1
484: 0d 40 09 10 wl16 r8,0x50
488: 0d 60 01 03 wh16 r8,0x3
48c: 10 40 01 08 ld32 r8,r8
490: 0d 40 22 0c wl16 r16,0x10c
494: 0d 60 02 03 wh16 r16,0x3
498: 10 40 02 10 ld32 r16,r16
49c: 0d 40 39 28 wl16 r9,0x1c8
4a0: 0d 60 01 23 wh16 r9,0x3
4a4: 10 40 01 29 ld32 r9,r9
4a8: 08 00 01 10 shl r8,r16
4ac: 20 70 03 e2 movepc rret,8
4b0: 14 30 fe d8 br 10 <compare>,#al
4b4: 00 10 00 41 add r2,1
4b8: 0d 40 09 14 wl16 r8,0x54
4bc: 0d 60 01 03 wh16 r8,0x3
4c0: 10 40 01 08 ld32 r8,r8
4c4: 0d 40 22 10 wl16 r16,0x110
4c8: 0d 60 02 03 wh16 r16,0x3
4cc: 10 40 02 10 ld32 r16,r16
4d0: 0d 40 39 2c wl16 r9,0x1cc
4d4: 0d 60 01 23 wh16 r9,0x3
4d8: 10 40 01 29 ld32 r9,r9
4dc: 08 00 01 10 shl r8,r16
4e0: 20 70 03 e2 movepc rret,8
4e4: 14 30 fe cb br 10 <compare>,#al
4e8: 00 10 00 41 add r2,1
4ec: 0d 40 09 18 wl16 r8,0x58
4f0: 0d 60 01 03 wh16 r8,0x3
4f4: 10 40 01 08 ld32 r8,r8
4f8: 0d 40 22 14 wl16 r16,0x114
4fc: 0d 60 02 03 wh16 r16,0x3
500: 10 40 02 10 ld32 r16,r16
504: 0d 40 39 30 wl16 r9,0x1d0
508: 0d 60 01 23 wh16 r9,0x3
50c: 10 40 01 29 ld32 r9,r9
510: 08 00 01 10 shl r8,r16
514: 20 70 03 e2 movepc rret,8
518: 14 30 fe be br 10 <compare>,#al
51c: 00 10 00 41 add r2,1
520: 0d 40 09 1c wl16 r8,0x5c
524: 0d 60 01 03 wh16 r8,0x3
528: 10 40 01 08 ld32 r8,r8
52c: 0d 40 22 18 wl16 r16,0x118
530: 0d 60 02 03 wh16 r16,0x3
534: 10 40 02 10 ld32 r16,r16
538: 0d 40 39 34 wl16 r9,0x1d4
53c: 0d 60 01 23 wh16 r9,0x3
540: 10 40 01 29 ld32 r9,r9
544: 08 00 01 10 shl r8,r16
548: 20 70 03 e2 movepc rret,8
54c: 14 30 fe b1 br 10 <compare>,#al
550: 00 10 00 41 add r2,1
554: 0d 40 0d 00 wl16 r8,0x60
558: 0d 60 01 03 wh16 r8,0x3
55c: 10 40 01 08 ld32 r8,r8
560: 0d 40 22 1c wl16 r16,0x11c
564: 0d 60 02 03 wh16 r16,0x3
568: 10 40 02 10 ld32 r16,r16
56c: 0d 40 39 38 wl16 r9,0x1d8
570: 0d 60 01 23 wh16 r9,0x3
574: 10 40 01 29 ld32 r9,r9
578: 08 00 01 10 shl r8,r16
57c: 20 70 03 e2 movepc rret,8
580: 14 30 fe a4 br 10 <compare>,#al
584: 00 10 00 41 add r2,1
588: 0d 40 0d 04 wl16 r8,0x64
58c: 0d 60 01 03 wh16 r8,0x3
590: 10 40 01 08 ld32 r8,r8
594: 0d 40 26 00 wl16 r16,0x120
598: 0d 60 02 03 wh16 r16,0x3
59c: 10 40 02 10 ld32 r16,r16
5a0: 0d 40 39 3c wl16 r9,0x1dc
5a4: 0d 60 01 23 wh16 r9,0x3
5a8: 10 40 01 29 ld32 r9,r9
5ac: 08 00 01 10 shl r8,r16
5b0: 20 70 03 e2 movepc rret,8
5b4: 14 30 fe 97 br 10 <compare>,#al
5b8: 00 10 00 41 add r2,1
5bc: 0d 40 0d 08 wl16 r8,0x68
5c0: 0d 60 01 03 wh16 r8,0x3
5c4: 10 40 01 08 ld32 r8,r8
5c8: 0d 40 26 04 wl16 r16,0x124
5cc: 0d 60 02 03 wh16 r16,0x3
5d0: 10 40 02 10 ld32 r16,r16
5d4: 0d 40 3d 20 wl16 r9,0x1e0
5d8: 0d 60 01 23 wh16 r9,0x3
5dc: 10 40 01 29 ld32 r9,r9
5e0: 08 00 01 10 shl r8,r16
5e4: 20 70 03 e2 movepc rret,8
5e8: 14 30 fe 8a br 10 <compare>,#al
5ec: 00 10 00 41 add r2,1
5f0: 0d 40 0d 0c wl16 r8,0x6c
5f4: 0d 60 01 03 wh16 r8,0x3
5f8: 10 40 01 08 ld32 r8,r8
5fc: 0d 40 26 08 wl16 r16,0x128
600: 0d 60 02 03 wh16 r16,0x3
604: 10 40 02 10 ld32 r16,r16
608: 0d 40 3d 24 wl16 r9,0x1e4
60c: 0d 60 01 23 wh16 r9,0x3
610: 10 40 01 29 ld32 r9,r9
614: 08 00 01 10 shl r8,r16
618: 20 70 03 e2 movepc rret,8
61c: 14 30 fe 7d br 10 <compare>,#al
620: 00 10 00 41 add r2,1
624: 0d 40 0d 10 wl16 r8,0x70
628: 0d 60 01 03 wh16 r8,0x3
62c: 10 40 01 08 ld32 r8,r8
630: 0d 40 26 0c wl16 r16,0x12c
634: 0d 60 02 03 wh16 r16,0x3
638: 10 40 02 10 ld32 r16,r16
63c: 0d 40 3d 28 wl16 r9,0x1e8
640: 0d 60 01 23 wh16 r9,0x3
644: 10 40 01 29 ld32 r9,r9
648: 08 00 01 10 shl r8,r16
64c: 20 70 03 e2 movepc rret,8
650: 14 30 fe 70 br 10 <compare>,#al
654: 00 10 00 41 add r2,1
658: 0d 40 0d 14 wl16 r8,0x74
65c: 0d 60 01 03 wh16 r8,0x3
660: 10 40 01 08 ld32 r8,r8
664: 0d 40 26 10 wl16 r16,0x130
668: 0d 60 02 03 wh16 r16,0x3
66c: 10 40 02 10 ld32 r16,r16
670: 0d 40 3d 2c wl16 r9,0x1ec
674: 0d 60 01 23 wh16 r9,0x3
678: 10 40 01 29 ld32 r9,r9
67c: 08 00 01 10 shl r8,r16
680: 20 70 03 e2 movepc rret,8
684: 14 30 fe 63 br 10 <compare>,#al
688: 00 10 00 41 add r2,1
68c: 0d 40 0d 18 wl16 r8,0x78
690: 0d 60 01 03 wh16 r8,0x3
694: 10 40 01 08 ld32 r8,r8
698: 0d 40 26 14 wl16 r16,0x134
69c: 0d 60 02 03 wh16 r16,0x3
6a0: 10 40 02 10 ld32 r16,r16
6a4: 0d 40 3d 30 wl16 r9,0x1f0
6a8: 0d 60 01 23 wh16 r9,0x3
6ac: 10 40 01 29 ld32 r9,r9
6b0: 08 00 01 10 shl r8,r16
6b4: 20 70 03 e2 movepc rret,8
6b8: 14 30 fe 56 br 10 <compare>,#al
6bc: 00 10 00 41 add r2,1
6c0: 0d 40 0d 1c wl16 r8,0x7c
6c4: 0d 60 01 03 wh16 r8,0x3
6c8: 10 40 01 08 ld32 r8,r8
6cc: 0d 40 26 18 wl16 r16,0x138
6d0: 0d 60 02 03 wh16 r16,0x3
6d4: 10 40 02 10 ld32 r16,r16
6d8: 0d 40 3d 34 wl16 r9,0x1f4
6dc: 0d 60 01 23 wh16 r9,0x3
6e0: 10 40 01 29 ld32 r9,r9
6e4: 08 00 01 10 shl r8,r16
6e8: 20 70 03 e2 movepc rret,8
6ec: 14 30 fe 49 br 10 <compare>,#al
6f0: 00 10 00 41 add r2,1
6f4: 0d 40 11 00 wl16 r8,0x80
6f8: 0d 60 01 03 wh16 r8,0x3
6fc: 10 40 01 08 ld32 r8,r8
700: 0d 40 26 1c wl16 r16,0x13c
704: 0d 60 02 03 wh16 r16,0x3
708: 10 40 02 10 ld32 r16,r16
70c: 0d 40 3d 38 wl16 r9,0x1f8
710: 0d 60 01 23 wh16 r9,0x3
714: 10 40 01 29 ld32 r9,r9
718: 08 00 01 10 shl r8,r16
71c: 20 70 03 e2 movepc rret,8
720: 14 30 fe 3c br 10 <compare>,#al
724: 00 10 00 41 add r2,1
728: 0d 40 11 04 wl16 r8,0x84
72c: 0d 60 01 03 wh16 r8,0x3
730: 10 40 01 08 ld32 r8,r8
734: 0d 40 2a 00 wl16 r16,0x140
738: 0d 60 02 03 wh16 r16,0x3
73c: 10 40 02 10 ld32 r16,r16
740: 0d 40 3d 3c wl16 r9,0x1fc
744: 0d 60 01 23 wh16 r9,0x3
748: 10 40 01 29 ld32 r9,r9
74c: 08 00 01 10 shl r8,r16
750: 20 70 03 e2 movepc rret,8
754: 14 30 fe 2f br 10 <compare>,#al
758: 00 10 00 41 add r2,1
75c: 0d 40 11 08 wl16 r8,0x88
760: 0d 60 01 03 wh16 r8,0x3
764: 10 40 01 08 ld32 r8,r8
768: 0d 40 2a 04 wl16 r16,0x144
76c: 0d 60 02 03 wh16 r16,0x3
770: 10 40 02 10 ld32 r16,r16
774: 0d 40 41 20 wl16 r9,0x200
778: 0d 60 01 23 wh16 r9,0x3
77c: 10 40 01 29 ld32 r9,r9
780: 08 00 01 10 shl r8,r16
784: 20 70 03 e2 movepc rret,8
788: 14 30 fe 22 br 10 <compare>,#al
78c: 00 10 00 41 add r2,1
790: 0d 40 11 0c wl16 r8,0x8c
794: 0d 60 01 03 wh16 r8,0x3
798: 10 40 01 08 ld32 r8,r8
79c: 0d 40 2a 08 wl16 r16,0x148
7a0: 0d 60 02 03 wh16 r16,0x3
7a4: 10 40 02 10 ld32 r16,r16
7a8: 0d 40 41 24 wl16 r9,0x204
7ac: 0d 60 01 23 wh16 r9,0x3
7b0: 10 40 01 29 ld32 r9,r9
7b4: 08 00 01 10 shl r8,r16
7b8: 20 70 03 e2 movepc rret,8
7bc: 14 30 fe 15 br 10 <compare>,#al
7c0: 00 10 00 41 add r2,1
7c4: 0d 40 11 10 wl16 r8,0x90
7c8: 0d 60 01 03 wh16 r8,0x3
7cc: 10 40 01 08 ld32 r8,r8
7d0: 0d 40 2a 0c wl16 r16,0x14c
7d4: 0d 60 02 03 wh16 r16,0x3
7d8: 10 40 02 10 ld32 r16,r16
7dc: 0d 40 41 28 wl16 r9,0x208
7e0: 0d 60 01 23 wh16 r9,0x3
7e4: 10 40 01 29 ld32 r9,r9
7e8: 08 00 01 10 shl r8,r16
7ec: 20 70 03 e2 movepc rret,8
7f0: 14 30 fe 08 br 10 <compare>,#al
7f4: 00 10 00 41 add r2,1
7f8: 0d 40 11 14 wl16 r8,0x94
7fc: 0d 60 01 03 wh16 r8,0x3
800: 10 40 01 08 ld32 r8,r8
804: 0d 40 2a 10 wl16 r16,0x150
808: 0d 60 02 03 wh16 r16,0x3
80c: 10 40 02 10 ld32 r16,r16
810: 0d 40 41 2c wl16 r9,0x20c
814: 0d 60 01 23 wh16 r9,0x3
818: 10 40 01 29 ld32 r9,r9
81c: 08 00 01 10 shl r8,r16
820: 20 70 03 e2 movepc rret,8
824: 14 30 fd fb br 10 <compare>,#al
828: 00 10 00 41 add r2,1
82c: 0d 40 11 18 wl16 r8,0x98
830: 0d 60 01 03 wh16 r8,0x3
834: 10 40 01 08 ld32 r8,r8
838: 0d 40 2a 14 wl16 r16,0x154
83c: 0d 60 02 03 wh16 r16,0x3
840: 10 40 02 10 ld32 r16,r16
844: 0d 40 41 30 wl16 r9,0x210
848: 0d 60 01 23 wh16 r9,0x3
84c: 10 40 01 29 ld32 r9,r9
850: 08 00 01 10 shl r8,r16
854: 20 70 03 e2 movepc rret,8
858: 14 30 fd ee br 10 <compare>,#al
85c: 00 10 00 41 add r2,1
860: 0d 40 11 1c wl16 r8,0x9c
864: 0d 60 01 03 wh16 r8,0x3
868: 10 40 01 08 ld32 r8,r8
86c: 0d 40 2a 18 wl16 r16,0x158
870: 0d 60 02 03 wh16 r16,0x3
874: 10 40 02 10 ld32 r16,r16
878: 0d 40 41 34 wl16 r9,0x214
87c: 0d 60 01 23 wh16 r9,0x3
880: 10 40 01 29 ld32 r9,r9
884: 08 00 01 10 shl r8,r16
888: 20 70 03 e2 movepc rret,8
88c: 14 30 fd e1 br 10 <compare>,#al
890: 00 10 00 41 add r2,1
894: 0d 40 15 00 wl16 r8,0xa0
898: 0d 60 01 03 wh16 r8,0x3
89c: 10 40 01 08 ld32 r8,r8
8a0: 0d 40 2a 1c wl16 r16,0x15c
8a4: 0d 60 02 03 wh16 r16,0x3
8a8: 10 40 02 10 ld32 r16,r16
8ac: 0d 40 41 38 wl16 r9,0x218
8b0: 0d 60 01 23 wh16 r9,0x3
8b4: 10 40 01 29 ld32 r9,r9
8b8: 08 00 01 10 shl r8,r16
8bc: 20 70 03 e2 movepc rret,8
8c0: 14 30 fd d4 br 10 <compare>,#al
8c4: 00 10 00 41 add r2,1
8c8: 0d 40 15 04 wl16 r8,0xa4
8cc: 0d 60 01 03 wh16 r8,0x3
8d0: 10 40 01 08 ld32 r8,r8
8d4: 0d 40 2e 00 wl16 r16,0x160
8d8: 0d 60 02 03 wh16 r16,0x3
8dc: 10 40 02 10 ld32 r16,r16
8e0: 0d 40 41 3c wl16 r9,0x21c
8e4: 0d 60 01 23 wh16 r9,0x3
8e8: 10 40 01 29 ld32 r9,r9
8ec: 08 00 01 10 shl r8,r16
8f0: 20 70 03 e2 movepc rret,8
8f4: 14 30 fd c7 br 10 <compare>,#al
8f8: 00 10 00 41 add r2,1
8fc: 0d 40 15 08 wl16 r8,0xa8
900: 0d 60 01 03 wh16 r8,0x3
904: 10 40 01 08 ld32 r8,r8
908: 0d 40 2e 04 wl16 r16,0x164
90c: 0d 60 02 03 wh16 r16,0x3
910: 10 40 02 10 ld32 r16,r16
914: 0d 40 45 20 wl16 r9,0x220
918: 0d 60 01 23 wh16 r9,0x3
91c: 10 40 01 29 ld32 r9,r9
920: 08 00 01 10 shl r8,r16
924: 20 70 03 e2 movepc rret,8
928: 14 30 fd ba br 10 <compare>,#al
92c: 00 10 00 41 add r2,1
930: 0d 40 15 0c wl16 r8,0xac
934: 0d 60 01 03 wh16 r8,0x3
938: 10 40 01 08 ld32 r8,r8
93c: 0d 40 2e 08 wl16 r16,0x168
940: 0d 60 02 03 wh16 r16,0x3
944: 10 40 02 10 ld32 r16,r16
948: 0d 40 45 24 wl16 r9,0x224
94c: 0d 60 01 23 wh16 r9,0x3
950: 10 40 01 29 ld32 r9,r9
954: 08 00 01 10 shl r8,r16
958: 20 70 03 e2 movepc rret,8
95c: 14 30 fd ad br 10 <compare>,#al
960: 00 10 00 41 add r2,1
964: 0d 40 15 10 wl16 r8,0xb0
968: 0d 60 01 03 wh16 r8,0x3
96c: 10 40 01 08 ld32 r8,r8
970: 0d 40 2e 0c wl16 r16,0x16c
974: 0d 60 02 03 wh16 r16,0x3
978: 10 40 02 10 ld32 r16,r16
97c: 0d 40 45 28 wl16 r9,0x228
980: 0d 60 01 23 wh16 r9,0x3
984: 10 40 01 29 ld32 r9,r9
988: 08 00 01 10 shl r8,r16
98c: 20 70 03 e2 movepc rret,8
990: 14 30 fd a0 br 10 <compare>,#al
994: 00 10 00 41 add r2,1
998: 0d 40 15 14 wl16 r8,0xb4
99c: 0d 60 01 03 wh16 r8,0x3
9a0: 10 40 01 08 ld32 r8,r8
9a4: 0d 40 2e 10 wl16 r16,0x170
9a8: 0d 60 02 03 wh16 r16,0x3
9ac: 10 40 02 10 ld32 r16,r16
9b0: 0d 40 45 2c wl16 r9,0x22c
9b4: 0d 60 01 23 wh16 r9,0x3
9b8: 10 40 01 29 ld32 r9,r9
9bc: 08 00 01 10 shl r8,r16
9c0: 20 70 03 e2 movepc rret,8
9c4: 14 30 fd 93 br 10 <compare>,#al
9c8: 00 10 00 41 add r2,1
9cc: 0d 40 15 18 wl16 r8,0xb8
9d0: 0d 60 01 03 wh16 r8,0x3
9d4: 10 40 01 08 ld32 r8,r8
9d8: 0d 40 2e 14 wl16 r16,0x174
9dc: 0d 60 02 03 wh16 r16,0x3
9e0: 10 40 02 10 ld32 r16,r16
9e4: 0d 40 45 30 wl16 r9,0x230
9e8: 0d 60 01 23 wh16 r9,0x3
9ec: 10 40 01 29 ld32 r9,r9
9f0: 08 00 01 10 shl r8,r16
9f4: 20 70 03 e2 movepc rret,8
9f8: 14 30 fd 86 br 10 <compare>,#al
9fc: 00 10 00 41 add r2,1
a00: 0c 40 00 42 xor r2,r2
a04: 00 10 00 61 add r3,1
a08: 0d 40 45 14 wl16 r8,0x234
a0c: 0d 60 01 03 wh16 r8,0x3
a10: 10 40 01 08 ld32 r8,r8
a14: 0d 40 5d 30 wl16 r9,0x2f0
a18: 0d 60 01 23 wh16 r9,0x3
a1c: 10 40 01 29 ld32 r9,r9
a20: 08 10 01 01 shl r8,0x1
a24: 20 70 03 e2 movepc rret,8
a28: 14 30 fd 7a br 10 <compare>,#al
a2c: 00 10 00 41 add r2,1
a30: 0d 40 45 18 wl16 r8,0x238
a34: 0d 60 01 03 wh16 r8,0x3
a38: 10 40 01 08 ld32 r8,r8
a3c: 0d 40 5d 34 wl16 r9,0x2f4
a40: 0d 60 01 23 wh16 r9,0x3
a44: 10 40 01 29 ld32 r9,r9
a48: 08 10 01 02 shl r8,0x2
a4c: 20 70 03 e2 movepc rret,8
a50: 14 30 fd 70 br 10 <compare>,#al
a54: 00 10 00 41 add r2,1
a58: 0d 40 45 1c wl16 r8,0x23c
a5c: 0d 60 01 03 wh16 r8,0x3
a60: 10 40 01 08 ld32 r8,r8
a64: 0d 40 5d 38 wl16 r9,0x2f8
a68: 0d 60 01 23 wh16 r9,0x3
a6c: 10 40 01 29 ld32 r9,r9
a70: 08 10 01 04 shl r8,0x4
a74: 20 70 03 e2 movepc rret,8
a78: 14 30 fd 66 br 10 <compare>,#al
a7c: 00 10 00 41 add r2,1
a80: 0d 40 49 00 wl16 r8,0x240
a84: 0d 60 01 03 wh16 r8,0x3
a88: 10 40 01 08 ld32 r8,r8
a8c: 0d 40 5d 3c wl16 r9,0x2fc
a90: 0d 60 01 23 wh16 r9,0x3
a94: 10 40 01 29 ld32 r9,r9
a98: 08 10 01 08 shl r8,0x8
a9c: 20 70 03 e2 movepc rret,8
aa0: 14 30 fd 5c br 10 <compare>,#al
aa4: 00 10 00 41 add r2,1
aa8: 0d 40 49 04 wl16 r8,0x244
aac: 0d 60 01 03 wh16 r8,0x3
ab0: 10 40 01 08 ld32 r8,r8
ab4: 0d 40 61 20 wl16 r9,0x300
ab8: 0d 60 01 23 wh16 r9,0x3
abc: 10 40 01 29 ld32 r9,r9
ac0: 08 10 01 10 shl r8,0x10
ac4: 20 70 03 e2 movepc rret,8
ac8: 14 30 fd 52 br 10 <compare>,#al
acc: 00 10 00 41 add r2,1
ad0: 0d 40 49 08 wl16 r8,0x248
ad4: 0d 60 01 03 wh16 r8,0x3
ad8: 10 40 01 08 ld32 r8,r8
adc: 0d 40 61 24 wl16 r9,0x304
ae0: 0d 60 01 23 wh16 r9,0x3
ae4: 10 40 01 29 ld32 r9,r9
ae8: 08 10 05 00 shl r8,0x20
aec: 20 70 03 e2 movepc rret,8
af0: 14 30 fd 48 br 10 <compare>,#al
af4: 00 10 00 41 add r2,1
af8: 0d 40 49 0c wl16 r8,0x24c
afc: 0d 60 01 03 wh16 r8,0x3
b00: 10 40 01 08 ld32 r8,r8
b04: 0d 40 61 28 wl16 r9,0x308
b08: 0d 60 01 23 wh16 r9,0x3
b0c: 10 40 01 29 ld32 r9,r9
b10: 08 10 01 01 shl r8,0x1
b14: 20 70 03 e2 movepc rret,8
b18: 14 30 fd 3e br 10 <compare>,#al
b1c: 00 10 00 41 add r2,1
b20: 0d 40 49 10 wl16 r8,0x250
b24: 0d 60 01 03 wh16 r8,0x3
b28: 10 40 01 08 ld32 r8,r8
b2c: 0d 40 61 2c wl16 r9,0x30c
b30: 0d 60 01 23 wh16 r9,0x3
b34: 10 40 01 29 ld32 r9,r9
b38: 08 10 01 02 shl r8,0x2
b3c: 20 70 03 e2 movepc rret,8
b40: 14 30 fd 34 br 10 <compare>,#al
b44: 00 10 00 41 add r2,1
b48: 0d 40 49 14 wl16 r8,0x254
b4c: 0d 60 01 03 wh16 r8,0x3
b50: 10 40 01 08 ld32 r8,r8
b54: 0d 40 61 30 wl16 r9,0x310
b58: 0d 60 01 23 wh16 r9,0x3
b5c: 10 40 01 29 ld32 r9,r9
b60: 08 10 01 04 shl r8,0x4
b64: 20 70 03 e2 movepc rret,8
b68: 14 30 fd 2a br 10 <compare>,#al
b6c: 00 10 00 41 add r2,1
b70: 0d 40 49 18 wl16 r8,0x258
b74: 0d 60 01 03 wh16 r8,0x3
b78: 10 40 01 08 ld32 r8,r8
b7c: 0d 40 61 34 wl16 r9,0x314
b80: 0d 60 01 23 wh16 r9,0x3
b84: 10 40 01 29 ld32 r9,r9
b88: 08 10 01 08 shl r8,0x8
b8c: 20 70 03 e2 movepc rret,8
b90: 14 30 fd 20 br 10 <compare>,#al
b94: 00 10 00 41 add r2,1
b98: 0d 40 49 1c wl16 r8,0x25c
b9c: 0d 60 01 03 wh16 r8,0x3
ba0: 10 40 01 08 ld32 r8,r8
ba4: 0d 40 61 38 wl16 r9,0x318
ba8: 0d 60 01 23 wh16 r9,0x3
bac: 10 40 01 29 ld32 r9,r9
bb0: 08 10 01 10 shl r8,0x10
bb4: 20 70 03 e2 movepc rret,8
bb8: 14 30 fd 16 br 10 <compare>,#al
bbc: 00 10 00 41 add r2,1
bc0: 0d 40 4d 00 wl16 r8,0x260
bc4: 0d 60 01 03 wh16 r8,0x3
bc8: 10 40 01 08 ld32 r8,r8
bcc: 0d 40 61 3c wl16 r9,0x31c
bd0: 0d 60 01 23 wh16 r9,0x3
bd4: 10 40 01 29 ld32 r9,r9
bd8: 08 10 05 00 shl r8,0x20
bdc: 20 70 03 e2 movepc rret,8
be0: 14 30 fd 0c br 10 <compare>,#al
be4: 00 10 00 41 add r2,1
be8: 0d 40 4d 04 wl16 r8,0x264
bec: 0d 60 01 03 wh16 r8,0x3
bf0: 10 40 01 08 ld32 r8,r8
bf4: 0d 40 65 20 wl16 r9,0x320
bf8: 0d 60 01 23 wh16 r9,0x3
bfc: 10 40 01 29 ld32 r9,r9
c00: 08 10 01 01 shl r8,0x1
c04: 20 70 03 e2 movepc rret,8
c08: 14 30 fd 02 br 10 <compare>,#al
c0c: 00 10 00 41 add r2,1
c10: 0d 40 4d 08 wl16 r8,0x268
c14: 0d 60 01 03 wh16 r8,0x3
c18: 10 40 01 08 ld32 r8,r8
c1c: 0d 40 65 24 wl16 r9,0x324
c20: 0d 60 01 23 wh16 r9,0x3
c24: 10 40 01 29 ld32 r9,r9
c28: 08 10 01 02 shl r8,0x2
c2c: 20 70 03 e2 movepc rret,8
c30: 14 30 fc f8 br 10 <compare>,#al
c34: 00 10 00 41 add r2,1
c38: 0d 40 4d 0c wl16 r8,0x26c
c3c: 0d 60 01 03 wh16 r8,0x3
c40: 10 40 01 08 ld32 r8,r8
c44: 0d 40 65 28 wl16 r9,0x328
c48: 0d 60 01 23 wh16 r9,0x3
c4c: 10 40 01 29 ld32 r9,r9
c50: 08 10 01 04 shl r8,0x4
c54: 20 70 03 e2 movepc rret,8
c58: 14 30 fc ee br 10 <compare>,#al
c5c: 00 10 00 41 add r2,1
c60: 0d 40 4d 10 wl16 r8,0x270
c64: 0d 60 01 03 wh16 r8,0x3
c68: 10 40 01 08 ld32 r8,r8
c6c: 0d 40 65 2c wl16 r9,0x32c
c70: 0d 60 01 23 wh16 r9,0x3
c74: 10 40 01 29 ld32 r9,r9
c78: 08 10 01 08 shl r8,0x8
c7c: 20 70 03 e2 movepc rret,8
c80: 14 30 fc e4 br 10 <compare>,#al
c84: 00 10 00 41 add r2,1
c88: 0d 40 4d 14 wl16 r8,0x274
c8c: 0d 60 01 03 wh16 r8,0x3
c90: 10 40 01 08 ld32 r8,r8
c94: 0d 40 65 30 wl16 r9,0x330
c98: 0d 60 01 23 wh16 r9,0x3
c9c: 10 40 01 29 ld32 r9,r9
ca0: 08 10 01 10 shl r8,0x10
ca4: 20 70 03 e2 movepc rret,8
ca8: 14 30 fc da br 10 <compare>,#al
cac: 00 10 00 41 add r2,1
cb0: 0d 40 4d 18 wl16 r8,0x278
cb4: 0d 60 01 03 wh16 r8,0x3
cb8: 10 40 01 08 ld32 r8,r8
cbc: 0d 40 65 34 wl16 r9,0x334
cc0: 0d 60 01 23 wh16 r9,0x3
cc4: 10 40 01 29 ld32 r9,r9
cc8: 08 10 05 00 shl r8,0x20
ccc: 20 70 03 e2 movepc rret,8
cd0: 14 30 fc d0 br 10 <compare>,#al
cd4: 00 10 00 41 add r2,1
cd8: 0d 40 4d 1c wl16 r8,0x27c
cdc: 0d 60 01 03 wh16 r8,0x3
ce0: 10 40 01 08 ld32 r8,r8
ce4: 0d 40 65 38 wl16 r9,0x338
ce8: 0d 60 01 23 wh16 r9,0x3
cec: 10 40 01 29 ld32 r9,r9
cf0: 08 10 01 01 shl r8,0x1
cf4: 20 70 03 e2 movepc rret,8
cf8: 14 30 fc c6 br 10 <compare>,#al
cfc: 00 10 00 41 add r2,1
d00: 0d 40 51 00 wl16 r8,0x280
d04: 0d 60 01 03 wh16 r8,0x3
d08: 10 40 01 08 ld32 r8,r8
d0c: 0d 40 65 3c wl16 r9,0x33c
d10: 0d 60 01 23 wh16 r9,0x3
d14: 10 40 01 29 ld32 r9,r9
d18: 08 10 01 02 shl r8,0x2
d1c: 20 70 03 e2 movepc rret,8
d20: 14 30 fc bc br 10 <compare>,#al
d24: 00 10 00 41 add r2,1
d28: 0d 40 51 04 wl16 r8,0x284
d2c: 0d 60 01 03 wh16 r8,0x3
d30: 10 40 01 08 ld32 r8,r8
d34: 0d 40 69 20 wl16 r9,0x340
d38: 0d 60 01 23 wh16 r9,0x3
d3c: 10 40 01 29 ld32 r9,r9
d40: 08 10 01 04 shl r8,0x4
d44: 20 70 03 e2 movepc rret,8
d48: 14 30 fc b2 br 10 <compare>,#al
d4c: 00 10 00 41 add r2,1
d50: 0d 40 51 08 wl16 r8,0x288
d54: 0d 60 01 03 wh16 r8,0x3
d58: 10 40 01 08 ld32 r8,r8
d5c: 0d 40 69 24 wl16 r9,0x344
d60: 0d 60 01 23 wh16 r9,0x3
d64: 10 40 01 29 ld32 r9,r9
d68: 08 10 01 08 shl r8,0x8
d6c: 20 70 03 e2 movepc rret,8
d70: 14 30 fc a8 br 10 <compare>,#al
d74: 00 10 00 41 add r2,1
d78: 0d 40 51 0c wl16 r8,0x28c
d7c: 0d 60 01 03 wh16 r8,0x3
d80: 10 40 01 08 ld32 r8,r8
d84: 0d 40 69 28 wl16 r9,0x348
d88: 0d 60 01 23 wh16 r9,0x3
d8c: 10 40 01 29 ld32 r9,r9
d90: 08 10 01 10 shl r8,0x10
d94: 20 70 03 e2 movepc rret,8
d98: 14 30 fc 9e br 10 <compare>,#al
d9c: 00 10 00 41 add r2,1
da0: 0d 40 51 10 wl16 r8,0x290
da4: 0d 60 01 03 wh16 r8,0x3
da8: 10 40 01 08 ld32 r8,r8
dac: 0d 40 69 2c wl16 r9,0x34c
db0: 0d 60 01 23 wh16 r9,0x3
db4: 10 40 01 29 ld32 r9,r9
db8: 08 10 05 00 shl r8,0x20
dbc: 20 70 03 e2 movepc rret,8
dc0: 14 30 fc 94 br 10 <compare>,#al
dc4: 00 10 00 41 add r2,1
dc8: 0d 40 51 14 wl16 r8,0x294
dcc: 0d 60 01 03 wh16 r8,0x3
dd0: 10 40 01 08 ld32 r8,r8
dd4: 0d 40 69 30 wl16 r9,0x350
dd8: 0d 60 01 23 wh16 r9,0x3
ddc: 10 40 01 29 ld32 r9,r9
de0: 08 10 01 01 shl r8,0x1
de4: 20 70 03 e2 movepc rret,8
de8: 14 30 fc 8a br 10 <compare>,#al
dec: 00 10 00 41 add r2,1
df0: 0d 40 51 18 wl16 r8,0x298
df4: 0d 60 01 03 wh16 r8,0x3
df8: 10 40 01 08 ld32 r8,r8
dfc: 0d 40 69 34 wl16 r9,0x354
e00: 0d 60 01 23 wh16 r9,0x3
e04: 10 40 01 29 ld32 r9,r9
e08: 08 10 01 02 shl r8,0x2
e0c: 20 70 03 e2 movepc rret,8
e10: 14 30 fc 80 br 10 <compare>,#al
e14: 00 10 00 41 add r2,1
e18: 0d 40 51 1c wl16 r8,0x29c
e1c: 0d 60 01 03 wh16 r8,0x3
e20: 10 40 01 08 ld32 r8,r8
e24: 0d 40 69 38 wl16 r9,0x358
e28: 0d 60 01 23 wh16 r9,0x3
e2c: 10 40 01 29 ld32 r9,r9
e30: 08 10 01 04 shl r8,0x4
e34: 20 70 03 e2 movepc rret,8
e38: 14 30 fc 76 br 10 <compare>,#al
e3c: 00 10 00 41 add r2,1
e40: 0d 40 55 00 wl16 r8,0x2a0
e44: 0d 60 01 03 wh16 r8,0x3
e48: 10 40 01 08 ld32 r8,r8
e4c: 0d 40 69 3c wl16 r9,0x35c
e50: 0d 60 01 23 wh16 r9,0x3
e54: 10 40 01 29 ld32 r9,r9
e58: 08 10 01 08 shl r8,0x8
e5c: 20 70 03 e2 movepc rret,8
e60: 14 30 fc 6c br 10 <compare>,#al
e64: 00 10 00 41 add r2,1
e68: 0d 40 55 04 wl16 r8,0x2a4
e6c: 0d 60 01 03 wh16 r8,0x3
e70: 10 40 01 08 ld32 r8,r8
e74: 0d 40 6d 20 wl16 r9,0x360
e78: 0d 60 01 23 wh16 r9,0x3
e7c: 10 40 01 29 ld32 r9,r9
e80: 08 10 01 10 shl r8,0x10
e84: 20 70 03 e2 movepc rret,8
e88: 14 30 fc 62 br 10 <compare>,#al
e8c: 00 10 00 41 add r2,1
e90: 0d 40 55 08 wl16 r8,0x2a8
e94: 0d 60 01 03 wh16 r8,0x3
e98: 10 40 01 08 ld32 r8,r8
e9c: 0d 40 6d 24 wl16 r9,0x364
ea0: 0d 60 01 23 wh16 r9,0x3
ea4: 10 40 01 29 ld32 r9,r9
ea8: 08 10 05 00 shl r8,0x20
eac: 20 70 03 e2 movepc rret,8
eb0: 14 30 fc 58 br 10 <compare>,#al
eb4: 00 10 00 41 add r2,1
eb8: 0d 40 55 0c wl16 r8,0x2ac
ebc: 0d 60 01 03 wh16 r8,0x3
ec0: 10 40 01 08 ld32 r8,r8
ec4: 0d 40 6d 28 wl16 r9,0x368
ec8: 0d 60 01 23 wh16 r9,0x3
ecc: 10 40 01 29 ld32 r9,r9
ed0: 08 10 01 01 shl r8,0x1
ed4: 20 70 03 e2 movepc rret,8
ed8: 14 30 fc 4e br 10 <compare>,#al
edc: 00 10 00 41 add r2,1
ee0: 0d 40 55 10 wl16 r8,0x2b0
ee4: 0d 60 01 03 wh16 r8,0x3
ee8: 10 40 01 08 ld32 r8,r8
eec: 0d 40 6d 2c wl16 r9,0x36c
ef0: 0d 60 01 23 wh16 r9,0x3
ef4: 10 40 01 29 ld32 r9,r9
ef8: 08 10 01 02 shl r8,0x2
efc: 20 70 03 e2 movepc rret,8
f00: 14 30 fc 44 br 10 <compare>,#al
f04: 00 10 00 41 add r2,1
f08: 0d 40 55 14 wl16 r8,0x2b4
f0c: 0d 60 01 03 wh16 r8,0x3
f10: 10 40 01 08 ld32 r8,r8
f14: 0d 40 6d 30 wl16 r9,0x370
f18: 0d 60 01 23 wh16 r9,0x3
f1c: 10 40 01 29 ld32 r9,r9
f20: 08 10 01 04 shl r8,0x4
f24: 20 70 03 e2 movepc rret,8
f28: 14 30 fc 3a br 10 <compare>,#al
f2c: 00 10 00 41 add r2,1
f30: 0d 40 55 18 wl16 r8,0x2b8
f34: 0d 60 01 03 wh16 r8,0x3
f38: 10 40 01 08 ld32 r8,r8
f3c: 0d 40 6d 34 wl16 r9,0x374
f40: 0d 60 01 23 wh16 r9,0x3
f44: 10 40 01 29 ld32 r9,r9
f48: 08 10 01 08 shl r8,0x8
f4c: 20 70 03 e2 movepc rret,8
f50: 14 30 fc 30 br 10 <compare>,#al
f54: 00 10 00 41 add r2,1
f58: 0d 40 55 1c wl16 r8,0x2bc
f5c: 0d 60 01 03 wh16 r8,0x3
f60: 10 40 01 08 ld32 r8,r8
f64: 0d 40 6d 38 wl16 r9,0x378
f68: 0d 60 01 23 wh16 r9,0x3
f6c: 10 40 01 29 ld32 r9,r9
f70: 08 10 01 10 shl r8,0x10
f74: 20 70 03 e2 movepc rret,8
f78: 14 30 fc 26 br 10 <compare>,#al
f7c: 00 10 00 41 add r2,1
f80: 0d 40 59 00 wl16 r8,0x2c0
f84: 0d 60 01 03 wh16 r8,0x3
f88: 10 40 01 08 ld32 r8,r8
f8c: 0d 40 6d 3c wl16 r9,0x37c
f90: 0d 60 01 23 wh16 r9,0x3
f94: 10 40 01 29 ld32 r9,r9
f98: 08 10 05 00 shl r8,0x20
f9c: 20 70 03 e2 movepc rret,8
fa0: 14 30 fc 1c br 10 <compare>,#al
fa4: 00 10 00 41 add r2,1
fa8: 0d 40 59 04 wl16 r8,0x2c4
fac: 0d 60 01 03 wh16 r8,0x3
fb0: 10 40 01 08 ld32 r8,r8
fb4: 0d 40 71 20 wl16 r9,0x380
fb8: 0d 60 01 23 wh16 r9,0x3
fbc: 10 40 01 29 ld32 r9,r9
fc0: 08 10 01 01 shl r8,0x1
fc4: 20 70 03 e2 movepc rret,8
fc8: 14 30 fc 12 br 10 <compare>,#al
fcc: 00 10 00 41 add r2,1
fd0: 0d 40 59 08 wl16 r8,0x2c8
fd4: 0d 60 01 03 wh16 r8,0x3
fd8: 10 40 01 08 ld32 r8,r8
fdc: 0d 40 71 24 wl16 r9,0x384
fe0: 0d 60 01 23 wh16 r9,0x3
fe4: 10 40 01 29 ld32 r9,r9
fe8: 08 10 01 02 shl r8,0x2
fec: 20 70 03 e2 movepc rret,8
ff0: 14 30 fc 08 br 10 <compare>,#al
ff4: 00 10 00 41 add r2,1
ff8: 0d 40 59 0c wl16 r8,0x2cc
ffc: 0d 60 01 03 wh16 r8,0x3
1000: 10 40 01 08 ld32 r8,r8
1004: 0d 40 71 28 wl16 r9,0x388
1008: 0d 60 01 23 wh16 r9,0x3
100c: 10 40 01 29 ld32 r9,r9
1010: 08 10 01 04 shl r8,0x4
1014: 20 70 03 e2 movepc rret,8
1018: 14 30 fb fe br 10 <compare>,#al
101c: 00 10 00 41 add r2,1
1020: 0d 40 59 10 wl16 r8,0x2d0
1024: 0d 60 01 03 wh16 r8,0x3
1028: 10 40 01 08 ld32 r8,r8
102c: 0d 40 71 2c wl16 r9,0x38c
1030: 0d 60 01 23 wh16 r9,0x3
1034: 10 40 01 29 ld32 r9,r9
1038: 08 10 01 08 shl r8,0x8
103c: 20 70 03 e2 movepc rret,8
1040: 14 30 fb f4 br 10 <compare>,#al
1044: 00 10 00 41 add r2,1
1048: 0d 40 59 14 wl16 r8,0x2d4
104c: 0d 60 01 03 wh16 r8,0x3
1050: 10 40 01 08 ld32 r8,r8
1054: 0d 40 71 30 wl16 r9,0x390
1058: 0d 60 01 23 wh16 r9,0x3
105c: 10 40 01 29 ld32 r9,r9
1060: 08 10 01 10 shl r8,0x10
1064: 20 70 03 e2 movepc rret,8
1068: 14 30 fb ea br 10 <compare>,#al
106c: 00 10 00 41 add r2,1
1070: 0d 40 59 18 wl16 r8,0x2d8
1074: 0d 60 01 03 wh16 r8,0x3
1078: 10 40 01 08 ld32 r8,r8
107c: 0d 40 71 34 wl16 r9,0x394
1080: 0d 60 01 23 wh16 r9,0x3
1084: 10 40 01 29 ld32 r9,r9
1088: 08 10 05 00 shl r8,0x20
108c: 20 70 03 e2 movepc rret,8
1090: 14 30 fb e0 br 10 <compare>,#al
1094: 00 10 00 41 add r2,1
1098: 0d 40 59 1c wl16 r8,0x2dc
109c: 0d 60 01 03 wh16 r8,0x3
10a0: 10 40 01 08 ld32 r8,r8
10a4: 0d 40 71 38 wl16 r9,0x398
10a8: 0d 60 01 23 wh16 r9,0x3
10ac: 10 40 01 29 ld32 r9,r9
10b0: 08 10 01 03 shl r8,0x3
10b4: 20 70 03 e2 movepc rret,8
10b8: 14 30 fb d6 br 10 <compare>,#al
10bc: 00 10 00 41 add r2,1
10c0: 0d 40 5d 00 wl16 r8,0x2e0
10c4: 0d 60 01 03 wh16 r8,0x3
10c8: 10 40 01 08 ld32 r8,r8
10cc: 0d 40 71 3c wl16 r9,0x39c
10d0: 0d 60 01 23 wh16 r9,0x3
10d4: 10 40 01 29 ld32 r9,r9
10d8: 08 10 01 07 shl r8,0x7
10dc: 20 70 03 e2 movepc rret,8
10e0: 14 30 fb cc br 10 <compare>,#al
10e4: 00 10 00 41 add r2,1
10e8: 0d 40 5d 04 wl16 r8,0x2e4
10ec: 0d 60 01 03 wh16 r8,0x3
10f0: 10 40 01 08 ld32 r8,r8
10f4: 0d 40 75 20 wl16 r9,0x3a0
10f8: 0d 60 01 23 wh16 r9,0x3
10fc: 10 40 01 29 ld32 r9,r9
1100: 08 10 01 0f shl r8,0xf
1104: 20 70 03 e2 movepc rret,8
1108: 14 30 fb c2 br 10 <compare>,#al
110c: 00 10 00 41 add r2,1
1110: 0d 40 5d 08 wl16 r8,0x2e8
1114: 0d 60 01 03 wh16 r8,0x3
1118: 10 40 01 08 ld32 r8,r8
111c: 0d 40 75 24 wl16 r9,0x3a4
1120: 0d 60 01 23 wh16 r9,0x3
1124: 10 40 01 29 ld32 r9,r9
1128: 08 10 01 1f shl r8,0x1f
112c: 20 70 03 e2 movepc rret,8
1130: 14 30 fb b8 br 10 <compare>,#al
1134: 00 10 00 41 add r2,1
1138: 0d 40 5d 0c wl16 r8,0x2ec
113c: 0d 60 01 03 wh16 r8,0x3
1140: 10 40 01 08 ld32 r8,r8
1144: 0d 40 75 28 wl16 r9,0x3a8
1148: 0d 60 01 23 wh16 r9,0x3
114c: 10 40 01 29 ld32 r9,r9
1150: 08 10 05 1f shl r8,0x3f
1154: 20 70 03 e2 movepc rret,8
1158: 14 30 fb ae br 10 <compare>,#al
115c: 00 10 00 41 add r2,1
1160: 14 30 fb be br 58 <finish>,#al
セクション .assert の逆アセンブル:
00020000 <CHECK_FLAG>:
20000: 00 00 00 01 add r0,r1
00020004 <CHECK_FINISH>:
20004: 00 00 00 00 add r0,r0
00020008 <ERROR_TYPE>:
20008: 00 00 00 00 add r0,r0
0002000c <ERROR_NUMBER>:
2000c: 00 00 00 00 add r0,r0
00020010 <ERROR_RESULT>:
20010: 00 00 00 00 add r0,r0
00020014 <ERROR_EXPECT>:
20014: 00 00 00 00 add r0,r0
セクション .data の逆アセンブル:
00030000 <T_SRC0_0>:
30000: 00 00 00 00 add r0,r0
00030004 <T_SRC0_1>:
30004: 00 00 00 00 add r0,r0
00030008 <T_SRC0_2>:
30008: 00 00 00 00 add r0,r0
0003000c <T_SRC0_3>:
3000c: 00 00 00 00 add r0,r0
00030010 <T_SRC0_4>:
30010: 00 00 00 00 add r0,r0
00030014 <T_SRC0_5>:
30014: 00 00 00 00 add r0,r0
00030018 <T_SRC0_6>:
30018: 00 00 00 01 add r0,r1
0003001c <T_SRC0_7>:
3001c: 00 00 00 01 add r0,r1
00030020 <T_SRC0_8>:
30020: 00 00 00 01 add r0,r1
00030024 <T_SRC0_9>:
30024: 00 00 00 01 add r0,r1
00030028 <T_SRC0_10>:
30028: 00 00 00 01 add r0,r1
0003002c <T_SRC0_11>:
3002c: 00 00 00 01 add r0,r1
00030030 <T_SRC0_12>:
30030: 00 00 00 02 add r0,r2
00030034 <T_SRC0_13>:
30034: 00 00 00 02 add r0,r2
00030038 <T_SRC0_14>:
30038: 00 00 00 02 add r0,r2
0003003c <T_SRC0_15>:
3003c: 00 00 00 02 add r0,r2
00030040 <T_SRC0_16>:
30040: 00 00 00 02 add r0,r2
00030044 <T_SRC0_17>:
30044: 00 00 00 02 add r0,r2
00030048 <T_SRC0_18>:
30048: 00 00 00 04 add r0,r4
0003004c <T_SRC0_19>:
3004c: 00 00 00 04 add r0,r4
00030050 <T_SRC0_20>:
30050: 00 00 00 04 add r0,r4
00030054 <T_SRC0_21>:
30054: 00 00 00 04 add r0,r4
00030058 <T_SRC0_22>:
30058: 00 00 00 04 add r0,r4
0003005c <T_SRC0_23>:
3005c: 00 00 00 04 add r0,r4
00030060 <T_SRC0_24>:
30060: 00 00 00 08 add r0,r8
00030064 <T_SRC0_25>:
30064: 00 00 00 08 add r0,r8
00030068 <T_SRC0_26>:
30068: 00 00 00 08 add r0,r8
0003006c <T_SRC0_27>:
3006c: 00 00 00 08 add r0,r8
00030070 <T_SRC0_28>:
30070: 00 00 00 08 add r0,r8
00030074 <T_SRC0_29>:
30074: 00 00 00 08 add r0,r8
00030078 <T_SRC0_30>:
30078: 00 00 00 10 add r0,r16
0003007c <T_SRC0_31>:
3007c: 00 00 00 10 add r0,r16
00030080 <T_SRC0_32>:
30080: 00 00 00 10 add r0,r16
00030084 <T_SRC0_33>:
30084: 00 00 00 10 add r0,r16
00030088 <T_SRC0_34>:
30088: 00 00 00 10 add r0,r16
0003008c <T_SRC0_35>:
3008c: 00 00 00 10 add r0,r16
00030090 <T_SRC0_36>:
30090: 00 00 00 20 add r1,r0
00030094 <T_SRC0_37>:
30094: 00 00 00 20 add r1,r0
00030098 <T_SRC0_38>:
30098: 00 00 00 20 add r1,r0
0003009c <T_SRC0_39>:
3009c: 00 00 00 20 add r1,r0
000300a0 <T_SRC0_40>:
300a0: 00 00 00 20 add r1,r0
000300a4 <T_SRC0_41>:
300a4: 00 00 00 20 add r1,r0
000300a8 <T_SRC0_42>:
300a8: 00 00 00 03 add r0,r3
000300ac <T_SRC0_43>:
300ac: 00 00 00 07 add r0,rtmp
000300b0 <T_SRC0_44>:
300b0: 00 00 00 0f add r0,r15
000300b4 <T_SRC0_45>:
300b4: 00 00 00 1f add r0,rret
000300b8 <T_SRC0_46>:
300b8: 00 00 00 3f add r1,rret
000300bc <T_SRC1_0>:
300bc: 00 00 00 01 add r0,r1
000300c0 <T_SRC1_1>:
300c0: 00 00 00 02 add r0,r2
000300c4 <T_SRC1_2>:
300c4: 00 00 00 04 add r0,r4
000300c8 <T_SRC1_3>:
300c8: 00 00 00 08 add r0,r8
000300cc <T_SRC1_4>:
300cc: 00 00 00 10 add r0,r16
000300d0 <T_SRC1_5>:
300d0: 00 00 00 20 add r1,r0
000300d4 <T_SRC1_6>:
300d4: 00 00 00 01 add r0,r1
000300d8 <T_SRC1_7>:
300d8: 00 00 00 02 add r0,r2
000300dc <T_SRC1_8>:
300dc: 00 00 00 04 add r0,r4
000300e0 <T_SRC1_9>:
300e0: 00 00 00 08 add r0,r8
000300e4 <T_SRC1_10>:
300e4: 00 00 00 10 add r0,r16
000300e8 <T_SRC1_11>:
300e8: 00 00 00 20 add r1,r0
000300ec <T_SRC1_12>:
300ec: 00 00 00 01 add r0,r1
000300f0 <T_SRC1_13>:
300f0: 00 00 00 02 add r0,r2
000300f4 <T_SRC1_14>:
300f4: 00 00 00 04 add r0,r4
000300f8 <T_SRC1_15>:
300f8: 00 00 00 08 add r0,r8
000300fc <T_SRC1_16>:
300fc: 00 00 00 10 add r0,r16
00030100 <T_SRC1_17>:
30100: 00 00 00 20 add r1,r0
00030104 <T_SRC1_18>:
30104: 00 00 00 01 add r0,r1
00030108 <T_SRC1_19>:
30108: 00 00 00 02 add r0,r2
0003010c <T_SRC1_20>:
3010c: 00 00 00 04 add r0,r4
00030110 <T_SRC1_21>:
30110: 00 00 00 08 add r0,r8
00030114 <T_SRC1_22>:
30114: 00 00 00 10 add r0,r16
00030118 <T_SRC1_23>:
30118: 00 00 00 20 add r1,r0
0003011c <T_SRC1_24>:
3011c: 00 00 00 01 add r0,r1
00030120 <T_SRC1_25>:
30120: 00 00 00 02 add r0,r2
00030124 <T_SRC1_26>:
30124: 00 00 00 04 add r0,r4
00030128 <T_SRC1_27>:
30128: 00 00 00 08 add r0,r8
0003012c <T_SRC1_28>:
3012c: 00 00 00 10 add r0,r16
00030130 <T_SRC1_29>:
30130: 00 00 00 20 add r1,r0
00030134 <T_SRC1_30>:
30134: 00 00 00 01 add r0,r1
00030138 <T_SRC1_31>:
30138: 00 00 00 02 add r0,r2
0003013c <T_SRC1_32>:
3013c: 00 00 00 04 add r0,r4
00030140 <T_SRC1_33>:
30140: 00 00 00 08 add r0,r8
00030144 <T_SRC1_34>:
30144: 00 00 00 10 add r0,r16
00030148 <T_SRC1_35>:
30148: 00 00 00 20 add r1,r0
0003014c <T_SRC1_36>:
3014c: 00 00 00 01 add r0,r1
00030150 <T_SRC1_37>:
30150: 00 00 00 02 add r0,r2
00030154 <T_SRC1_38>:
30154: 00 00 00 04 add r0,r4
00030158 <T_SRC1_39>:
30158: 00 00 00 08 add r0,r8
0003015c <T_SRC1_40>:
3015c: 00 00 00 10 add r0,r16
00030160 <T_SRC1_41>:
30160: 00 00 00 20 add r1,r0
00030164 <T_SRC1_42>:
30164: 00 00 00 03 add r0,r3
00030168 <T_SRC1_43>:
30168: 00 00 00 07 add r0,rtmp
0003016c <T_SRC1_44>:
3016c: 00 00 00 0f add r0,r15
00030170 <T_SRC1_45>:
30170: 00 00 00 1f add r0,rret
00030174 <T_SRC1_46>:
30174: 00 00 00 3f add r1,rret
00030178 <T_EXPECT0>:
30178: 00 00 00 00 add r0,r0
0003017c <T_EXPECT1>:
3017c: 00 00 00 00 add r0,r0
00030180 <T_EXPECT2>:
30180: 00 00 00 00 add r0,r0
00030184 <T_EXPECT3>:
30184: 00 00 00 00 add r0,r0
00030188 <T_EXPECT4>:
30188: 00 00 00 00 add r0,r0
0003018c <T_EXPECT5>:
3018c: 00 00 00 00 add r0,r0
00030190 <T_EXPECT6>:
30190: 00 00 00 02 add r0,r2
00030194 <T_EXPECT7>:
30194: 00 00 00 04 add r0,r4
00030198 <T_EXPECT8>:
30198: 00 00 00 10 add r0,r16
0003019c <T_EXPECT9>:
3019c: 00 00 01 00 add r8,r0
000301a0 <T_EXPECT10>:
301a0: 00 01 00 00 *unknown*
000301a4 <T_EXPECT11>:
301a4: 00 00 00 00 add r0,r0
000301a8 <T_EXPECT12>:
301a8: 00 00 00 04 add r0,r4
000301ac <T_EXPECT13>:
301ac: 00 00 00 08 add r0,r8
000301b0 <T_EXPECT14>:
301b0: 00 00 00 20 add r1,r0
000301b4 <T_EXPECT15>:
301b4: 00 00 02 00 add r16,r0
000301b8 <T_EXPECT16>:
301b8: 00 02 00 00 *unknown*
000301bc <T_EXPECT17>:
301bc: 00 00 00 00 add r0,r0
000301c0 <T_EXPECT18>:
301c0: 00 00 00 08 add r0,r8
000301c4 <T_EXPECT19>:
301c4: 00 00 00 10 add r0,r16
000301c8 <T_EXPECT20>:
301c8: 00 00 00 40 add r2,r0
000301cc <T_EXPECT21>:
301cc: 00 00 04 00 *unknown*
000301d0 <T_EXPECT22>:
301d0: 00 04 00 00 *unknown*
000301d4 <T_EXPECT23>:
301d4: 00 00 00 00 add r0,r0
000301d8 <T_EXPECT24>:
301d8: 00 00 00 10 add r0,r16
000301dc <T_EXPECT25>:
301dc: 00 00 00 20 add r1,r0
000301e0 <T_EXPECT26>:
301e0: 00 00 00 80 add r4,r0
000301e4 <T_EXPECT27>:
301e4: 00 00 08 00 *unknown*
000301e8 <T_EXPECT28>:
301e8: 00 08 00 00 *unknown*
000301ec <T_EXPECT29>:
301ec: 00 00 00 00 add r0,r0
000301f0 <T_EXPECT30>:
301f0: 00 00 00 20 add r1,r0
000301f4 <T_EXPECT31>:
301f4: 00 00 00 40 add r2,r0
000301f8 <T_EXPECT32>:
301f8: 00 00 01 00 add r8,r0
000301fc <T_EXPECT33>:
301fc: 00 00 10 00 *unknown*
00030200 <T_EXPECT34>:
30200: 00 10 00 00 add r0,0
00030204 <T_EXPECT35>:
30204: 00 00 00 00 add r0,r0
00030208 <T_EXPECT36>:
30208: 00 00 00 40 add r2,r0
0003020c <T_EXPECT37>:
3020c: 00 00 00 80 add r4,r0
00030210 <T_EXPECT38>:
30210: 00 00 02 00 add r16,r0
00030214 <T_EXPECT39>:
30214: 00 00 20 00 *unknown*
00030218 <T_EXPECT40>:
30218: 00 20 00 00 sub r0,r0
0003021c <T_EXPECT41>:
3021c: 00 00 00 00 add r0,r0
00030220 <T_EXPECT42>:
30220: 00 00 00 18 add r0,r24
00030224 <T_EXPECT43>:
30224: 00 00 03 80 add r28,r0
00030228 <T_EXPECT44>:
30228: 00 07 80 00 *unknown*
0003022c <T_EXPECT45>:
3022c: 80 00 00 00 *unknown*
00030230 <T_EXPECT46>:
30230: 00 00 00 00 add r0,r0
00030234 <T_IMM_DST0>:
30234: 00 00 00 00 add r0,r0
00030238 <T_IMM_DST1>:
30238: 00 00 00 00 add r0,r0
0003023c <T_IMM_DST2>:
3023c: 00 00 00 00 add r0,r0
00030240 <T_IMM_DST3>:
30240: 00 00 00 00 add r0,r0
00030244 <T_IMM_DST4>:
30244: 00 00 00 00 add r0,r0
00030248 <T_IMM_DST5>:
30248: 00 00 00 00 add r0,r0
0003024c <T_IMM_DST6>:
3024c: 00 00 00 01 add r0,r1
00030250 <T_IMM_DST7>:
30250: 00 00 00 01 add r0,r1
00030254 <T_IMM_DST8>:
30254: 00 00 00 01 add r0,r1
00030258 <T_IMM_DST9>:
30258: 00 00 00 01 add r0,r1
0003025c <T_IMM_DST10>:
3025c: 00 00 00 01 add r0,r1
00030260 <T_IMM_DST11>:
30260: 00 00 00 01 add r0,r1
00030264 <T_IMM_DST12>:
30264: 00 00 00 02 add r0,r2
00030268 <T_IMM_DST13>:
30268: 00 00 00 02 add r0,r2
0003026c <T_IMM_DST14>:
3026c: 00 00 00 02 add r0,r2
00030270 <T_IMM_DST15>:
30270: 00 00 00 02 add r0,r2
00030274 <T_IMM_DST16>:
30274: 00 00 00 02 add r0,r2
00030278 <T_IMM_DST17>:
30278: 00 00 00 02 add r0,r2
0003027c <T_IMM_DST18>:
3027c: 00 00 00 04 add r0,r4
00030280 <T_IMM_DST19>:
30280: 00 00 00 04 add r0,r4
00030284 <T_IMM_DST20>:
30284: 00 00 00 04 add r0,r4
00030288 <T_IMM_DST21>:
30288: 00 00 00 04 add r0,r4
0003028c <T_IMM_DST22>:
3028c: 00 00 00 04 add r0,r4
00030290 <T_IMM_DST23>:
30290: 00 00 00 04 add r0,r4
00030294 <T_IMM_DST24>:
30294: 00 00 00 08 add r0,r8
00030298 <T_IMM_DST25>:
30298: 00 00 00 08 add r0,r8
0003029c <T_IMM_DST26>:
3029c: 00 00 00 08 add r0,r8
000302a0 <T_IMM_DST27>:
302a0: 00 00 00 08 add r0,r8
000302a4 <T_IMM_DST28>:
302a4: 00 00 00 08 add r0,r8
000302a8 <T_IMM_DST29>:
302a8: 00 00 00 08 add r0,r8
000302ac <T_IMM_DST30>:
302ac: 00 00 00 10 add r0,r16
000302b0 <T_IMM_DST31>:
302b0: 00 00 00 10 add r0,r16
000302b4 <T_IMM_DST32>:
302b4: 00 00 00 10 add r0,r16
000302b8 <T_IMM_DST33>:
302b8: 00 00 00 10 add r0,r16
000302bc <T_IMM_DST34>:
302bc: 00 00 00 10 add r0,r16
000302c0 <T_IMM_DST35>:
302c0: 00 00 00 10 add r0,r16
000302c4 <T_IMM_DST36>:
302c4: 00 00 00 20 add r1,r0
000302c8 <T_IMM_DST37>:
302c8: 00 00 00 20 add r1,r0
000302cc <T_IMM_DST38>:
302cc: 00 00 00 20 add r1,r0
000302d0 <T_IMM_DST39>:
302d0: 00 00 00 20 add r1,r0
000302d4 <T_IMM_DST40>:
302d4: 00 00 00 20 add r1,r0
000302d8 <T_IMM_DST41>:
302d8: 00 00 00 20 add r1,r0
000302dc <T_IMM_DST42>:
302dc: 00 00 00 03 add r0,r3
000302e0 <T_IMM_DST43>:
302e0: 00 00 00 07 add r0,rtmp
000302e4 <T_IMM_DST44>:
302e4: 00 00 00 0f add r0,r15
000302e8 <T_IMM_DST45>:
302e8: 00 00 00 1f add r0,rret
000302ec <T_IMM_DST46>:
302ec: 00 00 00 3f add r1,rret
000302f0 <T_IMM_EXPECT0>:
302f0: 00 00 00 00 add r0,r0
000302f4 <T_IMM_EXPECT1>:
302f4: 00 00 00 00 add r0,r0
000302f8 <T_IMM_EXPECT2>:
302f8: 00 00 00 00 add r0,r0
000302fc <T_IMM_EXPECT3>:
302fc: 00 00 00 00 add r0,r0
00030300 <T_IMM_EXPECT4>:
30300: 00 00 00 00 add r0,r0
00030304 <T_IMM_EXPECT5>:
30304: 00 00 00 00 add r0,r0
00030308 <T_IMM_EXPECT6>:
30308: 00 00 00 02 add r0,r2
0003030c <T_IMM_EXPECT7>:
3030c: 00 00 00 04 add r0,r4
00030310 <T_IMM_EXPECT8>:
30310: 00 00 00 10 add r0,r16
00030314 <T_IMM_EXPECT9>:
30314: 00 00 01 00 add r8,r0
00030318 <T_IMM_EXPECT10>:
30318: 00 01 00 00 *unknown*
0003031c <T_IMM_EXPECT11>:
3031c: 00 00 00 00 add r0,r0
00030320 <T_IMM_EXPECT12>:
30320: 00 00 00 04 add r0,r4
00030324 <T_IMM_EXPECT13>:
30324: 00 00 00 08 add r0,r8
00030328 <T_IMM_EXPECT14>:
30328: 00 00 00 20 add r1,r0
0003032c <T_IMM_EXPECT15>:
3032c: 00 00 02 00 add r16,r0
00030330 <T_IMM_EXPECT16>:
30330: 00 02 00 00 *unknown*
00030334 <T_IMM_EXPECT17>:
30334: 00 00 00 00 add r0,r0
00030338 <T_IMM_EXPECT18>:
30338: 00 00 00 08 add r0,r8
0003033c <T_IMM_EXPECT19>:
3033c: 00 00 00 10 add r0,r16
00030340 <T_IMM_EXPECT20>:
30340: 00 00 00 40 add r2,r0
00030344 <T_IMM_EXPECT21>:
30344: 00 00 04 00 *unknown*
00030348 <T_IMM_EXPECT22>:
30348: 00 04 00 00 *unknown*
0003034c <T_IMM_EXPECT23>:
3034c: 00 00 00 00 add r0,r0
00030350 <T_IMM_EXPECT24>:
30350: 00 00 00 10 add r0,r16
00030354 <T_IMM_EXPECT25>:
30354: 00 00 00 20 add r1,r0
00030358 <T_IMM_EXPECT26>:
30358: 00 00 00 80 add r4,r0
0003035c <T_IMM_EXPECT27>:
3035c: 00 00 08 00 *unknown*
00030360 <T_IMM_EXPECT28>:
30360: 00 08 00 00 *unknown*
00030364 <T_IMM_EXPECT29>:
30364: 00 00 00 00 add r0,r0
00030368 <T_IMM_EXPECT30>:
30368: 00 00 00 20 add r1,r0
0003036c <T_IMM_EXPECT31>:
3036c: 00 00 00 40 add r2,r0
00030370 <T_IMM_EXPECT32>:
30370: 00 00 01 00 add r8,r0
00030374 <T_IMM_EXPECT33>:
30374: 00 00 10 00 *unknown*
00030378 <T_IMM_EXPECT34>:
30378: 00 10 00 00 add r0,0
0003037c <T_IMM_EXPECT35>:
3037c: 00 00 00 00 add r0,r0
00030380 <T_IMM_EXPECT36>:
30380: 00 00 00 40 add r2,r0
00030384 <T_IMM_EXPECT37>:
30384: 00 00 00 80 add r4,r0
00030388 <T_IMM_EXPECT38>:
30388: 00 00 02 00 add r16,r0
0003038c <T_IMM_EXPECT39>:
3038c: 00 00 20 00 *unknown*
00030390 <T_IMM_EXPECT40>:
30390: 00 20 00 00 sub r0,r0
00030394 <T_IMM_EXPECT41>:
30394: 00 00 00 00 add r0,r0
00030398 <T_IMM_EXPECT42>:
30398: 00 00 00 18 add r0,r24
0003039c <T_IMM_EXPECT43>:
3039c: 00 00 03 80 add r28,r0
000303a0 <T_IMM_EXPECT44>:
303a0: 00 07 80 00 *unknown*
000303a4 <T_IMM_EXPECT45>:
303a4: 80 00 00 00 *unknown*
000303a8 <T_IMM_EXPECT46>:
303a8: 00 00 00 00 add r0,r0
セクション .stack の逆アセンブル:
000f0000 <STACK_INDEX>:
f0000: 00 00 00 00 add r0,r0
| cpulabs/mist1032sa | sim/inst_level/bin/shl.asm | Assembly | bsd-2-clause | 54,175 |
;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
EXPORT |vp8_short_walsh4x4_armv6|
ARM
REQUIRE8
PRESERVE8
AREA |.text|, CODE, READONLY ; name this block of code
;short vp8_short_walsh4x4_armv6(short *input, short *output, int pitch)
; r0 short *input,
; r1 short *output,
; r2 int pitch
|vp8_short_walsh4x4_armv6| PROC
stmdb sp!, {r4 - r11, lr}
ldrd r4, r5, [r0], r2
ldr lr, c00040004
ldrd r6, r7, [r0], r2
; 0-3
qadd16 r3, r4, r5 ; [d1|a1] [1+3 | 0+2]
qsub16 r4, r4, r5 ; [c1|b1] [1-3 | 0-2]
ldrd r8, r9, [r0], r2
; 4-7
qadd16 r5, r6, r7 ; [d1|a1] [5+7 | 4+6]
qsub16 r6, r6, r7 ; [c1|b1] [5-7 | 4-6]
ldrd r10, r11, [r0]
; 8-11
qadd16 r7, r8, r9 ; [d1|a1] [9+11 | 8+10]
qsub16 r8, r8, r9 ; [c1|b1] [9-11 | 8-10]
; 12-15
qadd16 r9, r10, r11 ; [d1|a1] [13+15 | 12+14]
qsub16 r10, r10, r11 ; [c1|b1] [13-15 | 12-14]
lsls r2, r3, #16
smuad r11, r3, lr ; A0 = a1<<2 + d1<<2
addne r11, r11, #1 ; A0 += (a1!=0)
lsls r2, r7, #16
smuad r12, r7, lr ; C0 = a1<<2 + d1<<2
addne r12, r12, #1 ; C0 += (a1!=0)
add r0, r11, r12 ; a1_0 = A0 + C0
sub r11, r11, r12 ; b1_0 = A0 - C0
lsls r2, r5, #16
smuad r12, r5, lr ; B0 = a1<<2 + d1<<2
addne r12, r12, #1 ; B0 += (a1!=0)
lsls r2, r9, #16
smuad r2, r9, lr ; D0 = a1<<2 + d1<<2
addne r2, r2, #1 ; D0 += (a1!=0)
add lr, r12, r2 ; d1_0 = B0 + D0
sub r12, r12, r2 ; c1_0 = B0 - D0
; op[0,4,8,12]
adds r2, r0, lr ; a2 = a1_0 + d1_0
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
subs r0, r0, lr ; d2 = a1_0 - d1_0
mov r2, r2, asr #3 ; >> 3
strh r2, [r1] ; op[0]
addmi r0, r0, #1 ; += a2 < 0
add r0, r0, #3 ; += 3
ldr lr, c00040004
mov r0, r0, asr #3 ; >> 3
strh r0, [r1, #24] ; op[12]
adds r2, r11, r12 ; b2 = b1_0 + c1_0
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
subs r0, r11, r12 ; c2 = b1_0 - c1_0
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #8] ; op[4]
addmi r0, r0, #1 ; += a2 < 0
add r0, r0, #3 ; += 3
smusd r3, r3, lr ; A3 = a1<<2 - d1<<2
smusd r7, r7, lr ; C3 = a1<<2 - d1<<2
mov r0, r0, asr #3 ; >> 3
strh r0, [r1, #16] ; op[8]
; op[3,7,11,15]
add r0, r3, r7 ; a1_3 = A3 + C3
sub r3, r3, r7 ; b1_3 = A3 - C3
smusd r5, r5, lr ; B3 = a1<<2 - d1<<2
smusd r9, r9, lr ; D3 = a1<<2 - d1<<2
add r7, r5, r9 ; d1_3 = B3 + D3
sub r5, r5, r9 ; c1_3 = B3 - D3
adds r2, r0, r7 ; a2 = a1_3 + d1_3
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
adds r9, r3, r5 ; b2 = b1_3 + c1_3
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #6] ; op[3]
addmi r9, r9, #1 ; += a2 < 0
add r9, r9, #3 ; += 3
subs r2, r3, r5 ; c2 = b1_3 - c1_3
mov r9, r9, asr #3 ; >> 3
strh r9, [r1, #14] ; op[7]
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
subs r9, r0, r7 ; d2 = a1_3 - d1_3
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #22] ; op[11]
addmi r9, r9, #1 ; += a2 < 0
add r9, r9, #3 ; += 3
smuad r3, r4, lr ; A1 = b1<<2 + c1<<2
smuad r5, r8, lr ; C1 = b1<<2 + c1<<2
mov r9, r9, asr #3 ; >> 3
strh r9, [r1, #30] ; op[15]
; op[1,5,9,13]
add r0, r3, r5 ; a1_1 = A1 + C1
sub r3, r3, r5 ; b1_1 = A1 - C1
smuad r7, r6, lr ; B1 = b1<<2 + c1<<2
smuad r9, r10, lr ; D1 = b1<<2 + c1<<2
add r5, r7, r9 ; d1_1 = B1 + D1
sub r7, r7, r9 ; c1_1 = B1 - D1
adds r2, r0, r5 ; a2 = a1_1 + d1_1
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
adds r9, r3, r7 ; b2 = b1_1 + c1_1
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #2] ; op[1]
addmi r9, r9, #1 ; += a2 < 0
add r9, r9, #3 ; += 3
subs r2, r3, r7 ; c2 = b1_1 - c1_1
mov r9, r9, asr #3 ; >> 3
strh r9, [r1, #10] ; op[5]
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
subs r9, r0, r5 ; d2 = a1_1 - d1_1
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #18] ; op[9]
addmi r9, r9, #1 ; += a2 < 0
add r9, r9, #3 ; += 3
smusd r4, r4, lr ; A2 = b1<<2 - c1<<2
smusd r8, r8, lr ; C2 = b1<<2 - c1<<2
mov r9, r9, asr #3 ; >> 3
strh r9, [r1, #26] ; op[13]
; op[2,6,10,14]
add r11, r4, r8 ; a1_2 = A2 + C2
sub r12, r4, r8 ; b1_2 = A2 - C2
smusd r6, r6, lr ; B2 = b1<<2 - c1<<2
smusd r10, r10, lr ; D2 = b1<<2 - c1<<2
add r4, r6, r10 ; d1_2 = B2 + D2
sub r8, r6, r10 ; c1_2 = B2 - D2
adds r2, r11, r4 ; a2 = a1_2 + d1_2
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
adds r9, r12, r8 ; b2 = b1_2 + c1_2
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #4] ; op[2]
addmi r9, r9, #1 ; += a2 < 0
add r9, r9, #3 ; += 3
subs r2, r12, r8 ; c2 = b1_2 - c1_2
mov r9, r9, asr #3 ; >> 3
strh r9, [r1, #12] ; op[6]
addmi r2, r2, #1 ; += a2 < 0
add r2, r2, #3 ; += 3
subs r9, r11, r4 ; d2 = a1_2 - d1_2
mov r2, r2, asr #3 ; >> 3
strh r2, [r1, #20] ; op[10]
addmi r9, r9, #1 ; += a2 < 0
add r9, r9, #3 ; += 3
mov r9, r9, asr #3 ; >> 3
strh r9, [r1, #28] ; op[14]
ldmia sp!, {r4 - r11, pc}
ENDP ; |vp8_short_walsh4x4_armv6|
c00040004
DCD 0x00040004
END
| blloyd75/theoraplayer | vpx/vp8/encoder/arm/armv6/walsh_v6.asm | Assembly | bsd-3-clause | 7,532 |
;-------------------------------------------------------------------
; Praktikum SMD 2015
; M.Wahyudin (140310120031)
;
; Name : LATIH19.ASM
; Desc : Menggerakkan motor DC dengan metoda PWM
; Input : PB di P0(0,1,2)
; Output: Motor DC P1(0)
;-------------------------------------------------------------------
T_UP equ 30h
T_DN equ 31h
TB0 BIT P0.0
TB1 BIT P0.1
TB2 BIT P0.2
cseg at 0
awal:
mov T_UP, #07fh ;hi cycle counting
mov T_DN, #07fh ;lo cycle counting
ulang:
anl T_UP, #0ffh
anl T_DN, #0ffh
setb P1.0 ;make hi cycle
mov r0, T_UP ;hold it
djnz r0, $
clr P1.0 ;make lo cycle
mov r0, T_DN ;hold it
djnz r0, $
jb TB0, L0
mov r1, 0fh
djnz r1, $ ;debouncing delay
jb TB0, L0 ;check consistency
jnb TB0, $ ;wait until released
inc T_UP ;use TB0 to increase pwm duty cycle
dec T_DN ;lower speed and then turning opposite dir
L0:
jb TB1, L1
mov r1, 0fh
djnz r1, $
jb TB1, L1
jnb TB1, $
dec T_UP ;use TB1 to lower pwm duty cycle
inc T_DN ;lower speed and then turning opposite dir
L1:
jb TB2, L2
mov r1, 0fh
djnz r1, $
jb TB2, L2
jnb TB2, $
mov T_UP, #07fh ;use TB2 to stop
mov T_DN, #07fh ;50% duty cycle made motor stop
L2:
jmp ulang
end
| hyuwah/fu-praktikum-smd | Modul 4/latih19.asm | Assembly | mit | 1,362 |
PS2_COMMAND_PORT equ 0x64
PS2_STATUS_PORT equ 0x64
PS2_DATA_PORT equ 0x60
PS2_READ_CONFIG equ 0x20
PS2_WRITE_CONFIG equ 0x60
PS2_TEST_CONTROLLER equ 0xAA
PS2_ENABLE_PORT1 equ 0xAE
PS2_DISABLE_PORT1 equ 0xAD
PS2_TEST_PORT1 equ 0xAB
PS2_SEND_PORT1 equ 0xD1 ; is this right?
PS2_FAKEAS_PORT1 equ 0xD2
PS2_ENABLE_PORT2 equ 0xA8
PS2_DISABLE_PORT2 equ 0xA7
PS2_TEST_PORT2 equ 0xA9
PS2_SEND_PORT2 equ 0xD4
PS2_FAKEAS_PORT2 equ 0xD3
PS2_RESET_CPU equ 0xFE
PS2_SELFTEST_SUCCESS equ 0x55
PS2_ACK equ 0xFA
PS2_OUTB_FULL_FLAG equ 0b00000001
PS2_INPB_FULL_FLAG equ 0b00000010
PS2_TRANSLATE_FLAG equ 0b01000000
PS2_PORT1_INT_FLAG equ 0b00000001
PS2_PORT2_INT_FLAG equ 0b00000010
PS2_P2CLKDSBL_FLAG equ 0b00100000
ps2.init :
methodTraceEnter
pusha
; Disable all ps2 devices
call ps2.waitForWrite
mov al, PS2_DISABLE_PORT1
out PS2_COMMAND_PORT, al ; first controller
call ps2.waitForWrite
mov al, PS2_DISABLE_PORT2
out PS2_COMMAND_PORT, al ; second controller (if exists)
; Discard any residual data
call ps2.discardAllData
; Disable translation and ints in controller config byte
call ps2.readConfigByte
mov bl, (PS2_TRANSLATE_FLAG | PS2_PORT1_INT_FLAG | PS2_PORT2_INT_FLAG)
not bl
or al, bl
mov cl, al
call ps2.waitForWrite
mov al, PS2_WRITE_CONFIG
out PS2_COMMAND_PORT, al
call ps2.waitForWrite
mov al, cl
out PS2_DATA_PORT, al
; Perform self-test
call ps2.waitForWrite
mov al, PS2_TEST_CONTROLLER
out PS2_COMMAND_PORT, al
call ps2.waitForData
in al, PS2_DATA_PORT
cmp al, PS2_SELFTEST_SUCCESS
jne ps2.sw_selftestFail
; Check for second ps2 port
call ps2.waitForWrite
mov al, PS2_ENABLE_PORT2
out PS2_COMMAND_PORT, al
call ps2.readConfigByte
test al, PS2_P2CLKDSBL_FLAG
jnz ps2.sw_singlePortController
call ps2.waitForWrite
mov al, PS2_DISABLE_PORT2
out PS2_COMMAND_PORT, al
; Test both ports
call ps2.waitForWrite
mov al, PS2_TEST_PORT1
out PS2_COMMAND_PORT, al
call ps2.waitForData
in al, PS2_DATA_PORT
cmp al, 0x0
jne ps2.sw_test1fail
call ps2.waitForWrite
mov al, PS2_TEST_PORT2
out PS2_COMMAND_PORT, al
call ps2.waitForData
in al, PS2_DATA_PORT
cmp al, 0x0
jne ps2.sw_test2fail
; Enable ps2 devices
call ps2.waitForWrite
mov al, PS2_ENABLE_PORT1
out PS2_COMMAND_PORT, al
call ps2.waitForWrite
mov al, PS2_ENABLE_PORT2
out PS2_COMMAND_PORT, al
; Enable ints on all devices (should probably check to see what kind of devices they are before blindly enabling them...)
call ps2.readConfigByte
or al, (PS2_PORT1_INT_FLAG | PS2_PORT2_INT_FLAG)
mov cl, al
call ps2.waitForWrite
mov al, PS2_WRITE_CONFIG
out PS2_COMMAND_PORT, al
call ps2.waitForWrite
mov al, cl
out PS2_DATA_PORT, al
call mouse.init ; should not be done here...
popa
methodTraceLeave
ret
ps2firstrep :
db 0x0
ps2.discardAllData :
methodTraceEnter
in al, PS2_STATUS_PORT
test al, PS2_OUTB_FULL_FLAG
jz ps2.discardAllData.ret
in al, PS2_DATA_PORT
jmp ps2.discardAllData
ps2.discardAllData.ret :
methodTraceLeave
ret
ps2.readConfigByte :
methodTraceEnter
call ps2.waitForWrite
mov al, PS2_READ_CONFIG
out PS2_COMMAND_PORT, al
call ps2.waitForData
in al, PS2_DATA_PORT
methodTraceLeave
ret
ps2.waitForData :
methodTraceEnter
ps2.waitForDataLoop :
in al, PS2_STATUS_PORT
test al, PS2_OUTB_FULL_FLAG
jz ps2.waitForDataLoop
methodTraceLeave
ret
ps2.waitForWrite :
methodTraceEnter
ps2.waitForWriteLoop :
in al, PS2_STATUS_PORT
test al, PS2_INPB_FULL_FLAG
jnz ps2.waitForWriteLoop
methodTraceLeave
ret
ps2.waitForACK :
methodTraceEnter
mov al, PS2_ACK
call ps2.waitForResponse
methodTraceLeave
ret
ps2.waitForResponse :
methodTraceEnter
mov bl, al
ps2.waitForResponse.loop :
in al, PS2_DATA_PORT
cmp al, bl
jne ps2.waitForResponse.loop
methodTraceLeave
ret
ps2.commandPort1 : ; is this right?
methodTraceEnter
push ax
call ps2.waitForWrite
out PS2_DATA_PORT, al
pop ax
methodTraceLeave
ret
ps2.commandPort2 :
methodTraceEnter
push ax
mov ah, al
call ps2.waitForWrite
mov al, PS2_SEND_PORT2
out PS2_COMMAND_PORT, al
call ps2.waitForWrite
mov al, ah
out PS2_DATA_PORT, al
pop ax
methodTraceLeave
ret
ps2.sw_selftestFail :
mov eax, SysHaltScreen.RESET
mov ebx, PS2.SELFTEST_FAILMSG
mov ecx, 5
call SysHaltScreen.show
methodTraceLeave
popa
ret
ps2.sw_singlePortController :
mov eax, SysHaltScreen.WARN
mov ebx, PS2.SINGLEPORT_MSG
mov ecx, 3
call SysHaltScreen.show
methodTraceLeave
popa
ret
ps2.sw_test1fail :
mov eax, SysHaltScreen.RESET
mov ebx, PS2.PORT1_FAILMSG
mov ecx, 5
call SysHaltScreen.show
methodTraceLeave
popa
ret
ps2.sw_test2fail :
mov eax, SysHaltScreen.WARN
mov ebx, PS2.PORT2_FAILMSG
mov ecx, 3
call SysHaltScreen.show
methodTraceLeave
popa
ret
ps2.sw_timeout :
mov eax, SysHaltScreen.RESET
mov ebx, PS2.TIMEOUT_MSG
mov ecx, 5
call SysHaltScreen.show
methodTraceLeave
popa
ret
ps2.resetCPU :
methodTraceEnter
call ps2.waitForWrite
mov al, PS2_RESET_CPU
out PS2_COMMAND_PORT, al
mov eax, SysHaltScreen.WARN
mov ebx, PS2.RESET_FAILMSG
mov ecx, 10
call SysHaltScreen.show
methodTraceLeave
ret
PS2.RESET_FAILMSG :
db "Could not reset the CPU.", 0
PS2.SELFTEST_FAILMSG :
db "PS/2 Controller test fail. Restarting the computer...", 0
PS2.SINGLEPORT_MSG :
db "PS/2 Controller does not have a second port.", 0
PS2.PORT1_FAILMSG :
db "PS/2 Port 1 test fail. Restarting the computer...", 0
PS2.PORT2_FAILMSG :
db "PS/2 Port 2 test fail.", 0
PS2.TIMEOUT_MSG :
db "PS/2 Controller not responding. Restarting the computer...", 0 | jaredwhitney/os3 | Drivers/PS2/PS_2.asm | Assembly | mit | 5,488 |
; Copyright 2015-2021 Matt "MateoConLechuga" Waltz
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
flash_backup_ram:
call port_unlock
ld a,$3f
call flash_erase_sector ; clean out the flash sectors
ld a,$3e
call flash_erase_sector
ld a,$3d
call flash_erase_sector
ld a,$3c
call flash_erase_sector
ld hl,$d00001
ld (hl),$a5
dec hl
ld (hl),$5a ; write some magical bytes
ld de,$3c0000 ; write all of ram
ld bc,$40000
call ti.WriteFlash
jp port_lock
flash_erase_sector:
ld bc,$f8
push bc
jp ti.EraseFlashSector
flash_clear_backup:
ld de,$3c0000 ; backup address
ld hl,$d00001
xor a,a
ld b,a ; write 0
ld (hl),a
inc hl
ld (hl),a
ld a,(de)
or a,a
ret z ; dont clear if done already
call port_unlock
call ti.WriteFlashByte ; clear old backup
jp port_lock
if config_english
string_ram_backup:
db 'Backing up...',0
end if
if config_french
string_ram_backup:
db 'Sauvegarde en cours...',0
end if
if config_dutch
string_ram_backup:
db 'Backup wordt gemaakt...',0
end if
| MateoConLechuga/Cesium | src/flash.asm | Assembly | bsd-3-clause | 2,458 |
; Generated at 3/12/2016 8:37:32 PM
%ifndef Exclude_IOPort_Based_SerialInit
DebugStub_InitSerial:
Mov DX, 1
Mov AL, 0
Call DebugStub_WriteRegister
Mov DX, 3
Mov AL, 0x80
Call DebugStub_WriteRegister
Mov DX, 0
Mov AL, 0x01
Call DebugStub_WriteRegister
Mov DX, 1
Mov AL, 0x00
Call DebugStub_WriteRegister
Mov DX, 3
Mov AL, 0x03
Call DebugStub_WriteRegister
Mov DX, 2
Mov AL, 0xC7
Call DebugStub_WriteRegister
Mov DX, 4
Mov AL, 0x03
Call DebugStub_WriteRegister
DebugStub_InitSerial_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_InitSerial_Exit
Ret
DebugStub_ComReadAL:
Mov DX, 5
DebugStub_ComReadAL_Wait:
Call DebugStub_ReadRegister
Test AL, 0x01
JZ DebugStub_ComReadAL_Wait
Mov DX, 0
Call DebugStub_ReadRegister
DebugStub_ComReadAL_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_ComReadAL_Exit
Ret
DebugStub_ComWrite8:
Mov DX, 5
DebugStub_ComWrite8_Wait:
Call DebugStub_ReadRegister
Test AL, 0x20
JZ DebugStub_ComWrite8_Wait
Mov DX, 0
Mov AL, [ESI + 0]
Call DebugStub_WriteRegister
Inc ESI
DebugStub_ComWrite8_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_ComWrite8_Exit
Ret
%endif
| Cyber4/Cosmos | source/Cosmos.Debug.DebugStub/Serial.asm | Assembly | bsd-3-clause | 1,292 |
; Autogenerated by the Meson build system.
; Do not edit, your changes will be lost.
%define ARCH_X86_32 1
%define ARCH_X86_64 0
%define FORCE_VEX_ENCODING 0
%define HAVE_AVX512ICL 1
%define PIC 1
; %define STACK_ALIGNMENT 16 -- Stack alignment is controlled by Chromium
%define private_prefix dav1d
| nwjs/chromium.src | third_party/dav1d/config/linux/x86/config.asm | Assembly | bsd-3-clause | 307 |
MAXWDS EQU 1200
PERM ORIG *+MAXWDS
ANS ORIG *+MAXWDS
OUTBUF ORIG *+24
CARDS EQU 16
PRINTER EQU 18
BEGIN IN PERM(CARDS)
ENT2 0
LDA EQUALS
1H JBUS *(CARDS)
CMPA PERM+15,2
JE *+2
IN PERM+16,2(CARDS)
ENT1 OUTBUF
JBUS *(PRINTER)
MOVE PERM,2(16)
OUT OUTBUF(PRINTER)
JE 1F
INC2 16
CMP2 =MAXWDS-16=
JLE 1B
HLT
1H INC2 15
ST2 SIZE
ENT3 0
2H LDAN PERM,3
CMPA LPREN(1:5)
JNE 1F
STA PERM,3
INC3 1
LDXN PERM,3
JXZ *-2
1H CMPA RPREN(1:5)
JNE *+2
STX PERM,3
INC3 1
CMP3 SIZE
JL 2B
LDA LPREN
ENT1 ANS
OPEN ENT3 0
1H LDXN PERM,3
JXN GO
INC3 1
CMP3 SIZE
JL 1B
*
DONE CMP1 =ANS=
JNE *+2
MOVE LPREN(2)
MOVE =0=
MOVE -1,1(22)
ENT3 0
OUT ANS,3(PRINTER)
INC3 24
LDX ANS,3
JXNZ *-3
HLT
*
LPREN ALF (
RPREN ALF )
EQUALS ALF =
*
GO MOVE LPREN
MOVE PERM,3
STX START
SUCC STX PERM,3
INC3 1
LDXN PERM,3(1:5)
JXN 1F
JMP *-3
5H STX 0,1
INC1 1
ENT3 0
4H CMPX PERM,3(1:5)
JE SUCC
1H INC3 1
CMP3 SIZE
JL 4B
CMPX START(1:5)
JNE 5B
CLOSE MOVE RPREN
CMPA -3,1
JNE OPEN
INC1 -3
JMP OPEN
END BEGIN | thkim1011/MIX | src/test/resources/permutation1.asm | Assembly | mit | 1,572 |
GLOBAL read_key
read_key:
in al, 60h
ret
| jcaracciolo/Arqui2016 | Kernel/asm/keys.asm | Assembly | bsd-3-clause | 45 |
;---------------------------------------
; CLi² (Command Line Interface) API
; 2016 © breeze/fishbone crew
;---------------------------------------
; MODULE: #65 getMonthNameByNumber
;---------------------------------------
; Получить 3-х буквенное назавание месяца по номеру
; i: A' - номер месяца (1-12)
; DE - адрес строки куда сохранить 3 символа
;---------------------------------------
ex af,af'
_getMonthNameByNumber
dec a
ld c,a
sla a ; * 2
add a,c ; * 3 ?
ld hl,monthNames
ld b,0
ld c,a
add hl,bc
ld b,3
gmnbnLoop ld a,(hl)
ld (de),a
inc hl
inc de
djnz gmnbnLoop
ret
;---------------------------------------
| LessNick/cli2 | src/system/api/getMonthNameByNumber.asm | Assembly | bsd-3-clause | 773 |
ORG 42
BSA MMA
HEAD, VECTOR
LEN, DEC 7
MAX, DEC 0
MIN, DEC 0
AVG, DEC 0
HLT
MMA, HEX 0
LDA MMA I
STA CUR
ISZ MMA
LDA MMA I
STA IN_Y
CMA
INC
STA _LEN
ISZ MMA
BUN LOOP
CUR, HEX 0
_LEN, DEC 0
_MAX, DEC -32768
_MIN, DEC 32767
_SUM, DEC 0
LOOP, LDA _SUM
ADD CUR I
STA _SUM
// Check MAX
LDA CUR I
CMA
INC
ADD _MAX
SNA
BUN CHECK_MAX
LDA CUR I
STA _MAX
CHECK_MAX, SZE
BUN NEW_MAX
BUN BRANCH_MIN
NEW_MAX, LDA CUR I
STA _MAX
// Check MIN
BRANCH_MIN, CLA
CLE
LDA CUR I
CMA
INC
ADD _MIN
SPA
BUN CHECK_MIN
LDA CUR I
STA _MIN
CHECK_MIN, SZE
BUN NEW_MIN
BUN NEXT
NEW_MIN, LDA CUR I
STA _MIN
NEXT, ISZ CUR
ISZ _LEN
BUN LOOP
CLA
CLE
LDA _MAX
STA MMA I
ISZ MMA
LDA _MIN
STA MMA I
ISZ MMA
CLA
CLE
LDA _SUM
STA IN_X
BSA DIV
IN_X, DEC 0
IN_Y, DEC 0
OUT_DIV, DEC 0
LDA OUT_DIV
STA MMA I
ISZ MMA
BUN MMA I
DIV,HEX 0
CLA
CLE
BUN START
X, DEC 0
Y, DEC 0
RIS, DEC -1
START, LDA DIV I
STA X
ISZ DIV
LDA DIV I
CMA
INC
STA Y
ISZ DIV
LDA X
DIV_LOOP, ADD Y
ISZ RIS
SNA
BUN DIV_LOOP
LDA RIS
STA DIV I
ISZ DIV
BUN DIV I
VECTOR, DEC 1
DEC 5
DEC 88
DEC 7
DEC 21
DEC -16
DEC 99
END | MircoT/js-pdp8 | lib/test/sources/max_min_avg.asm | Assembly | mit | 1,064 |
;Testname=test; Arguments=-fbin -obr890790.bin; Files=stdout stderr br890790.bin
%rep 5
db 0
%include "br890790_i.asm"
%endrep
db 1
| coapp-packages/nasm | test/br890790.asm | Assembly | bsd-2-clause | 144 |
/*
* All Video Processing kernels
* Copyright © <2010>, Intel Corporation.
*
* This program is licensed under the terms and conditions of the
* Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
* http://www.opensource.org/licenses/eclipse-1.0.php.
*
*/
#define DI_ENABLE
#include "DNDI.inc"
#undef nY_NUM_OF_ROWS
#define nY_NUM_OF_ROWS 8 // Number of Y rows per block (4 rows for each frame)
#undef nUV_NUM_OF_ROWS
#define nUV_NUM_OF_ROWS 8 // Number of U/V rows per block
#undef nSMPL_RESP_LEN
#define nSMPL_RESP_LEN nSMPL_RESP_LEN_DNDI // set the number of GRF
#undef nDPW_BLOCK_SIZE_HIST
#define nDPW_BLOCK_SIZE_HIST nBLOCK_WIDTH_4+nBLOCK_HEIGHT_1 // HIST Block Size for Write is 4x2
#undef nDPW_BLOCK_SIZE_DN
#define nDPW_BLOCK_SIZE_DN nBLOCK_WIDTH_16+nBLOCK_HEIGHT_4 // DN Block Size for Write is 16x4
#undef nDPR_BLOCK_SIZE_UV
#define nDPR_BLOCK_SIZE_UV nBLOCK_WIDTH_16+nBLOCK_HEIGHT_2 // DN Block Size for UV Write/Read is 16x2
////////////////////////////////////// Run the DN Algorithm ///////////////////////////////////////
#include "DNDI_COMMAND.asm"
////////////////////////////////////// Rearrange for Internal Planar //////////////////////////////
// move the previous frame Y component to internal planar format
$for (0; <nY_NUM_OF_ROWS/2; 1) {
mov (16) uwDEST_Y(%1,0)<1> ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16)
}
// move the previous frame U,V components to internal planar format
$for (0; <nUV_NUM_OF_ROWS/2; 1) {
mov (8) uwDEST_U(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels
mov (8) uwDEST_V(0,%1*8)<1> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels
}
// move the current frame Y component to internal planar format
$for (0; <nY_NUM_OF_ROWS/2; 1) {
mov (16) uwDEST_Y(%1+4,0)<1> ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16)
}
// move the current frame U,V components to internal planar format
$for (0; <nUV_NUM_OF_ROWS/2; 1) {
mov (8) uwDEST_U(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16+1)<16;8,2> //U pixels
mov (8) uwDEST_V(2,%1*8)<1> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET,%1*16)<16;8,2> //V pixels
}
////////////////////////////////////// Save the STMM Data for Next Run /////////////////////////
// Write STMM to memory
shr (1) rMSGSRC.0<1>:ud wORIX<0;1,0>:w 1:w // X origin / 2
mov (1) rMSGSRC.1<1>:ud wORIY<0;1,0>:w // Y origin
mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_STMM:ud // block width and height (8x4)
mov (8) mudMSGHDR_STMM(0)<1> rMSGSRC.0<8;8,1>:ud // message header
mov (8) mudMSGHDR_STMM(1)<1> udRESP(nDI_STMM_OFFSET,0) // Move STMM to MRF
send (8) dNULLREG mMSGHDR_STMM udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_STMM+nBI_STMM_HISTORY_OUTPUT:ud
////////////////////////////////////// Save the History Data for Next Run /////////////////////////
#include "DI_Hist_Save.asm"
////////////////////////////////////// Save the DN Curr Frame for Next Run ////////////////////////
// previous frame
$for (0; <nY_NUM_OF_ROWS/2; 1) {
mov (16) mubMSGHDR_DN(1, %1*16)<1> ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16)
}
mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4)
mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud
//Write UV through DATAPORT
mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's
mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // block width and height (16x2)
mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
mov (8) mubMSGHDR_DN(1, 0)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET, 1)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 1)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET, 16)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 16)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET+1, 1)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 17)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET+1, 16)<16 ;8,2>
send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_UV:ud
// current frame
$for (0; <nY_NUM_OF_ROWS/2; 1) {
mov (16) mubMSGHDR_DN(1, %1*16)<1> ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16)
}
mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4)
mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_1_Y:ud
//Write UV through DATAPORT
mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's
mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // block width and height (16x2)
mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
mov (8) mubMSGHDR_DN(1, 0)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 1)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 1)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 16)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 16)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 1)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 17)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 16)<16 ;8,2>
send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_1_UV:ud
| fritsch/libva-intel-driver | src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm | Assembly | mit | 6,212 |
;[]-----------------------------------------------------------------[]
;| COMPARE.ASM -- string comparing functions |
;[]-----------------------------------------------------------------[]
;
; $Copyright: 2005$
; $Revision: 1.1.1.1 $
;
;int __fastcall Compare(const AnsiString& rhs) const;
;int __fastcall Compare(const AnsiString& rhs, const Mode &mode) const;
;bool __fastcall operator !=(const AnsiString& rhs) const;
;bool __fastcall operator ==(const AnsiString& rhs) const;
;bool __fastcall operator <(const AnsiString& rhs) const;
;bool __fastcall operator <=(const AnsiString& rhs) const;
;bool __fastcall operator >(const AnsiString& rhs) const;
;bool __fastcall operator >=(const AnsiString& rhs) const;
%include 'constant.inc'
GLOBAL Compare_table
GLOBAL CompareSymbol_table
GLOBAL @FastString@Compare$xqqrrx10FastString
GLOBAL @FastString@Compare$xqqrrx10FastStringrx4Mode
GLOBAL @FastString@$bequ$xqqrrx10FastString
GLOBAL @FastString@$bneq$xqqrrx10FastString
GLOBAL @FastString@$bblw$xqqrrx10FastString
GLOBAL @FastString@$babw$xqqrrx10FastString
GLOBAL @FastString@$bble$xqqrrx10FastString
GLOBAL @FastString@$babe$xqqrrx10FastString
EXTERN IsEmpty
section _TEXT
@FastString@Compare$xqqrrx10FastString:
;in
;eax: this
;edx: FastString
;out
;eax: code -1 0 1
call IsEmpty
jz @FastString@Compare$xqqrrx10FastString_exit
call [CompareSymbol_table+edx*4]
@FastString@Compare$xqqrrx10FastString_exit:
ret
@FastString@Compare$xqqrrx10FastStringrx4Mode:
;in
;eax: this
;edx: FastString
;ecx: CompareMode
;out
;eax: code -1 0 1
ret
@FastString@$bequ$xqqrrx10FastString:
ret
@FastString@$bneq$xqqrrx10FastString:
ret
@FastString@$bblw$xqqrrx10FastString:
ret
@FastString@$babw$xqqrrx10FastString:
ret
@FastString@$bble$xqqrrx10FastString:
ret
@FastString@$babe$xqqrrx10FastString:
ret
section _DATA
CompareSymbol_table: dd 0
Compare_table: dd 0
| majioa/fleco | src/strings/compare.asm | Assembly | mit | 1,970 |
;
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
EXPORT |vp8_subtract_b_neon|
EXPORT |vp8_subtract_mby_neon|
EXPORT |vp8_subtract_mbuv_neon|
INCLUDE asm_enc_offsets.asm
ARM
REQUIRE8
PRESERVE8
AREA ||.text||, CODE, READONLY, ALIGN=2
;void vp8_subtract_b_neon(BLOCK *be, BLOCKD *bd, int pitch)
|vp8_subtract_b_neon| PROC
stmfd sp!, {r4-r7}
ldr r3, [r0, #vp8_block_base_src]
ldr r4, [r0, #vp8_block_src]
ldr r5, [r0, #vp8_block_src_diff]
ldr r3, [r3]
ldr r6, [r0, #vp8_block_src_stride]
add r3, r3, r4 ; src = *base_src + src
ldr r7, [r1, #vp8_blockd_predictor_base]
add r7, r7, #vp8_blockd_predictor_offset
vld1.8 {d0}, [r3], r6 ;load src
vld1.8 {d1}, [r7], r2 ;load pred
vld1.8 {d2}, [r3], r6
vld1.8 {d3}, [r7], r2
vld1.8 {d4}, [r3], r6
vld1.8 {d5}, [r7], r2
vld1.8 {d6}, [r3], r6
vld1.8 {d7}, [r7], r2
vsubl.u8 q10, d0, d1
vsubl.u8 q11, d2, d3
vsubl.u8 q12, d4, d5
vsubl.u8 q13, d6, d7
mov r2, r2, lsl #1
vst1.16 {d20}, [r5], r2 ;store diff
vst1.16 {d22}, [r5], r2
vst1.16 {d24}, [r5], r2
vst1.16 {d26}, [r5], r2
ldmfd sp!, {r4-r7}
bx lr
ENDP
;==========================================
;void vp8_subtract_mby_neon(short *diff, unsigned char *src, int src_stride
; unsigned char *pred, int pred_stride)
|vp8_subtract_mby_neon| PROC
push {r4-r7}
mov r12, #4
ldr r4, [sp, #16] ; pred_stride
mov r6, #32 ; "diff" stride x2
add r5, r0, #16 ; second diff pointer
subtract_mby_loop
vld1.8 {q0}, [r1], r2 ;load src
vld1.8 {q1}, [r3], r4 ;load pred
vld1.8 {q2}, [r1], r2
vld1.8 {q3}, [r3], r4
vld1.8 {q4}, [r1], r2
vld1.8 {q5}, [r3], r4
vld1.8 {q6}, [r1], r2
vld1.8 {q7}, [r3], r4
vsubl.u8 q8, d0, d2
vsubl.u8 q9, d1, d3
vsubl.u8 q10, d4, d6
vsubl.u8 q11, d5, d7
vsubl.u8 q12, d8, d10
vsubl.u8 q13, d9, d11
vsubl.u8 q14, d12, d14
vsubl.u8 q15, d13, d15
vst1.16 {q8}, [r0], r6 ;store diff
vst1.16 {q9}, [r5], r6
vst1.16 {q10}, [r0], r6
vst1.16 {q11}, [r5], r6
vst1.16 {q12}, [r0], r6
vst1.16 {q13}, [r5], r6
vst1.16 {q14}, [r0], r6
vst1.16 {q15}, [r5], r6
subs r12, r12, #1
bne subtract_mby_loop
pop {r4-r7}
bx lr
ENDP
;=================================
;void vp8_subtract_mbuv_c(short *diff, unsigned char *usrc, unsigned char *vsrc,
; int src_stride, unsigned char *upred,
; unsigned char *vpred, int pred_stride)
|vp8_subtract_mbuv_neon| PROC
push {r4-r7}
ldr r4, [sp, #16] ; upred
ldr r5, [sp, #20] ; vpred
ldr r6, [sp, #24] ; pred_stride
add r0, r0, #512 ; short *udiff = diff + 256;
mov r12, #32 ; "diff" stride x2
add r7, r0, #16 ; second diff pointer
;u
vld1.8 {d0}, [r1], r3 ;load usrc
vld1.8 {d1}, [r4], r6 ;load upred
vld1.8 {d2}, [r1], r3
vld1.8 {d3}, [r4], r6
vld1.8 {d4}, [r1], r3
vld1.8 {d5}, [r4], r6
vld1.8 {d6}, [r1], r3
vld1.8 {d7}, [r4], r6
vld1.8 {d8}, [r1], r3
vld1.8 {d9}, [r4], r6
vld1.8 {d10}, [r1], r3
vld1.8 {d11}, [r4], r6
vld1.8 {d12}, [r1], r3
vld1.8 {d13}, [r4], r6
vld1.8 {d14}, [r1], r3
vld1.8 {d15}, [r4], r6
vsubl.u8 q8, d0, d1
vsubl.u8 q9, d2, d3
vsubl.u8 q10, d4, d5
vsubl.u8 q11, d6, d7
vsubl.u8 q12, d8, d9
vsubl.u8 q13, d10, d11
vsubl.u8 q14, d12, d13
vsubl.u8 q15, d14, d15
vst1.16 {q8}, [r0], r12 ;store diff
vst1.16 {q9}, [r7], r12
vst1.16 {q10}, [r0], r12
vst1.16 {q11}, [r7], r12
vst1.16 {q12}, [r0], r12
vst1.16 {q13}, [r7], r12
vst1.16 {q14}, [r0], r12
vst1.16 {q15}, [r7], r12
;v
vld1.8 {d0}, [r2], r3 ;load vsrc
vld1.8 {d1}, [r5], r6 ;load vpred
vld1.8 {d2}, [r2], r3
vld1.8 {d3}, [r5], r6
vld1.8 {d4}, [r2], r3
vld1.8 {d5}, [r5], r6
vld1.8 {d6}, [r2], r3
vld1.8 {d7}, [r5], r6
vld1.8 {d8}, [r2], r3
vld1.8 {d9}, [r5], r6
vld1.8 {d10}, [r2], r3
vld1.8 {d11}, [r5], r6
vld1.8 {d12}, [r2], r3
vld1.8 {d13}, [r5], r6
vld1.8 {d14}, [r2], r3
vld1.8 {d15}, [r5], r6
vsubl.u8 q8, d0, d1
vsubl.u8 q9, d2, d3
vsubl.u8 q10, d4, d5
vsubl.u8 q11, d6, d7
vsubl.u8 q12, d8, d9
vsubl.u8 q13, d10, d11
vsubl.u8 q14, d12, d13
vsubl.u8 q15, d14, d15
vst1.16 {q8}, [r0], r12 ;store diff
vst1.16 {q9}, [r7], r12
vst1.16 {q10}, [r0], r12
vst1.16 {q11}, [r7], r12
vst1.16 {q12}, [r0], r12
vst1.16 {q13}, [r7], r12
vst1.16 {q14}, [r0], r12
vst1.16 {q15}, [r7], r12
pop {r4-r7}
bx lr
ENDP
END
| awatry/libvpx.opencl | vp8/encoder/arm/neon/subtract_neon.asm | Assembly | bsd-3-clause | 6,362 |
;---------------------------------------
; CLi² (Command Line Interface) hex to int converter
; 2013,2014 © breeze/fishbone crew
;---------------------------------------
; in: de,str addr | "0A"
;out: h=0,l=byte | #0a (10)
; a=0 - ok, a=#ff - wrong hex
_hex2int ld a,(de)
call ascii2Number
sla a
sla a
sla a
sla a
and %11110000
ld c,a
inc de
ld a,(de)
inc de
call ascii2Number
and %00001111
or c
ld h,#00
ld l,a
xor a
ret
ascii2Number cp "0"
jr c,wrongHex
cp "9"+1
jr nc,ascii2Number_00
sub #30 ; 0 - 9
ret
ascii2Number_00 cp "A"
jr c,wrongHex
cp "F"+1
jr nc,ascii2Number_01
sub 55 ; A = 10
ret
ascii2Number_01 cp "a"
jr c,wrongHex
cp "f"+1
jr nc,wrongHex
sub 87 ; a = 10
ret
wrongHex ld a,#ff ; error
ld hl,#0000
ret
| LessNick/cli2 | src/system/hex2int.asm | Assembly | bsd-3-clause | 868 |
DATA = $b500
STATUS = $b501
DIVIDER_LO = $b502
DIVIDER_HI = $b503
PORTC = $b002
HEXOUT = $f802
STROUT = $f7d1
CLOCK = 16000000
BAUD = 115200
DIVIDER = CLOCK / BAUD / 4
start = $80
mem = $82
ptr = $84
crc = $86
fcrc = $88
tmpa = $8a
.org $3000 - 22
.byte "SERIAL "
.word startOfCode
.word startOfCode
.word endOfCode - startOfCode
startOfCode:
LDA #$00
STA start
LDA #$40
STA start + 1
JSR STROUT
.byte "SEND DATA", 10, 13
LDA #<DIVIDER
STA DIVIDER_LO
LDA #>DIVIDER
STA DIVIDER_HI
LDA start
STA mem
LDA start + 1
STA mem + 1
LDY #$00
STY fcrc
STY fcrc + 1
waitForFirstByte:
LDA STATUS
AND #$02
BEQ waitForFirstByte
BNE gotByte
waitForByte:
LDX #$00
loop:
LDA STATUS
AND #$02
BNE gotByte
DEX
BNE loop
DEY
BNE loop
BEQ end
gotByte:
LDY #$00
LDA PORTC
EOR #$04
STA PORTC
LDX fcrc ; 3
LDA fcrc + 1 ; 3
EOR crcTableLo, X ; 4*
STA fcrc ; 3
LDA DATA
STA (mem),Y
EOR crcTableHi, X ; 4*
STA fcrc + 1 ; 3
INC mem
BNE waitForByte
INC mem+1
BNE waitForByte
end:
JSR STROUT
.byte "START: "
LDA start + 1
JSR HEXOUT
LDA start
JSR HEXOUT
JSR STROUT
.byte 10, 13, " END: "
LDA mem + 1
JSR HEXOUT
LDA mem
JSR HEXOUT
JSR slowCRC
JSR STROUT
.byte 10, 13, " CRC1: "
LDA crc + 1
JSR HEXOUT
LDA crc
JSR HEXOUT
JSR mirrorFastCRC
JSR STROUT
.byte 10, 13, " CRC2: "
LDA fcrc + 1
JSR HEXOUT
LDA fcrc
JSR HEXOUT
JSR fastCRC
JSR STROUT
.byte 10, 13, " CRC3: "
LDA fcrc + 1
JSR HEXOUT
LDA fcrc
JSR HEXOUT
JSR STROUT
.byte 10, 13
NOP
RTS
slowCRC:
LDA start
STA ptr
LDA start + 1
STA ptr + 1
LDA #$00
STA crc
STA crc + 1
slowCRC1:
LDY #$00
LDA (ptr),Y
STA tmpa
LDX #$08
slowCRC2:
LSR tmpa
ROL crc
ROL crc + 1
BCC slowCRC3
LDA crc
EOR #$2D
STA crc
slowCRC3:
DEX
BNE slowCRC2
INC ptr
BNE slowCRC4
INC ptr + 1
slowCRC4:
LDA ptr
CMP mem
BNE slowCRC1
LDA ptr + 1
CMP mem + 1
BNE slowCRC1
RTS
fastCRC:
LDA start
STA ptr
LDA start + 1
STA ptr + 1
LDA #$00
STA fcrc
STA fcrc + 1
LDY #$00
fastCRC1:
;; crc = (crc >> 8) ^ CRCtbl[(crc & 0xFF)] ^ ((b & 0xff) << 8);
LDX fcrc ; 3
LDA fcrc + 1 ; 3
EOR crcTableLo, X ; 4*
STA fcrc ; 3
LDA (ptr),Y ; 5*
EOR crcTableHi, X ; 4*
STA fcrc + 1 ; 3
INC ptr ; 3
BNE fastCRC4 ; 3
INC ptr + 1 ; 3
fastCRC4:
LDA ptr ; 3
CMP mem ; 3
BNE fastCRC1 ; 3
LDA ptr + 1 ; 3
CMP mem + 1 ; 3
BNE fastCRC1 ; 3
mirrorFastCRC:
;; reverse the result bits to get the standard Atom CRC
LDA fcrc
JSR mirror
PHA
LDA fcrc + 1
JSR mirror
STA fcrc
PLA
STA fcrc + 1
RTS
mirror:
LDX #7
mirror1:
ASL A
ROR tmpa
DEX
BPL mirror1
LDA tmpa
RTS
;; low byte
crcTableLo:
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
.byte $00, $68, $d0, $b8, $a0, $c8, $70, $18
.byte $40, $28, $90, $f8, $e0, $88, $30, $58
.byte $80, $e8, $50, $38, $20, $48, $f0, $98
.byte $c0, $a8, $10, $78, $60, $08, $b0, $d8
;; high byte
crcTableHi:
.byte $00, $01, $02, $03, $05, $04, $07, $06
.byte $0b, $0a, $09, $08, $0e, $0f, $0c, $0d
.byte $16, $17, $14, $15, $13, $12, $11, $10
.byte $1d, $1c, $1f, $1e, $18, $19, $1a, $1b
.byte $2d, $2c, $2f, $2e, $28, $29, $2a, $2b
.byte $26, $27, $24, $25, $23, $22, $21, $20
.byte $3b, $3a, $39, $38, $3e, $3f, $3c, $3d
.byte $30, $31, $32, $33, $35, $34, $37, $36
.byte $5a, $5b, $58, $59, $5f, $5e, $5d, $5c
.byte $51, $50, $53, $52, $54, $55, $56, $57
.byte $4c, $4d, $4e, $4f, $49, $48, $4b, $4a
.byte $47, $46, $45, $44, $42, $43, $40, $41
.byte $77, $76, $75, $74, $72, $73, $70, $71
.byte $7c, $7d, $7e, $7f, $79, $78, $7b, $7a
.byte $61, $60, $63, $62, $64, $65, $66, $67
.byte $6a, $6b, $68, $69, $6f, $6e, $6d, $6c
.byte $b4, $b5, $b6, $b7, $b1, $b0, $b3, $b2
.byte $bf, $be, $bd, $bc, $ba, $bb, $b8, $b9
.byte $a2, $a3, $a0, $a1, $a7, $a6, $a5, $a4
.byte $a9, $a8, $ab, $aa, $ac, $ad, $ae, $af
.byte $99, $98, $9b, $9a, $9c, $9d, $9e, $9f
.byte $92, $93, $90, $91, $97, $96, $95, $94
.byte $8f, $8e, $8d, $8c, $8a, $8b, $88, $89
.byte $84, $85, $86, $87, $81, $80, $83, $82
.byte $ee, $ef, $ec, $ed, $eb, $ea, $e9, $e8
.byte $e5, $e4, $e7, $e6, $e0, $e1, $e2, $e3
.byte $f8, $f9, $fa, $fb, $fd, $fc, $ff, $fe
.byte $f3, $f2, $f1, $f0, $f6, $f7, $f4, $f5
.byte $c3, $c2, $c1, $c0, $c6, $c7, $c4, $c5
.byte $c8, $c9, $ca, $cb, $cd, $cc, $cf, $ce
.byte $d5, $d4, $d7, $d6, $d0, $d1, $d2, $d3
.byte $de, $df, $dc, $dd, $db, $da, $d9, $d8
endOfCode:
| wsoltys/AtomFpga | utils/serial.asm | Assembly | apache-2.0 | 6,620 |
; Copyright (c) 2008-2009, diamond
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of the <organization> nor the
; names of its contributors may be used to endorse or promote products
; derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY Alexey Teplov aka <Lrz> ''AS IS'' AND ANY
; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL <copyright holder> BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
use_lba = 0
org 0x7C00
jmp start
nop
; FAT parameters, BPB
; they must be changed at install, replaced with real values
rb 8 ; BS_OEMName, ignored
dw 200h ; BPB_BytsPerSec
BPB_SecsPerClus db ?
BPB_RsvdSecCnt dw ?
BPB_NumFATs db ?
BPB_RootEntCnt dw ?
dw ? ; BPB_TotSec16
db ? ; BPB_Media
dw ? ; BPB_FATSz16 = 0 for FAT32
BPB_SecPerTrk dw ?
BPB_NumHeads dw ?
BPB_HiddSec dd ?
dd ? ; BPB_TotSec32
BPB_FATSz32 dd ?
BPB_ExtFlags dw ?
dw ? ; BPB_FSVer
BPB_RootClus dd ?
dw ? ; BPB_FSInfo
BPB_BkBootSec dw ?
rb 12 ; BPB_Reserved
BS_DrvNum db ?
db ? ; BS_Reserved1
db ? ; BS_BootSig
dd ? ; BS_VolID
rb 11 ; BS_VolLab
rb 8 ;
curseg dw 0x8000
start:
xor ax, ax
mov ss, ax
mov sp, 0x7C00
mov ds, ax
mov bp, sp
cld
sti
push dx ; byte [bp-2] = boot drive
if use_lba
mov ah, 41h
mov bx, 55AAh
int 13h
mov si, aNoLBA
jc err_
cmp bx, 0AA55h
jnz err_
test cl, 1
jz err_
else
mov ah, 8
int 13h
jc @f
movzx ax, dh
inc ax
mov [bp+BPB_NumHeads-0x7C00], ax
and cx, 3Fh
mov [bp+BPB_SecPerTrk-0x7C00], cx
@@:
end if
; get FAT parameters
xor bx, bx
movzx eax, [bp+BPB_NumFATs-0x7C00]
mul [bp+BPB_FATSz32-0x7C00]
movzx ecx, [bp+BPB_RsvdSecCnt-0x7C00]
push ecx ; FAT start = dword [bp-6]
add eax, ecx
push eax ; data start = dword [bp-10]
;push dword -1 ; dword [bp-14] = current sector for FAT cache
db 66h
push -1 ; dword [bp-14] = current sector for FAT cache
mov eax, [bp+BPB_RootClus-0x7C00]
mov si, main_loader
call lookup_in_dir
jnc kordldr_ok
noloader:
mov si, aLoaderNotFound
err_:
call out_string
mov si, aPressAnyKey
call out_string
xor ax, ax
int 16h
int 18h
jmp $
kordldr_ok:
mov eax, [es:di+20-2] ; hiword(eax) = hiword(cluster)
mov ax, [es:di+26] ; loword(eax) = loword(cluster)
mov es, bx ; es = 0
mov bx, 0x7E00
push bx ; save return address: bx = 7E00
; fall through - 'ret' in read_cluster will return to 7E00
read_cluster:
; ss:bp = 0:7C00
; es:bx = pointer to data
; eax = cluster
sub eax, 2
movzx ecx, [bp+BPB_SecsPerClus-0x7C00]
mul ecx
read_sectors2:
; same as read_sectors32, but eax is relative to start of data
add eax, [bp-10]
read_sectors32:
; ss:bp = 0:7C00
; es:bx = pointer to data
; eax = first sector
; cx = number of sectors
; some high words of 32-bit registers are destroyed!
pusha
add eax, [bp+BPB_HiddSec-0x7C00]
if use_lba
push ds
do_read_sectors:
push ax
push cx
cmp cx, 0x7F
jbe @f
mov cx, 0x7F
@@:
; create disk address packet on the stack
; dq starting LBA
push 0
push 0
push eax
; dd buffer
push es
push bx
; dw number of blocks to transfer (no more than 0x7F)
push cx
; dw packet size in bytes
push 10h
; issue BIOS call
push ss
pop ds
mov si, sp
mov dl, [bp-2]
mov ah, 42h
int 13h
mov si, aReadError
jc err_
; restore stack
add sp, 10h
; increase current sector & buffer; decrease number of sectors
movzx esi, cx
mov ax, es
shl cx, 5
add ax, cx
mov es, ax
pop cx
pop ax
add eax, esi
sub cx, si
jnz do_read_sectors
pop ds
popa
ret
else
do_read_sectors:
pusha
pop edi ; loword(edi) = di, hiword(edi) = si
push bx
; eax / (SectorsPerTrack) -> eax, remainder bx
movzx esi, [bp+BPB_SecPerTrk-0x7C00]
xor edx, edx
div esi
mov bx, dx ; bx=sector-1
; eax -> dx:ax
push eax
pop ax
pop dx
; (dword in dx:ax) / (NumHeads) -> (word in ax), remainder dx
div [bp+BPB_NumHeads-0x7C00]
; number of sectors: read no more than to end of track
sub si, bx
cmp cx, si
jbe @f
mov cx, si
@@:
inc bx
; now ax=track, dl=head, dh=0, cl=number of sectors, ch=0, bl=sector; convert to int13 format
movzx edi, cx
mov dh, dl
mov dl, [bp-2]
shl ah, 6
mov ch, al
mov al, cl
mov cl, bl
or cl, ah
pop bx
mov si, 3
mov ah, 2
@@:
push ax
int 13h
jnc @f
xor ax, ax
int 13h ; reset drive
pop ax
dec si
jnz @b
mov si, aReadError
jmp err_
@@:
pop ax
mov ax, es
mov cx, di
shl cx, 5
add ax, cx
mov es, ax
push edi
popa
add eax, edi
sub cx, di
jnz do_read_sectors
popa
ret
end if
lookup_in_dir:
; in: ds:si -> 11-bytes FAT name
; in: eax = cluster
; in: bx = 0
; out: if found: CF=0, es:di -> directory entry
; out: if not found: CF=1
; push 0x8000
; pop es
; read current cluster: first cluster goes to 8000:0000, others - to 8200:0000
mov es, [bp-7C00h + curseg]
push es
push eax
call read_cluster
mov ax, es
cmp ah, 82h
jb @f
mov ax, 8200h
@@:
mov [bp-7C00h + curseg], ax
pop eax
pop es
; scan for filename
shl cx, 4
xor di, di
sloop:
cmp byte [es:di], bl
jz snotfound
test byte [es:di+11], 8 ; volume label?
jnz scont ; ignore volume labels
pusha
mov cx, 11
repz cmpsb
popa
jz sdone
scont:
add di, 0x20
loop sloop
; next cluster
push 0x6000
pop es
push es ax
shr eax, 7
cmp eax, [bp-14]
mov [bp-14], eax
jz @f
add eax, [bp-6]
mov cx, 1
call read_sectors32
@@:
pop di es
and di, 0x7F
shl di, 2
and byte [es:di+3], 0x0F
mov eax, [es:di]
;and eax, 0x0FFFFFFF
cmp eax, 0x0FFFFFF7
jb lookup_in_dir
snotfound:
stc
sdone:
ret
out_string:
; in: ds:si -> ASCIIZ string
lodsb
test al, al
jz sdone
mov ah, 0Eh
mov bx, 7
int 10h
jmp out_string
aReadError db 'Read error',0
if use_lba
aNoLBA db 'The drive does not support LBA!',0
end if
aLoaderNotFound db 'Loader not found',0
aPressAnyKey db 13,10,'Press any key...',13,10,0
main_loader db 'KORDLDR F32'
db 56h
; just to make file 512 bytes long :)
db 'd' xor 'i' xor 'a' xor 'm' xor 'o' xor 'n' xor 'd'
; bootsector signature
dw 0xAA55
; display offsets of all procedures used by kordldr.f12.asm
macro show [procedure]
{
bits = 16
display `procedure,' = '
repeat bits/4
d = '0' + procedure shr (bits - %*4) and 0Fh
if d > '9'
d = d + 'A'-'9'-1
end if
display d
end repeat
display 13,10
}
show read_sectors32, read_sectors2, err_, noloader
| devlato/kolibrios-llvm | kernel/trunk/sec_loader/trunk/boot/fat32/bootsect.asm | Assembly | mit | 10,154 |
OPTION DOTNAME
.text$ SEGMENT ALIGN(256) 'CODE'
EXTERN OPENSSL_ia32cap_P:NEAR
PUBLIC rsaz_512_sqr
ALIGN 32
rsaz_512_sqr PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_rsaz_512_sqr::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD PTR[40+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
sub rsp,128+24
$L$sqr_body::
mov rbp,rdx
mov rdx,QWORD PTR[rsi]
mov rax,QWORD PTR[8+rsi]
mov QWORD PTR[128+rsp],rcx
jmp $L$oop_sqr
ALIGN 32
$L$oop_sqr::
mov DWORD PTR[((128+8))+rsp],r8d
mov rbx,rdx
mul rdx
mov r8,rax
mov rax,QWORD PTR[16+rsi]
mov r9,rdx
mul rbx
add r9,rax
mov rax,QWORD PTR[24+rsi]
mov r10,rdx
adc r10,0
mul rbx
add r10,rax
mov rax,QWORD PTR[32+rsi]
mov r11,rdx
adc r11,0
mul rbx
add r11,rax
mov rax,QWORD PTR[40+rsi]
mov r12,rdx
adc r12,0
mul rbx
add r12,rax
mov rax,QWORD PTR[48+rsi]
mov r13,rdx
adc r13,0
mul rbx
add r13,rax
mov rax,QWORD PTR[56+rsi]
mov r14,rdx
adc r14,0
mul rbx
add r14,rax
mov rax,rbx
mov r15,rdx
adc r15,0
add r8,r8
mov rcx,r9
adc r9,r9
mul rax
mov QWORD PTR[rsp],rax
add r8,rdx
adc r9,0
mov QWORD PTR[8+rsp],r8
shr rcx,63
mov r8,QWORD PTR[8+rsi]
mov rax,QWORD PTR[16+rsi]
mul r8
add r10,rax
mov rax,QWORD PTR[24+rsi]
mov rbx,rdx
adc rbx,0
mul r8
add r11,rax
mov rax,QWORD PTR[32+rsi]
adc rdx,0
add r11,rbx
mov rbx,rdx
adc rbx,0
mul r8
add r12,rax
mov rax,QWORD PTR[40+rsi]
adc rdx,0
add r12,rbx
mov rbx,rdx
adc rbx,0
mul r8
add r13,rax
mov rax,QWORD PTR[48+rsi]
adc rdx,0
add r13,rbx
mov rbx,rdx
adc rbx,0
mul r8
add r14,rax
mov rax,QWORD PTR[56+rsi]
adc rdx,0
add r14,rbx
mov rbx,rdx
adc rbx,0
mul r8
add r15,rax
mov rax,r8
adc rdx,0
add r15,rbx
mov r8,rdx
mov rdx,r10
adc r8,0
add rdx,rdx
lea r10,QWORD PTR[r10*2+rcx]
mov rbx,r11
adc r11,r11
mul rax
add r9,rax
adc r10,rdx
adc r11,0
mov QWORD PTR[16+rsp],r9
mov QWORD PTR[24+rsp],r10
shr rbx,63
mov r9,QWORD PTR[16+rsi]
mov rax,QWORD PTR[24+rsi]
mul r9
add r12,rax
mov rax,QWORD PTR[32+rsi]
mov rcx,rdx
adc rcx,0
mul r9
add r13,rax
mov rax,QWORD PTR[40+rsi]
adc rdx,0
add r13,rcx
mov rcx,rdx
adc rcx,0
mul r9
add r14,rax
mov rax,QWORD PTR[48+rsi]
adc rdx,0
add r14,rcx
mov rcx,rdx
adc rcx,0
mul r9
mov r10,r12
lea r12,QWORD PTR[r12*2+rbx]
add r15,rax
mov rax,QWORD PTR[56+rsi]
adc rdx,0
add r15,rcx
mov rcx,rdx
adc rcx,0
mul r9
shr r10,63
add r8,rax
mov rax,r9
adc rdx,0
add r8,rcx
mov r9,rdx
adc r9,0
mov rcx,r13
lea r13,QWORD PTR[r13*2+r10]
mul rax
add r11,rax
adc r12,rdx
adc r13,0
mov QWORD PTR[32+rsp],r11
mov QWORD PTR[40+rsp],r12
shr rcx,63
mov r10,QWORD PTR[24+rsi]
mov rax,QWORD PTR[32+rsi]
mul r10
add r14,rax
mov rax,QWORD PTR[40+rsi]
mov rbx,rdx
adc rbx,0
mul r10
add r15,rax
mov rax,QWORD PTR[48+rsi]
adc rdx,0
add r15,rbx
mov rbx,rdx
adc rbx,0
mul r10
mov r12,r14
lea r14,QWORD PTR[r14*2+rcx]
add r8,rax
mov rax,QWORD PTR[56+rsi]
adc rdx,0
add r8,rbx
mov rbx,rdx
adc rbx,0
mul r10
shr r12,63
add r9,rax
mov rax,r10
adc rdx,0
add r9,rbx
mov r10,rdx
adc r10,0
mov rbx,r15
lea r15,QWORD PTR[r15*2+r12]
mul rax
add r13,rax
adc r14,rdx
adc r15,0
mov QWORD PTR[48+rsp],r13
mov QWORD PTR[56+rsp],r14
shr rbx,63
mov r11,QWORD PTR[32+rsi]
mov rax,QWORD PTR[40+rsi]
mul r11
add r8,rax
mov rax,QWORD PTR[48+rsi]
mov rcx,rdx
adc rcx,0
mul r11
add r9,rax
mov rax,QWORD PTR[56+rsi]
adc rdx,0
mov r12,r8
lea r8,QWORD PTR[r8*2+rbx]
add r9,rcx
mov rcx,rdx
adc rcx,0
mul r11
shr r12,63
add r10,rax
mov rax,r11
adc rdx,0
add r10,rcx
mov r11,rdx
adc r11,0
mov rcx,r9
lea r9,QWORD PTR[r9*2+r12]
mul rax
add r15,rax
adc r8,rdx
adc r9,0
mov QWORD PTR[64+rsp],r15
mov QWORD PTR[72+rsp],r8
shr rcx,63
mov r12,QWORD PTR[40+rsi]
mov rax,QWORD PTR[48+rsi]
mul r12
add r10,rax
mov rax,QWORD PTR[56+rsi]
mov rbx,rdx
adc rbx,0
mul r12
add r11,rax
mov rax,r12
mov r15,r10
lea r10,QWORD PTR[r10*2+rcx]
adc rdx,0
shr r15,63
add r11,rbx
mov r12,rdx
adc r12,0
mov rbx,r11
lea r11,QWORD PTR[r11*2+r15]
mul rax
add r9,rax
adc r10,rdx
adc r11,0
mov QWORD PTR[80+rsp],r9
mov QWORD PTR[88+rsp],r10
mov r13,QWORD PTR[48+rsi]
mov rax,QWORD PTR[56+rsi]
mul r13
add r12,rax
mov rax,r13
mov r13,rdx
adc r13,0
xor r14,r14
shl rbx,1
adc r12,r12
adc r13,r13
adc r14,r14
mul rax
add r11,rax
adc r12,rdx
adc r13,0
mov QWORD PTR[96+rsp],r11
mov QWORD PTR[104+rsp],r12
mov rax,QWORD PTR[56+rsi]
mul rax
add r13,rax
adc rdx,0
add r14,rdx
mov QWORD PTR[112+rsp],r13
mov QWORD PTR[120+rsp],r14
mov r8,QWORD PTR[rsp]
mov r9,QWORD PTR[8+rsp]
mov r10,QWORD PTR[16+rsp]
mov r11,QWORD PTR[24+rsp]
mov r12,QWORD PTR[32+rsp]
mov r13,QWORD PTR[40+rsp]
mov r14,QWORD PTR[48+rsp]
mov r15,QWORD PTR[56+rsp]
call __rsaz_512_reduce
add r8,QWORD PTR[64+rsp]
adc r9,QWORD PTR[72+rsp]
adc r10,QWORD PTR[80+rsp]
adc r11,QWORD PTR[88+rsp]
adc r12,QWORD PTR[96+rsp]
adc r13,QWORD PTR[104+rsp]
adc r14,QWORD PTR[112+rsp]
adc r15,QWORD PTR[120+rsp]
sbb rcx,rcx
call __rsaz_512_subtract
mov rdx,r8
mov rax,r9
mov r8d,DWORD PTR[((128+8))+rsp]
mov rsi,rdi
dec r8d
jnz $L$oop_sqr
lea rax,QWORD PTR[((128+24+48))+rsp]
mov r15,QWORD PTR[((-48))+rax]
mov r14,QWORD PTR[((-40))+rax]
mov r13,QWORD PTR[((-32))+rax]
mov r12,QWORD PTR[((-24))+rax]
mov rbp,QWORD PTR[((-16))+rax]
mov rbx,QWORD PTR[((-8))+rax]
lea rsp,QWORD PTR[rax]
$L$sqr_epilogue::
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_rsaz_512_sqr::
rsaz_512_sqr ENDP
PUBLIC rsaz_512_mul
ALIGN 32
rsaz_512_mul PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_rsaz_512_mul::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD PTR[40+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
sub rsp,128+24
$L$mul_body::
DB 102,72,15,110,199
DB 102,72,15,110,201
mov QWORD PTR[128+rsp],r8
mov rbx,QWORD PTR[rdx]
mov rbp,rdx
call __rsaz_512_mul
DB 102,72,15,126,199
DB 102,72,15,126,205
mov r8,QWORD PTR[rsp]
mov r9,QWORD PTR[8+rsp]
mov r10,QWORD PTR[16+rsp]
mov r11,QWORD PTR[24+rsp]
mov r12,QWORD PTR[32+rsp]
mov r13,QWORD PTR[40+rsp]
mov r14,QWORD PTR[48+rsp]
mov r15,QWORD PTR[56+rsp]
call __rsaz_512_reduce
add r8,QWORD PTR[64+rsp]
adc r9,QWORD PTR[72+rsp]
adc r10,QWORD PTR[80+rsp]
adc r11,QWORD PTR[88+rsp]
adc r12,QWORD PTR[96+rsp]
adc r13,QWORD PTR[104+rsp]
adc r14,QWORD PTR[112+rsp]
adc r15,QWORD PTR[120+rsp]
sbb rcx,rcx
call __rsaz_512_subtract
lea rax,QWORD PTR[((128+24+48))+rsp]
mov r15,QWORD PTR[((-48))+rax]
mov r14,QWORD PTR[((-40))+rax]
mov r13,QWORD PTR[((-32))+rax]
mov r12,QWORD PTR[((-24))+rax]
mov rbp,QWORD PTR[((-16))+rax]
mov rbx,QWORD PTR[((-8))+rax]
lea rsp,QWORD PTR[rax]
$L$mul_epilogue::
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_rsaz_512_mul::
rsaz_512_mul ENDP
PUBLIC rsaz_512_mul_gather4
ALIGN 32
rsaz_512_mul_gather4 PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_rsaz_512_mul_gather4::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD PTR[40+rsp]
mov r9,QWORD PTR[48+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
mov r9d,r9d
sub rsp,128+24
$L$mul_gather4_body::
mov eax,DWORD PTR[64+r9*4+rdx]
DB 102,72,15,110,199
mov ebx,DWORD PTR[r9*4+rdx]
DB 102,72,15,110,201
mov QWORD PTR[128+rsp],r8
shl rax,32
or rbx,rax
mov rax,QWORD PTR[rsi]
mov rcx,QWORD PTR[8+rsi]
lea rbp,QWORD PTR[128+r9*4+rdx]
mul rbx
mov QWORD PTR[rsp],rax
mov rax,rcx
mov r8,rdx
mul rbx
movd xmm4,DWORD PTR[rbp]
add r8,rax
mov rax,QWORD PTR[16+rsi]
mov r9,rdx
adc r9,0
mul rbx
movd xmm5,DWORD PTR[64+rbp]
add r9,rax
mov rax,QWORD PTR[24+rsi]
mov r10,rdx
adc r10,0
mul rbx
pslldq xmm5,4
add r10,rax
mov rax,QWORD PTR[32+rsi]
mov r11,rdx
adc r11,0
mul rbx
por xmm4,xmm5
add r11,rax
mov rax,QWORD PTR[40+rsi]
mov r12,rdx
adc r12,0
mul rbx
add r12,rax
mov rax,QWORD PTR[48+rsi]
mov r13,rdx
adc r13,0
mul rbx
lea rbp,QWORD PTR[128+rbp]
add r13,rax
mov rax,QWORD PTR[56+rsi]
mov r14,rdx
adc r14,0
mul rbx
DB 102,72,15,126,227
add r14,rax
mov rax,QWORD PTR[rsi]
mov r15,rdx
adc r15,0
lea rdi,QWORD PTR[8+rsp]
mov ecx,7
jmp $L$oop_mul_gather
ALIGN 32
$L$oop_mul_gather::
mul rbx
add r8,rax
mov rax,QWORD PTR[8+rsi]
mov QWORD PTR[rdi],r8
mov r8,rdx
adc r8,0
mul rbx
movd xmm4,DWORD PTR[rbp]
add r9,rax
mov rax,QWORD PTR[16+rsi]
adc rdx,0
add r8,r9
mov r9,rdx
adc r9,0
mul rbx
movd xmm5,DWORD PTR[64+rbp]
add r10,rax
mov rax,QWORD PTR[24+rsi]
adc rdx,0
add r9,r10
mov r10,rdx
adc r10,0
mul rbx
pslldq xmm5,4
add r11,rax
mov rax,QWORD PTR[32+rsi]
adc rdx,0
add r10,r11
mov r11,rdx
adc r11,0
mul rbx
por xmm4,xmm5
add r12,rax
mov rax,QWORD PTR[40+rsi]
adc rdx,0
add r11,r12
mov r12,rdx
adc r12,0
mul rbx
add r13,rax
mov rax,QWORD PTR[48+rsi]
adc rdx,0
add r12,r13
mov r13,rdx
adc r13,0
mul rbx
add r14,rax
mov rax,QWORD PTR[56+rsi]
adc rdx,0
add r13,r14
mov r14,rdx
adc r14,0
mul rbx
DB 102,72,15,126,227
add r15,rax
mov rax,QWORD PTR[rsi]
adc rdx,0
add r14,r15
mov r15,rdx
adc r15,0
lea rbp,QWORD PTR[128+rbp]
lea rdi,QWORD PTR[8+rdi]
dec ecx
jnz $L$oop_mul_gather
mov QWORD PTR[rdi],r8
mov QWORD PTR[8+rdi],r9
mov QWORD PTR[16+rdi],r10
mov QWORD PTR[24+rdi],r11
mov QWORD PTR[32+rdi],r12
mov QWORD PTR[40+rdi],r13
mov QWORD PTR[48+rdi],r14
mov QWORD PTR[56+rdi],r15
DB 102,72,15,126,199
DB 102,72,15,126,205
mov r8,QWORD PTR[rsp]
mov r9,QWORD PTR[8+rsp]
mov r10,QWORD PTR[16+rsp]
mov r11,QWORD PTR[24+rsp]
mov r12,QWORD PTR[32+rsp]
mov r13,QWORD PTR[40+rsp]
mov r14,QWORD PTR[48+rsp]
mov r15,QWORD PTR[56+rsp]
call __rsaz_512_reduce
add r8,QWORD PTR[64+rsp]
adc r9,QWORD PTR[72+rsp]
adc r10,QWORD PTR[80+rsp]
adc r11,QWORD PTR[88+rsp]
adc r12,QWORD PTR[96+rsp]
adc r13,QWORD PTR[104+rsp]
adc r14,QWORD PTR[112+rsp]
adc r15,QWORD PTR[120+rsp]
sbb rcx,rcx
call __rsaz_512_subtract
lea rax,QWORD PTR[((128+24+48))+rsp]
mov r15,QWORD PTR[((-48))+rax]
mov r14,QWORD PTR[((-40))+rax]
mov r13,QWORD PTR[((-32))+rax]
mov r12,QWORD PTR[((-24))+rax]
mov rbp,QWORD PTR[((-16))+rax]
mov rbx,QWORD PTR[((-8))+rax]
lea rsp,QWORD PTR[rax]
$L$mul_gather4_epilogue::
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_rsaz_512_mul_gather4::
rsaz_512_mul_gather4 ENDP
PUBLIC rsaz_512_mul_scatter4
ALIGN 32
rsaz_512_mul_scatter4 PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_rsaz_512_mul_scatter4::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD PTR[40+rsp]
mov r9,QWORD PTR[48+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
mov r9d,r9d
sub rsp,128+24
$L$mul_scatter4_body::
lea r8,QWORD PTR[r9*4+r8]
DB 102,72,15,110,199
DB 102,72,15,110,202
DB 102,73,15,110,208
mov QWORD PTR[128+rsp],rcx
mov rbp,rdi
mov rbx,QWORD PTR[rdi]
call __rsaz_512_mul
DB 102,72,15,126,199
DB 102,72,15,126,205
mov r8,QWORD PTR[rsp]
mov r9,QWORD PTR[8+rsp]
mov r10,QWORD PTR[16+rsp]
mov r11,QWORD PTR[24+rsp]
mov r12,QWORD PTR[32+rsp]
mov r13,QWORD PTR[40+rsp]
mov r14,QWORD PTR[48+rsp]
mov r15,QWORD PTR[56+rsp]
call __rsaz_512_reduce
add r8,QWORD PTR[64+rsp]
adc r9,QWORD PTR[72+rsp]
adc r10,QWORD PTR[80+rsp]
adc r11,QWORD PTR[88+rsp]
adc r12,QWORD PTR[96+rsp]
adc r13,QWORD PTR[104+rsp]
adc r14,QWORD PTR[112+rsp]
adc r15,QWORD PTR[120+rsp]
DB 102,72,15,126,214
sbb rcx,rcx
call __rsaz_512_subtract
mov DWORD PTR[rsi],r8d
shr r8,32
mov DWORD PTR[128+rsi],r9d
shr r9,32
mov DWORD PTR[256+rsi],r10d
shr r10,32
mov DWORD PTR[384+rsi],r11d
shr r11,32
mov DWORD PTR[512+rsi],r12d
shr r12,32
mov DWORD PTR[640+rsi],r13d
shr r13,32
mov DWORD PTR[768+rsi],r14d
shr r14,32
mov DWORD PTR[896+rsi],r15d
shr r15,32
mov DWORD PTR[64+rsi],r8d
mov DWORD PTR[192+rsi],r9d
mov DWORD PTR[320+rsi],r10d
mov DWORD PTR[448+rsi],r11d
mov DWORD PTR[576+rsi],r12d
mov DWORD PTR[704+rsi],r13d
mov DWORD PTR[832+rsi],r14d
mov DWORD PTR[960+rsi],r15d
lea rax,QWORD PTR[((128+24+48))+rsp]
mov r15,QWORD PTR[((-48))+rax]
mov r14,QWORD PTR[((-40))+rax]
mov r13,QWORD PTR[((-32))+rax]
mov r12,QWORD PTR[((-24))+rax]
mov rbp,QWORD PTR[((-16))+rax]
mov rbx,QWORD PTR[((-8))+rax]
lea rsp,QWORD PTR[rax]
$L$mul_scatter4_epilogue::
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_rsaz_512_mul_scatter4::
rsaz_512_mul_scatter4 ENDP
PUBLIC rsaz_512_mul_by_one
ALIGN 32
rsaz_512_mul_by_one PROC PUBLIC
mov QWORD PTR[8+rsp],rdi ;WIN64 prologue
mov QWORD PTR[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_rsaz_512_mul_by_one::
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
push rbx
push rbp
push r12
push r13
push r14
push r15
sub rsp,128+24
$L$mul_by_one_body::
mov rbp,rdx
mov QWORD PTR[128+rsp],rcx
mov r8,QWORD PTR[rsi]
pxor xmm0,xmm0
mov r9,QWORD PTR[8+rsi]
mov r10,QWORD PTR[16+rsi]
mov r11,QWORD PTR[24+rsi]
mov r12,QWORD PTR[32+rsi]
mov r13,QWORD PTR[40+rsi]
mov r14,QWORD PTR[48+rsi]
mov r15,QWORD PTR[56+rsi]
movdqa XMMWORD PTR[rsp],xmm0
movdqa XMMWORD PTR[16+rsp],xmm0
movdqa XMMWORD PTR[32+rsp],xmm0
movdqa XMMWORD PTR[48+rsp],xmm0
movdqa XMMWORD PTR[64+rsp],xmm0
movdqa XMMWORD PTR[80+rsp],xmm0
movdqa XMMWORD PTR[96+rsp],xmm0
call __rsaz_512_reduce
mov QWORD PTR[rdi],r8
mov QWORD PTR[8+rdi],r9
mov QWORD PTR[16+rdi],r10
mov QWORD PTR[24+rdi],r11
mov QWORD PTR[32+rdi],r12
mov QWORD PTR[40+rdi],r13
mov QWORD PTR[48+rdi],r14
mov QWORD PTR[56+rdi],r15
lea rax,QWORD PTR[((128+24+48))+rsp]
mov r15,QWORD PTR[((-48))+rax]
mov r14,QWORD PTR[((-40))+rax]
mov r13,QWORD PTR[((-32))+rax]
mov r12,QWORD PTR[((-24))+rax]
mov rbp,QWORD PTR[((-16))+rax]
mov rbx,QWORD PTR[((-8))+rax]
lea rsp,QWORD PTR[rax]
$L$mul_by_one_epilogue::
mov rdi,QWORD PTR[8+rsp] ;WIN64 epilogue
mov rsi,QWORD PTR[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_rsaz_512_mul_by_one::
rsaz_512_mul_by_one ENDP
ALIGN 32
__rsaz_512_reduce PROC PRIVATE
mov rbx,r8
imul rbx,QWORD PTR[((128+8))+rsp]
mov rax,QWORD PTR[rbp]
mov ecx,8
jmp $L$reduction_loop
ALIGN 32
$L$reduction_loop::
mul rbx
mov rax,QWORD PTR[8+rbp]
neg r8
mov r8,rdx
adc r8,0
mul rbx
add r9,rax
mov rax,QWORD PTR[16+rbp]
adc rdx,0
add r8,r9
mov r9,rdx
adc r9,0
mul rbx
add r10,rax
mov rax,QWORD PTR[24+rbp]
adc rdx,0
add r9,r10
mov r10,rdx
adc r10,0
mul rbx
add r11,rax
mov rax,QWORD PTR[32+rbp]
adc rdx,0
add r10,r11
mov rsi,QWORD PTR[((128+8))+rsp]
adc rdx,0
mov r11,rdx
mul rbx
add r12,rax
mov rax,QWORD PTR[40+rbp]
adc rdx,0
imul rsi,r8
add r11,r12
mov r12,rdx
adc r12,0
mul rbx
add r13,rax
mov rax,QWORD PTR[48+rbp]
adc rdx,0
add r12,r13
mov r13,rdx
adc r13,0
mul rbx
add r14,rax
mov rax,QWORD PTR[56+rbp]
adc rdx,0
add r13,r14
mov r14,rdx
adc r14,0
mul rbx
mov rbx,rsi
add r15,rax
mov rax,QWORD PTR[rbp]
adc rdx,0
add r14,r15
mov r15,rdx
adc r15,0
dec ecx
jne $L$reduction_loop
DB 0F3h,0C3h ;repret
__rsaz_512_reduce ENDP
ALIGN 32
__rsaz_512_subtract PROC PRIVATE
mov QWORD PTR[rdi],r8
mov QWORD PTR[8+rdi],r9
mov QWORD PTR[16+rdi],r10
mov QWORD PTR[24+rdi],r11
mov QWORD PTR[32+rdi],r12
mov QWORD PTR[40+rdi],r13
mov QWORD PTR[48+rdi],r14
mov QWORD PTR[56+rdi],r15
mov r8,QWORD PTR[rbp]
mov r9,QWORD PTR[8+rbp]
neg r8
not r9
and r8,rcx
mov r10,QWORD PTR[16+rbp]
and r9,rcx
not r10
mov r11,QWORD PTR[24+rbp]
and r10,rcx
not r11
mov r12,QWORD PTR[32+rbp]
and r11,rcx
not r12
mov r13,QWORD PTR[40+rbp]
and r12,rcx
not r13
mov r14,QWORD PTR[48+rbp]
and r13,rcx
not r14
mov r15,QWORD PTR[56+rbp]
and r14,rcx
not r15
and r15,rcx
add r8,QWORD PTR[rdi]
adc r9,QWORD PTR[8+rdi]
adc r10,QWORD PTR[16+rdi]
adc r11,QWORD PTR[24+rdi]
adc r12,QWORD PTR[32+rdi]
adc r13,QWORD PTR[40+rdi]
adc r14,QWORD PTR[48+rdi]
adc r15,QWORD PTR[56+rdi]
mov QWORD PTR[rdi],r8
mov QWORD PTR[8+rdi],r9
mov QWORD PTR[16+rdi],r10
mov QWORD PTR[24+rdi],r11
mov QWORD PTR[32+rdi],r12
mov QWORD PTR[40+rdi],r13
mov QWORD PTR[48+rdi],r14
mov QWORD PTR[56+rdi],r15
DB 0F3h,0C3h ;repret
__rsaz_512_subtract ENDP
ALIGN 32
__rsaz_512_mul PROC PRIVATE
lea rdi,QWORD PTR[8+rsp]
mov rax,QWORD PTR[rsi]
mul rbx
mov QWORD PTR[rdi],rax
mov rax,QWORD PTR[8+rsi]
mov r8,rdx
mul rbx
add r8,rax
mov rax,QWORD PTR[16+rsi]
mov r9,rdx
adc r9,0
mul rbx
add r9,rax
mov rax,QWORD PTR[24+rsi]
mov r10,rdx
adc r10,0
mul rbx
add r10,rax
mov rax,QWORD PTR[32+rsi]
mov r11,rdx
adc r11,0
mul rbx
add r11,rax
mov rax,QWORD PTR[40+rsi]
mov r12,rdx
adc r12,0
mul rbx
add r12,rax
mov rax,QWORD PTR[48+rsi]
mov r13,rdx
adc r13,0
mul rbx
add r13,rax
mov rax,QWORD PTR[56+rsi]
mov r14,rdx
adc r14,0
mul rbx
add r14,rax
mov rax,QWORD PTR[rsi]
mov r15,rdx
adc r15,0
lea rbp,QWORD PTR[8+rbp]
lea rdi,QWORD PTR[8+rdi]
mov ecx,7
jmp $L$oop_mul
ALIGN 32
$L$oop_mul::
mov rbx,QWORD PTR[rbp]
mul rbx
add r8,rax
mov rax,QWORD PTR[8+rsi]
mov QWORD PTR[rdi],r8
mov r8,rdx
adc r8,0
mul rbx
add r9,rax
mov rax,QWORD PTR[16+rsi]
adc rdx,0
add r8,r9
mov r9,rdx
adc r9,0
mul rbx
add r10,rax
mov rax,QWORD PTR[24+rsi]
adc rdx,0
add r9,r10
mov r10,rdx
adc r10,0
mul rbx
add r11,rax
mov rax,QWORD PTR[32+rsi]
adc rdx,0
add r10,r11
mov r11,rdx
adc r11,0
mul rbx
add r12,rax
mov rax,QWORD PTR[40+rsi]
adc rdx,0
add r11,r12
mov r12,rdx
adc r12,0
mul rbx
add r13,rax
mov rax,QWORD PTR[48+rsi]
adc rdx,0
add r12,r13
mov r13,rdx
adc r13,0
mul rbx
add r14,rax
mov rax,QWORD PTR[56+rsi]
adc rdx,0
add r13,r14
mov r14,rdx
lea rbp,QWORD PTR[8+rbp]
adc r14,0
mul rbx
add r15,rax
mov rax,QWORD PTR[rsi]
adc rdx,0
add r14,r15
mov r15,rdx
adc r15,0
lea rdi,QWORD PTR[8+rdi]
dec ecx
jnz $L$oop_mul
mov QWORD PTR[rdi],r8
mov QWORD PTR[8+rdi],r9
mov QWORD PTR[16+rdi],r10
mov QWORD PTR[24+rdi],r11
mov QWORD PTR[32+rdi],r12
mov QWORD PTR[40+rdi],r13
mov QWORD PTR[48+rdi],r14
mov QWORD PTR[56+rdi],r15
DB 0F3h,0C3h ;repret
__rsaz_512_mul ENDP
PUBLIC rsaz_512_scatter4
ALIGN 16
rsaz_512_scatter4 PROC PUBLIC
lea rcx,QWORD PTR[r8*4+rcx]
mov r9d,8
jmp $L$oop_scatter
ALIGN 16
$L$oop_scatter::
mov rax,QWORD PTR[rdx]
lea rdx,QWORD PTR[8+rdx]
mov DWORD PTR[rcx],eax
shr rax,32
mov DWORD PTR[64+rcx],eax
lea rcx,QWORD PTR[128+rcx]
dec r9d
jnz $L$oop_scatter
DB 0F3h,0C3h ;repret
rsaz_512_scatter4 ENDP
PUBLIC rsaz_512_gather4
ALIGN 16
rsaz_512_gather4 PROC PUBLIC
lea rdx,QWORD PTR[r8*4+rdx]
mov r9d,8
jmp $L$oop_gather
ALIGN 16
$L$oop_gather::
mov eax,DWORD PTR[rdx]
mov r8d,DWORD PTR[64+rdx]
lea rdx,QWORD PTR[128+rdx]
shl r8,32
or rax,r8
mov QWORD PTR[rcx],rax
lea rcx,QWORD PTR[8+rcx]
dec r9d
jnz $L$oop_gather
DB 0F3h,0C3h ;repret
rsaz_512_gather4 ENDP
EXTERN __imp_RtlVirtualUnwind:NEAR
ALIGN 16
se_handler PROC PRIVATE
push rsi
push rdi
push rbx
push rbp
push r12
push r13
push r14
push r15
pushfq
sub rsp,64
mov rax,QWORD PTR[120+r8]
mov rbx,QWORD PTR[248+r8]
mov rsi,QWORD PTR[8+r9]
mov r11,QWORD PTR[56+r9]
mov r10d,DWORD PTR[r11]
lea r10,QWORD PTR[r10*1+rsi]
cmp rbx,r10
jb $L$common_seh_tail
mov rax,QWORD PTR[152+r8]
mov r10d,DWORD PTR[4+r11]
lea r10,QWORD PTR[r10*1+rsi]
cmp rbx,r10
jae $L$common_seh_tail
lea rax,QWORD PTR[((128+24+48))+rax]
mov rbx,QWORD PTR[((-8))+rax]
mov rbp,QWORD PTR[((-16))+rax]
mov r12,QWORD PTR[((-24))+rax]
mov r13,QWORD PTR[((-32))+rax]
mov r14,QWORD PTR[((-40))+rax]
mov r15,QWORD PTR[((-48))+rax]
mov QWORD PTR[144+r8],rbx
mov QWORD PTR[160+r8],rbp
mov QWORD PTR[216+r8],r12
mov QWORD PTR[224+r8],r13
mov QWORD PTR[232+r8],r14
mov QWORD PTR[240+r8],r15
$L$common_seh_tail::
mov rdi,QWORD PTR[8+rax]
mov rsi,QWORD PTR[16+rax]
mov QWORD PTR[152+r8],rax
mov QWORD PTR[168+r8],rsi
mov QWORD PTR[176+r8],rdi
mov rdi,QWORD PTR[40+r9]
mov rsi,r8
mov ecx,154
DD 0a548f3fch
mov rsi,r9
xor rcx,rcx
mov rdx,QWORD PTR[8+rsi]
mov r8,QWORD PTR[rsi]
mov r9,QWORD PTR[16+rsi]
mov r10,QWORD PTR[40+rsi]
lea r11,QWORD PTR[56+rsi]
lea r12,QWORD PTR[24+rsi]
mov QWORD PTR[32+rsp],r10
mov QWORD PTR[40+rsp],r11
mov QWORD PTR[48+rsp],r12
mov QWORD PTR[56+rsp],rcx
call QWORD PTR[__imp_RtlVirtualUnwind]
mov eax,1
add rsp,64
popfq
pop r15
pop r14
pop r13
pop r12
pop rbp
pop rbx
pop rdi
pop rsi
DB 0F3h,0C3h ;repret
se_handler ENDP
.text$ ENDS
.pdata SEGMENT READONLY ALIGN(4)
ALIGN 4
DD imagerel $L$SEH_begin_rsaz_512_sqr
DD imagerel $L$SEH_end_rsaz_512_sqr
DD imagerel $L$SEH_info_rsaz_512_sqr
DD imagerel $L$SEH_begin_rsaz_512_mul
DD imagerel $L$SEH_end_rsaz_512_mul
DD imagerel $L$SEH_info_rsaz_512_mul
DD imagerel $L$SEH_begin_rsaz_512_mul_gather4
DD imagerel $L$SEH_end_rsaz_512_mul_gather4
DD imagerel $L$SEH_info_rsaz_512_mul_gather4
DD imagerel $L$SEH_begin_rsaz_512_mul_scatter4
DD imagerel $L$SEH_end_rsaz_512_mul_scatter4
DD imagerel $L$SEH_info_rsaz_512_mul_scatter4
DD imagerel $L$SEH_begin_rsaz_512_mul_by_one
DD imagerel $L$SEH_end_rsaz_512_mul_by_one
DD imagerel $L$SEH_info_rsaz_512_mul_by_one
.pdata ENDS
.xdata SEGMENT READONLY ALIGN(8)
ALIGN 8
$L$SEH_info_rsaz_512_sqr::
DB 9,0,0,0
DD imagerel se_handler
DD imagerel $L$sqr_body,imagerel $L$sqr_epilogue
$L$SEH_info_rsaz_512_mul::
DB 9,0,0,0
DD imagerel se_handler
DD imagerel $L$mul_body,imagerel $L$mul_epilogue
$L$SEH_info_rsaz_512_mul_gather4::
DB 9,0,0,0
DD imagerel se_handler
DD imagerel $L$mul_gather4_body,imagerel $L$mul_gather4_epilogue
$L$SEH_info_rsaz_512_mul_scatter4::
DB 9,0,0,0
DD imagerel se_handler
DD imagerel $L$mul_scatter4_body,imagerel $L$mul_scatter4_epilogue
$L$SEH_info_rsaz_512_mul_by_one::
DB 9,0,0,0
DD imagerel se_handler
DD imagerel $L$mul_by_one_body,imagerel $L$mul_by_one_epilogue
.xdata ENDS
END
| dkoontz/nodegit | vendor/openssl/asm_obsolete/x64-win32-masm/bn/rsaz-x86_64.asm | Assembly | mit | 22,063 |
format elf64
use32
section '.multiboot'
Multiboot:
.magic:
dd 0x1BADB002
.flags:
dd 0x00000003
.checksum:
dd -(0x1BADB005)
section '.rodata'
Gdt:
.pointer:
dw .userData + 7 - $
dd $ - 2
dw 0x0
.kernelCode:
dd 0x00000000
dd 0x00209A00
.kernelData:
dd 0x00000000
dd 0x00009200
.userCode:
dd 0x00000000
dd 0x0020FA00
.userData:
dd 0x00000000
dd 0x0000F200
section '.bss' writeable
PageTables:
.pml4:
rb 4096
.pdp:
rb 4096
.pd:
rb 4096
KernelStack:
rb 65535
.base:
section '.text' executable
public _start
_start:
.init:
mov esp, KernelStack.base
push ebx
.checkCpu:
mov eax, 0x1
cpuid
test ecx, (1 shl 20) or (1 shl 12)
jz .error
.enablePaging:
mov eax, PageTables.pdp
mov ebx, PageTables.pd
or eax, 0x03
or ebx, 0x3
mov [PageTables.pml4], eax
mov [PageTables.pdp], ebx
xor ecx, ecx
@@:
mov eax, 0x200000
mul ecx
or eax, 0x83
mov [PageTables.pd + ecx * 8], eax
add ecx, 1
cmp ecx, 0x200
jne @b
.enableLM:
mov ecx, 0xC0000080
rdmsr
or eax, (1 shl 8)
wrmsr
mov ebx, PageTables.pml4
mov cr3, ebx
mov ecx, cr4
or ecx, (1 shl 5)
mov cr4, ecx
mov eax, cr0
or eax, (1 shl 31)
mov cr0, eax
lgdt [Gdt.pointer]
jmp 0x8:lm
.error:
jmp $
extrn kmain
use64
lm:
mov ax, 0x10
mov ds, ax
mov es, ax
mov ss, ax
mov gs, ax
mov fs, ax
pop rax
jmp kmain
| Lowl3v3l/myos_64 | arch/x86_64/boot/start.asm | Assembly | mit | 1,523 |
; label_name
label0 db "System", 0x00, " "
label1 db "User", 0x00, " "
label2 db "BRASS", 0x00, " "
label3 db "", 0x00, " "
label4 db "", 0x00, " "
label5 db "", 0x00, " "
label6 db "", 0x00, " "
label7 db "", 0x00, " "
label8 db "", 0x00, " "
label9 db "", 0x00, " "
labelA db "", 0x00, " "
labelB db "", 0x00, " "
labelC db "", 0x00, " "
labelD db "", 0x00, " "
labelE db "", 0x00, " "
labelF db "", 0x00, " "
; label_num next size file_name (11 char)
file0 db 0x01, 0x00, 0x01, 0x04, "kernel ", 0x00
file1 db 0x03, 0x00, 0xFF, 0x01, "shell ", 0x00
file2 db 0x02, 0x00, 0xFF, 0x01, "user1 ", 0x00
file3 db 0x02, 0x00, 0xFF, 0x01, "user2 ", 0x00
file4 db 0x00, 0x00, 0x00, 0x00, " ", 0x00
file5 db 0x00, 0x00, 0x00, 0x00, " ", 0x00
file6 db 0x00, 0x00, 0x00, 0x00, " ", 0x00
file7 db 0x00, 0x00, 0x00, 0x00, " ", 0x00
file8 db 0x00, 0x00, 0x00, 0x00, " ", 0x00
file9 db 0x00, 0x00, 0x00, 0x00, " ", 0x00
fileA db 0x00, 0x00, 0x00, 0x00, " ", 0x00
fileB db 0x00, 0x00, 0x00, 0x00, " ", 0x00
fileC db 0x00, 0x00, 0x00, 0x00, " ", 0x00
fileD db 0x00, 0x00, 0x00, 0x00, " ", 0x00
fileE db 0x00, 0x00, 0x00, 0x00, " ", 0x00
fileF db 0x00, 0x00, 0x00, 0x00, " ", 0x00
;file0 db 0x01, 0x00, 0x01, 0x04, "kernel", 0x00, " "
;file1 db 0x03, 0x00, 0xFF, 0x01, "shell", 0x00, " "
;file2 db 0x02, 0x00, 0xFF, 0x01, "user1", 0x00, " "
;file3 db 0x02, 0x00, 0xFF, 0x01, "user2", 0x00, " "
;file4 db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;file5 db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;file6 db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;file7 db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;file8 db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;file9 db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;fileA db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;fileB db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;fileC db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;fileD db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;fileE db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
;fileF db 0x00, 0x00, 0x00, 0x00, "", 0x00, " "
db 0x02, 0x03, 0xFF
TIMES 508-($-$$) DB 0
tmp dw 0x0000, 0xAA55
| jasonmel/jasonmel-os | src/ftable.asm | Assembly | mit | 2,401 |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; WriteDr2.Asm
;
; Abstract:
;
; AsmWriteDr2 function
;
; Notes:
;
;------------------------------------------------------------------------------
.code
;------------------------------------------------------------------------------
; UINTN
; EFIAPI
; AsmWriteDr2 (
; IN UINTN Value
; );
;------------------------------------------------------------------------------
AsmWriteDr2 PROC
mov dr2, rcx
mov rax, rcx
ret
AsmWriteDr2 ENDP
END
| tenpoku1000/UEFI_SecureBoot | src/lib/external/BSD/UDK/MdePkg/Library/BaseLib/X64/WriteDr2.asm | Assembly | mit | 1,061 |
;/**********************************************************
;ChaiOS 0.05 Copyright (C) 2012-2015 Nathaniel Cleland
;Licensed under the ChaiOS License
;See License for full details
;
;Project: Hal
;File: SMPasm32.asm
;Path: C:\Users\Nathaniel\Documents\Visual Studio 2013\Projects\ChaiOS\Hal\SMPasm32.asm
;Created by Nathaniel on 23/12/2015 at 21:42
;
;Description: SMP Startup routine for x86 Multiprocessing
;**********************************************************/
BITS 32
section .text
%define LOADED_BASE 0
%define ACTUAL_BASE 0x1000
extern _SMP_CPU_entry
extern _thread_exit
extern _thread_eoi_helper
global _SMP_StartupRoutine
_SMP_StartupRoutine:
cli
mov ax, cs
mov ds, ax
mov es, ax
mov ss, ax
;Forcing size overrides
;Base of this code module
db 0x66 ;Size override
mov ebx, _SMP_StartupRoutine
db 0x66
mov ecx, .flat
db 0x66
sub ecx, ebx
db 0x66
add ecx, ACTUAL_BASE
db 0x66
mov edx, .jump_flat
db 0x66
sub edx, ebx
db 0x66
add edx, LOADED_BASE+1
db 0x67
mov [edx], ecx
;Jump from segmented to flat
.jump_flat:
db 0xea
dw 0x0, 0x0
.flat:
mov ax, cs
mov ds, ax
mov es, ax
mov ss, ax
;Load GDT address
db 0x66 ;Size override
mov eax, temp_gdt_ent
;Fixup GDT address
db 0x66 ;Size override
sub eax, ebx
db 0x66 ;Size override
add eax, ACTUAL_BASE
;Fixup address of GDT
db 0x66
mov ecx, temp_gdt
db 0x66
sub ecx, ebx
db 0x66
add ecx, ACTUAL_BASE
db 0x66, 0x67
mov [eax+2], ecx
;Load the GDT
.lgdt:
db 0x67
lgdt [eax]
;Setup address of next
db 0x66
mov ecx, .next
db 0x66
sub ecx, ebx
db 0x66
add ecx, ACTUAL_BASE
;Setup address of jump to PMODE
db 0x66
mov edx, .jump
db 0x66
sub edx, ebx
db 0x66
add edx, ACTUAL_BASE+1
;Make jump to pmode
db 0x67
mov [edx], ecx
;Setup CR3
db 0x66
mov edx, _cr3_val
db 0x66
sub edx, ebx
db 0x66
add edx, ACTUAL_BASE
db 0x66, 0x67
mov ecx, [edx]
mov cr3, ecx
;Setup CR0
mov eax, cr0
db 0x66
or eax, 0x80000001
mov cr0, eax
.jump:
db 0xea
dw 0x0, 0x8
.next:
BITS 32
mov ax, 0x10
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
lgdt [_gdt_addr] ;Now we're 32 bit, we can go into the kernel address space
mov eax, .in_kernel_addr
jmp eax
.in_kernel_addr:
;Setup IDT
lidt [_idt_addr]
;Setup CR4
mov eax, [_cr4_val]
mov cr4, eax
;Find the local APIC ID
mov eax, [_mapped_lapic]
mov ecx, [eax+0x20] ;LAPIC ID Register
shr ecx, 24 ;This puts the ID (which is in high bits), to the value
;Now we synchronise with the kernel
.syncloop:
mov eax, [_kernel_sync]
cmp eax, 0
je .syncloop
test eax, 1
jz .syncloop
.cpu_test:
mov ebx, eax
shr ebx, 8
and ebx, 0xff
cmp ebx, ecx
jnz .syncloop
;OK, this is us. We have an instruction
mov ebx, eax
shr ebx, 16
;and ebx, 0xFFFF ;Not neccessary
;EBX now contains the instruction
cmp ebx, 1
jne .syncloop
mov eax, 2
mov [_kernel_sync], eax
;Get some initialisation data
.dataloop:
mov eax, [_kernel_sync_ptr]
cmp eax, 0
je .dataloop
mov ebx, [eax]
mov esp, ebx
mov DWORD[_kernel_sync_ptr], 0
;More CPU setup
mov eax, cr0
or eax, 0x22
and eax, 0xFFFFFFF3
mov cr0, eax
;Enable our APIC (just to be safe)
mov ecx, 0x1B
rdmsr
or eax, 0x800
wrmsr
;APIC Surious interrupt register
mov eax, [_mapped_lapic]
mov ecx, 0xF0 | 0x100
mov [eax+0xF0], ecx
;APIC timer
mov ecx, 0x28 | 0x20000
mov [eax+0x320], ecx
mov ecx, 0b1010 ;Divide by 128
mov [eax+0x3E0], ecx
mov ecx, 10
mov [eax+0x380], ecx
;Enable interrupts
sti
call _SMP_CPU_entry
cli
hlt
align 4
global _gdt_addr
_gdt_addr:
.len: dw 0
.base: dd 0
align 4
global _idt_addr
_idt_addr:
.len: dw 0
.base: dd 0
align 4
global _cr3_val
_cr3_val: dd 0
global _cr4_val
_cr4_val: dd 0
global _mapped_lapic
_mapped_lapic: dd 0
global _kernel_sync
_kernel_sync:
.flags: db 0
.cpu: db 0
.instruc: dw 0
global _kernel_sync_ptr
_kernel_sync_ptr:
dd 0
align 4
temp_gdt_ent:
.len: dw 0x17
.base: dd temp_gdt
align 4
temp_gdt:
dq 0
dd 0x0000FFFF, 0x00CF9A00
dd 0x0000FFFF, 0x00CF9200
global _SMP_StartupRoutine_End
_SMP_StartupRoutine_End:
cli
hlt
ret
global _scheduler_start_thread
_scheduler_start_thread:
push ebp ;Simulate stack frame with return address
push ebp
mov ebp, esp
mov eax, [ebp+24]
mov ebx, [ebp+20]
mov ecx, [ebp+16]
and ecx, 0xFFFF
mov edx, [ebp+12] ;Stack
mov gs, ax ;TLS
mov es, bx
mov ds, bx
mov eax, [ebp+8]
;Build a return address.
mov ebx, .end
push ebx
;Build a iret frame to call the stack
cmp cx, 0x8 ;Kernel?
je .no_stack_iret
push ds ;SS
push edx ;ESP
.no_stack_iret:
pushfd
pop ebx
or ebx, 1<<9 ;IF
push ebx
push ecx ;CS
push eax ;EIP
call _thread_eoi_helper
iret
.end:
call _thread_exit
jmp $
pop ebp
ret | solocle/ChaiOS | Hal/arch/i386-x64/SMPasm32.asm | Assembly | mit | 4,499 |
;******************************************************************************
;* *
;* I$$TOFS - convert a 16-bit signed integer to floating point *
;* I_TOFS v15.12.3 *
;* *
;* Copyright (c) 2000-2016 Texas Instruments Incorporated *
;* http://www.ti.com/ *
;* *
;* Redistribution and use in source and binary forms, with or without *
;* modification, are permitted provided that the following conditions *
;* are met: *
;* *
;* Redistributions of source code must retain the above copyright *
;* notice, this list of conditions and the following disclaimer. *
;* *
;* Redistributions in binary form must reproduce the above copyright *
;* notice, this list of conditions and the following disclaimer in *
;* the documentation and/or other materials provided with the *
;* distribution. *
;* *
;* Neither the name of Texas Instruments Incorporated nor the names *
;* of its contributors may be used to endorse or promote products *
;* derived from this software without specific prior written *
;* permission. *
;* *
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS *
;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *
;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR *
;* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *
;* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *
;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, *
;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *
;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
;* *
;* *
;******************************************************************************
.include "c2000asm.inc"
.if .TMS320C2700
.include "i_tofs27.inc"
.elseif .TMS320C2800
.include "i_tofs28.inc"
.endif
| gexd7127/MIT-Pico-Grid | Project/New_MG/Firmware/EVAL/c2000_15.12.3.LTS/lib/src/i_tofs.asm | Assembly | mit | 3,301 |
section .data
voijuma:
db "Tuplattava nro: " ; Viesti.
.len: equ $-voijuma ; Maaritetaan .len-labelin arvoksi voijuman pituus.
newline:
db 0Ah ; Newline.
.len equ $-newline ; Newlinen pituus.
section .bss
firstnum:
resb 1 ; Varataan tilaa kayttajasyotteelle.
result:
resb 2 ; Varataan tilaa tulokselle.
global _start
section .text
_start:
; Naytetaan ohjeviesti.
mov rax, 1
mov rdi, 1
mov rsi, voijuma ; Viestin osoite.
mov rdx, voijuma.len ; Viestin pituus.
syscall
; Hypataan numeron lukukoodiin.
mov rbx, firstnum
call _getnum
_getnum:
; Luetaan numero.
mov rax, 0 ; Read-operaatio.
mov rdx, 1 ; Merkkien maara.
mov rsi, rbx ; Tallennetaan rbx-rekisterin sisaltamaan muistiosoitteeseen.
syscall
; Validoidaan syote ja lopetetaan mikali virheellinen.
cmp byte[rsi], 48 ; Jos annettu numero on pienempi kuin 48 (ascii 0),
jl _error ; hyppaa virhekoodiin.
cmp byte[rsi], 57 ; Jos annettu numero on suurempi kuin 57 (ascii 9),
jg _error ; hyppaa virhekoodiin.
; Oli numero joten hypataan laskukoodiin.
call _calculate
_calculate:
; Suoritetaan numeron tuplaava laskuoperaatio.
mov al, [firstnum] ; Siirretaan numero al-rekisteriin.
sub al, '0' ; Muutetaan desimaaliksi poistamalla ascii-0:n verran numeroita (esim. 5: '5'-'0' = 53-48 = 5).
add al, al ; Summataan itsensa kanssa, tulos menee ax-rekisteriin.
; Koska numero voi olla yli kymmenen, kaytetaan kahden rekisterin magiaa desimaali->ascii-muunnoksessa.
mov bl, 0 ; Ensimmainen numero.
cmp ax, 9 ; Vertaillaan tulosta ja yhdeksikkoa.
jg _addone ; Ruma hack joka hoitaa homman jos tulos on yli 9.
jle _finishcalc ; Jos alle kymmenen niin jatketaan tuloksen kasittelya.
_addone:
add bl, 1 ; Lisataan ykkonen tuloksen ekaan numeroon.
sub ax, 10 ; Vahennetaan 10 tuloksesta.
jle _finishcalc ; Jatketaan tuloksen kasittelya.
_finishcalc:
add bl, '0' ; Muutetaan tuloksen eka numero ascii-muotoon.
add ax, '0' ; Muutetaan tuloksen toinen numero ascii-muotoon.
mov [result], bl ; Siirretaan tuloksen eka ascii-numero resultiin.
mov [result+1], ax ; Siirretaan tuloksen toka ascii-numero resultiin.
; Hypataan tuloksen tulostukseen.
call _showresult
_showresult:
; Naytetaan tulos.
mov rax, 1
mov rdi, 1
mov rsi, result ; Viestin osoite.
mov rdx, 2 ; Viestin pituus.
syscall
; Tulostetaan tyhja rivi.
mov rax, 1
mov rdi, 1
mov rsi, newline ; Viestin osoite.
mov rdx, newline.len ; Viestin pituus.
syscall
; Hypataan exit coden palautukseen.
call _success
_success:
; Poistutaan success exit codella.
mov rax, 60
xor rdi, rdi ; Xor itsensa kanssa on aina 0.
syscall
_error:
; Poistutaan error exit codella.
mov rax, 60
xor rdi, 65 ; 65 on Linuxin error-koodi 'data format error'.
syscall
| putsi/assembly-bungles | doubler/doubler.asm | Assembly | mit | 2,769 |
; a PE with a checked broken MANIFEST resource
; Ange Albertini, BSD LICENCE 2012-2013
%include 'consts.inc'
%include 'headers.inc'
istruc IMAGE_DATA_DIRECTORY_16
at IMAGE_DATA_DIRECTORY_16.ImportsVA, dd Import_Descriptor - IMAGEBASE
at IMAGE_DATA_DIRECTORY_16.ResourceVA, dd Directory_Entry_Resource - IMAGEBASE
iend
%include 'section_1fa.inc'
%include 'code_printf.inc'
Msg db " * a PE with an incorrect manifest type (ignored)", 0ah, 0
_d
%include 'imports_printfexitprocess.inc'
;*******************************************************************************
MYMAN equ 3 ; incorrect - this file wouldn't run if it's set to 1 or 2
LANGUAGE equ 0
Directory_Entry_Resource:
; root directory
istruc IMAGE_RESOURCE_DIRECTORY
at IMAGE_RESOURCE_DIRECTORY.NumberOfIdEntries, dw 1
iend
_resourceDirectoryEntry RT_MANIFEST, resource_directory_type
resource_directory_type:
istruc IMAGE_RESOURCE_DIRECTORY
at IMAGE_RESOURCE_DIRECTORY.NumberOfIdEntries, dw 1
iend
_resourceDirectoryEntry MYMAN, resource_directory_language
resource_directory_language:
istruc IMAGE_RESOURCE_DIRECTORY
at IMAGE_RESOURCE_DIRECTORY.NumberOfIdEntries, dw 1
iend
istruc IMAGE_RESOURCE_DIRECTORY_ENTRY
at IMAGE_RESOURCE_DIRECTORY_ENTRY.NameID, dd LANGUAGE ; name of the underneath resource
at IMAGE_RESOURCE_DIRECTORY_ENTRY.OffsetToData, dd resource_entry - Directory_Entry_Resource
iend
resource_entry:
istruc IMAGE_RESOURCE_DATA_ENTRY
at IMAGE_RESOURCE_DATA_ENTRY.OffsetToData, dd resource_data - IMAGEBASE
at IMAGE_RESOURCE_DATA_ENTRY.Size1, dd RESOURCE_SIZE
iend
resource_data:
db "<assembly xmlns='urn:schemas-microsoft-com:asm.v1' manifestVersion='1.0'>" ; broken end
RESOURCE_SIZE equ $ - resource_data
align FILEALIGN, db 0
| angea/corkami | src/PE/manifest_broken.asm | Assembly | bsd-2-clause | 1,815 |
;Testname=unoptimized; Arguments=-O0 -fbin -oalign13.bin; Files=stdout stderr align13.bin
;Testname=optimized; Arguments=-Ox -fbin -oalign13.bin; Files=stdout stderr align13.bin
; Test of non-power-of-2 alignment
bits 32
inc eax
inc eax
align 13
inc eax
inc eax
align 13
inc eax
inc eax
align 13
align 13 ;should do nothing
inc eax
inc eax
| endlessm/chromium-browser | third_party/nasm/test/align13.asm | Assembly | bsd-3-clause | 356 |
/*
Copyright Oliver Kowalke 2009.
Copyright Thomas Sailer 2013.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/****************************************************************************************
* *
* ----------------------------------------------------------------------------------
* | 0 | 1 | |
* ----------------------------------------------------------------------------------
* | 0x0 | 0x4 | |
* ----------------------------------------------------------------------------------
* | <indicator> | |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
* ----------------------------------------------------------------------------------
* | 0x8 | 0xc | 0x10 | 0x14 | 0x18 | 0x1c | 0x20 | 0x24 |
* ----------------------------------------------------------------------------------
* | SEE registers (XMM6-XMM15) |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 |
* ----------------------------------------------------------------------------------
* | 0x28 | 0x2c | 0x30 | 0x34 | 0x38 | 0x3c | 0x40 | 0x44 |
* ----------------------------------------------------------------------------------
* | SEE registers (XMM6-XMM15) |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 |
* ----------------------------------------------------------------------------------
* | 0x48 | 0x4c | 0x50 | 0x54 | 0x58 | 0x5c | 0x60 | 0x64 |
* ----------------------------------------------------------------------------------
* | SEE registers (XMM6-XMM15) |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 |
* ----------------------------------------------------------------------------------
* | 0x68 | 0x6c | 0x70 | 0x74 | 0x78 | 0x7c | 0x80 | 0x84 |
* ----------------------------------------------------------------------------------
* | SEE registers (XMM6-XMM15) |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 |
* ----------------------------------------------------------------------------------
* | 0x88 | 0x8c | 0x90 | 0x94 | 0x98 | 0x9c | 0xa0 | 0xa4 |
* ----------------------------------------------------------------------------------
* | SEE registers (XMM6-XMM15) |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 |
* ----------------------------------------------------------------------------------
* | 0xa8 | 0xac | 0xb0 | 0xb4 | 0xb8 | 0xbc | 0xc0 | 0xc4 |
* ----------------------------------------------------------------------------------
* | fc_mxcsr|fc_x87_cw| <alignment> | fbr_strg | fc_dealloc |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 |
* ----------------------------------------------------------------------------------
* | 0xc8 | 0xcc | 0xd0 | 0xd4 | 0xd8 | 0xdc | 0xe0 | 0xe4 |
* ----------------------------------------------------------------------------------
* | limit | base | R12 | R13 |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 |
* ----------------------------------------------------------------------------------
* | 0xe8 | 0xec | 0xf0 | 0xf4 | 0xf8 | 0xfc | 0x100 | 0x104 |
* ----------------------------------------------------------------------------------
* | R14 | R15 | RDI | RSI |
* ----------------------------------------------------------------------------------
* ----------------------------------------------------------------------------------
* | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 |
* ----------------------------------------------------------------------------------
* | 0x108 | 0x10c | 0x110 | 0x114 | 0x118 | 0x11c | 0x120 | 0x124 |
* ----------------------------------------------------------------------------------
* | RBX | RBP | RIP | EXIT |
* ----------------------------------------------------------------------------------
* *
* *************************************************************************************/
.file "jump_x86_64_ms_pe_gas.asm"
.text
.p2align 4,,15
.globl copp_jump_fcontext
.def copp_jump_fcontext; .scl 2; .type 32; .endef
.seh_proc copp_jump_fcontext
copp_jump_fcontext:
.seh_endprologue
pushq %rbp /* save RBP */
pushq %rbx /* save RBX */
pushq %rsi /* save RSI */
pushq %rdi /* save RDI */
pushq %r15 /* save R15 */
pushq %r14 /* save R14 */
pushq %r13 /* save R13 */
pushq %r12 /* save R12 */
/* load NT_TIB */
movq %gs:(0x30), %r10
/* save current stack base */
movq 0x08(%r10), %rax
pushq %rax
/* save current stack limit */
movq 0x10(%r10), %rax
pushq %rax
/* save current deallocation stack */
movq 0x1478(%r10), %rax
pushq %rax
/* save fiber local storage */
movq 0x18(%r10), %rax
pushq %rax
/* prepare stack for FPU */
leaq -0xa8(%rsp), %rsp
/* test for flag preserve_fpu */
testq %r9, %r9
je 1f
/* save MMX control- and status-word */
stmxcsr 0xa0(%rsp)
/* save x87 control-word */
fnstcw 0xa4(%rsp)
/* save XMM storage */
movaps %xmm6, (%rsp)
movaps %xmm7, 0x10(%rsp)
movaps %xmm8, 0x20(%rsp)
movaps %xmm9, 0x30(%rsp)
movaps %xmm10, 0x40(%rsp)
movaps %xmm11, 0x50(%rsp)
movaps %xmm12, 0x60(%rsp)
movaps %xmm13, 0x70(%rsp)
movaps %xmm14, 0x80(%rsp)
movaps %xmm15, 0x90(%rsp)
1:
/* set R10 to zero */
xorq %r10, %r10
/* set indicator */
pushq %r10
/* store RSP (pointing to context-data) in RCX */
movq %rsp, (%rcx)
/* restore RSP (pointing to context-data) from RDX */
movq %rdx, %rsp
/* load indicator */
popq %r10
/* test for flag preserve_fpu */
testq %r9, %r9
je 2f
/* restore MMX control- and status-word */
ldmxcsr 0xa0(%rsp)
/* save x87 control-word */
fldcw 0xa4(%rsp)
/* restore XMM storage */
movaps (%rsp), %xmm6
movaps 0x10(%rsp), %xmm7
movaps 0x20(%rsp), %xmm8
movaps 0x30(%rsp), %xmm9
movaps 0x40(%rsp), %xmm10
movaps 0x50(%rsp), %xmm11
movaps 0x60(%rsp), %xmm12
movaps 0x70(%rsp), %xmm13
movaps 0x80(%rsp), %xmm14
movaps 0x90(%rsp), %xmm15
2:
/* set offset of stack */
movq 0xa8, %rcx
/* test for indicator */
testq %r10, %r10
je 3f
addq 0x8, %rcx
3:
/* prepare stack for FPU */
leaq (%rsp,%rcx), %rsp
/* load NT_TIB */
movq %gs:(0x30), %r10
/* restore fiber local storage */
popq %rax
movq %rax, 0x18(%r10)
/* restore deallocation stack */
popq %rax
movq %rax, 0x1478(%r10)
/* restore stack limit */
popq %rax
movq %rax, 0x10(%r10)
/* restore stack base */
popq %rax
movq %rax, 0x8(%r10)
popq %r12 /* restore R12 */
popq %r13 /* restore R13 */
popq %r14 /* restore R14 */
popq %r15 /* restore R15 */
popq %rdi /* restore RDI */
popq %rsi /* restore RSI */
popq %rbx /* restore RBX */
popq %rbp /* restore RBP */
/* restore return-address */
popq %r10
/* use third arg as return-value after jump */
movq %r8, %rax
/* use third arg as first arg in context function */
movq %r8, %rcx
/* indirect jump to context */
jmp *%r10
.seh_endproc
| sotter/libcopp | src/libcopp/fcontext/asm/jump_x86_64_ms_pe_gas.asm | Assembly | mit | 10,027 |
.ifndef F_UART
.error "F_UART not defined!"
.endif
.ifndef F_CPU
.error "F_CPU not defined!"
.endif
; No args. F_CPU defined required
UART_init:
ldi r16, high(F_CPU/16/F_UART-1 )
out UBRRH, r16
ldi r16, low(F_CPU/16/F_UART-1)
out UBRRL, r16
ldi r16, (1<<RXEN)|(1<<TXEN)
out UCSRB, r16
; 8N1
ldi r16, (1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); ;8bit
out UCSRC, r16
ret
; r16 - byte
UART_putc:
sbis UCSRA, UDRE
rjmp UART_putc
out UDR, r16
ret
; Z - String address
UART_puts:
; Z -> r0
lpm r16, Z+
cpi r16, 0
breq UART_puts_end
rcall UART_putc
rjmp UART_puts
UART_puts_end:
ret
; r16 - byte
UART_getc:
sbis UCSRA, RXC
rjmp UART_getc
in r16, UDR
ret
| JaCzekanski/VGA_Tetris | UART.asm | Assembly | mit | 728 |
main:
MOV r0 1 ; for (var i = 1 loop setup
start_of_loop:
CMP r0 10 ; i <= 10 loop conditional
> JMP end_of_loop
; {
PRINT r0 ;
PRINT "\n" ; console.log(i);
; }
INC r0 ; i++) loop incrementer
JMP start_of_loop
end_of_loop:
PRINT "Loop complete\n" ; console.log("Loop complete")
| astrellon/moss | docs/exercises/06-looping.asm | Assembly | mit | 478 |
.686
.model flat,stdcall
option casemap:none
include .\bnlib.inc
include .\bignum.inc
.code
;;
;; copies bn to sequence of bytes
;; returns sign
;;
;_a_
bnToBytes proc uses edi esi bn:DWORD, pBytes:DWORD
mov esi,bn
mov edi,pBytes
mov ecx,[esi].BN.dwSize
shl ecx,2
lea esi,[esi].BN.dwArray[0]
rep movsb
mov eax,[esi].BN.bSigned
ret
bnToBytes endp
end
| FloydZ/Crypto-Hash | BigNum/Mod/Io/bnToBytes.asm | Assembly | mit | 361 |
assume cs:code,ds:data
data segment
cmc_out db ' $'
cmc_in db ' $'
cmc_temp db 01
cmc_t0 dw 02
data ends
code segment
start:
mov dx,data
mov ds,dx
mov ax,2
mov cmc_t0,ax
mov ah,4ch
int 21h
code ends
end start
| vysakhpr/C-Masm-Compiler | masm/8086/out.asm | Assembly | mit | 223 |
LCD_data equ P2 ;LCD Data port
LCD_rs equ P0.0 ;LCD Register Select
LCD_rw equ P0.1 ;LCD Read/Write
LCD_en equ P0.2 ;LCD Enable
LED equ P1
ORG 0000H
LJMP MAIN
ORG 000BH ;ISR address for Timer 0
INC R0 ;To keep the count of no. of times timer has overflown
RETI
ORG 200H
MAIN:
LCALL DISPLAY_MSG1
BACK:
LCALL START_TIMER
LCALL DISPLAY_MSG2
SJMP BACK
HERE: SJMP HERE
DISPLAY_MSG1:
mov P2,#00h
mov P1,#00h
;initial delay for lcd power up
acall delay
acall delay
acall lcd_init ;initialise LCD
acall delay
acall delay
acall delay
mov a,#80h ;Put cursor on first row,0 column
acall lcd_command ;send command to LCD
acall delay
mov dptr,#STR1 ;Load DPTR with sring1 Addr
acall lcd_sendstring ;call text strings sending routine
acall delay
mov a,#0C2h ;Put cursor on second row,2 column
acall lcd_command
acall delay
mov dptr,#STR2
acall lcd_sendstring
ret
;-------------starting timer----------------------------------------------------------
START_TIMER:
MOV TMOD,#01h ;Configures TMOD,(for 16 bit mode)
MOV TL0,#0
MOV TH0,#0
SETB EA
SETB ET0 ;Setting IE correctly and actions on timer overflow should be
MOV p1,#1Fh ;-Switches on LED
MOV R0,#0
SETB TR0 ;Starts Timer ()
AGAIN:jnb p1.0,AGAIN ;Wait for switch to go off.
MOV p1,#0Fh
CLR TR0 ;Clear TR0 to stop timer.
RET
;-----------Displays second msg---------------------------------------------
DISPLAY_MSG2:
mov P2,#00h
mov P1,#01h
;initial delay for lcd power up
acall delay
acall delay
acall lcd_init ;initialise LCD
acall delay
acall delay
acall delay
mov a,#81h ;Put cursor on first row,1 column
acall lcd_command ;send command to LCD
acall delay
mov dptr,#STR3 ;Load DPTR with sring1 Addr
acall lcd_sendstring ;call text strings sending routine
acall delay
mov a,#0C0h ;Put cursor on second row,0 column
acall lcd_command
acall delay
mov dptr,#STR4
acall lcd_sendstring
;-----display R0-------------------------------
MOV A,R0
lcall ASCIICONV ;Convert to ascii and display values of R0
;-----display TH0-------------------------------
MOV A,TH0
lcall ASCIICONV ;Convert to ascii and display values of TH0
;-----display TL0-------------------------------
MOV a,TL0
lcall ASCIICONV ;Convert to ascii and display values of TL0
MOV 4FH, #10 ; Delay time =5 SEC
LCALL longDelay
RET
;----------------------delay routine-----------------------------------------------------
delay:
USING 00H
PUSH PSW
PUSH AR0
PUSH AR2
mov r0,#1
loop2: mov r1,#255
loop1: djnz r1, loop1
djnz r0,loop2
POP AR2
POP AR0
POP PSW
ret
;----------------------delay routine-----------------------------------------------------
longDelay: ; this subroutine is for introducing delay
USING 0
;push registers being used in this subroutine on the stack
PUSH AR0
PUSH AR1
PUSH AR2
MOV A,4FH
MOV B,#10
MUL AB ; for calculting the number of cycle delay1 should run
MOV R0,A
delay1:
MOV R2,#200
BACK1:
MOV R1,#0FFH
BACK2:
DJNZ R1,BACK2
DJNZ R2,BACK1
DJNZ R0,delay1
;restored registers pushed
POP AR2
POP AR1
POP AR0
RET
;-------convert byte to ascii and also send the ascii values to the lcd--------------
ASCIICONV:
PUSH PSW
PUSH AR2
PUSH AR3
MOV R2,A
ANL A,#0F0h
SWAP A
MOV R3,A
SUBB A,#0Ah ;CHECK IF NIBBLE IS DIGIT OR ALPHABET
JNC ALPHA
MOV A,R3
ADD A,#30h ;ADD 30H TO CONV HEX TO ASCII
lcall lcd_senddata ;send msb in ascii
JMP NEXT
ALPHA: MOV A,R3 ;ADD 37H TO CONVERT ALPHABET TO ASCII
ADD A,#37h
lcall lcd_senddata ;send msb in ascii
NEXT:MOV A,R2
ANL A,#0Fh ;CHECK HIGHER NIBBLE IS DIGIT OR ALPHABET
MOV R3,A
SUBB A,#0Ah
JNC ALPHA2
MOV A,R3 ;DIGIT TO ASCII
ADD A,#30h
lcall lcd_senddata ;send lsb in ascii
POP AR3
POP AR2
POP PSW
RET
ALPHA2:MOV A,R3
ADD A,#37h ;ALPHABET TO ASCII
lcall lcd_senddata ;send lsb in ascii
POP AR3
POP AR2
POP PSW
RET ;Return from routine
;------------------------LCD Initialisation routine----------------------------------------------------
lcd_init:
mov LCD_data,#38H ;Function set: 2 Line, 8-bit, 5x7 dots
clr LCD_rs ;Selected command register
clr LCD_rw ;We are writing in instruction register
setb LCD_en ;Enable H->L
acall delay
clr LCD_en
acall delay
mov LCD_data,#0CH ;Display on, Curson off
clr LCD_rs ;Selected instruction register
clr LCD_rw ;We are writing in instruction register
setb LCD_en ;Enable H->L
acall delay
clr LCD_en
acall delay
mov LCD_data,#01H ;Clear LCD
clr LCD_rs ;Selected command register
clr LCD_rw ;We are writing in instruction register
setb LCD_en ;Enable H->L
acall delay
clr LCD_en
acall delay
mov LCD_data,#06H ;Entry mode, auto increment with no shift
clr LCD_rs ;Selected command register
clr LCD_rw ;We are writing in instruction register
setb LCD_en ;Enable H->L
acall delay
clr LCD_en
acall delay
ret ;Return from routine
;-----------------------command sending routine-------------------------------------
lcd_command:
mov LCD_data,A ;Move the command to LCD port
clr LCD_rs ;Selected command register
clr LCD_rw ;We are writing in instruction register
setb LCD_en ;Enable H->L
acall delay
clr LCD_en
acall delay
ret
;-----------------------data sending routine-------------------------------------
lcd_senddata:
mov LCD_data,A ;Move the command to LCD port
setb LCD_rs ;Selected data register
clr LCD_rw ;We are writing
setb LCD_en ;Enable H->L
acall delay
clr LCD_en
acall delay
acall delay
ret ;Return from busy routine
;-----------------------text strings sending routine-------------------------------------
lcd_sendstring:
clr a ;clear Accumulator for any previous data
movc a,@a+dptr ;load the first character in accumulator
jz exit ;go to exit if zero
acall lcd_senddata ;send first char
inc dptr ;increment data pointer
sjmp LCD_sendstring ;jump back to send the next character
exit:
ret ;End of routine
;-----------------------------------------------------------------------
;------------- ROM text strings---------------------------------------------------------------
org 700h
STR1:DB "PRESS SWITCH SW1", 00H
STR2:DB "AS LED GLOWS", 00H
STR3:DB "REACTION TIME", 00H
STR4:DB "COUNT IS ", 00H
END
| khushhallchandra/Microprocessor-lab | exp5/lab_work/Q2.asm | Assembly | cc0-1.0 | 7,820 |
//===========================================================================//
// GLOSS - Generic Loader for Operating System Software //
// An extensible and configurable bootloader. //
//---------------------------------------------------------------------------//
// Copyright (C) 2013-2016 ~ Adrian J. Collado <acollado@polaritech.com> //
// All Rights Reserved //
//===========================================================================//
// Seeing as how AT&T syntax is much more obscure and difficult to read (IMO)
// than Intel syntax, the assembly language code in this project for x86 based
// architectures will be using Intel syntax.
.intel_syntax noprefix
// This code will be executed in a 64 bit long mode environment.
.code64
// This code is located in the .TEXT (executable) section of the executable.
.section .text
.global AMD64.IDT.ISR0E
AMD64.IDT.ISR0E:
pop rdi
mov rsi, 0x0E
cld
mov rax, [AMD64.IDT.HandlerAddress]
call [rax + 0x70]
iretq
| SlickOS/SlickOS | Modules/Gloss/Arch/x86_64/Source/IDT/ISR0E.asm | Assembly | mit | 1,105 |
/*
* All Video Processing kernels
* Copyright © <2010>, Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* This file was originally licensed under the following license
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
//---------- PA_Scaling.asm ----------
#include "Scaling.inc"
// Build 16 elements ramp in float32 and normalized it
// mov (8) SAMPLER_RAMP(0)<1> 0x76543210:v
// add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f
mov (4) SAMPLER_RAMP(0)<1> 0x48403000:vf //3, 2, 1, 0 in float vector
mov (4) SAMPLER_RAMP(0,4)<1> 0x5C585450:vf //7, 6, 5, 4 in float vector
add (8) SAMPLER_RAMP(1)<1> SAMPLER_RAMP(0) 8.0:f
//Module: PrepareScaleCoord.asm
// Setup for sampler msg hdr
mov (2) rMSGSRC.0<1>:ud 0:ud { NoDDClr } // Unused fields
mov (1) rMSGSRC.2<1>:ud 0:ud { NoDDChk } // Write and offset
// Calculate 16 v based on the step Y and vertical origin
mov (16) mfMSGPAYLOAD(2)<1> fSRC_VID_V_ORI<0;1,0>:f
mov (16) SCALE_COORD_Y<1>:f fSRC_VID_V_ORI<0;1,0>:f
// Calculate 16 u based on the step X and hori origin
// line (16) mfMSGPAYLOAD(0)<1> SCALE_STEP_X<0;1,0>:f SAMPLER_RAMP(0) // Assign to mrf directly
mov (16) acc0:f fSRC_VID_H_ORI<0;1,0>:f { Compr }
mac (16) mfMSGPAYLOAD(0)<1> fVIDEO_STEP_X<0;1,0>:f SAMPLER_RAMP(0) { Compr }
//Setup the constants for line instruction
mov (1) SCALE_LINE_P255<1>:f 255.0:f { NoDDClr } //{ NoDDClr, NoDDChk }
mov (1) SCALE_LINE_P0_5<1>:f 0.5:f { NoDDChk }
//------------------------------------------------------------------------------
$for (0; <nY_NUM_OF_ROWS; 1) {
// Read 16 sampled pixels and store them in float32 in 8 GRFs in the order of BGRA (VYUA).
mov (8) MSGHDR_SCALE.0:ud rMSGSRC.0<8;8,1>:ud // Copy msg header and payload mirrors to MRFs
send (16) SCALE_RESPONSE_YW(0)<1> MSGHDR_SCALE udDUMMY_NULL nSMPL_ENGINE SMPLR_MSG_DSC+nSI_SRC_SIMD16_YUV+nBI_CURRENT_SRC_YUV
// Calculate 16 v for next line
add (16) mfMSGPAYLOAD(2)<1> SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly
add (16) SCALE_COORD_Y<1>:f SCALE_COORD_Y<8;8,1>:f fVIDEO_STEP_Y<0;1,0>:f // Assign to mrf directly
// Scale back to [0, 255], convert f to ud
line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(0) { Compr } // Process B, V
mov (16) SCALE_RESPONSE_YD(0)<1> acc0:f { Compr }
line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(2) { Compr } // Process B, V
mov (16) SCALE_RESPONSE_YD(2)<1> acc0:f { Compr }
line (16) acc0:f SCALE_LINE_P255<0;1,0>:f SCALE_RESPONSE_YF(4) { Compr } // Process B, V
mov (16) SCALE_RESPONSE_YD(4)<1> acc0:f { Compr }
mov (16) DEST_V(%1)<1> SCALE_RESPONSE_YB(0) //possible error due to truncation - vK
mov (16) DEST_Y(%1)<1> SCALE_RESPONSE_YB(2) //possible error due to truncation - vK
mov (16) DEST_U(%1)<1> SCALE_RESPONSE_YB(4) //possible error due to truncation - vK
}
#define nSRC_REGION nREGION_1
//------------------------------------------------------------------------------
| uartie/vaapi-intel-driver | src/shaders/post_processing/gen5_6/Core_Kernels/PA_Scaling.asm | Assembly | mit | 4,735 |
;*****************************************************************************
;* predict-a.asm: x86 intra prediction
;*****************************************************************************
;* Copyright (C) 2005-2016 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Holger Lubitz <holger@lubitz.org>
;* Fiona Glaser <fiona@x264.com>
;* Henrik Gramner <henrik@gramner.com>
;*
;* This program is free software; you can redistribute it and/or modify
;* it under the terms of the GNU General Public License as published by
;* the Free Software Foundation; either version 2 of the License, or
;* (at your option) any later version.
;*
;* This program is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;* GNU General Public License for more details.
;*
;* You should have received a copy of the GNU General Public License
;* along with this program; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
;*
;* This program is also available under a commercial proprietary license.
;* For more information, contact us at licensing@x264.com.
;*****************************************************************************
%include "x86inc.asm"
%include "x86util.asm"
SECTION_RODATA 32
pw_43210123: times 2 dw -3, -2, -1, 0, 1, 2, 3, 4
pw_m3: times 16 dw -3
pw_m7: times 16 dw -7
pb_00s_ff: times 8 db 0
pb_0s_ff: times 7 db 0
db 0xff
shuf_fixtr: db 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7
shuf_nop: db 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
shuf_hu: db 7,6,5,4,3,2,1,0,0,0,0,0,0,0,0,0
shuf_vr: db 2,4,6,8,9,10,11,12,13,14,15,0,1,3,5,7
pw_reverse: db 14,15,12,13,10,11,8,9,6,7,4,5,2,3,0,1
SECTION .text
cextern pb_0
cextern pb_1
cextern pb_3
cextern pw_1
cextern pw_2
cextern pw_4
cextern pw_8
cextern pw_16
cextern pw_00ff
cextern pw_pixel_max
cextern pw_0to15
%macro STORE8 1
mova [r0+0*FDEC_STRIDEB], %1
mova [r0+1*FDEC_STRIDEB], %1
add r0, 4*FDEC_STRIDEB
mova [r0-2*FDEC_STRIDEB], %1
mova [r0-1*FDEC_STRIDEB], %1
mova [r0+0*FDEC_STRIDEB], %1
mova [r0+1*FDEC_STRIDEB], %1
mova [r0+2*FDEC_STRIDEB], %1
mova [r0+3*FDEC_STRIDEB], %1
%endmacro
%macro STORE16 1-4
%if %0 > 1
mov r1d, 2*%0
.loop:
mova [r0+0*FDEC_STRIDEB+0*mmsize], %1
mova [r0+0*FDEC_STRIDEB+1*mmsize], %2
mova [r0+1*FDEC_STRIDEB+0*mmsize], %1
mova [r0+1*FDEC_STRIDEB+1*mmsize], %2
%ifidn %0, 4
mova [r0+0*FDEC_STRIDEB+2*mmsize], %3
mova [r0+0*FDEC_STRIDEB+3*mmsize], %4
mova [r0+1*FDEC_STRIDEB+2*mmsize], %3
mova [r0+1*FDEC_STRIDEB+3*mmsize], %4
add r0, 2*FDEC_STRIDEB
%else ; %0 == 2
add r0, 4*FDEC_STRIDEB
mova [r0-2*FDEC_STRIDEB+0*mmsize], %1
mova [r0-2*FDEC_STRIDEB+1*mmsize], %2
mova [r0-1*FDEC_STRIDEB+0*mmsize], %1
mova [r0-1*FDEC_STRIDEB+1*mmsize], %2
%endif
dec r1d
jg .loop
%else ; %0 == 1
STORE8 %1
%if HIGH_BIT_DEPTH ; Different code paths to reduce code size
add r0, 6*FDEC_STRIDEB
mova [r0-2*FDEC_STRIDEB], %1
mova [r0-1*FDEC_STRIDEB], %1
mova [r0+0*FDEC_STRIDEB], %1
mova [r0+1*FDEC_STRIDEB], %1
add r0, 4*FDEC_STRIDEB
mova [r0-2*FDEC_STRIDEB], %1
mova [r0-1*FDEC_STRIDEB], %1
mova [r0+0*FDEC_STRIDEB], %1
mova [r0+1*FDEC_STRIDEB], %1
%else
add r0, 8*FDEC_STRIDE
mova [r0-4*FDEC_STRIDE], %1
mova [r0-3*FDEC_STRIDE], %1
mova [r0-2*FDEC_STRIDE], %1
mova [r0-1*FDEC_STRIDE], %1
mova [r0+0*FDEC_STRIDE], %1
mova [r0+1*FDEC_STRIDE], %1
mova [r0+2*FDEC_STRIDE], %1
mova [r0+3*FDEC_STRIDE], %1
%endif ; HIGH_BIT_DEPTH
%endif
%endmacro
%macro PRED_H_LOAD 2 ; reg, offset
%if cpuflag(avx2)
vpbroadcastpix %1, [r0+(%2)*FDEC_STRIDEB-SIZEOF_PIXEL]
%elif HIGH_BIT_DEPTH
movd %1, [r0+(%2)*FDEC_STRIDEB-4]
SPLATW %1, %1, 1
%else
SPLATB_LOAD %1, r0+(%2)*FDEC_STRIDE-1, m2
%endif
%endmacro
%macro PRED_H_STORE 3 ; reg, offset, width
%assign %%w %3*SIZEOF_PIXEL
%if %%w == 8
movq [r0+(%2)*FDEC_STRIDEB], %1
%else
%assign %%i 0
%rep %%w/mmsize
mova [r0+(%2)*FDEC_STRIDEB+%%i], %1
%assign %%i %%i+mmsize
%endrep
%endif
%endmacro
%macro PRED_H_4ROWS 2 ; width, inc_ptr
PRED_H_LOAD m0, 0
PRED_H_LOAD m1, 1
PRED_H_STORE m0, 0, %1
PRED_H_STORE m1, 1, %1
PRED_H_LOAD m0, 2
%if %2
add r0, 4*FDEC_STRIDEB
%endif
PRED_H_LOAD m1, 3-4*%2
PRED_H_STORE m0, 2-4*%2, %1
PRED_H_STORE m1, 3-4*%2, %1
%endmacro
; dest, left, right, src, tmp
; output: %1 = (t[n-1] + t[n]*2 + t[n+1] + 2) >> 2
%macro PRED8x8_LOWPASS 4-5
%if HIGH_BIT_DEPTH
paddw %2, %3
psrlw %2, 1
pavgw %1, %4, %2
%else
mova %5, %2
pavgb %2, %3
pxor %3, %5
pand %3, [pb_1]
psubusb %2, %3
pavgb %1, %4, %2
%endif
%endmacro
;-----------------------------------------------------------------------------
; void predict_4x4_h( pixel *src )
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH
INIT_XMM avx2
cglobal predict_4x4_h, 1,1
PRED_H_4ROWS 4, 0
RET
%endif
;-----------------------------------------------------------------------------
; void predict_4x4_ddl( pixel *src )
;-----------------------------------------------------------------------------
%macro PREDICT_4x4_DDL 0
cglobal predict_4x4_ddl, 1,1
movu m1, [r0-FDEC_STRIDEB]
PSLLPIX m2, m1, 1
mova m0, m1
%if HIGH_BIT_DEPTH
PSRLPIX m1, m1, 1
pshufhw m1, m1, q2210
%else
pxor m1, m2
PSRLPIX m1, m1, 1
pxor m1, m0
%endif
PRED8x8_LOWPASS m0, m2, m1, m0, m3
%assign Y 0
%rep 4
PSRLPIX m0, m0, 1
movh [r0+Y*FDEC_STRIDEB], m0
%assign Y (Y+1)
%endrep
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_4x4_DDL
INIT_XMM avx
PREDICT_4x4_DDL
INIT_MMX mmx2
cglobal predict_4x4_ddl, 1,2
movu m1, [r0-FDEC_STRIDEB+4]
PRED8x8_LOWPASS m0, m1, [r0-FDEC_STRIDEB+0], [r0-FDEC_STRIDEB+2]
mova m3, [r0-FDEC_STRIDEB+8]
mova [r0+0*FDEC_STRIDEB], m0
pshufw m4, m3, q3321
PRED8x8_LOWPASS m2, m4, [r0-FDEC_STRIDEB+6], m3
mova [r0+3*FDEC_STRIDEB], m2
pshufw m1, m0, q0021
punpckldq m1, m2
mova [r0+1*FDEC_STRIDEB], m1
psllq m0, 16
PALIGNR m2, m0, 6, m0
mova [r0+2*FDEC_STRIDEB], m2
RET
%else ; !HIGH_BIT_DEPTH
INIT_MMX mmx2
PREDICT_4x4_DDL
%endif
;-----------------------------------------------------------------------------
; void predict_4x4_vr( pixel *src )
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH == 0
INIT_MMX ssse3
cglobal predict_4x4_vr, 1,1
movd m1, [r0-1*FDEC_STRIDEB] ; ........t3t2t1t0
mova m4, m1
palignr m1, [r0-1*FDEC_STRIDEB-8], 7 ; ......t3t2t1t0lt
pavgb m4, m1
palignr m1, [r0+0*FDEC_STRIDEB-8], 7 ; ....t3t2t1t0ltl0
mova m0, m1
palignr m1, [r0+1*FDEC_STRIDEB-8], 7 ; ..t3t2t1t0ltl0l1
mova m2, m1
palignr m1, [r0+2*FDEC_STRIDEB-8], 7 ; t3t2t1t0ltl0l1l2
PRED8x8_LOWPASS m2, m0, m1, m2, m3
pshufw m0, m2, 0
psrlq m2, 16
movd [r0+0*FDEC_STRIDEB], m4
palignr m4, m0, 7
movd [r0+1*FDEC_STRIDEB], m2
psllq m0, 8
movd [r0+2*FDEC_STRIDEB], m4
palignr m2, m0, 7
movd [r0+3*FDEC_STRIDEB], m2
RET
%endif ; !HIGH_BIT_DEPTH
;-----------------------------------------------------------------------------
; void predict_4x4_ddr( pixel *src )
;-----------------------------------------------------------------------------
%macro PREDICT_4x4 4
cglobal predict_4x4_ddr, 1,1
%if HIGH_BIT_DEPTH
movu m2, [r0-1*FDEC_STRIDEB-8]
pinsrw m2, [r0+0*FDEC_STRIDEB-2], 2
pinsrw m2, [r0+1*FDEC_STRIDEB-2], 1
pinsrw m2, [r0+2*FDEC_STRIDEB-2], 0
movhps m3, [r0+3*FDEC_STRIDEB-8]
%else ; !HIGH_BIT_DEPTH
movd m0, [r0+2*FDEC_STRIDEB-4]
movd m1, [r0+0*FDEC_STRIDEB-4]
punpcklbw m0, [r0+1*FDEC_STRIDEB-4]
punpcklbw m1, [r0-1*FDEC_STRIDEB-4]
punpckhwd m0, m1
movd m2, [r0-1*FDEC_STRIDEB]
%if cpuflag(ssse3)
palignr m2, m0, 4
%else
psllq m2, 32
punpckhdq m0, m2
SWAP 2, 0
%endif
movd m3, [r0+3*FDEC_STRIDEB-4]
psllq m3, 32
%endif ; !HIGH_BIT_DEPTH
PSRLPIX m1, m2, 1
mova m0, m2
PALIGNR m2, m3, 7*SIZEOF_PIXEL, m3
PRED8x8_LOWPASS m0, m2, m1, m0, m3
%assign Y 3
movh [r0+Y*FDEC_STRIDEB], m0
%rep 3
%assign Y (Y-1)
PSRLPIX m0, m0, 1
movh [r0+Y*FDEC_STRIDEB], m0
%endrep
RET
;-----------------------------------------------------------------------------
; void predict_4x4_vr( pixel *src )
;-----------------------------------------------------------------------------
cglobal predict_4x4_vr, 1,1
%if HIGH_BIT_DEPTH
movu m1, [r0-1*FDEC_STRIDEB-8]
pinsrw m1, [r0+0*FDEC_STRIDEB-2], 2
pinsrw m1, [r0+1*FDEC_STRIDEB-2], 1
pinsrw m1, [r0+2*FDEC_STRIDEB-2], 0
%else ; !HIGH_BIT_DEPTH
movd m0, [r0+2*FDEC_STRIDEB-4]
movd m1, [r0+0*FDEC_STRIDEB-4]
punpcklbw m0, [r0+1*FDEC_STRIDEB-4]
punpcklbw m1, [r0-1*FDEC_STRIDEB-4]
punpckhwd m0, m1
movd m1, [r0-1*FDEC_STRIDEB]
%if cpuflag(ssse3)
palignr m1, m0, 4
%else
psllq m1, 32
punpckhdq m0, m1
SWAP 1, 0
%endif
%endif ; !HIGH_BIT_DEPTH
PSRLPIX m2, m1, 1
PSRLPIX m0, m1, 2
pavg%1 m4, m1, m2
PSRLPIX m4, m4, 3
PRED8x8_LOWPASS m2, m0, m1, m2, m3
PSLLPIX m0, m2, 6
PSRLPIX m2, m2, 2
movh [r0+0*FDEC_STRIDEB], m4
PALIGNR m4, m0, 7*SIZEOF_PIXEL, m3
movh [r0+1*FDEC_STRIDEB], m2
PSLLPIX m0, m0, 1
movh [r0+2*FDEC_STRIDEB], m4
PALIGNR m2, m0, 7*SIZEOF_PIXEL, m0
movh [r0+3*FDEC_STRIDEB], m2
RET
;-----------------------------------------------------------------------------
; void predict_4x4_hd( pixel *src )
;-----------------------------------------------------------------------------
cglobal predict_4x4_hd, 1,1
%if HIGH_BIT_DEPTH
movu m1, [r0-1*FDEC_STRIDEB-8]
PSLLPIX m1, m1, 1
pinsrw m1, [r0+0*FDEC_STRIDEB-2], 3
pinsrw m1, [r0+1*FDEC_STRIDEB-2], 2
pinsrw m1, [r0+2*FDEC_STRIDEB-2], 1
pinsrw m1, [r0+3*FDEC_STRIDEB-2], 0
%else
movd m0, [r0-1*FDEC_STRIDEB-4] ; lt ..
punpckldq m0, [r0-1*FDEC_STRIDEB] ; t3 t2 t1 t0 lt .. .. ..
PSLLPIX m0, m0, 1 ; t2 t1 t0 lt .. .. .. ..
movd m1, [r0+3*FDEC_STRIDEB-4] ; l3
punpcklbw m1, [r0+2*FDEC_STRIDEB-4] ; l2 l3
movd m2, [r0+1*FDEC_STRIDEB-4] ; l1
punpcklbw m2, [r0+0*FDEC_STRIDEB-4] ; l0 l1
punpckh%3 m1, m2 ; l0 l1 l2 l3
punpckh%4 m1, m0 ; t2 t1 t0 lt l0 l1 l2 l3
%endif
PSRLPIX m2, m1, 1 ; .. t2 t1 t0 lt l0 l1 l2
PSRLPIX m0, m1, 2 ; .. .. t2 t1 t0 lt l0 l1
pavg%1 m5, m1, m2
PRED8x8_LOWPASS m3, m1, m0, m2, m4
punpckl%2 m5, m3
PSRLPIX m3, m3, 4
PALIGNR m3, m5, 6*SIZEOF_PIXEL, m4
%assign Y 3
movh [r0+Y*FDEC_STRIDEB], m5
%rep 2
%assign Y (Y-1)
PSRLPIX m5, m5, 2
movh [r0+Y*FDEC_STRIDEB], m5
%endrep
movh [r0+0*FDEC_STRIDEB], m3
RET
%endmacro ; PREDICT_4x4
;-----------------------------------------------------------------------------
; void predict_4x4_ddr( pixel *src )
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH
INIT_MMX mmx2
cglobal predict_4x4_ddr, 1,1
mova m0, [r0+1*FDEC_STRIDEB-8]
punpckhwd m0, [r0+0*FDEC_STRIDEB-8]
mova m3, [r0+3*FDEC_STRIDEB-8]
punpckhwd m3, [r0+2*FDEC_STRIDEB-8]
punpckhdq m3, m0
pshufw m0, m3, q3321
pinsrw m0, [r0-1*FDEC_STRIDEB-2], 3
pshufw m1, m0, q3321
PRED8x8_LOWPASS m0, m1, m3, m0
movq [r0+3*FDEC_STRIDEB], m0
movq m2, [r0-1*FDEC_STRIDEB-0]
pshufw m4, m2, q2100
pinsrw m4, [r0-1*FDEC_STRIDEB-2], 0
movq m1, m4
PALIGNR m4, m3, 6, m3
PRED8x8_LOWPASS m1, m4, m2, m1
movq [r0+0*FDEC_STRIDEB], m1
pshufw m2, m0, q3321
punpckldq m2, m1
psllq m0, 16
PALIGNR m1, m0, 6, m0
movq [r0+1*FDEC_STRIDEB], m1
movq [r0+2*FDEC_STRIDEB], m2
movd [r0+3*FDEC_STRIDEB+4], m1
RET
;-----------------------------------------------------------------------------
; void predict_4x4_hd( pixel *src )
;-----------------------------------------------------------------------------
cglobal predict_4x4_hd, 1,1
mova m0, [r0+1*FDEC_STRIDEB-8]
punpckhwd m0, [r0+0*FDEC_STRIDEB-8]
mova m1, [r0+3*FDEC_STRIDEB-8]
punpckhwd m1, [r0+2*FDEC_STRIDEB-8]
punpckhdq m1, m0
mova m0, m1
movu m3, [r0-1*FDEC_STRIDEB-2]
pshufw m4, m1, q0032
mova m7, m3
punpckldq m4, m3
PALIGNR m3, m1, 2, m2
PRED8x8_LOWPASS m2, m4, m1, m3
pavgw m0, m3
punpcklwd m5, m0, m2
punpckhwd m4, m0, m2
mova [r0+3*FDEC_STRIDEB], m5
mova [r0+1*FDEC_STRIDEB], m4
psrlq m5, 32
punpckldq m5, m4
mova [r0+2*FDEC_STRIDEB], m5
pshufw m4, m7, q2100
mova m6, [r0-1*FDEC_STRIDEB+0]
pinsrw m4, [r0+0*FDEC_STRIDEB-2], 0
PRED8x8_LOWPASS m3, m4, m6, m7
PALIGNR m3, m0, 6, m0
mova [r0+0*FDEC_STRIDEB], m3
RET
INIT_XMM sse2
PREDICT_4x4 w, wd, dq, qdq
INIT_XMM ssse3
PREDICT_4x4 w, wd, dq, qdq
INIT_XMM avx
PREDICT_4x4 w, wd, dq, qdq
%else ; !HIGH_BIT_DEPTH
INIT_MMX mmx2
PREDICT_4x4 b, bw, wd, dq
INIT_MMX ssse3
%define predict_4x4_vr_ssse3 predict_4x4_vr_ssse3_cache64
PREDICT_4x4 b, bw, wd, dq
%endif
;-----------------------------------------------------------------------------
; void predict_4x4_hu( pixel *src )
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH
INIT_MMX
cglobal predict_4x4_hu_mmx2, 1,1
movq m0, [r0+0*FDEC_STRIDEB-8]
punpckhwd m0, [r0+1*FDEC_STRIDEB-8]
movq m1, [r0+2*FDEC_STRIDEB-8]
punpckhwd m1, [r0+3*FDEC_STRIDEB-8]
punpckhdq m0, m1
pshufw m1, m1, q3333
movq [r0+3*FDEC_STRIDEB], m1
pshufw m3, m0, q3321
pshufw m4, m0, q3332
pavgw m2, m0, m3
PRED8x8_LOWPASS m3, m0, m4, m3
punpcklwd m4, m2, m3
mova [r0+0*FDEC_STRIDEB], m4
psrlq m2, 16
psrlq m3, 16
punpcklwd m2, m3
mova [r0+1*FDEC_STRIDEB], m2
punpckhdq m2, m1
mova [r0+2*FDEC_STRIDEB], m2
RET
%else ; !HIGH_BIT_DEPTH
INIT_MMX
cglobal predict_4x4_hu_mmx2, 1,1
movd m1, [r0+0*FDEC_STRIDEB-4]
punpcklbw m1, [r0+1*FDEC_STRIDEB-4]
movd m0, [r0+2*FDEC_STRIDEB-4]
punpcklbw m0, [r0+3*FDEC_STRIDEB-4]
punpckhwd m1, m0
movq m0, m1
punpckhbw m1, m1
pshufw m1, m1, q3333
punpckhdq m0, m1
movq m2, m0
movq m3, m0
movq m5, m0
psrlq m3, 8
psrlq m2, 16
pavgb m5, m3
PRED8x8_LOWPASS m3, m0, m2, m3, m4
movd [r0+3*FDEC_STRIDEB], m1
punpcklbw m5, m3
movd [r0+0*FDEC_STRIDEB], m5
psrlq m5, 16
movd [r0+1*FDEC_STRIDEB], m5
psrlq m5, 16
movd [r0+2*FDEC_STRIDEB], m5
RET
%endif ; HIGH_BIT_DEPTH
;-----------------------------------------------------------------------------
; void predict_4x4_vl( pixel *src )
;-----------------------------------------------------------------------------
%macro PREDICT_4x4_V1 1
cglobal predict_4x4_vl, 1,1
movu m1, [r0-FDEC_STRIDEB]
PSRLPIX m3, m1, 1
PSRLPIX m2, m1, 2
pavg%1 m4, m3, m1
PRED8x8_LOWPASS m0, m1, m2, m3, m5
movh [r0+0*FDEC_STRIDEB], m4
movh [r0+1*FDEC_STRIDEB], m0
PSRLPIX m4, m4, 1
PSRLPIX m0, m0, 1
movh [r0+2*FDEC_STRIDEB], m4
movh [r0+3*FDEC_STRIDEB], m0
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_4x4_V1 w
INIT_XMM avx
PREDICT_4x4_V1 w
INIT_MMX mmx2
cglobal predict_4x4_vl, 1,4
mova m1, [r0-FDEC_STRIDEB+0]
mova m2, [r0-FDEC_STRIDEB+8]
mova m0, m2
PALIGNR m2, m1, 4, m4
PALIGNR m0, m1, 2, m4
mova m3, m0
pavgw m3, m1
mova [r0+0*FDEC_STRIDEB], m3
psrlq m3, 16
mova [r0+2*FDEC_STRIDEB], m3
PRED8x8_LOWPASS m0, m1, m2, m0
mova [r0+1*FDEC_STRIDEB], m0
psrlq m0, 16
mova [r0+3*FDEC_STRIDEB], m0
movzx r1d, word [r0-FDEC_STRIDEB+ 8]
movzx r2d, word [r0-FDEC_STRIDEB+10]
movzx r3d, word [r0-FDEC_STRIDEB+12]
lea r1d, [r1+r2+1]
add r3d, r2d
lea r3d, [r3+r1+1]
shr r1d, 1
shr r3d, 2
mov [r0+2*FDEC_STRIDEB+6], r1w
mov [r0+3*FDEC_STRIDEB+6], r3w
RET
%else ; !HIGH_BIT_DEPTH
INIT_MMX mmx2
PREDICT_4x4_V1 b
%endif
;-----------------------------------------------------------------------------
; void predict_4x4_dc( pixel *src )
;-----------------------------------------------------------------------------
INIT_MMX mmx2
%if HIGH_BIT_DEPTH
cglobal predict_4x4_dc, 1,1
mova m2, [r0+0*FDEC_STRIDEB-4*SIZEOF_PIXEL]
paddw m2, [r0+1*FDEC_STRIDEB-4*SIZEOF_PIXEL]
paddw m2, [r0+2*FDEC_STRIDEB-4*SIZEOF_PIXEL]
paddw m2, [r0+3*FDEC_STRIDEB-4*SIZEOF_PIXEL]
psrlq m2, 48
mova m0, [r0-FDEC_STRIDEB]
HADDW m0, m1
paddw m0, [pw_4]
paddw m0, m2
psrlw m0, 3
SPLATW m0, m0
mova [r0+0*FDEC_STRIDEB], m0
mova [r0+1*FDEC_STRIDEB], m0
mova [r0+2*FDEC_STRIDEB], m0
mova [r0+3*FDEC_STRIDEB], m0
RET
%else ; !HIGH_BIT_DEPTH
cglobal predict_4x4_dc, 1,4
pxor mm7, mm7
movd mm0, [r0-FDEC_STRIDEB]
psadbw mm0, mm7
movd r3d, mm0
movzx r1d, byte [r0-1]
%assign Y 1
%rep 3
movzx r2d, byte [r0+FDEC_STRIDEB*Y-1]
add r1d, r2d
%assign Y Y+1
%endrep
lea r1d, [r1+r3+4]
shr r1d, 3
imul r1d, 0x01010101
mov [r0+FDEC_STRIDEB*0], r1d
mov [r0+FDEC_STRIDEB*1], r1d
mov [r0+FDEC_STRIDEB*2], r1d
mov [r0+FDEC_STRIDEB*3], r1d
RET
%endif ; HIGH_BIT_DEPTH
%macro PREDICT_FILTER 4
;-----------------------------------------------------------------------------
;void predict_8x8_filter( pixel *src, pixel edge[36], int i_neighbor, int i_filters )
;-----------------------------------------------------------------------------
cglobal predict_8x8_filter, 4,6,6
add r0, 0x58*SIZEOF_PIXEL
%define src r0-0x58*SIZEOF_PIXEL
%if ARCH_X86_64 == 0
mov r4, r1
%define t1 r4
%define t4 r1
%else
%define t1 r1
%define t4 r4
%endif
test r3b, 1
je .check_top
mov t4d, r2d
and t4d, 8
neg t4
mova m0, [src+0*FDEC_STRIDEB-8*SIZEOF_PIXEL]
punpckh%1%2 m0, [src+0*FDEC_STRIDEB-8*SIZEOF_PIXEL+t4*(FDEC_STRIDEB/8)]
mova m1, [src+2*FDEC_STRIDEB-8*SIZEOF_PIXEL]
punpckh%1%2 m1, [src+1*FDEC_STRIDEB-8*SIZEOF_PIXEL]
punpckh%2%3 m1, m0
mova m2, [src+4*FDEC_STRIDEB-8*SIZEOF_PIXEL]
punpckh%1%2 m2, [src+3*FDEC_STRIDEB-8*SIZEOF_PIXEL]
mova m3, [src+6*FDEC_STRIDEB-8*SIZEOF_PIXEL]
punpckh%1%2 m3, [src+5*FDEC_STRIDEB-8*SIZEOF_PIXEL]
punpckh%2%3 m3, m2
punpckh%3%4 m3, m1
mova m0, [src+7*FDEC_STRIDEB-8*SIZEOF_PIXEL]
mova m1, [src-1*FDEC_STRIDEB]
PALIGNR m4, m3, m0, 7*SIZEOF_PIXEL, m0
PALIGNR m1, m1, m3, 1*SIZEOF_PIXEL, m2
PRED8x8_LOWPASS m3, m1, m4, m3, m5
mova [t1+8*SIZEOF_PIXEL], m3
movzx t4d, pixel [src+7*FDEC_STRIDEB-1*SIZEOF_PIXEL]
movzx r5d, pixel [src+6*FDEC_STRIDEB-1*SIZEOF_PIXEL]
lea t4d, [t4*3+2]
add t4d, r5d
shr t4d, 2
mov [t1+7*SIZEOF_PIXEL], t4%1
mov [t1+6*SIZEOF_PIXEL], t4%1
test r3b, 2
je .done
.check_top:
%if SIZEOF_PIXEL==1 && cpuflag(ssse3)
INIT_XMM cpuname
movu m3, [src-1*FDEC_STRIDEB]
movhps m0, [src-1*FDEC_STRIDEB-8]
test r2b, 8
je .fix_lt_2
.do_top:
and r2d, 4
%ifdef PIC
lea r3, [shuf_fixtr]
pshufb m3, [r3+r2*4]
%else
pshufb m3, [shuf_fixtr+r2*4] ; neighbor&MB_TOPRIGHT ? shuf_nop : shuf_fixtr
%endif
psrldq m1, m3, 15
PALIGNR m2, m3, m0, 15, m0
PALIGNR m1, m3, 1, m5
PRED8x8_LOWPASS m0, m2, m1, m3, m5
mova [t1+16*SIZEOF_PIXEL], m0
psrldq m0, 15
movd [t1+32*SIZEOF_PIXEL], m0
.done:
REP_RET
.fix_lt_2:
pslldq m0, m3, 15
jmp .do_top
%else
mova m0, [src-1*FDEC_STRIDEB-8*SIZEOF_PIXEL]
mova m3, [src-1*FDEC_STRIDEB]
mova m1, [src-1*FDEC_STRIDEB+8*SIZEOF_PIXEL]
test r2b, 8
je .fix_lt_2
test r2b, 4
je .fix_tr_1
.do_top:
PALIGNR m2, m3, m0, 7*SIZEOF_PIXEL, m0
PALIGNR m0, m1, m3, 1*SIZEOF_PIXEL, m5
PRED8x8_LOWPASS m4, m2, m0, m3, m5
mova [t1+16*SIZEOF_PIXEL], m4
test r3b, 4
je .done
PSRLPIX m5, m1, 7
PALIGNR m2, m1, m3, 7*SIZEOF_PIXEL, m3
PALIGNR m5, m1, 1*SIZEOF_PIXEL, m4
PRED8x8_LOWPASS m0, m2, m5, m1, m4
mova [t1+24*SIZEOF_PIXEL], m0
PSRLPIX m0, m0, 7
movd [t1+32*SIZEOF_PIXEL], m0
.done:
REP_RET
.fix_lt_2:
PSLLPIX m0, m3, 7
test r2b, 4
jne .do_top
.fix_tr_1:
punpckh%1%2 m1, m3, m3
pshuf%2 m1, m1, q3333
jmp .do_top
%endif
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_FILTER w, d, q, dq
INIT_XMM ssse3
PREDICT_FILTER w, d, q, dq
INIT_XMM avx
PREDICT_FILTER w, d, q, dq
%else
INIT_MMX mmx2
PREDICT_FILTER b, w, d, q
INIT_MMX ssse3
PREDICT_FILTER b, w, d, q
%endif
;-----------------------------------------------------------------------------
; void predict_8x8_v( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_V 0
cglobal predict_8x8_v, 2,2
mova m0, [r1+16*SIZEOF_PIXEL]
STORE8 m0
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse
PREDICT_8x8_V
%else
INIT_MMX mmx2
PREDICT_8x8_V
%endif
;-----------------------------------------------------------------------------
; void predict_8x8_h( pixel *src, pixel edge[36] )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_H 2
cglobal predict_8x8_h, 2,2
movu m1, [r1+7*SIZEOF_PIXEL]
add r0, 4*FDEC_STRIDEB
punpckl%1 m2, m1, m1
punpckh%1 m1, m1
%assign Y 0
%rep 8
%assign i 1+Y/4
SPLAT%2 m0, m %+ i, (3-Y)&3
mova [r0+(Y-4)*FDEC_STRIDEB], m0
%assign Y Y+1
%endrep
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_8x8_H wd, D
%else
INIT_MMX mmx2
PREDICT_8x8_H bw, W
%endif
;-----------------------------------------------------------------------------
; void predict_8x8_dc( pixel *src, pixel *edge );
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH
INIT_XMM sse2
cglobal predict_8x8_dc, 2,2
movu m0, [r1+14]
paddw m0, [r1+32]
HADDW m0, m1
paddw m0, [pw_8]
psrlw m0, 4
SPLATW m0, m0
STORE8 m0
RET
%else ; !HIGH_BIT_DEPTH
INIT_MMX mmx2
cglobal predict_8x8_dc, 2,2
pxor mm0, mm0
pxor mm1, mm1
psadbw mm0, [r1+7]
psadbw mm1, [r1+16]
paddw mm0, [pw_8]
paddw mm0, mm1
psrlw mm0, 4
pshufw mm0, mm0, 0
packuswb mm0, mm0
STORE8 mm0
RET
%endif ; HIGH_BIT_DEPTH
;-----------------------------------------------------------------------------
; void predict_8x8_dc_top ( pixel *src, pixel *edge );
; void predict_8x8_dc_left( pixel *src, pixel *edge );
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH
%macro PREDICT_8x8_DC 3
cglobal %1, 2,2
%3 m0, [r1+%2]
HADDW m0, m1
paddw m0, [pw_4]
psrlw m0, 3
SPLATW m0, m0
STORE8 m0
RET
%endmacro
INIT_XMM sse2
PREDICT_8x8_DC predict_8x8_dc_top , 32, mova
PREDICT_8x8_DC predict_8x8_dc_left, 14, movu
%else ; !HIGH_BIT_DEPTH
%macro PREDICT_8x8_DC 2
cglobal %1, 2,2
pxor mm0, mm0
psadbw mm0, [r1+%2]
paddw mm0, [pw_4]
psrlw mm0, 3
pshufw mm0, mm0, 0
packuswb mm0, mm0
STORE8 mm0
RET
%endmacro
INIT_MMX
PREDICT_8x8_DC predict_8x8_dc_top_mmx2, 16
PREDICT_8x8_DC predict_8x8_dc_left_mmx2, 7
%endif ; HIGH_BIT_DEPTH
; sse2 is faster even on amd for 8-bit, so there's no sense in spending exe
; size on the 8-bit mmx functions below if we know sse2 is available.
%macro PREDICT_8x8_DDLR 0
;-----------------------------------------------------------------------------
; void predict_8x8_ddl( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
cglobal predict_8x8_ddl, 2,2,7
mova m0, [r1+16*SIZEOF_PIXEL]
mova m1, [r1+24*SIZEOF_PIXEL]
%if cpuflag(cache64)
movd m5, [r1+32*SIZEOF_PIXEL]
palignr m3, m1, m0, 1*SIZEOF_PIXEL
palignr m5, m5, m1, 1*SIZEOF_PIXEL
palignr m4, m1, m0, 7*SIZEOF_PIXEL
%else
movu m3, [r1+17*SIZEOF_PIXEL]
movu m4, [r1+23*SIZEOF_PIXEL]
movu m5, [r1+25*SIZEOF_PIXEL]
%endif
PSLLPIX m2, m0, 1
add r0, FDEC_STRIDEB*4
PRED8x8_LOWPASS m0, m2, m3, m0, m6
PRED8x8_LOWPASS m1, m4, m5, m1, m6
mova [r0+3*FDEC_STRIDEB], m1
%assign Y 2
%rep 6
PALIGNR m1, m0, 7*SIZEOF_PIXEL, m2
PSLLPIX m0, m0, 1
mova [r0+Y*FDEC_STRIDEB], m1
%assign Y (Y-1)
%endrep
PALIGNR m1, m0, 7*SIZEOF_PIXEL, m0
mova [r0+Y*FDEC_STRIDEB], m1
RET
;-----------------------------------------------------------------------------
; void predict_8x8_ddr( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
cglobal predict_8x8_ddr, 2,2,7
add r0, FDEC_STRIDEB*4
mova m0, [r1+ 8*SIZEOF_PIXEL]
mova m1, [r1+16*SIZEOF_PIXEL]
; edge[] is 32byte aligned, so some of the unaligned loads are known to be not cachesplit
movu m2, [r1+ 7*SIZEOF_PIXEL]
movu m5, [r1+17*SIZEOF_PIXEL]
%if cpuflag(cache64)
palignr m3, m1, m0, 1*SIZEOF_PIXEL
palignr m4, m1, m0, 7*SIZEOF_PIXEL
%else
movu m3, [r1+ 9*SIZEOF_PIXEL]
movu m4, [r1+15*SIZEOF_PIXEL]
%endif
PRED8x8_LOWPASS m0, m2, m3, m0, m6
PRED8x8_LOWPASS m1, m4, m5, m1, m6
mova [r0+3*FDEC_STRIDEB], m0
%assign Y -4
%rep 6
PALIGNR m1, m0, 7*SIZEOF_PIXEL, m2
PSLLPIX m0, m0, 1
mova [r0+Y*FDEC_STRIDEB], m1
%assign Y (Y+1)
%endrep
PALIGNR m1, m0, 7*SIZEOF_PIXEL, m0
mova [r0+Y*FDEC_STRIDEB], m1
RET
%endmacro ; PREDICT_8x8_DDLR
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_8x8_DDLR
INIT_XMM ssse3
PREDICT_8x8_DDLR
INIT_XMM ssse3, cache64
PREDICT_8x8_DDLR
%elif ARCH_X86_64 == 0
INIT_MMX mmx2
PREDICT_8x8_DDLR
%endif
;-----------------------------------------------------------------------------
; void predict_8x8_hu( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_HU 2
cglobal predict_8x8_hu, 2,2,8
add r0, 4*FDEC_STRIDEB
%if HIGH_BIT_DEPTH
%if cpuflag(ssse3)
movu m5, [r1+7*SIZEOF_PIXEL]
pshufb m5, [pw_reverse]
%else
movq m6, [r1+7*SIZEOF_PIXEL]
movq m5, [r1+11*SIZEOF_PIXEL]
pshuflw m6, m6, q0123
pshuflw m5, m5, q0123
movlhps m5, m6
%endif ; cpuflag
psrldq m2, m5, 2
pshufd m3, m5, q0321
pshufhw m2, m2, q2210
pshufhw m3, m3, q1110
pavgw m4, m5, m2
%else ; !HIGH_BIT_DEPTH
movu m1, [r1+7*SIZEOF_PIXEL] ; l0 l1 l2 l3 l4 l5 l6 l7
pshufw m0, m1, q0123 ; l6 l7 l4 l5 l2 l3 l0 l1
psllq m1, 56 ; l7 .. .. .. .. .. .. ..
mova m2, m0
psllw m0, 8
psrlw m2, 8
por m2, m0
mova m3, m2
mova m4, m2
mova m5, m2 ; l7 l6 l5 l4 l3 l2 l1 l0
psrlq m3, 16
psrlq m2, 8
por m2, m1 ; l7 l7 l6 l5 l4 l3 l2 l1
punpckhbw m1, m1
por m3, m1 ; l7 l7 l7 l6 l5 l4 l3 l2
pavgb m4, m2
%endif ; !HIGH_BIT_DEPTH
PRED8x8_LOWPASS m2, m3, m5, m2, m6
punpckh%2 m0, m4, m2 ; p8 p7 p6 p5
punpckl%2 m4, m2 ; p4 p3 p2 p1
PALIGNR m5, m0, m4, 2*SIZEOF_PIXEL, m3
pshuf%1 m1, m0, q3321
PALIGNR m6, m0, m4, 4*SIZEOF_PIXEL, m3
pshuf%1 m2, m0, q3332
PALIGNR m7, m0, m4, 6*SIZEOF_PIXEL, m3
pshuf%1 m3, m0, q3333
mova [r0-4*FDEC_STRIDEB], m4
mova [r0-3*FDEC_STRIDEB], m5
mova [r0-2*FDEC_STRIDEB], m6
mova [r0-1*FDEC_STRIDEB], m7
mova [r0+0*FDEC_STRIDEB], m0
mova [r0+1*FDEC_STRIDEB], m1
mova [r0+2*FDEC_STRIDEB], m2
mova [r0+3*FDEC_STRIDEB], m3
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_8x8_HU d, wd
INIT_XMM ssse3
PREDICT_8x8_HU d, wd
INIT_XMM avx
PREDICT_8x8_HU d, wd
%elif ARCH_X86_64 == 0
INIT_MMX mmx2
PREDICT_8x8_HU w, bw
%endif
;-----------------------------------------------------------------------------
; void predict_8x8_vr( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_VR 1
cglobal predict_8x8_vr, 2,3
mova m2, [r1+16*SIZEOF_PIXEL]
%ifidn cpuname, ssse3
mova m0, [r1+8*SIZEOF_PIXEL]
palignr m3, m2, m0, 7*SIZEOF_PIXEL
palignr m1, m2, m0, 6*SIZEOF_PIXEL
%else
movu m3, [r1+15*SIZEOF_PIXEL]
movu m1, [r1+14*SIZEOF_PIXEL]
%endif
pavg%1 m4, m3, m2
add r0, FDEC_STRIDEB*4
PRED8x8_LOWPASS m3, m1, m2, m3, m5
mova [r0-4*FDEC_STRIDEB], m4
mova [r0-3*FDEC_STRIDEB], m3
mova m1, [r1+8*SIZEOF_PIXEL]
PSLLPIX m0, m1, 1
PSLLPIX m2, m1, 2
PRED8x8_LOWPASS m0, m1, m2, m0, m6
%assign Y -2
%rep 5
PALIGNR m4, m0, 7*SIZEOF_PIXEL, m5
mova [r0+Y*FDEC_STRIDEB], m4
PSLLPIX m0, m0, 1
SWAP 3, 4
%assign Y (Y+1)
%endrep
PALIGNR m4, m0, 7*SIZEOF_PIXEL, m0
mova [r0+Y*FDEC_STRIDEB], m4
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_8x8_VR w
INIT_XMM ssse3
PREDICT_8x8_VR w
INIT_XMM avx
PREDICT_8x8_VR w
%elif ARCH_X86_64 == 0
INIT_MMX mmx2
PREDICT_8x8_VR b
%endif
%macro LOAD_PLANE_ARGS 0
%if cpuflag(avx2) && ARCH_X86_64 == 0
vpbroadcastw m0, r1m
vpbroadcastw m2, r2m
vpbroadcastw m4, r3m
%elif mmsize == 8 ; MMX is only used on x86_32
SPLATW m0, r1m
SPLATW m2, r2m
SPLATW m4, r3m
%else
movd xm0, r1m
movd xm2, r2m
movd xm4, r3m
SPLATW m0, xm0
SPLATW m2, xm2
SPLATW m4, xm4
%endif
%endmacro
;-----------------------------------------------------------------------------
; void predict_8x8c_p_core( uint8_t *src, int i00, int b, int c )
;-----------------------------------------------------------------------------
%if ARCH_X86_64 == 0 && HIGH_BIT_DEPTH == 0
%macro PREDICT_CHROMA_P_MMX 1
cglobal predict_8x%1c_p_core, 1,2
LOAD_PLANE_ARGS
movq m1, m2
pmullw m2, [pw_0to15]
psllw m1, 2
paddsw m0, m2 ; m0 = {i+0*b, i+1*b, i+2*b, i+3*b}
paddsw m1, m0 ; m1 = {i+4*b, i+5*b, i+6*b, i+7*b}
mov r1d, %1
ALIGN 4
.loop:
movq m5, m0
movq m6, m1
psraw m5, 5
psraw m6, 5
packuswb m5, m6
movq [r0], m5
paddsw m0, m4
paddsw m1, m4
add r0, FDEC_STRIDE
dec r1d
jg .loop
RET
%endmacro ; PREDICT_CHROMA_P_MMX
INIT_MMX mmx2
PREDICT_CHROMA_P_MMX 8
PREDICT_CHROMA_P_MMX 16
%endif ; !ARCH_X86_64 && !HIGH_BIT_DEPTH
%macro PREDICT_CHROMA_P 1
%if HIGH_BIT_DEPTH
cglobal predict_8x%1c_p_core, 1,2,7
LOAD_PLANE_ARGS
mova m3, [pw_pixel_max]
pxor m1, m1
pmullw m2, [pw_43210123] ; b
%if %1 == 16
pmullw m5, m4, [pw_m7] ; c
%else
pmullw m5, m4, [pw_m3]
%endif
paddw m5, [pw_16]
%if mmsize == 32
mova xm6, xm4
paddw m4, m4
paddw m5, m6
%endif
mov r1d, %1/(mmsize/16)
.loop:
paddsw m6, m2, m5
paddsw m6, m0
psraw m6, 5
CLIPW m6, m1, m3
paddw m5, m4
%if mmsize == 32
vextracti128 [r0], m6, 1
mova [r0+FDEC_STRIDEB], xm6
add r0, 2*FDEC_STRIDEB
%else
mova [r0], m6
add r0, FDEC_STRIDEB
%endif
dec r1d
jg .loop
RET
%else ; !HIGH_BIT_DEPTH
cglobal predict_8x%1c_p_core, 1,2
LOAD_PLANE_ARGS
%if mmsize == 32
vbroadcasti128 m1, [pw_0to15] ; 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
pmullw m2, m1
mova xm1, xm4 ; zero upper half
paddsw m4, m4
paddsw m0, m1
%else
pmullw m2, [pw_0to15]
%endif
paddsw m0, m2 ; m0 = {i+0*b, i+1*b, i+2*b, i+3*b, i+4*b, i+5*b, i+6*b, i+7*b}
paddsw m1, m0, m4
paddsw m4, m4
mov r1d, %1/(mmsize/8)
.loop:
psraw m2, m0, 5
psraw m3, m1, 5
paddsw m0, m4
paddsw m1, m4
packuswb m2, m3
%if mmsize == 32
movq [r0+FDEC_STRIDE*1], xm2
movhps [r0+FDEC_STRIDE*3], xm2
vextracti128 xm2, m2, 1
movq [r0+FDEC_STRIDE*0], xm2
movhps [r0+FDEC_STRIDE*2], xm2
%else
movq [r0+FDEC_STRIDE*0], xm2
movhps [r0+FDEC_STRIDE*1], xm2
%endif
add r0, FDEC_STRIDE*mmsize/8
dec r1d
jg .loop
RET
%endif ; HIGH_BIT_DEPTH
%endmacro ; PREDICT_CHROMA_P
INIT_XMM sse2
PREDICT_CHROMA_P 8
PREDICT_CHROMA_P 16
INIT_XMM avx
PREDICT_CHROMA_P 8
PREDICT_CHROMA_P 16
INIT_YMM avx2
PREDICT_CHROMA_P 8
PREDICT_CHROMA_P 16
;-----------------------------------------------------------------------------
; void predict_16x16_p_core( uint8_t *src, int i00, int b, int c )
;-----------------------------------------------------------------------------
%if HIGH_BIT_DEPTH == 0 && ARCH_X86_64 == 0
INIT_MMX mmx2
cglobal predict_16x16_p_core, 1,2
LOAD_PLANE_ARGS
movq mm5, mm2
movq mm1, mm2
pmullw mm5, [pw_0to15]
psllw mm2, 3
psllw mm1, 2
movq mm3, mm2
paddsw mm0, mm5 ; mm0 = {i+ 0*b, i+ 1*b, i+ 2*b, i+ 3*b}
paddsw mm1, mm0 ; mm1 = {i+ 4*b, i+ 5*b, i+ 6*b, i+ 7*b}
paddsw mm2, mm0 ; mm2 = {i+ 8*b, i+ 9*b, i+10*b, i+11*b}
paddsw mm3, mm1 ; mm3 = {i+12*b, i+13*b, i+14*b, i+15*b}
mov r1d, 16
ALIGN 4
.loop:
movq mm5, mm0
movq mm6, mm1
psraw mm5, 5
psraw mm6, 5
packuswb mm5, mm6
movq [r0], mm5
movq mm5, mm2
movq mm6, mm3
psraw mm5, 5
psraw mm6, 5
packuswb mm5, mm6
movq [r0+8], mm5
paddsw mm0, mm4
paddsw mm1, mm4
paddsw mm2, mm4
paddsw mm3, mm4
add r0, FDEC_STRIDE
dec r1d
jg .loop
RET
%endif ; !HIGH_BIT_DEPTH && !ARCH_X86_64
%macro PREDICT_16x16_P 0
cglobal predict_16x16_p_core, 1,2,8
movd m0, r1m
movd m1, r2m
movd m2, r3m
SPLATW m0, m0, 0
SPLATW m1, m1, 0
SPLATW m2, m2, 0
pmullw m3, m1, [pw_0to15]
psllw m1, 3
%if HIGH_BIT_DEPTH
pxor m6, m6
mov r1d, 16
.loop:
mova m4, m0
mova m5, m0
mova m7, m3
paddsw m7, m6
paddsw m4, m7
paddsw m7, m1
paddsw m5, m7
psraw m4, 5
psraw m5, 5
CLIPW m4, [pb_0], [pw_pixel_max]
CLIPW m5, [pb_0], [pw_pixel_max]
mova [r0], m4
mova [r0+16], m5
add r0, FDEC_STRIDEB
paddw m6, m2
%else ; !HIGH_BIT_DEPTH
paddsw m0, m3 ; m0 = {i+ 0*b, i+ 1*b, i+ 2*b, i+ 3*b, i+ 4*b, i+ 5*b, i+ 6*b, i+ 7*b}
paddsw m1, m0 ; m1 = {i+ 8*b, i+ 9*b, i+10*b, i+11*b, i+12*b, i+13*b, i+14*b, i+15*b}
paddsw m7, m2, m2
mov r1d, 8
ALIGN 4
.loop:
psraw m3, m0, 5
psraw m4, m1, 5
paddsw m5, m0, m2
paddsw m6, m1, m2
psraw m5, 5
psraw m6, 5
packuswb m3, m4
packuswb m5, m6
mova [r0+FDEC_STRIDE*0], m3
mova [r0+FDEC_STRIDE*1], m5
paddsw m0, m7
paddsw m1, m7
add r0, FDEC_STRIDE*2
%endif ; !HIGH_BIT_DEPTH
dec r1d
jg .loop
RET
%endmacro ; PREDICT_16x16_P
INIT_XMM sse2
PREDICT_16x16_P
%if HIGH_BIT_DEPTH == 0
INIT_XMM avx
PREDICT_16x16_P
%endif
INIT_YMM avx2
cglobal predict_16x16_p_core, 1,2,8*HIGH_BIT_DEPTH
LOAD_PLANE_ARGS
%if HIGH_BIT_DEPTH
pmullw m2, [pw_0to15]
pxor m5, m5
pxor m6, m6
mova m7, [pw_pixel_max]
mov r1d, 8
.loop:
paddsw m1, m2, m5
paddw m5, m4
paddsw m1, m0
paddsw m3, m2, m5
psraw m1, 5
paddsw m3, m0
psraw m3, 5
CLIPW m1, m6, m7
mova [r0+0*FDEC_STRIDEB], m1
CLIPW m3, m6, m7
mova [r0+1*FDEC_STRIDEB], m3
paddw m5, m4
add r0, 2*FDEC_STRIDEB
%else ; !HIGH_BIT_DEPTH
vbroadcasti128 m1, [pw_0to15]
mova xm3, xm4 ; zero high bits
pmullw m1, m2
psllw m2, 3
paddsw m0, m3
paddsw m0, m1 ; X+1*C X+0*C
paddsw m1, m0, m2 ; Y+1*C Y+0*C
paddsw m4, m4
mov r1d, 4
.loop:
psraw m2, m0, 5
psraw m3, m1, 5
paddsw m0, m4
paddsw m1, m4
packuswb m2, m3 ; X+1*C Y+1*C X+0*C Y+0*C
vextracti128 [r0+0*FDEC_STRIDE], m2, 1
mova [r0+1*FDEC_STRIDE], xm2
psraw m2, m0, 5
psraw m3, m1, 5
paddsw m0, m4
paddsw m1, m4
packuswb m2, m3 ; X+3*C Y+3*C X+2*C Y+2*C
vextracti128 [r0+2*FDEC_STRIDE], m2, 1
mova [r0+3*FDEC_STRIDE], xm2
add r0, FDEC_STRIDE*4
%endif ; !HIGH_BIT_DEPTH
dec r1d
jg .loop
RET
%if HIGH_BIT_DEPTH == 0
%macro PREDICT_8x8 0
;-----------------------------------------------------------------------------
; void predict_8x8_ddl( uint8_t *src, uint8_t *edge )
;-----------------------------------------------------------------------------
cglobal predict_8x8_ddl, 2,2
mova m0, [r1+16]
%ifidn cpuname, ssse3
movd m2, [r1+32]
palignr m2, m0, 1
%else
movu m2, [r1+17]
%endif
pslldq m1, m0, 1
add r0, FDEC_STRIDE*4
PRED8x8_LOWPASS m0, m1, m2, m0, m3
%assign Y -4
%rep 8
psrldq m0, 1
movq [r0+Y*FDEC_STRIDE], m0
%assign Y (Y+1)
%endrep
RET
%ifnidn cpuname, ssse3
;-----------------------------------------------------------------------------
; void predict_8x8_ddr( uint8_t *src, uint8_t *edge )
;-----------------------------------------------------------------------------
cglobal predict_8x8_ddr, 2,2
movu m0, [r1+8]
movu m1, [r1+7]
psrldq m2, m0, 1
add r0, FDEC_STRIDE*4
PRED8x8_LOWPASS m0, m1, m2, m0, m3
psrldq m1, m0, 1
%assign Y 3
%rep 3
movq [r0+Y*FDEC_STRIDE], m0
movq [r0+(Y-1)*FDEC_STRIDE], m1
psrldq m0, 2
psrldq m1, 2
%assign Y (Y-2)
%endrep
movq [r0-3*FDEC_STRIDE], m0
movq [r0-4*FDEC_STRIDE], m1
RET
;-----------------------------------------------------------------------------
; void predict_8x8_vl( uint8_t *src, uint8_t *edge )
;-----------------------------------------------------------------------------
cglobal predict_8x8_vl, 2,2
mova m0, [r1+16]
pslldq m1, m0, 1
psrldq m2, m0, 1
pavgb m3, m0, m2
add r0, FDEC_STRIDE*4
PRED8x8_LOWPASS m0, m1, m2, m0, m5
; m0: (t0 + 2*t1 + t2 + 2) >> 2
; m3: (t0 + t1 + 1) >> 1
%assign Y -4
%rep 3
psrldq m0, 1
movq [r0+ Y *FDEC_STRIDE], m3
movq [r0+(Y+1)*FDEC_STRIDE], m0
psrldq m3, 1
%assign Y (Y+2)
%endrep
psrldq m0, 1
movq [r0+ Y *FDEC_STRIDE], m3
movq [r0+(Y+1)*FDEC_STRIDE], m0
RET
%endif ; !ssse3
;-----------------------------------------------------------------------------
; void predict_8x8_vr( uint8_t *src, uint8_t *edge )
;-----------------------------------------------------------------------------
cglobal predict_8x8_vr, 2,2
movu m2, [r1+8]
add r0, 4*FDEC_STRIDE
pslldq m1, m2, 2
pslldq m0, m2, 1
pavgb m3, m2, m0
PRED8x8_LOWPASS m0, m2, m1, m0, m4
movhps [r0-4*FDEC_STRIDE], m3
movhps [r0-3*FDEC_STRIDE], m0
%if cpuflag(ssse3)
punpckhqdq m3, m3
pshufb m0, [shuf_vr]
palignr m3, m0, 13
%else
mova m2, m0
mova m1, [pw_00ff]
pand m1, m0
psrlw m0, 8
packuswb m1, m0
pslldq m1, 4
movhlps m3, m1
shufps m1, m2, q3210
psrldq m3, 5
psrldq m1, 5
SWAP 0, 1
%endif
movq [r0+3*FDEC_STRIDE], m0
movq [r0+2*FDEC_STRIDE], m3
psrldq m0, 1
psrldq m3, 1
movq [r0+1*FDEC_STRIDE], m0
movq [r0+0*FDEC_STRIDE], m3
psrldq m0, 1
psrldq m3, 1
movq [r0-1*FDEC_STRIDE], m0
movq [r0-2*FDEC_STRIDE], m3
RET
%endmacro ; PREDICT_8x8
INIT_XMM sse2
PREDICT_8x8
INIT_XMM ssse3
PREDICT_8x8
INIT_XMM avx
PREDICT_8x8
%endif ; !HIGH_BIT_DEPTH
;-----------------------------------------------------------------------------
; void predict_8x8_vl( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_VL_10 1
cglobal predict_8x8_vl, 2,2,8
mova m0, [r1+16*SIZEOF_PIXEL]
mova m1, [r1+24*SIZEOF_PIXEL]
PALIGNR m2, m1, m0, SIZEOF_PIXEL*1, m4
PSRLPIX m4, m1, 1
pavg%1 m6, m0, m2
pavg%1 m7, m1, m4
add r0, FDEC_STRIDEB*4
mova [r0-4*FDEC_STRIDEB], m6
PALIGNR m3, m7, m6, SIZEOF_PIXEL*1, m5
mova [r0-2*FDEC_STRIDEB], m3
PALIGNR m3, m7, m6, SIZEOF_PIXEL*2, m5
mova [r0+0*FDEC_STRIDEB], m3
PALIGNR m7, m7, m6, SIZEOF_PIXEL*3, m5
mova [r0+2*FDEC_STRIDEB], m7
PALIGNR m3, m1, m0, SIZEOF_PIXEL*7, m6
PSLLPIX m5, m0, 1
PRED8x8_LOWPASS m0, m5, m2, m0, m7
PRED8x8_LOWPASS m1, m3, m4, m1, m7
PALIGNR m4, m1, m0, SIZEOF_PIXEL*1, m2
mova [r0-3*FDEC_STRIDEB], m4
PALIGNR m4, m1, m0, SIZEOF_PIXEL*2, m2
mova [r0-1*FDEC_STRIDEB], m4
PALIGNR m4, m1, m0, SIZEOF_PIXEL*3, m2
mova [r0+1*FDEC_STRIDEB], m4
PALIGNR m1, m1, m0, SIZEOF_PIXEL*4, m2
mova [r0+3*FDEC_STRIDEB], m1
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_8x8_VL_10 w
INIT_XMM ssse3
PREDICT_8x8_VL_10 w
INIT_XMM avx
PREDICT_8x8_VL_10 w
%else
INIT_MMX mmx2
PREDICT_8x8_VL_10 b
%endif
;-----------------------------------------------------------------------------
; void predict_8x8_hd( pixel *src, pixel *edge )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_HD 2
cglobal predict_8x8_hd, 2,2
add r0, 4*FDEC_STRIDEB
mova m0, [r1+ 8*SIZEOF_PIXEL] ; lt l0 l1 l2 l3 l4 l5 l6
movu m1, [r1+ 7*SIZEOF_PIXEL] ; l0 l1 l2 l3 l4 l5 l6 l7
%ifidn cpuname, ssse3
mova m2, [r1+16*SIZEOF_PIXEL] ; t7 t6 t5 t4 t3 t2 t1 t0
mova m4, m2 ; t7 t6 t5 t4 t3 t2 t1 t0
palignr m2, m0, 7*SIZEOF_PIXEL ; t6 t5 t4 t3 t2 t1 t0 lt
palignr m4, m0, 1*SIZEOF_PIXEL ; t0 lt l0 l1 l2 l3 l4 l5
%else
movu m2, [r1+15*SIZEOF_PIXEL]
movu m4, [r1+ 9*SIZEOF_PIXEL]
%endif ; cpuflag
pavg%1 m3, m0, m1
PRED8x8_LOWPASS m0, m4, m1, m0, m5
PSRLPIX m4, m2, 2 ; .. .. t6 t5 t4 t3 t2 t1
PSRLPIX m1, m2, 1 ; .. t6 t5 t4 t3 t2 t1 t0
PRED8x8_LOWPASS m1, m4, m2, m1, m5
; .. p11 p10 p9
punpckh%2 m2, m3, m0 ; p8 p7 p6 p5
punpckl%2 m3, m0 ; p4 p3 p2 p1
mova [r0+3*FDEC_STRIDEB], m3
PALIGNR m0, m2, m3, 2*SIZEOF_PIXEL, m5
mova [r0+2*FDEC_STRIDEB], m0
PALIGNR m0, m2, m3, 4*SIZEOF_PIXEL, m5
mova [r0+1*FDEC_STRIDEB], m0
PALIGNR m0, m2, m3, 6*SIZEOF_PIXEL, m3
mova [r0+0*FDEC_STRIDEB], m0
mova [r0-1*FDEC_STRIDEB], m2
PALIGNR m0, m1, m2, 2*SIZEOF_PIXEL, m5
mova [r0-2*FDEC_STRIDEB], m0
PALIGNR m0, m1, m2, 4*SIZEOF_PIXEL, m5
mova [r0-3*FDEC_STRIDEB], m0
PALIGNR m1, m1, m2, 6*SIZEOF_PIXEL, m2
mova [r0-4*FDEC_STRIDEB], m1
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_8x8_HD w, wd
INIT_XMM ssse3
PREDICT_8x8_HD w, wd
INIT_XMM avx
PREDICT_8x8_HD w, wd
%else
INIT_MMX mmx2
PREDICT_8x8_HD b, bw
;-----------------------------------------------------------------------------
; void predict_8x8_hd( uint8_t *src, uint8_t *edge )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8_HD 0
cglobal predict_8x8_hd, 2,2
add r0, 4*FDEC_STRIDE
movu m1, [r1+7]
movu m3, [r1+8]
movu m2, [r1+9]
pavgb m4, m1, m3
PRED8x8_LOWPASS m0, m1, m2, m3, m5
punpcklbw m4, m0
movhlps m0, m4
%assign Y 3
%rep 3
movq [r0+(Y)*FDEC_STRIDE], m4
movq [r0+(Y-4)*FDEC_STRIDE], m0
psrldq m4, 2
psrldq m0, 2
%assign Y (Y-1)
%endrep
movq [r0+(Y)*FDEC_STRIDE], m4
movq [r0+(Y-4)*FDEC_STRIDE], m0
RET
%endmacro
INIT_XMM sse2
PREDICT_8x8_HD
INIT_XMM avx
PREDICT_8x8_HD
%endif ; HIGH_BIT_DEPTH
%if HIGH_BIT_DEPTH == 0
;-----------------------------------------------------------------------------
; void predict_8x8_hu( uint8_t *src, uint8_t *edge )
;-----------------------------------------------------------------------------
INIT_MMX
cglobal predict_8x8_hu_sse2, 2,2
add r0, 4*FDEC_STRIDE
movq mm1, [r1+7] ; l0 l1 l2 l3 l4 l5 l6 l7
pshufw mm0, mm1, q0123 ; l6 l7 l4 l5 l2 l3 l0 l1
movq mm2, mm0
psllw mm0, 8
psrlw mm2, 8
por mm2, mm0 ; l7 l6 l5 l4 l3 l2 l1 l0
psllq mm1, 56 ; l7 .. .. .. .. .. .. ..
movq mm3, mm2
movq mm4, mm2
movq mm5, mm2
psrlq mm2, 8
psrlq mm3, 16
por mm2, mm1 ; l7 l7 l6 l5 l4 l3 l2 l1
punpckhbw mm1, mm1
por mm3, mm1 ; l7 l7 l7 l6 l5 l4 l3 l2
pavgb mm4, mm2
PRED8x8_LOWPASS mm1, mm3, mm5, mm2, mm6
movq2dq xmm0, mm4
movq2dq xmm1, mm1
punpcklbw xmm0, xmm1
punpckhbw mm4, mm1
%assign Y -4
%rep 3
movq [r0+Y*FDEC_STRIDE], xmm0
psrldq xmm0, 2
%assign Y (Y+1)
%endrep
pshufw mm5, mm4, q3321
pshufw mm6, mm4, q3332
pshufw mm7, mm4, q3333
movq [r0+Y*FDEC_STRIDE], xmm0
movq [r0+0*FDEC_STRIDE], mm4
movq [r0+1*FDEC_STRIDE], mm5
movq [r0+2*FDEC_STRIDE], mm6
movq [r0+3*FDEC_STRIDE], mm7
RET
INIT_XMM
cglobal predict_8x8_hu_ssse3, 2,2
add r0, 4*FDEC_STRIDE
movq m3, [r1+7]
pshufb m3, [shuf_hu]
psrldq m1, m3, 1
psrldq m2, m3, 2
pavgb m0, m1, m3
PRED8x8_LOWPASS m1, m3, m2, m1, m4
punpcklbw m0, m1
%assign Y -4
%rep 3
movq [r0+ Y *FDEC_STRIDE], m0
movhps [r0+(Y+4)*FDEC_STRIDE], m0
psrldq m0, 2
pshufhw m0, m0, q2210
%assign Y (Y+1)
%endrep
movq [r0+ Y *FDEC_STRIDE], m0
movhps [r0+(Y+4)*FDEC_STRIDE], m0
RET
%endif ; !HIGH_BIT_DEPTH
;-----------------------------------------------------------------------------
; void predict_8x8c_v( uint8_t *src )
;-----------------------------------------------------------------------------
%macro PREDICT_8x8C_V 0
cglobal predict_8x8c_v, 1,1
mova m0, [r0 - FDEC_STRIDEB]
STORE8 m0
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse
PREDICT_8x8C_V
%else
INIT_MMX mmx
PREDICT_8x8C_V
%endif
%if HIGH_BIT_DEPTH
INIT_MMX
cglobal predict_8x8c_v_mmx, 1,1
mova m0, [r0 - FDEC_STRIDEB]
mova m1, [r0 - FDEC_STRIDEB + 8]
%assign Y 0
%rep 8
mova [r0 + (Y&1)*FDEC_STRIDEB], m0
mova [r0 + (Y&1)*FDEC_STRIDEB + 8], m1
%if (Y&1) && (Y!=7)
add r0, FDEC_STRIDEB*2
%endif
%assign Y Y+1
%endrep
RET
%endif
%macro PREDICT_8x16C_V 0
cglobal predict_8x16c_v, 1,1
mova m0, [r0 - FDEC_STRIDEB]
STORE16 m0
RET
%endmacro
%if HIGH_BIT_DEPTH
INIT_XMM sse
PREDICT_8x16C_V
%else
INIT_MMX mmx
PREDICT_8x16C_V
%endif
;-----------------------------------------------------------------------------
; void predict_8x8c_h( uint8_t *src )
;-----------------------------------------------------------------------------
%macro PREDICT_C_H 0
cglobal predict_8x8c_h, 1,1
%if cpuflag(ssse3) && notcpuflag(avx2)
mova m2, [pb_3]
%endif
PRED_H_4ROWS 8, 1
PRED_H_4ROWS 8, 0
RET
cglobal predict_8x16c_h, 1,2
%if cpuflag(ssse3) && notcpuflag(avx2)
mova m2, [pb_3]
%endif
mov r1d, 4
.loop:
PRED_H_4ROWS 8, 1
dec r1d
jg .loop
RET
%endmacro
INIT_MMX mmx2
PREDICT_C_H
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_C_H
INIT_XMM avx2
PREDICT_C_H
%else
INIT_MMX ssse3
PREDICT_C_H
%endif
;-----------------------------------------------------------------------------
; void predict_8x8c_dc( pixel *src )
;-----------------------------------------------------------------------------
%macro LOAD_LEFT 1
movzx r1d, pixel [r0+FDEC_STRIDEB*(%1-4)-SIZEOF_PIXEL]
movzx r2d, pixel [r0+FDEC_STRIDEB*(%1-3)-SIZEOF_PIXEL]
add r1d, r2d
movzx r2d, pixel [r0+FDEC_STRIDEB*(%1-2)-SIZEOF_PIXEL]
add r1d, r2d
movzx r2d, pixel [r0+FDEC_STRIDEB*(%1-1)-SIZEOF_PIXEL]
add r1d, r2d
%endmacro
%macro PREDICT_8x8C_DC 0
cglobal predict_8x8c_dc, 1,3
pxor m7, m7
%if HIGH_BIT_DEPTH
movq m0, [r0-FDEC_STRIDEB+0]
movq m1, [r0-FDEC_STRIDEB+8]
HADDW m0, m2
HADDW m1, m2
%else ; !HIGH_BIT_DEPTH
movd m0, [r0-FDEC_STRIDEB+0]
movd m1, [r0-FDEC_STRIDEB+4]
psadbw m0, m7 ; s0
psadbw m1, m7 ; s1
%endif
add r0, FDEC_STRIDEB*4
LOAD_LEFT 0 ; s2
movd m2, r1d
LOAD_LEFT 4 ; s3
movd m3, r1d
punpcklwd m0, m1
punpcklwd m2, m3
punpckldq m0, m2 ; s0, s1, s2, s3
pshufw m3, m0, q3312 ; s2, s1, s3, s3
pshufw m0, m0, q1310 ; s0, s1, s3, s1
paddw m0, m3
psrlw m0, 2
pavgw m0, m7 ; s0+s2, s1, s3, s1+s3
%if HIGH_BIT_DEPTH
%if cpuflag(sse2)
movq2dq xmm0, m0
punpcklwd xmm0, xmm0
pshufd xmm1, xmm0, q3322
punpckldq xmm0, xmm0
%assign Y 0
%rep 8
%assign i (0 + (Y/4))
movdqa [r0+FDEC_STRIDEB*(Y-4)+0], xmm %+ i
%assign Y Y+1
%endrep
%else ; !sse2
pshufw m1, m0, q0000
pshufw m2, m0, q1111
pshufw m3, m0, q2222
pshufw m4, m0, q3333
%assign Y 0
%rep 8
%assign i (1 + (Y/4)*2)
%assign j (2 + (Y/4)*2)
movq [r0+FDEC_STRIDEB*(Y-4)+0], m %+ i
movq [r0+FDEC_STRIDEB*(Y-4)+8], m %+ j
%assign Y Y+1
%endrep
%endif
%else ; !HIGH_BIT_DEPTH
packuswb m0, m0
punpcklbw m0, m0
movq m1, m0
punpcklbw m0, m0
punpckhbw m1, m1
%assign Y 0
%rep 8
%assign i (0 + (Y/4))
movq [r0+FDEC_STRIDEB*(Y-4)], m %+ i
%assign Y Y+1
%endrep
%endif
RET
%endmacro
INIT_MMX mmx2
PREDICT_8x8C_DC
%if HIGH_BIT_DEPTH
INIT_MMX sse2
PREDICT_8x8C_DC
%endif
%if HIGH_BIT_DEPTH
%macro STORE_4LINES 3
%if cpuflag(sse2)
movdqa [r0+FDEC_STRIDEB*(%3-4)], %1
movdqa [r0+FDEC_STRIDEB*(%3-3)], %1
movdqa [r0+FDEC_STRIDEB*(%3-2)], %1
movdqa [r0+FDEC_STRIDEB*(%3-1)], %1
%else
movq [r0+FDEC_STRIDEB*(%3-4)+0], %1
movq [r0+FDEC_STRIDEB*(%3-4)+8], %2
movq [r0+FDEC_STRIDEB*(%3-3)+0], %1
movq [r0+FDEC_STRIDEB*(%3-3)+8], %2
movq [r0+FDEC_STRIDEB*(%3-2)+0], %1
movq [r0+FDEC_STRIDEB*(%3-2)+8], %2
movq [r0+FDEC_STRIDEB*(%3-1)+0], %1
movq [r0+FDEC_STRIDEB*(%3-1)+8], %2
%endif
%endmacro
%else
%macro STORE_4LINES 2
movq [r0+FDEC_STRIDEB*(%2-4)], %1
movq [r0+FDEC_STRIDEB*(%2-3)], %1
movq [r0+FDEC_STRIDEB*(%2-2)], %1
movq [r0+FDEC_STRIDEB*(%2-1)], %1
%endmacro
%endif
%macro PREDICT_8x16C_DC 0
cglobal predict_8x16c_dc, 1,3
pxor m7, m7
%if HIGH_BIT_DEPTH
movq m0, [r0-FDEC_STRIDEB+0]
movq m1, [r0-FDEC_STRIDEB+8]
HADDW m0, m2
HADDW m1, m2
%else
movd m0, [r0-FDEC_STRIDEB+0]
movd m1, [r0-FDEC_STRIDEB+4]
psadbw m0, m7 ; s0
psadbw m1, m7 ; s1
%endif
punpcklwd m0, m1 ; s0, s1
add r0, FDEC_STRIDEB*4
LOAD_LEFT 0 ; s2
pinsrw m0, r1d, 2
LOAD_LEFT 4 ; s3
pinsrw m0, r1d, 3 ; s0, s1, s2, s3
add r0, FDEC_STRIDEB*8
LOAD_LEFT 0 ; s4
pinsrw m1, r1d, 2
LOAD_LEFT 4 ; s5
pinsrw m1, r1d, 3 ; s1, __, s4, s5
sub r0, FDEC_STRIDEB*8
pshufw m2, m0, q1310 ; s0, s1, s3, s1
pshufw m0, m0, q3312 ; s2, s1, s3, s3
pshufw m3, m1, q0302 ; s4, s1, s5, s1
pshufw m1, m1, q3322 ; s4, s4, s5, s5
paddw m0, m2
paddw m1, m3
psrlw m0, 2
psrlw m1, 2
pavgw m0, m7
pavgw m1, m7
%if HIGH_BIT_DEPTH
%if cpuflag(sse2)
movq2dq xmm0, m0
movq2dq xmm1, m1
punpcklwd xmm0, xmm0
punpcklwd xmm1, xmm1
pshufd xmm2, xmm0, q3322
pshufd xmm3, xmm1, q3322
punpckldq xmm0, xmm0
punpckldq xmm1, xmm1
STORE_4LINES xmm0, xmm0, 0
STORE_4LINES xmm2, xmm2, 4
STORE_4LINES xmm1, xmm1, 8
STORE_4LINES xmm3, xmm3, 12
%else
pshufw m2, m0, q0000
pshufw m3, m0, q1111
pshufw m4, m0, q2222
pshufw m5, m0, q3333
STORE_4LINES m2, m3, 0
STORE_4LINES m4, m5, 4
pshufw m2, m1, q0000
pshufw m3, m1, q1111
pshufw m4, m1, q2222
pshufw m5, m1, q3333
STORE_4LINES m2, m3, 8
STORE_4LINES m4, m5, 12
%endif
%else
packuswb m0, m0 ; dc0, dc1, dc2, dc3
packuswb m1, m1 ; dc4, dc5, dc6, dc7
punpcklbw m0, m0
punpcklbw m1, m1
pshufw m2, m0, q1100
pshufw m3, m0, q3322
pshufw m4, m1, q1100
pshufw m5, m1, q3322
STORE_4LINES m2, 0
STORE_4LINES m3, 4
add r0, FDEC_STRIDEB*8
STORE_4LINES m4, 0
STORE_4LINES m5, 4
%endif
RET
%endmacro
INIT_MMX mmx2
PREDICT_8x16C_DC
%if HIGH_BIT_DEPTH
INIT_MMX sse2
PREDICT_8x16C_DC
%endif
%macro PREDICT_C_DC_TOP 1
%if HIGH_BIT_DEPTH
INIT_XMM
cglobal predict_8x%1c_dc_top_sse2, 1,1
pxor m2, m2
mova m0, [r0 - FDEC_STRIDEB]
pshufd m1, m0, q2301
paddw m0, m1
pshuflw m1, m0, q2301
pshufhw m1, m1, q2301
paddw m0, m1
psrlw m0, 1
pavgw m0, m2
STORE%1 m0
RET
%else ; !HIGH_BIT_DEPTH
INIT_MMX
cglobal predict_8x%1c_dc_top_mmx2, 1,1
movq mm0, [r0 - FDEC_STRIDE]
pxor mm1, mm1
pxor mm2, mm2
punpckhbw mm1, mm0
punpcklbw mm0, mm2
psadbw mm1, mm2 ; s1
psadbw mm0, mm2 ; s0
psrlw mm1, 1
psrlw mm0, 1
pavgw mm1, mm2
pavgw mm0, mm2
pshufw mm1, mm1, 0
pshufw mm0, mm0, 0 ; dc0 (w)
packuswb mm0, mm1 ; dc0,dc1 (b)
STORE%1 mm0
RET
%endif
%endmacro
PREDICT_C_DC_TOP 8
PREDICT_C_DC_TOP 16
;-----------------------------------------------------------------------------
; void predict_16x16_v( pixel *src )
;-----------------------------------------------------------------------------
%macro PREDICT_16x16_V 0
cglobal predict_16x16_v, 1,2
%assign %%i 0
%rep 16*SIZEOF_PIXEL/mmsize
mova m %+ %%i, [r0-FDEC_STRIDEB+%%i*mmsize]
%assign %%i %%i+1
%endrep
%if 16*SIZEOF_PIXEL/mmsize == 4
STORE16 m0, m1, m2, m3
%elif 16*SIZEOF_PIXEL/mmsize == 2
STORE16 m0, m1
%else
STORE16 m0
%endif
RET
%endmacro
INIT_MMX mmx2
PREDICT_16x16_V
INIT_XMM sse
PREDICT_16x16_V
%if HIGH_BIT_DEPTH
INIT_YMM avx
PREDICT_16x16_V
%endif
;-----------------------------------------------------------------------------
; void predict_16x16_h( pixel *src )
;-----------------------------------------------------------------------------
%macro PREDICT_16x16_H 0
cglobal predict_16x16_h, 1,2
%if cpuflag(ssse3) && notcpuflag(avx2)
mova m2, [pb_3]
%endif
mov r1d, 4
.loop:
PRED_H_4ROWS 16, 1
dec r1d
jg .loop
RET
%endmacro
INIT_MMX mmx2
PREDICT_16x16_H
%if HIGH_BIT_DEPTH
INIT_XMM sse2
PREDICT_16x16_H
INIT_YMM avx2
PREDICT_16x16_H
%else
;no SSE2 for 8-bit, it's slower than MMX on all systems that don't support SSSE3
INIT_XMM ssse3
PREDICT_16x16_H
%endif
;-----------------------------------------------------------------------------
; void predict_16x16_dc_core( pixel *src, int i_dc_left )
;-----------------------------------------------------------------------------
%macro PRED16x16_DC_MMX 2
%if HIGH_BIT_DEPTH
mova m0, [r0 - FDEC_STRIDEB+ 0]
paddw m0, [r0 - FDEC_STRIDEB+ 8]
paddw m0, [r0 - FDEC_STRIDEB+16]
paddw m0, [r0 - FDEC_STRIDEB+24]
HADDW m0, m1
paddw m0, %1
psrlw m0, %2
SPLATW m0, m0
STORE16 m0, m0, m0, m0
%else ; !HIGH_BIT_DEPTH
pxor m0, m0
pxor m1, m1
psadbw m0, [r0 - FDEC_STRIDE]
psadbw m1, [r0 - FDEC_STRIDE + 8]
paddusw m0, m1
paddusw m0, %1
psrlw m0, %2 ; dc
pshufw m0, m0, 0
packuswb m0, m0 ; dc in bytes
STORE16 m0, m0
%endif
%endmacro
INIT_MMX mmx2
cglobal predict_16x16_dc_core, 1,2
%if ARCH_X86_64
movd m6, r1d
PRED16x16_DC_MMX m6, 5
%else
PRED16x16_DC_MMX r1m, 5
%endif
RET
INIT_MMX mmx2
cglobal predict_16x16_dc_top, 1,2
PRED16x16_DC_MMX [pw_8], 4
RET
INIT_MMX mmx2
%if HIGH_BIT_DEPTH
cglobal predict_16x16_dc_left_core, 1,2
movd m0, r1m
SPLATW m0, m0
STORE16 m0, m0, m0, m0
RET
%else ; !HIGH_BIT_DEPTH
cglobal predict_16x16_dc_left_core, 1,1
movd m0, r1m
pshufw m0, m0, 0
packuswb m0, m0
STORE16 m0, m0
RET
%endif
%macro PRED16x16_DC 2
%if HIGH_BIT_DEPTH
mova xm0, [r0 - FDEC_STRIDEB+ 0]
paddw xm0, [r0 - FDEC_STRIDEB+16]
HADDW xm0, xm2
paddw xm0, %1
psrlw xm0, %2
SPLATW m0, xm0
%if mmsize == 32
STORE16 m0
%else
STORE16 m0, m0
%endif
%else ; !HIGH_BIT_DEPTH
pxor m0, m0
psadbw m0, [r0 - FDEC_STRIDE]
MOVHL m1, m0
paddw m0, m1
paddusw m0, %1
psrlw m0, %2 ; dc
SPLATW m0, m0
packuswb m0, m0 ; dc in bytes
STORE16 m0
%endif
%endmacro
%macro PREDICT_16x16_DC_CORE 0
cglobal predict_16x16_dc_core, 2,2,4
movd xm3, r1m
PRED16x16_DC xm3, 5
RET
cglobal predict_16x16_dc_top, 1,2
PRED16x16_DC [pw_8], 4
RET
cglobal predict_16x16_dc_left_core, 1,2
movd xm0, r1m
SPLATW m0, xm0
%if HIGH_BIT_DEPTH && mmsize == 16
STORE16 m0, m0
%else
%if HIGH_BIT_DEPTH == 0
packuswb m0, m0
%endif
STORE16 m0
%endif
RET
%endmacro
INIT_XMM sse2
PREDICT_16x16_DC_CORE
%if HIGH_BIT_DEPTH
INIT_YMM avx2
PREDICT_16x16_DC_CORE
%else
INIT_XMM avx2
PREDICT_16x16_DC_CORE
%endif
| malvanos/Video-SIMDBench | src/asm/x86/predict-a.asm | Assembly | bsd-3-clause | 60,212 |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; WriteCr2.Asm
;
; Abstract:
;
; AsmWriteCr2 function
;
; Notes:
;
;------------------------------------------------------------------------------
.code
;------------------------------------------------------------------------------
; UINTN
; EFIAPI
; AsmWriteCr2 (
; UINTN Cr2
; );
;------------------------------------------------------------------------------
AsmWriteCr2 PROC
mov cr2, rcx
mov rax, rcx
ret
AsmWriteCr2 ENDP
END
| tenpoku1000/UEFI_SecureBoot | src/lib/external/BSD/UDK/MdePkg/Library/BaseLib/X64/WriteCr2.asm | Assembly | mit | 1,057 |
;
; jdmerge.asm - merged upsampling/color conversion (MMX)
;
; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
; Copyright (C) 2009, 2016, D. R. Commander.
;
; Based on the x86 SIMD extension for IJG JPEG library
; Copyright (C) 1999-2006, MIYASAKA Masaru.
; For conditions of distribution and use, see copyright notice in jsimdext.inc
;
; This file should be assembled with NASM (Netwide Assembler),
; can *not* be assembled with Microsoft's MASM or any compatible
; assembler (including Borland's Turbo Assembler).
; NASM is available from http://nasm.sourceforge.net/ or
; http://sourceforge.net/project/showfiles.php?group_id=6208
;
; [TAB8]
%include "jsimdext.inc"
; --------------------------------------------------------------------------
%define SCALEBITS 16
F_0_344 equ 22554 ; FIX(0.34414)
F_0_714 equ 46802 ; FIX(0.71414)
F_1_402 equ 91881 ; FIX(1.40200)
F_1_772 equ 116130 ; FIX(1.77200)
F_0_402 equ (F_1_402 - 65536) ; FIX(1.40200) - FIX(1)
F_0_285 equ ( 65536 - F_0_714) ; FIX(1) - FIX(0.71414)
F_0_228 equ (131072 - F_1_772) ; FIX(2) - FIX(1.77200)
; --------------------------------------------------------------------------
SECTION SEG_CONST
alignz 32
GLOBAL_DATA(jconst_merged_upsample_mmx)
EXTN(jconst_merged_upsample_mmx):
PW_F0402 times 4 dw F_0_402
PW_MF0228 times 4 dw -F_0_228
PW_MF0344_F0285 times 2 dw -F_0_344, F_0_285
PW_ONE times 4 dw 1
PD_ONEHALF times 2 dd 1 << (SCALEBITS - 1)
alignz 32
; --------------------------------------------------------------------------
SECTION SEG_TEXT
BITS 32
%include "jdmrgext-mmx.asm"
%undef RGB_RED
%undef RGB_GREEN
%undef RGB_BLUE
%undef RGB_PIXELSIZE
%define RGB_RED EXT_RGB_RED
%define RGB_GREEN EXT_RGB_GREEN
%define RGB_BLUE EXT_RGB_BLUE
%define RGB_PIXELSIZE EXT_RGB_PIXELSIZE
%define jsimd_h2v1_merged_upsample_mmx jsimd_h2v1_extrgb_merged_upsample_mmx
%define jsimd_h2v2_merged_upsample_mmx jsimd_h2v2_extrgb_merged_upsample_mmx
%include "jdmrgext-mmx.asm"
%undef RGB_RED
%undef RGB_GREEN
%undef RGB_BLUE
%undef RGB_PIXELSIZE
%define RGB_RED EXT_RGBX_RED
%define RGB_GREEN EXT_RGBX_GREEN
%define RGB_BLUE EXT_RGBX_BLUE
%define RGB_PIXELSIZE EXT_RGBX_PIXELSIZE
%define jsimd_h2v1_merged_upsample_mmx jsimd_h2v1_extrgbx_merged_upsample_mmx
%define jsimd_h2v2_merged_upsample_mmx jsimd_h2v2_extrgbx_merged_upsample_mmx
%include "jdmrgext-mmx.asm"
%undef RGB_RED
%undef RGB_GREEN
%undef RGB_BLUE
%undef RGB_PIXELSIZE
%define RGB_RED EXT_BGR_RED
%define RGB_GREEN EXT_BGR_GREEN
%define RGB_BLUE EXT_BGR_BLUE
%define RGB_PIXELSIZE EXT_BGR_PIXELSIZE
%define jsimd_h2v1_merged_upsample_mmx jsimd_h2v1_extbgr_merged_upsample_mmx
%define jsimd_h2v2_merged_upsample_mmx jsimd_h2v2_extbgr_merged_upsample_mmx
%include "jdmrgext-mmx.asm"
%undef RGB_RED
%undef RGB_GREEN
%undef RGB_BLUE
%undef RGB_PIXELSIZE
%define RGB_RED EXT_BGRX_RED
%define RGB_GREEN EXT_BGRX_GREEN
%define RGB_BLUE EXT_BGRX_BLUE
%define RGB_PIXELSIZE EXT_BGRX_PIXELSIZE
%define jsimd_h2v1_merged_upsample_mmx jsimd_h2v1_extbgrx_merged_upsample_mmx
%define jsimd_h2v2_merged_upsample_mmx jsimd_h2v2_extbgrx_merged_upsample_mmx
%include "jdmrgext-mmx.asm"
%undef RGB_RED
%undef RGB_GREEN
%undef RGB_BLUE
%undef RGB_PIXELSIZE
%define RGB_RED EXT_XBGR_RED
%define RGB_GREEN EXT_XBGR_GREEN
%define RGB_BLUE EXT_XBGR_BLUE
%define RGB_PIXELSIZE EXT_XBGR_PIXELSIZE
%define jsimd_h2v1_merged_upsample_mmx jsimd_h2v1_extxbgr_merged_upsample_mmx
%define jsimd_h2v2_merged_upsample_mmx jsimd_h2v2_extxbgr_merged_upsample_mmx
%include "jdmrgext-mmx.asm"
%undef RGB_RED
%undef RGB_GREEN
%undef RGB_BLUE
%undef RGB_PIXELSIZE
%define RGB_RED EXT_XRGB_RED
%define RGB_GREEN EXT_XRGB_GREEN
%define RGB_BLUE EXT_XRGB_BLUE
%define RGB_PIXELSIZE EXT_XRGB_PIXELSIZE
%define jsimd_h2v1_merged_upsample_mmx jsimd_h2v1_extxrgb_merged_upsample_mmx
%define jsimd_h2v2_merged_upsample_mmx jsimd_h2v2_extxrgb_merged_upsample_mmx
%include "jdmrgext-mmx.asm"
| endlessm/chromium-browser | third_party/libjpeg_turbo/simd/i386/jdmerge-mmx.asm | Assembly | bsd-3-clause | 4,066 |
; Program 8.8
; AVX - MASM (32-bit)
; Copyright (c) 2017 Hall & Slonka
.686
.XMM
.MODEL FLAT, C
.STACK 4096
ExitProcess PROTO stdcall, dwExitCode:DWORD
.data
vectorA REAL4 1.2, 3.4, 5.6, 7.8, 8.9, 9.0, 0.9, 9.8
vectorB REAL4 7.8, 5.6, 3.4, 1.2, 0.1, 0.0, 8.1, -0.8
vectorC DWORD 1, 1, 1, 1
vectorD DWORD -2, -2, -2, -2
.code
_main PROC ; AVX/AVX2 example
lea eax, vectorA
lea ebx, vectorB
vmovups ymm0, YMMWORD PTR [eax] ; move vectorA to YMM0
vmovups ymm1, YMMWORD PTR [ebx] ; move vectorA to YMM1
vaddps ymm2, ymm1, ymm0 ; add vectorA and B, store in YMM2
lea eax, vectorC
lea ebx, vectorD
vmovdqa xmm3, XMMWORD PTR [eax] ; move vectorC to XMM3
vmovdqa xmm4, XMMWORD PTR [ebx] ; move vectorC to XMM4
vpsignd xmm4, xmm3, vectorD ; negate sign of XMM3 values if vectorD
; values are < 0, store in XMM4
; vpsign AVX support
; (CPUID for 128 or 256-bit capability)
INVOKE ExitProcess, 0
_main ENDP
END
| brianrhall/Assembly | Chapter_8/Program 8.8_AVX/x86/Program_8.8_MASM.asm | Assembly | mit | 938 |
// init SP pointing to 256
@256
D=A
@SP
M=D
// init LCL pointing to 300
@300
D=A
@LCL
M=D
// init ARG pointing to 400
@400
D=A
@ARG
M=D
// init THIS pointing to 3000
@3000
D=A
@THIS
M=D
// init THAT pointing to 3010
@3010
D=A
@THAT
M=D
// constant
@3030
D=A // Store the numeric value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// segment direct
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // store popped value in D
@R3 // set address to R3
M=D // store the value at the address
// constant
@3040
D=A // Store the numeric value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// segment direct
@1
D=A // Store the index value in D
@R3 // set address to R3
D=D+A // store the address of R3 + index in D
@R13 // temp store the address
M=D // store the address in R13
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // store the value in D
@R13 // R13 address
A=M // use the value stored in R13 as the next address
M=D // store the value at the address
// constant
@32
D=A // Store the numeric value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// this
@2
D=A // Store the index value in D
@THIS // set address to THIS
D=D+M // store the address stored in THIS + index in D
@R13 // temp store the address
M=D // store the address in R13
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // store the value in D
@R13 // R13 address
A=M // use the value stored in R13 as the next address
M=D // store the value at the address
// constant
@46
D=A // Store the numeric value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// that
@6
D=A // Store the index value in D
@THAT // set address to THAT
D=D+M // store the address stored in THAT + index in D
@R13 // temp store the address
M=D // store the address in R13
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // store the value in D
@R13 // R13 address
A=M // use the value stored in R13 as the next address
M=D // store the value at the address
// segment direct
@0
D=A // Store the index value in D
@R3 // set address to R3
A=D+A // set the address to be address of R3 + index
D=M // store the push value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// segment direct
@1
D=A // Store the index value in D
@R3 // set address to R3
A=D+A // set the address to be address of R3 + index
D=M // store the push value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// add
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // the last entered value
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=D+M // x+y
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// this
@2
D=A // Store the index value in D
@THIS // set address to THIS
A=D+M // set the address to be THIS + index
D=M // store the push value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// sub
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // the last entered value
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M-D // x-y
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// that
@6
D=A // Store the index value in D
@THAT // set address to THAT
A=D+M // set the address to be THAT + index
D=M // store the push value in D
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
// add
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=M // the last entered value
// POP
@SP
M=M-1 // decrement (pop) the stack pointer
A=M // set the address to where the SP is pointing
D=D+M // x+y
// PUSH
@SP
A=M // set the address to where the SP is pointing
M=D // store the value in the stack
@SP
M=M+1 // Advance the stack pointer
| theapi/nand2tetris | projects/07/MemoryAccess/PointerTest/PointerTest.asm | Assembly | mit | 5,179 |
;------------------------------------
;- Generated Initialization File --
;------------------------------------
$include (C8051F020.inc)
cseg at 0
jmp main
main:
mov P0MDOUT,#02h
mov XBR2,#40h
call Oscillator_Init
call Timer_Init
setb TR0
loop:
jnb TF0,loop
cpl P0.1
clr TF0
sjmp loop
;
;INIT SEGMENT CODE
; rseg INIT
; Peripheral specific initialization functions,
; Called from the Init_Device label
Timer_Init:
mov CKCON, #08h
mov TMOD, #02h
mov TL0, #-120
mov TH0, #-120
ret
Oscillator_Init:
mov OSCXCN, #067h
mov R0, #030 ; Wait 1ms for initialization
Osc_Wait1:
clr A
djnz ACC, $
djnz R0, Osc_Wait1
Osc_Wait2:
mov A, OSCXCN
jnb ACC.7, Osc_Wait2
mov OSCICN, #008h
ret
; Initialization function for device,
; Call Init_Device from your main program
END
| tblong/school | ECET 3220/Code/Verify Oscillator/verify.asm | Assembly | mit | 932 |
; Licensed to the .NET Foundation under one or more agreements.
; The .NET Foundation licenses this file to you under the MIT license.
; See the LICENSE file in the project root for more information.
;; ==++==
;;
;;
;; ==--==
#include "ksarm.h"
#include "asmconstants.h"
#include "asmmacros.h"
SETALIAS JIT_Box,?JIT_Box@@YAPAVObject@@PAUCORINFO_CLASS_STRUCT_@@PAX@Z
SETALIAS JIT_New, ?JIT_New@@YAPAVObject@@PAUCORINFO_CLASS_STRUCT_@@@Z
SETALIAS JIT_Box, ?JIT_Box@@YAPAVObject@@PAUCORINFO_CLASS_STRUCT_@@PAX@Z
SETALIAS FramedAllocateString, ?FramedAllocateString@@YAPAVStringObject@@K@Z
SETALIAS g_pStringClass, ?g_pStringClass@@3PAVMethodTable@@A
SETALIAS JIT_NewArr1, ?JIT_NewArr1@@YAPAVObject@@PAUCORINFO_CLASS_STRUCT_@@H@Z
SETALIAS CopyValueClassUnchecked, ?CopyValueClassUnchecked@@YAXPAX0PAVMethodTable@@@Z
IMPORT $JIT_New
IMPORT $JIT_Box
IMPORT $FramedAllocateString
IMPORT $g_pStringClass
IMPORT $JIT_NewArr1
IMPORT $CopyValueClassUnchecked
IMPORT SetAppDomainInObject
IMPORT JIT_GetSharedNonGCStaticBase_Helper
IMPORT JIT_GetSharedGCStaticBase_Helper
EXPORT JIT_TrialAllocSFastMP_InlineGetThread__PatchTLSOffset
EXPORT JIT_BoxFastMP_InlineGetThread__PatchTLSOffset
EXPORT AllocateStringFastMP_InlineGetThread__PatchTLSOffset
EXPORT JIT_NewArr1VC_MP_InlineGetThread__PatchTLSOffset
EXPORT JIT_NewArr1OBJ_MP_InlineGetThread__PatchTLSOffset
EXPORT JIT_GetSharedNonGCStaticBase__PatchTLSLabel
EXPORT JIT_GetSharedNonGCStaticBaseNoCtor__PatchTLSLabel
EXPORT JIT_GetSharedGCStaticBase__PatchTLSLabel
EXPORT JIT_GetSharedGCStaticBaseNoCtor__PatchTLSLabel
MACRO
PATCHABLE_INLINE_GETTHREAD $reg, $label
$label
mrc p15, 0, $reg, c13, c0, 2
ldr $reg, [$reg, #0xe10]
MEND
MACRO
PATCHABLE_INLINE_GETAPPDOMAIN $reg, $label
$label
mrc p15, 0, $reg, c13, c0, 2
ldr $reg, [$reg, #0xe10]
MEND
TEXTAREA
MACRO
FIX_INDIRECTION $Reg, $label
#ifdef FEATURE_PREJIT
tst $Reg, #1
beq $label
ldr $Reg, [$Reg, #-1]
$label
#endif
MEND
; ------------------------------------------------------------------
; Start of the writeable code region
LEAF_ENTRY JIT_PatchedCodeStart
bx lr
LEAF_END
; ------------------------------------------------------------------
; Optimized TLS getters
ALIGN 4
LEAF_ENTRY GetThread
; This will be overwritten at runtime with optimized GetThread implementation
b GetTLSDummy
; Just allocate space that will be filled in at runtime
SPACE (TLS_GETTER_MAX_SIZE_ASM - 2)
LEAF_END
ALIGN 4
LEAF_ENTRY GetAppDomain
; This will be overwritten at runtime with optimized GetThread implementation
b GetTLSDummy
; Just allocate space that will be filled in at runtime
SPACE (TLS_GETTER_MAX_SIZE_ASM - 2)
LEAF_END
LEAF_ENTRY GetTLSDummy
mov r0, #0
bx lr
LEAF_END
ALIGN 4
LEAF_ENTRY ClrFlsGetBlock
; This will be overwritten at runtime with optimized ClrFlsGetBlock implementation
b GetTLSDummy
; Just allocate space that will be filled in at runtime
SPACE (TLS_GETTER_MAX_SIZE_ASM - 2)
LEAF_END
; ------------------------------------------------------------------
; GC write barrier support.
;
; GC Write barriers are defined in asmhelpers.asm. The following functions are used to define
; patchable location where the write-barriers are copied over at runtime
LEAF_ENTRY JIT_PatchedWriteBarrierStart
; Cannot be empty function to prevent LNK1223
bx lr
LEAF_END
; These write barriers are overwritten on the fly
; See ValidateWriteBarriers on how the sizes of these should be calculated
ALIGN 4
LEAF_ENTRY JIT_WriteBarrier
SPACE (0x84)
LEAF_END_MARKED JIT_WriteBarrier
ALIGN 4
LEAF_ENTRY JIT_CheckedWriteBarrier
SPACE (0x9C)
LEAF_END_MARKED JIT_CheckedWriteBarrier
ALIGN 4
LEAF_ENTRY JIT_ByRefWriteBarrier
SPACE (0xA0)
LEAF_END_MARKED JIT_ByRefWriteBarrier
LEAF_ENTRY JIT_PatchedWriteBarrierLast
; Cannot be empty function to prevent LNK1223
bx lr
LEAF_END
; JIT Allocation helpers when TLS Index for Thread is low enough for fast helpers
;---------------------------------------------------------------------------
; IN: r0: MethodTable*
;; OUT: r0: new object
LEAF_ENTRY JIT_TrialAllocSFastMP_InlineGetThread
;get object size
ldr r1, [r0, #MethodTable__m_BaseSize]
; m_BaseSize is guaranteed to be a multiple of 4.
;getThread
PATCHABLE_INLINE_GETTHREAD r12, JIT_TrialAllocSFastMP_InlineGetThread__PatchTLSOffset
;load current allocation pointers
ldr r2, [r12, #Thread__m_alloc_context__alloc_limit]
ldr r3, [r12, #Thread__m_alloc_context__alloc_ptr]
;add object size to current pointer
add r1, r3
;if beyond the limit call c++ method
cmp r1, r2
bhi AllocFailed
;r1 is the new alloc_ptr and r3 has object address
;update the alloc_ptr in Thread
str r1, [r12, #Thread__m_alloc_context__alloc_ptr]
;write methodTable in object
str r0, [r3]
;return object in r0
mov r0, r3
#ifdef _DEBUG
; Tail call to a helper that will set the current AppDomain index into the object header and then
; return the object pointer back to our original caller.
b SetAppDomainInObject
#else
;return
bx lr
#endif
AllocFailed
b $JIT_New
LEAF_END
;---------------------------------------------------------------------------
; HCIMPL2(Object*, JIT_Box, CORINFO_CLASS_HANDLE type, void* unboxedData)
; IN: r0: MethodTable*
; IN: r1: data pointer
;; OUT: r0: new object
LEAF_ENTRY JIT_BoxFastMP_InlineGetThread
ldr r2, [r0, #MethodTable__m_pWriteableData]
;Check whether the class has been initialized
ldr r2, [r2, #MethodTableWriteableData__m_dwFlags]
cmp r2, #MethodTableWriteableData__enum_flag_Unrestored
bne ClassNotInited
; Check whether the object contains pointers
ldr r3, [r0, #MethodTable__m_dwFlags]
cmp r3, #MethodTable__enum_flag_ContainsPointers
bne ContainsPointers
ldr r2, [r0, #MethodTable__m_BaseSize]
;m_BaseSize is guranteed to be a multiple of 4
;GetThread
PATCHABLE_INLINE_GETTHREAD r12, JIT_BoxFastMP_InlineGetThread__PatchTLSOffset
ldr r3, [r12, #Thread__m_alloc_context__alloc_ptr]
add r3, r2
ldr r2, [r12, #Thread__m_alloc_context__alloc_limit]
cmp r3, r2
bhi AllocFailed2
ldr r2, [r12, #Thread__m_alloc_context__alloc_ptr]
;advance alloc_ptr in Thread
str r3, [r12, #Thread__m_alloc_context__alloc_ptr]
;write methodtable* in the object
str r0, [r2]
;copy the contents of value type in the object
ldr r3, [r0, #MethodTable__m_BaseSize]
sub r3, #0xc
;r3 = no of bytes to copy
;move address of object to return register
mov r0, r2
;advance r2 to skip methodtable location
add r2, #4
CopyLoop
ldr r12, [r1, r3]
str r12, [r2, r3]
sub r3, #4
bne CopyLoop
#ifdef _DEBUG
; Tail call to a helper that will set the current AppDomain index into the object header and then
; return the object pointer back to our original caller.
b SetAppDomainInObject
#else
;return
bx lr
#endif
ContainsPointers
ClassNotInited
AllocFailed2
b $JIT_Box
LEAF_END
;---------------------------------------------------------------------------
; IN: r0: number of characters to allocate
;; OUT: r0: address of newly allocated string
LEAF_ENTRY AllocateStringFastMP_InlineGetThread
; Instead of doing elaborate overflow checks, we just limit the number of elements to
; MAX_FAST_ALLOCATE_STRING_SIZE. This is picked (in asmconstants.h) to avoid any possibility of
; overflow and to ensure we never try to allocate anything here that really should go on the large
; object heap instead. Additionally the size has been selected so that it will encode into an
; immediate in a single cmp instruction.
cmp r0, #MAX_FAST_ALLOCATE_STRING_SIZE
bhs OversizedString
; Calculate total string size: Align(base size + (characters * 2), 4).
mov r1, #(SIZEOF__BaseStringObject + 3) ; r1 == string base size + 3 for alignment round up
add r1, r1, r0, lsl #1 ; r1 += characters * 2
bic r1, r1, #3 ; r1 &= ~3; round size to multiple of 4
;GetThread
PATCHABLE_INLINE_GETTHREAD r12, AllocateStringFastMP_InlineGetThread__PatchTLSOffset
ldr r2, [r12, #Thread__m_alloc_context__alloc_limit]
ldr r3, [r12, #Thread__m_alloc_context__alloc_ptr]
add r1, r3
cmp r1, r2
bhi AllocFailed3
;can allocate
;advance alloc_ptr
str r1, [r12, #Thread__m_alloc_context__alloc_ptr]
; Write MethodTable pointer into new object.
ldr r1, =$g_pStringClass
ldr r1, [r1]
str r1, [r3]
; Write string length into new object.
str r0, [r3, #StringObject__m_StringLength]
;prepare to return new object address
mov r0, r3
#ifdef _DEBUG
; Tail call to a helper that will set the current AppDomain index into the object header and then
; return the object pointer back to our original caller.
b SetAppDomainInObject
#else
;return
bx lr
#endif
OversizedString
AllocFailed3
b $FramedAllocateString
LEAF_END
; HCIMPL2(Object*, JIT_NewArr1, CORINFO_CLASS_HANDLE arrayTypeHnd_, INT_PTR size)
;---------------------------------------------------------------------------
; IN: r0: type descriptor which contains the (shared) array method table and the element type.
; IN: r1: number of array elements
;; OUT: r0: address of newly allocated string
LEAF_ENTRY JIT_NewArr1VC_MP_InlineGetThread
; Do a conservative check here for number of elements.
; This is to avoid overflow while doing the calculations. We don't
; have to worry about "large" objects, since the allocation quantum is never big enough for
; LARGE_OBJECT_SIZE.
; For Value Classes, this needs to be < (max_value_in_4byte - size_of_base_array)/(max_size_of_each_element)
; This evaluates to (2^32-1 - 0xc)/2^16
; Additionally the constant has been chosen such that it can be encoded in a
; single Thumb2 CMP instruction.
cmp r1, #MAX_FAST_ALLOCATE_ARRAY_VC_SIZE
bhs OverSizedArray3
;load MethodTable from ArrayTypeDesc
ldr r3, [r0, #ArrayTypeDesc__m_TemplateMT - 2]
FIX_INDIRECTION r3, label1
;get element size - stored in low 16bits of m_dwFlags
ldrh r12, [r3, #MethodTable__m_dwFlags]
; getting size of object to allocate
; multiply number of elements with size of each element
mul r2, r12, r1
; add the base array size and 3 to align total bytes at 4 byte boundary
add r2, r2, #SIZEOF__ArrayOfValueType + 3
bic r2, #3
;GetThread
PATCHABLE_INLINE_GETTHREAD r12, JIT_NewArr1VC_MP_InlineGetThread__PatchTLSOffset
ldr r3, [r12, #Thread__m_alloc_context__alloc_ptr]
add r3, r2
ldr r2, [r12, #Thread__m_alloc_context__alloc_limit]
cmp r3, r2
bhi AllocFailed6
; can allocate
;r2 = address of new object
ldr r2, [r12, #Thread__m_alloc_context__alloc_ptr]
;update pointer in allocation context
str r3, [r12, #Thread__m_alloc_context__alloc_ptr]
;store number of elements
str r1, [r2, #ArrayBase__m_NumComponents]
;store methodtable
ldr r3, [r0, #ArrayTypeDesc__m_TemplateMT - 2]
FIX_INDIRECTION r3, label2
str r3, [r2]
;copy return value
mov r0, r2
#ifdef _DEBUG
; Tail call to a helper that will set the current AppDomain index into the object header and then
; return the object pointer back to our original caller.
b SetAppDomainInObject
#else
;return
bx lr
#endif
AllocFailed6
OverSizedArray3
b $JIT_NewArr1
LEAF_END
; HCIMPL2(Object*, JIT_NewArr1, CORINFO_CLASS_HANDLE arrayTypeHnd_, INT_PTR size)
;---------------------------------------------------------------------------
; IN: r0: type descriptor which contains the (shared) array method table and the element type.
; IN: r1: number of array elements
;; OUT: r0: address of newly allocated string
LEAF_ENTRY JIT_NewArr1OBJ_MP_InlineGetThread
cmp r1, #MAX_FAST_ALLOCATE_ARRAY_OBJECTREF_SIZE
bhs OverSizedArray
mov r2, #SIZEOF__ArrayOfObjectRef
add r2, r2, r1, lsl #2
;r2 will be a multiple of 4
;GetThread
PATCHABLE_INLINE_GETTHREAD r12, JIT_NewArr1OBJ_MP_InlineGetThread__PatchTLSOffset
ldr r3, [r12, #Thread__m_alloc_context__alloc_ptr]
add r3, r2
ldr r2, [r12, #Thread__m_alloc_context__alloc_limit]
cmp r3, r2
bhi AllocFailed4
;can allocate
;r2 = address of new object
ldr r2, [r12, #Thread__m_alloc_context__alloc_ptr]
;update pointer in allocation context
str r3, [r12, #Thread__m_alloc_context__alloc_ptr]
;store number of elements
str r1, [r2, #ArrayBase__m_NumComponents]
;store methodtable
ldr r3, [r0, #ArrayTypeDesc__m_TemplateMT - 2]
FIX_INDIRECTION r3, label3
str r3, [r2]
;copy return value
mov r0, r2
#ifdef _DEBUG
; Tail call to a helper that will set the current AppDomain index into the object header and then
; return the object pointer back to our original caller.
b SetAppDomainInObject
#else
;return
bx lr
#endif
OverSizedArray
AllocFailed4
b $JIT_NewArr1
LEAF_END
;
; JIT Static access helpers when TLS Index for AppDomain is low enough for fast helpers
;
; ------------------------------------------------------------------
; void* JIT_GetSharedNonGCStaticBase(SIZE_T moduleDomainID, DWORD dwClassDomainID)
LEAF_ENTRY JIT_GetSharedNonGCStaticBase_InlineGetAppDomain
; Check if r0 (moduleDomainID) is not a moduleID
tst r0, #1
beq HaveLocalModule1
PATCHABLE_INLINE_GETAPPDOMAIN r2, JIT_GetSharedNonGCStaticBase__PatchTLSLabel
; Get the LocalModule, r0 will always be odd, so: r0 * 2 - 2 <=> (r0 >> 1) * 4
ldr r2, [r2 , #AppDomain__m_sDomainLocalBlock + DomainLocalBlock__m_pModuleSlots]
add r2, r2, r0, LSL #1
ldr r0, [r2, #-2]
HaveLocalModule1
; If class is not initialized, bail to C++ helper
add r2, r0, #DomainLocalModule__m_pDataBlob
ldrb r2, [r2, r1]
tst r2, #1
beq CallHelper1
bx lr
CallHelper1
; Tail call JIT_GetSharedNonGCStaticBase_Helper
b JIT_GetSharedNonGCStaticBase_Helper
LEAF_END
; ------------------------------------------------------------------
; void* JIT_GetSharedNonGCStaticBaseNoCtor(SIZE_T moduleDomainID, DWORD dwClassDomainID)
LEAF_ENTRY JIT_GetSharedNonGCStaticBaseNoCtor_InlineGetAppDomain
; Check if r0 (moduleDomainID) is not a moduleID
tst r0, #1
beq HaveLocalModule2
PATCHABLE_INLINE_GETAPPDOMAIN r2, JIT_GetSharedNonGCStaticBaseNoCtor__PatchTLSLabel
; Get the LocalModule, r0 will always be odd, so: r0 * 2 - 2 <=> (r0 >> 1) * 4
ldr r2, [r2 , #AppDomain__m_sDomainLocalBlock + DomainLocalBlock__m_pModuleSlots]
add r2, r2, r0, LSL #1
ldr r0, [r2, #-2]
HaveLocalModule2
bx lr
LEAF_END
; ------------------------------------------------------------------
; void* JIT_GetSharedGCStaticBase(SIZE_T moduleDomainID, DWORD dwClassDomainID)
LEAF_ENTRY JIT_GetSharedGCStaticBase_InlineGetAppDomain
; Check if r0 (moduleDomainID) is not a moduleID
tst r0, #1
beq HaveLocalModule3
PATCHABLE_INLINE_GETAPPDOMAIN r2, JIT_GetSharedGCStaticBase__PatchTLSLabel
; Get the LocalModule, r0 will always be odd, so: r0 * 2 - 2 <=> (r0 >> 1) * 4
ldr r2, [r2 , #AppDomain__m_sDomainLocalBlock + DomainLocalBlock__m_pModuleSlots]
add r2, r2, r0, LSL #1
ldr r0, [r2, #-2]
HaveLocalModule3
; If class is not initialized, bail to C++ helper
add r2, r0, #DomainLocalModule__m_pDataBlob
ldrb r2, [r2, r1]
tst r2, #1
beq CallHelper3
ldr r0, [r0, #DomainLocalModule__m_pGCStatics]
bx lr
CallHelper3
; Tail call Jit_GetSharedGCStaticBase_Helper
b JIT_GetSharedGCStaticBase_Helper
LEAF_END
; ------------------------------------------------------------------
; void* JIT_GetSharedGCStaticBaseNoCtor(SIZE_T moduleDomainID, DWORD dwClassDomainID)
LEAF_ENTRY JIT_GetSharedGCStaticBaseNoCtor_InlineGetAppDomain
; Check if r0 (moduleDomainID) is not a moduleID
tst r0, #1
beq HaveLocalModule4
PATCHABLE_INLINE_GETAPPDOMAIN r2, JIT_GetSharedGCStaticBaseNoCtor__PatchTLSLabel
; Get the LocalModule, r0 will always be odd, so: r0 * 2 - 2 <=> (r0 >> 1) * 4
ldr r2, [r2 , #AppDomain__m_sDomainLocalBlock + DomainLocalBlock__m_pModuleSlots]
add r2, r2, r0, LSL #1
ldr r0, [r2, #-2]
HaveLocalModule4
ldr r0, [r0, #DomainLocalModule__m_pGCStatics]
bx lr
LEAF_END
; ------------------------------------------------------------------
; End of the writeable code region
LEAF_ENTRY JIT_PatchedCodeLast
bx lr
LEAF_END
; Must be at very end of file
END
| qiudesong/coreclr | src/vm/arm/patchedcode.asm | Assembly | mit | 17,393 |
Image_type equ 0
Image_image equ 4
Image_x equ 8
Image_y equ 12
Image_w equ 16
Image_h equ 20
Image_source equ Component_CLASS_SIZE
Image_sw equ Component_CLASS_SIZE+4
Image_sh equ Component_CLASS_SIZE+8
Image.Create : ; Image source, int sw, int sh, int x, int y, int w, int h
methodTraceEnter
pop dword [Image.Create.retval]
pop dword [Image.Create.h]
pop dword [Image.Create.w]
pop dword [Image.Create.y]
pop dword [Image.Create.x]
pop dword [Image.Create.sh]
pop dword [Image.Create.sw]
pop dword [Image.Create.source]
push edx
push eax
push ebx
mov ebx, Component_CLASS_SIZE+12
call ProgramManager.reserveMemory
call Component.initToDefaults
mov eax, [Image.Create.source]
mov [ebx+Image_source], eax
mov eax, [Image.Create.sw]
mov [ebx+Image_sw], eax
mov eax, [Image.Create.sh]
mov [ebx+Image_sh], eax
mov eax, [Image.Create.x]
mov [ebx+Image_x], eax
mov eax, [Image.Create.y]
mov [ebx+Image_y], eax
mov eax, [Image.Create.w]
mov [ebx+Image_w], eax
mov eax, [Image.Create.h]
mov [ebx+Image_h], eax
mov eax, Component.TYPE_IMAGE
mov [ebx+Image_type], eax
mov dword [ebx+Component_renderFunc], Image.Render
pusha
mov edx, ebx
mov eax, [ebx+Image_w]
imul eax, [ebx+Image_h]
mov ebx, eax
call ProgramManager.reserveMemory
mov [edx+Image_image], ebx
popa
mov ecx, ebx
pop ebx
pop eax
pop edx
push dword [Image.Create.retval]
methodTraceLeave
ret
Image.Create.retval :
dd 0x0
Image.Create.x :
dd 0x0
Image.Create.y :
dd 0x0
Image.Create.w :
dd 0x0
Image.Create.h :
dd 0x0
Image.Create.sw :
dd 0x0
Image.Create.sh :
dd 0x0
Image.Create.source :
dd 0x0
Image.Render : ; Image in ebx
methodTraceEnter
pusha
mov eax, [ebx+Image_w] ; take min(Image_w, Image_sw)
cmp eax, [ebx+Image_sw]
jle Image.Render.nos0
mov eax, [ebx+Image_sw]
Image.Render.nos0 :
mov dword [Image.copyRegion.w], eax
mov eax, [ebx+Image_w]
mov dword [Image.copyRegion.nw], eax
mov eax, [ebx+Image_sw]
mov dword [Image.copyRegion.ow], eax
mov eax, [ebx+Image_h] ; take min(Image_h, Image_sh)
cmp eax, [ebx+Image_sh]
jle Image.Render.nos1
mov eax, [ebx+Image_sh]
Image.Render.nos1 :
mov dword [Image.copyRegion.h], eax
mov eax, [ebx+Image_source]
mov [Image.copyRegion.obuf], eax
mov eax, [ebx+Image_image]
mov [Image.copyRegion.nbuf], eax
call Image.copyRegion
popa
methodTraceLeave
ret
Imagescalable_type equ 0
Imagescalable_image equ 4
Imagescalable_x equ 8
Imagescalable_y equ 12
Imagescalable_w equ 16
Imagescalable_h equ 20
Imagescalable_source equ Component_CLASS_SIZE
Imagescalable_sw equ Component_CLASS_SIZE+4
Imagescalable_sh equ Component_CLASS_SIZE+8
ImageScalable.Create : ; Image source, int sw, int sh, int x, int y, int w, int h
methodTraceEnter
pop dword [ImageScalable.Create.retval]
pop dword [ImageScalable.Create.h]
pop dword [ImageScalable.Create.w]
pop dword [ImageScalable.Create.y]
pop dword [ImageScalable.Create.x]
pop dword [ImageScalable.Create.sh]
pop dword [ImageScalable.Create.sw]
pop dword [ImageScalable.Create.source]
push eax
push ebx
mov ebx, Component_CLASS_SIZE+12
call ProgramManager.reserveMemory
call Component.initToDefaults
mov eax, [ImageScalable.Create.source]
mov [ebx+Imagescalable_source], eax
mov eax, [ImageScalable.Create.sw]
mov [ebx+Imagescalable_sw], eax
mov eax, [ImageScalable.Create.sh]
mov [ebx+Imagescalable_sh], eax
mov eax, [ImageScalable.Create.x]
mov [ebx+Imagescalable_x], eax
mov eax, [ImageScalable.Create.y]
mov [ebx+Imagescalable_y], eax
mov eax, [ImageScalable.Create.w]
mov [ebx+Imagescalable_w], eax
mov eax, [ImageScalable.Create.h]
mov [ebx+Imagescalable_h], eax
mov eax, Component.TYPE_IMAGE_SCALABLE
mov [ebx+Imagescalable_type], eax
mov dword [ebx+Component_renderFunc], ImageScalable.Render
pusha
mov edx, ebx
mov eax, [ebx+Image_w]
imul eax, [ebx+Image_h]
mov ebx, eax
call ProgramManager.reserveMemory
mov [edx+Image_image], ebx
popa
mov ecx, ebx
pop ebx
pop eax
push dword [ImageScalable.Create.retval]
methodTraceLeave
ret
ImageScalable.Create.retval :
dd 0x0
ImageScalable.Create.x :
dd 0x0
ImageScalable.Create.y :
dd 0x0
ImageScalable.Create.w :
dd 0x0
ImageScalable.Create.h :
dd 0x0
ImageScalable.Create.sw :
dd 0x0
ImageScalable.Create.sh :
dd 0x0
ImageScalable.Create.source :
dd 0x0
ImageScalable.Render : ; ImageScalable in ebx
methodTraceEnter
pusha
; Figure out how to nicely scale images!
popa
methodTraceLeave
ret
; Image, ImageScalable [s:w,h], ImageScrollable[mscrolls]
| jaredwhitney/os3 | Graphics/Image.asm | Assembly | mit | 4,608 |
;*!
;* \copy
;* Copyright (c) 2009-2013, Cisco Systems
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions
;* are met:
;*
;* * Redistributions of source code must retain the above copyright
;* notice, this list of conditions and the following disclaimer.
;*
;* * Redistributions in binary form must reproduce the above copyright
;* notice, this list of conditions and the following disclaimer in
;* the documentation and/or other materials provided with the
;* distribution.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
;* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;*
;* intra_pred.asm
;*
;* Abstract
;* sse2 function for intra predict operations
;*
;* History
;* 18/09/2009 Created
;*
;*
;*************************************************************************/
%include "asm_inc.asm"
;***********************************************************************
; Local Data (Read Only)
;***********************************************************************
SECTION .rodata align=16
align 16
sse2_plane_inc_minus dw -7, -6, -5, -4, -3, -2, -1, 0
align 16
sse2_plane_inc dw 1, 2, 3, 4, 5, 6, 7, 8
align 16
sse2_plane_dec dw 8, 7, 6, 5, 4, 3, 2, 1
; for chroma plane mode
sse2_plane_inc_c dw 1, 2, 3, 4
sse2_plane_dec_c dw 4, 3, 2, 1
align 16
sse2_plane_mul_b_c dw -3, -2, -1, 0, 1, 2, 3, 4
align 16
mmx_01bytes: times 16 db 1
align 16
mmx_0x02: dw 0x02, 0x00, 0x00, 0x00
;***********************************************************************
; macros
;***********************************************************************
;dB 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1
;%1 will keep the last result
%macro SSE_DB_1_2REG 2
pxor %1, %1
pcmpeqw %2, %2
psubb %1, %2
%endmacro
;xmm0, xmm1, xmm2, eax, ecx
;lower 64 bits of xmm0 save the result
%macro SSE2_PRED_H_4X4_TWO_LINE 5
movd %1, [%4-1]
movdqa %3, %1
punpcklbw %1, %3
movdqa %3, %1
punpcklbw %1, %3
;add %4, %5
movd %2, [%4+%5-1]
movdqa %3, %2
punpcklbw %2, %3
movdqa %3, %2
punpcklbw %2, %3
punpckldq %1, %2
%endmacro
%macro SUMW_HORIZON1 2
movdqa %2, %1
psrldq %2, 8
paddusw %1, %2
movdqa %2, %1
psrldq %2, 4
paddusw %1, %2
movdqa %2, %1
psrldq %2, 2
paddusw %1, %2
%endmacro
%macro LOAD_COLUMN 6
movd %1, [%5]
movd %2, [%5+%6]
punpcklbw %1, %2
lea %5, [%5+2*%6]
movd %3, [%5]
movd %2, [%5+%6]
punpcklbw %3, %2
punpcklwd %1, %3
lea %5, [%5+2*%6]
movd %4, [%5]
movd %2, [%5+%6]
punpcklbw %4, %2
lea %5, [%5+2*%6]
movd %3, [%5]
movd %2, [%5+%6]
lea %5, [%5+2*%6]
punpcklbw %3, %2
punpcklwd %4, %3
punpckhdq %1, %4
%endmacro
%macro SUMW_HORIZON 3
movhlps %2, %1 ; x2 = xx xx xx xx d7 d6 d5 d4
paddw %1, %2 ; x1 = xx xx xx xx d37 d26 d15 d04
punpcklwd %1, %3 ; x1 = d37 d26 d15 d04
movhlps %2, %1 ; x2 = xxxx xxxx d37 d26
paddd %1, %2 ; x1 = xxxx xxxx d1357 d0246
pshuflw %2, %1, 0x4e ; x2 = xxxx xxxx d0246 d1357
paddd %1, %2 ; x1 = xxxx xxxx xxxx d01234567
%endmacro
%macro COPY_16_TIMES 2
movdqa %2, [%1-16]
psrldq %2, 15
pmuludq %2, [mmx_01bytes]
pshufd %2, %2, 0
%endmacro
%macro COPY_16_TIMESS 3
movdqa %2, [%1+%3-16]
psrldq %2, 15
pmuludq %2, [mmx_01bytes]
pshufd %2, %2, 0
%endmacro
%macro LOAD_COLUMN_C 6
movd %1, [%5]
movd %2, [%5+%6]
punpcklbw %1,%2
lea %5, [%5+2*%6]
movd %3, [%5]
movd %2, [%5+%6]
punpcklbw %3, %2
punpckhwd %1, %3
lea %5, [%5+2*%6]
%endmacro
%macro LOAD_2_LEFT_AND_ADD 0
lea r1, [r1+2*r2]
movzx r4, byte [r1-0x01]
add r3, r4
movzx r4, byte [r1+r2-0x01]
add r3, r4
%endmacro
;***********************************************************************
; Code
;***********************************************************************
SECTION .text
;***********************************************************************
; void WelsI4x4LumaPredH_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride)
;
; pred must align to 16
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredH_sse2
push r3
%assign push_num 1
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
movzx r3, byte [r1-1]
movd xmm0, r3d
pmuludq xmm0, [mmx_01bytes]
movzx r3, byte [r1+r2-1]
movd xmm1, r3d
pmuludq xmm1, [mmx_01bytes]
unpcklps xmm0, xmm1
lea r1, [r1+r2*2]
movzx r3, byte [r1-1]
movd xmm2, r3d
pmuludq xmm2, [mmx_01bytes]
movzx r3, byte [r1+r2-1]
movd xmm3, r3d
pmuludq xmm3, [mmx_01bytes]
unpcklps xmm2, xmm3
unpcklpd xmm0, xmm2
movdqa [r0], xmm0
pop r3
ret
;***********************************************************************
; void WelsI16x16LumaPredPlane_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride);
;***********************************************************************
WELS_EXTERN WelsI16x16LumaPredPlane_sse2
push r3
push r4
%assign push_num 2
LOAD_3_PARA
PUSH_XMM 8
SIGN_EXTENSION r2, r2d
sub r1, 1
sub r1, r2
;for H
pxor xmm7, xmm7
movq xmm0, [r1]
movdqa xmm5, [sse2_plane_dec]
punpcklbw xmm0, xmm7
pmullw xmm0, xmm5
movq xmm1, [r1 + 9]
movdqa xmm6, [sse2_plane_inc]
punpcklbw xmm1, xmm7
pmullw xmm1, xmm6
psubw xmm1, xmm0
SUMW_HORIZON xmm1,xmm0,xmm2
movd r3d, xmm1 ; H += (i + 1) * (top[8 + i] - top[6 - i]);
movsx r3, r3w
imul r3, 5
add r3, 32
sar r3, 6 ; b = (5 * H + 32) >> 6;
SSE2_Copy8Times xmm1, r3d ; xmm1 = b,b,b,b,b,b,b,b
movzx r4, BYTE [r1+16]
sub r1, 3
LOAD_COLUMN xmm0, xmm2, xmm3, xmm4, r1, r2
add r1, 3
movzx r3, BYTE [r1+8*r2]
add r4, r3
shl r4, 4 ; a = (left[15*stride] + top[15]) << 4;
sub r1, 3
add r1, r2
LOAD_COLUMN xmm7, xmm2, xmm3, xmm4, r1, r2
pxor xmm4, xmm4
punpckhbw xmm0, xmm4
pmullw xmm0, xmm5
punpckhbw xmm7, xmm4
pmullw xmm7, xmm6
psubw xmm7, xmm0
SUMW_HORIZON xmm7,xmm0,xmm2
movd r3d, xmm7 ; V
movsx r3, r3w
imul r3, 5
add r3, 32
sar r3, 6 ; c = (5 * V + 32) >> 6;
SSE2_Copy8Times xmm4, r3d ; xmm4 = c,c,c,c,c,c,c,c
add r4, 16
imul r3, -7
add r3, r4 ; s = a + 16 + (-7)*c
SSE2_Copy8Times xmm0, r3d ; xmm0 = s,s,s,s,s,s,s,s
xor r3, r3
movdqa xmm5, [sse2_plane_inc_minus]
get_i16x16_luma_pred_plane_sse2_1:
movdqa xmm2, xmm1
pmullw xmm2, xmm5
paddw xmm2, xmm0
psraw xmm2, 5
movdqa xmm3, xmm1
pmullw xmm3, xmm6
paddw xmm3, xmm0
psraw xmm3, 5
packuswb xmm2, xmm3
movdqa [r0], xmm2
paddw xmm0, xmm4
add r0, 16
inc r3
cmp r3, 16
jnz get_i16x16_luma_pred_plane_sse2_1
POP_XMM
pop r4
pop r3
ret
;***********************************************************************
; void WelsI16x16LumaPredH_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride);
;***********************************************************************
%macro SSE2_PRED_H_16X16_ONE_LINE 0
add r0, 16
add r1, r2
movzx r3, byte [r1]
SSE2_Copy16Times xmm0, r3d
movdqa [r0], xmm0
%endmacro
WELS_EXTERN WelsI16x16LumaPredH_sse2
push r3
%assign push_num 1
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
dec r1
movzx r3, byte [r1]
SSE2_Copy16Times xmm0, r3d
movdqa [r0], xmm0
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
SSE2_PRED_H_16X16_ONE_LINE
pop r3
ret
;***********************************************************************
; void WelsI16x16LumaPredV_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride);
;***********************************************************************
WELS_EXTERN WelsI16x16LumaPredV_sse2
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movdqa xmm0, [r1]
movdqa [r0], xmm0
movdqa [r0+10h], xmm0
movdqa [r0+20h], xmm0
movdqa [r0+30h], xmm0
movdqa [r0+40h], xmm0
movdqa [r0+50h], xmm0
movdqa [r0+60h], xmm0
movdqa [r0+70h], xmm0
movdqa [r0+80h], xmm0
movdqa [r0+90h], xmm0
movdqa [r0+160], xmm0
movdqa [r0+176], xmm0
movdqa [r0+192], xmm0
movdqa [r0+208], xmm0
movdqa [r0+224], xmm0
movdqa [r0+240], xmm0
ret
;***********************************************************************
; void WelsIChromaPredPlane_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride);
;***********************************************************************
WELS_EXTERN WelsIChromaPredPlane_sse2
push r3
push r4
%assign push_num 2
LOAD_3_PARA
PUSH_XMM 8
SIGN_EXTENSION r2, r2d
sub r1, 1
sub r1, r2
pxor mm7, mm7
movq mm0, [r1]
movq mm5, [sse2_plane_dec_c]
punpcklbw mm0, mm7
pmullw mm0, mm5
movq mm1, [r1 + 5]
movq mm6, [sse2_plane_inc_c]
punpcklbw mm1, mm7
pmullw mm1, mm6
psubw mm1, mm0
movq2dq xmm1, mm1
pxor xmm2, xmm2
SUMW_HORIZON xmm1,xmm0,xmm2
movd r3d, xmm1
movsx r3, r3w
imul r3, 17
add r3, 16
sar r3, 5 ; b = (17 * H + 16) >> 5;
SSE2_Copy8Times xmm1, r3d ; mm1 = b,b,b,b,b,b,b,b
movzx r3, BYTE [r1+8]
sub r1, 3
LOAD_COLUMN_C mm0, mm2, mm3, mm4, r1, r2
add r1, 3
movzx r4, BYTE [r1+4*r2]
add r4, r3
shl r4, 4 ; a = (left[7*stride] + top[7]) << 4;
sub r1, 3
add r1, r2
LOAD_COLUMN_C mm7, mm2, mm3, mm4, r1, r2
pxor mm4, mm4
punpckhbw mm0, mm4
pmullw mm0, mm5
punpckhbw mm7, mm4
pmullw mm7, mm6
psubw mm7, mm0
movq2dq xmm7, mm7
pxor xmm2, xmm2
SUMW_HORIZON xmm7,xmm0,xmm2
movd r3d, xmm7 ; V
movsx r3, r3w
imul r3, 17
add r3, 16
sar r3, 5 ; c = (17 * V + 16) >> 5;
SSE2_Copy8Times xmm4, r3d ; mm4 = c,c,c,c,c,c,c,c
add r4, 16
imul r3, -3
add r3, r4 ; s = a + 16 + (-3)*c
SSE2_Copy8Times xmm0, r3d ; xmm0 = s,s,s,s,s,s,s,s
xor r3, r3
movdqa xmm5, [sse2_plane_mul_b_c]
get_i_chroma_pred_plane_sse2_1:
movdqa xmm2, xmm1
pmullw xmm2, xmm5
paddw xmm2, xmm0
psraw xmm2, 5
packuswb xmm2, xmm2
movq [r0], xmm2
paddw xmm0, xmm4
add r0, 8
inc r3
cmp r3, 8
jnz get_i_chroma_pred_plane_sse2_1
POP_XMM
pop r4
pop r3
WELSEMMS
ret
;***********************************************************************
; 0 |1 |2 |3 |4 |
; 6 |7 |8 |9 |10|
; 11|12|13|14|15|
; 16|17|18|19|20|
; 21|22|23|24|25|
; 7 is the start pixel of current 4x4 block
; pred[7] = ([6]+[0]*2+[1]+2)/4
;
; void WelsI4x4LumaPredDDR_mmx(uint8_t *pred,uint8_t *pRef,int32_t stride)
;
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredDDR_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
movq mm1,[r1+r2-8] ;get value of 11,decreasing 8 is trying to improve the performance of movq mm1[8] = 11
movq mm2,[r1-8] ;get value of 6 mm2[8] = 6
sub r1, r2 ;mov eax to above line of current block(postion of 1)
punpckhbw mm2,[r1-8] ;mm2[8](high 8th byte of mm2) = [0](value of 0), mm2[7]= [6]
movd mm3,[r1] ;get value 1, mm3[1] = [1],mm3[2]=[2],mm3[3]=[3]
punpckhwd mm1,mm2 ;mm1[8]=[0],mm1[7]=[6],mm1[6]=[11]
psllq mm3,18h ;mm3[5]=[1]
psrlq mm1,28h ;mm1[3]=[0],mm1[2]=[6],mm1[1]=[11]
por mm3,mm1 ;mm3[6]=[3],mm3[5]=[2],mm3[4]=[1],mm3[3]=[0],mm3[2]=[6],mm3[1]=[11]
movq mm1,mm3 ;mm1[6]=[3],mm1[5]=[2],mm1[4]=[1],mm1[3]=[0],mm1[2]=[6],mm1[1]=[11]
lea r1,[r1+r2*2-8h] ;set eax point to 12
movq mm4,[r1+r2] ;get value of 16, mm4[8]=[16]
psllq mm3,8 ;mm3[7]=[3],mm3[6]=[2],mm3[5]=[1],mm3[4]=[0],mm3[3]=[6],mm3[2]=[11],mm3[1]=0
psrlq mm4,38h ;mm4[1]=[16]
por mm3,mm4 ;mm3[7]=[3],mm3[6]=[2],mm3[5]=[1],mm3[4]=[0],mm3[3]=[6],mm3[2]=[11],mm3[1]=[16]
movq mm2,mm3 ;mm2[7]=[3],mm2[6]=[2],mm2[5]=[1],mm2[4]=[0],mm2[3]=[6],mm2[2]=[11],mm2[1]=[16]
movq mm4,[r1+r2*2] ;mm4[8]=[21]
psllq mm3,8 ;mm3[8]=[3],mm3[7]=[2],mm3[6]=[1],mm3[5]=[0],mm3[4]=[6],mm3[3]=[11],mm3[2]=[16],mm3[1]=0
psrlq mm4,38h ;mm4[1]=[21]
por mm3,mm4 ;mm3[8]=[3],mm3[7]=[2],mm3[6]=[1],mm3[5]=[0],mm3[4]=[6],mm3[3]=[11],mm3[2]=[16],mm3[1]=[21]
movq mm4,mm3 ;mm4[8]=[3],mm4[7]=[2],mm4[6]=[1],mm4[5]=[0],mm4[4]=[6],mm4[3]=[11],mm4[2]=[16],mm4[1]=[21]
pavgb mm3,mm1 ;mm3=([11]+[21]+1)/2
pxor mm1,mm4 ;find odd value in the lowest bit of each byte
pand mm1,[mmx_01bytes] ;set the odd bit
psubusb mm3,mm1 ;decrease 1 from odd bytes
pavgb mm2,mm3 ;mm2=(([11]+[21]+1)/2+1+[16])/2
movd [r0+12],mm2
psrlq mm2,8
movd [r0+8],mm2
psrlq mm2,8
movd [r0+4],mm2
psrlq mm2,8
movd [r0],mm2
WELSEMMS
ret
;***********************************************************************
; 0 |1 |2 |3 |4 |
; 5 |6 |7 |8 |9 |
; 10|11|12|13|14|
; 15|16|17|18|19|
; 20|21|22|23|24|
; 6 is the start pixel of current 4x4 block
; pred[6] = ([1]+[2]+[3]+[4]+[5]+[10]+[15]+[20]+4)/8
;
; void WelsI4x4LumaPredDc_sse2(uint8_t *pred,uint8_t *pRef,int32_t stride)
;
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredDc_sse2
push r3
push r4
%assign push_num 2
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
movzx r4, byte [r1-1h]
sub r1, r2
movd xmm0, [r1]
pxor xmm1, xmm1
psadbw xmm0, xmm1
xor r3, r3
movd r3d, xmm0
add r3, r4
movzx r4, byte [r1+r2*2-1h]
add r3, r4
lea r1, [r1+r2*2-1]
movzx r4, byte [r1+r2]
add r3, r4
movzx r4, byte [r1+r2*2]
add r3, r4
add r3, 4
sar r3, 3
imul r3, 0x01010101
movd xmm0, r3d
pshufd xmm0, xmm0, 0
movdqa [r0], xmm0
pop r4
pop r3
ret
;***********************************************************************
; void WelsIChromaPredH_mmx(uint8_t *pred, uint8_t *pRef, int32_t stride)
; copy 8 pixel of 8 line from left
;***********************************************************************
%macro MMX_PRED_H_8X8_ONE_LINE 4
movq %1, [%3-8]
psrlq %1, 38h
;pmuludq %1, [mmx_01bytes] ;extend to 4 bytes
pmullw %1, [mmx_01bytes]
pshufw %1, %1, 0
movq [%4], %1
%endmacro
%macro MMX_PRED_H_8X8_ONE_LINEE 4
movq %1, [%3+r2-8]
psrlq %1, 38h
;pmuludq %1, [mmx_01bytes] ;extend to 4 bytes
pmullw %1, [mmx_01bytes]
pshufw %1, %1, 0
movq [%4], %1
%endmacro
WELS_EXTERN WelsIChromaPredH_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
movq mm0, [r1-8]
psrlq mm0, 38h
;pmuludq mm0, [mmx_01bytes] ;extend to 4 bytes
pmullw mm0, [mmx_01bytes]
pshufw mm0, mm0, 0
movq [r0], mm0
MMX_PRED_H_8X8_ONE_LINEE mm0, mm1, r1,r0+8
lea r1,[r1+r2*2]
MMX_PRED_H_8X8_ONE_LINE mm0, mm1, r1,r0+16
MMX_PRED_H_8X8_ONE_LINEE mm0, mm1, r1,r0+24
lea r1,[r1+r2*2]
MMX_PRED_H_8X8_ONE_LINE mm0, mm1, r1,r0+32
MMX_PRED_H_8X8_ONE_LINEE mm0, mm1, r1,r0+40
lea r1,[r1+r2*2]
MMX_PRED_H_8X8_ONE_LINE mm0, mm1, r1,r0+48
MMX_PRED_H_8X8_ONE_LINEE mm0, mm1, r1,r0+56
WELSEMMS
ret
;***********************************************************************
; void WelsI4x4LumaPredV_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride)
; copy pixels from top 4 pixels
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredV_sse2
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movd xmm0, [r1]
pshufd xmm0, xmm0, 0
movdqa [r0], xmm0
ret
;***********************************************************************
; void WelsIChromaPredV_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride)
; copy 8 pixels from top 8 pixels
;***********************************************************************
WELS_EXTERN WelsIChromaPredV_sse2
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movq xmm0, [r1]
movdqa xmm1, xmm0
punpcklqdq xmm0, xmm1
movdqa [r0], xmm0
movdqa [r0+16], xmm0
movdqa [r0+32], xmm0
movdqa [r0+48], xmm0
ret
;***********************************************************************
; lt|t0|t1|t2|t3|
; l0|
; l1|
; l2|
; l3|
; t3 will never been used
; destination:
; |a |b |c |d |
; |e |f |a |b |
; |g |h |e |f |
; |i |j |g |h |
; a = (1 + lt + l0)>>1
; e = (1 + l0 + l1)>>1
; g = (1 + l1 + l2)>>1
; i = (1 + l2 + l3)>>1
; d = (2 + t0 + (t1<<1) + t2)>>2
; c = (2 + lt + (t0<<1) + t1)>>2
; b = (2 + l0 + (lt<<1) + t0)>>2
; f = (2 + l1 + (l0<<1) + lt)>>2
; h = (2 + l2 + (l1<<1) + l0)>>2
; j = (2 + l3 + (l2<<1) + l1)>>2
; [b a f e h g j i] + [d c b a] --> mov to memory
;
; void WelsI4x4LumaPredHD_mmx(uint8_t *pred,uint8_t *pRef,int32_t stride)
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredHD_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movd mm0, [r1-1] ; mm0 = [xx xx xx xx t2 t1 t0 lt]
psllq mm0, 20h ; mm0 = [t2 t1 t0 lt xx xx xx xx]
movd mm1, [r1+2*r2-4]
punpcklbw mm1, [r1+r2-4] ; mm1[7] = l0, mm1[6] = l1
lea r1, [r1+2*r2]
movd mm2, [r1+2*r2-4]
punpcklbw mm2, [r1+r2-4] ; mm2[7] = l2, mm2[6] = l3
punpckhwd mm2, mm1 ; mm2 = [l0 l1 l2 l3 xx xx xx xx]
psrlq mm2, 20h
pxor mm0, mm2 ; mm0 = [t2 t1 t0 lt l0 l1 l2 l3]
movq mm1, mm0
psrlq mm1, 10h ; mm1 = [xx xx t2 t1 t0 lt l0 l1]
movq mm2, mm0
psrlq mm2, 8h ; mm2 = [xx t2 t1 t0 lt l0 l1 l2]
movq mm3, mm2
movq mm4, mm1
pavgb mm1, mm0
pxor mm4, mm0 ; find odd value in the lowest bit of each byte
pand mm4, [mmx_01bytes] ; set the odd bit
psubusb mm1, mm4 ; decrease 1 from odd bytes
pavgb mm2, mm1 ; mm2 = [xx xx d c b f h j]
movq mm4, mm0
pavgb mm3, mm4 ; mm3 = [xx xx xx xx a e g i]
punpcklbw mm3, mm2 ; mm3 = [b a f e h g j i]
psrlq mm2, 20h
psllq mm2, 30h ; mm2 = [d c 0 0 0 0 0 0]
movq mm4, mm3
psrlq mm4, 10h ; mm4 = [0 0 b a f e h j]
pxor mm2, mm4 ; mm2 = [d c b a xx xx xx xx]
psrlq mm2, 20h ; mm2 = [xx xx xx xx d c b a]
movd [r0], mm2
movd [r0+12], mm3
psrlq mm3, 10h
movd [r0+8], mm3
psrlq mm3, 10h
movd [r0+4], mm3
WELSEMMS
ret
;***********************************************************************
; lt|t0|t1|t2|t3|
; l0|
; l1|
; l2|
; l3|
; t3 will never been used
; destination:
; |a |b |c |d |
; |c |d |e |f |
; |e |f |g |g |
; |g |g |g |g |
; a = (1 + l0 + l1)>>1
; c = (1 + l1 + l2)>>1
; e = (1 + l2 + l3)>>1
; g = l3
; b = (2 + l0 + (l1<<1) + l2)>>2
; d = (2 + l1 + (l2<<1) + l3)>>2
; f = (2 + l2 + (l3<<1) + l3)>>2
; [g g f e d c b a] + [g g g g] --> mov to memory
;
; void WelsI4x4LumaPredHU_mmx(uint8_t *pred,uint8_t *pRef,int32_t stride)
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredHU_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
movd mm0, [r1-4] ; mm0[3] = l0
punpcklbw mm0, [r1+r2-4] ; mm0[7] = l1, mm0[6] = l0
lea r1, [r1+2*r2]
movd mm2, [r1-4] ; mm2[3] = l2
movd mm4, [r1+r2-4] ; mm4[3] = l3
punpcklbw mm2, mm4
punpckhwd mm0, mm2 ; mm0 = [l3 l2 l1 l0 xx xx xx xx]
psrlq mm4, 18h
psllq mm4, 38h ; mm4 = [l3 xx xx xx xx xx xx xx]
psrlq mm0, 8h
pxor mm0, mm4 ; mm0 = [l3 l3 l2 l1 l0 xx xx xx]
movq mm1, mm0
psllq mm1, 8h ; mm1 = [l3 l2 l1 l0 xx xx xx xx]
movq mm3, mm1 ; mm3 = [l3 l2 l1 l0 xx xx xx xx]
pavgb mm1, mm0 ; mm1 = [g e c a xx xx xx xx]
movq mm2, mm0
psllq mm2, 10h ; mm2 = [l2 l1 l0 xx xx xx xx xx]
movq mm5, mm2
pavgb mm2, mm0
pxor mm5, mm0 ; find odd value in the lowest bit of each byte
pand mm5, [mmx_01bytes] ; set the odd bit
psubusb mm2, mm5 ; decrease 1 from odd bytes
pavgb mm2, mm3 ; mm2 = [f d b xx xx xx xx xx]
psrlq mm2, 8h
pxor mm2, mm4 ; mm2 = [g f d b xx xx xx xx]
punpckhbw mm1, mm2 ; mm1 = [g g f e d c b a]
punpckhbw mm4, mm4 ; mm4 = [g g xx xx xx xx xx xx]
punpckhbw mm4, mm4 ; mm4 = [g g g g xx xx xx xx]
psrlq mm4, 20h
movd [r0+12], mm4
movd [r0], mm1
psrlq mm1, 10h
movd [r0+4], mm1
psrlq mm1, 10h
movd [r0+8], mm1
WELSEMMS
ret
;***********************************************************************
; lt|t0|t1|t2|t3|
; l0|
; l1|
; l2|
; l3|
; l3 will never been used
; destination:
; |a |b |c |d |
; |e |f |g |h |
; |i |a |b |c |
; |j |e |f |g |
; a = (1 + lt + t0)>>1
; b = (1 + t0 + t1)>>1
; c = (1 + t1 + t2)>>1
; d = (1 + t2 + t3)>>1
; e = (2 + l0 + (lt<<1) + t0)>>2
; f = (2 + lt + (t0<<1) + t1)>>2
; g = (2 + t0 + (t1<<1) + t2)>>2
; h = (2 + t1 + (t2<<1) + t3)>>2
; i = (2 + lt + (l0<<1) + l1)>>2
; j = (2 + l0 + (l1<<1) + l2)>>2
;
; void WelsI4x4LumaPredVR_mmx(uint8_t *pred,uint8_t *pRef,int32_t stride)
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredVR_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movq mm0, [r1-1] ; mm0 = [xx xx xx t3 t2 t1 t0 lt]
psllq mm0, 18h ; mm0 = [t3 t2 t1 t0 lt xx xx xx]
movd mm1, [r1+2*r2-4]
punpcklbw mm1, [r1+r2-4] ; mm1[7] = l0, mm1[6] = l1
lea r1, [r1+2*r2]
movq mm2, [r1+r2-8] ; mm2[7] = l2
punpckhwd mm2, mm1 ; mm2 = [l0 l1 l2 xx xx xx xx xx]
psrlq mm2, 28h
pxor mm0, mm2 ; mm0 = [t3 t2 t1 t0 lt l0 l1 l2]
movq mm1, mm0
psllq mm1, 8h ; mm1 = [t2 t1 t0 lt l0 l1 l2 xx]
pavgb mm1, mm0 ; mm1 = [d c b a xx xx xx xx]
movq mm2, mm0
psllq mm2, 10h ; mm2 = [t1 t0 lt l0 l1 l2 xx xx]
movq mm3, mm2
pavgb mm2, mm0
pxor mm3, mm0 ; find odd value in the lowest bit of each byte
pand mm3, [mmx_01bytes] ; set the odd bit
psubusb mm2, mm3 ; decrease 1 from odd bytes
movq mm3, mm0
psllq mm3, 8h ; mm3 = [t2 t1 t0 lt l0 l1 l2 xx]
pavgb mm3, mm2 ; mm3 = [h g f e i j xx xx]
movq mm2, mm3
psrlq mm1, 20h ; mm1 = [xx xx xx xx d c b a]
movd [r0], mm1
psrlq mm2, 20h ; mm2 = [xx xx xx xx h g f e]
movd [r0+4], mm2
movq mm4, mm3
psllq mm4, 20h
psrlq mm4, 38h ; mm4 = [xx xx xx xx xx xx xx i]
movq mm5, mm3
psllq mm5, 28h
psrlq mm5, 38h ; mm5 = [xx xx xx xx xx xx xx j]
psllq mm1, 8h
pxor mm4, mm1 ; mm4 = [xx xx xx xx c b a i]
movd [r0+8], mm4
psllq mm2, 8h
pxor mm5, mm2 ; mm5 = [xx xx xx xx g f e j]
movd [r0+12], mm5
WELSEMMS
ret
;***********************************************************************
; lt|t0|t1|t2|t3|t4|t5|t6|t7
; l0|
; l1|
; l2|
; l3|
; lt,t0,t1,t2,t3 will never been used
; destination:
; |a |b |c |d |
; |b |c |d |e |
; |c |d |e |f |
; |d |e |f |g |
; a = (2 + t0 + t2 + (t1<<1))>>2
; b = (2 + t1 + t3 + (t2<<1))>>2
; c = (2 + t2 + t4 + (t3<<1))>>2
; d = (2 + t3 + t5 + (t4<<1))>>2
; e = (2 + t4 + t6 + (t5<<1))>>2
; f = (2 + t5 + t7 + (t6<<1))>>2
; g = (2 + t6 + t7 + (t7<<1))>>2
; [g f e d c b a] --> mov to memory
;
; void WelsI4x4LumaPredDDL_mmx(uint8_t *pred,uint8_t *pRef,int32_t stride)
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredDDL_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movq mm0, [r1] ; mm0 = [t7 t6 t5 t4 t3 t2 t1 t0]
movq mm1, mm0
movq mm2, mm0
movq mm3, mm0
psrlq mm3, 38h
psllq mm3, 38h ; mm3 = [t7 xx xx xx xx xx xx xx]
psllq mm1, 8h ; mm1 = [t6 t5 t4 t3 t2 t1 t0 xx]
psrlq mm2, 8h
pxor mm2, mm3 ; mm2 = [t7 t7 t6 t5 t4 t3 t2 t1]
movq mm3, mm1
pavgb mm1, mm2
pxor mm3, mm2 ; find odd value in the lowest bit of each byte
pand mm3, [mmx_01bytes] ; set the odd bit
psubusb mm1, mm3 ; decrease 1 from odd bytes
pavgb mm0, mm1 ; mm0 = [g f e d c b a xx]
psrlq mm0, 8h
movd [r0], mm0
psrlq mm0, 8h
movd [r0+4], mm0
psrlq mm0, 8h
movd [r0+8], mm0
psrlq mm0, 8h
movd [r0+12], mm0
WELSEMMS
ret
;***********************************************************************
; lt|t0|t1|t2|t3|t4|t5|t6|t7
; l0|
; l1|
; l2|
; l3|
; lt,t0,t1,t2,t3 will never been used
; destination:
; |a |b |c |d |
; |e |f |g |h |
; |b |c |d |i |
; |f |g |h |j |
; a = (1 + t0 + t1)>>1
; b = (1 + t1 + t2)>>1
; c = (1 + t2 + t3)>>1
; d = (1 + t3 + t4)>>1
; i = (1 + t4 + t5)>>1
; e = (2 + t0 + (t1<<1) + t2)>>2
; f = (2 + t1 + (t2<<1) + t3)>>2
; g = (2 + t2 + (t3<<1) + t4)>>2
; h = (2 + t3 + (t4<<1) + t5)>>2
; j = (2 + t4 + (t5<<1) + t6)>>2
; [i d c b a] + [j h g f e] --> mov to memory
;
; void WelsI4x4LumaPredVL_mmx(uint8_t *pred,uint8_t *pRef,int32_t stride)
;***********************************************************************
WELS_EXTERN WelsI4x4LumaPredVL_mmx
%assign push_num 0
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movq mm0, [r1] ; mm0 = [t7 t6 t5 t4 t3 t2 t1 t0]
movq mm1, mm0
movq mm2, mm0
psrlq mm1, 8h ; mm1 = [xx t7 t6 t5 t4 t3 t2 t1]
psrlq mm2, 10h ; mm2 = [xx xx t7 t6 t5 t4 t3 t2]
movq mm3, mm1
pavgb mm3, mm0 ; mm3 = [xx xx xx i d c b a]
movq mm4, mm2
pavgb mm2, mm0
pxor mm4, mm0 ; find odd value in the lowest bit of each byte
pand mm4, [mmx_01bytes] ; set the odd bit
psubusb mm2, mm4 ; decrease 1 from odd bytes
pavgb mm2, mm1 ; mm2 = [xx xx xx j h g f e]
movd [r0], mm3
psrlq mm3, 8h
movd [r0+8], mm3
movd [r0+4], mm2
psrlq mm2, 8h
movd [r0+12], mm2
WELSEMMS
ret
;***********************************************************************
;
; void WelsIChromaPredDc_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride)
;***********************************************************************
WELS_EXTERN WelsIChromaPredDc_sse2
push r3
push r4
%assign push_num 2
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movq mm0, [r1]
movzx r3, byte [r1+r2-0x01] ; l1
lea r1, [r1+2*r2]
movzx r4, byte [r1-0x01] ; l2
add r3, r4
movzx r4, byte [r1+r2-0x01] ; l3
add r3, r4
lea r1, [r1+2*r2]
movzx r4, byte [r1-0x01] ; l4
add r3, r4
movd mm1, r3d ; mm1 = l1+l2+l3+l4
movzx r3, byte [r1+r2-0x01] ; l5
lea r1, [r1+2*r2]
movzx r4, byte [r1-0x01] ; l6
add r3, r4
movzx r4, byte [r1+r2-0x01] ; l7
add r3, r4
lea r1, [r1+2*r2]
movzx r4, byte [r1-0x01] ; l8
add r3, r4
movd mm2, r3d ; mm2 = l5+l6+l7+l8
movq mm3, mm0
psrlq mm0, 0x20
psllq mm3, 0x20
psrlq mm3, 0x20
pxor mm4, mm4
psadbw mm0, mm4
psadbw mm3, mm4 ; sum1 = mm3+mm1, sum2 = mm0, sum3 = mm2
paddq mm3, mm1
movq mm1, mm2
paddq mm1, mm0; ; sum1 = mm3, sum2 = mm0, sum3 = mm2, sum4 = mm1
movq mm4, [mmx_0x02]
paddq mm0, mm4
psrlq mm0, 0x02
paddq mm2, mm4
psrlq mm2, 0x02
paddq mm3, mm4
paddq mm3, mm4
psrlq mm3, 0x03
paddq mm1, mm4
paddq mm1, mm4
psrlq mm1, 0x03
pmuludq mm0, [mmx_01bytes]
pmuludq mm3, [mmx_01bytes]
psllq mm0, 0x20
pxor mm0, mm3 ; mm0 = m_up
pmuludq mm2, [mmx_01bytes]
pmuludq mm1, [mmx_01bytes]
psllq mm1, 0x20
pxor mm1, mm2 ; mm2 = m_down
movq [r0], mm0
movq [r0+0x08], mm0
movq [r0+0x10], mm0
movq [r0+0x18], mm0
movq [r0+0x20], mm1
movq [r0+0x28], mm1
movq [r0+0x30], mm1
movq [r0+0x38], mm1
pop r4
pop r3
WELSEMMS
ret
;***********************************************************************
;
; void WelsI16x16LumaPredDc_sse2(uint8_t *pred, uint8_t *pRef, int32_t stride)
;***********************************************************************
WELS_EXTERN WelsI16x16LumaPredDc_sse2
push r3
push r4
%assign push_num 2
LOAD_3_PARA
SIGN_EXTENSION r2, r2d
sub r1, r2
movdqa xmm0, [r1] ; read one row
pxor xmm1, xmm1
psadbw xmm0, xmm1
movdqa xmm1, xmm0
psrldq xmm1, 0x08
pslldq xmm0, 0x08
psrldq xmm0, 0x08
paddw xmm0, xmm1
movzx r3, byte [r1+r2-0x01]
movzx r4, byte [r1+2*r2-0x01]
add r3, r4
lea r1, [r1+r2]
LOAD_2_LEFT_AND_ADD
LOAD_2_LEFT_AND_ADD
LOAD_2_LEFT_AND_ADD
LOAD_2_LEFT_AND_ADD
LOAD_2_LEFT_AND_ADD
LOAD_2_LEFT_AND_ADD
LOAD_2_LEFT_AND_ADD
add r3, 0x10
movd xmm1, r3d
paddw xmm0, xmm1
psrld xmm0, 0x05
pmuludq xmm0, [mmx_01bytes]
pshufd xmm0, xmm0, 0
movdqa [r0], xmm0
movdqa [r0+0x10], xmm0
movdqa [r0+0x20], xmm0
movdqa [r0+0x30], xmm0
movdqa [r0+0x40], xmm0
movdqa [r0+0x50], xmm0
movdqa [r0+0x60], xmm0
movdqa [r0+0x70], xmm0
movdqa [r0+0x80], xmm0
movdqa [r0+0x90], xmm0
movdqa [r0+0xa0], xmm0
movdqa [r0+0xb0], xmm0
movdqa [r0+0xc0], xmm0
movdqa [r0+0xd0], xmm0
movdqa [r0+0xe0], xmm0
movdqa [r0+0xf0], xmm0
pop r4
pop r3
ret | syureyi/gitTest | codec/encoder/core/x86/intra_pred.asm | Assembly | bsd-2-clause | 31,284 |
;
; Copyright (c) 2010 The Webm project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license and patent
; grant that can be found in the LICENSE file in the root of the source
; tree. All contributing project authors may be found in the AUTHORS
; file in the root of the source tree.
;
EXPORT |idct_dequant_dc_0_2x_neon|
ARM
REQUIRE8
PRESERVE8
AREA ||.text||, CODE, READONLY, ALIGN=2
;void idct_dequant_dc_0_2x_neon(short *q, short *dq,
; unsigned char *dst, int stride);
; r0 *q,
; r1 *dq,
; r2 *dst
; r3 stride
; sp *dc
|idct_dequant_dc_0_2x_neon| PROC
; no q- or dq-coeffs, so r0 and r1 are free to use
ldr r1, [sp] ; *dc
add r12, r2, #4
ldr r0, [r1]
vld1.32 {d2[0]}, [r2], r3 ; lo
vld1.32 {d8[0]}, [r12], r3 ; hi
vld1.32 {d2[1]}, [r2], r3
vld1.32 {d8[1]}, [r12], r3
vld1.32 {d4[0]}, [r2], r3
vld1.32 {d10[0]}, [r12], r3
vld1.32 {d4[1]}, [r2], r3
vld1.32 {d10[1]}, [r12]
sxth r1, r0 ; lo *dc
add r1, r1, #4
asr r1, r1, #3
vdup.16 q0, r1
sxth r0, r0, ror #16 ; hi *dc
add r0, r0, #4
asr r0, r0, #3
vdup.16 q3, r0
vaddw.u8 q1, q0, d2 ; lo
vaddw.u8 q2, q0, d4
vaddw.u8 q4, q3, d8 ; hi
vaddw.u8 q5, q3, d10
vqmovun.s16 d2, q1 ; lo
vqmovun.s16 d4, q2
vqmovun.s16 d8, q4 ; hi
vqmovun.s16 d10, q5
sub r2, r2, r3, lsl #2 ; dst - 4*stride
add r0, r2, #4
vst1.32 {d2[0]}, [r2], r3 ; lo
vst1.32 {d8[0]}, [r0], r3 ; hi
vst1.32 {d2[1]}, [r2], r3
vst1.32 {d8[1]}, [r0], r3
vst1.32 {d4[0]}, [r2], r3
vst1.32 {d10[0]}, [r0], r3
vst1.32 {d4[1]}, [r2]
vst1.32 {d10[1]}, [r0]
bx lr
ENDP ;|idct_dequant_dc_0_2x_neon|
END
| nsinha/libvpx | vp8/decoder/arm/neon/idct_dequant_dc_0_2x_neon.asm | Assembly | bsd-3-clause | 2,260 |
; The Z80 tester.
;
; Copyright (C) 2012 Patrik Rak (patrik@raxoft.cz)
;
; This source code is released under the MIT license, see included license.txt.
opsize equ 4+postccf ; Size of the tested instruction sequence.
datasize equ 16 ; Size of the tested registers and data.
vecsize equ opsize+datasize ; Size of entire test vector.
test: ld (.spptr+1),sp
if maskflags ; Keep mask for official flags.
ld a,(hl)
ld (.flagptr+1),a
endif
inc hl
ld de,vector ; Init the test vector, counter and shifter.
ld bc,vecsize
call .copy
add hl,bc
call .copy
call .copy
add hl,bc
ld (.valptr+1),de
inc de
call .clear
ld (.maskptr+1),de
xor a
ld (de),a
inc de
call .copy
ld a,0x07 ; Make sure we get 0
out (0xfe),a ; on MIC bit when doing IN.
ld a,0xa9 ; Set I,R,AF' to known values.
ld i,a
ld r,a
or a
ex af,af
ld bc,65535 ; Init CRC.
ld d,b
ld e,c
exx
ld sp,data.regs
; Test vector sequence combinator.
.loop ld hl,counter
ld de,shifter+1
ld bc,vector
macro combine base,count,offset:0,last:1
repeat count
ld a,(bc)
xor (hl)
ex de,hl
xor (hl)
ld (base+offset+@#),a
if ( @# < count-1 ) | ! last
inc c
inc e
inc l
endif
endrepeat
endm
ld a,(bc)
xor (hl)
ex de,hl
xor (hl)
cp 0x76 ; Skip halt.
jp z,.next
ld (.opcode),a
inc c
inc e
inc l
ld a,(bc)
xor (hl)
ex de,hl
xor (hl)
ld (.opcode+1),a
cp 0x76 ; Skip halt...
jp nz,.ok
ld a,(.opcode)
and 0xdf ; ... with IX/IY prefix.
cp 0xdd
jp z,.next
.ok inc c
inc e
inc l
combine .opcode,opsize-2,2,0
combine data,datasize
; The test itself.
pop af
pop bc
pop de
pop hl
pop ix
pop iy
ld sp,(data.sp)
.opcode ds opsize
.continue
if memptr
ld hl,data
bit 0,(hl)
endif
ld (data.sp),sp
ld sp,data.regstop
push iy
push ix
push hl
push de
push bc
push af
ld hl,data
if maskflags
ld a,(hl)
.flagptr and 0xff
if ! onlyflags
ld (hl),a
endif
endif
; CRC update.
if ! onlyflags
ld b,datasize
endif
if ! ( onlyflags & maskflags )
.crcloop ld a,(hl)
endif
exx
xor e
ld l,a
ld h,crctable/256
ld a,(hl)
xor d
ld e,a
inc h
ld a,(hl)
xor c
ld d,a
inc h
ld a,(hl)
xor b
ld c,a
inc h
ld b,(hl)
exx
if ! onlyflags
inc hl
djnz .crcloop
endif
; Multibyte counter with arbitrary bit mask.
.next ld hl,countmask
ld de,counter
ld b,vecsize
.countloop ld a,(de)
or a
jr z,.countnext
dec a
and (hl)
ld (de),a
jp .loop
.countnext ld a,(hl)
ld (de),a
inc l
inc e
djnz .countloop
; Multibyte shifter with arbitrary bit mask.
.maskptr ld hl,shiftmask
.valptr ld de,shifter
ld a,(de)
add a,a
neg
add (hl)
xor (hl)
and (hl)
ld (de),a
jp nz,.loop
.shiftloop inc l
inc e
ld a,e
cp shiftend % 256
jr z,.exit
ld a,(hl)
dec a
xor (hl)
and (hl)
jr z,.shiftloop
ld (de),a
ld (.maskptr+1),hl
ld (.valptr+1),de
jp .loop
.exit exx
.spptr ld sp,0
ret
; Misc helper routines.
.copy push hl
push bc
ldir
pop bc
pop hl
ret
.clear push hl
push bc
ld h,d
ld l,e
ld (hl),0
inc de
dec bc
ldir
pop bc
pop hl
ret
align 256
include crctab.asm
; If this moves from 0x8800, all tests which use this address
; will need to have their CRCs updated, so don't move it.
align 256
data
.regs ds datasize-4
.regstop
.mem ds 2
.sp ds 2
.jump
if postccf
ccf
else
inc bc
endif
jp test.continue
; This entire workspace must be kept within single 256 byte page.
vector ds vecsize
counter ds vecsize
countmask ds vecsize
shifter ds 1+vecsize
shiftend
shiftmask ds 1+vecsize
; EOF ;
| jbert/zog | z80test-1.0/src/idea.asm | Assembly | mit | 6,668 |
;******************************************************************************
;* MMX optimized deinterlacing functions
;* Copyright (c) 2010 Vitor Sessak
;* Copyright (c) 2002 Michael Niedermayer
;*
;* This file is part of FFmpeg.
;*
;* FFmpeg is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* FFmpeg is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with FFmpeg; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
%include "libavutil/x86/x86inc.asm"
%include "libavutil/x86/x86util.asm"
SECTION_RODATA
cextern pw_4
SECTION .text
%macro DEINTERLACE 1
%ifidn %1, inplace
;void ff_deinterlace_line_inplace_mmx(const uint8_t *lum_m4, const uint8_t *lum_m3, const uint8_t *lum_m2, const uint8_t *lum_m1, const uint8_t *lum, int size)
cglobal deinterlace_line_inplace_mmx, 6,6,7, lum_m4, lum_m3, lum_m2, lum_m1, lum, size
%else
;void ff_deinterlace_line_mmx(uint8_t *dst, const uint8_t *lum_m4, const uint8_t *lum_m3, const uint8_t *lum_m2, const uint8_t *lum_m1, const uint8_t *lum, int size)
cglobal deinterlace_line_mmx, 7,7,7, dst, lum_m4, lum_m3, lum_m2, lum_m1, lum, size
%endif
pxor mm7, mm7
movq mm6, [pw_4]
.nextrow:
movd mm0, [lum_m4q]
movd mm1, [lum_m3q]
movd mm2, [lum_m2q]
%ifidn %1, inplace
movd [lum_m4q], mm2
%endif
movd mm3, [lum_m1q]
movd mm4, [lumq]
punpcklbw mm0, mm7
punpcklbw mm1, mm7
punpcklbw mm2, mm7
punpcklbw mm3, mm7
punpcklbw mm4, mm7
paddw mm1, mm3
psllw mm2, 1
paddw mm0, mm4
psllw mm1, 2
paddw mm2, mm6
paddw mm1, mm2
psubusw mm1, mm0
psrlw mm1, 3
packuswb mm1, mm7
%ifidn %1, inplace
movd [lum_m2q], mm1
%else
movd [dstq], mm1
add dstq, 4
%endif
add lum_m4q, 4
add lum_m3q, 4
add lum_m2q, 4
add lum_m1q, 4
add lumq, 4
sub sized, 4
jg .nextrow
REP_RET
%endmacro
DEINTERLACE ""
DEINTERLACE inplace
| leighpauls/k2cro4 | third_party/ffmpeg/libavcodec/x86/deinterlace.asm | Assembly | bsd-3-clause | 2,569 |
{ 'abc_class': 'AbcFile'
, 'minor_version': 16
, 'major_version': 46
, 'int_pool': [ undefined
, '10' ]
, 'uint_pool': [ undefined ]
, 'double_pool': [ undefined ]
, 'utf8_pool': [ undefined
, ''
, 'Object'
, 'Array'
, 'RegExp'
, 'A'
, 'x'
, 'B'
, 'y'
, 'print'
, 'static hi'
, 'static hi from B' ]
, 'namespace_pool': [ undefined
, { 'kind': 'PackageNamespace'
, 'utf8': 1 }
, { 'kind': 'Namespace'
, 'utf8': 1 } ]
, 'nsset_pool': [ undefined
, [ 2 ] ]
, 'name_pool': [ undefined
, { 'kind': 'QName'
, 'ns': 1
, 'utf8': 2 }
, { 'kind': 'QName'
, 'ns': 1
, 'utf8': 3 }
, { 'kind': 'QName'
, 'ns': 1
, 'utf8': 4 }
, { 'kind': 'QName'
, 'ns': 2
, 'utf8': 5 }
, { 'kind': 'QName'
, 'ns': 2
, 'utf8': 2 }
, { 'kind': 'QName'
, 'ns': 2
, 'utf8': 6 }
, { 'kind': 'Multiname'
, 'utf8': 6
, 'nsset': 1 }
, { 'kind': 'QName'
, 'ns': 2
, 'utf8': 7 }
, { 'kind': 'QName'
, 'ns': 2
, 'utf8': 8 }
, { 'kind': 'Multiname'
, 'utf8': 9
, 'nsset': 1 }
, { 'kind': 'Multiname'
, 'utf8': 5
, 'nsset': 1 }
, { 'kind': 'Multiname'
, 'utf8': 7
, 'nsset': 1 }
, { 'kind': 'Multiname'
, 'utf8': 8
, 'nsset': 1 } ]
, 'method_infos': [ { 'ret_type': 0
, 'param_types': [0
, ]
, 'name': 0
, 'flags': 2
, 'optional_count': 0
, 'value_kind': [ ]
, 'param_names': [ ] }
, { 'ret_type': 0
, 'param_types': []
, 'name': 0
, 'flags': 0
, 'optional_count': 0
, 'value_kind': [ ]
, 'param_names': [ ] }
, { 'ret_type': 0
, 'param_types': [0
, ]
, 'name': 0
, 'flags': 2
, 'optional_count': 0
, 'value_kind': [ ]
, 'param_names': [ ] }
, { 'ret_type': 0
, 'param_types': []
, 'name': 0
, 'flags': 0
, 'optional_count': 0
, 'value_kind': [ ]
, 'param_names': [ ] }
, { 'ret_type': 0
, 'param_types': []
, 'name': 0
, 'flags': 0
, 'optional_count': 0
, 'value_kind': [ ]
, 'param_names': [ ] }
, ]
, 'metadata_infos': [ ]
, 'instance_infos': [ { 'name': 4
, 'super_name': 5
, 'flags': 0
, 'protected_namespace': 0
, 'interface_count': 0
, 'interfaces': []
, 'iinit': 0
, 'traits': [ { 'name': 6
, 'kind': 0
, 'attrs': 0
, 'slot_id': 0
, 'type_name': 0
, 'val_index': 0 }
, ] }
, { 'name': 8
, 'super_name': 5
, 'flags': 0
, 'protected_namespace': 0
, 'interface_count': 0
, 'interfaces': []
, 'iinit': 2
, 'traits': [ { 'name': 9
, 'kind': 0
, 'attrs': 0
, 'slot_id': 0
, 'type_name': 0
, 'val_index': 0 }
, ] }
, ]
, 'class_infos': [ { 'cinit': 1
, 'traits': [ ] }
, { 'cinit': 3
, 'traits': [ ] }
, ]
, 'script_infos': [ { 'init': 4
, 'traits': [ { 'name': 4
, 'kind': 4
, 'attrs': 0
, 'slot_id': 0
, 'class': 0 }
, { 'name': 8
, 'kind': 4
, 'attrs': 0
, 'slot_id': 0
, 'class': 1 }
, ] }
, ]
, 'method_bodys': [ { 'method_info': 0
, 'max_stack': 5
, 'max_regs': 3
, 'scope_depth': 2
, 'max_scope': 4
, 'code': [ [ 'getlocal0' ]
, [ 'dup' ]
, [ 'pushscope' ]
, [ 'pushundefined' ]
, [ 'pop' ]
, [ 'popscope' ]
, [ 'newactivation' ]
, [ 'dup' ]
, [ 'setlocal2' ]
, [ 'dup' ]
, [ 'pushwith' ]
, [ 'findproperty', 6 ]
, [ 'getlocal1' ]
, [ 'setproperty', 6 ]
, [ 'pushundefined' ]
, [ 'pop' ]
, [ 'getlocal0' ]
, [ 'findpropstrict', 7 ]
, [ 'getproperty', 7 ]
, [ 'setproperty', 6 ]
, [ 'pushundefined' ]
, [ 'pop' ]
, [ 'getlocal0' ]
, [ 'constructsuper', 0 ]
, [ 'popscope' ]
, [ 'getlocal0' ]
, [ 'pushscope' ]
, [ 'pushscope' ]
, [ 'kill', 2 ]
, [ 'returnvoid' ]
, ]
, 'exceptions': [ ]
, 'fixtures': [ ]
, 'traits': [ { 'name': 6
, 'kind': 0
, 'attrs': 0
, 'slot_id': 0
, 'type_name': 0
, 'val_index': 0 }
, ] }
, { 'method_info': 1
, 'max_stack': 1
, 'max_regs': 1
, 'scope_depth': 0
, 'max_scope': 1
, 'code': [ [ 'getlocal0' ]
, [ 'pushscope' ]
, [ 'returnvoid' ]
, ]
, 'exceptions': [ ]
, 'fixtures': [ ]
, 'traits': [ ] }
, { 'method_info': 2
, 'max_stack': 5
, 'max_regs': 3
, 'scope_depth': 2
, 'max_scope': 4
, 'code': [ [ 'getlocal0' ]
, [ 'dup' ]
, [ 'pushscope' ]
, [ 'pushundefined' ]
, [ 'pop' ]
, [ 'popscope' ]
, [ 'newactivation' ]
, [ 'dup' ]
, [ 'setlocal2' ]
, [ 'dup' ]
, [ 'pushwith' ]
, [ 'findproperty', 6 ]
, [ 'getlocal1' ]
, [ 'setproperty', 6 ]
, [ 'pushundefined' ]
, [ 'pop' ]
, [ 'getlocal0' ]
, [ 'findpropstrict', 7 ]
, [ 'getproperty', 7 ]
, [ 'setproperty', 9 ]
, [ 'pushundefined' ]
, [ 'pop' ]
, [ 'getlocal0' ]
, [ 'constructsuper', 0 ]
, [ 'popscope' ]
, [ 'getlocal0' ]
, [ 'pushscope' ]
, [ 'pushscope' ]
, [ 'kill', 2 ]
, [ 'returnvoid' ]
, ]
, 'exceptions': [ ]
, 'fixtures': [ ]
, 'traits': [ { 'name': 6
, 'kind': 0
, 'attrs': 0
, 'slot_id': 0
, 'type_name': 0
, 'val_index': 0 }
, ] }
, { 'method_info': 3
, 'max_stack': 1
, 'max_regs': 1
, 'scope_depth': 0
, 'max_scope': 1
, 'code': [ [ 'getlocal0' ]
, [ 'pushscope' ]
, [ 'returnvoid' ]
, ]
, 'exceptions': [ ]
, 'fixtures': [ ]
, 'traits': [ ] }
, { 'method_info': 4
, 'max_stack': 3
, 'max_regs': 1
, 'scope_depth': 0
, 'max_scope': 2
, 'code': [ [ 'getlocal0' ]
, [ 'pushscope' ]
, [ 'findpropstrict', 5 ]
, [ 'getproperty', 5 ]
, [ 'dup' ]
, [ 'pushscope' ]
, [ 'newclass', 0 ]
, [ 'popscope' ]
, [ 'getglobalscope' ]
, [ 'swap' ]
, [ 'initproperty', 4 ]
, [ 'findpropstrict', 5 ]
, [ 'getproperty', 5 ]
, [ 'dup' ]
, [ 'pushscope' ]
, [ 'newclass', 1 ]
, [ 'popscope' ]
, [ 'getglobalscope' ]
, [ 'swap' ]
, [ 'initproperty', 8 ]
, [ 'findpropstrict', 10 ]
, [ 'pushstring', 10 ]
, [ 'callproperty', 10, 1 ]
, [ 'pop' ]
, [ 'findpropstrict', 10 ]
, [ 'findpropstrict', 11 ]
, [ 'getproperty', 11 ]
, [ 'pushint', 1 ]
, [ 'construct', 1 ]
, [ 'getproperty', 7 ]
, [ 'callproperty', 10, 1 ]
, [ 'pop' ]
, [ 'findpropstrict', 10 ]
, [ 'pushstring', 11 ]
, [ 'callproperty', 10, 1 ]
, [ 'pop' ]
, [ 'findpropstrict', 10 ]
, [ 'findpropstrict', 12 ]
, [ 'getproperty', 12 ]
, [ 'pushint', 1 ]
, [ 'construct', 1 ]
, [ 'getproperty', 13 ]
, [ 'callproperty', 10, 1 ]
, [ 'pop' ]
, [ 'returnvoid' ]
, ]
, 'exceptions': [ ]
, 'fixtures': [ ]
, 'traits': [ ] }
, ] } | greyhavens/thane | tamarin-central/esc/test/sanity/base/cls.es.asm | Assembly | bsd-2-clause | 13,292 |
// --- System Core Data --
define CORE_RT_TABLE 20006h
// CORE RT TABLE
define rt_Instance 0000h
define rt_loadSymbol 0004h
define rt_loadName 0008h
define rt_interprete 000Ch
define rt_lasterr 0010h
define rt_loadaddrinfo 0014h
define rt_loadSubject 0018h
define rt_loadSubjName 001Ch
rstructure core_rt'dll_name
db 101 // e
db 108 // l
db 101 // e
db 110 // n
db 097 // a
db 114 // r
db 116 // t
db 046 // .
db 100 // d
db 108 // l
db 108 // l
db 0
end
rstructure core_rt'LoadAddressInfoFunc
db 076 // L
db 111 // o
db 097 // a
db 100 // d
db 065 // A
db 100 // d
db 100 // d
db 114 // r
db 101 // e
db 115 // s
db 115 // s
db 073 // I
db 110 // n
db 102 // f
db 111 // o
db 0
end
rstructure core_rt'LoadClassNameFunc
db 076 // L
db 111 // o
db 097 // a
db 100 // d
db 067 // C
db 108 // l
db 097 // a
db 115 // s
db 115 // s
db 078 // N
db 097 // a
db 109 // m
db 101 // e
db 0
end
rstructure core_rt'GetSymbolRefFunc
db 071 // G
db 101 // e
db 116 // t
db 083 // S
db 121 // y
db 109 // m
db 098 // b
db 111 // o
db 108 // l
db 082 // R
db 101 // e
db 102 // f
db 0
end
rstructure core_rt'InterpreterFunc
db 073 // I
db 110 // n
db 116 // t
db 101 // e
db 114 // r
db 112 // p
db 114 // r
db 101 // e
db 116 // t
db 101 // e
db 114 // r
db 0
end
rstructure core_rt'LastErrFunc
db 071 // G
db 101 // e
db 116 // t
db 082 // R
db 084 // T
db 076 // L
db 097 // a
db 115 // s
db 116 // t
db 069 // E
db 114 // r
db 114 // r
db 111 // o
db 114 // r
db 0
end
rstructure core_rt'InitFunc
db 073 // I
db 110 // n
db 105 // i
db 116 // t
db 0
end
rstructure core_rt'LoadSubjectFunc
db 076 // L
db 111 // o
db 097 // a
db 100 // d
db 083 // S
db 117 // u
db 098 // b
db 106 // j
db 101 // e
db 099 // c
db 116 // t
db 0
end
rstructure core_rt'LoadSubjectNameFunc
db 076 // L
db 111 // o
db 097 // a
db 100 // d
db 083 // S
db 117 // u
db 098 // b
db 106 // j
db 101 // e
db 099 // c
db 116 // t
db 078 // N
db 097 // a
db 109 // m
db 101 // e
db 0
end
procedure core_rt'init_rt_info
// load dll
mov eax, rdata : "$native'core_rt'dll_name"
push eax
call extern 'dlls'KERNEL32.LoadLibraryA
test eax, eax
jz lbCannotLoadDLL
push eax // save hModule
// ; init rt_table
mov esi, rdata:"$native'core_rt'LoadAddressInfoFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_loadaddrinfo], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'LoadClassNameFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_loadName], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'GetSymbolRefFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_loadSymbol], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'InterpreterFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_interprete], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'LastErrFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_lasterr], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'LoadSubjectFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_loadSubject], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'LoadSubjectNameFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_loadSubjName], eax
mov eax, [esp]
mov esi, rdata:"$native'core_rt'InitFunc"
push esi
push eax
call extern 'dlls'KERNEL32.GetProcAddress
test eax, eax
jz lbCannotLoadRT
push const : "$elena'@package"
push 0
call eax
add esp, 8
mov esi, data : %CORE_RT_TABLE
mov [esi + rt_Instance], eax
lbCannotLoadRT:
add esp, 4
lbCannotLoadDLL:
ret
end
| bencz/cpu-simulator | elena_lang/src30/asm/x32/core_rt.asm | Assembly | apache-2.0 | 4,707 |
global _start
%include "header.inc"
fldz
fchs
%include "footer.inc"
| copy/v86 | tests/nasm/fchs.asm | Assembly | bsd-2-clause | 79 |
mac1 MACRO
.mac1_start:
ld b,b
ld b,c
.mac1_end:
ENDM
mac2 MACRO
.mac2_start:
ld c,b
.mac1_emit:
mac1
ld c,c
.mac2_end:
ENDM
mac3 MACRO
.mac3_start:
ld d,b
.mac2_emit:
mac2
ld d,c
.mac3_end:
ENDM
DEVICE ZXSPECTRUMNEXT
MMU 0 7, 10 ; map pages 10..17 to each slot
ORG $8000
OUTPUT "sld_nested_macros.bin"
main:
.start:
ld e,b
.mac3_emit1:
mac3
ld e,c
.mac3_emit2:
mac3
ld e,d
.end:
CSPECTMAP "sld_nested_macros.sym"
| z00m128/sjasmplus | tests/listing/sld/sld_nested_macros.asm | Assembly | bsd-3-clause | 708 |
build/amo.elf: file format elf32-littleriscv
Disassembly of section .crt_section:
80000000 <_start>:
80000000: 00100e13 li t3,1
80000004: 00000097 auipc ra,0x0
80000008: 27408093 addi ra,ra,628 # 80000278 <test1_data>
8000000c: 02d00113 li sp,45
80000010: 0820a1af amoswap.w gp,sp,(ra)
80000014: 0000a203 lw tp,0(ra)
80000018: 02d00a13 li s4,45
8000001c: 224a1663 bne s4,tp,80000248 <fail>
80000020: 00b00a13 li s4,11
80000024: 223a1263 bne s4,gp,80000248 <fail>
80000028 <test2>:
80000028: 00200e13 li t3,2
8000002c: 00000097 auipc ra,0x0
80000030: 25008093 addi ra,ra,592 # 8000027c <test2_data>
80000034: 03700113 li sp,55
80000038: 0820a1af amoswap.w gp,sp,(ra)
8000003c: 0000a203 lw tp,0(ra)
80000040: 03700a13 li s4,55
80000044: 204a1263 bne s4,tp,80000248 <fail>
80000048: 01600a13 li s4,22
8000004c: 1e3a1e63 bne s4,gp,80000248 <fail>
80000050 <test3>:
80000050: 00300e13 li t3,3
80000054: 00000097 auipc ra,0x0
80000058: 22c08093 addi ra,ra,556 # 80000280 <test3_data>
8000005c: 04200113 li sp,66
80000060: 0020a1af amoadd.w gp,sp,(ra)
80000064: 0000a203 lw tp,0(ra)
80000068: 08b00a13 li s4,139
8000006c: 1c4a1e63 bne s4,tp,80000248 <fail>
80000070: 04900a13 li s4,73
80000074: 1c3a1a63 bne s4,gp,80000248 <fail>
80000078 <test4>:
80000078: 00400e13 li t3,4
8000007c: 00000097 auipc ra,0x0
80000080: 20808093 addi ra,ra,520 # 80000284 <test4_data>
80000084: 05700113 li sp,87
80000088: 2020a1af amoxor.w gp,sp,(ra)
8000008c: 0000a203 lw tp,0(ra)
80000090: 06d00a13 li s4,109
80000094: 1a4a1a63 bne s4,tp,80000248 <fail>
80000098: 03a00a13 li s4,58
8000009c: 1a3a1663 bne s4,gp,80000248 <fail>
800000a0 <test5>:
800000a0: 00500e13 li t3,5
800000a4: 00000097 auipc ra,0x0
800000a8: 1e408093 addi ra,ra,484 # 80000288 <test5_data>
800000ac: 02c00113 li sp,44
800000b0: 6020a1af amoand.w gp,sp,(ra)
800000b4: 0000a203 lw tp,0(ra)
800000b8: 02800a13 li s4,40
800000bc: 184a1663 bne s4,tp,80000248 <fail>
800000c0: 03800a13 li s4,56
800000c4: 183a1263 bne s4,gp,80000248 <fail>
800000c8 <test6>:
800000c8: 00600e13 li t3,6
800000cc: 00000097 auipc ra,0x0
800000d0: 1c008093 addi ra,ra,448 # 8000028c <test6_data>
800000d4: 01800113 li sp,24
800000d8: 4020a1af amoor.w gp,sp,(ra)
800000dc: 0000a203 lw tp,0(ra)
800000e0: 05b00a13 li s4,91
800000e4: 164a1263 bne s4,tp,80000248 <fail>
800000e8: 04b00a13 li s4,75
800000ec: 143a1e63 bne s4,gp,80000248 <fail>
800000f0 <test7>:
800000f0: 00700e13 li t3,7
800000f4: 00000097 auipc ra,0x0
800000f8: 19c08093 addi ra,ra,412 # 80000290 <test7_data>
800000fc: 01800113 li sp,24
80000100: 8020a1af amomin.w gp,sp,(ra)
80000104: 0000a203 lw tp,0(ra)
80000108: 01800a13 li s4,24
8000010c: 124a1e63 bne s4,tp,80000248 <fail>
80000110: 03800a13 li s4,56
80000114: 123a1a63 bne s4,gp,80000248 <fail>
80000118 <test8>:
80000118: 00800e13 li t3,8
8000011c: 00000097 auipc ra,0x0
80000120: 17808093 addi ra,ra,376 # 80000294 <test8_data>
80000124: 05800113 li sp,88
80000128: 8020a1af amomin.w gp,sp,(ra)
8000012c: 0000a203 lw tp,0(ra)
80000130: 05300a13 li s4,83
80000134: 104a1a63 bne s4,tp,80000248 <fail>
80000138: 05300a13 li s4,83
8000013c: 103a1663 bne s4,gp,80000248 <fail>
80000140 <test9>:
80000140: 00900e13 li t3,9
80000144: 00000097 auipc ra,0x0
80000148: 15408093 addi ra,ra,340 # 80000298 <test9_data>
8000014c: fca00113 li sp,-54
80000150: 8020a1af amomin.w gp,sp,(ra)
80000154: 0000a203 lw tp,0(ra)
80000158: fca00a13 li s4,-54
8000015c: 0e4a1663 bne s4,tp,80000248 <fail>
80000160: 02100a13 li s4,33
80000164: 0e3a1263 bne s4,gp,80000248 <fail>
80000168 <test10>:
80000168: 00a00e13 li t3,10
8000016c: 00000097 auipc ra,0x0
80000170: 13008093 addi ra,ra,304 # 8000029c <test10_data>
80000174: 03400113 li sp,52
80000178: 8020a1af amomin.w gp,sp,(ra)
8000017c: 0000a203 lw tp,0(ra)
80000180: fbf00a13 li s4,-65
80000184: 0c4a1263 bne s4,tp,80000248 <fail>
80000188: fbf00a13 li s4,-65
8000018c: 0a3a1e63 bne s4,gp,80000248 <fail>
80000190 <test11>:
80000190: 00b00e13 li t3,11
80000194: 00000097 auipc ra,0x0
80000198: 10c08093 addi ra,ra,268 # 800002a0 <test11_data>
8000019c: fcc00113 li sp,-52
800001a0: a020a1af amomax.w gp,sp,(ra)
800001a4: 0000a203 lw tp,0(ra)
800001a8: fcc00a13 li s4,-52
800001ac: 084a1e63 bne s4,tp,80000248 <fail>
800001b0: fa900a13 li s4,-87
800001b4: 083a1a63 bne s4,gp,80000248 <fail>
800001b8 <test12>:
800001b8: 00c00e13 li t3,12
800001bc: 00000097 auipc ra,0x0
800001c0: 0e808093 addi ra,ra,232 # 800002a4 <test12_data>
800001c4: 03400113 li sp,52
800001c8: a020a1af amomax.w gp,sp,(ra)
800001cc: 0000a203 lw tp,0(ra)
800001d0: 03400a13 li s4,52
800001d4: 064a1a63 bne s4,tp,80000248 <fail>
800001d8: fc900a13 li s4,-55
800001dc: 063a1663 bne s4,gp,80000248 <fail>
800001e0 <test13>:
800001e0: 00d00e13 li t3,13
800001e4: 00000097 auipc ra,0x0
800001e8: 0c408093 addi ra,ra,196 # 800002a8 <test13_data>
800001ec: ffff0137 lui sp,0xffff0
800001f0: c020a1af amominu.w gp,sp,(ra)
800001f4: 0000a203 lw tp,0(ra)
800001f8: ffff0a37 lui s4,0xffff0
800001fc: 044a1663 bne s4,tp,80000248 <fail>
80000200: ffff0a37 lui s4,0xffff0
80000204: 004a0a13 addi s4,s4,4 # ffff0004 <test14_data+0x7ffefd58>
80000208: 043a1063 bne s4,gp,80000248 <fail>
8000020c: 0480006f j 80000254 <pass>
80000210 <test14>:
80000210: 00e00e13 li t3,14
80000214: 00000097 auipc ra,0x0
80000218: 09808093 addi ra,ra,152 # 800002ac <test14_data>
8000021c: ffff0137 lui sp,0xffff0
80000220: 00c10113 addi sp,sp,12 # ffff000c <test14_data+0x7ffefd60>
80000224: e020a1af amomaxu.w gp,sp,(ra)
80000228: 0000a203 lw tp,0(ra)
8000022c: ffff0a37 lui s4,0xffff0
80000230: 00ca0a13 addi s4,s4,12 # ffff000c <test14_data+0x7ffefd60>
80000234: 004a1a63 bne s4,tp,80000248 <fail>
80000238: ffff0a37 lui s4,0xffff0
8000023c: 005a0a13 addi s4,s4,5 # ffff0005 <test14_data+0x7ffefd59>
80000240: 003a1463 bne s4,gp,80000248 <fail>
80000244: 0100006f j 80000254 <pass>
80000248 <fail>:
80000248: f0100137 lui sp,0xf0100
8000024c: f2410113 addi sp,sp,-220 # f00fff24 <test14_data+0x700ffc78>
80000250: 01c12023 sw t3,0(sp)
80000254 <pass>:
80000254: f0100137 lui sp,0xf0100
80000258: f2010113 addi sp,sp,-224 # f00fff20 <test14_data+0x700ffc74>
8000025c: 00012023 sw zero,0(sp)
80000260: 00000013 nop
80000264: 00000013 nop
80000268: 00000013 nop
8000026c: 00000013 nop
80000270: 00000013 nop
80000274: 00000013 nop
80000278 <test1_data>:
80000278: 0000000b 0xb
8000027c <test2_data>:
8000027c: 0016 c.slli zero,0x5
...
80000280 <test3_data>:
80000280: 0049 c.nop 18
...
80000284 <test4_data>:
80000284: 003a c.slli zero,0xe
...
80000288 <test5_data>:
80000288: 0038 addi a4,sp,8
...
8000028c <test6_data>:
8000028c: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne
80000290 <test7_data>:
80000290: 0038 addi a4,sp,8
...
80000294 <test8_data>:
80000294: 00000053 fadd.s ft0,ft0,ft0,rne
80000298 <test9_data>:
80000298: 0021 c.nop 8
...
8000029c <test10_data>:
8000029c: ffffffbf 0xffffffbf
800002a0 <test11_data>:
800002a0: ffa9 bnez a5,800001fa <test13+0x1a>
800002a2: ffff 0xffff
800002a4 <test12_data>:
800002a4: ffc9 bnez a5,8000023e <test14+0x2e>
800002a6: ffff 0xffff
800002a8 <test13_data>:
800002a8: 0004 0x4
800002aa: ffff 0xffff
800002ac <test14_data>:
800002ac: 0005 c.nop 1
800002ae: ffff 0xffff
| SpinalHDL/VexRiscv | src/test/cpp/raw/fpu/build/amo.asm | Assembly | mit | 9,007 |
format MS COFF
include "snd.inc"
include "proc32.inc"
section '.text' align 16 code readable executable
extrn hSound
public _SetBuffer@16
public _PlayBuffer@8
align 4
_SetBuffer@16: ;str:dword, src:dword, offs:dword, size:dword
push ebx
push ecx
xor eax, eax
lea ebx, [esp+12] ;[stream]
push eax ;.out_size
push eax ;.output
push 16 ;.inp_size
push ebx ;.input
push SND_SETBUFF ;.code
push dword [hSound] ;.handle
mov eax, 68
mov ebx, 17
mov ecx, esp
int 0x40
add esp, 24
pop ecx
pop ebx
ret 16
align 4
_PlayBuffer@8: ;str:dword,flags:dword
push ebx
push ecx
xor eax, eax
lea ebx, [esp+12] ;[stream]
push eax ;.out_size
push eax ;.output
push 8 ;.inp_size
push ebx ;.input
push SND_PLAY ;.code
push dword [hSound] ;.handle
mov eax, 68
mov ebx, 17
mov ecx, esp
int 0x40
add esp, 24
pop ecx
pop ebx
ret 8
| devlato/kolibrios-llvm | programs/develop/sdk/trunk/sound/src/setbuf.asm | Assembly | mit | 1,359 |
#ifdef OC_ARM_ASM
@********************************************************************
@* *
@* THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. *
@* USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
@* GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
@* IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
@* *
@* THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2010 *
@* by the Xiph.Org Foundation and contributors http://www.xiph.org/ *
@* *
@********************************************************************
@ Original implementation:
@ Copyright (C) 2009 Robin Watts for Pinknoise Productions Ltd
@ last mod: $Id:
@********************************************************************
.text; .p2align 2
.global oc_loop_filter_frag_rows_arm
@ Which bit this is depends on the order of packing within a bitfield.
@ Hopefully that doesn't change among any of the relevant compilers.
.set OC_FRAG_CODED_FLAG, 1
@ Vanilla ARM v4 version
@ .type loop_filter_h_arm, %function; loop_filter_h_arm: @ PROC
loop_filter_h_arm:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
STMFD r13!,{r3-r6,r14}
MOV r14,#8
MOV r6, #255
lfh_arm_lp:
LDRB r3, [r0, #-2] @ r3 = _pix[0]
LDRB r12,[r0, #1] @ r12= _pix[3]
LDRB r4, [r0, #-1] @ r4 = _pix[1]
LDRB r5, [r0] @ r5 = _pix[2]
SUB r3, r3, r12 @ r3 = _pix[0]-_pix[3]+4
ADD r3, r3, #4
SUB r12,r5, r4 @ r12= _pix[2]-_pix[1]
ADD r12,r12,r12,LSL #1 @ r12= 3*(_pix[2]-_pix[1])
ADD r12,r12,r3 @ r12= _pix[0]-_pix[3]+3*(_pix[2]-_pix[1])+4
MOV r12,r12,ASR #3
LDRSB r12,[r2, r12]
@ Stall (2 on Xscale)
ADDS r4, r4, r12
CMPGT r6, r4
EORLT r4, r6, r4, ASR #32
SUBS r5, r5, r12
CMPGT r6, r5
EORLT r5, r6, r5, ASR #32
STRB r4, [r0, #-1]
STRB r5, [r0], r1
SUBS r14,r14,#1
BGT lfh_arm_lp
SUB r0, r0, r1, LSL #3
LDMFD r13!,{r3-r6,PC}
@ @ .size loop_filter_h_arm, .-loop_filter_h_arm @ ENDP
@ .type loop_filter_v_arm, %function; loop_filter_v_arm: @ PROC
loop_filter_v_arm:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
STMFD r13!,{r3-r6,r14}
MOV r14,#8
MOV r6, #255
lfv_arm_lp:
LDRB r3, [r0, -r1, LSL #1] @ r3 = _pix[0]
LDRB r12,[r0, r1] @ r12= _pix[3]
LDRB r4, [r0, -r1] @ r4 = _pix[1]
LDRB r5, [r0] @ r5 = _pix[2]
SUB r3, r3, r12 @ r3 = _pix[0]-_pix[3]+4
ADD r3, r3, #4
SUB r12,r5, r4 @ r12= _pix[2]-_pix[1]
ADD r12,r12,r12,LSL #1 @ r12= 3*(_pix[2]-_pix[1])
ADD r12,r12,r3 @ r12= _pix[0]-_pix[3]+3*(_pix[2]-_pix[1])+4
MOV r12,r12,ASR #3
LDRSB r12,[r2, r12]
@ Stall (2 on Xscale)
ADDS r4, r4, r12
CMPGT r6, r4
EORLT r4, r6, r4, ASR #32
SUBS r5, r5, r12
CMPGT r6, r5
EORLT r5, r6, r5, ASR #32
STRB r4, [r0, -r1]
STRB r5, [r0], #1
SUBS r14,r14,#1
BGT lfv_arm_lp
SUB r0, r0, #8
LDMFD r13!,{r3-r6,PC}
@ @ .size loop_filter_v_arm, .-loop_filter_v_arm @ ENDP
@ .type oc_loop_filter_frag_rows_arm, %function; oc_loop_filter_frag_rows_arm: @ PROC
oc_loop_filter_frag_rows_arm:
@ r0 = _ref_frame_data
@ r1 = _ystride
@ r2 = _bv
@ r3 = _frags
@ r4 = _fragi0
@ r5 = _fragi0_end
@ r6 = _fragi_top
@ r7 = _fragi_bot
@ r8 = _frag_buf_offs
@ r9 = _nhfrags
MOV r12,r13
STMFD r13!,{r0,r4-r11,r14}
LDMFD r12,{r4-r9}
ADD r2, r2, #127 @ _bv += 127
CMP r4, r5 @ if(_fragi0>=_fragi0_end)
BGE oslffri_arm_end @ bail
SUBS r9, r9, #1 @ r9 = _nhfrags-1 if (r9<=0)
BLE oslffri_arm_end @ bail
ADD r3, r3, r4, LSL #2 @ r3 = &_frags[fragi]
ADD r8, r8, r4, LSL #2 @ r8 = &_frag_buf_offs[fragi]
SUB r7, r7, r9 @ _fragi_bot -= _nhfrags;
oslffri_arm_lp1:
MOV r10,r4 @ r10= fragi = _fragi0
ADD r11,r4, r9 @ r11= fragi_end-1=fragi+_nhfrags-1
oslffri_arm_lp2:
LDR r14,[r3], #4 @ r14= _frags[fragi] _frags++
LDR r0, [r13] @ r0 = _ref_frame_data
LDR r12,[r8], #4 @ r12= _frag_buf_offs[fragi] _frag_buf_offs++
TST r14,#OC_FRAG_CODED_FLAG
BEQ oslffri_arm_uncoded
CMP r10,r4 @ if (fragi>_fragi0)
ADD r0, r0, r12 @ r0 = _ref_frame_data + _frag_buf_offs[fragi]
BLGT loop_filter_h_arm
CMP r4, r6 @ if (_fragi0>_fragi_top)
BLGT loop_filter_v_arm
CMP r10,r11 @ if(fragi+1<fragi_end)===(fragi<fragi_end-1)
LDRLT r12,[r3] @ r12 = _frags[fragi+1]
ADD r0, r0, #8
ADD r10,r10,#1 @ r10 = fragi+1;
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG @ && _frags[fragi+1].coded==0
BLLT loop_filter_h_arm
CMP r10,r7 @ if (fragi<_fragi_bot)
LDRLT r12,[r3, r9, LSL #2] @ r12 = _frags[fragi+1+_nhfrags-1]
SUB r0, r0, #8
ADD r0, r0, r1, LSL #3
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG
BLLT loop_filter_v_arm
CMP r10,r11 @ while(fragi<=fragi_end-1)
BLE oslffri_arm_lp2
MOV r4, r10 @ r4 = fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_arm_lp1
oslffri_arm_end:
LDMFD r13!,{r0,r4-r11,PC}
oslffri_arm_uncoded:
ADD r10,r10,#1
CMP r10,r11
BLE oslffri_arm_lp2
MOV r4, r10 @ r4 = _fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_arm_lp1
LDMFD r13!,{r0,r4-r11,PC}
@ @ .size oc_loop_filter_frag_rows_arm, .-oc_loop_filter_frag_rows_arm @ ENDP
.if OC_ARM_ASM_MEDIA
.global oc_loop_filter_init_v6
.global oc_loop_filter_frag_rows_v6
@ .type oc_loop_filter_init_v6, %function; oc_loop_filter_init_v6: @ PROC
oc_loop_filter_init_v6:
@ r0 = _bv
@ r1 = _flimit (=L from the spec)
MVN r1, r1, LSL #1 @ r1 = <0xFFFFFF|255-2*L>
AND r1, r1, #255 @ r1 = ll=r10x0xFF
ORR r1, r1, r1, LSL #8 @ r1 = <ll|ll>
PKHBT r1, r1, r1, LSL #16 @ r1 = <ll|ll|ll|ll>
STR r1, [r0]
MOV PC,r14
@ @ .size oc_loop_filter_init_v6, .-oc_loop_filter_init_v6 @ ENDP
@ We could use the same strategy as the v filter below, but that would require
@ 40 instructions to load the data and transpose it into columns and another
@ 32 to write out the results at the end, plus the 52 instructions to do the
@ filtering itself.
@ This is slightly less, and less code, even assuming we could have shared the
@ 52 instructions in the middle with the other function.
@ It executes slightly fewer instructions than the ARMv6 approach David Conrad
@ proposed for FFmpeg, but not by much:
@ http://lists.mplayerhq.hu/pipermail/ffmpeg-devel/2010-February/083141.html
@ His is a lot less code, though, because it only does two rows at once instead
@ of four.
@ .type loop_filter_h_v6, %function; loop_filter_h_v6: @ PROC
loop_filter_h_v6:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int _ll
@ preserves r0-r3
STMFD r13!,{r4-r11,r14}
MOV r12, 0x0003
MOVT r12, 0x1
BL loop_filter_h_core_v6
ADD r0, r0, r1, LSL #2
BL loop_filter_h_core_v6
SUB r0, r0, r1, LSL #2
LDMFD r13!,{r4-r11,PC}
@ @ .size loop_filter_h_v6, .-loop_filter_h_v6 @ ENDP
@ .type loop_filter_h_core_v6, %function; loop_filter_h_core_v6: @ PROC
loop_filter_h_core_v6:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int _ll
@ r12= 0x10003
@ Preserves r0-r3, r12; Clobbers r4-r11.
LDR r4,[r0, #-2]! @ r4 = <p3|p2|p1|p0>
@ Single issue
LDR r5,[r0, r1]! @ r5 = <q3|q2|q1|q0>
UXTB16 r6, r4, ROR #16 @ r6 = <p0|p2>
UXTB16 r4, r4, ROR #8 @ r4 = <p3|p1>
UXTB16 r7, r5, ROR #16 @ r7 = <q0|q2>
UXTB16 r5, r5, ROR #8 @ r5 = <q3|q1>
PKHBT r8, r4, r5, LSL #16 @ r8 = <__|q1|__|p1>
PKHBT r9, r6, r7, LSL #16 @ r9 = <__|q2|__|p2>
SSUB16 r6, r4, r6 @ r6 = <p3-p0|p1-p2>
SMLAD r6, r6, r12,r12 @ r6 = <????|(p3-p0)+3*(p1-p2)+3>
SSUB16 r7, r5, r7 @ r7 = <q3-q0|q1-q2>
SMLAD r7, r7, r12,r12 @ r7 = <????|(q0-q3)+3*(q2-q1)+4>
LDR r4,[r0, r1]! @ r4 = <r3|r2|r1|r0>
MOV r6, r6, ASR #3 @ r6 = <??????|(p3-p0)+3*(p1-p2)+3>>3>
LDR r5,[r0, r1]! @ r5 = <s3|s2|s1|s0>
PKHBT r11,r6, r7, LSL #13 @ r11= <??|-R_q|??|-R_p>
UXTB16 r6, r4, ROR #16 @ r6 = <r0|r2>
UXTB16 r11,r11 @ r11= <__|-R_q|__|-R_p>
UXTB16 r4, r4, ROR #8 @ r4 = <r3|r1>
UXTB16 r7, r5, ROR #16 @ r7 = <s0|s2>
PKHBT r10,r6, r7, LSL #16 @ r10= <__|s2|__|r2>
SSUB16 r6, r4, r6 @ r6 = <r3-r0|r1-r2>
UXTB16 r5, r5, ROR #8 @ r5 = <s3|s1>
SMLAD r6, r6, r12,r12 @ r6 = <????|(r3-r0)+3*(r2-r1)+3>
SSUB16 r7, r5, r7 @ r7 = <r3-r0|r1-r2>
SMLAD r7, r7, r12,r12 @ r7 = <????|(s0-s3)+3*(s2-s1)+4>
ORR r9, r9, r10, LSL #8 @ r9 = <s2|q2|r2|p2>
MOV r6, r6, ASR #3 @ r6 = <??????|(r0-r3)+3*(r2-r1)+4>>3>
PKHBT r10,r4, r5, LSL #16 @ r10= <__|s1|__|r1>
PKHBT r6, r6, r7, LSL #13 @ r6 = <??|-R_s|??|-R_r>
ORR r8, r8, r10, LSL #8 @ r8 = <s1|q1|r1|p1>
UXTB16 r6, r6 @ r6 = <__|-R_s|__|-R_r>
MOV r10,#0
ORR r6, r11,r6, LSL #8 @ r6 = <-R_s|-R_q|-R_r|-R_p>
@ Single issue
@ There's no min, max or abs instruction.
@ SSUB8 and SEL will work for abs, and we can do all the rest with
@ unsigned saturated adds, which means the GE flags are still all
@ set when we're done computing lflim(abs(R_i),L).
@ This allows us to both add and subtract, and split the results by
@ the original sign of R_i.
SSUB8 r7, r10,r6
@ Single issue
SEL r7, r7, r6 @ r7 = abs(R_i)
@ Single issue
UQADD8 r4, r7, r2 @ r4 = 255-max(2*L-abs(R_i),0)
@ Single issue
UQADD8 r7, r7, r4
@ Single issue
UQSUB8 r7, r7, r4 @ r7 = min(abs(R_i),max(2*L-abs(R_i),0))
@ Single issue
UQSUB8 r4, r8, r7
UQADD8 r5, r9, r7
UQADD8 r8, r8, r7
UQSUB8 r9, r9, r7
SEL r8, r8, r4 @ r8 = p1+lflim(R_i,L)
SEL r9, r9, r5 @ r9 = p2-lflim(R_i,L)
MOV r5, r9, LSR #24 @ r5 = s2
STRB r5, [r0,#2]!
MOV r4, r8, LSR #24 @ r4 = s1
STRB r4, [r0,#-1]
MOV r5, r9, LSR #8 @ r5 = r2
STRB r5, [r0,-r1]!
MOV r4, r8, LSR #8 @ r4 = r1
STRB r4, [r0,#-1]
MOV r5, r9, LSR #16 @ r5 = q2
STRB r5, [r0,-r1]!
MOV r4, r8, LSR #16 @ r4 = q1
STRB r4, [r0,#-1]
@ Single issue
STRB r9, [r0,-r1]!
@ Single issue
STRB r8, [r0,#-1]
MOV PC,r14
@ @ .size loop_filter_h_core_v6, .-loop_filter_h_core_v6 @ ENDP
@ This uses the same strategy as the MMXEXT version for x86, except that UHADD8
@ computes (a+b>>1) instead of (a+b+1>>1) like PAVGB.
@ This works just as well, with the following procedure for computing the
@ filter value, f:
@ u = ~UHADD8(p1,~p2);
@ v = UHADD8(~p1,p2);
@ m = v-u;
@ a = m^UHADD8(m^p0,m^~p3);
@ f = UHADD8(UHADD8(a,u1),v1);
@ where f = 127+R, with R in [-127,128] defined as in the spec.
@ This is exactly the same amount of arithmetic as the version that uses PAVGB
@ as the basic operator.
@ It executes about 2/3 the number of instructions of David Conrad's approach,
@ but requires more code, because it does all eight columns at once, instead
@ of four at a time.
@ .type loop_filter_v_v6, %function; loop_filter_v_v6: @ PROC
loop_filter_v_v6:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int _ll
@ preserves r0-r11
STMFD r13!,{r4-r11,r14}
LDRD r6, r7, [r0, -r1]! @ r7, r6 = <p5|p1>
LDRD r4, r5, [r0, -r1] @ r5, r4 = <p4|p0>
LDRD r8, r9, [r0, r1]! @ r9, r8 = <p6|p2>
MVN r14,r6 @ r14= ~p1
LDRD r10,r11,[r0, r1] @ r11,r10= <p7|p3>
@ Filter the first four columns.
MVN r12,r8 @ r12= ~p2
UHADD8 r14,r14,r8 @ r14= v1=~p1+p2>>1
UHADD8 r12,r12,r6 @ r12= p1+~p2>>1
MVN r10, r10 @ r10=~p3
MVN r12,r12 @ r12= u1=~p1+p2+1>>1
SSUB8 r14,r14,r12 @ r14= m1=v1-u1
@ Single issue
EOR r4, r4, r14 @ r4 = m1^p0
EOR r10,r10,r14 @ r10= m1^~p3
UHADD8 r4, r4, r10 @ r4 = (m1^p0)+(m1^~p3)>>1
@ Single issue
EOR r4, r4, r14 @ r4 = a1=m1^((m1^p0)+(m1^~p3)>>1)
SADD8 r14,r14,r12 @ r14= v1=m1+u1
UHADD8 r4, r4, r12 @ r4 = a1+u1>>1
MVN r12,r9 @ r12= ~p6
UHADD8 r4, r4, r14 @ r4 = f1=(a1+u1>>1)+v1>>1
@ Filter the second four columns.
MVN r14,r7 @ r14= ~p5
UHADD8 r12,r12,r7 @ r12= p5+~p6>>1
UHADD8 r14,r14,r9 @ r14= v2=~p5+p6>>1
MVN r12,r12 @ r12= u2=~p5+p6+1>>1
MVN r11,r11 @ r11=~p7
SSUB8 r10,r14,r12 @ r10= m2=v2-u2
@ Single issue
EOR r5, r5, r10 @ r5 = m2^p4
EOR r11,r11,r10 @ r11= m2^~p7
UHADD8 r5, r5, r11 @ r5 = (m2^p4)+(m2^~p7)>>1
@ Single issue
EOR r5, r5, r10 @ r5 = a2=m2^((m2^p4)+(m2^~p7)>>1)
@ Single issue
UHADD8 r5, r5, r12 @ r5 = a2+u2>>1
MOV r12, #0x7F7F @ r12 = {127}x4
MOVT r12, #0x7F7F @ r12 = {127}x4
UHADD8 r5, r5, r14 @ r5 = f2=(a2+u2>>1)+v2>>1
@ Now split f[i] by sign.
@ There's no min or max instruction.
@ We could use SSUB8 and SEL, but this is just as many instructions and
@ dual issues more (for v7 without NEON).
UQSUB8 r10,r4, r12 @ r10= R_i>0?R_i:0
UQSUB8 r4, r12,r4 @ r4 = R_i<0?-R_i:0
UQADD8 r11,r10,r2 @ r11= 255-max(2*L-abs(R_i<0),0)
UQADD8 r14,r4, r2 @ r14= 255-max(2*L-abs(R_i>0),0)
UQADD8 r10,r10,r11
UQADD8 r4, r4, r14
UQSUB8 r10,r10,r11 @ r10= min(abs(R_i<0),max(2*L-abs(R_i<0),0))
UQSUB8 r4, r4, r14 @ r4 = min(abs(R_i>0),max(2*L-abs(R_i>0),0))
UQSUB8 r11,r5, r12 @ r11= R_i>0?R_i:0
UQADD8 r6, r6, r10
UQSUB8 r8, r8, r10
UQSUB8 r5, r12,r5 @ r5 = R_i<0?-R_i:0
UQSUB8 r6, r6, r4 @ r6 = p1+lflim(R_i,L)
UQADD8 r8, r8, r4 @ r8 = p2-lflim(R_i,L)
UQADD8 r10,r11,r2 @ r10= 255-max(2*L-abs(R_i<0),0)
UQADD8 r14,r5, r2 @ r14= 255-max(2*L-abs(R_i>0),0)
UQADD8 r11,r11,r10
UQADD8 r5, r5, r14
UQSUB8 r11,r11,r10 @ r11= min(abs(R_i<0),max(2*L-abs(R_i<0),0))
UQSUB8 r5, r5, r14 @ r5 = min(abs(R_i>0),max(2*L-abs(R_i>0),0))
UQADD8 r7, r7, r11
UQSUB8 r9, r9, r11
UQSUB8 r7, r7, r5 @ r7 = p5+lflim(R_i,L)
STRD r6, r7, [r0, -r1] @ [p5:p1] = [r7: r6]
UQADD8 r9, r9, r5 @ r9 = p6-lflim(R_i,L)
STRD r8, r9, [r0] @ [p6:p2] = [r9: r8]
LDMFD r13!,{r4-r11,PC}
@ @ .size loop_filter_v_v6, .-loop_filter_v_v6 @ ENDP
@ .type oc_loop_filter_frag_rows_v6, %function; oc_loop_filter_frag_rows_v6: @ PROC
oc_loop_filter_frag_rows_v6:
@ r0 = _ref_frame_data
@ r1 = _ystride
@ r2 = _bv
@ r3 = _frags
@ r4 = _fragi0
@ r5 = _fragi0_end
@ r6 = _fragi_top
@ r7 = _fragi_bot
@ r8 = _frag_buf_offs
@ r9 = _nhfrags
MOV r12,r13
STMFD r13!,{r0,r4-r11,r14}
LDMFD r12,{r4-r9}
LDR r2, [r2] @ ll = *(int *)_bv
CMP r4, r5 @ if(_fragi0>=_fragi0_end)
BGE oslffri_v6_end @ bail
SUBS r9, r9, #1 @ r9 = _nhfrags-1 if (r9<=0)
BLE oslffri_v6_end @ bail
ADD r3, r3, r4, LSL #2 @ r3 = &_frags[fragi]
ADD r8, r8, r4, LSL #2 @ r8 = &_frag_buf_offs[fragi]
SUB r7, r7, r9 @ _fragi_bot -= _nhfrags;
oslffri_v6_lp1:
MOV r10,r4 @ r10= fragi = _fragi0
ADD r11,r4, r9 @ r11= fragi_end-1=fragi+_nhfrags-1
oslffri_v6_lp2:
LDR r14,[r3], #4 @ r14= _frags[fragi] _frags++
LDR r0, [r13] @ r0 = _ref_frame_data
LDR r12,[r8], #4 @ r12= _frag_buf_offs[fragi] _frag_buf_offs++
TST r14,#OC_FRAG_CODED_FLAG
BEQ oslffri_v6_uncoded
CMP r10,r4 @ if (fragi>_fragi0)
ADD r0, r0, r12 @ r0 = _ref_frame_data + _frag_buf_offs[fragi]
BLGT loop_filter_h_v6
CMP r4, r6 @ if (fragi0>_fragi_top)
BLGT loop_filter_v_v6
CMP r10,r11 @ if(fragi+1<fragi_end)===(fragi<fragi_end-1)
LDRLT r12,[r3] @ r12 = _frags[fragi+1]
ADD r0, r0, #8
ADD r10,r10,#1 @ r10 = fragi+1;
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG @ && _frags[fragi+1].coded==0
BLLT loop_filter_h_v6
CMP r10,r7 @ if (fragi<_fragi_bot)
LDRLT r12,[r3, r9, LSL #2] @ r12 = _frags[fragi+1+_nhfrags-1]
SUB r0, r0, #8
ADD r0, r0, r1, LSL #3
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG
BLLT loop_filter_v_v6
CMP r10,r11 @ while(fragi<=fragi_end-1)
BLE oslffri_v6_lp2
MOV r4, r10 @ r4 = fragi0 += nhfrags
CMP r4, r5
BLT oslffri_v6_lp1
oslffri_v6_end:
LDMFD r13!,{r0,r4-r11,PC}
oslffri_v6_uncoded:
ADD r10,r10,#1
CMP r10,r11
BLE oslffri_v6_lp2
MOV r4, r10 @ r4 = fragi0 += nhfrags
CMP r4, r5
BLT oslffri_v6_lp1
LDMFD r13!,{r0,r4-r11,PC}
@ @ .size oc_loop_filter_frag_rows_v6, .-oc_loop_filter_frag_rows_v6 @ ENDP
.endif
.if OC_ARM_ASM_NEON
.global oc_loop_filter_init_neon
.global oc_loop_filter_frag_rows_neon
@ .type oc_loop_filter_init_neon, %function; oc_loop_filter_init_neon: @ PROC
oc_loop_filter_init_neon:
@ r0 = _bv
@ r1 = _flimit (=L from the spec)
MOV r1, r1, LSL #1 @ r1 = 2*L
VDUP.S16 Q15, r1 @ Q15= 2L in U16s
VST1.64 {D30,D31}, [r0,:128]
MOV PC,r14
@ @ .size oc_loop_filter_init_neon, .-oc_loop_filter_init_neon @ ENDP
@ .type loop_filter_h_neon, %function; loop_filter_h_neon: @ PROC
loop_filter_h_neon:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
@ We assume Q15= 2*L in U16s
@ My best guesses at cycle counts (and latency)--vvv
SUB r12,r0, #2
@ Doing a 2-element structure load saves doing two VTRN's below, at the
@ cost of using two more slower single-lane loads vs. the faster
@ all-lane loads.
@ It's less code this way, though, and benches a hair faster, but it
@ leaves D2 and D4 swapped.
VLD2.16 {D0[],D2[]}, [r12], r1 @ D0 = ____________1100 2,1
@ D2 = ____________3322
VLD2.16 {D4[],D6[]}, [r12], r1 @ D4 = ____________5544 2,1
@ D6 = ____________7766
VLD2.16 {D0[1],D2[1]},[r12], r1 @ D0 = ________99881100 3,1
@ D2 = ________BBAA3322
VLD2.16 {D4[1],D6[1]},[r12], r1 @ D4 = ________DDCC5544 3,1
@ D6 = ________FFEE7766
VLD2.16 {D0[2],D2[2]},[r12], r1 @ D0 = ____GGHH99881100 3,1
@ D2 = ____JJIIBBAA3322
VLD2.16 {D4[2],D6[2]},[r12], r1 @ D4 = ____KKLLDDCC5544 3,1
@ D6 = ____NNMMFFEE7766
VLD2.16 {D0[3],D2[3]},[r12], r1 @ D0 = PPOOGGHH99881100 3,1
@ D2 = RRQQJJIIBBAA3322
VLD2.16 {D4[3],D6[3]},[r12], r1 @ D4 = TTSSKKLLDDCC5544 3,1
@ D6 = VVUUNNMMFFEE7766
VTRN.8 D0, D4 @ D0 = SSOOKKGGCC884400 D4 = TTPPLLHHDD995511 1,1
VTRN.8 D2, D6 @ D2 = UUQQMMIIEEAA6622 D6 = VVRRNNJJFFBB7733 1,1
VSUBL.U8 Q0, D0, D6 @ Q0 = 00 - 33 in S16s 1,3
VSUBL.U8 Q8, D2, D4 @ Q8 = 22 - 11 in S16s 1,3
ADD r12,r0, #8
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12]
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12,r1]
VADD.S16 Q0, Q0, Q8 @ Q0 = [0-3]+3*[2-1] 1,3
PLD [r12,r1, LSL #1]
VRSHR.S16 Q0, Q0, #3 @ Q0 = f = ([0-3]+3*[2-1]+4)>>3 1,4
ADD r12,r12,r1, LSL #2
@ We want to do
@ f = CLAMP(MIN(-2L-f,0), f, MAX(2L-f,0))
@ = ((f >= 0) ? MIN( f ,MAX(2L- f ,0)) : MAX( f , MIN(-2L- f ,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) : MAX(-|f|, MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|,-MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|, MAX( 2L-|f|,0)))
@ So we've reduced the left and right hand terms to be the same, except
@ for a negation.
@ Stall x3
VABS.S16 Q9, Q0 @ Q9 = |f| in U16s 1,4
PLD [r12,-r1]
VSHR.S16 Q0, Q0, #15 @ Q0 = -1 or 0 according to sign 1,3
PLD [r12]
VQSUB.U16 Q10,Q15,Q9 @ Q10= MAX(2L-|f|,0) in U16s 1,4
PLD [r12,r1]
VMOVL.U8 Q1, D2 @ Q2 = __UU__QQ__MM__II__EE__AA__66__22 2,3
PLD [r12,r1,LSL #1]
VMIN.U16 Q9, Q10,Q9 @ Q9 = MIN(|f|,MAX(2L-|f|)) 1,4
ADD r12,r12,r1, LSL #2
@ Now we need to correct for the sign of f.
@ For negative elements of Q0, we want to subtract the appropriate
@ element of Q9. For positive elements we want to add them. No NEON
@ instruction exists to do this, so we need to negate the negative
@ elements, and we can then just add them. a-b = a-(1+!b) = a-1+!b
VADD.S16 Q9, Q9, Q0 @ 1,3
PLD [r12,-r1]
VEOR.S16 Q9, Q9, Q0 @ Q9 = real value of f 1,3
@ Bah. No VRSBW.U8
@ Stall (just 1 as Q9 not needed to second pipeline stage. I think.)
VADDW.U8 Q2, Q9, D4 @ Q1 = xxTTxxPPxxLLxxHHxxDDxx99xx55xx11 1,3
VSUB.S16 Q1, Q1, Q9 @ Q2 = xxUUxxQQxxMMxxIIxxEExxAAxx66xx22 1,3
VQMOVUN.S16 D4, Q2 @ D4 = TTPPLLHHDD995511 1,1
VQMOVUN.S16 D2, Q1 @ D2 = UUQQMMIIEEAA6622 1,1
SUB r12,r0, #1
VTRN.8 D4, D2 @ D4 = QQPPIIHHAA992211 D2 = MMLLEEDD6655 1,1
VST1.16 {D4[0]}, [r12], r1
VST1.16 {D2[0]}, [r12], r1
VST1.16 {D4[1]}, [r12], r1
VST1.16 {D2[1]}, [r12], r1
VST1.16 {D4[2]}, [r12], r1
VST1.16 {D2[2]}, [r12], r1
VST1.16 {D4[3]}, [r12], r1
VST1.16 {D2[3]}, [r12], r1
MOV PC,r14
@ @ .size loop_filter_h_neon, .-loop_filter_h_neon @ ENDP
@ .type loop_filter_v_neon, %function; loop_filter_v_neon: @ PROC
loop_filter_v_neon:
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
@ We assume Q15= 2*L in U16s
@ My best guesses at cycle counts (and latency)--vvv
SUB r12,r0, r1, LSL #1
VLD1.64 {D0}, [r12,:64], r1 @ D0 = SSOOKKGGCC884400 2,1
VLD1.64 {D2}, [r12,:64], r1 @ D2 = TTPPLLHHDD995511 2,1
VLD1.64 {D4}, [r12,:64], r1 @ D4 = UUQQMMIIEEAA6622 2,1
VLD1.64 {D6}, [r12,:64] @ D6 = VVRRNNJJFFBB7733 2,1
VSUBL.U8 Q8, D4, D2 @ Q8 = 22 - 11 in S16s 1,3
VSUBL.U8 Q0, D0, D6 @ Q0 = 00 - 33 in S16s 1,3
ADD r12, #8
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12]
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12,r1]
VADD.S16 Q0, Q0, Q8 @ Q0 = [0-3]+3*[2-1] 1,3
SUB r12, r0, r1
VRSHR.S16 Q0, Q0, #3 @ Q0 = f = ([0-3]+3*[2-1]+4)>>3 1,4
@ We want to do
@ f = CLAMP(MIN(-2L-f,0), f, MAX(2L-f,0))
@ = ((f >= 0) ? MIN( f ,MAX(2L- f ,0)) : MAX( f , MIN(-2L- f ,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) : MAX(-|f|, MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|,-MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|, MAX( 2L-|f|,0)))
@ So we've reduced the left and right hand terms to be the same, except
@ for a negation.
@ Stall x3
VABS.S16 Q9, Q0 @ Q9 = |f| in U16s 1,4
VSHR.S16 Q0, Q0, #15 @ Q0 = -1 or 0 according to sign 1,3
@ Stall x2
VQSUB.U16 Q10,Q15,Q9 @ Q10= MAX(2L-|f|,0) in U16s 1,4
VMOVL.U8 Q2, D4 @ Q2 = __UU__QQ__MM__II__EE__AA__66__22 2,3
@ Stall x2
VMIN.U16 Q9, Q10,Q9 @ Q9 = MIN(|f|,MAX(2L-|f|)) 1,4
@ Now we need to correct for the sign of f.
@ For negative elements of Q0, we want to subtract the appropriate
@ element of Q9. For positive elements we want to add them. No NEON
@ instruction exists to do this, so we need to negate the negative
@ elements, and we can then just add them. a-b = a-(1+!b) = a-1+!b
@ Stall x3
VADD.S16 Q9, Q9, Q0 @ 1,3
@ Stall x2
VEOR.S16 Q9, Q9, Q0 @ Q9 = real value of f 1,3
@ Bah. No VRSBW.U8
@ Stall (just 1 as Q9 not needed to second pipeline stage. I think.)
VADDW.U8 Q1, Q9, D2 @ Q1 = xxTTxxPPxxLLxxHHxxDDxx99xx55xx11 1,3
VSUB.S16 Q2, Q2, Q9 @ Q2 = xxUUxxQQxxMMxxIIxxEExxAAxx66xx22 1,3
VQMOVUN.S16 D2, Q1 @ D2 = TTPPLLHHDD995511 1,1
VQMOVUN.S16 D4, Q2 @ D4 = UUQQMMIIEEAA6622 1,1
VST1.64 {D2}, [r12,:64], r1
VST1.64 {D4}, [r12,:64], r1
MOV PC,r14
@ @ .size loop_filter_v_neon, .-loop_filter_v_neon @ ENDP
@ .type oc_loop_filter_frag_rows_neon, %function; oc_loop_filter_frag_rows_neon: @ PROC
oc_loop_filter_frag_rows_neon:
@ r0 = _ref_frame_data
@ r1 = _ystride
@ r2 = _bv
@ r3 = _frags
@ r4 = _fragi0
@ r5 = _fragi0_end
@ r6 = _fragi_top
@ r7 = _fragi_bot
@ r8 = _frag_buf_offs
@ r9 = _nhfrags
MOV r12,r13
STMFD r13!,{r0,r4-r11,r14}
LDMFD r12,{r4-r9}
CMP r4, r5 @ if(_fragi0>=_fragi0_end)
BGE oslffri_neon_end @ bail
SUBS r9, r9, #1 @ r9 = _nhfrags-1 if (r9<=0)
BLE oslffri_neon_end @ bail
VLD1.64 {D30,D31}, [r2,:128] @ Q15= 2L in U16s
ADD r3, r3, r4, LSL #2 @ r3 = &_frags[fragi]
ADD r8, r8, r4, LSL #2 @ r8 = &_frag_buf_offs[fragi]
SUB r7, r7, r9 @ _fragi_bot -= _nhfrags;
oslffri_neon_lp1:
MOV r10,r4 @ r10= fragi = _fragi0
ADD r11,r4, r9 @ r11= fragi_end-1=fragi+_nhfrags-1
oslffri_neon_lp2:
LDR r14,[r3], #4 @ r14= _frags[fragi] _frags++
LDR r0, [r13] @ r0 = _ref_frame_data
LDR r12,[r8], #4 @ r12= _frag_buf_offs[fragi] _frag_buf_offs++
TST r14,#OC_FRAG_CODED_FLAG
BEQ oslffri_neon_uncoded
CMP r10,r4 @ if (fragi>_fragi0)
ADD r0, r0, r12 @ r0 = _ref_frame_data + _frag_buf_offs[fragi]
BLGT loop_filter_h_neon
CMP r4, r6 @ if (_fragi0>_fragi_top)
BLGT loop_filter_v_neon
CMP r10,r11 @ if(fragi+1<fragi_end)===(fragi<fragi_end-1)
LDRLT r12,[r3] @ r12 = _frags[fragi+1]
ADD r0, r0, #8
ADD r10,r10,#1 @ r10 = fragi+1;
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG @ && _frags[fragi+1].coded==0
BLLT loop_filter_h_neon
CMP r10,r7 @ if (fragi<_fragi_bot)
LDRLT r12,[r3, r9, LSL #2] @ r12 = _frags[fragi+1+_nhfrags-1]
SUB r0, r0, #8
ADD r0, r0, r1, LSL #3
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG
BLLT loop_filter_v_neon
CMP r10,r11 @ while(fragi<=fragi_end-1)
BLE oslffri_neon_lp2
MOV r4, r10 @ r4 = _fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_neon_lp1
oslffri_neon_end:
LDMFD r13!,{r0,r4-r11,PC}
oslffri_neon_uncoded:
ADD r10,r10,#1
CMP r10,r11
BLE oslffri_neon_lp2
MOV r4, r10 @ r4 = _fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_neon_lp1
LDMFD r13!,{r0,r4-r11,PC}
@ @ .size oc_loop_filter_frag_rows_neon, .-oc_loop_filter_frag_rows_neon @ ENDP
.endif
@ END
@ .section .note.GNU-stack,"",%progbits
#endif
| blloyd75/theoraplayer | theora/lib/arm_llvm_android/armloop.asm | Assembly | bsd-3-clause | 24,875 |
;*****************************************************************************
;* x86-optimized Float DSP functions
;*
;* Copyright 2006 Loren Merritt
;*
;* This file is part of FFmpeg.
;*
;* FFmpeg is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* FFmpeg is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with FFmpeg; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
%include "x86inc.asm"
%include "x86util.asm"
SECTION .text
;-----------------------------------------------------------------------------
; void vector_fmul(float *dst, const float *src0, const float *src1, int len)
;-----------------------------------------------------------------------------
%macro VECTOR_FMUL 0
cglobal vector_fmul, 4,4,2, dst, src0, src1, len
lea lenq, [lend*4 - 2*mmsize]
ALIGN 16
.loop:
mova m0, [src0q + lenq]
mova m1, [src0q + lenq + mmsize]
mulps m0, m0, [src1q + lenq]
mulps m1, m1, [src1q + lenq + mmsize]
mova [dstq + lenq], m0
mova [dstq + lenq + mmsize], m1
sub lenq, 2*mmsize
jge .loop
REP_RET
%endmacro
INIT_XMM sse
VECTOR_FMUL
%if HAVE_AVX_EXTERNAL
INIT_YMM avx
VECTOR_FMUL
%endif
;------------------------------------------------------------------------------
; void ff_vector_fmac_scalar(float *dst, const float *src, float mul, int len)
;------------------------------------------------------------------------------
%macro VECTOR_FMAC_SCALAR 0
%if UNIX64
cglobal vector_fmac_scalar, 3,3,3, dst, src, len
%else
cglobal vector_fmac_scalar, 4,4,3, dst, src, mul, len
%endif
%if ARCH_X86_32
VBROADCASTSS m0, mulm
%else
%if WIN64
mova xmm0, xmm2
%endif
shufps xmm0, xmm0, 0
%if cpuflag(avx)
vinsertf128 m0, m0, xmm0, 1
%endif
%endif
lea lenq, [lend*4-2*mmsize]
.loop:
mulps m1, m0, [srcq+lenq ]
mulps m2, m0, [srcq+lenq+mmsize]
addps m1, m1, [dstq+lenq ]
addps m2, m2, [dstq+lenq+mmsize]
mova [dstq+lenq ], m1
mova [dstq+lenq+mmsize], m2
sub lenq, 2*mmsize
jge .loop
REP_RET
%endmacro
INIT_XMM sse
VECTOR_FMAC_SCALAR
%if HAVE_AVX_EXTERNAL
INIT_YMM avx
VECTOR_FMAC_SCALAR
%endif
| leighpauls/k2cro4 | third_party/ffmpeg/libavutil/x86/float_dsp.asm | Assembly | bsd-3-clause | 2,805 |
PORTB EQU $1004
PORTC EQU $1003
DDRC EQU $1007
ADCTL EQU $1030
ADR2 EQU $1032
OPTION EQU $1039
TCNT EQU $0E
TOC2 EQU $18
TMSK2 EQU $24
TFLG1 EQU $23
PRTB EQU $4
PRTC EQU $3
TEMPS EQU $B600
SHOW EQU $B655
UPDATE EQU $B6AC
DELAY EQU $B6D5
GETKEY EQU $B6E4
BOUNCE EQU $B700
SAMPLES EQU 16
ORG $0
LDS #$37
SHIFTH RMB 1
SHIFTL RMB 1 ;initialize number of shifts at -1
INPUT RMB 1
BIN_KEY RMB 1
TABLE FCB %01110111 ;0
FCB %01111011 ;1
FCB %01111101 ;2
FCB %01111110 ;3
FCB %10110111 ;4
FCB %10111011 ;5
FCB %10111101 ;6
FCB %10111110 ;7
FCB %11010111 ;8
FCB %11011011 ;9
FCB %11011101 ;A
FCB %11011110 ;B
FCB %11100111 ;C
FCB %11101011 ;D
FCB %11101101 ;E
FCB %11101110 ;F
ORG $100
;TEMPS
CLR SHIFTH
CLR SHIFTL
DEC SHIFTL
LDAA #SAMPLES
COUNTER INC SHIFTL ;keep shifting the number of samples right (dividing by 2)
LSRA ;count how many times you can do that and still get positive integer
BNE COUNTER
LDAA #$90 ; Turn on the ADC
STAA OPTION
LDY #SAMPLES ; Number of samples
LDX #0
SAMPLE LDAA #1
STAA ADCTL ; Channel Selection
WAIT TST ADCTL ; \ Wait for EOC
BPL WAIT
LDAB ADR2 ; Get Converted Result
ABX ;Add Temp to X
DEY
BNE SAMPLE
XGDX ; exchange D and X
LDY SHIFTH
BEQ DONE2
SHIFT LSRD ; shift D
DEY ; decrease number of remaining shifts
BNE SHIFT ; shift again if number of remaining shifts is above zero
; scale to display actual temperature
; P = 31
; S = 6
DONE2 LDAA #31
MUL
LSRD
LSRD
LSRD
LSRD
LSRD
LSRD
; B is temperature
LDAA #0
; convert to BCD
LDX #10
IDIV
XGDX
LSLD
LSLD
LSLD
LSLD
ABX
XGDX
COMB
STAB PORTB ; display average
RTS
;SHOW
MAIN LDX #$1000
CLR TFLG1,X
OLOOP LDX #PATS
TSY
LDAB 2,Y
ASLB
ABX
LDY 0,X
LDX #$1000
LDAA 0,Y
STAA CNT
STY PATCNT
ILOOP LDY PATCNT
INY
STY PATCNT
LDAA 0,Y
COMA
STAA PRTB,X
LDY #RATES
TSX
LDAB 3,X
LDX #$1000
LSLB
ABY
LDY 0,Y
LP2 LDD TCNT,X
ADDD #$00FF
STD TOC2,X
LP1 BRCLR TFLG1,X,$40,LP1
BCLR TFLG1,X,$BF
DEY
BNE LP2
DEC CNT
BNE ILOOP
RTS
ORG $1AC
RATES FDB 1000,750,500,5
PAT0 FCB 2
FCB %00001111
FCB %11110000
PAT1 FCB 8
FCB %10000000
FCB %01000000
FCB %00100000
FCB %00010000
FCB %00001000
FCB %00000100
FCB %00000010
FCB %00000001
PAT2 FCB 8
FCB %00000001
FCB %00000010
FCB %00000100
FCB %00001000
FCB %00010000
FCB %00100000
FCB %01000000
FCB %10000000
PAT3 FCB 14
FCB %10000000
FCB %01000000
FCB %00100000
FCB %00010000
FCB %00001000
FCB %00000100
FCB %00000010
FCB %00000001
FCB %00000010
FCB %00000100
FCB %00001000
FCB %00010000
FCB %00100000
FCB %01000000
PAT4 FCB 2
FCB %10101010
FCB %01010101
PAT5 FCB 4
FCB %10000001
FCB %01000010
FCB %00100100
FCB %00011000
PAT6 FCB 4
FCB %00011000
FCB %00100100
FCB %01000010
FCB %10000001
PAT7 FCB 6
FCB %10000001
FCB %01000010
FCB %00100100
FCB %00011000
FCB %00100100
FCB %01000010
PATS FDB PAT0,PAT1,PAT2,PAT3,PAT4,PAT5,PAT6,PAT7
PATCNT RMB 2
CNT RMB 1
END
| raudabaugh/68hc11-lightshow | subroutines1.asm | Assembly | mit | 4,990 |
default rel
%define XMMWORD
%define YMMWORD
%define ZMMWORD
section .text code align=64
EXTERN OPENSSL_ia32cap_P
global aesni_cbc_sha256_enc
ALIGN 16
aesni_cbc_sha256_enc:
lea r11,[OPENSSL_ia32cap_P]
mov eax,1
cmp rcx,0
je NEAR $L$probe
mov eax,DWORD[r11]
mov r10,QWORD[4+r11]
bt r10,61
jc NEAR aesni_cbc_sha256_enc_shaext
mov r11,r10
shr r11,32
test r10d,2048
jnz NEAR aesni_cbc_sha256_enc_xop
and r11d,296
cmp r11d,296
je NEAR aesni_cbc_sha256_enc_avx2
and r10d,268435456
jnz NEAR aesni_cbc_sha256_enc_avx
ud2
xor eax,eax
cmp rcx,0
je NEAR $L$probe
ud2
$L$probe:
DB 0F3h,0C3h ;repret
ALIGN 64
K256:
DD 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
DD 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
DD 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
DD 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
DD 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
DD 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
DD 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
DD 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
DD 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
DD 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
DD 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
DD 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
DD 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
DD 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
DD 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
DD 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
DD 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
DD 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
DD 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
DD 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
DD 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
DD 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
DD 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
DD 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
DD 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
DD 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
DD 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
DD 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
DD 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
DD 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
DD 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
DD 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
DD 0x00010203,0x04050607,0x08090a0b,0x0c0d0e0f
DD 0x00010203,0x04050607,0x08090a0b,0x0c0d0e0f
DD 0,0,0,0,0,0,0,0,-1,-1,-1,-1
DD 0,0,0,0,0,0,0,0
DB 65,69,83,78,73,45,67,66,67,43,83,72,65,50,53,54
DB 32,115,116,105,116,99,104,32,102,111,114,32,120,56,54,95
DB 54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98
DB 121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108
DB 46,111,114,103,62,0
ALIGN 64
ALIGN 64
aesni_cbc_sha256_enc_xop:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_aesni_cbc_sha256_enc_xop:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD[40+rsp]
mov r9,QWORD[48+rsp]
$L$xop_shortcut:
mov r10,QWORD[56+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
mov r11,rsp
sub rsp,288
and rsp,-64
shl rdx,6
sub rsi,rdi
sub r10,rdi
add rdx,rdi
mov QWORD[((64+8))+rsp],rsi
mov QWORD[((64+16))+rsp],rdx
mov QWORD[((64+32))+rsp],r8
mov QWORD[((64+40))+rsp],r9
mov QWORD[((64+48))+rsp],r10
mov QWORD[((64+56))+rsp],r11
movaps XMMWORD[128+rsp],xmm6
movaps XMMWORD[144+rsp],xmm7
movaps XMMWORD[160+rsp],xmm8
movaps XMMWORD[176+rsp],xmm9
movaps XMMWORD[192+rsp],xmm10
movaps XMMWORD[208+rsp],xmm11
movaps XMMWORD[224+rsp],xmm12
movaps XMMWORD[240+rsp],xmm13
movaps XMMWORD[256+rsp],xmm14
movaps XMMWORD[272+rsp],xmm15
$L$prologue_xop:
vzeroall
mov r12,rdi
lea rdi,[128+rcx]
lea r13,[((K256+544))]
mov r14d,DWORD[((240-128))+rdi]
mov r15,r9
mov rsi,r10
vmovdqu xmm8,XMMWORD[r8]
sub r14,9
mov eax,DWORD[r15]
mov ebx,DWORD[4+r15]
mov ecx,DWORD[8+r15]
mov edx,DWORD[12+r15]
mov r8d,DWORD[16+r15]
mov r9d,DWORD[20+r15]
mov r10d,DWORD[24+r15]
mov r11d,DWORD[28+r15]
vmovdqa xmm14,XMMWORD[r14*8+r13]
vmovdqa xmm13,XMMWORD[16+r14*8+r13]
vmovdqa xmm12,XMMWORD[32+r14*8+r13]
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
jmp NEAR $L$loop_xop
ALIGN 16
$L$loop_xop:
vmovdqa xmm7,XMMWORD[((K256+512))]
vmovdqu xmm0,XMMWORD[r12*1+rsi]
vmovdqu xmm1,XMMWORD[16+r12*1+rsi]
vmovdqu xmm2,XMMWORD[32+r12*1+rsi]
vmovdqu xmm3,XMMWORD[48+r12*1+rsi]
vpshufb xmm0,xmm0,xmm7
lea rbp,[K256]
vpshufb xmm1,xmm1,xmm7
vpshufb xmm2,xmm2,xmm7
vpaddd xmm4,xmm0,XMMWORD[rbp]
vpshufb xmm3,xmm3,xmm7
vpaddd xmm5,xmm1,XMMWORD[32+rbp]
vpaddd xmm6,xmm2,XMMWORD[64+rbp]
vpaddd xmm7,xmm3,XMMWORD[96+rbp]
vmovdqa XMMWORD[rsp],xmm4
mov r14d,eax
vmovdqa XMMWORD[16+rsp],xmm5
mov esi,ebx
vmovdqa XMMWORD[32+rsp],xmm6
xor esi,ecx
vmovdqa XMMWORD[48+rsp],xmm7
mov r13d,r8d
jmp NEAR $L$xop_00_47
ALIGN 16
$L$xop_00_47:
sub rbp,-16*2*4
vmovdqu xmm9,XMMWORD[r12]
mov QWORD[((64+0))+rsp],r12
vpalignr xmm4,xmm1,xmm0,4
ror r13d,14
mov eax,r14d
vpalignr xmm7,xmm3,xmm2,4
mov r12d,r9d
xor r13d,r8d
DB 143,232,120,194,236,14
ror r14d,9
xor r12d,r10d
vpsrld xmm4,xmm4,3
ror r13d,5
xor r14d,eax
vpaddd xmm0,xmm0,xmm7
and r12d,r8d
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r13d,r8d
add r11d,DWORD[rsp]
mov r15d,eax
DB 143,232,120,194,245,11
ror r14d,11
xor r12d,r10d
vpxor xmm4,xmm4,xmm5
xor r15d,ebx
ror r13d,6
add r11d,r12d
and esi,r15d
DB 143,232,120,194,251,13
xor r14d,eax
add r11d,r13d
vpxor xmm4,xmm4,xmm6
xor esi,ebx
add edx,r11d
vpsrld xmm6,xmm3,10
ror r14d,2
add r11d,esi
vpaddd xmm0,xmm0,xmm4
mov r13d,edx
add r14d,r11d
DB 143,232,120,194,239,2
ror r13d,14
mov r11d,r14d
vpxor xmm7,xmm7,xmm6
mov r12d,r8d
xor r13d,edx
ror r14d,9
xor r12d,r9d
vpxor xmm7,xmm7,xmm5
ror r13d,5
xor r14d,r11d
and r12d,edx
vpxor xmm9,xmm9,xmm8
xor r13d,edx
vpsrldq xmm7,xmm7,8
add r10d,DWORD[4+rsp]
mov esi,r11d
ror r14d,11
xor r12d,r9d
vpaddd xmm0,xmm0,xmm7
xor esi,eax
ror r13d,6
add r10d,r12d
and r15d,esi
DB 143,232,120,194,248,13
xor r14d,r11d
add r10d,r13d
vpsrld xmm6,xmm0,10
xor r15d,eax
add ecx,r10d
DB 143,232,120,194,239,2
ror r14d,2
add r10d,r15d
vpxor xmm7,xmm7,xmm6
mov r13d,ecx
add r14d,r10d
ror r13d,14
mov r10d,r14d
vpxor xmm7,xmm7,xmm5
mov r12d,edx
xor r13d,ecx
ror r14d,9
xor r12d,r8d
vpslldq xmm7,xmm7,8
ror r13d,5
xor r14d,r10d
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r13d,ecx
vpaddd xmm0,xmm0,xmm7
add r9d,DWORD[8+rsp]
mov r15d,r10d
ror r14d,11
xor r12d,r8d
vpaddd xmm6,xmm0,XMMWORD[rbp]
xor r15d,r11d
ror r13d,6
add r9d,r12d
and esi,r15d
xor r14d,r10d
add r9d,r13d
xor esi,r11d
add ebx,r9d
ror r14d,2
add r9d,esi
mov r13d,ebx
add r14d,r9d
ror r13d,14
mov r9d,r14d
mov r12d,ecx
xor r13d,ebx
ror r14d,9
xor r12d,edx
ror r13d,5
xor r14d,r9d
and r12d,ebx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r13d,ebx
add r8d,DWORD[12+rsp]
mov esi,r9d
ror r14d,11
xor r12d,edx
xor esi,r10d
ror r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
ror r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
vmovdqa XMMWORD[rsp],xmm6
vpalignr xmm4,xmm2,xmm1,4
ror r13d,14
mov r8d,r14d
vpalignr xmm7,xmm0,xmm3,4
mov r12d,ebx
xor r13d,eax
DB 143,232,120,194,236,14
ror r14d,9
xor r12d,ecx
vpsrld xmm4,xmm4,3
ror r13d,5
xor r14d,r8d
vpaddd xmm1,xmm1,xmm7
and r12d,eax
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r13d,eax
add edx,DWORD[16+rsp]
mov r15d,r8d
DB 143,232,120,194,245,11
ror r14d,11
xor r12d,ecx
vpxor xmm4,xmm4,xmm5
xor r15d,r9d
ror r13d,6
add edx,r12d
and esi,r15d
DB 143,232,120,194,248,13
xor r14d,r8d
add edx,r13d
vpxor xmm4,xmm4,xmm6
xor esi,r9d
add r11d,edx
vpsrld xmm6,xmm0,10
ror r14d,2
add edx,esi
vpaddd xmm1,xmm1,xmm4
mov r13d,r11d
add r14d,edx
DB 143,232,120,194,239,2
ror r13d,14
mov edx,r14d
vpxor xmm7,xmm7,xmm6
mov r12d,eax
xor r13d,r11d
ror r14d,9
xor r12d,ebx
vpxor xmm7,xmm7,xmm5
ror r13d,5
xor r14d,edx
and r12d,r11d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r13d,r11d
vpsrldq xmm7,xmm7,8
add ecx,DWORD[20+rsp]
mov esi,edx
ror r14d,11
xor r12d,ebx
vpaddd xmm1,xmm1,xmm7
xor esi,r8d
ror r13d,6
add ecx,r12d
and r15d,esi
DB 143,232,120,194,249,13
xor r14d,edx
add ecx,r13d
vpsrld xmm6,xmm1,10
xor r15d,r8d
add r10d,ecx
DB 143,232,120,194,239,2
ror r14d,2
add ecx,r15d
vpxor xmm7,xmm7,xmm6
mov r13d,r10d
add r14d,ecx
ror r13d,14
mov ecx,r14d
vpxor xmm7,xmm7,xmm5
mov r12d,r11d
xor r13d,r10d
ror r14d,9
xor r12d,eax
vpslldq xmm7,xmm7,8
ror r13d,5
xor r14d,ecx
and r12d,r10d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r13d,r10d
vpaddd xmm1,xmm1,xmm7
add ebx,DWORD[24+rsp]
mov r15d,ecx
ror r14d,11
xor r12d,eax
vpaddd xmm6,xmm1,XMMWORD[32+rbp]
xor r15d,edx
ror r13d,6
add ebx,r12d
and esi,r15d
xor r14d,ecx
add ebx,r13d
xor esi,edx
add r9d,ebx
ror r14d,2
add ebx,esi
mov r13d,r9d
add r14d,ebx
ror r13d,14
mov ebx,r14d
mov r12d,r10d
xor r13d,r9d
ror r14d,9
xor r12d,r11d
ror r13d,5
xor r14d,ebx
and r12d,r9d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r13d,r9d
add eax,DWORD[28+rsp]
mov esi,ebx
ror r14d,11
xor r12d,r11d
xor esi,ecx
ror r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
ror r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
vmovdqa XMMWORD[16+rsp],xmm6
vpalignr xmm4,xmm3,xmm2,4
ror r13d,14
mov eax,r14d
vpalignr xmm7,xmm1,xmm0,4
mov r12d,r9d
xor r13d,r8d
DB 143,232,120,194,236,14
ror r14d,9
xor r12d,r10d
vpsrld xmm4,xmm4,3
ror r13d,5
xor r14d,eax
vpaddd xmm2,xmm2,xmm7
and r12d,r8d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r13d,r8d
add r11d,DWORD[32+rsp]
mov r15d,eax
DB 143,232,120,194,245,11
ror r14d,11
xor r12d,r10d
vpxor xmm4,xmm4,xmm5
xor r15d,ebx
ror r13d,6
add r11d,r12d
and esi,r15d
DB 143,232,120,194,249,13
xor r14d,eax
add r11d,r13d
vpxor xmm4,xmm4,xmm6
xor esi,ebx
add edx,r11d
vpsrld xmm6,xmm1,10
ror r14d,2
add r11d,esi
vpaddd xmm2,xmm2,xmm4
mov r13d,edx
add r14d,r11d
DB 143,232,120,194,239,2
ror r13d,14
mov r11d,r14d
vpxor xmm7,xmm7,xmm6
mov r12d,r8d
xor r13d,edx
ror r14d,9
xor r12d,r9d
vpxor xmm7,xmm7,xmm5
ror r13d,5
xor r14d,r11d
and r12d,edx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r13d,edx
vpsrldq xmm7,xmm7,8
add r10d,DWORD[36+rsp]
mov esi,r11d
ror r14d,11
xor r12d,r9d
vpaddd xmm2,xmm2,xmm7
xor esi,eax
ror r13d,6
add r10d,r12d
and r15d,esi
DB 143,232,120,194,250,13
xor r14d,r11d
add r10d,r13d
vpsrld xmm6,xmm2,10
xor r15d,eax
add ecx,r10d
DB 143,232,120,194,239,2
ror r14d,2
add r10d,r15d
vpxor xmm7,xmm7,xmm6
mov r13d,ecx
add r14d,r10d
ror r13d,14
mov r10d,r14d
vpxor xmm7,xmm7,xmm5
mov r12d,edx
xor r13d,ecx
ror r14d,9
xor r12d,r8d
vpslldq xmm7,xmm7,8
ror r13d,5
xor r14d,r10d
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r13d,ecx
vpaddd xmm2,xmm2,xmm7
add r9d,DWORD[40+rsp]
mov r15d,r10d
ror r14d,11
xor r12d,r8d
vpaddd xmm6,xmm2,XMMWORD[64+rbp]
xor r15d,r11d
ror r13d,6
add r9d,r12d
and esi,r15d
xor r14d,r10d
add r9d,r13d
xor esi,r11d
add ebx,r9d
ror r14d,2
add r9d,esi
mov r13d,ebx
add r14d,r9d
ror r13d,14
mov r9d,r14d
mov r12d,ecx
xor r13d,ebx
ror r14d,9
xor r12d,edx
ror r13d,5
xor r14d,r9d
and r12d,ebx
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r13d,ebx
add r8d,DWORD[44+rsp]
mov esi,r9d
ror r14d,11
xor r12d,edx
xor esi,r10d
ror r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
ror r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
vmovdqa XMMWORD[32+rsp],xmm6
vpalignr xmm4,xmm0,xmm3,4
ror r13d,14
mov r8d,r14d
vpalignr xmm7,xmm2,xmm1,4
mov r12d,ebx
xor r13d,eax
DB 143,232,120,194,236,14
ror r14d,9
xor r12d,ecx
vpsrld xmm4,xmm4,3
ror r13d,5
xor r14d,r8d
vpaddd xmm3,xmm3,xmm7
and r12d,eax
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r13d,eax
add edx,DWORD[48+rsp]
mov r15d,r8d
DB 143,232,120,194,245,11
ror r14d,11
xor r12d,ecx
vpxor xmm4,xmm4,xmm5
xor r15d,r9d
ror r13d,6
add edx,r12d
and esi,r15d
DB 143,232,120,194,250,13
xor r14d,r8d
add edx,r13d
vpxor xmm4,xmm4,xmm6
xor esi,r9d
add r11d,edx
vpsrld xmm6,xmm2,10
ror r14d,2
add edx,esi
vpaddd xmm3,xmm3,xmm4
mov r13d,r11d
add r14d,edx
DB 143,232,120,194,239,2
ror r13d,14
mov edx,r14d
vpxor xmm7,xmm7,xmm6
mov r12d,eax
xor r13d,r11d
ror r14d,9
xor r12d,ebx
vpxor xmm7,xmm7,xmm5
ror r13d,5
xor r14d,edx
and r12d,r11d
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r13d,r11d
vpsrldq xmm7,xmm7,8
add ecx,DWORD[52+rsp]
mov esi,edx
ror r14d,11
xor r12d,ebx
vpaddd xmm3,xmm3,xmm7
xor esi,r8d
ror r13d,6
add ecx,r12d
and r15d,esi
DB 143,232,120,194,251,13
xor r14d,edx
add ecx,r13d
vpsrld xmm6,xmm3,10
xor r15d,r8d
add r10d,ecx
DB 143,232,120,194,239,2
ror r14d,2
add ecx,r15d
vpxor xmm7,xmm7,xmm6
mov r13d,r10d
add r14d,ecx
ror r13d,14
mov ecx,r14d
vpxor xmm7,xmm7,xmm5
mov r12d,r11d
xor r13d,r10d
ror r14d,9
xor r12d,eax
vpslldq xmm7,xmm7,8
ror r13d,5
xor r14d,ecx
and r12d,r10d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r13d,r10d
vpaddd xmm3,xmm3,xmm7
add ebx,DWORD[56+rsp]
mov r15d,ecx
ror r14d,11
xor r12d,eax
vpaddd xmm6,xmm3,XMMWORD[96+rbp]
xor r15d,edx
ror r13d,6
add ebx,r12d
and esi,r15d
xor r14d,ecx
add ebx,r13d
xor esi,edx
add r9d,ebx
ror r14d,2
add ebx,esi
mov r13d,r9d
add r14d,ebx
ror r13d,14
mov ebx,r14d
mov r12d,r10d
xor r13d,r9d
ror r14d,9
xor r12d,r11d
ror r13d,5
xor r14d,ebx
and r12d,r9d
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r13d,r9d
add eax,DWORD[60+rsp]
mov esi,ebx
ror r14d,11
xor r12d,r11d
xor esi,ecx
ror r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
ror r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
vmovdqa XMMWORD[48+rsp],xmm6
mov r12,QWORD[((64+0))+rsp]
vpand xmm11,xmm11,xmm14
mov r15,QWORD[((64+8))+rsp]
vpor xmm8,xmm8,xmm11
vmovdqu XMMWORD[r12*1+r15],xmm8
lea r12,[16+r12]
cmp BYTE[131+rbp],0
jne NEAR $L$xop_00_47
vmovdqu xmm9,XMMWORD[r12]
mov QWORD[((64+0))+rsp],r12
ror r13d,14
mov eax,r14d
mov r12d,r9d
xor r13d,r8d
ror r14d,9
xor r12d,r10d
ror r13d,5
xor r14d,eax
and r12d,r8d
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r13d,r8d
add r11d,DWORD[rsp]
mov r15d,eax
ror r14d,11
xor r12d,r10d
xor r15d,ebx
ror r13d,6
add r11d,r12d
and esi,r15d
xor r14d,eax
add r11d,r13d
xor esi,ebx
add edx,r11d
ror r14d,2
add r11d,esi
mov r13d,edx
add r14d,r11d
ror r13d,14
mov r11d,r14d
mov r12d,r8d
xor r13d,edx
ror r14d,9
xor r12d,r9d
ror r13d,5
xor r14d,r11d
and r12d,edx
vpxor xmm9,xmm9,xmm8
xor r13d,edx
add r10d,DWORD[4+rsp]
mov esi,r11d
ror r14d,11
xor r12d,r9d
xor esi,eax
ror r13d,6
add r10d,r12d
and r15d,esi
xor r14d,r11d
add r10d,r13d
xor r15d,eax
add ecx,r10d
ror r14d,2
add r10d,r15d
mov r13d,ecx
add r14d,r10d
ror r13d,14
mov r10d,r14d
mov r12d,edx
xor r13d,ecx
ror r14d,9
xor r12d,r8d
ror r13d,5
xor r14d,r10d
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r13d,ecx
add r9d,DWORD[8+rsp]
mov r15d,r10d
ror r14d,11
xor r12d,r8d
xor r15d,r11d
ror r13d,6
add r9d,r12d
and esi,r15d
xor r14d,r10d
add r9d,r13d
xor esi,r11d
add ebx,r9d
ror r14d,2
add r9d,esi
mov r13d,ebx
add r14d,r9d
ror r13d,14
mov r9d,r14d
mov r12d,ecx
xor r13d,ebx
ror r14d,9
xor r12d,edx
ror r13d,5
xor r14d,r9d
and r12d,ebx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r13d,ebx
add r8d,DWORD[12+rsp]
mov esi,r9d
ror r14d,11
xor r12d,edx
xor esi,r10d
ror r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
ror r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
ror r13d,14
mov r8d,r14d
mov r12d,ebx
xor r13d,eax
ror r14d,9
xor r12d,ecx
ror r13d,5
xor r14d,r8d
and r12d,eax
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r13d,eax
add edx,DWORD[16+rsp]
mov r15d,r8d
ror r14d,11
xor r12d,ecx
xor r15d,r9d
ror r13d,6
add edx,r12d
and esi,r15d
xor r14d,r8d
add edx,r13d
xor esi,r9d
add r11d,edx
ror r14d,2
add edx,esi
mov r13d,r11d
add r14d,edx
ror r13d,14
mov edx,r14d
mov r12d,eax
xor r13d,r11d
ror r14d,9
xor r12d,ebx
ror r13d,5
xor r14d,edx
and r12d,r11d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r13d,r11d
add ecx,DWORD[20+rsp]
mov esi,edx
ror r14d,11
xor r12d,ebx
xor esi,r8d
ror r13d,6
add ecx,r12d
and r15d,esi
xor r14d,edx
add ecx,r13d
xor r15d,r8d
add r10d,ecx
ror r14d,2
add ecx,r15d
mov r13d,r10d
add r14d,ecx
ror r13d,14
mov ecx,r14d
mov r12d,r11d
xor r13d,r10d
ror r14d,9
xor r12d,eax
ror r13d,5
xor r14d,ecx
and r12d,r10d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r13d,r10d
add ebx,DWORD[24+rsp]
mov r15d,ecx
ror r14d,11
xor r12d,eax
xor r15d,edx
ror r13d,6
add ebx,r12d
and esi,r15d
xor r14d,ecx
add ebx,r13d
xor esi,edx
add r9d,ebx
ror r14d,2
add ebx,esi
mov r13d,r9d
add r14d,ebx
ror r13d,14
mov ebx,r14d
mov r12d,r10d
xor r13d,r9d
ror r14d,9
xor r12d,r11d
ror r13d,5
xor r14d,ebx
and r12d,r9d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r13d,r9d
add eax,DWORD[28+rsp]
mov esi,ebx
ror r14d,11
xor r12d,r11d
xor esi,ecx
ror r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
ror r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
ror r13d,14
mov eax,r14d
mov r12d,r9d
xor r13d,r8d
ror r14d,9
xor r12d,r10d
ror r13d,5
xor r14d,eax
and r12d,r8d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r13d,r8d
add r11d,DWORD[32+rsp]
mov r15d,eax
ror r14d,11
xor r12d,r10d
xor r15d,ebx
ror r13d,6
add r11d,r12d
and esi,r15d
xor r14d,eax
add r11d,r13d
xor esi,ebx
add edx,r11d
ror r14d,2
add r11d,esi
mov r13d,edx
add r14d,r11d
ror r13d,14
mov r11d,r14d
mov r12d,r8d
xor r13d,edx
ror r14d,9
xor r12d,r9d
ror r13d,5
xor r14d,r11d
and r12d,edx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r13d,edx
add r10d,DWORD[36+rsp]
mov esi,r11d
ror r14d,11
xor r12d,r9d
xor esi,eax
ror r13d,6
add r10d,r12d
and r15d,esi
xor r14d,r11d
add r10d,r13d
xor r15d,eax
add ecx,r10d
ror r14d,2
add r10d,r15d
mov r13d,ecx
add r14d,r10d
ror r13d,14
mov r10d,r14d
mov r12d,edx
xor r13d,ecx
ror r14d,9
xor r12d,r8d
ror r13d,5
xor r14d,r10d
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r13d,ecx
add r9d,DWORD[40+rsp]
mov r15d,r10d
ror r14d,11
xor r12d,r8d
xor r15d,r11d
ror r13d,6
add r9d,r12d
and esi,r15d
xor r14d,r10d
add r9d,r13d
xor esi,r11d
add ebx,r9d
ror r14d,2
add r9d,esi
mov r13d,ebx
add r14d,r9d
ror r13d,14
mov r9d,r14d
mov r12d,ecx
xor r13d,ebx
ror r14d,9
xor r12d,edx
ror r13d,5
xor r14d,r9d
and r12d,ebx
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r13d,ebx
add r8d,DWORD[44+rsp]
mov esi,r9d
ror r14d,11
xor r12d,edx
xor esi,r10d
ror r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
ror r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
ror r13d,14
mov r8d,r14d
mov r12d,ebx
xor r13d,eax
ror r14d,9
xor r12d,ecx
ror r13d,5
xor r14d,r8d
and r12d,eax
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r13d,eax
add edx,DWORD[48+rsp]
mov r15d,r8d
ror r14d,11
xor r12d,ecx
xor r15d,r9d
ror r13d,6
add edx,r12d
and esi,r15d
xor r14d,r8d
add edx,r13d
xor esi,r9d
add r11d,edx
ror r14d,2
add edx,esi
mov r13d,r11d
add r14d,edx
ror r13d,14
mov edx,r14d
mov r12d,eax
xor r13d,r11d
ror r14d,9
xor r12d,ebx
ror r13d,5
xor r14d,edx
and r12d,r11d
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r13d,r11d
add ecx,DWORD[52+rsp]
mov esi,edx
ror r14d,11
xor r12d,ebx
xor esi,r8d
ror r13d,6
add ecx,r12d
and r15d,esi
xor r14d,edx
add ecx,r13d
xor r15d,r8d
add r10d,ecx
ror r14d,2
add ecx,r15d
mov r13d,r10d
add r14d,ecx
ror r13d,14
mov ecx,r14d
mov r12d,r11d
xor r13d,r10d
ror r14d,9
xor r12d,eax
ror r13d,5
xor r14d,ecx
and r12d,r10d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r13d,r10d
add ebx,DWORD[56+rsp]
mov r15d,ecx
ror r14d,11
xor r12d,eax
xor r15d,edx
ror r13d,6
add ebx,r12d
and esi,r15d
xor r14d,ecx
add ebx,r13d
xor esi,edx
add r9d,ebx
ror r14d,2
add ebx,esi
mov r13d,r9d
add r14d,ebx
ror r13d,14
mov ebx,r14d
mov r12d,r10d
xor r13d,r9d
ror r14d,9
xor r12d,r11d
ror r13d,5
xor r14d,ebx
and r12d,r9d
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r13d,r9d
add eax,DWORD[60+rsp]
mov esi,ebx
ror r14d,11
xor r12d,r11d
xor esi,ecx
ror r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
ror r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
mov r12,QWORD[((64+0))+rsp]
mov r13,QWORD[((64+8))+rsp]
mov r15,QWORD[((64+40))+rsp]
mov rsi,QWORD[((64+48))+rsp]
vpand xmm11,xmm11,xmm14
mov eax,r14d
vpor xmm8,xmm8,xmm11
vmovdqu XMMWORD[r13*1+r12],xmm8
lea r12,[16+r12]
add eax,DWORD[r15]
add ebx,DWORD[4+r15]
add ecx,DWORD[8+r15]
add edx,DWORD[12+r15]
add r8d,DWORD[16+r15]
add r9d,DWORD[20+r15]
add r10d,DWORD[24+r15]
add r11d,DWORD[28+r15]
cmp r12,QWORD[((64+16))+rsp]
mov DWORD[r15],eax
mov DWORD[4+r15],ebx
mov DWORD[8+r15],ecx
mov DWORD[12+r15],edx
mov DWORD[16+r15],r8d
mov DWORD[20+r15],r9d
mov DWORD[24+r15],r10d
mov DWORD[28+r15],r11d
jb NEAR $L$loop_xop
mov r8,QWORD[((64+32))+rsp]
mov rsi,QWORD[((64+56))+rsp]
vmovdqu XMMWORD[r8],xmm8
vzeroall
movaps xmm6,XMMWORD[128+rsp]
movaps xmm7,XMMWORD[144+rsp]
movaps xmm8,XMMWORD[160+rsp]
movaps xmm9,XMMWORD[176+rsp]
movaps xmm10,XMMWORD[192+rsp]
movaps xmm11,XMMWORD[208+rsp]
movaps xmm12,XMMWORD[224+rsp]
movaps xmm13,XMMWORD[240+rsp]
movaps xmm14,XMMWORD[256+rsp]
movaps xmm15,XMMWORD[272+rsp]
mov r15,QWORD[rsi]
mov r14,QWORD[8+rsi]
mov r13,QWORD[16+rsi]
mov r12,QWORD[24+rsi]
mov rbp,QWORD[32+rsi]
mov rbx,QWORD[40+rsi]
lea rsp,[48+rsi]
$L$epilogue_xop:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_aesni_cbc_sha256_enc_xop:
ALIGN 64
aesni_cbc_sha256_enc_avx:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_aesni_cbc_sha256_enc_avx:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD[40+rsp]
mov r9,QWORD[48+rsp]
$L$avx_shortcut:
mov r10,QWORD[56+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
mov r11,rsp
sub rsp,288
and rsp,-64
shl rdx,6
sub rsi,rdi
sub r10,rdi
add rdx,rdi
mov QWORD[((64+8))+rsp],rsi
mov QWORD[((64+16))+rsp],rdx
mov QWORD[((64+32))+rsp],r8
mov QWORD[((64+40))+rsp],r9
mov QWORD[((64+48))+rsp],r10
mov QWORD[((64+56))+rsp],r11
movaps XMMWORD[128+rsp],xmm6
movaps XMMWORD[144+rsp],xmm7
movaps XMMWORD[160+rsp],xmm8
movaps XMMWORD[176+rsp],xmm9
movaps XMMWORD[192+rsp],xmm10
movaps XMMWORD[208+rsp],xmm11
movaps XMMWORD[224+rsp],xmm12
movaps XMMWORD[240+rsp],xmm13
movaps XMMWORD[256+rsp],xmm14
movaps XMMWORD[272+rsp],xmm15
$L$prologue_avx:
vzeroall
mov r12,rdi
lea rdi,[128+rcx]
lea r13,[((K256+544))]
mov r14d,DWORD[((240-128))+rdi]
mov r15,r9
mov rsi,r10
vmovdqu xmm8,XMMWORD[r8]
sub r14,9
mov eax,DWORD[r15]
mov ebx,DWORD[4+r15]
mov ecx,DWORD[8+r15]
mov edx,DWORD[12+r15]
mov r8d,DWORD[16+r15]
mov r9d,DWORD[20+r15]
mov r10d,DWORD[24+r15]
mov r11d,DWORD[28+r15]
vmovdqa xmm14,XMMWORD[r14*8+r13]
vmovdqa xmm13,XMMWORD[16+r14*8+r13]
vmovdqa xmm12,XMMWORD[32+r14*8+r13]
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
jmp NEAR $L$loop_avx
ALIGN 16
$L$loop_avx:
vmovdqa xmm7,XMMWORD[((K256+512))]
vmovdqu xmm0,XMMWORD[r12*1+rsi]
vmovdqu xmm1,XMMWORD[16+r12*1+rsi]
vmovdqu xmm2,XMMWORD[32+r12*1+rsi]
vmovdqu xmm3,XMMWORD[48+r12*1+rsi]
vpshufb xmm0,xmm0,xmm7
lea rbp,[K256]
vpshufb xmm1,xmm1,xmm7
vpshufb xmm2,xmm2,xmm7
vpaddd xmm4,xmm0,XMMWORD[rbp]
vpshufb xmm3,xmm3,xmm7
vpaddd xmm5,xmm1,XMMWORD[32+rbp]
vpaddd xmm6,xmm2,XMMWORD[64+rbp]
vpaddd xmm7,xmm3,XMMWORD[96+rbp]
vmovdqa XMMWORD[rsp],xmm4
mov r14d,eax
vmovdqa XMMWORD[16+rsp],xmm5
mov esi,ebx
vmovdqa XMMWORD[32+rsp],xmm6
xor esi,ecx
vmovdqa XMMWORD[48+rsp],xmm7
mov r13d,r8d
jmp NEAR $L$avx_00_47
ALIGN 16
$L$avx_00_47:
sub rbp,-16*2*4
vmovdqu xmm9,XMMWORD[r12]
mov QWORD[((64+0))+rsp],r12
vpalignr xmm4,xmm1,xmm0,4
shrd r13d,r13d,14
mov eax,r14d
mov r12d,r9d
vpalignr xmm7,xmm3,xmm2,4
xor r13d,r8d
shrd r14d,r14d,9
xor r12d,r10d
vpsrld xmm6,xmm4,7
shrd r13d,r13d,5
xor r14d,eax
and r12d,r8d
vpaddd xmm0,xmm0,xmm7
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r13d,r8d
add r11d,DWORD[rsp]
mov r15d,eax
vpsrld xmm7,xmm4,3
shrd r14d,r14d,11
xor r12d,r10d
xor r15d,ebx
vpslld xmm5,xmm4,14
shrd r13d,r13d,6
add r11d,r12d
and esi,r15d
vpxor xmm4,xmm7,xmm6
xor r14d,eax
add r11d,r13d
xor esi,ebx
vpshufd xmm7,xmm3,250
add edx,r11d
shrd r14d,r14d,2
add r11d,esi
vpsrld xmm6,xmm6,11
mov r13d,edx
add r14d,r11d
shrd r13d,r13d,14
vpxor xmm4,xmm4,xmm5
mov r11d,r14d
mov r12d,r8d
xor r13d,edx
vpslld xmm5,xmm5,11
shrd r14d,r14d,9
xor r12d,r9d
shrd r13d,r13d,5
vpxor xmm4,xmm4,xmm6
xor r14d,r11d
and r12d,edx
vpxor xmm9,xmm9,xmm8
xor r13d,edx
vpsrld xmm6,xmm7,10
add r10d,DWORD[4+rsp]
mov esi,r11d
shrd r14d,r14d,11
vpxor xmm4,xmm4,xmm5
xor r12d,r9d
xor esi,eax
shrd r13d,r13d,6
vpsrlq xmm7,xmm7,17
add r10d,r12d
and r15d,esi
xor r14d,r11d
vpaddd xmm0,xmm0,xmm4
add r10d,r13d
xor r15d,eax
add ecx,r10d
vpxor xmm6,xmm6,xmm7
shrd r14d,r14d,2
add r10d,r15d
mov r13d,ecx
vpsrlq xmm7,xmm7,2
add r14d,r10d
shrd r13d,r13d,14
mov r10d,r14d
vpxor xmm6,xmm6,xmm7
mov r12d,edx
xor r13d,ecx
shrd r14d,r14d,9
vpshufd xmm6,xmm6,132
xor r12d,r8d
shrd r13d,r13d,5
xor r14d,r10d
vpsrldq xmm6,xmm6,8
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r13d,ecx
add r9d,DWORD[8+rsp]
vpaddd xmm0,xmm0,xmm6
mov r15d,r10d
shrd r14d,r14d,11
xor r12d,r8d
vpshufd xmm7,xmm0,80
xor r15d,r11d
shrd r13d,r13d,6
add r9d,r12d
vpsrld xmm6,xmm7,10
and esi,r15d
xor r14d,r10d
add r9d,r13d
vpsrlq xmm7,xmm7,17
xor esi,r11d
add ebx,r9d
shrd r14d,r14d,2
vpxor xmm6,xmm6,xmm7
add r9d,esi
mov r13d,ebx
add r14d,r9d
vpsrlq xmm7,xmm7,2
shrd r13d,r13d,14
mov r9d,r14d
mov r12d,ecx
vpxor xmm6,xmm6,xmm7
xor r13d,ebx
shrd r14d,r14d,9
xor r12d,edx
vpshufd xmm6,xmm6,232
shrd r13d,r13d,5
xor r14d,r9d
and r12d,ebx
vpslldq xmm6,xmm6,8
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r13d,ebx
add r8d,DWORD[12+rsp]
mov esi,r9d
vpaddd xmm0,xmm0,xmm6
shrd r14d,r14d,11
xor r12d,edx
xor esi,r10d
vpaddd xmm6,xmm0,XMMWORD[rbp]
shrd r13d,r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
shrd r14d,r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
vmovdqa XMMWORD[rsp],xmm6
vpalignr xmm4,xmm2,xmm1,4
shrd r13d,r13d,14
mov r8d,r14d
mov r12d,ebx
vpalignr xmm7,xmm0,xmm3,4
xor r13d,eax
shrd r14d,r14d,9
xor r12d,ecx
vpsrld xmm6,xmm4,7
shrd r13d,r13d,5
xor r14d,r8d
and r12d,eax
vpaddd xmm1,xmm1,xmm7
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r13d,eax
add edx,DWORD[16+rsp]
mov r15d,r8d
vpsrld xmm7,xmm4,3
shrd r14d,r14d,11
xor r12d,ecx
xor r15d,r9d
vpslld xmm5,xmm4,14
shrd r13d,r13d,6
add edx,r12d
and esi,r15d
vpxor xmm4,xmm7,xmm6
xor r14d,r8d
add edx,r13d
xor esi,r9d
vpshufd xmm7,xmm0,250
add r11d,edx
shrd r14d,r14d,2
add edx,esi
vpsrld xmm6,xmm6,11
mov r13d,r11d
add r14d,edx
shrd r13d,r13d,14
vpxor xmm4,xmm4,xmm5
mov edx,r14d
mov r12d,eax
xor r13d,r11d
vpslld xmm5,xmm5,11
shrd r14d,r14d,9
xor r12d,ebx
shrd r13d,r13d,5
vpxor xmm4,xmm4,xmm6
xor r14d,edx
and r12d,r11d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r13d,r11d
vpsrld xmm6,xmm7,10
add ecx,DWORD[20+rsp]
mov esi,edx
shrd r14d,r14d,11
vpxor xmm4,xmm4,xmm5
xor r12d,ebx
xor esi,r8d
shrd r13d,r13d,6
vpsrlq xmm7,xmm7,17
add ecx,r12d
and r15d,esi
xor r14d,edx
vpaddd xmm1,xmm1,xmm4
add ecx,r13d
xor r15d,r8d
add r10d,ecx
vpxor xmm6,xmm6,xmm7
shrd r14d,r14d,2
add ecx,r15d
mov r13d,r10d
vpsrlq xmm7,xmm7,2
add r14d,ecx
shrd r13d,r13d,14
mov ecx,r14d
vpxor xmm6,xmm6,xmm7
mov r12d,r11d
xor r13d,r10d
shrd r14d,r14d,9
vpshufd xmm6,xmm6,132
xor r12d,eax
shrd r13d,r13d,5
xor r14d,ecx
vpsrldq xmm6,xmm6,8
and r12d,r10d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r13d,r10d
add ebx,DWORD[24+rsp]
vpaddd xmm1,xmm1,xmm6
mov r15d,ecx
shrd r14d,r14d,11
xor r12d,eax
vpshufd xmm7,xmm1,80
xor r15d,edx
shrd r13d,r13d,6
add ebx,r12d
vpsrld xmm6,xmm7,10
and esi,r15d
xor r14d,ecx
add ebx,r13d
vpsrlq xmm7,xmm7,17
xor esi,edx
add r9d,ebx
shrd r14d,r14d,2
vpxor xmm6,xmm6,xmm7
add ebx,esi
mov r13d,r9d
add r14d,ebx
vpsrlq xmm7,xmm7,2
shrd r13d,r13d,14
mov ebx,r14d
mov r12d,r10d
vpxor xmm6,xmm6,xmm7
xor r13d,r9d
shrd r14d,r14d,9
xor r12d,r11d
vpshufd xmm6,xmm6,232
shrd r13d,r13d,5
xor r14d,ebx
and r12d,r9d
vpslldq xmm6,xmm6,8
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r13d,r9d
add eax,DWORD[28+rsp]
mov esi,ebx
vpaddd xmm1,xmm1,xmm6
shrd r14d,r14d,11
xor r12d,r11d
xor esi,ecx
vpaddd xmm6,xmm1,XMMWORD[32+rbp]
shrd r13d,r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
shrd r14d,r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
vmovdqa XMMWORD[16+rsp],xmm6
vpalignr xmm4,xmm3,xmm2,4
shrd r13d,r13d,14
mov eax,r14d
mov r12d,r9d
vpalignr xmm7,xmm1,xmm0,4
xor r13d,r8d
shrd r14d,r14d,9
xor r12d,r10d
vpsrld xmm6,xmm4,7
shrd r13d,r13d,5
xor r14d,eax
and r12d,r8d
vpaddd xmm2,xmm2,xmm7
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r13d,r8d
add r11d,DWORD[32+rsp]
mov r15d,eax
vpsrld xmm7,xmm4,3
shrd r14d,r14d,11
xor r12d,r10d
xor r15d,ebx
vpslld xmm5,xmm4,14
shrd r13d,r13d,6
add r11d,r12d
and esi,r15d
vpxor xmm4,xmm7,xmm6
xor r14d,eax
add r11d,r13d
xor esi,ebx
vpshufd xmm7,xmm1,250
add edx,r11d
shrd r14d,r14d,2
add r11d,esi
vpsrld xmm6,xmm6,11
mov r13d,edx
add r14d,r11d
shrd r13d,r13d,14
vpxor xmm4,xmm4,xmm5
mov r11d,r14d
mov r12d,r8d
xor r13d,edx
vpslld xmm5,xmm5,11
shrd r14d,r14d,9
xor r12d,r9d
shrd r13d,r13d,5
vpxor xmm4,xmm4,xmm6
xor r14d,r11d
and r12d,edx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r13d,edx
vpsrld xmm6,xmm7,10
add r10d,DWORD[36+rsp]
mov esi,r11d
shrd r14d,r14d,11
vpxor xmm4,xmm4,xmm5
xor r12d,r9d
xor esi,eax
shrd r13d,r13d,6
vpsrlq xmm7,xmm7,17
add r10d,r12d
and r15d,esi
xor r14d,r11d
vpaddd xmm2,xmm2,xmm4
add r10d,r13d
xor r15d,eax
add ecx,r10d
vpxor xmm6,xmm6,xmm7
shrd r14d,r14d,2
add r10d,r15d
mov r13d,ecx
vpsrlq xmm7,xmm7,2
add r14d,r10d
shrd r13d,r13d,14
mov r10d,r14d
vpxor xmm6,xmm6,xmm7
mov r12d,edx
xor r13d,ecx
shrd r14d,r14d,9
vpshufd xmm6,xmm6,132
xor r12d,r8d
shrd r13d,r13d,5
xor r14d,r10d
vpsrldq xmm6,xmm6,8
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r13d,ecx
add r9d,DWORD[40+rsp]
vpaddd xmm2,xmm2,xmm6
mov r15d,r10d
shrd r14d,r14d,11
xor r12d,r8d
vpshufd xmm7,xmm2,80
xor r15d,r11d
shrd r13d,r13d,6
add r9d,r12d
vpsrld xmm6,xmm7,10
and esi,r15d
xor r14d,r10d
add r9d,r13d
vpsrlq xmm7,xmm7,17
xor esi,r11d
add ebx,r9d
shrd r14d,r14d,2
vpxor xmm6,xmm6,xmm7
add r9d,esi
mov r13d,ebx
add r14d,r9d
vpsrlq xmm7,xmm7,2
shrd r13d,r13d,14
mov r9d,r14d
mov r12d,ecx
vpxor xmm6,xmm6,xmm7
xor r13d,ebx
shrd r14d,r14d,9
xor r12d,edx
vpshufd xmm6,xmm6,232
shrd r13d,r13d,5
xor r14d,r9d
and r12d,ebx
vpslldq xmm6,xmm6,8
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r13d,ebx
add r8d,DWORD[44+rsp]
mov esi,r9d
vpaddd xmm2,xmm2,xmm6
shrd r14d,r14d,11
xor r12d,edx
xor esi,r10d
vpaddd xmm6,xmm2,XMMWORD[64+rbp]
shrd r13d,r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
shrd r14d,r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
vmovdqa XMMWORD[32+rsp],xmm6
vpalignr xmm4,xmm0,xmm3,4
shrd r13d,r13d,14
mov r8d,r14d
mov r12d,ebx
vpalignr xmm7,xmm2,xmm1,4
xor r13d,eax
shrd r14d,r14d,9
xor r12d,ecx
vpsrld xmm6,xmm4,7
shrd r13d,r13d,5
xor r14d,r8d
and r12d,eax
vpaddd xmm3,xmm3,xmm7
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r13d,eax
add edx,DWORD[48+rsp]
mov r15d,r8d
vpsrld xmm7,xmm4,3
shrd r14d,r14d,11
xor r12d,ecx
xor r15d,r9d
vpslld xmm5,xmm4,14
shrd r13d,r13d,6
add edx,r12d
and esi,r15d
vpxor xmm4,xmm7,xmm6
xor r14d,r8d
add edx,r13d
xor esi,r9d
vpshufd xmm7,xmm2,250
add r11d,edx
shrd r14d,r14d,2
add edx,esi
vpsrld xmm6,xmm6,11
mov r13d,r11d
add r14d,edx
shrd r13d,r13d,14
vpxor xmm4,xmm4,xmm5
mov edx,r14d
mov r12d,eax
xor r13d,r11d
vpslld xmm5,xmm5,11
shrd r14d,r14d,9
xor r12d,ebx
shrd r13d,r13d,5
vpxor xmm4,xmm4,xmm6
xor r14d,edx
and r12d,r11d
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r13d,r11d
vpsrld xmm6,xmm7,10
add ecx,DWORD[52+rsp]
mov esi,edx
shrd r14d,r14d,11
vpxor xmm4,xmm4,xmm5
xor r12d,ebx
xor esi,r8d
shrd r13d,r13d,6
vpsrlq xmm7,xmm7,17
add ecx,r12d
and r15d,esi
xor r14d,edx
vpaddd xmm3,xmm3,xmm4
add ecx,r13d
xor r15d,r8d
add r10d,ecx
vpxor xmm6,xmm6,xmm7
shrd r14d,r14d,2
add ecx,r15d
mov r13d,r10d
vpsrlq xmm7,xmm7,2
add r14d,ecx
shrd r13d,r13d,14
mov ecx,r14d
vpxor xmm6,xmm6,xmm7
mov r12d,r11d
xor r13d,r10d
shrd r14d,r14d,9
vpshufd xmm6,xmm6,132
xor r12d,eax
shrd r13d,r13d,5
xor r14d,ecx
vpsrldq xmm6,xmm6,8
and r12d,r10d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r13d,r10d
add ebx,DWORD[56+rsp]
vpaddd xmm3,xmm3,xmm6
mov r15d,ecx
shrd r14d,r14d,11
xor r12d,eax
vpshufd xmm7,xmm3,80
xor r15d,edx
shrd r13d,r13d,6
add ebx,r12d
vpsrld xmm6,xmm7,10
and esi,r15d
xor r14d,ecx
add ebx,r13d
vpsrlq xmm7,xmm7,17
xor esi,edx
add r9d,ebx
shrd r14d,r14d,2
vpxor xmm6,xmm6,xmm7
add ebx,esi
mov r13d,r9d
add r14d,ebx
vpsrlq xmm7,xmm7,2
shrd r13d,r13d,14
mov ebx,r14d
mov r12d,r10d
vpxor xmm6,xmm6,xmm7
xor r13d,r9d
shrd r14d,r14d,9
xor r12d,r11d
vpshufd xmm6,xmm6,232
shrd r13d,r13d,5
xor r14d,ebx
and r12d,r9d
vpslldq xmm6,xmm6,8
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r13d,r9d
add eax,DWORD[60+rsp]
mov esi,ebx
vpaddd xmm3,xmm3,xmm6
shrd r14d,r14d,11
xor r12d,r11d
xor esi,ecx
vpaddd xmm6,xmm3,XMMWORD[96+rbp]
shrd r13d,r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
shrd r14d,r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
vmovdqa XMMWORD[48+rsp],xmm6
mov r12,QWORD[((64+0))+rsp]
vpand xmm11,xmm11,xmm14
mov r15,QWORD[((64+8))+rsp]
vpor xmm8,xmm8,xmm11
vmovdqu XMMWORD[r12*1+r15],xmm8
lea r12,[16+r12]
cmp BYTE[131+rbp],0
jne NEAR $L$avx_00_47
vmovdqu xmm9,XMMWORD[r12]
mov QWORD[((64+0))+rsp],r12
shrd r13d,r13d,14
mov eax,r14d
mov r12d,r9d
xor r13d,r8d
shrd r14d,r14d,9
xor r12d,r10d
shrd r13d,r13d,5
xor r14d,eax
and r12d,r8d
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r13d,r8d
add r11d,DWORD[rsp]
mov r15d,eax
shrd r14d,r14d,11
xor r12d,r10d
xor r15d,ebx
shrd r13d,r13d,6
add r11d,r12d
and esi,r15d
xor r14d,eax
add r11d,r13d
xor esi,ebx
add edx,r11d
shrd r14d,r14d,2
add r11d,esi
mov r13d,edx
add r14d,r11d
shrd r13d,r13d,14
mov r11d,r14d
mov r12d,r8d
xor r13d,edx
shrd r14d,r14d,9
xor r12d,r9d
shrd r13d,r13d,5
xor r14d,r11d
and r12d,edx
vpxor xmm9,xmm9,xmm8
xor r13d,edx
add r10d,DWORD[4+rsp]
mov esi,r11d
shrd r14d,r14d,11
xor r12d,r9d
xor esi,eax
shrd r13d,r13d,6
add r10d,r12d
and r15d,esi
xor r14d,r11d
add r10d,r13d
xor r15d,eax
add ecx,r10d
shrd r14d,r14d,2
add r10d,r15d
mov r13d,ecx
add r14d,r10d
shrd r13d,r13d,14
mov r10d,r14d
mov r12d,edx
xor r13d,ecx
shrd r14d,r14d,9
xor r12d,r8d
shrd r13d,r13d,5
xor r14d,r10d
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r13d,ecx
add r9d,DWORD[8+rsp]
mov r15d,r10d
shrd r14d,r14d,11
xor r12d,r8d
xor r15d,r11d
shrd r13d,r13d,6
add r9d,r12d
and esi,r15d
xor r14d,r10d
add r9d,r13d
xor esi,r11d
add ebx,r9d
shrd r14d,r14d,2
add r9d,esi
mov r13d,ebx
add r14d,r9d
shrd r13d,r13d,14
mov r9d,r14d
mov r12d,ecx
xor r13d,ebx
shrd r14d,r14d,9
xor r12d,edx
shrd r13d,r13d,5
xor r14d,r9d
and r12d,ebx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r13d,ebx
add r8d,DWORD[12+rsp]
mov esi,r9d
shrd r14d,r14d,11
xor r12d,edx
xor esi,r10d
shrd r13d,r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
shrd r14d,r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
shrd r13d,r13d,14
mov r8d,r14d
mov r12d,ebx
xor r13d,eax
shrd r14d,r14d,9
xor r12d,ecx
shrd r13d,r13d,5
xor r14d,r8d
and r12d,eax
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r13d,eax
add edx,DWORD[16+rsp]
mov r15d,r8d
shrd r14d,r14d,11
xor r12d,ecx
xor r15d,r9d
shrd r13d,r13d,6
add edx,r12d
and esi,r15d
xor r14d,r8d
add edx,r13d
xor esi,r9d
add r11d,edx
shrd r14d,r14d,2
add edx,esi
mov r13d,r11d
add r14d,edx
shrd r13d,r13d,14
mov edx,r14d
mov r12d,eax
xor r13d,r11d
shrd r14d,r14d,9
xor r12d,ebx
shrd r13d,r13d,5
xor r14d,edx
and r12d,r11d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r13d,r11d
add ecx,DWORD[20+rsp]
mov esi,edx
shrd r14d,r14d,11
xor r12d,ebx
xor esi,r8d
shrd r13d,r13d,6
add ecx,r12d
and r15d,esi
xor r14d,edx
add ecx,r13d
xor r15d,r8d
add r10d,ecx
shrd r14d,r14d,2
add ecx,r15d
mov r13d,r10d
add r14d,ecx
shrd r13d,r13d,14
mov ecx,r14d
mov r12d,r11d
xor r13d,r10d
shrd r14d,r14d,9
xor r12d,eax
shrd r13d,r13d,5
xor r14d,ecx
and r12d,r10d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r13d,r10d
add ebx,DWORD[24+rsp]
mov r15d,ecx
shrd r14d,r14d,11
xor r12d,eax
xor r15d,edx
shrd r13d,r13d,6
add ebx,r12d
and esi,r15d
xor r14d,ecx
add ebx,r13d
xor esi,edx
add r9d,ebx
shrd r14d,r14d,2
add ebx,esi
mov r13d,r9d
add r14d,ebx
shrd r13d,r13d,14
mov ebx,r14d
mov r12d,r10d
xor r13d,r9d
shrd r14d,r14d,9
xor r12d,r11d
shrd r13d,r13d,5
xor r14d,ebx
and r12d,r9d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r13d,r9d
add eax,DWORD[28+rsp]
mov esi,ebx
shrd r14d,r14d,11
xor r12d,r11d
xor esi,ecx
shrd r13d,r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
shrd r14d,r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
shrd r13d,r13d,14
mov eax,r14d
mov r12d,r9d
xor r13d,r8d
shrd r14d,r14d,9
xor r12d,r10d
shrd r13d,r13d,5
xor r14d,eax
and r12d,r8d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r13d,r8d
add r11d,DWORD[32+rsp]
mov r15d,eax
shrd r14d,r14d,11
xor r12d,r10d
xor r15d,ebx
shrd r13d,r13d,6
add r11d,r12d
and esi,r15d
xor r14d,eax
add r11d,r13d
xor esi,ebx
add edx,r11d
shrd r14d,r14d,2
add r11d,esi
mov r13d,edx
add r14d,r11d
shrd r13d,r13d,14
mov r11d,r14d
mov r12d,r8d
xor r13d,edx
shrd r14d,r14d,9
xor r12d,r9d
shrd r13d,r13d,5
xor r14d,r11d
and r12d,edx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r13d,edx
add r10d,DWORD[36+rsp]
mov esi,r11d
shrd r14d,r14d,11
xor r12d,r9d
xor esi,eax
shrd r13d,r13d,6
add r10d,r12d
and r15d,esi
xor r14d,r11d
add r10d,r13d
xor r15d,eax
add ecx,r10d
shrd r14d,r14d,2
add r10d,r15d
mov r13d,ecx
add r14d,r10d
shrd r13d,r13d,14
mov r10d,r14d
mov r12d,edx
xor r13d,ecx
shrd r14d,r14d,9
xor r12d,r8d
shrd r13d,r13d,5
xor r14d,r10d
and r12d,ecx
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r13d,ecx
add r9d,DWORD[40+rsp]
mov r15d,r10d
shrd r14d,r14d,11
xor r12d,r8d
xor r15d,r11d
shrd r13d,r13d,6
add r9d,r12d
and esi,r15d
xor r14d,r10d
add r9d,r13d
xor esi,r11d
add ebx,r9d
shrd r14d,r14d,2
add r9d,esi
mov r13d,ebx
add r14d,r9d
shrd r13d,r13d,14
mov r9d,r14d
mov r12d,ecx
xor r13d,ebx
shrd r14d,r14d,9
xor r12d,edx
shrd r13d,r13d,5
xor r14d,r9d
and r12d,ebx
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r13d,ebx
add r8d,DWORD[44+rsp]
mov esi,r9d
shrd r14d,r14d,11
xor r12d,edx
xor esi,r10d
shrd r13d,r13d,6
add r8d,r12d
and r15d,esi
xor r14d,r9d
add r8d,r13d
xor r15d,r10d
add eax,r8d
shrd r14d,r14d,2
add r8d,r15d
mov r13d,eax
add r14d,r8d
shrd r13d,r13d,14
mov r8d,r14d
mov r12d,ebx
xor r13d,eax
shrd r14d,r14d,9
xor r12d,ecx
shrd r13d,r13d,5
xor r14d,r8d
and r12d,eax
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r13d,eax
add edx,DWORD[48+rsp]
mov r15d,r8d
shrd r14d,r14d,11
xor r12d,ecx
xor r15d,r9d
shrd r13d,r13d,6
add edx,r12d
and esi,r15d
xor r14d,r8d
add edx,r13d
xor esi,r9d
add r11d,edx
shrd r14d,r14d,2
add edx,esi
mov r13d,r11d
add r14d,edx
shrd r13d,r13d,14
mov edx,r14d
mov r12d,eax
xor r13d,r11d
shrd r14d,r14d,9
xor r12d,ebx
shrd r13d,r13d,5
xor r14d,edx
and r12d,r11d
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r13d,r11d
add ecx,DWORD[52+rsp]
mov esi,edx
shrd r14d,r14d,11
xor r12d,ebx
xor esi,r8d
shrd r13d,r13d,6
add ecx,r12d
and r15d,esi
xor r14d,edx
add ecx,r13d
xor r15d,r8d
add r10d,ecx
shrd r14d,r14d,2
add ecx,r15d
mov r13d,r10d
add r14d,ecx
shrd r13d,r13d,14
mov ecx,r14d
mov r12d,r11d
xor r13d,r10d
shrd r14d,r14d,9
xor r12d,eax
shrd r13d,r13d,5
xor r14d,ecx
and r12d,r10d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r13d,r10d
add ebx,DWORD[56+rsp]
mov r15d,ecx
shrd r14d,r14d,11
xor r12d,eax
xor r15d,edx
shrd r13d,r13d,6
add ebx,r12d
and esi,r15d
xor r14d,ecx
add ebx,r13d
xor esi,edx
add r9d,ebx
shrd r14d,r14d,2
add ebx,esi
mov r13d,r9d
add r14d,ebx
shrd r13d,r13d,14
mov ebx,r14d
mov r12d,r10d
xor r13d,r9d
shrd r14d,r14d,9
xor r12d,r11d
shrd r13d,r13d,5
xor r14d,ebx
and r12d,r9d
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r13d,r9d
add eax,DWORD[60+rsp]
mov esi,ebx
shrd r14d,r14d,11
xor r12d,r11d
xor esi,ecx
shrd r13d,r13d,6
add eax,r12d
and r15d,esi
xor r14d,ebx
add eax,r13d
xor r15d,ecx
add r8d,eax
shrd r14d,r14d,2
add eax,r15d
mov r13d,r8d
add r14d,eax
mov r12,QWORD[((64+0))+rsp]
mov r13,QWORD[((64+8))+rsp]
mov r15,QWORD[((64+40))+rsp]
mov rsi,QWORD[((64+48))+rsp]
vpand xmm11,xmm11,xmm14
mov eax,r14d
vpor xmm8,xmm8,xmm11
vmovdqu XMMWORD[r13*1+r12],xmm8
lea r12,[16+r12]
add eax,DWORD[r15]
add ebx,DWORD[4+r15]
add ecx,DWORD[8+r15]
add edx,DWORD[12+r15]
add r8d,DWORD[16+r15]
add r9d,DWORD[20+r15]
add r10d,DWORD[24+r15]
add r11d,DWORD[28+r15]
cmp r12,QWORD[((64+16))+rsp]
mov DWORD[r15],eax
mov DWORD[4+r15],ebx
mov DWORD[8+r15],ecx
mov DWORD[12+r15],edx
mov DWORD[16+r15],r8d
mov DWORD[20+r15],r9d
mov DWORD[24+r15],r10d
mov DWORD[28+r15],r11d
jb NEAR $L$loop_avx
mov r8,QWORD[((64+32))+rsp]
mov rsi,QWORD[((64+56))+rsp]
vmovdqu XMMWORD[r8],xmm8
vzeroall
movaps xmm6,XMMWORD[128+rsp]
movaps xmm7,XMMWORD[144+rsp]
movaps xmm8,XMMWORD[160+rsp]
movaps xmm9,XMMWORD[176+rsp]
movaps xmm10,XMMWORD[192+rsp]
movaps xmm11,XMMWORD[208+rsp]
movaps xmm12,XMMWORD[224+rsp]
movaps xmm13,XMMWORD[240+rsp]
movaps xmm14,XMMWORD[256+rsp]
movaps xmm15,XMMWORD[272+rsp]
mov r15,QWORD[rsi]
mov r14,QWORD[8+rsi]
mov r13,QWORD[16+rsi]
mov r12,QWORD[24+rsi]
mov rbp,QWORD[32+rsi]
mov rbx,QWORD[40+rsi]
lea rsp,[48+rsi]
$L$epilogue_avx:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_aesni_cbc_sha256_enc_avx:
ALIGN 64
aesni_cbc_sha256_enc_avx2:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_aesni_cbc_sha256_enc_avx2:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD[40+rsp]
mov r9,QWORD[48+rsp]
$L$avx2_shortcut:
mov r10,QWORD[56+rsp]
push rbx
push rbp
push r12
push r13
push r14
push r15
mov r11,rsp
sub rsp,736
and rsp,-256*4
add rsp,448
shl rdx,6
sub rsi,rdi
sub r10,rdi
add rdx,rdi
mov QWORD[((64+16))+rsp],rdx
mov QWORD[((64+32))+rsp],r8
mov QWORD[((64+40))+rsp],r9
mov QWORD[((64+48))+rsp],r10
mov QWORD[((64+56))+rsp],r11
movaps XMMWORD[128+rsp],xmm6
movaps XMMWORD[144+rsp],xmm7
movaps XMMWORD[160+rsp],xmm8
movaps XMMWORD[176+rsp],xmm9
movaps XMMWORD[192+rsp],xmm10
movaps XMMWORD[208+rsp],xmm11
movaps XMMWORD[224+rsp],xmm12
movaps XMMWORD[240+rsp],xmm13
movaps XMMWORD[256+rsp],xmm14
movaps XMMWORD[272+rsp],xmm15
$L$prologue_avx2:
vzeroall
mov r13,rdi
vpinsrq xmm15,xmm15,rsi,1
lea rdi,[128+rcx]
lea r12,[((K256+544))]
mov r14d,DWORD[((240-128))+rdi]
mov r15,r9
mov rsi,r10
vmovdqu xmm8,XMMWORD[r8]
lea r14,[((-9))+r14]
vmovdqa xmm14,XMMWORD[r14*8+r12]
vmovdqa xmm13,XMMWORD[16+r14*8+r12]
vmovdqa xmm12,XMMWORD[32+r14*8+r12]
sub r13,-16*4
mov eax,DWORD[r15]
lea r12,[r13*1+rsi]
mov ebx,DWORD[4+r15]
cmp r13,rdx
mov ecx,DWORD[8+r15]
cmove r12,rsp
mov edx,DWORD[12+r15]
mov r8d,DWORD[16+r15]
mov r9d,DWORD[20+r15]
mov r10d,DWORD[24+r15]
mov r11d,DWORD[28+r15]
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
jmp NEAR $L$oop_avx2
ALIGN 16
$L$oop_avx2:
vmovdqa ymm7,YMMWORD[((K256+512))]
vmovdqu xmm0,XMMWORD[((-64+0))+r13*1+rsi]
vmovdqu xmm1,XMMWORD[((-64+16))+r13*1+rsi]
vmovdqu xmm2,XMMWORD[((-64+32))+r13*1+rsi]
vmovdqu xmm3,XMMWORD[((-64+48))+r13*1+rsi]
vinserti128 ymm0,ymm0,XMMWORD[r12],1
vinserti128 ymm1,ymm1,XMMWORD[16+r12],1
vpshufb ymm0,ymm0,ymm7
vinserti128 ymm2,ymm2,XMMWORD[32+r12],1
vpshufb ymm1,ymm1,ymm7
vinserti128 ymm3,ymm3,XMMWORD[48+r12],1
lea rbp,[K256]
vpshufb ymm2,ymm2,ymm7
lea r13,[((-64))+r13]
vpaddd ymm4,ymm0,YMMWORD[rbp]
vpshufb ymm3,ymm3,ymm7
vpaddd ymm5,ymm1,YMMWORD[32+rbp]
vpaddd ymm6,ymm2,YMMWORD[64+rbp]
vpaddd ymm7,ymm3,YMMWORD[96+rbp]
vmovdqa YMMWORD[rsp],ymm4
xor r14d,r14d
vmovdqa YMMWORD[32+rsp],ymm5
lea rsp,[((-64))+rsp]
mov esi,ebx
vmovdqa YMMWORD[rsp],ymm6
xor esi,ecx
vmovdqa YMMWORD[32+rsp],ymm7
mov r12d,r9d
sub rbp,-16*2*4
jmp NEAR $L$avx2_00_47
ALIGN 16
$L$avx2_00_47:
vmovdqu xmm9,XMMWORD[r13]
vpinsrq xmm15,xmm15,r13,0
lea rsp,[((-64))+rsp]
vpalignr ymm4,ymm1,ymm0,4
add r11d,DWORD[((0+128))+rsp]
and r12d,r8d
rorx r13d,r8d,25
vpalignr ymm7,ymm3,ymm2,4
rorx r15d,r8d,11
lea eax,[r14*1+rax]
lea r11d,[r12*1+r11]
vpsrld ymm6,ymm4,7
andn r12d,r8d,r10d
xor r13d,r15d
rorx r14d,r8d,6
vpaddd ymm0,ymm0,ymm7
lea r11d,[r12*1+r11]
xor r13d,r14d
mov r15d,eax
vpsrld ymm7,ymm4,3
rorx r12d,eax,22
lea r11d,[r13*1+r11]
xor r15d,ebx
vpslld ymm5,ymm4,14
rorx r14d,eax,13
rorx r13d,eax,2
lea edx,[r11*1+rdx]
vpxor ymm4,ymm7,ymm6
and esi,r15d
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r14d,r12d
xor esi,ebx
vpshufd ymm7,ymm3,250
xor r14d,r13d
lea r11d,[rsi*1+r11]
mov r12d,r8d
vpsrld ymm6,ymm6,11
add r10d,DWORD[((4+128))+rsp]
and r12d,edx
rorx r13d,edx,25
vpxor ymm4,ymm4,ymm5
rorx esi,edx,11
lea r11d,[r14*1+r11]
lea r10d,[r12*1+r10]
vpslld ymm5,ymm5,11
andn r12d,edx,r9d
xor r13d,esi
rorx r14d,edx,6
vpxor ymm4,ymm4,ymm6
lea r10d,[r12*1+r10]
xor r13d,r14d
mov esi,r11d
vpsrld ymm6,ymm7,10
rorx r12d,r11d,22
lea r10d,[r13*1+r10]
xor esi,eax
vpxor ymm4,ymm4,ymm5
rorx r14d,r11d,13
rorx r13d,r11d,2
lea ecx,[r10*1+rcx]
vpsrlq ymm7,ymm7,17
and r15d,esi
vpxor xmm9,xmm9,xmm8
xor r14d,r12d
xor r15d,eax
vpaddd ymm0,ymm0,ymm4
xor r14d,r13d
lea r10d,[r15*1+r10]
mov r12d,edx
vpxor ymm6,ymm6,ymm7
add r9d,DWORD[((8+128))+rsp]
and r12d,ecx
rorx r13d,ecx,25
vpsrlq ymm7,ymm7,2
rorx r15d,ecx,11
lea r10d,[r14*1+r10]
lea r9d,[r12*1+r9]
vpxor ymm6,ymm6,ymm7
andn r12d,ecx,r8d
xor r13d,r15d
rorx r14d,ecx,6
vpshufd ymm6,ymm6,132
lea r9d,[r12*1+r9]
xor r13d,r14d
mov r15d,r10d
vpsrldq ymm6,ymm6,8
rorx r12d,r10d,22
lea r9d,[r13*1+r9]
xor r15d,r11d
vpaddd ymm0,ymm0,ymm6
rorx r14d,r10d,13
rorx r13d,r10d,2
lea ebx,[r9*1+rbx]
vpshufd ymm7,ymm0,80
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r14d,r12d
xor esi,r11d
vpsrld ymm6,ymm7,10
xor r14d,r13d
lea r9d,[rsi*1+r9]
mov r12d,ecx
vpsrlq ymm7,ymm7,17
add r8d,DWORD[((12+128))+rsp]
and r12d,ebx
rorx r13d,ebx,25
vpxor ymm6,ymm6,ymm7
rorx esi,ebx,11
lea r9d,[r14*1+r9]
lea r8d,[r12*1+r8]
vpsrlq ymm7,ymm7,2
andn r12d,ebx,edx
xor r13d,esi
rorx r14d,ebx,6
vpxor ymm6,ymm6,ymm7
lea r8d,[r12*1+r8]
xor r13d,r14d
mov esi,r9d
vpshufd ymm6,ymm6,232
rorx r12d,r9d,22
lea r8d,[r13*1+r8]
xor esi,r10d
vpslldq ymm6,ymm6,8
rorx r14d,r9d,13
rorx r13d,r9d,2
lea eax,[r8*1+rax]
vpaddd ymm0,ymm0,ymm6
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r14d,r12d
xor r15d,r10d
vpaddd ymm6,ymm0,YMMWORD[rbp]
xor r14d,r13d
lea r8d,[r15*1+r8]
mov r12d,ebx
vmovdqa YMMWORD[rsp],ymm6
vpalignr ymm4,ymm2,ymm1,4
add edx,DWORD[((32+128))+rsp]
and r12d,eax
rorx r13d,eax,25
vpalignr ymm7,ymm0,ymm3,4
rorx r15d,eax,11
lea r8d,[r14*1+r8]
lea edx,[r12*1+rdx]
vpsrld ymm6,ymm4,7
andn r12d,eax,ecx
xor r13d,r15d
rorx r14d,eax,6
vpaddd ymm1,ymm1,ymm7
lea edx,[r12*1+rdx]
xor r13d,r14d
mov r15d,r8d
vpsrld ymm7,ymm4,3
rorx r12d,r8d,22
lea edx,[r13*1+rdx]
xor r15d,r9d
vpslld ymm5,ymm4,14
rorx r14d,r8d,13
rorx r13d,r8d,2
lea r11d,[rdx*1+r11]
vpxor ymm4,ymm7,ymm6
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r14d,r12d
xor esi,r9d
vpshufd ymm7,ymm0,250
xor r14d,r13d
lea edx,[rsi*1+rdx]
mov r12d,eax
vpsrld ymm6,ymm6,11
add ecx,DWORD[((36+128))+rsp]
and r12d,r11d
rorx r13d,r11d,25
vpxor ymm4,ymm4,ymm5
rorx esi,r11d,11
lea edx,[r14*1+rdx]
lea ecx,[r12*1+rcx]
vpslld ymm5,ymm5,11
andn r12d,r11d,ebx
xor r13d,esi
rorx r14d,r11d,6
vpxor ymm4,ymm4,ymm6
lea ecx,[r12*1+rcx]
xor r13d,r14d
mov esi,edx
vpsrld ymm6,ymm7,10
rorx r12d,edx,22
lea ecx,[r13*1+rcx]
xor esi,r8d
vpxor ymm4,ymm4,ymm5
rorx r14d,edx,13
rorx r13d,edx,2
lea r10d,[rcx*1+r10]
vpsrlq ymm7,ymm7,17
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r14d,r12d
xor r15d,r8d
vpaddd ymm1,ymm1,ymm4
xor r14d,r13d
lea ecx,[r15*1+rcx]
mov r12d,r11d
vpxor ymm6,ymm6,ymm7
add ebx,DWORD[((40+128))+rsp]
and r12d,r10d
rorx r13d,r10d,25
vpsrlq ymm7,ymm7,2
rorx r15d,r10d,11
lea ecx,[r14*1+rcx]
lea ebx,[r12*1+rbx]
vpxor ymm6,ymm6,ymm7
andn r12d,r10d,eax
xor r13d,r15d
rorx r14d,r10d,6
vpshufd ymm6,ymm6,132
lea ebx,[r12*1+rbx]
xor r13d,r14d
mov r15d,ecx
vpsrldq ymm6,ymm6,8
rorx r12d,ecx,22
lea ebx,[r13*1+rbx]
xor r15d,edx
vpaddd ymm1,ymm1,ymm6
rorx r14d,ecx,13
rorx r13d,ecx,2
lea r9d,[rbx*1+r9]
vpshufd ymm7,ymm1,80
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r14d,r12d
xor esi,edx
vpsrld ymm6,ymm7,10
xor r14d,r13d
lea ebx,[rsi*1+rbx]
mov r12d,r10d
vpsrlq ymm7,ymm7,17
add eax,DWORD[((44+128))+rsp]
and r12d,r9d
rorx r13d,r9d,25
vpxor ymm6,ymm6,ymm7
rorx esi,r9d,11
lea ebx,[r14*1+rbx]
lea eax,[r12*1+rax]
vpsrlq ymm7,ymm7,2
andn r12d,r9d,r11d
xor r13d,esi
rorx r14d,r9d,6
vpxor ymm6,ymm6,ymm7
lea eax,[r12*1+rax]
xor r13d,r14d
mov esi,ebx
vpshufd ymm6,ymm6,232
rorx r12d,ebx,22
lea eax,[r13*1+rax]
xor esi,ecx
vpslldq ymm6,ymm6,8
rorx r14d,ebx,13
rorx r13d,ebx,2
lea r8d,[rax*1+r8]
vpaddd ymm1,ymm1,ymm6
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r14d,r12d
xor r15d,ecx
vpaddd ymm6,ymm1,YMMWORD[32+rbp]
xor r14d,r13d
lea eax,[r15*1+rax]
mov r12d,r9d
vmovdqa YMMWORD[32+rsp],ymm6
lea rsp,[((-64))+rsp]
vpalignr ymm4,ymm3,ymm2,4
add r11d,DWORD[((0+128))+rsp]
and r12d,r8d
rorx r13d,r8d,25
vpalignr ymm7,ymm1,ymm0,4
rorx r15d,r8d,11
lea eax,[r14*1+rax]
lea r11d,[r12*1+r11]
vpsrld ymm6,ymm4,7
andn r12d,r8d,r10d
xor r13d,r15d
rorx r14d,r8d,6
vpaddd ymm2,ymm2,ymm7
lea r11d,[r12*1+r11]
xor r13d,r14d
mov r15d,eax
vpsrld ymm7,ymm4,3
rorx r12d,eax,22
lea r11d,[r13*1+r11]
xor r15d,ebx
vpslld ymm5,ymm4,14
rorx r14d,eax,13
rorx r13d,eax,2
lea edx,[r11*1+rdx]
vpxor ymm4,ymm7,ymm6
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r14d,r12d
xor esi,ebx
vpshufd ymm7,ymm1,250
xor r14d,r13d
lea r11d,[rsi*1+r11]
mov r12d,r8d
vpsrld ymm6,ymm6,11
add r10d,DWORD[((4+128))+rsp]
and r12d,edx
rorx r13d,edx,25
vpxor ymm4,ymm4,ymm5
rorx esi,edx,11
lea r11d,[r14*1+r11]
lea r10d,[r12*1+r10]
vpslld ymm5,ymm5,11
andn r12d,edx,r9d
xor r13d,esi
rorx r14d,edx,6
vpxor ymm4,ymm4,ymm6
lea r10d,[r12*1+r10]
xor r13d,r14d
mov esi,r11d
vpsrld ymm6,ymm7,10
rorx r12d,r11d,22
lea r10d,[r13*1+r10]
xor esi,eax
vpxor ymm4,ymm4,ymm5
rorx r14d,r11d,13
rorx r13d,r11d,2
lea ecx,[r10*1+rcx]
vpsrlq ymm7,ymm7,17
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r14d,r12d
xor r15d,eax
vpaddd ymm2,ymm2,ymm4
xor r14d,r13d
lea r10d,[r15*1+r10]
mov r12d,edx
vpxor ymm6,ymm6,ymm7
add r9d,DWORD[((8+128))+rsp]
and r12d,ecx
rorx r13d,ecx,25
vpsrlq ymm7,ymm7,2
rorx r15d,ecx,11
lea r10d,[r14*1+r10]
lea r9d,[r12*1+r9]
vpxor ymm6,ymm6,ymm7
andn r12d,ecx,r8d
xor r13d,r15d
rorx r14d,ecx,6
vpshufd ymm6,ymm6,132
lea r9d,[r12*1+r9]
xor r13d,r14d
mov r15d,r10d
vpsrldq ymm6,ymm6,8
rorx r12d,r10d,22
lea r9d,[r13*1+r9]
xor r15d,r11d
vpaddd ymm2,ymm2,ymm6
rorx r14d,r10d,13
rorx r13d,r10d,2
lea ebx,[r9*1+rbx]
vpshufd ymm7,ymm2,80
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r14d,r12d
xor esi,r11d
vpsrld ymm6,ymm7,10
xor r14d,r13d
lea r9d,[rsi*1+r9]
mov r12d,ecx
vpsrlq ymm7,ymm7,17
add r8d,DWORD[((12+128))+rsp]
and r12d,ebx
rorx r13d,ebx,25
vpxor ymm6,ymm6,ymm7
rorx esi,ebx,11
lea r9d,[r14*1+r9]
lea r8d,[r12*1+r8]
vpsrlq ymm7,ymm7,2
andn r12d,ebx,edx
xor r13d,esi
rorx r14d,ebx,6
vpxor ymm6,ymm6,ymm7
lea r8d,[r12*1+r8]
xor r13d,r14d
mov esi,r9d
vpshufd ymm6,ymm6,232
rorx r12d,r9d,22
lea r8d,[r13*1+r8]
xor esi,r10d
vpslldq ymm6,ymm6,8
rorx r14d,r9d,13
rorx r13d,r9d,2
lea eax,[r8*1+rax]
vpaddd ymm2,ymm2,ymm6
and r15d,esi
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r14d,r12d
xor r15d,r10d
vpaddd ymm6,ymm2,YMMWORD[64+rbp]
xor r14d,r13d
lea r8d,[r15*1+r8]
mov r12d,ebx
vmovdqa YMMWORD[rsp],ymm6
vpalignr ymm4,ymm0,ymm3,4
add edx,DWORD[((32+128))+rsp]
and r12d,eax
rorx r13d,eax,25
vpalignr ymm7,ymm2,ymm1,4
rorx r15d,eax,11
lea r8d,[r14*1+r8]
lea edx,[r12*1+rdx]
vpsrld ymm6,ymm4,7
andn r12d,eax,ecx
xor r13d,r15d
rorx r14d,eax,6
vpaddd ymm3,ymm3,ymm7
lea edx,[r12*1+rdx]
xor r13d,r14d
mov r15d,r8d
vpsrld ymm7,ymm4,3
rorx r12d,r8d,22
lea edx,[r13*1+rdx]
xor r15d,r9d
vpslld ymm5,ymm4,14
rorx r14d,r8d,13
rorx r13d,r8d,2
lea r11d,[rdx*1+r11]
vpxor ymm4,ymm7,ymm6
and esi,r15d
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r14d,r12d
xor esi,r9d
vpshufd ymm7,ymm2,250
xor r14d,r13d
lea edx,[rsi*1+rdx]
mov r12d,eax
vpsrld ymm6,ymm6,11
add ecx,DWORD[((36+128))+rsp]
and r12d,r11d
rorx r13d,r11d,25
vpxor ymm4,ymm4,ymm5
rorx esi,r11d,11
lea edx,[r14*1+rdx]
lea ecx,[r12*1+rcx]
vpslld ymm5,ymm5,11
andn r12d,r11d,ebx
xor r13d,esi
rorx r14d,r11d,6
vpxor ymm4,ymm4,ymm6
lea ecx,[r12*1+rcx]
xor r13d,r14d
mov esi,edx
vpsrld ymm6,ymm7,10
rorx r12d,edx,22
lea ecx,[r13*1+rcx]
xor esi,r8d
vpxor ymm4,ymm4,ymm5
rorx r14d,edx,13
rorx r13d,edx,2
lea r10d,[rcx*1+r10]
vpsrlq ymm7,ymm7,17
and r15d,esi
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r14d,r12d
xor r15d,r8d
vpaddd ymm3,ymm3,ymm4
xor r14d,r13d
lea ecx,[r15*1+rcx]
mov r12d,r11d
vpxor ymm6,ymm6,ymm7
add ebx,DWORD[((40+128))+rsp]
and r12d,r10d
rorx r13d,r10d,25
vpsrlq ymm7,ymm7,2
rorx r15d,r10d,11
lea ecx,[r14*1+rcx]
lea ebx,[r12*1+rbx]
vpxor ymm6,ymm6,ymm7
andn r12d,r10d,eax
xor r13d,r15d
rorx r14d,r10d,6
vpshufd ymm6,ymm6,132
lea ebx,[r12*1+rbx]
xor r13d,r14d
mov r15d,ecx
vpsrldq ymm6,ymm6,8
rorx r12d,ecx,22
lea ebx,[r13*1+rbx]
xor r15d,edx
vpaddd ymm3,ymm3,ymm6
rorx r14d,ecx,13
rorx r13d,ecx,2
lea r9d,[rbx*1+r9]
vpshufd ymm7,ymm3,80
and esi,r15d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r14d,r12d
xor esi,edx
vpsrld ymm6,ymm7,10
xor r14d,r13d
lea ebx,[rsi*1+rbx]
mov r12d,r10d
vpsrlq ymm7,ymm7,17
add eax,DWORD[((44+128))+rsp]
and r12d,r9d
rorx r13d,r9d,25
vpxor ymm6,ymm6,ymm7
rorx esi,r9d,11
lea ebx,[r14*1+rbx]
lea eax,[r12*1+rax]
vpsrlq ymm7,ymm7,2
andn r12d,r9d,r11d
xor r13d,esi
rorx r14d,r9d,6
vpxor ymm6,ymm6,ymm7
lea eax,[r12*1+rax]
xor r13d,r14d
mov esi,ebx
vpshufd ymm6,ymm6,232
rorx r12d,ebx,22
lea eax,[r13*1+rax]
xor esi,ecx
vpslldq ymm6,ymm6,8
rorx r14d,ebx,13
rorx r13d,ebx,2
lea r8d,[rax*1+r8]
vpaddd ymm3,ymm3,ymm6
and r15d,esi
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r14d,r12d
xor r15d,ecx
vpaddd ymm6,ymm3,YMMWORD[96+rbp]
xor r14d,r13d
lea eax,[r15*1+rax]
mov r12d,r9d
vmovdqa YMMWORD[32+rsp],ymm6
vmovq r13,xmm15
vpextrq r15,xmm15,1
vpand xmm11,xmm11,xmm14
vpor xmm8,xmm8,xmm11
vmovdqu XMMWORD[r13*1+r15],xmm8
lea r13,[16+r13]
lea rbp,[128+rbp]
cmp BYTE[3+rbp],0
jne NEAR $L$avx2_00_47
vmovdqu xmm9,XMMWORD[r13]
vpinsrq xmm15,xmm15,r13,0
add r11d,DWORD[((0+64))+rsp]
and r12d,r8d
rorx r13d,r8d,25
rorx r15d,r8d,11
lea eax,[r14*1+rax]
lea r11d,[r12*1+r11]
andn r12d,r8d,r10d
xor r13d,r15d
rorx r14d,r8d,6
lea r11d,[r12*1+r11]
xor r13d,r14d
mov r15d,eax
rorx r12d,eax,22
lea r11d,[r13*1+r11]
xor r15d,ebx
rorx r14d,eax,13
rorx r13d,eax,2
lea edx,[r11*1+rdx]
and esi,r15d
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r14d,r12d
xor esi,ebx
xor r14d,r13d
lea r11d,[rsi*1+r11]
mov r12d,r8d
add r10d,DWORD[((4+64))+rsp]
and r12d,edx
rorx r13d,edx,25
rorx esi,edx,11
lea r11d,[r14*1+r11]
lea r10d,[r12*1+r10]
andn r12d,edx,r9d
xor r13d,esi
rorx r14d,edx,6
lea r10d,[r12*1+r10]
xor r13d,r14d
mov esi,r11d
rorx r12d,r11d,22
lea r10d,[r13*1+r10]
xor esi,eax
rorx r14d,r11d,13
rorx r13d,r11d,2
lea ecx,[r10*1+rcx]
and r15d,esi
vpxor xmm9,xmm9,xmm8
xor r14d,r12d
xor r15d,eax
xor r14d,r13d
lea r10d,[r15*1+r10]
mov r12d,edx
add r9d,DWORD[((8+64))+rsp]
and r12d,ecx
rorx r13d,ecx,25
rorx r15d,ecx,11
lea r10d,[r14*1+r10]
lea r9d,[r12*1+r9]
andn r12d,ecx,r8d
xor r13d,r15d
rorx r14d,ecx,6
lea r9d,[r12*1+r9]
xor r13d,r14d
mov r15d,r10d
rorx r12d,r10d,22
lea r9d,[r13*1+r9]
xor r15d,r11d
rorx r14d,r10d,13
rorx r13d,r10d,2
lea ebx,[r9*1+rbx]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r14d,r12d
xor esi,r11d
xor r14d,r13d
lea r9d,[rsi*1+r9]
mov r12d,ecx
add r8d,DWORD[((12+64))+rsp]
and r12d,ebx
rorx r13d,ebx,25
rorx esi,ebx,11
lea r9d,[r14*1+r9]
lea r8d,[r12*1+r8]
andn r12d,ebx,edx
xor r13d,esi
rorx r14d,ebx,6
lea r8d,[r12*1+r8]
xor r13d,r14d
mov esi,r9d
rorx r12d,r9d,22
lea r8d,[r13*1+r8]
xor esi,r10d
rorx r14d,r9d,13
rorx r13d,r9d,2
lea eax,[r8*1+rax]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r14d,r12d
xor r15d,r10d
xor r14d,r13d
lea r8d,[r15*1+r8]
mov r12d,ebx
add edx,DWORD[((32+64))+rsp]
and r12d,eax
rorx r13d,eax,25
rorx r15d,eax,11
lea r8d,[r14*1+r8]
lea edx,[r12*1+rdx]
andn r12d,eax,ecx
xor r13d,r15d
rorx r14d,eax,6
lea edx,[r12*1+rdx]
xor r13d,r14d
mov r15d,r8d
rorx r12d,r8d,22
lea edx,[r13*1+rdx]
xor r15d,r9d
rorx r14d,r8d,13
rorx r13d,r8d,2
lea r11d,[rdx*1+r11]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r14d,r12d
xor esi,r9d
xor r14d,r13d
lea edx,[rsi*1+rdx]
mov r12d,eax
add ecx,DWORD[((36+64))+rsp]
and r12d,r11d
rorx r13d,r11d,25
rorx esi,r11d,11
lea edx,[r14*1+rdx]
lea ecx,[r12*1+rcx]
andn r12d,r11d,ebx
xor r13d,esi
rorx r14d,r11d,6
lea ecx,[r12*1+rcx]
xor r13d,r14d
mov esi,edx
rorx r12d,edx,22
lea ecx,[r13*1+rcx]
xor esi,r8d
rorx r14d,edx,13
rorx r13d,edx,2
lea r10d,[rcx*1+r10]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r14d,r12d
xor r15d,r8d
xor r14d,r13d
lea ecx,[r15*1+rcx]
mov r12d,r11d
add ebx,DWORD[((40+64))+rsp]
and r12d,r10d
rorx r13d,r10d,25
rorx r15d,r10d,11
lea ecx,[r14*1+rcx]
lea ebx,[r12*1+rbx]
andn r12d,r10d,eax
xor r13d,r15d
rorx r14d,r10d,6
lea ebx,[r12*1+rbx]
xor r13d,r14d
mov r15d,ecx
rorx r12d,ecx,22
lea ebx,[r13*1+rbx]
xor r15d,edx
rorx r14d,ecx,13
rorx r13d,ecx,2
lea r9d,[rbx*1+r9]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r14d,r12d
xor esi,edx
xor r14d,r13d
lea ebx,[rsi*1+rbx]
mov r12d,r10d
add eax,DWORD[((44+64))+rsp]
and r12d,r9d
rorx r13d,r9d,25
rorx esi,r9d,11
lea ebx,[r14*1+rbx]
lea eax,[r12*1+rax]
andn r12d,r9d,r11d
xor r13d,esi
rorx r14d,r9d,6
lea eax,[r12*1+rax]
xor r13d,r14d
mov esi,ebx
rorx r12d,ebx,22
lea eax,[r13*1+rax]
xor esi,ecx
rorx r14d,ebx,13
rorx r13d,ebx,2
lea r8d,[rax*1+r8]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r14d,r12d
xor r15d,ecx
xor r14d,r13d
lea eax,[r15*1+rax]
mov r12d,r9d
add r11d,DWORD[rsp]
and r12d,r8d
rorx r13d,r8d,25
rorx r15d,r8d,11
lea eax,[r14*1+rax]
lea r11d,[r12*1+r11]
andn r12d,r8d,r10d
xor r13d,r15d
rorx r14d,r8d,6
lea r11d,[r12*1+r11]
xor r13d,r14d
mov r15d,eax
rorx r12d,eax,22
lea r11d,[r13*1+r11]
xor r15d,ebx
rorx r14d,eax,13
rorx r13d,eax,2
lea edx,[r11*1+rdx]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r14d,r12d
xor esi,ebx
xor r14d,r13d
lea r11d,[rsi*1+r11]
mov r12d,r8d
add r10d,DWORD[4+rsp]
and r12d,edx
rorx r13d,edx,25
rorx esi,edx,11
lea r11d,[r14*1+r11]
lea r10d,[r12*1+r10]
andn r12d,edx,r9d
xor r13d,esi
rorx r14d,edx,6
lea r10d,[r12*1+r10]
xor r13d,r14d
mov esi,r11d
rorx r12d,r11d,22
lea r10d,[r13*1+r10]
xor esi,eax
rorx r14d,r11d,13
rorx r13d,r11d,2
lea ecx,[r10*1+rcx]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r14d,r12d
xor r15d,eax
xor r14d,r13d
lea r10d,[r15*1+r10]
mov r12d,edx
add r9d,DWORD[8+rsp]
and r12d,ecx
rorx r13d,ecx,25
rorx r15d,ecx,11
lea r10d,[r14*1+r10]
lea r9d,[r12*1+r9]
andn r12d,ecx,r8d
xor r13d,r15d
rorx r14d,ecx,6
lea r9d,[r12*1+r9]
xor r13d,r14d
mov r15d,r10d
rorx r12d,r10d,22
lea r9d,[r13*1+r9]
xor r15d,r11d
rorx r14d,r10d,13
rorx r13d,r10d,2
lea ebx,[r9*1+rbx]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r14d,r12d
xor esi,r11d
xor r14d,r13d
lea r9d,[rsi*1+r9]
mov r12d,ecx
add r8d,DWORD[12+rsp]
and r12d,ebx
rorx r13d,ebx,25
rorx esi,ebx,11
lea r9d,[r14*1+r9]
lea r8d,[r12*1+r8]
andn r12d,ebx,edx
xor r13d,esi
rorx r14d,ebx,6
lea r8d,[r12*1+r8]
xor r13d,r14d
mov esi,r9d
rorx r12d,r9d,22
lea r8d,[r13*1+r8]
xor esi,r10d
rorx r14d,r9d,13
rorx r13d,r9d,2
lea eax,[r8*1+rax]
and r15d,esi
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r14d,r12d
xor r15d,r10d
xor r14d,r13d
lea r8d,[r15*1+r8]
mov r12d,ebx
add edx,DWORD[32+rsp]
and r12d,eax
rorx r13d,eax,25
rorx r15d,eax,11
lea r8d,[r14*1+r8]
lea edx,[r12*1+rdx]
andn r12d,eax,ecx
xor r13d,r15d
rorx r14d,eax,6
lea edx,[r12*1+rdx]
xor r13d,r14d
mov r15d,r8d
rorx r12d,r8d,22
lea edx,[r13*1+rdx]
xor r15d,r9d
rorx r14d,r8d,13
rorx r13d,r8d,2
lea r11d,[rdx*1+r11]
and esi,r15d
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r14d,r12d
xor esi,r9d
xor r14d,r13d
lea edx,[rsi*1+rdx]
mov r12d,eax
add ecx,DWORD[36+rsp]
and r12d,r11d
rorx r13d,r11d,25
rorx esi,r11d,11
lea edx,[r14*1+rdx]
lea ecx,[r12*1+rcx]
andn r12d,r11d,ebx
xor r13d,esi
rorx r14d,r11d,6
lea ecx,[r12*1+rcx]
xor r13d,r14d
mov esi,edx
rorx r12d,edx,22
lea ecx,[r13*1+rcx]
xor esi,r8d
rorx r14d,edx,13
rorx r13d,edx,2
lea r10d,[rcx*1+r10]
and r15d,esi
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r14d,r12d
xor r15d,r8d
xor r14d,r13d
lea ecx,[r15*1+rcx]
mov r12d,r11d
add ebx,DWORD[40+rsp]
and r12d,r10d
rorx r13d,r10d,25
rorx r15d,r10d,11
lea ecx,[r14*1+rcx]
lea ebx,[r12*1+rbx]
andn r12d,r10d,eax
xor r13d,r15d
rorx r14d,r10d,6
lea ebx,[r12*1+rbx]
xor r13d,r14d
mov r15d,ecx
rorx r12d,ecx,22
lea ebx,[r13*1+rbx]
xor r15d,edx
rorx r14d,ecx,13
rorx r13d,ecx,2
lea r9d,[rbx*1+r9]
and esi,r15d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r14d,r12d
xor esi,edx
xor r14d,r13d
lea ebx,[rsi*1+rbx]
mov r12d,r10d
add eax,DWORD[44+rsp]
and r12d,r9d
rorx r13d,r9d,25
rorx esi,r9d,11
lea ebx,[r14*1+rbx]
lea eax,[r12*1+rax]
andn r12d,r9d,r11d
xor r13d,esi
rorx r14d,r9d,6
lea eax,[r12*1+rax]
xor r13d,r14d
mov esi,ebx
rorx r12d,ebx,22
lea eax,[r13*1+rax]
xor esi,ecx
rorx r14d,ebx,13
rorx r13d,ebx,2
lea r8d,[rax*1+r8]
and r15d,esi
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r14d,r12d
xor r15d,ecx
xor r14d,r13d
lea eax,[r15*1+rax]
mov r12d,r9d
vpextrq r12,xmm15,1
vmovq r13,xmm15
mov r15,QWORD[552+rsp]
add eax,r14d
lea rbp,[448+rsp]
vpand xmm11,xmm11,xmm14
vpor xmm8,xmm8,xmm11
vmovdqu XMMWORD[r13*1+r12],xmm8
lea r13,[16+r13]
add eax,DWORD[r15]
add ebx,DWORD[4+r15]
add ecx,DWORD[8+r15]
add edx,DWORD[12+r15]
add r8d,DWORD[16+r15]
add r9d,DWORD[20+r15]
add r10d,DWORD[24+r15]
add r11d,DWORD[28+r15]
mov DWORD[r15],eax
mov DWORD[4+r15],ebx
mov DWORD[8+r15],ecx
mov DWORD[12+r15],edx
mov DWORD[16+r15],r8d
mov DWORD[20+r15],r9d
mov DWORD[24+r15],r10d
mov DWORD[28+r15],r11d
cmp r13,QWORD[80+rbp]
je NEAR $L$done_avx2
xor r14d,r14d
mov esi,ebx
mov r12d,r9d
xor esi,ecx
jmp NEAR $L$ower_avx2
ALIGN 16
$L$ower_avx2:
vmovdqu xmm9,XMMWORD[r13]
vpinsrq xmm15,xmm15,r13,0
add r11d,DWORD[((0+16))+rbp]
and r12d,r8d
rorx r13d,r8d,25
rorx r15d,r8d,11
lea eax,[r14*1+rax]
lea r11d,[r12*1+r11]
andn r12d,r8d,r10d
xor r13d,r15d
rorx r14d,r8d,6
lea r11d,[r12*1+r11]
xor r13d,r14d
mov r15d,eax
rorx r12d,eax,22
lea r11d,[r13*1+r11]
xor r15d,ebx
rorx r14d,eax,13
rorx r13d,eax,2
lea edx,[r11*1+rdx]
and esi,r15d
vpxor xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((16-128))+rdi]
xor r14d,r12d
xor esi,ebx
xor r14d,r13d
lea r11d,[rsi*1+r11]
mov r12d,r8d
add r10d,DWORD[((4+16))+rbp]
and r12d,edx
rorx r13d,edx,25
rorx esi,edx,11
lea r11d,[r14*1+r11]
lea r10d,[r12*1+r10]
andn r12d,edx,r9d
xor r13d,esi
rorx r14d,edx,6
lea r10d,[r12*1+r10]
xor r13d,r14d
mov esi,r11d
rorx r12d,r11d,22
lea r10d,[r13*1+r10]
xor esi,eax
rorx r14d,r11d,13
rorx r13d,r11d,2
lea ecx,[r10*1+rcx]
and r15d,esi
vpxor xmm9,xmm9,xmm8
xor r14d,r12d
xor r15d,eax
xor r14d,r13d
lea r10d,[r15*1+r10]
mov r12d,edx
add r9d,DWORD[((8+16))+rbp]
and r12d,ecx
rorx r13d,ecx,25
rorx r15d,ecx,11
lea r10d,[r14*1+r10]
lea r9d,[r12*1+r9]
andn r12d,ecx,r8d
xor r13d,r15d
rorx r14d,ecx,6
lea r9d,[r12*1+r9]
xor r13d,r14d
mov r15d,r10d
rorx r12d,r10d,22
lea r9d,[r13*1+r9]
xor r15d,r11d
rorx r14d,r10d,13
rorx r13d,r10d,2
lea ebx,[r9*1+rbx]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((32-128))+rdi]
xor r14d,r12d
xor esi,r11d
xor r14d,r13d
lea r9d,[rsi*1+r9]
mov r12d,ecx
add r8d,DWORD[((12+16))+rbp]
and r12d,ebx
rorx r13d,ebx,25
rorx esi,ebx,11
lea r9d,[r14*1+r9]
lea r8d,[r12*1+r8]
andn r12d,ebx,edx
xor r13d,esi
rorx r14d,ebx,6
lea r8d,[r12*1+r8]
xor r13d,r14d
mov esi,r9d
rorx r12d,r9d,22
lea r8d,[r13*1+r8]
xor esi,r10d
rorx r14d,r9d,13
rorx r13d,r9d,2
lea eax,[r8*1+rax]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((48-128))+rdi]
xor r14d,r12d
xor r15d,r10d
xor r14d,r13d
lea r8d,[r15*1+r8]
mov r12d,ebx
add edx,DWORD[((32+16))+rbp]
and r12d,eax
rorx r13d,eax,25
rorx r15d,eax,11
lea r8d,[r14*1+r8]
lea edx,[r12*1+rdx]
andn r12d,eax,ecx
xor r13d,r15d
rorx r14d,eax,6
lea edx,[r12*1+rdx]
xor r13d,r14d
mov r15d,r8d
rorx r12d,r8d,22
lea edx,[r13*1+rdx]
xor r15d,r9d
rorx r14d,r8d,13
rorx r13d,r8d,2
lea r11d,[rdx*1+r11]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((64-128))+rdi]
xor r14d,r12d
xor esi,r9d
xor r14d,r13d
lea edx,[rsi*1+rdx]
mov r12d,eax
add ecx,DWORD[((36+16))+rbp]
and r12d,r11d
rorx r13d,r11d,25
rorx esi,r11d,11
lea edx,[r14*1+rdx]
lea ecx,[r12*1+rcx]
andn r12d,r11d,ebx
xor r13d,esi
rorx r14d,r11d,6
lea ecx,[r12*1+rcx]
xor r13d,r14d
mov esi,edx
rorx r12d,edx,22
lea ecx,[r13*1+rcx]
xor esi,r8d
rorx r14d,edx,13
rorx r13d,edx,2
lea r10d,[rcx*1+r10]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((80-128))+rdi]
xor r14d,r12d
xor r15d,r8d
xor r14d,r13d
lea ecx,[r15*1+rcx]
mov r12d,r11d
add ebx,DWORD[((40+16))+rbp]
and r12d,r10d
rorx r13d,r10d,25
rorx r15d,r10d,11
lea ecx,[r14*1+rcx]
lea ebx,[r12*1+rbx]
andn r12d,r10d,eax
xor r13d,r15d
rorx r14d,r10d,6
lea ebx,[r12*1+rbx]
xor r13d,r14d
mov r15d,ecx
rorx r12d,ecx,22
lea ebx,[r13*1+rbx]
xor r15d,edx
rorx r14d,ecx,13
rorx r13d,ecx,2
lea r9d,[rbx*1+r9]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((96-128))+rdi]
xor r14d,r12d
xor esi,edx
xor r14d,r13d
lea ebx,[rsi*1+rbx]
mov r12d,r10d
add eax,DWORD[((44+16))+rbp]
and r12d,r9d
rorx r13d,r9d,25
rorx esi,r9d,11
lea ebx,[r14*1+rbx]
lea eax,[r12*1+rax]
andn r12d,r9d,r11d
xor r13d,esi
rorx r14d,r9d,6
lea eax,[r12*1+rax]
xor r13d,r14d
mov esi,ebx
rorx r12d,ebx,22
lea eax,[r13*1+rax]
xor esi,ecx
rorx r14d,ebx,13
rorx r13d,ebx,2
lea r8d,[rax*1+r8]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((112-128))+rdi]
xor r14d,r12d
xor r15d,ecx
xor r14d,r13d
lea eax,[r15*1+rax]
mov r12d,r9d
lea rbp,[((-64))+rbp]
add r11d,DWORD[((0+16))+rbp]
and r12d,r8d
rorx r13d,r8d,25
rorx r15d,r8d,11
lea eax,[r14*1+rax]
lea r11d,[r12*1+r11]
andn r12d,r8d,r10d
xor r13d,r15d
rorx r14d,r8d,6
lea r11d,[r12*1+r11]
xor r13d,r14d
mov r15d,eax
rorx r12d,eax,22
lea r11d,[r13*1+r11]
xor r15d,ebx
rorx r14d,eax,13
rorx r13d,eax,2
lea edx,[r11*1+rdx]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((128-128))+rdi]
xor r14d,r12d
xor esi,ebx
xor r14d,r13d
lea r11d,[rsi*1+r11]
mov r12d,r8d
add r10d,DWORD[((4+16))+rbp]
and r12d,edx
rorx r13d,edx,25
rorx esi,edx,11
lea r11d,[r14*1+r11]
lea r10d,[r12*1+r10]
andn r12d,edx,r9d
xor r13d,esi
rorx r14d,edx,6
lea r10d,[r12*1+r10]
xor r13d,r14d
mov esi,r11d
rorx r12d,r11d,22
lea r10d,[r13*1+r10]
xor esi,eax
rorx r14d,r11d,13
rorx r13d,r11d,2
lea ecx,[r10*1+rcx]
and r15d,esi
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((144-128))+rdi]
xor r14d,r12d
xor r15d,eax
xor r14d,r13d
lea r10d,[r15*1+r10]
mov r12d,edx
add r9d,DWORD[((8+16))+rbp]
and r12d,ecx
rorx r13d,ecx,25
rorx r15d,ecx,11
lea r10d,[r14*1+r10]
lea r9d,[r12*1+r9]
andn r12d,ecx,r8d
xor r13d,r15d
rorx r14d,ecx,6
lea r9d,[r12*1+r9]
xor r13d,r14d
mov r15d,r10d
rorx r12d,r10d,22
lea r9d,[r13*1+r9]
xor r15d,r11d
rorx r14d,r10d,13
rorx r13d,r10d,2
lea ebx,[r9*1+rbx]
and esi,r15d
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((160-128))+rdi]
xor r14d,r12d
xor esi,r11d
xor r14d,r13d
lea r9d,[rsi*1+r9]
mov r12d,ecx
add r8d,DWORD[((12+16))+rbp]
and r12d,ebx
rorx r13d,ebx,25
rorx esi,ebx,11
lea r9d,[r14*1+r9]
lea r8d,[r12*1+r8]
andn r12d,ebx,edx
xor r13d,esi
rorx r14d,ebx,6
lea r8d,[r12*1+r8]
xor r13d,r14d
mov esi,r9d
rorx r12d,r9d,22
lea r8d,[r13*1+r8]
xor esi,r10d
rorx r14d,r9d,13
rorx r13d,r9d,2
lea eax,[r8*1+rax]
and r15d,esi
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((176-128))+rdi]
xor r14d,r12d
xor r15d,r10d
xor r14d,r13d
lea r8d,[r15*1+r8]
mov r12d,ebx
add edx,DWORD[((32+16))+rbp]
and r12d,eax
rorx r13d,eax,25
rorx r15d,eax,11
lea r8d,[r14*1+r8]
lea edx,[r12*1+rdx]
andn r12d,eax,ecx
xor r13d,r15d
rorx r14d,eax,6
lea edx,[r12*1+rdx]
xor r13d,r14d
mov r15d,r8d
rorx r12d,r8d,22
lea edx,[r13*1+rdx]
xor r15d,r9d
rorx r14d,r8d,13
rorx r13d,r8d,2
lea r11d,[rdx*1+r11]
and esi,r15d
vpand xmm8,xmm11,xmm12
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((192-128))+rdi]
xor r14d,r12d
xor esi,r9d
xor r14d,r13d
lea edx,[rsi*1+rdx]
mov r12d,eax
add ecx,DWORD[((36+16))+rbp]
and r12d,r11d
rorx r13d,r11d,25
rorx esi,r11d,11
lea edx,[r14*1+rdx]
lea ecx,[r12*1+rcx]
andn r12d,r11d,ebx
xor r13d,esi
rorx r14d,r11d,6
lea ecx,[r12*1+rcx]
xor r13d,r14d
mov esi,edx
rorx r12d,edx,22
lea ecx,[r13*1+rcx]
xor esi,r8d
rorx r14d,edx,13
rorx r13d,edx,2
lea r10d,[rcx*1+r10]
and r15d,esi
vaesenclast xmm11,xmm9,xmm10
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((208-128))+rdi]
xor r14d,r12d
xor r15d,r8d
xor r14d,r13d
lea ecx,[r15*1+rcx]
mov r12d,r11d
add ebx,DWORD[((40+16))+rbp]
and r12d,r10d
rorx r13d,r10d,25
rorx r15d,r10d,11
lea ecx,[r14*1+rcx]
lea ebx,[r12*1+rbx]
andn r12d,r10d,eax
xor r13d,r15d
rorx r14d,r10d,6
lea ebx,[r12*1+rbx]
xor r13d,r14d
mov r15d,ecx
rorx r12d,ecx,22
lea ebx,[r13*1+rbx]
xor r15d,edx
rorx r14d,ecx,13
rorx r13d,ecx,2
lea r9d,[rbx*1+r9]
and esi,r15d
vpand xmm11,xmm11,xmm13
vaesenc xmm9,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((224-128))+rdi]
xor r14d,r12d
xor esi,edx
xor r14d,r13d
lea ebx,[rsi*1+rbx]
mov r12d,r10d
add eax,DWORD[((44+16))+rbp]
and r12d,r9d
rorx r13d,r9d,25
rorx esi,r9d,11
lea ebx,[r14*1+rbx]
lea eax,[r12*1+rax]
andn r12d,r9d,r11d
xor r13d,esi
rorx r14d,r9d,6
lea eax,[r12*1+rax]
xor r13d,r14d
mov esi,ebx
rorx r12d,ebx,22
lea eax,[r13*1+rax]
xor esi,ecx
rorx r14d,ebx,13
rorx r13d,ebx,2
lea r8d,[rax*1+r8]
and r15d,esi
vpor xmm8,xmm8,xmm11
vaesenclast xmm11,xmm9,xmm10
vmovdqu xmm10,XMMWORD[((0-128))+rdi]
xor r14d,r12d
xor r15d,ecx
xor r14d,r13d
lea eax,[r15*1+rax]
mov r12d,r9d
vmovq r13,xmm15
vpextrq r15,xmm15,1
vpand xmm11,xmm11,xmm14
vpor xmm8,xmm8,xmm11
lea rbp,[((-64))+rbp]
vmovdqu XMMWORD[r13*1+r15],xmm8
lea r13,[16+r13]
cmp rbp,rsp
jae NEAR $L$ower_avx2
mov r15,QWORD[552+rsp]
lea r13,[64+r13]
mov rsi,QWORD[560+rsp]
add eax,r14d
lea rsp,[448+rsp]
add eax,DWORD[r15]
add ebx,DWORD[4+r15]
add ecx,DWORD[8+r15]
add edx,DWORD[12+r15]
add r8d,DWORD[16+r15]
add r9d,DWORD[20+r15]
add r10d,DWORD[24+r15]
lea r12,[r13*1+rsi]
add r11d,DWORD[28+r15]
cmp r13,QWORD[((64+16))+rsp]
mov DWORD[r15],eax
cmove r12,rsp
mov DWORD[4+r15],ebx
mov DWORD[8+r15],ecx
mov DWORD[12+r15],edx
mov DWORD[16+r15],r8d
mov DWORD[20+r15],r9d
mov DWORD[24+r15],r10d
mov DWORD[28+r15],r11d
jbe NEAR $L$oop_avx2
lea rbp,[rsp]
$L$done_avx2:
lea rsp,[rbp]
mov r8,QWORD[((64+32))+rsp]
mov rsi,QWORD[((64+56))+rsp]
vmovdqu XMMWORD[r8],xmm8
vzeroall
movaps xmm6,XMMWORD[128+rsp]
movaps xmm7,XMMWORD[144+rsp]
movaps xmm8,XMMWORD[160+rsp]
movaps xmm9,XMMWORD[176+rsp]
movaps xmm10,XMMWORD[192+rsp]
movaps xmm11,XMMWORD[208+rsp]
movaps xmm12,XMMWORD[224+rsp]
movaps xmm13,XMMWORD[240+rsp]
movaps xmm14,XMMWORD[256+rsp]
movaps xmm15,XMMWORD[272+rsp]
mov r15,QWORD[rsi]
mov r14,QWORD[8+rsi]
mov r13,QWORD[16+rsi]
mov r12,QWORD[24+rsi]
mov rbp,QWORD[32+rsi]
mov rbx,QWORD[40+rsi]
lea rsp,[48+rsi]
$L$epilogue_avx2:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_aesni_cbc_sha256_enc_avx2:
ALIGN 32
aesni_cbc_sha256_enc_shaext:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_aesni_cbc_sha256_enc_shaext:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
mov rcx,r9
mov r8,QWORD[40+rsp]
mov r9,QWORD[48+rsp]
mov r10,QWORD[56+rsp]
lea rsp,[((-168))+rsp]
movaps XMMWORD[(-8-160)+rax],xmm6
movaps XMMWORD[(-8-144)+rax],xmm7
movaps XMMWORD[(-8-128)+rax],xmm8
movaps XMMWORD[(-8-112)+rax],xmm9
movaps XMMWORD[(-8-96)+rax],xmm10
movaps XMMWORD[(-8-80)+rax],xmm11
movaps XMMWORD[(-8-64)+rax],xmm12
movaps XMMWORD[(-8-48)+rax],xmm13
movaps XMMWORD[(-8-32)+rax],xmm14
movaps XMMWORD[(-8-16)+rax],xmm15
$L$prologue_shaext:
lea rax,[((K256+128))]
movdqu xmm1,XMMWORD[r9]
movdqu xmm2,XMMWORD[16+r9]
movdqa xmm3,XMMWORD[((512-128))+rax]
mov r11d,DWORD[240+rcx]
sub rsi,rdi
movups xmm15,XMMWORD[rcx]
movups xmm6,XMMWORD[r8]
movups xmm4,XMMWORD[16+rcx]
lea rcx,[112+rcx]
pshufd xmm0,xmm1,0x1b
pshufd xmm1,xmm1,0xb1
pshufd xmm2,xmm2,0x1b
movdqa xmm7,xmm3
DB 102,15,58,15,202,8
punpcklqdq xmm2,xmm0
jmp NEAR $L$oop_shaext
ALIGN 16
$L$oop_shaext:
movdqu xmm10,XMMWORD[r10]
movdqu xmm11,XMMWORD[16+r10]
movdqu xmm12,XMMWORD[32+r10]
DB 102,68,15,56,0,211
movdqu xmm13,XMMWORD[48+r10]
movdqa xmm0,XMMWORD[((0-128))+rax]
paddd xmm0,xmm10
DB 102,68,15,56,0,219
movdqa xmm9,xmm2
movdqa xmm8,xmm1
movups xmm14,XMMWORD[rdi]
xorps xmm14,xmm15
xorps xmm6,xmm14
movups xmm5,XMMWORD[((-80))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movups xmm4,XMMWORD[((-64))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,202
movdqa xmm0,XMMWORD[((32-128))+rax]
paddd xmm0,xmm11
DB 102,68,15,56,0,227
lea r10,[64+r10]
movups xmm5,XMMWORD[((-48))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movups xmm4,XMMWORD[((-32))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,202
movdqa xmm0,XMMWORD[((64-128))+rax]
paddd xmm0,xmm12
DB 102,68,15,56,0,235
DB 69,15,56,204,211
movups xmm5,XMMWORD[((-16))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm13
DB 102,65,15,58,15,220,4
paddd xmm10,xmm3
movups xmm4,XMMWORD[rcx]
aesenc xmm6,xmm5
DB 15,56,203,202
movdqa xmm0,XMMWORD[((96-128))+rax]
paddd xmm0,xmm13
DB 69,15,56,205,213
DB 69,15,56,204,220
movups xmm5,XMMWORD[16+rcx]
aesenc xmm6,xmm4
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movups xmm4,XMMWORD[32+rcx]
aesenc xmm6,xmm5
movdqa xmm3,xmm10
DB 102,65,15,58,15,221,4
paddd xmm11,xmm3
DB 15,56,203,202
movdqa xmm0,XMMWORD[((128-128))+rax]
paddd xmm0,xmm10
DB 69,15,56,205,218
DB 69,15,56,204,229
movups xmm5,XMMWORD[48+rcx]
aesenc xmm6,xmm4
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm11
DB 102,65,15,58,15,218,4
paddd xmm12,xmm3
cmp r11d,11
jb NEAR $L$aesenclast1
movups xmm4,XMMWORD[64+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[80+rcx]
aesenc xmm6,xmm4
je NEAR $L$aesenclast1
movups xmm4,XMMWORD[96+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[112+rcx]
aesenc xmm6,xmm4
$L$aesenclast1:
aesenclast xmm6,xmm5
movups xmm4,XMMWORD[((16-112))+rcx]
nop
DB 15,56,203,202
movups xmm14,XMMWORD[16+rdi]
xorps xmm14,xmm15
movups XMMWORD[rdi*1+rsi],xmm6
xorps xmm6,xmm14
movups xmm5,XMMWORD[((-80))+rcx]
aesenc xmm6,xmm4
movdqa xmm0,XMMWORD[((160-128))+rax]
paddd xmm0,xmm11
DB 69,15,56,205,227
DB 69,15,56,204,234
movups xmm4,XMMWORD[((-64))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm12
DB 102,65,15,58,15,219,4
paddd xmm13,xmm3
movups xmm5,XMMWORD[((-48))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((192-128))+rax]
paddd xmm0,xmm12
DB 69,15,56,205,236
DB 69,15,56,204,211
movups xmm4,XMMWORD[((-32))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm13
DB 102,65,15,58,15,220,4
paddd xmm10,xmm3
movups xmm5,XMMWORD[((-16))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((224-128))+rax]
paddd xmm0,xmm13
DB 69,15,56,205,213
DB 69,15,56,204,220
movups xmm4,XMMWORD[rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm10
DB 102,65,15,58,15,221,4
paddd xmm11,xmm3
movups xmm5,XMMWORD[16+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((256-128))+rax]
paddd xmm0,xmm10
DB 69,15,56,205,218
DB 69,15,56,204,229
movups xmm4,XMMWORD[32+rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm11
DB 102,65,15,58,15,218,4
paddd xmm12,xmm3
movups xmm5,XMMWORD[48+rcx]
aesenc xmm6,xmm4
cmp r11d,11
jb NEAR $L$aesenclast2
movups xmm4,XMMWORD[64+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[80+rcx]
aesenc xmm6,xmm4
je NEAR $L$aesenclast2
movups xmm4,XMMWORD[96+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[112+rcx]
aesenc xmm6,xmm4
$L$aesenclast2:
aesenclast xmm6,xmm5
movups xmm4,XMMWORD[((16-112))+rcx]
nop
DB 15,56,203,202
movups xmm14,XMMWORD[32+rdi]
xorps xmm14,xmm15
movups XMMWORD[16+rdi*1+rsi],xmm6
xorps xmm6,xmm14
movups xmm5,XMMWORD[((-80))+rcx]
aesenc xmm6,xmm4
movdqa xmm0,XMMWORD[((288-128))+rax]
paddd xmm0,xmm11
DB 69,15,56,205,227
DB 69,15,56,204,234
movups xmm4,XMMWORD[((-64))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm12
DB 102,65,15,58,15,219,4
paddd xmm13,xmm3
movups xmm5,XMMWORD[((-48))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((320-128))+rax]
paddd xmm0,xmm12
DB 69,15,56,205,236
DB 69,15,56,204,211
movups xmm4,XMMWORD[((-32))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm13
DB 102,65,15,58,15,220,4
paddd xmm10,xmm3
movups xmm5,XMMWORD[((-16))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((352-128))+rax]
paddd xmm0,xmm13
DB 69,15,56,205,213
DB 69,15,56,204,220
movups xmm4,XMMWORD[rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm10
DB 102,65,15,58,15,221,4
paddd xmm11,xmm3
movups xmm5,XMMWORD[16+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((384-128))+rax]
paddd xmm0,xmm10
DB 69,15,56,205,218
DB 69,15,56,204,229
movups xmm4,XMMWORD[32+rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm11
DB 102,65,15,58,15,218,4
paddd xmm12,xmm3
movups xmm5,XMMWORD[48+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movdqa xmm0,XMMWORD[((416-128))+rax]
paddd xmm0,xmm11
DB 69,15,56,205,227
DB 69,15,56,204,234
cmp r11d,11
jb NEAR $L$aesenclast3
movups xmm4,XMMWORD[64+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[80+rcx]
aesenc xmm6,xmm4
je NEAR $L$aesenclast3
movups xmm4,XMMWORD[96+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[112+rcx]
aesenc xmm6,xmm4
$L$aesenclast3:
aesenclast xmm6,xmm5
movups xmm4,XMMWORD[((16-112))+rcx]
nop
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movdqa xmm3,xmm12
DB 102,65,15,58,15,219,4
paddd xmm13,xmm3
movups xmm14,XMMWORD[48+rdi]
xorps xmm14,xmm15
movups XMMWORD[32+rdi*1+rsi],xmm6
xorps xmm6,xmm14
movups xmm5,XMMWORD[((-80))+rcx]
aesenc xmm6,xmm4
movups xmm4,XMMWORD[((-64))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,202
movdqa xmm0,XMMWORD[((448-128))+rax]
paddd xmm0,xmm12
DB 69,15,56,205,236
movdqa xmm3,xmm7
movups xmm5,XMMWORD[((-48))+rcx]
aesenc xmm6,xmm4
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movups xmm4,XMMWORD[((-32))+rcx]
aesenc xmm6,xmm5
DB 15,56,203,202
movdqa xmm0,XMMWORD[((480-128))+rax]
paddd xmm0,xmm13
movups xmm5,XMMWORD[((-16))+rcx]
aesenc xmm6,xmm4
movups xmm4,XMMWORD[rcx]
aesenc xmm6,xmm5
DB 15,56,203,209
pshufd xmm0,xmm0,0x0e
movups xmm5,XMMWORD[16+rcx]
aesenc xmm6,xmm4
DB 15,56,203,202
movups xmm4,XMMWORD[32+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[48+rcx]
aesenc xmm6,xmm4
cmp r11d,11
jb NEAR $L$aesenclast4
movups xmm4,XMMWORD[64+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[80+rcx]
aesenc xmm6,xmm4
je NEAR $L$aesenclast4
movups xmm4,XMMWORD[96+rcx]
aesenc xmm6,xmm5
movups xmm5,XMMWORD[112+rcx]
aesenc xmm6,xmm4
$L$aesenclast4:
aesenclast xmm6,xmm5
movups xmm4,XMMWORD[((16-112))+rcx]
nop
paddd xmm2,xmm9
paddd xmm1,xmm8
dec rdx
movups XMMWORD[48+rdi*1+rsi],xmm6
lea rdi,[64+rdi]
jnz NEAR $L$oop_shaext
pshufd xmm2,xmm2,0xb1
pshufd xmm3,xmm1,0x1b
pshufd xmm1,xmm1,0xb1
punpckhqdq xmm1,xmm2
DB 102,15,58,15,211,8
movups XMMWORD[r8],xmm6
movdqu XMMWORD[r9],xmm1
movdqu XMMWORD[16+r9],xmm2
movaps xmm6,XMMWORD[rsp]
movaps xmm7,XMMWORD[16+rsp]
movaps xmm8,XMMWORD[32+rsp]
movaps xmm9,XMMWORD[48+rsp]
movaps xmm10,XMMWORD[64+rsp]
movaps xmm11,XMMWORD[80+rsp]
movaps xmm12,XMMWORD[96+rsp]
movaps xmm13,XMMWORD[112+rsp]
movaps xmm14,XMMWORD[128+rsp]
movaps xmm15,XMMWORD[144+rsp]
lea rsp,[((8+160))+rsp]
$L$epilogue_shaext:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_aesni_cbc_sha256_enc_shaext:
EXTERN __imp_RtlVirtualUnwind
ALIGN 16
se_handler:
push rsi
push rdi
push rbx
push rbp
push r12
push r13
push r14
push r15
pushfq
sub rsp,64
mov rax,QWORD[120+r8]
mov rbx,QWORD[248+r8]
mov rsi,QWORD[8+r9]
mov r11,QWORD[56+r9]
mov r10d,DWORD[r11]
lea r10,[r10*1+rsi]
cmp rbx,r10
jb NEAR $L$in_prologue
mov rax,QWORD[152+r8]
mov r10d,DWORD[4+r11]
lea r10,[r10*1+rsi]
cmp rbx,r10
jae NEAR $L$in_prologue
lea r10,[aesni_cbc_sha256_enc_shaext]
cmp rbx,r10
jb NEAR $L$not_in_shaext
lea rsi,[rax]
lea rdi,[512+r8]
mov ecx,20
DD 0xa548f3fc
lea rax,[168+rax]
jmp NEAR $L$in_prologue
$L$not_in_shaext:
lea r10,[$L$avx2_shortcut]
cmp rbx,r10
jb NEAR $L$not_in_avx2
and rax,-256*4
add rax,448
$L$not_in_avx2:
mov rsi,rax
mov rax,QWORD[((64+56))+rax]
lea rax,[48+rax]
mov rbx,QWORD[((-8))+rax]
mov rbp,QWORD[((-16))+rax]
mov r12,QWORD[((-24))+rax]
mov r13,QWORD[((-32))+rax]
mov r14,QWORD[((-40))+rax]
mov r15,QWORD[((-48))+rax]
mov QWORD[144+r8],rbx
mov QWORD[160+r8],rbp
mov QWORD[216+r8],r12
mov QWORD[224+r8],r13
mov QWORD[232+r8],r14
mov QWORD[240+r8],r15
lea rsi,[((64+64))+rsi]
lea rdi,[512+r8]
mov ecx,20
DD 0xa548f3fc
$L$in_prologue:
mov rdi,QWORD[8+rax]
mov rsi,QWORD[16+rax]
mov QWORD[152+r8],rax
mov QWORD[168+r8],rsi
mov QWORD[176+r8],rdi
mov rdi,QWORD[40+r9]
mov rsi,r8
mov ecx,154
DD 0xa548f3fc
mov rsi,r9
xor rcx,rcx
mov rdx,QWORD[8+rsi]
mov r8,QWORD[rsi]
mov r9,QWORD[16+rsi]
mov r10,QWORD[40+rsi]
lea r11,[56+rsi]
lea r12,[24+rsi]
mov QWORD[32+rsp],r10
mov QWORD[40+rsp],r11
mov QWORD[48+rsp],r12
mov QWORD[56+rsp],rcx
call QWORD[__imp_RtlVirtualUnwind]
mov eax,1
add rsp,64
popfq
pop r15
pop r14
pop r13
pop r12
pop rbp
pop rbx
pop rdi
pop rsi
DB 0F3h,0C3h ;repret
section .pdata rdata align=4
DD $L$SEH_begin_aesni_cbc_sha256_enc_xop wrt ..imagebase
DD $L$SEH_end_aesni_cbc_sha256_enc_xop wrt ..imagebase
DD $L$SEH_info_aesni_cbc_sha256_enc_xop wrt ..imagebase
DD $L$SEH_begin_aesni_cbc_sha256_enc_avx wrt ..imagebase
DD $L$SEH_end_aesni_cbc_sha256_enc_avx wrt ..imagebase
DD $L$SEH_info_aesni_cbc_sha256_enc_avx wrt ..imagebase
DD $L$SEH_begin_aesni_cbc_sha256_enc_avx2 wrt ..imagebase
DD $L$SEH_end_aesni_cbc_sha256_enc_avx2 wrt ..imagebase
DD $L$SEH_info_aesni_cbc_sha256_enc_avx2 wrt ..imagebase
DD $L$SEH_begin_aesni_cbc_sha256_enc_shaext wrt ..imagebase
DD $L$SEH_end_aesni_cbc_sha256_enc_shaext wrt ..imagebase
DD $L$SEH_info_aesni_cbc_sha256_enc_shaext wrt ..imagebase
section .xdata rdata align=8
ALIGN 8
$L$SEH_info_aesni_cbc_sha256_enc_xop:
DB 9,0,0,0
DD se_handler wrt ..imagebase
DD $L$prologue_xop wrt ..imagebase,$L$epilogue_xop wrt ..imagebase
$L$SEH_info_aesni_cbc_sha256_enc_avx:
DB 9,0,0,0
DD se_handler wrt ..imagebase
DD $L$prologue_avx wrt ..imagebase,$L$epilogue_avx wrt ..imagebase
$L$SEH_info_aesni_cbc_sha256_enc_avx2:
DB 9,0,0,0
DD se_handler wrt ..imagebase
DD $L$prologue_avx2 wrt ..imagebase,$L$epilogue_avx2 wrt ..imagebase
$L$SEH_info_aesni_cbc_sha256_enc_shaext:
DB 9,0,0,0
DD se_handler wrt ..imagebase
DD $L$prologue_shaext wrt ..imagebase,$L$epilogue_shaext wrt ..imagebase
| MTASZTAKI/ApertusVR | plugins/languageAPI/jsAPI/3rdParty/nodejs/10.1.0/source/deps/openssl/config/archs/VC-WIN64A/asm/crypto/aes/aesni-sha256-x86_64.asm | Assembly | mit | 88,110 |
[bits 32]
dd 9690
db "TEXT", 0
db "iConsole", 0 | jaredwhitney/os3 | _not os code/image/consoleMount.asm | Assembly | mit | 47 |
;
; VIDEO.ASM
;
; (c) Copyright 2001, P. Jakubco ml.
;
; Display adapter & video mode setup
;
;
;
.model compact
.386p
.data
nA db ?
.code
start:
cld
mov byte ptr [nA], 0 ;Na zaciatku nemame nic
mov ah, 12h
mov bh, 10h ;bl?
int 10h
test bl, 0FCh
jnz @basic_ret
mov byte ptr [nA],1 ;Zatial mame EGA
mov ax, 1A00h
int 10h
cmp al, 1Ah
jne @CGA
mov byte ptr [nA],2 ;A sme na konci - mame VGA adapter
jmp short @basic_ret
@CGA:
segds
mov byte ptr [nA],0
@basic_ret:
mov al, byte ptr [nA]
xor ah, ah
xor bh, bh
mov ah, 0eh
cmp al, 0
jne @eg
mov al, 'C'
int 10h
mov al, 'G'
int 10h
mov al,'A'
int 10h
jmp short @exit
@eg:
cmp al, 1
jne @vg
mov al, 'E'
int 10h
mov al, 'G'
int 10h
mov al, 'A'
int 10h
jmp short @exit
@vg:
cmp al, 2
jne @exit
mov al, 'V'
int 10h
mov al,'G'
int 10h
mov al, 'A'
int 10h
@exit:
mov ax, 4c00h
int 21h
end start | vbmacher/qsOS | utils/hardware/video-adapter/video.asm | Assembly | apache-2.0 | 881 |
; PPU palette RAM read/write and mirroring test
; to do: check that upper two bits aren't stored
.include "prefix_ppu.a"
; Set VRAM address to $3f00 + X
; Preserved: A, X, Y
set_pal_addr:
pha
bit $2002
lda #$3f
sta $2006
txa
sta $2006
pla
rts
; Set palette entry X to A
; Preserved: A, X, Y
set_pal_entry:
jsr set_pal_addr
sta $2007
rts
; Read palette entry X into A
; Preserved: X, Y
get_pal_entry:
jsr set_pal_addr
lda $2007
and #$3f
rts
reset:
lda #50
jsr delay_msec
jsr wait_vbl
lda #0
sta $2000
sta $2001
lda #2;) Palette read shouldn't be buffered like other VRAM
sta result
ldx #$00
lda #$12
jsr set_pal_entry
lda #$34
sta $2007
jsr get_pal_entry
lda $2007
cmp #$12
jsr error_if_eq
lda #3;) Palette write/read doesn't work
sta result
ldx #$00
lda #$34
jsr set_pal_entry
jsr get_pal_entry
lda $2007
cmp #$34
jsr error_if_ne
lda #4;) Palette should be mirrored within $3f00-$3fff
sta result
ldx #$00
lda #$12
jsr set_pal_entry
ldx #$e0
lda #$34
jsr set_pal_entry
ldx #$00
jsr get_pal_entry
cmp #$34
jsr error_if_ne
lda #5;) Write to $10 should be mirrored at $00
sta result
ldx #$00
lda #$12
jsr set_pal_entry
ldx #$10
lda #$34
jsr set_pal_entry
ldx #$00
jsr get_pal_entry
cmp #$34
jsr error_if_ne
lda #6;) Write to $00 should be mirrored at $10
sta result
ldx #$10
lda #$12
jsr set_pal_entry
ldx #$00
lda #$34
jsr set_pal_entry
ldx #$10
jsr get_pal_entry
cmp #$34
jsr error_if_ne
lda #1;) Tests passed
sta result
jmp report_final_result
| koenkivits/nesnes | test/ppu2/source/palette_ram.asm | Assembly | mit | 2,138 |
;*****************************************************************
;* - Description: Device definition file for RC Calibration
;* - File: m165P.asm
;* - AppNote: AVR053 - Production calibration of the
;* RC oscillator
;*
;* - Author: Atmel Corporation: http://www.atmel.com
;* Support email: avr@atmel.com
;*
;* $Name$
;* $Revision: 62 $
;* $RCSfile$
;* $Date: 2006-03-23 11:14:52 +0100 (to, 23 mar 2006) $
;*****************************************************************
.include "m165Pdef.inc"
.include "Common\memoryMap.inc"
.include "Device specific\m169_family_pinout.inc"
.equ OSC_VER = 4
.equ TCCR0 = TCCR0A
.equ TIFR = TIFR0
.equ MCUCSR = MCUCR
| smart-electro/BMS_SLAVE_V2.0 | Software/AtTiny_programmer/RC calib Projekt/Device specific/m165P.asm | Assembly | cc0-1.0 | 719 |
;==============================================================
; WLA-DX banking setup
;==============================================================
.memorymap
defaultslot 0
; rom area
slotsize $4000
slot 0 $0000
slot 1 $4000
slot 2 $8000
; ram area
slotsize $2000
slot 3 $C000
slot 4 $E000
.endme
.rombankmap
bankstotal 4
banksize $4000
banks 4
.endro
;==============================================================
; SDSC tag and SMS rom header
;==============================================================
.sdsctag 0.02,"S.A.M. - Simple Adventure Maker","Version 0.02 - Multi-script and sound support","Haroldo O. Pinheiro"
;==============================================================
; S.A.M. Includes
;==============================================================
.include "..\..\lib\Useful functions.inc"
.include "..\..\lib\SAM_Interpreter.asm"
.include "..\..\lib\math.asm"
.include "..\..\lib\joypad.asm"
.include "..\..\lib\sam_jumptable.asm"
.include "..\..\lib\sam_instructions.asm"
.include "..\..\lib\sprite.asm"
.include "..\..\lib\resource.asm"
.include "..\..\lib\Phantasy Star decompressors.inc"
.section "PSGMOD Code" FREE
.include "..\..\lib\psgmod.inc"
.include "..\..\lib\psgmod.asm"
.ends
.section "Data" FREE
PaletteData:
.db $00,$3f ; Black, White
PaletteDataEnd:
FontData:
.include "..\..\lib\BBC Micro font.inc"
.ends
.include "Script.list.txt.inc"
.include "Music.list.txt.inc"
.slot 0
.include "Images.txt.inc"
.SLOT 2
.section "PSGMOD Vibrato" SUPERFREE
PSGMOD_VIBRATO_TABLES:
.incbin "..\..\lib\psgmod.vib"
.ends
| haroldo-ok/sam | example/first_test/game.asm | Assembly | apache-2.0 | 1,697 |
; This macro creates a stub for an ISR which does NOT pass it's own
; error code (adds a dummy errcode byte).
%macro ISR_NOERRCODE 1
global int_%1
int_%1:
cli ; Disable interrupts firstly.
push byte 0 ; Push a dummy error code.
push byte %1 ; Push the interrupt number.
jmp isr_common_stub ; Go to our common handler code.
%endmacro
; This macro creates a stub for an ISR which passes it's own
; error code.
%macro ISR_ERRCODE 1
global int_%1
int_%1:
cli ; Disable interrupts.
push byte %1 ; Push the interrupt number
jmp isr_common_stub
%endmacro
ISR_NOERRCODE 0
ISR_NOERRCODE 1
ISR_NOERRCODE 2
ISR_NOERRCODE 3
ISR_NOERRCODE 4
ISR_NOERRCODE 5
ISR_NOERRCODE 6
ISR_NOERRCODE 7
ISR_ERRCODE 8
ISR_NOERRCODE 9
ISR_ERRCODE 10
ISR_ERRCODE 11
ISR_ERRCODE 12
ISR_ERRCODE 13
ISR_ERRCODE 14
ISR_NOERRCODE 15
ISR_NOERRCODE 16
ISR_NOERRCODE 17
ISR_NOERRCODE 18
ISR_NOERRCODE 19
ISR_NOERRCODE 20
ISR_NOERRCODE 21
ISR_NOERRCODE 22
ISR_NOERRCODE 23
ISR_NOERRCODE 24
ISR_NOERRCODE 25
ISR_NOERRCODE 26
ISR_NOERRCODE 27
ISR_NOERRCODE 28
ISR_NOERRCODE 29
ISR_NOERRCODE 30
ISR_NOERRCODE 31
ISR_NOERRCODE 32
ISR_NOERRCODE 33
ISR_NOERRCODE 34
ISR_NOERRCODE 35
ISR_NOERRCODE 36
ISR_NOERRCODE 37
ISR_NOERRCODE 38
ISR_NOERRCODE 39
ISR_NOERRCODE 40
ISR_NOERRCODE 41
ISR_NOERRCODE 42
ISR_NOERRCODE 43
ISR_NOERRCODE 44
ISR_NOERRCODE 45
ISR_NOERRCODE 46
ISR_NOERRCODE 47
ISR_NOERRCODE 48
ISR_NOERRCODE 49
ISR_NOERRCODE 50
ISR_NOERRCODE 51
ISR_NOERRCODE 52
ISR_NOERRCODE 53
ISR_NOERRCODE 54
ISR_NOERRCODE 55
ISR_NOERRCODE 56
ISR_NOERRCODE 57
ISR_NOERRCODE 58
ISR_NOERRCODE 59
ISR_NOERRCODE 60
ISR_NOERRCODE 61
ISR_NOERRCODE 62
ISR_NOERRCODE 63
; In isr.c
extern arch_exc_handler
; This is our common ISR stub. It saves the processor state, sets
; up for kernel mode segments, calls the C-level fault handler,
; and finally restores the stack frame.
isr_common_stub:
pusha ; Pushes edi,esi,ebp,esp,ebx,edx,ecx,eax
mov ax, ds ; Lower 16-bits of eax = ds.
push eax ; save the data segment descriptor
mov ax, 0x10 ; load the kernel data segment descriptor
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
call arch_exc_handler
pop ebx ; reload the original data segment descriptor
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
popa ; Pops edi,esi,ebp...
add esp, 8 ; Cleans up the pushed error code and pushed ISR number
sti
iret ; pops 5 things at once: CS, EIP, EFLAGS, SS, and ESP
| cycl0ne/poweros_x86 | system/exec/arch_x86/interrupt.asm | Assembly | apache-2.0 | 2,672 |
%ifidn __OUTPUT_FORMAT__,obj
section code use32 class=code align=64
%elifidn __OUTPUT_FORMAT__,win32
$@feat.00 equ 1
section .text code align=64
%else
section .text code
%endif
global _padlock_capability
align 16
_padlock_capability:
L$_padlock_capability_begin:
push ebx
pushfd
pop eax
mov ecx,eax
xor eax,2097152
push eax
popfd
pushfd
pop eax
xor ecx,eax
xor eax,eax
bt ecx,21
jnc NEAR L$000noluck
cpuid
xor eax,eax
cmp ebx,0x746e6543
jne NEAR L$000noluck
cmp edx,0x48727561
jne NEAR L$000noluck
cmp ecx,0x736c7561
jne NEAR L$000noluck
mov eax,3221225472
cpuid
mov edx,eax
xor eax,eax
cmp edx,3221225473
jb NEAR L$000noluck
mov eax,1
cpuid
or eax,15
xor ebx,ebx
and eax,4095
cmp eax,1791
sete bl
mov eax,3221225473
push ebx
cpuid
pop ebx
mov eax,edx
shl ebx,4
and eax,4294967279
or eax,ebx
L$000noluck:
pop ebx
ret
global _padlock_key_bswap
align 16
_padlock_key_bswap:
L$_padlock_key_bswap_begin:
mov edx,DWORD [4+esp]
mov ecx,DWORD [240+edx]
L$001bswap_loop:
mov eax,DWORD [edx]
bswap eax
mov DWORD [edx],eax
lea edx,[4+edx]
sub ecx,1
jnz NEAR L$001bswap_loop
ret
global _padlock_verify_context
align 16
_padlock_verify_context:
L$_padlock_verify_context_begin:
mov edx,DWORD [4+esp]
lea eax,[L$padlock_saved_context]
pushfd
call __padlock_verify_ctx
L$002verify_pic_point:
lea esp,[4+esp]
ret
align 16
__padlock_verify_ctx:
bt DWORD [4+esp],30
jnc NEAR L$003verified
cmp edx,DWORD [eax]
je NEAR L$003verified
pushfd
popfd
L$003verified:
mov DWORD [eax],edx
ret
global _padlock_reload_key
align 16
_padlock_reload_key:
L$_padlock_reload_key_begin:
pushfd
popfd
ret
global _padlock_aes_block
align 16
_padlock_aes_block:
L$_padlock_aes_block_begin:
push edi
push esi
push ebx
mov edi,DWORD [16+esp]
mov esi,DWORD [20+esp]
mov edx,DWORD [24+esp]
mov ecx,1
lea ebx,[32+edx]
lea edx,[16+edx]
db 243,15,167,200
pop ebx
pop esi
pop edi
ret
global _padlock_ecb_encrypt
align 16
_padlock_ecb_encrypt:
L$_padlock_ecb_encrypt_begin:
push ebp
push ebx
push esi
push edi
mov edi,DWORD [20+esp]
mov esi,DWORD [24+esp]
mov edx,DWORD [28+esp]
mov ecx,DWORD [32+esp]
test edx,15
jnz NEAR L$004ecb_abort
test ecx,15
jnz NEAR L$004ecb_abort
lea eax,[L$padlock_saved_context]
pushfd
cld
call __padlock_verify_ctx
L$005ecb_pic_point:
lea edx,[16+edx]
xor eax,eax
xor ebx,ebx
test DWORD [edx],32
jnz NEAR L$006ecb_aligned
test edi,15
setz al
test esi,15
setz bl
test eax,ebx
jnz NEAR L$006ecb_aligned
neg eax
mov ebx,512
not eax
lea ebp,[esp-24]
cmp ecx,ebx
cmovc ebx,ecx
and eax,ebx
mov ebx,ecx
neg eax
and ebx,511
lea esp,[ebp*1+eax]
mov eax,512
cmovz ebx,eax
mov eax,ebp
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
cmp ecx,ebx
ja NEAR L$007ecb_loop
mov eax,esi
cmp ebp,esp
cmove eax,edi
add eax,ecx
neg eax
and eax,4095
cmp eax,128
mov eax,-128
cmovae eax,ebx
and ebx,eax
jz NEAR L$008ecb_unaligned_tail
jmp NEAR L$007ecb_loop
align 16
L$007ecb_loop:
mov DWORD [ebp],edi
mov DWORD [4+ebp],esi
mov DWORD [8+ebp],ecx
mov ecx,ebx
mov DWORD [12+ebp],ebx
test edi,15
cmovnz edi,esp
test esi,15
jz NEAR L$009ecb_inp_aligned
shr ecx,2
db 243,165
sub edi,ebx
mov ecx,ebx
mov esi,edi
L$009ecb_inp_aligned:
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,200
mov edi,DWORD [ebp]
mov ebx,DWORD [12+ebp]
test edi,15
jz NEAR L$010ecb_out_aligned
mov ecx,ebx
lea esi,[esp]
shr ecx,2
db 243,165
sub edi,ebx
L$010ecb_out_aligned:
mov esi,DWORD [4+ebp]
mov ecx,DWORD [8+ebp]
add edi,ebx
add esi,ebx
sub ecx,ebx
mov ebx,512
jz NEAR L$011ecb_break
cmp ecx,ebx
jae NEAR L$007ecb_loop
L$008ecb_unaligned_tail:
xor eax,eax
cmp esp,ebp
cmove eax,ecx
sub esp,eax
mov eax,edi
mov ebx,ecx
shr ecx,2
lea edi,[esp]
db 243,165
mov esi,esp
mov edi,eax
mov ecx,ebx
jmp NEAR L$007ecb_loop
align 16
L$011ecb_break:
cmp esp,ebp
je NEAR L$012ecb_done
pxor xmm0,xmm0
lea eax,[esp]
L$013ecb_bzero:
movaps [eax],xmm0
lea eax,[16+eax]
cmp ebp,eax
ja NEAR L$013ecb_bzero
L$012ecb_done:
mov ebp,DWORD [16+ebp]
lea esp,[24+ebp]
jmp NEAR L$014ecb_exit
align 16
L$006ecb_aligned:
lea ebp,[ecx*1+esi]
neg ebp
and ebp,4095
xor eax,eax
cmp ebp,128
mov ebp,127
cmovae ebp,eax
and ebp,ecx
sub ecx,ebp
jz NEAR L$015ecb_aligned_tail
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,200
test ebp,ebp
jz NEAR L$014ecb_exit
L$015ecb_aligned_tail:
mov ecx,ebp
lea ebp,[esp-24]
mov esp,ebp
mov eax,ebp
sub esp,ecx
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
mov eax,edi
mov ebx,ecx
shr ecx,2
lea edi,[esp]
db 243,165
mov esi,esp
mov edi,eax
mov ecx,ebx
jmp NEAR L$007ecb_loop
L$014ecb_exit:
mov eax,1
lea esp,[4+esp]
L$004ecb_abort:
pop edi
pop esi
pop ebx
pop ebp
ret
global _padlock_cbc_encrypt
align 16
_padlock_cbc_encrypt:
L$_padlock_cbc_encrypt_begin:
push ebp
push ebx
push esi
push edi
mov edi,DWORD [20+esp]
mov esi,DWORD [24+esp]
mov edx,DWORD [28+esp]
mov ecx,DWORD [32+esp]
test edx,15
jnz NEAR L$016cbc_abort
test ecx,15
jnz NEAR L$016cbc_abort
lea eax,[L$padlock_saved_context]
pushfd
cld
call __padlock_verify_ctx
L$017cbc_pic_point:
lea edx,[16+edx]
xor eax,eax
xor ebx,ebx
test DWORD [edx],32
jnz NEAR L$018cbc_aligned
test edi,15
setz al
test esi,15
setz bl
test eax,ebx
jnz NEAR L$018cbc_aligned
neg eax
mov ebx,512
not eax
lea ebp,[esp-24]
cmp ecx,ebx
cmovc ebx,ecx
and eax,ebx
mov ebx,ecx
neg eax
and ebx,511
lea esp,[ebp*1+eax]
mov eax,512
cmovz ebx,eax
mov eax,ebp
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
cmp ecx,ebx
ja NEAR L$019cbc_loop
mov eax,esi
cmp ebp,esp
cmove eax,edi
add eax,ecx
neg eax
and eax,4095
cmp eax,64
mov eax,-64
cmovae eax,ebx
and ebx,eax
jz NEAR L$020cbc_unaligned_tail
jmp NEAR L$019cbc_loop
align 16
L$019cbc_loop:
mov DWORD [ebp],edi
mov DWORD [4+ebp],esi
mov DWORD [8+ebp],ecx
mov ecx,ebx
mov DWORD [12+ebp],ebx
test edi,15
cmovnz edi,esp
test esi,15
jz NEAR L$021cbc_inp_aligned
shr ecx,2
db 243,165
sub edi,ebx
mov ecx,ebx
mov esi,edi
L$021cbc_inp_aligned:
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,208
movaps xmm0,[eax]
movaps [edx-16],xmm0
mov edi,DWORD [ebp]
mov ebx,DWORD [12+ebp]
test edi,15
jz NEAR L$022cbc_out_aligned
mov ecx,ebx
lea esi,[esp]
shr ecx,2
db 243,165
sub edi,ebx
L$022cbc_out_aligned:
mov esi,DWORD [4+ebp]
mov ecx,DWORD [8+ebp]
add edi,ebx
add esi,ebx
sub ecx,ebx
mov ebx,512
jz NEAR L$023cbc_break
cmp ecx,ebx
jae NEAR L$019cbc_loop
L$020cbc_unaligned_tail:
xor eax,eax
cmp esp,ebp
cmove eax,ecx
sub esp,eax
mov eax,edi
mov ebx,ecx
shr ecx,2
lea edi,[esp]
db 243,165
mov esi,esp
mov edi,eax
mov ecx,ebx
jmp NEAR L$019cbc_loop
align 16
L$023cbc_break:
cmp esp,ebp
je NEAR L$024cbc_done
pxor xmm0,xmm0
lea eax,[esp]
L$025cbc_bzero:
movaps [eax],xmm0
lea eax,[16+eax]
cmp ebp,eax
ja NEAR L$025cbc_bzero
L$024cbc_done:
mov ebp,DWORD [16+ebp]
lea esp,[24+ebp]
jmp NEAR L$026cbc_exit
align 16
L$018cbc_aligned:
lea ebp,[ecx*1+esi]
neg ebp
and ebp,4095
xor eax,eax
cmp ebp,64
mov ebp,63
cmovae ebp,eax
and ebp,ecx
sub ecx,ebp
jz NEAR L$027cbc_aligned_tail
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,208
movaps xmm0,[eax]
movaps [edx-16],xmm0
test ebp,ebp
jz NEAR L$026cbc_exit
L$027cbc_aligned_tail:
mov ecx,ebp
lea ebp,[esp-24]
mov esp,ebp
mov eax,ebp
sub esp,ecx
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
mov eax,edi
mov ebx,ecx
shr ecx,2
lea edi,[esp]
db 243,165
mov esi,esp
mov edi,eax
mov ecx,ebx
jmp NEAR L$019cbc_loop
L$026cbc_exit:
mov eax,1
lea esp,[4+esp]
L$016cbc_abort:
pop edi
pop esi
pop ebx
pop ebp
ret
global _padlock_cfb_encrypt
align 16
_padlock_cfb_encrypt:
L$_padlock_cfb_encrypt_begin:
push ebp
push ebx
push esi
push edi
mov edi,DWORD [20+esp]
mov esi,DWORD [24+esp]
mov edx,DWORD [28+esp]
mov ecx,DWORD [32+esp]
test edx,15
jnz NEAR L$028cfb_abort
test ecx,15
jnz NEAR L$028cfb_abort
lea eax,[L$padlock_saved_context]
pushfd
cld
call __padlock_verify_ctx
L$029cfb_pic_point:
lea edx,[16+edx]
xor eax,eax
xor ebx,ebx
test DWORD [edx],32
jnz NEAR L$030cfb_aligned
test edi,15
setz al
test esi,15
setz bl
test eax,ebx
jnz NEAR L$030cfb_aligned
neg eax
mov ebx,512
not eax
lea ebp,[esp-24]
cmp ecx,ebx
cmovc ebx,ecx
and eax,ebx
mov ebx,ecx
neg eax
and ebx,511
lea esp,[ebp*1+eax]
mov eax,512
cmovz ebx,eax
mov eax,ebp
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
jmp NEAR L$031cfb_loop
align 16
L$031cfb_loop:
mov DWORD [ebp],edi
mov DWORD [4+ebp],esi
mov DWORD [8+ebp],ecx
mov ecx,ebx
mov DWORD [12+ebp],ebx
test edi,15
cmovnz edi,esp
test esi,15
jz NEAR L$032cfb_inp_aligned
shr ecx,2
db 243,165
sub edi,ebx
mov ecx,ebx
mov esi,edi
L$032cfb_inp_aligned:
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,224
movaps xmm0,[eax]
movaps [edx-16],xmm0
mov edi,DWORD [ebp]
mov ebx,DWORD [12+ebp]
test edi,15
jz NEAR L$033cfb_out_aligned
mov ecx,ebx
lea esi,[esp]
shr ecx,2
db 243,165
sub edi,ebx
L$033cfb_out_aligned:
mov esi,DWORD [4+ebp]
mov ecx,DWORD [8+ebp]
add edi,ebx
add esi,ebx
sub ecx,ebx
mov ebx,512
jnz NEAR L$031cfb_loop
cmp esp,ebp
je NEAR L$034cfb_done
pxor xmm0,xmm0
lea eax,[esp]
L$035cfb_bzero:
movaps [eax],xmm0
lea eax,[16+eax]
cmp ebp,eax
ja NEAR L$035cfb_bzero
L$034cfb_done:
mov ebp,DWORD [16+ebp]
lea esp,[24+ebp]
jmp NEAR L$036cfb_exit
align 16
L$030cfb_aligned:
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,224
movaps xmm0,[eax]
movaps [edx-16],xmm0
L$036cfb_exit:
mov eax,1
lea esp,[4+esp]
L$028cfb_abort:
pop edi
pop esi
pop ebx
pop ebp
ret
global _padlock_ofb_encrypt
align 16
_padlock_ofb_encrypt:
L$_padlock_ofb_encrypt_begin:
push ebp
push ebx
push esi
push edi
mov edi,DWORD [20+esp]
mov esi,DWORD [24+esp]
mov edx,DWORD [28+esp]
mov ecx,DWORD [32+esp]
test edx,15
jnz NEAR L$037ofb_abort
test ecx,15
jnz NEAR L$037ofb_abort
lea eax,[L$padlock_saved_context]
pushfd
cld
call __padlock_verify_ctx
L$038ofb_pic_point:
lea edx,[16+edx]
xor eax,eax
xor ebx,ebx
test DWORD [edx],32
jnz NEAR L$039ofb_aligned
test edi,15
setz al
test esi,15
setz bl
test eax,ebx
jnz NEAR L$039ofb_aligned
neg eax
mov ebx,512
not eax
lea ebp,[esp-24]
cmp ecx,ebx
cmovc ebx,ecx
and eax,ebx
mov ebx,ecx
neg eax
and ebx,511
lea esp,[ebp*1+eax]
mov eax,512
cmovz ebx,eax
mov eax,ebp
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
jmp NEAR L$040ofb_loop
align 16
L$040ofb_loop:
mov DWORD [ebp],edi
mov DWORD [4+ebp],esi
mov DWORD [8+ebp],ecx
mov ecx,ebx
mov DWORD [12+ebp],ebx
test edi,15
cmovnz edi,esp
test esi,15
jz NEAR L$041ofb_inp_aligned
shr ecx,2
db 243,165
sub edi,ebx
mov ecx,ebx
mov esi,edi
L$041ofb_inp_aligned:
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,232
movaps xmm0,[eax]
movaps [edx-16],xmm0
mov edi,DWORD [ebp]
mov ebx,DWORD [12+ebp]
test edi,15
jz NEAR L$042ofb_out_aligned
mov ecx,ebx
lea esi,[esp]
shr ecx,2
db 243,165
sub edi,ebx
L$042ofb_out_aligned:
mov esi,DWORD [4+ebp]
mov ecx,DWORD [8+ebp]
add edi,ebx
add esi,ebx
sub ecx,ebx
mov ebx,512
jnz NEAR L$040ofb_loop
cmp esp,ebp
je NEAR L$043ofb_done
pxor xmm0,xmm0
lea eax,[esp]
L$044ofb_bzero:
movaps [eax],xmm0
lea eax,[16+eax]
cmp ebp,eax
ja NEAR L$044ofb_bzero
L$043ofb_done:
mov ebp,DWORD [16+ebp]
lea esp,[24+ebp]
jmp NEAR L$045ofb_exit
align 16
L$039ofb_aligned:
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,232
movaps xmm0,[eax]
movaps [edx-16],xmm0
L$045ofb_exit:
mov eax,1
lea esp,[4+esp]
L$037ofb_abort:
pop edi
pop esi
pop ebx
pop ebp
ret
global _padlock_ctr32_encrypt
align 16
_padlock_ctr32_encrypt:
L$_padlock_ctr32_encrypt_begin:
push ebp
push ebx
push esi
push edi
mov edi,DWORD [20+esp]
mov esi,DWORD [24+esp]
mov edx,DWORD [28+esp]
mov ecx,DWORD [32+esp]
test edx,15
jnz NEAR L$046ctr32_abort
test ecx,15
jnz NEAR L$046ctr32_abort
lea eax,[L$padlock_saved_context]
pushfd
cld
call __padlock_verify_ctx
L$047ctr32_pic_point:
lea edx,[16+edx]
xor eax,eax
movq mm0,[edx-16]
mov ebx,512
not eax
lea ebp,[esp-24]
cmp ecx,ebx
cmovc ebx,ecx
and eax,ebx
mov ebx,ecx
neg eax
and ebx,511
lea esp,[ebp*1+eax]
mov eax,512
cmovz ebx,eax
mov eax,ebp
and ebp,-16
and esp,-16
mov DWORD [16+ebp],eax
jmp NEAR L$048ctr32_loop
align 16
L$048ctr32_loop:
mov DWORD [ebp],edi
mov DWORD [4+ebp],esi
mov DWORD [8+ebp],ecx
mov ecx,ebx
mov DWORD [12+ebp],ebx
mov ecx,DWORD [edx-4]
xor edi,edi
mov eax,DWORD [edx-8]
L$049ctr32_prepare:
mov DWORD [12+edi*1+esp],ecx
bswap ecx
movq [edi*1+esp],mm0
inc ecx
mov DWORD [8+edi*1+esp],eax
bswap ecx
lea edi,[16+edi]
cmp edi,ebx
jb NEAR L$049ctr32_prepare
mov DWORD [edx-4],ecx
lea esi,[esp]
lea edi,[esp]
mov ecx,ebx
lea eax,[edx-16]
lea ebx,[16+edx]
shr ecx,4
db 243,15,167,200
mov edi,DWORD [ebp]
mov ebx,DWORD [12+ebp]
mov esi,DWORD [4+ebp]
xor ecx,ecx
L$050ctr32_xor:
movups xmm1,[ecx*1+esi]
lea ecx,[16+ecx]
pxor xmm1,[ecx*1+esp-16]
movups [ecx*1+edi-16],xmm1
cmp ecx,ebx
jb NEAR L$050ctr32_xor
mov ecx,DWORD [8+ebp]
add edi,ebx
add esi,ebx
sub ecx,ebx
mov ebx,512
jnz NEAR L$048ctr32_loop
pxor xmm0,xmm0
lea eax,[esp]
L$051ctr32_bzero:
movaps [eax],xmm0
lea eax,[16+eax]
cmp ebp,eax
ja NEAR L$051ctr32_bzero
L$052ctr32_done:
mov ebp,DWORD [16+ebp]
lea esp,[24+ebp]
mov eax,1
lea esp,[4+esp]
emms
L$046ctr32_abort:
pop edi
pop esi
pop ebx
pop ebp
ret
global _padlock_xstore
align 16
_padlock_xstore:
L$_padlock_xstore_begin:
push edi
mov edi,DWORD [8+esp]
mov edx,DWORD [12+esp]
db 15,167,192
pop edi
ret
align 16
__win32_segv_handler:
mov eax,1
mov edx,DWORD [4+esp]
mov ecx,DWORD [12+esp]
cmp DWORD [edx],3221225477
jne NEAR L$053ret
add DWORD [184+ecx],4
mov eax,0
L$053ret:
ret
%if __NASM_VERSION_ID__ >= 0x02030000
safeseh __win32_segv_handler
%endif
global _padlock_sha1_oneshot
align 16
_padlock_sha1_oneshot:
L$_padlock_sha1_oneshot_begin:
push edi
push esi
xor eax,eax
mov edi,DWORD [12+esp]
mov esi,DWORD [16+esp]
mov ecx,DWORD [20+esp]
push __win32_segv_handler
db 100,255,48
db 100,137,32
mov edx,esp
add esp,-128
movups xmm0,[edi]
and esp,-16
mov eax,DWORD [16+edi]
movaps [esp],xmm0
mov edi,esp
mov DWORD [16+esp],eax
xor eax,eax
db 243,15,166,200
movaps xmm0,[esp]
mov eax,DWORD [16+esp]
mov esp,edx
db 100,143,5,0,0,0,0
lea esp,[4+esp]
mov edi,DWORD [16+esp]
movups [edi],xmm0
mov DWORD [16+edi],eax
pop esi
pop edi
ret
global _padlock_sha1_blocks
align 16
_padlock_sha1_blocks:
L$_padlock_sha1_blocks_begin:
push edi
push esi
mov edi,DWORD [12+esp]
mov esi,DWORD [16+esp]
mov edx,esp
mov ecx,DWORD [20+esp]
add esp,-128
movups xmm0,[edi]
and esp,-16
mov eax,DWORD [16+edi]
movaps [esp],xmm0
mov edi,esp
mov DWORD [16+esp],eax
mov eax,-1
db 243,15,166,200
movaps xmm0,[esp]
mov eax,DWORD [16+esp]
mov esp,edx
mov edi,DWORD [12+esp]
movups [edi],xmm0
mov DWORD [16+edi],eax
pop esi
pop edi
ret
global _padlock_sha256_oneshot
align 16
_padlock_sha256_oneshot:
L$_padlock_sha256_oneshot_begin:
push edi
push esi
xor eax,eax
mov edi,DWORD [12+esp]
mov esi,DWORD [16+esp]
mov ecx,DWORD [20+esp]
push __win32_segv_handler
db 100,255,48
db 100,137,32
mov edx,esp
add esp,-128
movups xmm0,[edi]
and esp,-16
movups xmm1,[16+edi]
movaps [esp],xmm0
mov edi,esp
movaps [16+esp],xmm1
xor eax,eax
db 243,15,166,208
movaps xmm0,[esp]
movaps xmm1,[16+esp]
mov esp,edx
db 100,143,5,0,0,0,0
lea esp,[4+esp]
mov edi,DWORD [16+esp]
movups [edi],xmm0
movups [16+edi],xmm1
pop esi
pop edi
ret
global _padlock_sha256_blocks
align 16
_padlock_sha256_blocks:
L$_padlock_sha256_blocks_begin:
push edi
push esi
mov edi,DWORD [12+esp]
mov esi,DWORD [16+esp]
mov ecx,DWORD [20+esp]
mov edx,esp
add esp,-128
movups xmm0,[edi]
and esp,-16
movups xmm1,[16+edi]
movaps [esp],xmm0
mov edi,esp
movaps [16+esp],xmm1
mov eax,-1
db 243,15,166,208
movaps xmm0,[esp]
movaps xmm1,[16+esp]
mov esp,edx
mov edi,DWORD [12+esp]
movups [edi],xmm0
movups [16+edi],xmm1
pop esi
pop edi
ret
global _padlock_sha512_blocks
align 16
_padlock_sha512_blocks:
L$_padlock_sha512_blocks_begin:
push edi
push esi
mov edi,DWORD [12+esp]
mov esi,DWORD [16+esp]
mov ecx,DWORD [20+esp]
mov edx,esp
add esp,-128
movups xmm0,[edi]
and esp,-16
movups xmm1,[16+edi]
movups xmm2,[32+edi]
movups xmm3,[48+edi]
movaps [esp],xmm0
mov edi,esp
movaps [16+esp],xmm1
movaps [32+esp],xmm2
movaps [48+esp],xmm3
db 243,15,166,224
movaps xmm0,[esp]
movaps xmm1,[16+esp]
movaps xmm2,[32+esp]
movaps xmm3,[48+esp]
mov esp,edx
mov edi,DWORD [12+esp]
movups [edi],xmm0
movups [16+edi],xmm1
movups [32+edi],xmm2
movups [48+edi],xmm3
pop esi
pop edi
ret
db 86,73,65,32,80,97,100,108,111,99,107,32,120,56,54,32
db 109,111,100,117,108,101,44,32,67,82,89,80,84,79,71,65
db 77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101
db 110,115,115,108,46,111,114,103,62,0
align 16
section .data align=4
align 4
L$padlock_saved_context:
dd 0
| MTASZTAKI/ApertusVR | plugins/languageAPI/jsAPI/3rdParty/nodejs/10.1.0/source/deps/openssl/config/archs/VC-WIN32/asm/engines/e_padlock-x86.asm | Assembly | mit | 17,041 |
; Refer to http://wiki.osdev.org/ATA_in_x86_RealMode_(BIOS) for full
; documentation.
; @function: detect
; @brief: detect drive parameters via int 13h, ah=8h.
; @parameters: none.
detect:
pusha
xor ax, ax
mov es, ax
mov di, ax
mov ah, 0x8
mov dl, [boot_drive]
int 0x13
jnc .ok
popa
ret ; use default floopy
.ok:
mov dl, dh
xor dh, dh
inc dx
mov [total_heads], dx
mov ax, cx
and ax, 0x3f
mov [sectors_per_track], ax
popa
ret
; @function: load
; @brief: load the kernel image to memory.
; @parameters: start sector, destination, the number of sectors to read.
load:
push bp
mov bp, sp
pusha
mov ax, [bp + 4] ; sectors to read
xor bx, bx
mov dx, [bp + 6] ; load to where?
mov cx, [bp + 8] ; start sector
.loop:
cmp ax, 0
je .ok
push cx
push dx
push bx
call read
add sp, 6
dec ax
add bx, 0x200
inc cx
cmp bx, 0x1000
jne .loop
add dx, 0x100
xor bx, bx
jmp .loop
.ok:
popa
pop bp
ret
; @function: read
; @brief: read a sector from drive.
; @parameters: buffer offset, buffer segment, LBA.
read:
push bp
mov bp, sp
pusha
mov ax, [bp + 8]
xor dx, dx
mov bx, [sectors_per_track]
div bx
inc dx ; sector is 1-based
mov [sector_index], dx
xor dx, dx
mov bx, [total_heads]
div bx
mov [head_index], dx
mov [cylinder_index], ax
mov [number_retries], byte 0
; read a sector
mov bx, [cylinder_index]
mov ch, bl
mov bx, [sector_index]
mov cl, bl
mov bx, [cylinder_index]
shr bx, 2
and bx, 0xc0
or cl, bl ; not necessary for floppy
mov bx, [head_index]
mov dh, bl
mov bx, [bp + 4]
mov es, [bp + 6]
mov dl, [boot_drive]
.loop:
mov ah, 0x2
mov al, 0x1
int 0x13
jnc .ok
; reset disk drive
xor ax, ax
int 0x13
inc byte [number_retries]
cmp byte [number_retries], 5 ; retry 5 times
jne .loop
jmp disk_fatal ; see boot.asm
.ok:
popa
pop bp
ret
sector_index dw 0
head_index dw 0
cylinder_index dw 0
number_retries db 0
; floppy default value (place holder, can be overwritten)
sectors_per_track dw 18
total_heads dw 2
| foreverbell/BadAppleOS | boot/disk.asm | Assembly | mit | 2,123 |
########### helloIO.asm on p. 26-27 #############
# Miguel Rodriguez #
# helloIO.asm #
# Description #
# Program which displays a message #
# Program Logic #
# 1. Ask for a message #
# 2. input the message #
# 3. display a message from the data area #
# 4. display a new line #
# 5. return to operating system #
#################################################
.text
.globl __start
__start:
la $a0,p1 # Display the message below "Enter your message"
li $v0,4 # a0 = address of string
syscall # v0 = 4, indicates display a string
la $a0,str #Loads the address of the message area
li $a1,80 #Loads the number of characters available for the message
li $v0,8 #inputs the message
syscall #calls to do the command above
la $a0,str #displays the Message
li $v0,4
syscall
la $a0,p2 #displays the new line
li $v0,4
syscall
li $v0,10 # End Of Program
syscall # Call to system
.data
str: .space 80
p1: .asciiz "Enter Your Message: "
p2: .asciiz "\n"
############## Output ##################
# Console #
#========================= #
# Enter Your Message: Miguel Rodriguez #
# Miguel Rodriguez #
# #
######################################## | miguel2192/CSC-211-Assembly | HelloIO/helloIO.asm | Assembly | mit | 1,718 |
assume cs:code, ds:data
data segment public
tmp db 5 dup(?), ':', '$'
aux db 10 dup('1'), '$'
data ends
code segment public
public tipar
tipar:
push ax
push bx
push cx
push dx
mov bx, offset tmp + 5
mov cx, 10
bucla:
mov dx, 0
div cx
dec bx
add dl, '0'
mov byte ptr [bx], dl
cmp ax, 0
jne bucla
mov dx, bx
mov ah, 09h
int 21h
pop dx
pop cx
pop bx
pop ax
ret
code ends
end
| rusucosmin/courses | ubb/asc/lab11/RusuCosmin_11_tipar.asm | Assembly | mit | 411 |
start:
inc a
jp start | Lionel07/Ymgyrch-Old | test/loop.asm | Assembly | mit | 23 |
test START 0
LDA =1
ORG 5000
LTORG
END test
| kloboves/sicxe | tests/testdata/codegen-in-5-bad.asm | Assembly | mit | 106 |
include "defines.inc"
include "plus3dos.inc"
PUBLIC dodos
PUBLIC mypager
PUBLIC defaultBank
PUBLIC fputc_cons
PUBLIC _logNum
PUBLIC _toggleSpinner
PUBLIC _myexit
VARS equ 0x5c4b
DOS_SET_1346 equ 0x013f
ERR_NR equ 0x5c3a ; BASIC system variables
; copy all the data from this page to elsewhere in the memory map
;copydata:
ld hl, page2page ; hl = source address for ldir
ld de, farcall ; de = destination address for ldir
ld bc, page2pageend-page2page ; bc = number of bytes to copy for ldir
di
ldir
exx
ld (exhlBackup), hl ; save BASIC's HL'
exx
ei
ld a, 7
ld (destinationHighBank), a ; which high bank to go to (bank 7)
ld hl, jumpback
ld (jumptoit+1), hl
ld a, 4 ; how many loads to do
push af
ld b, [[firstEnd - first] % 512] / 2
ld c, [[firstEnd - first] / 512] + 1
ld (bcBackup), bc
ld hl, 0xec20 - first + firstEnd - 1
ld (hlBackup), hl
ld hl, first
Loop:
ld d, (hl)
inc hl
ld e, (hl)
push de
inc hl
djnz Loop
dec c
jr nz, Loop
xor a ; zero out the accumulator
ld (bankmBackup), a ; jump back to page 0
ld bc, (bcBackup) ; restore bc
ld hl, (hlBackup) ; restore hl
jp 0xbd00
jumpback:
pop af
dec a
push af
cp 3
jr z, secondcopy
cp 2
jr z, thirdcopy
cp 1
jr z, fourthcopy
pop af
jr inf
secondcopy:
ld b, [[secondEnd - second] % 512] / 2
ld c, [[secondEnd - second] / 512] + 1
ld (bcBackup), bc
ld hl, 0xf511 - second + secondEnd - 1
ld (hlBackup), hl
ld hl, second
jr Loop
thirdcopy:
ld b, [[thirdEnd - third] % 512] / 2
ld c, [[thirdEnd - third] / 512] + 1
ld (bcBackup), bc
ld hl, 0xe438 - third + thirdEnd - 1
ld (hlBackup), hl
ld hl, third
jr Loop
fourthcopy:
ld b, [[fourthEnd - fourth] % 512] / 2
ld c, [[fourthEnd - fourth] / 512] + 1
ld (bcBackup), bc
ld hl, 0xe60e - fourth + fourthEnd - 1
ld (hlBackup), hl
ld hl, fourth
jr Loop
inf:
ld a, 1
ld (destinationHighBank), a ; which high bank to go to (bank 1)
; shrink the workspaces to only use page 6
ld de, 0x601c ; just first half of page 6
ld hl, 0x7c04 ; just second half of page 6
ld iy, DOS_SET_1346
call dodos
ld a, 1
ld (currentVirtualPage), a ; update the current virtual page number to be that of the main function
ld (_libCPage), a
; update atexit jump
ld a, 0xcd ; call instruction
ld (atexit), a ; put instruction into the fputc_cons location
;update fputc_cons jump
ld (fputc_cons), a ; put instruction into the fputc_cons location
ld hl, jp_rom3
ld (fputc_cons+1), hl ; put jp_rom3 address here
ld a, 0xc3
ld (_toggleSpinner), a ; put jp instruction into the _toggleSpinner location
ld hl, setSpinner
ld (_toggleSpinner+1), hl
;setup standard streams
ld hl, __sgoioblk + 2
ld (hl), 19 ;stdin
ld hl, __sgoioblk + 12
ld (hl), 21 ;stdout
ld hl, __sgoioblk + 22
ld (hl), 21 ;stderr
; get the filename to load from basic variable a$
; zx_getstraddr:
ld d, 'A'
ld hl, (VARS)
loop:
ld a, (hl)
cp 128
jr z, notFound2
cp d
jr z, found2
push de
call call_rom3
defw 0x19b8 ; get the address of the next variable
ex de, hl
pop de
jr loop
; convert the Pascal string into a C string
found2:
inc hl
ld c, (hl)
xor a
ld (hl), a ; zero the first byte so we can find the start of the string later
inc hl
ld b, (hl)
ld a, b
or c
jp z, notFound2
ld (argName), hl
push hl
pop de
inc hl
di
ldir
ei
xor a
ld (de), a ; null terminate the string
ld bc, 2
jr startup
notFound2:
ld bc, 1
startup:
ld hl, argv
push hl ; argv
push bc ; argc
ld (spBackup), sp
; restore the interrupt mode 2 bytes
ld b, 255
ld hl, 0xbd00
intSetup:
ld (hl), 0xbf
inc hl
djnz intSetup
ld (hl), 0xbf ; unroll the last 2 loop iterations
inc hl
ld (hl), 0xbf
;update the isr jump
ld hl, isr2
ld (isr+1), hl
; switch to interrupt mode 2 so we can use the iy register and
; ram at 0x0000-0x2000 with interrupts enabled
di
ld a, 0xbd
ld i, a
im 2 ; Set Interrupt Mode 2
ei
; clear the second screen (and switch to it at the same time)
push bc
push de
push hl
call call_rom3
defw 0xf519
pop hl
pop de
pop bc
;ld bc, 0x0707
;push bc
;call fputc_cons
;pop bc
;ld bc, 0x4141
;push bc
;call fputc_cons
;pop bc
;ld bc, 0x4242
;push bc
;call fputc_cons
;pop bc
;start running main function
call _realmain
jp atexit
first:
binary "fputc_cons_first.bin"
firstEnd:
second:
binary "fputc_cons_second.bin"
secondEnd:
third:
binary "fputc_cons_third.bin"
thirdEnd:
fourth:
binary "atexit.bin"
fourthEnd:
page2page:
binary "pager.bin"
binary "page2page.bin"
page2pageend:
| pjshumphreys/querycsv | env/zx/plus3dos/plus3dos.asm | Assembly | mit | 4,710 |
[bits 32]
dd MathTest.$FILE_END - MathTest.$FILE_START
db "OrcaHLL Class", 0
db "MathTest", 0
MathTest.$FILE_START :
dd MathTest._init
MathTest._init:
pop dword [MathTest._init.returnVal]
push eax
push ebx
push edx
mov ax, 0x0104
int 0x30
call MathTest.getNumber
mov [MathTest._init.$local.y], ecx
mov ecx, [MathTest._init.string_0]
push ecx
mov ax, 0x0100
int 0x30
mov ecx, [MathTest._init.$local.y]
push ecx
mov ax, 0x0102
int 0x30
mov ax, 0x0103
int 0x30
push edx ; Math start
mov ecx, 5
mov edx, ecx
mov ecx, [MathTest._init.$local.y]
add ecx, edx
pop edx ; Math end
mov [MathTest._init.$local.y], ecx
mov ecx, [MathTest._init.string_1]
push ecx
mov ax, 0x0100
int 0x30
mov ecx, [MathTest._init.$local.y]
push ecx
mov ax, 0x0102
int 0x30
mov ax, 0x0103
int 0x30
mov ecx, [MathTest._init.string_2]
push ecx
mov ax, 0x0100
int 0x30
push edx ; Math start
mov ecx, 2
mov edx, ecx
mov ecx, [MathTest._init.$local.y]
sub ecx, edx
pop edx ; Math end
push ecx
mov ax, 0x0102
int 0x30
pop edx
pop ebx
pop eax
push dword [MathTest._init.returnVal]
ret
;Vars:
MathTest._init.string_0_data :
db "Y is 0x", 0
MathTest._init.string_1 :
dd MathTest._init.string_1_data
MathTest._init.string_2_data :
db "Y-2 = 0x", 0
MathTest._init.string_1_data :
db "Y is now 0x", 0
MathTest._init.$local.y :
dd 0x0
MathTest._init.string_0 :
dd MathTest._init.string_0_data
MathTest._init.string_2 :
dd MathTest._init.string_2_data
MathTest._init.returnVal:
dd 0x0
MathTest.getNumber:
pop dword [MathTest.getNumber.returnVal]
push eax
push ebx
push edx
mov ecx, 3
pop edx
pop ebx
pop eax
push dword [MathTest.getNumber.returnVal]
ret
;Vars:
MathTest.getNumber.returnVal:
dd 0x0
MathTest.$FILE_END :
| jaredwhitney/os3 | OrcaHLL/MathTest.asm | Assembly | mit | 1,693 |
; a PE with fake .NET EntryPoint, imports but no COM directory
; Ange Albertini, BSD LICENCE 2013
%include 'consts.inc'
%include 'headers.inc'
istruc IMAGE_DATA_DIRECTORY_16
at IMAGE_DATA_DIRECTORY_16.ImportsVA, dd Import_Descriptor - IMAGEBASE
at IMAGE_DATA_DIRECTORY_16.TLSVA, dd Image_Tls_Directory32 - IMAGEBASE
iend
SIZEOFOPTIONALHEADER equ $ - OptionalHeader
SectionHeader:
istruc IMAGE_SECTION_HEADER
at IMAGE_SECTION_HEADER.VirtualSize, dd 1 * SECTIONALIGN
at IMAGE_SECTION_HEADER.VirtualAddress, dd 1 * SECTIONALIGN
at IMAGE_SECTION_HEADER.SizeOfRawData, dd 2 * FILEALIGN ; <=
at IMAGE_SECTION_HEADER.PointerToRawData, dd 1 * FILEALIGN
at IMAGE_SECTION_HEADER.Characteristics, dd IMAGE_SCN_MEM_EXECUTE | IMAGE_SCN_MEM_WRITE
iend
NUMBEROFSECTIONS equ ($ - SectionHeader) / IMAGE_SECTION_HEADER_size
SIZEOFHEADERS equ $ - IMAGEBASE
;*******************************************************************************
section progbits vstart=IMAGEBASE + SECTIONALIGN align=FILEALIGN
next:
call $ + 5
base:
pop ebp
call LoadImports
lea eax, [ebp - base + Msg]
push eax
call [ebp + ddprintf - base]
add esp, 1 * 4
_
push 0
call [ebp + ddExitProcess - base]
_c
Msg db " * a PE with fake .NET EntryPoint, imports but no COM directory", 0ah, 0
_d
;generated with api_hash.py
LOADLIBRARYA equ 06FFFE488h
EXITPROCESS equ 031678333h
PRINTF equ 09DDEF696h
LoadImports:
; Locate Kernel32.dll imagebase
mov eax,[fs:030h] ; _TIB.PebPtr
mov eax,[eax + 0ch] ; _PEB.Ldr
mov eax,[eax + 0ch] ; _PEB_LDR_DATA.InLoadOrderModuleList.Flink
mov eax,[eax] ; _LDR_MODULE.InLoadOrderModuleList.Flink
mov eax,[eax] ; _LDR_MODULE.InLoadOrderModuleList.Flink
mov eax,[eax + 18h] ; _LDR_MODULE.BaseAddress
; brutal way, not as much compatible
; mov eax, [esp + 4]
; and eax, 0fff00000h
mov [ebp + hKernel32 - base], eax
mov eax, [ebp + hKernel32 - base]
mov ebx, LOADLIBRARYA
call GetProcAddress_Hash
mov [ebp + ddLoadLibrary - base], ebx
mov eax, [ebp + hKernel32 - base]
mov ebx, EXITPROCESS
call GetProcAddress_Hash
mov [ebp + ddExitProcess - base], ebx
lea eax, [szmsvcrt + ebp - base]
push eax
call [ebp + ddLoadLibrary - base]
mov ebx, PRINTF
call GetProcAddress_Hash
mov [ebp + ddprintf - base], ebx
retn
_c
szmsvcrt db "msvcrt", 0
_d
ddprintf dd 0
ddExitProcess dd 0
hKernel32 dd 0
ddLoadLibrary dd 0
%include 'gpa_ebp.inc'
EntryPoint:
jmp [__imp__corexemain]
;*******************************************************************************
Import_Descriptor:
istruc IMAGE_IMPORT_DESCRIPTOR
at IMAGE_IMPORT_DESCRIPTOR.Name1, dd aMscoree_dll - IMAGEBASE
at IMAGE_IMPORT_DESCRIPTOR.FirstThunk, dd mscoree.dll_iat - IMAGEBASE
iend
istruc IMAGE_IMPORT_DESCRIPTOR
iend
hn_CoreExeMain db 0,0, '_CorExeMain',0
_d
mscoree.dll_iat:
__imp__corexemain:
dd hn_CoreExeMain - IMAGEBASE
dd 0
_d
aMscoree_dll db 'mscoree.dll',0
_d
;*******************************************************************************
tls:
mov dword [__imp__corexemain], next
retn
Image_Tls_Directory32:
istruc IMAGE_TLS_DIRECTORY32
at IMAGE_TLS_DIRECTORY32.AddressOfIndex, dd tls_aoi
at IMAGE_TLS_DIRECTORY32.AddressOfCallBacks, dd CallBacks
iend
_d
tls_aoi dd 0
CallBacks:
dd tls
dd 0
_d
align FILEALIGN, db 0
| angea/corkami | src/PE/fakenet.asm | Assembly | bsd-2-clause | 3,580 |
%include "util.mac"
extern buffer, array, newline, newlinesize, outprompt, outpromptsize, inputarray
section data
maxprompt: db 'MAXIMUM: '
minprompt: db 'MINIMUM: '
mpromptsize: equ 9
section .bss
max: resb 1
min: resb 1
section .text
global _start
_start:
call inputarray
mov byte [max], 0
mov byte [min], 255
mov ecx, 9
next:
mov al, [max]
cmp [array + ecx - 1], al
jc skip1
mov al, [array + ecx - 1]
mov [max], al
skip1:
mov al, [min]
cmp al, [array + ecx - 1]
jc skip2
mov al, [array + ecx - 1]
mov [min], al
skip2:
loop next
mov al, [max]
mov ah, 0
write maxprompt, mpromptsize
printword ax, buffer, 2
write newline, newlinesize
mov al, [min]
mov ah, 0
write minprompt, mpromptsize
printword ax, buffer, 2
write newline, newlinesize
exit
| aaiijmrtt/JUCSE | SystemsProgramming/p8.asm | Assembly | mit | 780 |
; Compiling command: nasm core.asm -f bin -o os.bin
[BITS 16] ; 16-bit mode
[ORG 0x7C00] ; easy
; Switching mode
mov ah, 0
mov al, 0x13 ; VGA mode (320x200x8bit)
int 0x10
mov ax, 0A000h ; Video offset
mov es, ax
mov cx, 0
start:
mov ah, 0
int 0x16
cmp ah, 72 ; UP key code
je key_up_pressed ; Jump if equal
cmp ah, 80 ; DOWN key code
je key_down_pressed ; Jump if equal
jne key_other_pressed ; Very important to do negative check
key_up_pressed:
mov di, cx
mov byte [es:di], 14 ; Yellow
inc cx
jmp start
key_down_pressed:
mov di, cx
mov byte [es:di], 12 ; Red
inc cx
jmp start
key_other_pressed:
mov di, cx
mov byte [es:di], 10 ; Green
inc cx
jmp start
jmp start
JMP $
TIMES 510 - ($ - $$) db 0
DW 0xAA55 | Shemplo/asm-etudes | sandbox/video_mod_v1/core.asm | Assembly | apache-2.0 | 757 |
bits 64
movd r8d, mm1
movd r8, mm1
movq r8, mm1
movd [rax], mm1
movq [rax], mm1
movd dword [rax], mm1
; movq dword [rax], mm1
movd qword [rax], mm1
movq qword [rax], mm1
; movd mm2, mm1
movq mm2, mm1
| coapp-packages/nasm | test/movd64.asm | Assembly | bsd-2-clause | 229 |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; ReadDr0.Asm
;
; Abstract:
;
; AsmReadDr0 function
;
; Notes:
;
;------------------------------------------------------------------------------
.code
;------------------------------------------------------------------------------
; UINTN
; EFIAPI
; AsmReadDr0 (
; VOID
; );
;------------------------------------------------------------------------------
AsmReadDr0 PROC
mov rax, dr0
ret
AsmReadDr0 ENDP
END
| tenpoku1000/UEFI_SecureBoot | src/lib/external/BSD/UDK/MdePkg/Library/BaseLib/X64/ReadDr0.asm | Assembly | mit | 1,027 |
_test1: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
int n = 1;
void test_func(void *arg_ptr);
int main(int argc, char *argv[]){
0: 55 push %ebp
1: 89 e5 mov %esp,%ebp
3: 83 e4 f0 and $0xfffffff0,%esp
6: 83 ec 20 sub $0x20,%esp
init_semaphore(&s, 1);
9: c7 44 24 04 01 00 00 movl $0x1,0x4(%esp)
10: 00
11: c7 04 24 60 0e 00 00 movl $0xe60,(%esp)
18: e8 9b 0c 00 00 call cb8 <init_semaphore>
int pid = fork();
1d: e8 de 04 00 00 call 500 <fork>
22: 89 44 24 14 mov %eax,0x14(%esp)
if(pid == 0){
26: 83 7c 24 14 00 cmpl $0x0,0x14(%esp)
2b: 0f 85 43 01 00 00 jne 174 <main+0x174>
void *tid = thread_create(test_func,(void *)0);
31: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
38: 00
39: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
40: e8 8d 0a 00 00 call ad2 <thread_create>
45: 89 44 24 18 mov %eax,0x18(%esp)
if(tid == 0){
49: 83 7c 24 18 00 cmpl $0x0,0x18(%esp)
4e: 75 19 jne 69 <main+0x69>
printf(1,"thread_create fails\n");
50: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
57: 00
58: c7 04 24 01 00 00 00 movl $0x1,(%esp)
5f: e8 45 06 00 00 call 6a9 <printf>
exit();
64: e8 9f 04 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
69: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
70: 00
71: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
78: e8 55 0a 00 00 call ad2 <thread_create>
7d: 89 44 24 18 mov %eax,0x18(%esp)
if(tid == 0){
81: 83 7c 24 18 00 cmpl $0x0,0x18(%esp)
86: 75 19 jne a1 <main+0xa1>
printf(1,"thread_create fails\n");
88: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
8f: 00
90: c7 04 24 01 00 00 00 movl $0x1,(%esp)
97: e8 0d 06 00 00 call 6a9 <printf>
exit();
9c: e8 67 04 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
a1: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
a8: 00
a9: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
b0: e8 1d 0a 00 00 call ad2 <thread_create>
b5: 89 44 24 18 mov %eax,0x18(%esp)
if(tid == 0){
b9: 83 7c 24 18 00 cmpl $0x0,0x18(%esp)
be: 75 19 jne d9 <main+0xd9>
printf(1,"thread_create fails\n");
c0: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
c7: 00
c8: c7 04 24 01 00 00 00 movl $0x1,(%esp)
cf: e8 d5 05 00 00 call 6a9 <printf>
exit();
d4: e8 2f 04 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
d9: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
e0: 00
e1: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
e8: e8 e5 09 00 00 call ad2 <thread_create>
ed: 89 44 24 18 mov %eax,0x18(%esp)
if(tid == 0){
f1: 83 7c 24 18 00 cmpl $0x0,0x18(%esp)
f6: 75 19 jne 111 <main+0x111>
printf(1,"thread_create fails\n");
f8: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
ff: 00
100: c7 04 24 01 00 00 00 movl $0x1,(%esp)
107: e8 9d 05 00 00 call 6a9 <printf>
exit();
10c: e8 f7 03 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
111: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
118: 00
119: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
120: e8 ad 09 00 00 call ad2 <thread_create>
125: 89 44 24 18 mov %eax,0x18(%esp)
if(tid == 0){
129: 83 7c 24 18 00 cmpl $0x0,0x18(%esp)
12e: 75 19 jne 149 <main+0x149>
printf(1,"thread_create fails\n");
130: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
137: 00
138: c7 04 24 01 00 00 00 movl $0x1,(%esp)
13f: e8 65 05 00 00 call 6a9 <printf>
exit();
144: e8 bf 03 00 00 call 508 <exit>
}
while(wait()>=0);
149: e8 c2 03 00 00 call 510 <wait>
14e: 85 c0 test %eax,%eax
150: 79 f7 jns 149 <main+0x149>
printf(1,"I am child, [6] n = %d\n",n);
152: a1 3c 0e 00 00 mov 0xe3c,%eax
157: 89 44 24 08 mov %eax,0x8(%esp)
15b: c7 44 24 04 bf 0d 00 movl $0xdbf,0x4(%esp)
162: 00
163: c7 04 24 01 00 00 00 movl $0x1,(%esp)
16a: e8 3a 05 00 00 call 6a9 <printf>
16f: e9 11 01 00 00 jmp 285 <main+0x285>
}else if(pid > 0){
174: 83 7c 24 14 00 cmpl $0x0,0x14(%esp)
179: 0f 8e 06 01 00 00 jle 285 <main+0x285>
void *tid = thread_create(test_func,(void *)0);
17f: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
186: 00
187: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
18e: e8 3f 09 00 00 call ad2 <thread_create>
193: 89 44 24 1c mov %eax,0x1c(%esp)
if(tid == 0){
197: 83 7c 24 1c 00 cmpl $0x0,0x1c(%esp)
19c: 75 19 jne 1b7 <main+0x1b7>
printf(1,"thread_create fails\n");
19e: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
1a5: 00
1a6: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1ad: e8 f7 04 00 00 call 6a9 <printf>
exit();
1b2: e8 51 03 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
1b7: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1be: 00
1bf: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
1c6: e8 07 09 00 00 call ad2 <thread_create>
1cb: 89 44 24 1c mov %eax,0x1c(%esp)
if(tid == 0){
1cf: 83 7c 24 1c 00 cmpl $0x0,0x1c(%esp)
1d4: 75 19 jne 1ef <main+0x1ef>
printf(1,"thread_create fails\n");
1d6: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
1dd: 00
1de: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1e5: e8 bf 04 00 00 call 6a9 <printf>
exit();
1ea: e8 19 03 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
1ef: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1f6: 00
1f7: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
1fe: e8 cf 08 00 00 call ad2 <thread_create>
203: 89 44 24 1c mov %eax,0x1c(%esp)
if(tid == 0){
207: 83 7c 24 1c 00 cmpl $0x0,0x1c(%esp)
20c: 75 19 jne 227 <main+0x227>
printf(1,"thread_create fails\n");
20e: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
215: 00
216: c7 04 24 01 00 00 00 movl $0x1,(%esp)
21d: e8 87 04 00 00 call 6a9 <printf>
exit();
222: e8 e1 02 00 00 call 508 <exit>
}
tid = thread_create(test_func,(void *)0);
227: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
22e: 00
22f: c7 04 24 8a 02 00 00 movl $0x28a,(%esp)
236: e8 97 08 00 00 call ad2 <thread_create>
23b: 89 44 24 1c mov %eax,0x1c(%esp)
if(tid == 0){
23f: 83 7c 24 1c 00 cmpl $0x0,0x1c(%esp)
244: 75 19 jne 25f <main+0x25f>
printf(1,"thread_create fails\n");
246: c7 44 24 04 aa 0d 00 movl $0xdaa,0x4(%esp)
24d: 00
24e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
255: e8 4f 04 00 00 call 6a9 <printf>
exit();
25a: e8 a9 02 00 00 call 508 <exit>
}
while(wait()>=0);
25f: e8 ac 02 00 00 call 510 <wait>
264: 85 c0 test %eax,%eax
266: 79 f7 jns 25f <main+0x25f>
printf(1,"I am parent, [5] n = %d\n",n);
268: a1 3c 0e 00 00 mov 0xe3c,%eax
26d: 89 44 24 08 mov %eax,0x8(%esp)
271: c7 44 24 04 d7 0d 00 movl $0xdd7,0x4(%esp)
278: 00
279: c7 04 24 01 00 00 00 movl $0x1,(%esp)
280: e8 24 04 00 00 call 6a9 <printf>
}
exit();
285: e8 7e 02 00 00 call 508 <exit>
0000028a <test_func>:
}
void test_func(void *arg_ptr){
28a: 55 push %ebp
28b: 89 e5 mov %esp,%ebp
28d: 83 ec 08 sub $0x8,%esp
// printf(1,"\n n = %d\n",n);
n++;
290: a1 3c 0e 00 00 mov 0xe3c,%eax
295: 83 c0 01 add $0x1,%eax
298: a3 3c 0e 00 00 mov %eax,0xe3c
// printf(1,"after increase by 1 , n = %d\n\n",n);
texit();
29d: e8 0e 03 00 00 call 5b0 <texit>
2a2: 90 nop
2a3: 90 nop
000002a4 <stosb>:
"cc");
}
static inline void
stosb(void *addr, int data, int cnt)
{
2a4: 55 push %ebp
2a5: 89 e5 mov %esp,%ebp
2a7: 57 push %edi
2a8: 53 push %ebx
asm volatile("cld; rep stosb" :
2a9: 8b 4d 08 mov 0x8(%ebp),%ecx
2ac: 8b 55 10 mov 0x10(%ebp),%edx
2af: 8b 45 0c mov 0xc(%ebp),%eax
2b2: 89 cb mov %ecx,%ebx
2b4: 89 df mov %ebx,%edi
2b6: 89 d1 mov %edx,%ecx
2b8: fc cld
2b9: f3 aa rep stos %al,%es:(%edi)
2bb: 89 ca mov %ecx,%edx
2bd: 89 fb mov %edi,%ebx
2bf: 89 5d 08 mov %ebx,0x8(%ebp)
2c2: 89 55 10 mov %edx,0x10(%ebp)
"=D" (addr), "=c" (cnt) :
"0" (addr), "1" (cnt), "a" (data) :
"memory", "cc");
}
2c5: 5b pop %ebx
2c6: 5f pop %edi
2c7: 5d pop %ebp
2c8: c3 ret
000002c9 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, char *t)
{
2c9: 55 push %ebp
2ca: 89 e5 mov %esp,%ebp
2cc: 83 ec 10 sub $0x10,%esp
char *os;
os = s;
2cf: 8b 45 08 mov 0x8(%ebp),%eax
2d2: 89 45 fc mov %eax,-0x4(%ebp)
while((*s++ = *t++) != 0)
2d5: 8b 45 0c mov 0xc(%ebp),%eax
2d8: 0f b6 10 movzbl (%eax),%edx
2db: 8b 45 08 mov 0x8(%ebp),%eax
2de: 88 10 mov %dl,(%eax)
2e0: 8b 45 08 mov 0x8(%ebp),%eax
2e3: 0f b6 00 movzbl (%eax),%eax
2e6: 84 c0 test %al,%al
2e8: 0f 95 c0 setne %al
2eb: 83 45 08 01 addl $0x1,0x8(%ebp)
2ef: 83 45 0c 01 addl $0x1,0xc(%ebp)
2f3: 84 c0 test %al,%al
2f5: 75 de jne 2d5 <strcpy+0xc>
;
return os;
2f7: 8b 45 fc mov -0x4(%ebp),%eax
}
2fa: c9 leave
2fb: c3 ret
000002fc <strcmp>:
int
strcmp(const char *p, const char *q)
{
2fc: 55 push %ebp
2fd: 89 e5 mov %esp,%ebp
while(*p && *p == *q)
2ff: eb 08 jmp 309 <strcmp+0xd>
p++, q++;
301: 83 45 08 01 addl $0x1,0x8(%ebp)
305: 83 45 0c 01 addl $0x1,0xc(%ebp)
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
309: 8b 45 08 mov 0x8(%ebp),%eax
30c: 0f b6 00 movzbl (%eax),%eax
30f: 84 c0 test %al,%al
311: 74 10 je 323 <strcmp+0x27>
313: 8b 45 08 mov 0x8(%ebp),%eax
316: 0f b6 10 movzbl (%eax),%edx
319: 8b 45 0c mov 0xc(%ebp),%eax
31c: 0f b6 00 movzbl (%eax),%eax
31f: 38 c2 cmp %al,%dl
321: 74 de je 301 <strcmp+0x5>
p++, q++;
return (uchar)*p - (uchar)*q;
323: 8b 45 08 mov 0x8(%ebp),%eax
326: 0f b6 00 movzbl (%eax),%eax
329: 0f b6 d0 movzbl %al,%edx
32c: 8b 45 0c mov 0xc(%ebp),%eax
32f: 0f b6 00 movzbl (%eax),%eax
332: 0f b6 c0 movzbl %al,%eax
335: 89 d1 mov %edx,%ecx
337: 29 c1 sub %eax,%ecx
339: 89 c8 mov %ecx,%eax
}
33b: 5d pop %ebp
33c: c3 ret
0000033d <strlen>:
uint
strlen(char *s)
{
33d: 55 push %ebp
33e: 89 e5 mov %esp,%ebp
340: 83 ec 10 sub $0x10,%esp
int n;
for(n = 0; s[n]; n++)
343: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
34a: eb 04 jmp 350 <strlen+0x13>
34c: 83 45 fc 01 addl $0x1,-0x4(%ebp)
350: 8b 45 fc mov -0x4(%ebp),%eax
353: 03 45 08 add 0x8(%ebp),%eax
356: 0f b6 00 movzbl (%eax),%eax
359: 84 c0 test %al,%al
35b: 75 ef jne 34c <strlen+0xf>
;
return n;
35d: 8b 45 fc mov -0x4(%ebp),%eax
}
360: c9 leave
361: c3 ret
00000362 <memset>:
void*
memset(void *dst, int c, uint n)
{
362: 55 push %ebp
363: 89 e5 mov %esp,%ebp
365: 83 ec 0c sub $0xc,%esp
stosb(dst, c, n);
368: 8b 45 10 mov 0x10(%ebp),%eax
36b: 89 44 24 08 mov %eax,0x8(%esp)
36f: 8b 45 0c mov 0xc(%ebp),%eax
372: 89 44 24 04 mov %eax,0x4(%esp)
376: 8b 45 08 mov 0x8(%ebp),%eax
379: 89 04 24 mov %eax,(%esp)
37c: e8 23 ff ff ff call 2a4 <stosb>
return dst;
381: 8b 45 08 mov 0x8(%ebp),%eax
}
384: c9 leave
385: c3 ret
00000386 <strchr>:
char*
strchr(const char *s, char c)
{
386: 55 push %ebp
387: 89 e5 mov %esp,%ebp
389: 83 ec 04 sub $0x4,%esp
38c: 8b 45 0c mov 0xc(%ebp),%eax
38f: 88 45 fc mov %al,-0x4(%ebp)
for(; *s; s++)
392: eb 14 jmp 3a8 <strchr+0x22>
if(*s == c)
394: 8b 45 08 mov 0x8(%ebp),%eax
397: 0f b6 00 movzbl (%eax),%eax
39a: 3a 45 fc cmp -0x4(%ebp),%al
39d: 75 05 jne 3a4 <strchr+0x1e>
return (char*)s;
39f: 8b 45 08 mov 0x8(%ebp),%eax
3a2: eb 13 jmp 3b7 <strchr+0x31>
}
char*
strchr(const char *s, char c)
{
for(; *s; s++)
3a4: 83 45 08 01 addl $0x1,0x8(%ebp)
3a8: 8b 45 08 mov 0x8(%ebp),%eax
3ab: 0f b6 00 movzbl (%eax),%eax
3ae: 84 c0 test %al,%al
3b0: 75 e2 jne 394 <strchr+0xe>
if(*s == c)
return (char*)s;
return 0;
3b2: b8 00 00 00 00 mov $0x0,%eax
}
3b7: c9 leave
3b8: c3 ret
000003b9 <gets>:
char*
gets(char *buf, int max)
{
3b9: 55 push %ebp
3ba: 89 e5 mov %esp,%ebp
3bc: 83 ec 28 sub $0x28,%esp
int i, cc;
char c;
for(i=0; i+1 < max; ){
3bf: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
3c6: eb 44 jmp 40c <gets+0x53>
cc = read(0, &c, 1);
3c8: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
3cf: 00
3d0: 8d 45 ef lea -0x11(%ebp),%eax
3d3: 89 44 24 04 mov %eax,0x4(%esp)
3d7: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3de: e8 3d 01 00 00 call 520 <read>
3e3: 89 45 f4 mov %eax,-0xc(%ebp)
if(cc < 1)
3e6: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
3ea: 7e 2d jle 419 <gets+0x60>
break;
buf[i++] = c;
3ec: 8b 45 f0 mov -0x10(%ebp),%eax
3ef: 03 45 08 add 0x8(%ebp),%eax
3f2: 0f b6 55 ef movzbl -0x11(%ebp),%edx
3f6: 88 10 mov %dl,(%eax)
3f8: 83 45 f0 01 addl $0x1,-0x10(%ebp)
if(c == '\n' || c == '\r')
3fc: 0f b6 45 ef movzbl -0x11(%ebp),%eax
400: 3c 0a cmp $0xa,%al
402: 74 16 je 41a <gets+0x61>
404: 0f b6 45 ef movzbl -0x11(%ebp),%eax
408: 3c 0d cmp $0xd,%al
40a: 74 0e je 41a <gets+0x61>
gets(char *buf, int max)
{
int i, cc;
char c;
for(i=0; i+1 < max; ){
40c: 8b 45 f0 mov -0x10(%ebp),%eax
40f: 83 c0 01 add $0x1,%eax
412: 3b 45 0c cmp 0xc(%ebp),%eax
415: 7c b1 jl 3c8 <gets+0xf>
417: eb 01 jmp 41a <gets+0x61>
cc = read(0, &c, 1);
if(cc < 1)
break;
419: 90 nop
buf[i++] = c;
if(c == '\n' || c == '\r')
break;
}
buf[i] = '\0';
41a: 8b 45 f0 mov -0x10(%ebp),%eax
41d: 03 45 08 add 0x8(%ebp),%eax
420: c6 00 00 movb $0x0,(%eax)
return buf;
423: 8b 45 08 mov 0x8(%ebp),%eax
}
426: c9 leave
427: c3 ret
00000428 <stat>:
int
stat(char *n, struct stat *st)
{
428: 55 push %ebp
429: 89 e5 mov %esp,%ebp
42b: 83 ec 28 sub $0x28,%esp
int fd;
int r;
fd = open(n, O_RDONLY);
42e: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
435: 00
436: 8b 45 08 mov 0x8(%ebp),%eax
439: 89 04 24 mov %eax,(%esp)
43c: e8 07 01 00 00 call 548 <open>
441: 89 45 f0 mov %eax,-0x10(%ebp)
if(fd < 0)
444: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
448: 79 07 jns 451 <stat+0x29>
return -1;
44a: b8 ff ff ff ff mov $0xffffffff,%eax
44f: eb 23 jmp 474 <stat+0x4c>
r = fstat(fd, st);
451: 8b 45 0c mov 0xc(%ebp),%eax
454: 89 44 24 04 mov %eax,0x4(%esp)
458: 8b 45 f0 mov -0x10(%ebp),%eax
45b: 89 04 24 mov %eax,(%esp)
45e: e8 fd 00 00 00 call 560 <fstat>
463: 89 45 f4 mov %eax,-0xc(%ebp)
close(fd);
466: 8b 45 f0 mov -0x10(%ebp),%eax
469: 89 04 24 mov %eax,(%esp)
46c: e8 bf 00 00 00 call 530 <close>
return r;
471: 8b 45 f4 mov -0xc(%ebp),%eax
}
474: c9 leave
475: c3 ret
00000476 <atoi>:
int
atoi(const char *s)
{
476: 55 push %ebp
477: 89 e5 mov %esp,%ebp
479: 83 ec 10 sub $0x10,%esp
int n;
n = 0;
47c: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
while('0' <= *s && *s <= '9')
483: eb 24 jmp 4a9 <atoi+0x33>
n = n*10 + *s++ - '0';
485: 8b 55 fc mov -0x4(%ebp),%edx
488: 89 d0 mov %edx,%eax
48a: c1 e0 02 shl $0x2,%eax
48d: 01 d0 add %edx,%eax
48f: 01 c0 add %eax,%eax
491: 89 c2 mov %eax,%edx
493: 8b 45 08 mov 0x8(%ebp),%eax
496: 0f b6 00 movzbl (%eax),%eax
499: 0f be c0 movsbl %al,%eax
49c: 8d 04 02 lea (%edx,%eax,1),%eax
49f: 83 e8 30 sub $0x30,%eax
4a2: 89 45 fc mov %eax,-0x4(%ebp)
4a5: 83 45 08 01 addl $0x1,0x8(%ebp)
atoi(const char *s)
{
int n;
n = 0;
while('0' <= *s && *s <= '9')
4a9: 8b 45 08 mov 0x8(%ebp),%eax
4ac: 0f b6 00 movzbl (%eax),%eax
4af: 3c 2f cmp $0x2f,%al
4b1: 7e 0a jle 4bd <atoi+0x47>
4b3: 8b 45 08 mov 0x8(%ebp),%eax
4b6: 0f b6 00 movzbl (%eax),%eax
4b9: 3c 39 cmp $0x39,%al
4bb: 7e c8 jle 485 <atoi+0xf>
n = n*10 + *s++ - '0';
return n;
4bd: 8b 45 fc mov -0x4(%ebp),%eax
}
4c0: c9 leave
4c1: c3 ret
000004c2 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
4c2: 55 push %ebp
4c3: 89 e5 mov %esp,%ebp
4c5: 83 ec 10 sub $0x10,%esp
char *dst, *src;
dst = vdst;
4c8: 8b 45 08 mov 0x8(%ebp),%eax
4cb: 89 45 f8 mov %eax,-0x8(%ebp)
src = vsrc;
4ce: 8b 45 0c mov 0xc(%ebp),%eax
4d1: 89 45 fc mov %eax,-0x4(%ebp)
while(n-- > 0)
4d4: eb 13 jmp 4e9 <memmove+0x27>
*dst++ = *src++;
4d6: 8b 45 fc mov -0x4(%ebp),%eax
4d9: 0f b6 10 movzbl (%eax),%edx
4dc: 8b 45 f8 mov -0x8(%ebp),%eax
4df: 88 10 mov %dl,(%eax)
4e1: 83 45 f8 01 addl $0x1,-0x8(%ebp)
4e5: 83 45 fc 01 addl $0x1,-0x4(%ebp)
{
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
4e9: 83 7d 10 00 cmpl $0x0,0x10(%ebp)
4ed: 0f 9f c0 setg %al
4f0: 83 6d 10 01 subl $0x1,0x10(%ebp)
4f4: 84 c0 test %al,%al
4f6: 75 de jne 4d6 <memmove+0x14>
*dst++ = *src++;
return vdst;
4f8: 8b 45 08 mov 0x8(%ebp),%eax
}
4fb: c9 leave
4fc: c3 ret
4fd: 90 nop
4fe: 90 nop
4ff: 90 nop
00000500 <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
500: b8 01 00 00 00 mov $0x1,%eax
505: cd 40 int $0x40
507: c3 ret
00000508 <exit>:
SYSCALL(exit)
508: b8 02 00 00 00 mov $0x2,%eax
50d: cd 40 int $0x40
50f: c3 ret
00000510 <wait>:
SYSCALL(wait)
510: b8 03 00 00 00 mov $0x3,%eax
515: cd 40 int $0x40
517: c3 ret
00000518 <pipe>:
SYSCALL(pipe)
518: b8 04 00 00 00 mov $0x4,%eax
51d: cd 40 int $0x40
51f: c3 ret
00000520 <read>:
SYSCALL(read)
520: b8 05 00 00 00 mov $0x5,%eax
525: cd 40 int $0x40
527: c3 ret
00000528 <write>:
SYSCALL(write)
528: b8 10 00 00 00 mov $0x10,%eax
52d: cd 40 int $0x40
52f: c3 ret
00000530 <close>:
SYSCALL(close)
530: b8 15 00 00 00 mov $0x15,%eax
535: cd 40 int $0x40
537: c3 ret
00000538 <kill>:
SYSCALL(kill)
538: b8 06 00 00 00 mov $0x6,%eax
53d: cd 40 int $0x40
53f: c3 ret
00000540 <exec>:
SYSCALL(exec)
540: b8 07 00 00 00 mov $0x7,%eax
545: cd 40 int $0x40
547: c3 ret
00000548 <open>:
SYSCALL(open)
548: b8 0f 00 00 00 mov $0xf,%eax
54d: cd 40 int $0x40
54f: c3 ret
00000550 <mknod>:
SYSCALL(mknod)
550: b8 11 00 00 00 mov $0x11,%eax
555: cd 40 int $0x40
557: c3 ret
00000558 <unlink>:
SYSCALL(unlink)
558: b8 12 00 00 00 mov $0x12,%eax
55d: cd 40 int $0x40
55f: c3 ret
00000560 <fstat>:
SYSCALL(fstat)
560: b8 08 00 00 00 mov $0x8,%eax
565: cd 40 int $0x40
567: c3 ret
00000568 <link>:
SYSCALL(link)
568: b8 13 00 00 00 mov $0x13,%eax
56d: cd 40 int $0x40
56f: c3 ret
00000570 <mkdir>:
SYSCALL(mkdir)
570: b8 14 00 00 00 mov $0x14,%eax
575: cd 40 int $0x40
577: c3 ret
00000578 <chdir>:
SYSCALL(chdir)
578: b8 09 00 00 00 mov $0x9,%eax
57d: cd 40 int $0x40
57f: c3 ret
00000580 <dup>:
SYSCALL(dup)
580: b8 0a 00 00 00 mov $0xa,%eax
585: cd 40 int $0x40
587: c3 ret
00000588 <getpid>:
SYSCALL(getpid)
588: b8 0b 00 00 00 mov $0xb,%eax
58d: cd 40 int $0x40
58f: c3 ret
00000590 <sbrk>:
SYSCALL(sbrk)
590: b8 0c 00 00 00 mov $0xc,%eax
595: cd 40 int $0x40
597: c3 ret
00000598 <sleep>:
SYSCALL(sleep)
598: b8 0d 00 00 00 mov $0xd,%eax
59d: cd 40 int $0x40
59f: c3 ret
000005a0 <uptime>:
SYSCALL(uptime)
5a0: b8 0e 00 00 00 mov $0xe,%eax
5a5: cd 40 int $0x40
5a7: c3 ret
000005a8 <clone>:
SYSCALL(clone)
5a8: b8 16 00 00 00 mov $0x16,%eax
5ad: cd 40 int $0x40
5af: c3 ret
000005b0 <texit>:
SYSCALL(texit)
5b0: b8 17 00 00 00 mov $0x17,%eax
5b5: cd 40 int $0x40
5b7: c3 ret
000005b8 <tsleep>:
SYSCALL(tsleep)
5b8: b8 18 00 00 00 mov $0x18,%eax
5bd: cd 40 int $0x40
5bf: c3 ret
000005c0 <twakeup>:
SYSCALL(twakeup)
5c0: b8 19 00 00 00 mov $0x19,%eax
5c5: cd 40 int $0x40
5c7: c3 ret
000005c8 <thread_yield>:
SYSCALL(thread_yield)
5c8: b8 1a 00 00 00 mov $0x1a,%eax
5cd: cd 40 int $0x40
5cf: c3 ret
000005d0 <putc>:
#include "stat.h"
#include "user.h"
static void
putc(int fd, char c)
{
5d0: 55 push %ebp
5d1: 89 e5 mov %esp,%ebp
5d3: 83 ec 28 sub $0x28,%esp
5d6: 8b 45 0c mov 0xc(%ebp),%eax
5d9: 88 45 f4 mov %al,-0xc(%ebp)
write(fd, &c, 1);
5dc: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
5e3: 00
5e4: 8d 45 f4 lea -0xc(%ebp),%eax
5e7: 89 44 24 04 mov %eax,0x4(%esp)
5eb: 8b 45 08 mov 0x8(%ebp),%eax
5ee: 89 04 24 mov %eax,(%esp)
5f1: e8 32 ff ff ff call 528 <write>
}
5f6: c9 leave
5f7: c3 ret
000005f8 <printint>:
static void
printint(int fd, int xx, int base, int sgn)
{
5f8: 55 push %ebp
5f9: 89 e5 mov %esp,%ebp
5fb: 53 push %ebx
5fc: 83 ec 44 sub $0x44,%esp
static char digits[] = "0123456789ABCDEF";
char buf[16];
int i, neg;
uint x;
neg = 0;
5ff: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
if(sgn && xx < 0){
606: 83 7d 14 00 cmpl $0x0,0x14(%ebp)
60a: 74 17 je 623 <printint+0x2b>
60c: 83 7d 0c 00 cmpl $0x0,0xc(%ebp)
610: 79 11 jns 623 <printint+0x2b>
neg = 1;
612: c7 45 f0 01 00 00 00 movl $0x1,-0x10(%ebp)
x = -xx;
619: 8b 45 0c mov 0xc(%ebp),%eax
61c: f7 d8 neg %eax
61e: 89 45 f4 mov %eax,-0xc(%ebp)
char buf[16];
int i, neg;
uint x;
neg = 0;
if(sgn && xx < 0){
621: eb 06 jmp 629 <printint+0x31>
neg = 1;
x = -xx;
} else {
x = xx;
623: 8b 45 0c mov 0xc(%ebp),%eax
626: 89 45 f4 mov %eax,-0xc(%ebp)
}
i = 0;
629: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
do{
buf[i++] = digits[x % base];
630: 8b 4d ec mov -0x14(%ebp),%ecx
633: 8b 5d 10 mov 0x10(%ebp),%ebx
636: 8b 45 f4 mov -0xc(%ebp),%eax
639: ba 00 00 00 00 mov $0x0,%edx
63e: f7 f3 div %ebx
640: 89 d0 mov %edx,%eax
642: 0f b6 80 40 0e 00 00 movzbl 0xe40(%eax),%eax
649: 88 44 0d dc mov %al,-0x24(%ebp,%ecx,1)
64d: 83 45 ec 01 addl $0x1,-0x14(%ebp)
}while((x /= base) != 0);
651: 8b 45 10 mov 0x10(%ebp),%eax
654: 89 45 d4 mov %eax,-0x2c(%ebp)
657: 8b 45 f4 mov -0xc(%ebp),%eax
65a: ba 00 00 00 00 mov $0x0,%edx
65f: f7 75 d4 divl -0x2c(%ebp)
662: 89 45 f4 mov %eax,-0xc(%ebp)
665: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
669: 75 c5 jne 630 <printint+0x38>
if(neg)
66b: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
66f: 74 28 je 699 <printint+0xa1>
buf[i++] = '-';
671: 8b 45 ec mov -0x14(%ebp),%eax
674: c6 44 05 dc 2d movb $0x2d,-0x24(%ebp,%eax,1)
679: 83 45 ec 01 addl $0x1,-0x14(%ebp)
while(--i >= 0)
67d: eb 1a jmp 699 <printint+0xa1>
putc(fd, buf[i]);
67f: 8b 45 ec mov -0x14(%ebp),%eax
682: 0f b6 44 05 dc movzbl -0x24(%ebp,%eax,1),%eax
687: 0f be c0 movsbl %al,%eax
68a: 89 44 24 04 mov %eax,0x4(%esp)
68e: 8b 45 08 mov 0x8(%ebp),%eax
691: 89 04 24 mov %eax,(%esp)
694: e8 37 ff ff ff call 5d0 <putc>
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
699: 83 6d ec 01 subl $0x1,-0x14(%ebp)
69d: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
6a1: 79 dc jns 67f <printint+0x87>
putc(fd, buf[i]);
}
6a3: 83 c4 44 add $0x44,%esp
6a6: 5b pop %ebx
6a7: 5d pop %ebp
6a8: c3 ret
000006a9 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
6a9: 55 push %ebp
6aa: 89 e5 mov %esp,%ebp
6ac: 83 ec 38 sub $0x38,%esp
char *s;
int c, i, state;
uint *ap;
state = 0;
6af: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
ap = (uint*)(void*)&fmt + 1;
6b6: 8d 45 0c lea 0xc(%ebp),%eax
6b9: 83 c0 04 add $0x4,%eax
6bc: 89 45 f4 mov %eax,-0xc(%ebp)
for(i = 0; fmt[i]; i++){
6bf: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
6c6: e9 7e 01 00 00 jmp 849 <printf+0x1a0>
c = fmt[i] & 0xff;
6cb: 8b 55 0c mov 0xc(%ebp),%edx
6ce: 8b 45 ec mov -0x14(%ebp),%eax
6d1: 8d 04 02 lea (%edx,%eax,1),%eax
6d4: 0f b6 00 movzbl (%eax),%eax
6d7: 0f be c0 movsbl %al,%eax
6da: 25 ff 00 00 00 and $0xff,%eax
6df: 89 45 e8 mov %eax,-0x18(%ebp)
if(state == 0){
6e2: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
6e6: 75 2c jne 714 <printf+0x6b>
if(c == '%'){
6e8: 83 7d e8 25 cmpl $0x25,-0x18(%ebp)
6ec: 75 0c jne 6fa <printf+0x51>
state = '%';
6ee: c7 45 f0 25 00 00 00 movl $0x25,-0x10(%ebp)
6f5: e9 4b 01 00 00 jmp 845 <printf+0x19c>
} else {
putc(fd, c);
6fa: 8b 45 e8 mov -0x18(%ebp),%eax
6fd: 0f be c0 movsbl %al,%eax
700: 89 44 24 04 mov %eax,0x4(%esp)
704: 8b 45 08 mov 0x8(%ebp),%eax
707: 89 04 24 mov %eax,(%esp)
70a: e8 c1 fe ff ff call 5d0 <putc>
70f: e9 31 01 00 00 jmp 845 <printf+0x19c>
}
} else if(state == '%'){
714: 83 7d f0 25 cmpl $0x25,-0x10(%ebp)
718: 0f 85 27 01 00 00 jne 845 <printf+0x19c>
if(c == 'd'){
71e: 83 7d e8 64 cmpl $0x64,-0x18(%ebp)
722: 75 2d jne 751 <printf+0xa8>
printint(fd, *ap, 10, 1);
724: 8b 45 f4 mov -0xc(%ebp),%eax
727: 8b 00 mov (%eax),%eax
729: c7 44 24 0c 01 00 00 movl $0x1,0xc(%esp)
730: 00
731: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
738: 00
739: 89 44 24 04 mov %eax,0x4(%esp)
73d: 8b 45 08 mov 0x8(%ebp),%eax
740: 89 04 24 mov %eax,(%esp)
743: e8 b0 fe ff ff call 5f8 <printint>
ap++;
748: 83 45 f4 04 addl $0x4,-0xc(%ebp)
74c: e9 ed 00 00 00 jmp 83e <printf+0x195>
} else if(c == 'x' || c == 'p'){
751: 83 7d e8 78 cmpl $0x78,-0x18(%ebp)
755: 74 06 je 75d <printf+0xb4>
757: 83 7d e8 70 cmpl $0x70,-0x18(%ebp)
75b: 75 2d jne 78a <printf+0xe1>
printint(fd, *ap, 16, 0);
75d: 8b 45 f4 mov -0xc(%ebp),%eax
760: 8b 00 mov (%eax),%eax
762: c7 44 24 0c 00 00 00 movl $0x0,0xc(%esp)
769: 00
76a: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
771: 00
772: 89 44 24 04 mov %eax,0x4(%esp)
776: 8b 45 08 mov 0x8(%ebp),%eax
779: 89 04 24 mov %eax,(%esp)
77c: e8 77 fe ff ff call 5f8 <printint>
ap++;
781: 83 45 f4 04 addl $0x4,-0xc(%ebp)
}
} else if(state == '%'){
if(c == 'd'){
printint(fd, *ap, 10, 1);
ap++;
} else if(c == 'x' || c == 'p'){
785: e9 b4 00 00 00 jmp 83e <printf+0x195>
printint(fd, *ap, 16, 0);
ap++;
} else if(c == 's'){
78a: 83 7d e8 73 cmpl $0x73,-0x18(%ebp)
78e: 75 46 jne 7d6 <printf+0x12d>
s = (char*)*ap;
790: 8b 45 f4 mov -0xc(%ebp),%eax
793: 8b 00 mov (%eax),%eax
795: 89 45 e4 mov %eax,-0x1c(%ebp)
ap++;
798: 83 45 f4 04 addl $0x4,-0xc(%ebp)
if(s == 0)
79c: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
7a0: 75 27 jne 7c9 <printf+0x120>
s = "(null)";
7a2: c7 45 e4 f0 0d 00 00 movl $0xdf0,-0x1c(%ebp)
while(*s != 0){
7a9: eb 1f jmp 7ca <printf+0x121>
putc(fd, *s);
7ab: 8b 45 e4 mov -0x1c(%ebp),%eax
7ae: 0f b6 00 movzbl (%eax),%eax
7b1: 0f be c0 movsbl %al,%eax
7b4: 89 44 24 04 mov %eax,0x4(%esp)
7b8: 8b 45 08 mov 0x8(%ebp),%eax
7bb: 89 04 24 mov %eax,(%esp)
7be: e8 0d fe ff ff call 5d0 <putc>
s++;
7c3: 83 45 e4 01 addl $0x1,-0x1c(%ebp)
7c7: eb 01 jmp 7ca <printf+0x121>
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
7c9: 90 nop
7ca: 8b 45 e4 mov -0x1c(%ebp),%eax
7cd: 0f b6 00 movzbl (%eax),%eax
7d0: 84 c0 test %al,%al
7d2: 75 d7 jne 7ab <printf+0x102>
7d4: eb 68 jmp 83e <printf+0x195>
putc(fd, *s);
s++;
}
} else if(c == 'c'){
7d6: 83 7d e8 63 cmpl $0x63,-0x18(%ebp)
7da: 75 1d jne 7f9 <printf+0x150>
putc(fd, *ap);
7dc: 8b 45 f4 mov -0xc(%ebp),%eax
7df: 8b 00 mov (%eax),%eax
7e1: 0f be c0 movsbl %al,%eax
7e4: 89 44 24 04 mov %eax,0x4(%esp)
7e8: 8b 45 08 mov 0x8(%ebp),%eax
7eb: 89 04 24 mov %eax,(%esp)
7ee: e8 dd fd ff ff call 5d0 <putc>
ap++;
7f3: 83 45 f4 04 addl $0x4,-0xc(%ebp)
7f7: eb 45 jmp 83e <printf+0x195>
} else if(c == '%'){
7f9: 83 7d e8 25 cmpl $0x25,-0x18(%ebp)
7fd: 75 17 jne 816 <printf+0x16d>
putc(fd, c);
7ff: 8b 45 e8 mov -0x18(%ebp),%eax
802: 0f be c0 movsbl %al,%eax
805: 89 44 24 04 mov %eax,0x4(%esp)
809: 8b 45 08 mov 0x8(%ebp),%eax
80c: 89 04 24 mov %eax,(%esp)
80f: e8 bc fd ff ff call 5d0 <putc>
814: eb 28 jmp 83e <printf+0x195>
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
816: c7 44 24 04 25 00 00 movl $0x25,0x4(%esp)
81d: 00
81e: 8b 45 08 mov 0x8(%ebp),%eax
821: 89 04 24 mov %eax,(%esp)
824: e8 a7 fd ff ff call 5d0 <putc>
putc(fd, c);
829: 8b 45 e8 mov -0x18(%ebp),%eax
82c: 0f be c0 movsbl %al,%eax
82f: 89 44 24 04 mov %eax,0x4(%esp)
833: 8b 45 08 mov 0x8(%ebp),%eax
836: 89 04 24 mov %eax,(%esp)
839: e8 92 fd ff ff call 5d0 <putc>
}
state = 0;
83e: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
845: 83 45 ec 01 addl $0x1,-0x14(%ebp)
849: 8b 55 0c mov 0xc(%ebp),%edx
84c: 8b 45 ec mov -0x14(%ebp),%eax
84f: 8d 04 02 lea (%edx,%eax,1),%eax
852: 0f b6 00 movzbl (%eax),%eax
855: 84 c0 test %al,%al
857: 0f 85 6e fe ff ff jne 6cb <printf+0x22>
putc(fd, c);
}
state = 0;
}
}
}
85d: c9 leave
85e: c3 ret
85f: 90 nop
00000860 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
860: 55 push %ebp
861: 89 e5 mov %esp,%ebp
863: 83 ec 10 sub $0x10,%esp
Header *bp, *p;
bp = (Header*)ap - 1;
866: 8b 45 08 mov 0x8(%ebp),%eax
869: 83 e8 08 sub $0x8,%eax
86c: 89 45 f8 mov %eax,-0x8(%ebp)
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
86f: a1 5c 0e 00 00 mov 0xe5c,%eax
874: 89 45 fc mov %eax,-0x4(%ebp)
877: eb 24 jmp 89d <free+0x3d>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
879: 8b 45 fc mov -0x4(%ebp),%eax
87c: 8b 00 mov (%eax),%eax
87e: 3b 45 fc cmp -0x4(%ebp),%eax
881: 77 12 ja 895 <free+0x35>
883: 8b 45 f8 mov -0x8(%ebp),%eax
886: 3b 45 fc cmp -0x4(%ebp),%eax
889: 77 24 ja 8af <free+0x4f>
88b: 8b 45 fc mov -0x4(%ebp),%eax
88e: 8b 00 mov (%eax),%eax
890: 3b 45 f8 cmp -0x8(%ebp),%eax
893: 77 1a ja 8af <free+0x4f>
free(void *ap)
{
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
895: 8b 45 fc mov -0x4(%ebp),%eax
898: 8b 00 mov (%eax),%eax
89a: 89 45 fc mov %eax,-0x4(%ebp)
89d: 8b 45 f8 mov -0x8(%ebp),%eax
8a0: 3b 45 fc cmp -0x4(%ebp),%eax
8a3: 76 d4 jbe 879 <free+0x19>
8a5: 8b 45 fc mov -0x4(%ebp),%eax
8a8: 8b 00 mov (%eax),%eax
8aa: 3b 45 f8 cmp -0x8(%ebp),%eax
8ad: 76 ca jbe 879 <free+0x19>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
8af: 8b 45 f8 mov -0x8(%ebp),%eax
8b2: 8b 40 04 mov 0x4(%eax),%eax
8b5: c1 e0 03 shl $0x3,%eax
8b8: 89 c2 mov %eax,%edx
8ba: 03 55 f8 add -0x8(%ebp),%edx
8bd: 8b 45 fc mov -0x4(%ebp),%eax
8c0: 8b 00 mov (%eax),%eax
8c2: 39 c2 cmp %eax,%edx
8c4: 75 24 jne 8ea <free+0x8a>
bp->s.size += p->s.ptr->s.size;
8c6: 8b 45 f8 mov -0x8(%ebp),%eax
8c9: 8b 50 04 mov 0x4(%eax),%edx
8cc: 8b 45 fc mov -0x4(%ebp),%eax
8cf: 8b 00 mov (%eax),%eax
8d1: 8b 40 04 mov 0x4(%eax),%eax
8d4: 01 c2 add %eax,%edx
8d6: 8b 45 f8 mov -0x8(%ebp),%eax
8d9: 89 50 04 mov %edx,0x4(%eax)
bp->s.ptr = p->s.ptr->s.ptr;
8dc: 8b 45 fc mov -0x4(%ebp),%eax
8df: 8b 00 mov (%eax),%eax
8e1: 8b 10 mov (%eax),%edx
8e3: 8b 45 f8 mov -0x8(%ebp),%eax
8e6: 89 10 mov %edx,(%eax)
8e8: eb 0a jmp 8f4 <free+0x94>
} else
bp->s.ptr = p->s.ptr;
8ea: 8b 45 fc mov -0x4(%ebp),%eax
8ed: 8b 10 mov (%eax),%edx
8ef: 8b 45 f8 mov -0x8(%ebp),%eax
8f2: 89 10 mov %edx,(%eax)
if(p + p->s.size == bp){
8f4: 8b 45 fc mov -0x4(%ebp),%eax
8f7: 8b 40 04 mov 0x4(%eax),%eax
8fa: c1 e0 03 shl $0x3,%eax
8fd: 03 45 fc add -0x4(%ebp),%eax
900: 3b 45 f8 cmp -0x8(%ebp),%eax
903: 75 20 jne 925 <free+0xc5>
p->s.size += bp->s.size;
905: 8b 45 fc mov -0x4(%ebp),%eax
908: 8b 50 04 mov 0x4(%eax),%edx
90b: 8b 45 f8 mov -0x8(%ebp),%eax
90e: 8b 40 04 mov 0x4(%eax),%eax
911: 01 c2 add %eax,%edx
913: 8b 45 fc mov -0x4(%ebp),%eax
916: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
919: 8b 45 f8 mov -0x8(%ebp),%eax
91c: 8b 10 mov (%eax),%edx
91e: 8b 45 fc mov -0x4(%ebp),%eax
921: 89 10 mov %edx,(%eax)
923: eb 08 jmp 92d <free+0xcd>
} else
p->s.ptr = bp;
925: 8b 45 fc mov -0x4(%ebp),%eax
928: 8b 55 f8 mov -0x8(%ebp),%edx
92b: 89 10 mov %edx,(%eax)
freep = p;
92d: 8b 45 fc mov -0x4(%ebp),%eax
930: a3 5c 0e 00 00 mov %eax,0xe5c
}
935: c9 leave
936: c3 ret
00000937 <morecore>:
static Header*
morecore(uint nu)
{
937: 55 push %ebp
938: 89 e5 mov %esp,%ebp
93a: 83 ec 28 sub $0x28,%esp
char *p;
Header *hp;
if(nu < 4096)
93d: 81 7d 08 ff 0f 00 00 cmpl $0xfff,0x8(%ebp)
944: 77 07 ja 94d <morecore+0x16>
nu = 4096;
946: c7 45 08 00 10 00 00 movl $0x1000,0x8(%ebp)
p = sbrk(nu * sizeof(Header));
94d: 8b 45 08 mov 0x8(%ebp),%eax
950: c1 e0 03 shl $0x3,%eax
953: 89 04 24 mov %eax,(%esp)
956: e8 35 fc ff ff call 590 <sbrk>
95b: 89 45 f0 mov %eax,-0x10(%ebp)
if(p == (char*)-1)
95e: 83 7d f0 ff cmpl $0xffffffff,-0x10(%ebp)
962: 75 07 jne 96b <morecore+0x34>
return 0;
964: b8 00 00 00 00 mov $0x0,%eax
969: eb 22 jmp 98d <morecore+0x56>
hp = (Header*)p;
96b: 8b 45 f0 mov -0x10(%ebp),%eax
96e: 89 45 f4 mov %eax,-0xc(%ebp)
hp->s.size = nu;
971: 8b 45 f4 mov -0xc(%ebp),%eax
974: 8b 55 08 mov 0x8(%ebp),%edx
977: 89 50 04 mov %edx,0x4(%eax)
free((void*)(hp + 1));
97a: 8b 45 f4 mov -0xc(%ebp),%eax
97d: 83 c0 08 add $0x8,%eax
980: 89 04 24 mov %eax,(%esp)
983: e8 d8 fe ff ff call 860 <free>
return freep;
988: a1 5c 0e 00 00 mov 0xe5c,%eax
}
98d: c9 leave
98e: c3 ret
0000098f <malloc>:
void*
malloc(uint nbytes)
{
98f: 55 push %ebp
990: 89 e5 mov %esp,%ebp
992: 83 ec 28 sub $0x28,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
995: 8b 45 08 mov 0x8(%ebp),%eax
998: 83 c0 07 add $0x7,%eax
99b: c1 e8 03 shr $0x3,%eax
99e: 83 c0 01 add $0x1,%eax
9a1: 89 45 f4 mov %eax,-0xc(%ebp)
if((prevp = freep) == 0){
9a4: a1 5c 0e 00 00 mov 0xe5c,%eax
9a9: 89 45 f0 mov %eax,-0x10(%ebp)
9ac: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
9b0: 75 23 jne 9d5 <malloc+0x46>
base.s.ptr = freep = prevp = &base;
9b2: c7 45 f0 54 0e 00 00 movl $0xe54,-0x10(%ebp)
9b9: 8b 45 f0 mov -0x10(%ebp),%eax
9bc: a3 5c 0e 00 00 mov %eax,0xe5c
9c1: a1 5c 0e 00 00 mov 0xe5c,%eax
9c6: a3 54 0e 00 00 mov %eax,0xe54
base.s.size = 0;
9cb: c7 05 58 0e 00 00 00 movl $0x0,0xe58
9d2: 00 00 00
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
9d5: 8b 45 f0 mov -0x10(%ebp),%eax
9d8: 8b 00 mov (%eax),%eax
9da: 89 45 ec mov %eax,-0x14(%ebp)
if(p->s.size >= nunits){
9dd: 8b 45 ec mov -0x14(%ebp),%eax
9e0: 8b 40 04 mov 0x4(%eax),%eax
9e3: 3b 45 f4 cmp -0xc(%ebp),%eax
9e6: 72 4d jb a35 <malloc+0xa6>
if(p->s.size == nunits)
9e8: 8b 45 ec mov -0x14(%ebp),%eax
9eb: 8b 40 04 mov 0x4(%eax),%eax
9ee: 3b 45 f4 cmp -0xc(%ebp),%eax
9f1: 75 0c jne 9ff <malloc+0x70>
prevp->s.ptr = p->s.ptr;
9f3: 8b 45 ec mov -0x14(%ebp),%eax
9f6: 8b 10 mov (%eax),%edx
9f8: 8b 45 f0 mov -0x10(%ebp),%eax
9fb: 89 10 mov %edx,(%eax)
9fd: eb 26 jmp a25 <malloc+0x96>
else {
p->s.size -= nunits;
9ff: 8b 45 ec mov -0x14(%ebp),%eax
a02: 8b 40 04 mov 0x4(%eax),%eax
a05: 89 c2 mov %eax,%edx
a07: 2b 55 f4 sub -0xc(%ebp),%edx
a0a: 8b 45 ec mov -0x14(%ebp),%eax
a0d: 89 50 04 mov %edx,0x4(%eax)
p += p->s.size;
a10: 8b 45 ec mov -0x14(%ebp),%eax
a13: 8b 40 04 mov 0x4(%eax),%eax
a16: c1 e0 03 shl $0x3,%eax
a19: 01 45 ec add %eax,-0x14(%ebp)
p->s.size = nunits;
a1c: 8b 45 ec mov -0x14(%ebp),%eax
a1f: 8b 55 f4 mov -0xc(%ebp),%edx
a22: 89 50 04 mov %edx,0x4(%eax)
}
freep = prevp;
a25: 8b 45 f0 mov -0x10(%ebp),%eax
a28: a3 5c 0e 00 00 mov %eax,0xe5c
return (void*)(p + 1);
a2d: 8b 45 ec mov -0x14(%ebp),%eax
a30: 83 c0 08 add $0x8,%eax
a33: eb 38 jmp a6d <malloc+0xde>
}
if(p == freep)
a35: a1 5c 0e 00 00 mov 0xe5c,%eax
a3a: 39 45 ec cmp %eax,-0x14(%ebp)
a3d: 75 1b jne a5a <malloc+0xcb>
if((p = morecore(nunits)) == 0)
a3f: 8b 45 f4 mov -0xc(%ebp),%eax
a42: 89 04 24 mov %eax,(%esp)
a45: e8 ed fe ff ff call 937 <morecore>
a4a: 89 45 ec mov %eax,-0x14(%ebp)
a4d: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
a51: 75 07 jne a5a <malloc+0xcb>
return 0;
a53: b8 00 00 00 00 mov $0x0,%eax
a58: eb 13 jmp a6d <malloc+0xde>
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
a5a: 8b 45 ec mov -0x14(%ebp),%eax
a5d: 89 45 f0 mov %eax,-0x10(%ebp)
a60: 8b 45 ec mov -0x14(%ebp),%eax
a63: 8b 00 mov (%eax),%eax
a65: 89 45 ec mov %eax,-0x14(%ebp)
return (void*)(p + 1);
}
if(p == freep)
if((p = morecore(nunits)) == 0)
return 0;
}
a68: e9 70 ff ff ff jmp 9dd <malloc+0x4e>
}
a6d: c9 leave
a6e: c3 ret
a6f: 90 nop
00000a70 <xchg>:
asm volatile("sti");
}
static inline uint
xchg(volatile uint *addr, uint newval)
{
a70: 55 push %ebp
a71: 89 e5 mov %esp,%ebp
a73: 83 ec 10 sub $0x10,%esp
uint result;
// The + in "+m" denotes a read-modify-write operand.
asm volatile("lock; xchgl %0, %1" :
a76: 8b 55 08 mov 0x8(%ebp),%edx
a79: 8b 45 0c mov 0xc(%ebp),%eax
a7c: 8b 4d 08 mov 0x8(%ebp),%ecx
a7f: f0 87 02 lock xchg %eax,(%edx)
a82: 89 45 fc mov %eax,-0x4(%ebp)
"+m" (*addr), "=a" (result) :
"1" (newval) :
"cc");
return result;
a85: 8b 45 fc mov -0x4(%ebp),%eax
}
a88: c9 leave
a89: c3 ret
00000a8a <lock_init>:
#include "x86.h"
#include "proc.h"
void lock_init(lock_t *lock){
a8a: 55 push %ebp
a8b: 89 e5 mov %esp,%ebp
lock->locked = 0;
a8d: 8b 45 08 mov 0x8(%ebp),%eax
a90: c7 00 00 00 00 00 movl $0x0,(%eax)
}
a96: 5d pop %ebp
a97: c3 ret
00000a98 <lock_acquire>:
void lock_acquire(lock_t *lock){
a98: 55 push %ebp
a99: 89 e5 mov %esp,%ebp
a9b: 83 ec 08 sub $0x8,%esp
while(xchg(&lock->locked,1) != 0);
a9e: 8b 45 08 mov 0x8(%ebp),%eax
aa1: c7 44 24 04 01 00 00 movl $0x1,0x4(%esp)
aa8: 00
aa9: 89 04 24 mov %eax,(%esp)
aac: e8 bf ff ff ff call a70 <xchg>
ab1: 85 c0 test %eax,%eax
ab3: 75 e9 jne a9e <lock_acquire+0x6>
}
ab5: c9 leave
ab6: c3 ret
00000ab7 <lock_release>:
void lock_release(lock_t *lock){
ab7: 55 push %ebp
ab8: 89 e5 mov %esp,%ebp
aba: 83 ec 08 sub $0x8,%esp
xchg(&lock->locked,0);
abd: 8b 45 08 mov 0x8(%ebp),%eax
ac0: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
ac7: 00
ac8: 89 04 24 mov %eax,(%esp)
acb: e8 a0 ff ff ff call a70 <xchg>
}
ad0: c9 leave
ad1: c3 ret
00000ad2 <thread_create>:
void *thread_create(void(*start_routine)(void*), void *arg){
ad2: 55 push %ebp
ad3: 89 e5 mov %esp,%ebp
ad5: 83 ec 28 sub $0x28,%esp
int tid;
void * stack = malloc(2 * 4096);
ad8: c7 04 24 00 20 00 00 movl $0x2000,(%esp)
adf: e8 ab fe ff ff call 98f <malloc>
ae4: 89 45 f0 mov %eax,-0x10(%ebp)
void *garbage_stack = stack;
ae7: 8b 45 f0 mov -0x10(%ebp),%eax
aea: 89 45 f4 mov %eax,-0xc(%ebp)
// printf(1,"start routine addr : %d\n",(uint)start_routine);
if((uint)stack % 4096){
aed: 8b 45 f0 mov -0x10(%ebp),%eax
af0: 25 ff 0f 00 00 and $0xfff,%eax
af5: 85 c0 test %eax,%eax
af7: 74 15 je b0e <thread_create+0x3c>
stack = stack + (4096 - (uint)stack % 4096);
af9: 8b 45 f0 mov -0x10(%ebp),%eax
afc: 89 c2 mov %eax,%edx
afe: 81 e2 ff 0f 00 00 and $0xfff,%edx
b04: b8 00 10 00 00 mov $0x1000,%eax
b09: 29 d0 sub %edx,%eax
b0b: 01 45 f0 add %eax,-0x10(%ebp)
}
if (stack == 0){
b0e: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
b12: 75 1b jne b2f <thread_create+0x5d>
printf(1,"malloc fail \n");
b14: c7 44 24 04 f7 0d 00 movl $0xdf7,0x4(%esp)
b1b: 00
b1c: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b23: e8 81 fb ff ff call 6a9 <printf>
return 0;
b28: b8 00 00 00 00 mov $0x0,%eax
b2d: eb 6f jmp b9e <thread_create+0xcc>
}
tid = clone((uint)stack,PSIZE,(uint)start_routine,(int)arg);
b2f: 8b 4d 0c mov 0xc(%ebp),%ecx
b32: 8b 55 08 mov 0x8(%ebp),%edx
b35: 8b 45 f0 mov -0x10(%ebp),%eax
b38: 89 4c 24 0c mov %ecx,0xc(%esp)
b3c: 89 54 24 08 mov %edx,0x8(%esp)
b40: c7 44 24 04 00 10 00 movl $0x1000,0x4(%esp)
b47: 00
b48: 89 04 24 mov %eax,(%esp)
b4b: e8 58 fa ff ff call 5a8 <clone>
b50: 89 45 ec mov %eax,-0x14(%ebp)
if(tid < 0){
b53: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
b57: 79 1b jns b74 <thread_create+0xa2>
printf(1,"clone fails\n");
b59: c7 44 24 04 05 0e 00 movl $0xe05,0x4(%esp)
b60: 00
b61: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b68: e8 3c fb ff ff call 6a9 <printf>
return 0;
b6d: b8 00 00 00 00 mov $0x0,%eax
b72: eb 2a jmp b9e <thread_create+0xcc>
}
if(tid > 0){
b74: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
b78: 7e 05 jle b7f <thread_create+0xad>
//store threads on thread table
return garbage_stack;
b7a: 8b 45 f4 mov -0xc(%ebp),%eax
b7d: eb 1f jmp b9e <thread_create+0xcc>
}
if(tid == 0){
b7f: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
b83: 75 14 jne b99 <thread_create+0xc7>
printf(1,"tid = 0 return \n");
b85: c7 44 24 04 12 0e 00 movl $0xe12,0x4(%esp)
b8c: 00
b8d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b94: e8 10 fb ff ff call 6a9 <printf>
}
// wait();
// free(garbage_stack);
return 0;
b99: b8 00 00 00 00 mov $0x0,%eax
}
b9e: c9 leave
b9f: c3 ret
00000ba0 <init_q>:
#include "queue.h"
#include "types.h"
#include "user.h"
void init_q(struct queue *q){
ba0: 55 push %ebp
ba1: 89 e5 mov %esp,%ebp
q->size = 0;
ba3: 8b 45 08 mov 0x8(%ebp),%eax
ba6: c7 00 00 00 00 00 movl $0x0,(%eax)
q->head = 0;
bac: 8b 45 08 mov 0x8(%ebp),%eax
baf: c7 40 04 00 00 00 00 movl $0x0,0x4(%eax)
q->tail = 0;
bb6: 8b 45 08 mov 0x8(%ebp),%eax
bb9: c7 40 08 00 00 00 00 movl $0x0,0x8(%eax)
}
bc0: 5d pop %ebp
bc1: c3 ret
00000bc2 <add_q>:
void add_q(struct queue *q, int v){
bc2: 55 push %ebp
bc3: 89 e5 mov %esp,%ebp
bc5: 83 ec 28 sub $0x28,%esp
//printf(1, "here \n");
struct node * n = malloc(sizeof(struct node));
bc8: c7 04 24 08 00 00 00 movl $0x8,(%esp)
bcf: e8 bb fd ff ff call 98f <malloc>
bd4: 89 45 f4 mov %eax,-0xc(%ebp)
n->next = 0;
bd7: 8b 45 f4 mov -0xc(%ebp),%eax
bda: c7 40 04 00 00 00 00 movl $0x0,0x4(%eax)
n->value = v;
be1: 8b 45 f4 mov -0xc(%ebp),%eax
be4: 8b 55 0c mov 0xc(%ebp),%edx
be7: 89 10 mov %edx,(%eax)
if(q->head == 0){
be9: 8b 45 08 mov 0x8(%ebp),%eax
bec: 8b 40 04 mov 0x4(%eax),%eax
bef: 85 c0 test %eax,%eax
bf1: 75 0b jne bfe <add_q+0x3c>
q->head = n;
bf3: 8b 45 08 mov 0x8(%ebp),%eax
bf6: 8b 55 f4 mov -0xc(%ebp),%edx
bf9: 89 50 04 mov %edx,0x4(%eax)
bfc: eb 0c jmp c0a <add_q+0x48>
}else{
q->tail->next = n;
bfe: 8b 45 08 mov 0x8(%ebp),%eax
c01: 8b 40 08 mov 0x8(%eax),%eax
c04: 8b 55 f4 mov -0xc(%ebp),%edx
c07: 89 50 04 mov %edx,0x4(%eax)
}
q->tail = n;
c0a: 8b 45 08 mov 0x8(%ebp),%eax
c0d: 8b 55 f4 mov -0xc(%ebp),%edx
c10: 89 50 08 mov %edx,0x8(%eax)
q->size++;
c13: 8b 45 08 mov 0x8(%ebp),%eax
c16: 8b 00 mov (%eax),%eax
c18: 8d 50 01 lea 0x1(%eax),%edx
c1b: 8b 45 08 mov 0x8(%ebp),%eax
c1e: 89 10 mov %edx,(%eax)
}
c20: c9 leave
c21: c3 ret
00000c22 <empty_q>:
int empty_q(struct queue *q){
c22: 55 push %ebp
c23: 89 e5 mov %esp,%ebp
if(q->size == 0)
c25: 8b 45 08 mov 0x8(%ebp),%eax
c28: 8b 00 mov (%eax),%eax
c2a: 85 c0 test %eax,%eax
c2c: 75 07 jne c35 <empty_q+0x13>
return 1;
c2e: b8 01 00 00 00 mov $0x1,%eax
c33: eb 05 jmp c3a <empty_q+0x18>
else
return 0;
c35: b8 00 00 00 00 mov $0x0,%eax
}
c3a: 5d pop %ebp
c3b: c3 ret
00000c3c <pop_q>:
int pop_q(struct queue *q){
c3c: 55 push %ebp
c3d: 89 e5 mov %esp,%ebp
c3f: 83 ec 28 sub $0x28,%esp
int val;
struct node *destroy;
if(!empty_q(q)){
c42: 8b 45 08 mov 0x8(%ebp),%eax
c45: 89 04 24 mov %eax,(%esp)
c48: e8 d5 ff ff ff call c22 <empty_q>
c4d: 85 c0 test %eax,%eax
c4f: 75 5d jne cae <pop_q+0x72>
val = q->head->value;
c51: 8b 45 08 mov 0x8(%ebp),%eax
c54: 8b 40 04 mov 0x4(%eax),%eax
c57: 8b 00 mov (%eax),%eax
c59: 89 45 f0 mov %eax,-0x10(%ebp)
destroy = q->head;
c5c: 8b 45 08 mov 0x8(%ebp),%eax
c5f: 8b 40 04 mov 0x4(%eax),%eax
c62: 89 45 f4 mov %eax,-0xc(%ebp)
q->head = q->head->next;
c65: 8b 45 08 mov 0x8(%ebp),%eax
c68: 8b 40 04 mov 0x4(%eax),%eax
c6b: 8b 50 04 mov 0x4(%eax),%edx
c6e: 8b 45 08 mov 0x8(%ebp),%eax
c71: 89 50 04 mov %edx,0x4(%eax)
free(destroy);
c74: 8b 45 f4 mov -0xc(%ebp),%eax
c77: 89 04 24 mov %eax,(%esp)
c7a: e8 e1 fb ff ff call 860 <free>
q->size--;
c7f: 8b 45 08 mov 0x8(%ebp),%eax
c82: 8b 00 mov (%eax),%eax
c84: 8d 50 ff lea -0x1(%eax),%edx
c87: 8b 45 08 mov 0x8(%ebp),%eax
c8a: 89 10 mov %edx,(%eax)
if(q->size == 0){
c8c: 8b 45 08 mov 0x8(%ebp),%eax
c8f: 8b 00 mov (%eax),%eax
c91: 85 c0 test %eax,%eax
c93: 75 14 jne ca9 <pop_q+0x6d>
q->head = 0;
c95: 8b 45 08 mov 0x8(%ebp),%eax
c98: c7 40 04 00 00 00 00 movl $0x0,0x4(%eax)
q->tail = 0;
c9f: 8b 45 08 mov 0x8(%ebp),%eax
ca2: c7 40 08 00 00 00 00 movl $0x0,0x8(%eax)
}
return val;
ca9: 8b 45 f0 mov -0x10(%ebp),%eax
cac: eb 05 jmp cb3 <pop_q+0x77>
}
return -1;
cae: b8 ff ff ff ff mov $0xffffffff,%eax
}
cb3: c9 leave
cb4: c3 ret
cb5: 90 nop
cb6: 90 nop
cb7: 90 nop
00000cb8 <init_semaphore>:
#include "semaphore.h"
#include "user.h"
//lab 2
//Semaphore
void init_semaphore(struct Semaphore *s, int count_num) {
cb8: 55 push %ebp
cb9: 89 e5 mov %esp,%ebp
cbb: 83 ec 18 sub $0x18,%esp
s->count = count_num;
cbe: 8b 45 08 mov 0x8(%ebp),%eax
cc1: 8b 55 0c mov 0xc(%ebp),%edx
cc4: 89 10 mov %edx,(%eax)
init_q(&s->threads);
cc6: 8b 45 08 mov 0x8(%ebp),%eax
cc9: 83 c0 04 add $0x4,%eax
ccc: 89 04 24 mov %eax,(%esp)
ccf: e8 cc fe ff ff call ba0 <init_q>
lock_init(&s->lock);
cd4: 8b 45 08 mov 0x8(%ebp),%eax
cd7: 83 c0 10 add $0x10,%eax
cda: 89 04 24 mov %eax,(%esp)
cdd: e8 a8 fd ff ff call a8a <lock_init>
}
ce2: c9 leave
ce3: c3 ret
00000ce4 <sem_acquire>:
void sem_acquire(struct Semaphore *s) {
ce4: 55 push %ebp
ce5: 89 e5 mov %esp,%ebp
ce7: 83 ec 18 sub $0x18,%esp
while(1) {
if (s->count > 0) { //if there are available resources
cea: 8b 45 08 mov 0x8(%ebp),%eax
ced: 8b 00 mov (%eax),%eax
cef: 85 c0 test %eax,%eax
cf1: 7e 2c jle d1f <sem_acquire+0x3b>
//printf(1, "COUNT IS = %d\n", s->count);
//printf(1, "acquiring lock\n");
lock_acquire(&s->lock); //acquire count lock
cf3: 8b 45 08 mov 0x8(%ebp),%eax
cf6: 83 c0 10 add $0x10,%eax
cf9: 89 04 24 mov %eax,(%esp)
cfc: e8 97 fd ff ff call a98 <lock_acquire>
//printf(1, "acquired lock\n");
s->count = s->count - 1; //decrement resource by one
d01: 8b 45 08 mov 0x8(%ebp),%eax
d04: 8b 00 mov (%eax),%eax
d06: 8d 50 ff lea -0x1(%eax),%edx
d09: 8b 45 08 mov 0x8(%ebp),%eax
d0c: 89 10 mov %edx,(%eax)
//printf(1, "DECREMENT! COUNT IS = %d\n", s->count);
lock_release(&s->lock); //release count lock
d0e: 8b 45 08 mov 0x8(%ebp),%eax
d11: 83 c0 10 add $0x10,%eax
d14: 89 04 24 mov %eax,(%esp)
d17: e8 9b fd ff ff call ab7 <lock_release>
break;
d1c: 90 nop
add_q(&s->threads, getpid()); //add thread to sleep queueu
//printf(1, "asleep \n");
tsleep();
}
}
}
d1d: c9 leave
d1e: c3 ret
//printf(1, "DECREMENT! COUNT IS = %d\n", s->count);
lock_release(&s->lock); //release count lock
break;
}
else { //if there are no available resources
printf(1, "Waiting for semaphore\n");
d1f: c7 44 24 04 23 0e 00 movl $0xe23,0x4(%esp)
d26: 00
d27: c7 04 24 01 00 00 00 movl $0x1,(%esp)
d2e: e8 76 f9 ff ff call 6a9 <printf>
//printf(1, "%d", getpid());
add_q(&s->threads, getpid()); //add thread to sleep queueu
d33: e8 50 f8 ff ff call 588 <getpid>
d38: 8b 55 08 mov 0x8(%ebp),%edx
d3b: 83 c2 04 add $0x4,%edx
d3e: 89 44 24 04 mov %eax,0x4(%esp)
d42: 89 14 24 mov %edx,(%esp)
d45: e8 78 fe ff ff call bc2 <add_q>
//printf(1, "asleep \n");
tsleep();
d4a: e8 69 f8 ff ff call 5b8 <tsleep>
}
}
d4f: eb 99 jmp cea <sem_acquire+0x6>
00000d51 <sem_signal>:
}
void sem_signal(struct Semaphore *s) {
d51: 55 push %ebp
d52: 89 e5 mov %esp,%ebp
d54: 83 ec 18 sub $0x18,%esp
lock_acquire(&s->lock);
d57: 8b 45 08 mov 0x8(%ebp),%eax
d5a: 83 c0 10 add $0x10,%eax
d5d: 89 04 24 mov %eax,(%esp)
d60: e8 33 fd ff ff call a98 <lock_acquire>
s->count++;
d65: 8b 45 08 mov 0x8(%ebp),%eax
d68: 8b 00 mov (%eax),%eax
d6a: 8d 50 01 lea 0x1(%eax),%edx
d6d: 8b 45 08 mov 0x8(%ebp),%eax
d70: 89 10 mov %edx,(%eax)
lock_release(&s->lock);
d72: 8b 45 08 mov 0x8(%ebp),%eax
d75: 83 c0 10 add $0x10,%eax
d78: 89 04 24 mov %eax,(%esp)
d7b: e8 37 fd ff ff call ab7 <lock_release>
if (!empty_q(&s->threads)) {
d80: 8b 45 08 mov 0x8(%ebp),%eax
d83: 83 c0 04 add $0x4,%eax
d86: 89 04 24 mov %eax,(%esp)
d89: e8 94 fe ff ff call c22 <empty_q>
d8e: 85 c0 test %eax,%eax
d90: 75 16 jne da8 <sem_signal+0x57>
twakeup(pop_q(&s->threads)); //remove thread from queue and wake up
d92: 8b 45 08 mov 0x8(%ebp),%eax
d95: 83 c0 04 add $0x4,%eax
d98: 89 04 24 mov %eax,(%esp)
d9b: e8 9c fe ff ff call c3c <pop_q>
da0: 89 04 24 mov %eax,(%esp)
da3: e8 18 f8 ff ff call 5c0 <twakeup>
}
}
da8: c9 leave
da9: c3 ret
| phung001/xv6_lab2_mark | test1.asm | Assembly | mit | 64,501 |
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/06/max/MaxL.asm
// Symbol-less version of the Max.asm program.
@0
D=M
@1
D=D-M
@10
D;JGT
@1
D=M
@12
0;JMP
@0
D=M
@2
M=D
@14
0;JMP | josecu/nand2tetris | projects/06/max/MaxL.asm | Assembly | apache-2.0 | 309 |
.386
.model FLAT,STDCALL
OPTION CASEMAP:NONE
INCLUDE \masm32\INCLUDE\WINDOWS.INC
INCLUDE \masm32\INCLUDE\USER32.INC
INCLUDE \masm32\INCLUDE\KERNEL32.INC
INCLUDE \masm32\INCLUDE\COMCTL32.INC
INCLUDELIB \masm32\LIB\USER32.LIB
INCLUDELIB \masm32\LIB\KERNEL32.LIB
INCLUDELIB \masm32\LIB\COMCTL32.LIB
WinMain PROTO:dword,:dword,:dword,:dword
WINPROC PROTO:dword,:dword,:dword,:dword
CHECK PROTO
.DATA
szDlgTitle DB 'CHECK',0
CommandLine DD 0
hWnd DD 0
hInstance DD 0
hWndWdit DD 0
szEditClass DB "EDIT",0
szClassName DB "MainWndClass",0
MAXSIZE = 2000
BUF DB MAXSIZE+1 DUP(0)
EXIT DB 'QUIT',0
.CODE
START:
INVOKE GetModuleHandle,NULL
MOV hInstance,EAX
INVOKE InitCommonControls
INVOKE GetCommandLine
MOV CommandLine,EAX
INVOKE WinMain,hInstance,NULL,CommandLine,SW_SHOWDEFAULT
INVOKE ExitProcess,EAX
WinMain PROC hInst :dword,
hPrevInst :dword,
CmdLine :dword,
CmdShow :dword
local wc :WNDCLASSEX
local msg :MSG
local Wwd :dword
local Wht :dword
local Wtx :dword
local Wty :dword
local rectClient :RECT
MOV wc.cbSize,sizeof WNDCLASSEX
MOV wc.style,CS_VREDRAW or CS_HREDRAW or CS_DBLCLKS or CS_BYTEALIGNCLIENT or CS_BYTEALIGNWINDOW
MOV wc.lpfnWndProc,OFFSET WndProc
MOV wc.cbClsExtra,NULL
PUSH hInst
POP wc.hInstance
MOV wc.hbrBackground,COLOR_WINDOW+1
MOV wc.lpszMenuName,NULL
MOV wc.lpszClassName,OFFSET szClassName
MOV wc.hIcon,0
INVOKE LoadCursor,NULL,IDC_ARROW
MOV wc.hCursor,EAX
MOV wc.hIconSm,0
INVOKE RegisterClassEx, addr wc
MOV Wwd, 600
MOV Wht, 400
MOV Wtx, 10
MOV Wty, 10
INVOKE CreateWindowEx,
WS_EX_ACCEPTFILES+WS_EX_APPWINDOW,
addr szClassName,
addr szDlgTitle,
WS_OVERLAPPEDWINDOW+WS_VISIBLE,
Wtx,Wty,Wwd,Wht,
NULL,NULL,hInst,NULL
MOV hWnd,EAX
INVOKE LoadMenu,hInst,600
INVOKE SetMenu,hWnd,eax
INVOKE GetClientRect,hWnd,addr rectClient
INVOKE CreateWindowEx,
WS_EX_ACCEPTFILES or WS_EX_APPWINDOW,
addr szEditClass,
NULL,
WS_CHILD+WS_VISIBLE+WS_HSCROLL+WS_VSCROLL+ES_MULTILINE+ES_AUTOVSCROLL+ES_AUTOHSCROLL,
rectClient.left,
rectClient.top,
rectClient.right,
rectClient.bottom,
hWnd,
0,hInst,0
MOV hWndWdit,EAX
STARTLOOP:
INVOKE GetMessage,addr msg,NULL,0,0
CMP EAX,0
JE EXITLOOP
INVOKE TranslateMessage,addr msg
INVOKE DispatchMessage,addr msg
JMP STARTLOOP
EXITLOOP:
MOV EAX,msg.wParam
RET
WinMain ENDP
WndProc PROC hWin:dword,
uMsg :dword,
wParam :dword,
iParam :dword
.if uMsg == WM_COMMAND
.if wParam == 1000
INVOKE CHECK
.if EAX == 0
INVOKE PostQuitMessage,NULL
.endif
.endif
.else
INVOKE DefWindowProc,hWin,uMsg,wParam,iParam
RET
.endif
MOV EAX,0
RET
WndProc ENDP
CHECK PROC
INVOKE SendMessage,hWndWdit,WM_GETTEXT,EAX,addr BUF
MOV DI,-1
CBUF: INC DI
MOV BL,BUF[DI]
CMP BL,EXIT[DI]
JNE TEXIT
CMP EXIT[DI],0
JMP TEXIT
JMP CBUF
MOV EAX,1
RET
TEXIT: MOV EAX,0
RET
CHECK ENDP
END START | chaohu/Daily-Learning | Assembly/Homework/6-9.asm | Assembly | mit | 2,831 |
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