code stringlengths 2 1.05M | repo_name stringlengths 5 101 | path stringlengths 4 991 | language stringclasses 3 values | license stringclasses 5 values | size int64 2 1.05M |
|---|---|---|---|---|---|
class PaLdapProfile : PaConfigObject {
[string]$Name
[bool]$AdminUseOnly
[string]$Type
[string]$BaseDN
[string]$BindDN
[int]$BindTimeout
[int]$SearchTimout
[int]$RetryInterval
[bool]$RequireSSL
[bool]$VerifyServerCertificate
[array]$Servers
[string]$ConfigNode = "server-profile/ldap"
# XPath
[string] getXPath() {
$returnXPath = $this.getBaseXPath()
# Add Name
if ($this.Name) {
$returnXPath += "/entry[@name='"
$returnXPath += $this.Name
$returnXPath += "']"
}
return $returnXPath
}
# Xml
[System.Xml.Linq.XElement] getXml() {
# Document Root
$doc = [System.Xml.Linq.XDocument]::new()
# Create and add "entry" node
$entry = [System.Xml.Linq.XElement]::new("entry",$null)
return $doc.Element("entry")
}
} | brianaddicks/poweralto3 | poweralto3/src/classes/main/PaLdapProfile.ps1 | PowerShell | mit | 911 |
ag --smart-case --ignore-dir bin --ignore-dir obj $args
| yjpark/dotfiles | windows/PowerShell/aliases/a.ps1 | PowerShell | mit | 56 |
function Replace-Package {
param(
[Parameter(Mandatory = $true)]
[string]
$ToBeReplaced,
[Parameter(Mandatory = $true)]
[string]
$Replacement,
[Parameter(Mandatory = $false)]
[string]
$Version = "",
[Parameter(ValueFromPipeline = $true, ValueFromPipelineByPropertyName = $true)]
[string]
$ProjectName,
[switch]
$Force,
[switch]
$Pre
)
if (-not $ProjectName) {
$ProjectName = (get-project).ProjectName
}
Write-Host "Uninstalling" $ToBeReplaced "from" $ProjectName
Uninstall-Package -ProjectName $ProjectName -Id $ToBeReplaced -Force:$Force
Write-Host "Installing" $Replacement "to" $ProjectName
if ($Version)
{
Install-Package -ProjectName $ProjectName -Id $Replacement -Version $Version
}
else
{
Install-Package -ProjectName $ProjectName -Id $Replacement -Pre:$Pre
}
}
function Replace-Packages {
param(
[Parameter(Mandatory = $true)]
[string]
$ToBeReplaced,
[Parameter(Mandatory = $true)]
[string]
$Replacement,
[Parameter(Mandatory = $false)]
[string]
$Version = "",
[switch]
$Force,
[switch]
$Pre
)
$projects = Get-Project -All
foreach($project in $projects)
{
$packages = Get-Package -ProjectName $project.Name -pre | Where-Object {$_.Id -eq $ToBeReplaced}
foreach($package in $packages)
{
Replace-Package -ToBeReplaced $ToBeReplaced -Replacement $Replacement -Version $version -ProjectName $project.Name -Force:$Force -Pre:$Pre
}
}
}
Export-ModuleMember Replace-Package
Export-ModuleMember Replace-Packages
| ApocalypticOctopus/Replace-Package | ReplacePackage.psm1 | PowerShell | mit | 1,824 |
<#
.SYNOPSIS
The script scan Active Directory and retrieve huge data of many sources like:
-User objects
-Computer objects
-Organizational Unit
-Forest
-Access control list
-Etc.
Ability to export data to CSV and Excel format. Default save format is CSV
.NOTES
Author : Juan Garrido (http://windowstips.wordpress.com)
Twitter : @tr1ana
Company : http://www.innotecsystem.com
File Name : voyeur.ps1
#>
#---------------------------------------------------
# Search for Roles
# Perform search of common Service Principal Names
#---------------------------------------------------
Function Get-Roles([String] $Filter)
{
$FinalObject = @()
#Searcher
if ($Global:Domain)
{
$Searcher = New-Object System.DirectoryServices.DirectorySearcher($Domain,$($credential.UserName),$($credential.GetNetworkCredential().password))
$Searcher.SearchScope = "subtree"
}
elseif ($Global:DomainWPass)
{
$Searcher = New-Object System.DirectoryServices.DirectorySearcher($DomainWPass)
$Searcher.SearchRoot = "LDAP://" + $DomainWPass
}
else
{
$Searcher = New-Object System.DirectoryServices.DirectorySearcher($CurrentDomain.distinguishedname)
$Searcher.SearchRoot = "LDAP://" + $CurrentDomain.distinguishedname
}
$Searcher.PageSize = 200
if ($Filter)
{
$Searcher.SearchRoot ="LDAP://$($Filter)"
}
Foreach ($service in $Services)
{
$spn = [String]::Format($service.SPN)
$Searcher.filter = "(servicePrincipalName=$spn*/*)"
$Results = $Searcher.FindAll()
if ($Results)
{
Write-Verbose "Role Service Found....."
foreach ($r in $Results)
{
$account = $r.GetDirectoryEntry()
$record = @{}
$record.Add("Name", [String]$account.Name)
$record.Add("AccountName", [String]$account.sAMAccountName)
$record.Add("GUID", [String]$account.guid)
$record.Add("DN", [String]$account.DistinguishedName)
$record.Add("Service", [String]$service.Service)
$FinalObject +=$record
}
}
}
$AllRoles = Set-PSObject $FinalObject "Arsenal.AD.Roles"
return $AllRoles
} | liorvh/voyeur | Computers/Services.ps1 | PowerShell | mit | 2,138 |
#clean-up because I'm re-running this over and over
stop-process -Name VISIO -ea SilentlyContinue
remove-item c:\temp\testvisio5.vsdx -ea SilentlyContinue
import-module VisioBot3000 -Force
Diagram C:\temp\TestVisio5.vsdx -From C:\temp\IntegrationDiagram.vstx
# Define shapes, containers, and connectors for the diagram
Stencil Servers -From SERVER_U.vssx
Stencil Containers -From C:\temp\MyContainers.vssx
Shape WebServer -From Servers -MasterName 'Web Server'
Shape SQLServer -From Servers -masterName 'Database Server'
Container Location -From Containers -MasterName 'Location'
Connector SQL -color Red -Arrow
Set-NextShapePosition -x 3 -y 5.5
Location Datacenter {
WebServer PrimaryServer
WebServer SecondaryServer
WebServer ThirdServer
Set-RelativePositionDirection Vertical
SQLServer DBServer
}
SQL -from PrimaryServer,SecondaryServer,ThirdServer -to DBServer
Legend @{
'Information/CreatedBy/Name'='Mike Shepard - the boss!';
'Information/LastUpdateBy/Name'='Mike Shepard - the boss2!';
'Title/Title'='VisioBot3000 DSL Example';
'Title/SubTitle'='Relative positioning and legend'}
Complete-Diagram | MikeShepard/VisioBot3000 | Examples/VisioDSL5_RelativePositioning.ps1 | PowerShell | mit | 1,198 |
_rm: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "stat.h"
#include "user.h"
int
main(int argc, char *argv[])
{
0: 55 push %ebp
1: 89 e5 mov %esp,%ebp
3: 83 e4 f0 and $0xfffffff0,%esp
6: 83 ec 20 sub $0x20,%esp
int i;
if(argc < 2){
9: 83 7d 08 01 cmpl $0x1,0x8(%ebp)
d: 7f 19 jg 28 <main+0x28>
printf(2, "Usage: rm files...\n");
f: c7 44 24 04 43 08 00 movl $0x843,0x4(%esp)
16: 00
17: c7 04 24 02 00 00 00 movl $0x2,(%esp)
1e: e8 54 04 00 00 call 477 <printf>
exit();
23: e8 cf 02 00 00 call 2f7 <exit>
}
for(i = 1; i < argc; i++){
28: c7 44 24 1c 01 00 00 movl $0x1,0x1c(%esp)
2f: 00
30: eb 4f jmp 81 <main+0x81>
if(unlink(argv[i]) < 0){
32: 8b 44 24 1c mov 0x1c(%esp),%eax
36: 8d 14 85 00 00 00 00 lea 0x0(,%eax,4),%edx
3d: 8b 45 0c mov 0xc(%ebp),%eax
40: 01 d0 add %edx,%eax
42: 8b 00 mov (%eax),%eax
44: 89 04 24 mov %eax,(%esp)
47: e8 fb 02 00 00 call 347 <unlink>
4c: 85 c0 test %eax,%eax
4e: 79 2c jns 7c <main+0x7c>
printf(2, "rm: %s failed to delete\n", argv[i]);
50: 8b 44 24 1c mov 0x1c(%esp),%eax
54: 8d 14 85 00 00 00 00 lea 0x0(,%eax,4),%edx
5b: 8b 45 0c mov 0xc(%ebp),%eax
5e: 01 d0 add %edx,%eax
60: 8b 00 mov (%eax),%eax
62: 89 44 24 08 mov %eax,0x8(%esp)
66: c7 44 24 04 57 08 00 movl $0x857,0x4(%esp)
6d: 00
6e: c7 04 24 02 00 00 00 movl $0x2,(%esp)
75: e8 fd 03 00 00 call 477 <printf>
break;
7a: eb 0e jmp 8a <main+0x8a>
if(argc < 2){
printf(2, "Usage: rm files...\n");
exit();
}
for(i = 1; i < argc; i++){
7c: 83 44 24 1c 01 addl $0x1,0x1c(%esp)
81: 8b 44 24 1c mov 0x1c(%esp),%eax
85: 3b 45 08 cmp 0x8(%ebp),%eax
88: 7c a8 jl 32 <main+0x32>
printf(2, "rm: %s failed to delete\n", argv[i]);
break;
}
}
exit();
8a: e8 68 02 00 00 call 2f7 <exit>
0000008f <stosb>:
"cc");
}
static inline void
stosb(void *addr, int data, int cnt)
{
8f: 55 push %ebp
90: 89 e5 mov %esp,%ebp
92: 57 push %edi
93: 53 push %ebx
asm volatile("cld; rep stosb" :
94: 8b 4d 08 mov 0x8(%ebp),%ecx
97: 8b 55 10 mov 0x10(%ebp),%edx
9a: 8b 45 0c mov 0xc(%ebp),%eax
9d: 89 cb mov %ecx,%ebx
9f: 89 df mov %ebx,%edi
a1: 89 d1 mov %edx,%ecx
a3: fc cld
a4: f3 aa rep stos %al,%es:(%edi)
a6: 89 ca mov %ecx,%edx
a8: 89 fb mov %edi,%ebx
aa: 89 5d 08 mov %ebx,0x8(%ebp)
ad: 89 55 10 mov %edx,0x10(%ebp)
"=D" (addr), "=c" (cnt) :
"0" (addr), "1" (cnt), "a" (data) :
"memory", "cc");
}
b0: 5b pop %ebx
b1: 5f pop %edi
b2: 5d pop %ebp
b3: c3 ret
000000b4 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, char *t)
{
b4: 55 push %ebp
b5: 89 e5 mov %esp,%ebp
b7: 83 ec 10 sub $0x10,%esp
char *os;
os = s;
ba: 8b 45 08 mov 0x8(%ebp),%eax
bd: 89 45 fc mov %eax,-0x4(%ebp)
while((*s++ = *t++) != 0)
c0: 90 nop
c1: 8b 45 08 mov 0x8(%ebp),%eax
c4: 8d 50 01 lea 0x1(%eax),%edx
c7: 89 55 08 mov %edx,0x8(%ebp)
ca: 8b 55 0c mov 0xc(%ebp),%edx
cd: 8d 4a 01 lea 0x1(%edx),%ecx
d0: 89 4d 0c mov %ecx,0xc(%ebp)
d3: 0f b6 12 movzbl (%edx),%edx
d6: 88 10 mov %dl,(%eax)
d8: 0f b6 00 movzbl (%eax),%eax
db: 84 c0 test %al,%al
dd: 75 e2 jne c1 <strcpy+0xd>
;
return os;
df: 8b 45 fc mov -0x4(%ebp),%eax
}
e2: c9 leave
e3: c3 ret
000000e4 <strcmp>:
int
strcmp(const char *p, const char *q)
{
e4: 55 push %ebp
e5: 89 e5 mov %esp,%ebp
while(*p && *p == *q)
e7: eb 08 jmp f1 <strcmp+0xd>
p++, q++;
e9: 83 45 08 01 addl $0x1,0x8(%ebp)
ed: 83 45 0c 01 addl $0x1,0xc(%ebp)
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
f1: 8b 45 08 mov 0x8(%ebp),%eax
f4: 0f b6 00 movzbl (%eax),%eax
f7: 84 c0 test %al,%al
f9: 74 10 je 10b <strcmp+0x27>
fb: 8b 45 08 mov 0x8(%ebp),%eax
fe: 0f b6 10 movzbl (%eax),%edx
101: 8b 45 0c mov 0xc(%ebp),%eax
104: 0f b6 00 movzbl (%eax),%eax
107: 38 c2 cmp %al,%dl
109: 74 de je e9 <strcmp+0x5>
p++, q++;
return (uchar)*p - (uchar)*q;
10b: 8b 45 08 mov 0x8(%ebp),%eax
10e: 0f b6 00 movzbl (%eax),%eax
111: 0f b6 d0 movzbl %al,%edx
114: 8b 45 0c mov 0xc(%ebp),%eax
117: 0f b6 00 movzbl (%eax),%eax
11a: 0f b6 c0 movzbl %al,%eax
11d: 29 c2 sub %eax,%edx
11f: 89 d0 mov %edx,%eax
}
121: 5d pop %ebp
122: c3 ret
00000123 <strlen>:
uint
strlen(char *s)
{
123: 55 push %ebp
124: 89 e5 mov %esp,%ebp
126: 83 ec 10 sub $0x10,%esp
int n;
for(n = 0; s[n]; n++)
129: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
130: eb 04 jmp 136 <strlen+0x13>
132: 83 45 fc 01 addl $0x1,-0x4(%ebp)
136: 8b 55 fc mov -0x4(%ebp),%edx
139: 8b 45 08 mov 0x8(%ebp),%eax
13c: 01 d0 add %edx,%eax
13e: 0f b6 00 movzbl (%eax),%eax
141: 84 c0 test %al,%al
143: 75 ed jne 132 <strlen+0xf>
;
return n;
145: 8b 45 fc mov -0x4(%ebp),%eax
}
148: c9 leave
149: c3 ret
0000014a <memset>:
void*
memset(void *dst, int c, uint n)
{
14a: 55 push %ebp
14b: 89 e5 mov %esp,%ebp
14d: 83 ec 0c sub $0xc,%esp
stosb(dst, c, n);
150: 8b 45 10 mov 0x10(%ebp),%eax
153: 89 44 24 08 mov %eax,0x8(%esp)
157: 8b 45 0c mov 0xc(%ebp),%eax
15a: 89 44 24 04 mov %eax,0x4(%esp)
15e: 8b 45 08 mov 0x8(%ebp),%eax
161: 89 04 24 mov %eax,(%esp)
164: e8 26 ff ff ff call 8f <stosb>
return dst;
169: 8b 45 08 mov 0x8(%ebp),%eax
}
16c: c9 leave
16d: c3 ret
0000016e <strchr>:
char*
strchr(const char *s, char c)
{
16e: 55 push %ebp
16f: 89 e5 mov %esp,%ebp
171: 83 ec 04 sub $0x4,%esp
174: 8b 45 0c mov 0xc(%ebp),%eax
177: 88 45 fc mov %al,-0x4(%ebp)
for(; *s; s++)
17a: eb 14 jmp 190 <strchr+0x22>
if(*s == c)
17c: 8b 45 08 mov 0x8(%ebp),%eax
17f: 0f b6 00 movzbl (%eax),%eax
182: 3a 45 fc cmp -0x4(%ebp),%al
185: 75 05 jne 18c <strchr+0x1e>
return (char*)s;
187: 8b 45 08 mov 0x8(%ebp),%eax
18a: eb 13 jmp 19f <strchr+0x31>
}
char*
strchr(const char *s, char c)
{
for(; *s; s++)
18c: 83 45 08 01 addl $0x1,0x8(%ebp)
190: 8b 45 08 mov 0x8(%ebp),%eax
193: 0f b6 00 movzbl (%eax),%eax
196: 84 c0 test %al,%al
198: 75 e2 jne 17c <strchr+0xe>
if(*s == c)
return (char*)s;
return 0;
19a: b8 00 00 00 00 mov $0x0,%eax
}
19f: c9 leave
1a0: c3 ret
000001a1 <gets>:
char*
gets(char *buf, int max)
{
1a1: 55 push %ebp
1a2: 89 e5 mov %esp,%ebp
1a4: 83 ec 28 sub $0x28,%esp
int i, cc;
char c;
for(i=0; i+1 < max; ){
1a7: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1ae: eb 4c jmp 1fc <gets+0x5b>
cc = read(0, &c, 1);
1b0: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
1b7: 00
1b8: 8d 45 ef lea -0x11(%ebp),%eax
1bb: 89 44 24 04 mov %eax,0x4(%esp)
1bf: c7 04 24 00 00 00 00 movl $0x0,(%esp)
1c6: e8 44 01 00 00 call 30f <read>
1cb: 89 45 f0 mov %eax,-0x10(%ebp)
if(cc < 1)
1ce: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
1d2: 7f 02 jg 1d6 <gets+0x35>
break;
1d4: eb 31 jmp 207 <gets+0x66>
buf[i++] = c;
1d6: 8b 45 f4 mov -0xc(%ebp),%eax
1d9: 8d 50 01 lea 0x1(%eax),%edx
1dc: 89 55 f4 mov %edx,-0xc(%ebp)
1df: 89 c2 mov %eax,%edx
1e1: 8b 45 08 mov 0x8(%ebp),%eax
1e4: 01 c2 add %eax,%edx
1e6: 0f b6 45 ef movzbl -0x11(%ebp),%eax
1ea: 88 02 mov %al,(%edx)
if(c == '\n' || c == '\r')
1ec: 0f b6 45 ef movzbl -0x11(%ebp),%eax
1f0: 3c 0a cmp $0xa,%al
1f2: 74 13 je 207 <gets+0x66>
1f4: 0f b6 45 ef movzbl -0x11(%ebp),%eax
1f8: 3c 0d cmp $0xd,%al
1fa: 74 0b je 207 <gets+0x66>
gets(char *buf, int max)
{
int i, cc;
char c;
for(i=0; i+1 < max; ){
1fc: 8b 45 f4 mov -0xc(%ebp),%eax
1ff: 83 c0 01 add $0x1,%eax
202: 3b 45 0c cmp 0xc(%ebp),%eax
205: 7c a9 jl 1b0 <gets+0xf>
break;
buf[i++] = c;
if(c == '\n' || c == '\r')
break;
}
buf[i] = '\0';
207: 8b 55 f4 mov -0xc(%ebp),%edx
20a: 8b 45 08 mov 0x8(%ebp),%eax
20d: 01 d0 add %edx,%eax
20f: c6 00 00 movb $0x0,(%eax)
return buf;
212: 8b 45 08 mov 0x8(%ebp),%eax
}
215: c9 leave
216: c3 ret
00000217 <stat>:
int
stat(char *n, struct stat *st)
{
217: 55 push %ebp
218: 89 e5 mov %esp,%ebp
21a: 83 ec 28 sub $0x28,%esp
int fd;
int r;
fd = open(n, O_RDONLY);
21d: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
224: 00
225: 8b 45 08 mov 0x8(%ebp),%eax
228: 89 04 24 mov %eax,(%esp)
22b: e8 07 01 00 00 call 337 <open>
230: 89 45 f4 mov %eax,-0xc(%ebp)
if(fd < 0)
233: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
237: 79 07 jns 240 <stat+0x29>
return -1;
239: b8 ff ff ff ff mov $0xffffffff,%eax
23e: eb 23 jmp 263 <stat+0x4c>
r = fstat(fd, st);
240: 8b 45 0c mov 0xc(%ebp),%eax
243: 89 44 24 04 mov %eax,0x4(%esp)
247: 8b 45 f4 mov -0xc(%ebp),%eax
24a: 89 04 24 mov %eax,(%esp)
24d: e8 fd 00 00 00 call 34f <fstat>
252: 89 45 f0 mov %eax,-0x10(%ebp)
close(fd);
255: 8b 45 f4 mov -0xc(%ebp),%eax
258: 89 04 24 mov %eax,(%esp)
25b: e8 bf 00 00 00 call 31f <close>
return r;
260: 8b 45 f0 mov -0x10(%ebp),%eax
}
263: c9 leave
264: c3 ret
00000265 <atoi>:
int
atoi(const char *s)
{
265: 55 push %ebp
266: 89 e5 mov %esp,%ebp
268: 83 ec 10 sub $0x10,%esp
int n;
n = 0;
26b: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
while('0' <= *s && *s <= '9')
272: eb 25 jmp 299 <atoi+0x34>
n = n*10 + *s++ - '0';
274: 8b 55 fc mov -0x4(%ebp),%edx
277: 89 d0 mov %edx,%eax
279: c1 e0 02 shl $0x2,%eax
27c: 01 d0 add %edx,%eax
27e: 01 c0 add %eax,%eax
280: 89 c1 mov %eax,%ecx
282: 8b 45 08 mov 0x8(%ebp),%eax
285: 8d 50 01 lea 0x1(%eax),%edx
288: 89 55 08 mov %edx,0x8(%ebp)
28b: 0f b6 00 movzbl (%eax),%eax
28e: 0f be c0 movsbl %al,%eax
291: 01 c8 add %ecx,%eax
293: 83 e8 30 sub $0x30,%eax
296: 89 45 fc mov %eax,-0x4(%ebp)
atoi(const char *s)
{
int n;
n = 0;
while('0' <= *s && *s <= '9')
299: 8b 45 08 mov 0x8(%ebp),%eax
29c: 0f b6 00 movzbl (%eax),%eax
29f: 3c 2f cmp $0x2f,%al
2a1: 7e 0a jle 2ad <atoi+0x48>
2a3: 8b 45 08 mov 0x8(%ebp),%eax
2a6: 0f b6 00 movzbl (%eax),%eax
2a9: 3c 39 cmp $0x39,%al
2ab: 7e c7 jle 274 <atoi+0xf>
n = n*10 + *s++ - '0';
return n;
2ad: 8b 45 fc mov -0x4(%ebp),%eax
}
2b0: c9 leave
2b1: c3 ret
000002b2 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
2b2: 55 push %ebp
2b3: 89 e5 mov %esp,%ebp
2b5: 83 ec 10 sub $0x10,%esp
char *dst, *src;
dst = vdst;
2b8: 8b 45 08 mov 0x8(%ebp),%eax
2bb: 89 45 fc mov %eax,-0x4(%ebp)
src = vsrc;
2be: 8b 45 0c mov 0xc(%ebp),%eax
2c1: 89 45 f8 mov %eax,-0x8(%ebp)
while(n-- > 0)
2c4: eb 17 jmp 2dd <memmove+0x2b>
*dst++ = *src++;
2c6: 8b 45 fc mov -0x4(%ebp),%eax
2c9: 8d 50 01 lea 0x1(%eax),%edx
2cc: 89 55 fc mov %edx,-0x4(%ebp)
2cf: 8b 55 f8 mov -0x8(%ebp),%edx
2d2: 8d 4a 01 lea 0x1(%edx),%ecx
2d5: 89 4d f8 mov %ecx,-0x8(%ebp)
2d8: 0f b6 12 movzbl (%edx),%edx
2db: 88 10 mov %dl,(%eax)
{
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
2dd: 8b 45 10 mov 0x10(%ebp),%eax
2e0: 8d 50 ff lea -0x1(%eax),%edx
2e3: 89 55 10 mov %edx,0x10(%ebp)
2e6: 85 c0 test %eax,%eax
2e8: 7f dc jg 2c6 <memmove+0x14>
*dst++ = *src++;
return vdst;
2ea: 8b 45 08 mov 0x8(%ebp),%eax
}
2ed: c9 leave
2ee: c3 ret
000002ef <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
2ef: b8 01 00 00 00 mov $0x1,%eax
2f4: cd 40 int $0x40
2f6: c3 ret
000002f7 <exit>:
SYSCALL(exit)
2f7: b8 02 00 00 00 mov $0x2,%eax
2fc: cd 40 int $0x40
2fe: c3 ret
000002ff <wait>:
SYSCALL(wait)
2ff: b8 03 00 00 00 mov $0x3,%eax
304: cd 40 int $0x40
306: c3 ret
00000307 <pipe>:
SYSCALL(pipe)
307: b8 04 00 00 00 mov $0x4,%eax
30c: cd 40 int $0x40
30e: c3 ret
0000030f <read>:
SYSCALL(read)
30f: b8 05 00 00 00 mov $0x5,%eax
314: cd 40 int $0x40
316: c3 ret
00000317 <write>:
SYSCALL(write)
317: b8 10 00 00 00 mov $0x10,%eax
31c: cd 40 int $0x40
31e: c3 ret
0000031f <close>:
SYSCALL(close)
31f: b8 15 00 00 00 mov $0x15,%eax
324: cd 40 int $0x40
326: c3 ret
00000327 <kill>:
SYSCALL(kill)
327: b8 06 00 00 00 mov $0x6,%eax
32c: cd 40 int $0x40
32e: c3 ret
0000032f <exec>:
SYSCALL(exec)
32f: b8 07 00 00 00 mov $0x7,%eax
334: cd 40 int $0x40
336: c3 ret
00000337 <open>:
SYSCALL(open)
337: b8 0f 00 00 00 mov $0xf,%eax
33c: cd 40 int $0x40
33e: c3 ret
0000033f <mknod>:
SYSCALL(mknod)
33f: b8 11 00 00 00 mov $0x11,%eax
344: cd 40 int $0x40
346: c3 ret
00000347 <unlink>:
SYSCALL(unlink)
347: b8 12 00 00 00 mov $0x12,%eax
34c: cd 40 int $0x40
34e: c3 ret
0000034f <fstat>:
SYSCALL(fstat)
34f: b8 08 00 00 00 mov $0x8,%eax
354: cd 40 int $0x40
356: c3 ret
00000357 <link>:
SYSCALL(link)
357: b8 13 00 00 00 mov $0x13,%eax
35c: cd 40 int $0x40
35e: c3 ret
0000035f <mkdir>:
SYSCALL(mkdir)
35f: b8 14 00 00 00 mov $0x14,%eax
364: cd 40 int $0x40
366: c3 ret
00000367 <chdir>:
SYSCALL(chdir)
367: b8 09 00 00 00 mov $0x9,%eax
36c: cd 40 int $0x40
36e: c3 ret
0000036f <dup>:
SYSCALL(dup)
36f: b8 0a 00 00 00 mov $0xa,%eax
374: cd 40 int $0x40
376: c3 ret
00000377 <getpid>:
SYSCALL(getpid)
377: b8 0b 00 00 00 mov $0xb,%eax
37c: cd 40 int $0x40
37e: c3 ret
0000037f <sbrk>:
SYSCALL(sbrk)
37f: b8 0c 00 00 00 mov $0xc,%eax
384: cd 40 int $0x40
386: c3 ret
00000387 <sleep>:
SYSCALL(sleep)
387: b8 0d 00 00 00 mov $0xd,%eax
38c: cd 40 int $0x40
38e: c3 ret
0000038f <uptime>:
SYSCALL(uptime)
38f: b8 0e 00 00 00 mov $0xe,%eax
394: cd 40 int $0x40
396: c3 ret
00000397 <putc>:
#include "stat.h"
#include "user.h"
static void
putc(int fd, char c)
{
397: 55 push %ebp
398: 89 e5 mov %esp,%ebp
39a: 83 ec 18 sub $0x18,%esp
39d: 8b 45 0c mov 0xc(%ebp),%eax
3a0: 88 45 f4 mov %al,-0xc(%ebp)
write(fd, &c, 1);
3a3: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
3aa: 00
3ab: 8d 45 f4 lea -0xc(%ebp),%eax
3ae: 89 44 24 04 mov %eax,0x4(%esp)
3b2: 8b 45 08 mov 0x8(%ebp),%eax
3b5: 89 04 24 mov %eax,(%esp)
3b8: e8 5a ff ff ff call 317 <write>
}
3bd: c9 leave
3be: c3 ret
000003bf <printint>:
static void
printint(int fd, int xx, int base, int sgn)
{
3bf: 55 push %ebp
3c0: 89 e5 mov %esp,%ebp
3c2: 56 push %esi
3c3: 53 push %ebx
3c4: 83 ec 30 sub $0x30,%esp
static char digits[] = "0123456789ABCDEF";
char buf[16];
int i, neg;
uint x;
neg = 0;
3c7: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
if(sgn && xx < 0){
3ce: 83 7d 14 00 cmpl $0x0,0x14(%ebp)
3d2: 74 17 je 3eb <printint+0x2c>
3d4: 83 7d 0c 00 cmpl $0x0,0xc(%ebp)
3d8: 79 11 jns 3eb <printint+0x2c>
neg = 1;
3da: c7 45 f0 01 00 00 00 movl $0x1,-0x10(%ebp)
x = -xx;
3e1: 8b 45 0c mov 0xc(%ebp),%eax
3e4: f7 d8 neg %eax
3e6: 89 45 ec mov %eax,-0x14(%ebp)
3e9: eb 06 jmp 3f1 <printint+0x32>
} else {
x = xx;
3eb: 8b 45 0c mov 0xc(%ebp),%eax
3ee: 89 45 ec mov %eax,-0x14(%ebp)
}
i = 0;
3f1: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
do{
buf[i++] = digits[x % base];
3f8: 8b 4d f4 mov -0xc(%ebp),%ecx
3fb: 8d 41 01 lea 0x1(%ecx),%eax
3fe: 89 45 f4 mov %eax,-0xc(%ebp)
401: 8b 5d 10 mov 0x10(%ebp),%ebx
404: 8b 45 ec mov -0x14(%ebp),%eax
407: ba 00 00 00 00 mov $0x0,%edx
40c: f7 f3 div %ebx
40e: 89 d0 mov %edx,%eax
410: 0f b6 80 bc 0a 00 00 movzbl 0xabc(%eax),%eax
417: 88 44 0d dc mov %al,-0x24(%ebp,%ecx,1)
}while((x /= base) != 0);
41b: 8b 75 10 mov 0x10(%ebp),%esi
41e: 8b 45 ec mov -0x14(%ebp),%eax
421: ba 00 00 00 00 mov $0x0,%edx
426: f7 f6 div %esi
428: 89 45 ec mov %eax,-0x14(%ebp)
42b: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
42f: 75 c7 jne 3f8 <printint+0x39>
if(neg)
431: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
435: 74 10 je 447 <printint+0x88>
buf[i++] = '-';
437: 8b 45 f4 mov -0xc(%ebp),%eax
43a: 8d 50 01 lea 0x1(%eax),%edx
43d: 89 55 f4 mov %edx,-0xc(%ebp)
440: c6 44 05 dc 2d movb $0x2d,-0x24(%ebp,%eax,1)
while(--i >= 0)
445: eb 1f jmp 466 <printint+0xa7>
447: eb 1d jmp 466 <printint+0xa7>
putc(fd, buf[i]);
449: 8d 55 dc lea -0x24(%ebp),%edx
44c: 8b 45 f4 mov -0xc(%ebp),%eax
44f: 01 d0 add %edx,%eax
451: 0f b6 00 movzbl (%eax),%eax
454: 0f be c0 movsbl %al,%eax
457: 89 44 24 04 mov %eax,0x4(%esp)
45b: 8b 45 08 mov 0x8(%ebp),%eax
45e: 89 04 24 mov %eax,(%esp)
461: e8 31 ff ff ff call 397 <putc>
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
466: 83 6d f4 01 subl $0x1,-0xc(%ebp)
46a: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
46e: 79 d9 jns 449 <printint+0x8a>
putc(fd, buf[i]);
}
470: 83 c4 30 add $0x30,%esp
473: 5b pop %ebx
474: 5e pop %esi
475: 5d pop %ebp
476: c3 ret
00000477 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
477: 55 push %ebp
478: 89 e5 mov %esp,%ebp
47a: 83 ec 38 sub $0x38,%esp
char *s;
int c, i, state;
uint *ap;
state = 0;
47d: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
ap = (uint*)(void*)&fmt + 1;
484: 8d 45 0c lea 0xc(%ebp),%eax
487: 83 c0 04 add $0x4,%eax
48a: 89 45 e8 mov %eax,-0x18(%ebp)
for(i = 0; fmt[i]; i++){
48d: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
494: e9 7c 01 00 00 jmp 615 <printf+0x19e>
c = fmt[i] & 0xff;
499: 8b 55 0c mov 0xc(%ebp),%edx
49c: 8b 45 f0 mov -0x10(%ebp),%eax
49f: 01 d0 add %edx,%eax
4a1: 0f b6 00 movzbl (%eax),%eax
4a4: 0f be c0 movsbl %al,%eax
4a7: 25 ff 00 00 00 and $0xff,%eax
4ac: 89 45 e4 mov %eax,-0x1c(%ebp)
if(state == 0){
4af: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
4b3: 75 2c jne 4e1 <printf+0x6a>
if(c == '%'){
4b5: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
4b9: 75 0c jne 4c7 <printf+0x50>
state = '%';
4bb: c7 45 ec 25 00 00 00 movl $0x25,-0x14(%ebp)
4c2: e9 4a 01 00 00 jmp 611 <printf+0x19a>
} else {
putc(fd, c);
4c7: 8b 45 e4 mov -0x1c(%ebp),%eax
4ca: 0f be c0 movsbl %al,%eax
4cd: 89 44 24 04 mov %eax,0x4(%esp)
4d1: 8b 45 08 mov 0x8(%ebp),%eax
4d4: 89 04 24 mov %eax,(%esp)
4d7: e8 bb fe ff ff call 397 <putc>
4dc: e9 30 01 00 00 jmp 611 <printf+0x19a>
}
} else if(state == '%'){
4e1: 83 7d ec 25 cmpl $0x25,-0x14(%ebp)
4e5: 0f 85 26 01 00 00 jne 611 <printf+0x19a>
if(c == 'd'){
4eb: 83 7d e4 64 cmpl $0x64,-0x1c(%ebp)
4ef: 75 2d jne 51e <printf+0xa7>
printint(fd, *ap, 10, 1);
4f1: 8b 45 e8 mov -0x18(%ebp),%eax
4f4: 8b 00 mov (%eax),%eax
4f6: c7 44 24 0c 01 00 00 movl $0x1,0xc(%esp)
4fd: 00
4fe: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
505: 00
506: 89 44 24 04 mov %eax,0x4(%esp)
50a: 8b 45 08 mov 0x8(%ebp),%eax
50d: 89 04 24 mov %eax,(%esp)
510: e8 aa fe ff ff call 3bf <printint>
ap++;
515: 83 45 e8 04 addl $0x4,-0x18(%ebp)
519: e9 ec 00 00 00 jmp 60a <printf+0x193>
} else if(c == 'x' || c == 'p'){
51e: 83 7d e4 78 cmpl $0x78,-0x1c(%ebp)
522: 74 06 je 52a <printf+0xb3>
524: 83 7d e4 70 cmpl $0x70,-0x1c(%ebp)
528: 75 2d jne 557 <printf+0xe0>
printint(fd, *ap, 16, 0);
52a: 8b 45 e8 mov -0x18(%ebp),%eax
52d: 8b 00 mov (%eax),%eax
52f: c7 44 24 0c 00 00 00 movl $0x0,0xc(%esp)
536: 00
537: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
53e: 00
53f: 89 44 24 04 mov %eax,0x4(%esp)
543: 8b 45 08 mov 0x8(%ebp),%eax
546: 89 04 24 mov %eax,(%esp)
549: e8 71 fe ff ff call 3bf <printint>
ap++;
54e: 83 45 e8 04 addl $0x4,-0x18(%ebp)
552: e9 b3 00 00 00 jmp 60a <printf+0x193>
} else if(c == 's'){
557: 83 7d e4 73 cmpl $0x73,-0x1c(%ebp)
55b: 75 45 jne 5a2 <printf+0x12b>
s = (char*)*ap;
55d: 8b 45 e8 mov -0x18(%ebp),%eax
560: 8b 00 mov (%eax),%eax
562: 89 45 f4 mov %eax,-0xc(%ebp)
ap++;
565: 83 45 e8 04 addl $0x4,-0x18(%ebp)
if(s == 0)
569: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
56d: 75 09 jne 578 <printf+0x101>
s = "(null)";
56f: c7 45 f4 70 08 00 00 movl $0x870,-0xc(%ebp)
while(*s != 0){
576: eb 1e jmp 596 <printf+0x11f>
578: eb 1c jmp 596 <printf+0x11f>
putc(fd, *s);
57a: 8b 45 f4 mov -0xc(%ebp),%eax
57d: 0f b6 00 movzbl (%eax),%eax
580: 0f be c0 movsbl %al,%eax
583: 89 44 24 04 mov %eax,0x4(%esp)
587: 8b 45 08 mov 0x8(%ebp),%eax
58a: 89 04 24 mov %eax,(%esp)
58d: e8 05 fe ff ff call 397 <putc>
s++;
592: 83 45 f4 01 addl $0x1,-0xc(%ebp)
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
596: 8b 45 f4 mov -0xc(%ebp),%eax
599: 0f b6 00 movzbl (%eax),%eax
59c: 84 c0 test %al,%al
59e: 75 da jne 57a <printf+0x103>
5a0: eb 68 jmp 60a <printf+0x193>
putc(fd, *s);
s++;
}
} else if(c == 'c'){
5a2: 83 7d e4 63 cmpl $0x63,-0x1c(%ebp)
5a6: 75 1d jne 5c5 <printf+0x14e>
putc(fd, *ap);
5a8: 8b 45 e8 mov -0x18(%ebp),%eax
5ab: 8b 00 mov (%eax),%eax
5ad: 0f be c0 movsbl %al,%eax
5b0: 89 44 24 04 mov %eax,0x4(%esp)
5b4: 8b 45 08 mov 0x8(%ebp),%eax
5b7: 89 04 24 mov %eax,(%esp)
5ba: e8 d8 fd ff ff call 397 <putc>
ap++;
5bf: 83 45 e8 04 addl $0x4,-0x18(%ebp)
5c3: eb 45 jmp 60a <printf+0x193>
} else if(c == '%'){
5c5: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
5c9: 75 17 jne 5e2 <printf+0x16b>
putc(fd, c);
5cb: 8b 45 e4 mov -0x1c(%ebp),%eax
5ce: 0f be c0 movsbl %al,%eax
5d1: 89 44 24 04 mov %eax,0x4(%esp)
5d5: 8b 45 08 mov 0x8(%ebp),%eax
5d8: 89 04 24 mov %eax,(%esp)
5db: e8 b7 fd ff ff call 397 <putc>
5e0: eb 28 jmp 60a <printf+0x193>
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
5e2: c7 44 24 04 25 00 00 movl $0x25,0x4(%esp)
5e9: 00
5ea: 8b 45 08 mov 0x8(%ebp),%eax
5ed: 89 04 24 mov %eax,(%esp)
5f0: e8 a2 fd ff ff call 397 <putc>
putc(fd, c);
5f5: 8b 45 e4 mov -0x1c(%ebp),%eax
5f8: 0f be c0 movsbl %al,%eax
5fb: 89 44 24 04 mov %eax,0x4(%esp)
5ff: 8b 45 08 mov 0x8(%ebp),%eax
602: 89 04 24 mov %eax,(%esp)
605: e8 8d fd ff ff call 397 <putc>
}
state = 0;
60a: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
611: 83 45 f0 01 addl $0x1,-0x10(%ebp)
615: 8b 55 0c mov 0xc(%ebp),%edx
618: 8b 45 f0 mov -0x10(%ebp),%eax
61b: 01 d0 add %edx,%eax
61d: 0f b6 00 movzbl (%eax),%eax
620: 84 c0 test %al,%al
622: 0f 85 71 fe ff ff jne 499 <printf+0x22>
putc(fd, c);
}
state = 0;
}
}
}
628: c9 leave
629: c3 ret
0000062a <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
62a: 55 push %ebp
62b: 89 e5 mov %esp,%ebp
62d: 83 ec 10 sub $0x10,%esp
Header *bp, *p;
bp = (Header*)ap - 1;
630: 8b 45 08 mov 0x8(%ebp),%eax
633: 83 e8 08 sub $0x8,%eax
636: 89 45 f8 mov %eax,-0x8(%ebp)
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
639: a1 d8 0a 00 00 mov 0xad8,%eax
63e: 89 45 fc mov %eax,-0x4(%ebp)
641: eb 24 jmp 667 <free+0x3d>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
643: 8b 45 fc mov -0x4(%ebp),%eax
646: 8b 00 mov (%eax),%eax
648: 3b 45 fc cmp -0x4(%ebp),%eax
64b: 77 12 ja 65f <free+0x35>
64d: 8b 45 f8 mov -0x8(%ebp),%eax
650: 3b 45 fc cmp -0x4(%ebp),%eax
653: 77 24 ja 679 <free+0x4f>
655: 8b 45 fc mov -0x4(%ebp),%eax
658: 8b 00 mov (%eax),%eax
65a: 3b 45 f8 cmp -0x8(%ebp),%eax
65d: 77 1a ja 679 <free+0x4f>
free(void *ap)
{
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
65f: 8b 45 fc mov -0x4(%ebp),%eax
662: 8b 00 mov (%eax),%eax
664: 89 45 fc mov %eax,-0x4(%ebp)
667: 8b 45 f8 mov -0x8(%ebp),%eax
66a: 3b 45 fc cmp -0x4(%ebp),%eax
66d: 76 d4 jbe 643 <free+0x19>
66f: 8b 45 fc mov -0x4(%ebp),%eax
672: 8b 00 mov (%eax),%eax
674: 3b 45 f8 cmp -0x8(%ebp),%eax
677: 76 ca jbe 643 <free+0x19>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
679: 8b 45 f8 mov -0x8(%ebp),%eax
67c: 8b 40 04 mov 0x4(%eax),%eax
67f: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
686: 8b 45 f8 mov -0x8(%ebp),%eax
689: 01 c2 add %eax,%edx
68b: 8b 45 fc mov -0x4(%ebp),%eax
68e: 8b 00 mov (%eax),%eax
690: 39 c2 cmp %eax,%edx
692: 75 24 jne 6b8 <free+0x8e>
bp->s.size += p->s.ptr->s.size;
694: 8b 45 f8 mov -0x8(%ebp),%eax
697: 8b 50 04 mov 0x4(%eax),%edx
69a: 8b 45 fc mov -0x4(%ebp),%eax
69d: 8b 00 mov (%eax),%eax
69f: 8b 40 04 mov 0x4(%eax),%eax
6a2: 01 c2 add %eax,%edx
6a4: 8b 45 f8 mov -0x8(%ebp),%eax
6a7: 89 50 04 mov %edx,0x4(%eax)
bp->s.ptr = p->s.ptr->s.ptr;
6aa: 8b 45 fc mov -0x4(%ebp),%eax
6ad: 8b 00 mov (%eax),%eax
6af: 8b 10 mov (%eax),%edx
6b1: 8b 45 f8 mov -0x8(%ebp),%eax
6b4: 89 10 mov %edx,(%eax)
6b6: eb 0a jmp 6c2 <free+0x98>
} else
bp->s.ptr = p->s.ptr;
6b8: 8b 45 fc mov -0x4(%ebp),%eax
6bb: 8b 10 mov (%eax),%edx
6bd: 8b 45 f8 mov -0x8(%ebp),%eax
6c0: 89 10 mov %edx,(%eax)
if(p + p->s.size == bp){
6c2: 8b 45 fc mov -0x4(%ebp),%eax
6c5: 8b 40 04 mov 0x4(%eax),%eax
6c8: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
6cf: 8b 45 fc mov -0x4(%ebp),%eax
6d2: 01 d0 add %edx,%eax
6d4: 3b 45 f8 cmp -0x8(%ebp),%eax
6d7: 75 20 jne 6f9 <free+0xcf>
p->s.size += bp->s.size;
6d9: 8b 45 fc mov -0x4(%ebp),%eax
6dc: 8b 50 04 mov 0x4(%eax),%edx
6df: 8b 45 f8 mov -0x8(%ebp),%eax
6e2: 8b 40 04 mov 0x4(%eax),%eax
6e5: 01 c2 add %eax,%edx
6e7: 8b 45 fc mov -0x4(%ebp),%eax
6ea: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
6ed: 8b 45 f8 mov -0x8(%ebp),%eax
6f0: 8b 10 mov (%eax),%edx
6f2: 8b 45 fc mov -0x4(%ebp),%eax
6f5: 89 10 mov %edx,(%eax)
6f7: eb 08 jmp 701 <free+0xd7>
} else
p->s.ptr = bp;
6f9: 8b 45 fc mov -0x4(%ebp),%eax
6fc: 8b 55 f8 mov -0x8(%ebp),%edx
6ff: 89 10 mov %edx,(%eax)
freep = p;
701: 8b 45 fc mov -0x4(%ebp),%eax
704: a3 d8 0a 00 00 mov %eax,0xad8
}
709: c9 leave
70a: c3 ret
0000070b <morecore>:
static Header*
morecore(uint nu)
{
70b: 55 push %ebp
70c: 89 e5 mov %esp,%ebp
70e: 83 ec 28 sub $0x28,%esp
char *p;
Header *hp;
if(nu < 4096)
711: 81 7d 08 ff 0f 00 00 cmpl $0xfff,0x8(%ebp)
718: 77 07 ja 721 <morecore+0x16>
nu = 4096;
71a: c7 45 08 00 10 00 00 movl $0x1000,0x8(%ebp)
p = sbrk(nu * sizeof(Header));
721: 8b 45 08 mov 0x8(%ebp),%eax
724: c1 e0 03 shl $0x3,%eax
727: 89 04 24 mov %eax,(%esp)
72a: e8 50 fc ff ff call 37f <sbrk>
72f: 89 45 f4 mov %eax,-0xc(%ebp)
if(p == (char*)-1)
732: 83 7d f4 ff cmpl $0xffffffff,-0xc(%ebp)
736: 75 07 jne 73f <morecore+0x34>
return 0;
738: b8 00 00 00 00 mov $0x0,%eax
73d: eb 22 jmp 761 <morecore+0x56>
hp = (Header*)p;
73f: 8b 45 f4 mov -0xc(%ebp),%eax
742: 89 45 f0 mov %eax,-0x10(%ebp)
hp->s.size = nu;
745: 8b 45 f0 mov -0x10(%ebp),%eax
748: 8b 55 08 mov 0x8(%ebp),%edx
74b: 89 50 04 mov %edx,0x4(%eax)
free((void*)(hp + 1));
74e: 8b 45 f0 mov -0x10(%ebp),%eax
751: 83 c0 08 add $0x8,%eax
754: 89 04 24 mov %eax,(%esp)
757: e8 ce fe ff ff call 62a <free>
return freep;
75c: a1 d8 0a 00 00 mov 0xad8,%eax
}
761: c9 leave
762: c3 ret
00000763 <malloc>:
void*
malloc(uint nbytes)
{
763: 55 push %ebp
764: 89 e5 mov %esp,%ebp
766: 83 ec 28 sub $0x28,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
769: 8b 45 08 mov 0x8(%ebp),%eax
76c: 83 c0 07 add $0x7,%eax
76f: c1 e8 03 shr $0x3,%eax
772: 83 c0 01 add $0x1,%eax
775: 89 45 ec mov %eax,-0x14(%ebp)
if((prevp = freep) == 0){
778: a1 d8 0a 00 00 mov 0xad8,%eax
77d: 89 45 f0 mov %eax,-0x10(%ebp)
780: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
784: 75 23 jne 7a9 <malloc+0x46>
base.s.ptr = freep = prevp = &base;
786: c7 45 f0 d0 0a 00 00 movl $0xad0,-0x10(%ebp)
78d: 8b 45 f0 mov -0x10(%ebp),%eax
790: a3 d8 0a 00 00 mov %eax,0xad8
795: a1 d8 0a 00 00 mov 0xad8,%eax
79a: a3 d0 0a 00 00 mov %eax,0xad0
base.s.size = 0;
79f: c7 05 d4 0a 00 00 00 movl $0x0,0xad4
7a6: 00 00 00
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
7a9: 8b 45 f0 mov -0x10(%ebp),%eax
7ac: 8b 00 mov (%eax),%eax
7ae: 89 45 f4 mov %eax,-0xc(%ebp)
if(p->s.size >= nunits){
7b1: 8b 45 f4 mov -0xc(%ebp),%eax
7b4: 8b 40 04 mov 0x4(%eax),%eax
7b7: 3b 45 ec cmp -0x14(%ebp),%eax
7ba: 72 4d jb 809 <malloc+0xa6>
if(p->s.size == nunits)
7bc: 8b 45 f4 mov -0xc(%ebp),%eax
7bf: 8b 40 04 mov 0x4(%eax),%eax
7c2: 3b 45 ec cmp -0x14(%ebp),%eax
7c5: 75 0c jne 7d3 <malloc+0x70>
prevp->s.ptr = p->s.ptr;
7c7: 8b 45 f4 mov -0xc(%ebp),%eax
7ca: 8b 10 mov (%eax),%edx
7cc: 8b 45 f0 mov -0x10(%ebp),%eax
7cf: 89 10 mov %edx,(%eax)
7d1: eb 26 jmp 7f9 <malloc+0x96>
else {
p->s.size -= nunits;
7d3: 8b 45 f4 mov -0xc(%ebp),%eax
7d6: 8b 40 04 mov 0x4(%eax),%eax
7d9: 2b 45 ec sub -0x14(%ebp),%eax
7dc: 89 c2 mov %eax,%edx
7de: 8b 45 f4 mov -0xc(%ebp),%eax
7e1: 89 50 04 mov %edx,0x4(%eax)
p += p->s.size;
7e4: 8b 45 f4 mov -0xc(%ebp),%eax
7e7: 8b 40 04 mov 0x4(%eax),%eax
7ea: c1 e0 03 shl $0x3,%eax
7ed: 01 45 f4 add %eax,-0xc(%ebp)
p->s.size = nunits;
7f0: 8b 45 f4 mov -0xc(%ebp),%eax
7f3: 8b 55 ec mov -0x14(%ebp),%edx
7f6: 89 50 04 mov %edx,0x4(%eax)
}
freep = prevp;
7f9: 8b 45 f0 mov -0x10(%ebp),%eax
7fc: a3 d8 0a 00 00 mov %eax,0xad8
return (void*)(p + 1);
801: 8b 45 f4 mov -0xc(%ebp),%eax
804: 83 c0 08 add $0x8,%eax
807: eb 38 jmp 841 <malloc+0xde>
}
if(p == freep)
809: a1 d8 0a 00 00 mov 0xad8,%eax
80e: 39 45 f4 cmp %eax,-0xc(%ebp)
811: 75 1b jne 82e <malloc+0xcb>
if((p = morecore(nunits)) == 0)
813: 8b 45 ec mov -0x14(%ebp),%eax
816: 89 04 24 mov %eax,(%esp)
819: e8 ed fe ff ff call 70b <morecore>
81e: 89 45 f4 mov %eax,-0xc(%ebp)
821: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
825: 75 07 jne 82e <malloc+0xcb>
return 0;
827: b8 00 00 00 00 mov $0x0,%eax
82c: eb 13 jmp 841 <malloc+0xde>
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
82e: 8b 45 f4 mov -0xc(%ebp),%eax
831: 89 45 f0 mov %eax,-0x10(%ebp)
834: 8b 45 f4 mov -0xc(%ebp),%eax
837: 8b 00 mov (%eax),%eax
839: 89 45 f4 mov %eax,-0xc(%ebp)
return (void*)(p + 1);
}
if(p == freep)
if((p = morecore(nunits)) == 0)
return 0;
}
83c: e9 70 ff ff ff jmp 7b1 <malloc+0x4e>
}
841: c9 leave
842: c3 ret
| tzulang/xv6_4 | rm.asm | Assembly | mit | 40,983 |
;idta.asm sets up all the intterupt entry points
extern default_handler
extern idt_ftoi
;error interrupt entry point, we need to only push the error code details to stack
%macro error_interrupt 1
global interrupt_handler_%1
interrupt_handler_%1:
push dword %1
jmp common_handler
%endmacro
;regular interrupt entry point, need to push interrupt number and other data
%macro regular_interrupt 1
global interrupt_handler_%1
interrupt_handler_%1:
push dword 0
push dword %1
jmp common_handler
%endmacro
;common handler for all interrupts, saves all necessary stack data and calls our c intterupt handler
common_handler:
push dword ds
push dword es
push dword fs
push dword gs
pusha
call default_handler
popa
pop dword gs
pop dword fs
pop dword es
pop dword ds
add esp, 8
iret
regular_interrupt 0
regular_interrupt 1
regular_interrupt 2
regular_interrupt 3
regular_interrupt 4
regular_interrupt 5
regular_interrupt 6
regular_interrupt 7
error_interrupt 8
regular_interrupt 9
error_interrupt 10
error_interrupt 11
error_interrupt 12
error_interrupt 13
error_interrupt 14
regular_interrupt 15
regular_interrupt 16
error_interrupt 17
%assign i 18
%rep 12
regular_interrupt i
%assign i i+1
%endrep
error_interrupt 30
%assign i 31
%rep 225
regular_interrupt i
%assign i i+1
%endrep
;interrupt setup, adds all of out interrupt handlers to the idt
global idtsetup
idtsetup:
%assign i 0
%rep 256
push interrupt_handler_%[i]
push i
call idt_ftoi
add esp, 8
%assign i i+1
%endrep
ret
| MalcolmLorber/kernel | src/idta.asm | Assembly | mit | 1,579 |
;;; keydown-counter.asm -- Count keydown form P3.2 and outputs in P1 using LED
;; Author: Zeno Zeng <zenoofzeng@gmail.com>
;; Time-stamp: <2014-12-25 21:56:36 Zeno Zeng>
;;; Commentary:
;; Count keydown from P3.2 then ouputs using 8bit P1 (in LED)
;;; Code:
ORG 0000H
AJMP INIT
ORG 0003H
AJMP ONKEYDOWN
INIT:
CLR A
MOV TCON, #01H ; 设置触发方式为脉冲，下降沿有效（IT0 = 1）
MOV IE, #81H ; 中断总允许，允许 EX0（P3.2 引入） 外中断 （EA = 1, EX0 = 1）
LISTENING:
SJMP LISTENING
ONKEYDOWN:
INC A
MOV P1, A
RETI
EXIT:
END
| zenozeng/ASM-80C51 | keydown-counter.asm | Assembly | mit | 670 |
INCLUDE "hardware.inc"
INCLUDE "header.inc"
SECTION "Main",HOME
;--------------------------------------------------------------------------
;- Main() -
;--------------------------------------------------------------------------
Main:
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$87
ld [rNR14],a
;--------------------------------
ld a,LCDCF_ON
ld [rLCDC],a
REPT 100
ld b,140
call wait_ly
ld b,139
call wait_ly
ENDR
;--------------------------------
ld a,0
ld [rIF],a
ld a,IEF_HILO
ld [rIE],a
;--------------------------------
ei
.end:
ld b,1
call wait_ly
ld b,0
call wait_ly
ld a,$00
ld [rP1],a
ld a,$30
ld [rP1],a
inc a
inc a
inc a
inc a
inc a
jr .end
| AntonioND/gbc-hw-tests | interrupts/joy_interrupt_manual_delay/main.asm | Assembly | mit | 877 |
Map_347E30: dc.w Frame_347E4A-Map_347E30
dc.w Frame_347E4C-Map_347E30
dc.w Frame_347E66-Map_347E30
dc.w Frame_347E80-Map_347E30
dc.w Frame_347E9A-Map_347E30
dc.w Frame_347EB4-Map_347E30
dc.w Frame_347ECE-Map_347E30
dc.w Frame_347EE2-Map_347E30
dc.w Frame_347EFC-Map_347E30
dc.w Frame_347F16-Map_347E30
dc.w Frame_347F30-Map_347E30
dc.w Frame_347F4A-Map_347E30
dc.w Frame_347F6A-Map_347E30
Frame_347E4A: dc.w 0
Frame_347E4C: dc.w 4
dc.b $FC, $F, 0, 0,$FF,$FA
dc.b $EC, 7, 0,$10,$FF,$EA
dc.b $EC, 9, 0,$18,$FF,$FA
dc.b $DC, 9, 0,$1E,$FF,$F2
Frame_347E66: dc.w 4
dc.b $EE, 8, 0, 0,$FF,$F0
dc.b $F6, $D, 0, 3,$FF,$F0
dc.b 6, 8, 0, $B,$FF,$F8
dc.b $E, 6, 0, $E,$FF,$F8
Frame_347E80: dc.w 4
dc.b $E9, $A, 0, 0,$FF,$F1
dc.b $F9, 4, 0, 9, 0, 9
dc.b 1, $D, 0, $B,$FF,$F1
dc.b $11, 9, 0,$13,$FF,$E9
Frame_347E9A: dc.w 4
dc.b $EA, $F, 0, 0,$FF,$F3
dc.b $A, 8, 0,$10,$FF,$F3
dc.b $12, $C, 0,$13,$FF,$EB
dc.b $1A, 8, 0,$17,$FF,$EB
Frame_347EB4: dc.w 4
dc.b $EA, 8, 0, 0,$FF,$F5
dc.b $F2, $E, 0, 3,$FF,$ED
dc.b $A, 8, 0, $F,$FF,$F5
dc.b $12, $D, 0,$12,$FF,$F5
Frame_347ECE: dc.w 3
dc.b $EF, $F, 0, 0,$FF,$EC
dc.b $F, $C, 0,$10,$FF,$E4
dc.b $F, 8, 0,$14, 0, 4
Frame_347EE2: dc.w 4
dc.b $EF, $F, 0, 0,$FF,$EC
dc.b $F, $C, 0,$10,$FF,$E4
dc.b $F, 8, 0,$14, 0, 4
dc.b 7, 0, 0,$17, 0,$14
Frame_347EFC: dc.w 4
dc.b $EF, $F, 0, 0,$FF,$EC
dc.b 7, 4, 0,$10, 0, $C
dc.b $F, $C, 0,$12,$FF,$E4
dc.b $F, 0, 0,$16, 0, 4
Frame_347F16: dc.w 4
dc.b $F1, $E, 0, 0,$FF,$E5
dc.b $F1, 6, 0, $C, 0, 5
dc.b 9, $C, 0,$12,$FF,$ED
dc.b $11, $A, 0,$16,$FF,$ED
Frame_347F30: dc.w 4
dc.b $EB, $F, 0, 0,$FF,$F6
dc.b $F3, $A, 0,$10,$FF,$DE
dc.b $B, $C, 0,$19,$FF,$EE
dc.b $13, 9, 0,$1D,$FF,$F6
Frame_347F4A: dc.w 5
dc.b $EE, $F, 0, 0,$FF,$EC
dc.b $FE, 0, 0,$10, 0, $C
dc.b $E, $C, 0,$11,$FF,$E4
dc.b $E, 0, 0,$15, 0, 4
dc.b $16, $C, 0,$16,$FF,$FC
Frame_347F6A: dc.w 5
dc.b $EA, 8, 0, 0,$FF,$EE
dc.b $F2, $E, 0, 3,$FF,$EE
dc.b $A, $C, 0, $F,$FF,$E6
dc.b $12, $C, 0,$13,$FF,$EE
dc.b $1A, $C, 0,$17,$FF,$FE
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/General/Sprites/Sonic/Map - Sonic Snowboarding.asm | Assembly | apache-2.0 | 2,205 |
data segment
x dw 0FFFFh
s db "00000",0Dh,0Ah,"$"
data ends
code segment
assume cs:code, ds:data
main:
mov ax, data
mov ds, ax
mov bx, 4; 下标
mov ax, [x]
next:
mov dx, 0; 保证被除数的高16位为0
mov cx, 10
div cx; (DX:AX)/CX=AX..DX
add dl, '0'
mov s[bx], dl
cmp ax, 0
je done
dec bx
jmp next
done:
mov ah, 9
mov dx, offset s
int 21h
mov ah, 4Ch
int 21h
code ends
end main
| Tao-J/hw | asm80386/16int2dec1.asm | Assembly | apache-2.0 | 437 |
global _check_for_key
_check_for_key:
push bp
mov bp, sp
mov ax, word [bp+4]
call os_check_for_key
pop bp
ret
| I8087/mlib | src/check_for_key.asm | Assembly | bsd-2-clause | 138 |
# Copyright 2020 The Cobalt Authors. All Rights Reserved.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# NOTE:
# libdav1d's build process will generate this file and populate it with defines
# that configure the project appropriately and set compilation flags. These
# flags are migrated into Cobalt's gyp and ninja build process which makes this
# file superfluous. However, we keep |config.asm| since the file is referenced
# in the includes for several source files and to keep the overall code changes
# low for ease of rebasing upstream changes from libdav1d.
| youtube/cobalt | third_party/libdav1d/include/config.asm | Assembly | bsd-3-clause | 1,067 |
default rel
%define XMMWORD
%define YMMWORD
%define ZMMWORD
section .text code align=64
EXTERN OPENSSL_ia32cap_P
global sha1_block_data_order
ALIGN 16
sha1_block_data_order:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha1_block_data_order:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
lea r10,[OPENSSL_ia32cap_P]
mov r9d,DWORD[r10]
mov r8d,DWORD[4+r10]
mov r10d,DWORD[8+r10]
test r8d,512
jz NEAR $L$ialu
and r8d,268435456
and r9d,1073741824
or r8d,r9d
cmp r8d,1342177280
je NEAR _avx_shortcut
jmp NEAR _ssse3_shortcut
ALIGN 16
$L$ialu:
mov rax,rsp
push rbx
push rbp
push r12
push r13
push r14
mov r8,rdi
sub rsp,72
mov r9,rsi
and rsp,-64
mov r10,rdx
mov QWORD[64+rsp],rax
$L$prologue:
mov esi,DWORD[r8]
mov edi,DWORD[4+r8]
mov r11d,DWORD[8+r8]
mov r12d,DWORD[12+r8]
mov r13d,DWORD[16+r8]
jmp NEAR $L$loop
ALIGN 16
$L$loop:
mov edx,DWORD[r9]
bswap edx
mov ebp,DWORD[4+r9]
mov eax,r12d
mov DWORD[rsp],edx
mov ecx,esi
bswap ebp
xor eax,r11d
rol ecx,5
and eax,edi
lea r13d,[1518500249+r13*1+rdx]
add r13d,ecx
xor eax,r12d
rol edi,30
add r13d,eax
mov r14d,DWORD[8+r9]
mov eax,r11d
mov DWORD[4+rsp],ebp
mov ecx,r13d
bswap r14d
xor eax,edi
rol ecx,5
and eax,esi
lea r12d,[1518500249+r12*1+rbp]
add r12d,ecx
xor eax,r11d
rol esi,30
add r12d,eax
mov edx,DWORD[12+r9]
mov eax,edi
mov DWORD[8+rsp],r14d
mov ecx,r12d
bswap edx
xor eax,esi
rol ecx,5
and eax,r13d
lea r11d,[1518500249+r11*1+r14]
add r11d,ecx
xor eax,edi
rol r13d,30
add r11d,eax
mov ebp,DWORD[16+r9]
mov eax,esi
mov DWORD[12+rsp],edx
mov ecx,r11d
bswap ebp
xor eax,r13d
rol ecx,5
and eax,r12d
lea edi,[1518500249+rdi*1+rdx]
add edi,ecx
xor eax,esi
rol r12d,30
add edi,eax
mov r14d,DWORD[20+r9]
mov eax,r13d
mov DWORD[16+rsp],ebp
mov ecx,edi
bswap r14d
xor eax,r12d
rol ecx,5
and eax,r11d
lea esi,[1518500249+rsi*1+rbp]
add esi,ecx
xor eax,r13d
rol r11d,30
add esi,eax
mov edx,DWORD[24+r9]
mov eax,r12d
mov DWORD[20+rsp],r14d
mov ecx,esi
bswap edx
xor eax,r11d
rol ecx,5
and eax,edi
lea r13d,[1518500249+r13*1+r14]
add r13d,ecx
xor eax,r12d
rol edi,30
add r13d,eax
mov ebp,DWORD[28+r9]
mov eax,r11d
mov DWORD[24+rsp],edx
mov ecx,r13d
bswap ebp
xor eax,edi
rol ecx,5
and eax,esi
lea r12d,[1518500249+r12*1+rdx]
add r12d,ecx
xor eax,r11d
rol esi,30
add r12d,eax
mov r14d,DWORD[32+r9]
mov eax,edi
mov DWORD[28+rsp],ebp
mov ecx,r12d
bswap r14d
xor eax,esi
rol ecx,5
and eax,r13d
lea r11d,[1518500249+r11*1+rbp]
add r11d,ecx
xor eax,edi
rol r13d,30
add r11d,eax
mov edx,DWORD[36+r9]
mov eax,esi
mov DWORD[32+rsp],r14d
mov ecx,r11d
bswap edx
xor eax,r13d
rol ecx,5
and eax,r12d
lea edi,[1518500249+rdi*1+r14]
add edi,ecx
xor eax,esi
rol r12d,30
add edi,eax
mov ebp,DWORD[40+r9]
mov eax,r13d
mov DWORD[36+rsp],edx
mov ecx,edi
bswap ebp
xor eax,r12d
rol ecx,5
and eax,r11d
lea esi,[1518500249+rsi*1+rdx]
add esi,ecx
xor eax,r13d
rol r11d,30
add esi,eax
mov r14d,DWORD[44+r9]
mov eax,r12d
mov DWORD[40+rsp],ebp
mov ecx,esi
bswap r14d
xor eax,r11d
rol ecx,5
and eax,edi
lea r13d,[1518500249+r13*1+rbp]
add r13d,ecx
xor eax,r12d
rol edi,30
add r13d,eax
mov edx,DWORD[48+r9]
mov eax,r11d
mov DWORD[44+rsp],r14d
mov ecx,r13d
bswap edx
xor eax,edi
rol ecx,5
and eax,esi
lea r12d,[1518500249+r12*1+r14]
add r12d,ecx
xor eax,r11d
rol esi,30
add r12d,eax
mov ebp,DWORD[52+r9]
mov eax,edi
mov DWORD[48+rsp],edx
mov ecx,r12d
bswap ebp
xor eax,esi
rol ecx,5
and eax,r13d
lea r11d,[1518500249+r11*1+rdx]
add r11d,ecx
xor eax,edi
rol r13d,30
add r11d,eax
mov r14d,DWORD[56+r9]
mov eax,esi
mov DWORD[52+rsp],ebp
mov ecx,r11d
bswap r14d
xor eax,r13d
rol ecx,5
and eax,r12d
lea edi,[1518500249+rdi*1+rbp]
add edi,ecx
xor eax,esi
rol r12d,30
add edi,eax
mov edx,DWORD[60+r9]
mov eax,r13d
mov DWORD[56+rsp],r14d
mov ecx,edi
bswap edx
xor eax,r12d
rol ecx,5
and eax,r11d
lea esi,[1518500249+rsi*1+r14]
add esi,ecx
xor eax,r13d
rol r11d,30
add esi,eax
xor ebp,DWORD[rsp]
mov eax,r12d
mov DWORD[60+rsp],edx
mov ecx,esi
xor ebp,DWORD[8+rsp]
xor eax,r11d
rol ecx,5
xor ebp,DWORD[32+rsp]
and eax,edi
lea r13d,[1518500249+r13*1+rdx]
rol edi,30
xor eax,r12d
add r13d,ecx
rol ebp,1
add r13d,eax
xor r14d,DWORD[4+rsp]
mov eax,r11d
mov DWORD[rsp],ebp
mov ecx,r13d
xor r14d,DWORD[12+rsp]
xor eax,edi
rol ecx,5
xor r14d,DWORD[36+rsp]
and eax,esi
lea r12d,[1518500249+r12*1+rbp]
rol esi,30
xor eax,r11d
add r12d,ecx
rol r14d,1
add r12d,eax
xor edx,DWORD[8+rsp]
mov eax,edi
mov DWORD[4+rsp],r14d
mov ecx,r12d
xor edx,DWORD[16+rsp]
xor eax,esi
rol ecx,5
xor edx,DWORD[40+rsp]
and eax,r13d
lea r11d,[1518500249+r11*1+r14]
rol r13d,30
xor eax,edi
add r11d,ecx
rol edx,1
add r11d,eax
xor ebp,DWORD[12+rsp]
mov eax,esi
mov DWORD[8+rsp],edx
mov ecx,r11d
xor ebp,DWORD[20+rsp]
xor eax,r13d
rol ecx,5
xor ebp,DWORD[44+rsp]
and eax,r12d
lea edi,[1518500249+rdi*1+rdx]
rol r12d,30
xor eax,esi
add edi,ecx
rol ebp,1
add edi,eax
xor r14d,DWORD[16+rsp]
mov eax,r13d
mov DWORD[12+rsp],ebp
mov ecx,edi
xor r14d,DWORD[24+rsp]
xor eax,r12d
rol ecx,5
xor r14d,DWORD[48+rsp]
and eax,r11d
lea esi,[1518500249+rsi*1+rbp]
rol r11d,30
xor eax,r13d
add esi,ecx
rol r14d,1
add esi,eax
xor edx,DWORD[20+rsp]
mov eax,edi
mov DWORD[16+rsp],r14d
mov ecx,esi
xor edx,DWORD[28+rsp]
xor eax,r12d
rol ecx,5
xor edx,DWORD[52+rsp]
lea r13d,[1859775393+r13*1+r14]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol edx,1
xor ebp,DWORD[24+rsp]
mov eax,esi
mov DWORD[20+rsp],edx
mov ecx,r13d
xor ebp,DWORD[32+rsp]
xor eax,r11d
rol ecx,5
xor ebp,DWORD[56+rsp]
lea r12d,[1859775393+r12*1+rdx]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol ebp,1
xor r14d,DWORD[28+rsp]
mov eax,r13d
mov DWORD[24+rsp],ebp
mov ecx,r12d
xor r14d,DWORD[36+rsp]
xor eax,edi
rol ecx,5
xor r14d,DWORD[60+rsp]
lea r11d,[1859775393+r11*1+rbp]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol r14d,1
xor edx,DWORD[32+rsp]
mov eax,r12d
mov DWORD[28+rsp],r14d
mov ecx,r11d
xor edx,DWORD[40+rsp]
xor eax,esi
rol ecx,5
xor edx,DWORD[rsp]
lea edi,[1859775393+rdi*1+r14]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol edx,1
xor ebp,DWORD[36+rsp]
mov eax,r11d
mov DWORD[32+rsp],edx
mov ecx,edi
xor ebp,DWORD[44+rsp]
xor eax,r13d
rol ecx,5
xor ebp,DWORD[4+rsp]
lea esi,[1859775393+rsi*1+rdx]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol ebp,1
xor r14d,DWORD[40+rsp]
mov eax,edi
mov DWORD[36+rsp],ebp
mov ecx,esi
xor r14d,DWORD[48+rsp]
xor eax,r12d
rol ecx,5
xor r14d,DWORD[8+rsp]
lea r13d,[1859775393+r13*1+rbp]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol r14d,1
xor edx,DWORD[44+rsp]
mov eax,esi
mov DWORD[40+rsp],r14d
mov ecx,r13d
xor edx,DWORD[52+rsp]
xor eax,r11d
rol ecx,5
xor edx,DWORD[12+rsp]
lea r12d,[1859775393+r12*1+r14]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol edx,1
xor ebp,DWORD[48+rsp]
mov eax,r13d
mov DWORD[44+rsp],edx
mov ecx,r12d
xor ebp,DWORD[56+rsp]
xor eax,edi
rol ecx,5
xor ebp,DWORD[16+rsp]
lea r11d,[1859775393+r11*1+rdx]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol ebp,1
xor r14d,DWORD[52+rsp]
mov eax,r12d
mov DWORD[48+rsp],ebp
mov ecx,r11d
xor r14d,DWORD[60+rsp]
xor eax,esi
rol ecx,5
xor r14d,DWORD[20+rsp]
lea edi,[1859775393+rdi*1+rbp]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol r14d,1
xor edx,DWORD[56+rsp]
mov eax,r11d
mov DWORD[52+rsp],r14d
mov ecx,edi
xor edx,DWORD[rsp]
xor eax,r13d
rol ecx,5
xor edx,DWORD[24+rsp]
lea esi,[1859775393+rsi*1+r14]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol edx,1
xor ebp,DWORD[60+rsp]
mov eax,edi
mov DWORD[56+rsp],edx
mov ecx,esi
xor ebp,DWORD[4+rsp]
xor eax,r12d
rol ecx,5
xor ebp,DWORD[28+rsp]
lea r13d,[1859775393+r13*1+rdx]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol ebp,1
xor r14d,DWORD[rsp]
mov eax,esi
mov DWORD[60+rsp],ebp
mov ecx,r13d
xor r14d,DWORD[8+rsp]
xor eax,r11d
rol ecx,5
xor r14d,DWORD[32+rsp]
lea r12d,[1859775393+r12*1+rbp]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol r14d,1
xor edx,DWORD[4+rsp]
mov eax,r13d
mov DWORD[rsp],r14d
mov ecx,r12d
xor edx,DWORD[12+rsp]
xor eax,edi
rol ecx,5
xor edx,DWORD[36+rsp]
lea r11d,[1859775393+r11*1+r14]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol edx,1
xor ebp,DWORD[8+rsp]
mov eax,r12d
mov DWORD[4+rsp],edx
mov ecx,r11d
xor ebp,DWORD[16+rsp]
xor eax,esi
rol ecx,5
xor ebp,DWORD[40+rsp]
lea edi,[1859775393+rdi*1+rdx]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol ebp,1
xor r14d,DWORD[12+rsp]
mov eax,r11d
mov DWORD[8+rsp],ebp
mov ecx,edi
xor r14d,DWORD[20+rsp]
xor eax,r13d
rol ecx,5
xor r14d,DWORD[44+rsp]
lea esi,[1859775393+rsi*1+rbp]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol r14d,1
xor edx,DWORD[16+rsp]
mov eax,edi
mov DWORD[12+rsp],r14d
mov ecx,esi
xor edx,DWORD[24+rsp]
xor eax,r12d
rol ecx,5
xor edx,DWORD[48+rsp]
lea r13d,[1859775393+r13*1+r14]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol edx,1
xor ebp,DWORD[20+rsp]
mov eax,esi
mov DWORD[16+rsp],edx
mov ecx,r13d
xor ebp,DWORD[28+rsp]
xor eax,r11d
rol ecx,5
xor ebp,DWORD[52+rsp]
lea r12d,[1859775393+r12*1+rdx]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol ebp,1
xor r14d,DWORD[24+rsp]
mov eax,r13d
mov DWORD[20+rsp],ebp
mov ecx,r12d
xor r14d,DWORD[32+rsp]
xor eax,edi
rol ecx,5
xor r14d,DWORD[56+rsp]
lea r11d,[1859775393+r11*1+rbp]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol r14d,1
xor edx,DWORD[28+rsp]
mov eax,r12d
mov DWORD[24+rsp],r14d
mov ecx,r11d
xor edx,DWORD[36+rsp]
xor eax,esi
rol ecx,5
xor edx,DWORD[60+rsp]
lea edi,[1859775393+rdi*1+r14]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol edx,1
xor ebp,DWORD[32+rsp]
mov eax,r11d
mov DWORD[28+rsp],edx
mov ecx,edi
xor ebp,DWORD[40+rsp]
xor eax,r13d
rol ecx,5
xor ebp,DWORD[rsp]
lea esi,[1859775393+rsi*1+rdx]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol ebp,1
xor r14d,DWORD[36+rsp]
mov eax,r12d
mov DWORD[32+rsp],ebp
mov ebx,r12d
xor r14d,DWORD[44+rsp]
and eax,r11d
mov ecx,esi
xor r14d,DWORD[4+rsp]
lea r13d,[((-1894007588))+r13*1+rbp]
xor ebx,r11d
rol ecx,5
add r13d,eax
rol r14d,1
and ebx,edi
add r13d,ecx
rol edi,30
add r13d,ebx
xor edx,DWORD[40+rsp]
mov eax,r11d
mov DWORD[36+rsp],r14d
mov ebx,r11d
xor edx,DWORD[48+rsp]
and eax,edi
mov ecx,r13d
xor edx,DWORD[8+rsp]
lea r12d,[((-1894007588))+r12*1+r14]
xor ebx,edi
rol ecx,5
add r12d,eax
rol edx,1
and ebx,esi
add r12d,ecx
rol esi,30
add r12d,ebx
xor ebp,DWORD[44+rsp]
mov eax,edi
mov DWORD[40+rsp],edx
mov ebx,edi
xor ebp,DWORD[52+rsp]
and eax,esi
mov ecx,r12d
xor ebp,DWORD[12+rsp]
lea r11d,[((-1894007588))+r11*1+rdx]
xor ebx,esi
rol ecx,5
add r11d,eax
rol ebp,1
and ebx,r13d
add r11d,ecx
rol r13d,30
add r11d,ebx
xor r14d,DWORD[48+rsp]
mov eax,esi
mov DWORD[44+rsp],ebp
mov ebx,esi
xor r14d,DWORD[56+rsp]
and eax,r13d
mov ecx,r11d
xor r14d,DWORD[16+rsp]
lea edi,[((-1894007588))+rdi*1+rbp]
xor ebx,r13d
rol ecx,5
add edi,eax
rol r14d,1
and ebx,r12d
add edi,ecx
rol r12d,30
add edi,ebx
xor edx,DWORD[52+rsp]
mov eax,r13d
mov DWORD[48+rsp],r14d
mov ebx,r13d
xor edx,DWORD[60+rsp]
and eax,r12d
mov ecx,edi
xor edx,DWORD[20+rsp]
lea esi,[((-1894007588))+rsi*1+r14]
xor ebx,r12d
rol ecx,5
add esi,eax
rol edx,1
and ebx,r11d
add esi,ecx
rol r11d,30
add esi,ebx
xor ebp,DWORD[56+rsp]
mov eax,r12d
mov DWORD[52+rsp],edx
mov ebx,r12d
xor ebp,DWORD[rsp]
and eax,r11d
mov ecx,esi
xor ebp,DWORD[24+rsp]
lea r13d,[((-1894007588))+r13*1+rdx]
xor ebx,r11d
rol ecx,5
add r13d,eax
rol ebp,1
and ebx,edi
add r13d,ecx
rol edi,30
add r13d,ebx
xor r14d,DWORD[60+rsp]
mov eax,r11d
mov DWORD[56+rsp],ebp
mov ebx,r11d
xor r14d,DWORD[4+rsp]
and eax,edi
mov ecx,r13d
xor r14d,DWORD[28+rsp]
lea r12d,[((-1894007588))+r12*1+rbp]
xor ebx,edi
rol ecx,5
add r12d,eax
rol r14d,1
and ebx,esi
add r12d,ecx
rol esi,30
add r12d,ebx
xor edx,DWORD[rsp]
mov eax,edi
mov DWORD[60+rsp],r14d
mov ebx,edi
xor edx,DWORD[8+rsp]
and eax,esi
mov ecx,r12d
xor edx,DWORD[32+rsp]
lea r11d,[((-1894007588))+r11*1+r14]
xor ebx,esi
rol ecx,5
add r11d,eax
rol edx,1
and ebx,r13d
add r11d,ecx
rol r13d,30
add r11d,ebx
xor ebp,DWORD[4+rsp]
mov eax,esi
mov DWORD[rsp],edx
mov ebx,esi
xor ebp,DWORD[12+rsp]
and eax,r13d
mov ecx,r11d
xor ebp,DWORD[36+rsp]
lea edi,[((-1894007588))+rdi*1+rdx]
xor ebx,r13d
rol ecx,5
add edi,eax
rol ebp,1
and ebx,r12d
add edi,ecx
rol r12d,30
add edi,ebx
xor r14d,DWORD[8+rsp]
mov eax,r13d
mov DWORD[4+rsp],ebp
mov ebx,r13d
xor r14d,DWORD[16+rsp]
and eax,r12d
mov ecx,edi
xor r14d,DWORD[40+rsp]
lea esi,[((-1894007588))+rsi*1+rbp]
xor ebx,r12d
rol ecx,5
add esi,eax
rol r14d,1
and ebx,r11d
add esi,ecx
rol r11d,30
add esi,ebx
xor edx,DWORD[12+rsp]
mov eax,r12d
mov DWORD[8+rsp],r14d
mov ebx,r12d
xor edx,DWORD[20+rsp]
and eax,r11d
mov ecx,esi
xor edx,DWORD[44+rsp]
lea r13d,[((-1894007588))+r13*1+r14]
xor ebx,r11d
rol ecx,5
add r13d,eax
rol edx,1
and ebx,edi
add r13d,ecx
rol edi,30
add r13d,ebx
xor ebp,DWORD[16+rsp]
mov eax,r11d
mov DWORD[12+rsp],edx
mov ebx,r11d
xor ebp,DWORD[24+rsp]
and eax,edi
mov ecx,r13d
xor ebp,DWORD[48+rsp]
lea r12d,[((-1894007588))+r12*1+rdx]
xor ebx,edi
rol ecx,5
add r12d,eax
rol ebp,1
and ebx,esi
add r12d,ecx
rol esi,30
add r12d,ebx
xor r14d,DWORD[20+rsp]
mov eax,edi
mov DWORD[16+rsp],ebp
mov ebx,edi
xor r14d,DWORD[28+rsp]
and eax,esi
mov ecx,r12d
xor r14d,DWORD[52+rsp]
lea r11d,[((-1894007588))+r11*1+rbp]
xor ebx,esi
rol ecx,5
add r11d,eax
rol r14d,1
and ebx,r13d
add r11d,ecx
rol r13d,30
add r11d,ebx
xor edx,DWORD[24+rsp]
mov eax,esi
mov DWORD[20+rsp],r14d
mov ebx,esi
xor edx,DWORD[32+rsp]
and eax,r13d
mov ecx,r11d
xor edx,DWORD[56+rsp]
lea edi,[((-1894007588))+rdi*1+r14]
xor ebx,r13d
rol ecx,5
add edi,eax
rol edx,1
and ebx,r12d
add edi,ecx
rol r12d,30
add edi,ebx
xor ebp,DWORD[28+rsp]
mov eax,r13d
mov DWORD[24+rsp],edx
mov ebx,r13d
xor ebp,DWORD[36+rsp]
and eax,r12d
mov ecx,edi
xor ebp,DWORD[60+rsp]
lea esi,[((-1894007588))+rsi*1+rdx]
xor ebx,r12d
rol ecx,5
add esi,eax
rol ebp,1
and ebx,r11d
add esi,ecx
rol r11d,30
add esi,ebx
xor r14d,DWORD[32+rsp]
mov eax,r12d
mov DWORD[28+rsp],ebp
mov ebx,r12d
xor r14d,DWORD[40+rsp]
and eax,r11d
mov ecx,esi
xor r14d,DWORD[rsp]
lea r13d,[((-1894007588))+r13*1+rbp]
xor ebx,r11d
rol ecx,5
add r13d,eax
rol r14d,1
and ebx,edi
add r13d,ecx
rol edi,30
add r13d,ebx
xor edx,DWORD[36+rsp]
mov eax,r11d
mov DWORD[32+rsp],r14d
mov ebx,r11d
xor edx,DWORD[44+rsp]
and eax,edi
mov ecx,r13d
xor edx,DWORD[4+rsp]
lea r12d,[((-1894007588))+r12*1+r14]
xor ebx,edi
rol ecx,5
add r12d,eax
rol edx,1
and ebx,esi
add r12d,ecx
rol esi,30
add r12d,ebx
xor ebp,DWORD[40+rsp]
mov eax,edi
mov DWORD[36+rsp],edx
mov ebx,edi
xor ebp,DWORD[48+rsp]
and eax,esi
mov ecx,r12d
xor ebp,DWORD[8+rsp]
lea r11d,[((-1894007588))+r11*1+rdx]
xor ebx,esi
rol ecx,5
add r11d,eax
rol ebp,1
and ebx,r13d
add r11d,ecx
rol r13d,30
add r11d,ebx
xor r14d,DWORD[44+rsp]
mov eax,esi
mov DWORD[40+rsp],ebp
mov ebx,esi
xor r14d,DWORD[52+rsp]
and eax,r13d
mov ecx,r11d
xor r14d,DWORD[12+rsp]
lea edi,[((-1894007588))+rdi*1+rbp]
xor ebx,r13d
rol ecx,5
add edi,eax
rol r14d,1
and ebx,r12d
add edi,ecx
rol r12d,30
add edi,ebx
xor edx,DWORD[48+rsp]
mov eax,r13d
mov DWORD[44+rsp],r14d
mov ebx,r13d
xor edx,DWORD[56+rsp]
and eax,r12d
mov ecx,edi
xor edx,DWORD[16+rsp]
lea esi,[((-1894007588))+rsi*1+r14]
xor ebx,r12d
rol ecx,5
add esi,eax
rol edx,1
and ebx,r11d
add esi,ecx
rol r11d,30
add esi,ebx
xor ebp,DWORD[52+rsp]
mov eax,edi
mov DWORD[48+rsp],edx
mov ecx,esi
xor ebp,DWORD[60+rsp]
xor eax,r12d
rol ecx,5
xor ebp,DWORD[20+rsp]
lea r13d,[((-899497514))+r13*1+rdx]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol ebp,1
xor r14d,DWORD[56+rsp]
mov eax,esi
mov DWORD[52+rsp],ebp
mov ecx,r13d
xor r14d,DWORD[rsp]
xor eax,r11d
rol ecx,5
xor r14d,DWORD[24+rsp]
lea r12d,[((-899497514))+r12*1+rbp]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol r14d,1
xor edx,DWORD[60+rsp]
mov eax,r13d
mov DWORD[56+rsp],r14d
mov ecx,r12d
xor edx,DWORD[4+rsp]
xor eax,edi
rol ecx,5
xor edx,DWORD[28+rsp]
lea r11d,[((-899497514))+r11*1+r14]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol edx,1
xor ebp,DWORD[rsp]
mov eax,r12d
mov DWORD[60+rsp],edx
mov ecx,r11d
xor ebp,DWORD[8+rsp]
xor eax,esi
rol ecx,5
xor ebp,DWORD[32+rsp]
lea edi,[((-899497514))+rdi*1+rdx]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol ebp,1
xor r14d,DWORD[4+rsp]
mov eax,r11d
mov DWORD[rsp],ebp
mov ecx,edi
xor r14d,DWORD[12+rsp]
xor eax,r13d
rol ecx,5
xor r14d,DWORD[36+rsp]
lea esi,[((-899497514))+rsi*1+rbp]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol r14d,1
xor edx,DWORD[8+rsp]
mov eax,edi
mov DWORD[4+rsp],r14d
mov ecx,esi
xor edx,DWORD[16+rsp]
xor eax,r12d
rol ecx,5
xor edx,DWORD[40+rsp]
lea r13d,[((-899497514))+r13*1+r14]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol edx,1
xor ebp,DWORD[12+rsp]
mov eax,esi
mov DWORD[8+rsp],edx
mov ecx,r13d
xor ebp,DWORD[20+rsp]
xor eax,r11d
rol ecx,5
xor ebp,DWORD[44+rsp]
lea r12d,[((-899497514))+r12*1+rdx]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol ebp,1
xor r14d,DWORD[16+rsp]
mov eax,r13d
mov DWORD[12+rsp],ebp
mov ecx,r12d
xor r14d,DWORD[24+rsp]
xor eax,edi
rol ecx,5
xor r14d,DWORD[48+rsp]
lea r11d,[((-899497514))+r11*1+rbp]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol r14d,1
xor edx,DWORD[20+rsp]
mov eax,r12d
mov DWORD[16+rsp],r14d
mov ecx,r11d
xor edx,DWORD[28+rsp]
xor eax,esi
rol ecx,5
xor edx,DWORD[52+rsp]
lea edi,[((-899497514))+rdi*1+r14]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol edx,1
xor ebp,DWORD[24+rsp]
mov eax,r11d
mov DWORD[20+rsp],edx
mov ecx,edi
xor ebp,DWORD[32+rsp]
xor eax,r13d
rol ecx,5
xor ebp,DWORD[56+rsp]
lea esi,[((-899497514))+rsi*1+rdx]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol ebp,1
xor r14d,DWORD[28+rsp]
mov eax,edi
mov DWORD[24+rsp],ebp
mov ecx,esi
xor r14d,DWORD[36+rsp]
xor eax,r12d
rol ecx,5
xor r14d,DWORD[60+rsp]
lea r13d,[((-899497514))+r13*1+rbp]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol r14d,1
xor edx,DWORD[32+rsp]
mov eax,esi
mov DWORD[28+rsp],r14d
mov ecx,r13d
xor edx,DWORD[40+rsp]
xor eax,r11d
rol ecx,5
xor edx,DWORD[rsp]
lea r12d,[((-899497514))+r12*1+r14]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol edx,1
xor ebp,DWORD[36+rsp]
mov eax,r13d
mov ecx,r12d
xor ebp,DWORD[44+rsp]
xor eax,edi
rol ecx,5
xor ebp,DWORD[4+rsp]
lea r11d,[((-899497514))+r11*1+rdx]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol ebp,1
xor r14d,DWORD[40+rsp]
mov eax,r12d
mov ecx,r11d
xor r14d,DWORD[48+rsp]
xor eax,esi
rol ecx,5
xor r14d,DWORD[8+rsp]
lea edi,[((-899497514))+rdi*1+rbp]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol r14d,1
xor edx,DWORD[44+rsp]
mov eax,r11d
mov ecx,edi
xor edx,DWORD[52+rsp]
xor eax,r13d
rol ecx,5
xor edx,DWORD[12+rsp]
lea esi,[((-899497514))+rsi*1+r14]
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
rol edx,1
xor ebp,DWORD[48+rsp]
mov eax,edi
mov ecx,esi
xor ebp,DWORD[56+rsp]
xor eax,r12d
rol ecx,5
xor ebp,DWORD[16+rsp]
lea r13d,[((-899497514))+r13*1+rdx]
xor eax,r11d
add r13d,ecx
rol edi,30
add r13d,eax
rol ebp,1
xor r14d,DWORD[52+rsp]
mov eax,esi
mov ecx,r13d
xor r14d,DWORD[60+rsp]
xor eax,r11d
rol ecx,5
xor r14d,DWORD[20+rsp]
lea r12d,[((-899497514))+r12*1+rbp]
xor eax,edi
add r12d,ecx
rol esi,30
add r12d,eax
rol r14d,1
xor edx,DWORD[56+rsp]
mov eax,r13d
mov ecx,r12d
xor edx,DWORD[rsp]
xor eax,edi
rol ecx,5
xor edx,DWORD[24+rsp]
lea r11d,[((-899497514))+r11*1+r14]
xor eax,esi
add r11d,ecx
rol r13d,30
add r11d,eax
rol edx,1
xor ebp,DWORD[60+rsp]
mov eax,r12d
mov ecx,r11d
xor ebp,DWORD[4+rsp]
xor eax,esi
rol ecx,5
xor ebp,DWORD[28+rsp]
lea edi,[((-899497514))+rdi*1+rdx]
xor eax,r13d
add edi,ecx
rol r12d,30
add edi,eax
rol ebp,1
mov eax,r11d
mov ecx,edi
xor eax,r13d
lea esi,[((-899497514))+rsi*1+rbp]
rol ecx,5
xor eax,r12d
add esi,ecx
rol r11d,30
add esi,eax
add esi,DWORD[r8]
add edi,DWORD[4+r8]
add r11d,DWORD[8+r8]
add r12d,DWORD[12+r8]
add r13d,DWORD[16+r8]
mov DWORD[r8],esi
mov DWORD[4+r8],edi
mov DWORD[8+r8],r11d
mov DWORD[12+r8],r12d
mov DWORD[16+r8],r13d
sub r10,1
lea r9,[64+r9]
jnz NEAR $L$loop
mov rsi,QWORD[64+rsp]
mov r14,QWORD[((-40))+rsi]
mov r13,QWORD[((-32))+rsi]
mov r12,QWORD[((-24))+rsi]
mov rbp,QWORD[((-16))+rsi]
mov rbx,QWORD[((-8))+rsi]
lea rsp,[rsi]
$L$epilogue:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_sha1_block_data_order:
ALIGN 16
sha1_block_data_order_ssse3:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha1_block_data_order_ssse3:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
_ssse3_shortcut:
mov r11,rsp
push rbx
push rbp
push r12
push r13
push r14
lea rsp,[((-160))+rsp]
movaps XMMWORD[(-40-96)+r11],xmm6
movaps XMMWORD[(-40-80)+r11],xmm7
movaps XMMWORD[(-40-64)+r11],xmm8
movaps XMMWORD[(-40-48)+r11],xmm9
movaps XMMWORD[(-40-32)+r11],xmm10
movaps XMMWORD[(-40-16)+r11],xmm11
$L$prologue_ssse3:
and rsp,-64
mov r8,rdi
mov r9,rsi
mov r10,rdx
shl r10,6
add r10,r9
lea r14,[((K_XX_XX+64))]
mov eax,DWORD[r8]
mov ebx,DWORD[4+r8]
mov ecx,DWORD[8+r8]
mov edx,DWORD[12+r8]
mov esi,ebx
mov ebp,DWORD[16+r8]
mov edi,ecx
xor edi,edx
and esi,edi
movdqa xmm6,XMMWORD[64+r14]
movdqa xmm9,XMMWORD[((-64))+r14]
movdqu xmm0,XMMWORD[r9]
movdqu xmm1,XMMWORD[16+r9]
movdqu xmm2,XMMWORD[32+r9]
movdqu xmm3,XMMWORD[48+r9]
DB 102,15,56,0,198
DB 102,15,56,0,206
DB 102,15,56,0,214
add r9,64
paddd xmm0,xmm9
DB 102,15,56,0,222
paddd xmm1,xmm9
paddd xmm2,xmm9
movdqa XMMWORD[rsp],xmm0
psubd xmm0,xmm9
movdqa XMMWORD[16+rsp],xmm1
psubd xmm1,xmm9
movdqa XMMWORD[32+rsp],xmm2
psubd xmm2,xmm9
jmp NEAR $L$oop_ssse3
ALIGN 16
$L$oop_ssse3:
ror ebx,2
pshufd xmm4,xmm0,238
xor esi,edx
movdqa xmm8,xmm3
paddd xmm9,xmm3
mov edi,eax
add ebp,DWORD[rsp]
punpcklqdq xmm4,xmm1
xor ebx,ecx
rol eax,5
add ebp,esi
psrldq xmm8,4
and edi,ebx
xor ebx,ecx
pxor xmm4,xmm0
add ebp,eax
ror eax,7
pxor xmm8,xmm2
xor edi,ecx
mov esi,ebp
add edx,DWORD[4+rsp]
pxor xmm4,xmm8
xor eax,ebx
rol ebp,5
movdqa XMMWORD[48+rsp],xmm9
add edx,edi
and esi,eax
movdqa xmm10,xmm4
xor eax,ebx
add edx,ebp
ror ebp,7
movdqa xmm8,xmm4
xor esi,ebx
pslldq xmm10,12
paddd xmm4,xmm4
mov edi,edx
add ecx,DWORD[8+rsp]
psrld xmm8,31
xor ebp,eax
rol edx,5
add ecx,esi
movdqa xmm9,xmm10
and edi,ebp
xor ebp,eax
psrld xmm10,30
add ecx,edx
ror edx,7
por xmm4,xmm8
xor edi,eax
mov esi,ecx
add ebx,DWORD[12+rsp]
pslld xmm9,2
pxor xmm4,xmm10
xor edx,ebp
movdqa xmm10,XMMWORD[((-64))+r14]
rol ecx,5
add ebx,edi
and esi,edx
pxor xmm4,xmm9
xor edx,ebp
add ebx,ecx
ror ecx,7
pshufd xmm5,xmm1,238
xor esi,ebp
movdqa xmm9,xmm4
paddd xmm10,xmm4
mov edi,ebx
add eax,DWORD[16+rsp]
punpcklqdq xmm5,xmm2
xor ecx,edx
rol ebx,5
add eax,esi
psrldq xmm9,4
and edi,ecx
xor ecx,edx
pxor xmm5,xmm1
add eax,ebx
ror ebx,7
pxor xmm9,xmm3
xor edi,edx
mov esi,eax
add ebp,DWORD[20+rsp]
pxor xmm5,xmm9
xor ebx,ecx
rol eax,5
movdqa XMMWORD[rsp],xmm10
add ebp,edi
and esi,ebx
movdqa xmm8,xmm5
xor ebx,ecx
add ebp,eax
ror eax,7
movdqa xmm9,xmm5
xor esi,ecx
pslldq xmm8,12
paddd xmm5,xmm5
mov edi,ebp
add edx,DWORD[24+rsp]
psrld xmm9,31
xor eax,ebx
rol ebp,5
add edx,esi
movdqa xmm10,xmm8
and edi,eax
xor eax,ebx
psrld xmm8,30
add edx,ebp
ror ebp,7
por xmm5,xmm9
xor edi,ebx
mov esi,edx
add ecx,DWORD[28+rsp]
pslld xmm10,2
pxor xmm5,xmm8
xor ebp,eax
movdqa xmm8,XMMWORD[((-32))+r14]
rol edx,5
add ecx,edi
and esi,ebp
pxor xmm5,xmm10
xor ebp,eax
add ecx,edx
ror edx,7
pshufd xmm6,xmm2,238
xor esi,eax
movdqa xmm10,xmm5
paddd xmm8,xmm5
mov edi,ecx
add ebx,DWORD[32+rsp]
punpcklqdq xmm6,xmm3
xor edx,ebp
rol ecx,5
add ebx,esi
psrldq xmm10,4
and edi,edx
xor edx,ebp
pxor xmm6,xmm2
add ebx,ecx
ror ecx,7
pxor xmm10,xmm4
xor edi,ebp
mov esi,ebx
add eax,DWORD[36+rsp]
pxor xmm6,xmm10
xor ecx,edx
rol ebx,5
movdqa XMMWORD[16+rsp],xmm8
add eax,edi
and esi,ecx
movdqa xmm9,xmm6
xor ecx,edx
add eax,ebx
ror ebx,7
movdqa xmm10,xmm6
xor esi,edx
pslldq xmm9,12
paddd xmm6,xmm6
mov edi,eax
add ebp,DWORD[40+rsp]
psrld xmm10,31
xor ebx,ecx
rol eax,5
add ebp,esi
movdqa xmm8,xmm9
and edi,ebx
xor ebx,ecx
psrld xmm9,30
add ebp,eax
ror eax,7
por xmm6,xmm10
xor edi,ecx
mov esi,ebp
add edx,DWORD[44+rsp]
pslld xmm8,2
pxor xmm6,xmm9
xor eax,ebx
movdqa xmm9,XMMWORD[((-32))+r14]
rol ebp,5
add edx,edi
and esi,eax
pxor xmm6,xmm8
xor eax,ebx
add edx,ebp
ror ebp,7
pshufd xmm7,xmm3,238
xor esi,ebx
movdqa xmm8,xmm6
paddd xmm9,xmm6
mov edi,edx
add ecx,DWORD[48+rsp]
punpcklqdq xmm7,xmm4
xor ebp,eax
rol edx,5
add ecx,esi
psrldq xmm8,4
and edi,ebp
xor ebp,eax
pxor xmm7,xmm3
add ecx,edx
ror edx,7
pxor xmm8,xmm5
xor edi,eax
mov esi,ecx
add ebx,DWORD[52+rsp]
pxor xmm7,xmm8
xor edx,ebp
rol ecx,5
movdqa XMMWORD[32+rsp],xmm9
add ebx,edi
and esi,edx
movdqa xmm10,xmm7
xor edx,ebp
add ebx,ecx
ror ecx,7
movdqa xmm8,xmm7
xor esi,ebp
pslldq xmm10,12
paddd xmm7,xmm7
mov edi,ebx
add eax,DWORD[56+rsp]
psrld xmm8,31
xor ecx,edx
rol ebx,5
add eax,esi
movdqa xmm9,xmm10
and edi,ecx
xor ecx,edx
psrld xmm10,30
add eax,ebx
ror ebx,7
por xmm7,xmm8
xor edi,edx
mov esi,eax
add ebp,DWORD[60+rsp]
pslld xmm9,2
pxor xmm7,xmm10
xor ebx,ecx
movdqa xmm10,XMMWORD[((-32))+r14]
rol eax,5
add ebp,edi
and esi,ebx
pxor xmm7,xmm9
pshufd xmm9,xmm6,238
xor ebx,ecx
add ebp,eax
ror eax,7
pxor xmm0,xmm4
xor esi,ecx
mov edi,ebp
add edx,DWORD[rsp]
punpcklqdq xmm9,xmm7
xor eax,ebx
rol ebp,5
pxor xmm0,xmm1
add edx,esi
and edi,eax
movdqa xmm8,xmm10
xor eax,ebx
paddd xmm10,xmm7
add edx,ebp
pxor xmm0,xmm9
ror ebp,7
xor edi,ebx
mov esi,edx
add ecx,DWORD[4+rsp]
movdqa xmm9,xmm0
xor ebp,eax
rol edx,5
movdqa XMMWORD[48+rsp],xmm10
add ecx,edi
and esi,ebp
xor ebp,eax
pslld xmm0,2
add ecx,edx
ror edx,7
psrld xmm9,30
xor esi,eax
mov edi,ecx
add ebx,DWORD[8+rsp]
por xmm0,xmm9
xor edx,ebp
rol ecx,5
pshufd xmm10,xmm7,238
add ebx,esi
and edi,edx
xor edx,ebp
add ebx,ecx
add eax,DWORD[12+rsp]
xor edi,ebp
mov esi,ebx
rol ebx,5
add eax,edi
xor esi,edx
ror ecx,7
add eax,ebx
pxor xmm1,xmm5
add ebp,DWORD[16+rsp]
xor esi,ecx
punpcklqdq xmm10,xmm0
mov edi,eax
rol eax,5
pxor xmm1,xmm2
add ebp,esi
xor edi,ecx
movdqa xmm9,xmm8
ror ebx,7
paddd xmm8,xmm0
add ebp,eax
pxor xmm1,xmm10
add edx,DWORD[20+rsp]
xor edi,ebx
mov esi,ebp
rol ebp,5
movdqa xmm10,xmm1
add edx,edi
xor esi,ebx
movdqa XMMWORD[rsp],xmm8
ror eax,7
add edx,ebp
add ecx,DWORD[24+rsp]
pslld xmm1,2
xor esi,eax
mov edi,edx
psrld xmm10,30
rol edx,5
add ecx,esi
xor edi,eax
ror ebp,7
por xmm1,xmm10
add ecx,edx
add ebx,DWORD[28+rsp]
pshufd xmm8,xmm0,238
xor edi,ebp
mov esi,ecx
rol ecx,5
add ebx,edi
xor esi,ebp
ror edx,7
add ebx,ecx
pxor xmm2,xmm6
add eax,DWORD[32+rsp]
xor esi,edx
punpcklqdq xmm8,xmm1
mov edi,ebx
rol ebx,5
pxor xmm2,xmm3
add eax,esi
xor edi,edx
movdqa xmm10,XMMWORD[r14]
ror ecx,7
paddd xmm9,xmm1
add eax,ebx
pxor xmm2,xmm8
add ebp,DWORD[36+rsp]
xor edi,ecx
mov esi,eax
rol eax,5
movdqa xmm8,xmm2
add ebp,edi
xor esi,ecx
movdqa XMMWORD[16+rsp],xmm9
ror ebx,7
add ebp,eax
add edx,DWORD[40+rsp]
pslld xmm2,2
xor esi,ebx
mov edi,ebp
psrld xmm8,30
rol ebp,5
add edx,esi
xor edi,ebx
ror eax,7
por xmm2,xmm8
add edx,ebp
add ecx,DWORD[44+rsp]
pshufd xmm9,xmm1,238
xor edi,eax
mov esi,edx
rol edx,5
add ecx,edi
xor esi,eax
ror ebp,7
add ecx,edx
pxor xmm3,xmm7
add ebx,DWORD[48+rsp]
xor esi,ebp
punpcklqdq xmm9,xmm2
mov edi,ecx
rol ecx,5
pxor xmm3,xmm4
add ebx,esi
xor edi,ebp
movdqa xmm8,xmm10
ror edx,7
paddd xmm10,xmm2
add ebx,ecx
pxor xmm3,xmm9
add eax,DWORD[52+rsp]
xor edi,edx
mov esi,ebx
rol ebx,5
movdqa xmm9,xmm3
add eax,edi
xor esi,edx
movdqa XMMWORD[32+rsp],xmm10
ror ecx,7
add eax,ebx
add ebp,DWORD[56+rsp]
pslld xmm3,2
xor esi,ecx
mov edi,eax
psrld xmm9,30
rol eax,5
add ebp,esi
xor edi,ecx
ror ebx,7
por xmm3,xmm9
add ebp,eax
add edx,DWORD[60+rsp]
pshufd xmm10,xmm2,238
xor edi,ebx
mov esi,ebp
rol ebp,5
add edx,edi
xor esi,ebx
ror eax,7
add edx,ebp
pxor xmm4,xmm0
add ecx,DWORD[rsp]
xor esi,eax
punpcklqdq xmm10,xmm3
mov edi,edx
rol edx,5
pxor xmm4,xmm5
add ecx,esi
xor edi,eax
movdqa xmm9,xmm8
ror ebp,7
paddd xmm8,xmm3
add ecx,edx
pxor xmm4,xmm10
add ebx,DWORD[4+rsp]
xor edi,ebp
mov esi,ecx
rol ecx,5
movdqa xmm10,xmm4
add ebx,edi
xor esi,ebp
movdqa XMMWORD[48+rsp],xmm8
ror edx,7
add ebx,ecx
add eax,DWORD[8+rsp]
pslld xmm4,2
xor esi,edx
mov edi,ebx
psrld xmm10,30
rol ebx,5
add eax,esi
xor edi,edx
ror ecx,7
por xmm4,xmm10
add eax,ebx
add ebp,DWORD[12+rsp]
pshufd xmm8,xmm3,238
xor edi,ecx
mov esi,eax
rol eax,5
add ebp,edi
xor esi,ecx
ror ebx,7
add ebp,eax
pxor xmm5,xmm1
add edx,DWORD[16+rsp]
xor esi,ebx
punpcklqdq xmm8,xmm4
mov edi,ebp
rol ebp,5
pxor xmm5,xmm6
add edx,esi
xor edi,ebx
movdqa xmm10,xmm9
ror eax,7
paddd xmm9,xmm4
add edx,ebp
pxor xmm5,xmm8
add ecx,DWORD[20+rsp]
xor edi,eax
mov esi,edx
rol edx,5
movdqa xmm8,xmm5
add ecx,edi
xor esi,eax
movdqa XMMWORD[rsp],xmm9
ror ebp,7
add ecx,edx
add ebx,DWORD[24+rsp]
pslld xmm5,2
xor esi,ebp
mov edi,ecx
psrld xmm8,30
rol ecx,5
add ebx,esi
xor edi,ebp
ror edx,7
por xmm5,xmm8
add ebx,ecx
add eax,DWORD[28+rsp]
pshufd xmm9,xmm4,238
ror ecx,7
mov esi,ebx
xor edi,edx
rol ebx,5
add eax,edi
xor esi,ecx
xor ecx,edx
add eax,ebx
pxor xmm6,xmm2
add ebp,DWORD[32+rsp]
and esi,ecx
xor ecx,edx
ror ebx,7
punpcklqdq xmm9,xmm5
mov edi,eax
xor esi,ecx
pxor xmm6,xmm7
rol eax,5
add ebp,esi
movdqa xmm8,xmm10
xor edi,ebx
paddd xmm10,xmm5
xor ebx,ecx
pxor xmm6,xmm9
add ebp,eax
add edx,DWORD[36+rsp]
and edi,ebx
xor ebx,ecx
ror eax,7
movdqa xmm9,xmm6
mov esi,ebp
xor edi,ebx
movdqa XMMWORD[16+rsp],xmm10
rol ebp,5
add edx,edi
xor esi,eax
pslld xmm6,2
xor eax,ebx
add edx,ebp
psrld xmm9,30
add ecx,DWORD[40+rsp]
and esi,eax
xor eax,ebx
por xmm6,xmm9
ror ebp,7
mov edi,edx
xor esi,eax
rol edx,5
pshufd xmm10,xmm5,238
add ecx,esi
xor edi,ebp
xor ebp,eax
add ecx,edx
add ebx,DWORD[44+rsp]
and edi,ebp
xor ebp,eax
ror edx,7
mov esi,ecx
xor edi,ebp
rol ecx,5
add ebx,edi
xor esi,edx
xor edx,ebp
add ebx,ecx
pxor xmm7,xmm3
add eax,DWORD[48+rsp]
and esi,edx
xor edx,ebp
ror ecx,7
punpcklqdq xmm10,xmm6
mov edi,ebx
xor esi,edx
pxor xmm7,xmm0
rol ebx,5
add eax,esi
movdqa xmm9,XMMWORD[32+r14]
xor edi,ecx
paddd xmm8,xmm6
xor ecx,edx
pxor xmm7,xmm10
add eax,ebx
add ebp,DWORD[52+rsp]
and edi,ecx
xor ecx,edx
ror ebx,7
movdqa xmm10,xmm7
mov esi,eax
xor edi,ecx
movdqa XMMWORD[32+rsp],xmm8
rol eax,5
add ebp,edi
xor esi,ebx
pslld xmm7,2
xor ebx,ecx
add ebp,eax
psrld xmm10,30
add edx,DWORD[56+rsp]
and esi,ebx
xor ebx,ecx
por xmm7,xmm10
ror eax,7
mov edi,ebp
xor esi,ebx
rol ebp,5
pshufd xmm8,xmm6,238
add edx,esi
xor edi,eax
xor eax,ebx
add edx,ebp
add ecx,DWORD[60+rsp]
and edi,eax
xor eax,ebx
ror ebp,7
mov esi,edx
xor edi,eax
rol edx,5
add ecx,edi
xor esi,ebp
xor ebp,eax
add ecx,edx
pxor xmm0,xmm4
add ebx,DWORD[rsp]
and esi,ebp
xor ebp,eax
ror edx,7
punpcklqdq xmm8,xmm7
mov edi,ecx
xor esi,ebp
pxor xmm0,xmm1
rol ecx,5
add ebx,esi
movdqa xmm10,xmm9
xor edi,edx
paddd xmm9,xmm7
xor edx,ebp
pxor xmm0,xmm8
add ebx,ecx
add eax,DWORD[4+rsp]
and edi,edx
xor edx,ebp
ror ecx,7
movdqa xmm8,xmm0
mov esi,ebx
xor edi,edx
movdqa XMMWORD[48+rsp],xmm9
rol ebx,5
add eax,edi
xor esi,ecx
pslld xmm0,2
xor ecx,edx
add eax,ebx
psrld xmm8,30
add ebp,DWORD[8+rsp]
and esi,ecx
xor ecx,edx
por xmm0,xmm8
ror ebx,7
mov edi,eax
xor esi,ecx
rol eax,5
pshufd xmm9,xmm7,238
add ebp,esi
xor edi,ebx
xor ebx,ecx
add ebp,eax
add edx,DWORD[12+rsp]
and edi,ebx
xor ebx,ecx
ror eax,7
mov esi,ebp
xor edi,ebx
rol ebp,5
add edx,edi
xor esi,eax
xor eax,ebx
add edx,ebp
pxor xmm1,xmm5
add ecx,DWORD[16+rsp]
and esi,eax
xor eax,ebx
ror ebp,7
punpcklqdq xmm9,xmm0
mov edi,edx
xor esi,eax
pxor xmm1,xmm2
rol edx,5
add ecx,esi
movdqa xmm8,xmm10
xor edi,ebp
paddd xmm10,xmm0
xor ebp,eax
pxor xmm1,xmm9
add ecx,edx
add ebx,DWORD[20+rsp]
and edi,ebp
xor ebp,eax
ror edx,7
movdqa xmm9,xmm1
mov esi,ecx
xor edi,ebp
movdqa XMMWORD[rsp],xmm10
rol ecx,5
add ebx,edi
xor esi,edx
pslld xmm1,2
xor edx,ebp
add ebx,ecx
psrld xmm9,30
add eax,DWORD[24+rsp]
and esi,edx
xor edx,ebp
por xmm1,xmm9
ror ecx,7
mov edi,ebx
xor esi,edx
rol ebx,5
pshufd xmm10,xmm0,238
add eax,esi
xor edi,ecx
xor ecx,edx
add eax,ebx
add ebp,DWORD[28+rsp]
and edi,ecx
xor ecx,edx
ror ebx,7
mov esi,eax
xor edi,ecx
rol eax,5
add ebp,edi
xor esi,ebx
xor ebx,ecx
add ebp,eax
pxor xmm2,xmm6
add edx,DWORD[32+rsp]
and esi,ebx
xor ebx,ecx
ror eax,7
punpcklqdq xmm10,xmm1
mov edi,ebp
xor esi,ebx
pxor xmm2,xmm3
rol ebp,5
add edx,esi
movdqa xmm9,xmm8
xor edi,eax
paddd xmm8,xmm1
xor eax,ebx
pxor xmm2,xmm10
add edx,ebp
add ecx,DWORD[36+rsp]
and edi,eax
xor eax,ebx
ror ebp,7
movdqa xmm10,xmm2
mov esi,edx
xor edi,eax
movdqa XMMWORD[16+rsp],xmm8
rol edx,5
add ecx,edi
xor esi,ebp
pslld xmm2,2
xor ebp,eax
add ecx,edx
psrld xmm10,30
add ebx,DWORD[40+rsp]
and esi,ebp
xor ebp,eax
por xmm2,xmm10
ror edx,7
mov edi,ecx
xor esi,ebp
rol ecx,5
pshufd xmm8,xmm1,238
add ebx,esi
xor edi,edx
xor edx,ebp
add ebx,ecx
add eax,DWORD[44+rsp]
and edi,edx
xor edx,ebp
ror ecx,7
mov esi,ebx
xor edi,edx
rol ebx,5
add eax,edi
xor esi,edx
add eax,ebx
pxor xmm3,xmm7
add ebp,DWORD[48+rsp]
xor esi,ecx
punpcklqdq xmm8,xmm2
mov edi,eax
rol eax,5
pxor xmm3,xmm4
add ebp,esi
xor edi,ecx
movdqa xmm10,xmm9
ror ebx,7
paddd xmm9,xmm2
add ebp,eax
pxor xmm3,xmm8
add edx,DWORD[52+rsp]
xor edi,ebx
mov esi,ebp
rol ebp,5
movdqa xmm8,xmm3
add edx,edi
xor esi,ebx
movdqa XMMWORD[32+rsp],xmm9
ror eax,7
add edx,ebp
add ecx,DWORD[56+rsp]
pslld xmm3,2
xor esi,eax
mov edi,edx
psrld xmm8,30
rol edx,5
add ecx,esi
xor edi,eax
ror ebp,7
por xmm3,xmm8
add ecx,edx
add ebx,DWORD[60+rsp]
xor edi,ebp
mov esi,ecx
rol ecx,5
add ebx,edi
xor esi,ebp
ror edx,7
add ebx,ecx
add eax,DWORD[rsp]
xor esi,edx
mov edi,ebx
rol ebx,5
paddd xmm10,xmm3
add eax,esi
xor edi,edx
movdqa XMMWORD[48+rsp],xmm10
ror ecx,7
add eax,ebx
add ebp,DWORD[4+rsp]
xor edi,ecx
mov esi,eax
rol eax,5
add ebp,edi
xor esi,ecx
ror ebx,7
add ebp,eax
add edx,DWORD[8+rsp]
xor esi,ebx
mov edi,ebp
rol ebp,5
add edx,esi
xor edi,ebx
ror eax,7
add edx,ebp
add ecx,DWORD[12+rsp]
xor edi,eax
mov esi,edx
rol edx,5
add ecx,edi
xor esi,eax
ror ebp,7
add ecx,edx
cmp r9,r10
je NEAR $L$done_ssse3
movdqa xmm6,XMMWORD[64+r14]
movdqa xmm9,XMMWORD[((-64))+r14]
movdqu xmm0,XMMWORD[r9]
movdqu xmm1,XMMWORD[16+r9]
movdqu xmm2,XMMWORD[32+r9]
movdqu xmm3,XMMWORD[48+r9]
DB 102,15,56,0,198
add r9,64
add ebx,DWORD[16+rsp]
xor esi,ebp
mov edi,ecx
DB 102,15,56,0,206
rol ecx,5
add ebx,esi
xor edi,ebp
ror edx,7
paddd xmm0,xmm9
add ebx,ecx
add eax,DWORD[20+rsp]
xor edi,edx
mov esi,ebx
movdqa XMMWORD[rsp],xmm0
rol ebx,5
add eax,edi
xor esi,edx
ror ecx,7
psubd xmm0,xmm9
add eax,ebx
add ebp,DWORD[24+rsp]
xor esi,ecx
mov edi,eax
rol eax,5
add ebp,esi
xor edi,ecx
ror ebx,7
add ebp,eax
add edx,DWORD[28+rsp]
xor edi,ebx
mov esi,ebp
rol ebp,5
add edx,edi
xor esi,ebx
ror eax,7
add edx,ebp
add ecx,DWORD[32+rsp]
xor esi,eax
mov edi,edx
DB 102,15,56,0,214
rol edx,5
add ecx,esi
xor edi,eax
ror ebp,7
paddd xmm1,xmm9
add ecx,edx
add ebx,DWORD[36+rsp]
xor edi,ebp
mov esi,ecx
movdqa XMMWORD[16+rsp],xmm1
rol ecx,5
add ebx,edi
xor esi,ebp
ror edx,7
psubd xmm1,xmm9
add ebx,ecx
add eax,DWORD[40+rsp]
xor esi,edx
mov edi,ebx
rol ebx,5
add eax,esi
xor edi,edx
ror ecx,7
add eax,ebx
add ebp,DWORD[44+rsp]
xor edi,ecx
mov esi,eax
rol eax,5
add ebp,edi
xor esi,ecx
ror ebx,7
add ebp,eax
add edx,DWORD[48+rsp]
xor esi,ebx
mov edi,ebp
DB 102,15,56,0,222
rol ebp,5
add edx,esi
xor edi,ebx
ror eax,7
paddd xmm2,xmm9
add edx,ebp
add ecx,DWORD[52+rsp]
xor edi,eax
mov esi,edx
movdqa XMMWORD[32+rsp],xmm2
rol edx,5
add ecx,edi
xor esi,eax
ror ebp,7
psubd xmm2,xmm9
add ecx,edx
add ebx,DWORD[56+rsp]
xor esi,ebp
mov edi,ecx
rol ecx,5
add ebx,esi
xor edi,ebp
ror edx,7
add ebx,ecx
add eax,DWORD[60+rsp]
xor edi,edx
mov esi,ebx
rol ebx,5
add eax,edi
ror ecx,7
add eax,ebx
add eax,DWORD[r8]
add esi,DWORD[4+r8]
add ecx,DWORD[8+r8]
add edx,DWORD[12+r8]
mov DWORD[r8],eax
add ebp,DWORD[16+r8]
mov DWORD[4+r8],esi
mov ebx,esi
mov DWORD[8+r8],ecx
mov edi,ecx
mov DWORD[12+r8],edx
xor edi,edx
mov DWORD[16+r8],ebp
and esi,edi
jmp NEAR $L$oop_ssse3
ALIGN 16
$L$done_ssse3:
add ebx,DWORD[16+rsp]
xor esi,ebp
mov edi,ecx
rol ecx,5
add ebx,esi
xor edi,ebp
ror edx,7
add ebx,ecx
add eax,DWORD[20+rsp]
xor edi,edx
mov esi,ebx
rol ebx,5
add eax,edi
xor esi,edx
ror ecx,7
add eax,ebx
add ebp,DWORD[24+rsp]
xor esi,ecx
mov edi,eax
rol eax,5
add ebp,esi
xor edi,ecx
ror ebx,7
add ebp,eax
add edx,DWORD[28+rsp]
xor edi,ebx
mov esi,ebp
rol ebp,5
add edx,edi
xor esi,ebx
ror eax,7
add edx,ebp
add ecx,DWORD[32+rsp]
xor esi,eax
mov edi,edx
rol edx,5
add ecx,esi
xor edi,eax
ror ebp,7
add ecx,edx
add ebx,DWORD[36+rsp]
xor edi,ebp
mov esi,ecx
rol ecx,5
add ebx,edi
xor esi,ebp
ror edx,7
add ebx,ecx
add eax,DWORD[40+rsp]
xor esi,edx
mov edi,ebx
rol ebx,5
add eax,esi
xor edi,edx
ror ecx,7
add eax,ebx
add ebp,DWORD[44+rsp]
xor edi,ecx
mov esi,eax
rol eax,5
add ebp,edi
xor esi,ecx
ror ebx,7
add ebp,eax
add edx,DWORD[48+rsp]
xor esi,ebx
mov edi,ebp
rol ebp,5
add edx,esi
xor edi,ebx
ror eax,7
add edx,ebp
add ecx,DWORD[52+rsp]
xor edi,eax
mov esi,edx
rol edx,5
add ecx,edi
xor esi,eax
ror ebp,7
add ecx,edx
add ebx,DWORD[56+rsp]
xor esi,ebp
mov edi,ecx
rol ecx,5
add ebx,esi
xor edi,ebp
ror edx,7
add ebx,ecx
add eax,DWORD[60+rsp]
xor edi,edx
mov esi,ebx
rol ebx,5
add eax,edi
ror ecx,7
add eax,ebx
add eax,DWORD[r8]
add esi,DWORD[4+r8]
add ecx,DWORD[8+r8]
mov DWORD[r8],eax
add edx,DWORD[12+r8]
mov DWORD[4+r8],esi
add ebp,DWORD[16+r8]
mov DWORD[8+r8],ecx
mov DWORD[12+r8],edx
mov DWORD[16+r8],ebp
movaps xmm6,XMMWORD[((-40-96))+r11]
movaps xmm7,XMMWORD[((-40-80))+r11]
movaps xmm8,XMMWORD[((-40-64))+r11]
movaps xmm9,XMMWORD[((-40-48))+r11]
movaps xmm10,XMMWORD[((-40-32))+r11]
movaps xmm11,XMMWORD[((-40-16))+r11]
mov r14,QWORD[((-40))+r11]
mov r13,QWORD[((-32))+r11]
mov r12,QWORD[((-24))+r11]
mov rbp,QWORD[((-16))+r11]
mov rbx,QWORD[((-8))+r11]
lea rsp,[r11]
$L$epilogue_ssse3:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_sha1_block_data_order_ssse3:
ALIGN 16
sha1_block_data_order_avx:
mov QWORD[8+rsp],rdi ;WIN64 prologue
mov QWORD[16+rsp],rsi
mov rax,rsp
$L$SEH_begin_sha1_block_data_order_avx:
mov rdi,rcx
mov rsi,rdx
mov rdx,r8
_avx_shortcut:
mov r11,rsp
push rbx
push rbp
push r12
push r13
push r14
lea rsp,[((-160))+rsp]
vzeroupper
vmovaps XMMWORD[(-40-96)+r11],xmm6
vmovaps XMMWORD[(-40-80)+r11],xmm7
vmovaps XMMWORD[(-40-64)+r11],xmm8
vmovaps XMMWORD[(-40-48)+r11],xmm9
vmovaps XMMWORD[(-40-32)+r11],xmm10
vmovaps XMMWORD[(-40-16)+r11],xmm11
$L$prologue_avx:
and rsp,-64
mov r8,rdi
mov r9,rsi
mov r10,rdx
shl r10,6
add r10,r9
lea r14,[((K_XX_XX+64))]
mov eax,DWORD[r8]
mov ebx,DWORD[4+r8]
mov ecx,DWORD[8+r8]
mov edx,DWORD[12+r8]
mov esi,ebx
mov ebp,DWORD[16+r8]
mov edi,ecx
xor edi,edx
and esi,edi
vmovdqa xmm6,XMMWORD[64+r14]
vmovdqa xmm11,XMMWORD[((-64))+r14]
vmovdqu xmm0,XMMWORD[r9]
vmovdqu xmm1,XMMWORD[16+r9]
vmovdqu xmm2,XMMWORD[32+r9]
vmovdqu xmm3,XMMWORD[48+r9]
vpshufb xmm0,xmm0,xmm6
add r9,64
vpshufb xmm1,xmm1,xmm6
vpshufb xmm2,xmm2,xmm6
vpshufb xmm3,xmm3,xmm6
vpaddd xmm4,xmm0,xmm11
vpaddd xmm5,xmm1,xmm11
vpaddd xmm6,xmm2,xmm11
vmovdqa XMMWORD[rsp],xmm4
vmovdqa XMMWORD[16+rsp],xmm5
vmovdqa XMMWORD[32+rsp],xmm6
jmp NEAR $L$oop_avx
ALIGN 16
$L$oop_avx:
shrd ebx,ebx,2
xor esi,edx
vpalignr xmm4,xmm1,xmm0,8
mov edi,eax
add ebp,DWORD[rsp]
vpaddd xmm9,xmm11,xmm3
xor ebx,ecx
shld eax,eax,5
vpsrldq xmm8,xmm3,4
add ebp,esi
and edi,ebx
vpxor xmm4,xmm4,xmm0
xor ebx,ecx
add ebp,eax
vpxor xmm8,xmm8,xmm2
shrd eax,eax,7
xor edi,ecx
mov esi,ebp
add edx,DWORD[4+rsp]
vpxor xmm4,xmm4,xmm8
xor eax,ebx
shld ebp,ebp,5
vmovdqa XMMWORD[48+rsp],xmm9
add edx,edi
and esi,eax
vpsrld xmm8,xmm4,31
xor eax,ebx
add edx,ebp
shrd ebp,ebp,7
xor esi,ebx
vpslldq xmm10,xmm4,12
vpaddd xmm4,xmm4,xmm4
mov edi,edx
add ecx,DWORD[8+rsp]
xor ebp,eax
shld edx,edx,5
vpsrld xmm9,xmm10,30
vpor xmm4,xmm4,xmm8
add ecx,esi
and edi,ebp
xor ebp,eax
add ecx,edx
vpslld xmm10,xmm10,2
vpxor xmm4,xmm4,xmm9
shrd edx,edx,7
xor edi,eax
mov esi,ecx
add ebx,DWORD[12+rsp]
vpxor xmm4,xmm4,xmm10
xor edx,ebp
shld ecx,ecx,5
add ebx,edi
and esi,edx
xor edx,ebp
add ebx,ecx
shrd ecx,ecx,7
xor esi,ebp
vpalignr xmm5,xmm2,xmm1,8
mov edi,ebx
add eax,DWORD[16+rsp]
vpaddd xmm9,xmm11,xmm4
xor ecx,edx
shld ebx,ebx,5
vpsrldq xmm8,xmm4,4
add eax,esi
and edi,ecx
vpxor xmm5,xmm5,xmm1
xor ecx,edx
add eax,ebx
vpxor xmm8,xmm8,xmm3
shrd ebx,ebx,7
xor edi,edx
mov esi,eax
add ebp,DWORD[20+rsp]
vpxor xmm5,xmm5,xmm8
xor ebx,ecx
shld eax,eax,5
vmovdqa XMMWORD[rsp],xmm9
add ebp,edi
and esi,ebx
vpsrld xmm8,xmm5,31
xor ebx,ecx
add ebp,eax
shrd eax,eax,7
xor esi,ecx
vpslldq xmm10,xmm5,12
vpaddd xmm5,xmm5,xmm5
mov edi,ebp
add edx,DWORD[24+rsp]
xor eax,ebx
shld ebp,ebp,5
vpsrld xmm9,xmm10,30
vpor xmm5,xmm5,xmm8
add edx,esi
and edi,eax
xor eax,ebx
add edx,ebp
vpslld xmm10,xmm10,2
vpxor xmm5,xmm5,xmm9
shrd ebp,ebp,7
xor edi,ebx
mov esi,edx
add ecx,DWORD[28+rsp]
vpxor xmm5,xmm5,xmm10
xor ebp,eax
shld edx,edx,5
vmovdqa xmm11,XMMWORD[((-32))+r14]
add ecx,edi
and esi,ebp
xor ebp,eax
add ecx,edx
shrd edx,edx,7
xor esi,eax
vpalignr xmm6,xmm3,xmm2,8
mov edi,ecx
add ebx,DWORD[32+rsp]
vpaddd xmm9,xmm11,xmm5
xor edx,ebp
shld ecx,ecx,5
vpsrldq xmm8,xmm5,4
add ebx,esi
and edi,edx
vpxor xmm6,xmm6,xmm2
xor edx,ebp
add ebx,ecx
vpxor xmm8,xmm8,xmm4
shrd ecx,ecx,7
xor edi,ebp
mov esi,ebx
add eax,DWORD[36+rsp]
vpxor xmm6,xmm6,xmm8
xor ecx,edx
shld ebx,ebx,5
vmovdqa XMMWORD[16+rsp],xmm9
add eax,edi
and esi,ecx
vpsrld xmm8,xmm6,31
xor ecx,edx
add eax,ebx
shrd ebx,ebx,7
xor esi,edx
vpslldq xmm10,xmm6,12
vpaddd xmm6,xmm6,xmm6
mov edi,eax
add ebp,DWORD[40+rsp]
xor ebx,ecx
shld eax,eax,5
vpsrld xmm9,xmm10,30
vpor xmm6,xmm6,xmm8
add ebp,esi
and edi,ebx
xor ebx,ecx
add ebp,eax
vpslld xmm10,xmm10,2
vpxor xmm6,xmm6,xmm9
shrd eax,eax,7
xor edi,ecx
mov esi,ebp
add edx,DWORD[44+rsp]
vpxor xmm6,xmm6,xmm10
xor eax,ebx
shld ebp,ebp,5
add edx,edi
and esi,eax
xor eax,ebx
add edx,ebp
shrd ebp,ebp,7
xor esi,ebx
vpalignr xmm7,xmm4,xmm3,8
mov edi,edx
add ecx,DWORD[48+rsp]
vpaddd xmm9,xmm11,xmm6
xor ebp,eax
shld edx,edx,5
vpsrldq xmm8,xmm6,4
add ecx,esi
and edi,ebp
vpxor xmm7,xmm7,xmm3
xor ebp,eax
add ecx,edx
vpxor xmm8,xmm8,xmm5
shrd edx,edx,7
xor edi,eax
mov esi,ecx
add ebx,DWORD[52+rsp]
vpxor xmm7,xmm7,xmm8
xor edx,ebp
shld ecx,ecx,5
vmovdqa XMMWORD[32+rsp],xmm9
add ebx,edi
and esi,edx
vpsrld xmm8,xmm7,31
xor edx,ebp
add ebx,ecx
shrd ecx,ecx,7
xor esi,ebp
vpslldq xmm10,xmm7,12
vpaddd xmm7,xmm7,xmm7
mov edi,ebx
add eax,DWORD[56+rsp]
xor ecx,edx
shld ebx,ebx,5
vpsrld xmm9,xmm10,30
vpor xmm7,xmm7,xmm8
add eax,esi
and edi,ecx
xor ecx,edx
add eax,ebx
vpslld xmm10,xmm10,2
vpxor xmm7,xmm7,xmm9
shrd ebx,ebx,7
xor edi,edx
mov esi,eax
add ebp,DWORD[60+rsp]
vpxor xmm7,xmm7,xmm10
xor ebx,ecx
shld eax,eax,5
add ebp,edi
and esi,ebx
xor ebx,ecx
add ebp,eax
vpalignr xmm8,xmm7,xmm6,8
vpxor xmm0,xmm0,xmm4
shrd eax,eax,7
xor esi,ecx
mov edi,ebp
add edx,DWORD[rsp]
vpxor xmm0,xmm0,xmm1
xor eax,ebx
shld ebp,ebp,5
vpaddd xmm9,xmm11,xmm7
add edx,esi
and edi,eax
vpxor xmm0,xmm0,xmm8
xor eax,ebx
add edx,ebp
shrd ebp,ebp,7
xor edi,ebx
vpsrld xmm8,xmm0,30
vmovdqa XMMWORD[48+rsp],xmm9
mov esi,edx
add ecx,DWORD[4+rsp]
xor ebp,eax
shld edx,edx,5
vpslld xmm0,xmm0,2
add ecx,edi
and esi,ebp
xor ebp,eax
add ecx,edx
shrd edx,edx,7
xor esi,eax
mov edi,ecx
add ebx,DWORD[8+rsp]
vpor xmm0,xmm0,xmm8
xor edx,ebp
shld ecx,ecx,5
add ebx,esi
and edi,edx
xor edx,ebp
add ebx,ecx
add eax,DWORD[12+rsp]
xor edi,ebp
mov esi,ebx
shld ebx,ebx,5
add eax,edi
xor esi,edx
shrd ecx,ecx,7
add eax,ebx
vpalignr xmm8,xmm0,xmm7,8
vpxor xmm1,xmm1,xmm5
add ebp,DWORD[16+rsp]
xor esi,ecx
mov edi,eax
shld eax,eax,5
vpxor xmm1,xmm1,xmm2
add ebp,esi
xor edi,ecx
vpaddd xmm9,xmm11,xmm0
shrd ebx,ebx,7
add ebp,eax
vpxor xmm1,xmm1,xmm8
add edx,DWORD[20+rsp]
xor edi,ebx
mov esi,ebp
shld ebp,ebp,5
vpsrld xmm8,xmm1,30
vmovdqa XMMWORD[rsp],xmm9
add edx,edi
xor esi,ebx
shrd eax,eax,7
add edx,ebp
vpslld xmm1,xmm1,2
add ecx,DWORD[24+rsp]
xor esi,eax
mov edi,edx
shld edx,edx,5
add ecx,esi
xor edi,eax
shrd ebp,ebp,7
add ecx,edx
vpor xmm1,xmm1,xmm8
add ebx,DWORD[28+rsp]
xor edi,ebp
mov esi,ecx
shld ecx,ecx,5
add ebx,edi
xor esi,ebp
shrd edx,edx,7
add ebx,ecx
vpalignr xmm8,xmm1,xmm0,8
vpxor xmm2,xmm2,xmm6
add eax,DWORD[32+rsp]
xor esi,edx
mov edi,ebx
shld ebx,ebx,5
vpxor xmm2,xmm2,xmm3
add eax,esi
xor edi,edx
vpaddd xmm9,xmm11,xmm1
vmovdqa xmm11,XMMWORD[r14]
shrd ecx,ecx,7
add eax,ebx
vpxor xmm2,xmm2,xmm8
add ebp,DWORD[36+rsp]
xor edi,ecx
mov esi,eax
shld eax,eax,5
vpsrld xmm8,xmm2,30
vmovdqa XMMWORD[16+rsp],xmm9
add ebp,edi
xor esi,ecx
shrd ebx,ebx,7
add ebp,eax
vpslld xmm2,xmm2,2
add edx,DWORD[40+rsp]
xor esi,ebx
mov edi,ebp
shld ebp,ebp,5
add edx,esi
xor edi,ebx
shrd eax,eax,7
add edx,ebp
vpor xmm2,xmm2,xmm8
add ecx,DWORD[44+rsp]
xor edi,eax
mov esi,edx
shld edx,edx,5
add ecx,edi
xor esi,eax
shrd ebp,ebp,7
add ecx,edx
vpalignr xmm8,xmm2,xmm1,8
vpxor xmm3,xmm3,xmm7
add ebx,DWORD[48+rsp]
xor esi,ebp
mov edi,ecx
shld ecx,ecx,5
vpxor xmm3,xmm3,xmm4
add ebx,esi
xor edi,ebp
vpaddd xmm9,xmm11,xmm2
shrd edx,edx,7
add ebx,ecx
vpxor xmm3,xmm3,xmm8
add eax,DWORD[52+rsp]
xor edi,edx
mov esi,ebx
shld ebx,ebx,5
vpsrld xmm8,xmm3,30
vmovdqa XMMWORD[32+rsp],xmm9
add eax,edi
xor esi,edx
shrd ecx,ecx,7
add eax,ebx
vpslld xmm3,xmm3,2
add ebp,DWORD[56+rsp]
xor esi,ecx
mov edi,eax
shld eax,eax,5
add ebp,esi
xor edi,ecx
shrd ebx,ebx,7
add ebp,eax
vpor xmm3,xmm3,xmm8
add edx,DWORD[60+rsp]
xor edi,ebx
mov esi,ebp
shld ebp,ebp,5
add edx,edi
xor esi,ebx
shrd eax,eax,7
add edx,ebp
vpalignr xmm8,xmm3,xmm2,8
vpxor xmm4,xmm4,xmm0
add ecx,DWORD[rsp]
xor esi,eax
mov edi,edx
shld edx,edx,5
vpxor xmm4,xmm4,xmm5
add ecx,esi
xor edi,eax
vpaddd xmm9,xmm11,xmm3
shrd ebp,ebp,7
add ecx,edx
vpxor xmm4,xmm4,xmm8
add ebx,DWORD[4+rsp]
xor edi,ebp
mov esi,ecx
shld ecx,ecx,5
vpsrld xmm8,xmm4,30
vmovdqa XMMWORD[48+rsp],xmm9
add ebx,edi
xor esi,ebp
shrd edx,edx,7
add ebx,ecx
vpslld xmm4,xmm4,2
add eax,DWORD[8+rsp]
xor esi,edx
mov edi,ebx
shld ebx,ebx,5
add eax,esi
xor edi,edx
shrd ecx,ecx,7
add eax,ebx
vpor xmm4,xmm4,xmm8
add ebp,DWORD[12+rsp]
xor edi,ecx
mov esi,eax
shld eax,eax,5
add ebp,edi
xor esi,ecx
shrd ebx,ebx,7
add ebp,eax
vpalignr xmm8,xmm4,xmm3,8
vpxor xmm5,xmm5,xmm1
add edx,DWORD[16+rsp]
xor esi,ebx
mov edi,ebp
shld ebp,ebp,5
vpxor xmm5,xmm5,xmm6
add edx,esi
xor edi,ebx
vpaddd xmm9,xmm11,xmm4
shrd eax,eax,7
add edx,ebp
vpxor xmm5,xmm5,xmm8
add ecx,DWORD[20+rsp]
xor edi,eax
mov esi,edx
shld edx,edx,5
vpsrld xmm8,xmm5,30
vmovdqa XMMWORD[rsp],xmm9
add ecx,edi
xor esi,eax
shrd ebp,ebp,7
add ecx,edx
vpslld xmm5,xmm5,2
add ebx,DWORD[24+rsp]
xor esi,ebp
mov edi,ecx
shld ecx,ecx,5
add ebx,esi
xor edi,ebp
shrd edx,edx,7
add ebx,ecx
vpor xmm5,xmm5,xmm8
add eax,DWORD[28+rsp]
shrd ecx,ecx,7
mov esi,ebx
xor edi,edx
shld ebx,ebx,5
add eax,edi
xor esi,ecx
xor ecx,edx
add eax,ebx
vpalignr xmm8,xmm5,xmm4,8
vpxor xmm6,xmm6,xmm2
add ebp,DWORD[32+rsp]
and esi,ecx
xor ecx,edx
shrd ebx,ebx,7
vpxor xmm6,xmm6,xmm7
mov edi,eax
xor esi,ecx
vpaddd xmm9,xmm11,xmm5
shld eax,eax,5
add ebp,esi
vpxor xmm6,xmm6,xmm8
xor edi,ebx
xor ebx,ecx
add ebp,eax
add edx,DWORD[36+rsp]
vpsrld xmm8,xmm6,30
vmovdqa XMMWORD[16+rsp],xmm9
and edi,ebx
xor ebx,ecx
shrd eax,eax,7
mov esi,ebp
vpslld xmm6,xmm6,2
xor edi,ebx
shld ebp,ebp,5
add edx,edi
xor esi,eax
xor eax,ebx
add edx,ebp
add ecx,DWORD[40+rsp]
and esi,eax
vpor xmm6,xmm6,xmm8
xor eax,ebx
shrd ebp,ebp,7
mov edi,edx
xor esi,eax
shld edx,edx,5
add ecx,esi
xor edi,ebp
xor ebp,eax
add ecx,edx
add ebx,DWORD[44+rsp]
and edi,ebp
xor ebp,eax
shrd edx,edx,7
mov esi,ecx
xor edi,ebp
shld ecx,ecx,5
add ebx,edi
xor esi,edx
xor edx,ebp
add ebx,ecx
vpalignr xmm8,xmm6,xmm5,8
vpxor xmm7,xmm7,xmm3
add eax,DWORD[48+rsp]
and esi,edx
xor edx,ebp
shrd ecx,ecx,7
vpxor xmm7,xmm7,xmm0
mov edi,ebx
xor esi,edx
vpaddd xmm9,xmm11,xmm6
vmovdqa xmm11,XMMWORD[32+r14]
shld ebx,ebx,5
add eax,esi
vpxor xmm7,xmm7,xmm8
xor edi,ecx
xor ecx,edx
add eax,ebx
add ebp,DWORD[52+rsp]
vpsrld xmm8,xmm7,30
vmovdqa XMMWORD[32+rsp],xmm9
and edi,ecx
xor ecx,edx
shrd ebx,ebx,7
mov esi,eax
vpslld xmm7,xmm7,2
xor edi,ecx
shld eax,eax,5
add ebp,edi
xor esi,ebx
xor ebx,ecx
add ebp,eax
add edx,DWORD[56+rsp]
and esi,ebx
vpor xmm7,xmm7,xmm8
xor ebx,ecx
shrd eax,eax,7
mov edi,ebp
xor esi,ebx
shld ebp,ebp,5
add edx,esi
xor edi,eax
xor eax,ebx
add edx,ebp
add ecx,DWORD[60+rsp]
and edi,eax
xor eax,ebx
shrd ebp,ebp,7
mov esi,edx
xor edi,eax
shld edx,edx,5
add ecx,edi
xor esi,ebp
xor ebp,eax
add ecx,edx
vpalignr xmm8,xmm7,xmm6,8
vpxor xmm0,xmm0,xmm4
add ebx,DWORD[rsp]
and esi,ebp
xor ebp,eax
shrd edx,edx,7
vpxor xmm0,xmm0,xmm1
mov edi,ecx
xor esi,ebp
vpaddd xmm9,xmm11,xmm7
shld ecx,ecx,5
add ebx,esi
vpxor xmm0,xmm0,xmm8
xor edi,edx
xor edx,ebp
add ebx,ecx
add eax,DWORD[4+rsp]
vpsrld xmm8,xmm0,30
vmovdqa XMMWORD[48+rsp],xmm9
and edi,edx
xor edx,ebp
shrd ecx,ecx,7
mov esi,ebx
vpslld xmm0,xmm0,2
xor edi,edx
shld ebx,ebx,5
add eax,edi
xor esi,ecx
xor ecx,edx
add eax,ebx
add ebp,DWORD[8+rsp]
and esi,ecx
vpor xmm0,xmm0,xmm8
xor ecx,edx
shrd ebx,ebx,7
mov edi,eax
xor esi,ecx
shld eax,eax,5
add ebp,esi
xor edi,ebx
xor ebx,ecx
add ebp,eax
add edx,DWORD[12+rsp]
and edi,ebx
xor ebx,ecx
shrd eax,eax,7
mov esi,ebp
xor edi,ebx
shld ebp,ebp,5
add edx,edi
xor esi,eax
xor eax,ebx
add edx,ebp
vpalignr xmm8,xmm0,xmm7,8
vpxor xmm1,xmm1,xmm5
add ecx,DWORD[16+rsp]
and esi,eax
xor eax,ebx
shrd ebp,ebp,7
vpxor xmm1,xmm1,xmm2
mov edi,edx
xor esi,eax
vpaddd xmm9,xmm11,xmm0
shld edx,edx,5
add ecx,esi
vpxor xmm1,xmm1,xmm8
xor edi,ebp
xor ebp,eax
add ecx,edx
add ebx,DWORD[20+rsp]
vpsrld xmm8,xmm1,30
vmovdqa XMMWORD[rsp],xmm9
and edi,ebp
xor ebp,eax
shrd edx,edx,7
mov esi,ecx
vpslld xmm1,xmm1,2
xor edi,ebp
shld ecx,ecx,5
add ebx,edi
xor esi,edx
xor edx,ebp
add ebx,ecx
add eax,DWORD[24+rsp]
and esi,edx
vpor xmm1,xmm1,xmm8
xor edx,ebp
shrd ecx,ecx,7
mov edi,ebx
xor esi,edx
shld ebx,ebx,5
add eax,esi
xor edi,ecx
xor ecx,edx
add eax,ebx
add ebp,DWORD[28+rsp]
and edi,ecx
xor ecx,edx
shrd ebx,ebx,7
mov esi,eax
xor edi,ecx
shld eax,eax,5
add ebp,edi
xor esi,ebx
xor ebx,ecx
add ebp,eax
vpalignr xmm8,xmm1,xmm0,8
vpxor xmm2,xmm2,xmm6
add edx,DWORD[32+rsp]
and esi,ebx
xor ebx,ecx
shrd eax,eax,7
vpxor xmm2,xmm2,xmm3
mov edi,ebp
xor esi,ebx
vpaddd xmm9,xmm11,xmm1
shld ebp,ebp,5
add edx,esi
vpxor xmm2,xmm2,xmm8
xor edi,eax
xor eax,ebx
add edx,ebp
add ecx,DWORD[36+rsp]
vpsrld xmm8,xmm2,30
vmovdqa XMMWORD[16+rsp],xmm9
and edi,eax
xor eax,ebx
shrd ebp,ebp,7
mov esi,edx
vpslld xmm2,xmm2,2
xor edi,eax
shld edx,edx,5
add ecx,edi
xor esi,ebp
xor ebp,eax
add ecx,edx
add ebx,DWORD[40+rsp]
and esi,ebp
vpor xmm2,xmm2,xmm8
xor ebp,eax
shrd edx,edx,7
mov edi,ecx
xor esi,ebp
shld ecx,ecx,5
add ebx,esi
xor edi,edx
xor edx,ebp
add ebx,ecx
add eax,DWORD[44+rsp]
and edi,edx
xor edx,ebp
shrd ecx,ecx,7
mov esi,ebx
xor edi,edx
shld ebx,ebx,5
add eax,edi
xor esi,edx
add eax,ebx
vpalignr xmm8,xmm2,xmm1,8
vpxor xmm3,xmm3,xmm7
add ebp,DWORD[48+rsp]
xor esi,ecx
mov edi,eax
shld eax,eax,5
vpxor xmm3,xmm3,xmm4
add ebp,esi
xor edi,ecx
vpaddd xmm9,xmm11,xmm2
shrd ebx,ebx,7
add ebp,eax
vpxor xmm3,xmm3,xmm8
add edx,DWORD[52+rsp]
xor edi,ebx
mov esi,ebp
shld ebp,ebp,5
vpsrld xmm8,xmm3,30
vmovdqa XMMWORD[32+rsp],xmm9
add edx,edi
xor esi,ebx
shrd eax,eax,7
add edx,ebp
vpslld xmm3,xmm3,2
add ecx,DWORD[56+rsp]
xor esi,eax
mov edi,edx
shld edx,edx,5
add ecx,esi
xor edi,eax
shrd ebp,ebp,7
add ecx,edx
vpor xmm3,xmm3,xmm8
add ebx,DWORD[60+rsp]
xor edi,ebp
mov esi,ecx
shld ecx,ecx,5
add ebx,edi
xor esi,ebp
shrd edx,edx,7
add ebx,ecx
add eax,DWORD[rsp]
vpaddd xmm9,xmm11,xmm3
xor esi,edx
mov edi,ebx
shld ebx,ebx,5
add eax,esi
vmovdqa XMMWORD[48+rsp],xmm9
xor edi,edx
shrd ecx,ecx,7
add eax,ebx
add ebp,DWORD[4+rsp]
xor edi,ecx
mov esi,eax
shld eax,eax,5
add ebp,edi
xor esi,ecx
shrd ebx,ebx,7
add ebp,eax
add edx,DWORD[8+rsp]
xor esi,ebx
mov edi,ebp
shld ebp,ebp,5
add edx,esi
xor edi,ebx
shrd eax,eax,7
add edx,ebp
add ecx,DWORD[12+rsp]
xor edi,eax
mov esi,edx
shld edx,edx,5
add ecx,edi
xor esi,eax
shrd ebp,ebp,7
add ecx,edx
cmp r9,r10
je NEAR $L$done_avx
vmovdqa xmm6,XMMWORD[64+r14]
vmovdqa xmm11,XMMWORD[((-64))+r14]
vmovdqu xmm0,XMMWORD[r9]
vmovdqu xmm1,XMMWORD[16+r9]
vmovdqu xmm2,XMMWORD[32+r9]
vmovdqu xmm3,XMMWORD[48+r9]
vpshufb xmm0,xmm0,xmm6
add r9,64
add ebx,DWORD[16+rsp]
xor esi,ebp
vpshufb xmm1,xmm1,xmm6
mov edi,ecx
shld ecx,ecx,5
vpaddd xmm4,xmm0,xmm11
add ebx,esi
xor edi,ebp
shrd edx,edx,7
add ebx,ecx
vmovdqa XMMWORD[rsp],xmm4
add eax,DWORD[20+rsp]
xor edi,edx
mov esi,ebx
shld ebx,ebx,5
add eax,edi
xor esi,edx
shrd ecx,ecx,7
add eax,ebx
add ebp,DWORD[24+rsp]
xor esi,ecx
mov edi,eax
shld eax,eax,5
add ebp,esi
xor edi,ecx
shrd ebx,ebx,7
add ebp,eax
add edx,DWORD[28+rsp]
xor edi,ebx
mov esi,ebp
shld ebp,ebp,5
add edx,edi
xor esi,ebx
shrd eax,eax,7
add edx,ebp
add ecx,DWORD[32+rsp]
xor esi,eax
vpshufb xmm2,xmm2,xmm6
mov edi,edx
shld edx,edx,5
vpaddd xmm5,xmm1,xmm11
add ecx,esi
xor edi,eax
shrd ebp,ebp,7
add ecx,edx
vmovdqa XMMWORD[16+rsp],xmm5
add ebx,DWORD[36+rsp]
xor edi,ebp
mov esi,ecx
shld ecx,ecx,5
add ebx,edi
xor esi,ebp
shrd edx,edx,7
add ebx,ecx
add eax,DWORD[40+rsp]
xor esi,edx
mov edi,ebx
shld ebx,ebx,5
add eax,esi
xor edi,edx
shrd ecx,ecx,7
add eax,ebx
add ebp,DWORD[44+rsp]
xor edi,ecx
mov esi,eax
shld eax,eax,5
add ebp,edi
xor esi,ecx
shrd ebx,ebx,7
add ebp,eax
add edx,DWORD[48+rsp]
xor esi,ebx
vpshufb xmm3,xmm3,xmm6
mov edi,ebp
shld ebp,ebp,5
vpaddd xmm6,xmm2,xmm11
add edx,esi
xor edi,ebx
shrd eax,eax,7
add edx,ebp
vmovdqa XMMWORD[32+rsp],xmm6
add ecx,DWORD[52+rsp]
xor edi,eax
mov esi,edx
shld edx,edx,5
add ecx,edi
xor esi,eax
shrd ebp,ebp,7
add ecx,edx
add ebx,DWORD[56+rsp]
xor esi,ebp
mov edi,ecx
shld ecx,ecx,5
add ebx,esi
xor edi,ebp
shrd edx,edx,7
add ebx,ecx
add eax,DWORD[60+rsp]
xor edi,edx
mov esi,ebx
shld ebx,ebx,5
add eax,edi
shrd ecx,ecx,7
add eax,ebx
add eax,DWORD[r8]
add esi,DWORD[4+r8]
add ecx,DWORD[8+r8]
add edx,DWORD[12+r8]
mov DWORD[r8],eax
add ebp,DWORD[16+r8]
mov DWORD[4+r8],esi
mov ebx,esi
mov DWORD[8+r8],ecx
mov edi,ecx
mov DWORD[12+r8],edx
xor edi,edx
mov DWORD[16+r8],ebp
and esi,edi
jmp NEAR $L$oop_avx
ALIGN 16
$L$done_avx:
add ebx,DWORD[16+rsp]
xor esi,ebp
mov edi,ecx
shld ecx,ecx,5
add ebx,esi
xor edi,ebp
shrd edx,edx,7
add ebx,ecx
add eax,DWORD[20+rsp]
xor edi,edx
mov esi,ebx
shld ebx,ebx,5
add eax,edi
xor esi,edx
shrd ecx,ecx,7
add eax,ebx
add ebp,DWORD[24+rsp]
xor esi,ecx
mov edi,eax
shld eax,eax,5
add ebp,esi
xor edi,ecx
shrd ebx,ebx,7
add ebp,eax
add edx,DWORD[28+rsp]
xor edi,ebx
mov esi,ebp
shld ebp,ebp,5
add edx,edi
xor esi,ebx
shrd eax,eax,7
add edx,ebp
add ecx,DWORD[32+rsp]
xor esi,eax
mov edi,edx
shld edx,edx,5
add ecx,esi
xor edi,eax
shrd ebp,ebp,7
add ecx,edx
add ebx,DWORD[36+rsp]
xor edi,ebp
mov esi,ecx
shld ecx,ecx,5
add ebx,edi
xor esi,ebp
shrd edx,edx,7
add ebx,ecx
add eax,DWORD[40+rsp]
xor esi,edx
mov edi,ebx
shld ebx,ebx,5
add eax,esi
xor edi,edx
shrd ecx,ecx,7
add eax,ebx
add ebp,DWORD[44+rsp]
xor edi,ecx
mov esi,eax
shld eax,eax,5
add ebp,edi
xor esi,ecx
shrd ebx,ebx,7
add ebp,eax
add edx,DWORD[48+rsp]
xor esi,ebx
mov edi,ebp
shld ebp,ebp,5
add edx,esi
xor edi,ebx
shrd eax,eax,7
add edx,ebp
add ecx,DWORD[52+rsp]
xor edi,eax
mov esi,edx
shld edx,edx,5
add ecx,edi
xor esi,eax
shrd ebp,ebp,7
add ecx,edx
add ebx,DWORD[56+rsp]
xor esi,ebp
mov edi,ecx
shld ecx,ecx,5
add ebx,esi
xor edi,ebp
shrd edx,edx,7
add ebx,ecx
add eax,DWORD[60+rsp]
xor edi,edx
mov esi,ebx
shld ebx,ebx,5
add eax,edi
shrd ecx,ecx,7
add eax,ebx
vzeroupper
add eax,DWORD[r8]
add esi,DWORD[4+r8]
add ecx,DWORD[8+r8]
mov DWORD[r8],eax
add edx,DWORD[12+r8]
mov DWORD[4+r8],esi
add ebp,DWORD[16+r8]
mov DWORD[8+r8],ecx
mov DWORD[12+r8],edx
mov DWORD[16+r8],ebp
movaps xmm6,XMMWORD[((-40-96))+r11]
movaps xmm7,XMMWORD[((-40-80))+r11]
movaps xmm8,XMMWORD[((-40-64))+r11]
movaps xmm9,XMMWORD[((-40-48))+r11]
movaps xmm10,XMMWORD[((-40-32))+r11]
movaps xmm11,XMMWORD[((-40-16))+r11]
mov r14,QWORD[((-40))+r11]
mov r13,QWORD[((-32))+r11]
mov r12,QWORD[((-24))+r11]
mov rbp,QWORD[((-16))+r11]
mov rbx,QWORD[((-8))+r11]
lea rsp,[r11]
$L$epilogue_avx:
mov rdi,QWORD[8+rsp] ;WIN64 epilogue
mov rsi,QWORD[16+rsp]
DB 0F3h,0C3h ;repret
$L$SEH_end_sha1_block_data_order_avx:
ALIGN 64
K_XX_XX:
DD 0x5a827999,0x5a827999,0x5a827999,0x5a827999
DD 0x5a827999,0x5a827999,0x5a827999,0x5a827999
DD 0x6ed9eba1,0x6ed9eba1,0x6ed9eba1,0x6ed9eba1
DD 0x6ed9eba1,0x6ed9eba1,0x6ed9eba1,0x6ed9eba1
DD 0x8f1bbcdc,0x8f1bbcdc,0x8f1bbcdc,0x8f1bbcdc
DD 0x8f1bbcdc,0x8f1bbcdc,0x8f1bbcdc,0x8f1bbcdc
DD 0xca62c1d6,0xca62c1d6,0xca62c1d6,0xca62c1d6
DD 0xca62c1d6,0xca62c1d6,0xca62c1d6,0xca62c1d6
DD 0x00010203,0x04050607,0x08090a0b,0x0c0d0e0f
DD 0x00010203,0x04050607,0x08090a0b,0x0c0d0e0f
DB 0xf,0xe,0xd,0xc,0xb,0xa,0x9,0x8,0x7,0x6,0x5,0x4,0x3,0x2,0x1,0x0
DB 83,72,65,49,32,98,108,111,99,107,32,116,114,97,110,115
DB 102,111,114,109,32,102,111,114,32,120,56,54,95,54,52,44
DB 32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60
DB 97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114
DB 103,62,0
ALIGN 64
EXTERN __imp_RtlVirtualUnwind
ALIGN 16
se_handler:
push rsi
push rdi
push rbx
push rbp
push r12
push r13
push r14
push r15
pushfq
sub rsp,64
mov rax,QWORD[120+r8]
mov rbx,QWORD[248+r8]
lea r10,[$L$prologue]
cmp rbx,r10
jb NEAR $L$common_seh_tail
mov rax,QWORD[152+r8]
lea r10,[$L$epilogue]
cmp rbx,r10
jae NEAR $L$common_seh_tail
mov rax,QWORD[64+rax]
mov rbx,QWORD[((-8))+rax]
mov rbp,QWORD[((-16))+rax]
mov r12,QWORD[((-24))+rax]
mov r13,QWORD[((-32))+rax]
mov r14,QWORD[((-40))+rax]
mov QWORD[144+r8],rbx
mov QWORD[160+r8],rbp
mov QWORD[216+r8],r12
mov QWORD[224+r8],r13
mov QWORD[232+r8],r14
jmp NEAR $L$common_seh_tail
ALIGN 16
ssse3_handler:
push rsi
push rdi
push rbx
push rbp
push r12
push r13
push r14
push r15
pushfq
sub rsp,64
mov rax,QWORD[120+r8]
mov rbx,QWORD[248+r8]
mov rsi,QWORD[8+r9]
mov r11,QWORD[56+r9]
mov r10d,DWORD[r11]
lea r10,[r10*1+rsi]
cmp rbx,r10
jb NEAR $L$common_seh_tail
mov rax,QWORD[208+r8]
mov r10d,DWORD[4+r11]
lea r10,[r10*1+rsi]
cmp rbx,r10
jae NEAR $L$common_seh_tail
lea rsi,[((-40-96))+rax]
lea rdi,[512+r8]
mov ecx,12
DD 0xa548f3fc
mov rbx,QWORD[((-8))+rax]
mov rbp,QWORD[((-16))+rax]
mov r12,QWORD[((-24))+rax]
mov r13,QWORD[((-32))+rax]
mov r14,QWORD[((-40))+rax]
mov QWORD[144+r8],rbx
mov QWORD[160+r8],rbp
mov QWORD[216+r8],r12
mov QWORD[224+r8],r13
mov QWORD[232+r8],r14
$L$common_seh_tail:
mov rdi,QWORD[8+rax]
mov rsi,QWORD[16+rax]
mov QWORD[152+r8],rax
mov QWORD[168+r8],rsi
mov QWORD[176+r8],rdi
mov rdi,QWORD[40+r9]
mov rsi,r8
mov ecx,154
DD 0xa548f3fc
mov rsi,r9
xor rcx,rcx
mov rdx,QWORD[8+rsi]
mov r8,QWORD[rsi]
mov r9,QWORD[16+rsi]
mov r10,QWORD[40+rsi]
lea r11,[56+rsi]
lea r12,[24+rsi]
mov QWORD[32+rsp],r10
mov QWORD[40+rsp],r11
mov QWORD[48+rsp],r12
mov QWORD[56+rsp],rcx
call QWORD[__imp_RtlVirtualUnwind]
mov eax,1
add rsp,64
popfq
pop r15
pop r14
pop r13
pop r12
pop rbp
pop rbx
pop rdi
pop rsi
DB 0F3h,0C3h ;repret
section .pdata rdata align=4
ALIGN 4
DD $L$SEH_begin_sha1_block_data_order wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order wrt ..imagebase
DD $L$SEH_begin_sha1_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order_ssse3 wrt ..imagebase
DD $L$SEH_begin_sha1_block_data_order_avx wrt ..imagebase
DD $L$SEH_end_sha1_block_data_order_avx wrt ..imagebase
DD $L$SEH_info_sha1_block_data_order_avx wrt ..imagebase
section .xdata rdata align=8
ALIGN 8
$L$SEH_info_sha1_block_data_order:
DB 9,0,0,0
DD se_handler wrt ..imagebase
$L$SEH_info_sha1_block_data_order_ssse3:
DB 9,0,0,0
DD ssse3_handler wrt ..imagebase
DD $L$prologue_ssse3 wrt ..imagebase,$L$epilogue_ssse3 wrt ..imagebase
$L$SEH_info_sha1_block_data_order_avx:
DB 9,0,0,0
DD ssse3_handler wrt ..imagebase
DD $L$prologue_avx wrt ..imagebase,$L$epilogue_avx wrt ..imagebase
| chpatrick/boring-crypto | cbits/win-x86_64/crypto/fipsmodule/sha1-x86_64.asm | Assembly | mit | 62,409 |
; lzo1y_s2.asm -- lzo1y_decompress_asm_safe
;
; This file is part of the LZO real-time data compression library.
;
; Copyright (C) 2008 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2007 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2006 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2005 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2004 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2003 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2002 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2001 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 2000 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 1999 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 1998 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 1997 Markus Franz Xaver Johannes Oberhumer
; Copyright (C) 1996 Markus Franz Xaver Johannes Oberhumer
; All Rights Reserved.
;
; The LZO library is free software; you can redistribute it and/or
; modify it under the terms of the GNU General Public License as
; published by the Free Software Foundation; either version 2 of
; the License, or (at your option) any later version.
;
; The LZO library is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with the LZO library; see the file COPYING.
; If not, write to the Free Software Foundation, Inc.,
; 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
;
; Markus F.X.J. Oberhumer
; <markus@oberhumer.com>
; http://www.oberhumer.com/opensource/lzo/
;
; /***** DO NOT EDIT - GENERATED AUTOMATICALLY *****/
include asminit.def
public _lzo1y_decompress_asm_safe
_lzo1y_decompress_asm_safe:
db 85,87,86,83,81,82,131,236,12,252,139,116,36,40,139,124
db 36,48,189,3,0,0,0,141,70,253,3,68,36,44,137,68
db 36,4,137,248,139,84,36,52,3,2,137,4,36,49,192,49
db 219,172,60,17,118,87,44,17,60,4,115,92,141,20,7,57
db 20,36,15,130,130,2,0,0,141,20,6,57,84,36,4,15
db 130,110,2,0,0,137,193,235,110,5,255,0,0,0,141,84
db 6,18,57,84,36,4,15,130,87,2,0,0,138,30,70,8
db 219,116,230,141,68,24,18,235,31,141,180,38,0,0,0,0
db 57,116,36,4,15,130,57,2,0,0,138,6,70,60,16,115
db 127,8,192,116,215,131,192,3,141,84,7,0,57,20,36,15
db 130,37,2,0,0,141,84,6,0,57,84,36,4,15,130,16
db 2,0,0,137,193,193,232,2,33,233,139,22,131,198,4,137
db 23,131,199,4,72,117,243,243,164,138,6,70,60,16,115,64
db 141,87,3,57,20,36,15,130,238,1,0,0,193,232,2,138
db 30,141,151,255,251,255,255,141,4,152,70,41,194,59,84,36
db 48,15,130,218,1,0,0,138,2,136,7,138,66,1,136,71
db 1,138,66,2,136,71,2,1,239,233,163,0,0,0,137,246
db 60,64,114,68,137,193,193,232,2,141,87,255,33,232,138,30
db 193,233,4,141,4,152,70,41,194,73,57,232,115,76,233,181
db 0,0,0,5,255,0,0,0,141,86,3,57,84,36,4,15
db 130,126,1,0,0,138,30,70,8,219,116,231,141,76,24,33
db 49,192,235,20,141,116,38,0,60,32,15,130,200,0,0,0
db 131,224,31,116,224,141,72,2,102,139,6,141,87,255,193,232
db 2,131,198,2,41,194,57,232,114,110,59,84,36,48,15,130
db 77,1,0,0,141,4,15,57,4,36,15,130,58,1,0,0
db 137,203,193,235,2,116,17,139,2,131,194,4,137,7,131,199
db 4,75,117,243,33,233,116,9,138,2,66,136,7,71,73,117
db 247,138,70,254,33,232,15,132,196,254,255,255,141,20,7,57
db 20,36,15,130,2,1,0,0,141,20,6,57,84,36,4,15
db 130,238,0,0,0,138,14,70,136,15,71,72,117,247,138,6
db 70,233,42,255,255,255,137,246,59,84,36,48,15,130,223,0
db 0,0,141,68,15,0,57,4,36,15,130,203,0,0,0,135
db 214,243,164,137,214,235,170,129,193,255,0,0,0,141,86,3
db 57,84,36,4,15,130,169,0,0,0,138,30,70,8,219,116
db 230,141,76,11,9,235,21,144,60,16,114,44,137,193,131,224
db 8,193,224,13,131,225,7,116,225,131,193,2,102,139,6,131
db 198,2,141,151,0,192,255,255,193,232,2,116,57,41,194,233
db 38,255,255,255,141,116,38,0,141,87,2,57,20,36,114,106
db 193,232,2,138,30,141,87,255,141,4,152,70,41,194,59,84
db 36,48,114,93,138,2,136,7,138,90,1,136,95,1,131,199
db 2,233,43,255,255,255,131,249,3,15,149,192,59,60,36,119
db 57,139,84,36,40,3,84,36,44,57,214,119,38,114,29,43
db 124,36,48,139,84,36,52,137,58,247,216,131,196,12,90,89
db 91,94,95,93,195,184,1,0,0,0,235,227,184,8,0,0
db 0,235,220,184,4,0,0,0,235,213,184,5,0,0,0,235
db 206,184,6,0,0,0,235,199,144,141,180,38,0,0,0,0
end
| JosefMeixner/opentoonz | thirdparty/lzo/2.03/asm/i386/src_masm/lzo1y_s2.asm | Assembly | bsd-3-clause | 4,388 |
; This file contains the code that is gonna be linked at the beginning of
; the kernel binary.
; It should contain core CPU initialisation routines such as entering
; long mode, then it should call 'kernel_init'.
extern kernel_init
global startup
global load_tss
section .bss
align 4096
early_pagemap:
resq (512 * (8 + 1 + 1 + 1))
; 8 page tables (16 M)
; 1 page directory
; 1 pdpt
; 1 pml4
section .data
align 16
GDT:
dw .GDTEnd - .GDTStart - 1 ; GDT size
dd .GDTStart ; GDT start
align 16
.GDTStart:
; Null descriptor (required)
.NullDescriptor:
dw 0x0000 ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 00000000b ; Access
db 00000000b ; Granularity
db 0x00 ; Base (high 8 bits)
; Protected mode
.KernelCode64:
dw 0x0000 ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 10011010b ; Access
db 00100000b ; Granularity
db 0x00 ; Base (high 8 bits)
.KernelData64:
dw 0x0000 ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 10010010b ; Access
db 00000000b ; Granularity
db 0x00 ; Base (high 8 bits)
; Protected mode
.UserCode64:
dw 0x0000 ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 11111010b ; Access
db 00100000b ; Granularity
db 0x00 ; Base (high 8 bits)
.UserData64:
dw 0x0000 ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 11110010b ; Access
db 00000000b ; Granularity
db 0x00 ; Base (high 8 bits)
; Unreal mode
.UnrealCode:
dw 0xFFFF ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 10011010b ; Access
db 10001111b ; Granularity
db 0x00 ; Base (high 8 bits)
.UnrealData:
dw 0xFFFF ; Limit
dw 0x0000 ; Base (low 16 bits)
db 0x00 ; Base (mid 8 bits)
db 10010010b ; Access
db 10001111b ; Granularity
db 0x00 ; Base (high 8 bits)
.TSS:
dw TSS_end - TSS_begin - 1
.TSSlow dw 0
.TSSmid db 0
.TSSflags1 db 10001001b
.TSSflags2 db 00000000b
.TSShigh db 0
dd 0 ; res
dd 0
.GDTEnd:
align 16
TSS_begin:
dd 0
dd 0xEFFFF0
times 24 dd 0
TSS_end:
section .startup
bits 32
nolongmode:
call clearscreen
mov esi, .msg
call textmodeprint
.halt:
cli
hlt
jmp .halt
.msg db "This CPU does not support long mode.", 0
textmodeprint:
pusha
mov edi, 0xb8000
.loop:
lodsb
test al, al
jz .out
stosb
inc edi
jmp .loop
.out:
popa
ret
clearscreen:
; clear screen
pusha
mov edi, 0xb8000
mov ecx, 80*25
mov al, ' '
mov ah, 0x17
rep stosw
popa
ret
load_tss:
bits 64
; addr in RDI
mov eax, edi
mov word [GDT.TSSlow], ax
mov eax, edi
and eax, 0xff0000
shr eax, 16
mov byte [GDT.TSSmid], al
mov eax, edi
and eax, 0xff000000
shr eax, 24
mov byte [GDT.TSShigh], al
mov byte [GDT.TSSflags1], 10001001b
mov byte [GDT.TSSflags2], 0
ret
bits 32
startup:
; check if long mode is present
mov eax, 0x80000001
xor edx, edx
cpuid
and edx, 1 << 29
test edx, edx
jz nolongmode
; load the GDT
lgdt [GDT]
; prepare the page directory and page table
; identity map the first 16 MiB of RAM
; build the 8 identity mapped page tables starting at 0x10000
mov edi, early_pagemap
mov eax, 0x03
mov ecx, 512 * 8
.loop:
stosd
add eax, 0x1000
mov dword [edi], 0
add edi, 4
loop .loop
; build the page directory
mov edx, edi ; save starting address of page directory
mov eax, (early_pagemap + 0x03)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x1003)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x2003)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x3003)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x4003)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x5003)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x6003)
stosd
xor eax, eax
stosd
mov eax, (early_pagemap + 0x7003)
stosd
xor eax, eax
stosd
add edi, (4096 - (8 * 8))
; build the pdpt
mov eax, edx
mov edx, edi
or eax, 0x03
stosd
xor eax, eax
stosd
add edi, (4096 - (1 * 8))
; build the pml4
mov eax, edx
mov edx, edi
or eax, 0x03
stosd
xor eax, eax
stosd
mov cr3, edx
mov eax, 10100000b
mov cr4, eax
mov ecx, 0xc0000080
rdmsr
or eax, 0x00000100
wrmsr
mov eax, cr0
or eax, 0x80000000
mov cr0, eax
jmp 0x08:.mode64
.mode64:
bits 64
mov ax, 0x10
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
mov eax, TSS_begin
mov word [GDT.TSSlow], ax
mov eax, TSS_begin
and eax, 0xff0000
shr eax, 16
mov byte [GDT.TSSmid], al
mov eax, TSS_begin
and eax, 0xff000000
shr eax, 24
mov byte [GDT.TSShigh], al
mov ax, 0x38 ; load the TSS
ltr ax
; enable SSE
mov rax, cr0
and al, 0xfb
or al, 0x02
mov cr0, rax
mov rax, cr4
or ax, 3 << 9
mov cr4, rax
call kernel_init
| echidnaOS/echidnaOS | kernel/startup/startup.asm | Assembly | bsd-2-clause | 5,293 |
; rand-table.asm - Bruce Clark, Avik Das
;
; Linear congruential pseudo-random number generator, by Bruce Clark,
; ported to the Ophis assembler. This file contains the PRNG that uses a
; generated multiplication lookup table to significantly speed up number
; generation at cost of space and initial set up time.
;
; All credit goes to Bruce Clark's article:
; http://www.6502.org/source/integers/random/random.html
;
; Usage of this functionality works as follows:
;
; 1. Reserve space for all the variables listed below.
; 2. Include this file.
; 3. Initialize all four bytes of the seed (see below).
; 4. Call RNDGENTBLS to initialize the multiplication lookup tables.
; 5. Call RANDOM8 to generate an eight-bit random number between 0
; (inclusive) and the accumulator value (exclusive).
;
; The following variables are expected to be available:
;
; * SEED0, SEED1, SEED2, SEED3
; - SEEDn is byte n of the seed
; - these should be initialized before the first call to RAND
; * TMP, TMP+1, TMP+2
; - three bytes
; - need not be initialized
; * MOD
; - need not be initialized
; * T0, T1, T2, T3
; - four lookup tables. Each will take up one page (256 bytes) of
; space, and it is recommended they start on a page boundary.
;
; It is recommended, for speed, that all these be stored in page zero,
; but this is not necessary for correct operation.
;
; TODO: Bruce Clark's page provides a number of other functions, in
; particular ones to generate 16-bit random numbers, and functions
; to generate random numbers more uniformly. These should be
; ported over as well.
; == START CODE ========================================================
;
; The code style has been retained, and any changes have been
; documented. Changes related to scoping, such as using Ophis's
; anonymous labels ("*") or the use of Ophis directives ".scope" and
; ".scend" have not been noted.
; Calculate SEED = 1664525 * SEED + 1
;
; Enter with:
;
; SEED0 = byte 0 of seed
; SEED1 = byte 1 of seed
; SEED2 = byte 2 of seed
; SEED3 = byte 3 of seed
;
; Returns:
;
; SEED0 = byte 0 of seed
; SEED1 = byte 1 of seed
; SEED2 = byte 2 of seed
; SEED3 = byte 3 of seed
;
; TMP is overwritten
;
; For maximum speed, locate each table on a page boundary
;
; Assuming that (a) SEED0 to SEED3 and TMP are located on page zero, and
; (b) all four tables start on a page boundary:
;
; Space: 58 bytes for the routine
; 1024 bytes for the tables
; Speed: JSR RAND takes 94 cycles
RAND: CLC ; compute lower 32 bits of:
LDX SEED0 ; 1664525 * ($100 * SEED1 + SEED0) + 1
LDY SEED1
LDA T0,X
ADC #1
STA SEED0
LDA T1,X
ADC T0,Y
STA SEED1
LDA T2,X
ADC T1,Y
STA TMP
LDA T3,X
ADC T2,Y
TAY ; keep byte 3 in Y for now (for speed)
CLC ; add lower 32 bits of:
LDX SEED2 ; 1664525 * ($10000 * SEED2)
LDA TMP
ADC T0,X
STA SEED2
TYA
ADC T1,X
CLC
LDX SEED3 ; add lower 32 bits of:
ADC T0,X ; 1664525 * ($1000000 * SEED3)
STA SEED3
RTS
; Generate T0, T1, T2 and T3 tables
;
; A different multiplier can be used by simply replacing the four bytes
; that are commented below
;
; NOTE: The original version was named GENTBLS. This has been renamed
; for namespacing reasons.
; NOTE: The original version mentions a modification that speeds up the
; routine at the cost of one byte. This modification has been
; applied.
RNDGENTBLS: LDX #0 ; 1664525 * 0 = 0
STX T0
STX T1
STX T2
STX T3
CLC
* LDA T0,X ; add 1664525 to previous entry to get next entry
ADC #$0D ; byte 0 of multiplier
STA T0+1,X
LDA T1,X
ADC #$66 ; byte 1 of multiplier
STA T1+1,X
LDA T2,X
ADC #$19 ; byte 2 of multiplier
STA T2+1,X
LDA T3,X
ADC #$00 ; byte 3 of multiplier
STA T3+1,X
INX ; note: carry will be clear here
CPX #$FF
BNE -
RTS
; Get the next SEED and obtain an 8-bit random number from it
;
; Requires the RAND subroutine
;
; Enter with:
;
; accumulator = modulus
;
; Exit with:
;
; accumulator = random number, 0 <= accumulator < modulus
;
; MOD, TMP, TMP+1, and TMP+2 are overwritten
;
; Note that TMP to TMP+2 are only used after RAND is called.
;
.scope
RANDOM8: STA MOD ; store modulus in MOD
JSR RAND ; get next seed
LDA #0 ; multiply SEED by MOD
STA TMP+2
STA TMP+1
STA TMP
SEC
ROR MOD ; shift out modulus, shifting in a 1
; (will loop 8 times)
_R8A: BCC _R8B ; branch if a zero was shifted out
CLC ; add SEED, keep upper 8 bits of product in
; accumulator
TAX
LDA TMP
ADC SEED0
STA TMP
LDA TMP+1
ADC SEED1
STA TMP+1
LDA TMP+2
ADC SEED2
STA TMP+2
TXA
ADC SEED3
_R8B: ROR ; shift product right
ROR TMP+2
ROR TMP+1
ROR TMP
LSR MOD ; loop until all 8 bits of MOD have been shifted out
BNE _R8A
RTS
.scend
| avik-das/nesdev | lib/rand-table.asm | Assembly | bsd-3-clause | 5,510 |
;/*
; FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
; All rights reserved
;
; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
;
; This file is part of the FreeRTOS distribution.
;
; FreeRTOS is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License (version 2) as published by the
; Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
;
; ***************************************************************************
; >>! NOTE: The modification to the GPL is included to allow you to !<<
; >>! distribute a combined work that includes FreeRTOS without being !<<
; >>! obliged to provide the source code for proprietary components !<<
; >>! outside of the FreeRTOS kernel. !<<
; ***************************************************************************
;
; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
; FOR A PARTICULAR PURPOSE. Full license text is available on the following
; link: http://www.freertos.org/a00114.html
;
; ***************************************************************************
; * *
; * FreeRTOS provides completely free yet professionally developed, *
; * robust, strictly quality controlled, supported, and cross *
; * platform software that is more than just the market leader, it *
; * is the industry's de facto standard. *
; * *
; * Help yourself get started quickly while simultaneously helping *
; * to support the FreeRTOS project by purchasing a FreeRTOS *
; * tutorial book, reference manual, or both: *
; * http://www.FreeRTOS.org/Documentation *
; * *
; ***************************************************************************
;
; http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
; the FAQ page "My application does not run, what could be wrong?". Have you
; defined configASSERT()?
;
; http://www.FreeRTOS.org/support - In return for receiving this top quality
; embedded software for free we request you assist our global community by
; participating in the support forum.
;
; http://www.FreeRTOS.org/training - Investing in training allows your team to
; be as productive as possible as early as possible. Now you can receive
; FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
; Ltd, and the world's leading authority on the world's leading RTOS.
;
; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
; including FreeRTOS+Trace - an indispensable productivity tool, a DOS
; compatible FAT file system, and our tiny thread aware UDP/IP stack.
;
; http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
; Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
;
; http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
; Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
; licenses offer ticketed support, indemnification and commercial middleware.
;
; http://www.SafeRTOS.com - High Integrity Systems also provide a safety
; engineered and independently SIL3 certified version for use in safety and
; mission critical applications that require provable dependability.
;
; 1 tab == 4 spaces!
;*/
.thumb
.ref pxCurrentTCB
.ref vTaskSwitchContext
.ref ulMaxSyscallInterruptPriority
.def xPortPendSVHandler
.def ulPortGetIPSR
.def vPortSVCHandler
.def vPortStartFirstTask
.def vPortEnableVFP
NVICOffsetConst: .word 0xE000ED08
CPACRConst: .word 0xE000ED88
pxCurrentTCBConst: .word pxCurrentTCB
ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
; -----------------------------------------------------------
.align 4
ulPortGetIPSR: .asmfunc
mrs r0, ipsr
bx r14
.endasmfunc
; -----------------------------------------------------------
.align 4
vPortSetInterruptMask: .asmfunc
push {r0}
ldr r0, ulMaxSyscallInterruptPriorityConst
msr basepri, r0
pop {r0}
bx r14
.endasmfunc
; -----------------------------------------------------------
.align 4
xPortPendSVHandler: .asmfunc
mrs r0, psp
isb
;/* Get the location of the current TCB. */
ldr r3, pxCurrentTCBConst
ldr r2, [r3]
;/* Is the task using the FPU context? If so, push high vfp registers. */
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
;/* Save the core registers. */
stmdb r0!, {r4-r11, r14}
;/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
stmdb sp!, {r3}
ldr r0, ulMaxSyscallInterruptPriorityConst
ldr r1, [r0]
msr basepri, r1
dsb
isb
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r3}
;/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r0, [r1]
;/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
;/* Is the task using the FPU context? If so, pop the high vfp registers
;too. */
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
bx r14
.endasmfunc
; -----------------------------------------------------------
.align 4
vPortSVCHandler: .asmfunc
;/* Get the location of the current TCB. */
ldr r3, pxCurrentTCBConst
ldr r1, [r3]
ldr r0, [r1]
;/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
bx r14
.endasmfunc
; -----------------------------------------------------------
.align 4
vPortStartFirstTask: .asmfunc
;/* Use the NVIC offset register to locate the stack. */
ldr r0, NVICOffsetConst
ldr r0, [r0]
ldr r0, [r0]
;/* Set the msp back to the start of the stack. */
msr msp, r0
;/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
svc #0
.endasmfunc
; -----------------------------------------------------------
.align 4
vPortEnableVFP: .asmfunc
;/* The FPU enable bits are in the CPACR. */
ldr.w r0, CPACRConst
ldr r1, [r0]
;/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
.endasmfunc
.end
; -----------------------------------------------------------
| kpeeyush/dusthawk | tiva/third_party/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm | Assembly | mit | 6,681 |
.586 ;Target processor. Use instructions for Pentium class machines
.MODEL FLAT, C ;Use the flat memory model. Use C calling conventions
.STACK ;Define a stack segment of 1KB (Not required for this example)
.DATA ;Create a near data segment. Local variables are declared after
;this directive (Not required for this example)
.CODE ;Indicates the start of a code segment.
main PROC
push ebp
mov ebp,esp
mov edx, 80002418h
xor eax,eax
mov ecx,20h
SFT1:
shr edx,1
jnc LOOP1
inc eax
LOOP1:
loop SFT1
pop ebp
ret
main ENDP
END
| ShinoharaYuuyoru/Assembly-Language-Project | Test/Test/Test.asm | Assembly | mit | 653 |
; Single argument passed as a memory address stored in bx.
print_string:
pusha ; Save registers.
mov cx, [bx] ; Store the value saved at the memory
; address stored in bx in cx.
loop:
cmp cl, 0 ; Compare the low byte of cl to 0.
je end ; If it is zero, we have reached
; the end of our null terminated string.
; Jump to the end of this function.
mov al, cl ; Set up argument to print_char.
call print_char ; Call.
add bx, 1 ; Add one to the memory address stored in bx.
mov cx, [bx] ; Move the next char in the string into cx.
jmp loop ; Repeat.
end:
popa ; Restore registers.
ret ; Return.
print_char:
pusha ; Store all current register values on the stack.
; This way the caller can assume all registers
; will have the same values on return.
mov ah, 0x0e
int 0x10 ; Do the printing.
popa ; Restore all registers.
ret ; Pop the return address of the calling
; function from the stack and jump to it.
| timwilkens/smallos | print_string.asm | Assembly | apache-2.0 | 1,070 |
;===============================================================================
; Copyright 2015-2020 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;===============================================================================
;
;
; Purpose: Cryptography Primitive.
; Rijndael Inverse Cipher function
;
; Content:
; Encrypt_RIJ128_AES_NI()
;
;
%include "asmdefs.inc"
%include "ia_32e.inc"
%include "pcpvariant.inc"
%if (_AES_NI_ENABLING_ == _FEATURE_ON_) || (_AES_NI_ENABLING_ == _FEATURE_TICKTOCK_)
%if (_IPP32E >= _IPP32E_Y8)
%macro COPY_8U 4.nolist
%xdefine %%dst %1
%xdefine %%src %2
%xdefine %%limit %3
%xdefine %%tmp %4
xor rcx, rcx
%%next_byte:
mov %%tmp, byte [%%src+rcx]
mov byte [%%dst+rcx], %%tmp
add rcx, 1
cmp rcx, %%limit
jl %%next_byte
%endmacro
segment .text align=IPP_ALIGN_FACTOR
;***************************************************************
;* Purpose: RIJ128 OFB encryption
;*
;* void EncryptOFB_RIJ128_AES_NI(const Ipp32u* inpBlk,
;* Ipp32u* outBlk,
;* int nr,
;* const Ipp32u* pRKey,
;* int length,
;* int ofbBlks,
;* const Ipp8u* pIV)
;***************************************************************
;;
;; Lib = Y8
;;
;; Caller = ippsRijndael128DecryptCFB
;;
align IPP_ALIGN_FACTOR
IPPASM EncryptOFB_RIJ128_AES_NI,PUBLIC
%assign LOCAL_FRAME (1+1+4+4)*16
USES_GPR rsi,rdi,r12,r15
USES_XMM
COMP_ABI 7
;; rdi: pInpBlk: DWORD, ; input blocks address
;; rsi: pOutBlk: DWORD, ; output blocks address
;; rdx: nr: DWORD, ; number of rounds
;; rcx pKey: DWORD ; key material address
;; r8d cfbBlks: DWORD ; length of stream in bytes
;; r9d cfbSize: DWORD ; cfb blk size
;; [rsp+ARG_7] pIV BYTE ; pointer to the IV
%xdefine SC (4)
%assign BLKS_PER_LOOP (4)
%xdefine tmpInp [rsp]
%xdefine tmpOut [rsp+16*1]
%xdefine locDst [rsp+16*2]
%xdefine locSrc [rsp+16*6]
mov rax, [rsp+ARG_7] ; IV address
movdqu xmm0, oword [rax] ; get IV
movdqa oword [rsp+0*16], xmm0 ; into the stack
movsxd r8, r8d ; length of stream
movsxd r9, r9d ; cfb blk size
mov r15, rcx ; save key material address
; get actual address of key material: pRKeys += (nr-9) * SC
lea rax,[rdx*4]
lea rax, [r15+rax*4-9*(SC)*4] ; AES-128 round keys
;;
;; processing
;;
lea r10, [r9*BLKS_PER_LOOP] ; 4 cfb block
align IPP_ALIGN_FACTOR
.blks_loop:
cmp r8, r10
cmovl r10, r8
COPY_8U {rsp+6*16}, rdi, r10, r11b ; move 1-4 input blocks to stack
mov r12, r10 ; copy length to be processed
xor r11, r11 ; index
align IPP_ALIGN_FACTOR
.single_blk:
pxor xmm0, oword [r15] ; whitening
cmp rdx,12 ; switch according to number of rounds
jl .key_128_s
jz .key_192_s
; do encryption
.key_256_s:
aesenc xmm0, oword [rax-4*4*SC]
aesenc xmm0, oword [rax-3*4*SC]
.key_192_s:
aesenc xmm0, oword [rax-2*4*SC]
aesenc xmm0, oword [rax-1*4*SC]
.key_128_s:
aesenc xmm0, oword [rax+0*4*SC]
aesenc xmm0, oword [rax+1*4*SC]
aesenc xmm0, oword [rax+2*4*SC]
aesenc xmm0, oword [rax+3*4*SC]
aesenc xmm0, oword [rax+4*4*SC]
aesenc xmm0, oword [rax+5*4*SC]
aesenc xmm0, oword [rax+6*4*SC]
aesenc xmm0, oword [rax+7*4*SC]
aesenc xmm0, oword [rax+8*4*SC]
aesenclast xmm0, oword [rax+9*4*SC]
movdqa oword [rsp+1*16], xmm0 ; save chipher output
movdqu xmm1, oword [rsp+6*16+r11] ; get src blocks from the stack
pxor xmm1, xmm0 ; xor src
movdqu oword [rsp+2*16+r11],xmm1 ;and store into the stack
movdqu xmm0, oword [rsp+r9] ; update chiper input (IV)
movdqa oword [rsp], xmm0
add r11, r9 ; advance index
sub r12, r9 ; decrease lenth
jg .single_blk
COPY_8U rsi, {rsp+2*16}, r10, r11b ; move 1-4 blocks to output
add rdi, r10
add rsi, r10
sub r8, r10
jg .blks_loop
mov rax, [rsp+ARG_7] ; IV address
movdqa xmm0, oword [rsp] ; update IV before return
movdqu oword [rax], xmm0
REST_XMM
REST_GPR
ret
ENDFUNC EncryptOFB_RIJ128_AES_NI
align IPP_ALIGN_FACTOR
IPPASM EncryptOFB128_RIJ128_AES_NI,PUBLIC
%assign LOCAL_FRAME 0
USES_GPR rsi,rdi
USES_XMM
COMP_ABI 6
;; rdi: pInpBlk: DWORD, ; input blocks address
;; rsi: pOutBlk: DWORD, ; output blocks address
;; rdx: nr: DWORD, ; number of rounds
;; rcx pKey: DWORD ; key material address
;; r8d cfbBlks: DWORD ; length of stream in bytes
;; r9 pIV: BYTE ; pointer to the IV
%xdefine SC (4)
%assign BLKS_PER_LOOP (4)
movdqu xmm0, oword [r9] ; get IV
movsxd r8, r8d ; length of stream
; get actual address of key material: pRKeys += (nr-9) * SC
lea rax,[rdx*4]
lea rax, [rcx+rax*4-9*(SC)*4] ; AES-128 round keys
;;
;; processing
;;
.blks_loop:
pxor xmm0, oword [rcx] ; whitening
movdqu xmm1, oword [rdi] ; input blocks
cmp rdx,12 ; switch according to number of rounds
jl .key_128_s
jz .key_192_s
; do encryption
.key_256_s:
aesenc xmm0, oword [rax-4*4*SC]
aesenc xmm0, oword [rax-3*4*SC]
.key_192_s:
aesenc xmm0, oword [rax-2*4*SC]
aesenc xmm0, oword [rax-1*4*SC]
.key_128_s:
aesenc xmm0, oword [rax+0*4*SC]
aesenc xmm0, oword [rax+1*4*SC]
aesenc xmm0, oword [rax+2*4*SC]
aesenc xmm0, oword [rax+3*4*SC]
aesenc xmm0, oword [rax+4*4*SC]
aesenc xmm0, oword [rax+5*4*SC]
aesenc xmm0, oword [rax+6*4*SC]
aesenc xmm0, oword [rax+7*4*SC]
aesenc xmm0, oword [rax+8*4*SC]
aesenclast xmm0, oword [rax+9*4*SC]
pxor xmm1, xmm0 ; xor src
movdqu oword [rsi],xmm1 ;and store into the dst
add rdi, 16
add rsi, 16
sub r8, 16
jg .blks_loop
movdqu oword [r9], xmm0 ; update IV before return
REST_XMM
REST_GPR
ret
ENDFUNC EncryptOFB128_RIJ128_AES_NI
%endif
%endif ;; _AES_NI_ENABLING_
| Intel-EPID-SDK/epid-sdk | ext/ipp-crypto/sources/ippcp/asm_intel64/pcprij128encryptofbe9as.asm | Assembly | apache-2.0 | 7,373 |
; when only single DEVICE directive is used in whole source, the DEVICE becomes "global"
; do device-only things before declaring actual DEVICE
ORG 0x8000
binStart:
BLOCK 8, 8 ; 8x value 8
binEnd:
SAVEBIN "single_device.bin", 0x8000, binEnd-binStart
; set ZX48 as global device
DEVICE ZXSPECTRUM48
| z00m128/sjasmplus | tests/devices/single_device.asm | Assembly | bsd-3-clause | 337 |
BITS 64
default rel
%include "x86-helpers.asm"
nasm_util_assert_boilerplate
thunk_boilerplate
; depedent series of adds
define_bench rs_dep_add
xor eax, eax
.top:
times 128 add rax, rax
dec rdi
jnz .top
ret
; dependent series of muls, takes 3 per cycle
define_bench rs_dep_imul
xor eax, eax
.top:
times 128 imul rax, rax
dec rdi
jnz .top
ret
; 4 chains of indepedent adds
define_bench rs_dep_add4
xor eax, eax
.top:
%rep 128
add rax, rax
add rcx, rcx
add rdx, rdx
add r8 , r8
%endrep
dec rdi
jnz .top
ret
; split stores, should fill the SB since split stores take 2 cycles to commit
define_bench rs_split_stores
push rbp
mov rbp, rsp
and rsp, -64 ; align to 64-byte boundary
sub rsp, 128 ; we have a 128 byte byte buffer above rsp, aligned to 64 bytes
.top:
times 128 mov qword [rsp + 60], 0
dec rdi
jnz .top
mov rsp, rbp
pop rbp
ret
define_bench rs_dep_fsqrt
fldz
.top:
times 128 fsqrt
dec rdi
jnz .top
fstp st0
ret
; the following tests interleave fsqrt (latency 14) with varying numbers of nops
; in a 1:N ratio (N the number of nops per fqrt instruction.
; The idea is with a low nop:fsqrt ratio, the RS will be the limit, since the RS
; will fill with nops before exhausting another resource. With more nops, the ROB
; will be exhausted. Generally, if the RS has size R and the ROB size O, we expect
; the crossover point to be when N == O / R - 1;
;
; %1 number of filler ops
; %2 long latency op
; %3 name (suffix)
; %4 filler op asm
%macro define_rs_op_op 4-*
%xdefine ratio %1
define_bench rs_fsqrt_%3%1
push rbp
mov rbp, rsp
and rsp, -64 ; align to 64-byte boundary
sub rsp, 128 ; we have a 128 byte byte buffer above rsp, aligned to 64 bytes
fldz
vzeroupper
.top:
%rep 32
%2
%rep ratio
%rep (%0 - 3)
%4
%rotate 1
%endrep
%rotate 3
%endrep
%endrep
dec rdi
jnz .top
fstp st0
mov rsp, rbp
pop rbp
vzeroupper
ret
%endmacro
%assign i 0
%rep 20
define_rs_op_op i, fsqrt, nop , nop
define_rs_op_op i, fsqrt, add , {add eax, 1}
define_rs_op_op i, fsqrt, xorzero , {xor eax, eax}
define_rs_op_op i, fsqrt, load , {mov eax, [rsp]}
define_rs_op_op i, fsqrt, store , {mov [rsp], eax}
define_rs_op_op i, fsqrt, paddb , {paddb xmm0, xmm1}
define_rs_op_op i, fsqrt, vpaddb , {vpaddb xmm0, xmm1, xmm2}
define_rs_op_op i, fsqrt, add_padd, {vpaddb xmm0, xmm1, xmm2}, {add eax, 1} ; mixed scalar and vector adds
define_rs_op_op i, fsqrt, load_dep, {mov eax, [rsp]}, {add eax, 0}, {add eax, 0}, {add eax, 0}
%assign i (i + 1)
%endrep
%macro define_rs_load_op 3-*
%xdefine ratio %1
; like the fsqrt bench, but with 5-cycle loads as the limiting instruction
define_bench rs_load_%2%1
push rbp
mov rbp, rsp
and rsp, -64 ; align to 64-byte boundary
sub rsp, 128 ; we have a 128 byte byte buffer above rsp, aligned to 64 bytes
xor eax, eax
xor ecx, ecx
xor edx, edx
mov QWORD [rsp], 0
vzeroupper
.top:
%rep 32
mov rax, [rax + rsp]
%rep ratio
%rep (%0 - 2)
%3
%rotate 1
%endrep
%rotate 2
%endrep
%endrep
dec rdi
jnz .top
mov rsp, rbp
pop rbp
vzeroupper
ret
%endmacro
%assign i 0
%rep 20
define_rs_load_op i, nop , nop
define_rs_load_op i, add , {add edx, eax}, {add r8d, eax}, {add r9d, eax}
%assign i (i + 1)
%endrep
; here we test how many dependent loads can enter the RS at once
;
%macro define_rs_loadchain 2
%xdefine ratio %1
; like the fsqrt bench, but with 5-cycle loads as the limiting instruction
define_bench rs_loadchain%2
push rbp
mov rbp, rsp
and rsp, -64 ; align to 64-byte boundary
sub rsp, 128 ; we have a 128 byte byte buffer above rsp, aligned to 64 bytes
mov QWORD [rsp], 0
xor eax, eax
xor ecx, ecx
mov rdx, rsp
.top:
%rep 32
%rep %1
;imul rax, rax, 1
%endrep
%rep %2
;jc udd
;add eax, 0
;mov ecx, [rax + rdx]
;movsx rcx, eax
;lea rcx, [rax + rdx]
;cdq
;imul rax, rax, 1
popcnt rax, rax
;times 4 nop
%endrep
lfence
;mov rax, 0
%endrep
dec rdi
jnz .top
mov rsp, rbp
pop rbp
vzeroupper
ret
%endmacro
%assign i 0
%rep 120
define_rs_loadchain 20,i
%assign i (i + 1)
%endrep
; test store buffer capacity
; %1 number of vsqrtss latency builders
; %2 number of dependent store instructions
%macro define_rs_storebuf 2
; the basic idea is that we issue a bunch of dependent vsqrtss
; then N indepedent stores
; then a dependency breaking op vxorps so that the next sqrt chian
; is indepedent
; when N is equal to size of the store buffer + 1, allocation will
; stall and the sqrt chains won't be able to run in parallel and there
; will be a big jump (~43 cycles on SKL) in the iteration time
define_bench rs_storebuf%2
sub rsp, 8
vxorps xmm0, xmm0, xmm0
.top:
%rep 32
%rep %1
vsqrtss xmm0, xmm0, xmm0
%endrep
movq rax, xmm0
%rep %2
mov DWORD [rsp], 0
%endrep
vxorps xmm0, xmm0, xmm0
%endrep
dec rdi
jnz .top
add rsp, 8
ret
%endmacro
%assign i 0
%rep 80
define_rs_storebuf 10,i
%assign i (i + 1)
%endrep
mov ebx, [rsp]
mov [rsp - 0x8], ebx
| travisdowns/uarch-bench | x86-resource-stalls.asm | Assembly | mit | 5,251 |
ARCH_ARM equ 0
ARCH_MIPS equ 0
ARCH_X86 equ 0
ARCH_X86_64 equ 1
ARCH_PPC32 equ 0
ARCH_PPC64 equ 0
HAVE_EDSP equ 0
HAVE_MEDIA equ 0
HAVE_NEON equ 0
HAVE_NEON_ASM equ 0
HAVE_MIPS32 equ 0
HAVE_DSPR2 equ 0
HAVE_MIPS64 equ 0
HAVE_MMX equ 1
HAVE_SSE equ 1
HAVE_SSE2 equ 1
HAVE_SSE3 equ 1
HAVE_SSSE3 equ 1
HAVE_SSE4_1 equ 1
HAVE_AVX equ 1
HAVE_AVX2 equ 1
HAVE_ALTIVEC equ 0
HAVE_VPX_PORTS equ 1
HAVE_STDINT_H equ 1
HAVE_ALT_TREE_LAYOUT equ 0
HAVE_PTHREAD_H equ 1
HAVE_SYS_MMAN_H equ 1
HAVE_UNISTD_H equ 1
CONFIG_DEPENDENCY_TRACKING equ 1
CONFIG_EXTERNAL_BUILD equ 0
CONFIG_INSTALL_DOCS equ 0
CONFIG_INSTALL_BINS equ 1
CONFIG_INSTALL_LIBS equ 1
CONFIG_INSTALL_SRCS equ 0
CONFIG_USE_X86INC equ 1
CONFIG_DEBUG equ 0
CONFIG_GPROF equ 0
CONFIG_GCOV equ 0
CONFIG_RVCT equ 0
CONFIG_GCC equ 1
CONFIG_MSVS equ 0
CONFIG_PIC equ 0
CONFIG_BIG_ENDIAN equ 0
CONFIG_CODEC_SRCS equ 0
CONFIG_DEBUG_LIBS equ 0
CONFIG_FAST_UNALIGNED equ 1
CONFIG_MEM_MANAGER equ 0
CONFIG_MEM_TRACKER equ 0
CONFIG_MEM_CHECKS equ 0
CONFIG_DEQUANT_TOKENS equ 0
CONFIG_DC_RECON equ 0
CONFIG_RUNTIME_CPU_DETECT equ 1
CONFIG_POSTPROC equ 1
CONFIG_VP9_POSTPROC equ 0
CONFIG_MULTITHREAD equ 1
CONFIG_INTERNAL_STATS equ 0
CONFIG_VP8_ENCODER equ 1
CONFIG_VP8_DECODER equ 1
CONFIG_VP9_ENCODER equ 1
CONFIG_VP9_DECODER equ 1
CONFIG_VP8 equ 1
CONFIG_VP9 equ 1
CONFIG_ENCODERS equ 1
CONFIG_DECODERS equ 1
CONFIG_STATIC_MSVCRT equ 0
CONFIG_SPATIAL_RESAMPLING equ 1
CONFIG_REALTIME_ONLY equ 0
CONFIG_ONTHEFLY_BITPACKING equ 0
CONFIG_ERROR_CONCEALMENT equ 0
CONFIG_SHARED equ 0
CONFIG_STATIC equ 1
CONFIG_SMALL equ 0
CONFIG_POSTPROC_VISUALIZER equ 0
CONFIG_OS_SUPPORT equ 1
CONFIG_UNIT_TESTS equ 0
CONFIG_WEBM_IO equ 1
CONFIG_LIBYUV equ 1
CONFIG_DECODE_PERF_TESTS equ 0
CONFIG_ENCODE_PERF_TESTS equ 0
CONFIG_MULTI_RES_ENCODING equ 0
CONFIG_TEMPORAL_DENOISING equ 1
CONFIG_VP9_TEMPORAL_DENOISING equ 0
CONFIG_COEFFICIENT_RANGE_CHECKING equ 0
CONFIG_VP9_HIGHBITDEPTH equ 0
CONFIG_EXPERIMENTAL equ 0
CONFIG_SIZE_LIMIT equ 0
CONFIG_SPATIAL_SVC equ 0
CONFIG_FP_MB_STATS equ 0
CONFIG_EMULATE_HARDWARE equ 0
| mrcdk/linc_libvpx | lib/build/vpx_config.asm | Assembly | mit | 2,041 |
INCLUDE "hardware.inc"
INCLUDE "header.inc"
;--------------------------------------------------------------------------
SECTION "Main",HOME
;------------------------------------
ClearSprites:
push hl
ld b,144
call wait_ly
xor a,a
ld b,$A0
ld hl,$FE00
.loop:
ld [hl+],a
dec b
jr nz,.loop
pop hl
ret
PrepareSprites: ; d = number of sprites in test line
ld b,144
call wait_ly
ld hl,$FE00
.loop:
ld a,d
and a,a
ret z
ld a,48+16
ld [hl+],a
ld a,50
ld [hl+],a
ld a,0
ld [hl+],a
ld [hl+],a
dec d
jr .loop
;--------------------------------------------------------------------------
;- Main() -
;--------------------------------------------------------------------------
Main:
; -------------------------------------------------------
ld a,$0A
ld [$0000],a ; enable ram
ld hl,$A000
ld a,LCDCF_ON|LCDCF_OBJON
ld [rLCDC],a
; -------------------------------------------------------
PERFORM_TEST : MACRO
di
push hl
ld bc,$007F
ld hl,\1
ld de,$FF80
call memcopy
ld b,45
call wait_ly
ld a,50
ld [rLYC],a
ld a,STATF_LYC
ld [rSTAT],a
ld a,IEF_LCDC
ld [rIE],a
xor a,a
ld [rIF],a
pop hl
ei
halt
ENDM
call ClearSprites
ld d,0
.next_spr_number:
push de
push hl
call PrepareSprites
pop hl
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$82
ld [rNR14],a
PERFORM_TEST LCD_INT_HANDLER_0
PERFORM_TEST LCD_INT_HANDLER_1
PERFORM_TEST LCD_INT_HANDLER_2
PERFORM_TEST LCD_INT_HANDLER_3
PERFORM_TEST LCD_INT_HANDLER_4
PERFORM_TEST LCD_INT_HANDLER_5
PERFORM_TEST LCD_INT_HANDLER_6
PERFORM_TEST LCD_INT_HANDLER_7
PERFORM_TEST LCD_INT_HANDLER_8
PERFORM_TEST LCD_INT_HANDLER_9
PERFORM_TEST LCD_INT_HANDLER_10
PERFORM_TEST LCD_INT_HANDLER_11
PERFORM_TEST LCD_INT_HANDLER_12
PERFORM_TEST LCD_INT_HANDLER_13
PERFORM_TEST LCD_INT_HANDLER_14
PERFORM_TEST LCD_INT_HANDLER_15
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$83
ld [rNR14],a
PERFORM_TEST LCD_INT_HANDLER_16
PERFORM_TEST LCD_INT_HANDLER_17
PERFORM_TEST LCD_INT_HANDLER_18
PERFORM_TEST LCD_INT_HANDLER_19
PERFORM_TEST LCD_INT_HANDLER_20
PERFORM_TEST LCD_INT_HANDLER_21
PERFORM_TEST LCD_INT_HANDLER_22
PERFORM_TEST LCD_INT_HANDLER_23
PERFORM_TEST LCD_INT_HANDLER_24
PERFORM_TEST LCD_INT_HANDLER_25
PERFORM_TEST LCD_INT_HANDLER_26
PERFORM_TEST LCD_INT_HANDLER_27
PERFORM_TEST LCD_INT_HANDLER_28
PERFORM_TEST LCD_INT_HANDLER_29
PERFORM_TEST LCD_INT_HANDLER_30
PERFORM_TEST LCD_INT_HANDLER_31
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$82
ld [rNR14],a
pop de
inc d
ld a,16
cp a,d
jp nz,.next_spr_number
; --------------------------------
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$87
ld [rNR14],a
push hl
ld [hl],$12
inc hl
ld [hl],$34
inc hl
ld [hl],$56
inc hl
ld [hl],$78
pop hl
ld a,$00
ld [$0000],a ; disable ram
.endloop:
halt
jr .endloop
; --------------------------------------------------------------
SECTION "functions",ROMX,BANK[1]
LCD_INT_HANDLER_MACRO : MACRO
REPT \1
nop
ENDR
ld a,[$FE00]
ld [hl+],a
ret
ENDM
LCD_INT_HANDLER_0: LCD_INT_HANDLER_MACRO 0
LCD_INT_HANDLER_1: LCD_INT_HANDLER_MACRO 1
LCD_INT_HANDLER_2: LCD_INT_HANDLER_MACRO 2
LCD_INT_HANDLER_3: LCD_INT_HANDLER_MACRO 3
LCD_INT_HANDLER_4: LCD_INT_HANDLER_MACRO 4
LCD_INT_HANDLER_5: LCD_INT_HANDLER_MACRO 5
LCD_INT_HANDLER_6: LCD_INT_HANDLER_MACRO 6
LCD_INT_HANDLER_7: LCD_INT_HANDLER_MACRO 7
LCD_INT_HANDLER_8: LCD_INT_HANDLER_MACRO 8
LCD_INT_HANDLER_9: LCD_INT_HANDLER_MACRO 9
LCD_INT_HANDLER_10: LCD_INT_HANDLER_MACRO 10
LCD_INT_HANDLER_11: LCD_INT_HANDLER_MACRO 11
LCD_INT_HANDLER_12: LCD_INT_HANDLER_MACRO 12
LCD_INT_HANDLER_13: LCD_INT_HANDLER_MACRO 13
LCD_INT_HANDLER_14: LCD_INT_HANDLER_MACRO 14
LCD_INT_HANDLER_15: LCD_INT_HANDLER_MACRO 15
LCD_INT_HANDLER_16: LCD_INT_HANDLER_MACRO 16
LCD_INT_HANDLER_17: LCD_INT_HANDLER_MACRO 17
LCD_INT_HANDLER_18: LCD_INT_HANDLER_MACRO 18
LCD_INT_HANDLER_19: LCD_INT_HANDLER_MACRO 19
LCD_INT_HANDLER_20: LCD_INT_HANDLER_MACRO 20
LCD_INT_HANDLER_21: LCD_INT_HANDLER_MACRO 21
LCD_INT_HANDLER_22: LCD_INT_HANDLER_MACRO 22
LCD_INT_HANDLER_23: LCD_INT_HANDLER_MACRO 23
LCD_INT_HANDLER_24: LCD_INT_HANDLER_MACRO 24
LCD_INT_HANDLER_25: LCD_INT_HANDLER_MACRO 25
LCD_INT_HANDLER_26: LCD_INT_HANDLER_MACRO 26
LCD_INT_HANDLER_27: LCD_INT_HANDLER_MACRO 27
LCD_INT_HANDLER_28: LCD_INT_HANDLER_MACRO 28
LCD_INT_HANDLER_29: LCD_INT_HANDLER_MACRO 29
LCD_INT_HANDLER_30: LCD_INT_HANDLER_MACRO 30
LCD_INT_HANDLER_31: LCD_INT_HANDLER_MACRO 31
; --------------------------------------------------------------
| AntonioND/gbc-hw-tests | lcd/mode2/mode2_oam_timing_spr_en_dmg_mode/main.asm | Assembly | mit | 5,024 |
;; Licensed to the .NET Foundation under one or more agreements.
;; The .NET Foundation licenses this file to you under the MIT license.
;; See the LICENSE file in the project root for more information.
include asmmacros.inc
;; Allocate non-array, non-finalizable object. If the allocation doesn't fit into the current thread's
;; allocation context then automatically fallback to the slow allocation path.
;; RCX == EEType
LEAF_ENTRY RhpNewFast, _TEXT
;; rdx = GetThread(), TRASHES rax
INLINE_GETTHREAD rdx, rax
;;
;; rcx contains EEType pointer
;;
mov r8d, [rcx + OFFSETOF__EEType__m_uBaseSize]
;;
;; eax: base size
;; rcx: EEType pointer
;; rdx: Thread pointer
;;
mov rax, [rdx + OFFSETOF__Thread__m_alloc_context__alloc_ptr]
add r8, rax
cmp r8, [rdx + OFFSETOF__Thread__m_alloc_context__alloc_limit]
ja RhpNewFast_RarePath
;; set the new alloc pointer
mov [rdx + OFFSETOF__Thread__m_alloc_context__alloc_ptr], r8
;; set the new object's EEType pointer
mov [rax], rcx
ret
RhpNewFast_RarePath:
xor edx, edx
jmp RhpNewObject
LEAF_END RhpNewFast, _TEXT
;; Allocate non-array object with finalizer
;; RCX == EEType
LEAF_ENTRY RhpNewFinalizable, _TEXT
mov edx, GC_ALLOC_FINALIZE
jmp RhpNewObject
LEAF_END RhpNewFinalizable, _TEXT
;; Allocate non-array object
;; RCX == EEType
;; EDX == alloc flags
NESTED_ENTRY RhpNewObject, _TEXT
PUSH_COOP_PINVOKE_FRAME r9
END_PROLOGUE
; R9: transition frame
;; Preserve the EEType in RSI
mov rsi, rcx
mov r8d, [rsi + OFFSETOF__EEType__m_uBaseSize] ; cbSize
;; Call the rest of the allocation helper.
;; void* RhpGcAlloc(EEType *pEEType, UInt32 uFlags, UIntNative cbSize, void * pTransitionFrame)
call RhpGcAlloc
;; Set the new object's EEType pointer on success.
test rax, rax
jz NewOutOfMemory
mov [rax + OFFSETOF__Object__m_pEEType], rsi
;; If the object is bigger than RH_LARGE_OBJECT_SIZE, we must publish it to the BGC
mov edx, [rsi + OFFSETOF__EEType__m_uBaseSize]
cmp rdx, RH_LARGE_OBJECT_SIZE
jb New_SkipPublish
mov rcx, rax ;; rcx: object
;; rdx: already contains object size
call RhpPublishObject ;; rax: this function returns the object that was passed-in
New_SkipPublish:
POP_COOP_PINVOKE_FRAME
ret
NewOutOfMemory:
;; This is the OOM failure path. We're going to tail-call to a managed helper that will throw
;; an out of memory exception that the caller of this allocator understands.
mov rcx, rsi ; EEType pointer
xor edx, edx ; Indicate that we should throw OOM.
POP_COOP_PINVOKE_FRAME
jmp RhExceptionHandling_FailedAllocation
NESTED_END RhpNewObject, _TEXT
;; Allocate a string.
;; RCX == EEType
;; EDX == character/element count
LEAF_ENTRY RhNewString, _TEXT
; we want to limit the element count to the non-negative 32-bit int range
cmp rdx, 07fffffffh
ja StringSizeOverflow
; Compute overall allocation size (align(base size + (element size * elements), 8)).
lea rax, [(rdx * STRING_COMPONENT_SIZE) + (STRING_BASE_SIZE + 7)]
and rax, -8
; rax == string size
; rcx == EEType
; rdx == element count
INLINE_GETTHREAD r10, r8
mov r8, rax
add rax, [r10 + OFFSETOF__Thread__m_alloc_context__alloc_ptr]
jc RhpNewArrayRare
; rax == new alloc ptr
; rcx == EEType
; rdx == element count
; r8 == array size
; r10 == thread
cmp rax, [r10 + OFFSETOF__Thread__m_alloc_context__alloc_limit]
ja RhpNewArrayRare
mov [r10 + OFFSETOF__Thread__m_alloc_context__alloc_ptr], rax
; calc the new object pointer
sub rax, r8
mov [rax + OFFSETOF__Object__m_pEEType], rcx
mov [rax + OFFSETOF__String__m_Length], edx
ret
StringSizeOverflow:
; We get here if the size of the final string object can't be represented as an unsigned
; 32-bit value. We're going to tail-call to a managed helper that will throw
; an OOM exception that the caller of this allocator understands.
; rcx holds EEType pointer already
xor edx, edx ; Indicate that we should throw OOM.
jmp RhExceptionHandling_FailedAllocation
LEAF_END RhNewString, _TEXT
;; Allocate one dimensional, zero based array (SZARRAY).
;; RCX == EEType
;; EDX == element count
LEAF_ENTRY RhpNewArray, _TEXT
; we want to limit the element count to the non-negative 32-bit int range
cmp rdx, 07fffffffh
ja ArraySizeOverflow
; save element count
mov r8, rdx
; Compute overall allocation size (align(base size + (element size * elements), 8)).
movzx eax, word ptr [rcx + OFFSETOF__EEType__m_usComponentSize]
mul rdx
mov edx, [rcx + OFFSETOF__EEType__m_uBaseSize]
add rax, rdx
add rax, 7
and rax, -8
mov rdx, r8
; rax == array size
; rcx == EEType
; rdx == element count
INLINE_GETTHREAD r10, r8
mov r8, rax
add rax, [r10 + OFFSETOF__Thread__m_alloc_context__alloc_ptr]
jc RhpNewArrayRare
; rax == new alloc ptr
; rcx == EEType
; rdx == element count
; r8 == array size
; r10 == thread
cmp rax, [r10 + OFFSETOF__Thread__m_alloc_context__alloc_limit]
ja RhpNewArrayRare
mov [r10 + OFFSETOF__Thread__m_alloc_context__alloc_ptr], rax
; calc the new object pointer
sub rax, r8
mov [rax + OFFSETOF__Object__m_pEEType], rcx
mov [rax + OFFSETOF__Array__m_Length], edx
ret
ArraySizeOverflow:
; We get here if the size of the final array object can't be represented as an unsigned
; 32-bit value. We're going to tail-call to a managed helper that will throw
; an overflow exception that the caller of this allocator understands.
; rcx holds EEType pointer already
mov edx, 1 ; Indicate that we should throw OverflowException
jmp RhExceptionHandling_FailedAllocation
LEAF_END RhpNewArray, _TEXT
NESTED_ENTRY RhpNewArrayRare, _TEXT
; rcx == EEType
; rdx == element count
; r8 == array size
PUSH_COOP_PINVOKE_FRAME r9
END_PROLOGUE
; r9: transition frame
; Preserve the EEType in RSI
mov rsi, rcx
; Preserve the element count in RBX
mov rbx, rdx
; Preserve the size in RDI
mov rdi, r8
; passing EEType in rcx
xor rdx, rdx ; uFlags
; pasing size in r8
; pasing pTransitionFrame in r9
; Call the rest of the allocation helper.
; void* RhpGcAlloc(EEType *pEEType, UInt32 uFlags, UIntNative cbSize, void * pTransitionFrame)
call RhpGcAlloc
; Set the new object's EEType pointer and length on success.
test rax, rax
jz ArrayOutOfMemory
mov [rax + OFFSETOF__Object__m_pEEType], rsi
mov [rax + OFFSETOF__Array__m_Length], ebx
;; If the object is bigger than RH_LARGE_OBJECT_SIZE, we must publish it to the BGC
cmp rdi, RH_LARGE_OBJECT_SIZE
jb NewArray_SkipPublish
mov rcx, rax ;; rcx: object
mov rdx, rdi ;; rdx: object size
call RhpPublishObject ;; rax: this function returns the object that was passed-in
NewArray_SkipPublish:
POP_COOP_PINVOKE_FRAME
ret
ArrayOutOfMemory:
;; This is the OOM failure path. We're going to tail-call to a managed helper that will throw
;; an out of memory exception that the caller of this allocator understands.
mov rcx, rsi ; EEType pointer
xor edx, edx ; Indicate that we should throw OOM.
POP_COOP_PINVOKE_FRAME
jmp RhExceptionHandling_FailedAllocation
NESTED_END RhpNewArrayRare, _TEXT
END
| shrah/corert | src/Native/Runtime/amd64/AllocFast.asm | Assembly | mit | 8,940 |
;code by unic0rn/Asm Force
org 100h
segment .code
mov al,13h
int 10h
xor ax,ax
mov dx,03C8h
out dx,al
inc dx
pal: push ax
not al
and al,0Fh
pop ax
push ax
ror ax,2
je ps1
ror ax,1
ps1: out dx,al
out dx,al
je ps2
rol ax,1
ps2: out dx,al
pop ax
inc al
jne pal
les bp,[bx]
shl bp,1
mov fs,bp
mov bx,sm
stars: mov si,[bx]
l1: cmp byte [bp+si],cl
jne s11
mov di,si
shl di,4
add di,[bx]
rdtsc
xor eax,[bx+14]
push ax
cbw
mov [di],ax
pop ax
mov al,ah
cbw
mov [di+2],ax
mov dword [di+4],43800000h
bswap eax
xor ah,ah
inc ax
mov [di+8],ax
inc byte [bp+si]
add dword [bx+14],eax
s11: dec si
jne l1
l2: sub byte [fs:si],17
jnc s21
mov byte [fs:si],bh
s21: inc si
loop l2
inc dword [bx+4]
mov si,[bx]
l3: mov di,si
shl di,4
add di,[bx]
fild word [di+8]
fmul dword [bx-4]
fld dword [di+4]
fsubrp st1,st0
fst dword [di+4]
push bp
xor bp,bp
scalc: fild word [di+bp]
fimul word [bx]
fdiv st1
fild dword [bx+4]
fmul dword [bx-4]
jc sc1
fcos
jmp short sc2
sc1: fsin
sc2: fld1
faddp st1,st0
fimul word [bx+2]
faddp st1,st0
fistp word [time+bp+4]
inc bp
inc bp
cmc
jc scalc
pop bp
fistp word [bx+12]
mov di,[bx+10]
cmp di,cx
js s31
cmp di,200
jnc s31
imul di,320
mov dx,[bx+8]
add dx,byte 60
cmp dx,cx
js s31
cmp dx,320
jnc s31
add di,dx
xor dl,dl
sub dl,[bx+12]
or dl,0Fh
mov [fs:di],dl
jmp short s32
s31: mov [bp+si],cl
s32: dec si
jne l3
dec cx
mov di,16
rep fs movsb
in al,60h
dec al
jnz stars
ret
tm: dd 0.0028
sm: dw 768
hm: dw 100
time:
| unic0rn/asmforce | wsmz/stages/263.asm | Assembly | mit | 1,823 |
_ln: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "stat.h"
#include "user.h"
int
main(int argc, char *argv[])
{
0: 8d 4c 24 04 lea 0x4(%esp),%ecx
4: 83 e4 f0 and $0xfffffff0,%esp
7: ff 71 fc pushl -0x4(%ecx)
a: 55 push %ebp
b: 89 e5 mov %esp,%ebp
d: 53 push %ebx
e: 51 push %ecx
f: 89 cb mov %ecx,%ebx
if(argc != 3){
11: 83 3b 03 cmpl $0x3,(%ebx)
14: 74 17 je 2d <main+0x2d>
printf(2, "Usage: ln old new\n");
16: 83 ec 08 sub $0x8,%esp
19: 68 50 08 00 00 push $0x850
1e: 6a 02 push $0x2
20: e8 75 04 00 00 call 49a <printf>
25: 83 c4 10 add $0x10,%esp
exit();
28: e8 ce 02 00 00 call 2fb <exit>
}
if(link(argv[1], argv[2]) < 0)
2d: 8b 43 04 mov 0x4(%ebx),%eax
30: 83 c0 08 add $0x8,%eax
33: 8b 10 mov (%eax),%edx
35: 8b 43 04 mov 0x4(%ebx),%eax
38: 83 c0 04 add $0x4,%eax
3b: 8b 00 mov (%eax),%eax
3d: 83 ec 08 sub $0x8,%esp
40: 52 push %edx
41: 50 push %eax
42: e8 14 03 00 00 call 35b <link>
47: 83 c4 10 add $0x10,%esp
4a: 85 c0 test %eax,%eax
4c: 79 21 jns 6f <main+0x6f>
printf(2, "link %s %s: failed\n", argv[1], argv[2]);
4e: 8b 43 04 mov 0x4(%ebx),%eax
51: 83 c0 08 add $0x8,%eax
54: 8b 10 mov (%eax),%edx
56: 8b 43 04 mov 0x4(%ebx),%eax
59: 83 c0 04 add $0x4,%eax
5c: 8b 00 mov (%eax),%eax
5e: 52 push %edx
5f: 50 push %eax
60: 68 63 08 00 00 push $0x863
65: 6a 02 push $0x2
67: e8 2e 04 00 00 call 49a <printf>
6c: 83 c4 10 add $0x10,%esp
exit();
6f: e8 87 02 00 00 call 2fb <exit>
00000074 <stosb>:
"cc");
}
static inline void
stosb(void *addr, int data, int cnt)
{
74: 55 push %ebp
75: 89 e5 mov %esp,%ebp
77: 57 push %edi
78: 53 push %ebx
asm volatile("cld; rep stosb" :
79: 8b 4d 08 mov 0x8(%ebp),%ecx
7c: 8b 55 10 mov 0x10(%ebp),%edx
7f: 8b 45 0c mov 0xc(%ebp),%eax
82: 89 cb mov %ecx,%ebx
84: 89 df mov %ebx,%edi
86: 89 d1 mov %edx,%ecx
88: fc cld
89: f3 aa rep stos %al,%es:(%edi)
8b: 89 ca mov %ecx,%edx
8d: 89 fb mov %edi,%ebx
8f: 89 5d 08 mov %ebx,0x8(%ebp)
92: 89 55 10 mov %edx,0x10(%ebp)
"=D" (addr), "=c" (cnt) :
"0" (addr), "1" (cnt), "a" (data) :
"memory", "cc");
}
95: 90 nop
96: 5b pop %ebx
97: 5f pop %edi
98: 5d pop %ebp
99: c3 ret
0000009a <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, char *t)
{
9a: 55 push %ebp
9b: 89 e5 mov %esp,%ebp
9d: 83 ec 10 sub $0x10,%esp
char *os;
os = s;
a0: 8b 45 08 mov 0x8(%ebp),%eax
a3: 89 45 fc mov %eax,-0x4(%ebp)
while((*s++ = *t++) != 0)
a6: 90 nop
a7: 8b 45 08 mov 0x8(%ebp),%eax
aa: 8d 50 01 lea 0x1(%eax),%edx
ad: 89 55 08 mov %edx,0x8(%ebp)
b0: 8b 55 0c mov 0xc(%ebp),%edx
b3: 8d 4a 01 lea 0x1(%edx),%ecx
b6: 89 4d 0c mov %ecx,0xc(%ebp)
b9: 0f b6 12 movzbl (%edx),%edx
bc: 88 10 mov %dl,(%eax)
be: 0f b6 00 movzbl (%eax),%eax
c1: 84 c0 test %al,%al
c3: 75 e2 jne a7 <strcpy+0xd>
;
return os;
c5: 8b 45 fc mov -0x4(%ebp),%eax
}
c8: c9 leave
c9: c3 ret
000000ca <strcmp>:
int
strcmp(const char *p, const char *q)
{
ca: 55 push %ebp
cb: 89 e5 mov %esp,%ebp
while(*p && *p == *q)
cd: eb 08 jmp d7 <strcmp+0xd>
p++, q++;
cf: 83 45 08 01 addl $0x1,0x8(%ebp)
d3: 83 45 0c 01 addl $0x1,0xc(%ebp)
}
int
strcmp(const char *p, const char *q)
{
while(*p && *p == *q)
d7: 8b 45 08 mov 0x8(%ebp),%eax
da: 0f b6 00 movzbl (%eax),%eax
dd: 84 c0 test %al,%al
df: 74 10 je f1 <strcmp+0x27>
e1: 8b 45 08 mov 0x8(%ebp),%eax
e4: 0f b6 10 movzbl (%eax),%edx
e7: 8b 45 0c mov 0xc(%ebp),%eax
ea: 0f b6 00 movzbl (%eax),%eax
ed: 38 c2 cmp %al,%dl
ef: 74 de je cf <strcmp+0x5>
p++, q++;
return (uchar)*p - (uchar)*q;
f1: 8b 45 08 mov 0x8(%ebp),%eax
f4: 0f b6 00 movzbl (%eax),%eax
f7: 0f b6 d0 movzbl %al,%edx
fa: 8b 45 0c mov 0xc(%ebp),%eax
fd: 0f b6 00 movzbl (%eax),%eax
100: 0f b6 c0 movzbl %al,%eax
103: 29 c2 sub %eax,%edx
105: 89 d0 mov %edx,%eax
}
107: 5d pop %ebp
108: c3 ret
00000109 <strlen>:
uint
strlen(char *s)
{
109: 55 push %ebp
10a: 89 e5 mov %esp,%ebp
10c: 83 ec 10 sub $0x10,%esp
int n;
for(n = 0; s[n]; n++)
10f: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
116: eb 04 jmp 11c <strlen+0x13>
118: 83 45 fc 01 addl $0x1,-0x4(%ebp)
11c: 8b 55 fc mov -0x4(%ebp),%edx
11f: 8b 45 08 mov 0x8(%ebp),%eax
122: 01 d0 add %edx,%eax
124: 0f b6 00 movzbl (%eax),%eax
127: 84 c0 test %al,%al
129: 75 ed jne 118 <strlen+0xf>
;
return n;
12b: 8b 45 fc mov -0x4(%ebp),%eax
}
12e: c9 leave
12f: c3 ret
00000130 <memset>:
void*
memset(void *dst, int c, uint n)
{
130: 55 push %ebp
131: 89 e5 mov %esp,%ebp
stosb(dst, c, n);
133: 8b 45 10 mov 0x10(%ebp),%eax
136: 50 push %eax
137: ff 75 0c pushl 0xc(%ebp)
13a: ff 75 08 pushl 0x8(%ebp)
13d: e8 32 ff ff ff call 74 <stosb>
142: 83 c4 0c add $0xc,%esp
return dst;
145: 8b 45 08 mov 0x8(%ebp),%eax
}
148: c9 leave
149: c3 ret
0000014a <strchr>:
char*
strchr(const char *s, char c)
{
14a: 55 push %ebp
14b: 89 e5 mov %esp,%ebp
14d: 83 ec 04 sub $0x4,%esp
150: 8b 45 0c mov 0xc(%ebp),%eax
153: 88 45 fc mov %al,-0x4(%ebp)
for(; *s; s++)
156: eb 14 jmp 16c <strchr+0x22>
if(*s == c)
158: 8b 45 08 mov 0x8(%ebp),%eax
15b: 0f b6 00 movzbl (%eax),%eax
15e: 3a 45 fc cmp -0x4(%ebp),%al
161: 75 05 jne 168 <strchr+0x1e>
return (char*)s;
163: 8b 45 08 mov 0x8(%ebp),%eax
166: eb 13 jmp 17b <strchr+0x31>
}
char*
strchr(const char *s, char c)
{
for(; *s; s++)
168: 83 45 08 01 addl $0x1,0x8(%ebp)
16c: 8b 45 08 mov 0x8(%ebp),%eax
16f: 0f b6 00 movzbl (%eax),%eax
172: 84 c0 test %al,%al
174: 75 e2 jne 158 <strchr+0xe>
if(*s == c)
return (char*)s;
return 0;
176: b8 00 00 00 00 mov $0x0,%eax
}
17b: c9 leave
17c: c3 ret
0000017d <gets>:
char*
gets(char *buf, int max)
{
17d: 55 push %ebp
17e: 89 e5 mov %esp,%ebp
180: 83 ec 18 sub $0x18,%esp
int i, cc;
char c;
for(i=0; i+1 < max; ){
183: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
18a: eb 42 jmp 1ce <gets+0x51>
cc = read(0, &c, 1);
18c: 83 ec 04 sub $0x4,%esp
18f: 6a 01 push $0x1
191: 8d 45 ef lea -0x11(%ebp),%eax
194: 50 push %eax
195: 6a 00 push $0x0
197: e8 77 01 00 00 call 313 <read>
19c: 83 c4 10 add $0x10,%esp
19f: 89 45 f0 mov %eax,-0x10(%ebp)
if(cc < 1)
1a2: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
1a6: 7e 33 jle 1db <gets+0x5e>
break;
buf[i++] = c;
1a8: 8b 45 f4 mov -0xc(%ebp),%eax
1ab: 8d 50 01 lea 0x1(%eax),%edx
1ae: 89 55 f4 mov %edx,-0xc(%ebp)
1b1: 89 c2 mov %eax,%edx
1b3: 8b 45 08 mov 0x8(%ebp),%eax
1b6: 01 c2 add %eax,%edx
1b8: 0f b6 45 ef movzbl -0x11(%ebp),%eax
1bc: 88 02 mov %al,(%edx)
if(c == '\n' || c == '\r')
1be: 0f b6 45 ef movzbl -0x11(%ebp),%eax
1c2: 3c 0a cmp $0xa,%al
1c4: 74 16 je 1dc <gets+0x5f>
1c6: 0f b6 45 ef movzbl -0x11(%ebp),%eax
1ca: 3c 0d cmp $0xd,%al
1cc: 74 0e je 1dc <gets+0x5f>
gets(char *buf, int max)
{
int i, cc;
char c;
for(i=0; i+1 < max; ){
1ce: 8b 45 f4 mov -0xc(%ebp),%eax
1d1: 83 c0 01 add $0x1,%eax
1d4: 3b 45 0c cmp 0xc(%ebp),%eax
1d7: 7c b3 jl 18c <gets+0xf>
1d9: eb 01 jmp 1dc <gets+0x5f>
cc = read(0, &c, 1);
if(cc < 1)
break;
1db: 90 nop
buf[i++] = c;
if(c == '\n' || c == '\r')
break;
}
buf[i] = '\0';
1dc: 8b 55 f4 mov -0xc(%ebp),%edx
1df: 8b 45 08 mov 0x8(%ebp),%eax
1e2: 01 d0 add %edx,%eax
1e4: c6 00 00 movb $0x0,(%eax)
return buf;
1e7: 8b 45 08 mov 0x8(%ebp),%eax
}
1ea: c9 leave
1eb: c3 ret
000001ec <stat>:
int
stat(char *n, struct stat *st)
{
1ec: 55 push %ebp
1ed: 89 e5 mov %esp,%ebp
1ef: 83 ec 18 sub $0x18,%esp
int fd;
int r;
fd = open(n, O_RDONLY);
1f2: 83 ec 08 sub $0x8,%esp
1f5: 6a 00 push $0x0
1f7: ff 75 08 pushl 0x8(%ebp)
1fa: e8 3c 01 00 00 call 33b <open>
1ff: 83 c4 10 add $0x10,%esp
202: 89 45 f4 mov %eax,-0xc(%ebp)
if(fd < 0)
205: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
209: 79 07 jns 212 <stat+0x26>
return -1;
20b: b8 ff ff ff ff mov $0xffffffff,%eax
210: eb 25 jmp 237 <stat+0x4b>
r = fstat(fd, st);
212: 83 ec 08 sub $0x8,%esp
215: ff 75 0c pushl 0xc(%ebp)
218: ff 75 f4 pushl -0xc(%ebp)
21b: e8 33 01 00 00 call 353 <fstat>
220: 83 c4 10 add $0x10,%esp
223: 89 45 f0 mov %eax,-0x10(%ebp)
close(fd);
226: 83 ec 0c sub $0xc,%esp
229: ff 75 f4 pushl -0xc(%ebp)
22c: e8 f2 00 00 00 call 323 <close>
231: 83 c4 10 add $0x10,%esp
return r;
234: 8b 45 f0 mov -0x10(%ebp),%eax
}
237: c9 leave
238: c3 ret
00000239 <atoi>:
int
atoi(const char *s)
{
239: 55 push %ebp
23a: 89 e5 mov %esp,%ebp
23c: 83 ec 10 sub $0x10,%esp
int n;
n = 0;
23f: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
while('0' <= *s && *s <= '9')
246: eb 25 jmp 26d <atoi+0x34>
n = n*10 + *s++ - '0';
248: 8b 55 fc mov -0x4(%ebp),%edx
24b: 89 d0 mov %edx,%eax
24d: c1 e0 02 shl $0x2,%eax
250: 01 d0 add %edx,%eax
252: 01 c0 add %eax,%eax
254: 89 c1 mov %eax,%ecx
256: 8b 45 08 mov 0x8(%ebp),%eax
259: 8d 50 01 lea 0x1(%eax),%edx
25c: 89 55 08 mov %edx,0x8(%ebp)
25f: 0f b6 00 movzbl (%eax),%eax
262: 0f be c0 movsbl %al,%eax
265: 01 c8 add %ecx,%eax
267: 83 e8 30 sub $0x30,%eax
26a: 89 45 fc mov %eax,-0x4(%ebp)
atoi(const char *s)
{
int n;
n = 0;
while('0' <= *s && *s <= '9')
26d: 8b 45 08 mov 0x8(%ebp),%eax
270: 0f b6 00 movzbl (%eax),%eax
273: 3c 2f cmp $0x2f,%al
275: 7e 0a jle 281 <atoi+0x48>
277: 8b 45 08 mov 0x8(%ebp),%eax
27a: 0f b6 00 movzbl (%eax),%eax
27d: 3c 39 cmp $0x39,%al
27f: 7e c7 jle 248 <atoi+0xf>
n = n*10 + *s++ - '0';
return n;
281: 8b 45 fc mov -0x4(%ebp),%eax
}
284: c9 leave
285: c3 ret
00000286 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
286: 55 push %ebp
287: 89 e5 mov %esp,%ebp
289: 83 ec 10 sub $0x10,%esp
char *dst, *src;
dst = vdst;
28c: 8b 45 08 mov 0x8(%ebp),%eax
28f: 89 45 fc mov %eax,-0x4(%ebp)
src = vsrc;
292: 8b 45 0c mov 0xc(%ebp),%eax
295: 89 45 f8 mov %eax,-0x8(%ebp)
while(n-- > 0)
298: eb 17 jmp 2b1 <memmove+0x2b>
*dst++ = *src++;
29a: 8b 45 fc mov -0x4(%ebp),%eax
29d: 8d 50 01 lea 0x1(%eax),%edx
2a0: 89 55 fc mov %edx,-0x4(%ebp)
2a3: 8b 55 f8 mov -0x8(%ebp),%edx
2a6: 8d 4a 01 lea 0x1(%edx),%ecx
2a9: 89 4d f8 mov %ecx,-0x8(%ebp)
2ac: 0f b6 12 movzbl (%edx),%edx
2af: 88 10 mov %dl,(%eax)
{
char *dst, *src;
dst = vdst;
src = vsrc;
while(n-- > 0)
2b1: 8b 45 10 mov 0x10(%ebp),%eax
2b4: 8d 50 ff lea -0x1(%eax),%edx
2b7: 89 55 10 mov %edx,0x10(%ebp)
2ba: 85 c0 test %eax,%eax
2bc: 7f dc jg 29a <memmove+0x14>
*dst++ = *src++;
return vdst;
2be: 8b 45 08 mov 0x8(%ebp),%eax
}
2c1: c9 leave
2c2: c3 ret
000002c3 <restorer>:
2c3: 83 c4 0c add $0xc,%esp
2c6: 5a pop %edx
2c7: 59 pop %ecx
2c8: 58 pop %eax
2c9: c3 ret
000002ca <signal>:
"pop %ecx\n\t"
"pop %eax\n\t"
"ret\n\t");
int signal(int signum, void(*handler)(int))
{
2ca: 55 push %ebp
2cb: 89 e5 mov %esp,%ebp
2cd: 83 ec 08 sub $0x8,%esp
signal_restorer(restorer);
2d0: 83 ec 0c sub $0xc,%esp
2d3: 68 c3 02 00 00 push $0x2c3
2d8: e8 ce 00 00 00 call 3ab <signal_restorer>
2dd: 83 c4 10 add $0x10,%esp
return signal_register(signum, handler);
2e0: 83 ec 08 sub $0x8,%esp
2e3: ff 75 0c pushl 0xc(%ebp)
2e6: ff 75 08 pushl 0x8(%ebp)
2e9: e8 b5 00 00 00 call 3a3 <signal_register>
2ee: 83 c4 10 add $0x10,%esp
}
2f1: c9 leave
2f2: c3 ret
000002f3 <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
2f3: b8 01 00 00 00 mov $0x1,%eax
2f8: cd 40 int $0x40
2fa: c3 ret
000002fb <exit>:
SYSCALL(exit)
2fb: b8 02 00 00 00 mov $0x2,%eax
300: cd 40 int $0x40
302: c3 ret
00000303 <wait>:
SYSCALL(wait)
303: b8 03 00 00 00 mov $0x3,%eax
308: cd 40 int $0x40
30a: c3 ret
0000030b <pipe>:
SYSCALL(pipe)
30b: b8 04 00 00 00 mov $0x4,%eax
310: cd 40 int $0x40
312: c3 ret
00000313 <read>:
SYSCALL(read)
313: b8 05 00 00 00 mov $0x5,%eax
318: cd 40 int $0x40
31a: c3 ret
0000031b <write>:
SYSCALL(write)
31b: b8 10 00 00 00 mov $0x10,%eax
320: cd 40 int $0x40
322: c3 ret
00000323 <close>:
SYSCALL(close)
323: b8 15 00 00 00 mov $0x15,%eax
328: cd 40 int $0x40
32a: c3 ret
0000032b <kill>:
SYSCALL(kill)
32b: b8 06 00 00 00 mov $0x6,%eax
330: cd 40 int $0x40
332: c3 ret
00000333 <exec>:
SYSCALL(exec)
333: b8 07 00 00 00 mov $0x7,%eax
338: cd 40 int $0x40
33a: c3 ret
0000033b <open>:
SYSCALL(open)
33b: b8 0f 00 00 00 mov $0xf,%eax
340: cd 40 int $0x40
342: c3 ret
00000343 <mknod>:
SYSCALL(mknod)
343: b8 11 00 00 00 mov $0x11,%eax
348: cd 40 int $0x40
34a: c3 ret
0000034b <unlink>:
SYSCALL(unlink)
34b: b8 12 00 00 00 mov $0x12,%eax
350: cd 40 int $0x40
352: c3 ret
00000353 <fstat>:
SYSCALL(fstat)
353: b8 08 00 00 00 mov $0x8,%eax
358: cd 40 int $0x40
35a: c3 ret
0000035b <link>:
SYSCALL(link)
35b: b8 13 00 00 00 mov $0x13,%eax
360: cd 40 int $0x40
362: c3 ret
00000363 <mkdir>:
SYSCALL(mkdir)
363: b8 14 00 00 00 mov $0x14,%eax
368: cd 40 int $0x40
36a: c3 ret
0000036b <chdir>:
SYSCALL(chdir)
36b: b8 09 00 00 00 mov $0x9,%eax
370: cd 40 int $0x40
372: c3 ret
00000373 <dup>:
SYSCALL(dup)
373: b8 0a 00 00 00 mov $0xa,%eax
378: cd 40 int $0x40
37a: c3 ret
0000037b <getpid>:
SYSCALL(getpid)
37b: b8 0b 00 00 00 mov $0xb,%eax
380: cd 40 int $0x40
382: c3 ret
00000383 <sbrk>:
SYSCALL(sbrk)
383: b8 0c 00 00 00 mov $0xc,%eax
388: cd 40 int $0x40
38a: c3 ret
0000038b <sleep>:
SYSCALL(sleep)
38b: b8 0d 00 00 00 mov $0xd,%eax
390: cd 40 int $0x40
392: c3 ret
00000393 <uptime>:
SYSCALL(uptime)
393: b8 0e 00 00 00 mov $0xe,%eax
398: cd 40 int $0x40
39a: c3 ret
0000039b <halt>:
SYSCALL(halt)
39b: b8 16 00 00 00 mov $0x16,%eax
3a0: cd 40 int $0x40
3a2: c3 ret
000003a3 <signal_register>:
SYSCALL(signal_register)
3a3: b8 17 00 00 00 mov $0x17,%eax
3a8: cd 40 int $0x40
3aa: c3 ret
000003ab <signal_restorer>:
SYSCALL(signal_restorer)
3ab: b8 18 00 00 00 mov $0x18,%eax
3b0: cd 40 int $0x40
3b2: c3 ret
000003b3 <mprotect>:
SYSCALL(mprotect)
3b3: b8 19 00 00 00 mov $0x19,%eax
3b8: cd 40 int $0x40
3ba: c3 ret
000003bb <cowfork>:
SYSCALL(cowfork)
3bb: b8 1a 00 00 00 mov $0x1a,%eax
3c0: cd 40 int $0x40
3c2: c3 ret
000003c3 <putc>:
#include "stat.h"
#include "user.h"
static void
putc(int fd, char c)
{
3c3: 55 push %ebp
3c4: 89 e5 mov %esp,%ebp
3c6: 83 ec 18 sub $0x18,%esp
3c9: 8b 45 0c mov 0xc(%ebp),%eax
3cc: 88 45 f4 mov %al,-0xc(%ebp)
write(fd, &c, 1);
3cf: 83 ec 04 sub $0x4,%esp
3d2: 6a 01 push $0x1
3d4: 8d 45 f4 lea -0xc(%ebp),%eax
3d7: 50 push %eax
3d8: ff 75 08 pushl 0x8(%ebp)
3db: e8 3b ff ff ff call 31b <write>
3e0: 83 c4 10 add $0x10,%esp
}
3e3: 90 nop
3e4: c9 leave
3e5: c3 ret
000003e6 <printint>:
static void
printint(int fd, int xx, int base, int sgn)
{
3e6: 55 push %ebp
3e7: 89 e5 mov %esp,%ebp
3e9: 53 push %ebx
3ea: 83 ec 24 sub $0x24,%esp
static char digits[] = "0123456789ABCDEF";
char buf[16];
int i, neg;
uint x;
neg = 0;
3ed: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
if(sgn && xx < 0){
3f4: 83 7d 14 00 cmpl $0x0,0x14(%ebp)
3f8: 74 17 je 411 <printint+0x2b>
3fa: 83 7d 0c 00 cmpl $0x0,0xc(%ebp)
3fe: 79 11 jns 411 <printint+0x2b>
neg = 1;
400: c7 45 f0 01 00 00 00 movl $0x1,-0x10(%ebp)
x = -xx;
407: 8b 45 0c mov 0xc(%ebp),%eax
40a: f7 d8 neg %eax
40c: 89 45 ec mov %eax,-0x14(%ebp)
40f: eb 06 jmp 417 <printint+0x31>
} else {
x = xx;
411: 8b 45 0c mov 0xc(%ebp),%eax
414: 89 45 ec mov %eax,-0x14(%ebp)
}
i = 0;
417: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
do{
buf[i++] = digits[x % base];
41e: 8b 4d f4 mov -0xc(%ebp),%ecx
421: 8d 41 01 lea 0x1(%ecx),%eax
424: 89 45 f4 mov %eax,-0xc(%ebp)
427: 8b 5d 10 mov 0x10(%ebp),%ebx
42a: 8b 45 ec mov -0x14(%ebp),%eax
42d: ba 00 00 00 00 mov $0x0,%edx
432: f7 f3 div %ebx
434: 89 d0 mov %edx,%eax
436: 0f b6 80 ec 0a 00 00 movzbl 0xaec(%eax),%eax
43d: 88 44 0d dc mov %al,-0x24(%ebp,%ecx,1)
}while((x /= base) != 0);
441: 8b 5d 10 mov 0x10(%ebp),%ebx
444: 8b 45 ec mov -0x14(%ebp),%eax
447: ba 00 00 00 00 mov $0x0,%edx
44c: f7 f3 div %ebx
44e: 89 45 ec mov %eax,-0x14(%ebp)
451: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
455: 75 c7 jne 41e <printint+0x38>
if(neg)
457: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
45b: 74 2d je 48a <printint+0xa4>
buf[i++] = '-';
45d: 8b 45 f4 mov -0xc(%ebp),%eax
460: 8d 50 01 lea 0x1(%eax),%edx
463: 89 55 f4 mov %edx,-0xc(%ebp)
466: c6 44 05 dc 2d movb $0x2d,-0x24(%ebp,%eax,1)
while(--i >= 0)
46b: eb 1d jmp 48a <printint+0xa4>
putc(fd, buf[i]);
46d: 8d 55 dc lea -0x24(%ebp),%edx
470: 8b 45 f4 mov -0xc(%ebp),%eax
473: 01 d0 add %edx,%eax
475: 0f b6 00 movzbl (%eax),%eax
478: 0f be c0 movsbl %al,%eax
47b: 83 ec 08 sub $0x8,%esp
47e: 50 push %eax
47f: ff 75 08 pushl 0x8(%ebp)
482: e8 3c ff ff ff call 3c3 <putc>
487: 83 c4 10 add $0x10,%esp
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
48a: 83 6d f4 01 subl $0x1,-0xc(%ebp)
48e: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
492: 79 d9 jns 46d <printint+0x87>
putc(fd, buf[i]);
}
494: 90 nop
495: 8b 5d fc mov -0x4(%ebp),%ebx
498: c9 leave
499: c3 ret
0000049a <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
49a: 55 push %ebp
49b: 89 e5 mov %esp,%ebp
49d: 83 ec 28 sub $0x28,%esp
char *s;
int c, i, state;
uint *ap;
state = 0;
4a0: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
ap = (uint*)(void*)&fmt + 1;
4a7: 8d 45 0c lea 0xc(%ebp),%eax
4aa: 83 c0 04 add $0x4,%eax
4ad: 89 45 e8 mov %eax,-0x18(%ebp)
for(i = 0; fmt[i]; i++){
4b0: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
4b7: e9 59 01 00 00 jmp 615 <printf+0x17b>
c = fmt[i] & 0xff;
4bc: 8b 55 0c mov 0xc(%ebp),%edx
4bf: 8b 45 f0 mov -0x10(%ebp),%eax
4c2: 01 d0 add %edx,%eax
4c4: 0f b6 00 movzbl (%eax),%eax
4c7: 0f be c0 movsbl %al,%eax
4ca: 25 ff 00 00 00 and $0xff,%eax
4cf: 89 45 e4 mov %eax,-0x1c(%ebp)
if(state == 0){
4d2: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
4d6: 75 2c jne 504 <printf+0x6a>
if(c == '%'){
4d8: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
4dc: 75 0c jne 4ea <printf+0x50>
state = '%';
4de: c7 45 ec 25 00 00 00 movl $0x25,-0x14(%ebp)
4e5: e9 27 01 00 00 jmp 611 <printf+0x177>
} else {
putc(fd, c);
4ea: 8b 45 e4 mov -0x1c(%ebp),%eax
4ed: 0f be c0 movsbl %al,%eax
4f0: 83 ec 08 sub $0x8,%esp
4f3: 50 push %eax
4f4: ff 75 08 pushl 0x8(%ebp)
4f7: e8 c7 fe ff ff call 3c3 <putc>
4fc: 83 c4 10 add $0x10,%esp
4ff: e9 0d 01 00 00 jmp 611 <printf+0x177>
}
} else if(state == '%'){
504: 83 7d ec 25 cmpl $0x25,-0x14(%ebp)
508: 0f 85 03 01 00 00 jne 611 <printf+0x177>
if(c == 'd'){
50e: 83 7d e4 64 cmpl $0x64,-0x1c(%ebp)
512: 75 1e jne 532 <printf+0x98>
printint(fd, *ap, 10, 1);
514: 8b 45 e8 mov -0x18(%ebp),%eax
517: 8b 00 mov (%eax),%eax
519: 6a 01 push $0x1
51b: 6a 0a push $0xa
51d: 50 push %eax
51e: ff 75 08 pushl 0x8(%ebp)
521: e8 c0 fe ff ff call 3e6 <printint>
526: 83 c4 10 add $0x10,%esp
ap++;
529: 83 45 e8 04 addl $0x4,-0x18(%ebp)
52d: e9 d8 00 00 00 jmp 60a <printf+0x170>
} else if(c == 'x' || c == 'p'){
532: 83 7d e4 78 cmpl $0x78,-0x1c(%ebp)
536: 74 06 je 53e <printf+0xa4>
538: 83 7d e4 70 cmpl $0x70,-0x1c(%ebp)
53c: 75 1e jne 55c <printf+0xc2>
printint(fd, *ap, 16, 0);
53e: 8b 45 e8 mov -0x18(%ebp),%eax
541: 8b 00 mov (%eax),%eax
543: 6a 00 push $0x0
545: 6a 10 push $0x10
547: 50 push %eax
548: ff 75 08 pushl 0x8(%ebp)
54b: e8 96 fe ff ff call 3e6 <printint>
550: 83 c4 10 add $0x10,%esp
ap++;
553: 83 45 e8 04 addl $0x4,-0x18(%ebp)
557: e9 ae 00 00 00 jmp 60a <printf+0x170>
} else if(c == 's'){
55c: 83 7d e4 73 cmpl $0x73,-0x1c(%ebp)
560: 75 43 jne 5a5 <printf+0x10b>
s = (char*)*ap;
562: 8b 45 e8 mov -0x18(%ebp),%eax
565: 8b 00 mov (%eax),%eax
567: 89 45 f4 mov %eax,-0xc(%ebp)
ap++;
56a: 83 45 e8 04 addl $0x4,-0x18(%ebp)
if(s == 0)
56e: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
572: 75 25 jne 599 <printf+0xff>
s = "(null)";
574: c7 45 f4 77 08 00 00 movl $0x877,-0xc(%ebp)
while(*s != 0){
57b: eb 1c jmp 599 <printf+0xff>
putc(fd, *s);
57d: 8b 45 f4 mov -0xc(%ebp),%eax
580: 0f b6 00 movzbl (%eax),%eax
583: 0f be c0 movsbl %al,%eax
586: 83 ec 08 sub $0x8,%esp
589: 50 push %eax
58a: ff 75 08 pushl 0x8(%ebp)
58d: e8 31 fe ff ff call 3c3 <putc>
592: 83 c4 10 add $0x10,%esp
s++;
595: 83 45 f4 01 addl $0x1,-0xc(%ebp)
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
599: 8b 45 f4 mov -0xc(%ebp),%eax
59c: 0f b6 00 movzbl (%eax),%eax
59f: 84 c0 test %al,%al
5a1: 75 da jne 57d <printf+0xe3>
5a3: eb 65 jmp 60a <printf+0x170>
putc(fd, *s);
s++;
}
} else if(c == 'c'){
5a5: 83 7d e4 63 cmpl $0x63,-0x1c(%ebp)
5a9: 75 1d jne 5c8 <printf+0x12e>
putc(fd, *ap);
5ab: 8b 45 e8 mov -0x18(%ebp),%eax
5ae: 8b 00 mov (%eax),%eax
5b0: 0f be c0 movsbl %al,%eax
5b3: 83 ec 08 sub $0x8,%esp
5b6: 50 push %eax
5b7: ff 75 08 pushl 0x8(%ebp)
5ba: e8 04 fe ff ff call 3c3 <putc>
5bf: 83 c4 10 add $0x10,%esp
ap++;
5c2: 83 45 e8 04 addl $0x4,-0x18(%ebp)
5c6: eb 42 jmp 60a <printf+0x170>
} else if(c == '%'){
5c8: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
5cc: 75 17 jne 5e5 <printf+0x14b>
putc(fd, c);
5ce: 8b 45 e4 mov -0x1c(%ebp),%eax
5d1: 0f be c0 movsbl %al,%eax
5d4: 83 ec 08 sub $0x8,%esp
5d7: 50 push %eax
5d8: ff 75 08 pushl 0x8(%ebp)
5db: e8 e3 fd ff ff call 3c3 <putc>
5e0: 83 c4 10 add $0x10,%esp
5e3: eb 25 jmp 60a <printf+0x170>
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
5e5: 83 ec 08 sub $0x8,%esp
5e8: 6a 25 push $0x25
5ea: ff 75 08 pushl 0x8(%ebp)
5ed: e8 d1 fd ff ff call 3c3 <putc>
5f2: 83 c4 10 add $0x10,%esp
putc(fd, c);
5f5: 8b 45 e4 mov -0x1c(%ebp),%eax
5f8: 0f be c0 movsbl %al,%eax
5fb: 83 ec 08 sub $0x8,%esp
5fe: 50 push %eax
5ff: ff 75 08 pushl 0x8(%ebp)
602: e8 bc fd ff ff call 3c3 <putc>
607: 83 c4 10 add $0x10,%esp
}
state = 0;
60a: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
611: 83 45 f0 01 addl $0x1,-0x10(%ebp)
615: 8b 55 0c mov 0xc(%ebp),%edx
618: 8b 45 f0 mov -0x10(%ebp),%eax
61b: 01 d0 add %edx,%eax
61d: 0f b6 00 movzbl (%eax),%eax
620: 84 c0 test %al,%al
622: 0f 85 94 fe ff ff jne 4bc <printf+0x22>
putc(fd, c);
}
state = 0;
}
}
}
628: 90 nop
629: c9 leave
62a: c3 ret
0000062b <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
62b: 55 push %ebp
62c: 89 e5 mov %esp,%ebp
62e: 83 ec 10 sub $0x10,%esp
Header *bp, *p;
bp = (Header*)ap - 1;
631: 8b 45 08 mov 0x8(%ebp),%eax
634: 83 e8 08 sub $0x8,%eax
637: 89 45 f8 mov %eax,-0x8(%ebp)
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
63a: a1 08 0b 00 00 mov 0xb08,%eax
63f: 89 45 fc mov %eax,-0x4(%ebp)
642: eb 24 jmp 668 <free+0x3d>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
644: 8b 45 fc mov -0x4(%ebp),%eax
647: 8b 00 mov (%eax),%eax
649: 3b 45 fc cmp -0x4(%ebp),%eax
64c: 77 12 ja 660 <free+0x35>
64e: 8b 45 f8 mov -0x8(%ebp),%eax
651: 3b 45 fc cmp -0x4(%ebp),%eax
654: 77 24 ja 67a <free+0x4f>
656: 8b 45 fc mov -0x4(%ebp),%eax
659: 8b 00 mov (%eax),%eax
65b: 3b 45 f8 cmp -0x8(%ebp),%eax
65e: 77 1a ja 67a <free+0x4f>
free(void *ap)
{
Header *bp, *p;
bp = (Header*)ap - 1;
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
660: 8b 45 fc mov -0x4(%ebp),%eax
663: 8b 00 mov (%eax),%eax
665: 89 45 fc mov %eax,-0x4(%ebp)
668: 8b 45 f8 mov -0x8(%ebp),%eax
66b: 3b 45 fc cmp -0x4(%ebp),%eax
66e: 76 d4 jbe 644 <free+0x19>
670: 8b 45 fc mov -0x4(%ebp),%eax
673: 8b 00 mov (%eax),%eax
675: 3b 45 f8 cmp -0x8(%ebp),%eax
678: 76 ca jbe 644 <free+0x19>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
break;
if(bp + bp->s.size == p->s.ptr){
67a: 8b 45 f8 mov -0x8(%ebp),%eax
67d: 8b 40 04 mov 0x4(%eax),%eax
680: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
687: 8b 45 f8 mov -0x8(%ebp),%eax
68a: 01 c2 add %eax,%edx
68c: 8b 45 fc mov -0x4(%ebp),%eax
68f: 8b 00 mov (%eax),%eax
691: 39 c2 cmp %eax,%edx
693: 75 24 jne 6b9 <free+0x8e>
bp->s.size += p->s.ptr->s.size;
695: 8b 45 f8 mov -0x8(%ebp),%eax
698: 8b 50 04 mov 0x4(%eax),%edx
69b: 8b 45 fc mov -0x4(%ebp),%eax
69e: 8b 00 mov (%eax),%eax
6a0: 8b 40 04 mov 0x4(%eax),%eax
6a3: 01 c2 add %eax,%edx
6a5: 8b 45 f8 mov -0x8(%ebp),%eax
6a8: 89 50 04 mov %edx,0x4(%eax)
bp->s.ptr = p->s.ptr->s.ptr;
6ab: 8b 45 fc mov -0x4(%ebp),%eax
6ae: 8b 00 mov (%eax),%eax
6b0: 8b 10 mov (%eax),%edx
6b2: 8b 45 f8 mov -0x8(%ebp),%eax
6b5: 89 10 mov %edx,(%eax)
6b7: eb 0a jmp 6c3 <free+0x98>
} else
bp->s.ptr = p->s.ptr;
6b9: 8b 45 fc mov -0x4(%ebp),%eax
6bc: 8b 10 mov (%eax),%edx
6be: 8b 45 f8 mov -0x8(%ebp),%eax
6c1: 89 10 mov %edx,(%eax)
if(p + p->s.size == bp){
6c3: 8b 45 fc mov -0x4(%ebp),%eax
6c6: 8b 40 04 mov 0x4(%eax),%eax
6c9: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
6d0: 8b 45 fc mov -0x4(%ebp),%eax
6d3: 01 d0 add %edx,%eax
6d5: 3b 45 f8 cmp -0x8(%ebp),%eax
6d8: 75 20 jne 6fa <free+0xcf>
p->s.size += bp->s.size;
6da: 8b 45 fc mov -0x4(%ebp),%eax
6dd: 8b 50 04 mov 0x4(%eax),%edx
6e0: 8b 45 f8 mov -0x8(%ebp),%eax
6e3: 8b 40 04 mov 0x4(%eax),%eax
6e6: 01 c2 add %eax,%edx
6e8: 8b 45 fc mov -0x4(%ebp),%eax
6eb: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
6ee: 8b 45 f8 mov -0x8(%ebp),%eax
6f1: 8b 10 mov (%eax),%edx
6f3: 8b 45 fc mov -0x4(%ebp),%eax
6f6: 89 10 mov %edx,(%eax)
6f8: eb 08 jmp 702 <free+0xd7>
} else
p->s.ptr = bp;
6fa: 8b 45 fc mov -0x4(%ebp),%eax
6fd: 8b 55 f8 mov -0x8(%ebp),%edx
700: 89 10 mov %edx,(%eax)
freep = p;
702: 8b 45 fc mov -0x4(%ebp),%eax
705: a3 08 0b 00 00 mov %eax,0xb08
}
70a: 90 nop
70b: c9 leave
70c: c3 ret
0000070d <morecore>:
static Header*
morecore(uint nu)
{
70d: 55 push %ebp
70e: 89 e5 mov %esp,%ebp
710: 83 ec 18 sub $0x18,%esp
char *p;
Header *hp;
if(nu < 4096)
713: 81 7d 08 ff 0f 00 00 cmpl $0xfff,0x8(%ebp)
71a: 77 07 ja 723 <morecore+0x16>
nu = 4096;
71c: c7 45 08 00 10 00 00 movl $0x1000,0x8(%ebp)
p = sbrk(nu * sizeof(Header));
723: 8b 45 08 mov 0x8(%ebp),%eax
726: c1 e0 03 shl $0x3,%eax
729: 83 ec 0c sub $0xc,%esp
72c: 50 push %eax
72d: e8 51 fc ff ff call 383 <sbrk>
732: 83 c4 10 add $0x10,%esp
735: 89 45 f4 mov %eax,-0xc(%ebp)
if(p == (char*)-1)
738: 83 7d f4 ff cmpl $0xffffffff,-0xc(%ebp)
73c: 75 07 jne 745 <morecore+0x38>
return 0;
73e: b8 00 00 00 00 mov $0x0,%eax
743: eb 26 jmp 76b <morecore+0x5e>
hp = (Header*)p;
745: 8b 45 f4 mov -0xc(%ebp),%eax
748: 89 45 f0 mov %eax,-0x10(%ebp)
hp->s.size = nu;
74b: 8b 45 f0 mov -0x10(%ebp),%eax
74e: 8b 55 08 mov 0x8(%ebp),%edx
751: 89 50 04 mov %edx,0x4(%eax)
free((void*)(hp + 1));
754: 8b 45 f0 mov -0x10(%ebp),%eax
757: 83 c0 08 add $0x8,%eax
75a: 83 ec 0c sub $0xc,%esp
75d: 50 push %eax
75e: e8 c8 fe ff ff call 62b <free>
763: 83 c4 10 add $0x10,%esp
return freep;
766: a1 08 0b 00 00 mov 0xb08,%eax
}
76b: c9 leave
76c: c3 ret
0000076d <malloc>:
void*
malloc(uint nbytes)
{
76d: 55 push %ebp
76e: 89 e5 mov %esp,%ebp
770: 83 ec 18 sub $0x18,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
773: 8b 45 08 mov 0x8(%ebp),%eax
776: 83 c0 07 add $0x7,%eax
779: c1 e8 03 shr $0x3,%eax
77c: 83 c0 01 add $0x1,%eax
77f: 89 45 ec mov %eax,-0x14(%ebp)
if((prevp = freep) == 0){
782: a1 08 0b 00 00 mov 0xb08,%eax
787: 89 45 f0 mov %eax,-0x10(%ebp)
78a: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
78e: 75 23 jne 7b3 <malloc+0x46>
base.s.ptr = freep = prevp = &base;
790: c7 45 f0 00 0b 00 00 movl $0xb00,-0x10(%ebp)
797: 8b 45 f0 mov -0x10(%ebp),%eax
79a: a3 08 0b 00 00 mov %eax,0xb08
79f: a1 08 0b 00 00 mov 0xb08,%eax
7a4: a3 00 0b 00 00 mov %eax,0xb00
base.s.size = 0;
7a9: c7 05 04 0b 00 00 00 movl $0x0,0xb04
7b0: 00 00 00
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
7b3: 8b 45 f0 mov -0x10(%ebp),%eax
7b6: 8b 00 mov (%eax),%eax
7b8: 89 45 f4 mov %eax,-0xc(%ebp)
if(p->s.size >= nunits){
7bb: 8b 45 f4 mov -0xc(%ebp),%eax
7be: 8b 40 04 mov 0x4(%eax),%eax
7c1: 3b 45 ec cmp -0x14(%ebp),%eax
7c4: 72 4d jb 813 <malloc+0xa6>
if(p->s.size == nunits)
7c6: 8b 45 f4 mov -0xc(%ebp),%eax
7c9: 8b 40 04 mov 0x4(%eax),%eax
7cc: 3b 45 ec cmp -0x14(%ebp),%eax
7cf: 75 0c jne 7dd <malloc+0x70>
prevp->s.ptr = p->s.ptr;
7d1: 8b 45 f4 mov -0xc(%ebp),%eax
7d4: 8b 10 mov (%eax),%edx
7d6: 8b 45 f0 mov -0x10(%ebp),%eax
7d9: 89 10 mov %edx,(%eax)
7db: eb 26 jmp 803 <malloc+0x96>
else {
p->s.size -= nunits;
7dd: 8b 45 f4 mov -0xc(%ebp),%eax
7e0: 8b 40 04 mov 0x4(%eax),%eax
7e3: 2b 45 ec sub -0x14(%ebp),%eax
7e6: 89 c2 mov %eax,%edx
7e8: 8b 45 f4 mov -0xc(%ebp),%eax
7eb: 89 50 04 mov %edx,0x4(%eax)
p += p->s.size;
7ee: 8b 45 f4 mov -0xc(%ebp),%eax
7f1: 8b 40 04 mov 0x4(%eax),%eax
7f4: c1 e0 03 shl $0x3,%eax
7f7: 01 45 f4 add %eax,-0xc(%ebp)
p->s.size = nunits;
7fa: 8b 45 f4 mov -0xc(%ebp),%eax
7fd: 8b 55 ec mov -0x14(%ebp),%edx
800: 89 50 04 mov %edx,0x4(%eax)
}
freep = prevp;
803: 8b 45 f0 mov -0x10(%ebp),%eax
806: a3 08 0b 00 00 mov %eax,0xb08
return (void*)(p + 1);
80b: 8b 45 f4 mov -0xc(%ebp),%eax
80e: 83 c0 08 add $0x8,%eax
811: eb 3b jmp 84e <malloc+0xe1>
}
if(p == freep)
813: a1 08 0b 00 00 mov 0xb08,%eax
818: 39 45 f4 cmp %eax,-0xc(%ebp)
81b: 75 1e jne 83b <malloc+0xce>
if((p = morecore(nunits)) == 0)
81d: 83 ec 0c sub $0xc,%esp
820: ff 75 ec pushl -0x14(%ebp)
823: e8 e5 fe ff ff call 70d <morecore>
828: 83 c4 10 add $0x10,%esp
82b: 89 45 f4 mov %eax,-0xc(%ebp)
82e: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
832: 75 07 jne 83b <malloc+0xce>
return 0;
834: b8 00 00 00 00 mov $0x0,%eax
839: eb 13 jmp 84e <malloc+0xe1>
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
if((prevp = freep) == 0){
base.s.ptr = freep = prevp = &base;
base.s.size = 0;
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
83b: 8b 45 f4 mov -0xc(%ebp),%eax
83e: 89 45 f0 mov %eax,-0x10(%ebp)
841: 8b 45 f4 mov -0xc(%ebp),%eax
844: 8b 00 mov (%eax),%eax
846: 89 45 f4 mov %eax,-0xc(%ebp)
return (void*)(p + 1);
}
if(p == freep)
if((p = morecore(nunits)) == 0)
return 0;
}
849: e9 6d ff ff ff jmp 7bb <malloc+0x4e>
}
84e: c9 leave
84f: c3 ret
| CHRISTOPHERDIEHL/xv6-mprotect | ln.asm | Assembly | mit | 43,052 |
; ******************************************************************************************************************
;
; Simple H/W Test
;
; Echo keystrokes and beep on lower 3 bits of ASCII code. Basic hardware check.
;
; ******************************************************************************************************************
cpu sc/mp
org 0x0000
nop
cls: xpal p1 ; clear screen
ldi ' '
st @1(p1)
xpal p1
jnz cls
xpal p1 ; P1 will be $100
ldi 0x08 ; point P2 to the keyboard
xpah p2
nextKey:ldi 0x7F ; solid block cursor
st 0(p1)
waitKey:ld 0(p2) ; wait for key press
jp waitKey
ani 0x7F ; throw away bit 7
ccl
adi 0x20 ; will now be +ve if lower case
jp _Continue
ccl
adi 0xE0
_Continue:
scl
cai 0x20+0x20 ; unpick 0x20, sub 0x20 will be +ve if not ctrl
jp _SkipControl
ccl ; convert Ctrl+x to x
adi 0x40
xae
ldi '^' & 0x3F ; output control marker.
st @1(p1)
xae
_SkipControl:
ccl ; fix up subtract
adi 0x20
ani 0x3F ; 6 bit ASCII
st @1(p1) ; output it
ani 7 ; and set beep tone.
cas
_WaitRelease: ; wait for key release.
ld 0(p2)
jp nextKey
jmp _WaitRelease
| paulscottrobson/wallpaper-one | software/miscellany/hardware_test.asm | Assembly | mit | 1,378 |
; The CHK macro causes a checksum to be computed and deposited at the current location.
; The starting point of the checksum calculation is indicated as an argument.
;
; The checksum is calculated as the simple arithmetic sum of all bytes starting
; at the provided address up to but not including the address of the CHK macro instance.
; The least significant byte is all that is used.
;
; The macro requires the virtual DEVICE memory (checksum needs access to previously
; defined machine code bytes).
; CHK macro definition
MACRO .CHK address?
OPT push listoff
.SUM = 0 ; init values for checksumming
.ADR = address? : ASSERT address? < $ ; starting address must be below current
DUP $ - address? ; do simple sum of all bytes
.SUM = .SUM + {B .ADR}
.ADR = .ADR + 1
EDUP
OPT pop
DB low .SUM
ENDM
; similar as .CHK macro, but does use XOR to calculate checksum
MACRO .CHKXOR address?
OPT push listoff
.CSUM = 0 ; init values for checksumming
.ADR = address? : ASSERT address? < $ ; starting address must be below current
DUP $ - address? ; do simple sum of all bytes
.CSUM = .CSUM ^ {B .ADR}
.ADR = .ADR + 1
EDUP
OPT pop
DB .CSUM
ENDM
; Examples and verification (ZX Spectrum 48 virtual device is used for the test)
DEVICE ZXSPECTRUM48 : OUTPUT "sum_checksum.bin"
TEST1 DB 'A'
.CHK TEST1 ; expected 'A'
TEST2 DS 300, 'b'
DB 'B' - ((300*'b')&$FF) ; adjust checksum to become 'B'
.CHK TEST2 ; expected 'B'
TEST3 inc hl ; $23
inc h ; $24
.CHK TEST3 ; expected 'G' ($47)
TESTXOR
HEX 20 50 49 38 30 20
HEX 20 20 20 20 20 43 01 00
HEX 40 08 40 20 20 20 20 20
HEX 20 43 41
.CHKXOR TESTXOR ; expected $79
| z00m128/sjasmplus | tests/macro_examples/sum_checksum.asm | Assembly | bsd-3-clause | 1,989 |
;§ £®«®¢®ª ¯à¨«®¦¥¨ï
use32 ; âà á«ïâ®à, ¨á¯®«ì§ãî騩 32 à §àï¤ëå ª®¬ ¤ë
org 0x0 ; ¡ §®¢ë© ¤à¥á ª®¤ , ¢á¥£¤ 0x0
db 'MENUET01' ; ¨¤¥â¨ä¨ª â®à ¨á¯®«ï¥¬®£® ä ©« (8 ¡ ©â)
dd 0x1 ; ¢¥àá¨ï ä®à¬ â § £®«®¢ª ¨á¯®«ï¥¬®£® ä ©«
dd start ; ¤à¥á, ª®â®àë© á¨á⥬ ¯¥à¥¤ ñâ ã¯à ¢«¥¨¥
; ¯®á«¥ § £à㧪¨ ¯à¨«®¦¥¨ï ¢ ¯ ¬ïâì
dd i_end ; à §¬¥à ¯à¨«®¦¥¨ï
dd mem ; ¡ê¥¬ ¨á¯®«ì§ã¥¬®© ¯ ¬ïâ¨, ¤«ï á⥪ ®â¢¥¤¥¬ 0å100 ¡ ©â ¨ ¢ë஢¨¬ £à¨æã 4 ¡ ©â
dd mem ; à ᯮ«®¦¨¬ ¯®§¨æ¨î á⥪ ¢ ®¡« á⨠¯ ¬ïâ¨, áà §ã § ⥫®¬ ¯à®£à ¬¬ë. ¥àè¨ á⥪ ¢ ¤¨ ¯ §®¥ ¯ ¬ïâ¨, 㪠§ ®¬ ¢ëè¥
dd 0x0 ; 㪠§ ⥫ì áâபã á ¯ à ¬¥âà ¬¨.
dd cur_dir_path ; 㪠§ â¥«ì ¤à¥á, ªã¤ ¯®¬¥é ¥âáï áâப , ᮤ¥à¦ é ï ¯ãâì ¤® ¯à®£à ¬¬ë ¢ ¬®¬¥â § ¯ã᪠.
include '../../../../../macros.inc'
include '../../trunk/box_lib.mac'
include '../../load_lib.mac'
@use_library ;use load lib macros
start:
;universal load library/librarys
sys_load_library library_name, cur_dir_path, library_path, system_path, \
err_message_found_lib, head_f_l, myimport, err_message_import, head_f_i
;if return code =-1 then exit, else nornary work
cmp eax,-1
jz exit
mcall 40,0x27 ;ãáâ ®¢¨âì ¬ áªã ¤«ï ®¦¨¤ ¥¬ëå ᮡë⨩
push dword check1 ;¯®¤áçñâ ¤¨ë ⥪áâ ¤«ï Checkbox'®¢
call [init_checkbox]
push dword check2
call [init_checkbox]
red_win:
call draw_window ;¯¥à¢® ç «ì® ¥®¡å®¤¨¬® à¨á®¢ âì ®ª®
align 4
still: ;®á®¢®© ®¡à ¡®â稪
mcall 10 ;¦¨¤ âì ᮡëâ¨ï
dec eax
jz red_win
dec eax
jz key
dec eax
jz button
push dword edit1
call [edit_box_mouse]
push dword edit2
call [edit_box_mouse]
push dword check1
call [check_box_mouse]
push dword check2
call [check_box_mouse]
push dword Option_boxs
call [option_box_mouse]
push dword Option_boxs2
call [option_box_mouse]
jmp still ;¥á«¨ ¨ç¥£® ¨§ ¯¥à¥ç¨á«¥®£® ⮠ᮢ ¢ 横«
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
button:
mcall 17 ;¯®«ãç¨âì ¨¤¥â¨ä¨ª â®à ¦ ⮩ ª« ¢¨è¨
test ah,ah ;¥á«¨ ¢ ah 0, â® ¯¥à¥©â¨ ®¡à ¡®â稪 ᮡë⨩ still
jz still
exit:
mcall -1
key:
mcall 2 ;§ £à㧨¬ § 票¥ 2 ¢ ॣ¨áâ®à eax ¨ ¯®«ã稬 ª®¤ ¦ ⮩ ª« ¢¨è¨
push dword edit1
call [edit_box_key]
push dword edit2
call [edit_box_key]
jmp still
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
align 4
draw_window: ;à¨á®¢ ¨¥ ®ª ¯à¨«®¦¥¨ï
mcall 12,1
mcall 0,(50*65536+390),(30*65536+200),0x33AABBCC,0x805080DD,hed
push dword edit1
call [edit_box_draw]
push dword edit2
call [edit_box_draw]
push dword check1
call [check_box_draw]
push dword check2
call [check_box_draw]
push dword Option_boxs
call [option_box_draw]
push dword Option_boxs2
call [option_box_draw]
mcall 12,2
ret
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
;DATA ¤ ë¥
;ᥣ¤ ᮡ«î¤ âì ¯®á«¥¤®¢ ⥫ì®áâì ¢ ¨¬¥¨.
system_path db '/sys/lib/'
library_name db 'box_lib.obj',0
;
᫨ ¥áâì ¦¥« ¨¥ à §ê¥¤¨¨âì, ⮠㦮 ¨á¯®«ì§®¢ âì á«¥¤ãîé¨î ª®áâàãªæ¨î
;system_path db '/sys/lib/box_lib.obj',0
;... «î¡ ï ¯®á«¥¤®¢ ⥫ì®áâì ¤àã£¨å ª®¬ ¤ ¨ ®¯à¥¤¥«¥¨©.
;library_name db 'box_lib.obj',0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
err_message_found_lib db 'Sorry I cannot load library box_lib.obj',0
head_f_i:
head_f_l db 'System error',0
err_message_import db 'Error on load import library box_lib.obj',0
myimport:
edit_box_draw dd aEdit_box_draw
edit_box_key dd aEdit_box_key
edit_box_mouse dd aEdit_box_mouse
version_ed dd aVersion_ed
init_checkbox dd aInit_checkbox
check_box_draw dd aCheck_box_draw
check_box_mouse dd aCheck_box_mouse
version_ch dd aVersion_ch
option_box_draw dd aOption_box_draw
option_box_mouse dd aOption_box_mouse
version_op dd aVersion_op
dd 0
dd 0
aEdit_box_draw db 'edit_box',0
aEdit_box_key db 'edit_box_key',0
aEdit_box_mouse db 'edit_box_mouse',0
aVersion_ed db 'version_ed',0
aInit_checkbox db 'init_checkbox2',0
aCheck_box_draw db 'check_box_draw2',0
aCheck_box_mouse db 'check_box_mouse2',0
aVersion_ch db 'version_ch2',0
aOption_box_draw db 'option_box_draw',0
aOption_box_mouse db 'option_box_mouse',0
aVersion_op db 'version_op',0
check1 check_box2 (10 shl 16 + 12),(45 shl 16 + 12),5,0x80AABBCC,0,0,check_text1,ch_flag_en
check2 check_box2 (10 shl 16 + 12),(60 shl 16 + 12),6,0x80AABBCC,0,0,check_text2
edit1 edit_box 350,3,5,0xffffff,0x6f9480,0,0xAABBCC,0,308,hed,mouse_dd,ed_focus,hed_end-hed-1,hed_end-hed-1
edit2 edit_box 350,3,25,0xffffff,0x6a9480,0,0,0,99,ed_buffer,mouse_dd,ed_figure_only
op1 option_box option_group1,10,90,6,12,0xffffff,0,0,op_text.1,op_text.e1-op_text.1
op2 option_box option_group1,10,105,6,12,0xFFFFFF,0,0,op_text.2,op_text.e2-op_text.2
op3 option_box option_group1,10,120,6,12,0xffffff,0,0,op_text.3,op_text.e3-op_text.3
op11 option_box option_group2,120,90,6,12,0xffffff,0,0,op_text.1,op_text.e1-op_text.1
op12 option_box option_group2,120,105,6,12,0xffffff,0,0,op_text.2,op_text.e2-op_text.2
op13 option_box option_group2,120,120,6,12,0xffffff,0,0,op_text.3,op_text.e3-op_text.3
option_group1 dd op1 ;㪠§ ⥫¨, ®¨ ®â®¡à ¦ îâáï ¯® 㬮«ç ¨î, ª®£¤ ¢ë¢®¤¨âáï
option_group2 dd op12 ;¯à¨«®¦¥¨¥
Option_boxs dd op1,op2,op3,0
Option_boxs2 dd op11,op12,op13,0
hed db 'BOXs load from lib <Lrz> date 27.04.2009',0
hed_end:
rb 256
check_text1 db 'First checkbox',0
check_text2 db 'Second checkbox',0
op_text: ; ®¯à®¢®¦¤ î騩 ⥪áâ ¤«ï Optionbox'
.1 db 'Option_Box #1'
.e1:
.2 db 'Option_Box #2'
.e2:
.3 db 'Option_Box #3'
.e3:
ed_buffer rb 100
;-----------------------
;sc system_colors
mouse_dd rd 1
p_info process_information
cur_dir_path rb 4096
library_path rb 4096
i_end:
rb 1024
mem: | devlato/kolibrios-llvm | programs/develop/libraries/box_lib/asm/trunk/editbox_ex.asm | Assembly | mit | 6,288 |
format MS COFF
section '.text' code readable executable
public _memset
_memset:
push edi
mov edi, [esp+8]
mov al, [esp+12]
mov ecx, [esp+16]
rep stosb
pop edi
ret
| devlato/kolibrios-llvm | programs/other/graph/memset.asm | Assembly | mit | 170 |
;
; Copyright (c) 2016, Alliance for Open Media. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia.org/license/software. If the Alliance for Open
; Media Patent License 1.0 was not distributed with this source code in the
; PATENTS file, you can obtain it at www.aomedia.org/license/patent.
;
;
%define private_prefix av1
%include "third_party/x86inc/x86inc.asm"
SECTION .text
; int64_t av1_block_error(int16_t *coeff, int16_t *dqcoeff, intptr_t block_size,
; int64_t *ssz)
INIT_XMM sse2
cglobal block_error, 3, 3, 8, uqc, dqc, size, ssz
pxor m4, m4 ; sse accumulator
pxor m6, m6 ; ssz accumulator
pxor m5, m5 ; dedicated zero register
lea uqcq, [uqcq+sizeq*2]
lea dqcq, [dqcq+sizeq*2]
neg sizeq
.loop:
mova m2, [uqcq+sizeq*2]
mova m0, [dqcq+sizeq*2]
mova m3, [uqcq+sizeq*2+mmsize]
mova m1, [dqcq+sizeq*2+mmsize]
psubw m0, m2
psubw m1, m3
; individual errors are max. 15bit+sign, so squares are 30bit, and
; thus the sum of 2 should fit in a 31bit integer (+ unused sign bit)
pmaddwd m0, m0
pmaddwd m1, m1
pmaddwd m2, m2
pmaddwd m3, m3
; accumulate in 64bit
punpckldq m7, m0, m5
punpckhdq m0, m5
paddq m4, m7
punpckldq m7, m1, m5
paddq m4, m0
punpckhdq m1, m5
paddq m4, m7
punpckldq m7, m2, m5
paddq m4, m1
punpckhdq m2, m5
paddq m6, m7
punpckldq m7, m3, m5
paddq m6, m2
punpckhdq m3, m5
paddq m6, m7
paddq m6, m3
add sizeq, mmsize
jl .loop
; accumulate horizontally and store in return value
movhlps m5, m4
movhlps m7, m6
paddq m4, m5
paddq m6, m7
%if ARCH_X86_64
movq rax, m4
movq [sszq], m6
%else
mov eax, sszm
pshufd m5, m4, 0x1
movq [eax], m6
movd eax, m4
movd edx, m5
%endif
RET
; Compute the sum of squared difference between two int16_t vectors.
; int64_t av1_block_error_fp(int16_t *coeff, int16_t *dqcoeff,
; intptr_t block_size)
INIT_XMM sse2
cglobal block_error_fp, 3, 3, 6, uqc, dqc, size
pxor m4, m4 ; sse accumulator
pxor m5, m5 ; dedicated zero register
lea uqcq, [uqcq+sizeq*2]
lea dqcq, [dqcq+sizeq*2]
neg sizeq
.loop:
mova m2, [uqcq+sizeq*2]
mova m0, [dqcq+sizeq*2]
mova m3, [uqcq+sizeq*2+mmsize]
mova m1, [dqcq+sizeq*2+mmsize]
psubw m0, m2
psubw m1, m3
; individual errors are max. 15bit+sign, so squares are 30bit, and
; thus the sum of 2 should fit in a 31bit integer (+ unused sign bit)
pmaddwd m0, m0
pmaddwd m1, m1
; accumulate in 64bit
punpckldq m3, m0, m5
punpckhdq m0, m5
paddq m4, m3
punpckldq m3, m1, m5
paddq m4, m0
punpckhdq m1, m5
paddq m4, m3
paddq m4, m1
add sizeq, mmsize
jl .loop
; accumulate horizontally and store in return value
movhlps m5, m4
paddq m4, m5
%if ARCH_X86_64
movq rax, m4
%else
pshufd m5, m4, 0x1
movd eax, m4
movd edx, m5
%endif
RET
| luctrudeau/aom | av1/encoder/x86/error_sse2.asm | Assembly | bsd-2-clause | 3,336 |
; decimal up counter
.model small
.stack
.data
temp dw 00
.code
mov ax,@data
mov ds,ax
mov cx,0063d
mov ax,0000h
lp3:mov temp,ax
mov ah,0fh ; clearing the screen every time
int 10h
mov ah,00h
int 10h
mov ax,temp
call disp
call delay
mov ax,temp
inc ax
loop lp3
mov ah,4ch
int 21h
delay proc
push dx
mov dx,0000fh
up2:dec dx
jnz up2
pop dx
ret
disp proc
aam
add ax,3030h
mov bx,ax
mov dl,ah
mov ah,02h
int 21h
mov dl,bl
mov ah,02h
int 21h
ret
disp endp
end
| Amanskywalker/mp-lab | lab programs/10a.asm | Assembly | mit | 567 |
// JEQ, JNE, JGT, JLT, JGE, JLE
MACRO JEQ ( _rX_, _rY_, _dest_ )
CMP _rX_ _rY_
JZ { _dest_ }
ENDMACRO
MACRO JNE ( _rX_, _rY_, _dest_ )
CMP _rX_ _rY_
JNZ { _dest_ }
ENDMACRO
// stackoverflow.com/a/36909033
MACRO JGT ( _rX_, _rY_, _dest_ ) // JC
CMP _rX_ _rY_
JC { _dest_ }
ENDMACRO
MACRO JLT ( _rX_, _rY_, _dest_, _rTemp_ ) // NC & NZ
CMP _rX_ _rY_
MOV _rTemp_ rStatus
AND _rTemp_ r0 0b11 // check if both carry(1) and zero(0) bits are clear
JZ { _dest_ }
ENDMACRO
MACRO JGE ( _rX_, _rY_, _dest_ ) // C | Z
CMP _rX_ _rY_
JC { _dest_ }
JZ { _dest_ }
ENDMACRO
MACRO JLE ( _rX_, _rY_, _dest_ ) // NC
CMP _rX_ _rY_
JNC { _dest_ }
ENDMACRO
| JetStarBlues/Nand-2-Tetris | Assembler/macros/comparisons.asm | Assembly | mit | 701 |
;Los comentarios van antecedidos de un punto y coma
list p=18f4550 ;Modelo del microcontrolador
#include <p18f4550.inc> ;Librería de nombres de los registros
;Zona de declaración de los bits de configuración del microcontrolador
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT oscillator (XT))
CONFIG PWRT = ON ; Power-up Timer Enable bit (PWRT enabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
org 0x0000 ;Vector de RESET
goto init_conf
org 0x0008 ;Vector de interrupcion
org 0x0020 ;Zona de programa de usuario
init_conf:
bcf TRISD, 0 ;Hacer que el puerto RD0 sea una salida
bsf TRISB, 0 ;Hacer que el puerto RB0 sea una entrada
loop: btfss PORTB, 0 ;Leer y preguntar si RB0 es uno
goto falso ;Cuando se obtiene un falso, salta a etiqueta falso
bcf LATD, 0 ;Cuando se obtiene un verdadero, manda cero a RD0
goto loop ;Salta a etiqueta loop
falso: bsf LATD, 0 ;Manda uno a RD0
goto loop ;Salta a etiqueta loop
end ;Fin del programa
| tocache/picomones | UPC Microcontroladores 2020-1/Semana 01/20201-Prueba NOT.X/maincode.asm | Assembly | cc0-1.0 | 1,968 |
dc.w word_18AFC-Map_Invincibility
dc.w word_18AFE-Map_Invincibility
dc.w word_18B06-Map_Invincibility
dc.w word_18B0E-Map_Invincibility
dc.w word_18B16-Map_Invincibility
dc.w word_18B1E-Map_Invincibility
dc.w word_18B26-Map_Invincibility
dc.w word_18B2E-Map_Invincibility
dc.w word_18B36-Map_Invincibility
word_18AFC: dc.w 0 ; DATA XREF: ROM:00018AEAo
word_18AFE: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 0, 0, 0, $FF, $FC
word_18B06: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 0, 0, 1, $FF, $FC
word_18B0E: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 1, 0, 2, $FF, $FC
word_18B16: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 1, 0, 4, $FF, $FC
word_18B1E: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 1, 0, 6, $FF, $FC
word_18B26: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 5, 0, 8, $FF, $F8
word_18B2E: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F8, 5, 0, $C, $FF, $F8
word_18B36: dc.w 1 ; DATA XREF: ROM:00018AEAo
dc.b $F0, $F, 0, $10, $FF, $F0
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/General/Sprites/Shields/Map - Invincibility.asm | Assembly | apache-2.0 | 1,061 |
_x$ = 8 ; size = 4
bool <lambda_38b13499cc98be0a488fd10e7e4a1541>::operator()(int)const PROC ; <lambda_38b13499cc98be0a488fd10e7e4a1541>::operator(), COMDAT
mov eax, DWORD PTR _x$[esp-4]
cmp eax, 42 ; 0000002aH
je SHORT $LN3@operator
cmp eax, -1
je SHORT $LN3@operator
xor al, al
ret 4
$LN3@operator:
mov al, 1
ret 4
bool <lambda_38b13499cc98be0a488fd10e7e4a1541>::operator()(int)const ENDP ; <lambda_38b13499cc98be0a488fd10e7e4a1541>::operator()
_x$ = 8 ; size = 4
bool <lambda_6030eb0ee5ee5712779754fc8d958e43>::operator()(int)const PROC ; <lambda_6030eb0ee5ee5712779754fc8d958e43>::operator(), COMDAT
mov eax, DWORD PTR _x$[esp-4]
cmp eax, 42 ; 0000002aH
je SHORT $LN3@operator
cmp eax, -1
je SHORT $LN3@operator
xor al, al
ret 4
$LN3@operator:
mov al, 1
ret 4
bool <lambda_6030eb0ee5ee5712779754fc8d958e43>::operator()(int)const ENDP ; <lambda_6030eb0ee5ee5712779754fc8d958e43>::operator()
_v$ = 8 ; size = 4
unsigned int count_if_epi32(std::vector<int,std::allocator<int> > const &) PROC ; count_if_epi32, COMDAT
mov eax, DWORD PTR _v$[esp-4]
push esi
push edi
xor esi, esi
mov edi, DWORD PTR [eax+4]
mov ecx, DWORD PTR [eax]
cmp ecx, edi
je SHORT $LN30@count_if_e
$LL23@count_if_e:
mov eax, DWORD PTR [ecx]
cmp eax, 42 ; 0000002aH
je SHORT $LN24@count_if_e
cmp eax, -1
je SHORT $LN24@count_if_e
xor dl, dl
jmp SHORT $LN25@count_if_e
$LN24@count_if_e:
mov dl, 1
$LN25@count_if_e:
test dl, dl
lea eax, DWORD PTR [esi+1]
cmove eax, esi
add ecx, 4
mov esi, eax
cmp ecx, edi
jne SHORT $LL23@count_if_e
$LN30@count_if_e:
pop edi
mov eax, esi
pop esi
ret 0
unsigned int count_if_epi32(std::vector<int,std::allocator<int> > const &) ENDP ; count_if_epi32
_v$ = 8 ; size = 4
unsigned int count_if_epi8(std::vector<signed char,std::allocator<signed char> > const &) PROC ; count_if_epi8, COMDAT
mov eax, DWORD PTR _v$[esp-4]
push esi
push edi
xor esi, esi
mov edi, DWORD PTR [eax+4]
mov ecx, DWORD PTR [eax]
cmp ecx, edi
je SHORT $LN30@count_if_e
$LL23@count_if_e:
movsx eax, BYTE PTR [ecx]
cmp eax, 42 ; 0000002aH
je SHORT $LN24@count_if_e
cmp eax, -1
je SHORT $LN24@count_if_e
xor dl, dl
jmp SHORT $LN25@count_if_e
$LN24@count_if_e:
mov dl, 1
$LN25@count_if_e:
test dl, dl
lea eax, DWORD PTR [esi+1]
cmove eax, esi
inc ecx
mov esi, eax
cmp ecx, edi
jne SHORT $LL23@count_if_e
$LN30@count_if_e:
pop edi
mov eax, esi
pop esi
ret 0
unsigned int count_if_epi8(std::vector<signed char,std::allocator<signed char> > const &) ENDP ; count_if_epi8
| WojciechMula/toys | autovectorization-tests/results/msvc19.28.29333-avx2/count_if.asm | Assembly | bsd-2-clause | 3,571 |
;---------------------------------------
; CLi² (Command Line Interface) API
; 2016 © breeze/fishbone crew
;---------------------------------------
; MODULE: #63 getCurrentDate
;---------------------------------------
; Получить текущую дату
; o:HL - год
; D - месяц
; E - день
; C - день недели
;---------------------------------------
_getCurrentDate ld a,#0b ; включить режим BIN данных
ld l,#04
call _nvRamSetData+1 ; устанавливаем данные
ld a,#09 ; регистр года (смещение относительно 2000)
call _nvRamGetData+1 ; читаем данные
ld hl,2000
ld b,0
ld c,a
add hl,bc
ld a,#08 ; регистр месяца
call _nvRamGetData+1 ; читаем данные
ld d,a
ld a,#07 ; регистр дня месяца
call _nvRamGetData+1 ; читаем данные
ld e,a
ld a,#06 ; регистр дня недели
call _nvRamGetData+1 ; читаем данные
ld c,a
ret
;---------------------------------------
| LessNick/cli2 | src/system/api/getCurrentDate.asm | Assembly | bsd-3-clause | 1,172 |
;Testname=test; Arguments=-O0 -fbin -opinsr16.bin; Files=stdout stderr pinsr16.bin
bits 16
pinsrw mm0,eax,0
pinsrw mm1,si,0
pinsrw mm2,[bx],0
pinsrw mm3,word [bx],0
pinsrb xmm0,eax,0
pinsrb xmm1,sil,0
; pinsrb xmm1,bh,0
pinsrb xmm2,[bx],0
pinsrb xmm3,byte [bx],0
pinsrw xmm0,eax,0
pinsrw xmm1,si,0
pinsrw xmm2,[bx],0
pinsrw xmm3,word [bx],0
pinsrd xmm0,eax,0
pinsrd xmm1,esi,0
pinsrd xmm2,[bx],0
pinsrd xmm3,dword [bx],0
vpinsrb xmm0,eax,0
vpinsrb xmm1,bl,0
vpinsrb xmm2,[bx],0
vpinsrb xmm3,byte [bx],0
vpinsrw xmm0,eax,0
vpinsrw xmm1,si,0
vpinsrw xmm2,[bx],0
vpinsrw xmm3,word [bx],0
vpinsrd xmm0,eax,0
vpinsrd xmm1,esi,0
vpinsrd xmm2,[bx],0
vpinsrd xmm3,dword [bx],0
vpinsrb xmm4,xmm0,eax,0
vpinsrb xmm5,xmm1,bl,0
vpinsrb xmm6,xmm2,[bx],0
vpinsrb xmm7,xmm3,byte [bx],0
vpinsrw xmm4,xmm0,eax,0
vpinsrw xmm5,xmm1,si,0
vpinsrw xmm6,xmm2,[bx],0
vpinsrw xmm7,xmm3,word [bx],0
vpinsrd xmm4,xmm0,eax,0
vpinsrd xmm5,xmm1,esi,0
vpinsrd xmm6,xmm2,[bx],0
vpinsrd xmm7,xmm3,dword [bx],0
| coapp-packages/nasm | test/pinsr16.asm | Assembly | bsd-2-clause | 1,081 |
;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
;* Copyright (C) 2005-2015 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Anton Mitrofanov <BugMaster@narod.ru>
;* Fiona Glaser <fiona@x264.com>
;* Henrik Gramner <henrik@gramner.com>
;*
;* Permission to use, copy, modify, and/or distribute this software for any
;* purpose with or without fee is hereby granted, provided that the above
;* copyright notice and this permission notice appear in all copies.
;*
;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
;*****************************************************************************
; This is a header file for the x264ASM assembly language, which uses
; NASM/YASM syntax combined with a large number of macros to provide easy
; abstraction between different calling conventions (x86_32, win64, linux64).
; It also has various other useful features to simplify writing the kind of
; DSP functions that are most often used in x264.
; Unlike the rest of x264, this file is available under an ISC license, as it
; has significant usefulness outside of x264 and we want it to be available
; to the largest audience possible. Of course, if you modify it for your own
; purposes to add a new feature, we strongly encourage contributing a patch
; as this feature might be useful for others as well. Send patches or ideas
; to x264-devel@videolan.org .
%include "vpx_config.asm"
%ifndef private_prefix
%define private_prefix vpx
%endif
%ifndef public_prefix
%define public_prefix private_prefix
%endif
%ifndef STACK_ALIGNMENT
%if ARCH_X86_64
%define STACK_ALIGNMENT 16
%else
%define STACK_ALIGNMENT 4
%endif
%endif
%define WIN64 0
%define UNIX64 0
%if ARCH_X86_64
%ifidn __OUTPUT_FORMAT__,win32
%define WIN64 1
%elifidn __OUTPUT_FORMAT__,win64
%define WIN64 1
%elifidn __OUTPUT_FORMAT__,x64
%define WIN64 1
%else
%define UNIX64 1
%endif
%endif
%ifidn __OUTPUT_FORMAT__,elf32
%define mangle(x) x
%elifidn __OUTPUT_FORMAT__,elf64
%define mangle(x) x
%elifidn __OUTPUT_FORMAT__,x64
%define mangle(x) x
%elifidn __OUTPUT_FORMAT__,win64
%define mangle(x) x
%else
%define mangle(x) _ %+ x
%endif
; In some instances macho32 tables get misaligned when using .rodata.
; When looking at the disassembly it appears that the offset is either
; correct or consistently off by 90. Placing them in the .text section
; works around the issue. It appears to be specific to the way libvpx
; handles the tables.
%macro SECTION_RODATA 0-1 16
%ifidn __OUTPUT_FORMAT__,macho32
SECTION .text align=%1
fakegot:
%elifidn __OUTPUT_FORMAT__,aout
SECTION .text
%else
SECTION .rodata align=%1
%endif
%endmacro
%macro SECTION_TEXT 0-1 16
%ifidn __OUTPUT_FORMAT__,aout
SECTION .text
%else
SECTION .text align=%1
%endif
%endmacro
; PIC macros are copied from vpx_ports/x86_abi_support.asm. The "define PIC"
; from original code is added in for 64bit.
%ifidn __OUTPUT_FORMAT__,elf32
%define ABI_IS_32BIT 1
%elifidn __OUTPUT_FORMAT__,macho32
%define ABI_IS_32BIT 1
%elifidn __OUTPUT_FORMAT__,win32
%define ABI_IS_32BIT 1
%elifidn __OUTPUT_FORMAT__,aout
%define ABI_IS_32BIT 1
%else
%define ABI_IS_32BIT 0
%endif
%if ABI_IS_32BIT
%if CONFIG_PIC=1
%ifidn __OUTPUT_FORMAT__,elf32
%define GET_GOT_SAVE_ARG 1
%define WRT_PLT wrt ..plt
%macro GET_GOT 1
extern _GLOBAL_OFFSET_TABLE_
push %1
call %%get_got
%%sub_offset:
jmp %%exitGG
%%get_got:
mov %1, [esp]
add %1, _GLOBAL_OFFSET_TABLE_ + $$ - %%sub_offset wrt ..gotpc
ret
%%exitGG:
%undef GLOBAL
%define GLOBAL(x) x + %1 wrt ..gotoff
%undef RESTORE_GOT
%define RESTORE_GOT pop %1
%endmacro
%elifidn __OUTPUT_FORMAT__,macho32
%define GET_GOT_SAVE_ARG 1
%macro GET_GOT 1
push %1
call %%get_got
%%get_got:
pop %1
%undef GLOBAL
%define GLOBAL(x) x + %1 - %%get_got
%undef RESTORE_GOT
%define RESTORE_GOT pop %1
%endmacro
%endif
%endif
%if ARCH_X86_64 == 0
%undef PIC
%endif
%else
%macro GET_GOT 1
%endmacro
%define GLOBAL(x) rel x
%define WRT_PLT wrt ..plt
%if WIN64
%define PIC
%elifidn __OUTPUT_FORMAT__,macho64
%define PIC
%elif CONFIG_PIC
%define PIC
%endif
%endif
%ifnmacro GET_GOT
%macro GET_GOT 1
%endmacro
%define GLOBAL(x) x
%endif
%ifndef RESTORE_GOT
%define RESTORE_GOT
%endif
%ifndef WRT_PLT
%define WRT_PLT
%endif
%ifdef PIC
default rel
%endif
; Done with PIC macros
; Macros to eliminate most code duplication between x86_32 and x86_64:
; Currently this works only for leaf functions which load all their arguments
; into registers at the start, and make no other use of the stack. Luckily that
; covers most of x264's asm.
; PROLOGUE:
; %1 = number of arguments. loads them from stack if needed.
; %2 = number of registers used. pushes callee-saved regs if needed.
; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
; %4 = (optional) stack size to be allocated. The stack will be aligned before
; allocating the specified stack size. If the required stack alignment is
; larger than the known stack alignment the stack will be manually aligned
; and an extra register will be allocated to hold the original stack
; pointer (to not invalidate r0m etc.). To prevent the use of an extra
; register as stack pointer, request a negative stack size.
; %4+/%5+ = list of names to define to registers
; PROLOGUE can also be invoked by adding the same options to cglobal
; e.g.
; cglobal foo, 2,3,7,0x40, dst, src, tmp
; declares a function (foo) that automatically loads two arguments (dst and
; src) into registers, uses one additional register (tmp) plus 7 vector
; registers (m0-m6) and allocates 0x40 bytes of stack space.
; TODO Some functions can use some args directly from the stack. If they're the
; last args then you can just not declare them, but if they're in the middle
; we need more flexible macro.
; RET:
; Pops anything that was pushed by PROLOGUE, and returns.
; REP_RET:
; Use this instead of RET if it's a branch target.
; registers:
; rN and rNq are the native-size register holding function argument N
; rNd, rNw, rNb are dword, word, and byte size
; rNh is the high 8 bits of the word size
; rNm is the original location of arg N (a register or on the stack), dword
; rNmp is native size
%macro DECLARE_REG 2-3
%define r%1q %2
%define r%1d %2d
%define r%1w %2w
%define r%1b %2b
%define r%1h %2h
%if %0 == 2
%define r%1m %2d
%define r%1mp %2
%elif ARCH_X86_64 ; memory
%define r%1m [rstk + stack_offset + %3]
%define r%1mp qword r %+ %1 %+ m
%else
%define r%1m [rstk + stack_offset + %3]
%define r%1mp dword r %+ %1 %+ m
%endif
%define r%1 %2
%endmacro
%macro DECLARE_REG_SIZE 3
%define r%1q r%1
%define e%1q r%1
%define r%1d e%1
%define e%1d e%1
%define r%1w %1
%define e%1w %1
%define r%1h %3
%define e%1h %3
%define r%1b %2
%define e%1b %2
%if ARCH_X86_64 == 0
%define r%1 e%1
%endif
%endmacro
DECLARE_REG_SIZE ax, al, ah
DECLARE_REG_SIZE bx, bl, bh
DECLARE_REG_SIZE cx, cl, ch
DECLARE_REG_SIZE dx, dl, dh
DECLARE_REG_SIZE si, sil, null
DECLARE_REG_SIZE di, dil, null
DECLARE_REG_SIZE bp, bpl, null
; t# defines for when per-arch register allocation is more complex than just function arguments
%macro DECLARE_REG_TMP 1-*
%assign %%i 0
%rep %0
CAT_XDEFINE t, %%i, r%1
%assign %%i %%i+1
%rotate 1
%endrep
%endmacro
%macro DECLARE_REG_TMP_SIZE 0-*
%rep %0
%define t%1q t%1 %+ q
%define t%1d t%1 %+ d
%define t%1w t%1 %+ w
%define t%1h t%1 %+ h
%define t%1b t%1 %+ b
%rotate 1
%endrep
%endmacro
DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
%if ARCH_X86_64
%define gprsize 8
%else
%define gprsize 4
%endif
%macro PUSH 1
push %1
%ifidn rstk, rsp
%assign stack_offset stack_offset+gprsize
%endif
%endmacro
%macro POP 1
pop %1
%ifidn rstk, rsp
%assign stack_offset stack_offset-gprsize
%endif
%endmacro
%macro PUSH_IF_USED 1-*
%rep %0
%if %1 < regs_used
PUSH r%1
%endif
%rotate 1
%endrep
%endmacro
%macro POP_IF_USED 1-*
%rep %0
%if %1 < regs_used
pop r%1
%endif
%rotate 1
%endrep
%endmacro
%macro LOAD_IF_USED 1-*
%rep %0
%if %1 < num_args
mov r%1, r %+ %1 %+ mp
%endif
%rotate 1
%endrep
%endmacro
%macro SUB 2
sub %1, %2
%ifidn %1, rstk
%assign stack_offset stack_offset+(%2)
%endif
%endmacro
%macro ADD 2
add %1, %2
%ifidn %1, rstk
%assign stack_offset stack_offset-(%2)
%endif
%endmacro
%macro movifnidn 2
%ifnidn %1, %2
mov %1, %2
%endif
%endmacro
%macro movsxdifnidn 2
%ifnidn %1, %2
movsxd %1, %2
%endif
%endmacro
%macro ASSERT 1
%if (%1) == 0
%error assert failed
%endif
%endmacro
%macro DEFINE_ARGS 0-*
%ifdef n_arg_names
%assign %%i 0
%rep n_arg_names
CAT_UNDEF arg_name %+ %%i, q
CAT_UNDEF arg_name %+ %%i, d
CAT_UNDEF arg_name %+ %%i, w
CAT_UNDEF arg_name %+ %%i, h
CAT_UNDEF arg_name %+ %%i, b
CAT_UNDEF arg_name %+ %%i, m
CAT_UNDEF arg_name %+ %%i, mp
CAT_UNDEF arg_name, %%i
%assign %%i %%i+1
%endrep
%endif
%xdefine %%stack_offset stack_offset
%undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
%assign %%i 0
%rep %0
%xdefine %1q r %+ %%i %+ q
%xdefine %1d r %+ %%i %+ d
%xdefine %1w r %+ %%i %+ w
%xdefine %1h r %+ %%i %+ h
%xdefine %1b r %+ %%i %+ b
%xdefine %1m r %+ %%i %+ m
%xdefine %1mp r %+ %%i %+ mp
CAT_XDEFINE arg_name, %%i, %1
%assign %%i %%i+1
%rotate 1
%endrep
%xdefine stack_offset %%stack_offset
%assign n_arg_names %0
%endmacro
%define required_stack_alignment ((mmsize + 15) & ~15)
%macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
%ifnum %1
%if %1 != 0
%assign %%pad 0
%assign stack_size %1
%if stack_size < 0
%assign stack_size -stack_size
%endif
%if WIN64
%assign %%pad %%pad + 32 ; shadow space
%if mmsize != 8
%assign xmm_regs_used %2
%if xmm_regs_used > 8
%assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers
%endif
%endif
%endif
%if required_stack_alignment <= STACK_ALIGNMENT
; maintain the current stack alignment
%assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
SUB rsp, stack_size_padded
%else
%assign %%reg_num (regs_used - 1)
%xdefine rstk r %+ %%reg_num
; align stack, and save original stack location directly above
; it, i.e. in [rsp+stack_size_padded], so we can restore the
; stack in a single instruction (i.e. mov rsp, rstk or mov
; rsp, [rsp+stack_size_padded])
%if %1 < 0 ; need to store rsp on stack
%xdefine rstkm [rsp + stack_size + %%pad]
%assign %%pad %%pad + gprsize
%else ; can keep rsp in rstk during whole function
%xdefine rstkm rstk
%endif
%assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))
mov rstk, rsp
and rsp, ~(required_stack_alignment-1)
sub rsp, stack_size_padded
movifnidn rstkm, rstk
%endif
WIN64_PUSH_XMM
%endif
%endif
%endmacro
%macro SETUP_STACK_POINTER 1
%ifnum %1
%if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT
%if %1 > 0
%assign regs_used (regs_used + 1)
%elif ARCH_X86_64 && regs_used == num_args && num_args <= 4 + UNIX64 * 2
%warning "Stack pointer will overwrite register argument"
%endif
%endif
%endif
%endmacro
%macro DEFINE_ARGS_INTERNAL 3+
%ifnum %2
DEFINE_ARGS %3
%elif %1 == 4
DEFINE_ARGS %2
%elif %1 > 4
DEFINE_ARGS %2, %3
%endif
%endmacro
%if WIN64 ; Windows x64 ;=================================================
DECLARE_REG 0, rcx
DECLARE_REG 1, rdx
DECLARE_REG 2, R8
DECLARE_REG 3, R9
DECLARE_REG 4, R10, 40
DECLARE_REG 5, R11, 48
DECLARE_REG 6, rax, 56
DECLARE_REG 7, rdi, 64
DECLARE_REG 8, rsi, 72
DECLARE_REG 9, rbx, 80
DECLARE_REG 10, rbp, 88
DECLARE_REG 11, R12, 96
DECLARE_REG 12, R13, 104
DECLARE_REG 13, R14, 112
DECLARE_REG 14, R15, 120
%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
%assign num_args %1
%assign regs_used %2
ASSERT regs_used >= num_args
SETUP_STACK_POINTER %4
ASSERT regs_used <= 15
PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
ALLOC_STACK %4, %3
%if mmsize != 8 && stack_size == 0
WIN64_SPILL_XMM %3
%endif
LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
DEFINE_ARGS_INTERNAL %0, %4, %5
%endmacro
%macro WIN64_PUSH_XMM 0
; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
%if xmm_regs_used > 6
movaps [rstk + stack_offset + 8], xmm6
%endif
%if xmm_regs_used > 7
movaps [rstk + stack_offset + 24], xmm7
%endif
%if xmm_regs_used > 8
%assign %%i 8
%rep xmm_regs_used-8
movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
%assign %%i %%i+1
%endrep
%endif
%endmacro
%macro WIN64_SPILL_XMM 1
%assign xmm_regs_used %1
ASSERT xmm_regs_used <= 16
%if xmm_regs_used > 8
; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.
%assign %%pad (xmm_regs_used-8)*16 + 32
%assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
SUB rsp, stack_size_padded
%endif
WIN64_PUSH_XMM
%endmacro
%macro WIN64_RESTORE_XMM_INTERNAL 1
%assign %%pad_size 0
%if xmm_regs_used > 8
%assign %%i xmm_regs_used
%rep xmm_regs_used-8
%assign %%i %%i-1
movaps xmm %+ %%i, [%1 + (%%i-8)*16 + stack_size + 32]
%endrep
%endif
%if stack_size_padded > 0
%if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT
mov rsp, rstkm
%else
add %1, stack_size_padded
%assign %%pad_size stack_size_padded
%endif
%endif
%if xmm_regs_used > 7
movaps xmm7, [%1 + stack_offset - %%pad_size + 24]
%endif
%if xmm_regs_used > 6
movaps xmm6, [%1 + stack_offset - %%pad_size + 8]
%endif
%endmacro
%macro WIN64_RESTORE_XMM 1
WIN64_RESTORE_XMM_INTERNAL %1
%assign stack_offset (stack_offset-stack_size_padded)
%assign xmm_regs_used 0
%endmacro
%define has_epilogue regs_used > 7 || xmm_regs_used > 6 || mmsize == 32 || stack_size > 0
%macro RET 0
WIN64_RESTORE_XMM_INTERNAL rsp
POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
%if mmsize == 32
vzeroupper
%endif
AUTO_REP_RET
%endmacro
%elif ARCH_X86_64 ; *nix x64 ;=============================================
DECLARE_REG 0, rdi
DECLARE_REG 1, rsi
DECLARE_REG 2, rdx
DECLARE_REG 3, rcx
DECLARE_REG 4, R8
DECLARE_REG 5, R9
DECLARE_REG 6, rax, 8
DECLARE_REG 7, R10, 16
DECLARE_REG 8, R11, 24
DECLARE_REG 9, rbx, 32
DECLARE_REG 10, rbp, 40
DECLARE_REG 11, R12, 48
DECLARE_REG 12, R13, 56
DECLARE_REG 13, R14, 64
DECLARE_REG 14, R15, 72
%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
%assign num_args %1
%assign regs_used %2
ASSERT regs_used >= num_args
SETUP_STACK_POINTER %4
ASSERT regs_used <= 15
PUSH_IF_USED 9, 10, 11, 12, 13, 14
ALLOC_STACK %4
LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
DEFINE_ARGS_INTERNAL %0, %4, %5
%endmacro
%define has_epilogue regs_used > 9 || mmsize == 32 || stack_size > 0
%macro RET 0
%if stack_size_padded > 0
%if required_stack_alignment > STACK_ALIGNMENT
mov rsp, rstkm
%else
add rsp, stack_size_padded
%endif
%endif
POP_IF_USED 14, 13, 12, 11, 10, 9
%if mmsize == 32
vzeroupper
%endif
AUTO_REP_RET
%endmacro
%else ; X86_32 ;==============================================================
DECLARE_REG 0, eax, 4
DECLARE_REG 1, ecx, 8
DECLARE_REG 2, edx, 12
DECLARE_REG 3, ebx, 16
DECLARE_REG 4, esi, 20
DECLARE_REG 5, edi, 24
DECLARE_REG 6, ebp, 28
%define rsp esp
%macro DECLARE_ARG 1-*
%rep %0
%define r%1m [rstk + stack_offset + 4*%1 + 4]
%define r%1mp dword r%1m
%rotate 1
%endrep
%endmacro
DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
%assign num_args %1
%assign regs_used %2
ASSERT regs_used >= num_args
%if num_args > 7
%assign num_args 7
%endif
%if regs_used > 7
%assign regs_used 7
%endif
SETUP_STACK_POINTER %4
ASSERT regs_used <= 7
PUSH_IF_USED 3, 4, 5, 6
ALLOC_STACK %4
LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
DEFINE_ARGS_INTERNAL %0, %4, %5
%endmacro
%define has_epilogue regs_used > 3 || mmsize == 32 || stack_size > 0
%macro RET 0
%if stack_size_padded > 0
%if required_stack_alignment > STACK_ALIGNMENT
mov rsp, rstkm
%else
add rsp, stack_size_padded
%endif
%endif
POP_IF_USED 6, 5, 4, 3
%if mmsize == 32
vzeroupper
%endif
AUTO_REP_RET
%endmacro
%endif ;======================================================================
%if WIN64 == 0
%macro WIN64_SPILL_XMM 1
%endmacro
%macro WIN64_RESTORE_XMM 1
%endmacro
%macro WIN64_PUSH_XMM 0
%endmacro
%endif
; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
; a branch or a branch target. So switch to a 2-byte form of ret in that case.
; We can automatically detect "follows a branch", but not a branch target.
; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
%macro REP_RET 0
%if has_epilogue
RET
%else
rep ret
%endif
%endmacro
%define last_branch_adr $$
%macro AUTO_REP_RET 0
%ifndef cpuflags
times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ != last_branch_adr.
%elif notcpuflag(ssse3)
times ((last_branch_adr-$)>>31)+1 rep
%endif
ret
%endmacro
%macro BRANCH_INSTR 0-*
%rep %0
%macro %1 1-2 %1
%2 %1
%%branch_instr:
%xdefine last_branch_adr %%branch_instr
%endmacro
%rotate 1
%endrep
%endmacro
BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
%macro TAIL_CALL 2 ; callee, is_nonadjacent
%if has_epilogue
call %1
RET
%elif %2
jmp %1
%endif
%endmacro
;=============================================================================
; arch-independent part
;=============================================================================
%assign function_align 16
; Begin a function.
; Applies any symbol mangling needed for C linkage, and sets up a define such that
; subsequent uses of the function name automatically refer to the mangled version.
; Appends cpuflags to the function name if cpuflags has been specified.
; The "" empty default parameter is a workaround for nasm, which fails if SUFFIX
; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).
%macro cglobal 1-2+ "" ; name, [PROLOGUE args]
cglobal_internal 1, %1 %+ SUFFIX, %2
%endmacro
%macro cvisible 1-2+ "" ; name, [PROLOGUE args]
cglobal_internal 0, %1 %+ SUFFIX, %2
%endmacro
%macro cglobal_internal 2-3+
%if %1
%xdefine %%FUNCTION_PREFIX private_prefix
; libvpx explicitly sets visibility in shared object builds. Avoid
; setting visibility to hidden as it may break builds that split
; sources on e.g., directory boundaries.
%ifdef CHROMIUM
%xdefine %%VISIBILITY hidden
%else
%xdefine %%VISIBILITY
%endif
%else
%xdefine %%FUNCTION_PREFIX public_prefix
%xdefine %%VISIBILITY
%endif
%ifndef cglobaled_%2
%xdefine %2 mangle(%%FUNCTION_PREFIX %+ _ %+ %2)
%xdefine %2.skip_prologue %2 %+ .skip_prologue
CAT_XDEFINE cglobaled_, %2, 1
%endif
%xdefine current_function %2
%ifidn __OUTPUT_FORMAT__,elf32
global %2:function %%VISIBILITY
%elifidn __OUTPUT_FORMAT__,elf64
global %2:function %%VISIBILITY
%elifidn __OUTPUT_FORMAT__,macho32
%ifdef __NASM_VER__
global %2
%else
global %2:private_extern
%endif
%elifidn __OUTPUT_FORMAT__,macho64
%ifdef __NASM_VER__
global %2
%else
global %2:private_extern
%endif
%else
global %2
%endif
align function_align
%2:
RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
%xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
%assign stack_offset 0 ; stack pointer offset relative to the return address
%assign stack_size 0 ; amount of stack space that can be freely used inside a function
%assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
%assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64
%ifnidn %3, ""
PROLOGUE %3
%endif
%endmacro
%macro cextern 1
%xdefine %1 mangle(private_prefix %+ _ %+ %1)
CAT_XDEFINE cglobaled_, %1, 1
extern %1
%endmacro
; like cextern, but without the prefix
%macro cextern_naked 1
%xdefine %1 mangle(%1)
CAT_XDEFINE cglobaled_, %1, 1
extern %1
%endmacro
%macro const 1-2+
%xdefine %1 mangle(private_prefix %+ _ %+ %1)
%ifidn __OUTPUT_FORMAT__,elf32
global %1:data hidden
%elifidn __OUTPUT_FORMAT__,elf64
global %1:data hidden
%else
global %1
%endif
%1: %2
%endmacro
; This is needed for ELF, otherwise the GNU linker assumes the stack is
; executable by default.
%ifidn __OUTPUT_FORMAT__,elf32
SECTION .note.GNU-stack noalloc noexec nowrite progbits
%elifidn __OUTPUT_FORMAT__,elf64
SECTION .note.GNU-stack noalloc noexec nowrite progbits
%endif
; cpuflags
%assign cpuflags_mmx (1<<0)
%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
%assign cpuflags_3dnow (1<<2) | cpuflags_mmx
%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
%assign cpuflags_sse (1<<4) | cpuflags_mmx2
%assign cpuflags_sse2 (1<<5) | cpuflags_sse
%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
%assign cpuflags_sse3 (1<<7) | cpuflags_sse2
%assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
%assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
%assign cpuflags_sse42 (1<<10)| cpuflags_sse4
%assign cpuflags_avx (1<<11)| cpuflags_sse42
%assign cpuflags_xop (1<<12)| cpuflags_avx
%assign cpuflags_fma4 (1<<13)| cpuflags_avx
%assign cpuflags_fma3 (1<<14)| cpuflags_avx
%assign cpuflags_avx2 (1<<15)| cpuflags_fma3
%assign cpuflags_cache32 (1<<16)
%assign cpuflags_cache64 (1<<17)
%assign cpuflags_slowctz (1<<18)
%assign cpuflags_lzcnt (1<<19)
%assign cpuflags_aligned (1<<20) ; not a cpu feature, but a function variant
%assign cpuflags_atom (1<<21)
%assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt
%assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1
%define cpuflag(x) ((cpuflags & (cpuflags_ %+ x)) == (cpuflags_ %+ x))
%define notcpuflag(x) ((cpuflags & (cpuflags_ %+ x)) != (cpuflags_ %+ x))
; Takes an arbitrary number of cpuflags from the above list.
; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
%macro INIT_CPUFLAGS 0-*
%xdefine SUFFIX
%undef cpuname
%assign cpuflags 0
%if %0 >= 1
%rep %0
%ifdef cpuname
%xdefine cpuname cpuname %+ _%1
%else
%xdefine cpuname %1
%endif
%assign cpuflags cpuflags | cpuflags_%1
%rotate 1
%endrep
%xdefine SUFFIX _ %+ cpuname
%if cpuflag(avx)
%assign avx_enabled 1
%endif
%if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
%define mova movaps
%define movu movups
%define movnta movntps
%endif
%if cpuflag(aligned)
%define movu mova
%elif cpuflag(sse3) && notcpuflag(ssse3)
%define movu lddqu
%endif
%endif
%ifdef __NASM_VER__
%use smartalign
ALIGNMODE k7
%elif ARCH_X86_64 || cpuflag(sse2)
CPU amdnop
%else
CPU basicnop
%endif
%endmacro
; Merge mmx and sse*
; m# is a simd register of the currently selected size
; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#
; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#
; (All 3 remain in sync through SWAP.)
%macro CAT_XDEFINE 3
%xdefine %1%2 %3
%endmacro
%macro CAT_UNDEF 2
%undef %1%2
%endmacro
%macro INIT_MMX 0-1+
%assign avx_enabled 0
%define RESET_MM_PERMUTATION INIT_MMX %1
%define mmsize 8
%define num_mmregs 8
%define mova movq
%define movu movq
%define movh movd
%define movnta movntq
%assign %%i 0
%rep 8
CAT_XDEFINE m, %%i, mm %+ %%i
CAT_XDEFINE nnmm, %%i, %%i
%assign %%i %%i+1
%endrep
%rep 8
CAT_UNDEF m, %%i
CAT_UNDEF nnmm, %%i
%assign %%i %%i+1
%endrep
INIT_CPUFLAGS %1
%endmacro
%macro INIT_XMM 0-1+
%assign avx_enabled 0
%define RESET_MM_PERMUTATION INIT_XMM %1
%define mmsize 16
%define num_mmregs 8
%if ARCH_X86_64
%define num_mmregs 16
%endif
%define mova movdqa
%define movu movdqu
%define movh movq
%define movnta movntdq
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, xmm %+ %%i
CAT_XDEFINE nnxmm, %%i, %%i
%assign %%i %%i+1
%endrep
INIT_CPUFLAGS %1
%endmacro
%macro INIT_YMM 0-1+
%assign avx_enabled 1
%define RESET_MM_PERMUTATION INIT_YMM %1
%define mmsize 32
%define num_mmregs 8
%if ARCH_X86_64
%define num_mmregs 16
%endif
%define mova movdqa
%define movu movdqu
%undef movh
%define movnta movntdq
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, ymm %+ %%i
CAT_XDEFINE nnymm, %%i, %%i
%assign %%i %%i+1
%endrep
INIT_CPUFLAGS %1
%endmacro
INIT_XMM
%macro DECLARE_MMCAST 1
%define mmmm%1 mm%1
%define mmxmm%1 mm%1
%define mmymm%1 mm%1
%define xmmmm%1 mm%1
%define xmmxmm%1 xmm%1
%define xmmymm%1 xmm%1
%define ymmmm%1 mm%1
%define ymmxmm%1 xmm%1
%define ymmymm%1 ymm%1
%define xm%1 xmm %+ m%1
%define ym%1 ymm %+ m%1
%endmacro
%assign i 0
%rep 16
DECLARE_MMCAST i
%assign i i+1
%endrep
; I often want to use macros that permute their arguments. e.g. there's no
; efficient way to implement butterfly or transpose or dct without swapping some
; arguments.
;
; I would like to not have to manually keep track of the permutations:
; If I insert a permutation in the middle of a function, it should automatically
; change everything that follows. For more complex macros I may also have multiple
; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
;
; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
; permutes its arguments. It's equivalent to exchanging the contents of the
; registers, except that this way you exchange the register names instead, so it
; doesn't cost any cycles.
%macro PERMUTE 2-* ; takes a list of pairs to swap
%rep %0/2
%xdefine %%tmp%2 m%2
%rotate 2
%endrep
%rep %0/2
%xdefine m%1 %%tmp%2
CAT_XDEFINE nn, m%1, %1
%rotate 2
%endrep
%endmacro
%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
%ifnum %1 ; SWAP 0, 1, ...
SWAP_INTERNAL_NUM %1, %2
%else ; SWAP m0, m1, ...
SWAP_INTERNAL_NAME %1, %2
%endif
%endmacro
%macro SWAP_INTERNAL_NUM 2-*
%rep %0-1
%xdefine %%tmp m%1
%xdefine m%1 m%2
%xdefine m%2 %%tmp
CAT_XDEFINE nn, m%1, %1
CAT_XDEFINE nn, m%2, %2
%rotate 1
%endrep
%endmacro
%macro SWAP_INTERNAL_NAME 2-*
%xdefine %%args nn %+ %1
%rep %0-1
%xdefine %%args %%args, nn %+ %2
%rotate 1
%endrep
SWAP_INTERNAL_NUM %%args
%endmacro
; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
; calls to that function will automatically load the permutation, so values can
; be returned in mmregs.
%macro SAVE_MM_PERMUTATION 0-1
%if %0
%xdefine %%f %1_m
%else
%xdefine %%f current_function %+ _m
%endif
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE %%f, %%i, m %+ %%i
%assign %%i %%i+1
%endrep
%endmacro
%macro LOAD_MM_PERMUTATION 1 ; name to load from
%ifdef %1_m0
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, %1_m %+ %%i
CAT_XDEFINE nn, m %+ %%i, %%i
%assign %%i %%i+1
%endrep
%endif
%endmacro
; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
%macro call 1
call_internal %1, %1 %+ SUFFIX
%endmacro
%macro call_internal 2
%xdefine %%i %1
%ifndef cglobaled_%1
%ifdef cglobaled_%2
%xdefine %%i %2
%endif
%endif
call %%i
LOAD_MM_PERMUTATION %%i
%endmacro
; Substitutions that reduce instruction size but are functionally equivalent
%macro add 2
%ifnum %2
%if %2==128
sub %1, -128
%else
add %1, %2
%endif
%else
add %1, %2
%endif
%endmacro
%macro sub 2
%ifnum %2
%if %2==128
add %1, -128
%else
sub %1, %2
%endif
%else
sub %1, %2
%endif
%endmacro
;=============================================================================
; AVX abstraction layer
;=============================================================================
%assign i 0
%rep 16
%if i < 8
CAT_XDEFINE sizeofmm, i, 8
%endif
CAT_XDEFINE sizeofxmm, i, 16
CAT_XDEFINE sizeofymm, i, 32
%assign i i+1
%endrep
%undef i
%macro CHECK_AVX_INSTR_EMU 3-*
%xdefine %%opcode %1
%xdefine %%dst %2
%rep %0-2
%ifidn %%dst, %3
%error non-avx emulation of ``%%opcode'' is not supported
%endif
%rotate 1
%endrep
%endmacro
;%1 == instruction
;%2 == minimal instruction set
;%3 == 1 if float, 0 if int
;%4 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
;%6+: operands
%macro RUN_AVX_INSTR 6-9+
%ifnum sizeof%7
%assign __sizeofreg sizeof%7
%elifnum sizeof%6
%assign __sizeofreg sizeof%6
%else
%assign __sizeofreg mmsize
%endif
%assign __emulate_avx 0
%if avx_enabled && __sizeofreg >= 16
%xdefine __instr v%1
%else
%xdefine __instr %1
%if %0 >= 8+%4
%assign __emulate_avx 1
%endif
%endif
%ifnidn %2, fnord
%ifdef cpuname
%if notcpuflag(%2)
%error use of ``%1'' %2 instruction in cpuname function: current_function
%elif cpuflags_%2 < cpuflags_sse && notcpuflag(sse2) && __sizeofreg > 8
%error use of ``%1'' sse2 instruction in cpuname function: current_function
%endif
%endif
%endif
%if __emulate_avx
%xdefine __src1 %7
%xdefine __src2 %8
%ifnidn %6, %7
%if %0 >= 9
CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, %8, %9
%else
CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, %8
%endif
%if %5 && %4 == 0
%ifnid %8
; 3-operand AVX instructions with a memory arg can only have it in src2,
; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
; So, if the instruction is commutative with a memory arg, swap them.
%xdefine __src1 %8
%xdefine __src2 %7
%endif
%endif
%if __sizeofreg == 8
MOVQ %6, __src1
%elif %3
MOVAPS %6, __src1
%else
MOVDQA %6, __src1
%endif
%endif
%if %0 >= 9
%1 %6, __src2, %9
%else
%1 %6, __src2
%endif
%elif %0 >= 9
__instr %6, %7, %8, %9
%elif %0 == 8
__instr %6, %7, %8
%elif %0 == 7
__instr %6, %7
%else
__instr %6
%endif
%endmacro
;%1 == instruction
;%2 == minimal instruction set
;%3 == 1 if float, 0 if int
;%4 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
%macro AVX_INSTR 1-5 fnord, 0, 1, 0
%macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5
%ifidn %2, fnord
RUN_AVX_INSTR %6, %7, %8, %9, %10, %1
%elifidn %3, fnord
RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2
%elifidn %4, fnord
RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3
%elifidn %5, fnord
RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4
%else
RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5
%endif
%endmacro
%endmacro
; Instructions with both VEX and non-VEX encodings
; Non-destructive instructions are written without parameters
AVX_INSTR addpd, sse2, 1, 0, 1
AVX_INSTR addps, sse, 1, 0, 1
AVX_INSTR addsd, sse2, 1, 0, 1
AVX_INSTR addss, sse, 1, 0, 1
AVX_INSTR addsubpd, sse3, 1, 0, 0
AVX_INSTR addsubps, sse3, 1, 0, 0
AVX_INSTR aesdec, fnord, 0, 0, 0
AVX_INSTR aesdeclast, fnord, 0, 0, 0
AVX_INSTR aesenc, fnord, 0, 0, 0
AVX_INSTR aesenclast, fnord, 0, 0, 0
AVX_INSTR aesimc
AVX_INSTR aeskeygenassist
AVX_INSTR andnpd, sse2, 1, 0, 0
AVX_INSTR andnps, sse, 1, 0, 0
AVX_INSTR andpd, sse2, 1, 0, 1
AVX_INSTR andps, sse, 1, 0, 1
AVX_INSTR blendpd, sse4, 1, 0, 0
AVX_INSTR blendps, sse4, 1, 0, 0
AVX_INSTR blendvpd, sse4, 1, 0, 0
AVX_INSTR blendvps, sse4, 1, 0, 0
AVX_INSTR cmppd, sse2, 1, 1, 0
AVX_INSTR cmpps, sse, 1, 1, 0
AVX_INSTR cmpsd, sse2, 1, 1, 0
AVX_INSTR cmpss, sse, 1, 1, 0
AVX_INSTR comisd, sse2
AVX_INSTR comiss, sse
AVX_INSTR cvtdq2pd, sse2
AVX_INSTR cvtdq2ps, sse2
AVX_INSTR cvtpd2dq, sse2
AVX_INSTR cvtpd2ps, sse2
AVX_INSTR cvtps2dq, sse2
AVX_INSTR cvtps2pd, sse2
AVX_INSTR cvtsd2si, sse2
AVX_INSTR cvtsd2ss, sse2
AVX_INSTR cvtsi2sd, sse2
AVX_INSTR cvtsi2ss, sse
AVX_INSTR cvtss2sd, sse2
AVX_INSTR cvtss2si, sse
AVX_INSTR cvttpd2dq, sse2
AVX_INSTR cvttps2dq, sse2
AVX_INSTR cvttsd2si, sse2
AVX_INSTR cvttss2si, sse
AVX_INSTR divpd, sse2, 1, 0, 0
AVX_INSTR divps, sse, 1, 0, 0
AVX_INSTR divsd, sse2, 1, 0, 0
AVX_INSTR divss, sse, 1, 0, 0
AVX_INSTR dppd, sse4, 1, 1, 0
AVX_INSTR dpps, sse4, 1, 1, 0
AVX_INSTR extractps, sse4
AVX_INSTR haddpd, sse3, 1, 0, 0
AVX_INSTR haddps, sse3, 1, 0, 0
AVX_INSTR hsubpd, sse3, 1, 0, 0
AVX_INSTR hsubps, sse3, 1, 0, 0
AVX_INSTR insertps, sse4, 1, 1, 0
AVX_INSTR lddqu, sse3
AVX_INSTR ldmxcsr, sse
AVX_INSTR maskmovdqu, sse2
AVX_INSTR maxpd, sse2, 1, 0, 1
AVX_INSTR maxps, sse, 1, 0, 1
AVX_INSTR maxsd, sse2, 1, 0, 1
AVX_INSTR maxss, sse, 1, 0, 1
AVX_INSTR minpd, sse2, 1, 0, 1
AVX_INSTR minps, sse, 1, 0, 1
AVX_INSTR minsd, sse2, 1, 0, 1
AVX_INSTR minss, sse, 1, 0, 1
AVX_INSTR movapd, sse2
AVX_INSTR movaps, sse
AVX_INSTR movd, mmx
AVX_INSTR movddup, sse3
AVX_INSTR movdqa, sse2
AVX_INSTR movdqu, sse2
AVX_INSTR movhlps, sse, 1, 0, 0
AVX_INSTR movhpd, sse2, 1, 0, 0
AVX_INSTR movhps, sse, 1, 0, 0
AVX_INSTR movlhps, sse, 1, 0, 0
AVX_INSTR movlpd, sse2, 1, 0, 0
AVX_INSTR movlps, sse, 1, 0, 0
AVX_INSTR movmskpd, sse2
AVX_INSTR movmskps, sse
AVX_INSTR movntdq, sse2
AVX_INSTR movntdqa, sse4
AVX_INSTR movntpd, sse2
AVX_INSTR movntps, sse
AVX_INSTR movq, mmx
AVX_INSTR movsd, sse2, 1, 0, 0
AVX_INSTR movshdup, sse3
AVX_INSTR movsldup, sse3
AVX_INSTR movss, sse, 1, 0, 0
AVX_INSTR movupd, sse2
AVX_INSTR movups, sse
AVX_INSTR mpsadbw, sse4
AVX_INSTR mulpd, sse2, 1, 0, 1
AVX_INSTR mulps, sse, 1, 0, 1
AVX_INSTR mulsd, sse2, 1, 0, 1
AVX_INSTR mulss, sse, 1, 0, 1
AVX_INSTR orpd, sse2, 1, 0, 1
AVX_INSTR orps, sse, 1, 0, 1
AVX_INSTR pabsb, ssse3
AVX_INSTR pabsd, ssse3
AVX_INSTR pabsw, ssse3
AVX_INSTR packsswb, mmx, 0, 0, 0
AVX_INSTR packssdw, mmx, 0, 0, 0
AVX_INSTR packuswb, mmx, 0, 0, 0
AVX_INSTR packusdw, sse4, 0, 0, 0
AVX_INSTR paddb, mmx, 0, 0, 1
AVX_INSTR paddw, mmx, 0, 0, 1
AVX_INSTR paddd, mmx, 0, 0, 1
AVX_INSTR paddq, sse2, 0, 0, 1
AVX_INSTR paddsb, mmx, 0, 0, 1
AVX_INSTR paddsw, mmx, 0, 0, 1
AVX_INSTR paddusb, mmx, 0, 0, 1
AVX_INSTR paddusw, mmx, 0, 0, 1
AVX_INSTR palignr, ssse3
AVX_INSTR pand, mmx, 0, 0, 1
AVX_INSTR pandn, mmx, 0, 0, 0
AVX_INSTR pavgb, mmx2, 0, 0, 1
AVX_INSTR pavgw, mmx2, 0, 0, 1
AVX_INSTR pblendvb, sse4, 0, 0, 0
AVX_INSTR pblendw, sse4
AVX_INSTR pclmulqdq
AVX_INSTR pcmpestri, sse42
AVX_INSTR pcmpestrm, sse42
AVX_INSTR pcmpistri, sse42
AVX_INSTR pcmpistrm, sse42
AVX_INSTR pcmpeqb, mmx, 0, 0, 1
AVX_INSTR pcmpeqw, mmx, 0, 0, 1
AVX_INSTR pcmpeqd, mmx, 0, 0, 1
AVX_INSTR pcmpeqq, sse4, 0, 0, 1
AVX_INSTR pcmpgtb, mmx, 0, 0, 0
AVX_INSTR pcmpgtw, mmx, 0, 0, 0
AVX_INSTR pcmpgtd, mmx, 0, 0, 0
AVX_INSTR pcmpgtq, sse42, 0, 0, 0
AVX_INSTR pextrb, sse4
AVX_INSTR pextrd, sse4
AVX_INSTR pextrq, sse4
AVX_INSTR pextrw, mmx2
AVX_INSTR phaddw, ssse3, 0, 0, 0
AVX_INSTR phaddd, ssse3, 0, 0, 0
AVX_INSTR phaddsw, ssse3, 0, 0, 0
AVX_INSTR phminposuw, sse4
AVX_INSTR phsubw, ssse3, 0, 0, 0
AVX_INSTR phsubd, ssse3, 0, 0, 0
AVX_INSTR phsubsw, ssse3, 0, 0, 0
AVX_INSTR pinsrb, sse4
AVX_INSTR pinsrd, sse4
AVX_INSTR pinsrq, sse4
AVX_INSTR pinsrw, mmx2
AVX_INSTR pmaddwd, mmx, 0, 0, 1
AVX_INSTR pmaddubsw, ssse3, 0, 0, 0
AVX_INSTR pmaxsb, sse4, 0, 0, 1
AVX_INSTR pmaxsw, mmx2, 0, 0, 1
AVX_INSTR pmaxsd, sse4, 0, 0, 1
AVX_INSTR pmaxub, mmx2, 0, 0, 1
AVX_INSTR pmaxuw, sse4, 0, 0, 1
AVX_INSTR pmaxud, sse4, 0, 0, 1
AVX_INSTR pminsb, sse4, 0, 0, 1
AVX_INSTR pminsw, mmx2, 0, 0, 1
AVX_INSTR pminsd, sse4, 0, 0, 1
AVX_INSTR pminub, mmx2, 0, 0, 1
AVX_INSTR pminuw, sse4, 0, 0, 1
AVX_INSTR pminud, sse4, 0, 0, 1
AVX_INSTR pmovmskb, mmx2
AVX_INSTR pmovsxbw, sse4
AVX_INSTR pmovsxbd, sse4
AVX_INSTR pmovsxbq, sse4
AVX_INSTR pmovsxwd, sse4
AVX_INSTR pmovsxwq, sse4
AVX_INSTR pmovsxdq, sse4
AVX_INSTR pmovzxbw, sse4
AVX_INSTR pmovzxbd, sse4
AVX_INSTR pmovzxbq, sse4
AVX_INSTR pmovzxwd, sse4
AVX_INSTR pmovzxwq, sse4
AVX_INSTR pmovzxdq, sse4
AVX_INSTR pmuldq, sse4, 0, 0, 1
AVX_INSTR pmulhrsw, ssse3, 0, 0, 1
AVX_INSTR pmulhuw, mmx2, 0, 0, 1
AVX_INSTR pmulhw, mmx, 0, 0, 1
AVX_INSTR pmullw, mmx, 0, 0, 1
AVX_INSTR pmulld, sse4, 0, 0, 1
AVX_INSTR pmuludq, sse2, 0, 0, 1
AVX_INSTR por, mmx, 0, 0, 1
AVX_INSTR psadbw, mmx2, 0, 0, 1
AVX_INSTR pshufb, ssse3, 0, 0, 0
AVX_INSTR pshufd, sse2
AVX_INSTR pshufhw, sse2
AVX_INSTR pshuflw, sse2
AVX_INSTR psignb, ssse3, 0, 0, 0
AVX_INSTR psignw, ssse3, 0, 0, 0
AVX_INSTR psignd, ssse3, 0, 0, 0
AVX_INSTR psllw, mmx, 0, 0, 0
AVX_INSTR pslld, mmx, 0, 0, 0
AVX_INSTR psllq, mmx, 0, 0, 0
AVX_INSTR pslldq, sse2, 0, 0, 0
AVX_INSTR psraw, mmx, 0, 0, 0
AVX_INSTR psrad, mmx, 0, 0, 0
AVX_INSTR psrlw, mmx, 0, 0, 0
AVX_INSTR psrld, mmx, 0, 0, 0
AVX_INSTR psrlq, mmx, 0, 0, 0
AVX_INSTR psrldq, sse2, 0, 0, 0
AVX_INSTR psubb, mmx, 0, 0, 0
AVX_INSTR psubw, mmx, 0, 0, 0
AVX_INSTR psubd, mmx, 0, 0, 0
AVX_INSTR psubq, sse2, 0, 0, 0
AVX_INSTR psubsb, mmx, 0, 0, 0
AVX_INSTR psubsw, mmx, 0, 0, 0
AVX_INSTR psubusb, mmx, 0, 0, 0
AVX_INSTR psubusw, mmx, 0, 0, 0
AVX_INSTR ptest, sse4
AVX_INSTR punpckhbw, mmx, 0, 0, 0
AVX_INSTR punpckhwd, mmx, 0, 0, 0
AVX_INSTR punpckhdq, mmx, 0, 0, 0
AVX_INSTR punpckhqdq, sse2, 0, 0, 0
AVX_INSTR punpcklbw, mmx, 0, 0, 0
AVX_INSTR punpcklwd, mmx, 0, 0, 0
AVX_INSTR punpckldq, mmx, 0, 0, 0
AVX_INSTR punpcklqdq, sse2, 0, 0, 0
AVX_INSTR pxor, mmx, 0, 0, 1
AVX_INSTR rcpps, sse, 1, 0, 0
AVX_INSTR rcpss, sse, 1, 0, 0
AVX_INSTR roundpd, sse4
AVX_INSTR roundps, sse4
AVX_INSTR roundsd, sse4
AVX_INSTR roundss, sse4
AVX_INSTR rsqrtps, sse, 1, 0, 0
AVX_INSTR rsqrtss, sse, 1, 0, 0
AVX_INSTR shufpd, sse2, 1, 1, 0
AVX_INSTR shufps, sse, 1, 1, 0
AVX_INSTR sqrtpd, sse2, 1, 0, 0
AVX_INSTR sqrtps, sse, 1, 0, 0
AVX_INSTR sqrtsd, sse2, 1, 0, 0
AVX_INSTR sqrtss, sse, 1, 0, 0
AVX_INSTR stmxcsr, sse
AVX_INSTR subpd, sse2, 1, 0, 0
AVX_INSTR subps, sse, 1, 0, 0
AVX_INSTR subsd, sse2, 1, 0, 0
AVX_INSTR subss, sse, 1, 0, 0
AVX_INSTR ucomisd, sse2
AVX_INSTR ucomiss, sse
AVX_INSTR unpckhpd, sse2, 1, 0, 0
AVX_INSTR unpckhps, sse, 1, 0, 0
AVX_INSTR unpcklpd, sse2, 1, 0, 0
AVX_INSTR unpcklps, sse, 1, 0, 0
AVX_INSTR xorpd, sse2, 1, 0, 1
AVX_INSTR xorps, sse, 1, 0, 1
; 3DNow instructions, for sharing code between AVX, SSE and 3DN
AVX_INSTR pfadd, 3dnow, 1, 0, 1
AVX_INSTR pfsub, 3dnow, 1, 0, 0
AVX_INSTR pfmul, 3dnow, 1, 0, 1
; base-4 constants for shuffles
%assign i 0
%rep 256
%assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
%if j < 10
CAT_XDEFINE q000, j, i
%elif j < 100
CAT_XDEFINE q00, j, i
%elif j < 1000
CAT_XDEFINE q0, j, i
%else
CAT_XDEFINE q, j, i
%endif
%assign i i+1
%endrep
%undef i
%undef j
%macro FMA_INSTR 3
%macro %1 4-7 %1, %2, %3
%if cpuflag(xop)
v%5 %1, %2, %3, %4
%elifnidn %1, %4
%6 %1, %2, %3
%7 %1, %4
%else
%error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported
%endif
%endmacro
%endmacro
FMA_INSTR pmacsww, pmullw, paddw
FMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation
FMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation
FMA_INSTR pmadcswd, pmaddwd, paddd
; convert FMA4 to FMA3 if possible
%macro FMA4_INSTR 4
%macro %1 4-8 %1, %2, %3, %4
%if cpuflag(fma4)
v%5 %1, %2, %3, %4
%elifidn %1, %2
v%6 %1, %4, %3 ; %1 = %1 * %3 + %4
%elifidn %1, %3
v%7 %1, %2, %4 ; %1 = %2 * %1 + %4
%elifidn %1, %4
v%8 %1, %2, %3 ; %1 = %2 * %3 + %1
%else
%error fma3 emulation of ``%5 %1, %2, %3, %4'' is not supported
%endif
%endmacro
%endmacro
FMA4_INSTR fmaddpd, fmadd132pd, fmadd213pd, fmadd231pd
FMA4_INSTR fmaddps, fmadd132ps, fmadd213ps, fmadd231ps
FMA4_INSTR fmaddsd, fmadd132sd, fmadd213sd, fmadd231sd
FMA4_INSTR fmaddss, fmadd132ss, fmadd213ss, fmadd231ss
FMA4_INSTR fmaddsubpd, fmaddsub132pd, fmaddsub213pd, fmaddsub231pd
FMA4_INSTR fmaddsubps, fmaddsub132ps, fmaddsub213ps, fmaddsub231ps
FMA4_INSTR fmsubaddpd, fmsubadd132pd, fmsubadd213pd, fmsubadd231pd
FMA4_INSTR fmsubaddps, fmsubadd132ps, fmsubadd213ps, fmsubadd231ps
FMA4_INSTR fmsubpd, fmsub132pd, fmsub213pd, fmsub231pd
FMA4_INSTR fmsubps, fmsub132ps, fmsub213ps, fmsub231ps
FMA4_INSTR fmsubsd, fmsub132sd, fmsub213sd, fmsub231sd
FMA4_INSTR fmsubss, fmsub132ss, fmsub213ss, fmsub231ss
FMA4_INSTR fnmaddpd, fnmadd132pd, fnmadd213pd, fnmadd231pd
FMA4_INSTR fnmaddps, fnmadd132ps, fnmadd213ps, fnmadd231ps
FMA4_INSTR fnmaddsd, fnmadd132sd, fnmadd213sd, fnmadd231sd
FMA4_INSTR fnmaddss, fnmadd132ss, fnmadd213ss, fnmadd231ss
FMA4_INSTR fnmsubpd, fnmsub132pd, fnmsub213pd, fnmsub231pd
FMA4_INSTR fnmsubps, fnmsub132ps, fnmsub213ps, fnmsub231ps
FMA4_INSTR fnmsubsd, fnmsub132sd, fnmsub213sd, fnmsub231sd
FMA4_INSTR fnmsubss, fnmsub132ss, fnmsub213ss, fnmsub231ss
; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug
%if ARCH_X86_64 == 0
%macro vpbroadcastq 2
%if sizeof%1 == 16
movddup %1, %2
%else
vbroadcastsd %1, %2
%endif
%endmacro
%endif
| liqianggao/libvpx | third_party/x86inc/x86inc.asm | Assembly | bsd-3-clause | 45,789 |
%include "asm/vesa.inc"
[section .text]
[BITS 16]
vesa:
.getcardinfo:
mov ax, 0x4F00
mov di, VBECardInfo
int 0x10
cmp ax, 0x4F
je .edid
mov eax, 1
ret
.edid:
cmp dword [.required], 0 ;if both required x and required y are set, forget this
jne near .findmode
mov ax, 0x4F15
mov bl, 1
mov di, VBEEDID
int 0x10
cmp ax, 0x4F
jne near .noedid
xor di, di
.lp:
xor cx, cx
mov cl, [di+VBEEDID.standardtiming]
shl cx, 3
add cx, 248
push ecx
call decshowrm
mov al, 'x'
call charrm
pop ecx
mov bx, cx
inc di
mov al, [di+VBEEDID.standardtiming]
and al, 11000000b
cmp al, VBEEDID.aspect.4.3
jne .not43
mov ax, 3
mul cx
mov cx, ax
shr cx, 2
jmp .gotres
.not43:
cmp al, VBEEDID.aspect.5.4
jne .not54
shl cx, 2
mov ax, cx
mov cx, 5
xor dx, dx
div cx
mov cx, ax
jmp .gotres
.not54:
cmp al, VBEEDID.aspect.16.10
jne .not1610
mov ax, 10
mul cx
mov cx, ax
shr cx, 4
jmp .gotres
.not1610:
mov ax, 9
mul cx
mov cx, ax
shr cx, 4
.gotres:
call decshowrm
mov si, .edidmsg
call printrm
inc di
cmp di, 8
jb .lp
jmp .findmode
.noedid:
mov si, .noedidmsg
call printrm
jmp .findmode
.resetlist:
;if needed, reset mins/maxes/stuff
xor cx, cx
mov [.minx], cx
mov [.miny], cx
mov [.requiredx], cx
mov [.requiredy], cx
mov [.requiredmode], cx
.findmode:
mov si, [VBECardInfo.videomodeptr]
mov ax, [VBECardInfo.videomodeptr+2]
mov fs, ax
sub si, 2
mov cx, [.requiredmode]
test cx, cx
jnz .getmodeinfo
.searchmodes:
add si, 2
mov cx, [fs:si]
cmp cx, 0xFFFF
jne .getmodeinfo
cmp word [.goodmode], 0
je .resetlist
jmp .findmode
.getmodeinfo:
push esi
;or cx, 1 << 14
mov [.currentmode], cx
mov ax, 0x4F01
mov di, VBEModeInfo
int 0x10
pop esi
cmp ax, 0x4F
je .foundmode
mov eax, 1
ret
.foundmode:
;check minimum values, really not minimums from an OS perspective but ugly for users
cmp byte [VBEModeInfo.bitsperpixel], 32
jb .searchmodes
.testx:
mov cx, [VBEModeInfo.xresolution]
cmp word [.requiredx], 0
je .notrequiredx
cmp cx, [.requiredx]
je .testy
jmp .searchmodes
.notrequiredx:
cmp cx, [.minx]
jb .searchmodes
.testy:
mov cx, [VBEModeInfo.yresolution]
cmp word [.requiredy], 0
je .notrequiredy
cmp cx, [.requiredy]
jne .searchmodes ;as if there weren't enough warnings, USE WITH CAUTION
cmp word [.requiredx], 0
jnz .setmode
jmp .testgood
.notrequiredy:
cmp cx, [.miny]
jb .searchmodes
.testgood:
mov cx, [.currentmode]
mov [.goodmode], cx
push esi
mov cx, [VBEModeInfo.xresolution]
call decshowrm
mov al, 'x'
call charrm
mov cx, [VBEModeInfo.yresolution]
call decshowrm
mov al, '@'
call charrm
xor ch, ch
mov cl, [VBEModeInfo.bitsperpixel]
call decshowrm
mov si, .modeok
call printrm
xor ax, ax
int 0x16
pop esi
cmp al, 'y'
jne .searchmodes
.setmode:
mov bx, [.currentmode]
cmp bx, 0
je .nomode
or bx, 0x4000
mov ax, 0x4F02
int 0x10
.nomode:
cmp ax, 0x4F
je .returngood
mov eax, 1
ret
.returngood:
xor eax, eax
ret
.minx dw 1024
.miny dw 768
.required:
.requiredx dw 1024 ;USE THESE WITH CAUTION
.requiredy dw 768
.requiredmode dw 0
.noedidmsg db "EDID not supported.",10,13,0
.edidmsg db " is supported.",10,13,0
.modeok db 10,13,"Is this OK?(y/n)",10,13,0
.goodmode dw 0
.currentmode dw 0
;useful functions
decshowrm:
mov si, .number
.clear:
mov al, "0"
mov [si], al
inc si
cmp si, .numberend
jb .clear
dec si
call convertrm
mov si, .number
.lp:
lodsb
cmp si, .numberend
jae .end
cmp al, "0"
jbe .lp
.end:
dec si
call printrm
ret
.number times 7 db 0
.numberend db 0
convertrm:
dec si
mov bx, si ;place to convert into must be in si, number to convert must be in cx
.cnvrt:
mov si, bx
sub si, 4
.ten4: inc si
cmp cx, 10000
jb .ten3
sub cx, 10000
inc byte [si]
jmp .cnvrt
.ten3: inc si
cmp cx, 1000
jb .ten2
sub cx, 1000
inc byte [si]
jmp .cnvrt
.ten2: inc si
cmp cx, 100
jb .ten1
sub cx, 100
inc byte [si]
jmp .cnvrt
.ten1: inc si
cmp cx, 10
jb .ten0
sub cx, 10
inc byte [si]
jmp .cnvrt
.ten0: inc si
cmp cx, 1
jb .return
sub cx, 1
inc byte [si]
jmp .cnvrt
.return:
ret
printrm:
mov al, [si]
test al, al
jz .return
call charrm
inc si
jmp printrm
.return:
ret
charrm: ;char must be in al
mov bx, 7
mov ah, 0xE
int 10h
ret
; .bestmode: ;preference is width > height > color
; mov bx, [VBEModeInfo.xresolution]
; cmp bx, [.width]
; ja .switchmode
; jb .searchmodes
; mov bx, [VBEModeInfo.yresolution]
; cmp bx, [.height]
; ja .switchmode
; jb .searchmodes
; mov bl, [VBEModeInfo.bitsperpixel]
; cmp bl, [.color]
; jb .searchmodes
; .switchmode:
; mov cx, [.currentmode]
; mov [.mode], cx
; mov bx, [VBEModeInfo.xresolution]
; mov [.width], bx
; mov bx, [VBEModeInfo.yresolution]
; mov [.height], bx
; mov bl, [VBEModeInfo.bitsperpixel]
; mov [.color], bl
; jmp .searchmodes
; .mode dw 0
; .color db 0
; .height dw 0
; .width dw 0
| alexzhang2015/redox | src/asm/vesa.asm | Assembly | mit | 4,846 |
LEN EQU 5
.MODEL small
.STACK
.DATA
VETT DB 1,2,3,-4,-5
RISULTATO DB 0
.CODE
.STARTUP
MOV DX, 0
MOV CX , LEN
MOV DI, 0
MOV AX, 0
CICLO:
ADD AL , VETT[DI]
INC DI
DEC CX
CMP CX,0
JNZ CICLO
CBW
MOV CX, LEN
IDIV CX
MOV RISULTATO, AL
.EXIT
END | neskov7/AssemblyProgramsCE | lab2/es1.asm | Assembly | mit | 283 |
.data
.waiting string "Waiting for A key...\n"
.text
.global main:
get_input:
psh A
psh C
mvi A, 1 ; syscall for stdin
ldv C, 0 ; mode for output
sys ; initiate system call
pop C
pop A
ret
main:
mvi A, 0
mvi b, .waiting
ldv c, 4
sys
mvi A, 97
mvi B, 0
ldv16 C, loop:
ldv16 D, get_input:
loop:
cal D
jne A, B, C
hlt | francisrstokes/16bitjs | asm/loop-until-a-is-pressed.asm | Assembly | mit | 373 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; * Neither the name of Intel Corporation nor the names of its
; contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%ifndef _REG_SIZES_ASM_
%define _REG_SIZES_ASM_
%ifndef AS_FEATURE_LEVEL
%define AS_FEATURE_LEVEL 4
%endif
%define EFLAGS_HAS_CPUID (1<<21)
%define FLAG_CPUID1_ECX_CLMUL (1<<1)
%define FLAG_CPUID1_EDX_SSE2 (1<<26)
%define FLAG_CPUID1_ECX_SSE3 (1)
%define FLAG_CPUID1_ECX_SSE4_1 (1<<19)
%define FLAG_CPUID1_ECX_SSE4_2 (1<<20)
%define FLAG_CPUID1_ECX_POPCNT (1<<23)
%define FLAG_CPUID1_ECX_AESNI (1<<25)
%define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
%define FLAG_CPUID1_ECX_AVX (1<<28)
%define FLAG_CPUID1_EBX_AVX2 (1<<5)
%define FLAG_CPUID7_EBX_AVX2 (1<<5)
%define FLAG_CPUID7_EBX_AVX512F (1<<16)
%define FLAG_CPUID7_EBX_AVX512DQ (1<<17)
%define FLAG_CPUID7_EBX_AVX512IFMA (1<<21)
%define FLAG_CPUID7_EBX_AVX512PF (1<<26)
%define FLAG_CPUID7_EBX_AVX512ER (1<<27)
%define FLAG_CPUID7_EBX_AVX512CD (1<<28)
%define FLAG_CPUID7_EBX_AVX512BW (1<<30)
%define FLAG_CPUID7_EBX_AVX512VL (1<<31)
%define FLAG_CPUID7_ECX_AVX512VBMI (1<<1)
%define FLAG_CPUID7_ECX_AVX512VBMI2 (1 << 6)
%define FLAG_CPUID7_ECX_GFNI (1 << 8)
%define FLAG_CPUID7_ECX_VAES (1 << 9)
%define FLAG_CPUID7_ECX_VPCLMULQDQ (1 << 10)
%define FLAG_CPUID7_ECX_VNNI (1 << 11)
%define FLAG_CPUID7_ECX_BITALG (1 << 12)
%define FLAG_CPUID7_ECX_VPOPCNTDQ (1 << 14)
%define FLAGS_CPUID7_EBX_AVX512_G1 (FLAG_CPUID7_EBX_AVX512F | FLAG_CPUID7_EBX_AVX512VL | FLAG_CPUID7_EBX_AVX512BW | FLAG_CPUID7_EBX_AVX512CD | FLAG_CPUID7_EBX_AVX512DQ)
%define FLAGS_CPUID7_ECX_AVX512_G2 (FLAG_CPUID7_ECX_AVX512VBMI2 | FLAG_CPUID7_ECX_GFNI | FLAG_CPUID7_ECX_VAES | FLAG_CPUID7_ECX_VPCLMULQDQ | FLAG_CPUID7_ECX_VNNI | FLAG_CPUID7_ECX_BITALG | FLAG_CPUID7_ECX_VPOPCNTDQ)
%define FLAG_XGETBV_EAX_XMM (1<<1)
%define FLAG_XGETBV_EAX_YMM (1<<2)
%define FLAG_XGETBV_EAX_XMM_YMM 0x6
%define FLAG_XGETBV_EAX_ZMM_OPM 0xe0
%define FLAG_CPUID1_EAX_AVOTON 0x000406d0
%define FLAG_CPUID1_EAX_STEP_MASK 0xfffffff0
; define d and w variants for registers
%define raxd eax
%define raxw ax
%define raxb al
%define rbxd ebx
%define rbxw bx
%define rbxb bl
%define rcxd ecx
%define rcxw cx
%define rcxb cl
%define rdxd edx
%define rdxw dx
%define rdxb dl
%define rsid esi
%define rsiw si
%define rsib sil
%define rdid edi
%define rdiw di
%define rdib dil
%define rbpd ebp
%define rbpw bp
%define rbpb bpl
%define ymm0x xmm0
%define ymm1x xmm1
%define ymm2x xmm2
%define ymm3x xmm3
%define ymm4x xmm4
%define ymm5x xmm5
%define ymm6x xmm6
%define ymm7x xmm7
%define ymm8x xmm8
%define ymm9x xmm9
%define ymm10x xmm10
%define ymm11x xmm11
%define ymm12x xmm12
%define ymm13x xmm13
%define ymm14x xmm14
%define ymm15x xmm15
%define zmm0x xmm0
%define zmm1x xmm1
%define zmm2x xmm2
%define zmm3x xmm3
%define zmm4x xmm4
%define zmm5x xmm5
%define zmm6x xmm6
%define zmm7x xmm7
%define zmm8x xmm8
%define zmm9x xmm9
%define zmm10x xmm10
%define zmm11x xmm11
%define zmm12x xmm12
%define zmm13x xmm13
%define zmm14x xmm14
%define zmm15x xmm15
%define zmm16x xmm16
%define zmm17x xmm17
%define zmm18x xmm18
%define zmm19x xmm19
%define zmm20x xmm20
%define zmm21x xmm21
%define zmm22x xmm22
%define zmm23x xmm23
%define zmm24x xmm24
%define zmm25x xmm25
%define zmm26x xmm26
%define zmm27x xmm27
%define zmm28x xmm28
%define zmm29x xmm29
%define zmm30x xmm30
%define zmm31x xmm31
%define zmm0y ymm0
%define zmm1y ymm1
%define zmm2y ymm2
%define zmm3y ymm3
%define zmm4y ymm4
%define zmm5y ymm5
%define zmm6y ymm6
%define zmm7y ymm7
%define zmm8y ymm8
%define zmm9y ymm9
%define zmm10y ymm10
%define zmm11y ymm11
%define zmm12y ymm12
%define zmm13y ymm13
%define zmm14y ymm14
%define zmm15y ymm15
%define zmm16y ymm16
%define zmm17y ymm17
%define zmm18y ymm18
%define zmm19y ymm19
%define zmm20y ymm20
%define zmm21y ymm21
%define zmm22y ymm22
%define zmm23y ymm23
%define zmm24y ymm24
%define zmm25y ymm25
%define zmm26y ymm26
%define zmm27y ymm27
%define zmm28y ymm28
%define zmm29y ymm29
%define zmm30y ymm30
%define zmm31y ymm31
%define DWORD(reg) reg %+ d
%define WORD(reg) reg %+ w
%define BYTE(reg) reg %+ b
%define XWORD(reg) reg %+ x
%ifidn __OUTPUT_FORMAT__,elf32
section .note.GNU-stack noalloc noexec nowrite progbits
section .text
%endif
%ifidn __OUTPUT_FORMAT__,elf64
%define __x86_64__
section .note.GNU-stack noalloc noexec nowrite progbits
section .text
%endif
%ifidn __OUTPUT_FORMAT__,win64
%define __x86_64__
%endif
%ifidn __OUTPUT_FORMAT__,macho64
%define __x86_64__
%endif
%ifdef __x86_64__
%define endbranch db 0xf3, 0x0f, 0x1e, 0xfa
%else
%define endbranch db 0xf3, 0x0f, 0x1e, 0xfb
%endif
%ifdef REL_TEXT
%define WRT_OPT
%elifidn __OUTPUT_FORMAT__, elf64
%define WRT_OPT wrt ..plt
%else
%define WRT_OPT
%endif
%macro mk_global 1-3
%ifdef __NASM_VER__
%ifidn __OUTPUT_FORMAT__, macho64
global %1
%elifidn __OUTPUT_FORMAT__, win64
global %1
%else
global %1:%2 %3
%endif
%else
global %1:%2 %3
%endif
%endmacro
; Fixes for nasm lack of MS proc helpers
%ifdef __NASM_VER__
%ifidn __OUTPUT_FORMAT__, win64
%macro alloc_stack 1
sub rsp, %1
%endmacro
%macro proc_frame 1
%1:
%endmacro
%macro save_xmm128 2
movdqa [rsp + %2], %1
%endmacro
%macro save_reg 2
mov [rsp + %2], %1
%endmacro
%macro rex_push_reg 1
push %1
%endmacro
%macro push_reg 1
push %1
%endmacro
%define end_prolog
%endif
%define endproc_frame
%endif
%ifidn __OUTPUT_FORMAT__, macho64
%define elf64 macho64
mac_equ equ 1
%endif
%macro slversion 4
section .text
global %1_slver_%2%3%4
global %1_slver
%1_slver:
%1_slver_%2%3%4:
dw 0x%4
db 0x%3, 0x%2
%endmacro
%endif ; ifndef _REG_SIZES_ASM_
| Intel-HLS/GKL | src/main/native/compression/isa-l-master/include/reg_sizes.asm | Assembly | mit | 7,433 |
loop:
cpl p1.0
nop
sjmp loop
end
| amtlib-dot-dll/EELC3034 | Lab1_3/main.asm | Assembly | cc0-1.0 | 38 |
;; Licensed to the .NET Foundation under one or more agreements.
;; The .NET Foundation licenses this file to you under the MIT license.
;; See the LICENSE file in the project root for more information.
#include "ksarm64.h"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; DATA SECTIONS ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
__tls_array equ 0x58 ;; offsetof(TEB, ThreadLocalStoragePointer)
POINTER_SIZE equ 0x08
;; TLS variables
AREA |.tls$|, DATA
ThunkParamSlot % 0x8
TEXTAREA
EXTERN _tls_index
;; Section relocs are 32 bits. Using an extra DCD initialized to zero for 8-byte alignment.
__SECTIONREL_ThunkParamSlot
DCD ThunkParamSlot
RELOC 8, ThunkParamSlot ;; SECREL
DCD 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Interop Thunks Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; RhCommonStub
;;
;; INPUT: xip0: thunk's data block
;;
;; TRASHES: x9, x10, x11, xip0
;;
LEAF_ENTRY RhCommonStub
;; There are arbitrary callers passing arguments with arbitrary signatures.
;; Custom calling convention:
;; xip0 pointer to the current thunk's data block (data contains 2 pointer values: context + target pointers)
;; Save context data into the ThunkParamSlot thread-local variable
;; A pointer to the delegate and function pointer for open static delegate should have been saved in the thunk's context cell during thunk allocation
ldr x10, =_tls_index
ldr w10, [x10]
ldr x9, [xpr, #__tls_array]
ldr x9, [x9, x10 lsl #3] ;; x9 <- our TLS base
;; x9 = base address of TLS data
;; x10 = trashed
;; xip0 = address of context cell in thunk's data
;; store thunk address in thread static
ldr x10, [xip0]
ldr x11, =__SECTIONREL_ThunkParamSlot
ldr x11, [x11]
str x10, [x9, x11] ;; ThunkParamSlot <- context slot data
;; Now load the target address and jump to it.
ldr xip0, [xip0, #POINTER_SIZE]
ret xip0
LEAF_END RhCommonStub
;;
;; IntPtr RhGetCommonStubAddress()
;;
LEAF_ENTRY RhGetCommonStubAddress
ldr x0, =RhCommonStub
ret
LEAF_END RhGetCommonStubAddress
;;
;; IntPtr RhGetCurrentThunkContext()
;;
LEAF_ENTRY RhGetCurrentThunkContext
ldr x1, =_tls_index
ldr w1, [x1]
ldr x0, [xpr, #__tls_array]
ldr x0, [x0, x1 lsl #3] ;; x0 <- our TLS base
ldr x1, =__SECTIONREL_ThunkParamSlot
ldr x1, [x1]
ldr x0, [x0, x1] ;; x0 <- ThunkParamSlot
ret
LEAF_END RhGetCurrentThunkContext
END
| gregkalapos/corert | src/Native/Runtime/arm64/InteropThunksHelpers.asm | Assembly | mit | 2,893 |
;
; jcsample.asm - downsampling (AVX2)
;
; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
; Copyright (C) 2015, Intel Corporation.
; Copyright (C) 2016, D. R. Commander.
;
; Based on the x86 SIMD extension for IJG JPEG library
; Copyright (C) 1999-2006, MIYASAKA Masaru.
; For conditions of distribution and use, see copyright notice in jsimdext.inc
;
; This file should be assembled with NASM (Netwide Assembler),
; can *not* be assembled with Microsoft's MASM or any compatible
; assembler (including Borland's Turbo Assembler).
; NASM is available from http://nasm.sourceforge.net/ or
; http://sourceforge.net/project/showfiles.php?group_id=6208
%include "jsimdext.inc"
; --------------------------------------------------------------------------
SECTION SEG_TEXT
BITS 32
;
; Downsample pixel values of a single component.
; This version handles the common case of 2:1 horizontal and 1:1 vertical,
; without smoothing.
;
; GLOBAL(void)
; jsimd_h2v1_downsample_avx2(JDIMENSION image_width, int max_v_samp_factor,
; JDIMENSION v_samp_factor,
; JDIMENSION width_in_blocks, JSAMPARRAY input_data,
; JSAMPARRAY output_data);
;
%define img_width(b) (b) + 8 ; JDIMENSION image_width
%define max_v_samp(b) (b) + 12 ; int max_v_samp_factor
%define v_samp(b) (b) + 16 ; JDIMENSION v_samp_factor
%define width_blks(b) (b) + 20 ; JDIMENSION width_in_blocks
%define input_data(b) (b) + 24 ; JSAMPARRAY input_data
%define output_data(b) (b) + 28 ; JSAMPARRAY output_data
align 32
GLOBAL_FUNCTION(jsimd_h2v1_downsample_avx2)
EXTN(jsimd_h2v1_downsample_avx2):
push ebp
mov ebp, esp
; push ebx ; unused
; push ecx ; need not be preserved
; push edx ; need not be preserved
push esi
push edi
mov ecx, JDIMENSION [width_blks(ebp)]
shl ecx, 3 ; imul ecx,DCTSIZE (ecx = output_cols)
jz near .return
mov edx, JDIMENSION [img_width(ebp)]
; -- expand_right_edge
push ecx
shl ecx, 1 ; output_cols * 2
sub ecx, edx
jle short .expand_end
mov eax, INT [max_v_samp(ebp)]
test eax, eax
jle short .expand_end
cld
mov esi, JSAMPARRAY [input_data(ebp)] ; input_data
alignx 16, 7
.expandloop:
push eax
push ecx
mov edi, JSAMPROW [esi]
add edi, edx
mov al, JSAMPLE [edi-1]
rep stosb
pop ecx
pop eax
add esi, byte SIZEOF_JSAMPROW
dec eax
jg short .expandloop
.expand_end:
pop ecx ; output_cols
; -- h2v1_downsample
mov eax, JDIMENSION [v_samp(ebp)] ; rowctr
test eax, eax
jle near .return
mov edx, 0x00010000 ; bias pattern
vmovd xmm7, edx
vpshufd xmm7, xmm7, 0x00 ; xmm7={0, 1, 0, 1, 0, 1, 0, 1}
vperm2i128 ymm7, ymm7, ymm7, 0 ; ymm7={xmm7, xmm7}
vpcmpeqw ymm6, ymm6, ymm6
vpsrlw ymm6, ymm6, BYTE_BIT ; ymm6={0xFF 0x00 0xFF 0x00 ..}
mov esi, JSAMPARRAY [input_data(ebp)] ; input_data
mov edi, JSAMPARRAY [output_data(ebp)] ; output_data
alignx 16, 7
.rowloop:
push ecx
push edi
push esi
mov esi, JSAMPROW [esi] ; inptr
mov edi, JSAMPROW [edi] ; outptr
cmp ecx, byte SIZEOF_YMMWORD
jae short .columnloop
alignx 16, 7
.columnloop_r24:
; ecx can possibly be 8, 16, 24
cmp ecx, 24
jne .columnloop_r16
vmovdqu ymm0, YMMWORD [esi+0*SIZEOF_YMMWORD]
vmovdqu xmm1, XMMWORD [esi+1*SIZEOF_YMMWORD]
mov ecx, SIZEOF_YMMWORD
jmp short .downsample
.columnloop_r16:
cmp ecx, 16
jne .columnloop_r8
vmovdqu ymm0, YMMWORD [esi+0*SIZEOF_YMMWORD]
vpxor ymm1, ymm1, ymm1
mov ecx, SIZEOF_YMMWORD
jmp short .downsample
.columnloop_r8:
vmovdqu xmm0, XMMWORD[esi+0*SIZEOF_YMMWORD]
vpxor ymm1, ymm1, ymm1
mov ecx, SIZEOF_YMMWORD
jmp short .downsample
alignx 16, 7
.columnloop:
vmovdqu ymm0, YMMWORD [esi+0*SIZEOF_YMMWORD]
vmovdqu ymm1, YMMWORD [esi+1*SIZEOF_YMMWORD]
.downsample:
vpsrlw ymm2, ymm0, BYTE_BIT
vpand ymm0, ymm0, ymm6
vpsrlw ymm3, ymm1, BYTE_BIT
vpand ymm1, ymm1, ymm6
vpaddw ymm0, ymm0, ymm2
vpaddw ymm1, ymm1, ymm3
vpaddw ymm0, ymm0, ymm7
vpaddw ymm1, ymm1, ymm7
vpsrlw ymm0, ymm0, 1
vpsrlw ymm1, ymm1, 1
vpackuswb ymm0, ymm0, ymm1
vpermq ymm0, ymm0, 0xd8
vmovdqu YMMWORD [edi+0*SIZEOF_YMMWORD], ymm0
sub ecx, byte SIZEOF_YMMWORD ; outcol
add esi, byte 2*SIZEOF_YMMWORD ; inptr
add edi, byte 1*SIZEOF_YMMWORD ; outptr
cmp ecx, byte SIZEOF_YMMWORD
jae short .columnloop
test ecx, ecx
jnz near .columnloop_r24
pop esi
pop edi
pop ecx
add esi, byte SIZEOF_JSAMPROW ; input_data
add edi, byte SIZEOF_JSAMPROW ; output_data
dec eax ; rowctr
jg near .rowloop
.return:
vzeroupper
pop edi
pop esi
; pop edx ; need not be preserved
; pop ecx ; need not be preserved
; pop ebx ; unused
pop ebp
ret
; --------------------------------------------------------------------------
;
; Downsample pixel values of a single component.
; This version handles the standard case of 2:1 horizontal and 2:1 vertical,
; without smoothing.
;
; GLOBAL(void)
; jsimd_h2v2_downsample_avx2(JDIMENSION image_width, int max_v_samp_factor,
; JDIMENSION v_samp_factor,
; JDIMENSION width_in_blocks, JSAMPARRAY input_data,
; JSAMPARRAY output_data);
;
%define img_width(b) (b) + 8 ; JDIMENSION image_width
%define max_v_samp(b) (b) + 12 ; int max_v_samp_factor
%define v_samp(b) (b) + 16 ; JDIMENSION v_samp_factor
%define width_blks(b) (b) + 20 ; JDIMENSION width_in_blocks
%define input_data(b) (b) + 24 ; JSAMPARRAY input_data
%define output_data(b) (b) + 28 ; JSAMPARRAY output_data
align 32
GLOBAL_FUNCTION(jsimd_h2v2_downsample_avx2)
EXTN(jsimd_h2v2_downsample_avx2):
push ebp
mov ebp, esp
; push ebx ; unused
; push ecx ; need not be preserved
; push edx ; need not be preserved
push esi
push edi
mov ecx, JDIMENSION [width_blks(ebp)]
shl ecx, 3 ; imul ecx,DCTSIZE (ecx = output_cols)
jz near .return
mov edx, JDIMENSION [img_width(ebp)]
; -- expand_right_edge
push ecx
shl ecx, 1 ; output_cols * 2
sub ecx, edx
jle short .expand_end
mov eax, INT [max_v_samp(ebp)]
test eax, eax
jle short .expand_end
cld
mov esi, JSAMPARRAY [input_data(ebp)] ; input_data
alignx 16, 7
.expandloop:
push eax
push ecx
mov edi, JSAMPROW [esi]
add edi, edx
mov al, JSAMPLE [edi-1]
rep stosb
pop ecx
pop eax
add esi, byte SIZEOF_JSAMPROW
dec eax
jg short .expandloop
.expand_end:
pop ecx ; output_cols
; -- h2v2_downsample
mov eax, JDIMENSION [v_samp(ebp)] ; rowctr
test eax, eax
jle near .return
mov edx, 0x00020001 ; bias pattern
vmovd xmm7, edx
vpcmpeqw ymm6, ymm6, ymm6
vpshufd xmm7, xmm7, 0x00 ; ymm7={1, 2, 1, 2, 1, 2, 1, 2}
vperm2i128 ymm7, ymm7, ymm7, 0
vpsrlw ymm6, ymm6, BYTE_BIT ; ymm6={0xFF 0x00 0xFF 0x00 ..}
mov esi, JSAMPARRAY [input_data(ebp)] ; input_data
mov edi, JSAMPARRAY [output_data(ebp)] ; output_data
alignx 16, 7
.rowloop:
push ecx
push edi
push esi
mov edx, JSAMPROW [esi+0*SIZEOF_JSAMPROW] ; inptr0
mov esi, JSAMPROW [esi+1*SIZEOF_JSAMPROW] ; inptr1
mov edi, JSAMPROW [edi] ; outptr
cmp ecx, byte SIZEOF_YMMWORD
jae short .columnloop
alignx 16, 7
.columnloop_r24:
cmp ecx, 24
jne .columnloop_r16
vmovdqu ymm0, YMMWORD [edx+0*SIZEOF_YMMWORD]
vmovdqu ymm1, YMMWORD [esi+0*SIZEOF_YMMWORD]
vmovdqu xmm2, XMMWORD [edx+1*SIZEOF_YMMWORD]
vmovdqu xmm3, XMMWORD [esi+1*SIZEOF_YMMWORD]
mov ecx, SIZEOF_YMMWORD
jmp short .downsample
.columnloop_r16:
cmp ecx, 16
jne .columnloop_r8
vmovdqu ymm0, YMMWORD [edx+0*SIZEOF_YMMWORD]
vmovdqu ymm1, YMMWORD [esi+0*SIZEOF_YMMWORD]
vpxor ymm2, ymm2, ymm2
vpxor ymm3, ymm3, ymm3
mov ecx, SIZEOF_YMMWORD
jmp short .downsample
.columnloop_r8:
vmovdqu xmm0, XMMWORD [edx+0*SIZEOF_XMMWORD]
vmovdqu xmm1, XMMWORD [esi+0*SIZEOF_XMMWORD]
vpxor ymm2, ymm2, ymm2
vpxor ymm3, ymm3, ymm3
mov ecx, SIZEOF_YMMWORD
jmp short .downsample
alignx 16, 7
.columnloop:
vmovdqu ymm0, YMMWORD [edx+0*SIZEOF_YMMWORD]
vmovdqu ymm1, YMMWORD [esi+0*SIZEOF_YMMWORD]
vmovdqu ymm2, YMMWORD [edx+1*SIZEOF_YMMWORD]
vmovdqu ymm3, YMMWORD [esi+1*SIZEOF_YMMWORD]
.downsample:
vpand ymm4, ymm0, ymm6
vpsrlw ymm0, ymm0, BYTE_BIT
vpand ymm5, ymm1, ymm6
vpsrlw ymm1, ymm1, BYTE_BIT
vpaddw ymm0, ymm0, ymm4
vpaddw ymm1, ymm1, ymm5
vpand ymm4, ymm2, ymm6
vpsrlw ymm2, ymm2, BYTE_BIT
vpand ymm5, ymm3, ymm6
vpsrlw ymm3, ymm3, BYTE_BIT
vpaddw ymm2, ymm2, ymm4
vpaddw ymm3, ymm3, ymm5
vpaddw ymm0, ymm0, ymm1
vpaddw ymm2, ymm2, ymm3
vpaddw ymm0, ymm0, ymm7
vpaddw ymm2, ymm2, ymm7
vpsrlw ymm0, ymm0, 2
vpsrlw ymm2, ymm2, 2
vpackuswb ymm0, ymm0, ymm2
vpermq ymm0, ymm0, 0xd8
vmovdqu YMMWORD [edi+0*SIZEOF_YMMWORD], ymm0
sub ecx, byte SIZEOF_YMMWORD ; outcol
add edx, byte 2*SIZEOF_YMMWORD ; inptr0
add esi, byte 2*SIZEOF_YMMWORD ; inptr1
add edi, byte 1*SIZEOF_YMMWORD ; outptr
cmp ecx, byte SIZEOF_YMMWORD
jae near .columnloop
test ecx, ecx
jnz near .columnloop_r24
pop esi
pop edi
pop ecx
add esi, byte 2*SIZEOF_JSAMPROW ; input_data
add edi, byte 1*SIZEOF_JSAMPROW ; output_data
dec eax ; rowctr
jg near .rowloop
.return:
vzeroupper
pop edi
pop esi
; pop edx ; need not be preserved
; pop ecx ; need not be preserved
; pop ebx ; unused
pop ebp
ret
; For some reason, the OS X linker does not honor the request to align the
; segment unless we do this.
align 32
| youtube/cobalt | third_party/libjpeg-turbo/simd/i386/jcsample-avx2.asm | Assembly | bsd-3-clause | 12,031 |
drawScreen:
pcall(clearBuffer)
push af
push de
push hl
push ix
;----------Window-----------
kld(hl, windowTitle)
ld a, 0x04
corelib(drawWindow)
;----------Binary-----------
ld d, 4
ld e, 9
kld(hl, (upperWord))
kcall(drawBits)
push af
ld a, d
add a, 9
ld d, a
pop af
ld h, l
kcall(drawBits)
ld d, 4
ld e, 17
kld(hl, (lowerWord))
kcall(drawBits)
push af
ld a, d
add a, 9
ld d, a
pop af
ld h, l
kcall(drawBits)
ld d, 0
ld e, 24
ld h, 95
ld l, 24
pcall(drawLine)
;Skip Draw oldNumber and operator if no operator
kld(a, (operator))
cp 0
kjp(z, .drawNewNumber)
;----------OldNumber-----------
ld d, 4
ld e, 26
kld(a, (numberBase))
cp 0
jr z, .oldDecimalDraw
cp 1
jr z, .oldHexDraw
cp 2
jr z, .oldBinaryDraw
.oldBinaryDraw:
;Draw Binary
kld(hl, (oldUpperWord))
kcall(drawBits)
ld h, l
kcall(drawBits)
ld d, 4
ld e, 34
kld(hl, (oldLowerWord))
kcall(drawBits)
ld h, l
kcall(drawBits)
jr .oldEndDraw
.oldHexDraw:
;Draw Hex
kld(hl, (oldUpperWord))
pcall(drawHexHL)
kld(hl, (oldLowerWord))
pcall(drawHexHL)
jr .oldEndDraw
.oldDecimalDraw:
;Draw Decimal
kld(hl, (oldUpperWord))
ld a, h
ld c, l
kld(ix, (oldLowerWord))
pcall(drawDecACIX)
jr .oldEndDraw
.oldEndDraw:
;----------Operator -----------
ld d, 90
ld e, 38
kld(a, (operator))
cp 0
jr z, .drawNewNumber
cp 1
jr z, .drawPlus
cp 2
jr z, .drawMinus
cp 3
jr z, .drawMul
cp 4
jr z, .drawDiv
cp 5
jr z, .drawMod
cp 6
jr z, .drawLSH
cp 7
jr z, .drawRSH
cp 8
jr z, .drawOR
cp 9
jr z, .drawAND
cp 10
jr z, .drawXOR
cp 11
jr z, .drawNOT
.drawPlus:
ld a, '+'
pcall(drawChar)
jr .drawNewNumber
.drawMinus:
ld a, '-'
pcall(drawChar)
jr .drawNewNumber
.drawMul:
ld a, '*'
pcall(drawChar)
jr .drawNewNumber
.drawDiv:
ld a, '/'
pcall(drawChar)
jr .drawNewNumber
.drawMOD:
ld a, 'M'
pcall(drawChar)
jr .drawNewNumber
.drawLSH:
ld a, '<'
pcall(drawChar)
jr .drawNewNumber
.drawRSH:
ld a, '>'
pcall(drawChar)
jr .drawNewNumber
.drawOR:
ld a, '|'
pcall(drawChar)
jr .drawNewNumber
.drawAND:
ld a, '&'
pcall(drawChar)
jr .drawNewNumber
.drawXOR:
ld a, 'X'
pcall(drawChar)
jr .drawNewNumber
.drawNOT:
ld a, '`'
pcall(drawChar)
jr .drawNewNumber
;----------NewNumber-----------
.drawNewNumber:
ld d, 4
ld e, 50
kld(a, (numberBase))
cp 0
jr z, .decimalDraw
cp 1
jr z, .hexDraw
cp 2
jr z, .binaryDraw
.binaryDraw:
;Draw Binary
ld d, 4
ld e, 43
kld(hl, (upperWord))
kcall(drawBits)
ld h, l
kcall(drawBits)
ld d, 4
ld e, 50
kld(hl, (lowerWord))
kcall(drawBits)
ld h, l
kcall(drawBits)
jr .endDraw
.hexDraw:
;Draw Hex
kld(hl, (upperWord))
pcall(drawHexHL)
kld(hl, (lowerWord))
pcall(drawHexHL)
jr .endDraw
.decimalDraw:
;Draw Decimal
kld(hl, (upperWord))
ld a, h
ld c, l
kld(ix, (lowerWord))
pcall(drawDecACIX)
jr .endDraw
.endDraw:
pop ix
pop hl
pop de
pop af
ret
;; drawBits [Text]
;; Draws a byte to the screen
;; Inputs:
;; H: Byte to be displayed
;; A: Size of element
drawBits:
push af
ld a, 8
.moreBits:
dec a
bit 7, h
jr nz, .one
;draw a zero
push af
ld a, '0'
pcall(drawChar)
pop af
jr .skipOne
;draw a one
.one:
push af
ld a, '1'
pcall(drawChar)
pop af
.skipOne:
inc d ;add padding between bits
SLA h ;shift left
cp 0
jr nz, .moreBits
pop af
ret
| boos1993/progcalc | drawScreen.asm | Assembly | mit | 4,649 |
processor 6502
org $0801 ; sys2061
sysline:
.byte $0b,$08,$01,$00,$9e,$32,$30,$36,$31,$00,$00,$00
org $080d ; sys2061
lda #$00
sta $02
incloop:
lda $02
cmp $d012
bne incloop
inc $d021
adc #$10
sta $02
decloop:
lda $02
cmp $d012
bne decloop
dec $d021
sbc #$10
sta $02
jmp incloop
| ennorehling/c64 | bars.asm | Assembly | mit | 329 |
_start:
sub sp, sp, #0x20
stp x29, x30, [sp, #0x10]
add x29, sp, #0x10
mov x0, #0x123
subs x0, x0, #0x123
b.eq done
add x0, x0, #0x123
done:
ret
| googleprojectzero/reil | analysis/test_data/control_flow_constraint.asm | Assembly | apache-2.0 | 162 |
.include "hdr.asm"
.section ".libc_mem" superfree
.accu 16
.index 16
.16bit
__builtin_memcpy:
memcpy:
lda.b 4,s ; destination
sta.b tcc__r0
tay
lda.b 8,s ; source
tax
lda.b 10,s ; source bank
xba
ora.b 6,s ; dest bank
sta.b move_insn + 1
lda.b 12,s ; length
beq +
dec a
phb
jsr move_insn
plb
lda.b 6,s
sta.b tcc__r0h
+ rtl
__builtin_mempcpy:
mempcpy:
lda.b 4,s ; destination
sta.b tcc__r0
tay
lda.b 8,s ; source
tax
lda.b 10,s ; source bank
xba
ora.b 6,s ; dest bank
sta.b move_insn + 1
lda.b 12,s ; length
beq +
dec a
phb
jsr move_insn
plb
+ lda.b 6,s
sta.b tcc__r0h
lda.b 4,s
clc
adc.b 12,s
sta.b tcc__r0
rtl
__builtin_memmove:
memmove:
lda.b 6,s ; dest bank
cmp.b 10,s
beq memcpy ; different banks -> no overlap
sta.b tcc__r0h
lda.b 4,s ; dest
cmp.b 8,s ; src
beq __local_finished ; nop
bcc memcpy ; dest before src -> forward
sta.b tcc__r0 ; dest
clc
adc.b 12,s ; +size -> end of dest
tay
lda.b 8,s ; source
clc
adc.b 12,s ; + size -> end of source
tax
lda.b 10,s ; source bank
xba
ora.b 6,s ; dest bank
sta.b move_backwards_insn + 1
lda.b 12,s ; length
beq __local_finished
dec a
phb
jsr move_backwards_insn
plb
__local_finished: rtl
__builtin_memset:
memset:
lda.b 4,s ; ptr
sta.b tcc__r0
lda.b 6,s
sta.b tcc__r0h
lda.b 10,s ; count
beq +
tay
lda.b 8,s ; character
sep #$20
- dey
sta.b [tcc__r0],y
bne -
rep #$20
+ rtl
__builtin_bzero:
bzero:
lda.b 4,s
sta.b tcc__r9
lda.b 6,s
sta.b tcc__r9h
lda.b 8,s
beq +
tay
lda.w #0
sep #$20
- dey
sta.b [tcc__r9],y
bne -
rep #$20
+ rtl
.accu 16
.index 16
__builtin_strcmp:
strcmp:
lda.b 4,s ; dest
sta.b tcc__r9
lda.b 6,s
sta.b tcc__r9h
lda.b 8,s ; src
sta.b tcc__r10
lda.b 10,s
sta.b tcc__r10h
ldy.w #0
sep #$20
- lda.b [tcc__r9],y
sec
sbc.b [tcc__r10],y
beq + ; schaumermol
bcs __local_gresser
bcc __local_kloaner
+ lda.b [tcc__r9],y
beq __local_gleich
iny
bra -
__local_gleich: rep #$20
stz.b tcc__r0
rtl
__local_gresser: rep #$20
lda.w #1
sta.b tcc__r0
rtl
__local_kloaner: rep #$20
lda.w #-1
sta.b tcc__r0
rtl
.accu 16
.index 16
__builtin_memcmp:
memcmp:
lda.b 4,s
sta.b tcc__r9
lda.b 6,s
sta.b tcc__r9h
lda.b 8,s
sta.b tcc__r10
lda.b 10,s
sta.b tcc__r10h
lda.b 12,s
beq __local_gleich
tax
ldy.w #0
sep #$20
- lda.b [tcc__r9],y
sec
sbc.b [tcc__r10],y
beq + ; schaumermol
bcs __local_gresser ; from strcmp
bcc __local_kloaner
+ dex
beq __local_gleich
iny
bra -
.ends | Techokami/classickong | libs/libc.asm | Assembly | apache-2.0 | 3,203 |
;; Test branching instructions
;;
[bits 64]
jnz near x
jo near x
jno word x
jc near x
jnc word x
jae dword x
jcxz x
jecxz x
jrcxz x
jmp dword near x
call dword near x
jmp word x
jmp dword x
jmp word [eax]
x: jmp qword [rax]
jmp word x
jmp dword x
| semi/udis86 | tests/asm/64/branch.asm | Assembly | bsd-2-clause | 265 |
; Copyright (c) 2005-2017 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;
;
;
.686
.model flat,c
.code
ALIGN 4
PUBLIC c __TBB_machine_try_lock_elided
__TBB_machine_try_lock_elided:
mov ecx, 4[esp]
xor eax, eax
mov al, 1
BYTE 0F2H
xchg al, byte ptr [ecx]
xor al, 1
ret
.code
ALIGN 4
PUBLIC c __TBB_machine_unlock_elided
__TBB_machine_unlock_elided:
mov ecx, 4[esp]
BYTE 0F3H
mov byte ptr [ecx], 0
ret
.code
ALIGN 4
PUBLIC c __TBB_machine_begin_transaction
__TBB_machine_begin_transaction:
mov eax, -1
BYTE 0C7H
BYTE 0F8H
BYTE 000H
BYTE 000H
BYTE 000H
BYTE 000H
ret
.code
ALIGN 4
PUBLIC c __TBB_machine_end_transaction
__TBB_machine_end_transaction:
BYTE 00FH
BYTE 001H
BYTE 0D5H
ret
.code
ALIGN 4
PUBLIC c __TBB_machine_transaction_conflict_abort
__TBB_machine_transaction_conflict_abort:
BYTE 0C6H
BYTE 0F8H
BYTE 0FFH ; 12.4.5 Abort argument: lock not free when tested
ret
.code
ALIGN 4
PUBLIC c __TBB_machine_is_in_transaction
__TBB_machine_is_in_transaction:
xor eax, eax
BYTE 00FH
BYTE 001H
BYTE 0D6H
JZ rset
MOV al,1
rset:
RET
end
| variar/contest-template | external/tbb/src/tbb/ia32-masm/itsx.asm | Assembly | mit | 1,885 |
; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "ext/x86/x86inc.asm"
%if ARCH_X86_64
%macro JMP_TABLE 2-*
%xdefine %1_jmptable %%table
%xdefine %%base mangle(private_prefix %+ _%1_avx2)
%%table:
%rep %0 - 1
dd %%base %+ .%2 - %%table
%rotate 1
%endrep
%endmacro
%macro CDEF_FILTER_JMP_TABLE 1
JMP_TABLE cdef_filter_%1, \
d6k0, d6k1, d7k0, d7k1, \
d0k0, d0k1, d1k0, d1k1, d2k0, d2k1, d3k0, d3k1, \
d4k0, d4k1, d5k0, d5k1, d6k0, d6k1, d7k0, d7k1, \
d0k0, d0k1, d1k0, d1k1
%endmacro
SECTION_RODATA 32
pd_47130256: dd 4, 7, 1, 3, 0, 2, 5, 6
blend_4x4: dd 0x00, 0x80, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00
dd 0x80, 0x00, 0x00
blend_4x8_0: dd 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
blend_4x8_1: dd 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
dd 0x00, 0x00
blend_4x8_2: dd 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080
dd 0x0000
blend_4x8_3: dd 0x0000, 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080, 0x8080
dd 0x0000, 0x0000
blend_8x8_0: dq 0x00, 0x00, 0x80, 0x80, 0x80, 0x80
blend_8x8_1: dq 0x0000, 0x0000, 0x8080, 0x8080, 0x8080, 0x8080, 0x0000, 0x0000
div_table: dd 840, 420, 280, 210, 168, 140, 120, 105, 420, 210, 140, 105
shufw_6543210x:db 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1, 14, 15
shufb_lohi: db 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15
pw_128: times 2 dw 128
pw_2048: times 2 dw 2048
tap_table: ; masks for 8 bit shifts
db 0xFF, 0x7F, 0x3F, 0x1F, 0x0F, 0x07, 0x03, 0x01
; weights
db 4, 2, 3, 3, 2, 1
db -1 * 16 + 1, -2 * 16 + 2
db 0 * 16 + 1, -1 * 16 + 2
db 0 * 16 + 1, 0 * 16 + 2
db 0 * 16 + 1, 1 * 16 + 2
db 1 * 16 + 1, 2 * 16 + 2
db 1 * 16 + 0, 2 * 16 + 1
db 1 * 16 + 0, 2 * 16 + 0
db 1 * 16 + 0, 2 * 16 - 1
; the last 6 are repeats of the first 6 so we don't need to & 7
db -1 * 16 + 1, -2 * 16 + 2
db 0 * 16 + 1, -1 * 16 + 2
db 0 * 16 + 1, 0 * 16 + 2
db 0 * 16 + 1, 1 * 16 + 2
db 1 * 16 + 1, 2 * 16 + 2
db 1 * 16 + 0, 2 * 16 + 1
CDEF_FILTER_JMP_TABLE 4x4
CDEF_FILTER_JMP_TABLE 4x8
CDEF_FILTER_JMP_TABLE 8x8
SECTION .text
%macro PREP_REGS 2 ; w, h
; off1/2/3[k] [6 total] from [tapq+12+(dir+0/2/6)*2+k]
mov dird, r6m
lea tableq, [cdef_filter_%1x%2_jmptable]
lea dirq, [tableq+dirq*2*4]
%if %1 == 4
%if %2 == 4
DEFINE_ARGS dst, stride, left, top, pri, sec, \
table, dir, dirjmp, dst4, stride3, k
%else
DEFINE_ARGS dst, stride, left, top, pri, sec, \
table, dir, dirjmp, dst4, dst8, stride3, k
lea dst8q, [dstq+strideq*8]
%endif
%else
DEFINE_ARGS dst, stride, h, top1, pri, sec, \
table, dir, dirjmp, top2, dst4, stride3, k
mov hq, -8
lea top1q, [top1q+strideq*0]
lea top2q, [top1q+strideq*1]
%endif
lea dst4q, [dstq+strideq*4]
%if %1 == 4
lea stride3q, [strideq*3]
%endif
%endmacro
%macro LOAD_BLOCK 2-3 0 ; w, h, init_min_max
mov kd, 1
pxor m15, m15 ; sum
%if %2 == 8
pxor m12, m12
%if %1 == 4
movd xm4, [dstq +strideq*0]
movd xm6, [dstq +strideq*1]
movd xm5, [dstq +strideq*2]
movd xm7, [dstq +stride3q ]
vinserti128 m4, [dst4q+strideq*0], 1
vinserti128 m6, [dst4q+strideq*1], 1
vinserti128 m5, [dst4q+strideq*2], 1
vinserti128 m7, [dst4q+stride3q ], 1
punpckldq m4, m6
punpckldq m5, m7
%else
movq xm4, [dstq+strideq*0]
movq xm5, [dstq+strideq*1]
vinserti128 m4, [dstq+strideq*2], 1
vinserti128 m5, [dstq+stride3q ], 1
%endif
punpcklqdq m4, m5
%else
movd xm4, [dstq+strideq*0]
movd xm5, [dstq+strideq*1]
vinserti128 m4, [dstq+strideq*2], 1
vinserti128 m5, [dstq+stride3q ], 1
punpckldq m4, m5
%endif
%if %3 == 1
mova m7, m4 ; min
mova m8, m4 ; max
%endif
%endmacro
%macro ACCUMULATE_TAP_BYTE 7-8 0 ; tap_offset, shift, mask, strength
; mul_tap, w, h, clip
; load p0/p1
movsxd dirjmpq, [dirq+kq*4+%1*2*4]
add dirjmpq, tableq
call dirjmpq
%if %8 == 1
pmaxub m7, m5
pminub m8, m5
pmaxub m7, m6
pminub m8, m6
%endif
; accumulate sum[m15] over p0/p1
%if %7 == 4
punpcklbw m5, m6
punpcklbw m6, m4, m4
psubusb m9, m5, m6
psubusb m5, m6, m5
por m9, m5 ; abs_diff_p01(p01 - px)
pcmpeqb m5, m9
por m5, %5
psignb m6, %5, m5
psrlw m5, m9, %2 ; emulate 8-bit shift
pand m5, %3
psubusb m5, %4, m5
pminub m5, m9
pmaddubsw m5, m6
paddw m15, m5
%else
psubusb m9, m5, m4
psubusb m5, m4, m5
psubusb m11, m6, m4
psubusb m6, m4, m6
por m9, m5 ; abs_diff_p0(p0 - px)
por m11, m6 ; abs_diff_p1(p1 - px)
pcmpeqb m5, m9
pcmpeqb m6, m11
punpckhbw m10, m9, m11
punpcklbw m9, m11
por m5, %5
por m11, m6, %5
punpckhbw m6, m5, m11
punpcklbw m5, m11
psignb m11, %5, m6
psrlw m6, m10, %2 ; emulate 8-bit shift
pand m6, %3
psubusb m6, %4, m6
pminub m6, m10
pmaddubsw m6, m11
paddw m12, m6
psignb m11, %5, m5
psrlw m5, m9, %2 ; emulate 8-bit shift
pand m5, %3
psubusb m5, %4, m5
pminub m5, m9
pmaddubsw m5, m11
paddw m15, m5
%endif
%endmacro
%macro ADJUST_PIXEL 4-5 0 ; w, h, zero, pw_2048, clip
%if %2 == 4
%if %5 == 1
punpcklbw m4, %3
%endif
pcmpgtw %3, m15
paddw m15, %3
pmulhrsw m15, %4
%if %5 == 0
packsswb m15, m15
paddb m4, m15
%else
paddw m4, m15
packuswb m4, m4 ; clip px in [0x0,0xff]
pminub m4, m7
pmaxub m4, m8
%endif
vextracti128 xm5, m4, 1
movd [dstq+strideq*0], xm4
movd [dstq+strideq*2], xm5
pextrd [dstq+strideq*1], xm4, 1
pextrd [dstq+stride3q ], xm5, 1
%else
pcmpgtw m6, %3, m12
pcmpgtw m5, %3, m15
paddw m12, m6
paddw m15, m5
%if %5 == 1
punpckhbw m5, m4, %3
punpcklbw m4, %3
%endif
pmulhrsw m12, %4
pmulhrsw m15, %4
%if %5 == 0
packsswb m15, m12
paddb m4, m15
%else
paddw m5, m12
paddw m4, m15
packuswb m4, m5 ; clip px in [0x0,0xff]
pminub m4, m7
pmaxub m4, m8
%endif
vextracti128 xm5, m4, 1
%if %1 == 4
movd [dstq +strideq*0], xm4
movd [dst4q+strideq*0], xm5
pextrd [dstq +strideq*1], xm4, 1
pextrd [dst4q+strideq*1], xm5, 1
pextrd [dstq +strideq*2], xm4, 2
pextrd [dst4q+strideq*2], xm5, 2
pextrd [dstq +stride3q ], xm4, 3
pextrd [dst4q+stride3q ], xm5, 3
%else
movq [dstq+strideq*0], xm4
movq [dstq+strideq*2], xm5
movhps [dstq+strideq*1], xm4
movhps [dstq+stride3q ], xm5
%endif
%endif
%endmacro
%macro BORDER_PREP_REGS 2 ; w, h
; off1/2/3[k] [6 total] from [tapq+12+(dir+0/2/6)*2+k]
mov dird, r6m
lea dirq, [tableq+dirq*2+14]
%if %1*%2*2/mmsize > 1
%if %1 == 4
DEFINE_ARGS dst, stride, dir, stk, pri, sec, stride3, h, off, k
%else
DEFINE_ARGS dst, stride, dir, stk, pri, sec, h, off, k
%endif
mov hd, %1*%2*2/mmsize
%else
DEFINE_ARGS dst, stride, dir, stk, pri, sec, stride3, off, k
%endif
lea stkq, [px]
pxor m11, m11
%endmacro
%macro BORDER_LOAD_BLOCK 2-3 0 ; w, h, init_min_max
mov kd, 1
%if %1 == 4
movq xm4, [stkq+32*0]
movhps xm4, [stkq+32*1]
movq xm5, [stkq+32*2]
movhps xm5, [stkq+32*3]
vinserti128 m4, xm5, 1
%else
mova xm4, [stkq+32*0] ; px
vinserti128 m4, [stkq+32*1], 1
%endif
pxor m15, m15 ; sum
%if %3 == 1
mova m7, m4 ; max
mova m8, m4 ; min
%endif
%endmacro
%macro ACCUMULATE_TAP_WORD 6-7 0 ; tap_offset, shift, mask, strength
; mul_tap, w, clip
; load p0/p1
movsx offq, byte [dirq+kq+%1] ; off1
%if %6 == 4
movq xm5, [stkq+offq*2+32*0] ; p0
movq xm6, [stkq+offq*2+32*2]
movhps xm5, [stkq+offq*2+32*1]
movhps xm6, [stkq+offq*2+32*3]
vinserti128 m5, xm6, 1
%else
movu xm5, [stkq+offq*2+32*0] ; p0
vinserti128 m5, [stkq+offq*2+32*1], 1
%endif
neg offq ; -off1
%if %6 == 4
movq xm6, [stkq+offq*2+32*0] ; p1
movq xm9, [stkq+offq*2+32*2]
movhps xm6, [stkq+offq*2+32*1]
movhps xm9, [stkq+offq*2+32*3]
vinserti128 m6, xm9, 1
%else
movu xm6, [stkq+offq*2+32*0] ; p1
vinserti128 m6, [stkq+offq*2+32*1], 1
%endif
%if %7 == 1
; out of bounds values are set to a value that is a both a large unsigned
; value and a negative signed value.
; use signed max and unsigned min to remove them
pmaxsw m7, m5 ; max after p0
pminuw m8, m5 ; min after p0
pmaxsw m7, m6 ; max after p1
pminuw m8, m6 ; min after p1
%endif
; accumulate sum[m15] over p0/p1
; calculate difference before converting
psubw m5, m4 ; diff_p0(p0 - px)
psubw m6, m4 ; diff_p1(p1 - px)
; convert to 8-bits with signed saturation
; saturating to large diffs has no impact on the results
packsswb m5, m6
; group into pairs so we can accumulate using maddubsw
pshufb m5, m12
pabsb m9, m5
psignb m10, %5, m5
psrlw m5, m9, %2 ; emulate 8-bit shift
pand m5, %3
psubusb m5, %4, m5
; use unsigned min since abs diff can equal 0x80
pminub m5, m9
pmaddubsw m5, m10
paddw m15, m5
%endmacro
%macro BORDER_ADJUST_PIXEL 2-3 0 ; w, pw_2048, clip
pcmpgtw m9, m11, m15
paddw m15, m9
pmulhrsw m15, %2
paddw m4, m15
%if %3 == 1
pminsw m4, m7
pmaxsw m4, m8
%endif
packuswb m4, m4
vextracti128 xm5, m4, 1
%if %1 == 4
movd [dstq+strideq*0], xm4
pextrd [dstq+strideq*1], xm4, 1
movd [dstq+strideq*2], xm5
pextrd [dstq+stride3q], xm5, 1
%else
movq [dstq+strideq*0], xm4
movq [dstq+strideq*1], xm5
%endif
%endmacro
%macro CDEF_FILTER 2 ; w, h
INIT_YMM avx2
cglobal cdef_filter_%1x%2, 4, 9, 0, dst, stride, left, top, \
pri, sec, dir, damping, edge
%assign stack_offset_entry stack_offset
mov edged, edgem
cmp edged, 0xf
jne .border_block
PUSH r9
PUSH r10
PUSH r11
%if %2 == 4
%assign regs_used 12
%if STACK_ALIGNMENT < 32
PUSH r%+regs_used
%assign regs_used regs_used+1
%endif
ALLOC_STACK 0x60, 16
pmovzxbw xm0, [leftq+1]
vpermq m0, m0, q0110
psrldq m1, m0, 4
vpalignr m2, m0, m0, 12
movu [rsp+0x10], m0
movu [rsp+0x28], m1
movu [rsp+0x40], m2
%elif %1 == 4
PUSH r12
%assign regs_used 13
%if STACK_ALIGNMENT < 32
PUSH r%+regs_used
%assign regs_used regs_used+1
%endif
ALLOC_STACK 8*2+%1*%2*1, 16
pmovzxwd m0, [leftq]
mova [rsp+0x10], m0
%else
PUSH r12
PUSH r13
%assign regs_used 14
%if STACK_ALIGNMENT < 32
PUSH r%+regs_used
%assign regs_used regs_used+1
%endif
ALLOC_STACK 8*2+%1*%2*2+32, 16
lea r11, [strideq*3]
movu xm4, [dstq+strideq*2]
pmovzxwq m0, [leftq+0]
pmovzxwq m1, [leftq+8]
vinserti128 m4, [dstq+r11], 1
pmovzxbd m2, [leftq+1]
pmovzxbd m3, [leftq+9]
mova [rsp+0x10], m0
mova [rsp+0x30], m1
mova [rsp+0x50], m2
mova [rsp+0x70], m3
mova [rsp+0x90], m4
%endif
DEFINE_ARGS dst, stride, left, top, pri, secdmp, zero, pridmp, damping
mov dampingd, r7m
xor zerod, zerod
movifnidn prid, prim
sub dampingd, 31
movifnidn secdmpd, secdmpm
or prid, 0
jz .sec_only
movd xm0, prid
lzcnt pridmpd, prid
add pridmpd, dampingd
cmovs pridmpd, zerod
mov [rsp+0], pridmpq ; pri_shift
or secdmpd, 0
jz .pri_only
movd xm1, secdmpd
lzcnt secdmpd, secdmpd
add secdmpd, dampingd
cmovs secdmpd, zerod
mov [rsp+8], secdmpq ; sec_shift
DEFINE_ARGS dst, stride, left, top, pri, secdmp, table, pridmp
lea tableq, [tap_table]
vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask
vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask
; pri/sec_taps[k] [4 total]
DEFINE_ARGS dst, stride, left, top, pri, sec, table, dir
vpbroadcastb m0, xm0 ; pri_strength
vpbroadcastb m1, xm1 ; sec_strength
and prid, 1
lea priq, [tableq+priq*2+8] ; pri_taps
lea secq, [tableq+12] ; sec_taps
PREP_REGS %1, %2
%if %1*%2 > mmsize
.v_loop:
%endif
LOAD_BLOCK %1, %2, 1
.k_loop:
vpbroadcastb m2, [priq+kq] ; pri_taps
vpbroadcastb m3, [secq+kq] ; sec_taps
ACCUMULATE_TAP_BYTE 2, [rsp+0], m13, m0, m2, %1, %2, 1 ; dir + 0
ACCUMULATE_TAP_BYTE 4, [rsp+8], m14, m1, m3, %1, %2, 1 ; dir + 2
ACCUMULATE_TAP_BYTE 0, [rsp+8], m14, m1, m3, %1, %2, 1 ; dir - 2
dec kq
jge .k_loop
vpbroadcastd m10, [pw_2048]
pxor m9, m9
ADJUST_PIXEL %1, %2, m9, m10, 1
%if %1*%2 > mmsize
mov dstq, dst4q
lea top1q, [rsp+0x90]
lea top2q, [rsp+0xA0]
lea dst4q, [dst4q+strideq*4]
add hq, 4
jl .v_loop
%endif
RET
.pri_only:
DEFINE_ARGS dst, stride, left, top, pri, _, table, pridmp
lea tableq, [tap_table]
vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask
; pri/sec_taps[k] [4 total]
DEFINE_ARGS dst, stride, left, top, pri, _, table, dir
vpbroadcastb m0, xm0 ; pri_strength
and prid, 1
lea priq, [tableq+priq*2+8] ; pri_taps
PREP_REGS %1, %2
vpbroadcastd m3, [pw_2048]
pxor m1, m1
%if %1*%2 > mmsize
.pri_v_loop:
%endif
LOAD_BLOCK %1, %2
.pri_k_loop:
vpbroadcastb m2, [priq+kq] ; pri_taps
ACCUMULATE_TAP_BYTE 2, [rsp+0], m13, m0, m2, %1, %2 ; dir + 0
dec kq
jge .pri_k_loop
ADJUST_PIXEL %1, %2, m1, m3
%if %1*%2 > mmsize
mov dstq, dst4q
lea top1q, [rsp+0x90]
lea top2q, [rsp+0xA0]
lea dst4q, [dst4q+strideq*4]
add hq, 4
jl .pri_v_loop
%endif
RET
.sec_only:
DEFINE_ARGS dst, stride, left, top, _, secdmp, zero, _, damping
movd xm1, secdmpd
lzcnt secdmpd, secdmpd
add secdmpd, dampingd
cmovs secdmpd, zerod
mov [rsp+8], secdmpq ; sec_shift
DEFINE_ARGS dst, stride, left, top, _, secdmp, table
lea tableq, [tap_table]
vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask
; pri/sec_taps[k] [4 total]
DEFINE_ARGS dst, stride, left, top, _, sec, table, dir
vpbroadcastb m1, xm1 ; sec_strength
lea secq, [tableq+12] ; sec_taps
PREP_REGS %1, %2
vpbroadcastd m2, [pw_2048]
pxor m0, m0
%if %1*%2 > mmsize
.sec_v_loop:
%endif
LOAD_BLOCK %1, %2
.sec_k_loop:
vpbroadcastb m3, [secq+kq] ; sec_taps
ACCUMULATE_TAP_BYTE 4, [rsp+8], m14, m1, m3, %1, %2 ; dir + 2
ACCUMULATE_TAP_BYTE 0, [rsp+8], m14, m1, m3, %1, %2 ; dir - 2
dec kq
jge .sec_k_loop
ADJUST_PIXEL %1, %2, m0, m2
%if %1*%2 > mmsize
mov dstq, dst4q
lea top1q, [rsp+0x90]
lea top2q, [rsp+0xA0]
lea dst4q, [dst4q+strideq*4]
add hq, 4
jl .sec_v_loop
%endif
RET
.d0k0:
%if %1 == 4
%if %2 == 4
vpbroadcastq m6, [dstq+strideq*1-1]
vpbroadcastq m10, [dstq+strideq*2-1]
movd xm5, [topq+strideq*1+1]
movd xm9, [dstq+strideq*0+1]
psrldq m11, m6, 2
psrldq m12, m10, 2
vinserti128 m6, [dstq+stride3q -1], 1
vinserti128 m10, [dstq+strideq*4-1], 1
vpblendd m5, m11, 0x10
vpblendd m9, m12, 0x10
movu m11, [blend_4x4+16]
punpckldq m6, m10
punpckldq m5, m9
vpblendvb m6, [rsp+gprsize+0x28], m11
%else
movd xm5, [topq +strideq*1+1]
movq xm6, [dstq +strideq*1-1]
movq xm10, [dstq +stride3q -1]
movq xm11, [dst4q+strideq*1-1]
pinsrd xm5, [dstq +strideq*0+1], 1
movhps xm6, [dstq +strideq*2-1]
movhps xm10, [dst4q+strideq*0-1]
movhps xm11, [dst4q+strideq*2-1]
psrldq xm9, xm6, 2
shufps xm5, xm9, q2010 ; -1 +0 +1 +2
shufps xm6, xm10, q2020 ; +1 +2 +3 +4
psrldq xm9, xm11, 2
psrldq xm10, 2
shufps xm10, xm9, q2020 ; +3 +4 +5 +6
movd xm9, [dst4q+stride3q -1]
pinsrd xm9, [dst4q+strideq*4-1], 1
shufps xm11, xm9, q1020 ; +5 +6 +7 +8
pmovzxbw m9, [leftq+3]
vinserti128 m6, xm11, 1
movu m11, [blend_4x8_0+4]
vinserti128 m5, xm10, 1
vpblendvb m6, m9, m11
%endif
%else
lea r13, [blend_8x8_0+16]
movq xm5, [top2q +1]
vbroadcasti128 m10, [dstq+strideq*1-1]
vbroadcasti128 m11, [dstq+strideq*2-1]
movhps xm5, [dstq+strideq*0+1]
vinserti128 m6, m10, [dstq+stride3q -1], 1
vinserti128 m9, m11, [dstq+strideq*4-1], 1
psrldq m10, 2
psrldq m11, 2
punpcklqdq m6, m9
movu m9, [r13+hq*2*1+16*1]
punpcklqdq m10, m11
vpblendd m5, m10, 0xF0
vpblendvb m6, [rsp+gprsize+80+hq*8+64+8*1], m9
%endif
ret
.d1k0:
.d2k0:
.d3k0:
%if %1 == 4
%if %2 == 4
movq xm6, [dstq+strideq*0-1]
movq xm9, [dstq+strideq*1-1]
vinserti128 m6, [dstq+strideq*2-1], 1
vinserti128 m9, [dstq+stride3q -1], 1
movu m11, [rsp+gprsize+0x10]
pcmpeqd m12, m12
psrldq m5, m6, 2
psrldq m10, m9, 2
psrld m12, 24
punpckldq m6, m9
punpckldq m5, m10
vpblendvb m6, m11, m12
%else
movq xm6, [dstq +strideq*0-1]
movq xm9, [dstq +strideq*2-1]
movhps xm6, [dstq +strideq*1-1]
movhps xm9, [dstq +stride3q -1]
movq xm10, [dst4q+strideq*0-1]
movhps xm10, [dst4q+strideq*1-1]
psrldq xm5, xm6, 2
psrldq xm11, xm9, 2
shufps xm5, xm11, q2020
movq xm11, [dst4q+strideq*2-1]
movhps xm11, [dst4q+stride3q -1]
shufps xm6, xm9, q2020
shufps xm9, xm10, xm11, q2020
vinserti128 m6, xm9, 1
pmovzxbw m9, [leftq+1]
psrldq xm10, 2
psrldq xm11, 2
shufps xm10, xm11, q2020
vpbroadcastd m11, [blend_4x8_0+4]
vinserti128 m5, xm10, 1
vpblendvb m6, m9, m11
%endif
%else
movu xm5, [dstq+strideq*0-1]
movu xm9, [dstq+strideq*1-1]
vinserti128 m5, [dstq+strideq*2-1], 1
vinserti128 m9, [dstq+stride3q -1], 1
movu m10, [blend_8x8_0+16]
punpcklqdq m6, m5, m9
vpblendvb m6, [rsp+gprsize+80+hq*8+64], m10
psrldq m5, 2
psrldq m9, 2
punpcklqdq m5, m9
%endif
ret
.d4k0:
%if %1 == 4
%if %2 == 4
vpbroadcastq m10, [dstq+strideq*1-1]
vpbroadcastq m11, [dstq+strideq*2-1]
movd xm6, [topq+strideq*1-1]
movd xm9, [dstq+strideq*0-1]
psrldq m5, m10, 2
psrldq m12, m11, 2
vpblendd m6, m10, 0x10
vpblendd m9, m11, 0x10
movu m10, [blend_4x4]
vinserti128 m5, [dstq+stride3q +1], 1
vinserti128 m12, [dstq+strideq*4+1], 1
punpckldq m6, m9
punpckldq m5, m12
vpblendvb m6, [rsp+gprsize+0x40], m10
%else
movd xm6, [topq +strideq*1-1]
movq xm9, [dstq +strideq*1-1]
movq xm10, [dstq +stride3q -1]
movq xm11, [dst4q+strideq*1-1]
pinsrd xm6, [dstq +strideq*0-1], 1
movhps xm9, [dstq +strideq*2-1]
movhps xm10, [dst4q+strideq*0-1]
movhps xm11, [dst4q+strideq*2-1]
psrldq xm5, xm9, 2
shufps xm6, xm9, q2010
psrldq xm9, xm10, 2
shufps xm5, xm9, q2020
shufps xm10, xm11, q2020
movd xm9, [dst4q+stride3q +1]
vinserti128 m6, xm10, 1
pinsrd xm9, [dst4q+strideq*4+1], 1
psrldq xm11, 2
pmovzxbw m10, [leftq-1]
shufps xm11, xm9, q1020
movu m9, [blend_4x8_0]
vinserti128 m5, xm11, 1
vpblendvb m6, m10, m9
%endif
%else
lea r13, [blend_8x8_0+8]
movq xm6, [top2q -1]
vbroadcasti128 m5, [dstq+strideq*1-1]
vbroadcasti128 m9, [dstq+strideq*2-1]
movhps xm6, [dstq+strideq*0-1]
movu m11, [r13+hq*2*1+16*1]
punpcklqdq m10, m5, m9
vinserti128 m5, [dstq+stride3q -1], 1
vinserti128 m9, [dstq+strideq*4-1], 1
vpblendd m6, m10, 0xF0
vpblendvb m6, [rsp+gprsize+80+hq*8+64-8*1], m11
psrldq m5, 2
psrldq m9, 2
punpcklqdq m5, m9
%endif
ret
.d5k0:
.d6k0:
.d7k0:
%if %1 == 4
%if %2 == 4
movd xm6, [topq+strideq*1 ]
vpbroadcastd m5, [dstq+strideq*1 ]
vpbroadcastd m9, [dstq+strideq*2 ]
vpblendd xm6, [dstq+strideq*0-4], 0x2
vpblendd m5, m9, 0x22
vpblendd m6, m5, 0x30
vinserti128 m5, [dstq+stride3q ], 1
vpblendd m5, [dstq+strideq*4-20], 0x20
%else
movd xm6, [topq +strideq*1]
movd xm5, [dstq +strideq*1]
movd xm9, [dstq +stride3q ]
movd xm10, [dst4q+strideq*1]
movd xm11, [dst4q+stride3q ]
pinsrd xm6, [dstq +strideq*0], 1
pinsrd xm5, [dstq +strideq*2], 1
pinsrd xm9, [dst4q+strideq*0], 1
pinsrd xm10, [dst4q+strideq*2], 1
pinsrd xm11, [dst4q+strideq*4], 1
punpcklqdq xm6, xm5
punpcklqdq xm5, xm9
punpcklqdq xm9, xm10
punpcklqdq xm10, xm11
vinserti128 m6, xm9, 1
vinserti128 m5, xm10, 1
%endif
%else
movq xm6, [top2q ]
movq xm5, [dstq+strideq*1]
movq xm9, [dstq+stride3q ]
movhps xm6, [dstq+strideq*0]
movhps xm5, [dstq+strideq*2]
movhps xm9, [dstq+strideq*4]
vinserti128 m6, xm5, 1
vinserti128 m5, xm9, 1
%endif
ret
.d0k1:
%if %1 == 4
%if %2 == 4
movd xm6, [dstq +strideq*2-2]
movd xm9, [dstq +stride3q -2]
movd xm5, [topq +strideq*0+2]
movd xm10, [topq +strideq*1+2]
pinsrw xm6, [leftq+4], 0
pinsrw xm9, [leftq+6], 0
vinserti128 m5, [dstq +strideq*0+2], 1
vinserti128 m10, [dstq +strideq*1+2], 1
vinserti128 m6, [dst4q+strideq*0-2], 1
vinserti128 m9, [dst4q+strideq*1-2], 1
punpckldq m5, m10
punpckldq m6, m9
%else
movq xm6, [dstq +strideq*2-2]
movd xm10, [dst4q+strideq*2-2]
movd xm5, [topq +strideq*0+2]
movq xm9, [dst4q+strideq*0-2]
movhps xm6, [dstq +stride3q -2]
pinsrw xm10, [dst4q+stride3q ], 3
pinsrd xm5, [topq +strideq*1+2], 1
movhps xm9, [dst4q+strideq*1-2]
pinsrd xm10, [dst8q+strideq*0-2], 2
pinsrd xm5, [dstq +strideq*0+2], 2
pinsrd xm10, [dst8q+strideq*1-2], 3
pinsrd xm5, [dstq +strideq*1+2], 3
shufps xm11, xm6, xm9, q3131
shufps xm6, xm9, q2020
movu m9, [blend_4x8_3+8]
vinserti128 m6, xm10, 1
vinserti128 m5, xm11, 1
vpblendvb m6, [rsp+gprsize+16+8], m9
%endif
%else
lea r13, [blend_8x8_1+16]
movq xm6, [dstq +strideq*2-2]
movq xm9, [dstq +stride3q -2]
movq xm5, [top1q +2]
movq xm10, [top2q +2]
movu m11, [r13+hq*2*2+16*2]
vinserti128 m6, [dst4q+strideq*0-2], 1
vinserti128 m9, [dst4q+strideq*1-2], 1
vinserti128 m5, [dstq +strideq*0+2], 1
vinserti128 m10, [dstq +strideq*1+2], 1
punpcklqdq m6, m9
punpcklqdq m5, m10
vpblendvb m6, [rsp+gprsize+16+hq*8+64+8*2], m11
%endif
ret
.d1k1:
%if %1 == 4
%if %2 == 4
vpbroadcastq m6, [dstq+strideq*1-2]
vpbroadcastq m9, [dstq+strideq*2-2]
movd xm5, [topq+strideq*1+2]
movd xm10, [dstq+strideq*0+2]
psrldq m11, m6, 4
psrldq m12, m9, 4
vpblendd m5, m11, 0x10
movq xm11, [leftq+2]
vinserti128 m6, [dstq+stride3q -2], 1
punpckldq xm11, xm11
vpblendd m10, m12, 0x10
pcmpeqd m12, m12
pmovzxwd m11, xm11
psrld m12, 16
punpckldq m6, m9
vpbroadcastd m9, [dstq+strideq*4-2]
vpblendvb m6, m11, m12
punpckldq m5, m10
vpblendd m6, m9, 0x20
%else
movd xm5, [topq +strideq*1+2]
movq xm6, [dstq +strideq*1-2]
movq xm9, [dstq +stride3q -2]
movq xm10, [dst4q+strideq*1-2]
movd xm11, [dst4q+stride3q -2]
pinsrd xm5, [dstq +strideq*0+2], 1
movhps xm6, [dstq +strideq*2-2]
movhps xm9, [dst4q+strideq*0-2]
movhps xm10, [dst4q+strideq*2-2]
pinsrd xm11, [dst4q+strideq*4-2], 1
shufps xm5, xm6, q3110
shufps xm6, xm9, q2020
shufps xm9, xm10, q3131
shufps xm10, xm11, q1020
movu m11, [blend_4x8_2+4]
vinserti128 m6, xm10, 1
vinserti128 m5, xm9, 1
vpblendvb m6, [rsp+gprsize+16+4], m11
%endif
%else
lea r13, [blend_8x8_1+16]
movq xm5, [top2q +2]
vbroadcasti128 m6, [dstq+strideq*1-2]
vbroadcasti128 m9, [dstq+strideq*2-2]
movhps xm5, [dstq+strideq*0+2]
shufps m10, m6, m9, q2121
vinserti128 m6, [dstq+stride3q -2], 1
vinserti128 m9, [dstq+strideq*4-2], 1
movu m11, [r13+hq*2*1+16*1]
vpblendd m5, m10, 0xF0
punpcklqdq m6, m9
vpblendvb m6, [rsp+gprsize+16+hq*8+64+8*1], m11
%endif
ret
.d2k1:
%if %1 == 4
%if %2 == 4
movq xm11, [leftq]
movq xm6, [dstq+strideq*0-2]
movq xm9, [dstq+strideq*1-2]
vinserti128 m6, [dstq+strideq*2-2], 1
vinserti128 m9, [dstq+stride3q -2], 1
punpckldq xm11, xm11
psrldq m5, m6, 4
psrldq m10, m9, 4
pmovzxwd m11, xm11
punpckldq m6, m9
punpckldq m5, m10
pblendw m6, m11, 0x05
%else
movq xm5, [dstq +strideq*0-2]
movq xm9, [dstq +strideq*2-2]
movq xm10, [dst4q+strideq*0-2]
movq xm11, [dst4q+strideq*2-2]
movhps xm5, [dstq +strideq*1-2]
movhps xm9, [dstq +stride3q -2]
movhps xm10, [dst4q+strideq*1-2]
movhps xm11, [dst4q+stride3q -2]
shufps xm6, xm5, xm9, q2020
shufps xm5, xm9, q3131
shufps xm9, xm10, xm11, q2020
shufps xm10, xm11, q3131
pmovzxwd m11, [leftq]
vinserti128 m6, xm9, 1
vinserti128 m5, xm10, 1
pblendw m6, m11, 0x55
%endif
%else
mova m11, [rsp+gprsize+16+hq*8+64]
movu xm5, [dstq+strideq*0-2]
movu xm9, [dstq+strideq*1-2]
vinserti128 m5, [dstq+strideq*2-2], 1
vinserti128 m9, [dstq+stride3q -2], 1
shufps m6, m5, m9, q1010
shufps m5, m9, q2121
pblendw m6, m11, 0x11
%endif
ret
.d3k1:
%if %1 == 4
%if %2 == 4
vpbroadcastq m11, [dstq+strideq*1-2]
vpbroadcastq m12, [dstq+strideq*2-2]
movd xm6, [topq+strideq*1-2]
movd xm9, [dstq+strideq*0-2]
pblendw m11, [leftq-16+2], 0x01
pblendw m12, [leftq-16+4], 0x01
pinsrw xm9, [leftq- 0+0], 0
psrldq m5, m11, 4
psrldq m10, m12, 4
vinserti128 m5, [dstq+stride3q +2], 1
vinserti128 m10, [dstq+strideq*4+2], 1
vpblendd m6, m11, 0x10
vpblendd m9, m12, 0x10
punpckldq m6, m9
punpckldq m5, m10
%else
movd xm6, [topq +strideq*1-2]
movq xm5, [dstq +strideq*1-2]
movq xm9, [dstq +stride3q -2]
movq xm10, [dst4q+strideq*1-2]
movd xm11, [dst4q+stride3q +2]
pinsrw xm6, [dstq +strideq*0 ], 3
movhps xm5, [dstq +strideq*2-2]
movhps xm9, [dst4q+strideq*0-2]
movhps xm10, [dst4q+strideq*2-2]
pinsrd xm11, [dst4q+strideq*4+2], 1
shufps xm6, xm5, q2010
shufps xm5, xm9, q3131
shufps xm9, xm10, q2020
shufps xm10, xm11, q1031
movu m11, [blend_4x8_2]
vinserti128 m6, xm9, 1
vinserti128 m5, xm10, 1
vpblendvb m6, [rsp+gprsize+16-4], m11
%endif
%else
lea r13, [blend_8x8_1+8]
movq xm6, [top2q -2]
vbroadcasti128 m5, [dstq+strideq*1-2]
vbroadcasti128 m10, [dstq+strideq*2-2]
movhps xm6, [dstq+strideq*0-2]
punpcklqdq m9, m5, m10
vinserti128 m5, [dstq+stride3q -2], 1
vinserti128 m10, [dstq+strideq*4-2], 1
movu m11, [r13+hq*2*1+16*1]
vpblendd m6, m9, 0xF0
shufps m5, m10, q2121
vpblendvb m6, [rsp+gprsize+16+hq*8+64-8*1], m11
%endif
ret
.d4k1:
%if %1 == 4
%if %2 == 4
vinserti128 m6, [dstq +strideq*0-2], 1
vinserti128 m9, [dstq +strideq*1-2], 1
movd xm5, [dstq +strideq*2+2]
movd xm10, [dstq +stride3q +2]
pblendw m6, [leftq-16+0], 0x01
pblendw m9, [leftq-16+2], 0x01
vinserti128 m5, [dst4q+strideq*0+2], 1
vinserti128 m10, [dst4q+strideq*1+2], 1
vpblendd m6, [topq +strideq*0-2], 0x01
vpblendd m9, [topq +strideq*1-2], 0x01
punpckldq m5, m10
punpckldq m6, m9
%else
movd xm6, [topq +strideq*0-2]
movq xm5, [dstq +strideq*2-2]
movq xm9, [dst4q+strideq*0-2]
movd xm10, [dst4q+strideq*2+2]
pinsrd xm6, [topq +strideq*1-2], 1
movhps xm5, [dstq +stride3q -2]
movhps xm9, [dst4q+strideq*1-2]
pinsrd xm10, [dst4q+stride3q +2], 1
pinsrd xm6, [dstq +strideq*0-2], 2
pinsrd xm10, [dst8q+strideq*0+2], 2
pinsrd xm6, [dstq +strideq*1-2], 3
pinsrd xm10, [dst8q+strideq*1+2], 3
shufps xm11, xm5, xm9, q2020
shufps xm5, xm9, q3131
movu m9, [blend_4x8_3]
vinserti128 m6, xm11, 1
vinserti128 m5, xm10, 1
vpblendvb m6, [rsp+gprsize+16-8], m9
%endif
%else
lea r13, [blend_8x8_1]
movu m11, [r13+hq*2*2+16*2]
movq xm6, [top1q -2]
movq xm9, [top2q -2]
movq xm5, [dstq +strideq*2+2]
movq xm10, [dstq +stride3q +2]
vinserti128 m6, [dstq +strideq*0-2], 1
vinserti128 m9, [dstq +strideq*1-2], 1
vinserti128 m5, [dst4q+strideq*0+2], 1
vinserti128 m10, [dst4q+strideq*1+2], 1
punpcklqdq m6, m9
vpblendvb m6, [rsp+gprsize+16+hq*8+64-8*2], m11
punpcklqdq m5, m10
%endif
ret
.d5k1:
%if %1 == 4
%if %2 == 4
movd xm6, [topq +strideq*0-1]
movd xm9, [topq +strideq*1-1]
movd xm5, [dstq +strideq*2+1]
movd xm10, [dstq +stride3q +1]
pcmpeqd m12, m12
pmovzxbw m11, [leftq-8+1]
psrld m12, 24
vinserti128 m6, [dstq +strideq*0-1], 1
vinserti128 m9, [dstq +strideq*1-1], 1
vinserti128 m5, [dst4q+strideq*0+1], 1
vinserti128 m10, [dst4q+strideq*1+1], 1
punpckldq m6, m9
pxor m9, m9
vpblendd m12, m9, 0x0F
punpckldq m5, m10
vpblendvb m6, m11, m12
%else
movd xm6, [topq +strideq*0-1]
movq xm5, [dstq +strideq*2-1]
movq xm9, [dst4q+strideq*0-1]
movd xm10, [dst4q+strideq*2+1]
pinsrd xm6, [topq +strideq*1-1], 1
movhps xm5, [dstq +stride3q -1]
movhps xm9, [dst4q+strideq*1-1]
pinsrd xm10, [dst4q+stride3q +1], 1
pinsrd xm6, [dstq +strideq*0-1], 2
pinsrd xm10, [dst8q+strideq*0+1], 2
pinsrd xm6, [dstq +strideq*1-1], 3
pinsrd xm10, [dst8q+strideq*1+1], 3
shufps xm11, xm5, xm9, q2020
vinserti128 m6, xm11, 1
pmovzxbw m11, [leftq-3]
psrldq xm5, 2
psrldq xm9, 2
shufps xm5, xm9, q2020
movu m9, [blend_4x8_1]
vinserti128 m5, xm10, 1
vpblendvb m6, m11, m9
%endif
%else
lea r13, [blend_8x8_0]
movu m11, [r13+hq*2*2+16*2]
movq xm6, [top1q -1]
movq xm9, [top2q -1]
movq xm5, [dstq +strideq*2+1]
movq xm10, [dstq +stride3q +1]
vinserti128 m6, [dstq +strideq*0-1], 1
vinserti128 m9, [dstq +strideq*1-1], 1
vinserti128 m5, [dst4q+strideq*0+1], 1
vinserti128 m10, [dst4q+strideq*1+1], 1
punpcklqdq m6, m9
punpcklqdq m5, m10
vpblendvb m6, [rsp+gprsize+80+hq*8+64-8*2], m11
%endif
ret
.d6k1:
%if %1 == 4
%if %2 == 4
movd xm6, [topq +strideq*0]
movd xm9, [topq +strideq*1]
movd xm5, [dstq +strideq*2]
movd xm10, [dstq +stride3q ]
vinserti128 m6, [dstq +strideq*0], 1
vinserti128 m9, [dstq +strideq*1], 1
vinserti128 m5, [dst4q+strideq*0], 1
vinserti128 m10, [dst4q+strideq*1], 1
punpckldq m6, m9
punpckldq m5, m10
%else
movd xm5, [dstq +strideq*2]
movd xm6, [topq +strideq*0]
movd xm9, [dst4q+strideq*2]
pinsrd xm5, [dstq +stride3q ], 1
pinsrd xm6, [topq +strideq*1], 1
pinsrd xm9, [dst4q+stride3q ], 1
pinsrd xm5, [dst4q+strideq*0], 2
pinsrd xm6, [dstq +strideq*0], 2
pinsrd xm9, [dst8q+strideq*0], 2
pinsrd xm5, [dst4q+strideq*1], 3
pinsrd xm6, [dstq +strideq*1], 3
pinsrd xm9, [dst8q+strideq*1], 3
vinserti128 m6, xm5, 1
vinserti128 m5, xm9, 1
%endif
%else
movq xm5, [dstq +strideq*2]
movq xm9, [dst4q+strideq*0]
movq xm6, [top1q ]
movq xm10, [dstq +strideq*0]
movhps xm5, [dstq +stride3q ]
movhps xm9, [dst4q+strideq*1]
movhps xm6, [top2q ]
movhps xm10, [dstq +strideq*1]
vinserti128 m5, xm9, 1
vinserti128 m6, xm10, 1
%endif
ret
.d7k1:
%if %1 == 4
%if %2 == 4
movd xm5, [dstq +strideq*2-1]
movd xm9, [dstq +stride3q -1]
movd xm6, [topq +strideq*0+1]
movd xm10, [topq +strideq*1+1]
pinsrb xm5, [leftq+ 5], 0
pinsrb xm9, [leftq+ 7], 0
vinserti128 m6, [dstq +strideq*0+1], 1
vinserti128 m10, [dstq +strideq*1+1], 1
vinserti128 m5, [dst4q+strideq*0-1], 1
vinserti128 m9, [dst4q+strideq*1-1], 1
punpckldq m6, m10
punpckldq m5, m9
%else
movd xm6, [topq +strideq*0+1]
movq xm9, [dstq +strideq*2-1]
movq xm10, [dst4q+strideq*0-1]
movd xm11, [dst4q+strideq*2-1]
pinsrd xm6, [topq +strideq*1+1], 1
movhps xm9, [dstq +stride3q -1]
movhps xm10, [dst4q+strideq*1-1]
pinsrd xm11, [dst4q+stride3q -1], 1
pinsrd xm6, [dstq +strideq*0+1], 2
pinsrd xm11, [dst8q+strideq*0-1], 2
pinsrd xm6, [dstq +strideq*1+1], 3
pinsrd xm11, [dst8q+strideq*1-1], 3
shufps xm5, xm9, xm10, q2020
vinserti128 m5, xm11, 1
pmovzxbw m11, [leftq+5]
psrldq xm9, 2
psrldq xm10, 2
shufps xm9, xm10, q2020
movu m10, [blend_4x8_1+8]
vinserti128 m6, xm9, 1
vpblendvb m5, m11, m10
%endif
%else
lea r13, [blend_8x8_0+16]
movq xm5, [dstq +strideq*2-1]
movq xm9, [dst4q+strideq*0-1]
movq xm6, [top1q +1]
movq xm10, [dstq +strideq*0+1]
movhps xm5, [dstq +stride3q -1]
movhps xm9, [dst4q+strideq*1-1]
movhps xm6, [top2q +1]
movhps xm10, [dstq +strideq*1+1]
movu m11, [r13+hq*2*2+16*2]
vinserti128 m5, xm9, 1
vinserti128 m6, xm10, 1
vpblendvb m5, [rsp+gprsize+80+hq*8+64+8*2], m11
%endif
ret
.border_block:
DEFINE_ARGS dst, stride, left, top, pri, sec, stride3, dst4, edge
%define rstk rsp
%assign stack_offset stack_offset_entry
%if %1 == 4 && %2 == 8
PUSH r9
%assign regs_used 10
%else
%assign regs_used 9
%endif
%if STACK_ALIGNMENT < 32
PUSH r%+regs_used
%assign regs_used regs_used+1
%endif
ALLOC_STACK 2*16+(%2+4)*32, 16
%define px rsp+2*16+2*32
pcmpeqw m14, m14
psllw m14, 15 ; 0x8000
; prepare pixel buffers - body/right
%if %1 == 4
INIT_XMM avx2
%endif
%if %2 == 8
lea dst4q, [dstq+strideq*4]
%endif
lea stride3q, [strideq*3]
test edgeb, 2 ; have_right
jz .no_right
pmovzxbw m1, [dstq+strideq*0]
pmovzxbw m2, [dstq+strideq*1]
pmovzxbw m3, [dstq+strideq*2]
pmovzxbw m4, [dstq+stride3q]
mova [px+0*32], m1
mova [px+1*32], m2
mova [px+2*32], m3
mova [px+3*32], m4
%if %2 == 8
pmovzxbw m1, [dst4q+strideq*0]
pmovzxbw m2, [dst4q+strideq*1]
pmovzxbw m3, [dst4q+strideq*2]
pmovzxbw m4, [dst4q+stride3q]
mova [px+4*32], m1
mova [px+5*32], m2
mova [px+6*32], m3
mova [px+7*32], m4
%endif
jmp .body_done
.no_right:
%if %1 == 4
movd xm1, [dstq+strideq*0]
movd xm2, [dstq+strideq*1]
movd xm3, [dstq+strideq*2]
movd xm4, [dstq+stride3q]
pmovzxbw xm1, xm1
pmovzxbw xm2, xm2
pmovzxbw xm3, xm3
pmovzxbw xm4, xm4
movq [px+0*32], xm1
movq [px+1*32], xm2
movq [px+2*32], xm3
movq [px+3*32], xm4
%else
pmovzxbw xm1, [dstq+strideq*0]
pmovzxbw xm2, [dstq+strideq*1]
pmovzxbw xm3, [dstq+strideq*2]
pmovzxbw xm4, [dstq+stride3q]
mova [px+0*32], xm1
mova [px+1*32], xm2
mova [px+2*32], xm3
mova [px+3*32], xm4
%endif
movd [px+0*32+%1*2], xm14
movd [px+1*32+%1*2], xm14
movd [px+2*32+%1*2], xm14
movd [px+3*32+%1*2], xm14
%if %2 == 8
%if %1 == 4
movd xm1, [dst4q+strideq*0]
movd xm2, [dst4q+strideq*1]
movd xm3, [dst4q+strideq*2]
movd xm4, [dst4q+stride3q]
pmovzxbw xm1, xm1
pmovzxbw xm2, xm2
pmovzxbw xm3, xm3
pmovzxbw xm4, xm4
movq [px+4*32], xm1
movq [px+5*32], xm2
movq [px+6*32], xm3
movq [px+7*32], xm4
%else
pmovzxbw xm1, [dst4q+strideq*0]
pmovzxbw xm2, [dst4q+strideq*1]
pmovzxbw xm3, [dst4q+strideq*2]
pmovzxbw xm4, [dst4q+stride3q]
mova [px+4*32], xm1
mova [px+5*32], xm2
mova [px+6*32], xm3
mova [px+7*32], xm4
%endif
movd [px+4*32+%1*2], xm14
movd [px+5*32+%1*2], xm14
movd [px+6*32+%1*2], xm14
movd [px+7*32+%1*2], xm14
%endif
.body_done:
; top
test edgeb, 4 ; have_top
jz .no_top
test edgeb, 1 ; have_left
jz .top_no_left
test edgeb, 2 ; have_right
jz .top_no_right
pmovzxbw m1, [topq+strideq*0-(%1/2)]
pmovzxbw m2, [topq+strideq*1-(%1/2)]
movu [px-2*32-%1], m1
movu [px-1*32-%1], m2
jmp .top_done
.top_no_right:
pmovzxbw m1, [topq+strideq*0-%1]
pmovzxbw m2, [topq+strideq*1-%1]
movu [px-2*32-%1*2], m1
movu [px-1*32-%1*2], m2
movd [px-2*32+%1*2], xm14
movd [px-1*32+%1*2], xm14
jmp .top_done
.top_no_left:
test edgeb, 2 ; have_right
jz .top_no_left_right
pmovzxbw m1, [topq+strideq*0]
pmovzxbw m2, [topq+strideq*1]
mova [px-2*32+0], m1
mova [px-1*32+0], m2
movd [px-2*32-4], xm14
movd [px-1*32-4], xm14
jmp .top_done
.top_no_left_right:
%if %1 == 4
movd xm1, [topq+strideq*0]
pinsrd xm1, [topq+strideq*1], 1
pmovzxbw xm1, xm1
movq [px-2*32+0], xm1
movhps [px-1*32+0], xm1
%else
pmovzxbw xm1, [topq+strideq*0]
pmovzxbw xm2, [topq+strideq*1]
mova [px-2*32+0], xm1
mova [px-1*32+0], xm2
%endif
movd [px-2*32-4], xm14
movd [px-1*32-4], xm14
movd [px-2*32+%1*2], xm14
movd [px-1*32+%1*2], xm14
jmp .top_done
.no_top:
movu [px-2*32-%1], m14
movu [px-1*32-%1], m14
.top_done:
; left
test edgeb, 1 ; have_left
jz .no_left
pmovzxbw xm1, [leftq+ 0]
%if %2 == 8
pmovzxbw xm2, [leftq+ 8]
%endif
movd [px+0*32-4], xm1
pextrd [px+1*32-4], xm1, 1
pextrd [px+2*32-4], xm1, 2
pextrd [px+3*32-4], xm1, 3
%if %2 == 8
movd [px+4*32-4], xm2
pextrd [px+5*32-4], xm2, 1
pextrd [px+6*32-4], xm2, 2
pextrd [px+7*32-4], xm2, 3
%endif
jmp .left_done
.no_left:
movd [px+0*32-4], xm14
movd [px+1*32-4], xm14
movd [px+2*32-4], xm14
movd [px+3*32-4], xm14
%if %2 == 8
movd [px+4*32-4], xm14
movd [px+5*32-4], xm14
movd [px+6*32-4], xm14
movd [px+7*32-4], xm14
%endif
.left_done:
; bottom
DEFINE_ARGS dst, stride, dst8, dummy1, pri, sec, stride3, dummy3, edge
test edgeb, 8 ; have_bottom
jz .no_bottom
lea dst8q, [dstq+%2*strideq]
test edgeb, 1 ; have_left
jz .bottom_no_left
test edgeb, 2 ; have_right
jz .bottom_no_right
pmovzxbw m1, [dst8q-(%1/2)]
pmovzxbw m2, [dst8q+strideq-(%1/2)]
movu [px+(%2+0)*32-%1], m1
movu [px+(%2+1)*32-%1], m2
jmp .bottom_done
.bottom_no_right:
pmovzxbw m1, [dst8q-%1]
pmovzxbw m2, [dst8q+strideq-%1]
movu [px+(%2+0)*32-%1*2], m1
movu [px+(%2+1)*32-%1*2], m2
%if %1 == 8
movd [px+(%2-1)*32+%1*2], xm14 ; overwritten by previous movu
%endif
movd [px+(%2+0)*32+%1*2], xm14
movd [px+(%2+1)*32+%1*2], xm14
jmp .bottom_done
.bottom_no_left:
test edgeb, 2 ; have_right
jz .bottom_no_left_right
pmovzxbw m1, [dst8q]
pmovzxbw m2, [dst8q+strideq]
mova [px+(%2+0)*32+0], m1
mova [px+(%2+1)*32+0], m2
movd [px+(%2+0)*32-4], xm14
movd [px+(%2+1)*32-4], xm14
jmp .bottom_done
.bottom_no_left_right:
%if %1 == 4
movd xm1, [dst8q]
pinsrd xm1, [dst8q+strideq], 1
pmovzxbw xm1, xm1
movq [px+(%2+0)*32+0], xm1
movhps [px+(%2+1)*32+0], xm1
%else
pmovzxbw xm1, [dst8q]
pmovzxbw xm2, [dst8q+strideq]
mova [px+(%2+0)*32+0], xm1
mova [px+(%2+1)*32+0], xm2
%endif
movd [px+(%2+0)*32-4], xm14
movd [px+(%2+1)*32-4], xm14
movd [px+(%2+0)*32+%1*2], xm14
movd [px+(%2+1)*32+%1*2], xm14
jmp .bottom_done
.no_bottom:
movu [px+(%2+0)*32-%1], m14
movu [px+(%2+1)*32-%1], m14
.bottom_done:
; actual filter
INIT_YMM avx2
DEFINE_ARGS dst, stride, pridmp, damping, pri, secdmp, stride3, zero
%undef edged
; register to shuffle values into after packing
vbroadcasti128 m12, [shufb_lohi]
mov dampingd, r7m
xor zerod, zerod
movifnidn prid, prim
sub dampingd, 31
movifnidn secdmpd, secdmpm
or prid, 0
jz .border_sec_only
movd xm0, prid
lzcnt pridmpd, prid
add pridmpd, dampingd
cmovs pridmpd, zerod
mov [rsp+0], pridmpq ; pri_shift
or secdmpd, 0
jz .border_pri_only
movd xm1, secdmpd
lzcnt secdmpd, secdmpd
add secdmpd, dampingd
cmovs secdmpd, zerod
mov [rsp+8], secdmpq ; sec_shift
DEFINE_ARGS dst, stride, pridmp, table, pri, secdmp, stride3
lea tableq, [tap_table]
vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask
vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask
; pri/sec_taps[k] [4 total]
DEFINE_ARGS dst, stride, dir, table, pri, sec, stride3
vpbroadcastb m0, xm0 ; pri_strength
vpbroadcastb m1, xm1 ; sec_strength
and prid, 1
lea priq, [tableq+priq*2+8] ; pri_taps
lea secq, [tableq+12] ; sec_taps
BORDER_PREP_REGS %1, %2
%if %1*%2*2/mmsize > 1
.border_v_loop:
%endif
BORDER_LOAD_BLOCK %1, %2, 1
.border_k_loop:
vpbroadcastb m2, [priq+kq] ; pri_taps
vpbroadcastb m3, [secq+kq] ; sec_taps
ACCUMULATE_TAP_WORD 0*2, [rsp+0], m13, m0, m2, %1, 1
ACCUMULATE_TAP_WORD 2*2, [rsp+8], m14, m1, m3, %1, 1
ACCUMULATE_TAP_WORD 6*2, [rsp+8], m14, m1, m3, %1, 1
dec kq
jge .border_k_loop
vpbroadcastd m10, [pw_2048]
BORDER_ADJUST_PIXEL %1, m10, 1
%if %1*%2*2/mmsize > 1
%define vloop_lines (mmsize/(%1*2))
lea dstq, [dstq+strideq*vloop_lines]
add stkq, 32*vloop_lines
dec hd
jg .border_v_loop
%endif
RET
.border_pri_only:
DEFINE_ARGS dst, stride, pridmp, table, pri, _, stride3
lea tableq, [tap_table]
vpbroadcastb m13, [tableq+pridmpq] ; pri_shift_mask
DEFINE_ARGS dst, stride, dir, table, pri, _, stride3
vpbroadcastb m0, xm0 ; pri_strength
and prid, 1
lea priq, [tableq+priq*2+8] ; pri_taps
BORDER_PREP_REGS %1, %2
vpbroadcastd m1, [pw_2048]
%if %1*%2*2/mmsize > 1
.border_pri_v_loop:
%endif
BORDER_LOAD_BLOCK %1, %2
.border_pri_k_loop:
vpbroadcastb m2, [priq+kq] ; pri_taps
ACCUMULATE_TAP_WORD 0*2, [rsp+0], m13, m0, m2, %1
dec kq
jge .border_pri_k_loop
BORDER_ADJUST_PIXEL %1, m1
%if %1*%2*2/mmsize > 1
%define vloop_lines (mmsize/(%1*2))
lea dstq, [dstq+strideq*vloop_lines]
add stkq, 32*vloop_lines
dec hd
jg .border_pri_v_loop
%endif
RET
.border_sec_only:
DEFINE_ARGS dst, stride, _, damping, _, secdmp, stride3, zero
movd xm1, secdmpd
lzcnt secdmpd, secdmpd
add secdmpd, dampingd
cmovs secdmpd, zerod
mov [rsp+8], secdmpq ; sec_shift
DEFINE_ARGS dst, stride, _, table, _, secdmp, stride3
lea tableq, [tap_table]
vpbroadcastb m14, [tableq+secdmpq] ; sec_shift_mask
DEFINE_ARGS dst, stride, dir, table, _, sec, stride3
vpbroadcastb m1, xm1 ; sec_strength
lea secq, [tableq+12] ; sec_taps
BORDER_PREP_REGS %1, %2
vpbroadcastd m0, [pw_2048]
%if %1*%2*2/mmsize > 1
.border_sec_v_loop:
%endif
BORDER_LOAD_BLOCK %1, %2
.border_sec_k_loop:
vpbroadcastb m3, [secq+kq] ; sec_taps
ACCUMULATE_TAP_WORD 2*2, [rsp+8], m14, m1, m3, %1
ACCUMULATE_TAP_WORD 6*2, [rsp+8], m14, m1, m3, %1
dec kq
jge .border_sec_k_loop
BORDER_ADJUST_PIXEL %1, m0
%if %1*%2*2/mmsize > 1
%define vloop_lines (mmsize/(%1*2))
lea dstq, [dstq+strideq*vloop_lines]
add stkq, 32*vloop_lines
dec hd
jg .border_sec_v_loop
%endif
RET
%endmacro
CDEF_FILTER 8, 8
CDEF_FILTER 4, 8
CDEF_FILTER 4, 4
INIT_YMM avx2
cglobal cdef_dir, 3, 4, 15, src, stride, var, stride3
lea stride3q, [strideq*3]
movq xm0, [srcq+strideq*0]
movq xm1, [srcq+strideq*1]
movq xm2, [srcq+strideq*2]
movq xm3, [srcq+stride3q]
lea srcq, [srcq+strideq*4]
vpbroadcastq m4, [srcq+strideq*0]
vpbroadcastq m5, [srcq+strideq*1]
vpbroadcastq m6, [srcq+strideq*2]
vpbroadcastq m7, [srcq+stride3q]
vpbroadcastd m8, [pw_128]
pxor m9, m9
vpblendd m0, m0, m7, 0xf0
vpblendd m1, m1, m6, 0xf0
vpblendd m2, m2, m5, 0xf0
vpblendd m3, m3, m4, 0xf0
punpcklbw m0, m9
punpcklbw m1, m9
punpcklbw m2, m9
punpcklbw m3, m9
psubw m0, m8
psubw m1, m8
psubw m2, m8
psubw m3, m8
; shuffle registers to generate partial_sum_diag[0-1] together
vpermq m7, m0, q1032
vpermq m6, m1, q1032
vpermq m5, m2, q1032
vpermq m4, m3, q1032
; start with partial_sum_hv[0-1]
paddw m8, m0, m1
paddw m9, m2, m3
phaddw m10, m0, m1
phaddw m11, m2, m3
paddw m8, m9
phaddw m10, m11
vextracti128 xm9, m8, 1
vextracti128 xm11, m10, 1
paddw xm8, xm9 ; partial_sum_hv[1]
phaddw xm10, xm11 ; partial_sum_hv[0]
vinserti128 m8, xm10, 1
vpbroadcastd m9, [div_table+44]
pmaddwd m8, m8
pmulld m8, m9 ; cost6[2a-d] | cost2[a-d]
; create aggregates [lower half]:
; m9 = m0:01234567+m1:x0123456+m2:xx012345+m3:xxx01234+
; m4:xxxx0123+m5:xxxxx012+m6:xxxxxx01+m7:xxxxxxx0
; m10= m1:7xxxxxxx+m2:67xxxxxx+m3:567xxxxx+
; m4:4567xxxx+m5:34567xxx+m6:234567xx+m7:1234567x
; and [upper half]:
; m9 = m0:xxxxxxx0+m1:xxxxxx01+m2:xxxxx012+m3:xxxx0123+
; m4:xxx01234+m5:xx012345+m6:x0123456+m7:01234567
; m10= m0:1234567x+m1:234567xx+m2:34567xxx+m3:4567xxxx+
; m4:567xxxxx+m5:67xxxxxx+m6:7xxxxxxx
; and then shuffle m11 [shufw_6543210x], unpcklwd, pmaddwd, pmulld, paddd
pslldq m9, m1, 2
psrldq m10, m1, 14
pslldq m11, m2, 4
psrldq m12, m2, 12
pslldq m13, m3, 6
psrldq m14, m3, 10
paddw m9, m11
paddw m10, m12
paddw m9, m13
paddw m10, m14
pslldq m11, m4, 8
psrldq m12, m4, 8
pslldq m13, m5, 10
psrldq m14, m5, 6
paddw m9, m11
paddw m10, m12
paddw m9, m13
paddw m10, m14
pslldq m11, m6, 12
psrldq m12, m6, 4
pslldq m13, m7, 14
psrldq m14, m7, 2
paddw m9, m11
paddw m10, m12
paddw m9, m13
paddw m10, m14 ; partial_sum_diag[0/1][8-14,zero]
vbroadcasti128 m14, [shufw_6543210x]
vbroadcasti128 m13, [div_table+16]
vbroadcasti128 m12, [div_table+0]
paddw m9, m0 ; partial_sum_diag[0/1][0-7]
pshufb m10, m14
punpckhwd m11, m9, m10
punpcklwd m9, m10
pmaddwd m11, m11
pmaddwd m9, m9
pmulld m11, m13
pmulld m9, m12
paddd m9, m11 ; cost0[a-d] | cost4[a-d]
; merge horizontally and vertically for partial_sum_alt[0-3]
paddw m10, m0, m1
paddw m11, m2, m3
paddw m12, m4, m5
paddw m13, m6, m7
phaddw m0, m4
phaddw m1, m5
phaddw m2, m6
phaddw m3, m7
; create aggregates [lower half]:
; m4 = m10:01234567+m11:x0123456+m12:xx012345+m13:xxx01234
; m11= m11:7xxxxxxx+m12:67xxxxxx+m13:567xxxxx
; and [upper half]:
; m4 = m10:xxx01234+m11:xx012345+m12:x0123456+m13:01234567
; m11= m10:567xxxxx+m11:67xxxxxx+m12:7xxxxxxx
; and then pshuflw m11 3012, unpcklwd, pmaddwd, pmulld, paddd
pslldq m4, m11, 2
psrldq m11, 14
pslldq m5, m12, 4
psrldq m12, 12
pslldq m6, m13, 6
psrldq m13, 10
paddw m4, m10
paddw m11, m12
vpbroadcastd m12, [div_table+44]
paddw m5, m6
paddw m11, m13 ; partial_sum_alt[3/2] right
vbroadcasti128 m13, [div_table+32]
paddw m4, m5 ; partial_sum_alt[3/2] left
pshuflw m5, m11, q3012
punpckhwd m6, m11, m4
punpcklwd m4, m5
pmaddwd m6, m6
pmaddwd m4, m4
pmulld m6, m12
pmulld m4, m13
paddd m4, m6 ; cost7[a-d] | cost5[a-d]
; create aggregates [lower half]:
; m5 = m0:01234567+m1:x0123456+m2:xx012345+m3:xxx01234
; m1 = m1:7xxxxxxx+m2:67xxxxxx+m3:567xxxxx
; and [upper half]:
; m5 = m0:xxx01234+m1:xx012345+m2:x0123456+m3:01234567
; m1 = m0:567xxxxx+m1:67xxxxxx+m2:7xxxxxxx
; and then pshuflw m1 3012, unpcklwd, pmaddwd, pmulld, paddd
pslldq m5, m1, 2
psrldq m1, 14
pslldq m6, m2, 4
psrldq m2, 12
pslldq m7, m3, 6
psrldq m3, 10
paddw m5, m0
paddw m1, m2
paddw m6, m7
paddw m1, m3 ; partial_sum_alt[0/1] right
paddw m5, m6 ; partial_sum_alt[0/1] left
pshuflw m0, m1, q3012
punpckhwd m1, m5
punpcklwd m5, m0
pmaddwd m1, m1
pmaddwd m5, m5
pmulld m1, m12
pmulld m5, m13
paddd m5, m1 ; cost1[a-d] | cost3[a-d]
mova xm0, [pd_47130256+ 16]
mova m1, [pd_47130256]
phaddd m9, m8
phaddd m5, m4
phaddd m9, m5
vpermd m0, m9 ; cost[0-3]
vpermd m1, m9 ; cost[4-7] | cost[0-3]
; now find the best cost
pmaxsd xm2, xm0, xm1
pshufd xm3, xm2, q1032
pmaxsd xm2, xm3
pshufd xm3, xm2, q2301
pmaxsd xm2, xm3 ; best cost
; find the idx using minpos
; make everything other than the best cost negative via subtraction
; find the min of unsigned 16-bit ints to sort out the negative values
psubd xm4, xm1, xm2
psubd xm3, xm0, xm2
packssdw xm3, xm4
phminposuw xm3, xm3
; convert idx to 32-bits
psrld xm3, 16
movd eax, xm3
; get idx^4 complement
vpermd m3, m1
psubd xm2, xm3
psrld xm2, 10
movd [varq], xm2
RET
%endif ; ARCH_X86_64
| endlessm/chromium-browser | third_party/dav1d/libdav1d/src/x86/cdef_avx2.asm | Assembly | bsd-3-clause | 59,002 |
; =============================================================================
; Pure64 -- a 64-bit OS loader written in Assembly for x86-64 systems
; Copyright (C) 2008-2012 Return Infinity -- see LICENSE.TXT
;
; INIT IO-APIC
; =============================================================================
global init_ioapic
os_IOAPICAddress: dq 0x0
init_ioapic:
push rbp
mov rbp, rsp
mov [os_IOAPICAddress], rdi
mov al, 0x70 ; IMCR access
out 0x22, al
mov al, 0x01 ; set bit 1 for SMP mode
out 0x23, al
xor eax, eax
mov rcx, 1 ; Register 1 - IOAPIC VERSION REGISTER
call ioapic_reg_read
shr eax, 16 ; Extract bytes 16-23 (Maximum Redirection Entry)
and eax, 0xFF ; Clear bits 16-31
add eax, 1
mov rcx, rax
xor rax, rax
mov eax, dword [rsi+0x20] ; Grab the BSP APIC ID; stored in bits 31:24
shr rax, 24 ; AL now holds the BSP CPU's APIC ID
shl rax, 56
bts rax, 16 ; Interrupt Mask Enabled
initentry: ; Initialize all entries 1:1
dec rcx
call ioapic_entry_write
cmp rcx, 0
jne initentry
; Enable the Keyboard
mov rcx, 1 ; IRQ value
mov rax, 0x21 ; Interrupt value
call ioapic_entry_write
; Enable the RTC
mov rcx, 8 ; IRQ value
mov rax, 0x28 ; Interrupt value
call ioapic_entry_write
; Set the periodic flag in the RTC
mov al, 0x0B ; Status Register B
out 0x70, al ; Select the address
in al, 0x71 ; Read the current settings
push rax
mov al, 0x0B ; Status Register B
out 0x70, al ; Select the address
pop rax
bts ax, 6 ; Set Periodic(6)
out 0x71, al ; Write the new settings
sti ; Enable interrupts
; Acknowledge the RTC
mov al, 0x0C ; Status Register C
out 0x70, al ; Select the address
in al, 0x71 ; Read the current settings
pop rbp
ret
; -----------------------------------------------------------------------------
; ioapic_reg_write -- Write to an I/O APIC register
; IN: EAX = Value to write
; ECX = Index of register
; OUT: Nothing. All registers preserved
ioapic_reg_write:
push rsi
mov rsi, [os_IOAPICAddress]
mov dword [rsi], ecx ; Write index to register selector
mov dword [rsi + 0x10], eax ; Write data to window register
pop rsi
ret
; -----------------------------------------------------------------------------
; -----------------------------------------------------------------------------
; ioapic_reg_read -- Read from an I/O APIC register
; IN: ECX = Index of register
; OUT: EAX = Value of register
; All other registers preserved
ioapic_reg_read:
push rsi
mov rsi, [os_IOAPICAddress]
mov dword [rsi], ecx ; Write index to register selector
mov eax, dword [rsi + 0x10] ; Read data from window register
pop rsi
ret
; -----------------------------------------------------------------------------
; -----------------------------------------------------------------------------
; ioapic_entry_write -- Write to an I/O APIC entry in the redirection table
; IN: RAX = Data to write to entry
; ECX = Index of the entry
; OUT: Nothing. All registers preserved
ioapic_entry_write:
push rax
push rcx
; Calculate index for lower DWORD
shl rcx, 1 ; Quick multiply by 2
add rcx, 0x10 ; IO Redirection tables start at 0x10
; Write lower DWORD
call ioapic_reg_write
; Write higher DWORD
shr rax, 32
add rcx, 1
call ioapic_reg_write
pop rcx
pop rax
ret
; -----------------------------------------------------------------------------
; -----------------------------------------------------------------------------
; ioapic_entry_read -- Read an I/O APIC entry from the redirection table
; IN: ECX = Index of the entry
; OUT: RAX = Data that was read
; All other registers preserved
ioapic_entry_read:
push rbx
push rcx
; Calculate index for lower DWORD
shl rcx, 1 ; Quick multiply by 2
add rcx, 0x10 ; IO Redirection tables start at 0x10
; Read lower DWORD
call ioapic_reg_read
mov rbx, rax
; Read higher DWORD
add rcx, 1
call ioapic_reg_read
; Combine
shr rax, 32
or rbx, rax
xchg rbx, rax
pop rcx
pop rbx
ret
; -----------------------------------------------------------------------------
; =============================================================================
; EOF
| Izikiel/intel_multicore | DeliriOS_64bits/common_code/init_ioapic.asm | Assembly | mit | 4,173 |
// Module name: PA_LOAD_SAVE_NV12
.kernel PA_LOAD_SAVE_NV12
.code
#include "SetupVPKernel.asm"
#include "Multiple_Loop_Head.asm"
#include "PA_Load_8x8.asm"
#include "PL8x8_PL8x4.asm"
#include "PL8x4_Save_NV12.asm"
#include "Multiple_Loop.asm"
END_THREAD // End of Thread
.end_code
.end_kernel
// end of nv12_load_save_pl1.asm
| chenxianqin/vaapi-intel-driver | src/shaders/post_processing/gen5_6/pa_load_save_nv12.asm | Assembly | mit | 343 |
start = $120c
org $351
model_detection:
lda #vic_unexpanded
sta model
; Test on +3K.
ldx #vic_3k
ldy #$04
jsr check_model
; Test on +8K.
ldx #vic_8k
ldy #$20
jsr check_model
; Test on +16K.
ldx #vic_16k
ldy #$40
jsr check_model
; Test on +24K.
ldx #vic_24k
ldy #$60
jsr check_model
; Relocate for unexpanded.
lda model
bne +n
lda #$10
bne relocate
; No relocation for other than +3K.
n: lsr
bne +done
lda #$04
relocate:
sta @(+ +p 2)
ldx #0
ldy #2
p: lda $ff01,x
q: sta $1201,x
inx
bne -p
inc @(+ -p 2)
inc @(+ -q 2)
dey
bne -p
done:
jmp start
check_model:
sty @(+ +p 2)
sty @(+ +q 2)
dey
tya
p: sta $1200
q: cmp $1200
bne +n
txa
ora model
sta model
n: rts
| SvenMichaelKlose/nipkow | src/model-detection.asm | Assembly | mit | 853 |
_usertests: ファイル形式 elf32-i386
セクション .text の逆アセンブル:
00000000 <iputtest>:
0: 55 push %ebp
1: 89 e5 mov %esp,%ebp
3: 83 ec 18 sub $0x18,%esp
6: a1 ec 62 00 00 mov 0x62ec,%eax
b: c7 44 24 04 42 44 00 movl $0x4442,0x4(%esp)
12: 00
13: 89 04 24 mov %eax,(%esp)
16: e8 42 40 00 00 call 405d <printf>
1b: c7 04 24 4d 44 00 00 movl $0x444d,(%esp)
22: e8 f6 3e 00 00 call 3f1d <mkdir>
27: 85 c0 test %eax,%eax
29: 79 1a jns 45 <iputtest+0x45>
2b: a1 ec 62 00 00 mov 0x62ec,%eax
30: c7 44 24 04 55 44 00 movl $0x4455,0x4(%esp)
37: 00
38: 89 04 24 mov %eax,(%esp)
3b: e8 1d 40 00 00 call 405d <printf>
40: e8 70 3e 00 00 call 3eb5 <exit>
45: c7 04 24 4d 44 00 00 movl $0x444d,(%esp)
4c: e8 d4 3e 00 00 call 3f25 <chdir>
51: 85 c0 test %eax,%eax
53: 79 1a jns 6f <iputtest+0x6f>
55: a1 ec 62 00 00 mov 0x62ec,%eax
5a: c7 44 24 04 63 44 00 movl $0x4463,0x4(%esp)
61: 00
62: 89 04 24 mov %eax,(%esp)
65: e8 f3 3f 00 00 call 405d <printf>
6a: e8 46 3e 00 00 call 3eb5 <exit>
6f: c7 04 24 79 44 00 00 movl $0x4479,(%esp)
76: e8 8a 3e 00 00 call 3f05 <unlink>
7b: 85 c0 test %eax,%eax
7d: 79 1a jns 99 <iputtest+0x99>
7f: a1 ec 62 00 00 mov 0x62ec,%eax
84: c7 44 24 04 84 44 00 movl $0x4484,0x4(%esp)
8b: 00
8c: 89 04 24 mov %eax,(%esp)
8f: e8 c9 3f 00 00 call 405d <printf>
94: e8 1c 3e 00 00 call 3eb5 <exit>
99: c7 04 24 9e 44 00 00 movl $0x449e,(%esp)
a0: e8 80 3e 00 00 call 3f25 <chdir>
a5: 85 c0 test %eax,%eax
a7: 79 1a jns c3 <iputtest+0xc3>
a9: a1 ec 62 00 00 mov 0x62ec,%eax
ae: c7 44 24 04 a0 44 00 movl $0x44a0,0x4(%esp)
b5: 00
b6: 89 04 24 mov %eax,(%esp)
b9: e8 9f 3f 00 00 call 405d <printf>
be: e8 f2 3d 00 00 call 3eb5 <exit>
c3: a1 ec 62 00 00 mov 0x62ec,%eax
c8: c7 44 24 04 b0 44 00 movl $0x44b0,0x4(%esp)
cf: 00
d0: 89 04 24 mov %eax,(%esp)
d3: e8 85 3f 00 00 call 405d <printf>
d8: c9 leave
d9: c3 ret
000000da <exitiputtest>:
da: 55 push %ebp
db: 89 e5 mov %esp,%ebp
dd: 83 ec 28 sub $0x28,%esp
e0: a1 ec 62 00 00 mov 0x62ec,%eax
e5: c7 44 24 04 be 44 00 movl $0x44be,0x4(%esp)
ec: 00
ed: 89 04 24 mov %eax,(%esp)
f0: e8 68 3f 00 00 call 405d <printf>
f5: e8 b3 3d 00 00 call 3ead <fork>
fa: 89 45 f4 mov %eax,-0xc(%ebp)
fd: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
101: 79 1a jns 11d <exitiputtest+0x43>
103: a1 ec 62 00 00 mov 0x62ec,%eax
108: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
10f: 00
110: 89 04 24 mov %eax,(%esp)
113: e8 45 3f 00 00 call 405d <printf>
118: e8 98 3d 00 00 call 3eb5 <exit>
11d: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
121: 0f 85 83 00 00 00 jne 1aa <exitiputtest+0xd0>
127: c7 04 24 4d 44 00 00 movl $0x444d,(%esp)
12e: e8 ea 3d 00 00 call 3f1d <mkdir>
133: 85 c0 test %eax,%eax
135: 79 1a jns 151 <exitiputtest+0x77>
137: a1 ec 62 00 00 mov 0x62ec,%eax
13c: c7 44 24 04 55 44 00 movl $0x4455,0x4(%esp)
143: 00
144: 89 04 24 mov %eax,(%esp)
147: e8 11 3f 00 00 call 405d <printf>
14c: e8 64 3d 00 00 call 3eb5 <exit>
151: c7 04 24 4d 44 00 00 movl $0x444d,(%esp)
158: e8 c8 3d 00 00 call 3f25 <chdir>
15d: 85 c0 test %eax,%eax
15f: 79 1a jns 17b <exitiputtest+0xa1>
161: a1 ec 62 00 00 mov 0x62ec,%eax
166: c7 44 24 04 da 44 00 movl $0x44da,0x4(%esp)
16d: 00
16e: 89 04 24 mov %eax,(%esp)
171: e8 e7 3e 00 00 call 405d <printf>
176: e8 3a 3d 00 00 call 3eb5 <exit>
17b: c7 04 24 79 44 00 00 movl $0x4479,(%esp)
182: e8 7e 3d 00 00 call 3f05 <unlink>
187: 85 c0 test %eax,%eax
189: 79 1a jns 1a5 <exitiputtest+0xcb>
18b: a1 ec 62 00 00 mov 0x62ec,%eax
190: c7 44 24 04 84 44 00 movl $0x4484,0x4(%esp)
197: 00
198: 89 04 24 mov %eax,(%esp)
19b: e8 bd 3e 00 00 call 405d <printf>
1a0: e8 10 3d 00 00 call 3eb5 <exit>
1a5: e8 0b 3d 00 00 call 3eb5 <exit>
1aa: e8 0e 3d 00 00 call 3ebd <wait>
1af: a1 ec 62 00 00 mov 0x62ec,%eax
1b4: c7 44 24 04 ee 44 00 movl $0x44ee,0x4(%esp)
1bb: 00
1bc: 89 04 24 mov %eax,(%esp)
1bf: e8 99 3e 00 00 call 405d <printf>
1c4: c9 leave
1c5: c3 ret
000001c6 <openiputtest>:
1c6: 55 push %ebp
1c7: 89 e5 mov %esp,%ebp
1c9: 83 ec 28 sub $0x28,%esp
1cc: a1 ec 62 00 00 mov 0x62ec,%eax
1d1: c7 44 24 04 00 45 00 movl $0x4500,0x4(%esp)
1d8: 00
1d9: 89 04 24 mov %eax,(%esp)
1dc: e8 7c 3e 00 00 call 405d <printf>
1e1: c7 04 24 0f 45 00 00 movl $0x450f,(%esp)
1e8: e8 30 3d 00 00 call 3f1d <mkdir>
1ed: 85 c0 test %eax,%eax
1ef: 79 1a jns 20b <openiputtest+0x45>
1f1: a1 ec 62 00 00 mov 0x62ec,%eax
1f6: c7 44 24 04 15 45 00 movl $0x4515,0x4(%esp)
1fd: 00
1fe: 89 04 24 mov %eax,(%esp)
201: e8 57 3e 00 00 call 405d <printf>
206: e8 aa 3c 00 00 call 3eb5 <exit>
20b: e8 9d 3c 00 00 call 3ead <fork>
210: 89 45 f4 mov %eax,-0xc(%ebp)
213: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
217: 79 1a jns 233 <openiputtest+0x6d>
219: a1 ec 62 00 00 mov 0x62ec,%eax
21e: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
225: 00
226: 89 04 24 mov %eax,(%esp)
229: e8 2f 3e 00 00 call 405d <printf>
22e: e8 82 3c 00 00 call 3eb5 <exit>
233: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
237: 75 3c jne 275 <openiputtest+0xaf>
239: c7 44 24 04 02 00 00 movl $0x2,0x4(%esp)
240: 00
241: c7 04 24 0f 45 00 00 movl $0x450f,(%esp)
248: e8 a8 3c 00 00 call 3ef5 <open>
24d: 89 45 f0 mov %eax,-0x10(%ebp)
250: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
254: 78 1a js 270 <openiputtest+0xaa>
256: a1 ec 62 00 00 mov 0x62ec,%eax
25b: c7 44 24 04 2c 45 00 movl $0x452c,0x4(%esp)
262: 00
263: 89 04 24 mov %eax,(%esp)
266: e8 f2 3d 00 00 call 405d <printf>
26b: e8 45 3c 00 00 call 3eb5 <exit>
270: e8 40 3c 00 00 call 3eb5 <exit>
275: c7 04 24 01 00 00 00 movl $0x1,(%esp)
27c: e8 c4 3c 00 00 call 3f45 <sleep>
281: c7 04 24 0f 45 00 00 movl $0x450f,(%esp)
288: e8 78 3c 00 00 call 3f05 <unlink>
28d: 85 c0 test %eax,%eax
28f: 74 1a je 2ab <openiputtest+0xe5>
291: a1 ec 62 00 00 mov 0x62ec,%eax
296: c7 44 24 04 50 45 00 movl $0x4550,0x4(%esp)
29d: 00
29e: 89 04 24 mov %eax,(%esp)
2a1: e8 b7 3d 00 00 call 405d <printf>
2a6: e8 0a 3c 00 00 call 3eb5 <exit>
2ab: e8 0d 3c 00 00 call 3ebd <wait>
2b0: a1 ec 62 00 00 mov 0x62ec,%eax
2b5: c7 44 24 04 5f 45 00 movl $0x455f,0x4(%esp)
2bc: 00
2bd: 89 04 24 mov %eax,(%esp)
2c0: e8 98 3d 00 00 call 405d <printf>
2c5: c9 leave
2c6: c3 ret
000002c7 <opentest>:
2c7: 55 push %ebp
2c8: 89 e5 mov %esp,%ebp
2ca: 83 ec 28 sub $0x28,%esp
2cd: a1 ec 62 00 00 mov 0x62ec,%eax
2d2: c7 44 24 04 71 45 00 movl $0x4571,0x4(%esp)
2d9: 00
2da: 89 04 24 mov %eax,(%esp)
2dd: e8 7b 3d 00 00 call 405d <printf>
2e2: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
2e9: 00
2ea: c7 04 24 2c 44 00 00 movl $0x442c,(%esp)
2f1: e8 ff 3b 00 00 call 3ef5 <open>
2f6: 89 45 f4 mov %eax,-0xc(%ebp)
2f9: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2fd: 79 1a jns 319 <opentest+0x52>
2ff: a1 ec 62 00 00 mov 0x62ec,%eax
304: c7 44 24 04 7c 45 00 movl $0x457c,0x4(%esp)
30b: 00
30c: 89 04 24 mov %eax,(%esp)
30f: e8 49 3d 00 00 call 405d <printf>
314: e8 9c 3b 00 00 call 3eb5 <exit>
319: 8b 45 f4 mov -0xc(%ebp),%eax
31c: 89 04 24 mov %eax,(%esp)
31f: e8 b9 3b 00 00 call 3edd <close>
324: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
32b: 00
32c: c7 04 24 8f 45 00 00 movl $0x458f,(%esp)
333: e8 bd 3b 00 00 call 3ef5 <open>
338: 89 45 f4 mov %eax,-0xc(%ebp)
33b: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
33f: 78 1a js 35b <opentest+0x94>
341: a1 ec 62 00 00 mov 0x62ec,%eax
346: c7 44 24 04 9c 45 00 movl $0x459c,0x4(%esp)
34d: 00
34e: 89 04 24 mov %eax,(%esp)
351: e8 07 3d 00 00 call 405d <printf>
356: e8 5a 3b 00 00 call 3eb5 <exit>
35b: a1 ec 62 00 00 mov 0x62ec,%eax
360: c7 44 24 04 ba 45 00 movl $0x45ba,0x4(%esp)
367: 00
368: 89 04 24 mov %eax,(%esp)
36b: e8 ed 3c 00 00 call 405d <printf>
370: c9 leave
371: c3 ret
00000372 <writetest>:
372: 55 push %ebp
373: 89 e5 mov %esp,%ebp
375: 83 ec 28 sub $0x28,%esp
378: a1 ec 62 00 00 mov 0x62ec,%eax
37d: c7 44 24 04 c8 45 00 movl $0x45c8,0x4(%esp)
384: 00
385: 89 04 24 mov %eax,(%esp)
388: e8 d0 3c 00 00 call 405d <printf>
38d: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
394: 00
395: c7 04 24 d9 45 00 00 movl $0x45d9,(%esp)
39c: e8 54 3b 00 00 call 3ef5 <open>
3a1: 89 45 f0 mov %eax,-0x10(%ebp)
3a4: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
3a8: 78 21 js 3cb <writetest+0x59>
3aa: a1 ec 62 00 00 mov 0x62ec,%eax
3af: c7 44 24 04 df 45 00 movl $0x45df,0x4(%esp)
3b6: 00
3b7: 89 04 24 mov %eax,(%esp)
3ba: e8 9e 3c 00 00 call 405d <printf>
3bf: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
3c6: e9 a0 00 00 00 jmp 46b <writetest+0xf9>
3cb: a1 ec 62 00 00 mov 0x62ec,%eax
3d0: c7 44 24 04 fa 45 00 movl $0x45fa,0x4(%esp)
3d7: 00
3d8: 89 04 24 mov %eax,(%esp)
3db: e8 7d 3c 00 00 call 405d <printf>
3e0: e8 d0 3a 00 00 call 3eb5 <exit>
3e5: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
3ec: 00
3ed: c7 44 24 04 16 46 00 movl $0x4616,0x4(%esp)
3f4: 00
3f5: 8b 45 f0 mov -0x10(%ebp),%eax
3f8: 89 04 24 mov %eax,(%esp)
3fb: e8 d5 3a 00 00 call 3ed5 <write>
400: 83 f8 0a cmp $0xa,%eax
403: 74 21 je 426 <writetest+0xb4>
405: a1 ec 62 00 00 mov 0x62ec,%eax
40a: 8b 55 f4 mov -0xc(%ebp),%edx
40d: 89 54 24 08 mov %edx,0x8(%esp)
411: c7 44 24 04 24 46 00 movl $0x4624,0x4(%esp)
418: 00
419: 89 04 24 mov %eax,(%esp)
41c: e8 3c 3c 00 00 call 405d <printf>
421: e8 8f 3a 00 00 call 3eb5 <exit>
426: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
42d: 00
42e: c7 44 24 04 48 46 00 movl $0x4648,0x4(%esp)
435: 00
436: 8b 45 f0 mov -0x10(%ebp),%eax
439: 89 04 24 mov %eax,(%esp)
43c: e8 94 3a 00 00 call 3ed5 <write>
441: 83 f8 0a cmp $0xa,%eax
444: 74 21 je 467 <writetest+0xf5>
446: a1 ec 62 00 00 mov 0x62ec,%eax
44b: 8b 55 f4 mov -0xc(%ebp),%edx
44e: 89 54 24 08 mov %edx,0x8(%esp)
452: c7 44 24 04 54 46 00 movl $0x4654,0x4(%esp)
459: 00
45a: 89 04 24 mov %eax,(%esp)
45d: e8 fb 3b 00 00 call 405d <printf>
462: e8 4e 3a 00 00 call 3eb5 <exit>
467: 83 45 f4 01 addl $0x1,-0xc(%ebp)
46b: 83 7d f4 63 cmpl $0x63,-0xc(%ebp)
46f: 0f 8e 70 ff ff ff jle 3e5 <writetest+0x73>
475: a1 ec 62 00 00 mov 0x62ec,%eax
47a: c7 44 24 04 78 46 00 movl $0x4678,0x4(%esp)
481: 00
482: 89 04 24 mov %eax,(%esp)
485: e8 d3 3b 00 00 call 405d <printf>
48a: 8b 45 f0 mov -0x10(%ebp),%eax
48d: 89 04 24 mov %eax,(%esp)
490: e8 48 3a 00 00 call 3edd <close>
495: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
49c: 00
49d: c7 04 24 d9 45 00 00 movl $0x45d9,(%esp)
4a4: e8 4c 3a 00 00 call 3ef5 <open>
4a9: 89 45 f0 mov %eax,-0x10(%ebp)
4ac: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
4b0: 78 3e js 4f0 <writetest+0x17e>
4b2: a1 ec 62 00 00 mov 0x62ec,%eax
4b7: c7 44 24 04 83 46 00 movl $0x4683,0x4(%esp)
4be: 00
4bf: 89 04 24 mov %eax,(%esp)
4c2: e8 96 3b 00 00 call 405d <printf>
4c7: c7 44 24 08 d0 07 00 movl $0x7d0,0x8(%esp)
4ce: 00
4cf: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
4d6: 00
4d7: 8b 45 f0 mov -0x10(%ebp),%eax
4da: 89 04 24 mov %eax,(%esp)
4dd: e8 eb 39 00 00 call 3ecd <read>
4e2: 89 45 f4 mov %eax,-0xc(%ebp)
4e5: 81 7d f4 d0 07 00 00 cmpl $0x7d0,-0xc(%ebp)
4ec: 75 4e jne 53c <writetest+0x1ca>
4ee: eb 1a jmp 50a <writetest+0x198>
4f0: a1 ec 62 00 00 mov 0x62ec,%eax
4f5: c7 44 24 04 9c 46 00 movl $0x469c,0x4(%esp)
4fc: 00
4fd: 89 04 24 mov %eax,(%esp)
500: e8 58 3b 00 00 call 405d <printf>
505: e8 ab 39 00 00 call 3eb5 <exit>
50a: a1 ec 62 00 00 mov 0x62ec,%eax
50f: c7 44 24 04 b7 46 00 movl $0x46b7,0x4(%esp)
516: 00
517: 89 04 24 mov %eax,(%esp)
51a: e8 3e 3b 00 00 call 405d <printf>
51f: 8b 45 f0 mov -0x10(%ebp),%eax
522: 89 04 24 mov %eax,(%esp)
525: e8 b3 39 00 00 call 3edd <close>
52a: c7 04 24 d9 45 00 00 movl $0x45d9,(%esp)
531: e8 cf 39 00 00 call 3f05 <unlink>
536: 85 c0 test %eax,%eax
538: 79 36 jns 570 <writetest+0x1fe>
53a: eb 1a jmp 556 <writetest+0x1e4>
53c: a1 ec 62 00 00 mov 0x62ec,%eax
541: c7 44 24 04 ca 46 00 movl $0x46ca,0x4(%esp)
548: 00
549: 89 04 24 mov %eax,(%esp)
54c: e8 0c 3b 00 00 call 405d <printf>
551: e8 5f 39 00 00 call 3eb5 <exit>
556: a1 ec 62 00 00 mov 0x62ec,%eax
55b: c7 44 24 04 d7 46 00 movl $0x46d7,0x4(%esp)
562: 00
563: 89 04 24 mov %eax,(%esp)
566: e8 f2 3a 00 00 call 405d <printf>
56b: e8 45 39 00 00 call 3eb5 <exit>
570: a1 ec 62 00 00 mov 0x62ec,%eax
575: c7 44 24 04 ec 46 00 movl $0x46ec,0x4(%esp)
57c: 00
57d: 89 04 24 mov %eax,(%esp)
580: e8 d8 3a 00 00 call 405d <printf>
585: c9 leave
586: c3 ret
00000587 <writetest1>:
587: 55 push %ebp
588: 89 e5 mov %esp,%ebp
58a: 83 ec 28 sub $0x28,%esp
58d: a1 ec 62 00 00 mov 0x62ec,%eax
592: c7 44 24 04 00 47 00 movl $0x4700,0x4(%esp)
599: 00
59a: 89 04 24 mov %eax,(%esp)
59d: e8 bb 3a 00 00 call 405d <printf>
5a2: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
5a9: 00
5aa: c7 04 24 10 47 00 00 movl $0x4710,(%esp)
5b1: e8 3f 39 00 00 call 3ef5 <open>
5b6: 89 45 ec mov %eax,-0x14(%ebp)
5b9: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
5bd: 79 1a jns 5d9 <writetest1+0x52>
5bf: a1 ec 62 00 00 mov 0x62ec,%eax
5c4: c7 44 24 04 14 47 00 movl $0x4714,0x4(%esp)
5cb: 00
5cc: 89 04 24 mov %eax,(%esp)
5cf: e8 89 3a 00 00 call 405d <printf>
5d4: e8 dc 38 00 00 call 3eb5 <exit>
5d9: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
5e0: eb 51 jmp 633 <writetest1+0xac>
5e2: b8 e0 8a 00 00 mov $0x8ae0,%eax
5e7: 8b 55 f4 mov -0xc(%ebp),%edx
5ea: 89 10 mov %edx,(%eax)
5ec: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
5f3: 00
5f4: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
5fb: 00
5fc: 8b 45 ec mov -0x14(%ebp),%eax
5ff: 89 04 24 mov %eax,(%esp)
602: e8 ce 38 00 00 call 3ed5 <write>
607: 3d 00 02 00 00 cmp $0x200,%eax
60c: 74 21 je 62f <writetest1+0xa8>
60e: a1 ec 62 00 00 mov 0x62ec,%eax
613: 8b 55 f4 mov -0xc(%ebp),%edx
616: 89 54 24 08 mov %edx,0x8(%esp)
61a: c7 44 24 04 2e 47 00 movl $0x472e,0x4(%esp)
621: 00
622: 89 04 24 mov %eax,(%esp)
625: e8 33 3a 00 00 call 405d <printf>
62a: e8 86 38 00 00 call 3eb5 <exit>
62f: 83 45 f4 01 addl $0x1,-0xc(%ebp)
633: 8b 45 f4 mov -0xc(%ebp),%eax
636: 3d 8b 00 00 00 cmp $0x8b,%eax
63b: 76 a5 jbe 5e2 <writetest1+0x5b>
63d: 8b 45 ec mov -0x14(%ebp),%eax
640: 89 04 24 mov %eax,(%esp)
643: e8 95 38 00 00 call 3edd <close>
648: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
64f: 00
650: c7 04 24 10 47 00 00 movl $0x4710,(%esp)
657: e8 99 38 00 00 call 3ef5 <open>
65c: 89 45 ec mov %eax,-0x14(%ebp)
65f: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
663: 79 1a jns 67f <writetest1+0xf8>
665: a1 ec 62 00 00 mov 0x62ec,%eax
66a: c7 44 24 04 4c 47 00 movl $0x474c,0x4(%esp)
671: 00
672: 89 04 24 mov %eax,(%esp)
675: e8 e3 39 00 00 call 405d <printf>
67a: e8 36 38 00 00 call 3eb5 <exit>
67f: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
686: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
68d: 00
68e: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
695: 00
696: 8b 45 ec mov -0x14(%ebp),%eax
699: 89 04 24 mov %eax,(%esp)
69c: e8 2c 38 00 00 call 3ecd <read>
6a1: 89 45 f4 mov %eax,-0xc(%ebp)
6a4: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
6a8: 75 4c jne 6f6 <writetest1+0x16f>
6aa: 81 7d f0 8b 00 00 00 cmpl $0x8b,-0x10(%ebp)
6b1: 75 21 jne 6d4 <writetest1+0x14d>
6b3: a1 ec 62 00 00 mov 0x62ec,%eax
6b8: 8b 55 f0 mov -0x10(%ebp),%edx
6bb: 89 54 24 08 mov %edx,0x8(%esp)
6bf: c7 44 24 04 65 47 00 movl $0x4765,0x4(%esp)
6c6: 00
6c7: 89 04 24 mov %eax,(%esp)
6ca: e8 8e 39 00 00 call 405d <printf>
6cf: e8 e1 37 00 00 call 3eb5 <exit>
6d4: 90 nop
6d5: 8b 45 ec mov -0x14(%ebp),%eax
6d8: 89 04 24 mov %eax,(%esp)
6db: e8 fd 37 00 00 call 3edd <close>
6e0: c7 04 24 10 47 00 00 movl $0x4710,(%esp)
6e7: e8 19 38 00 00 call 3f05 <unlink>
6ec: 85 c0 test %eax,%eax
6ee: 0f 89 87 00 00 00 jns 77b <writetest1+0x1f4>
6f4: eb 6b jmp 761 <writetest1+0x1da>
6f6: 81 7d f4 00 02 00 00 cmpl $0x200,-0xc(%ebp)
6fd: 74 21 je 720 <writetest1+0x199>
6ff: a1 ec 62 00 00 mov 0x62ec,%eax
704: 8b 55 f4 mov -0xc(%ebp),%edx
707: 89 54 24 08 mov %edx,0x8(%esp)
70b: c7 44 24 04 82 47 00 movl $0x4782,0x4(%esp)
712: 00
713: 89 04 24 mov %eax,(%esp)
716: e8 42 39 00 00 call 405d <printf>
71b: e8 95 37 00 00 call 3eb5 <exit>
720: b8 e0 8a 00 00 mov $0x8ae0,%eax
725: 8b 00 mov (%eax),%eax
727: 3b 45 f0 cmp -0x10(%ebp),%eax
72a: 74 2c je 758 <writetest1+0x1d1>
72c: b8 e0 8a 00 00 mov $0x8ae0,%eax
731: 8b 10 mov (%eax),%edx
733: a1 ec 62 00 00 mov 0x62ec,%eax
738: 89 54 24 0c mov %edx,0xc(%esp)
73c: 8b 55 f0 mov -0x10(%ebp),%edx
73f: 89 54 24 08 mov %edx,0x8(%esp)
743: c7 44 24 04 94 47 00 movl $0x4794,0x4(%esp)
74a: 00
74b: 89 04 24 mov %eax,(%esp)
74e: e8 0a 39 00 00 call 405d <printf>
753: e8 5d 37 00 00 call 3eb5 <exit>
758: 83 45 f0 01 addl $0x1,-0x10(%ebp)
75c: e9 25 ff ff ff jmp 686 <writetest1+0xff>
761: a1 ec 62 00 00 mov 0x62ec,%eax
766: c7 44 24 04 b4 47 00 movl $0x47b4,0x4(%esp)
76d: 00
76e: 89 04 24 mov %eax,(%esp)
771: e8 e7 38 00 00 call 405d <printf>
776: e8 3a 37 00 00 call 3eb5 <exit>
77b: a1 ec 62 00 00 mov 0x62ec,%eax
780: c7 44 24 04 c7 47 00 movl $0x47c7,0x4(%esp)
787: 00
788: 89 04 24 mov %eax,(%esp)
78b: e8 cd 38 00 00 call 405d <printf>
790: c9 leave
791: c3 ret
00000792 <createtest>:
792: 55 push %ebp
793: 89 e5 mov %esp,%ebp
795: 83 ec 28 sub $0x28,%esp
798: a1 ec 62 00 00 mov 0x62ec,%eax
79d: c7 44 24 04 d8 47 00 movl $0x47d8,0x4(%esp)
7a4: 00
7a5: 89 04 24 mov %eax,(%esp)
7a8: e8 b0 38 00 00 call 405d <printf>
7ad: c6 05 e0 aa 00 00 61 movb $0x61,0xaae0
7b4: c6 05 e2 aa 00 00 00 movb $0x0,0xaae2
7bb: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
7c2: eb 31 jmp 7f5 <createtest+0x63>
7c4: 8b 45 f4 mov -0xc(%ebp),%eax
7c7: 83 c0 30 add $0x30,%eax
7ca: a2 e1 aa 00 00 mov %al,0xaae1
7cf: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
7d6: 00
7d7: c7 04 24 e0 aa 00 00 movl $0xaae0,(%esp)
7de: e8 12 37 00 00 call 3ef5 <open>
7e3: 89 45 f0 mov %eax,-0x10(%ebp)
7e6: 8b 45 f0 mov -0x10(%ebp),%eax
7e9: 89 04 24 mov %eax,(%esp)
7ec: e8 ec 36 00 00 call 3edd <close>
7f1: 83 45 f4 01 addl $0x1,-0xc(%ebp)
7f5: 83 7d f4 33 cmpl $0x33,-0xc(%ebp)
7f9: 7e c9 jle 7c4 <createtest+0x32>
7fb: c6 05 e0 aa 00 00 61 movb $0x61,0xaae0
802: c6 05 e2 aa 00 00 00 movb $0x0,0xaae2
809: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
810: eb 1b jmp 82d <createtest+0x9b>
812: 8b 45 f4 mov -0xc(%ebp),%eax
815: 83 c0 30 add $0x30,%eax
818: a2 e1 aa 00 00 mov %al,0xaae1
81d: c7 04 24 e0 aa 00 00 movl $0xaae0,(%esp)
824: e8 dc 36 00 00 call 3f05 <unlink>
829: 83 45 f4 01 addl $0x1,-0xc(%ebp)
82d: 83 7d f4 33 cmpl $0x33,-0xc(%ebp)
831: 7e df jle 812 <createtest+0x80>
833: a1 ec 62 00 00 mov 0x62ec,%eax
838: c7 44 24 04 00 48 00 movl $0x4800,0x4(%esp)
83f: 00
840: 89 04 24 mov %eax,(%esp)
843: e8 15 38 00 00 call 405d <printf>
848: c9 leave
849: c3 ret
0000084a <dirtest>:
84a: 55 push %ebp
84b: 89 e5 mov %esp,%ebp
84d: 83 ec 18 sub $0x18,%esp
850: a1 ec 62 00 00 mov 0x62ec,%eax
855: c7 44 24 04 26 48 00 movl $0x4826,0x4(%esp)
85c: 00
85d: 89 04 24 mov %eax,(%esp)
860: e8 f8 37 00 00 call 405d <printf>
865: c7 04 24 32 48 00 00 movl $0x4832,(%esp)
86c: e8 ac 36 00 00 call 3f1d <mkdir>
871: 85 c0 test %eax,%eax
873: 79 1a jns 88f <dirtest+0x45>
875: a1 ec 62 00 00 mov 0x62ec,%eax
87a: c7 44 24 04 55 44 00 movl $0x4455,0x4(%esp)
881: 00
882: 89 04 24 mov %eax,(%esp)
885: e8 d3 37 00 00 call 405d <printf>
88a: e8 26 36 00 00 call 3eb5 <exit>
88f: c7 04 24 32 48 00 00 movl $0x4832,(%esp)
896: e8 8a 36 00 00 call 3f25 <chdir>
89b: 85 c0 test %eax,%eax
89d: 79 1a jns 8b9 <dirtest+0x6f>
89f: a1 ec 62 00 00 mov 0x62ec,%eax
8a4: c7 44 24 04 37 48 00 movl $0x4837,0x4(%esp)
8ab: 00
8ac: 89 04 24 mov %eax,(%esp)
8af: e8 a9 37 00 00 call 405d <printf>
8b4: e8 fc 35 00 00 call 3eb5 <exit>
8b9: c7 04 24 4a 48 00 00 movl $0x484a,(%esp)
8c0: e8 60 36 00 00 call 3f25 <chdir>
8c5: 85 c0 test %eax,%eax
8c7: 79 1a jns 8e3 <dirtest+0x99>
8c9: a1 ec 62 00 00 mov 0x62ec,%eax
8ce: c7 44 24 04 4d 48 00 movl $0x484d,0x4(%esp)
8d5: 00
8d6: 89 04 24 mov %eax,(%esp)
8d9: e8 7f 37 00 00 call 405d <printf>
8de: e8 d2 35 00 00 call 3eb5 <exit>
8e3: c7 04 24 32 48 00 00 movl $0x4832,(%esp)
8ea: e8 16 36 00 00 call 3f05 <unlink>
8ef: 85 c0 test %eax,%eax
8f1: 79 1a jns 90d <dirtest+0xc3>
8f3: a1 ec 62 00 00 mov 0x62ec,%eax
8f8: c7 44 24 04 5e 48 00 movl $0x485e,0x4(%esp)
8ff: 00
900: 89 04 24 mov %eax,(%esp)
903: e8 55 37 00 00 call 405d <printf>
908: e8 a8 35 00 00 call 3eb5 <exit>
90d: a1 ec 62 00 00 mov 0x62ec,%eax
912: c7 44 24 04 72 48 00 movl $0x4872,0x4(%esp)
919: 00
91a: 89 04 24 mov %eax,(%esp)
91d: e8 3b 37 00 00 call 405d <printf>
922: c9 leave
923: c3 ret
00000924 <exectest>:
924: 55 push %ebp
925: 89 e5 mov %esp,%ebp
927: 83 ec 18 sub $0x18,%esp
92a: a1 ec 62 00 00 mov 0x62ec,%eax
92f: c7 44 24 04 81 48 00 movl $0x4881,0x4(%esp)
936: 00
937: 89 04 24 mov %eax,(%esp)
93a: e8 1e 37 00 00 call 405d <printf>
93f: c7 44 24 04 d8 62 00 movl $0x62d8,0x4(%esp)
946: 00
947: c7 04 24 2c 44 00 00 movl $0x442c,(%esp)
94e: e8 9a 35 00 00 call 3eed <exec>
953: 85 c0 test %eax,%eax
955: 79 1a jns 971 <exectest+0x4d>
957: a1 ec 62 00 00 mov 0x62ec,%eax
95c: c7 44 24 04 8c 48 00 movl $0x488c,0x4(%esp)
963: 00
964: 89 04 24 mov %eax,(%esp)
967: e8 f1 36 00 00 call 405d <printf>
96c: e8 44 35 00 00 call 3eb5 <exit>
971: c9 leave
972: c3 ret
00000973 <pipe1>:
973: 55 push %ebp
974: 89 e5 mov %esp,%ebp
976: 83 ec 38 sub $0x38,%esp
979: 8d 45 d8 lea -0x28(%ebp),%eax
97c: 89 04 24 mov %eax,(%esp)
97f: e8 41 35 00 00 call 3ec5 <pipe>
984: 85 c0 test %eax,%eax
986: 74 19 je 9a1 <pipe1+0x2e>
988: c7 44 24 04 9e 48 00 movl $0x489e,0x4(%esp)
98f: 00
990: c7 04 24 01 00 00 00 movl $0x1,(%esp)
997: e8 c1 36 00 00 call 405d <printf>
99c: e8 14 35 00 00 call 3eb5 <exit>
9a1: e8 07 35 00 00 call 3ead <fork>
9a6: 89 45 e0 mov %eax,-0x20(%ebp)
9a9: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
9b0: 83 7d e0 00 cmpl $0x0,-0x20(%ebp)
9b4: 0f 85 88 00 00 00 jne a42 <pipe1+0xcf>
9ba: 8b 45 d8 mov -0x28(%ebp),%eax
9bd: 89 04 24 mov %eax,(%esp)
9c0: e8 18 35 00 00 call 3edd <close>
9c5: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
9cc: eb 69 jmp a37 <pipe1+0xc4>
9ce: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
9d5: eb 18 jmp 9ef <pipe1+0x7c>
9d7: 8b 45 f4 mov -0xc(%ebp),%eax
9da: 8d 50 01 lea 0x1(%eax),%edx
9dd: 89 55 f4 mov %edx,-0xc(%ebp)
9e0: 8b 55 f0 mov -0x10(%ebp),%edx
9e3: 81 c2 e0 8a 00 00 add $0x8ae0,%edx
9e9: 88 02 mov %al,(%edx)
9eb: 83 45 f0 01 addl $0x1,-0x10(%ebp)
9ef: 81 7d f0 08 04 00 00 cmpl $0x408,-0x10(%ebp)
9f6: 7e df jle 9d7 <pipe1+0x64>
9f8: 8b 45 dc mov -0x24(%ebp),%eax
9fb: c7 44 24 08 09 04 00 movl $0x409,0x8(%esp)
a02: 00
a03: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
a0a: 00
a0b: 89 04 24 mov %eax,(%esp)
a0e: e8 c2 34 00 00 call 3ed5 <write>
a13: 3d 09 04 00 00 cmp $0x409,%eax
a18: 74 19 je a33 <pipe1+0xc0>
a1a: c7 44 24 04 ad 48 00 movl $0x48ad,0x4(%esp)
a21: 00
a22: c7 04 24 01 00 00 00 movl $0x1,(%esp)
a29: e8 2f 36 00 00 call 405d <printf>
a2e: e8 82 34 00 00 call 3eb5 <exit>
a33: 83 45 ec 01 addl $0x1,-0x14(%ebp)
a37: 83 7d ec 04 cmpl $0x4,-0x14(%ebp)
a3b: 7e 91 jle 9ce <pipe1+0x5b>
a3d: e8 73 34 00 00 call 3eb5 <exit>
a42: 83 7d e0 00 cmpl $0x0,-0x20(%ebp)
a46: 0f 8e f9 00 00 00 jle b45 <pipe1+0x1d2>
a4c: 8b 45 dc mov -0x24(%ebp),%eax
a4f: 89 04 24 mov %eax,(%esp)
a52: e8 86 34 00 00 call 3edd <close>
a57: c7 45 e4 00 00 00 00 movl $0x0,-0x1c(%ebp)
a5e: c7 45 e8 01 00 00 00 movl $0x1,-0x18(%ebp)
a65: eb 68 jmp acf <pipe1+0x15c>
a67: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
a6e: eb 3d jmp aad <pipe1+0x13a>
a70: 8b 45 f0 mov -0x10(%ebp),%eax
a73: 05 e0 8a 00 00 add $0x8ae0,%eax
a78: 0f b6 00 movzbl (%eax),%eax
a7b: 0f be c8 movsbl %al,%ecx
a7e: 8b 45 f4 mov -0xc(%ebp),%eax
a81: 8d 50 01 lea 0x1(%eax),%edx
a84: 89 55 f4 mov %edx,-0xc(%ebp)
a87: 31 c8 xor %ecx,%eax
a89: 0f b6 c0 movzbl %al,%eax
a8c: 85 c0 test %eax,%eax
a8e: 74 19 je aa9 <pipe1+0x136>
a90: c7 44 24 04 bb 48 00 movl $0x48bb,0x4(%esp)
a97: 00
a98: c7 04 24 01 00 00 00 movl $0x1,(%esp)
a9f: e8 b9 35 00 00 call 405d <printf>
aa4: e9 b5 00 00 00 jmp b5e <pipe1+0x1eb>
aa9: 83 45 f0 01 addl $0x1,-0x10(%ebp)
aad: 8b 45 f0 mov -0x10(%ebp),%eax
ab0: 3b 45 ec cmp -0x14(%ebp),%eax
ab3: 7c bb jl a70 <pipe1+0xfd>
ab5: 8b 45 ec mov -0x14(%ebp),%eax
ab8: 01 45 e4 add %eax,-0x1c(%ebp)
abb: d1 65 e8 shll -0x18(%ebp)
abe: 8b 45 e8 mov -0x18(%ebp),%eax
ac1: 3d 00 20 00 00 cmp $0x2000,%eax
ac6: 76 07 jbe acf <pipe1+0x15c>
ac8: c7 45 e8 00 20 00 00 movl $0x2000,-0x18(%ebp)
acf: 8b 45 d8 mov -0x28(%ebp),%eax
ad2: 8b 55 e8 mov -0x18(%ebp),%edx
ad5: 89 54 24 08 mov %edx,0x8(%esp)
ad9: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
ae0: 00
ae1: 89 04 24 mov %eax,(%esp)
ae4: e8 e4 33 00 00 call 3ecd <read>
ae9: 89 45 ec mov %eax,-0x14(%ebp)
aec: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
af0: 0f 8f 71 ff ff ff jg a67 <pipe1+0xf4>
af6: 81 7d e4 2d 14 00 00 cmpl $0x142d,-0x1c(%ebp)
afd: 74 20 je b1f <pipe1+0x1ac>
aff: 8b 45 e4 mov -0x1c(%ebp),%eax
b02: 89 44 24 08 mov %eax,0x8(%esp)
b06: c7 44 24 04 c9 48 00 movl $0x48c9,0x4(%esp)
b0d: 00
b0e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b15: e8 43 35 00 00 call 405d <printf>
b1a: e8 96 33 00 00 call 3eb5 <exit>
b1f: 8b 45 d8 mov -0x28(%ebp),%eax
b22: 89 04 24 mov %eax,(%esp)
b25: e8 b3 33 00 00 call 3edd <close>
b2a: e8 8e 33 00 00 call 3ebd <wait>
b2f: c7 44 24 04 ef 48 00 movl $0x48ef,0x4(%esp)
b36: 00
b37: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b3e: e8 1a 35 00 00 call 405d <printf>
b43: eb 19 jmp b5e <pipe1+0x1eb>
b45: c7 44 24 04 e0 48 00 movl $0x48e0,0x4(%esp)
b4c: 00
b4d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b54: e8 04 35 00 00 call 405d <printf>
b59: e8 57 33 00 00 call 3eb5 <exit>
b5e: c9 leave
b5f: c3 ret
00000b60 <preempt>:
b60: 55 push %ebp
b61: 89 e5 mov %esp,%ebp
b63: 83 ec 38 sub $0x38,%esp
b66: c7 44 24 04 f9 48 00 movl $0x48f9,0x4(%esp)
b6d: 00
b6e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
b75: e8 e3 34 00 00 call 405d <printf>
b7a: e8 2e 33 00 00 call 3ead <fork>
b7f: 89 45 f4 mov %eax,-0xc(%ebp)
b82: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
b86: 75 02 jne b8a <preempt+0x2a>
b88: eb fe jmp b88 <preempt+0x28>
b8a: e8 1e 33 00 00 call 3ead <fork>
b8f: 89 45 f0 mov %eax,-0x10(%ebp)
b92: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
b96: 75 02 jne b9a <preempt+0x3a>
b98: eb fe jmp b98 <preempt+0x38>
b9a: 8d 45 e4 lea -0x1c(%ebp),%eax
b9d: 89 04 24 mov %eax,(%esp)
ba0: e8 20 33 00 00 call 3ec5 <pipe>
ba5: e8 03 33 00 00 call 3ead <fork>
baa: 89 45 ec mov %eax,-0x14(%ebp)
bad: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
bb1: 75 4c jne bff <preempt+0x9f>
bb3: 8b 45 e4 mov -0x1c(%ebp),%eax
bb6: 89 04 24 mov %eax,(%esp)
bb9: e8 1f 33 00 00 call 3edd <close>
bbe: 8b 45 e8 mov -0x18(%ebp),%eax
bc1: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
bc8: 00
bc9: c7 44 24 04 03 49 00 movl $0x4903,0x4(%esp)
bd0: 00
bd1: 89 04 24 mov %eax,(%esp)
bd4: e8 fc 32 00 00 call 3ed5 <write>
bd9: 83 f8 01 cmp $0x1,%eax
bdc: 74 14 je bf2 <preempt+0x92>
bde: c7 44 24 04 05 49 00 movl $0x4905,0x4(%esp)
be5: 00
be6: c7 04 24 01 00 00 00 movl $0x1,(%esp)
bed: e8 6b 34 00 00 call 405d <printf>
bf2: 8b 45 e8 mov -0x18(%ebp),%eax
bf5: 89 04 24 mov %eax,(%esp)
bf8: e8 e0 32 00 00 call 3edd <close>
bfd: eb fe jmp bfd <preempt+0x9d>
bff: 8b 45 e8 mov -0x18(%ebp),%eax
c02: 89 04 24 mov %eax,(%esp)
c05: e8 d3 32 00 00 call 3edd <close>
c0a: 8b 45 e4 mov -0x1c(%ebp),%eax
c0d: c7 44 24 08 00 20 00 movl $0x2000,0x8(%esp)
c14: 00
c15: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
c1c: 00
c1d: 89 04 24 mov %eax,(%esp)
c20: e8 a8 32 00 00 call 3ecd <read>
c25: 83 f8 01 cmp $0x1,%eax
c28: 74 16 je c40 <preempt+0xe0>
c2a: c7 44 24 04 19 49 00 movl $0x4919,0x4(%esp)
c31: 00
c32: c7 04 24 01 00 00 00 movl $0x1,(%esp)
c39: e8 1f 34 00 00 call 405d <printf>
c3e: eb 77 jmp cb7 <preempt+0x157>
c40: 8b 45 e4 mov -0x1c(%ebp),%eax
c43: 89 04 24 mov %eax,(%esp)
c46: e8 92 32 00 00 call 3edd <close>
c4b: c7 44 24 04 2c 49 00 movl $0x492c,0x4(%esp)
c52: 00
c53: c7 04 24 01 00 00 00 movl $0x1,(%esp)
c5a: e8 fe 33 00 00 call 405d <printf>
c5f: 8b 45 f4 mov -0xc(%ebp),%eax
c62: 89 04 24 mov %eax,(%esp)
c65: e8 7b 32 00 00 call 3ee5 <kill>
c6a: 8b 45 f0 mov -0x10(%ebp),%eax
c6d: 89 04 24 mov %eax,(%esp)
c70: e8 70 32 00 00 call 3ee5 <kill>
c75: 8b 45 ec mov -0x14(%ebp),%eax
c78: 89 04 24 mov %eax,(%esp)
c7b: e8 65 32 00 00 call 3ee5 <kill>
c80: c7 44 24 04 35 49 00 movl $0x4935,0x4(%esp)
c87: 00
c88: c7 04 24 01 00 00 00 movl $0x1,(%esp)
c8f: e8 c9 33 00 00 call 405d <printf>
c94: e8 24 32 00 00 call 3ebd <wait>
c99: e8 1f 32 00 00 call 3ebd <wait>
c9e: e8 1a 32 00 00 call 3ebd <wait>
ca3: c7 44 24 04 3e 49 00 movl $0x493e,0x4(%esp)
caa: 00
cab: c7 04 24 01 00 00 00 movl $0x1,(%esp)
cb2: e8 a6 33 00 00 call 405d <printf>
cb7: c9 leave
cb8: c3 ret
00000cb9 <exitwait>:
cb9: 55 push %ebp
cba: 89 e5 mov %esp,%ebp
cbc: 83 ec 28 sub $0x28,%esp
cbf: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
cc6: eb 53 jmp d1b <exitwait+0x62>
cc8: e8 e0 31 00 00 call 3ead <fork>
ccd: 89 45 f0 mov %eax,-0x10(%ebp)
cd0: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
cd4: 79 16 jns cec <exitwait+0x33>
cd6: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
cdd: 00
cde: c7 04 24 01 00 00 00 movl $0x1,(%esp)
ce5: e8 73 33 00 00 call 405d <printf>
cea: eb 49 jmp d35 <exitwait+0x7c>
cec: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
cf0: 74 20 je d12 <exitwait+0x59>
cf2: e8 c6 31 00 00 call 3ebd <wait>
cf7: 3b 45 f0 cmp -0x10(%ebp),%eax
cfa: 74 1b je d17 <exitwait+0x5e>
cfc: c7 44 24 04 4a 49 00 movl $0x494a,0x4(%esp)
d03: 00
d04: c7 04 24 01 00 00 00 movl $0x1,(%esp)
d0b: e8 4d 33 00 00 call 405d <printf>
d10: eb 23 jmp d35 <exitwait+0x7c>
d12: e8 9e 31 00 00 call 3eb5 <exit>
d17: 83 45 f4 01 addl $0x1,-0xc(%ebp)
d1b: 83 7d f4 63 cmpl $0x63,-0xc(%ebp)
d1f: 7e a7 jle cc8 <exitwait+0xf>
d21: c7 44 24 04 5a 49 00 movl $0x495a,0x4(%esp)
d28: 00
d29: c7 04 24 01 00 00 00 movl $0x1,(%esp)
d30: e8 28 33 00 00 call 405d <printf>
d35: c9 leave
d36: c3 ret
00000d37 <mem>:
d37: 55 push %ebp
d38: 89 e5 mov %esp,%ebp
d3a: 83 ec 28 sub $0x28,%esp
d3d: c7 44 24 04 67 49 00 movl $0x4967,0x4(%esp)
d44: 00
d45: c7 04 24 01 00 00 00 movl $0x1,(%esp)
d4c: e8 0c 33 00 00 call 405d <printf>
d51: e8 df 31 00 00 call 3f35 <getpid>
d56: 89 45 f0 mov %eax,-0x10(%ebp)
d59: e8 4f 31 00 00 call 3ead <fork>
d5e: 89 45 ec mov %eax,-0x14(%ebp)
d61: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
d65: 0f 85 aa 00 00 00 jne e15 <mem+0xde>
d6b: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
d72: eb 0e jmp d82 <mem+0x4b>
d74: 8b 45 e8 mov -0x18(%ebp),%eax
d77: 8b 55 f4 mov -0xc(%ebp),%edx
d7a: 89 10 mov %edx,(%eax)
d7c: 8b 45 e8 mov -0x18(%ebp),%eax
d7f: 89 45 f4 mov %eax,-0xc(%ebp)
d82: c7 04 24 11 27 00 00 movl $0x2711,(%esp)
d89: e8 bb 35 00 00 call 4349 <malloc>
d8e: 89 45 e8 mov %eax,-0x18(%ebp)
d91: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
d95: 75 dd jne d74 <mem+0x3d>
d97: eb 19 jmp db2 <mem+0x7b>
d99: 8b 45 f4 mov -0xc(%ebp),%eax
d9c: 8b 00 mov (%eax),%eax
d9e: 89 45 e8 mov %eax,-0x18(%ebp)
da1: 8b 45 f4 mov -0xc(%ebp),%eax
da4: 89 04 24 mov %eax,(%esp)
da7: e8 64 34 00 00 call 4210 <free>
dac: 8b 45 e8 mov -0x18(%ebp),%eax
daf: 89 45 f4 mov %eax,-0xc(%ebp)
db2: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
db6: 75 e1 jne d99 <mem+0x62>
db8: c7 04 24 00 50 00 00 movl $0x5000,(%esp)
dbf: e8 85 35 00 00 call 4349 <malloc>
dc4: 89 45 f4 mov %eax,-0xc(%ebp)
dc7: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
dcb: 75 24 jne df1 <mem+0xba>
dcd: c7 44 24 04 71 49 00 movl $0x4971,0x4(%esp)
dd4: 00
dd5: c7 04 24 01 00 00 00 movl $0x1,(%esp)
ddc: e8 7c 32 00 00 call 405d <printf>
de1: 8b 45 f0 mov -0x10(%ebp),%eax
de4: 89 04 24 mov %eax,(%esp)
de7: e8 f9 30 00 00 call 3ee5 <kill>
dec: e8 c4 30 00 00 call 3eb5 <exit>
df1: 8b 45 f4 mov -0xc(%ebp),%eax
df4: 89 04 24 mov %eax,(%esp)
df7: e8 14 34 00 00 call 4210 <free>
dfc: c7 44 24 04 8b 49 00 movl $0x498b,0x4(%esp)
e03: 00
e04: c7 04 24 01 00 00 00 movl $0x1,(%esp)
e0b: e8 4d 32 00 00 call 405d <printf>
e10: e8 a0 30 00 00 call 3eb5 <exit>
e15: e8 a3 30 00 00 call 3ebd <wait>
e1a: c9 leave
e1b: c3 ret
00000e1c <sharedfd>:
e1c: 55 push %ebp
e1d: 89 e5 mov %esp,%ebp
e1f: 83 ec 48 sub $0x48,%esp
e22: c7 44 24 04 93 49 00 movl $0x4993,0x4(%esp)
e29: 00
e2a: c7 04 24 01 00 00 00 movl $0x1,(%esp)
e31: e8 27 32 00 00 call 405d <printf>
e36: c7 04 24 a2 49 00 00 movl $0x49a2,(%esp)
e3d: e8 c3 30 00 00 call 3f05 <unlink>
e42: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
e49: 00
e4a: c7 04 24 a2 49 00 00 movl $0x49a2,(%esp)
e51: e8 9f 30 00 00 call 3ef5 <open>
e56: 89 45 e8 mov %eax,-0x18(%ebp)
e59: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
e5d: 79 19 jns e78 <sharedfd+0x5c>
e5f: c7 44 24 04 ac 49 00 movl $0x49ac,0x4(%esp)
e66: 00
e67: c7 04 24 01 00 00 00 movl $0x1,(%esp)
e6e: e8 ea 31 00 00 call 405d <printf>
e73: e9 a0 01 00 00 jmp 1018 <sharedfd+0x1fc>
e78: e8 30 30 00 00 call 3ead <fork>
e7d: 89 45 e4 mov %eax,-0x1c(%ebp)
e80: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
e84: 75 07 jne e8d <sharedfd+0x71>
e86: b8 63 00 00 00 mov $0x63,%eax
e8b: eb 05 jmp e92 <sharedfd+0x76>
e8d: b8 70 00 00 00 mov $0x70,%eax
e92: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
e99: 00
e9a: 89 44 24 04 mov %eax,0x4(%esp)
e9e: 8d 45 d6 lea -0x2a(%ebp),%eax
ea1: 89 04 24 mov %eax,(%esp)
ea4: e8 5f 2e 00 00 call 3d08 <memset>
ea9: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
eb0: eb 39 jmp eeb <sharedfd+0xcf>
eb2: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
eb9: 00
eba: 8d 45 d6 lea -0x2a(%ebp),%eax
ebd: 89 44 24 04 mov %eax,0x4(%esp)
ec1: 8b 45 e8 mov -0x18(%ebp),%eax
ec4: 89 04 24 mov %eax,(%esp)
ec7: e8 09 30 00 00 call 3ed5 <write>
ecc: 83 f8 0a cmp $0xa,%eax
ecf: 74 16 je ee7 <sharedfd+0xcb>
ed1: c7 44 24 04 d8 49 00 movl $0x49d8,0x4(%esp)
ed8: 00
ed9: c7 04 24 01 00 00 00 movl $0x1,(%esp)
ee0: e8 78 31 00 00 call 405d <printf>
ee5: eb 0d jmp ef4 <sharedfd+0xd8>
ee7: 83 45 f4 01 addl $0x1,-0xc(%ebp)
eeb: 81 7d f4 e7 03 00 00 cmpl $0x3e7,-0xc(%ebp)
ef2: 7e be jle eb2 <sharedfd+0x96>
ef4: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
ef8: 75 05 jne eff <sharedfd+0xe3>
efa: e8 b6 2f 00 00 call 3eb5 <exit>
eff: e8 b9 2f 00 00 call 3ebd <wait>
f04: 8b 45 e8 mov -0x18(%ebp),%eax
f07: 89 04 24 mov %eax,(%esp)
f0a: e8 ce 2f 00 00 call 3edd <close>
f0f: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
f16: 00
f17: c7 04 24 a2 49 00 00 movl $0x49a2,(%esp)
f1e: e8 d2 2f 00 00 call 3ef5 <open>
f23: 89 45 e8 mov %eax,-0x18(%ebp)
f26: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
f2a: 79 19 jns f45 <sharedfd+0x129>
f2c: c7 44 24 04 f8 49 00 movl $0x49f8,0x4(%esp)
f33: 00
f34: c7 04 24 01 00 00 00 movl $0x1,(%esp)
f3b: e8 1d 31 00 00 call 405d <printf>
f40: e9 d3 00 00 00 jmp 1018 <sharedfd+0x1fc>
f45: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
f4c: 8b 45 ec mov -0x14(%ebp),%eax
f4f: 89 45 f0 mov %eax,-0x10(%ebp)
f52: eb 3b jmp f8f <sharedfd+0x173>
f54: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
f5b: eb 2a jmp f87 <sharedfd+0x16b>
f5d: 8d 55 d6 lea -0x2a(%ebp),%edx
f60: 8b 45 f4 mov -0xc(%ebp),%eax
f63: 01 d0 add %edx,%eax
f65: 0f b6 00 movzbl (%eax),%eax
f68: 3c 63 cmp $0x63,%al
f6a: 75 04 jne f70 <sharedfd+0x154>
f6c: 83 45 f0 01 addl $0x1,-0x10(%ebp)
f70: 8d 55 d6 lea -0x2a(%ebp),%edx
f73: 8b 45 f4 mov -0xc(%ebp),%eax
f76: 01 d0 add %edx,%eax
f78: 0f b6 00 movzbl (%eax),%eax
f7b: 3c 70 cmp $0x70,%al
f7d: 75 04 jne f83 <sharedfd+0x167>
f7f: 83 45 ec 01 addl $0x1,-0x14(%ebp)
f83: 83 45 f4 01 addl $0x1,-0xc(%ebp)
f87: 8b 45 f4 mov -0xc(%ebp),%eax
f8a: 83 f8 09 cmp $0x9,%eax
f8d: 76 ce jbe f5d <sharedfd+0x141>
f8f: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
f96: 00
f97: 8d 45 d6 lea -0x2a(%ebp),%eax
f9a: 89 44 24 04 mov %eax,0x4(%esp)
f9e: 8b 45 e8 mov -0x18(%ebp),%eax
fa1: 89 04 24 mov %eax,(%esp)
fa4: e8 24 2f 00 00 call 3ecd <read>
fa9: 89 45 e0 mov %eax,-0x20(%ebp)
fac: 83 7d e0 00 cmpl $0x0,-0x20(%ebp)
fb0: 7f a2 jg f54 <sharedfd+0x138>
fb2: 8b 45 e8 mov -0x18(%ebp),%eax
fb5: 89 04 24 mov %eax,(%esp)
fb8: e8 20 2f 00 00 call 3edd <close>
fbd: c7 04 24 a2 49 00 00 movl $0x49a2,(%esp)
fc4: e8 3c 2f 00 00 call 3f05 <unlink>
fc9: 81 7d f0 10 27 00 00 cmpl $0x2710,-0x10(%ebp)
fd0: 75 1f jne ff1 <sharedfd+0x1d5>
fd2: 81 7d ec 10 27 00 00 cmpl $0x2710,-0x14(%ebp)
fd9: 75 16 jne ff1 <sharedfd+0x1d5>
fdb: c7 44 24 04 23 4a 00 movl $0x4a23,0x4(%esp)
fe2: 00
fe3: c7 04 24 01 00 00 00 movl $0x1,(%esp)
fea: e8 6e 30 00 00 call 405d <printf>
fef: eb 27 jmp 1018 <sharedfd+0x1fc>
ff1: 8b 45 ec mov -0x14(%ebp),%eax
ff4: 89 44 24 0c mov %eax,0xc(%esp)
ff8: 8b 45 f0 mov -0x10(%ebp),%eax
ffb: 89 44 24 08 mov %eax,0x8(%esp)
fff: c7 44 24 04 30 4a 00 movl $0x4a30,0x4(%esp)
1006: 00
1007: c7 04 24 01 00 00 00 movl $0x1,(%esp)
100e: e8 4a 30 00 00 call 405d <printf>
1013: e8 9d 2e 00 00 call 3eb5 <exit>
1018: c9 leave
1019: c3 ret
0000101a <fourfiles>:
101a: 55 push %ebp
101b: 89 e5 mov %esp,%ebp
101d: 83 ec 48 sub $0x48,%esp
1020: c7 45 c8 45 4a 00 00 movl $0x4a45,-0x38(%ebp)
1027: c7 45 cc 48 4a 00 00 movl $0x4a48,-0x34(%ebp)
102e: c7 45 d0 4b 4a 00 00 movl $0x4a4b,-0x30(%ebp)
1035: c7 45 d4 4e 4a 00 00 movl $0x4a4e,-0x2c(%ebp)
103c: c7 44 24 04 51 4a 00 movl $0x4a51,0x4(%esp)
1043: 00
1044: c7 04 24 01 00 00 00 movl $0x1,(%esp)
104b: e8 0d 30 00 00 call 405d <printf>
1050: c7 45 e8 00 00 00 00 movl $0x0,-0x18(%ebp)
1057: e9 fc 00 00 00 jmp 1158 <fourfiles+0x13e>
105c: 8b 45 e8 mov -0x18(%ebp),%eax
105f: 8b 44 85 c8 mov -0x38(%ebp,%eax,4),%eax
1063: 89 45 e4 mov %eax,-0x1c(%ebp)
1066: 8b 45 e4 mov -0x1c(%ebp),%eax
1069: 89 04 24 mov %eax,(%esp)
106c: e8 94 2e 00 00 call 3f05 <unlink>
1071: e8 37 2e 00 00 call 3ead <fork>
1076: 89 45 e0 mov %eax,-0x20(%ebp)
1079: 83 7d e0 00 cmpl $0x0,-0x20(%ebp)
107d: 79 19 jns 1098 <fourfiles+0x7e>
107f: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
1086: 00
1087: c7 04 24 01 00 00 00 movl $0x1,(%esp)
108e: e8 ca 2f 00 00 call 405d <printf>
1093: e8 1d 2e 00 00 call 3eb5 <exit>
1098: 83 7d e0 00 cmpl $0x0,-0x20(%ebp)
109c: 0f 85 b2 00 00 00 jne 1154 <fourfiles+0x13a>
10a2: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
10a9: 00
10aa: 8b 45 e4 mov -0x1c(%ebp),%eax
10ad: 89 04 24 mov %eax,(%esp)
10b0: e8 40 2e 00 00 call 3ef5 <open>
10b5: 89 45 dc mov %eax,-0x24(%ebp)
10b8: 83 7d dc 00 cmpl $0x0,-0x24(%ebp)
10bc: 79 19 jns 10d7 <fourfiles+0xbd>
10be: c7 44 24 04 61 4a 00 movl $0x4a61,0x4(%esp)
10c5: 00
10c6: c7 04 24 01 00 00 00 movl $0x1,(%esp)
10cd: e8 8b 2f 00 00 call 405d <printf>
10d2: e8 de 2d 00 00 call 3eb5 <exit>
10d7: 8b 45 e8 mov -0x18(%ebp),%eax
10da: 83 c0 30 add $0x30,%eax
10dd: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
10e4: 00
10e5: 89 44 24 04 mov %eax,0x4(%esp)
10e9: c7 04 24 e0 8a 00 00 movl $0x8ae0,(%esp)
10f0: e8 13 2c 00 00 call 3d08 <memset>
10f5: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
10fc: eb 4b jmp 1149 <fourfiles+0x12f>
10fe: c7 44 24 08 f4 01 00 movl $0x1f4,0x8(%esp)
1105: 00
1106: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
110d: 00
110e: 8b 45 dc mov -0x24(%ebp),%eax
1111: 89 04 24 mov %eax,(%esp)
1114: e8 bc 2d 00 00 call 3ed5 <write>
1119: 89 45 d8 mov %eax,-0x28(%ebp)
111c: 81 7d d8 f4 01 00 00 cmpl $0x1f4,-0x28(%ebp)
1123: 74 20 je 1145 <fourfiles+0x12b>
1125: 8b 45 d8 mov -0x28(%ebp),%eax
1128: 89 44 24 08 mov %eax,0x8(%esp)
112c: c7 44 24 04 70 4a 00 movl $0x4a70,0x4(%esp)
1133: 00
1134: c7 04 24 01 00 00 00 movl $0x1,(%esp)
113b: e8 1d 2f 00 00 call 405d <printf>
1140: e8 70 2d 00 00 call 3eb5 <exit>
1145: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1149: 83 7d f4 0b cmpl $0xb,-0xc(%ebp)
114d: 7e af jle 10fe <fourfiles+0xe4>
114f: e8 61 2d 00 00 call 3eb5 <exit>
1154: 83 45 e8 01 addl $0x1,-0x18(%ebp)
1158: 83 7d e8 03 cmpl $0x3,-0x18(%ebp)
115c: 0f 8e fa fe ff ff jle 105c <fourfiles+0x42>
1162: c7 45 e8 00 00 00 00 movl $0x0,-0x18(%ebp)
1169: eb 09 jmp 1174 <fourfiles+0x15a>
116b: e8 4d 2d 00 00 call 3ebd <wait>
1170: 83 45 e8 01 addl $0x1,-0x18(%ebp)
1174: 83 7d e8 03 cmpl $0x3,-0x18(%ebp)
1178: 7e f1 jle 116b <fourfiles+0x151>
117a: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1181: e9 dc 00 00 00 jmp 1262 <fourfiles+0x248>
1186: 8b 45 f4 mov -0xc(%ebp),%eax
1189: 8b 44 85 c8 mov -0x38(%ebp,%eax,4),%eax
118d: 89 45 e4 mov %eax,-0x1c(%ebp)
1190: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1197: 00
1198: 8b 45 e4 mov -0x1c(%ebp),%eax
119b: 89 04 24 mov %eax,(%esp)
119e: e8 52 2d 00 00 call 3ef5 <open>
11a3: 89 45 dc mov %eax,-0x24(%ebp)
11a6: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
11ad: eb 4c jmp 11fb <fourfiles+0x1e1>
11af: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
11b6: eb 35 jmp 11ed <fourfiles+0x1d3>
11b8: 8b 45 f0 mov -0x10(%ebp),%eax
11bb: 05 e0 8a 00 00 add $0x8ae0,%eax
11c0: 0f b6 00 movzbl (%eax),%eax
11c3: 0f be c0 movsbl %al,%eax
11c6: 8b 55 f4 mov -0xc(%ebp),%edx
11c9: 83 c2 30 add $0x30,%edx
11cc: 39 d0 cmp %edx,%eax
11ce: 74 19 je 11e9 <fourfiles+0x1cf>
11d0: c7 44 24 04 81 4a 00 movl $0x4a81,0x4(%esp)
11d7: 00
11d8: c7 04 24 01 00 00 00 movl $0x1,(%esp)
11df: e8 79 2e 00 00 call 405d <printf>
11e4: e8 cc 2c 00 00 call 3eb5 <exit>
11e9: 83 45 f0 01 addl $0x1,-0x10(%ebp)
11ed: 8b 45 f0 mov -0x10(%ebp),%eax
11f0: 3b 45 d8 cmp -0x28(%ebp),%eax
11f3: 7c c3 jl 11b8 <fourfiles+0x19e>
11f5: 8b 45 d8 mov -0x28(%ebp),%eax
11f8: 01 45 ec add %eax,-0x14(%ebp)
11fb: c7 44 24 08 00 20 00 movl $0x2000,0x8(%esp)
1202: 00
1203: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
120a: 00
120b: 8b 45 dc mov -0x24(%ebp),%eax
120e: 89 04 24 mov %eax,(%esp)
1211: e8 b7 2c 00 00 call 3ecd <read>
1216: 89 45 d8 mov %eax,-0x28(%ebp)
1219: 83 7d d8 00 cmpl $0x0,-0x28(%ebp)
121d: 7f 90 jg 11af <fourfiles+0x195>
121f: 8b 45 dc mov -0x24(%ebp),%eax
1222: 89 04 24 mov %eax,(%esp)
1225: e8 b3 2c 00 00 call 3edd <close>
122a: 81 7d ec 70 17 00 00 cmpl $0x1770,-0x14(%ebp)
1231: 74 20 je 1253 <fourfiles+0x239>
1233: 8b 45 ec mov -0x14(%ebp),%eax
1236: 89 44 24 08 mov %eax,0x8(%esp)
123a: c7 44 24 04 8d 4a 00 movl $0x4a8d,0x4(%esp)
1241: 00
1242: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1249: e8 0f 2e 00 00 call 405d <printf>
124e: e8 62 2c 00 00 call 3eb5 <exit>
1253: 8b 45 e4 mov -0x1c(%ebp),%eax
1256: 89 04 24 mov %eax,(%esp)
1259: e8 a7 2c 00 00 call 3f05 <unlink>
125e: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1262: 83 7d f4 01 cmpl $0x1,-0xc(%ebp)
1266: 0f 8e 1a ff ff ff jle 1186 <fourfiles+0x16c>
126c: c7 44 24 04 9e 4a 00 movl $0x4a9e,0x4(%esp)
1273: 00
1274: c7 04 24 01 00 00 00 movl $0x1,(%esp)
127b: e8 dd 2d 00 00 call 405d <printf>
1280: c9 leave
1281: c3 ret
00001282 <createdelete>:
1282: 55 push %ebp
1283: 89 e5 mov %esp,%ebp
1285: 83 ec 48 sub $0x48,%esp
1288: c7 44 24 04 ac 4a 00 movl $0x4aac,0x4(%esp)
128f: 00
1290: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1297: e8 c1 2d 00 00 call 405d <printf>
129c: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
12a3: e9 f4 00 00 00 jmp 139c <createdelete+0x11a>
12a8: e8 00 2c 00 00 call 3ead <fork>
12ad: 89 45 ec mov %eax,-0x14(%ebp)
12b0: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
12b4: 79 19 jns 12cf <createdelete+0x4d>
12b6: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
12bd: 00
12be: c7 04 24 01 00 00 00 movl $0x1,(%esp)
12c5: e8 93 2d 00 00 call 405d <printf>
12ca: e8 e6 2b 00 00 call 3eb5 <exit>
12cf: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
12d3: 0f 85 bf 00 00 00 jne 1398 <createdelete+0x116>
12d9: 8b 45 f0 mov -0x10(%ebp),%eax
12dc: 83 c0 70 add $0x70,%eax
12df: 88 45 c8 mov %al,-0x38(%ebp)
12e2: c6 45 ca 00 movb $0x0,-0x36(%ebp)
12e6: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
12ed: e9 97 00 00 00 jmp 1389 <createdelete+0x107>
12f2: 8b 45 f4 mov -0xc(%ebp),%eax
12f5: 83 c0 30 add $0x30,%eax
12f8: 88 45 c9 mov %al,-0x37(%ebp)
12fb: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
1302: 00
1303: 8d 45 c8 lea -0x38(%ebp),%eax
1306: 89 04 24 mov %eax,(%esp)
1309: e8 e7 2b 00 00 call 3ef5 <open>
130e: 89 45 e8 mov %eax,-0x18(%ebp)
1311: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
1315: 79 19 jns 1330 <createdelete+0xae>
1317: c7 44 24 04 61 4a 00 movl $0x4a61,0x4(%esp)
131e: 00
131f: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1326: e8 32 2d 00 00 call 405d <printf>
132b: e8 85 2b 00 00 call 3eb5 <exit>
1330: 8b 45 e8 mov -0x18(%ebp),%eax
1333: 89 04 24 mov %eax,(%esp)
1336: e8 a2 2b 00 00 call 3edd <close>
133b: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
133f: 7e 44 jle 1385 <createdelete+0x103>
1341: 8b 45 f4 mov -0xc(%ebp),%eax
1344: 83 e0 01 and $0x1,%eax
1347: 85 c0 test %eax,%eax
1349: 75 3a jne 1385 <createdelete+0x103>
134b: 8b 45 f4 mov -0xc(%ebp),%eax
134e: 89 c2 mov %eax,%edx
1350: c1 ea 1f shr $0x1f,%edx
1353: 01 d0 add %edx,%eax
1355: d1 f8 sar %eax
1357: 83 c0 30 add $0x30,%eax
135a: 88 45 c9 mov %al,-0x37(%ebp)
135d: 8d 45 c8 lea -0x38(%ebp),%eax
1360: 89 04 24 mov %eax,(%esp)
1363: e8 9d 2b 00 00 call 3f05 <unlink>
1368: 85 c0 test %eax,%eax
136a: 79 19 jns 1385 <createdelete+0x103>
136c: c7 44 24 04 50 45 00 movl $0x4550,0x4(%esp)
1373: 00
1374: c7 04 24 01 00 00 00 movl $0x1,(%esp)
137b: e8 dd 2c 00 00 call 405d <printf>
1380: e8 30 2b 00 00 call 3eb5 <exit>
1385: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1389: 83 7d f4 13 cmpl $0x13,-0xc(%ebp)
138d: 0f 8e 5f ff ff ff jle 12f2 <createdelete+0x70>
1393: e8 1d 2b 00 00 call 3eb5 <exit>
1398: 83 45 f0 01 addl $0x1,-0x10(%ebp)
139c: 83 7d f0 03 cmpl $0x3,-0x10(%ebp)
13a0: 0f 8e 02 ff ff ff jle 12a8 <createdelete+0x26>
13a6: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
13ad: eb 09 jmp 13b8 <createdelete+0x136>
13af: e8 09 2b 00 00 call 3ebd <wait>
13b4: 83 45 f0 01 addl $0x1,-0x10(%ebp)
13b8: 83 7d f0 03 cmpl $0x3,-0x10(%ebp)
13bc: 7e f1 jle 13af <createdelete+0x12d>
13be: c6 45 ca 00 movb $0x0,-0x36(%ebp)
13c2: 0f b6 45 ca movzbl -0x36(%ebp),%eax
13c6: 88 45 c9 mov %al,-0x37(%ebp)
13c9: 0f b6 45 c9 movzbl -0x37(%ebp),%eax
13cd: 88 45 c8 mov %al,-0x38(%ebp)
13d0: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
13d7: e9 bb 00 00 00 jmp 1497 <createdelete+0x215>
13dc: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
13e3: e9 a1 00 00 00 jmp 1489 <createdelete+0x207>
13e8: 8b 45 f0 mov -0x10(%ebp),%eax
13eb: 83 c0 70 add $0x70,%eax
13ee: 88 45 c8 mov %al,-0x38(%ebp)
13f1: 8b 45 f4 mov -0xc(%ebp),%eax
13f4: 83 c0 30 add $0x30,%eax
13f7: 88 45 c9 mov %al,-0x37(%ebp)
13fa: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1401: 00
1402: 8d 45 c8 lea -0x38(%ebp),%eax
1405: 89 04 24 mov %eax,(%esp)
1408: e8 e8 2a 00 00 call 3ef5 <open>
140d: 89 45 e8 mov %eax,-0x18(%ebp)
1410: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
1414: 74 06 je 141c <createdelete+0x19a>
1416: 83 7d f4 09 cmpl $0x9,-0xc(%ebp)
141a: 7e 26 jle 1442 <createdelete+0x1c0>
141c: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
1420: 79 20 jns 1442 <createdelete+0x1c0>
1422: 8d 45 c8 lea -0x38(%ebp),%eax
1425: 89 44 24 08 mov %eax,0x8(%esp)
1429: c7 44 24 04 c0 4a 00 movl $0x4ac0,0x4(%esp)
1430: 00
1431: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1438: e8 20 2c 00 00 call 405d <printf>
143d: e8 73 2a 00 00 call 3eb5 <exit>
1442: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
1446: 7e 2c jle 1474 <createdelete+0x1f2>
1448: 83 7d f4 09 cmpl $0x9,-0xc(%ebp)
144c: 7f 26 jg 1474 <createdelete+0x1f2>
144e: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
1452: 78 20 js 1474 <createdelete+0x1f2>
1454: 8d 45 c8 lea -0x38(%ebp),%eax
1457: 89 44 24 08 mov %eax,0x8(%esp)
145b: c7 44 24 04 e4 4a 00 movl $0x4ae4,0x4(%esp)
1462: 00
1463: c7 04 24 01 00 00 00 movl $0x1,(%esp)
146a: e8 ee 2b 00 00 call 405d <printf>
146f: e8 41 2a 00 00 call 3eb5 <exit>
1474: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
1478: 78 0b js 1485 <createdelete+0x203>
147a: 8b 45 e8 mov -0x18(%ebp),%eax
147d: 89 04 24 mov %eax,(%esp)
1480: e8 58 2a 00 00 call 3edd <close>
1485: 83 45 f0 01 addl $0x1,-0x10(%ebp)
1489: 83 7d f0 03 cmpl $0x3,-0x10(%ebp)
148d: 0f 8e 55 ff ff ff jle 13e8 <createdelete+0x166>
1493: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1497: 83 7d f4 13 cmpl $0x13,-0xc(%ebp)
149b: 0f 8e 3b ff ff ff jle 13dc <createdelete+0x15a>
14a1: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
14a8: eb 34 jmp 14de <createdelete+0x25c>
14aa: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
14b1: eb 21 jmp 14d4 <createdelete+0x252>
14b3: 8b 45 f4 mov -0xc(%ebp),%eax
14b6: 83 c0 70 add $0x70,%eax
14b9: 88 45 c8 mov %al,-0x38(%ebp)
14bc: 8b 45 f4 mov -0xc(%ebp),%eax
14bf: 83 c0 30 add $0x30,%eax
14c2: 88 45 c9 mov %al,-0x37(%ebp)
14c5: 8d 45 c8 lea -0x38(%ebp),%eax
14c8: 89 04 24 mov %eax,(%esp)
14cb: e8 35 2a 00 00 call 3f05 <unlink>
14d0: 83 45 f0 01 addl $0x1,-0x10(%ebp)
14d4: 83 7d f0 03 cmpl $0x3,-0x10(%ebp)
14d8: 7e d9 jle 14b3 <createdelete+0x231>
14da: 83 45 f4 01 addl $0x1,-0xc(%ebp)
14de: 83 7d f4 13 cmpl $0x13,-0xc(%ebp)
14e2: 7e c6 jle 14aa <createdelete+0x228>
14e4: c7 44 24 04 04 4b 00 movl $0x4b04,0x4(%esp)
14eb: 00
14ec: c7 04 24 01 00 00 00 movl $0x1,(%esp)
14f3: e8 65 2b 00 00 call 405d <printf>
14f8: c9 leave
14f9: c3 ret
000014fa <unlinkread>:
14fa: 55 push %ebp
14fb: 89 e5 mov %esp,%ebp
14fd: 83 ec 28 sub $0x28,%esp
1500: c7 44 24 04 15 4b 00 movl $0x4b15,0x4(%esp)
1507: 00
1508: c7 04 24 01 00 00 00 movl $0x1,(%esp)
150f: e8 49 2b 00 00 call 405d <printf>
1514: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
151b: 00
151c: c7 04 24 26 4b 00 00 movl $0x4b26,(%esp)
1523: e8 cd 29 00 00 call 3ef5 <open>
1528: 89 45 f4 mov %eax,-0xc(%ebp)
152b: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
152f: 79 19 jns 154a <unlinkread+0x50>
1531: c7 44 24 04 31 4b 00 movl $0x4b31,0x4(%esp)
1538: 00
1539: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1540: e8 18 2b 00 00 call 405d <printf>
1545: e8 6b 29 00 00 call 3eb5 <exit>
154a: c7 44 24 08 05 00 00 movl $0x5,0x8(%esp)
1551: 00
1552: c7 44 24 04 4b 4b 00 movl $0x4b4b,0x4(%esp)
1559: 00
155a: 8b 45 f4 mov -0xc(%ebp),%eax
155d: 89 04 24 mov %eax,(%esp)
1560: e8 70 29 00 00 call 3ed5 <write>
1565: 8b 45 f4 mov -0xc(%ebp),%eax
1568: 89 04 24 mov %eax,(%esp)
156b: e8 6d 29 00 00 call 3edd <close>
1570: c7 44 24 04 02 00 00 movl $0x2,0x4(%esp)
1577: 00
1578: c7 04 24 26 4b 00 00 movl $0x4b26,(%esp)
157f: e8 71 29 00 00 call 3ef5 <open>
1584: 89 45 f4 mov %eax,-0xc(%ebp)
1587: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
158b: 79 19 jns 15a6 <unlinkread+0xac>
158d: c7 44 24 04 51 4b 00 movl $0x4b51,0x4(%esp)
1594: 00
1595: c7 04 24 01 00 00 00 movl $0x1,(%esp)
159c: e8 bc 2a 00 00 call 405d <printf>
15a1: e8 0f 29 00 00 call 3eb5 <exit>
15a6: c7 04 24 26 4b 00 00 movl $0x4b26,(%esp)
15ad: e8 53 29 00 00 call 3f05 <unlink>
15b2: 85 c0 test %eax,%eax
15b4: 74 19 je 15cf <unlinkread+0xd5>
15b6: c7 44 24 04 69 4b 00 movl $0x4b69,0x4(%esp)
15bd: 00
15be: c7 04 24 01 00 00 00 movl $0x1,(%esp)
15c5: e8 93 2a 00 00 call 405d <printf>
15ca: e8 e6 28 00 00 call 3eb5 <exit>
15cf: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
15d6: 00
15d7: c7 04 24 26 4b 00 00 movl $0x4b26,(%esp)
15de: e8 12 29 00 00 call 3ef5 <open>
15e3: 89 45 f0 mov %eax,-0x10(%ebp)
15e6: c7 44 24 08 03 00 00 movl $0x3,0x8(%esp)
15ed: 00
15ee: c7 44 24 04 83 4b 00 movl $0x4b83,0x4(%esp)
15f5: 00
15f6: 8b 45 f0 mov -0x10(%ebp),%eax
15f9: 89 04 24 mov %eax,(%esp)
15fc: e8 d4 28 00 00 call 3ed5 <write>
1601: 8b 45 f0 mov -0x10(%ebp),%eax
1604: 89 04 24 mov %eax,(%esp)
1607: e8 d1 28 00 00 call 3edd <close>
160c: c7 44 24 08 00 20 00 movl $0x2000,0x8(%esp)
1613: 00
1614: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
161b: 00
161c: 8b 45 f4 mov -0xc(%ebp),%eax
161f: 89 04 24 mov %eax,(%esp)
1622: e8 a6 28 00 00 call 3ecd <read>
1627: 83 f8 05 cmp $0x5,%eax
162a: 74 19 je 1645 <unlinkread+0x14b>
162c: c7 44 24 04 87 4b 00 movl $0x4b87,0x4(%esp)
1633: 00
1634: c7 04 24 01 00 00 00 movl $0x1,(%esp)
163b: e8 1d 2a 00 00 call 405d <printf>
1640: e8 70 28 00 00 call 3eb5 <exit>
1645: 0f b6 05 e0 8a 00 00 movzbl 0x8ae0,%eax
164c: 3c 68 cmp $0x68,%al
164e: 74 19 je 1669 <unlinkread+0x16f>
1650: c7 44 24 04 9e 4b 00 movl $0x4b9e,0x4(%esp)
1657: 00
1658: c7 04 24 01 00 00 00 movl $0x1,(%esp)
165f: e8 f9 29 00 00 call 405d <printf>
1664: e8 4c 28 00 00 call 3eb5 <exit>
1669: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
1670: 00
1671: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
1678: 00
1679: 8b 45 f4 mov -0xc(%ebp),%eax
167c: 89 04 24 mov %eax,(%esp)
167f: e8 51 28 00 00 call 3ed5 <write>
1684: 83 f8 0a cmp $0xa,%eax
1687: 74 19 je 16a2 <unlinkread+0x1a8>
1689: c7 44 24 04 b5 4b 00 movl $0x4bb5,0x4(%esp)
1690: 00
1691: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1698: e8 c0 29 00 00 call 405d <printf>
169d: e8 13 28 00 00 call 3eb5 <exit>
16a2: 8b 45 f4 mov -0xc(%ebp),%eax
16a5: 89 04 24 mov %eax,(%esp)
16a8: e8 30 28 00 00 call 3edd <close>
16ad: c7 04 24 26 4b 00 00 movl $0x4b26,(%esp)
16b4: e8 4c 28 00 00 call 3f05 <unlink>
16b9: c7 44 24 04 ce 4b 00 movl $0x4bce,0x4(%esp)
16c0: 00
16c1: c7 04 24 01 00 00 00 movl $0x1,(%esp)
16c8: e8 90 29 00 00 call 405d <printf>
16cd: c9 leave
16ce: c3 ret
000016cf <linktest>:
16cf: 55 push %ebp
16d0: 89 e5 mov %esp,%ebp
16d2: 83 ec 28 sub $0x28,%esp
16d5: c7 44 24 04 dd 4b 00 movl $0x4bdd,0x4(%esp)
16dc: 00
16dd: c7 04 24 01 00 00 00 movl $0x1,(%esp)
16e4: e8 74 29 00 00 call 405d <printf>
16e9: c7 04 24 e7 4b 00 00 movl $0x4be7,(%esp)
16f0: e8 10 28 00 00 call 3f05 <unlink>
16f5: c7 04 24 eb 4b 00 00 movl $0x4beb,(%esp)
16fc: e8 04 28 00 00 call 3f05 <unlink>
1701: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
1708: 00
1709: c7 04 24 e7 4b 00 00 movl $0x4be7,(%esp)
1710: e8 e0 27 00 00 call 3ef5 <open>
1715: 89 45 f4 mov %eax,-0xc(%ebp)
1718: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
171c: 79 19 jns 1737 <linktest+0x68>
171e: c7 44 24 04 ef 4b 00 movl $0x4bef,0x4(%esp)
1725: 00
1726: c7 04 24 01 00 00 00 movl $0x1,(%esp)
172d: e8 2b 29 00 00 call 405d <printf>
1732: e8 7e 27 00 00 call 3eb5 <exit>
1737: c7 44 24 08 05 00 00 movl $0x5,0x8(%esp)
173e: 00
173f: c7 44 24 04 4b 4b 00 movl $0x4b4b,0x4(%esp)
1746: 00
1747: 8b 45 f4 mov -0xc(%ebp),%eax
174a: 89 04 24 mov %eax,(%esp)
174d: e8 83 27 00 00 call 3ed5 <write>
1752: 83 f8 05 cmp $0x5,%eax
1755: 74 19 je 1770 <linktest+0xa1>
1757: c7 44 24 04 02 4c 00 movl $0x4c02,0x4(%esp)
175e: 00
175f: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1766: e8 f2 28 00 00 call 405d <printf>
176b: e8 45 27 00 00 call 3eb5 <exit>
1770: 8b 45 f4 mov -0xc(%ebp),%eax
1773: 89 04 24 mov %eax,(%esp)
1776: e8 62 27 00 00 call 3edd <close>
177b: c7 44 24 04 eb 4b 00 movl $0x4beb,0x4(%esp)
1782: 00
1783: c7 04 24 e7 4b 00 00 movl $0x4be7,(%esp)
178a: e8 86 27 00 00 call 3f15 <link>
178f: 85 c0 test %eax,%eax
1791: 79 19 jns 17ac <linktest+0xdd>
1793: c7 44 24 04 14 4c 00 movl $0x4c14,0x4(%esp)
179a: 00
179b: c7 04 24 01 00 00 00 movl $0x1,(%esp)
17a2: e8 b6 28 00 00 call 405d <printf>
17a7: e8 09 27 00 00 call 3eb5 <exit>
17ac: c7 04 24 e7 4b 00 00 movl $0x4be7,(%esp)
17b3: e8 4d 27 00 00 call 3f05 <unlink>
17b8: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
17bf: 00
17c0: c7 04 24 e7 4b 00 00 movl $0x4be7,(%esp)
17c7: e8 29 27 00 00 call 3ef5 <open>
17cc: 85 c0 test %eax,%eax
17ce: 78 19 js 17e9 <linktest+0x11a>
17d0: c7 44 24 04 2c 4c 00 movl $0x4c2c,0x4(%esp)
17d7: 00
17d8: c7 04 24 01 00 00 00 movl $0x1,(%esp)
17df: e8 79 28 00 00 call 405d <printf>
17e4: e8 cc 26 00 00 call 3eb5 <exit>
17e9: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
17f0: 00
17f1: c7 04 24 eb 4b 00 00 movl $0x4beb,(%esp)
17f8: e8 f8 26 00 00 call 3ef5 <open>
17fd: 89 45 f4 mov %eax,-0xc(%ebp)
1800: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
1804: 79 19 jns 181f <linktest+0x150>
1806: c7 44 24 04 51 4c 00 movl $0x4c51,0x4(%esp)
180d: 00
180e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1815: e8 43 28 00 00 call 405d <printf>
181a: e8 96 26 00 00 call 3eb5 <exit>
181f: c7 44 24 08 00 20 00 movl $0x2000,0x8(%esp)
1826: 00
1827: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
182e: 00
182f: 8b 45 f4 mov -0xc(%ebp),%eax
1832: 89 04 24 mov %eax,(%esp)
1835: e8 93 26 00 00 call 3ecd <read>
183a: 83 f8 05 cmp $0x5,%eax
183d: 74 19 je 1858 <linktest+0x189>
183f: c7 44 24 04 62 4c 00 movl $0x4c62,0x4(%esp)
1846: 00
1847: c7 04 24 01 00 00 00 movl $0x1,(%esp)
184e: e8 0a 28 00 00 call 405d <printf>
1853: e8 5d 26 00 00 call 3eb5 <exit>
1858: 8b 45 f4 mov -0xc(%ebp),%eax
185b: 89 04 24 mov %eax,(%esp)
185e: e8 7a 26 00 00 call 3edd <close>
1863: c7 44 24 04 eb 4b 00 movl $0x4beb,0x4(%esp)
186a: 00
186b: c7 04 24 eb 4b 00 00 movl $0x4beb,(%esp)
1872: e8 9e 26 00 00 call 3f15 <link>
1877: 85 c0 test %eax,%eax
1879: 78 19 js 1894 <linktest+0x1c5>
187b: c7 44 24 04 73 4c 00 movl $0x4c73,0x4(%esp)
1882: 00
1883: c7 04 24 01 00 00 00 movl $0x1,(%esp)
188a: e8 ce 27 00 00 call 405d <printf>
188f: e8 21 26 00 00 call 3eb5 <exit>
1894: c7 04 24 eb 4b 00 00 movl $0x4beb,(%esp)
189b: e8 65 26 00 00 call 3f05 <unlink>
18a0: c7 44 24 04 e7 4b 00 movl $0x4be7,0x4(%esp)
18a7: 00
18a8: c7 04 24 eb 4b 00 00 movl $0x4beb,(%esp)
18af: e8 61 26 00 00 call 3f15 <link>
18b4: 85 c0 test %eax,%eax
18b6: 78 19 js 18d1 <linktest+0x202>
18b8: c7 44 24 04 94 4c 00 movl $0x4c94,0x4(%esp)
18bf: 00
18c0: c7 04 24 01 00 00 00 movl $0x1,(%esp)
18c7: e8 91 27 00 00 call 405d <printf>
18cc: e8 e4 25 00 00 call 3eb5 <exit>
18d1: c7 44 24 04 e7 4b 00 movl $0x4be7,0x4(%esp)
18d8: 00
18d9: c7 04 24 b7 4c 00 00 movl $0x4cb7,(%esp)
18e0: e8 30 26 00 00 call 3f15 <link>
18e5: 85 c0 test %eax,%eax
18e7: 78 19 js 1902 <linktest+0x233>
18e9: c7 44 24 04 b9 4c 00 movl $0x4cb9,0x4(%esp)
18f0: 00
18f1: c7 04 24 01 00 00 00 movl $0x1,(%esp)
18f8: e8 60 27 00 00 call 405d <printf>
18fd: e8 b3 25 00 00 call 3eb5 <exit>
1902: c7 44 24 04 d5 4c 00 movl $0x4cd5,0x4(%esp)
1909: 00
190a: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1911: e8 47 27 00 00 call 405d <printf>
1916: c9 leave
1917: c3 ret
00001918 <concreate>:
1918: 55 push %ebp
1919: 89 e5 mov %esp,%ebp
191b: 83 ec 68 sub $0x68,%esp
191e: c7 44 24 04 e2 4c 00 movl $0x4ce2,0x4(%esp)
1925: 00
1926: c7 04 24 01 00 00 00 movl $0x1,(%esp)
192d: e8 2b 27 00 00 call 405d <printf>
1932: c6 45 e5 43 movb $0x43,-0x1b(%ebp)
1936: c6 45 e7 00 movb $0x0,-0x19(%ebp)
193a: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1941: e9 f7 00 00 00 jmp 1a3d <concreate+0x125>
1946: 8b 45 f4 mov -0xc(%ebp),%eax
1949: 83 c0 30 add $0x30,%eax
194c: 88 45 e6 mov %al,-0x1a(%ebp)
194f: 8d 45 e5 lea -0x1b(%ebp),%eax
1952: 89 04 24 mov %eax,(%esp)
1955: e8 ab 25 00 00 call 3f05 <unlink>
195a: e8 4e 25 00 00 call 3ead <fork>
195f: 89 45 ec mov %eax,-0x14(%ebp)
1962: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1966: 74 3a je 19a2 <concreate+0x8a>
1968: 8b 4d f4 mov -0xc(%ebp),%ecx
196b: ba 56 55 55 55 mov $0x55555556,%edx
1970: 89 c8 mov %ecx,%eax
1972: f7 ea imul %edx
1974: 89 c8 mov %ecx,%eax
1976: c1 f8 1f sar $0x1f,%eax
1979: 29 c2 sub %eax,%edx
197b: 89 d0 mov %edx,%eax
197d: 01 c0 add %eax,%eax
197f: 01 d0 add %edx,%eax
1981: 29 c1 sub %eax,%ecx
1983: 89 ca mov %ecx,%edx
1985: 83 fa 01 cmp $0x1,%edx
1988: 75 18 jne 19a2 <concreate+0x8a>
198a: 8d 45 e5 lea -0x1b(%ebp),%eax
198d: 89 44 24 04 mov %eax,0x4(%esp)
1991: c7 04 24 f2 4c 00 00 movl $0x4cf2,(%esp)
1998: e8 78 25 00 00 call 3f15 <link>
199d: e9 87 00 00 00 jmp 1a29 <concreate+0x111>
19a2: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
19a6: 75 3a jne 19e2 <concreate+0xca>
19a8: 8b 4d f4 mov -0xc(%ebp),%ecx
19ab: ba 67 66 66 66 mov $0x66666667,%edx
19b0: 89 c8 mov %ecx,%eax
19b2: f7 ea imul %edx
19b4: d1 fa sar %edx
19b6: 89 c8 mov %ecx,%eax
19b8: c1 f8 1f sar $0x1f,%eax
19bb: 29 c2 sub %eax,%edx
19bd: 89 d0 mov %edx,%eax
19bf: c1 e0 02 shl $0x2,%eax
19c2: 01 d0 add %edx,%eax
19c4: 29 c1 sub %eax,%ecx
19c6: 89 ca mov %ecx,%edx
19c8: 83 fa 01 cmp $0x1,%edx
19cb: 75 15 jne 19e2 <concreate+0xca>
19cd: 8d 45 e5 lea -0x1b(%ebp),%eax
19d0: 89 44 24 04 mov %eax,0x4(%esp)
19d4: c7 04 24 f2 4c 00 00 movl $0x4cf2,(%esp)
19db: e8 35 25 00 00 call 3f15 <link>
19e0: eb 47 jmp 1a29 <concreate+0x111>
19e2: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
19e9: 00
19ea: 8d 45 e5 lea -0x1b(%ebp),%eax
19ed: 89 04 24 mov %eax,(%esp)
19f0: e8 00 25 00 00 call 3ef5 <open>
19f5: 89 45 e8 mov %eax,-0x18(%ebp)
19f8: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
19fc: 79 20 jns 1a1e <concreate+0x106>
19fe: 8d 45 e5 lea -0x1b(%ebp),%eax
1a01: 89 44 24 08 mov %eax,0x8(%esp)
1a05: c7 44 24 04 f5 4c 00 movl $0x4cf5,0x4(%esp)
1a0c: 00
1a0d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1a14: e8 44 26 00 00 call 405d <printf>
1a19: e8 97 24 00 00 call 3eb5 <exit>
1a1e: 8b 45 e8 mov -0x18(%ebp),%eax
1a21: 89 04 24 mov %eax,(%esp)
1a24: e8 b4 24 00 00 call 3edd <close>
1a29: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1a2d: 75 05 jne 1a34 <concreate+0x11c>
1a2f: e8 81 24 00 00 call 3eb5 <exit>
1a34: e8 84 24 00 00 call 3ebd <wait>
1a39: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1a3d: 83 7d f4 27 cmpl $0x27,-0xc(%ebp)
1a41: 0f 8e ff fe ff ff jle 1946 <concreate+0x2e>
1a47: c7 44 24 08 28 00 00 movl $0x28,0x8(%esp)
1a4e: 00
1a4f: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1a56: 00
1a57: 8d 45 bd lea -0x43(%ebp),%eax
1a5a: 89 04 24 mov %eax,(%esp)
1a5d: e8 a6 22 00 00 call 3d08 <memset>
1a62: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1a69: 00
1a6a: c7 04 24 b7 4c 00 00 movl $0x4cb7,(%esp)
1a71: e8 7f 24 00 00 call 3ef5 <open>
1a76: 89 45 e8 mov %eax,-0x18(%ebp)
1a79: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
1a80: e9 a1 00 00 00 jmp 1b26 <concreate+0x20e>
1a85: 0f b7 45 ac movzwl -0x54(%ebp),%eax
1a89: 66 85 c0 test %ax,%ax
1a8c: 75 05 jne 1a93 <concreate+0x17b>
1a8e: e9 93 00 00 00 jmp 1b26 <concreate+0x20e>
1a93: 0f b6 45 ae movzbl -0x52(%ebp),%eax
1a97: 3c 43 cmp $0x43,%al
1a99: 0f 85 87 00 00 00 jne 1b26 <concreate+0x20e>
1a9f: 0f b6 45 b0 movzbl -0x50(%ebp),%eax
1aa3: 84 c0 test %al,%al
1aa5: 75 7f jne 1b26 <concreate+0x20e>
1aa7: 0f b6 45 af movzbl -0x51(%ebp),%eax
1aab: 0f be c0 movsbl %al,%eax
1aae: 83 e8 30 sub $0x30,%eax
1ab1: 89 45 f4 mov %eax,-0xc(%ebp)
1ab4: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
1ab8: 78 08 js 1ac2 <concreate+0x1aa>
1aba: 8b 45 f4 mov -0xc(%ebp),%eax
1abd: 83 f8 27 cmp $0x27,%eax
1ac0: 76 23 jbe 1ae5 <concreate+0x1cd>
1ac2: 8d 45 ac lea -0x54(%ebp),%eax
1ac5: 83 c0 02 add $0x2,%eax
1ac8: 89 44 24 08 mov %eax,0x8(%esp)
1acc: c7 44 24 04 11 4d 00 movl $0x4d11,0x4(%esp)
1ad3: 00
1ad4: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1adb: e8 7d 25 00 00 call 405d <printf>
1ae0: e8 d0 23 00 00 call 3eb5 <exit>
1ae5: 8d 55 bd lea -0x43(%ebp),%edx
1ae8: 8b 45 f4 mov -0xc(%ebp),%eax
1aeb: 01 d0 add %edx,%eax
1aed: 0f b6 00 movzbl (%eax),%eax
1af0: 84 c0 test %al,%al
1af2: 74 23 je 1b17 <concreate+0x1ff>
1af4: 8d 45 ac lea -0x54(%ebp),%eax
1af7: 83 c0 02 add $0x2,%eax
1afa: 89 44 24 08 mov %eax,0x8(%esp)
1afe: c7 44 24 04 2a 4d 00 movl $0x4d2a,0x4(%esp)
1b05: 00
1b06: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1b0d: e8 4b 25 00 00 call 405d <printf>
1b12: e8 9e 23 00 00 call 3eb5 <exit>
1b17: 8d 55 bd lea -0x43(%ebp),%edx
1b1a: 8b 45 f4 mov -0xc(%ebp),%eax
1b1d: 01 d0 add %edx,%eax
1b1f: c6 00 01 movb $0x1,(%eax)
1b22: 83 45 f0 01 addl $0x1,-0x10(%ebp)
1b26: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
1b2d: 00
1b2e: 8d 45 ac lea -0x54(%ebp),%eax
1b31: 89 44 24 04 mov %eax,0x4(%esp)
1b35: 8b 45 e8 mov -0x18(%ebp),%eax
1b38: 89 04 24 mov %eax,(%esp)
1b3b: e8 8d 23 00 00 call 3ecd <read>
1b40: 85 c0 test %eax,%eax
1b42: 0f 8f 3d ff ff ff jg 1a85 <concreate+0x16d>
1b48: 8b 45 e8 mov -0x18(%ebp),%eax
1b4b: 89 04 24 mov %eax,(%esp)
1b4e: e8 8a 23 00 00 call 3edd <close>
1b53: 83 7d f0 28 cmpl $0x28,-0x10(%ebp)
1b57: 74 19 je 1b72 <concreate+0x25a>
1b59: c7 44 24 04 48 4d 00 movl $0x4d48,0x4(%esp)
1b60: 00
1b61: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1b68: e8 f0 24 00 00 call 405d <printf>
1b6d: e8 43 23 00 00 call 3eb5 <exit>
1b72: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1b79: e9 2d 01 00 00 jmp 1cab <concreate+0x393>
1b7e: 8b 45 f4 mov -0xc(%ebp),%eax
1b81: 83 c0 30 add $0x30,%eax
1b84: 88 45 e6 mov %al,-0x1a(%ebp)
1b87: e8 21 23 00 00 call 3ead <fork>
1b8c: 89 45 ec mov %eax,-0x14(%ebp)
1b8f: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1b93: 79 19 jns 1bae <concreate+0x296>
1b95: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
1b9c: 00
1b9d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1ba4: e8 b4 24 00 00 call 405d <printf>
1ba9: e8 07 23 00 00 call 3eb5 <exit>
1bae: 8b 4d f4 mov -0xc(%ebp),%ecx
1bb1: ba 56 55 55 55 mov $0x55555556,%edx
1bb6: 89 c8 mov %ecx,%eax
1bb8: f7 ea imul %edx
1bba: 89 c8 mov %ecx,%eax
1bbc: c1 f8 1f sar $0x1f,%eax
1bbf: 29 c2 sub %eax,%edx
1bc1: 89 d0 mov %edx,%eax
1bc3: 01 c0 add %eax,%eax
1bc5: 01 d0 add %edx,%eax
1bc7: 29 c1 sub %eax,%ecx
1bc9: 89 ca mov %ecx,%edx
1bcb: 85 d2 test %edx,%edx
1bcd: 75 06 jne 1bd5 <concreate+0x2bd>
1bcf: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1bd3: 74 28 je 1bfd <concreate+0x2e5>
1bd5: 8b 4d f4 mov -0xc(%ebp),%ecx
1bd8: ba 56 55 55 55 mov $0x55555556,%edx
1bdd: 89 c8 mov %ecx,%eax
1bdf: f7 ea imul %edx
1be1: 89 c8 mov %ecx,%eax
1be3: c1 f8 1f sar $0x1f,%eax
1be6: 29 c2 sub %eax,%edx
1be8: 89 d0 mov %edx,%eax
1bea: 01 c0 add %eax,%eax
1bec: 01 d0 add %edx,%eax
1bee: 29 c1 sub %eax,%ecx
1bf0: 89 ca mov %ecx,%edx
1bf2: 83 fa 01 cmp $0x1,%edx
1bf5: 75 74 jne 1c6b <concreate+0x353>
1bf7: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1bfb: 74 6e je 1c6b <concreate+0x353>
1bfd: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1c04: 00
1c05: 8d 45 e5 lea -0x1b(%ebp),%eax
1c08: 89 04 24 mov %eax,(%esp)
1c0b: e8 e5 22 00 00 call 3ef5 <open>
1c10: 89 04 24 mov %eax,(%esp)
1c13: e8 c5 22 00 00 call 3edd <close>
1c18: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1c1f: 00
1c20: 8d 45 e5 lea -0x1b(%ebp),%eax
1c23: 89 04 24 mov %eax,(%esp)
1c26: e8 ca 22 00 00 call 3ef5 <open>
1c2b: 89 04 24 mov %eax,(%esp)
1c2e: e8 aa 22 00 00 call 3edd <close>
1c33: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1c3a: 00
1c3b: 8d 45 e5 lea -0x1b(%ebp),%eax
1c3e: 89 04 24 mov %eax,(%esp)
1c41: e8 af 22 00 00 call 3ef5 <open>
1c46: 89 04 24 mov %eax,(%esp)
1c49: e8 8f 22 00 00 call 3edd <close>
1c4e: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
1c55: 00
1c56: 8d 45 e5 lea -0x1b(%ebp),%eax
1c59: 89 04 24 mov %eax,(%esp)
1c5c: e8 94 22 00 00 call 3ef5 <open>
1c61: 89 04 24 mov %eax,(%esp)
1c64: e8 74 22 00 00 call 3edd <close>
1c69: eb 2c jmp 1c97 <concreate+0x37f>
1c6b: 8d 45 e5 lea -0x1b(%ebp),%eax
1c6e: 89 04 24 mov %eax,(%esp)
1c71: e8 8f 22 00 00 call 3f05 <unlink>
1c76: 8d 45 e5 lea -0x1b(%ebp),%eax
1c79: 89 04 24 mov %eax,(%esp)
1c7c: e8 84 22 00 00 call 3f05 <unlink>
1c81: 8d 45 e5 lea -0x1b(%ebp),%eax
1c84: 89 04 24 mov %eax,(%esp)
1c87: e8 79 22 00 00 call 3f05 <unlink>
1c8c: 8d 45 e5 lea -0x1b(%ebp),%eax
1c8f: 89 04 24 mov %eax,(%esp)
1c92: e8 6e 22 00 00 call 3f05 <unlink>
1c97: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1c9b: 75 05 jne 1ca2 <concreate+0x38a>
1c9d: e8 13 22 00 00 call 3eb5 <exit>
1ca2: e8 16 22 00 00 call 3ebd <wait>
1ca7: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1cab: 83 7d f4 27 cmpl $0x27,-0xc(%ebp)
1caf: 0f 8e c9 fe ff ff jle 1b7e <concreate+0x266>
1cb5: c7 44 24 04 79 4d 00 movl $0x4d79,0x4(%esp)
1cbc: 00
1cbd: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1cc4: e8 94 23 00 00 call 405d <printf>
1cc9: c9 leave
1cca: c3 ret
00001ccb <linkunlink>:
1ccb: 55 push %ebp
1ccc: 89 e5 mov %esp,%ebp
1cce: 83 ec 28 sub $0x28,%esp
1cd1: c7 44 24 04 87 4d 00 movl $0x4d87,0x4(%esp)
1cd8: 00
1cd9: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1ce0: e8 78 23 00 00 call 405d <printf>
1ce5: c7 04 24 03 49 00 00 movl $0x4903,(%esp)
1cec: e8 14 22 00 00 call 3f05 <unlink>
1cf1: e8 b7 21 00 00 call 3ead <fork>
1cf6: 89 45 ec mov %eax,-0x14(%ebp)
1cf9: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1cfd: 79 19 jns 1d18 <linkunlink+0x4d>
1cff: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
1d06: 00
1d07: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1d0e: e8 4a 23 00 00 call 405d <printf>
1d13: e8 9d 21 00 00 call 3eb5 <exit>
1d18: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1d1c: 74 07 je 1d25 <linkunlink+0x5a>
1d1e: b8 01 00 00 00 mov $0x1,%eax
1d23: eb 05 jmp 1d2a <linkunlink+0x5f>
1d25: b8 61 00 00 00 mov $0x61,%eax
1d2a: 89 45 f0 mov %eax,-0x10(%ebp)
1d2d: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1d34: e9 8e 00 00 00 jmp 1dc7 <linkunlink+0xfc>
1d39: 8b 45 f0 mov -0x10(%ebp),%eax
1d3c: 69 c0 6d 4e c6 41 imul $0x41c64e6d,%eax,%eax
1d42: 05 39 30 00 00 add $0x3039,%eax
1d47: 89 45 f0 mov %eax,-0x10(%ebp)
1d4a: 8b 4d f0 mov -0x10(%ebp),%ecx
1d4d: ba ab aa aa aa mov $0xaaaaaaab,%edx
1d52: 89 c8 mov %ecx,%eax
1d54: f7 e2 mul %edx
1d56: d1 ea shr %edx
1d58: 89 d0 mov %edx,%eax
1d5a: 01 c0 add %eax,%eax
1d5c: 01 d0 add %edx,%eax
1d5e: 29 c1 sub %eax,%ecx
1d60: 89 ca mov %ecx,%edx
1d62: 85 d2 test %edx,%edx
1d64: 75 1e jne 1d84 <linkunlink+0xb9>
1d66: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
1d6d: 00
1d6e: c7 04 24 03 49 00 00 movl $0x4903,(%esp)
1d75: e8 7b 21 00 00 call 3ef5 <open>
1d7a: 89 04 24 mov %eax,(%esp)
1d7d: e8 5b 21 00 00 call 3edd <close>
1d82: eb 3f jmp 1dc3 <linkunlink+0xf8>
1d84: 8b 4d f0 mov -0x10(%ebp),%ecx
1d87: ba ab aa aa aa mov $0xaaaaaaab,%edx
1d8c: 89 c8 mov %ecx,%eax
1d8e: f7 e2 mul %edx
1d90: d1 ea shr %edx
1d92: 89 d0 mov %edx,%eax
1d94: 01 c0 add %eax,%eax
1d96: 01 d0 add %edx,%eax
1d98: 29 c1 sub %eax,%ecx
1d9a: 89 ca mov %ecx,%edx
1d9c: 83 fa 01 cmp $0x1,%edx
1d9f: 75 16 jne 1db7 <linkunlink+0xec>
1da1: c7 44 24 04 03 49 00 movl $0x4903,0x4(%esp)
1da8: 00
1da9: c7 04 24 98 4d 00 00 movl $0x4d98,(%esp)
1db0: e8 60 21 00 00 call 3f15 <link>
1db5: eb 0c jmp 1dc3 <linkunlink+0xf8>
1db7: c7 04 24 03 49 00 00 movl $0x4903,(%esp)
1dbe: e8 42 21 00 00 call 3f05 <unlink>
1dc3: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1dc7: 83 7d f4 63 cmpl $0x63,-0xc(%ebp)
1dcb: 0f 8e 68 ff ff ff jle 1d39 <linkunlink+0x6e>
1dd1: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
1dd5: 74 07 je 1dde <linkunlink+0x113>
1dd7: e8 e1 20 00 00 call 3ebd <wait>
1ddc: eb 05 jmp 1de3 <linkunlink+0x118>
1dde: e8 d2 20 00 00 call 3eb5 <exit>
1de3: c7 44 24 04 9c 4d 00 movl $0x4d9c,0x4(%esp)
1dea: 00
1deb: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1df2: e8 66 22 00 00 call 405d <printf>
1df7: c9 leave
1df8: c3 ret
00001df9 <bigdir>:
1df9: 55 push %ebp
1dfa: 89 e5 mov %esp,%ebp
1dfc: 83 ec 38 sub $0x38,%esp
1dff: c7 44 24 04 ab 4d 00 movl $0x4dab,0x4(%esp)
1e06: 00
1e07: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1e0e: e8 4a 22 00 00 call 405d <printf>
1e13: c7 04 24 b8 4d 00 00 movl $0x4db8,(%esp)
1e1a: e8 e6 20 00 00 call 3f05 <unlink>
1e1f: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
1e26: 00
1e27: c7 04 24 b8 4d 00 00 movl $0x4db8,(%esp)
1e2e: e8 c2 20 00 00 call 3ef5 <open>
1e33: 89 45 f0 mov %eax,-0x10(%ebp)
1e36: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
1e3a: 79 19 jns 1e55 <bigdir+0x5c>
1e3c: c7 44 24 04 bb 4d 00 movl $0x4dbb,0x4(%esp)
1e43: 00
1e44: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1e4b: e8 0d 22 00 00 call 405d <printf>
1e50: e8 60 20 00 00 call 3eb5 <exit>
1e55: 8b 45 f0 mov -0x10(%ebp),%eax
1e58: 89 04 24 mov %eax,(%esp)
1e5b: e8 7d 20 00 00 call 3edd <close>
1e60: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1e67: eb 64 jmp 1ecd <bigdir+0xd4>
1e69: c6 45 e6 78 movb $0x78,-0x1a(%ebp)
1e6d: 8b 45 f4 mov -0xc(%ebp),%eax
1e70: 8d 50 3f lea 0x3f(%eax),%edx
1e73: 85 c0 test %eax,%eax
1e75: 0f 48 c2 cmovs %edx,%eax
1e78: c1 f8 06 sar $0x6,%eax
1e7b: 83 c0 30 add $0x30,%eax
1e7e: 88 45 e7 mov %al,-0x19(%ebp)
1e81: 8b 45 f4 mov -0xc(%ebp),%eax
1e84: 99 cltd
1e85: c1 ea 1a shr $0x1a,%edx
1e88: 01 d0 add %edx,%eax
1e8a: 83 e0 3f and $0x3f,%eax
1e8d: 29 d0 sub %edx,%eax
1e8f: 83 c0 30 add $0x30,%eax
1e92: 88 45 e8 mov %al,-0x18(%ebp)
1e95: c6 45 e9 00 movb $0x0,-0x17(%ebp)
1e99: 8d 45 e6 lea -0x1a(%ebp),%eax
1e9c: 89 44 24 04 mov %eax,0x4(%esp)
1ea0: c7 04 24 b8 4d 00 00 movl $0x4db8,(%esp)
1ea7: e8 69 20 00 00 call 3f15 <link>
1eac: 85 c0 test %eax,%eax
1eae: 74 19 je 1ec9 <bigdir+0xd0>
1eb0: c7 44 24 04 d1 4d 00 movl $0x4dd1,0x4(%esp)
1eb7: 00
1eb8: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1ebf: e8 99 21 00 00 call 405d <printf>
1ec4: e8 ec 1f 00 00 call 3eb5 <exit>
1ec9: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1ecd: 81 7d f4 f3 01 00 00 cmpl $0x1f3,-0xc(%ebp)
1ed4: 7e 93 jle 1e69 <bigdir+0x70>
1ed6: c7 04 24 b8 4d 00 00 movl $0x4db8,(%esp)
1edd: e8 23 20 00 00 call 3f05 <unlink>
1ee2: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
1ee9: eb 5c jmp 1f47 <bigdir+0x14e>
1eeb: c6 45 e6 78 movb $0x78,-0x1a(%ebp)
1eef: 8b 45 f4 mov -0xc(%ebp),%eax
1ef2: 8d 50 3f lea 0x3f(%eax),%edx
1ef5: 85 c0 test %eax,%eax
1ef7: 0f 48 c2 cmovs %edx,%eax
1efa: c1 f8 06 sar $0x6,%eax
1efd: 83 c0 30 add $0x30,%eax
1f00: 88 45 e7 mov %al,-0x19(%ebp)
1f03: 8b 45 f4 mov -0xc(%ebp),%eax
1f06: 99 cltd
1f07: c1 ea 1a shr $0x1a,%edx
1f0a: 01 d0 add %edx,%eax
1f0c: 83 e0 3f and $0x3f,%eax
1f0f: 29 d0 sub %edx,%eax
1f11: 83 c0 30 add $0x30,%eax
1f14: 88 45 e8 mov %al,-0x18(%ebp)
1f17: c6 45 e9 00 movb $0x0,-0x17(%ebp)
1f1b: 8d 45 e6 lea -0x1a(%ebp),%eax
1f1e: 89 04 24 mov %eax,(%esp)
1f21: e8 df 1f 00 00 call 3f05 <unlink>
1f26: 85 c0 test %eax,%eax
1f28: 74 19 je 1f43 <bigdir+0x14a>
1f2a: c7 44 24 04 e5 4d 00 movl $0x4de5,0x4(%esp)
1f31: 00
1f32: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1f39: e8 1f 21 00 00 call 405d <printf>
1f3e: e8 72 1f 00 00 call 3eb5 <exit>
1f43: 83 45 f4 01 addl $0x1,-0xc(%ebp)
1f47: 81 7d f4 f3 01 00 00 cmpl $0x1f3,-0xc(%ebp)
1f4e: 7e 9b jle 1eeb <bigdir+0xf2>
1f50: c7 44 24 04 fa 4d 00 movl $0x4dfa,0x4(%esp)
1f57: 00
1f58: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1f5f: e8 f9 20 00 00 call 405d <printf>
1f64: c9 leave
1f65: c3 ret
00001f66 <subdir>:
1f66: 55 push %ebp
1f67: 89 e5 mov %esp,%ebp
1f69: 83 ec 28 sub $0x28,%esp
1f6c: c7 44 24 04 05 4e 00 movl $0x4e05,0x4(%esp)
1f73: 00
1f74: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1f7b: e8 dd 20 00 00 call 405d <printf>
1f80: c7 04 24 12 4e 00 00 movl $0x4e12,(%esp)
1f87: e8 79 1f 00 00 call 3f05 <unlink>
1f8c: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
1f93: e8 85 1f 00 00 call 3f1d <mkdir>
1f98: 85 c0 test %eax,%eax
1f9a: 74 19 je 1fb5 <subdir+0x4f>
1f9c: c7 44 24 04 18 4e 00 movl $0x4e18,0x4(%esp)
1fa3: 00
1fa4: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1fab: e8 ad 20 00 00 call 405d <printf>
1fb0: e8 00 1f 00 00 call 3eb5 <exit>
1fb5: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
1fbc: 00
1fbd: c7 04 24 30 4e 00 00 movl $0x4e30,(%esp)
1fc4: e8 2c 1f 00 00 call 3ef5 <open>
1fc9: 89 45 f4 mov %eax,-0xc(%ebp)
1fcc: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
1fd0: 79 19 jns 1feb <subdir+0x85>
1fd2: c7 44 24 04 36 4e 00 movl $0x4e36,0x4(%esp)
1fd9: 00
1fda: c7 04 24 01 00 00 00 movl $0x1,(%esp)
1fe1: e8 77 20 00 00 call 405d <printf>
1fe6: e8 ca 1e 00 00 call 3eb5 <exit>
1feb: c7 44 24 08 02 00 00 movl $0x2,0x8(%esp)
1ff2: 00
1ff3: c7 44 24 04 12 4e 00 movl $0x4e12,0x4(%esp)
1ffa: 00
1ffb: 8b 45 f4 mov -0xc(%ebp),%eax
1ffe: 89 04 24 mov %eax,(%esp)
2001: e8 cf 1e 00 00 call 3ed5 <write>
2006: 8b 45 f4 mov -0xc(%ebp),%eax
2009: 89 04 24 mov %eax,(%esp)
200c: e8 cc 1e 00 00 call 3edd <close>
2011: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
2018: e8 e8 1e 00 00 call 3f05 <unlink>
201d: 85 c0 test %eax,%eax
201f: 78 19 js 203a <subdir+0xd4>
2021: c7 44 24 04 4c 4e 00 movl $0x4e4c,0x4(%esp)
2028: 00
2029: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2030: e8 28 20 00 00 call 405d <printf>
2035: e8 7b 1e 00 00 call 3eb5 <exit>
203a: c7 04 24 72 4e 00 00 movl $0x4e72,(%esp)
2041: e8 d7 1e 00 00 call 3f1d <mkdir>
2046: 85 c0 test %eax,%eax
2048: 74 19 je 2063 <subdir+0xfd>
204a: c7 44 24 04 79 4e 00 movl $0x4e79,0x4(%esp)
2051: 00
2052: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2059: e8 ff 1f 00 00 call 405d <printf>
205e: e8 52 1e 00 00 call 3eb5 <exit>
2063: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
206a: 00
206b: c7 04 24 94 4e 00 00 movl $0x4e94,(%esp)
2072: e8 7e 1e 00 00 call 3ef5 <open>
2077: 89 45 f4 mov %eax,-0xc(%ebp)
207a: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
207e: 79 19 jns 2099 <subdir+0x133>
2080: c7 44 24 04 9d 4e 00 movl $0x4e9d,0x4(%esp)
2087: 00
2088: c7 04 24 01 00 00 00 movl $0x1,(%esp)
208f: e8 c9 1f 00 00 call 405d <printf>
2094: e8 1c 1e 00 00 call 3eb5 <exit>
2099: c7 44 24 08 02 00 00 movl $0x2,0x8(%esp)
20a0: 00
20a1: c7 44 24 04 b5 4e 00 movl $0x4eb5,0x4(%esp)
20a8: 00
20a9: 8b 45 f4 mov -0xc(%ebp),%eax
20ac: 89 04 24 mov %eax,(%esp)
20af: e8 21 1e 00 00 call 3ed5 <write>
20b4: 8b 45 f4 mov -0xc(%ebp),%eax
20b7: 89 04 24 mov %eax,(%esp)
20ba: e8 1e 1e 00 00 call 3edd <close>
20bf: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
20c6: 00
20c7: c7 04 24 b8 4e 00 00 movl $0x4eb8,(%esp)
20ce: e8 22 1e 00 00 call 3ef5 <open>
20d3: 89 45 f4 mov %eax,-0xc(%ebp)
20d6: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
20da: 79 19 jns 20f5 <subdir+0x18f>
20dc: c7 44 24 04 c4 4e 00 movl $0x4ec4,0x4(%esp)
20e3: 00
20e4: c7 04 24 01 00 00 00 movl $0x1,(%esp)
20eb: e8 6d 1f 00 00 call 405d <printf>
20f0: e8 c0 1d 00 00 call 3eb5 <exit>
20f5: c7 44 24 08 00 20 00 movl $0x2000,0x8(%esp)
20fc: 00
20fd: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
2104: 00
2105: 8b 45 f4 mov -0xc(%ebp),%eax
2108: 89 04 24 mov %eax,(%esp)
210b: e8 bd 1d 00 00 call 3ecd <read>
2110: 89 45 f0 mov %eax,-0x10(%ebp)
2113: 83 7d f0 02 cmpl $0x2,-0x10(%ebp)
2117: 75 0b jne 2124 <subdir+0x1be>
2119: 0f b6 05 e0 8a 00 00 movzbl 0x8ae0,%eax
2120: 3c 66 cmp $0x66,%al
2122: 74 19 je 213d <subdir+0x1d7>
2124: c7 44 24 04 dd 4e 00 movl $0x4edd,0x4(%esp)
212b: 00
212c: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2133: e8 25 1f 00 00 call 405d <printf>
2138: e8 78 1d 00 00 call 3eb5 <exit>
213d: 8b 45 f4 mov -0xc(%ebp),%eax
2140: 89 04 24 mov %eax,(%esp)
2143: e8 95 1d 00 00 call 3edd <close>
2148: c7 44 24 04 f8 4e 00 movl $0x4ef8,0x4(%esp)
214f: 00
2150: c7 04 24 94 4e 00 00 movl $0x4e94,(%esp)
2157: e8 b9 1d 00 00 call 3f15 <link>
215c: 85 c0 test %eax,%eax
215e: 74 19 je 2179 <subdir+0x213>
2160: c7 44 24 04 04 4f 00 movl $0x4f04,0x4(%esp)
2167: 00
2168: c7 04 24 01 00 00 00 movl $0x1,(%esp)
216f: e8 e9 1e 00 00 call 405d <printf>
2174: e8 3c 1d 00 00 call 3eb5 <exit>
2179: c7 04 24 94 4e 00 00 movl $0x4e94,(%esp)
2180: e8 80 1d 00 00 call 3f05 <unlink>
2185: 85 c0 test %eax,%eax
2187: 74 19 je 21a2 <subdir+0x23c>
2189: c7 44 24 04 25 4f 00 movl $0x4f25,0x4(%esp)
2190: 00
2191: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2198: e8 c0 1e 00 00 call 405d <printf>
219d: e8 13 1d 00 00 call 3eb5 <exit>
21a2: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
21a9: 00
21aa: c7 04 24 94 4e 00 00 movl $0x4e94,(%esp)
21b1: e8 3f 1d 00 00 call 3ef5 <open>
21b6: 85 c0 test %eax,%eax
21b8: 78 19 js 21d3 <subdir+0x26d>
21ba: c7 44 24 04 40 4f 00 movl $0x4f40,0x4(%esp)
21c1: 00
21c2: c7 04 24 01 00 00 00 movl $0x1,(%esp)
21c9: e8 8f 1e 00 00 call 405d <printf>
21ce: e8 e2 1c 00 00 call 3eb5 <exit>
21d3: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
21da: e8 46 1d 00 00 call 3f25 <chdir>
21df: 85 c0 test %eax,%eax
21e1: 74 19 je 21fc <subdir+0x296>
21e3: c7 44 24 04 64 4f 00 movl $0x4f64,0x4(%esp)
21ea: 00
21eb: c7 04 24 01 00 00 00 movl $0x1,(%esp)
21f2: e8 66 1e 00 00 call 405d <printf>
21f7: e8 b9 1c 00 00 call 3eb5 <exit>
21fc: c7 04 24 75 4f 00 00 movl $0x4f75,(%esp)
2203: e8 1d 1d 00 00 call 3f25 <chdir>
2208: 85 c0 test %eax,%eax
220a: 74 19 je 2225 <subdir+0x2bf>
220c: c7 44 24 04 81 4f 00 movl $0x4f81,0x4(%esp)
2213: 00
2214: c7 04 24 01 00 00 00 movl $0x1,(%esp)
221b: e8 3d 1e 00 00 call 405d <printf>
2220: e8 90 1c 00 00 call 3eb5 <exit>
2225: c7 04 24 9b 4f 00 00 movl $0x4f9b,(%esp)
222c: e8 f4 1c 00 00 call 3f25 <chdir>
2231: 85 c0 test %eax,%eax
2233: 74 19 je 224e <subdir+0x2e8>
2235: c7 44 24 04 81 4f 00 movl $0x4f81,0x4(%esp)
223c: 00
223d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2244: e8 14 1e 00 00 call 405d <printf>
2249: e8 67 1c 00 00 call 3eb5 <exit>
224e: c7 04 24 aa 4f 00 00 movl $0x4faa,(%esp)
2255: e8 cb 1c 00 00 call 3f25 <chdir>
225a: 85 c0 test %eax,%eax
225c: 74 19 je 2277 <subdir+0x311>
225e: c7 44 24 04 af 4f 00 movl $0x4faf,0x4(%esp)
2265: 00
2266: c7 04 24 01 00 00 00 movl $0x1,(%esp)
226d: e8 eb 1d 00 00 call 405d <printf>
2272: e8 3e 1c 00 00 call 3eb5 <exit>
2277: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
227e: 00
227f: c7 04 24 f8 4e 00 00 movl $0x4ef8,(%esp)
2286: e8 6a 1c 00 00 call 3ef5 <open>
228b: 89 45 f4 mov %eax,-0xc(%ebp)
228e: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2292: 79 19 jns 22ad <subdir+0x347>
2294: c7 44 24 04 c2 4f 00 movl $0x4fc2,0x4(%esp)
229b: 00
229c: c7 04 24 01 00 00 00 movl $0x1,(%esp)
22a3: e8 b5 1d 00 00 call 405d <printf>
22a8: e8 08 1c 00 00 call 3eb5 <exit>
22ad: c7 44 24 08 00 20 00 movl $0x2000,0x8(%esp)
22b4: 00
22b5: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
22bc: 00
22bd: 8b 45 f4 mov -0xc(%ebp),%eax
22c0: 89 04 24 mov %eax,(%esp)
22c3: e8 05 1c 00 00 call 3ecd <read>
22c8: 83 f8 02 cmp $0x2,%eax
22cb: 74 19 je 22e6 <subdir+0x380>
22cd: c7 44 24 04 da 4f 00 movl $0x4fda,0x4(%esp)
22d4: 00
22d5: c7 04 24 01 00 00 00 movl $0x1,(%esp)
22dc: e8 7c 1d 00 00 call 405d <printf>
22e1: e8 cf 1b 00 00 call 3eb5 <exit>
22e6: 8b 45 f4 mov -0xc(%ebp),%eax
22e9: 89 04 24 mov %eax,(%esp)
22ec: e8 ec 1b 00 00 call 3edd <close>
22f1: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
22f8: 00
22f9: c7 04 24 94 4e 00 00 movl $0x4e94,(%esp)
2300: e8 f0 1b 00 00 call 3ef5 <open>
2305: 85 c0 test %eax,%eax
2307: 78 19 js 2322 <subdir+0x3bc>
2309: c7 44 24 04 f8 4f 00 movl $0x4ff8,0x4(%esp)
2310: 00
2311: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2318: e8 40 1d 00 00 call 405d <printf>
231d: e8 93 1b 00 00 call 3eb5 <exit>
2322: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
2329: 00
232a: c7 04 24 1d 50 00 00 movl $0x501d,(%esp)
2331: e8 bf 1b 00 00 call 3ef5 <open>
2336: 85 c0 test %eax,%eax
2338: 78 19 js 2353 <subdir+0x3ed>
233a: c7 44 24 04 26 50 00 movl $0x5026,0x4(%esp)
2341: 00
2342: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2349: e8 0f 1d 00 00 call 405d <printf>
234e: e8 62 1b 00 00 call 3eb5 <exit>
2353: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
235a: 00
235b: c7 04 24 42 50 00 00 movl $0x5042,(%esp)
2362: e8 8e 1b 00 00 call 3ef5 <open>
2367: 85 c0 test %eax,%eax
2369: 78 19 js 2384 <subdir+0x41e>
236b: c7 44 24 04 4b 50 00 movl $0x504b,0x4(%esp)
2372: 00
2373: c7 04 24 01 00 00 00 movl $0x1,(%esp)
237a: e8 de 1c 00 00 call 405d <printf>
237f: e8 31 1b 00 00 call 3eb5 <exit>
2384: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
238b: 00
238c: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
2393: e8 5d 1b 00 00 call 3ef5 <open>
2398: 85 c0 test %eax,%eax
239a: 78 19 js 23b5 <subdir+0x44f>
239c: c7 44 24 04 67 50 00 movl $0x5067,0x4(%esp)
23a3: 00
23a4: c7 04 24 01 00 00 00 movl $0x1,(%esp)
23ab: e8 ad 1c 00 00 call 405d <printf>
23b0: e8 00 1b 00 00 call 3eb5 <exit>
23b5: c7 44 24 04 02 00 00 movl $0x2,0x4(%esp)
23bc: 00
23bd: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
23c4: e8 2c 1b 00 00 call 3ef5 <open>
23c9: 85 c0 test %eax,%eax
23cb: 78 19 js 23e6 <subdir+0x480>
23cd: c7 44 24 04 7d 50 00 movl $0x507d,0x4(%esp)
23d4: 00
23d5: c7 04 24 01 00 00 00 movl $0x1,(%esp)
23dc: e8 7c 1c 00 00 call 405d <printf>
23e1: e8 cf 1a 00 00 call 3eb5 <exit>
23e6: c7 44 24 04 01 00 00 movl $0x1,0x4(%esp)
23ed: 00
23ee: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
23f5: e8 fb 1a 00 00 call 3ef5 <open>
23fa: 85 c0 test %eax,%eax
23fc: 78 19 js 2417 <subdir+0x4b1>
23fe: c7 44 24 04 96 50 00 movl $0x5096,0x4(%esp)
2405: 00
2406: c7 04 24 01 00 00 00 movl $0x1,(%esp)
240d: e8 4b 1c 00 00 call 405d <printf>
2412: e8 9e 1a 00 00 call 3eb5 <exit>
2417: c7 44 24 04 b1 50 00 movl $0x50b1,0x4(%esp)
241e: 00
241f: c7 04 24 1d 50 00 00 movl $0x501d,(%esp)
2426: e8 ea 1a 00 00 call 3f15 <link>
242b: 85 c0 test %eax,%eax
242d: 75 19 jne 2448 <subdir+0x4e2>
242f: c7 44 24 04 bc 50 00 movl $0x50bc,0x4(%esp)
2436: 00
2437: c7 04 24 01 00 00 00 movl $0x1,(%esp)
243e: e8 1a 1c 00 00 call 405d <printf>
2443: e8 6d 1a 00 00 call 3eb5 <exit>
2448: c7 44 24 04 b1 50 00 movl $0x50b1,0x4(%esp)
244f: 00
2450: c7 04 24 42 50 00 00 movl $0x5042,(%esp)
2457: e8 b9 1a 00 00 call 3f15 <link>
245c: 85 c0 test %eax,%eax
245e: 75 19 jne 2479 <subdir+0x513>
2460: c7 44 24 04 e0 50 00 movl $0x50e0,0x4(%esp)
2467: 00
2468: c7 04 24 01 00 00 00 movl $0x1,(%esp)
246f: e8 e9 1b 00 00 call 405d <printf>
2474: e8 3c 1a 00 00 call 3eb5 <exit>
2479: c7 44 24 04 f8 4e 00 movl $0x4ef8,0x4(%esp)
2480: 00
2481: c7 04 24 30 4e 00 00 movl $0x4e30,(%esp)
2488: e8 88 1a 00 00 call 3f15 <link>
248d: 85 c0 test %eax,%eax
248f: 75 19 jne 24aa <subdir+0x544>
2491: c7 44 24 04 04 51 00 movl $0x5104,0x4(%esp)
2498: 00
2499: c7 04 24 01 00 00 00 movl $0x1,(%esp)
24a0: e8 b8 1b 00 00 call 405d <printf>
24a5: e8 0b 1a 00 00 call 3eb5 <exit>
24aa: c7 04 24 1d 50 00 00 movl $0x501d,(%esp)
24b1: e8 67 1a 00 00 call 3f1d <mkdir>
24b6: 85 c0 test %eax,%eax
24b8: 75 19 jne 24d3 <subdir+0x56d>
24ba: c7 44 24 04 26 51 00 movl $0x5126,0x4(%esp)
24c1: 00
24c2: c7 04 24 01 00 00 00 movl $0x1,(%esp)
24c9: e8 8f 1b 00 00 call 405d <printf>
24ce: e8 e2 19 00 00 call 3eb5 <exit>
24d3: c7 04 24 42 50 00 00 movl $0x5042,(%esp)
24da: e8 3e 1a 00 00 call 3f1d <mkdir>
24df: 85 c0 test %eax,%eax
24e1: 75 19 jne 24fc <subdir+0x596>
24e3: c7 44 24 04 41 51 00 movl $0x5141,0x4(%esp)
24ea: 00
24eb: c7 04 24 01 00 00 00 movl $0x1,(%esp)
24f2: e8 66 1b 00 00 call 405d <printf>
24f7: e8 b9 19 00 00 call 3eb5 <exit>
24fc: c7 04 24 f8 4e 00 00 movl $0x4ef8,(%esp)
2503: e8 15 1a 00 00 call 3f1d <mkdir>
2508: 85 c0 test %eax,%eax
250a: 75 19 jne 2525 <subdir+0x5bf>
250c: c7 44 24 04 5c 51 00 movl $0x515c,0x4(%esp)
2513: 00
2514: c7 04 24 01 00 00 00 movl $0x1,(%esp)
251b: e8 3d 1b 00 00 call 405d <printf>
2520: e8 90 19 00 00 call 3eb5 <exit>
2525: c7 04 24 42 50 00 00 movl $0x5042,(%esp)
252c: e8 d4 19 00 00 call 3f05 <unlink>
2531: 85 c0 test %eax,%eax
2533: 75 19 jne 254e <subdir+0x5e8>
2535: c7 44 24 04 79 51 00 movl $0x5179,0x4(%esp)
253c: 00
253d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2544: e8 14 1b 00 00 call 405d <printf>
2549: e8 67 19 00 00 call 3eb5 <exit>
254e: c7 04 24 1d 50 00 00 movl $0x501d,(%esp)
2555: e8 ab 19 00 00 call 3f05 <unlink>
255a: 85 c0 test %eax,%eax
255c: 75 19 jne 2577 <subdir+0x611>
255e: c7 44 24 04 95 51 00 movl $0x5195,0x4(%esp)
2565: 00
2566: c7 04 24 01 00 00 00 movl $0x1,(%esp)
256d: e8 eb 1a 00 00 call 405d <printf>
2572: e8 3e 19 00 00 call 3eb5 <exit>
2577: c7 04 24 30 4e 00 00 movl $0x4e30,(%esp)
257e: e8 a2 19 00 00 call 3f25 <chdir>
2583: 85 c0 test %eax,%eax
2585: 75 19 jne 25a0 <subdir+0x63a>
2587: c7 44 24 04 b1 51 00 movl $0x51b1,0x4(%esp)
258e: 00
258f: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2596: e8 c2 1a 00 00 call 405d <printf>
259b: e8 15 19 00 00 call 3eb5 <exit>
25a0: c7 04 24 c9 51 00 00 movl $0x51c9,(%esp)
25a7: e8 79 19 00 00 call 3f25 <chdir>
25ac: 85 c0 test %eax,%eax
25ae: 75 19 jne 25c9 <subdir+0x663>
25b0: c7 44 24 04 cf 51 00 movl $0x51cf,0x4(%esp)
25b7: 00
25b8: c7 04 24 01 00 00 00 movl $0x1,(%esp)
25bf: e8 99 1a 00 00 call 405d <printf>
25c4: e8 ec 18 00 00 call 3eb5 <exit>
25c9: c7 04 24 f8 4e 00 00 movl $0x4ef8,(%esp)
25d0: e8 30 19 00 00 call 3f05 <unlink>
25d5: 85 c0 test %eax,%eax
25d7: 74 19 je 25f2 <subdir+0x68c>
25d9: c7 44 24 04 25 4f 00 movl $0x4f25,0x4(%esp)
25e0: 00
25e1: c7 04 24 01 00 00 00 movl $0x1,(%esp)
25e8: e8 70 1a 00 00 call 405d <printf>
25ed: e8 c3 18 00 00 call 3eb5 <exit>
25f2: c7 04 24 30 4e 00 00 movl $0x4e30,(%esp)
25f9: e8 07 19 00 00 call 3f05 <unlink>
25fe: 85 c0 test %eax,%eax
2600: 74 19 je 261b <subdir+0x6b5>
2602: c7 44 24 04 e7 51 00 movl $0x51e7,0x4(%esp)
2609: 00
260a: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2611: e8 47 1a 00 00 call 405d <printf>
2616: e8 9a 18 00 00 call 3eb5 <exit>
261b: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
2622: e8 de 18 00 00 call 3f05 <unlink>
2627: 85 c0 test %eax,%eax
2629: 75 19 jne 2644 <subdir+0x6de>
262b: c7 44 24 04 fc 51 00 movl $0x51fc,0x4(%esp)
2632: 00
2633: c7 04 24 01 00 00 00 movl $0x1,(%esp)
263a: e8 1e 1a 00 00 call 405d <printf>
263f: e8 71 18 00 00 call 3eb5 <exit>
2644: c7 04 24 1c 52 00 00 movl $0x521c,(%esp)
264b: e8 b5 18 00 00 call 3f05 <unlink>
2650: 85 c0 test %eax,%eax
2652: 79 19 jns 266d <subdir+0x707>
2654: c7 44 24 04 22 52 00 movl $0x5222,0x4(%esp)
265b: 00
265c: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2663: e8 f5 19 00 00 call 405d <printf>
2668: e8 48 18 00 00 call 3eb5 <exit>
266d: c7 04 24 15 4e 00 00 movl $0x4e15,(%esp)
2674: e8 8c 18 00 00 call 3f05 <unlink>
2679: 85 c0 test %eax,%eax
267b: 79 19 jns 2696 <subdir+0x730>
267d: c7 44 24 04 37 52 00 movl $0x5237,0x4(%esp)
2684: 00
2685: c7 04 24 01 00 00 00 movl $0x1,(%esp)
268c: e8 cc 19 00 00 call 405d <printf>
2691: e8 1f 18 00 00 call 3eb5 <exit>
2696: c7 44 24 04 49 52 00 movl $0x5249,0x4(%esp)
269d: 00
269e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
26a5: e8 b3 19 00 00 call 405d <printf>
26aa: c9 leave
26ab: c3 ret
000026ac <bigwrite>:
26ac: 55 push %ebp
26ad: 89 e5 mov %esp,%ebp
26af: 83 ec 28 sub $0x28,%esp
26b2: c7 44 24 04 54 52 00 movl $0x5254,0x4(%esp)
26b9: 00
26ba: c7 04 24 01 00 00 00 movl $0x1,(%esp)
26c1: e8 97 19 00 00 call 405d <printf>
26c6: c7 04 24 63 52 00 00 movl $0x5263,(%esp)
26cd: e8 33 18 00 00 call 3f05 <unlink>
26d2: c7 45 f4 f3 01 00 00 movl $0x1f3,-0xc(%ebp)
26d9: e9 b3 00 00 00 jmp 2791 <bigwrite+0xe5>
26de: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
26e5: 00
26e6: c7 04 24 63 52 00 00 movl $0x5263,(%esp)
26ed: e8 03 18 00 00 call 3ef5 <open>
26f2: 89 45 ec mov %eax,-0x14(%ebp)
26f5: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
26f9: 79 19 jns 2714 <bigwrite+0x68>
26fb: c7 44 24 04 6c 52 00 movl $0x526c,0x4(%esp)
2702: 00
2703: c7 04 24 01 00 00 00 movl $0x1,(%esp)
270a: e8 4e 19 00 00 call 405d <printf>
270f: e8 a1 17 00 00 call 3eb5 <exit>
2714: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
271b: eb 50 jmp 276d <bigwrite+0xc1>
271d: 8b 45 f4 mov -0xc(%ebp),%eax
2720: 89 44 24 08 mov %eax,0x8(%esp)
2724: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
272b: 00
272c: 8b 45 ec mov -0x14(%ebp),%eax
272f: 89 04 24 mov %eax,(%esp)
2732: e8 9e 17 00 00 call 3ed5 <write>
2737: 89 45 e8 mov %eax,-0x18(%ebp)
273a: 8b 45 e8 mov -0x18(%ebp),%eax
273d: 3b 45 f4 cmp -0xc(%ebp),%eax
2740: 74 27 je 2769 <bigwrite+0xbd>
2742: 8b 45 e8 mov -0x18(%ebp),%eax
2745: 89 44 24 0c mov %eax,0xc(%esp)
2749: 8b 45 f4 mov -0xc(%ebp),%eax
274c: 89 44 24 08 mov %eax,0x8(%esp)
2750: c7 44 24 04 84 52 00 movl $0x5284,0x4(%esp)
2757: 00
2758: c7 04 24 01 00 00 00 movl $0x1,(%esp)
275f: e8 f9 18 00 00 call 405d <printf>
2764: e8 4c 17 00 00 call 3eb5 <exit>
2769: 83 45 f0 01 addl $0x1,-0x10(%ebp)
276d: 83 7d f0 01 cmpl $0x1,-0x10(%ebp)
2771: 7e aa jle 271d <bigwrite+0x71>
2773: 8b 45 ec mov -0x14(%ebp),%eax
2776: 89 04 24 mov %eax,(%esp)
2779: e8 5f 17 00 00 call 3edd <close>
277e: c7 04 24 63 52 00 00 movl $0x5263,(%esp)
2785: e8 7b 17 00 00 call 3f05 <unlink>
278a: 81 45 f4 d7 01 00 00 addl $0x1d7,-0xc(%ebp)
2791: 81 7d f4 ff 17 00 00 cmpl $0x17ff,-0xc(%ebp)
2798: 0f 8e 40 ff ff ff jle 26de <bigwrite+0x32>
279e: c7 44 24 04 96 52 00 movl $0x5296,0x4(%esp)
27a5: 00
27a6: c7 04 24 01 00 00 00 movl $0x1,(%esp)
27ad: e8 ab 18 00 00 call 405d <printf>
27b2: c9 leave
27b3: c3 ret
000027b4 <bigfile>:
27b4: 55 push %ebp
27b5: 89 e5 mov %esp,%ebp
27b7: 83 ec 28 sub $0x28,%esp
27ba: c7 44 24 04 a3 52 00 movl $0x52a3,0x4(%esp)
27c1: 00
27c2: c7 04 24 01 00 00 00 movl $0x1,(%esp)
27c9: e8 8f 18 00 00 call 405d <printf>
27ce: c7 04 24 b1 52 00 00 movl $0x52b1,(%esp)
27d5: e8 2b 17 00 00 call 3f05 <unlink>
27da: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
27e1: 00
27e2: c7 04 24 b1 52 00 00 movl $0x52b1,(%esp)
27e9: e8 07 17 00 00 call 3ef5 <open>
27ee: 89 45 ec mov %eax,-0x14(%ebp)
27f1: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
27f5: 79 19 jns 2810 <bigfile+0x5c>
27f7: c7 44 24 04 b9 52 00 movl $0x52b9,0x4(%esp)
27fe: 00
27ff: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2806: e8 52 18 00 00 call 405d <printf>
280b: e8 a5 16 00 00 call 3eb5 <exit>
2810: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
2817: eb 5a jmp 2873 <bigfile+0xbf>
2819: c7 44 24 08 58 02 00 movl $0x258,0x8(%esp)
2820: 00
2821: 8b 45 f4 mov -0xc(%ebp),%eax
2824: 89 44 24 04 mov %eax,0x4(%esp)
2828: c7 04 24 e0 8a 00 00 movl $0x8ae0,(%esp)
282f: e8 d4 14 00 00 call 3d08 <memset>
2834: c7 44 24 08 58 02 00 movl $0x258,0x8(%esp)
283b: 00
283c: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
2843: 00
2844: 8b 45 ec mov -0x14(%ebp),%eax
2847: 89 04 24 mov %eax,(%esp)
284a: e8 86 16 00 00 call 3ed5 <write>
284f: 3d 58 02 00 00 cmp $0x258,%eax
2854: 74 19 je 286f <bigfile+0xbb>
2856: c7 44 24 04 cf 52 00 movl $0x52cf,0x4(%esp)
285d: 00
285e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2865: e8 f3 17 00 00 call 405d <printf>
286a: e8 46 16 00 00 call 3eb5 <exit>
286f: 83 45 f4 01 addl $0x1,-0xc(%ebp)
2873: 83 7d f4 13 cmpl $0x13,-0xc(%ebp)
2877: 7e a0 jle 2819 <bigfile+0x65>
2879: 8b 45 ec mov -0x14(%ebp),%eax
287c: 89 04 24 mov %eax,(%esp)
287f: e8 59 16 00 00 call 3edd <close>
2884: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
288b: 00
288c: c7 04 24 b1 52 00 00 movl $0x52b1,(%esp)
2893: e8 5d 16 00 00 call 3ef5 <open>
2898: 89 45 ec mov %eax,-0x14(%ebp)
289b: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
289f: 79 19 jns 28ba <bigfile+0x106>
28a1: c7 44 24 04 e5 52 00 movl $0x52e5,0x4(%esp)
28a8: 00
28a9: c7 04 24 01 00 00 00 movl $0x1,(%esp)
28b0: e8 a8 17 00 00 call 405d <printf>
28b5: e8 fb 15 00 00 call 3eb5 <exit>
28ba: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
28c1: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
28c8: c7 44 24 08 2c 01 00 movl $0x12c,0x8(%esp)
28cf: 00
28d0: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
28d7: 00
28d8: 8b 45 ec mov -0x14(%ebp),%eax
28db: 89 04 24 mov %eax,(%esp)
28de: e8 ea 15 00 00 call 3ecd <read>
28e3: 89 45 e8 mov %eax,-0x18(%ebp)
28e6: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
28ea: 79 19 jns 2905 <bigfile+0x151>
28ec: c7 44 24 04 fa 52 00 movl $0x52fa,0x4(%esp)
28f3: 00
28f4: c7 04 24 01 00 00 00 movl $0x1,(%esp)
28fb: e8 5d 17 00 00 call 405d <printf>
2900: e8 b0 15 00 00 call 3eb5 <exit>
2905: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
2909: 75 1b jne 2926 <bigfile+0x172>
290b: 90 nop
290c: 8b 45 ec mov -0x14(%ebp),%eax
290f: 89 04 24 mov %eax,(%esp)
2912: e8 c6 15 00 00 call 3edd <close>
2917: 81 7d f0 e0 2e 00 00 cmpl $0x2ee0,-0x10(%ebp)
291e: 0f 84 99 00 00 00 je 29bd <bigfile+0x209>
2924: eb 7e jmp 29a4 <bigfile+0x1f0>
2926: 81 7d e8 2c 01 00 00 cmpl $0x12c,-0x18(%ebp)
292d: 74 19 je 2948 <bigfile+0x194>
292f: c7 44 24 04 0f 53 00 movl $0x530f,0x4(%esp)
2936: 00
2937: c7 04 24 01 00 00 00 movl $0x1,(%esp)
293e: e8 1a 17 00 00 call 405d <printf>
2943: e8 6d 15 00 00 call 3eb5 <exit>
2948: 0f b6 05 e0 8a 00 00 movzbl 0x8ae0,%eax
294f: 0f be d0 movsbl %al,%edx
2952: 8b 45 f4 mov -0xc(%ebp),%eax
2955: 89 c1 mov %eax,%ecx
2957: c1 e9 1f shr $0x1f,%ecx
295a: 01 c8 add %ecx,%eax
295c: d1 f8 sar %eax
295e: 39 c2 cmp %eax,%edx
2960: 75 1a jne 297c <bigfile+0x1c8>
2962: 0f b6 05 0b 8c 00 00 movzbl 0x8c0b,%eax
2969: 0f be d0 movsbl %al,%edx
296c: 8b 45 f4 mov -0xc(%ebp),%eax
296f: 89 c1 mov %eax,%ecx
2971: c1 e9 1f shr $0x1f,%ecx
2974: 01 c8 add %ecx,%eax
2976: d1 f8 sar %eax
2978: 39 c2 cmp %eax,%edx
297a: 74 19 je 2995 <bigfile+0x1e1>
297c: c7 44 24 04 23 53 00 movl $0x5323,0x4(%esp)
2983: 00
2984: c7 04 24 01 00 00 00 movl $0x1,(%esp)
298b: e8 cd 16 00 00 call 405d <printf>
2990: e8 20 15 00 00 call 3eb5 <exit>
2995: 8b 45 e8 mov -0x18(%ebp),%eax
2998: 01 45 f0 add %eax,-0x10(%ebp)
299b: 83 45 f4 01 addl $0x1,-0xc(%ebp)
299f: e9 24 ff ff ff jmp 28c8 <bigfile+0x114>
29a4: c7 44 24 04 3c 53 00 movl $0x533c,0x4(%esp)
29ab: 00
29ac: c7 04 24 01 00 00 00 movl $0x1,(%esp)
29b3: e8 a5 16 00 00 call 405d <printf>
29b8: e8 f8 14 00 00 call 3eb5 <exit>
29bd: c7 04 24 b1 52 00 00 movl $0x52b1,(%esp)
29c4: e8 3c 15 00 00 call 3f05 <unlink>
29c9: c7 44 24 04 56 53 00 movl $0x5356,0x4(%esp)
29d0: 00
29d1: c7 04 24 01 00 00 00 movl $0x1,(%esp)
29d8: e8 80 16 00 00 call 405d <printf>
29dd: c9 leave
29de: c3 ret
000029df <fourteen>:
29df: 55 push %ebp
29e0: 89 e5 mov %esp,%ebp
29e2: 83 ec 28 sub $0x28,%esp
29e5: c7 44 24 04 67 53 00 movl $0x5367,0x4(%esp)
29ec: 00
29ed: c7 04 24 01 00 00 00 movl $0x1,(%esp)
29f4: e8 64 16 00 00 call 405d <printf>
29f9: c7 04 24 76 53 00 00 movl $0x5376,(%esp)
2a00: e8 18 15 00 00 call 3f1d <mkdir>
2a05: 85 c0 test %eax,%eax
2a07: 74 19 je 2a22 <fourteen+0x43>
2a09: c7 44 24 04 85 53 00 movl $0x5385,0x4(%esp)
2a10: 00
2a11: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2a18: e8 40 16 00 00 call 405d <printf>
2a1d: e8 93 14 00 00 call 3eb5 <exit>
2a22: c7 04 24 a4 53 00 00 movl $0x53a4,(%esp)
2a29: e8 ef 14 00 00 call 3f1d <mkdir>
2a2e: 85 c0 test %eax,%eax
2a30: 74 19 je 2a4b <fourteen+0x6c>
2a32: c7 44 24 04 c4 53 00 movl $0x53c4,0x4(%esp)
2a39: 00
2a3a: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2a41: e8 17 16 00 00 call 405d <printf>
2a46: e8 6a 14 00 00 call 3eb5 <exit>
2a4b: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
2a52: 00
2a53: c7 04 24 f4 53 00 00 movl $0x53f4,(%esp)
2a5a: e8 96 14 00 00 call 3ef5 <open>
2a5f: 89 45 f4 mov %eax,-0xc(%ebp)
2a62: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2a66: 79 19 jns 2a81 <fourteen+0xa2>
2a68: c7 44 24 04 24 54 00 movl $0x5424,0x4(%esp)
2a6f: 00
2a70: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2a77: e8 e1 15 00 00 call 405d <printf>
2a7c: e8 34 14 00 00 call 3eb5 <exit>
2a81: 8b 45 f4 mov -0xc(%ebp),%eax
2a84: 89 04 24 mov %eax,(%esp)
2a87: e8 51 14 00 00 call 3edd <close>
2a8c: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
2a93: 00
2a94: c7 04 24 64 54 00 00 movl $0x5464,(%esp)
2a9b: e8 55 14 00 00 call 3ef5 <open>
2aa0: 89 45 f4 mov %eax,-0xc(%ebp)
2aa3: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2aa7: 79 19 jns 2ac2 <fourteen+0xe3>
2aa9: c7 44 24 04 94 54 00 movl $0x5494,0x4(%esp)
2ab0: 00
2ab1: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2ab8: e8 a0 15 00 00 call 405d <printf>
2abd: e8 f3 13 00 00 call 3eb5 <exit>
2ac2: 8b 45 f4 mov -0xc(%ebp),%eax
2ac5: 89 04 24 mov %eax,(%esp)
2ac8: e8 10 14 00 00 call 3edd <close>
2acd: c7 04 24 ce 54 00 00 movl $0x54ce,(%esp)
2ad4: e8 44 14 00 00 call 3f1d <mkdir>
2ad9: 85 c0 test %eax,%eax
2adb: 75 19 jne 2af6 <fourteen+0x117>
2add: c7 44 24 04 ec 54 00 movl $0x54ec,0x4(%esp)
2ae4: 00
2ae5: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2aec: e8 6c 15 00 00 call 405d <printf>
2af1: e8 bf 13 00 00 call 3eb5 <exit>
2af6: c7 04 24 1c 55 00 00 movl $0x551c,(%esp)
2afd: e8 1b 14 00 00 call 3f1d <mkdir>
2b02: 85 c0 test %eax,%eax
2b04: 75 19 jne 2b1f <fourteen+0x140>
2b06: c7 44 24 04 3c 55 00 movl $0x553c,0x4(%esp)
2b0d: 00
2b0e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2b15: e8 43 15 00 00 call 405d <printf>
2b1a: e8 96 13 00 00 call 3eb5 <exit>
2b1f: c7 44 24 04 6d 55 00 movl $0x556d,0x4(%esp)
2b26: 00
2b27: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2b2e: e8 2a 15 00 00 call 405d <printf>
2b33: c9 leave
2b34: c3 ret
00002b35 <rmdot>:
2b35: 55 push %ebp
2b36: 89 e5 mov %esp,%ebp
2b38: 83 ec 18 sub $0x18,%esp
2b3b: c7 44 24 04 7a 55 00 movl $0x557a,0x4(%esp)
2b42: 00
2b43: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2b4a: e8 0e 15 00 00 call 405d <printf>
2b4f: c7 04 24 86 55 00 00 movl $0x5586,(%esp)
2b56: e8 c2 13 00 00 call 3f1d <mkdir>
2b5b: 85 c0 test %eax,%eax
2b5d: 74 19 je 2b78 <rmdot+0x43>
2b5f: c7 44 24 04 8b 55 00 movl $0x558b,0x4(%esp)
2b66: 00
2b67: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2b6e: e8 ea 14 00 00 call 405d <printf>
2b73: e8 3d 13 00 00 call 3eb5 <exit>
2b78: c7 04 24 86 55 00 00 movl $0x5586,(%esp)
2b7f: e8 a1 13 00 00 call 3f25 <chdir>
2b84: 85 c0 test %eax,%eax
2b86: 74 19 je 2ba1 <rmdot+0x6c>
2b88: c7 44 24 04 9e 55 00 movl $0x559e,0x4(%esp)
2b8f: 00
2b90: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2b97: e8 c1 14 00 00 call 405d <printf>
2b9c: e8 14 13 00 00 call 3eb5 <exit>
2ba1: c7 04 24 b7 4c 00 00 movl $0x4cb7,(%esp)
2ba8: e8 58 13 00 00 call 3f05 <unlink>
2bad: 85 c0 test %eax,%eax
2baf: 75 19 jne 2bca <rmdot+0x95>
2bb1: c7 44 24 04 b1 55 00 movl $0x55b1,0x4(%esp)
2bb8: 00
2bb9: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2bc0: e8 98 14 00 00 call 405d <printf>
2bc5: e8 eb 12 00 00 call 3eb5 <exit>
2bca: c7 04 24 4a 48 00 00 movl $0x484a,(%esp)
2bd1: e8 2f 13 00 00 call 3f05 <unlink>
2bd6: 85 c0 test %eax,%eax
2bd8: 75 19 jne 2bf3 <rmdot+0xbe>
2bda: c7 44 24 04 bf 55 00 movl $0x55bf,0x4(%esp)
2be1: 00
2be2: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2be9: e8 6f 14 00 00 call 405d <printf>
2bee: e8 c2 12 00 00 call 3eb5 <exit>
2bf3: c7 04 24 9e 44 00 00 movl $0x449e,(%esp)
2bfa: e8 26 13 00 00 call 3f25 <chdir>
2bff: 85 c0 test %eax,%eax
2c01: 74 19 je 2c1c <rmdot+0xe7>
2c03: c7 44 24 04 a0 44 00 movl $0x44a0,0x4(%esp)
2c0a: 00
2c0b: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2c12: e8 46 14 00 00 call 405d <printf>
2c17: e8 99 12 00 00 call 3eb5 <exit>
2c1c: c7 04 24 ce 55 00 00 movl $0x55ce,(%esp)
2c23: e8 dd 12 00 00 call 3f05 <unlink>
2c28: 85 c0 test %eax,%eax
2c2a: 75 19 jne 2c45 <rmdot+0x110>
2c2c: c7 44 24 04 d5 55 00 movl $0x55d5,0x4(%esp)
2c33: 00
2c34: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2c3b: e8 1d 14 00 00 call 405d <printf>
2c40: e8 70 12 00 00 call 3eb5 <exit>
2c45: c7 04 24 ec 55 00 00 movl $0x55ec,(%esp)
2c4c: e8 b4 12 00 00 call 3f05 <unlink>
2c51: 85 c0 test %eax,%eax
2c53: 75 19 jne 2c6e <rmdot+0x139>
2c55: c7 44 24 04 f4 55 00 movl $0x55f4,0x4(%esp)
2c5c: 00
2c5d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2c64: e8 f4 13 00 00 call 405d <printf>
2c69: e8 47 12 00 00 call 3eb5 <exit>
2c6e: c7 04 24 86 55 00 00 movl $0x5586,(%esp)
2c75: e8 8b 12 00 00 call 3f05 <unlink>
2c7a: 85 c0 test %eax,%eax
2c7c: 74 19 je 2c97 <rmdot+0x162>
2c7e: c7 44 24 04 0c 56 00 movl $0x560c,0x4(%esp)
2c85: 00
2c86: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2c8d: e8 cb 13 00 00 call 405d <printf>
2c92: e8 1e 12 00 00 call 3eb5 <exit>
2c97: c7 44 24 04 21 56 00 movl $0x5621,0x4(%esp)
2c9e: 00
2c9f: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2ca6: e8 b2 13 00 00 call 405d <printf>
2cab: c9 leave
2cac: c3 ret
00002cad <dirfile>:
2cad: 55 push %ebp
2cae: 89 e5 mov %esp,%ebp
2cb0: 83 ec 28 sub $0x28,%esp
2cb3: c7 44 24 04 2b 56 00 movl $0x562b,0x4(%esp)
2cba: 00
2cbb: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2cc2: e8 96 13 00 00 call 405d <printf>
2cc7: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
2cce: 00
2ccf: c7 04 24 38 56 00 00 movl $0x5638,(%esp)
2cd6: e8 1a 12 00 00 call 3ef5 <open>
2cdb: 89 45 f4 mov %eax,-0xc(%ebp)
2cde: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2ce2: 79 19 jns 2cfd <dirfile+0x50>
2ce4: c7 44 24 04 40 56 00 movl $0x5640,0x4(%esp)
2ceb: 00
2cec: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2cf3: e8 65 13 00 00 call 405d <printf>
2cf8: e8 b8 11 00 00 call 3eb5 <exit>
2cfd: 8b 45 f4 mov -0xc(%ebp),%eax
2d00: 89 04 24 mov %eax,(%esp)
2d03: e8 d5 11 00 00 call 3edd <close>
2d08: c7 04 24 38 56 00 00 movl $0x5638,(%esp)
2d0f: e8 11 12 00 00 call 3f25 <chdir>
2d14: 85 c0 test %eax,%eax
2d16: 75 19 jne 2d31 <dirfile+0x84>
2d18: c7 44 24 04 57 56 00 movl $0x5657,0x4(%esp)
2d1f: 00
2d20: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2d27: e8 31 13 00 00 call 405d <printf>
2d2c: e8 84 11 00 00 call 3eb5 <exit>
2d31: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
2d38: 00
2d39: c7 04 24 71 56 00 00 movl $0x5671,(%esp)
2d40: e8 b0 11 00 00 call 3ef5 <open>
2d45: 89 45 f4 mov %eax,-0xc(%ebp)
2d48: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2d4c: 78 19 js 2d67 <dirfile+0xba>
2d4e: c7 44 24 04 7c 56 00 movl $0x567c,0x4(%esp)
2d55: 00
2d56: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2d5d: e8 fb 12 00 00 call 405d <printf>
2d62: e8 4e 11 00 00 call 3eb5 <exit>
2d67: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
2d6e: 00
2d6f: c7 04 24 71 56 00 00 movl $0x5671,(%esp)
2d76: e8 7a 11 00 00 call 3ef5 <open>
2d7b: 89 45 f4 mov %eax,-0xc(%ebp)
2d7e: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2d82: 78 19 js 2d9d <dirfile+0xf0>
2d84: c7 44 24 04 7c 56 00 movl $0x567c,0x4(%esp)
2d8b: 00
2d8c: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2d93: e8 c5 12 00 00 call 405d <printf>
2d98: e8 18 11 00 00 call 3eb5 <exit>
2d9d: c7 04 24 71 56 00 00 movl $0x5671,(%esp)
2da4: e8 74 11 00 00 call 3f1d <mkdir>
2da9: 85 c0 test %eax,%eax
2dab: 75 19 jne 2dc6 <dirfile+0x119>
2dad: c7 44 24 04 9a 56 00 movl $0x569a,0x4(%esp)
2db4: 00
2db5: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2dbc: e8 9c 12 00 00 call 405d <printf>
2dc1: e8 ef 10 00 00 call 3eb5 <exit>
2dc6: c7 04 24 71 56 00 00 movl $0x5671,(%esp)
2dcd: e8 33 11 00 00 call 3f05 <unlink>
2dd2: 85 c0 test %eax,%eax
2dd4: 75 19 jne 2def <dirfile+0x142>
2dd6: c7 44 24 04 b7 56 00 movl $0x56b7,0x4(%esp)
2ddd: 00
2dde: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2de5: e8 73 12 00 00 call 405d <printf>
2dea: e8 c6 10 00 00 call 3eb5 <exit>
2def: c7 44 24 04 71 56 00 movl $0x5671,0x4(%esp)
2df6: 00
2df7: c7 04 24 d5 56 00 00 movl $0x56d5,(%esp)
2dfe: e8 12 11 00 00 call 3f15 <link>
2e03: 85 c0 test %eax,%eax
2e05: 75 19 jne 2e20 <dirfile+0x173>
2e07: c7 44 24 04 dc 56 00 movl $0x56dc,0x4(%esp)
2e0e: 00
2e0f: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2e16: e8 42 12 00 00 call 405d <printf>
2e1b: e8 95 10 00 00 call 3eb5 <exit>
2e20: c7 04 24 38 56 00 00 movl $0x5638,(%esp)
2e27: e8 d9 10 00 00 call 3f05 <unlink>
2e2c: 85 c0 test %eax,%eax
2e2e: 74 19 je 2e49 <dirfile+0x19c>
2e30: c7 44 24 04 fb 56 00 movl $0x56fb,0x4(%esp)
2e37: 00
2e38: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2e3f: e8 19 12 00 00 call 405d <printf>
2e44: e8 6c 10 00 00 call 3eb5 <exit>
2e49: c7 44 24 04 02 00 00 movl $0x2,0x4(%esp)
2e50: 00
2e51: c7 04 24 b7 4c 00 00 movl $0x4cb7,(%esp)
2e58: e8 98 10 00 00 call 3ef5 <open>
2e5d: 89 45 f4 mov %eax,-0xc(%ebp)
2e60: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2e64: 78 19 js 2e7f <dirfile+0x1d2>
2e66: c7 44 24 04 14 57 00 movl $0x5714,0x4(%esp)
2e6d: 00
2e6e: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2e75: e8 e3 11 00 00 call 405d <printf>
2e7a: e8 36 10 00 00 call 3eb5 <exit>
2e7f: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
2e86: 00
2e87: c7 04 24 b7 4c 00 00 movl $0x4cb7,(%esp)
2e8e: e8 62 10 00 00 call 3ef5 <open>
2e93: 89 45 f4 mov %eax,-0xc(%ebp)
2e96: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
2e9d: 00
2e9e: c7 44 24 04 03 49 00 movl $0x4903,0x4(%esp)
2ea5: 00
2ea6: 8b 45 f4 mov -0xc(%ebp),%eax
2ea9: 89 04 24 mov %eax,(%esp)
2eac: e8 24 10 00 00 call 3ed5 <write>
2eb1: 85 c0 test %eax,%eax
2eb3: 7e 19 jle 2ece <dirfile+0x221>
2eb5: c7 44 24 04 33 57 00 movl $0x5733,0x4(%esp)
2ebc: 00
2ebd: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2ec4: e8 94 11 00 00 call 405d <printf>
2ec9: e8 e7 0f 00 00 call 3eb5 <exit>
2ece: 8b 45 f4 mov -0xc(%ebp),%eax
2ed1: 89 04 24 mov %eax,(%esp)
2ed4: e8 04 10 00 00 call 3edd <close>
2ed9: c7 44 24 04 47 57 00 movl $0x5747,0x4(%esp)
2ee0: 00
2ee1: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2ee8: e8 70 11 00 00 call 405d <printf>
2eed: c9 leave
2eee: c3 ret
00002eef <iref>:
2eef: 55 push %ebp
2ef0: 89 e5 mov %esp,%ebp
2ef2: 83 ec 28 sub $0x28,%esp
2ef5: c7 44 24 04 57 57 00 movl $0x5757,0x4(%esp)
2efc: 00
2efd: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2f04: e8 54 11 00 00 call 405d <printf>
2f09: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
2f10: e9 d2 00 00 00 jmp 2fe7 <iref+0xf8>
2f15: c7 04 24 68 57 00 00 movl $0x5768,(%esp)
2f1c: e8 fc 0f 00 00 call 3f1d <mkdir>
2f21: 85 c0 test %eax,%eax
2f23: 74 19 je 2f3e <iref+0x4f>
2f25: c7 44 24 04 6e 57 00 movl $0x576e,0x4(%esp)
2f2c: 00
2f2d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2f34: e8 24 11 00 00 call 405d <printf>
2f39: e8 77 0f 00 00 call 3eb5 <exit>
2f3e: c7 04 24 68 57 00 00 movl $0x5768,(%esp)
2f45: e8 db 0f 00 00 call 3f25 <chdir>
2f4a: 85 c0 test %eax,%eax
2f4c: 74 19 je 2f67 <iref+0x78>
2f4e: c7 44 24 04 82 57 00 movl $0x5782,0x4(%esp)
2f55: 00
2f56: c7 04 24 01 00 00 00 movl $0x1,(%esp)
2f5d: e8 fb 10 00 00 call 405d <printf>
2f62: e8 4e 0f 00 00 call 3eb5 <exit>
2f67: c7 04 24 96 57 00 00 movl $0x5796,(%esp)
2f6e: e8 aa 0f 00 00 call 3f1d <mkdir>
2f73: c7 44 24 04 96 57 00 movl $0x5796,0x4(%esp)
2f7a: 00
2f7b: c7 04 24 d5 56 00 00 movl $0x56d5,(%esp)
2f82: e8 8e 0f 00 00 call 3f15 <link>
2f87: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
2f8e: 00
2f8f: c7 04 24 96 57 00 00 movl $0x5796,(%esp)
2f96: e8 5a 0f 00 00 call 3ef5 <open>
2f9b: 89 45 f0 mov %eax,-0x10(%ebp)
2f9e: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
2fa2: 78 0b js 2faf <iref+0xc0>
2fa4: 8b 45 f0 mov -0x10(%ebp),%eax
2fa7: 89 04 24 mov %eax,(%esp)
2faa: e8 2e 0f 00 00 call 3edd <close>
2faf: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
2fb6: 00
2fb7: c7 04 24 97 57 00 00 movl $0x5797,(%esp)
2fbe: e8 32 0f 00 00 call 3ef5 <open>
2fc3: 89 45 f0 mov %eax,-0x10(%ebp)
2fc6: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
2fca: 78 0b js 2fd7 <iref+0xe8>
2fcc: 8b 45 f0 mov -0x10(%ebp),%eax
2fcf: 89 04 24 mov %eax,(%esp)
2fd2: e8 06 0f 00 00 call 3edd <close>
2fd7: c7 04 24 97 57 00 00 movl $0x5797,(%esp)
2fde: e8 22 0f 00 00 call 3f05 <unlink>
2fe3: 83 45 f4 01 addl $0x1,-0xc(%ebp)
2fe7: 83 7d f4 32 cmpl $0x32,-0xc(%ebp)
2feb: 0f 8e 24 ff ff ff jle 2f15 <iref+0x26>
2ff1: c7 04 24 9e 44 00 00 movl $0x449e,(%esp)
2ff8: e8 28 0f 00 00 call 3f25 <chdir>
2ffd: c7 44 24 04 9a 57 00 movl $0x579a,0x4(%esp)
3004: 00
3005: c7 04 24 01 00 00 00 movl $0x1,(%esp)
300c: e8 4c 10 00 00 call 405d <printf>
3011: c9 leave
3012: c3 ret
00003013 <forktest>:
3013: 55 push %ebp
3014: 89 e5 mov %esp,%ebp
3016: 83 ec 28 sub $0x28,%esp
3019: c7 44 24 04 ae 57 00 movl $0x57ae,0x4(%esp)
3020: 00
3021: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3028: e8 30 10 00 00 call 405d <printf>
302d: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
3034: eb 1f jmp 3055 <forktest+0x42>
3036: e8 72 0e 00 00 call 3ead <fork>
303b: 89 45 f0 mov %eax,-0x10(%ebp)
303e: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
3042: 79 02 jns 3046 <forktest+0x33>
3044: eb 18 jmp 305e <forktest+0x4b>
3046: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
304a: 75 05 jne 3051 <forktest+0x3e>
304c: e8 64 0e 00 00 call 3eb5 <exit>
3051: 83 45 f4 01 addl $0x1,-0xc(%ebp)
3055: 81 7d f4 e7 03 00 00 cmpl $0x3e7,-0xc(%ebp)
305c: 7e d8 jle 3036 <forktest+0x23>
305e: 81 7d f4 e8 03 00 00 cmpl $0x3e8,-0xc(%ebp)
3065: 75 19 jne 3080 <forktest+0x6d>
3067: c7 44 24 04 bc 57 00 movl $0x57bc,0x4(%esp)
306e: 00
306f: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3076: e8 e2 0f 00 00 call 405d <printf>
307b: e8 35 0e 00 00 call 3eb5 <exit>
3080: eb 26 jmp 30a8 <forktest+0x95>
3082: e8 36 0e 00 00 call 3ebd <wait>
3087: 85 c0 test %eax,%eax
3089: 79 19 jns 30a4 <forktest+0x91>
308b: c7 44 24 04 de 57 00 movl $0x57de,0x4(%esp)
3092: 00
3093: c7 04 24 01 00 00 00 movl $0x1,(%esp)
309a: e8 be 0f 00 00 call 405d <printf>
309f: e8 11 0e 00 00 call 3eb5 <exit>
30a4: 83 6d f4 01 subl $0x1,-0xc(%ebp)
30a8: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
30ac: 7f d4 jg 3082 <forktest+0x6f>
30ae: e8 0a 0e 00 00 call 3ebd <wait>
30b3: 83 f8 ff cmp $0xffffffff,%eax
30b6: 74 19 je 30d1 <forktest+0xbe>
30b8: c7 44 24 04 f2 57 00 movl $0x57f2,0x4(%esp)
30bf: 00
30c0: c7 04 24 01 00 00 00 movl $0x1,(%esp)
30c7: e8 91 0f 00 00 call 405d <printf>
30cc: e8 e4 0d 00 00 call 3eb5 <exit>
30d1: c7 44 24 04 05 58 00 movl $0x5805,0x4(%esp)
30d8: 00
30d9: c7 04 24 01 00 00 00 movl $0x1,(%esp)
30e0: e8 78 0f 00 00 call 405d <printf>
30e5: c9 leave
30e6: c3 ret
000030e7 <sbrktest>:
30e7: 55 push %ebp
30e8: 89 e5 mov %esp,%ebp
30ea: 53 push %ebx
30eb: 81 ec 84 00 00 00 sub $0x84,%esp
30f1: a1 ec 62 00 00 mov 0x62ec,%eax
30f6: c7 44 24 04 13 58 00 movl $0x5813,0x4(%esp)
30fd: 00
30fe: 89 04 24 mov %eax,(%esp)
3101: e8 57 0f 00 00 call 405d <printf>
3106: c7 04 24 00 00 00 00 movl $0x0,(%esp)
310d: e8 2b 0e 00 00 call 3f3d <sbrk>
3112: 89 45 ec mov %eax,-0x14(%ebp)
3115: c7 04 24 00 00 00 00 movl $0x0,(%esp)
311c: e8 1c 0e 00 00 call 3f3d <sbrk>
3121: 89 45 f4 mov %eax,-0xc(%ebp)
3124: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
312b: eb 59 jmp 3186 <sbrktest+0x9f>
312d: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3134: e8 04 0e 00 00 call 3f3d <sbrk>
3139: 89 45 e8 mov %eax,-0x18(%ebp)
313c: 8b 45 e8 mov -0x18(%ebp),%eax
313f: 3b 45 f4 cmp -0xc(%ebp),%eax
3142: 74 2f je 3173 <sbrktest+0x8c>
3144: a1 ec 62 00 00 mov 0x62ec,%eax
3149: 8b 55 e8 mov -0x18(%ebp),%edx
314c: 89 54 24 10 mov %edx,0x10(%esp)
3150: 8b 55 f4 mov -0xc(%ebp),%edx
3153: 89 54 24 0c mov %edx,0xc(%esp)
3157: 8b 55 f0 mov -0x10(%ebp),%edx
315a: 89 54 24 08 mov %edx,0x8(%esp)
315e: c7 44 24 04 1e 58 00 movl $0x581e,0x4(%esp)
3165: 00
3166: 89 04 24 mov %eax,(%esp)
3169: e8 ef 0e 00 00 call 405d <printf>
316e: e8 42 0d 00 00 call 3eb5 <exit>
3173: 8b 45 e8 mov -0x18(%ebp),%eax
3176: c6 00 01 movb $0x1,(%eax)
3179: 8b 45 e8 mov -0x18(%ebp),%eax
317c: 83 c0 01 add $0x1,%eax
317f: 89 45 f4 mov %eax,-0xc(%ebp)
3182: 83 45 f0 01 addl $0x1,-0x10(%ebp)
3186: 81 7d f0 87 13 00 00 cmpl $0x1387,-0x10(%ebp)
318d: 7e 9e jle 312d <sbrktest+0x46>
318f: e8 19 0d 00 00 call 3ead <fork>
3194: 89 45 e4 mov %eax,-0x1c(%ebp)
3197: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
319b: 79 1a jns 31b7 <sbrktest+0xd0>
319d: a1 ec 62 00 00 mov 0x62ec,%eax
31a2: c7 44 24 04 39 58 00 movl $0x5839,0x4(%esp)
31a9: 00
31aa: 89 04 24 mov %eax,(%esp)
31ad: e8 ab 0e 00 00 call 405d <printf>
31b2: e8 fe 0c 00 00 call 3eb5 <exit>
31b7: c7 04 24 01 00 00 00 movl $0x1,(%esp)
31be: e8 7a 0d 00 00 call 3f3d <sbrk>
31c3: 89 45 e0 mov %eax,-0x20(%ebp)
31c6: c7 04 24 01 00 00 00 movl $0x1,(%esp)
31cd: e8 6b 0d 00 00 call 3f3d <sbrk>
31d2: 89 45 e0 mov %eax,-0x20(%ebp)
31d5: 8b 45 f4 mov -0xc(%ebp),%eax
31d8: 83 c0 01 add $0x1,%eax
31db: 3b 45 e0 cmp -0x20(%ebp),%eax
31de: 74 1a je 31fa <sbrktest+0x113>
31e0: a1 ec 62 00 00 mov 0x62ec,%eax
31e5: c7 44 24 04 50 58 00 movl $0x5850,0x4(%esp)
31ec: 00
31ed: 89 04 24 mov %eax,(%esp)
31f0: e8 68 0e 00 00 call 405d <printf>
31f5: e8 bb 0c 00 00 call 3eb5 <exit>
31fa: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
31fe: 75 05 jne 3205 <sbrktest+0x11e>
3200: e8 b0 0c 00 00 call 3eb5 <exit>
3205: e8 b3 0c 00 00 call 3ebd <wait>
320a: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3211: e8 27 0d 00 00 call 3f3d <sbrk>
3216: 89 45 f4 mov %eax,-0xc(%ebp)
3219: 8b 45 f4 mov -0xc(%ebp),%eax
321c: ba 00 00 40 06 mov $0x6400000,%edx
3221: 29 c2 sub %eax,%edx
3223: 89 d0 mov %edx,%eax
3225: 89 45 dc mov %eax,-0x24(%ebp)
3228: 8b 45 dc mov -0x24(%ebp),%eax
322b: 89 04 24 mov %eax,(%esp)
322e: e8 0a 0d 00 00 call 3f3d <sbrk>
3233: 89 45 d8 mov %eax,-0x28(%ebp)
3236: 8b 45 d8 mov -0x28(%ebp),%eax
3239: 3b 45 f4 cmp -0xc(%ebp),%eax
323c: 74 1a je 3258 <sbrktest+0x171>
323e: a1 ec 62 00 00 mov 0x62ec,%eax
3243: c7 44 24 04 6c 58 00 movl $0x586c,0x4(%esp)
324a: 00
324b: 89 04 24 mov %eax,(%esp)
324e: e8 0a 0e 00 00 call 405d <printf>
3253: e8 5d 0c 00 00 call 3eb5 <exit>
3258: c7 45 d4 ff ff 3f 06 movl $0x63fffff,-0x2c(%ebp)
325f: 8b 45 d4 mov -0x2c(%ebp),%eax
3262: c6 00 63 movb $0x63,(%eax)
3265: c7 04 24 00 00 00 00 movl $0x0,(%esp)
326c: e8 cc 0c 00 00 call 3f3d <sbrk>
3271: 89 45 f4 mov %eax,-0xc(%ebp)
3274: c7 04 24 00 f0 ff ff movl $0xfffff000,(%esp)
327b: e8 bd 0c 00 00 call 3f3d <sbrk>
3280: 89 45 e0 mov %eax,-0x20(%ebp)
3283: 83 7d e0 ff cmpl $0xffffffff,-0x20(%ebp)
3287: 75 1a jne 32a3 <sbrktest+0x1bc>
3289: a1 ec 62 00 00 mov 0x62ec,%eax
328e: c7 44 24 04 aa 58 00 movl $0x58aa,0x4(%esp)
3295: 00
3296: 89 04 24 mov %eax,(%esp)
3299: e8 bf 0d 00 00 call 405d <printf>
329e: e8 12 0c 00 00 call 3eb5 <exit>
32a3: c7 04 24 00 00 00 00 movl $0x0,(%esp)
32aa: e8 8e 0c 00 00 call 3f3d <sbrk>
32af: 89 45 e0 mov %eax,-0x20(%ebp)
32b2: 8b 45 f4 mov -0xc(%ebp),%eax
32b5: 2d 00 10 00 00 sub $0x1000,%eax
32ba: 3b 45 e0 cmp -0x20(%ebp),%eax
32bd: 74 28 je 32e7 <sbrktest+0x200>
32bf: a1 ec 62 00 00 mov 0x62ec,%eax
32c4: 8b 55 e0 mov -0x20(%ebp),%edx
32c7: 89 54 24 0c mov %edx,0xc(%esp)
32cb: 8b 55 f4 mov -0xc(%ebp),%edx
32ce: 89 54 24 08 mov %edx,0x8(%esp)
32d2: c7 44 24 04 c8 58 00 movl $0x58c8,0x4(%esp)
32d9: 00
32da: 89 04 24 mov %eax,(%esp)
32dd: e8 7b 0d 00 00 call 405d <printf>
32e2: e8 ce 0b 00 00 call 3eb5 <exit>
32e7: c7 04 24 00 00 00 00 movl $0x0,(%esp)
32ee: e8 4a 0c 00 00 call 3f3d <sbrk>
32f3: 89 45 f4 mov %eax,-0xc(%ebp)
32f6: c7 04 24 00 10 00 00 movl $0x1000,(%esp)
32fd: e8 3b 0c 00 00 call 3f3d <sbrk>
3302: 89 45 e0 mov %eax,-0x20(%ebp)
3305: 8b 45 e0 mov -0x20(%ebp),%eax
3308: 3b 45 f4 cmp -0xc(%ebp),%eax
330b: 75 19 jne 3326 <sbrktest+0x23f>
330d: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3314: e8 24 0c 00 00 call 3f3d <sbrk>
3319: 8b 55 f4 mov -0xc(%ebp),%edx
331c: 81 c2 00 10 00 00 add $0x1000,%edx
3322: 39 d0 cmp %edx,%eax
3324: 74 28 je 334e <sbrktest+0x267>
3326: a1 ec 62 00 00 mov 0x62ec,%eax
332b: 8b 55 e0 mov -0x20(%ebp),%edx
332e: 89 54 24 0c mov %edx,0xc(%esp)
3332: 8b 55 f4 mov -0xc(%ebp),%edx
3335: 89 54 24 08 mov %edx,0x8(%esp)
3339: c7 44 24 04 00 59 00 movl $0x5900,0x4(%esp)
3340: 00
3341: 89 04 24 mov %eax,(%esp)
3344: e8 14 0d 00 00 call 405d <printf>
3349: e8 67 0b 00 00 call 3eb5 <exit>
334e: 8b 45 d4 mov -0x2c(%ebp),%eax
3351: 0f b6 00 movzbl (%eax),%eax
3354: 3c 63 cmp $0x63,%al
3356: 75 1a jne 3372 <sbrktest+0x28b>
3358: a1 ec 62 00 00 mov 0x62ec,%eax
335d: c7 44 24 04 28 59 00 movl $0x5928,0x4(%esp)
3364: 00
3365: 89 04 24 mov %eax,(%esp)
3368: e8 f0 0c 00 00 call 405d <printf>
336d: e8 43 0b 00 00 call 3eb5 <exit>
3372: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3379: e8 bf 0b 00 00 call 3f3d <sbrk>
337e: 89 45 f4 mov %eax,-0xc(%ebp)
3381: 8b 5d ec mov -0x14(%ebp),%ebx
3384: c7 04 24 00 00 00 00 movl $0x0,(%esp)
338b: e8 ad 0b 00 00 call 3f3d <sbrk>
3390: 29 c3 sub %eax,%ebx
3392: 89 d8 mov %ebx,%eax
3394: 89 04 24 mov %eax,(%esp)
3397: e8 a1 0b 00 00 call 3f3d <sbrk>
339c: 89 45 e0 mov %eax,-0x20(%ebp)
339f: 8b 45 e0 mov -0x20(%ebp),%eax
33a2: 3b 45 f4 cmp -0xc(%ebp),%eax
33a5: 74 28 je 33cf <sbrktest+0x2e8>
33a7: a1 ec 62 00 00 mov 0x62ec,%eax
33ac: 8b 55 e0 mov -0x20(%ebp),%edx
33af: 89 54 24 0c mov %edx,0xc(%esp)
33b3: 8b 55 f4 mov -0xc(%ebp),%edx
33b6: 89 54 24 08 mov %edx,0x8(%esp)
33ba: c7 44 24 04 58 59 00 movl $0x5958,0x4(%esp)
33c1: 00
33c2: 89 04 24 mov %eax,(%esp)
33c5: e8 93 0c 00 00 call 405d <printf>
33ca: e8 e6 0a 00 00 call 3eb5 <exit>
33cf: c7 45 f4 00 00 00 80 movl $0x80000000,-0xc(%ebp)
33d6: eb 7b jmp 3453 <sbrktest+0x36c>
33d8: e8 58 0b 00 00 call 3f35 <getpid>
33dd: 89 45 d0 mov %eax,-0x30(%ebp)
33e0: e8 c8 0a 00 00 call 3ead <fork>
33e5: 89 45 e4 mov %eax,-0x1c(%ebp)
33e8: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
33ec: 79 1a jns 3408 <sbrktest+0x321>
33ee: a1 ec 62 00 00 mov 0x62ec,%eax
33f3: c7 44 24 04 cd 44 00 movl $0x44cd,0x4(%esp)
33fa: 00
33fb: 89 04 24 mov %eax,(%esp)
33fe: e8 5a 0c 00 00 call 405d <printf>
3403: e8 ad 0a 00 00 call 3eb5 <exit>
3408: 83 7d e4 00 cmpl $0x0,-0x1c(%ebp)
340c: 75 39 jne 3447 <sbrktest+0x360>
340e: 8b 45 f4 mov -0xc(%ebp),%eax
3411: 0f b6 00 movzbl (%eax),%eax
3414: 0f be d0 movsbl %al,%edx
3417: a1 ec 62 00 00 mov 0x62ec,%eax
341c: 89 54 24 0c mov %edx,0xc(%esp)
3420: 8b 55 f4 mov -0xc(%ebp),%edx
3423: 89 54 24 08 mov %edx,0x8(%esp)
3427: c7 44 24 04 79 59 00 movl $0x5979,0x4(%esp)
342e: 00
342f: 89 04 24 mov %eax,(%esp)
3432: e8 26 0c 00 00 call 405d <printf>
3437: 8b 45 d0 mov -0x30(%ebp),%eax
343a: 89 04 24 mov %eax,(%esp)
343d: e8 a3 0a 00 00 call 3ee5 <kill>
3442: e8 6e 0a 00 00 call 3eb5 <exit>
3447: e8 71 0a 00 00 call 3ebd <wait>
344c: 81 45 f4 50 c3 00 00 addl $0xc350,-0xc(%ebp)
3453: 81 7d f4 7f 84 1e 80 cmpl $0x801e847f,-0xc(%ebp)
345a: 0f 86 78 ff ff ff jbe 33d8 <sbrktest+0x2f1>
3460: 8d 45 c8 lea -0x38(%ebp),%eax
3463: 89 04 24 mov %eax,(%esp)
3466: e8 5a 0a 00 00 call 3ec5 <pipe>
346b: 85 c0 test %eax,%eax
346d: 74 19 je 3488 <sbrktest+0x3a1>
346f: c7 44 24 04 9e 48 00 movl $0x489e,0x4(%esp)
3476: 00
3477: c7 04 24 01 00 00 00 movl $0x1,(%esp)
347e: e8 da 0b 00 00 call 405d <printf>
3483: e8 2d 0a 00 00 call 3eb5 <exit>
3488: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
348f: e9 87 00 00 00 jmp 351b <sbrktest+0x434>
3494: e8 14 0a 00 00 call 3ead <fork>
3499: 8b 55 f0 mov -0x10(%ebp),%edx
349c: 89 44 95 a0 mov %eax,-0x60(%ebp,%edx,4)
34a0: 8b 45 f0 mov -0x10(%ebp),%eax
34a3: 8b 44 85 a0 mov -0x60(%ebp,%eax,4),%eax
34a7: 85 c0 test %eax,%eax
34a9: 75 46 jne 34f1 <sbrktest+0x40a>
34ab: c7 04 24 00 00 00 00 movl $0x0,(%esp)
34b2: e8 86 0a 00 00 call 3f3d <sbrk>
34b7: ba 00 00 40 06 mov $0x6400000,%edx
34bc: 29 c2 sub %eax,%edx
34be: 89 d0 mov %edx,%eax
34c0: 89 04 24 mov %eax,(%esp)
34c3: e8 75 0a 00 00 call 3f3d <sbrk>
34c8: 8b 45 cc mov -0x34(%ebp),%eax
34cb: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
34d2: 00
34d3: c7 44 24 04 03 49 00 movl $0x4903,0x4(%esp)
34da: 00
34db: 89 04 24 mov %eax,(%esp)
34de: e8 f2 09 00 00 call 3ed5 <write>
34e3: c7 04 24 e8 03 00 00 movl $0x3e8,(%esp)
34ea: e8 56 0a 00 00 call 3f45 <sleep>
34ef: eb f2 jmp 34e3 <sbrktest+0x3fc>
34f1: 8b 45 f0 mov -0x10(%ebp),%eax
34f4: 8b 44 85 a0 mov -0x60(%ebp,%eax,4),%eax
34f8: 83 f8 ff cmp $0xffffffff,%eax
34fb: 74 1a je 3517 <sbrktest+0x430>
34fd: 8b 45 c8 mov -0x38(%ebp),%eax
3500: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
3507: 00
3508: 8d 55 9f lea -0x61(%ebp),%edx
350b: 89 54 24 04 mov %edx,0x4(%esp)
350f: 89 04 24 mov %eax,(%esp)
3512: e8 b6 09 00 00 call 3ecd <read>
3517: 83 45 f0 01 addl $0x1,-0x10(%ebp)
351b: 8b 45 f0 mov -0x10(%ebp),%eax
351e: 83 f8 09 cmp $0x9,%eax
3521: 0f 86 6d ff ff ff jbe 3494 <sbrktest+0x3ad>
3527: c7 04 24 00 10 00 00 movl $0x1000,(%esp)
352e: e8 0a 0a 00 00 call 3f3d <sbrk>
3533: 89 45 e0 mov %eax,-0x20(%ebp)
3536: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
353d: eb 26 jmp 3565 <sbrktest+0x47e>
353f: 8b 45 f0 mov -0x10(%ebp),%eax
3542: 8b 44 85 a0 mov -0x60(%ebp,%eax,4),%eax
3546: 83 f8 ff cmp $0xffffffff,%eax
3549: 75 02 jne 354d <sbrktest+0x466>
354b: eb 14 jmp 3561 <sbrktest+0x47a>
354d: 8b 45 f0 mov -0x10(%ebp),%eax
3550: 8b 44 85 a0 mov -0x60(%ebp,%eax,4),%eax
3554: 89 04 24 mov %eax,(%esp)
3557: e8 89 09 00 00 call 3ee5 <kill>
355c: e8 5c 09 00 00 call 3ebd <wait>
3561: 83 45 f0 01 addl $0x1,-0x10(%ebp)
3565: 8b 45 f0 mov -0x10(%ebp),%eax
3568: 83 f8 09 cmp $0x9,%eax
356b: 76 d2 jbe 353f <sbrktest+0x458>
356d: 83 7d e0 ff cmpl $0xffffffff,-0x20(%ebp)
3571: 75 1a jne 358d <sbrktest+0x4a6>
3573: a1 ec 62 00 00 mov 0x62ec,%eax
3578: c7 44 24 04 92 59 00 movl $0x5992,0x4(%esp)
357f: 00
3580: 89 04 24 mov %eax,(%esp)
3583: e8 d5 0a 00 00 call 405d <printf>
3588: e8 28 09 00 00 call 3eb5 <exit>
358d: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3594: e8 a4 09 00 00 call 3f3d <sbrk>
3599: 3b 45 ec cmp -0x14(%ebp),%eax
359c: 76 1b jbe 35b9 <sbrktest+0x4d2>
359e: 8b 5d ec mov -0x14(%ebp),%ebx
35a1: c7 04 24 00 00 00 00 movl $0x0,(%esp)
35a8: e8 90 09 00 00 call 3f3d <sbrk>
35ad: 29 c3 sub %eax,%ebx
35af: 89 d8 mov %ebx,%eax
35b1: 89 04 24 mov %eax,(%esp)
35b4: e8 84 09 00 00 call 3f3d <sbrk>
35b9: a1 ec 62 00 00 mov 0x62ec,%eax
35be: c7 44 24 04 ad 59 00 movl $0x59ad,0x4(%esp)
35c5: 00
35c6: 89 04 24 mov %eax,(%esp)
35c9: e8 8f 0a 00 00 call 405d <printf>
35ce: 81 c4 84 00 00 00 add $0x84,%esp
35d4: 5b pop %ebx
35d5: 5d pop %ebp
35d6: c3 ret
000035d7 <validateint>:
35d7: 55 push %ebp
35d8: 89 e5 mov %esp,%ebp
35da: 53 push %ebx
35db: 83 ec 10 sub $0x10,%esp
35de: b8 0d 00 00 00 mov $0xd,%eax
35e3: 8b 55 08 mov 0x8(%ebp),%edx
35e6: 89 d1 mov %edx,%ecx
35e8: 89 e3 mov %esp,%ebx
35ea: 89 cc mov %ecx,%esp
35ec: cd 40 int $0x40
35ee: 89 dc mov %ebx,%esp
35f0: 89 45 f8 mov %eax,-0x8(%ebp)
35f3: 83 c4 10 add $0x10,%esp
35f6: 5b pop %ebx
35f7: 5d pop %ebp
35f8: c3 ret
000035f9 <validatetest>:
35f9: 55 push %ebp
35fa: 89 e5 mov %esp,%ebp
35fc: 83 ec 28 sub $0x28,%esp
35ff: a1 ec 62 00 00 mov 0x62ec,%eax
3604: c7 44 24 04 bb 59 00 movl $0x59bb,0x4(%esp)
360b: 00
360c: 89 04 24 mov %eax,(%esp)
360f: e8 49 0a 00 00 call 405d <printf>
3614: c7 45 f0 00 30 11 00 movl $0x113000,-0x10(%ebp)
361b: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
3622: eb 7f jmp 36a3 <validatetest+0xaa>
3624: e8 84 08 00 00 call 3ead <fork>
3629: 89 45 ec mov %eax,-0x14(%ebp)
362c: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
3630: 75 10 jne 3642 <validatetest+0x49>
3632: 8b 45 f4 mov -0xc(%ebp),%eax
3635: 89 04 24 mov %eax,(%esp)
3638: e8 9a ff ff ff call 35d7 <validateint>
363d: e8 73 08 00 00 call 3eb5 <exit>
3642: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3649: e8 f7 08 00 00 call 3f45 <sleep>
364e: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3655: e8 eb 08 00 00 call 3f45 <sleep>
365a: 8b 45 ec mov -0x14(%ebp),%eax
365d: 89 04 24 mov %eax,(%esp)
3660: e8 80 08 00 00 call 3ee5 <kill>
3665: e8 53 08 00 00 call 3ebd <wait>
366a: 8b 45 f4 mov -0xc(%ebp),%eax
366d: 89 44 24 04 mov %eax,0x4(%esp)
3671: c7 04 24 ca 59 00 00 movl $0x59ca,(%esp)
3678: e8 98 08 00 00 call 3f15 <link>
367d: 83 f8 ff cmp $0xffffffff,%eax
3680: 74 1a je 369c <validatetest+0xa3>
3682: a1 ec 62 00 00 mov 0x62ec,%eax
3687: c7 44 24 04 d5 59 00 movl $0x59d5,0x4(%esp)
368e: 00
368f: 89 04 24 mov %eax,(%esp)
3692: e8 c6 09 00 00 call 405d <printf>
3697: e8 19 08 00 00 call 3eb5 <exit>
369c: 81 45 f4 00 10 00 00 addl $0x1000,-0xc(%ebp)
36a3: 8b 45 f0 mov -0x10(%ebp),%eax
36a6: 3b 45 f4 cmp -0xc(%ebp),%eax
36a9: 0f 83 75 ff ff ff jae 3624 <validatetest+0x2b>
36af: a1 ec 62 00 00 mov 0x62ec,%eax
36b4: c7 44 24 04 ee 59 00 movl $0x59ee,0x4(%esp)
36bb: 00
36bc: 89 04 24 mov %eax,(%esp)
36bf: e8 99 09 00 00 call 405d <printf>
36c4: c9 leave
36c5: c3 ret
000036c6 <bsstest>:
36c6: 55 push %ebp
36c7: 89 e5 mov %esp,%ebp
36c9: 83 ec 28 sub $0x28,%esp
36cc: a1 ec 62 00 00 mov 0x62ec,%eax
36d1: c7 44 24 04 fb 59 00 movl $0x59fb,0x4(%esp)
36d8: 00
36d9: 89 04 24 mov %eax,(%esp)
36dc: e8 7c 09 00 00 call 405d <printf>
36e1: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
36e8: eb 2d jmp 3717 <bsstest+0x51>
36ea: 8b 45 f4 mov -0xc(%ebp),%eax
36ed: 05 c0 63 00 00 add $0x63c0,%eax
36f2: 0f b6 00 movzbl (%eax),%eax
36f5: 84 c0 test %al,%al
36f7: 74 1a je 3713 <bsstest+0x4d>
36f9: a1 ec 62 00 00 mov 0x62ec,%eax
36fe: c7 44 24 04 05 5a 00 movl $0x5a05,0x4(%esp)
3705: 00
3706: 89 04 24 mov %eax,(%esp)
3709: e8 4f 09 00 00 call 405d <printf>
370e: e8 a2 07 00 00 call 3eb5 <exit>
3713: 83 45 f4 01 addl $0x1,-0xc(%ebp)
3717: 8b 45 f4 mov -0xc(%ebp),%eax
371a: 3d 0f 27 00 00 cmp $0x270f,%eax
371f: 76 c9 jbe 36ea <bsstest+0x24>
3721: a1 ec 62 00 00 mov 0x62ec,%eax
3726: c7 44 24 04 16 5a 00 movl $0x5a16,0x4(%esp)
372d: 00
372e: 89 04 24 mov %eax,(%esp)
3731: e8 27 09 00 00 call 405d <printf>
3736: c9 leave
3737: c3 ret
00003738 <bigargtest>:
3738: 55 push %ebp
3739: 89 e5 mov %esp,%ebp
373b: 83 ec 28 sub $0x28,%esp
373e: c7 04 24 23 5a 00 00 movl $0x5a23,(%esp)
3745: e8 bb 07 00 00 call 3f05 <unlink>
374a: e8 5e 07 00 00 call 3ead <fork>
374f: 89 45 f0 mov %eax,-0x10(%ebp)
3752: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
3756: 0f 85 90 00 00 00 jne 37ec <bigargtest+0xb4>
375c: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
3763: eb 12 jmp 3777 <bigargtest+0x3f>
3765: 8b 45 f4 mov -0xc(%ebp),%eax
3768: c7 04 85 20 63 00 00 movl $0x5a30,0x6320(,%eax,4)
376f: 30 5a 00 00
3773: 83 45 f4 01 addl $0x1,-0xc(%ebp)
3777: 83 7d f4 1e cmpl $0x1e,-0xc(%ebp)
377b: 7e e8 jle 3765 <bigargtest+0x2d>
377d: c7 05 9c 63 00 00 00 movl $0x0,0x639c
3784: 00 00 00
3787: a1 ec 62 00 00 mov 0x62ec,%eax
378c: c7 44 24 04 0d 5b 00 movl $0x5b0d,0x4(%esp)
3793: 00
3794: 89 04 24 mov %eax,(%esp)
3797: e8 c1 08 00 00 call 405d <printf>
379c: c7 44 24 04 20 63 00 movl $0x6320,0x4(%esp)
37a3: 00
37a4: c7 04 24 2c 44 00 00 movl $0x442c,(%esp)
37ab: e8 3d 07 00 00 call 3eed <exec>
37b0: a1 ec 62 00 00 mov 0x62ec,%eax
37b5: c7 44 24 04 1a 5b 00 movl $0x5b1a,0x4(%esp)
37bc: 00
37bd: 89 04 24 mov %eax,(%esp)
37c0: e8 98 08 00 00 call 405d <printf>
37c5: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
37cc: 00
37cd: c7 04 24 23 5a 00 00 movl $0x5a23,(%esp)
37d4: e8 1c 07 00 00 call 3ef5 <open>
37d9: 89 45 ec mov %eax,-0x14(%ebp)
37dc: 8b 45 ec mov -0x14(%ebp),%eax
37df: 89 04 24 mov %eax,(%esp)
37e2: e8 f6 06 00 00 call 3edd <close>
37e7: e8 c9 06 00 00 call 3eb5 <exit>
37ec: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
37f0: 79 1a jns 380c <bigargtest+0xd4>
37f2: a1 ec 62 00 00 mov 0x62ec,%eax
37f7: c7 44 24 04 2a 5b 00 movl $0x5b2a,0x4(%esp)
37fe: 00
37ff: 89 04 24 mov %eax,(%esp)
3802: e8 56 08 00 00 call 405d <printf>
3807: e8 a9 06 00 00 call 3eb5 <exit>
380c: e8 ac 06 00 00 call 3ebd <wait>
3811: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
3818: 00
3819: c7 04 24 23 5a 00 00 movl $0x5a23,(%esp)
3820: e8 d0 06 00 00 call 3ef5 <open>
3825: 89 45 ec mov %eax,-0x14(%ebp)
3828: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
382c: 79 1a jns 3848 <bigargtest+0x110>
382e: a1 ec 62 00 00 mov 0x62ec,%eax
3833: c7 44 24 04 43 5b 00 movl $0x5b43,0x4(%esp)
383a: 00
383b: 89 04 24 mov %eax,(%esp)
383e: e8 1a 08 00 00 call 405d <printf>
3843: e8 6d 06 00 00 call 3eb5 <exit>
3848: 8b 45 ec mov -0x14(%ebp),%eax
384b: 89 04 24 mov %eax,(%esp)
384e: e8 8a 06 00 00 call 3edd <close>
3853: c7 04 24 23 5a 00 00 movl $0x5a23,(%esp)
385a: e8 a6 06 00 00 call 3f05 <unlink>
385f: c9 leave
3860: c3 ret
00003861 <fsfull>:
3861: 55 push %ebp
3862: 89 e5 mov %esp,%ebp
3864: 53 push %ebx
3865: 83 ec 74 sub $0x74,%esp
3868: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
386f: c7 44 24 04 58 5b 00 movl $0x5b58,0x4(%esp)
3876: 00
3877: c7 04 24 01 00 00 00 movl $0x1,(%esp)
387e: e8 da 07 00 00 call 405d <printf>
3883: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
388a: c6 45 a4 66 movb $0x66,-0x5c(%ebp)
388e: 8b 4d f4 mov -0xc(%ebp),%ecx
3891: ba d3 4d 62 10 mov $0x10624dd3,%edx
3896: 89 c8 mov %ecx,%eax
3898: f7 ea imul %edx
389a: c1 fa 06 sar $0x6,%edx
389d: 89 c8 mov %ecx,%eax
389f: c1 f8 1f sar $0x1f,%eax
38a2: 29 c2 sub %eax,%edx
38a4: 89 d0 mov %edx,%eax
38a6: 83 c0 30 add $0x30,%eax
38a9: 88 45 a5 mov %al,-0x5b(%ebp)
38ac: 8b 5d f4 mov -0xc(%ebp),%ebx
38af: ba d3 4d 62 10 mov $0x10624dd3,%edx
38b4: 89 d8 mov %ebx,%eax
38b6: f7 ea imul %edx
38b8: c1 fa 06 sar $0x6,%edx
38bb: 89 d8 mov %ebx,%eax
38bd: c1 f8 1f sar $0x1f,%eax
38c0: 89 d1 mov %edx,%ecx
38c2: 29 c1 sub %eax,%ecx
38c4: 69 c1 e8 03 00 00 imul $0x3e8,%ecx,%eax
38ca: 29 c3 sub %eax,%ebx
38cc: 89 d9 mov %ebx,%ecx
38ce: ba 1f 85 eb 51 mov $0x51eb851f,%edx
38d3: 89 c8 mov %ecx,%eax
38d5: f7 ea imul %edx
38d7: c1 fa 05 sar $0x5,%edx
38da: 89 c8 mov %ecx,%eax
38dc: c1 f8 1f sar $0x1f,%eax
38df: 29 c2 sub %eax,%edx
38e1: 89 d0 mov %edx,%eax
38e3: 83 c0 30 add $0x30,%eax
38e6: 88 45 a6 mov %al,-0x5a(%ebp)
38e9: 8b 5d f4 mov -0xc(%ebp),%ebx
38ec: ba 1f 85 eb 51 mov $0x51eb851f,%edx
38f1: 89 d8 mov %ebx,%eax
38f3: f7 ea imul %edx
38f5: c1 fa 05 sar $0x5,%edx
38f8: 89 d8 mov %ebx,%eax
38fa: c1 f8 1f sar $0x1f,%eax
38fd: 89 d1 mov %edx,%ecx
38ff: 29 c1 sub %eax,%ecx
3901: 6b c1 64 imul $0x64,%ecx,%eax
3904: 29 c3 sub %eax,%ebx
3906: 89 d9 mov %ebx,%ecx
3908: ba 67 66 66 66 mov $0x66666667,%edx
390d: 89 c8 mov %ecx,%eax
390f: f7 ea imul %edx
3911: c1 fa 02 sar $0x2,%edx
3914: 89 c8 mov %ecx,%eax
3916: c1 f8 1f sar $0x1f,%eax
3919: 29 c2 sub %eax,%edx
391b: 89 d0 mov %edx,%eax
391d: 83 c0 30 add $0x30,%eax
3920: 88 45 a7 mov %al,-0x59(%ebp)
3923: 8b 4d f4 mov -0xc(%ebp),%ecx
3926: ba 67 66 66 66 mov $0x66666667,%edx
392b: 89 c8 mov %ecx,%eax
392d: f7 ea imul %edx
392f: c1 fa 02 sar $0x2,%edx
3932: 89 c8 mov %ecx,%eax
3934: c1 f8 1f sar $0x1f,%eax
3937: 29 c2 sub %eax,%edx
3939: 89 d0 mov %edx,%eax
393b: c1 e0 02 shl $0x2,%eax
393e: 01 d0 add %edx,%eax
3940: 01 c0 add %eax,%eax
3942: 29 c1 sub %eax,%ecx
3944: 89 ca mov %ecx,%edx
3946: 89 d0 mov %edx,%eax
3948: 83 c0 30 add $0x30,%eax
394b: 88 45 a8 mov %al,-0x58(%ebp)
394e: c6 45 a9 00 movb $0x0,-0x57(%ebp)
3952: 8d 45 a4 lea -0x5c(%ebp),%eax
3955: 89 44 24 08 mov %eax,0x8(%esp)
3959: c7 44 24 04 65 5b 00 movl $0x5b65,0x4(%esp)
3960: 00
3961: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3968: e8 f0 06 00 00 call 405d <printf>
396d: c7 44 24 04 02 02 00 movl $0x202,0x4(%esp)
3974: 00
3975: 8d 45 a4 lea -0x5c(%ebp),%eax
3978: 89 04 24 mov %eax,(%esp)
397b: e8 75 05 00 00 call 3ef5 <open>
3980: 89 45 e8 mov %eax,-0x18(%ebp)
3983: 83 7d e8 00 cmpl $0x0,-0x18(%ebp)
3987: 79 1d jns 39a6 <fsfull+0x145>
3989: 8d 45 a4 lea -0x5c(%ebp),%eax
398c: 89 44 24 08 mov %eax,0x8(%esp)
3990: c7 44 24 04 71 5b 00 movl $0x5b71,0x4(%esp)
3997: 00
3998: c7 04 24 01 00 00 00 movl $0x1,(%esp)
399f: e8 b9 06 00 00 call 405d <printf>
39a4: eb 74 jmp 3a1a <fsfull+0x1b9>
39a6: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
39ad: c7 44 24 08 00 02 00 movl $0x200,0x8(%esp)
39b4: 00
39b5: c7 44 24 04 e0 8a 00 movl $0x8ae0,0x4(%esp)
39bc: 00
39bd: 8b 45 e8 mov -0x18(%ebp),%eax
39c0: 89 04 24 mov %eax,(%esp)
39c3: e8 0d 05 00 00 call 3ed5 <write>
39c8: 89 45 e4 mov %eax,-0x1c(%ebp)
39cb: 81 7d e4 ff 01 00 00 cmpl $0x1ff,-0x1c(%ebp)
39d2: 7f 2f jg 3a03 <fsfull+0x1a2>
39d4: 90 nop
39d5: 8b 45 ec mov -0x14(%ebp),%eax
39d8: 89 44 24 08 mov %eax,0x8(%esp)
39dc: c7 44 24 04 81 5b 00 movl $0x5b81,0x4(%esp)
39e3: 00
39e4: c7 04 24 01 00 00 00 movl $0x1,(%esp)
39eb: e8 6d 06 00 00 call 405d <printf>
39f0: 8b 45 e8 mov -0x18(%ebp),%eax
39f3: 89 04 24 mov %eax,(%esp)
39f6: e8 e2 04 00 00 call 3edd <close>
39fb: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
39ff: 75 10 jne 3a11 <fsfull+0x1b0>
3a01: eb 0c jmp 3a0f <fsfull+0x1ae>
3a03: 8b 45 e4 mov -0x1c(%ebp),%eax
3a06: 01 45 ec add %eax,-0x14(%ebp)
3a09: 83 45 f0 01 addl $0x1,-0x10(%ebp)
3a0d: eb 9e jmp 39ad <fsfull+0x14c>
3a0f: eb 09 jmp 3a1a <fsfull+0x1b9>
3a11: 83 45 f4 01 addl $0x1,-0xc(%ebp)
3a15: e9 70 fe ff ff jmp 388a <fsfull+0x29>
3a1a: e9 d7 00 00 00 jmp 3af6 <fsfull+0x295>
3a1f: c6 45 a4 66 movb $0x66,-0x5c(%ebp)
3a23: 8b 4d f4 mov -0xc(%ebp),%ecx
3a26: ba d3 4d 62 10 mov $0x10624dd3,%edx
3a2b: 89 c8 mov %ecx,%eax
3a2d: f7 ea imul %edx
3a2f: c1 fa 06 sar $0x6,%edx
3a32: 89 c8 mov %ecx,%eax
3a34: c1 f8 1f sar $0x1f,%eax
3a37: 29 c2 sub %eax,%edx
3a39: 89 d0 mov %edx,%eax
3a3b: 83 c0 30 add $0x30,%eax
3a3e: 88 45 a5 mov %al,-0x5b(%ebp)
3a41: 8b 5d f4 mov -0xc(%ebp),%ebx
3a44: ba d3 4d 62 10 mov $0x10624dd3,%edx
3a49: 89 d8 mov %ebx,%eax
3a4b: f7 ea imul %edx
3a4d: c1 fa 06 sar $0x6,%edx
3a50: 89 d8 mov %ebx,%eax
3a52: c1 f8 1f sar $0x1f,%eax
3a55: 89 d1 mov %edx,%ecx
3a57: 29 c1 sub %eax,%ecx
3a59: 69 c1 e8 03 00 00 imul $0x3e8,%ecx,%eax
3a5f: 29 c3 sub %eax,%ebx
3a61: 89 d9 mov %ebx,%ecx
3a63: ba 1f 85 eb 51 mov $0x51eb851f,%edx
3a68: 89 c8 mov %ecx,%eax
3a6a: f7 ea imul %edx
3a6c: c1 fa 05 sar $0x5,%edx
3a6f: 89 c8 mov %ecx,%eax
3a71: c1 f8 1f sar $0x1f,%eax
3a74: 29 c2 sub %eax,%edx
3a76: 89 d0 mov %edx,%eax
3a78: 83 c0 30 add $0x30,%eax
3a7b: 88 45 a6 mov %al,-0x5a(%ebp)
3a7e: 8b 5d f4 mov -0xc(%ebp),%ebx
3a81: ba 1f 85 eb 51 mov $0x51eb851f,%edx
3a86: 89 d8 mov %ebx,%eax
3a88: f7 ea imul %edx
3a8a: c1 fa 05 sar $0x5,%edx
3a8d: 89 d8 mov %ebx,%eax
3a8f: c1 f8 1f sar $0x1f,%eax
3a92: 89 d1 mov %edx,%ecx
3a94: 29 c1 sub %eax,%ecx
3a96: 6b c1 64 imul $0x64,%ecx,%eax
3a99: 29 c3 sub %eax,%ebx
3a9b: 89 d9 mov %ebx,%ecx
3a9d: ba 67 66 66 66 mov $0x66666667,%edx
3aa2: 89 c8 mov %ecx,%eax
3aa4: f7 ea imul %edx
3aa6: c1 fa 02 sar $0x2,%edx
3aa9: 89 c8 mov %ecx,%eax
3aab: c1 f8 1f sar $0x1f,%eax
3aae: 29 c2 sub %eax,%edx
3ab0: 89 d0 mov %edx,%eax
3ab2: 83 c0 30 add $0x30,%eax
3ab5: 88 45 a7 mov %al,-0x59(%ebp)
3ab8: 8b 4d f4 mov -0xc(%ebp),%ecx
3abb: ba 67 66 66 66 mov $0x66666667,%edx
3ac0: 89 c8 mov %ecx,%eax
3ac2: f7 ea imul %edx
3ac4: c1 fa 02 sar $0x2,%edx
3ac7: 89 c8 mov %ecx,%eax
3ac9: c1 f8 1f sar $0x1f,%eax
3acc: 29 c2 sub %eax,%edx
3ace: 89 d0 mov %edx,%eax
3ad0: c1 e0 02 shl $0x2,%eax
3ad3: 01 d0 add %edx,%eax
3ad5: 01 c0 add %eax,%eax
3ad7: 29 c1 sub %eax,%ecx
3ad9: 89 ca mov %ecx,%edx
3adb: 89 d0 mov %edx,%eax
3add: 83 c0 30 add $0x30,%eax
3ae0: 88 45 a8 mov %al,-0x58(%ebp)
3ae3: c6 45 a9 00 movb $0x0,-0x57(%ebp)
3ae7: 8d 45 a4 lea -0x5c(%ebp),%eax
3aea: 89 04 24 mov %eax,(%esp)
3aed: e8 13 04 00 00 call 3f05 <unlink>
3af2: 83 6d f4 01 subl $0x1,-0xc(%ebp)
3af6: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
3afa: 0f 89 1f ff ff ff jns 3a1f <fsfull+0x1be>
3b00: c7 44 24 04 91 5b 00 movl $0x5b91,0x4(%esp)
3b07: 00
3b08: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3b0f: e8 49 05 00 00 call 405d <printf>
3b14: 83 c4 74 add $0x74,%esp
3b17: 5b pop %ebx
3b18: 5d pop %ebp
3b19: c3 ret
00003b1a <rand>:
3b1a: 55 push %ebp
3b1b: 89 e5 mov %esp,%ebp
3b1d: a1 f0 62 00 00 mov 0x62f0,%eax
3b22: 69 c0 0d 66 19 00 imul $0x19660d,%eax,%eax
3b28: 05 5f f3 6e 3c add $0x3c6ef35f,%eax
3b2d: a3 f0 62 00 00 mov %eax,0x62f0
3b32: a1 f0 62 00 00 mov 0x62f0,%eax
3b37: 5d pop %ebp
3b38: c3 ret
00003b39 <main>:
3b39: 55 push %ebp
3b3a: 89 e5 mov %esp,%ebp
3b3c: 83 e4 f0 and $0xfffffff0,%esp
3b3f: 83 ec 10 sub $0x10,%esp
3b42: c7 44 24 04 a7 5b 00 movl $0x5ba7,0x4(%esp)
3b49: 00
3b4a: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3b51: e8 07 05 00 00 call 405d <printf>
3b56: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
3b5d: 00
3b5e: c7 04 24 bb 5b 00 00 movl $0x5bbb,(%esp)
3b65: e8 8b 03 00 00 call 3ef5 <open>
3b6a: 85 c0 test %eax,%eax
3b6c: 78 19 js 3b87 <main+0x4e>
3b6e: c7 44 24 04 cc 5b 00 movl $0x5bcc,0x4(%esp)
3b75: 00
3b76: c7 04 24 01 00 00 00 movl $0x1,(%esp)
3b7d: e8 db 04 00 00 call 405d <printf>
3b82: e8 2e 03 00 00 call 3eb5 <exit>
3b87: c7 44 24 04 00 02 00 movl $0x200,0x4(%esp)
3b8e: 00
3b8f: c7 04 24 bb 5b 00 00 movl $0x5bbb,(%esp)
3b96: e8 5a 03 00 00 call 3ef5 <open>
3b9b: 89 04 24 mov %eax,(%esp)
3b9e: e8 3a 03 00 00 call 3edd <close>
3ba3: e8 da d6 ff ff call 1282 <createdelete>
3ba8: e8 1e e1 ff ff call 1ccb <linkunlink>
3bad: e8 66 dd ff ff call 1918 <concreate>
3bb2: e8 63 d4 ff ff call 101a <fourfiles>
3bb7: e8 60 d2 ff ff call e1c <sharedfd>
3bbc: e8 77 fb ff ff call 3738 <bigargtest>
3bc1: e8 e6 ea ff ff call 26ac <bigwrite>
3bc6: e8 6d fb ff ff call 3738 <bigargtest>
3bcb: e8 f6 fa ff ff call 36c6 <bsstest>
3bd0: e8 12 f5 ff ff call 30e7 <sbrktest>
3bd5: e8 1f fa ff ff call 35f9 <validatetest>
3bda: e8 e8 c6 ff ff call 2c7 <opentest>
3bdf: e8 8e c7 ff ff call 372 <writetest>
3be4: e8 9e c9 ff ff call 587 <writetest1>
3be9: e8 a4 cb ff ff call 792 <createtest>
3bee: e8 d3 c5 ff ff call 1c6 <openiputtest>
3bf3: e8 e2 c4 ff ff call da <exitiputtest>
3bf8: e8 03 c4 ff ff call 0 <iputtest>
3bfd: e8 35 d1 ff ff call d37 <mem>
3c02: e8 6c cd ff ff call 973 <pipe1>
3c07: e8 54 cf ff ff call b60 <preempt>
3c0c: e8 a8 d0 ff ff call cb9 <exitwait>
3c11: e8 1f ef ff ff call 2b35 <rmdot>
3c16: e8 c4 ed ff ff call 29df <fourteen>
3c1b: e8 94 eb ff ff call 27b4 <bigfile>
3c20: e8 41 e3 ff ff call 1f66 <subdir>
3c25: e8 a5 da ff ff call 16cf <linktest>
3c2a: e8 cb d8 ff ff call 14fa <unlinkread>
3c2f: e8 79 f0 ff ff call 2cad <dirfile>
3c34: e8 b6 f2 ff ff call 2eef <iref>
3c39: e8 d5 f3 ff ff call 3013 <forktest>
3c3e: e8 b6 e1 ff ff call 1df9 <bigdir>
3c43: e8 dc cc ff ff call 924 <exectest>
3c48: e8 68 02 00 00 call 3eb5 <exit>
00003c4d <stosb>:
3c4d: 55 push %ebp
3c4e: 89 e5 mov %esp,%ebp
3c50: 57 push %edi
3c51: 53 push %ebx
3c52: 8b 4d 08 mov 0x8(%ebp),%ecx
3c55: 8b 55 10 mov 0x10(%ebp),%edx
3c58: 8b 45 0c mov 0xc(%ebp),%eax
3c5b: 89 cb mov %ecx,%ebx
3c5d: 89 df mov %ebx,%edi
3c5f: 89 d1 mov %edx,%ecx
3c61: fc cld
3c62: f3 aa rep stos %al,%es:(%edi)
3c64: 89 ca mov %ecx,%edx
3c66: 89 fb mov %edi,%ebx
3c68: 89 5d 08 mov %ebx,0x8(%ebp)
3c6b: 89 55 10 mov %edx,0x10(%ebp)
3c6e: 5b pop %ebx
3c6f: 5f pop %edi
3c70: 5d pop %ebp
3c71: c3 ret
00003c72 <strcpy>:
3c72: 55 push %ebp
3c73: 89 e5 mov %esp,%ebp
3c75: 83 ec 10 sub $0x10,%esp
3c78: 8b 45 08 mov 0x8(%ebp),%eax
3c7b: 89 45 fc mov %eax,-0x4(%ebp)
3c7e: 90 nop
3c7f: 8b 45 08 mov 0x8(%ebp),%eax
3c82: 8d 50 01 lea 0x1(%eax),%edx
3c85: 89 55 08 mov %edx,0x8(%ebp)
3c88: 8b 55 0c mov 0xc(%ebp),%edx
3c8b: 8d 4a 01 lea 0x1(%edx),%ecx
3c8e: 89 4d 0c mov %ecx,0xc(%ebp)
3c91: 0f b6 12 movzbl (%edx),%edx
3c94: 88 10 mov %dl,(%eax)
3c96: 0f b6 00 movzbl (%eax),%eax
3c99: 84 c0 test %al,%al
3c9b: 75 e2 jne 3c7f <strcpy+0xd>
3c9d: 8b 45 fc mov -0x4(%ebp),%eax
3ca0: c9 leave
3ca1: c3 ret
00003ca2 <strcmp>:
3ca2: 55 push %ebp
3ca3: 89 e5 mov %esp,%ebp
3ca5: eb 08 jmp 3caf <strcmp+0xd>
3ca7: 83 45 08 01 addl $0x1,0x8(%ebp)
3cab: 83 45 0c 01 addl $0x1,0xc(%ebp)
3caf: 8b 45 08 mov 0x8(%ebp),%eax
3cb2: 0f b6 00 movzbl (%eax),%eax
3cb5: 84 c0 test %al,%al
3cb7: 74 10 je 3cc9 <strcmp+0x27>
3cb9: 8b 45 08 mov 0x8(%ebp),%eax
3cbc: 0f b6 10 movzbl (%eax),%edx
3cbf: 8b 45 0c mov 0xc(%ebp),%eax
3cc2: 0f b6 00 movzbl (%eax),%eax
3cc5: 38 c2 cmp %al,%dl
3cc7: 74 de je 3ca7 <strcmp+0x5>
3cc9: 8b 45 08 mov 0x8(%ebp),%eax
3ccc: 0f b6 00 movzbl (%eax),%eax
3ccf: 0f b6 d0 movzbl %al,%edx
3cd2: 8b 45 0c mov 0xc(%ebp),%eax
3cd5: 0f b6 00 movzbl (%eax),%eax
3cd8: 0f b6 c0 movzbl %al,%eax
3cdb: 29 c2 sub %eax,%edx
3cdd: 89 d0 mov %edx,%eax
3cdf: 5d pop %ebp
3ce0: c3 ret
00003ce1 <strlen>:
3ce1: 55 push %ebp
3ce2: 89 e5 mov %esp,%ebp
3ce4: 83 ec 10 sub $0x10,%esp
3ce7: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
3cee: eb 04 jmp 3cf4 <strlen+0x13>
3cf0: 83 45 fc 01 addl $0x1,-0x4(%ebp)
3cf4: 8b 55 fc mov -0x4(%ebp),%edx
3cf7: 8b 45 08 mov 0x8(%ebp),%eax
3cfa: 01 d0 add %edx,%eax
3cfc: 0f b6 00 movzbl (%eax),%eax
3cff: 84 c0 test %al,%al
3d01: 75 ed jne 3cf0 <strlen+0xf>
3d03: 8b 45 fc mov -0x4(%ebp),%eax
3d06: c9 leave
3d07: c3 ret
00003d08 <memset>:
3d08: 55 push %ebp
3d09: 89 e5 mov %esp,%ebp
3d0b: 83 ec 0c sub $0xc,%esp
3d0e: 8b 45 10 mov 0x10(%ebp),%eax
3d11: 89 44 24 08 mov %eax,0x8(%esp)
3d15: 8b 45 0c mov 0xc(%ebp),%eax
3d18: 89 44 24 04 mov %eax,0x4(%esp)
3d1c: 8b 45 08 mov 0x8(%ebp),%eax
3d1f: 89 04 24 mov %eax,(%esp)
3d22: e8 26 ff ff ff call 3c4d <stosb>
3d27: 8b 45 08 mov 0x8(%ebp),%eax
3d2a: c9 leave
3d2b: c3 ret
00003d2c <strchr>:
3d2c: 55 push %ebp
3d2d: 89 e5 mov %esp,%ebp
3d2f: 83 ec 04 sub $0x4,%esp
3d32: 8b 45 0c mov 0xc(%ebp),%eax
3d35: 88 45 fc mov %al,-0x4(%ebp)
3d38: eb 14 jmp 3d4e <strchr+0x22>
3d3a: 8b 45 08 mov 0x8(%ebp),%eax
3d3d: 0f b6 00 movzbl (%eax),%eax
3d40: 3a 45 fc cmp -0x4(%ebp),%al
3d43: 75 05 jne 3d4a <strchr+0x1e>
3d45: 8b 45 08 mov 0x8(%ebp),%eax
3d48: eb 13 jmp 3d5d <strchr+0x31>
3d4a: 83 45 08 01 addl $0x1,0x8(%ebp)
3d4e: 8b 45 08 mov 0x8(%ebp),%eax
3d51: 0f b6 00 movzbl (%eax),%eax
3d54: 84 c0 test %al,%al
3d56: 75 e2 jne 3d3a <strchr+0xe>
3d58: b8 00 00 00 00 mov $0x0,%eax
3d5d: c9 leave
3d5e: c3 ret
00003d5f <gets>:
3d5f: 55 push %ebp
3d60: 89 e5 mov %esp,%ebp
3d62: 83 ec 28 sub $0x28,%esp
3d65: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
3d6c: eb 4c jmp 3dba <gets+0x5b>
3d6e: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
3d75: 00
3d76: 8d 45 ef lea -0x11(%ebp),%eax
3d79: 89 44 24 04 mov %eax,0x4(%esp)
3d7d: c7 04 24 00 00 00 00 movl $0x0,(%esp)
3d84: e8 44 01 00 00 call 3ecd <read>
3d89: 89 45 f0 mov %eax,-0x10(%ebp)
3d8c: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
3d90: 7f 02 jg 3d94 <gets+0x35>
3d92: eb 31 jmp 3dc5 <gets+0x66>
3d94: 8b 45 f4 mov -0xc(%ebp),%eax
3d97: 8d 50 01 lea 0x1(%eax),%edx
3d9a: 89 55 f4 mov %edx,-0xc(%ebp)
3d9d: 89 c2 mov %eax,%edx
3d9f: 8b 45 08 mov 0x8(%ebp),%eax
3da2: 01 c2 add %eax,%edx
3da4: 0f b6 45 ef movzbl -0x11(%ebp),%eax
3da8: 88 02 mov %al,(%edx)
3daa: 0f b6 45 ef movzbl -0x11(%ebp),%eax
3dae: 3c 0a cmp $0xa,%al
3db0: 74 13 je 3dc5 <gets+0x66>
3db2: 0f b6 45 ef movzbl -0x11(%ebp),%eax
3db6: 3c 0d cmp $0xd,%al
3db8: 74 0b je 3dc5 <gets+0x66>
3dba: 8b 45 f4 mov -0xc(%ebp),%eax
3dbd: 83 c0 01 add $0x1,%eax
3dc0: 3b 45 0c cmp 0xc(%ebp),%eax
3dc3: 7c a9 jl 3d6e <gets+0xf>
3dc5: 8b 55 f4 mov -0xc(%ebp),%edx
3dc8: 8b 45 08 mov 0x8(%ebp),%eax
3dcb: 01 d0 add %edx,%eax
3dcd: c6 00 00 movb $0x0,(%eax)
3dd0: 8b 45 08 mov 0x8(%ebp),%eax
3dd3: c9 leave
3dd4: c3 ret
00003dd5 <stat>:
3dd5: 55 push %ebp
3dd6: 89 e5 mov %esp,%ebp
3dd8: 83 ec 28 sub $0x28,%esp
3ddb: c7 44 24 04 00 00 00 movl $0x0,0x4(%esp)
3de2: 00
3de3: 8b 45 08 mov 0x8(%ebp),%eax
3de6: 89 04 24 mov %eax,(%esp)
3de9: e8 07 01 00 00 call 3ef5 <open>
3dee: 89 45 f4 mov %eax,-0xc(%ebp)
3df1: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
3df5: 79 07 jns 3dfe <stat+0x29>
3df7: b8 ff ff ff ff mov $0xffffffff,%eax
3dfc: eb 23 jmp 3e21 <stat+0x4c>
3dfe: 8b 45 0c mov 0xc(%ebp),%eax
3e01: 89 44 24 04 mov %eax,0x4(%esp)
3e05: 8b 45 f4 mov -0xc(%ebp),%eax
3e08: 89 04 24 mov %eax,(%esp)
3e0b: e8 fd 00 00 00 call 3f0d <fstat>
3e10: 89 45 f0 mov %eax,-0x10(%ebp)
3e13: 8b 45 f4 mov -0xc(%ebp),%eax
3e16: 89 04 24 mov %eax,(%esp)
3e19: e8 bf 00 00 00 call 3edd <close>
3e1e: 8b 45 f0 mov -0x10(%ebp),%eax
3e21: c9 leave
3e22: c3 ret
00003e23 <atoi>:
3e23: 55 push %ebp
3e24: 89 e5 mov %esp,%ebp
3e26: 83 ec 10 sub $0x10,%esp
3e29: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
3e30: eb 25 jmp 3e57 <atoi+0x34>
3e32: 8b 55 fc mov -0x4(%ebp),%edx
3e35: 89 d0 mov %edx,%eax
3e37: c1 e0 02 shl $0x2,%eax
3e3a: 01 d0 add %edx,%eax
3e3c: 01 c0 add %eax,%eax
3e3e: 89 c1 mov %eax,%ecx
3e40: 8b 45 08 mov 0x8(%ebp),%eax
3e43: 8d 50 01 lea 0x1(%eax),%edx
3e46: 89 55 08 mov %edx,0x8(%ebp)
3e49: 0f b6 00 movzbl (%eax),%eax
3e4c: 0f be c0 movsbl %al,%eax
3e4f: 01 c8 add %ecx,%eax
3e51: 83 e8 30 sub $0x30,%eax
3e54: 89 45 fc mov %eax,-0x4(%ebp)
3e57: 8b 45 08 mov 0x8(%ebp),%eax
3e5a: 0f b6 00 movzbl (%eax),%eax
3e5d: 3c 2f cmp $0x2f,%al
3e5f: 7e 0a jle 3e6b <atoi+0x48>
3e61: 8b 45 08 mov 0x8(%ebp),%eax
3e64: 0f b6 00 movzbl (%eax),%eax
3e67: 3c 39 cmp $0x39,%al
3e69: 7e c7 jle 3e32 <atoi+0xf>
3e6b: 8b 45 fc mov -0x4(%ebp),%eax
3e6e: c9 leave
3e6f: c3 ret
00003e70 <memmove>:
3e70: 55 push %ebp
3e71: 89 e5 mov %esp,%ebp
3e73: 83 ec 10 sub $0x10,%esp
3e76: 8b 45 08 mov 0x8(%ebp),%eax
3e79: 89 45 fc mov %eax,-0x4(%ebp)
3e7c: 8b 45 0c mov 0xc(%ebp),%eax
3e7f: 89 45 f8 mov %eax,-0x8(%ebp)
3e82: eb 17 jmp 3e9b <memmove+0x2b>
3e84: 8b 45 fc mov -0x4(%ebp),%eax
3e87: 8d 50 01 lea 0x1(%eax),%edx
3e8a: 89 55 fc mov %edx,-0x4(%ebp)
3e8d: 8b 55 f8 mov -0x8(%ebp),%edx
3e90: 8d 4a 01 lea 0x1(%edx),%ecx
3e93: 89 4d f8 mov %ecx,-0x8(%ebp)
3e96: 0f b6 12 movzbl (%edx),%edx
3e99: 88 10 mov %dl,(%eax)
3e9b: 8b 45 10 mov 0x10(%ebp),%eax
3e9e: 8d 50 ff lea -0x1(%eax),%edx
3ea1: 89 55 10 mov %edx,0x10(%ebp)
3ea4: 85 c0 test %eax,%eax
3ea6: 7f dc jg 3e84 <memmove+0x14>
3ea8: 8b 45 08 mov 0x8(%ebp),%eax
3eab: c9 leave
3eac: c3 ret
00003ead <fork>:
3ead: b8 01 00 00 00 mov $0x1,%eax
3eb2: cd 40 int $0x40
3eb4: c3 ret
00003eb5 <exit>:
3eb5: b8 02 00 00 00 mov $0x2,%eax
3eba: cd 40 int $0x40
3ebc: c3 ret
00003ebd <wait>:
3ebd: b8 03 00 00 00 mov $0x3,%eax
3ec2: cd 40 int $0x40
3ec4: c3 ret
00003ec5 <pipe>:
3ec5: b8 04 00 00 00 mov $0x4,%eax
3eca: cd 40 int $0x40
3ecc: c3 ret
00003ecd <read>:
3ecd: b8 05 00 00 00 mov $0x5,%eax
3ed2: cd 40 int $0x40
3ed4: c3 ret
00003ed5 <write>:
3ed5: b8 10 00 00 00 mov $0x10,%eax
3eda: cd 40 int $0x40
3edc: c3 ret
00003edd <close>:
3edd: b8 15 00 00 00 mov $0x15,%eax
3ee2: cd 40 int $0x40
3ee4: c3 ret
00003ee5 <kill>:
3ee5: b8 06 00 00 00 mov $0x6,%eax
3eea: cd 40 int $0x40
3eec: c3 ret
00003eed <exec>:
3eed: b8 07 00 00 00 mov $0x7,%eax
3ef2: cd 40 int $0x40
3ef4: c3 ret
00003ef5 <open>:
3ef5: b8 0f 00 00 00 mov $0xf,%eax
3efa: cd 40 int $0x40
3efc: c3 ret
00003efd <mknod>:
3efd: b8 11 00 00 00 mov $0x11,%eax
3f02: cd 40 int $0x40
3f04: c3 ret
00003f05 <unlink>:
3f05: b8 12 00 00 00 mov $0x12,%eax
3f0a: cd 40 int $0x40
3f0c: c3 ret
00003f0d <fstat>:
3f0d: b8 08 00 00 00 mov $0x8,%eax
3f12: cd 40 int $0x40
3f14: c3 ret
00003f15 <link>:
3f15: b8 13 00 00 00 mov $0x13,%eax
3f1a: cd 40 int $0x40
3f1c: c3 ret
00003f1d <mkdir>:
3f1d: b8 14 00 00 00 mov $0x14,%eax
3f22: cd 40 int $0x40
3f24: c3 ret
00003f25 <chdir>:
3f25: b8 09 00 00 00 mov $0x9,%eax
3f2a: cd 40 int $0x40
3f2c: c3 ret
00003f2d <dup>:
3f2d: b8 0a 00 00 00 mov $0xa,%eax
3f32: cd 40 int $0x40
3f34: c3 ret
00003f35 <getpid>:
3f35: b8 0b 00 00 00 mov $0xb,%eax
3f3a: cd 40 int $0x40
3f3c: c3 ret
00003f3d <sbrk>:
3f3d: b8 0c 00 00 00 mov $0xc,%eax
3f42: cd 40 int $0x40
3f44: c3 ret
00003f45 <sleep>:
3f45: b8 0d 00 00 00 mov $0xd,%eax
3f4a: cd 40 int $0x40
3f4c: c3 ret
00003f4d <uptime>:
3f4d: b8 0e 00 00 00 mov $0xe,%eax
3f52: cd 40 int $0x40
3f54: c3 ret
00003f55 <hello>:
3f55: b8 16 00 00 00 mov $0x16,%eax
3f5a: cd 40 int $0x40
3f5c: c3 ret
00003f5d <insdb>:
3f5d: b8 17 00 00 00 mov $0x17,%eax
3f62: cd 40 int $0x40
3f64: c3 ret
00003f65 <serchdb>:
3f65: b8 18 00 00 00 mov $0x18,%eax
3f6a: cd 40 int $0x40
3f6c: c3 ret
00003f6d <listdb>:
3f6d: b8 19 00 00 00 mov $0x19,%eax
3f72: cd 40 int $0x40
3f74: c3 ret
00003f75 <deletedb>:
3f75: b8 1a 00 00 00 mov $0x1a,%eax
3f7a: cd 40 int $0x40
3f7c: c3 ret
00003f7d <putc>:
#include "stat.h"
#include "user.h"
static void
putc(int fd, char c)
{
3f7d: 55 push %ebp
3f7e: 89 e5 mov %esp,%ebp
3f80: 83 ec 18 sub $0x18,%esp
3f83: 8b 45 0c mov 0xc(%ebp),%eax
3f86: 88 45 f4 mov %al,-0xc(%ebp)
write(fd, &c, 1);
3f89: c7 44 24 08 01 00 00 movl $0x1,0x8(%esp)
3f90: 00
3f91: 8d 45 f4 lea -0xc(%ebp),%eax
3f94: 89 44 24 04 mov %eax,0x4(%esp)
3f98: 8b 45 08 mov 0x8(%ebp),%eax
3f9b: 89 04 24 mov %eax,(%esp)
3f9e: e8 32 ff ff ff call 3ed5 <write>
}
3fa3: c9 leave
3fa4: c3 ret
00003fa5 <printint>:
static void
printint(int fd, int xx, int base, int sgn)
{
3fa5: 55 push %ebp
3fa6: 89 e5 mov %esp,%ebp
3fa8: 56 push %esi
3fa9: 53 push %ebx
3faa: 83 ec 30 sub $0x30,%esp
static char digits[] = "0123456789ABCDEF";
char buf[16];
int i, neg;
uint x;
neg = 0;
3fad: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
if(sgn && xx < 0){
3fb4: 83 7d 14 00 cmpl $0x0,0x14(%ebp)
3fb8: 74 17 je 3fd1 <printint+0x2c>
3fba: 83 7d 0c 00 cmpl $0x0,0xc(%ebp)
3fbe: 79 11 jns 3fd1 <printint+0x2c>
neg = 1;
3fc0: c7 45 f0 01 00 00 00 movl $0x1,-0x10(%ebp)
x = -xx;
3fc7: 8b 45 0c mov 0xc(%ebp),%eax
3fca: f7 d8 neg %eax
3fcc: 89 45 ec mov %eax,-0x14(%ebp)
3fcf: eb 06 jmp 3fd7 <printint+0x32>
} else {
x = xx;
3fd1: 8b 45 0c mov 0xc(%ebp),%eax
3fd4: 89 45 ec mov %eax,-0x14(%ebp)
}
i = 0;
3fd7: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
do{
buf[i++] = digits[x % base];
3fde: 8b 4d f4 mov -0xc(%ebp),%ecx
3fe1: 8d 41 01 lea 0x1(%ecx),%eax
3fe4: 89 45 f4 mov %eax,-0xc(%ebp)
3fe7: 8b 5d 10 mov 0x10(%ebp),%ebx
3fea: 8b 45 ec mov -0x14(%ebp),%eax
3fed: ba 00 00 00 00 mov $0x0,%edx
3ff2: f7 f3 div %ebx
3ff4: 89 d0 mov %edx,%eax
3ff6: 0f b6 80 f4 62 00 00 movzbl 0x62f4(%eax),%eax
3ffd: 88 44 0d dc mov %al,-0x24(%ebp,%ecx,1)
}while((x /= base) != 0);
4001: 8b 75 10 mov 0x10(%ebp),%esi
4004: 8b 45 ec mov -0x14(%ebp),%eax
4007: ba 00 00 00 00 mov $0x0,%edx
400c: f7 f6 div %esi
400e: 89 45 ec mov %eax,-0x14(%ebp)
4011: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
4015: 75 c7 jne 3fde <printint+0x39>
if(neg)
4017: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
401b: 74 10 je 402d <printint+0x88>
buf[i++] = '-';
401d: 8b 45 f4 mov -0xc(%ebp),%eax
4020: 8d 50 01 lea 0x1(%eax),%edx
4023: 89 55 f4 mov %edx,-0xc(%ebp)
4026: c6 44 05 dc 2d movb $0x2d,-0x24(%ebp,%eax,1)
while(--i >= 0)
402b: eb 1f jmp 404c <printint+0xa7>
402d: eb 1d jmp 404c <printint+0xa7>
putc(fd, buf[i]);
402f: 8d 55 dc lea -0x24(%ebp),%edx
4032: 8b 45 f4 mov -0xc(%ebp),%eax
4035: 01 d0 add %edx,%eax
4037: 0f b6 00 movzbl (%eax),%eax
403a: 0f be c0 movsbl %al,%eax
403d: 89 44 24 04 mov %eax,0x4(%esp)
4041: 8b 45 08 mov 0x8(%ebp),%eax
4044: 89 04 24 mov %eax,(%esp)
4047: e8 31 ff ff ff call 3f7d <putc>
buf[i++] = digits[x % base];
}while((x /= base) != 0);
if(neg)
buf[i++] = '-';
while(--i >= 0)
404c: 83 6d f4 01 subl $0x1,-0xc(%ebp)
4050: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
4054: 79 d9 jns 402f <printint+0x8a>
putc(fd, buf[i]);
}
4056: 83 c4 30 add $0x30,%esp
4059: 5b pop %ebx
405a: 5e pop %esi
405b: 5d pop %ebp
405c: c3 ret
0000405d <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
405d: 55 push %ebp
405e: 89 e5 mov %esp,%ebp
4060: 83 ec 38 sub $0x38,%esp
char *s;
int c, i, state;
uint *ap;
state = 0;
4063: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
ap = (uint*)(void*)&fmt + 1;
406a: 8d 45 0c lea 0xc(%ebp),%eax
406d: 83 c0 04 add $0x4,%eax
4070: 89 45 e8 mov %eax,-0x18(%ebp)
for(i = 0; fmt[i]; i++){
4073: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
407a: e9 7c 01 00 00 jmp 41fb <printf+0x19e>
c = fmt[i] & 0xff;
407f: 8b 55 0c mov 0xc(%ebp),%edx
4082: 8b 45 f0 mov -0x10(%ebp),%eax
4085: 01 d0 add %edx,%eax
4087: 0f b6 00 movzbl (%eax),%eax
408a: 0f be c0 movsbl %al,%eax
408d: 25 ff 00 00 00 and $0xff,%eax
4092: 89 45 e4 mov %eax,-0x1c(%ebp)
if(state == 0){
4095: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
4099: 75 2c jne 40c7 <printf+0x6a>
if(c == '%'){
409b: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
409f: 75 0c jne 40ad <printf+0x50>
state = '%';
40a1: c7 45 ec 25 00 00 00 movl $0x25,-0x14(%ebp)
40a8: e9 4a 01 00 00 jmp 41f7 <printf+0x19a>
} else {
putc(fd, c);
40ad: 8b 45 e4 mov -0x1c(%ebp),%eax
40b0: 0f be c0 movsbl %al,%eax
40b3: 89 44 24 04 mov %eax,0x4(%esp)
40b7: 8b 45 08 mov 0x8(%ebp),%eax
40ba: 89 04 24 mov %eax,(%esp)
40bd: e8 bb fe ff ff call 3f7d <putc>
40c2: e9 30 01 00 00 jmp 41f7 <printf+0x19a>
}
} else if(state == '%'){
40c7: 83 7d ec 25 cmpl $0x25,-0x14(%ebp)
40cb: 0f 85 26 01 00 00 jne 41f7 <printf+0x19a>
if(c == 'd'){
40d1: 83 7d e4 64 cmpl $0x64,-0x1c(%ebp)
40d5: 75 2d jne 4104 <printf+0xa7>
printint(fd, *ap, 10, 1);
40d7: 8b 45 e8 mov -0x18(%ebp),%eax
40da: 8b 00 mov (%eax),%eax
40dc: c7 44 24 0c 01 00 00 movl $0x1,0xc(%esp)
40e3: 00
40e4: c7 44 24 08 0a 00 00 movl $0xa,0x8(%esp)
40eb: 00
40ec: 89 44 24 04 mov %eax,0x4(%esp)
40f0: 8b 45 08 mov 0x8(%ebp),%eax
40f3: 89 04 24 mov %eax,(%esp)
40f6: e8 aa fe ff ff call 3fa5 <printint>
ap++;
40fb: 83 45 e8 04 addl $0x4,-0x18(%ebp)
40ff: e9 ec 00 00 00 jmp 41f0 <printf+0x193>
} else if(c == 'x' || c == 'p'){
4104: 83 7d e4 78 cmpl $0x78,-0x1c(%ebp)
4108: 74 06 je 4110 <printf+0xb3>
410a: 83 7d e4 70 cmpl $0x70,-0x1c(%ebp)
410e: 75 2d jne 413d <printf+0xe0>
printint(fd, *ap, 16, 0);
4110: 8b 45 e8 mov -0x18(%ebp),%eax
4113: 8b 00 mov (%eax),%eax
4115: c7 44 24 0c 00 00 00 movl $0x0,0xc(%esp)
411c: 00
411d: c7 44 24 08 10 00 00 movl $0x10,0x8(%esp)
4124: 00
4125: 89 44 24 04 mov %eax,0x4(%esp)
4129: 8b 45 08 mov 0x8(%ebp),%eax
412c: 89 04 24 mov %eax,(%esp)
412f: e8 71 fe ff ff call 3fa5 <printint>
ap++;
4134: 83 45 e8 04 addl $0x4,-0x18(%ebp)
4138: e9 b3 00 00 00 jmp 41f0 <printf+0x193>
} else if(c == 's'){
413d: 83 7d e4 73 cmpl $0x73,-0x1c(%ebp)
4141: 75 45 jne 4188 <printf+0x12b>
s = (char*)*ap;
4143: 8b 45 e8 mov -0x18(%ebp),%eax
4146: 8b 00 mov (%eax),%eax
4148: 89 45 f4 mov %eax,-0xc(%ebp)
ap++;
414b: 83 45 e8 04 addl $0x4,-0x18(%ebp)
if(s == 0)
414f: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
4153: 75 09 jne 415e <printf+0x101>
s = "(null)";
4155: c7 45 f4 f6 5b 00 00 movl $0x5bf6,-0xc(%ebp)
while(*s != 0){
415c: eb 1e jmp 417c <printf+0x11f>
415e: eb 1c jmp 417c <printf+0x11f>
putc(fd, *s);
4160: 8b 45 f4 mov -0xc(%ebp),%eax
4163: 0f b6 00 movzbl (%eax),%eax
4166: 0f be c0 movsbl %al,%eax
4169: 89 44 24 04 mov %eax,0x4(%esp)
416d: 8b 45 08 mov 0x8(%ebp),%eax
4170: 89 04 24 mov %eax,(%esp)
4173: e8 05 fe ff ff call 3f7d <putc>
s++;
4178: 83 45 f4 01 addl $0x1,-0xc(%ebp)
} else if(c == 's'){
s = (char*)*ap;
ap++;
if(s == 0)
s = "(null)";
while(*s != 0){
417c: 8b 45 f4 mov -0xc(%ebp),%eax
417f: 0f b6 00 movzbl (%eax),%eax
4182: 84 c0 test %al,%al
4184: 75 da jne 4160 <printf+0x103>
4186: eb 68 jmp 41f0 <printf+0x193>
putc(fd, *s);
s++;
}
} else if(c == 'c'){
4188: 83 7d e4 63 cmpl $0x63,-0x1c(%ebp)
418c: 75 1d jne 41ab <printf+0x14e>
putc(fd, *ap);
418e: 8b 45 e8 mov -0x18(%ebp),%eax
4191: 8b 00 mov (%eax),%eax
4193: 0f be c0 movsbl %al,%eax
4196: 89 44 24 04 mov %eax,0x4(%esp)
419a: 8b 45 08 mov 0x8(%ebp),%eax
419d: 89 04 24 mov %eax,(%esp)
41a0: e8 d8 fd ff ff call 3f7d <putc>
ap++;
41a5: 83 45 e8 04 addl $0x4,-0x18(%ebp)
41a9: eb 45 jmp 41f0 <printf+0x193>
} else if(c == '%'){
41ab: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
41af: 75 17 jne 41c8 <printf+0x16b>
putc(fd, c);
41b1: 8b 45 e4 mov -0x1c(%ebp),%eax
41b4: 0f be c0 movsbl %al,%eax
41b7: 89 44 24 04 mov %eax,0x4(%esp)
41bb: 8b 45 08 mov 0x8(%ebp),%eax
41be: 89 04 24 mov %eax,(%esp)
41c1: e8 b7 fd ff ff call 3f7d <putc>
41c6: eb 28 jmp 41f0 <printf+0x193>
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
41c8: c7 44 24 04 25 00 00 movl $0x25,0x4(%esp)
41cf: 00
41d0: 8b 45 08 mov 0x8(%ebp),%eax
41d3: 89 04 24 mov %eax,(%esp)
41d6: e8 a2 fd ff ff call 3f7d <putc>
putc(fd, c);
41db: 8b 45 e4 mov -0x1c(%ebp),%eax
41de: 0f be c0 movsbl %al,%eax
41e1: 89 44 24 04 mov %eax,0x4(%esp)
41e5: 8b 45 08 mov 0x8(%ebp),%eax
41e8: 89 04 24 mov %eax,(%esp)
41eb: e8 8d fd ff ff call 3f7d <putc>
}
state = 0;
41f0: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
int c, i, state;
uint *ap;
state = 0;
ap = (uint*)(void*)&fmt + 1;
for(i = 0; fmt[i]; i++){
41f7: 83 45 f0 01 addl $0x1,-0x10(%ebp)
41fb: 8b 55 0c mov 0xc(%ebp),%edx
41fe: 8b 45 f0 mov -0x10(%ebp),%eax
4201: 01 d0 add %edx,%eax
4203: 0f b6 00 movzbl (%eax),%eax
4206: 84 c0 test %al,%al
4208: 0f 85 71 fe ff ff jne 407f <printf+0x22>
putc(fd, c);
}
state = 0;
}
}
}
420e: c9 leave
420f: c3 ret
00004210 <free>:
4210: 55 push %ebp
4211: 89 e5 mov %esp,%ebp
4213: 83 ec 10 sub $0x10,%esp
4216: 8b 45 08 mov 0x8(%ebp),%eax
4219: 83 e8 08 sub $0x8,%eax
421c: 89 45 f8 mov %eax,-0x8(%ebp)
421f: a1 a8 63 00 00 mov 0x63a8,%eax
4224: 89 45 fc mov %eax,-0x4(%ebp)
4227: eb 24 jmp 424d <free+0x3d>
4229: 8b 45 fc mov -0x4(%ebp),%eax
422c: 8b 00 mov (%eax),%eax
422e: 3b 45 fc cmp -0x4(%ebp),%eax
4231: 77 12 ja 4245 <free+0x35>
4233: 8b 45 f8 mov -0x8(%ebp),%eax
4236: 3b 45 fc cmp -0x4(%ebp),%eax
4239: 77 24 ja 425f <free+0x4f>
423b: 8b 45 fc mov -0x4(%ebp),%eax
423e: 8b 00 mov (%eax),%eax
4240: 3b 45 f8 cmp -0x8(%ebp),%eax
4243: 77 1a ja 425f <free+0x4f>
4245: 8b 45 fc mov -0x4(%ebp),%eax
4248: 8b 00 mov (%eax),%eax
424a: 89 45 fc mov %eax,-0x4(%ebp)
424d: 8b 45 f8 mov -0x8(%ebp),%eax
4250: 3b 45 fc cmp -0x4(%ebp),%eax
4253: 76 d4 jbe 4229 <free+0x19>
4255: 8b 45 fc mov -0x4(%ebp),%eax
4258: 8b 00 mov (%eax),%eax
425a: 3b 45 f8 cmp -0x8(%ebp),%eax
425d: 76 ca jbe 4229 <free+0x19>
425f: 8b 45 f8 mov -0x8(%ebp),%eax
4262: 8b 40 04 mov 0x4(%eax),%eax
4265: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
426c: 8b 45 f8 mov -0x8(%ebp),%eax
426f: 01 c2 add %eax,%edx
4271: 8b 45 fc mov -0x4(%ebp),%eax
4274: 8b 00 mov (%eax),%eax
4276: 39 c2 cmp %eax,%edx
4278: 75 24 jne 429e <free+0x8e>
427a: 8b 45 f8 mov -0x8(%ebp),%eax
427d: 8b 50 04 mov 0x4(%eax),%edx
4280: 8b 45 fc mov -0x4(%ebp),%eax
4283: 8b 00 mov (%eax),%eax
4285: 8b 40 04 mov 0x4(%eax),%eax
4288: 01 c2 add %eax,%edx
428a: 8b 45 f8 mov -0x8(%ebp),%eax
428d: 89 50 04 mov %edx,0x4(%eax)
4290: 8b 45 fc mov -0x4(%ebp),%eax
4293: 8b 00 mov (%eax),%eax
4295: 8b 10 mov (%eax),%edx
4297: 8b 45 f8 mov -0x8(%ebp),%eax
429a: 89 10 mov %edx,(%eax)
429c: eb 0a jmp 42a8 <free+0x98>
429e: 8b 45 fc mov -0x4(%ebp),%eax
42a1: 8b 10 mov (%eax),%edx
42a3: 8b 45 f8 mov -0x8(%ebp),%eax
42a6: 89 10 mov %edx,(%eax)
42a8: 8b 45 fc mov -0x4(%ebp),%eax
42ab: 8b 40 04 mov 0x4(%eax),%eax
42ae: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
42b5: 8b 45 fc mov -0x4(%ebp),%eax
42b8: 01 d0 add %edx,%eax
42ba: 3b 45 f8 cmp -0x8(%ebp),%eax
42bd: 75 20 jne 42df <free+0xcf>
42bf: 8b 45 fc mov -0x4(%ebp),%eax
42c2: 8b 50 04 mov 0x4(%eax),%edx
42c5: 8b 45 f8 mov -0x8(%ebp),%eax
42c8: 8b 40 04 mov 0x4(%eax),%eax
42cb: 01 c2 add %eax,%edx
42cd: 8b 45 fc mov -0x4(%ebp),%eax
42d0: 89 50 04 mov %edx,0x4(%eax)
42d3: 8b 45 f8 mov -0x8(%ebp),%eax
42d6: 8b 10 mov (%eax),%edx
42d8: 8b 45 fc mov -0x4(%ebp),%eax
42db: 89 10 mov %edx,(%eax)
42dd: eb 08 jmp 42e7 <free+0xd7>
42df: 8b 45 fc mov -0x4(%ebp),%eax
42e2: 8b 55 f8 mov -0x8(%ebp),%edx
42e5: 89 10 mov %edx,(%eax)
42e7: 8b 45 fc mov -0x4(%ebp),%eax
42ea: a3 a8 63 00 00 mov %eax,0x63a8
42ef: c9 leave
42f0: c3 ret
000042f1 <morecore>:
42f1: 55 push %ebp
42f2: 89 e5 mov %esp,%ebp
42f4: 83 ec 28 sub $0x28,%esp
42f7: 81 7d 08 ff 0f 00 00 cmpl $0xfff,0x8(%ebp)
42fe: 77 07 ja 4307 <morecore+0x16>
4300: c7 45 08 00 10 00 00 movl $0x1000,0x8(%ebp)
4307: 8b 45 08 mov 0x8(%ebp),%eax
430a: c1 e0 03 shl $0x3,%eax
430d: 89 04 24 mov %eax,(%esp)
4310: e8 28 fc ff ff call 3f3d <sbrk>
4315: 89 45 f4 mov %eax,-0xc(%ebp)
4318: 83 7d f4 ff cmpl $0xffffffff,-0xc(%ebp)
431c: 75 07 jne 4325 <morecore+0x34>
431e: b8 00 00 00 00 mov $0x0,%eax
4323: eb 22 jmp 4347 <morecore+0x56>
4325: 8b 45 f4 mov -0xc(%ebp),%eax
4328: 89 45 f0 mov %eax,-0x10(%ebp)
432b: 8b 45 f0 mov -0x10(%ebp),%eax
432e: 8b 55 08 mov 0x8(%ebp),%edx
4331: 89 50 04 mov %edx,0x4(%eax)
4334: 8b 45 f0 mov -0x10(%ebp),%eax
4337: 83 c0 08 add $0x8,%eax
433a: 89 04 24 mov %eax,(%esp)
433d: e8 ce fe ff ff call 4210 <free>
4342: a1 a8 63 00 00 mov 0x63a8,%eax
4347: c9 leave
4348: c3 ret
00004349 <malloc>:
4349: 55 push %ebp
434a: 89 e5 mov %esp,%ebp
434c: 83 ec 28 sub $0x28,%esp
434f: 8b 45 08 mov 0x8(%ebp),%eax
4352: 83 c0 07 add $0x7,%eax
4355: c1 e8 03 shr $0x3,%eax
4358: 83 c0 01 add $0x1,%eax
435b: 89 45 ec mov %eax,-0x14(%ebp)
435e: a1 a8 63 00 00 mov 0x63a8,%eax
4363: 89 45 f0 mov %eax,-0x10(%ebp)
4366: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
436a: 75 23 jne 438f <malloc+0x46>
436c: c7 45 f0 a0 63 00 00 movl $0x63a0,-0x10(%ebp)
4373: 8b 45 f0 mov -0x10(%ebp),%eax
4376: a3 a8 63 00 00 mov %eax,0x63a8
437b: a1 a8 63 00 00 mov 0x63a8,%eax
4380: a3 a0 63 00 00 mov %eax,0x63a0
4385: c7 05 a4 63 00 00 00 movl $0x0,0x63a4
438c: 00 00 00
438f: 8b 45 f0 mov -0x10(%ebp),%eax
4392: 8b 00 mov (%eax),%eax
4394: 89 45 f4 mov %eax,-0xc(%ebp)
4397: 8b 45 f4 mov -0xc(%ebp),%eax
439a: 8b 40 04 mov 0x4(%eax),%eax
439d: 3b 45 ec cmp -0x14(%ebp),%eax
43a0: 72 4d jb 43ef <malloc+0xa6>
43a2: 8b 45 f4 mov -0xc(%ebp),%eax
43a5: 8b 40 04 mov 0x4(%eax),%eax
43a8: 3b 45 ec cmp -0x14(%ebp),%eax
43ab: 75 0c jne 43b9 <malloc+0x70>
43ad: 8b 45 f4 mov -0xc(%ebp),%eax
43b0: 8b 10 mov (%eax),%edx
43b2: 8b 45 f0 mov -0x10(%ebp),%eax
43b5: 89 10 mov %edx,(%eax)
43b7: eb 26 jmp 43df <malloc+0x96>
43b9: 8b 45 f4 mov -0xc(%ebp),%eax
43bc: 8b 40 04 mov 0x4(%eax),%eax
43bf: 2b 45 ec sub -0x14(%ebp),%eax
43c2: 89 c2 mov %eax,%edx
43c4: 8b 45 f4 mov -0xc(%ebp),%eax
43c7: 89 50 04 mov %edx,0x4(%eax)
43ca: 8b 45 f4 mov -0xc(%ebp),%eax
43cd: 8b 40 04 mov 0x4(%eax),%eax
43d0: c1 e0 03 shl $0x3,%eax
43d3: 01 45 f4 add %eax,-0xc(%ebp)
43d6: 8b 45 f4 mov -0xc(%ebp),%eax
43d9: 8b 55 ec mov -0x14(%ebp),%edx
43dc: 89 50 04 mov %edx,0x4(%eax)
43df: 8b 45 f0 mov -0x10(%ebp),%eax
43e2: a3 a8 63 00 00 mov %eax,0x63a8
43e7: 8b 45 f4 mov -0xc(%ebp),%eax
43ea: 83 c0 08 add $0x8,%eax
43ed: eb 38 jmp 4427 <malloc+0xde>
43ef: a1 a8 63 00 00 mov 0x63a8,%eax
43f4: 39 45 f4 cmp %eax,-0xc(%ebp)
43f7: 75 1b jne 4414 <malloc+0xcb>
43f9: 8b 45 ec mov -0x14(%ebp),%eax
43fc: 89 04 24 mov %eax,(%esp)
43ff: e8 ed fe ff ff call 42f1 <morecore>
4404: 89 45 f4 mov %eax,-0xc(%ebp)
4407: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
440b: 75 07 jne 4414 <malloc+0xcb>
440d: b8 00 00 00 00 mov $0x0,%eax
4412: eb 13 jmp 4427 <malloc+0xde>
4414: 8b 45 f4 mov -0xc(%ebp),%eax
4417: 89 45 f0 mov %eax,-0x10(%ebp)
441a: 8b 45 f4 mov -0xc(%ebp),%eax
441d: 8b 00 mov (%eax),%eax
441f: 89 45 f4 mov %eax,-0xc(%ebp)
4422: e9 70 ff ff ff jmp 4397 <malloc+0x4e>
4427: c9 leave
4428: c3 ret
| sigmasigma/xv6_memorydb | usertests.asm | Assembly | mit | 230,592 |
; file testing registers initial values
; Ange Albertini, BSD LICENCE 2011
%include 'consts.inc'
IMAGEBASE equ 400000h
org IMAGEBASE
bits 32
TLSSIZE equ 34982734h
SECTIONALIGN equ 1000h
FILEALIGN equ 200h
istruc IMAGE_DOS_HEADER
at IMAGE_DOS_HEADER.e_magic, db 'MZ'
at IMAGE_DOS_HEADER.e_lfanew, dd NT_Signature - IMAGEBASE
iend
NT_Signature:
istruc IMAGE_NT_HEADERS
at IMAGE_NT_HEADERS.Signature, db 'PE', 0, 0
iend
istruc IMAGE_FILE_HEADER
at IMAGE_FILE_HEADER.Machine, dw IMAGE_FILE_MACHINE_I386
at IMAGE_FILE_HEADER.NumberOfSections, dw NUMBEROFSECTIONS
at IMAGE_FILE_HEADER.SizeOfOptionalHeader, dw SIZEOFOPTIONALHEADER
at IMAGE_FILE_HEADER.Characteristics, dw IMAGE_FILE_EXECUTABLE_IMAGE | IMAGE_FILE_32BIT_MACHINE
iend
OptionalHeader:
istruc IMAGE_OPTIONAL_HEADER32
at IMAGE_OPTIONAL_HEADER32.Magic, dw IMAGE_NT_OPTIONAL_HDR32_MAGIC
at IMAGE_OPTIONAL_HEADER32.AddressOfEntryPoint, dd EntryPoint - IMAGEBASE
at IMAGE_OPTIONAL_HEADER32.ImageBase, dd IMAGEBASE
at IMAGE_OPTIONAL_HEADER32.SectionAlignment, dd SECTIONALIGN
at IMAGE_OPTIONAL_HEADER32.FileAlignment, dd FILEALIGN
at IMAGE_OPTIONAL_HEADER32.MajorSubsystemVersion, dw 4
at IMAGE_OPTIONAL_HEADER32.SizeOfImage, dd 2 * SECTIONALIGN
at IMAGE_OPTIONAL_HEADER32.SizeOfHeaders, dd SIZEOFHEADERS
at IMAGE_OPTIONAL_HEADER32.Subsystem, dw IMAGE_SUBSYSTEM_WINDOWS_CUI
at IMAGE_OPTIONAL_HEADER32.NumberOfRvaAndSizes, dd 16
iend
istruc IMAGE_DATA_DIRECTORY_16
at IMAGE_DATA_DIRECTORY_16.ImportsVA, dd Import_Descriptor - IMAGEBASE
at IMAGE_DATA_DIRECTORY_16.TLSVA, dd Image_Tls_Directory32 - IMAGEBASE
at IMAGE_DATA_DIRECTORY_16.TLSSize, dd TLSSIZE
iend
SIZEOFOPTIONALHEADER equ $ - OptionalHeader
SectionHeader:
istruc IMAGE_SECTION_HEADER
at IMAGE_SECTION_HEADER.VirtualSize, dd 1 * SECTIONALIGN
at IMAGE_SECTION_HEADER.VirtualAddress, dd 1 * SECTIONALIGN
at IMAGE_SECTION_HEADER.SizeOfRawData, dd 3 * FILEALIGN
at IMAGE_SECTION_HEADER.PointerToRawData, dd 1 * FILEALIGN
at IMAGE_SECTION_HEADER.Characteristics, dd IMAGE_SCN_MEM_EXECUTE | IMAGE_SCN_MEM_WRITE
iend
NUMBEROFSECTIONS equ ($ - SectionHeader) / IMAGE_SECTION_HEADER_size
SIZEOFHEADERS equ $ - IMAGEBASE
%macro _p 1
push %1
call [__imp__printf]
add esp, 1 * 4
%endmacro
section progbits vstart=IMAGEBASE + SECTIONALIGN align=FILEALIGN
nop
EntryPoint:
xchg esp, [fake_esp]
pushf
pusha
xchg esp, [fake_esp]
_p EPstarted
_
mov eax, [flags]
cmp eax, 246h
jz good_EP_flags
_
_p bad_flags
good_EP_flags:
_
mov eax, [eax_]
cmp eax, 0 ; good XP value
jz good_EP_eax
_
cmp eax, 70000000h ; good >=Vista value
ja good_EP_eax
_
_p bad_eax
good_EP_eax:
mov ecx, [ecx_]
cmp ecx, 0 ; good >= Vista value
jz good_EP_ecx
mov eax, esp
sub eax, ecx
cmp eax, 20h ; good XP value
jbe good_EP_ecx
_
_p bad_ecx
good_EP_ecx:
mov edx, [edx_]
cmp edx, EntryPoint ; good >= Vista value
jz good_EP_edx
cmp edx, 70000000h ; good XP value
ja good_EP_edx
_
_p bad_edx
good_EP_edx:
; mov esi, [esi_]
; cmp esi, 10h ; standard range, 0 most of the time , not reliable under XP ?
; jbe good_EP_esi
;_
; _p bad_esi
;good_EP_esi:
; mov edi, [edi_]
; cmp edi, 10h ; standard range, 0 most of the time ?
; jbe good_EP_edi
;_
; _p bad_edi
;good_EP_edi:
_p finished
push 0
call [__imp__ExitProcess]
_c
EPstarted db ' # started EntryPoint', 0ah, 0
finished db ' # finished', 0ah, 0
_d
align FILEALIGN, db 90h
TLS:
xchg esp, [fake_esp]
pushf
pusha
xchg esp, [fake_esp]
_
mov dword [Callbacks], 0
_p msg
_p tls_started
_
mov eax, [flags]
cmp eax, 246h
jz good_tls_flags
_
_p bad_flags
good_tls_flags:
_
mov eax, [eax_]
cmp eax, 0 ; good >=Vista value
jz good_tls_eax
_
cmp eax, TLS ; good XP value
jz good_tls_eax
_
_p bad_eax
good_tls_eax:
mov ecx, [ecx_]
cmp ecx, 11h ; good >=Vista value
jz good_tls_ecx
cmp ecx, TLSSIZE ; good XP value
jz good_tls_ecx
_
_p bad_ecx
good_tls_ecx:
_
mov ebx, [ebx_]
cmp ebx, TLS ; good >=Vista Value
jz good_tls_ebx
cmp ebx, 0 ; good XP value
jz good_tls_ebx
_
_p bad_ebx
good_tls_ebx:
_
mov edx, [edx_]
cmp edx, Image_Tls_Directory32 - IMAGEBASE ; good XP value
jz good_tls_edx
cmp edx, 76000000h ; good >=Vista Value, in ntdll
jae good_tls_edx
_
_p bad_edx
good_tls_edx:
mov dword [fake_esp], fake_stack
retn
msg db ' * initial registers value tester:', 0ah, 0
tls_started db ' # started TLS', 0ah, 0
bad_flags db ' * bad flags', 0ah, 0
bad_eax db ' * bad EAX value', 0ah, 0
bad_ebx db ' * bad EBX value', 0ah, 0
bad_ecx db ' * bad ECX value', 0ah, 0
bad_edx db ' * bad EDX value', 0ah, 0
bad_esi db ' * bad ESI value', 0ah, 0
bad_edi db ' * bad EDI value', 0ah, 0
Image_Tls_Directory32:
StartAddressOfRawData dd 0
EndAddressOfRawData dd 0
AddressOfIndex dd Characteristics
AddressOfCallBacks dd Callbacks
SizeOfZeroFill dd 0
Characteristics dd 0
Callbacks dd TLS, 0
align FILEALIGN, db 0
Import_Descriptor:
;kernel32.dll_DESCRIPTOR:
dd kernel32.dll_hintnames - IMAGEBASE
dd 0, 0
dd kernel32.dll - IMAGEBASE
dd kernel32.dll_iat - IMAGEBASE
;msvcrt.dll_DESCRIPTOR:
dd msvcrt.dll_hintnames - IMAGEBASE
dd 0, 0
dd msvcrt.dll - IMAGEBASE
dd msvcrt.dll_iat - IMAGEBASE
;terminator
dd 0, 0, 0, 0, 0
_d
kernel32.dll_hintnames:
dd hnExitProcess - IMAGEBASE
dd 0
msvcrt.dll_hintnames:
dd hnprintf - IMAGEBASE
dd 0
_d
hnExitProcess:
dw 0
db 'ExitProcess', 0
hnprintf:
dw 0
db 'printf', 0
_d
kernel32.dll_iat:
__imp__ExitProcess:
dd hnExitProcess - IMAGEBASE
dd 0
msvcrt.dll_iat:
__imp__printf:
dd hnprintf - IMAGEBASE
dd 0
_d
kernel32.dll db 'kernel32.dll', 0
msvcrt.dll db 'msvcrt.dll', 0
_d
edi_ dd 0
esi_ dd 0
ebp_ dd 0
esp_ dd 0
ebx_ dd 0
edx_ dd 0
ecx_ dd 0
eax_ dd 0
flags dd 0
fake_stack dd 0
fake_esp dd fake_stack
_d
align FILEALIGN, db 0
| angea/corkami | wip/x86odd/initvals.asm | Assembly | bsd-2-clause | 6,620 |
/**
* Fails the test if the value in register a does not
* match the expected value
*/
.macro "expect.a.toBe" args expected
cp expected
call nz, smsspec.runner.expectationFailed
.endm
| eljay26/smsspec | src/expect.asm | Assembly | mit | 195 |
_main:
;PWM_ADC.mbas,7 :: org 0x1000
;PWM_ADC.mbas,10 :: TRISB.4 = 1
BSF TRISB+0, 4
;PWM_ADC.mbas,11 :: TRISC.5 = 0
BCF TRISC+0, 5
;PWM_ADC.mbas,12 :: ADC_Init_Advanced(_ADC_INTERNAL_REF)
CLRF FARG_ADC_Init_Advanced_reference+0
CALL _ADC_Init_Advanced+0, 0
;PWM_ADC.mbas,13 :: PWM1_Init(5000)
BCF T2CON+0, 0, 0
BCF T2CON+0, 1, 0
BSF T2CON+0, 0, 0
BSF T2CON+0, 1, 0
MOVLW 149
MOVWF PR2+0, 0
CALL _PWM1_Init+0, 0
;PWM_ADC.mbas,14 :: PWM1_Start()
CALL _PWM1_Start+0, 0
;PWM_ADC.mbas,16 :: loop:
L__main_loop:
;PWM_ADC.mbas,17 :: x = ADC_Get_Sample(10)
MOVLW 10
MOVWF FARG_ADC_Get_Sample_channel+0
CALL _ADC_Get_Sample+0, 0
MOVF R0, 0
MOVWF _x+0
MOVF R1, 0
MOVWF _x+1
;PWM_ADC.mbas,18 :: x = x>>2
MOVF R0, 0
MOVWF R2
MOVF R1, 0
MOVWF R3
RRCF R3, 1
RRCF R2, 1
BCF R3, 7
RRCF R3, 1
RRCF R2, 1
BCF R3, 7
MOVF R2, 0
MOVWF _x+0
MOVF R3, 0
MOVWF _x+1
;PWM_ADC.mbas,19 :: PWM1_Set_Duty(x)
MOVF R2, 0
MOVWF FARG_PWM1_Set_Duty_new_duty+0
CALL _PWM1_Set_Duty+0, 0
;PWM_ADC.mbas,20 :: delay_ms(20)
MOVLW 2
MOVWF R11, 0
MOVLW 56
MOVWF R12, 0
MOVLW 173
MOVWF R13, 0
L__main2:
DECFSZ R13, 1, 1
BRA L__main2
DECFSZ R12, 1, 1
BRA L__main2
DECFSZ R11, 1, 1
BRA L__main2
;PWM_ADC.mbas,22 :: if porta.3 = 0 then
BTFSC PORTA+0, 3
GOTO L__main4
;PWM_ADC.mbas,23 :: asm goto 0x30 end asm
GOTO 48
L__main4:
;PWM_ADC.mbas,26 :: goto loop
GOTO L__main_loop
L_end_main:
GOTO $+0
; end of _main
| DAFRELECTRONICS/ThunderBolt-Nova | Ejemplos/mikroBasic/PWM_ADC/PWM_ADC.asm | Assembly | mit | 1,830 |
LIST P=16F877A
#INCLUDE P16F877A.INC
BCF STATUS,RP1
BSF STATUS,RP0
MOVLW 0XFF
MOVWF TRISB
MOVWF TRISC
MOVLW 0X00
MOVWF TRISD
BCF STATUS,RP0
BCF STATUS,RP1
BTFSS PORTC,7
GOTO LOOPA
GOTO LOOPB
LOOPA
BTFSS PORTB,6
GOTO LOOPC
GOTO LOOPD
LOOPC
BTFSC PORTC,5
CALL S1
BTFSS PORTC,5
CALL S2
CALL T1
LOOPD
BTFSC PORTC,5
CALL S3
BTFSS PORTC,5
CALL S4
CALL T1
LOOPB
BTFSS PORTB,6
GOTO LOOPE
GOTO LOOPF
LOOPE
BTFSC PORTC,5
CALL S5
BTFSS PORTC,5
CALL S6
CALL T1
LOOPF
BTFSC PORTC,5
CALL S7
BTFSS PORTC,5
CALL S8
CALL T1
S1
MOVF PORTB,W
MOVWF 0X20
MOVF PORTC,W
ADDWF 0X20,W
MOVWF PORTD
RETURN
S2
MOVF PORTB,W
MOVWF 0X20
MOVF PORTC,W
SUBWF 0X20,W
MOVWF PORTD
RETURN
S3
MOVF PORTB,W
MOVWF 0X20
MOVLW 0X00
MOVWF 0X21
BCF PORTC,5
BCF PORTC,6
BCF PORTC,7
MOVF PORTC,W
MUL
ADDWF 0X21,F
DECFSZ 0X20
GOTO MUL
MOVF 0X21,W
MOVWF PORTD
RETURN
S4
MOVLW 0X00
MOVWF 0X40
MOVF PORTB,W
MOVWF 0X20
BCF PORTC,5
BCF PORTC,6
BCF PORTC,7
MOVF PORTC,W
DIV
SUBWF 0X20,W
BTFSS PORTC,C
INCF 0x40
BTFSS PORTC,C
GOTO DIV
MOVF 0X40,W
MOVWF PORTD
RETURN
S5
MOVF PORTB,W
MOVWF 0X20
MOVF PORTC,W
ANDWF 0X20,W
MOVWF PORTD
RETURN
S6
MOVF PORTB,W
MOVWF 0X20
MOVF PORTC,W
IORWF 0X20,W
MOVWF PORTD
RETURN
S7
MOVF PORTB,W
MOVWF 0X20
MOVF PORTC,W
XORWF 0X20,W
MOVWF PORTD
RETURN
S8
MOVF PORTB,W
MOVLW 0X20
COMF 0X20
MOVF 0X20,W
MOVWF PORTD
RETURN
T1
END
| geojoyce/geojoyce.github.io | C/led2.asm | Assembly | apache-2.0 | 1,522 |
.setcpu "6502"
.autoimport on
.export update_screen
.export main_screen_init
.export char_test
.export init_menu
.export init_ppu
.export jp_status
;;for debugging..
.export scroll_next
.segment "STARTUP"
;;;screen func table.
update_funcs:
.addr main_screen_updt ;0
.addr inet_screen_updt ;1
.addr game_screen_updt ;2
.addr shell_screen_updt ;3
.addr inet_bmark_scr_updt ;4
.addr inet_srch_scr_updt ;5
.addr inet_dirct_scr_updt ;6
.word $00
.proc update_screen
;;;get current screen stat.
lda screen_status
asl ;;offset address to word.
tay
lda update_funcs, y ;;get handler low.
sta $02
iny
lda update_funcs, y ;;get handler hi
sta $03
;;goto handler.
jmp ($02)
.endproc
;;;init func table.
init_funcs:
.addr main_screen_init ;0
.addr inet_screen_init ;1
.addr game_screen_init ;2
.addr shell_screen_init ;3
.addr inet_bmark_scr_init ;4
.addr inet_srch_scr_init ;5
.addr inet_dirct_scr_init ;6
.word $00
.proc init_screen
;;;get current screen stat.
lda screen_status
asl ;;offset address to word.
tay
lda init_funcs, y ;;get handler low.
sta $02
iny
lda init_funcs, y ;;get handler hi
sta $03
;;goto handler.
jmp ($02)
.endproc
.proc main_screen_updt
;;;case up
lda #$10
bit jp1_data
beq @down
lda #1
cmp top_menu_select
bne :+
jmp @end
:
;;move cursor up.
lda top_menu_cur_pos
sta $02
lda top_menu_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
sec
lda #$20
sta $00
lda top_menu_cur_pos+1
sbc $00
sta top_menu_cur_pos+1
sta $03
lda #$00
sta $00
lda top_menu_cur_pos
sbc $00
sta top_menu_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;decrement selected index.
dec top_menu_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @end
@down:
;;case down
lda #$20
bit jp1_data
beq @a
lda #3
cmp top_menu_select
beq @end
;;move cursor down.
lda top_menu_cur_pos
sta $02
lda top_menu_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
clc
lda #$20
adc top_menu_cur_pos+1
sta top_menu_cur_pos+1
sta $03
lda #$00
adc top_menu_cur_pos
sta top_menu_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
inc top_menu_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @end
@a:
;;case a
lda #$01
bit jp1_data
beq @end
lda top_menu_select
sta screen_status ;;navigate to next screen.
jsr init_screen
;;invalidate jp input for a while.
lda #$00
sta jp_status
@end:
rts
.endproc
.proc inet_screen_updt
;;;case up
lda #$10
bit jp1_data
beq @down
lda #4
cmp inet_menu_select
bne :+
jmp @end
:
;;move cursor up.
lda inet_menu_cur_pos
sta $02
lda inet_menu_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
sec
lda #$20
sta $00
lda inet_menu_cur_pos+1
sbc $00
sta inet_menu_cur_pos+1
sta $03
lda #$00
sta $00
lda inet_menu_cur_pos
sbc $00
sta inet_menu_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
dec inet_menu_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @end
@down:
;;case down
lda #$20
bit jp1_data
beq @a
lda #7
cmp inet_menu_select
beq @end
;;move cursor down.
lda inet_menu_cur_pos
sta $02
lda inet_menu_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
clc
lda #$20
adc inet_menu_cur_pos+1
sta inet_menu_cur_pos+1
sta $03
lda #$00
adc inet_menu_cur_pos
sta inet_menu_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
inc inet_menu_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @end
@a:
;;case a
lda #$01
bit jp1_data
beq @end
lda #7
cmp inet_menu_select
bne :+
;;case return.
jsr main_screen_init
jmp @next_page_done
:
lda inet_menu_select
sta screen_status ;;navigate to next screen.
jsr init_screen
@next_page_done:
;;invalidate jp input for a while.
lda #$00
sta jp_status
@end:
rts
.endproc
.proc inet_bmark_scr_updt
;;;case up
lda #$10
bit jp1_data
beq @down
lda #0
cmp bmark_menu_select
bne :+
jmp @end
:
;;move cursor up.
lda bmark_menu_cur_pos
sta $02
lda bmark_menu_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
sec
lda #$20
sta $00
lda bmark_menu_cur_pos+1
sbc $00
sta bmark_menu_cur_pos+1
sta $03
lda #$00
sta $00
lda bmark_menu_cur_pos
sbc $00
sta bmark_menu_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
dec bmark_menu_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @end
@down:
;;case down
lda #$20
bit jp1_data
beq @a
lda #4
cmp bmark_menu_select
bne :+
jmp @end
:
;;move cursor down.
lda bmark_menu_cur_pos
sta $02
lda bmark_menu_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
clc
lda #$20
adc bmark_menu_cur_pos+1
sta bmark_menu_cur_pos+1
sta $03
lda #$00
adc bmark_menu_cur_pos
sta bmark_menu_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
inc bmark_menu_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @end
@a:
;;case a
lda #$01
bit jp1_data
beq @end
lda #4
cmp bmark_menu_select
bne :+
;;case return
lda #$20
sta $00
lda #$6d
sta $01
lda #$20
sta $02
lda #$79
sta $03
lda #$21
sta $04
lda #$ad
sta $05
lda #$21
sta $06
lda #$b9
sta $07
jsr delete_rect
jsr inet_screen_init
jmp @next_page_done
:
;;case bmark is selected...
;;; sta screen_status ;;navigate to next screen.
;;; jsr init_screen
@next_page_done:
;;invalidate jp input for a while.
lda #$00
sta jp_status
@end:
rts
.endproc
.proc inet_srch_scr_updt
rts
.endproc
.proc inet_dirct_scr_updt
rts
.endproc
.proc game_screen_updt
rts
.endproc
.proc shell_screen_updt
;;;case up
lda #$10
bit jp1_data
beq @down
;;0 - 11 is the top line.
lda #11
cmp kb_select
bcc :+
jmp @kb_end
:
lda #$7f
cmp kb_select
bne :+
jmp @kb_end
:
;;move cursor up.
lda kb_cur_pos
sta $02
lda kb_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
sec
lda #$40
sta $00
lda kb_cur_pos+1
sbc $00
sta kb_cur_pos+1
sta $03
lda #$00
sta $00
lda kb_cur_pos
sbc $00
sta kb_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;update selected index.
lda #12
sta $0
sec
lda kb_select
sbc $0
sta kb_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@down:
;;case down
lda #$20
bit jp1_data
bne :+
jmp @left
:
;;36 - 47 is the bottom line.
lda #35
cmp kb_select
bcs :+
jmp @left
:
;;move cursor down.
lda kb_cur_pos
sta $02
lda kb_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
clc
lda #$40
adc kb_cur_pos+1
sta kb_cur_pos+1
sta $03
lda #$00
adc kb_cur_pos
sta kb_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;update selected index.
lda #12
clc
adc kb_select
sta kb_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@left:
;;case left
lda #$40
bit jp1_data
bne :+
jmp @right
:
;;left most side is 0, 12, 24, 36.
lda #0
cmp kb_select
bne :+
jmp @rtn_btn
:
lda #12
cmp kb_select
bne :+
jmp @rtn_btn
:
lda #24
cmp kb_select
bne :+
jmp @rtn_btn
:
lda #36
cmp kb_select
bne :+
jmp @rtn_btn
:
lda #$7f
cmp kb_select
bne :+
jmp @kb_end
:
;;move cursor left.
lda kb_cur_pos
sta $02
lda kb_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
sec
lda #$2
sta $00
lda kb_cur_pos+1
sbc $00
sta kb_cur_pos+1
sta $03
lda #$00
sta $00
lda kb_cur_pos
sbc $00
sta kb_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
dec kb_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@rtn_btn:
;;move cursor to return button pos.
lda kb_cur_pos
sta $02
lda kb_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
lda #$22
sta $00
sta kb_cur_pos
lda #$a1
sta $03
sta kb_cur_pos+1
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;set selected index.
lda #$7f
sta kb_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@right:
;;case down
lda #$80
bit jp1_data
bne :+
jmp @b
:
;;right most side is 11, 23, 35, 47
lda #11
cmp kb_select
bne :+
jmp @kb_end
:
lda #23
cmp kb_select
bne :+
jmp @kb_end
:
lda #35
cmp kb_select
bne :+
jmp @kb_end
:
lda #47
cmp kb_select
bne :+
jmp @kb_end
:
lda #$7f
cmp kb_select
bne :+
jmp @back_to_kb
:
;;move cursor right.
lda kb_cur_pos
sta $02
lda kb_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
clc
lda #$2
adc kb_cur_pos+1
sta kb_cur_pos+1
sta $03
lda #$00
adc kb_cur_pos
sta kb_cur_pos
sta $02
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;increment selected index.
inc kb_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@back_to_kb:
;;return from back btn.
lda kb_cur_pos
sta $02
lda kb_cur_pos+1
sta $03
lda un_select_cursor
sta $00
lda un_select_cursor+1
sta $01
jsr print_str
lda #$22
sta $00
sta kb_cur_pos
lda #$a4
sta $03
sta kb_cur_pos+1
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;set selected index.
lda #00
sta kb_select
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@b:
;;case b
;;select in the buffer.
lda #$02
bit jp1_data
bne :+
jmp @a
:
lda #60
;;max input text is 60 chars.
cmp in_text_carret
bne :+
jmp @kb_end
:
lda #$7f
cmp kb_select
bne :+
jmp @end_shell
:
lda #36
cmp kb_select
bne :+
jmp @sft_btn
:
lda #35
cmp kb_select
bne :+
jmp @bs_btn
:
clc
;;get selected char in x.
lda kb_sft_status
bne :+
;;case shift off
lda text_kb_matrix
sta $02
lda text_kb_matrix+1
sta $03
jmp @ld_chr
:
;;case shift on
lda text_kb_matrix_s
sta $02
lda text_kb_matrix_s+1
sta $03
@ld_chr:
ldy kb_select
lda ($02), y
tax
;;set buf base index.
ldy in_text_carret
lda in_text_buf_addr
sta $00
lda in_text_buf_addr+1
sta $01
;;set char.
txa
sta ($00), y
iny
;;put carret
lda #$8a
sta ($00), y
iny
;;terminate.
lda #0
sta ($00), y
lda carret_pos
sta $02
lda carret_pos+1
sta $03
jsr print_str
inc in_text_carret
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@end_shell:
;;close all window.
lda #$20
sta $00
sta $01
lda #$20
sta $02
lda #$3e
sta $03
lda #$23
sta $04
lda #$a0
sta $05
lda #$23
sta $06
lda #$be
sta $07
jsr delete_rect
;;back to main screen
jsr main_screen_init
;;invalidate jp input for a while.
lda #$00
sta jp_status
jmp @kb_end
@sft_btn:
lda kb_sft_status
bne @s_on
;;case shift off
lda #$22
sta $02
lda #$a5
sta $03
lda kb_1_s
sta $00
lda kb_1_s+1
sta $01
jsr print_str
lda #$22
sta $02
lda #$e5
sta $03
lda kb_2_s
sta $00
lda kb_2_s+1
sta $01
jsr print_str
lda #$23
sta $02
lda #$25
sta $03
lda kb_3_s
sta $00
lda kb_3_s+1
sta $01
jsr print_str
lda #$23
sta $02
lda #$65
sta $03
lda kb_4_s
sta $00
lda kb_4_s+1
sta $01
jsr print_str
;;set shift on.
lda #1
sta kb_sft_status
lda #$00
sta jp_status
jmp @kb_end
@s_on:
;;case shift on.
lda #$22
sta $02
lda #$a5
sta $03
lda kb_1
sta $00
lda kb_1+1
sta $01
jsr print_str
lda #$22
sta $02
lda #$e5
sta $03
lda kb_2
sta $00
lda kb_2+1
sta $01
jsr print_str
lda #$23
sta $02
lda #$25
sta $03
lda kb_3
sta $00
lda kb_3+1
sta $01
jsr print_str
lda #$23
sta $02
lda #$65
sta $03
lda kb_4
sta $00
lda kb_4+1
sta $01
jsr print_str
;;set shift off
lda #0
sta kb_sft_status
lda #$00
sta jp_status
jmp @kb_end
@bs_btn:
;;backspace.
lda in_text_carret
bne :+
jmp @kb_end
:
dec in_text_carret
ldy in_text_carret
lda in_text_buf_addr
sta $00
lda in_text_buf_addr+1
sta $01
;;put carret
lda #$8a
sta ($00), y
iny
;;erase old char.
lda #' '
sta ($00), y
iny
;;terminate.
lda #0
sta ($00), y
lda carret_pos
sta $02
lda carret_pos+1
sta $03
jsr print_str
lda #$00
sta jp_status
jmp @kb_end
@a:
;;case a..
lda #$01
bit jp1_data
beq @kb_end
;;; no need!! send them all!;;;;;;;;;;;;;;;
;;check if input text is empty.
;;the head char is carret(|), then input is empty.
; lda #$8a
; cmp in_text_buf
; beq @kb_end
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;send input line to i2c...
jsr send_i2c
;;reset carret.
lda #$22
sta $02
sta carret_pos
lda #$41
sta carret_pos+1
sta $03
lda #0
sta in_text_carret
lda in_text_buf_addr
sta $00
lda in_text_buf_addr+1
sta $01
lda #$8a
ldy #0
sta ($00), y
ldx #61
lda #' '
iny
:
sta ($00), y
iny
dex
bne :-
jsr print_str
;;invalidate jp input for a while.
lda #$00
sta jp_status
@kb_end:
;;check i2c input data...
;;check fifo_stat empty bit.
lda fifo_stat
bne :+
jsr print_i2c
:
rts
.endproc
.proc send_i2c
lda jp_status
bne :+
rts
:
;;in_text_carret holds offset from the head.
ldx in_text_carret
ldy #0
lda in_text_buf_addr
sta $00
lda in_text_buf_addr+1
sta $01
:
;;write i2c fifo
lda ($00), y
sta $fff9
iny
dex
bpl :-
rts
.endproc
.macro lda_line_addr_lo addr
;;lda imm
;;0xA9, imm
.byte $A9
.lobytes addr
.endmacro
.macro lda_line_addr_hi addr
;;lda imm
;;0xA9, imm
.byte $A9
.hibytes addr
.endmacro
.proc scroll_next
;;0x00=vram high
;;0x01=vram low
lda #$20
sta $00
lda #$40
sta $01
;;x=lines to copy
ldx #14
@next_line:
;;y=char to copy
ldy #31
lda_line_addr_lo shell_copy_buf
sta $05
lda_line_addr_hi shell_copy_buf
sta $06
lda $2002
;copy from 1 line ahead.
clc
lda #$20
adc $01
pha
bcc @no_pg_bdr1
;;next line is ahead of the boarder.
lda #1
clc
adc $00
sta $2006
pla
sta $2006
jmp :+
@no_pg_bdr1:
lda $00
sta $2006
pla
sta $2006
:
;;vram read first is dummy read.
lda $2007
;;copy vram to tmp buf.
:
lda $2007
sta ($05), y
dey
bpl :-
;;copy tmp buf to earlier line.
lda $2002
lda $00
sta $2006
lda $01
sta $2006
ldy #31
:
lda ($05), y
sta $2007
dey
bpl :-
;;next line.
dex
beq @no_next_line
lda #$20
clc
adc $01
sta $01
bcc @no_pg_bdr2
;case page boarder.
inc $00
@no_pg_bdr2:
jmp @next_line
@no_next_line:
;;clear off the last line.
lda $2002
lda #$22
sta $2006
lda #$02
sta $2006
lda #' '
ldy #27
:
sta $2007
dey
bpl :-
rts
.endproc
.proc shl_disp_move_next
ldx output_pos+1
lda output_pos
cmp #$22
beq @pg3
cmp #$21
beq @pg2
@pg1:
ldy #5 ;;line=6
;;load address of high(line_end_arr1)
lda_line_addr_lo line_end_arr1
sta $05
lda_line_addr_hi line_end_arr1
sta $06
jmp @line_check
@pg2:
ldy #7 ;;line=8
lda_line_addr_lo line_end_arr2
sta $05
lda_line_addr_hi line_end_arr2
sta $06
jmp @line_check
@pg3:
;pg3 end needs scroll up.
lda line_end_arr3
cmp output_pos+1
bne :+
jsr scroll_next
;;last line doesn't move. just cursor pos goes to head.
lda #02
sta output_pos+1
rts
:
@line_check:
:
lda ($05), y
sta $07
cpx $07
beq @line_end1
dey
bpl :-
;;no line/page crossing.
inc output_pos+1
jmp @pg_done
@line_end1:
;;new line.
;;you will need to reset vram.
lda $2002
clc
lda #5
adc output_pos+1
sta output_pos+1
bcc @pg_done
inc output_pos
@pg_done:
rts
.endproc
.proc linefeed
;;if it is last line, scroll_next
lda #$22
cmp output_pos
bne :+
lda #$02
sta output_pos+1
jsr scroll_next
rts
:
;;goto next line.
;;high half byte is odd num, +1x. (left half pos)
;;high half byte is even num, +2x. (right half pos)
lda #$10
and output_pos+1
bne @odd
@evn:
lda #$20
jmp :+
@odd:
lda #$10
:
clc
adc output_pos+1
bcc :+
inc output_pos
:
;;low half byte is x2.
sta $09
lda #$f0
and $09
sta $09
lda #$02
ora $09
sta output_pos+1
rts
.endproc
.proc print_i2c
;;pop i2c char from fifo..
lda $fff9
sta $0
;;check if input is new line char '\n'
lda #$0a
cmp $0
bne :+
jsr linefeed
jmp @new_line_ok
:
;;set cursor pos.
lda output_pos
sta $02
lda output_pos+1
sta $03
jsr print_chr
jsr shl_disp_move_next
@new_line_ok:
;;loop until fifo is empty or display area is full.
lda #$10
and $fff8
beq print_i2c
rts
.endproc
.proc inet_screen_init
;;create box.
lda #$20
sta $00
lda #$41
sta $01
lda #$20
sta $02
lda #$4e
sta $03
lda #$21
sta $04
lda #$61
sta $05
lda #$21
sta $06
lda #$6e
sta $07
jsr create_rect
;;set message.
lda #$20
sta $02
lda #$62
sta $03
lda top_menu_internet
sta $00
lda top_menu_internet+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$83
sta $03
lda inet_menu_bookmark
sta $00
lda inet_menu_bookmark+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$a3
sta $03
lda inet_menu_search
sta $00
lda inet_menu_search+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$c3
sta $03
lda inet_menu_direct
sta $00
lda inet_menu_direct+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$e3
sta $03
lda menu_return
sta $00
lda menu_return+1
sta $01
jsr print_str
lda #$20
sta $02
sta inet_menu_cur_pos
lda #$82
sta $03
sta inet_menu_cur_pos+1
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
lda #4
sta inet_menu_select
lda #1
sta screen_status
rts
.endproc
.proc inet_bmark_scr_init
;;create box.
lda #$20
sta $00
lda #$6d
sta $01
lda #$20
sta $02
lda #$79
sta $03
lda #$21
sta $04
lda #$ad
sta $05
lda #$21
sta $06
lda #$b9
sta $07
jsr create_rect
;;set message.
lda #$20
sta $02
lda #$8f
sta $03
lda bm_msn
sta $00
lda bm_msn+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$af
sta $03
lda bm_abc
sta $00
lda bm_abc+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$cf
sta $03
lda bm_cnn
sta $00
lda bm_cnn+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$ef
sta $03
lda bm_bbc
sta $00
lda bm_bbc+1
sta $01
jsr print_str
lda #$21
sta $02
lda #$0f
sta $03
lda menu_return
sta $00
lda menu_return+1
sta $01
jsr print_str
lda #$20
sta $02
sta bmark_menu_cur_pos
lda #$8e
sta $03
sta bmark_menu_cur_pos+1
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
lda #0
sta bmark_menu_select
lda #4
sta screen_status
rts
.endproc
.proc inet_srch_scr_init
rts
.endproc
.proc inet_dirct_scr_init
rts
.endproc
.proc game_screen_init
rts
.endproc
.proc shell_screen_init
;;create box.
lda #$20
sta $00
lda #$21
sta $01
lda #$20
sta $02
lda #$3e
sta $03
lda #$22
sta $04
lda #$21
sta $05
lda #$22
sta $06
lda #$3e
sta $07
jsr create_rect
;;create box.
lda #$22
sta $00
lda #$83
sta $01
lda #$22
sta $02
lda #$9d
sta $03
lda #$23
sta $04
lda #$83
sta $05
lda #$23
sta $06
lda #$9d
sta $07
jsr create_rect
;;top right back button
lda #$22
sta $02
lda #$a2
sta $03
lda shell_back_btn
sta $00
lda shell_back_btn+1
sta $01
jsr print_str
;;show keyboard first row.
lda #$22
sta $02
lda #$a5
sta $03
lda kb_1
sta $00
lda kb_1+1
sta $01
jsr print_str
lda #$22
sta $02
lda #$e5
sta $03
lda kb_2
sta $00
lda kb_2+1
sta $01
jsr print_str
lda #$23
sta $02
lda #$25
sta $03
lda kb_3
sta $00
lda kb_3+1
sta $01
jsr print_str
lda #$23
sta $02
lda #$65
sta $03
lda kb_4
sta $00
lda kb_4+1
sta $01
jsr print_str
;;draw blank text w/ carret.
lda #$22
sta $02
sta carret_pos
lda #$41
sta carret_pos+1
sta $03
lda #0
sta in_text_carret
lda in_text_buf_addr
sta $00
lda in_text_buf_addr+1
sta $01
lda #$8a
ldy #0
sta ($00), y
ldx #61
lda #' '
iny
:
sta ($00), y
iny
dex
bne :-
jsr print_str
lda #$22
sta $02
sta kb_cur_pos
lda #$a4
sta $03
sta kb_cur_pos+1
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
lda #3
sta screen_status
lda #0
sta kb_sft_status
rts
.endproc
.proc main_screen_init
;;create box.
lda #$20
sta $00
lda #$41
sta $01
lda #$20
sta $02
lda #$4e
sta $03
lda #$21
sta $04
lda #$61
sta $05
lda #$21
sta $06
lda #$6e
sta $07
jsr create_rect
;;set message.
lda #$20
sta $02
lda #$62
sta $03
lda top_menu1
sta $00
lda top_menu1+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$83
sta $03
lda top_menu_internet
sta $00
lda top_menu_internet+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$a3
sta $03
lda top_menu_game
sta $00
lda top_menu_game+1
sta $01
jsr print_str
lda #$20
sta $02
lda #$c3
sta $03
lda top_menu_shell
sta $00
lda top_menu_shell+1
sta $01
jsr print_str
;;show build ver.
lda #$23
sta $02
lda #$42
sta $03
lda build_msg
sta $00
lda build_msg+1
sta $01
jsr print_str
lda #$20
sta $02
sta top_menu_cur_pos
lda #$82
sta $03
sta top_menu_cur_pos+1
lda select_cursor
sta $00
lda select_cursor+1
sta $01
jsr print_str
;;set screen status
lda #1
sta top_menu_select
lda #0
sta screen_status
;;ready to input.
lda #$01
sta jp_status
rts
.endproc
;;;param $00, $01 = top left.
;;;param $02, $03 = top right
;;;param $04, $05 = bottom left.
;;;param $06, $07 = bottom right
.proc delete_rect
;;calc width
sec
lda $03
sbc $01
sta $08 ;;$08=width
;;get y index1
lda $01
lsr
lsr
lsr
lsr
lsr
sta $0a ;;$0a=top pos in y axis (bottom 3bit.)
lda #$1f
and $00 ;;$0b=top pos (top 5bit.)
asl
asl
asl
ora $0a ;;$09=top pos
sta $09
;;get y index2
lda $05
lsr
lsr
lsr
lsr
lsr
sta $0a ;;$0a=bottom pos in y axis (bottom 3bit.)
lda #$1f
and $04 ;;$0b=bottom pos (top 5bit.)
asl
asl
asl
ora $0a ;;$0a=bottom pos
sta $0a
sec
sbc $09
sta $09 ;;$09=hight
ldy $09
@y_loop:
lda $00
sta $2006
lda $01
sta $2006
ldx $08
lda #' '
:
sta $2007
dex
bpl :-
lda #$20
clc
adc $01
bcc :+
inc $00
:
sta $01
dey
bpl @y_loop
rts
.endproc
;;;param $00, $01 = top left.
;;;param $02, $03 = top right
;;;param $04, $05 = bottom left.
;;;param $06, $07 = bottom right
.proc create_rect
;leftmost @ 2021.
lda $00
sta $2006
lda $01
sta $2006
lda #$82
sta $2007
;top right
lda $02
sta $2006
lda $03
sta $2006
lda #$83
sta $2007
;left bottom
lda $04
sta $2006
lda $05
sta $2006
lda #$84
sta $2007
;right bottom
lda $06
sta $2006
lda $07
sta $2006
lda #$85
sta $2007
;;calc width
sec
lda $03
sbc $01
sta $08 ;;$08=width
dec $08
dec $08
;;get y index1
lda $01
lsr
lsr
lsr
lsr
lsr
sta $0a ;;$0a=top pos in y axis (bottom 3bit.)
lda #$1f
and $00 ;;$0b=top pos (top 5bit.)
asl
asl
asl
ora $0a ;;$09=top pos
sta $09
;;get y index2
lda $05
lsr
lsr
lsr
lsr
lsr
sta $0a ;;$0a=bottom pos in y axis (bottom 3bit.)
lda #$1f
and $04 ;;$0b=bottom pos (top 5bit.)
asl
asl
asl
ora $0a ;;$0a=bottom pos
sta $0a
sec
sbc $09
sta $09 ;;$09=hight
dec $09
dec $09
;;horizontal line.
lda $00
sta $2006
clc
lda #$01
adc $01
sta $2006
ldx $08
lda #$80
:
sta $2007
dex
bpl :-
lda $04
sta $2006
lda #$01
adc $05
sta $2006
ldx $08
lda #$80
:
sta $2007
dex
bpl :-
;;incretemt 32 bit.
lda #$04
ora ppu_ctl
sta ppu_ctl
sta $2000
;;vertical line.
clc
lda #32
adc $01
sta $0a
lda #0
adc $00
sta $2006
lda $0a
sta $2006
ldx $09
lda #$81
:
sta $2007
dex
bpl :-
;;
clc
lda #32
adc $03
sta $0a
lda #0
adc $02
sta $2006
lda $0a
sta $2006
ldx $09
lda #$81
:
sta $2007
dex
bpl :-
lda #$fb
and ppu_ctl
sta ppu_ctl
sta $2000
;;fill blank in the box.
lda #33
adc $01
sta $0c
lda #0
adc $00
sta $0b
;;set left most point @0b, 0c.
ldy $09
@y_loop:
lda $0b
sta $2006
lda $0c
sta $2006
ldx $08
lda #' '
:
sta $2007
dex
bpl :-
lda #$20
clc
adc $0c
bcc :+
inc $0b
:
sta $0c
dey
bpl @y_loop
rts
.endproc
.proc char_test
lda ad_start_msg
sta $00
lda ad_start_msg+1
sta $01
jsr print_ln
jsr print_ln
jsr print_ln
lda ad_cht_chk_msg1
sta $00
lda ad_cht_chk_msg1+1
sta $01
jsr print_ln
lda ad_cht_chk_msg2
sta $00
lda ad_cht_chk_msg2+1
sta $01
jsr print_ln
lda ad_cht_chk_msg3
sta $00
lda ad_cht_chk_msg3+1
sta $01
jsr print_ln
rts
.endproc
;;;param $00 = char to display.
;;;param $02, $03 = vram pos
;;;print character at the pos specified in the parameter.
.proc print_chr
lda $02
sta $2006
lda $03
sta $2006
lda $00
sta $2007
rts
.endproc
;;;param $00, $01 = msg addr.
;;;param $02, $03 = vram pos
;;;print string at the pos specified in the parameter.
.proc print_str
lda $02
sta $2006
lda $03
sta $2006
ldy #$00
@msg_loop:
lda ($00), y
beq @print_done
sta $2007
iny
jmp @msg_loop
@print_done:
rts
.endproc
;;;param $00, $01 = msg addr.
;;;print_ln display message.
;;;start position is the bottom of the screen.
.proc print_ln
lda vram_current
sta $2006
lda vram_current + 1
sta $2006
ldy #$00
@msg_loop:
lda ($00), y
sta $2007
beq @print_done
iny
jmp @msg_loop
@print_done:
;;clear remaining space.
@clr_line:
tya
and #$1f
cmp #$1f
beq @clr_done
lda #$00
sta $2007
iny
jmp @clr_line
@clr_done:
;;renew vram pos
lda vram_current + 1
sty vram_current + 1
adc vram_current + 1
sta vram_current + 1
tax ;; x = new vram_l
lda vram_current
bcc @no_carry
clc
adc #01 ;; a = new vram_h
sta vram_current
@no_carry:
cmp #$23
bne @vpos_done
txa
cmp #$c0
bne @vpos_done
;;;if vram pos = 23c0. reset pos.
lda #$20
sta vram_current
lda #$00
sta vram_current + 1
@vpos_done:
rts
.endproc
;;init menu items.
.proc init_menu
lda #0
sta screen_status
lda #1
sta top_menu_select
lda #4
sta inet_menu_select
lda #0
sta bmark_menu_select
rts
.endproc
;;ppu initialize
.proc init_ppu
;;init vram...
;;2000 - 3000 (16 pages.)
ldx #16
lda #$20
sta $0
@xloop:
lda $0
sta $2006
lda #$00
sta $2006
lda #' '
ldy #0
:
sta $2007
iny
beq :+
jmp :-
:
inc $0
dex
bne @xloop
;;init attr.
lda #$23
sta $2006
lda #$c0
sta $2006
lda #0
ldy #0
:
sta $2007
iny
beq :+
jmp :-
:
;;init sprite.
lda #0
sta $2003
ldy #0
:
sta $2004
iny
bne :-
;;vram pos start from the top left.
lda #$20
sta vram_current
lda #$00
sta vram_current + 1
;;init shell i2c display pos.
lda #$20
sta output_pos
lda #$42
sta output_pos+1
;ppu register initialize.
lda #$00
sta $2000
sta ppu_ctl
sta $2001
sta ppu_mask
;;load palette.
lda #$3f
sta $2006
lda #$00
sta $2006
ldx #$00
ldy #$20
@copypal:
lda @palettes, x
sta $2007
inx
dey
bne @copypal
rts
@palettes:
;;;bg palette
.byte $0f, $00, $10, $20
.byte $0f, $04, $14, $24
.byte $0f, $08, $18, $28
.byte $0f, $0c, $1c, $2c
;;;spr palette
.byte $0f, $00, $10, $20
.byte $0f, $06, $16, $26
.byte $0f, $08, $18, $28
.byte $0f, $0a, $1a, $2a
.endproc
;;;;string datas
ad_start_msg:
.addr :+
:
.byte "test start..."
.byte $00
ad_cht_chk_msg1:
.addr :+
:
.byte " !"
.byte $22 ;;;" char.
.byte "#$%&'()*+,-./0123456789:;<=>?"
.byte $00
ad_cht_chk_msg2:
.addr :+
:
.byte "@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_"
.byte $00
ad_cht_chk_msg3:
.addr :+
:
.byte "`abcdefghijklmnopqrstuvwxyz{|}~"
.byte $00
top_menu1:
.addr :+
:
.byte "Command"
.byte $00
top_menu_internet:
.addr :+
:
.byte "Internet"
.byte $00
top_menu_game:
.addr :+
:
.byte "Game"
.byte $00
top_menu_shell:
.addr :+
:
.byte "Shell"
.byte $00
select_cursor:
.addr :+
:
.byte $8b
.byte $00
un_select_cursor:
.addr :+
:
.byte " "
.byte $00
inet_menu_bookmark:
.addr :+
:
.byte "Bookmark"
.byte $00
inet_menu_search:
.addr :+
:
.byte "Search"
.byte $00
inet_menu_direct:
.addr :+
:
.byte "Direct"
.byte $00
inet_menu_history:
.addr :+
:
.byte "History"
.byte $00
menu_return:
.addr :+
:
.byte "Return"
.byte $00
bm_msn:
.addr :+
:
.byte "MSN"
.byte $00
bm_abc:
.addr :+
:
.byte "ABC"
.byte $00
bm_cnn:
.addr :+
:
.byte "CNN"
.byte $00
bm_bbc:
.addr :+
:
.byte "BBC"
.byte $00
kb_1:
.addr :+
:
.byte "1 2 3 4 5 6 7 8 9 0 - ="
.byte $00
kb_2:
.addr :+
:
.byte "q w e r t y u i o p [ ]"
.byte $00
kb_3:
.addr :+
:
.byte "a s d f g h j k l ; ' "
.byte $88
.byte $00
kb_4:
.addr :+
:
.byte $87
.byte " z x c v b n m , . / "
.byte $89
.byte $00
kb_1_s:
.addr :+
:
.byte "! @ # $ % ^ & * ( ) _ +"
.byte $00
kb_2_s:
.addr :+
:
.byte "Q W E R T Y U I O P { }"
.byte $00
kb_3_s:
.addr :+
:
.byte "A S D F G H J K L : "
.byte '"'
.byte ' '
.byte $88
.byte $00
kb_4_s:
.addr :+
:
.byte $86
.byte " Z X C V B N M < > ? "
.byte $89
.byte $00
in_text_buf_addr:
.addr in_text_buf
shell_back_btn:
.addr :+
:
.byte $8c
.byte $00
text_kb_matrix:
.addr :+
:
.byte "1234567890-="
.byte "qwertyuiop[]"
.byte "asdfghjkl;' "
.byte " zxcvbnm,./ "
text_kb_matrix_s:
.addr :+
:
.byte "!@#$%^&*()_+"
.byte "QWERTYUIOP{}"
.byte "ASDFGHJKL:"
.byte '"'
.byte $0
.byte " ZXCVBNM<>? "
;;page 2042 - 20fd
line_end_arr1:
.byte $5d, $7d, $9d, $bd, $dd, $fd
;;page 2102 - 21fd
line_end_arr2:
.byte $1d, $3d, $5d, $7d, $9d, $bd, $dd, $fd
;;page 2202 - 221d
line_end_arr3:
.byte $1d
;;;;r/w global variables.
.segment "BSS"
vram_current:
.byte $00
.byte $00
;;screen status
; 0: top page
; 1: internet top page
; 2: game top page
; 3: shell top page
; 4: bookmakr page
; 5: search page
; 6: direct page
screen_status:
.byte $00
;1 - 3
top_menu_select:
.byte $00
;4 - 6
inet_menu_select:
.byte $00
;0 - 4
bmark_menu_select:
.byte $00
; 0 - 11
;12 - 23
;24 - 35
;36 - 47
kb_select:
.byte $00
top_menu_cur_pos:
.byte $00
.byte $00
inet_menu_cur_pos:
.byte $00
.byte $00
bmark_menu_cur_pos:
.byte $00
.byte $00
kb_cur_pos:
.byte $00
.byte $00
carret_pos:
.byte $00
.byte $00
;;in_text_carret is the offset in from the text buffer top.
in_text_carret:
.byte $00
;;input text buffer is 2 lines (60 char + null char.)
in_text_buf:
.byte $8a ;; 0x8a is carret chr code.
.repeat 63
.byte $00
.endrepeat
output_pos:
.byte $00
.byte $00
;;input ready: 1
;;input suspend: 0
jp_status:
.byte $00
kb_sft_status:
.byte $00
;;scrolling function uses this area.
;;1 line is 32 chars.
shell_copy_buf:
.repeat 32
.byte $00
.endrepeat
| astoria-d/super-duper-nes | duper_rom/ppu.asm | Assembly | apache-2.0 | 39,370 |
# crtn.asm for ELF
# Copyright (C) 1992, 1999 Free Software Foundation, Inc.
# Written By David Vinayak Henkel-Wallace, June 1992
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 2, or (at your option) any
# later version.
#
# In addition to the permissions in the GNU General Public License, the
# Free Software Foundation gives you unlimited permission to link the
# compiled version of this file with other programs, and to distribute
# those programs without any restriction coming from the use of this
# file. (The General Public License restrictions do apply in other
# respects; for example, they cover modification of the file, and
# distribution when not linked into another program.)
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, 51 Franklin Street, Fifth Floor,
# Boston, MA 02110-1301, USA.
#
# As a special exception, if you link this library with files
# compiled with GCC to produce an executable, this does not cause
# the resulting executable to be covered by the GNU General Public License.
# This exception does not however invalidate any other reasons why
# the executable file might be covered by the GNU General Public License.
#
# This file just makes sure that the .fini and .init sections do in
# fact return. Users may put any desired instructions in those sections.
# This file is the last thing linked into any executable.
.file "crtn.s"
.section ".init"
.align 4
leave
ld @r15+,rp
ret
.section ".fini"
.align 4
leave
ld @r15+,rp
ret
# Th-th-th-that is all folks!
| avaitla/Haskell-to-C---Bridge | gccxml/GCC/gcc/config/fr30/crtn.asm | Assembly | bsd-3-clause | 2,187 |
;Este es un comentario, se le antecede un punto y coma
list p=18f4550 ;Modelo del microcontrolador
#include <p18f4550.inc> ;Llamada a la librería de nombre de los registros
;Directivas de preprocesador o bits de configuración
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT oscillator (XT))
CONFIG PWRT = ON ; Power-up Timer Enable bit (PWRT enabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
org 0x0000 ;vector de reset
goto init_conf
org 0x0020 ;zona de programa de usuario
init_conf: movlw 0x80
movwf TRISD ;RD(6:0) como salidas - a los segmentos
movlw 0xF0
movwf TRISB ;RB(3:0) como salidas - a los habilitadores
clrf LATB ;Cond. inicial de los habilitadores
loop: movlw 0x77 ; letra A
movwf LATD
bsf LATB, 0 ; habilitamos digito 0
bcf LATB, 0 ;deshabilitamos digito 0
movlw 0x37 ; letra M
movwf LATD
bsf LATB, 1 ; habilitamos digito 1
bcf LATB, 1 ;deshabilitamos digito 1
movlw 0x5C ; letra O
movwf LATD
bsf LATB, 2 ; habilitamos digito 2
bcf LATB, 2 ;deshabilitamos digito 2
movlw 0x50 ; letra R
movwf LATD
bsf LATB, 3 ; habilitamos digito 3
bcf LATB, 3 ;deshabilitamos digito 3
goto loop
end | tocache/picomones | UPC Microcontroladores 2021-1/Semana 07/20211_ls5a_cuadrada_tmr0_1k.X/20211_ls51_mux7s_b.X/maincode_1.asm | Assembly | cc0-1.0 | 2,194 |
.file "example.cpp"
.arch msp430f169
.cpu 430
.mpy none
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.p2align 1,0
.global square(int)
.type square(int),@function
/***********************
* Function `square(int)'
***********************/
square(int):
.LFB0:
.LM1:
push r10
.LCFI0:
push r4
.LCFI1:
mov r1, r4
.LCFI2:
add #4, r4
.LCFI3:
sub #2, r1
.LCFI4:
mov r15, -6(r4)
.LM2:
mov -6(r4), r10
mov -6(r4), r12
call #__mulhi3
mov r14, r15
.LM3:
add #2, r1
pop r4
pop r10
ret
.LFE0:
.Lfe1:
.size square(int),.Lfe1-square(int)
;; End of function
.section .debug_frame,"",@progbits
.Lframe0:
.4byte .LECIE0-.LSCIE0
.LSCIE0:
.4byte 0xffffffff
.byte 0x1
.string ""
.uleb128 0x1
.sleb128 -2
.byte 0x0
.byte 0xc
.uleb128 0x1
.uleb128 0x2
.byte 0x80
.uleb128 0x1
.p2align 1,0
.LECIE0:
.LSFDE0:
.4byte .LEFDE0-.LASFDE0
.LASFDE0:
.4byte .Lframe0
.2byte .LFB0
.2byte .LFE0-.LFB0
.byte 0x4
.4byte .LCFI0-.LFB0
.byte 0xe
.uleb128 0x4
.byte 0x4
.4byte .LCFI1-.LCFI0
.byte 0xe
.uleb128 0x6
.byte 0x84
.uleb128 0x3
.byte 0x8a
.uleb128 0x2
.byte 0x4
.4byte .LCFI2-.LCFI1
.byte 0xd
.uleb128 0x4
.byte 0x4
.4byte .LCFI3-.LCFI2
.byte 0xe
.uleb128 0x2
.p2align 1,0
.LEFDE0:
.text
.Letext0:
.section .debug_loc,"",@progbits
.Ldebug_loc0:
.LLST0:
.2byte .LFB0-.Ltext0
.2byte .LCFI0-.Ltext0
.2byte 0x2
.byte 0x71
.sleb128 2
.2byte .LCFI0-.Ltext0
.2byte .LCFI1-.Ltext0
.2byte 0x2
.byte 0x71
.sleb128 4
.2byte .LCFI1-.Ltext0
.2byte .LCFI2-.Ltext0
.2byte 0x2
.byte 0x71
.sleb128 6
.2byte .LCFI2-.Ltext0
.2byte .LCFI3-.Ltext0
.2byte 0x2
.byte 0x74
.sleb128 6
.2byte .LCFI3-.Ltext0
.2byte .LFE0-.Ltext0
.2byte 0x2
.byte 0x74
.sleb128 2
.2byte 0x0
.2byte 0x0
.section .debug_info
.4byte 0x4c
.2byte 0x2
.4byte .Ldebug_abbrev0
.byte 0x2
.uleb128 0x1
.4byte .LASF0
.byte 0x4
.4byte .LASF1
.2byte .Ltext0
.2byte .Letext0
.4byte .Ldebug_line0
.uleb128 0x2
.byte 0x1
.4byte .LASF2
.byte 0x1
.byte 0x2
.4byte .LASF3
.4byte 0x48
.2byte .LFB0
.2byte .LFE0
.4byte .LLST0
.4byte 0x48
.uleb128 0x3
.string "num"
.byte 0x1
.byte 0x2
.4byte 0x48
.byte 0x2
.byte 0x91
.sleb128 0
.byte 0x0
.uleb128 0x4
.byte 0x2
.byte 0x5
.string "int"
.byte 0x0
.section .debug_abbrev
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x10
.uleb128 0x6
.byte 0x0
.byte 0x0
.uleb128 0x2
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x2007
.uleb128 0xe
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0x6
.uleb128 0x1
.uleb128 0x13
.byte 0x0
.byte 0x0
.uleb128 0x3
.uleb128 0x5
.byte 0x0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0xa
.byte 0x0
.byte 0x0
.uleb128 0x4
.uleb128 0x24
.byte 0x0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0x0
.byte 0x0
.byte 0x0
.section .debug_pubnames,"",@progbits
.4byte 0x19
.2byte 0x2
.4byte .Ldebug_info0
.4byte 0x50
.4byte 0x1d
.string "square"
.4byte 0x0
.section .debug_aranges,"",@progbits
.4byte 0x10
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x2
.byte 0x0
.2byte .Ltext0
.2byte .Letext0-.Ltext0
.2byte 0x0
.2byte 0x0
.section .debug_line
.4byte .LELT0-.LSLT0
.LSLT0:
.2byte 0x2
.4byte .LELTP0-.LASLTP0
.LASLTP0:
.byte 0x1
.byte 0x1
.byte 0xf6
.byte 0xf5
.byte 0xa
.byte 0x0
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x1
.byte 0x0
.byte 0x0
.byte 0x0
.byte 0x1
.ascii "/tmp/compiler-explorer-compiler118016-56-1e03ruw.ddj4"
.byte 0
.byte 0x0
.string "example.cpp"
.uleb128 0x1
.uleb128 0x0
.uleb128 0x0
.byte 0x0
.LELTP0:
.byte 0x0
.uleb128 0x3
.byte 0x2
.2byte .LM1
.byte 0x15
.byte 0x0
.uleb128 0x3
.byte 0x2
.2byte .LM2
.byte 0x15
.byte 0x0
.uleb128 0x3
.byte 0x2
.2byte .LM3
.byte 0x15
.byte 0x0
.uleb128 0x3
.byte 0x2
.2byte .Letext0
.byte 0x0
.uleb128 0x1
.byte 0x1
.LELT0:
.section .debug_str,"MS",@progbits,1
.LASF0:
.string "GNU C++ 4.5.3"
.LASF1:
.ascii "/"
.string "tmp/compiler-explorer-compiler118016-56-1e03ruw.ddj4/example.cpp"
.LASF3:
.string "square(int)"
.LASF2:
.string "square" | mattgodbolt/gcc-explorer | test/filters-cases/bug-348.asm | Assembly | bsd-2-clause | 6,825 |
;******************************************************************************
;* VP8 MMXEXT optimizations
;* Copyright (c) 2010 Ronald S. Bultje <rsbultje@gmail.com>
;* Copyright (c) 2010 Fiona Glaser <fiona@x264.com>
;*
;* This file is part of FFmpeg.
;*
;* FFmpeg is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* FFmpeg is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with FFmpeg; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
%include "libavutil/x86/x86util.asm"
SECTION_RODATA
fourtap_filter_hw_m: times 4 dw -6, 123
times 4 dw 12, -1
times 4 dw -9, 93
times 4 dw 50, -6
times 4 dw -6, 50
times 4 dw 93, -9
times 4 dw -1, 12
times 4 dw 123, -6
sixtap_filter_hw_m: times 4 dw 2, -11
times 4 dw 108, 36
times 4 dw -8, 1
times 4 dw 3, -16
times 4 dw 77, 77
times 4 dw -16, 3
times 4 dw 1, -8
times 4 dw 36, 108
times 4 dw -11, 2
fourtap_filter_hb_m: times 8 db -6, 123
times 8 db 12, -1
times 8 db -9, 93
times 8 db 50, -6
times 8 db -6, 50
times 8 db 93, -9
times 8 db -1, 12
times 8 db 123, -6
sixtap_filter_hb_m: times 8 db 2, 1
times 8 db -11, 108
times 8 db 36, -8
times 8 db 3, 3
times 8 db -16, 77
times 8 db 77, -16
times 8 db 1, 2
times 8 db -8, 36
times 8 db 108, -11
fourtap_filter_v_m: times 8 dw -6
times 8 dw 123
times 8 dw 12
times 8 dw -1
times 8 dw -9
times 8 dw 93
times 8 dw 50
times 8 dw -6
times 8 dw -6
times 8 dw 50
times 8 dw 93
times 8 dw -9
times 8 dw -1
times 8 dw 12
times 8 dw 123
times 8 dw -6
sixtap_filter_v_m: times 8 dw 2
times 8 dw -11
times 8 dw 108
times 8 dw 36
times 8 dw -8
times 8 dw 1
times 8 dw 3
times 8 dw -16
times 8 dw 77
times 8 dw 77
times 8 dw -16
times 8 dw 3
times 8 dw 1
times 8 dw -8
times 8 dw 36
times 8 dw 108
times 8 dw -11
times 8 dw 2
bilinear_filter_vw_m: times 8 dw 1
times 8 dw 2
times 8 dw 3
times 8 dw 4
times 8 dw 5
times 8 dw 6
times 8 dw 7
bilinear_filter_vb_m: times 8 db 7, 1
times 8 db 6, 2
times 8 db 5, 3
times 8 db 4, 4
times 8 db 3, 5
times 8 db 2, 6
times 8 db 1, 7
%ifdef PIC
%define fourtap_filter_hw picregq
%define sixtap_filter_hw picregq
%define fourtap_filter_hb picregq
%define sixtap_filter_hb picregq
%define fourtap_filter_v picregq
%define sixtap_filter_v picregq
%define bilinear_filter_vw picregq
%define bilinear_filter_vb picregq
%define npicregs 1
%else
%define fourtap_filter_hw fourtap_filter_hw_m
%define sixtap_filter_hw sixtap_filter_hw_m
%define fourtap_filter_hb fourtap_filter_hb_m
%define sixtap_filter_hb sixtap_filter_hb_m
%define fourtap_filter_v fourtap_filter_v_m
%define sixtap_filter_v sixtap_filter_v_m
%define bilinear_filter_vw bilinear_filter_vw_m
%define bilinear_filter_vb bilinear_filter_vb_m
%define npicregs 0
%endif
filter_h2_shuf: db 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8
filter_h4_shuf: db 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10
filter_h6_shuf1: db 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7, 12
filter_h6_shuf2: db 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9
filter_h6_shuf3: db 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11
pw_256: times 8 dw 256
pw_20091: times 4 dw 20091
pw_17734: times 4 dw 17734
cextern pw_3
cextern pw_4
cextern pw_64
SECTION .text
;-------------------------------------------------------------------------------
; subpel MC functions:
;
; void ff_put_vp8_epel<size>_h<htap>v<vtap>_<opt>(uint8_t *dst, int deststride,
; uint8_t *src, int srcstride,
; int height, int mx, int my);
;-------------------------------------------------------------------------------
%macro FILTER_SSSE3 1
cglobal put_vp8_epel%1_h6, 6, 6 + npicregs, 8, dst, dststride, src, srcstride, height, mx, picreg
lea mxd, [mxq*3]
mova m3, [filter_h6_shuf2]
mova m4, [filter_h6_shuf3]
%ifdef PIC
lea picregq, [sixtap_filter_hb_m]
%endif
mova m5, [sixtap_filter_hb+mxq*8-48] ; set up 6tap filter in bytes
mova m6, [sixtap_filter_hb+mxq*8-32]
mova m7, [sixtap_filter_hb+mxq*8-16]
.nextrow:
movu m0, [srcq-2]
mova m1, m0
mova m2, m0
%if mmsize == 8
; For epel4, we need 9 bytes, but only 8 get loaded; to compensate, do the
; shuffle with a memory operand
punpcklbw m0, [srcq+3]
%else
pshufb m0, [filter_h6_shuf1]
%endif
pshufb m1, m3
pshufb m2, m4
pmaddubsw m0, m5
pmaddubsw m1, m6
pmaddubsw m2, m7
paddsw m0, m1
paddsw m0, m2
pmulhrsw m0, [pw_256]
packuswb m0, m0
movh [dstq], m0 ; store
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
cglobal put_vp8_epel%1_h4, 6, 6 + npicregs, 7, dst, dststride, src, srcstride, height, mx, picreg
shl mxd, 4
mova m2, [pw_256]
mova m3, [filter_h2_shuf]
mova m4, [filter_h4_shuf]
%ifdef PIC
lea picregq, [fourtap_filter_hb_m]
%endif
mova m5, [fourtap_filter_hb+mxq-16] ; set up 4tap filter in bytes
mova m6, [fourtap_filter_hb+mxq]
.nextrow:
movu m0, [srcq-1]
mova m1, m0
pshufb m0, m3
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m6
paddsw m0, m1
pmulhrsw m0, m2
packuswb m0, m0
movh [dstq], m0 ; store
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
cglobal put_vp8_epel%1_v4, 7, 7, 8, dst, dststride, src, srcstride, height, picreg, my
shl myd, 4
%ifdef PIC
lea picregq, [fourtap_filter_hb_m]
%endif
mova m5, [fourtap_filter_hb+myq-16]
mova m6, [fourtap_filter_hb+myq]
mova m7, [pw_256]
; read 3 lines
sub srcq, srcstrideq
movh m0, [srcq]
movh m1, [srcq+ srcstrideq]
movh m2, [srcq+2*srcstrideq]
add srcq, srcstrideq
.nextrow:
movh m3, [srcq+2*srcstrideq] ; read new row
mova m4, m0
mova m0, m1
punpcklbw m4, m1
mova m1, m2
punpcklbw m2, m3
pmaddubsw m4, m5
pmaddubsw m2, m6
paddsw m4, m2
mova m2, m3
pmulhrsw m4, m7
packuswb m4, m4
movh [dstq], m4
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
cglobal put_vp8_epel%1_v6, 7, 7, 8, dst, dststride, src, srcstride, height, picreg, my
lea myd, [myq*3]
%ifdef PIC
lea picregq, [sixtap_filter_hb_m]
%endif
lea myq, [sixtap_filter_hb+myq*8]
; read 5 lines
sub srcq, srcstrideq
sub srcq, srcstrideq
movh m0, [srcq]
movh m1, [srcq+srcstrideq]
movh m2, [srcq+srcstrideq*2]
lea srcq, [srcq+srcstrideq*2]
add srcq, srcstrideq
movh m3, [srcq]
movh m4, [srcq+srcstrideq]
.nextrow:
movh m5, [srcq+2*srcstrideq] ; read new row
mova m6, m0
punpcklbw m6, m5
mova m0, m1
punpcklbw m1, m2
mova m7, m3
punpcklbw m7, m4
pmaddubsw m6, [myq-48]
pmaddubsw m1, [myq-32]
pmaddubsw m7, [myq-16]
paddsw m6, m1
paddsw m6, m7
mova m1, m2
mova m2, m3
pmulhrsw m6, [pw_256]
mova m3, m4
packuswb m6, m6
mova m4, m5
movh [dstq], m6
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
%endmacro
INIT_MMX ssse3
FILTER_SSSE3 4
INIT_XMM ssse3
FILTER_SSSE3 8
; 4x4 block, H-only 4-tap filter
INIT_MMX mmxext
cglobal put_vp8_epel4_h4, 6, 6 + npicregs, 0, dst, dststride, src, srcstride, height, mx, picreg
shl mxd, 4
%ifdef PIC
lea picregq, [fourtap_filter_hw_m]
%endif
movq mm4, [fourtap_filter_hw+mxq-16] ; set up 4tap filter in words
movq mm5, [fourtap_filter_hw+mxq]
movq mm7, [pw_64]
pxor mm6, mm6
.nextrow:
movq mm1, [srcq-1] ; (ABCDEFGH) load 8 horizontal pixels
; first set of 2 pixels
movq mm2, mm1 ; byte ABCD..
punpcklbw mm1, mm6 ; byte->word ABCD
pshufw mm0, mm2, 9 ; byte CDEF..
punpcklbw mm0, mm6 ; byte->word CDEF
pshufw mm3, mm1, 0x94 ; word ABBC
pshufw mm1, mm0, 0x94 ; word CDDE
pmaddwd mm3, mm4 ; multiply 2px with F0/F1
movq mm0, mm1 ; backup for second set of pixels
pmaddwd mm1, mm5 ; multiply 2px with F2/F3
paddd mm3, mm1 ; finish 1st 2px
; second set of 2 pixels, use backup of above
punpckhbw mm2, mm6 ; byte->word EFGH
pmaddwd mm0, mm4 ; multiply backed up 2px with F0/F1
pshufw mm1, mm2, 0x94 ; word EFFG
pmaddwd mm1, mm5 ; multiply 2px with F2/F3
paddd mm0, mm1 ; finish 2nd 2px
; merge two sets of 2 pixels into one set of 4, round/clip/store
packssdw mm3, mm0 ; merge dword->word (4px)
paddsw mm3, mm7 ; rounding
psraw mm3, 7
packuswb mm3, mm6 ; clip and word->bytes
movd [dstq], mm3 ; store
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
; 4x4 block, H-only 6-tap filter
INIT_MMX mmxext
cglobal put_vp8_epel4_h6, 6, 6 + npicregs, 0, dst, dststride, src, srcstride, height, mx, picreg
lea mxd, [mxq*3]
%ifdef PIC
lea picregq, [sixtap_filter_hw_m]
%endif
movq mm4, [sixtap_filter_hw+mxq*8-48] ; set up 4tap filter in words
movq mm5, [sixtap_filter_hw+mxq*8-32]
movq mm6, [sixtap_filter_hw+mxq*8-16]
movq mm7, [pw_64]
pxor mm3, mm3
.nextrow:
movq mm1, [srcq-2] ; (ABCDEFGH) load 8 horizontal pixels
; first set of 2 pixels
movq mm2, mm1 ; byte ABCD..
punpcklbw mm1, mm3 ; byte->word ABCD
pshufw mm0, mm2, 0x9 ; byte CDEF..
punpckhbw mm2, mm3 ; byte->word EFGH
punpcklbw mm0, mm3 ; byte->word CDEF
pshufw mm1, mm1, 0x94 ; word ABBC
pshufw mm2, mm2, 0x94 ; word EFFG
pmaddwd mm1, mm4 ; multiply 2px with F0/F1
pshufw mm3, mm0, 0x94 ; word CDDE
movq mm0, mm3 ; backup for second set of pixels
pmaddwd mm3, mm5 ; multiply 2px with F2/F3
paddd mm1, mm3 ; add to 1st 2px cache
movq mm3, mm2 ; backup for second set of pixels
pmaddwd mm2, mm6 ; multiply 2px with F4/F5
paddd mm1, mm2 ; finish 1st 2px
; second set of 2 pixels, use backup of above
movd mm2, [srcq+3] ; byte FGHI (prevent overreads)
pmaddwd mm0, mm4 ; multiply 1st backed up 2px with F0/F1
pmaddwd mm3, mm5 ; multiply 2nd backed up 2px with F2/F3
paddd mm0, mm3 ; add to 2nd 2px cache
pxor mm3, mm3
punpcklbw mm2, mm3 ; byte->word FGHI
pshufw mm2, mm2, 0xE9 ; word GHHI
pmaddwd mm2, mm6 ; multiply 2px with F4/F5
paddd mm0, mm2 ; finish 2nd 2px
; merge two sets of 2 pixels into one set of 4, round/clip/store
packssdw mm1, mm0 ; merge dword->word (4px)
paddsw mm1, mm7 ; rounding
psraw mm1, 7
packuswb mm1, mm3 ; clip and word->bytes
movd [dstq], mm1 ; store
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
INIT_XMM sse2
cglobal put_vp8_epel8_h4, 6, 6 + npicregs, 10, dst, dststride, src, srcstride, height, mx, picreg
shl mxd, 5
%ifdef PIC
lea picregq, [fourtap_filter_v_m]
%endif
lea mxq, [fourtap_filter_v+mxq-32]
pxor m7, m7
mova m4, [pw_64]
mova m5, [mxq+ 0]
mova m6, [mxq+16]
%ifdef m8
mova m8, [mxq+32]
mova m9, [mxq+48]
%endif
.nextrow:
movq m0, [srcq-1]
movq m1, [srcq-0]
movq m2, [srcq+1]
movq m3, [srcq+2]
punpcklbw m0, m7
punpcklbw m1, m7
punpcklbw m2, m7
punpcklbw m3, m7
pmullw m0, m5
pmullw m1, m6
%ifdef m8
pmullw m2, m8
pmullw m3, m9
%else
pmullw m2, [mxq+32]
pmullw m3, [mxq+48]
%endif
paddsw m0, m1
paddsw m2, m3
paddsw m0, m2
paddsw m0, m4
psraw m0, 7
packuswb m0, m7
movh [dstq], m0 ; store
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
INIT_XMM sse2
cglobal put_vp8_epel8_h6, 6, 6 + npicregs, 14, dst, dststride, src, srcstride, height, mx, picreg
lea mxd, [mxq*3]
shl mxd, 4
%ifdef PIC
lea picregq, [sixtap_filter_v_m]
%endif
lea mxq, [sixtap_filter_v+mxq-96]
pxor m7, m7
mova m6, [pw_64]
%ifdef m8
mova m8, [mxq+ 0]
mova m9, [mxq+16]
mova m10, [mxq+32]
mova m11, [mxq+48]
mova m12, [mxq+64]
mova m13, [mxq+80]
%endif
.nextrow:
movq m0, [srcq-2]
movq m1, [srcq-1]
movq m2, [srcq-0]
movq m3, [srcq+1]
movq m4, [srcq+2]
movq m5, [srcq+3]
punpcklbw m0, m7
punpcklbw m1, m7
punpcklbw m2, m7
punpcklbw m3, m7
punpcklbw m4, m7
punpcklbw m5, m7
%ifdef m8
pmullw m0, m8
pmullw m1, m9
pmullw m2, m10
pmullw m3, m11
pmullw m4, m12
pmullw m5, m13
%else
pmullw m0, [mxq+ 0]
pmullw m1, [mxq+16]
pmullw m2, [mxq+32]
pmullw m3, [mxq+48]
pmullw m4, [mxq+64]
pmullw m5, [mxq+80]
%endif
paddsw m1, m4
paddsw m0, m5
paddsw m1, m2
paddsw m0, m3
paddsw m0, m1
paddsw m0, m6
psraw m0, 7
packuswb m0, m7
movh [dstq], m0 ; store
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
%macro FILTER_V 1
; 4x4 block, V-only 4-tap filter
cglobal put_vp8_epel%1_v4, 7, 7, 8, dst, dststride, src, srcstride, height, picreg, my
shl myd, 5
%ifdef PIC
lea picregq, [fourtap_filter_v_m]
%endif
lea myq, [fourtap_filter_v+myq-32]
mova m6, [pw_64]
pxor m7, m7
mova m5, [myq+48]
; read 3 lines
sub srcq, srcstrideq
movh m0, [srcq]
movh m1, [srcq+ srcstrideq]
movh m2, [srcq+2*srcstrideq]
add srcq, srcstrideq
punpcklbw m0, m7
punpcklbw m1, m7
punpcklbw m2, m7
.nextrow:
; first calculate negative taps (to prevent losing positive overflows)
movh m4, [srcq+2*srcstrideq] ; read new row
punpcklbw m4, m7
mova m3, m4
pmullw m0, [myq+0]
pmullw m4, m5
paddsw m4, m0
; then calculate positive taps
mova m0, m1
pmullw m1, [myq+16]
paddsw m4, m1
mova m1, m2
pmullw m2, [myq+32]
paddsw m4, m2
mova m2, m3
; round/clip/store
paddsw m4, m6
psraw m4, 7
packuswb m4, m7
movh [dstq], m4
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
; 4x4 block, V-only 6-tap filter
cglobal put_vp8_epel%1_v6, 7, 7, 8, dst, dststride, src, srcstride, height, picreg, my
shl myd, 4
lea myq, [myq*3]
%ifdef PIC
lea picregq, [sixtap_filter_v_m]
%endif
lea myq, [sixtap_filter_v+myq-96]
pxor m7, m7
; read 5 lines
sub srcq, srcstrideq
sub srcq, srcstrideq
movh m0, [srcq]
movh m1, [srcq+srcstrideq]
movh m2, [srcq+srcstrideq*2]
lea srcq, [srcq+srcstrideq*2]
add srcq, srcstrideq
movh m3, [srcq]
movh m4, [srcq+srcstrideq]
punpcklbw m0, m7
punpcklbw m1, m7
punpcklbw m2, m7
punpcklbw m3, m7
punpcklbw m4, m7
.nextrow:
; first calculate negative taps (to prevent losing positive overflows)
mova m5, m1
pmullw m5, [myq+16]
mova m6, m4
pmullw m6, [myq+64]
paddsw m6, m5
; then calculate positive taps
movh m5, [srcq+2*srcstrideq] ; read new row
punpcklbw m5, m7
pmullw m0, [myq+0]
paddsw m6, m0
mova m0, m1
mova m1, m2
pmullw m2, [myq+32]
paddsw m6, m2
mova m2, m3
pmullw m3, [myq+48]
paddsw m6, m3
mova m3, m4
mova m4, m5
pmullw m5, [myq+80]
paddsw m6, m5
; round/clip/store
paddsw m6, [pw_64]
psraw m6, 7
packuswb m6, m7
movh [dstq], m6
; go to next line
add dstq, dststrideq
add srcq, srcstrideq
dec heightd ; next row
jg .nextrow
REP_RET
%endmacro
INIT_MMX mmxext
FILTER_V 4
INIT_XMM sse2
FILTER_V 8
%macro FILTER_BILINEAR 1
cglobal put_vp8_bilinear%1_v, 7, 7, 7, dst, dststride, src, srcstride, height, picreg, my
shl myd, 4
%ifdef PIC
lea picregq, [bilinear_filter_vw_m]
%endif
pxor m6, m6
mova m5, [bilinear_filter_vw+myq-1*16]
neg myq
mova m4, [bilinear_filter_vw+myq+7*16]
.nextrow:
movh m0, [srcq+srcstrideq*0]
movh m1, [srcq+srcstrideq*1]
movh m3, [srcq+srcstrideq*2]
punpcklbw m0, m6
punpcklbw m1, m6
punpcklbw m3, m6
mova m2, m1
pmullw m0, m4
pmullw m1, m5
pmullw m2, m4
pmullw m3, m5
paddsw m0, m1
paddsw m2, m3
psraw m0, 2
psraw m2, 2
pavgw m0, m6
pavgw m2, m6
%if mmsize == 8
packuswb m0, m0
packuswb m2, m2
movh [dstq+dststrideq*0], m0
movh [dstq+dststrideq*1], m2
%else
packuswb m0, m2
movh [dstq+dststrideq*0], m0
movhps [dstq+dststrideq*1], m0
%endif
lea dstq, [dstq+dststrideq*2]
lea srcq, [srcq+srcstrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
cglobal put_vp8_bilinear%1_h, 6, 6 + npicregs, 7, dst, dststride, src, srcstride, height, mx, picreg
shl mxd, 4
%ifdef PIC
lea picregq, [bilinear_filter_vw_m]
%endif
pxor m6, m6
mova m5, [bilinear_filter_vw+mxq-1*16]
neg mxq
mova m4, [bilinear_filter_vw+mxq+7*16]
.nextrow:
movh m0, [srcq+srcstrideq*0+0]
movh m1, [srcq+srcstrideq*0+1]
movh m2, [srcq+srcstrideq*1+0]
movh m3, [srcq+srcstrideq*1+1]
punpcklbw m0, m6
punpcklbw m1, m6
punpcklbw m2, m6
punpcklbw m3, m6
pmullw m0, m4
pmullw m1, m5
pmullw m2, m4
pmullw m3, m5
paddsw m0, m1
paddsw m2, m3
psraw m0, 2
psraw m2, 2
pavgw m0, m6
pavgw m2, m6
%if mmsize == 8
packuswb m0, m0
packuswb m2, m2
movh [dstq+dststrideq*0], m0
movh [dstq+dststrideq*1], m2
%else
packuswb m0, m2
movh [dstq+dststrideq*0], m0
movhps [dstq+dststrideq*1], m0
%endif
lea dstq, [dstq+dststrideq*2]
lea srcq, [srcq+srcstrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
%endmacro
INIT_MMX mmxext
FILTER_BILINEAR 4
INIT_XMM sse2
FILTER_BILINEAR 8
%macro FILTER_BILINEAR_SSSE3 1
cglobal put_vp8_bilinear%1_v, 7, 7, 5, dst, dststride, src, srcstride, height, picreg, my
shl myd, 4
%ifdef PIC
lea picregq, [bilinear_filter_vb_m]
%endif
pxor m4, m4
mova m3, [bilinear_filter_vb+myq-16]
.nextrow:
movh m0, [srcq+srcstrideq*0]
movh m1, [srcq+srcstrideq*1]
movh m2, [srcq+srcstrideq*2]
punpcklbw m0, m1
punpcklbw m1, m2
pmaddubsw m0, m3
pmaddubsw m1, m3
psraw m0, 2
psraw m1, 2
pavgw m0, m4
pavgw m1, m4
%if mmsize==8
packuswb m0, m0
packuswb m1, m1
movh [dstq+dststrideq*0], m0
movh [dstq+dststrideq*1], m1
%else
packuswb m0, m1
movh [dstq+dststrideq*0], m0
movhps [dstq+dststrideq*1], m0
%endif
lea dstq, [dstq+dststrideq*2]
lea srcq, [srcq+srcstrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
cglobal put_vp8_bilinear%1_h, 6, 6 + npicregs, 5, dst, dststride, src, srcstride, height, mx, picreg
shl mxd, 4
%ifdef PIC
lea picregq, [bilinear_filter_vb_m]
%endif
pxor m4, m4
mova m2, [filter_h2_shuf]
mova m3, [bilinear_filter_vb+mxq-16]
.nextrow:
movu m0, [srcq+srcstrideq*0]
movu m1, [srcq+srcstrideq*1]
pshufb m0, m2
pshufb m1, m2
pmaddubsw m0, m3
pmaddubsw m1, m3
psraw m0, 2
psraw m1, 2
pavgw m0, m4
pavgw m1, m4
%if mmsize==8
packuswb m0, m0
packuswb m1, m1
movh [dstq+dststrideq*0], m0
movh [dstq+dststrideq*1], m1
%else
packuswb m0, m1
movh [dstq+dststrideq*0], m0
movhps [dstq+dststrideq*1], m0
%endif
lea dstq, [dstq+dststrideq*2]
lea srcq, [srcq+srcstrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
%endmacro
INIT_MMX ssse3
FILTER_BILINEAR_SSSE3 4
INIT_XMM ssse3
FILTER_BILINEAR_SSSE3 8
INIT_MMX mmx
cglobal put_vp8_pixels8, 5, 5, 0, dst, dststride, src, srcstride, height
.nextrow:
movq mm0, [srcq+srcstrideq*0]
movq mm1, [srcq+srcstrideq*1]
lea srcq, [srcq+srcstrideq*2]
movq [dstq+dststrideq*0], mm0
movq [dstq+dststrideq*1], mm1
lea dstq, [dstq+dststrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
%if ARCH_X86_32
INIT_MMX mmx
cglobal put_vp8_pixels16, 5, 5, 0, dst, dststride, src, srcstride, height
.nextrow:
movq mm0, [srcq+srcstrideq*0+0]
movq mm1, [srcq+srcstrideq*0+8]
movq mm2, [srcq+srcstrideq*1+0]
movq mm3, [srcq+srcstrideq*1+8]
lea srcq, [srcq+srcstrideq*2]
movq [dstq+dststrideq*0+0], mm0
movq [dstq+dststrideq*0+8], mm1
movq [dstq+dststrideq*1+0], mm2
movq [dstq+dststrideq*1+8], mm3
lea dstq, [dstq+dststrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
%endif
INIT_XMM sse
cglobal put_vp8_pixels16, 5, 5, 2, dst, dststride, src, srcstride, height
.nextrow:
movups xmm0, [srcq+srcstrideq*0]
movups xmm1, [srcq+srcstrideq*1]
lea srcq, [srcq+srcstrideq*2]
movaps [dstq+dststrideq*0], xmm0
movaps [dstq+dststrideq*1], xmm1
lea dstq, [dstq+dststrideq*2]
sub heightd, 2
jg .nextrow
REP_RET
;-----------------------------------------------------------------------------
; void ff_vp8_idct_dc_add_<opt>(uint8_t *dst, int16_t block[16], int stride);
;-----------------------------------------------------------------------------
%macro ADD_DC 4
%4 m2, [dst1q+%3]
%4 m3, [dst1q+strideq+%3]
%4 m4, [dst2q+%3]
%4 m5, [dst2q+strideq+%3]
paddusb m2, %1
paddusb m3, %1
paddusb m4, %1
paddusb m5, %1
psubusb m2, %2
psubusb m3, %2
psubusb m4, %2
psubusb m5, %2
%4 [dst1q+%3], m2
%4 [dst1q+strideq+%3], m3
%4 [dst2q+%3], m4
%4 [dst2q+strideq+%3], m5
%endmacro
INIT_MMX mmx
cglobal vp8_idct_dc_add, 3, 3, 0, dst, block, stride
; load data
movd m0, [blockq]
; calculate DC
paddw m0, [pw_4]
pxor m1, m1
psraw m0, 3
movd [blockq], m1
psubw m1, m0
packuswb m0, m0
packuswb m1, m1
punpcklbw m0, m0
punpcklbw m1, m1
punpcklwd m0, m0
punpcklwd m1, m1
; add DC
DEFINE_ARGS dst1, dst2, stride
lea dst2q, [dst1q+strideq*2]
ADD_DC m0, m1, 0, movh
RET
INIT_XMM sse4
cglobal vp8_idct_dc_add, 3, 3, 6, dst, block, stride
; load data
movd m0, [blockq]
pxor m1, m1
; calculate DC
paddw m0, [pw_4]
movd [blockq], m1
DEFINE_ARGS dst1, dst2, stride
lea dst2q, [dst1q+strideq*2]
movd m2, [dst1q]
movd m3, [dst1q+strideq]
movd m4, [dst2q]
movd m5, [dst2q+strideq]
psraw m0, 3
pshuflw m0, m0, 0
punpcklqdq m0, m0
punpckldq m2, m3
punpckldq m4, m5
punpcklbw m2, m1
punpcklbw m4, m1
paddw m2, m0
paddw m4, m0
packuswb m2, m4
movd [dst1q], m2
pextrd [dst1q+strideq], m2, 1
pextrd [dst2q], m2, 2
pextrd [dst2q+strideq], m2, 3
RET
;-----------------------------------------------------------------------------
; void ff_vp8_idct_dc_add4y_<opt>(uint8_t *dst, int16_t block[4][16], int stride);
;-----------------------------------------------------------------------------
%if ARCH_X86_32
INIT_MMX mmx
cglobal vp8_idct_dc_add4y, 3, 3, 0, dst, block, stride
; load data
movd m0, [blockq+32*0] ; A
movd m1, [blockq+32*2] ; C
punpcklwd m0, [blockq+32*1] ; A B
punpcklwd m1, [blockq+32*3] ; C D
punpckldq m0, m1 ; A B C D
pxor m6, m6
; calculate DC
paddw m0, [pw_4]
movd [blockq+32*0], m6
movd [blockq+32*1], m6
movd [blockq+32*2], m6
movd [blockq+32*3], m6
psraw m0, 3
psubw m6, m0
packuswb m0, m0
packuswb m6, m6
punpcklbw m0, m0 ; AABBCCDD
punpcklbw m6, m6 ; AABBCCDD
movq m1, m0
movq m7, m6
punpcklbw m0, m0 ; AAAABBBB
punpckhbw m1, m1 ; CCCCDDDD
punpcklbw m6, m6 ; AAAABBBB
punpckhbw m7, m7 ; CCCCDDDD
; add DC
DEFINE_ARGS dst1, dst2, stride
lea dst2q, [dst1q+strideq*2]
ADD_DC m0, m6, 0, mova
ADD_DC m1, m7, 8, mova
RET
%endif
INIT_XMM sse2
cglobal vp8_idct_dc_add4y, 3, 3, 6, dst, block, stride
; load data
movd m0, [blockq+32*0] ; A
movd m1, [blockq+32*2] ; C
punpcklwd m0, [blockq+32*1] ; A B
punpcklwd m1, [blockq+32*3] ; C D
punpckldq m0, m1 ; A B C D
pxor m1, m1
; calculate DC
paddw m0, [pw_4]
movd [blockq+32*0], m1
movd [blockq+32*1], m1
movd [blockq+32*2], m1
movd [blockq+32*3], m1
psraw m0, 3
psubw m1, m0
packuswb m0, m0
packuswb m1, m1
punpcklbw m0, m0
punpcklbw m1, m1
punpcklbw m0, m0
punpcklbw m1, m1
; add DC
DEFINE_ARGS dst1, dst2, stride
lea dst2q, [dst1q+strideq*2]
ADD_DC m0, m1, 0, mova
RET
;-----------------------------------------------------------------------------
; void ff_vp8_idct_dc_add4uv_<opt>(uint8_t *dst, int16_t block[4][16], int stride);
;-----------------------------------------------------------------------------
INIT_MMX mmx
cglobal vp8_idct_dc_add4uv, 3, 3, 0, dst, block, stride
; load data
movd m0, [blockq+32*0] ; A
movd m1, [blockq+32*2] ; C
punpcklwd m0, [blockq+32*1] ; A B
punpcklwd m1, [blockq+32*3] ; C D
punpckldq m0, m1 ; A B C D
pxor m6, m6
; calculate DC
paddw m0, [pw_4]
movd [blockq+32*0], m6
movd [blockq+32*1], m6
movd [blockq+32*2], m6
movd [blockq+32*3], m6
psraw m0, 3
psubw m6, m0
packuswb m0, m0
packuswb m6, m6
punpcklbw m0, m0 ; AABBCCDD
punpcklbw m6, m6 ; AABBCCDD
movq m1, m0
movq m7, m6
punpcklbw m0, m0 ; AAAABBBB
punpckhbw m1, m1 ; CCCCDDDD
punpcklbw m6, m6 ; AAAABBBB
punpckhbw m7, m7 ; CCCCDDDD
; add DC
DEFINE_ARGS dst1, dst2, stride
lea dst2q, [dst1q+strideq*2]
ADD_DC m0, m6, 0, mova
lea dst1q, [dst1q+strideq*4]
lea dst2q, [dst2q+strideq*4]
ADD_DC m1, m7, 0, mova
RET
;-----------------------------------------------------------------------------
; void ff_vp8_idct_add_<opt>(uint8_t *dst, int16_t block[16], int stride);
;-----------------------------------------------------------------------------
; calculate %1=mul_35468(%1)-mul_20091(%2); %2=mul_20091(%1)+mul_35468(%2)
; this macro assumes that m6/m7 have words for 20091/17734 loaded
%macro VP8_MULTIPLY_SUMSUB 4
mova %3, %1
mova %4, %2
pmulhw %3, m6 ;20091(1)
pmulhw %4, m6 ;20091(2)
paddw %3, %1
paddw %4, %2
paddw %1, %1
paddw %2, %2
pmulhw %1, m7 ;35468(1)
pmulhw %2, m7 ;35468(2)
psubw %1, %4
paddw %2, %3
%endmacro
; calculate x0=%1+%3; x1=%1-%3
; x2=mul_35468(%2)-mul_20091(%4); x3=mul_20091(%2)+mul_35468(%4)
; %1=x0+x3 (tmp0); %2=x1+x2 (tmp1); %3=x1-x2 (tmp2); %4=x0-x3 (tmp3)
; %5/%6 are temporary registers
; we assume m6/m7 have constant words 20091/17734 loaded in them
%macro VP8_IDCT_TRANSFORM4x4_1D 6
SUMSUB_BA w, %3, %1, %5 ;t0, t1
VP8_MULTIPLY_SUMSUB m%2, m%4, m%5,m%6 ;t2, t3
SUMSUB_BA w, %4, %3, %5 ;tmp0, tmp3
SUMSUB_BA w, %2, %1, %5 ;tmp1, tmp2
SWAP %4, %1
SWAP %4, %3
%endmacro
%macro VP8_IDCT_ADD 0
cglobal vp8_idct_add, 3, 3, 0, dst, block, stride
; load block data
movq m0, [blockq+ 0]
movq m1, [blockq+ 8]
movq m2, [blockq+16]
movq m3, [blockq+24]
movq m6, [pw_20091]
movq m7, [pw_17734]
%if cpuflag(sse)
xorps xmm0, xmm0
movaps [blockq+ 0], xmm0
movaps [blockq+16], xmm0
%else
pxor m4, m4
movq [blockq+ 0], m4
movq [blockq+ 8], m4
movq [blockq+16], m4
movq [blockq+24], m4
%endif
; actual IDCT
VP8_IDCT_TRANSFORM4x4_1D 0, 1, 2, 3, 4, 5
TRANSPOSE4x4W 0, 1, 2, 3, 4
paddw m0, [pw_4]
VP8_IDCT_TRANSFORM4x4_1D 0, 1, 2, 3, 4, 5
TRANSPOSE4x4W 0, 1, 2, 3, 4
; store
pxor m4, m4
DEFINE_ARGS dst1, dst2, stride
lea dst2q, [dst1q+2*strideq]
STORE_DIFFx2 m0, m1, m6, m7, m4, 3, dst1q, strideq
STORE_DIFFx2 m2, m3, m6, m7, m4, 3, dst2q, strideq
RET
%endmacro
%if ARCH_X86_32
INIT_MMX mmx
VP8_IDCT_ADD
%endif
INIT_MMX sse
VP8_IDCT_ADD
;-----------------------------------------------------------------------------
; void ff_vp8_luma_dc_wht(int16_t block[4][4][16], int16_t dc[16])
;-----------------------------------------------------------------------------
%macro SCATTER_WHT 3
movd dc1d, m%1
movd dc2d, m%2
mov [blockq+2*16*(0+%3)], dc1w
mov [blockq+2*16*(1+%3)], dc2w
shr dc1d, 16
shr dc2d, 16
psrlq m%1, 32
psrlq m%2, 32
mov [blockq+2*16*(4+%3)], dc1w
mov [blockq+2*16*(5+%3)], dc2w
movd dc1d, m%1
movd dc2d, m%2
mov [blockq+2*16*(8+%3)], dc1w
mov [blockq+2*16*(9+%3)], dc2w
shr dc1d, 16
shr dc2d, 16
mov [blockq+2*16*(12+%3)], dc1w
mov [blockq+2*16*(13+%3)], dc2w
%endmacro
%macro HADAMARD4_1D 4
SUMSUB_BADC w, %2, %1, %4, %3
SUMSUB_BADC w, %4, %2, %3, %1
SWAP %1, %4, %3
%endmacro
%macro VP8_DC_WHT 0
cglobal vp8_luma_dc_wht, 2, 3, 0, block, dc1, dc2
movq m0, [dc1q]
movq m1, [dc1q+8]
movq m2, [dc1q+16]
movq m3, [dc1q+24]
%if cpuflag(sse)
xorps xmm0, xmm0
movaps [dc1q+ 0], xmm0
movaps [dc1q+16], xmm0
%else
pxor m4, m4
movq [dc1q+ 0], m4
movq [dc1q+ 8], m4
movq [dc1q+16], m4
movq [dc1q+24], m4
%endif
HADAMARD4_1D 0, 1, 2, 3
TRANSPOSE4x4W 0, 1, 2, 3, 4
paddw m0, [pw_3]
HADAMARD4_1D 0, 1, 2, 3
psraw m0, 3
psraw m1, 3
psraw m2, 3
psraw m3, 3
SCATTER_WHT 0, 1, 0
SCATTER_WHT 2, 3, 2
RET
%endmacro
%if ARCH_X86_32
INIT_MMX mmx
VP8_DC_WHT
%endif
INIT_MMX sse
VP8_DC_WHT
| QuintonJason/qvids | front-end/build/ffmpeg/libavcodec/x86/vp8dsp.asm | Assembly | mit | 34,636 |
SECTION .data
SECTION .text
global _start
_start:
nop
mov eax, 447
mov ebx, 1739
mul ebx
mov eax, 0FFFFFFFFh
mov ebx, 03B72h
mul ebx
nop
mov eax, 1 ; exit system call
mov ebx, 0 ; return code
int 80H ; exit
SECTION .bss
| paulnguyen/cmpe279 | modules/module1/math/mul.asm | Assembly | apache-2.0 | 281 |
; Returns SGN (SIGN) for 8 bits signed integer
__SGNI8:
or a
ret z
ld a, 1
ret p
neg
ret
| haroldo-ok/really-old-stuff | mastersystem/zxb-sms-2012-02-23/zxb-sms/wip/zxb/library-asm/sgni8.asm | Assembly | apache-2.0 | 97 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright(c) 2011-2014 Intel Corporation All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; * Neither the name of Intel Corporation nor the names of its
; contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%define EFLAGS_HAS_CPUID (1<<21)
%define FLAG_CPUID1_ECX_CLMUL (1<<1)
%define FLAG_CPUID1_EDX_SSE2 (1<<26)
%define FLAG_CPUID1_ECX_SSE3 (1)
%define FLAG_CPUID1_ECX_SSE4_1 (1<<19)
%define FLAG_CPUID1_ECX_SSE4_2 (1<<20)
%define FLAG_CPUID1_ECX_POPCNT (1<<23)
%define FLAG_CPUID1_ECX_AESNI (1<<25)
%define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
%define FLAG_CPUID1_ECX_AVX (1<<28)
%define FLAG_CPUID1_EBX_AVX2 (1<<5)
%define FLAG_XGETBV_EAX_XMM_YMM 0x6
%define FLAG_CPUID1_EAX_AVOTON 0x000406d0
; define d and w variants for registers
%define raxd eax
%define raxw ax
%define raxb al
%define rbxd ebx
%define rbxw bx
%define rbxb bl
%define rcxd ecx
%define rcxw cx
%define rcxb cl
%define rdxd edx
%define rdxw dx
%define rdxb dl
%define rsid esi
%define rsiw si
%define rsib sil
%define rdid edi
%define rdiw di
%define rdib dil
%define rbpd ebp
%define rbpw bp
%define rbpb bpl
%define ymm0x xmm0
%define ymm1x xmm1
%define ymm2x xmm2
%define ymm3x xmm3
%define ymm4x xmm4
%define ymm5x xmm5
%define ymm6x xmm6
%define ymm7x xmm7
%define ymm8x xmm8
%define ymm9x xmm9
%define ymm10x xmm10
%define ymm11x xmm11
%define ymm12x xmm12
%define ymm13x xmm13
%define ymm14x xmm14
%define ymm15x xmm15
%define DWORD(reg) reg %+ d
%define WORD(reg) reg %+ w
%define BYTE(reg) reg %+ b
%define XWORD(reg) reg %+ x
| fkautz/minio | pkg/storage/erasure/isal/include/reg-sizes.asm | Assembly | apache-2.0 | 3,068 |
.ORIG x1234
XOR R1, R2, xa
.END | Zaydax/lc3bISAemulator | hw1_autograde/test/state_data_in/8.asm | Assembly | mit | 32 |
;
; Part of OS4, __idt_default_handler.asm
; Author Mikael Henriksson, miklhh
;
global __idt_default_handler:function (__idt_default_handler.end - __idt_default_handler)
__idt_default_handler:
pusha
mov al, 0x20 ; ???
mov dx, 0x20 ; ???
out dx, al ; ???
popa
iret
.end:
| miklhh/os4 | src/arch/i686/int_routines/__idt_default_handler.asm | Assembly | mit | 318 |
.ORIG x1234
RSHFL R2, R7, #4
RSHFL R2, R7, #4
RSHFL R2, R7, #4
RSHFL R2, R7, #4
RSHFL R2, R7, #4
.END
| Zaydax/PipelineProcessor | lab3_test_harness/test/state_data_in/11.asm | Assembly | mit | 107 |
;---------------------------------------
; CLi² (Command Line Interface)
; 2014 © breeze/fishbone crew
;---------------------------------------
; Grab TR-DOS Diks to TRD Image
;---------------------------------------
org #c000-4
include "system/constants.asm" ; Константы
include "system/api.h.asm" ; Список комманд CLi² API
include "system/errorcodes.asm" ; коды ошибок
include "drivers/drivers.h.asm" ; Список комманд Drivers API
appStart
db #7f,"CLA" ; Идентификатор приложения CLA (Command Line Application)
ld a,(hl)
cp #00
jp z,appShowInfo ; Выход. Вывод информации о программе
appExit ret
;---------------------------------------------
diskInfo
ret
;---------------------------------------------
appShowInfo call appVer ; Вывод информации о программе
call appHelp
jp appExit
appVer ld hl,appVersionMsg
ld a,printAppNameString
call cliKernel
ld hl,appCopyRMsg
ld a,printCopyrightString
call cliKernel
; ld a,#01 ; Просто выйти если файл не задан
; ld (sxgFileCheck+1),a
ret
appHelp ld hl,appUsageMsg
ld a,printString
call cliKernel
; ld a,#01 ; Просто выйти если файл не задан
; ld (sxgFileCheck+1),a
ret
;---------------------------------------------
appVersionMsg db "Dump TR-DOS Disk to TRD Image v 0.01",#00
appCopyRMsg db "2014 ",pCopy," Breeze\\\\Fishbone Crew",#0d,#00
appUsageMsg db #0d,15,csOk,"Usage: disk2trd [switches] filename.sxg",#0d
db 16,cRestore," -i ",15,csInfo,"\tinfo. Show disk information",#0d
db 16,cRestore," -v ",15,csInfo,"\tversion. show application's version and copyrights",#0d
db 16,cRestore," -h ",15,csInfo,"\thelp. show this info"
db 16,cRestore,#0d,#00
;---------------------------------------------
; Key's table for params
;---------------------------------------------
keyTable
db "-h"
db "*"
dw appShowInfo
db "-v"
db "*"
dw appVer
db "-i"
db "*"
dw diskInfo
;--- table end marker ---
db #00
appEnd nop
SAVEBIN "install/bin/disk2trd", appStart, appEnd-appStart
| LessNick/cli2 | src/app/disk2trd.asm | Assembly | bsd-3-clause | 2,287 |
/* Copyright 2014 Peter Goodman, all rights reserved. */
#include "arch/x86-64/asm/include.asm.inc"
START_FILE_INTEL
// Get the user-space TLS base address.
//
// Note: This is Linux-specific, and assumes the first quadword of memory
// pointed to by the base address of the segment descriptor for `FS`
// is a pointer to said base address (i.e. self-reference).
DEFINE_FUNC(granary_arch_get_segment_base)
mov rax, qword ptr [GRANARY_IF_USER_ELSE(fs, gs):0]
ret
END_FUNC(granary_arch_get_segment_base)
END_FILE
| Granary/granary2 | os/linux/arch/x86-64/segment.asm | Assembly | mit | 535 |
init mac a
end init
mac macro reg
ld reg, 0
endm
| scoffey/jz80sim | test/jzas/semantic/valid/success03.asm | Assembly | mit | 53 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; * Neither the name of Intel Corporation nor the names of its
; contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Optimized xor of N source vectors using SSE
;;; int xor_gen_sse(int vects, int len, void **array)
;;; Generates xor parity vector from N (vects-1) sources in array of pointers
;;; (**array). Last pointer is the dest.
;;; Vectors must be aligned to 16 bytes. Length can be any value.
%include "reg_sizes.asm"
%ifidn __OUTPUT_FORMAT__, elf64
%define arg0 rdi
%define arg1 rsi
%define arg2 rdx
%define arg3 rcx
%define arg4 r8
%define arg5 r9
%define tmp r11
%define tmp2 rax
%define tmp2.b al
%define tmp3 arg4
%define return rax
%define PS 8
%define func(x) x: endbranch
%define FUNC_SAVE
%define FUNC_RESTORE
%elifidn __OUTPUT_FORMAT__, win64
%define arg0 rcx
%define arg1 rdx
%define arg2 r8
%define arg3 r9
%define return rax
%define tmp2 rax
%define tmp2.b al
%define PS 8
%define tmp r11
%define tmp3 r10
%define stack_size 2*16 + 8 ; must be an odd multiple of 8
%define func(x) proc_frame x
%macro FUNC_SAVE 0
alloc_stack stack_size
save_xmm128 xmm6, 0*16
save_xmm128 xmm7, 1*16
end_prolog
%endmacro
%macro FUNC_RESTORE 0
movdqa xmm6, [rsp + 0*16]
movdqa xmm7, [rsp + 1*16]
add rsp, stack_size
%endmacro
%elifidn __OUTPUT_FORMAT__, elf32
%define arg0 arg(0)
%define arg1 ecx
%define tmp2 eax
%define tmp2.b al
%define tmp3 edx
%define return eax
%define PS 4
%define func(x) x: endbranch
%define arg(x) [ebp+8+PS*x]
%define arg2 edi ; must sav/restore
%define arg3 esi
%define tmp ebx
%macro FUNC_SAVE 0
push ebp
mov ebp, esp
push esi
push edi
push ebx
mov arg1, arg(1)
mov arg2, arg(2)
%endmacro
%macro FUNC_RESTORE 0
pop ebx
pop edi
pop esi
mov esp, ebp ;if has frame pointer
pop ebp
%endmacro
%endif ; output formats
%define vec arg0
%define len arg1
%define ptr arg3
%define pos tmp3
%ifidn PS,8 ; 64-bit code
default rel
[bits 64]
%endif
;;; Use Non-temporal load/stor
%ifdef NO_NT_LDST
%define XLDR movdqa
%define XSTR movdqa
%else
%define XLDR movntdqa
%define XSTR movntdq
%endif
section .text
align 16
mk_global xor_check_sse, function
func(xor_check_sse)
FUNC_SAVE
%ifidn PS,8 ;64-bit code
sub vec, 1 ; Keep as offset to last source
%else ;32-bit code
mov tmp, arg(0) ; Update vec length arg to last source
sub tmp, 1
mov arg(0), tmp
%endif
jng return_fail ;Must have at least 2 sources
cmp len, 0
je return_pass
test len, (128-1) ;Check alignment of length
jnz len_not_aligned
len_aligned_128bytes:
sub len, 128
mov pos, 0
mov tmp, vec ;Preset to last vector
loop128:
mov tmp2, [arg2+tmp*PS] ;Fetch last pointer in array
sub tmp, 1 ;Next vect
XLDR xmm0, [tmp2+pos] ;Start with end of array in last vector
XLDR xmm1, [tmp2+pos+16] ;Keep xor parity in xmm0-7
XLDR xmm2, [tmp2+pos+(2*16)]
XLDR xmm3, [tmp2+pos+(3*16)]
XLDR xmm4, [tmp2+pos+(4*16)]
XLDR xmm5, [tmp2+pos+(5*16)]
XLDR xmm6, [tmp2+pos+(6*16)]
XLDR xmm7, [tmp2+pos+(7*16)]
next_vect:
mov ptr, [arg2+tmp*PS]
sub tmp, 1
xorpd xmm0, [ptr+pos] ;Get next vector (source)
xorpd xmm1, [ptr+pos+16]
xorpd xmm2, [ptr+pos+(2*16)]
xorpd xmm3, [ptr+pos+(3*16)]
xorpd xmm4, [ptr+pos+(4*16)]
xorpd xmm5, [ptr+pos+(5*16)]
xorpd xmm6, [ptr+pos+(6*16)]
xorpd xmm7, [ptr+pos+(7*16)]
;;; prefetch [ptr+pos+(8*16)]
jge next_vect ;Loop for each vect
;; End of vects, chech that all parity regs = 0
mov tmp, vec ;Back to last vector
por xmm0, xmm1
por xmm0, xmm2
por xmm0, xmm3
por xmm0, xmm4
por xmm0, xmm5
por xmm0, xmm6
por xmm0, xmm7
ptest xmm0, xmm0
jnz return_fail
add pos, 128
cmp pos, len
jle loop128
return_pass:
FUNC_RESTORE
mov return, 0
ret
;;; Do one byte at a time for no alignment case
xor_gen_byte:
mov tmp, vec ;Preset to last vector
loop_1byte:
mov ptr, [arg2+tmp*PS] ;Fetch last pointer in array
mov tmp2.b, [ptr+len-1] ;Get array n
sub tmp, 1
nextvect_1byte:
mov ptr, [arg2+tmp*PS]
xor tmp2.b, [ptr+len-1]
sub tmp, 1
jge nextvect_1byte
mov tmp, vec ;Back to last vector
cmp tmp2.b, 0
jne return_fail
sub len, 1
test len, (8-1)
jnz loop_1byte
cmp len, 0
je return_pass
test len, (128-1) ;If not 0 and 128bit aligned
jz len_aligned_128bytes ; then do aligned case. len = y * 128
;; else we are 8-byte aligned so fall through to recheck
;; Unaligned length cases
len_not_aligned:
test len, (PS-1)
jne xor_gen_byte
mov tmp3, len
and tmp3, (128-1) ;Do the unaligned bytes 4-8 at a time
mov tmp, vec ;Preset to last vector
;; Run backwards 8 bytes (4B for 32bit) at a time for (tmp3) bytes
loopN_bytes:
mov ptr, [arg2+tmp*PS] ;Fetch last pointer in array
mov tmp2, [ptr+len-PS] ;Get array n
sub tmp, 1
nextvect_Nbytes:
mov ptr, [arg2+tmp*PS] ;Get pointer to next vector
xor tmp2, [ptr+len-PS]
sub tmp, 1
jge nextvect_Nbytes ;Loop for each source
mov tmp, vec ;Back to last vector
cmp tmp2, 0
jne return_fail
sub len, PS
sub tmp3, PS
jg loopN_bytes
cmp len, 128 ;Now len is aligned to 128B
jge len_aligned_128bytes ;We can do the rest aligned
cmp len, 0
je return_pass
return_fail:
mov return, 1
FUNC_RESTORE
ret
endproc_frame
section .data
;;; func core, ver, snum
slversion xor_check_sse, 00, 03, 0031
| Intel-HLS/GKL | src/main/native/compression/isa-l-master/raid/xor_check_sse.asm | Assembly | mit | 6,911 |
; ========================================================== ;
; ;
; Utilities for IAS subject labs ;
; ;
; Version: v0.3 ;
; Date: 2015-01-01 ;
; Author: Martin Zamba (izamba@fit.vutbr.cz) ;
; ;
; ========================================================== ;
%ifndef IAS_UTILS ; to avoid multiple inclusion
%define IAS_UTILS ;
; ========================================================== ;
; Macros ;
; ========================================================== ;
; macro for printing new line character(s)
%macro _nl 0
call WriteNewLine
%endmacro
; macro will print one character
%macro _putchar 1
push EAX
mov AL, %1
call WriteChar
pop EAX
%endmacro
; macro will print string starting at parameter
%macro _write 1
push ESI
mov ESI, %1
call WriteString
pop ESI
%endmacro
; macro will print string starting at parameter + new line
%macro _writeln 1
_write %1
_nl
%endmacro
; macro will print 32bit integer at parameter
%macro _iwrite 1
push EAX
mov EAX, %1
call WriteInt32
pop EAX
%endmacro
; macro will print 32bit integer at parameter + new line
%macro _iwriteln 1
_iwrite %1
call WriteNewLine
%endmacro
; macro will convert 64bit floating point number in specified
; register to 32bit format and print it
%macro _fwrite 1
push EAX
fxch %1 ; swap given register into ST0
fst dword [fwriteln_buf] ; convert it to 32bit float and store into buffer
fxch %1 ; swap given register content back from ST0
mov EAX, [fwriteln_buf]
call WriteFloat
pop EAX
%endmacro
; macro will convert 64bit floating point number in specified
; register to 32bit format and print it with new line character at end
%macro _fwriteln 1
_fwrite %1
call WriteNewLine
%endmacro
; macro will print out the content of FPU registers
%macro _fpu_regs 0
_writeln fpu_str_caption
_write fpu_str_ST0
_fwriteln ST0
_write fpu_str_ST1
_fwriteln ST1
_write fpu_str_ST2
_fwriteln ST2
_write fpu_str_ST3
_fwriteln ST3
_write fpu_str_ST4
_fwriteln ST4
_write fpu_str_ST5
_fwriteln ST5
_write fpu_str_ST6
_fwriteln ST6
_write fpu_str_ST7
_fwriteln ST7
%endmacro
; ========================================================== ;
; Variables ;
; ========================================================== ;
[section .bss] ; bss (uninitialised data) segment definition
fwriteln_buf: resd 1
; ========================================================== ;
; Variables ;
; ========================================================== ;
[section .data use32 class=DATA]
fpu_str_caption: db 'FPU register content:', 0
fpu_str_ST0: db ' ST0: ', 0
fpu_str_ST1: db ' ST1: ', 0
fpu_str_ST2: db ' ST2: ', 0
fpu_str_ST3: db ' ST3: ', 0
fpu_str_ST4: db ' ST4: ', 0
fpu_str_ST5: db ' ST5: ', 0
fpu_str_ST6: db ' ST6: ', 0
fpu_str_ST7: db ' ST7: ', 0
; ========================================================== ;
; Functions ;
; ========================================================== ;
[section .checker use32 class=CODE]
%endif ; to avoid multiple inclusion
| infiRD/IAS | lab7/workspace/lab7/libs/utils.asm | Assembly | apache-2.0 | 3,548 |
Map_A50A: dc.w word_A572-Map_A50A
dc.w word_A57A-Map_A50A
dc.w word_A582-Map_A50A
dc.w word_A58A-Map_A50A
dc.w word_A592-Map_A50A
dc.w word_A59A-Map_A50A
dc.w word_A5A2-Map_A50A
dc.w word_A5AA-Map_A50A
dc.w word_A5B2-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5BA-Map_A50A
dc.w word_A5D2-Map_A50A
dc.w word_A5DA-Map_A50A
dc.w word_A5E2-Map_A50A
dc.w word_A5EA-Map_A50A
dc.w word_A5F2-Map_A50A
dc.w word_A5FA-Map_A50A
dc.w word_A602-Map_A50A
dc.w word_A60A-Map_A50A
dc.w word_A612-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A61A-Map_A50A
dc.w word_A632-Map_A50A
dc.w word_A63A-Map_A50A
dc.w word_A642-Map_A50A
dc.w word_A64A-Map_A50A
dc.w word_A652-Map_A50A
dc.w word_A65A-Map_A50A
dc.w word_A662-Map_A50A
dc.w word_A66A-Map_A50A
dc.w word_A672-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A67A-Map_A50A
dc.w word_A692-Map_A50A
dc.w word_A69A-Map_A50A
dc.w word_A6A2-Map_A50A
dc.w word_A6AA-Map_A50A
word_A572: dc.w 1
dc.b $F8, 9, 0, 0, $FF, $F4
word_A57A: dc.w 1
dc.b $F8, 9, 0, $C, $FF, $F4
word_A582: dc.w 1
dc.b $F4, $A, 0, $18, $FF, $F4
word_A58A: dc.w 1
dc.b $F8, 9, 0, $27, $FF, $F4
word_A592: dc.w 1
dc.b $F8, 5, 0, $33, $FF, $F8
word_A59A: dc.w 1
dc.b $F8, 5, 0, $39, $FF, $F8
word_A5A2: dc.w 1
dc.b $F8, 5, 0, $3F, $FF, $F8
word_A5AA: dc.w 1
dc.b $FC, 4, 0, $45, $FF, $F8
word_A5B2: dc.w 1
dc.b $FC, 0, 0, $48, $FF, $FC
word_A5BA: dc.w 1
dc.b $FC, 0, 0, $4A, $FF, $FC
dc.w 1
dc.b $FC, 0, 0, $4C, $FF, $FC
dc.w 1
dc.b $FC, 0, 0, $4E, $FF, $FC
word_A5D2: dc.w 1
dc.b $F4, 6, 0, 6, $FF, $F8
word_A5DA: dc.w 1
dc.b $F4, 6, 0, $12, $FF, $F8
word_A5E2: dc.w 1
dc.b $F4, 6, 0, $21, $FF, $F8
word_A5EA: dc.w 1
dc.b $F4, 6, 0, $2D, $FF, $F8
word_A5F2: dc.w 1
dc.b $F8, 1, 0, $37, $FF, $FC
word_A5FA: dc.w 1
dc.b $F8, 1, 0, $3D, $FF, $FC
word_A602: dc.w 1
dc.b $F8, 1, 0, $43, $FF, $FC
word_A60A: dc.w 1
dc.b $FC, 0, 0, $47, $FF, $FC
word_A612: dc.w 1
dc.b $FC, 0, 0, $49, $FF, $FC
word_A61A: dc.w 1
dc.b $FC, 0, 0, $4B, $FF, $FC
dc.w 1
dc.b $FC, 0, 0, $4D, $FF, $FC
dc.w 1
dc.b $FC, 0, 0, $4F, $FF, $FC
word_A632: dc.w 1
dc.b $F4, 6, 8, 6, $FF, $F8
word_A63A: dc.w 1
dc.b $F4, 6, 8, $12, $FF, $F8
word_A642: dc.w 1
dc.b $F4, 6, 8, $21, $FF, $F8
word_A64A: dc.w 1
dc.b $F4, 6, 8, $2D, $FF, $F8
word_A652: dc.w 1
dc.b $F8, 1, 8, $37, $FF, $FC
word_A65A: dc.w 1
dc.b $F8, 1, 8, $3D, $FF, $FC
word_A662: dc.w 1
dc.b $F8, 1, 8, $43, $FF, $FC
word_A66A: dc.w 1
dc.b $FC, 0, 8, $47, $FF, $FC
word_A672: dc.w 1
dc.b $FC, 0, 8, $49, $FF, $FC
word_A67A: dc.w 1
dc.b $FC, 0, 8, $4B, $FF, $FC
dc.w 1
dc.b $FC, 0, 8, $4D, $FF, $FC
dc.w 1
dc.b $FC, 0, 8, $4F, $FF, $FC
word_A692: dc.w 1
dc.b $F4, $A, 0, $50, $FF, $F4
word_A69A: dc.w 1
dc.b $F4, $A, $18, $50, $FF, $F4
word_A6A2: dc.w 1
dc.b $F4, $A, 8, $50, $FF, $F4
word_A6AA: dc.w 1
dc.b $F4, $A, $10, $50, $FF, $F4
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/General/Special Stage/Map - Ring.asm | Assembly | apache-2.0 | 3,609 |
.686
.xmm
.model flat, c
DATA segment align(32)
F76543210 real4 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0
F88888888 real4 8.0, 8.0, 8.0, 8.0, 8.0, 8.0, 8.0, 8.0
F00000000 real4 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0
F3210 real4 0.0, 1.0, 2.0, 3.0
DATA ends
.code
projx32 PROC param:dword
; for (int iy=iy0; iy<iy1; iy++) {
; const int ifpidx = iy * ixdimp;
; const float fyoff = iy * fsin + foffset;
; for (int ix=0; ix<ixdimp; ix++) {
; int ix0 = (int)(ix * fcos + fyoff);
; if (ix0 < 0) continue;
; if (ix0 >= ixdimpg) continue;
; ifp[ifpidx + ix] += ipgp[ix0];
; }
; }
;local valiables
local ixdimp :dword
local ixdimp4 :dword
local iy0 :dword
local iy1 :dword
; local pmxcsr :dword
; local smxcsr :dword
;store registers
push esi
push edi
push ebx
push ebp
; stmxcsr smxcsr
;get pointer to args
mov esi, param ;arg #1
;load valiables and constants
; mov ixdimpg, [esi + 12]
mov eax, [esi + 16]
mov ixdimp, eax
; mov eax, ixdimp
shl eax, 2
mov ixdimp4, eax
; mov ifp, [esi + 20]
; mov igp, [esi + 24]
mov eax, [esi + 32] ;iy0
mov iy0, eax
mov eax, [esi + 36] ;iy1
mov iy1, eax
;sse rounding mode RC=00B (MXCSR[14:13])
; stmxcsr pmxcsr
; and pmxcsr, 0FFFF9FFFh
; or pmxcsr, 000000000h
; ldmxcsr pmxcsr
;jump to AVX routine
; mov eax, [esi + 28] ; AVX flag
; and eax, 000000001h
; jnz USEAVX
;SSE
mov eax, [esi] ; &fcos
movss xmm0, real4 ptr [eax]
shufps xmm0, xmm0, 0
mov eax, [esi + 4]; &fsin
movss xmm1, real4 ptr [eax]
shufps xmm1, xmm1, 0
mov eax, [esi + 8]; &foffset
movss xmm7, real4 ptr [eax]
shufps xmm7, xmm7, 0
movaps xmm6, F3210
mov eax, iy1 ; iy1
dec eax
mov ecx, ixdimp
imul ecx
shl eax, 2 ; ixy = ixdimp * (iy1 - 1) * 4
add eax, [esi + 20]; ixy += ifp
mov edi, eax
mov ecx, [esi + 12]; ixdimpg
mov esi, [esi + 24]; igp
mov edx, iy1; iy<==iy1
dec edx
mov eax, 0
LOOPY:
mov ebx, ixdimp ; ix<==ixdimp
dec ebx
cvtsi2ss xmm3, edx ; xmm3<==iy
shufps xmm3, xmm3, 0 ; xmm3<==iy, iy, iy, iy
movaps xmm5, xmm1 ; xmm5<==fsin, fsin, fsin, fsin
mulps xmm5, xmm3 ; iy * fsin for each float
addps xmm5, xmm7 ; + foffset for each float
LOOPX:
cvtsi2ss xmm2, ebx ; xmm2<==ix
shufps xmm2, xmm2, 0 ; xmm2<==ix, ix, ix, ix
subps xmm2, xmm6 ; xmm2<==ix-3, ix-2, ix-2, ix
movaps xmm4, xmm0 ; xmm4<==fcos, fcos, fcos, fcos
mulps xmm4, xmm2 ; (ix-n) * fcos
addps xmm4, xmm5 ; (ix-n) * fcos + foffset
cvttps2dq xmm4, xmm4 ; xmm4 float*4 to integer32*4
movd eax, xmm4 ; lower 4 bytes to eax
; pextrd eax, xmm4, 0 ; SSE4.1
cmp eax, ecx ; ix<=>ixdimpg
jae LOOPXSKIP1 ; ix0 >= ixdimp * DBPT_GINTP or ix0 < 0
mov eax, [esi + eax * 4] ; eax<==igp[ix * DBPT_GINTP]
add [edi + ebx * 4], eax ; ifp[ix] += eax
LOOPXSKIP1:
dec ebx ; ix--
jl LOOPYEND ; ix < 0
psrldq xmm4, 4 ; shift right by 4 bytes (integer32)
movd eax, xmm4
; pextrd eax, xmm4, 1 ; SSE4.1
cmp eax, ecx; ixdimpg
jae LOOPXSKIP2 ; ix0 >= ixdimp * DBPT_GINTP or ix0 < 0
mov eax, [esi + eax * 4]
add [edi + ebx * 4], eax
LOOPXSKIP2:
dec ebx ; ix--
jl LOOPYEND ; ix < 0
psrldq xmm4, 4
movd eax, xmm4
; pextrd eax, xmm4, 2 ; SSE4.1
cmp eax, ecx; ixdimpg
jae LOOPXSKIP3 ; ix0 >= ixdimp * DBPT_GINTP or ix0 < 0
mov eax, [esi + eax * 4]
add [edi + ebx * 4], eax
LOOPXSKIP3:
dec ebx ; ix--
jl LOOPYEND ; ix < 0
psrldq xmm4, 4
movd eax, xmm4
; pextrd eax, xmm4, 3 ; SSE4.1
cmp eax, ecx; ixdimpg
jae LOOPXEND ; ix0 >= ixdimp * DBPT_GINTP or ix0 < 0
mov eax, [esi + eax * 4]
add [edi + ebx * 4], eax
LOOPXEND:
dec ebx
jge LOOPX ; ix >= 0
LOOPYEND:
sub edi, ixdimp4
dec edx
cmp edx, iy0
jge LOOPY ; iy >= iy0
; ldmxcsr smxcsr
pop ebp
pop ebx
pop edi
pop esi
ret
projx32 ENDP
end
| mizutanilab/RecView | source/projx32VS2008.asm | Assembly | bsd-2-clause | 3,655 |
;
; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
EXPORT |vp8_loop_filter_horizontal_edge_y_neon|
ARM
REQUIRE8
PRESERVE8
AREA ||.text||, CODE, READONLY, ALIGN=2
;Note: flimit, limit, and thresh shpuld be positive numbers. All 16 elements in flimit
;are equal. So, in the code, only one load is needed
;for flimit. Same way applies to limit and thresh.
; r0 unsigned char *s,
; r1 int p, //pitch
; r2 const signed char *flimit,
; r3 const signed char *limit,
; stack(r4) const signed char *thresh,
; //stack(r5) int count --unused
|vp8_loop_filter_horizontal_edge_y_neon| PROC
sub r0, r0, r1, lsl #2 ; move src pointer down by 4 lines
ldr r12, [sp, #0] ; load thresh pointer
vld1.u8 {q3}, [r0], r1 ; p3
vld1.s8 {d0[], d1[]}, [r2] ; flimit
vld1.u8 {q4}, [r0], r1 ; p2
vld1.s8 {d2[], d3[]}, [r3] ; limit
vld1.u8 {q5}, [r0], r1 ; p1
vld1.s8 {d4[], d5[]}, [r12] ; thresh
vld1.u8 {q6}, [r0], r1 ; p0
ldr r12, _lfhy_coeff_
vld1.u8 {q7}, [r0], r1 ; q0
;vp8_filter_mask() function
;vp8_hevmask() function
vabd.u8 q11, q3, q4 ; abs(p3 - p2)
vld1.u8 {q8}, [r0], r1 ; q1
vabd.u8 q12, q4, q5 ; abs(p2 - p1)
vld1.u8 {q9}, [r0], r1 ; q2
vabd.u8 q13, q5, q6 ; abs(p1 - p0)
vld1.u8 {q10}, [r0], r1 ; q3
vabd.u8 q14, q8, q7 ; abs(q1 - q0)
vabd.u8 q3, q9, q8 ; abs(q2 - q1)
vabd.u8 q4, q10, q9 ; abs(q3 - q2)
vabd.u8 q9, q6, q7 ; abs(p0 - q0)
vcge.u8 q15, q1, q11 ; (abs(p3 - p2) > limit)*-1
vcge.u8 q12, q1, q12 ; (abs(p2 - p1) > limit)*-1
vcge.u8 q10, q1, q13 ; (abs(p1 - p0) > limit)*-1
vcge.u8 q11, q1, q14 ; (abs(q1 - q0) > limit)*-1
vcgt.u8 q13, q13, q2 ; (abs(p1 - p0) > thresh)*-1
vcgt.u8 q14, q14, q2 ; (abs(q1 - q0) > thresh)*-1
vcge.u8 q3, q1, q3 ; (abs(q2 - q1) > limit)*-1
vcge.u8 q4, q1, q4 ; (abs(q3 - q2) > limit)*-1
vadd.u8 q0, q0, q0 ; flimit * 2
vadd.u8 q0, q0, q1 ; flimit * 2 + limit
vand q15, q15, q12
vand q10, q10, q11
vand q3, q3, q4
vabd.u8 q2, q5, q8 ; abs(p1 - q1)
vqadd.u8 q9, q9, q9 ; abs(p0 - q0) * 2
vshr.u8 q2, q2, #1 ; abs(p1 - q1) / 2
vqadd.u8 q9, q9, q2 ; abs(p0 - q0) * 2 + abs(p1 - q1) / 2
vcge.u8 q9, q0, q9 ; (abs(p0 - q0)*2 + abs(p1-q1)/2 > flimit*2 + limit)*-1
vld1.u8 {q0}, [r12]!
vand q15, q15, q10
;vp8_filter() function
veor q7, q7, q0 ; qs0: q0 offset to convert to a signed value
veor q6, q6, q0 ; ps0: p0 offset to convert to a signed value
veor q5, q5, q0 ; ps1: p1 offset to convert to a signed value
veor q8, q8, q0 ; qs1: q1 offset to convert to a signed value
;;;;;;;;;;;;;;
vld1.u8 {q10}, [r12]!
;vqsub.s8 q2, q7, q6 ; ( qs0 - ps0)
vsubl.s8 q2, d14, d12 ; ( qs0 - ps0)
vsubl.s8 q11, d15, d13
vand q3, q3, q9
vmovl.u8 q4, d20
vqsub.s8 q1, q5, q8 ; vp8_filter = vp8_signed_char_clamp(ps1-qs1)
vorr q14, q13, q14 ; q14: vp8_hevmask
;vmul.i8 q2, q2, q10 ; 3 * ( qs0 - ps0)
vmul.i16 q2, q2, q4 ; 3 * ( qs0 - ps0)
vmul.i16 q11, q11, q4
vand q1, q1, q14 ; vp8_filter &= hev
vand q15, q15, q3 ; q15: vp8_filter_mask
;;
;vld1.u8 {q4}, [r12]! ;no need 7 any more
;vqadd.s8 q1, q1, q2
vaddw.s8 q2, q2, d2
vaddw.s8 q11, q11, d3
vld1.u8 {q9}, [r12]!
;
vqmovn.s16 d2, q2 ; vp8_filter = vp8_signed_char_clamp(vp8_filter + 3 * ( qs0 - ps0))
vqmovn.s16 d3, q11
;;
vand q1, q1, q15 ; vp8_filter &= mask
;;
;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;Change for VP8 from VP7
; vand q2, q1, q4 ; s = vp8_filter & 7
; vqadd.s8 q1, q1, q9 ; vp8_filter = vp8_signed_char_clamp(vp8_filter+4)
;;;;
; vshr.s8 q1, q1, #3 ; vp8_filter >>= 3
; vceq.i8 q2, q2, q9 ; s = (s==4)*-1
;;
; ;calculate output
; vqsub.s8 q10, q7, q1 ; u = vp8_signed_char_clamp(qs0 - vp8_filter)
; vqadd.s8 q11, q2, q1 ; u = vp8_signed_char_clamp(s + vp8_filter)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; q10=3
vqadd.s8 q2, q1, q10 ; Filter2 = vp8_signed_char_clamp(vp8_filter+3)
vqadd.s8 q1, q1, q9 ; Filter1 = vp8_signed_char_clamp(vp8_filter+4)
vshr.s8 q2, q2, #3 ; Filter2 >>= 3
vshr.s8 q1, q1, #3 ; Filter1 >>= 3
;calculate output
vqadd.s8 q11, q6, q2 ; u = vp8_signed_char_clamp(ps0 + Filter2)
vqsub.s8 q10, q7, q1 ; u = vp8_signed_char_clamp(qs0 - Filter1)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vrshr.s8 q1, q1, #1 ;round/shift: vp8_filter += 1; vp8_filter >>= 1
sub r0, r0, r1, lsl #2
sub r0, r0, r1, lsl #1
;
vbic q1, q1, q14 ; vp8_filter &= ~hev
;
add r2, r1, r0
vqadd.s8 q13, q5, q1 ; u = vp8_signed_char_clamp(ps1 + vp8_filter)
;vqadd.s8 q11, q6, q11 ; u = vp8_signed_char_clamp(ps0 + u)
vqsub.s8 q12, q8, q1 ; u = vp8_signed_char_clamp(qs1 - vp8_filter)
add r3, r2, r1
veor q5, q13, q0 ; *op1 = u^0x80
veor q6, q11, q0 ; *op0 = u^0x80
veor q7, q10, q0 ; *oq0 = u^0x80
veor q8, q12, q0 ; *oq1 = u^0x80
add r12, r3, r1
vst1.u8 {q5}, [r0] ; store op1
vst1.u8 {q6}, [r2] ; store op0
vst1.u8 {q7}, [r3] ; store oq0
vst1.u8 {q8}, [r12] ; store oq1
bx lr
ENDP ; |vp8_loop_filter_horizontal_edge_y_neon|
;-----------------
AREA hloopfiltery_dat, DATA, READWRITE ;read/write by default
;Data section with name data_area is specified. DCD reserves space in memory for 16 data.
;One word each is reserved. Label filter_coeff can be used to access the data.
;Data address: filter_coeff, filter_coeff+4, filter_coeff+8 ...
_lfhy_coeff_
DCD lfhy_coeff
lfhy_coeff
DCD 0x80808080, 0x80808080, 0x80808080, 0x80808080
DCD 0x03030303, 0x03030303, 0x03030303, 0x03030303
DCD 0x04040404, 0x04040404, 0x04040404, 0x04040404
DCD 0x01010101, 0x01010101, 0x01010101, 0x01010101
END
| mrchapp/libvpx | vp8/common/arm/neon/loopfilterhorizontaledge_y_neon.asm | Assembly | bsd-3-clause | 7,777 |
/*
* All Video Processing kernels
* Copyright © <2010>, Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* This file was originally licensed under the following license
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
// Module name: readSampler16x1.asm
//
// Read one row of pix through sampler
//
//#define SAMPLER_MSG_DSC 0x166A0000 // ILK Sampler Message Descriptor
// Send Message [DevILK] Message Descriptor
// MBZ MsgL=5 MsgR=8 H MBZ SIMD MsgType SmplrIndx BindTab
// 000 0 101 0 1000 1 0 10 0000 0000 00000000
// 0 A 8 A 0 0 0 0
// MsgL=1+2*2(u,v)=5 MsgR=8
#define SAMPLER_MSG_DSC 0x0A8A0000 // ILK Sampler Message Descriptor
// Assume MSGSRC is set already in the caller
//mov (8) rMSGSRC.0<1>:ud 0:ud // Unused fileds
// Read 16 sampled pixels and stored them in float32 in 8 GRFs
// 422 data is expanded to 444, return 8 GRF in the order of RGB- (UYV-).
// 420 data has three surfaces, return 8 GRF. Valid is always in the 1st GRF when in R8. Make sure no overwrite the following 3 GRFs.
// alpha data is expanded to 4444, return 8 GRF in the order of RGBA (UYVA).
mov(16) mMSGHDR<1>:uw rMSGSRC<16;16,1>:uw
send (16) DATABUF(0)<1> mMSGHDR udDUMMY_NULL 0x2 SAMPLER_MSG_DSC+SAMPLER_IDX+BINDING_IDX:ud
| uartie/vaapi-intel-driver | src/shaders/post_processing/gen5_6/Common/readSampler16x1.asm | Assembly | mit | 3,177 |
section ".data"
xdef pSnd_GetNote_voice1
pSnd_GetNote_voice1:
move.b note_voice1,d0
rts | bcherry/bcherry | oldstuff/tigcc/PolySnd/sources/statique/GetNote_voice1.asm | Assembly | mit | 92 |
;--------------------------------------------------
; Sp-3DPrinter -- A 3D printer
; By SirPython of Code Review and GitHub
;
; SP-3DPrinter.asm
;-------------------------------------------------- | SirPython/SP-3DPrinter | SP-3DPrinter/SP-3DPrinter/SP-3DPrinter.asm | Assembly | mit | 196 |
INCLUDE "hardware.inc"
INCLUDE "header.inc"
;--------------------------------------------------------------------------
SECTION "VAR",BSS
int_repetition: DS 1
SECTION "Main",HOME
;--------------------------------------------------------------------------
;- Main() -
;--------------------------------------------------------------------------
Main:
; -------------------------------------------------------
ld a,$0A
ld [$0000],a ; enable ram
ld hl,$A000
; -------------------------------------------------------
PERFORM_TEST_HALT : MACRO
di
push hl
xor a,a
ld [int_repetition],a
ld bc,$0200
ld hl,\1
ld de,$D000
call memcopy
ld a,TACF_START|TACF_262KHZ
ld [rTAC],a
xor a,a
ld c,rDIV & $FF
ld hl,rTIMA
ld a,$F0
ld [rTMA],a
ld [$FF00+c],a
ld [hl],a
ld [$FF00+c],a
ld [hl],a
ld a,IEF_TIMER
ld [rIE],a
xor a,a
ld [rIF],a
pop hl
ei
halt
ENDM
PERFORM_TEST_NO_HALT : MACRO
di
push hl
xor a,a
ld [int_repetition],a
ld bc,$0200
ld hl,\1
ld de,$D000
call memcopy
ld a,TACF_START|TACF_262KHZ
ld [rTAC],a
xor a,a
ld c,rDIV & $FF
ld hl,rTIMA
ld a,$F0
ld [rTMA],a
ld [$FF00+c],a
ld [hl],a
ld [$FF00+c],a
ld [hl],a
ld a,IEF_TIMER
ld [rIE],a
xor a,a
ld [rIF],a
pop hl
ei
REPT 50
nop
ENDR
ENDM
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$82
ld [rNR14],a
PERFORM_TEST_HALT TIMER_INT_HANDLER_0
PERFORM_TEST_HALT TIMER_INT_HANDLER_1
PERFORM_TEST_HALT TIMER_INT_HANDLER_2
PERFORM_TEST_HALT TIMER_INT_HANDLER_3
PERFORM_TEST_HALT TIMER_INT_HANDLER_4
PERFORM_TEST_HALT TIMER_INT_HANDLER_5
PERFORM_TEST_HALT TIMER_INT_HANDLER_6
PERFORM_TEST_HALT TIMER_INT_HANDLER_7
PERFORM_TEST_HALT TIMER_INT_HANDLER_8
PERFORM_TEST_HALT TIMER_INT_HANDLER_9
PERFORM_TEST_HALT TIMER_INT_HANDLER_10
PERFORM_TEST_HALT TIMER_INT_HANDLER_11
PERFORM_TEST_HALT TIMER_INT_HANDLER_12
PERFORM_TEST_HALT TIMER_INT_HANDLER_13
PERFORM_TEST_HALT TIMER_INT_HANDLER_14
PERFORM_TEST_HALT TIMER_INT_HANDLER_15
PERFORM_TEST_HALT TIMER_INT_HANDLER_16
PERFORM_TEST_HALT TIMER_INT_HANDLER_17
PERFORM_TEST_HALT TIMER_INT_HANDLER_18
PERFORM_TEST_HALT TIMER_INT_HANDLER_19
PERFORM_TEST_HALT TIMER_INT_HANDLER_20
PERFORM_TEST_HALT TIMER_INT_HANDLER_21
PERFORM_TEST_HALT TIMER_INT_HANDLER_22
PERFORM_TEST_HALT TIMER_INT_HANDLER_23
PERFORM_TEST_HALT TIMER_INT_HANDLER_24
PERFORM_TEST_HALT TIMER_INT_HANDLER_25
PERFORM_TEST_HALT TIMER_INT_HANDLER_26
PERFORM_TEST_HALT TIMER_INT_HANDLER_27
PERFORM_TEST_HALT TIMER_INT_HANDLER_28
PERFORM_TEST_HALT TIMER_INT_HANDLER_29
PERFORM_TEST_HALT TIMER_INT_HANDLER_30
PERFORM_TEST_HALT TIMER_INT_HANDLER_31
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_0
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_1
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_2
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_3
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_4
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_5
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_6
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_7
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_8
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_9
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_10
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_11
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_12
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_13
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_14
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_15
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_16
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_17
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_18
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_19
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_20
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_21
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_22
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_23
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_24
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_25
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_26
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_27
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_28
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_29
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_30
PERFORM_TEST_NO_HALT TIMER_INT_HANDLER_31
; -------------------------------------------------------
ld a,$80
ld [rNR52],a
ld a,$FF
ld [rNR51],a
ld a,$77
ld [rNR50],a
ld a,$C0
ld [rNR11],a
ld a,$E0
ld [rNR12],a
ld a,$00
ld [rNR13],a
ld a,$87
ld [rNR14],a
push hl
ld [hl],$12
inc hl
ld [hl],$34
inc hl
ld [hl],$56
inc hl
ld [hl],$78
pop hl
ld a,$00
ld [$0000],a ; disable ram
.endloop:
halt
jr .endloop
; --------------------------------------------------------------
SECTION "functions",ROMX,BANK[1]
TIMER_INT_HANDLER_MACRO : MACRO
ld a,[int_repetition]
cp a,1
jr z,.is_1\@
ld a,1
ld [int_repetition],a
push de
pop de
push de
pop de ; delay
ld b,0
ei
REPT \1
inc b
ENDR
di
ret
.is_1\@:
ld a,b
ld [hl+],a
ld a,[rTIMA]
ld [hl+],a
nop
ld a,[rTIMA]
ld [hl+],a
nop
ld a,[rTIMA]
ld [hl+],a
nop
ld a,[rTIMA]
ld [hl+],a
nop
ret
ENDM
TIMER_INT_HANDLER_0: TIMER_INT_HANDLER_MACRO 0
TIMER_INT_HANDLER_1: TIMER_INT_HANDLER_MACRO 1
TIMER_INT_HANDLER_2: TIMER_INT_HANDLER_MACRO 2
TIMER_INT_HANDLER_3: TIMER_INT_HANDLER_MACRO 3
TIMER_INT_HANDLER_4: TIMER_INT_HANDLER_MACRO 4
TIMER_INT_HANDLER_5: TIMER_INT_HANDLER_MACRO 5
TIMER_INT_HANDLER_6: TIMER_INT_HANDLER_MACRO 6
TIMER_INT_HANDLER_7: TIMER_INT_HANDLER_MACRO 7
TIMER_INT_HANDLER_8: TIMER_INT_HANDLER_MACRO 8
TIMER_INT_HANDLER_9: TIMER_INT_HANDLER_MACRO 9
TIMER_INT_HANDLER_10: TIMER_INT_HANDLER_MACRO 10
TIMER_INT_HANDLER_11: TIMER_INT_HANDLER_MACRO 11
TIMER_INT_HANDLER_12: TIMER_INT_HANDLER_MACRO 12
TIMER_INT_HANDLER_13: TIMER_INT_HANDLER_MACRO 13
TIMER_INT_HANDLER_14: TIMER_INT_HANDLER_MACRO 14
TIMER_INT_HANDLER_15: TIMER_INT_HANDLER_MACRO 15
TIMER_INT_HANDLER_16: TIMER_INT_HANDLER_MACRO 16
TIMER_INT_HANDLER_17: TIMER_INT_HANDLER_MACRO 17
TIMER_INT_HANDLER_18: TIMER_INT_HANDLER_MACRO 18
TIMER_INT_HANDLER_19: TIMER_INT_HANDLER_MACRO 19
TIMER_INT_HANDLER_20: TIMER_INT_HANDLER_MACRO 20
TIMER_INT_HANDLER_21: TIMER_INT_HANDLER_MACRO 21
TIMER_INT_HANDLER_22: TIMER_INT_HANDLER_MACRO 22
TIMER_INT_HANDLER_23: TIMER_INT_HANDLER_MACRO 23
TIMER_INT_HANDLER_24: TIMER_INT_HANDLER_MACRO 24
TIMER_INT_HANDLER_25: TIMER_INT_HANDLER_MACRO 25
TIMER_INT_HANDLER_26: TIMER_INT_HANDLER_MACRO 26
TIMER_INT_HANDLER_27: TIMER_INT_HANDLER_MACRO 27
TIMER_INT_HANDLER_28: TIMER_INT_HANDLER_MACRO 28
TIMER_INT_HANDLER_29: TIMER_INT_HANDLER_MACRO 29
TIMER_INT_HANDLER_30: TIMER_INT_HANDLER_MACRO 30
TIMER_INT_HANDLER_31: TIMER_INT_HANDLER_MACRO 31
; --------------------------------------------------------------
| AntonioND/gbc-hw-tests | interrupts/timer_int_handle_timing_dmg_mode/main.asm | Assembly | mit | 6,661 |
.if $defined(__MSPGCC__)
.macro twoNOPs
NOP
NOP
.endm
.macro NOPx2
NOP;
NOP;
.endm
.macro NOPx3
NOP;
NOP;
NOP;
.endm
.macro NOPx4
NOPx2
NOPx2
.endm
.macro NOPx5
NOPx4
NOP
.endm
.macro NOPx6
NOPx5
NOP;
.endm
.macro NOPx7
NOPx5
NOPx2;
.endm
.macro NOPx9
NOPx5
NOPx4;
.endm
.macro NOPx10
NOPx5;
NOPx5;
.endm
.macro NOPx11
NOPx10;
NOP;
.endm
.macro NOPx13
NOPx10;
NOPx3;
.endm
.macro NOPx14
NOPx10;
NOPx3;
.endm
.macro NOPx15
NOPx10;
NOPx5;
.endm
.macro NOPx18
NOPx15;
NOPx3;
.endm
.macro NOPx20
NOPx10;
NOPx10;
.endm
.macro NOPx22
NOPx20;
NOPx2;
.endm
.macro NOPx23
NOPx22;
NOP;
.endm
.macro NOPx25
NOPx15;
NOPx10;
.endm
.macro NOPx29
NOPx25;
NOPx4;
.endm
.macro NOPx30
NOPx15;
NOPx10;
.endm
.macro NOPx35
NOPx20;
NOPx15;
.endm
.macro NOPx36
NOPx35;
NOP
.endm
.macro NOPx40
NOPx20;
NOPx20;
.endm
.else
; For Code Composer Studio:
twoNOPs .macro
NOP
NOP
.endm
NOPx2 .macro
NOP;
NOP;
.endm
NOPx3 .macro
NOP;
NOP;
NOP;
.endm
NOPx4 .macro
NOPx2
NOPx2
.endm
NOPx5 .macro
NOPx4
NOP
.endm
NOPx6 .macro
NOPx5
NOP;
.endm
NOPx7 .macro
NOPx5
NOPx2;
.endm
NOPx9 .macro
NOPx5
NOPx4;
.endm
NOPx10 .macro
NOPx5;
NOPx5;
.endm
NOPx11 .macro
NOPx10;
NOP;
.endm
NOPx13 .macro
NOPx10;
NOPx3;
.endm
NOPx14 .macro
NOPx10;
NOPx3;
.endm
NOPx15 .macro
NOPx10;
NOPx5;
.endm
NOPx18 .macro
NOPx15;
NOPx3;
.endm
NOPx20 .macro
NOPx10;
NOPx10;
.endm
NOPx22 .macro
NOPx20;
NOPx2;
.endm
NOPx23 .macro
NOPx22;
NOP;
.endm
NOPx25 .macro
NOPx15;
NOPx10;
.endm
NOPx29 .macro
NOPx25;
NOPx4;
.endm
NOPx30 .macro
NOPx15;
NOPx10;
.endm
NOPx35 .macro
NOPx20;
NOPx15;
.endm
NOPx36 .macro
NOPx35;
NOP
.endm
NOPx40 .macro
NOPx20;
NOPx20;
.endm
.endif
| amjadmajid/stork | CRFID_firmware/STORKfull/wisp-base/internals/NOPdefs.asm | Assembly | bsd-3-clause | 2,538 |
push 1
push 0
st_em 0x0,2,0
push 0
ld_em 0x0,2,0
push 0
sethi 0x0200
st_em 0x0,2,0
push 0
push 1
push 2
push 3
push 4
push 5
push 6
push 7
push 8
push 9
push 10
push 11
push 12
push 13
push 14
push 15
push 16
push 17
push 0
ld_em 0x0,2,0
push 1
add
push 0
st_em 0x0,2,0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
drop 0
halt | ilebedev/stacktool | tests/emra/EM_MODE/asm_for_rb/EM02.asm | Assembly | mit | 400 |
; ==== STM32F30x PERIPHERALS =================================
;
; CTU Prague, FEL, Department of Measurement
;
; ------------------------------------------------------------
;
; Generated from "STM32F30x.svd"
;
; SVD parsing library (c) Paul Osborne, 2015-2016
; https://github.com/posborne/cmsis-svd
; ASM building script (c) Ondrej Hruska, 2016
;
; ============================================================
; ---- GPIOA -------------------------------------------------
; Desc: General-purpose I/Os
; GPIOA base address:
GPIOA_BASE EQU 0x48000000
; GPIOA registers:
GPIOA_MODER EQU (GPIOA_BASE + 0x0) ; GPIO port mode register
GPIOA_OTYPER EQU (GPIOA_BASE + 0x4) ; GPIO port output type register
GPIOA_OSPEEDR EQU (GPIOA_BASE + 0x8) ; GPIO port output speed register
GPIOA_PUPDR EQU (GPIOA_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOA_IDR EQU (GPIOA_BASE + 0x10) ; GPIO port input data register
GPIOA_ODR EQU (GPIOA_BASE + 0x14) ; GPIO port output data register
GPIOA_BSRR EQU (GPIOA_BASE + 0x18) ; GPIO port bit set/reset register
GPIOA_LCKR EQU (GPIOA_BASE + 0x1c) ; GPIO port configuration lock register
GPIOA_AFRL EQU (GPIOA_BASE + 0x20) ; GPIO alternate function low register
GPIOA_AFRH EQU (GPIOA_BASE + 0x24) ; GPIO alternate function high register
GPIOA_BRR EQU (GPIOA_BASE + 0x28) ; Port bit reset register
; GPIOA_MODER fields:
GPIO_MODER_MODER15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER15_ofs EQU 30
GPIO_MODER_MODER15_len EQU 2
GPIO_MODER_MODER14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER14_ofs EQU 28
GPIO_MODER_MODER14_len EQU 2
GPIO_MODER_MODER13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER13_ofs EQU 26
GPIO_MODER_MODER13_len EQU 2
GPIO_MODER_MODER12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER12_ofs EQU 24
GPIO_MODER_MODER12_len EQU 2
GPIO_MODER_MODER11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER11_ofs EQU 22
GPIO_MODER_MODER11_len EQU 2
GPIO_MODER_MODER10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER10_ofs EQU 20
GPIO_MODER_MODER10_len EQU 2
GPIO_MODER_MODER9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER9_ofs EQU 18
GPIO_MODER_MODER9_len EQU 2
GPIO_MODER_MODER8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER8_ofs EQU 16
GPIO_MODER_MODER8_len EQU 2
GPIO_MODER_MODER7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER7_ofs EQU 14
GPIO_MODER_MODER7_len EQU 2
GPIO_MODER_MODER6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER6_ofs EQU 12
GPIO_MODER_MODER6_len EQU 2
GPIO_MODER_MODER5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER5_ofs EQU 10
GPIO_MODER_MODER5_len EQU 2
GPIO_MODER_MODER4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER4_ofs EQU 8
GPIO_MODER_MODER4_len EQU 2
GPIO_MODER_MODER3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER3_ofs EQU 6
GPIO_MODER_MODER3_len EQU 2
GPIO_MODER_MODER2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER2_ofs EQU 4
GPIO_MODER_MODER2_len EQU 2
GPIO_MODER_MODER1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER1_ofs EQU 2
GPIO_MODER_MODER1_len EQU 2
GPIO_MODER_MODER0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_MODER_MODER0_ofs EQU 0
GPIO_MODER_MODER0_len EQU 2
; GPIOA_OTYPER fields:
GPIO_OTYPER_OT15 EQU 0x00008000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT15_ofs EQU 15
GPIO_OTYPER_OT15_len EQU 1
GPIO_OTYPER_OT14 EQU 0x00004000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT14_ofs EQU 14
GPIO_OTYPER_OT14_len EQU 1
GPIO_OTYPER_OT13 EQU 0x00002000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT13_ofs EQU 13
GPIO_OTYPER_OT13_len EQU 1
GPIO_OTYPER_OT12 EQU 0x00001000 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT12_ofs EQU 12
GPIO_OTYPER_OT12_len EQU 1
GPIO_OTYPER_OT11 EQU 0x00000800 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT11_ofs EQU 11
GPIO_OTYPER_OT11_len EQU 1
GPIO_OTYPER_OT10 EQU 0x00000400 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT10_ofs EQU 10
GPIO_OTYPER_OT10_len EQU 1
GPIO_OTYPER_OT9 EQU 0x00000200 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT9_ofs EQU 9
GPIO_OTYPER_OT9_len EQU 1
GPIO_OTYPER_OT8 EQU 0x00000100 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT8_ofs EQU 8
GPIO_OTYPER_OT8_len EQU 1
GPIO_OTYPER_OT7 EQU 0x00000080 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT7_ofs EQU 7
GPIO_OTYPER_OT7_len EQU 1
GPIO_OTYPER_OT6 EQU 0x00000040 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT6_ofs EQU 6
GPIO_OTYPER_OT6_len EQU 1
GPIO_OTYPER_OT5 EQU 0x00000020 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT5_ofs EQU 5
GPIO_OTYPER_OT5_len EQU 1
GPIO_OTYPER_OT4 EQU 0x00000010 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT4_ofs EQU 4
GPIO_OTYPER_OT4_len EQU 1
GPIO_OTYPER_OT3 EQU 0x00000008 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT3_ofs EQU 3
GPIO_OTYPER_OT3_len EQU 1
GPIO_OTYPER_OT2 EQU 0x00000004 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT2_ofs EQU 2
GPIO_OTYPER_OT2_len EQU 1
GPIO_OTYPER_OT1 EQU 0x00000002 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT1_ofs EQU 1
GPIO_OTYPER_OT1_len EQU 1
GPIO_OTYPER_OT0 EQU 0x00000001 ; Port x configuration bits (y = 0..15)
GPIO_OTYPER_OT0_ofs EQU 0
GPIO_OTYPER_OT0_len EQU 1
; GPIOA_OSPEEDR fields:
GPIO_OSPEEDR_OSPEEDR15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR15_ofs EQU 30
GPIO_OSPEEDR_OSPEEDR15_len EQU 2
GPIO_OSPEEDR_OSPEEDR14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR14_ofs EQU 28
GPIO_OSPEEDR_OSPEEDR14_len EQU 2
GPIO_OSPEEDR_OSPEEDR13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR13_ofs EQU 26
GPIO_OSPEEDR_OSPEEDR13_len EQU 2
GPIO_OSPEEDR_OSPEEDR12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR12_ofs EQU 24
GPIO_OSPEEDR_OSPEEDR12_len EQU 2
GPIO_OSPEEDR_OSPEEDR11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR11_ofs EQU 22
GPIO_OSPEEDR_OSPEEDR11_len EQU 2
GPIO_OSPEEDR_OSPEEDR10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR10_ofs EQU 20
GPIO_OSPEEDR_OSPEEDR10_len EQU 2
GPIO_OSPEEDR_OSPEEDR9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR9_ofs EQU 18
GPIO_OSPEEDR_OSPEEDR9_len EQU 2
GPIO_OSPEEDR_OSPEEDR8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR8_ofs EQU 16
GPIO_OSPEEDR_OSPEEDR8_len EQU 2
GPIO_OSPEEDR_OSPEEDR7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR7_ofs EQU 14
GPIO_OSPEEDR_OSPEEDR7_len EQU 2
GPIO_OSPEEDR_OSPEEDR6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR6_ofs EQU 12
GPIO_OSPEEDR_OSPEEDR6_len EQU 2
GPIO_OSPEEDR_OSPEEDR5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR5_ofs EQU 10
GPIO_OSPEEDR_OSPEEDR5_len EQU 2
GPIO_OSPEEDR_OSPEEDR4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR4_ofs EQU 8
GPIO_OSPEEDR_OSPEEDR4_len EQU 2
GPIO_OSPEEDR_OSPEEDR3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR3_ofs EQU 6
GPIO_OSPEEDR_OSPEEDR3_len EQU 2
GPIO_OSPEEDR_OSPEEDR2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR2_ofs EQU 4
GPIO_OSPEEDR_OSPEEDR2_len EQU 2
GPIO_OSPEEDR_OSPEEDR1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR1_ofs EQU 2
GPIO_OSPEEDR_OSPEEDR1_len EQU 2
GPIO_OSPEEDR_OSPEEDR0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_OSPEEDR_OSPEEDR0_ofs EQU 0
GPIO_OSPEEDR_OSPEEDR0_len EQU 2
; GPIOA_PUPDR fields:
GPIO_PUPDR_PUPDR15 EQU 0xc0000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR15_ofs EQU 30
GPIO_PUPDR_PUPDR15_len EQU 2
GPIO_PUPDR_PUPDR14 EQU 0x30000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR14_ofs EQU 28
GPIO_PUPDR_PUPDR14_len EQU 2
GPIO_PUPDR_PUPDR13 EQU 0x0c000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR13_ofs EQU 26
GPIO_PUPDR_PUPDR13_len EQU 2
GPIO_PUPDR_PUPDR12 EQU 0x03000000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR12_ofs EQU 24
GPIO_PUPDR_PUPDR12_len EQU 2
GPIO_PUPDR_PUPDR11 EQU 0x00c00000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR11_ofs EQU 22
GPIO_PUPDR_PUPDR11_len EQU 2
GPIO_PUPDR_PUPDR10 EQU 0x00300000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR10_ofs EQU 20
GPIO_PUPDR_PUPDR10_len EQU 2
GPIO_PUPDR_PUPDR9 EQU 0x000c0000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR9_ofs EQU 18
GPIO_PUPDR_PUPDR9_len EQU 2
GPIO_PUPDR_PUPDR8 EQU 0x00030000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR8_ofs EQU 16
GPIO_PUPDR_PUPDR8_len EQU 2
GPIO_PUPDR_PUPDR7 EQU 0x0000c000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR7_ofs EQU 14
GPIO_PUPDR_PUPDR7_len EQU 2
GPIO_PUPDR_PUPDR6 EQU 0x00003000 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR6_ofs EQU 12
GPIO_PUPDR_PUPDR6_len EQU 2
GPIO_PUPDR_PUPDR5 EQU 0x00000c00 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR5_ofs EQU 10
GPIO_PUPDR_PUPDR5_len EQU 2
GPIO_PUPDR_PUPDR4 EQU 0x00000300 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR4_ofs EQU 8
GPIO_PUPDR_PUPDR4_len EQU 2
GPIO_PUPDR_PUPDR3 EQU 0x000000c0 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR3_ofs EQU 6
GPIO_PUPDR_PUPDR3_len EQU 2
GPIO_PUPDR_PUPDR2 EQU 0x00000030 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR2_ofs EQU 4
GPIO_PUPDR_PUPDR2_len EQU 2
GPIO_PUPDR_PUPDR1 EQU 0x0000000c ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR1_ofs EQU 2
GPIO_PUPDR_PUPDR1_len EQU 2
GPIO_PUPDR_PUPDR0 EQU 0x00000003 ; Port x configuration bits (y = 0..15)
GPIO_PUPDR_PUPDR0_ofs EQU 0
GPIO_PUPDR_PUPDR0_len EQU 2
; GPIOA_IDR fields:
GPIO_IDR_IDR15 EQU 0x00008000 ; Port input data (y = 0..15)
GPIO_IDR_IDR15_ofs EQU 15
GPIO_IDR_IDR15_len EQU 1
GPIO_IDR_IDR14 EQU 0x00004000 ; Port input data (y = 0..15)
GPIO_IDR_IDR14_ofs EQU 14
GPIO_IDR_IDR14_len EQU 1
GPIO_IDR_IDR13 EQU 0x00002000 ; Port input data (y = 0..15)
GPIO_IDR_IDR13_ofs EQU 13
GPIO_IDR_IDR13_len EQU 1
GPIO_IDR_IDR12 EQU 0x00001000 ; Port input data (y = 0..15)
GPIO_IDR_IDR12_ofs EQU 12
GPIO_IDR_IDR12_len EQU 1
GPIO_IDR_IDR11 EQU 0x00000800 ; Port input data (y = 0..15)
GPIO_IDR_IDR11_ofs EQU 11
GPIO_IDR_IDR11_len EQU 1
GPIO_IDR_IDR10 EQU 0x00000400 ; Port input data (y = 0..15)
GPIO_IDR_IDR10_ofs EQU 10
GPIO_IDR_IDR10_len EQU 1
GPIO_IDR_IDR9 EQU 0x00000200 ; Port input data (y = 0..15)
GPIO_IDR_IDR9_ofs EQU 9
GPIO_IDR_IDR9_len EQU 1
GPIO_IDR_IDR8 EQU 0x00000100 ; Port input data (y = 0..15)
GPIO_IDR_IDR8_ofs EQU 8
GPIO_IDR_IDR8_len EQU 1
GPIO_IDR_IDR7 EQU 0x00000080 ; Port input data (y = 0..15)
GPIO_IDR_IDR7_ofs EQU 7
GPIO_IDR_IDR7_len EQU 1
GPIO_IDR_IDR6 EQU 0x00000040 ; Port input data (y = 0..15)
GPIO_IDR_IDR6_ofs EQU 6
GPIO_IDR_IDR6_len EQU 1
GPIO_IDR_IDR5 EQU 0x00000020 ; Port input data (y = 0..15)
GPIO_IDR_IDR5_ofs EQU 5
GPIO_IDR_IDR5_len EQU 1
GPIO_IDR_IDR4 EQU 0x00000010 ; Port input data (y = 0..15)
GPIO_IDR_IDR4_ofs EQU 4
GPIO_IDR_IDR4_len EQU 1
GPIO_IDR_IDR3 EQU 0x00000008 ; Port input data (y = 0..15)
GPIO_IDR_IDR3_ofs EQU 3
GPIO_IDR_IDR3_len EQU 1
GPIO_IDR_IDR2 EQU 0x00000004 ; Port input data (y = 0..15)
GPIO_IDR_IDR2_ofs EQU 2
GPIO_IDR_IDR2_len EQU 1
GPIO_IDR_IDR1 EQU 0x00000002 ; Port input data (y = 0..15)
GPIO_IDR_IDR1_ofs EQU 1
GPIO_IDR_IDR1_len EQU 1
GPIO_IDR_IDR0 EQU 0x00000001 ; Port input data (y = 0..15)
GPIO_IDR_IDR0_ofs EQU 0
GPIO_IDR_IDR0_len EQU 1
; GPIOA_ODR fields:
GPIO_ODR_ODR15 EQU 0x00008000 ; Port output data (y = 0..15)
GPIO_ODR_ODR15_ofs EQU 15
GPIO_ODR_ODR15_len EQU 1
GPIO_ODR_ODR14 EQU 0x00004000 ; Port output data (y = 0..15)
GPIO_ODR_ODR14_ofs EQU 14
GPIO_ODR_ODR14_len EQU 1
GPIO_ODR_ODR13 EQU 0x00002000 ; Port output data (y = 0..15)
GPIO_ODR_ODR13_ofs EQU 13
GPIO_ODR_ODR13_len EQU 1
GPIO_ODR_ODR12 EQU 0x00001000 ; Port output data (y = 0..15)
GPIO_ODR_ODR12_ofs EQU 12
GPIO_ODR_ODR12_len EQU 1
GPIO_ODR_ODR11 EQU 0x00000800 ; Port output data (y = 0..15)
GPIO_ODR_ODR11_ofs EQU 11
GPIO_ODR_ODR11_len EQU 1
GPIO_ODR_ODR10 EQU 0x00000400 ; Port output data (y = 0..15)
GPIO_ODR_ODR10_ofs EQU 10
GPIO_ODR_ODR10_len EQU 1
GPIO_ODR_ODR9 EQU 0x00000200 ; Port output data (y = 0..15)
GPIO_ODR_ODR9_ofs EQU 9
GPIO_ODR_ODR9_len EQU 1
GPIO_ODR_ODR8 EQU 0x00000100 ; Port output data (y = 0..15)
GPIO_ODR_ODR8_ofs EQU 8
GPIO_ODR_ODR8_len EQU 1
GPIO_ODR_ODR7 EQU 0x00000080 ; Port output data (y = 0..15)
GPIO_ODR_ODR7_ofs EQU 7
GPIO_ODR_ODR7_len EQU 1
GPIO_ODR_ODR6 EQU 0x00000040 ; Port output data (y = 0..15)
GPIO_ODR_ODR6_ofs EQU 6
GPIO_ODR_ODR6_len EQU 1
GPIO_ODR_ODR5 EQU 0x00000020 ; Port output data (y = 0..15)
GPIO_ODR_ODR5_ofs EQU 5
GPIO_ODR_ODR5_len EQU 1
GPIO_ODR_ODR4 EQU 0x00000010 ; Port output data (y = 0..15)
GPIO_ODR_ODR4_ofs EQU 4
GPIO_ODR_ODR4_len EQU 1
GPIO_ODR_ODR3 EQU 0x00000008 ; Port output data (y = 0..15)
GPIO_ODR_ODR3_ofs EQU 3
GPIO_ODR_ODR3_len EQU 1
GPIO_ODR_ODR2 EQU 0x00000004 ; Port output data (y = 0..15)
GPIO_ODR_ODR2_ofs EQU 2
GPIO_ODR_ODR2_len EQU 1
GPIO_ODR_ODR1 EQU 0x00000002 ; Port output data (y = 0..15)
GPIO_ODR_ODR1_ofs EQU 1
GPIO_ODR_ODR1_len EQU 1
GPIO_ODR_ODR0 EQU 0x00000001 ; Port output data (y = 0..15)
GPIO_ODR_ODR0_ofs EQU 0
GPIO_ODR_ODR0_len EQU 1
; GPIOA_BSRR fields:
GPIO_BSRR_BR15 EQU 0x80000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR15_ofs EQU 31
GPIO_BSRR_BR15_len EQU 1
GPIO_BSRR_BR14 EQU 0x40000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR14_ofs EQU 30
GPIO_BSRR_BR14_len EQU 1
GPIO_BSRR_BR13 EQU 0x20000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR13_ofs EQU 29
GPIO_BSRR_BR13_len EQU 1
GPIO_BSRR_BR12 EQU 0x10000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR12_ofs EQU 28
GPIO_BSRR_BR12_len EQU 1
GPIO_BSRR_BR11 EQU 0x08000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR11_ofs EQU 27
GPIO_BSRR_BR11_len EQU 1
GPIO_BSRR_BR10 EQU 0x04000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR10_ofs EQU 26
GPIO_BSRR_BR10_len EQU 1
GPIO_BSRR_BR9 EQU 0x02000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR9_ofs EQU 25
GPIO_BSRR_BR9_len EQU 1
GPIO_BSRR_BR8 EQU 0x01000000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR8_ofs EQU 24
GPIO_BSRR_BR8_len EQU 1
GPIO_BSRR_BR7 EQU 0x00800000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR7_ofs EQU 23
GPIO_BSRR_BR7_len EQU 1
GPIO_BSRR_BR6 EQU 0x00400000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR6_ofs EQU 22
GPIO_BSRR_BR6_len EQU 1
GPIO_BSRR_BR5 EQU 0x00200000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR5_ofs EQU 21
GPIO_BSRR_BR5_len EQU 1
GPIO_BSRR_BR4 EQU 0x00100000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR4_ofs EQU 20
GPIO_BSRR_BR4_len EQU 1
GPIO_BSRR_BR3 EQU 0x00080000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR3_ofs EQU 19
GPIO_BSRR_BR3_len EQU 1
GPIO_BSRR_BR2 EQU 0x00040000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR2_ofs EQU 18
GPIO_BSRR_BR2_len EQU 1
GPIO_BSRR_BR1 EQU 0x00020000 ; Port x reset bit y (y = 0..15)
GPIO_BSRR_BR1_ofs EQU 17
GPIO_BSRR_BR1_len EQU 1
GPIO_BSRR_BR0 EQU 0x00010000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BR0_ofs EQU 16
GPIO_BSRR_BR0_len EQU 1
GPIO_BSRR_BS15 EQU 0x00008000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS15_ofs EQU 15
GPIO_BSRR_BS15_len EQU 1
GPIO_BSRR_BS14 EQU 0x00004000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS14_ofs EQU 14
GPIO_BSRR_BS14_len EQU 1
GPIO_BSRR_BS13 EQU 0x00002000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS13_ofs EQU 13
GPIO_BSRR_BS13_len EQU 1
GPIO_BSRR_BS12 EQU 0x00001000 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS12_ofs EQU 12
GPIO_BSRR_BS12_len EQU 1
GPIO_BSRR_BS11 EQU 0x00000800 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS11_ofs EQU 11
GPIO_BSRR_BS11_len EQU 1
GPIO_BSRR_BS10 EQU 0x00000400 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS10_ofs EQU 10
GPIO_BSRR_BS10_len EQU 1
GPIO_BSRR_BS9 EQU 0x00000200 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS9_ofs EQU 9
GPIO_BSRR_BS9_len EQU 1
GPIO_BSRR_BS8 EQU 0x00000100 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS8_ofs EQU 8
GPIO_BSRR_BS8_len EQU 1
GPIO_BSRR_BS7 EQU 0x00000080 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS7_ofs EQU 7
GPIO_BSRR_BS7_len EQU 1
GPIO_BSRR_BS6 EQU 0x00000040 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS6_ofs EQU 6
GPIO_BSRR_BS6_len EQU 1
GPIO_BSRR_BS5 EQU 0x00000020 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS5_ofs EQU 5
GPIO_BSRR_BS5_len EQU 1
GPIO_BSRR_BS4 EQU 0x00000010 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS4_ofs EQU 4
GPIO_BSRR_BS4_len EQU 1
GPIO_BSRR_BS3 EQU 0x00000008 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS3_ofs EQU 3
GPIO_BSRR_BS3_len EQU 1
GPIO_BSRR_BS2 EQU 0x00000004 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS2_ofs EQU 2
GPIO_BSRR_BS2_len EQU 1
GPIO_BSRR_BS1 EQU 0x00000002 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS1_ofs EQU 1
GPIO_BSRR_BS1_len EQU 1
GPIO_BSRR_BS0 EQU 0x00000001 ; Port x set bit y (y= 0..15)
GPIO_BSRR_BS0_ofs EQU 0
GPIO_BSRR_BS0_len EQU 1
; GPIOA_LCKR fields:
GPIO_LCKR_LCKK EQU 0x00010000 ; Lok Key
GPIO_LCKR_LCKK_ofs EQU 16
GPIO_LCKR_LCKK_len EQU 1
GPIO_LCKR_LCK15 EQU 0x00008000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK15_ofs EQU 15
GPIO_LCKR_LCK15_len EQU 1
GPIO_LCKR_LCK14 EQU 0x00004000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK14_ofs EQU 14
GPIO_LCKR_LCK14_len EQU 1
GPIO_LCKR_LCK13 EQU 0x00002000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK13_ofs EQU 13
GPIO_LCKR_LCK13_len EQU 1
GPIO_LCKR_LCK12 EQU 0x00001000 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK12_ofs EQU 12
GPIO_LCKR_LCK12_len EQU 1
GPIO_LCKR_LCK11 EQU 0x00000800 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK11_ofs EQU 11
GPIO_LCKR_LCK11_len EQU 1
GPIO_LCKR_LCK10 EQU 0x00000400 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK10_ofs EQU 10
GPIO_LCKR_LCK10_len EQU 1
GPIO_LCKR_LCK9 EQU 0x00000200 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK9_ofs EQU 9
GPIO_LCKR_LCK9_len EQU 1
GPIO_LCKR_LCK8 EQU 0x00000100 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK8_ofs EQU 8
GPIO_LCKR_LCK8_len EQU 1
GPIO_LCKR_LCK7 EQU 0x00000080 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK7_ofs EQU 7
GPIO_LCKR_LCK7_len EQU 1
GPIO_LCKR_LCK6 EQU 0x00000040 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK6_ofs EQU 6
GPIO_LCKR_LCK6_len EQU 1
GPIO_LCKR_LCK5 EQU 0x00000020 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK5_ofs EQU 5
GPIO_LCKR_LCK5_len EQU 1
GPIO_LCKR_LCK4 EQU 0x00000010 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK4_ofs EQU 4
GPIO_LCKR_LCK4_len EQU 1
GPIO_LCKR_LCK3 EQU 0x00000008 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK3_ofs EQU 3
GPIO_LCKR_LCK3_len EQU 1
GPIO_LCKR_LCK2 EQU 0x00000004 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK2_ofs EQU 2
GPIO_LCKR_LCK2_len EQU 1
GPIO_LCKR_LCK1 EQU 0x00000002 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK1_ofs EQU 1
GPIO_LCKR_LCK1_len EQU 1
GPIO_LCKR_LCK0 EQU 0x00000001 ; Port x lock bit y (y= 0..15)
GPIO_LCKR_LCK0_ofs EQU 0
GPIO_LCKR_LCK0_len EQU 1
; GPIOA_AFRL fields:
GPIO_AFRL_AFRL7 EQU 0xf0000000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL7_ofs EQU 28
GPIO_AFRL_AFRL7_len EQU 4
GPIO_AFRL_AFRL6 EQU 0x0f000000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL6_ofs EQU 24
GPIO_AFRL_AFRL6_len EQU 4
GPIO_AFRL_AFRL5 EQU 0x00f00000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL5_ofs EQU 20
GPIO_AFRL_AFRL5_len EQU 4
GPIO_AFRL_AFRL4 EQU 0x000f0000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL4_ofs EQU 16
GPIO_AFRL_AFRL4_len EQU 4
GPIO_AFRL_AFRL3 EQU 0x0000f000 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL3_ofs EQU 12
GPIO_AFRL_AFRL3_len EQU 4
GPIO_AFRL_AFRL2 EQU 0x00000f00 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL2_ofs EQU 8
GPIO_AFRL_AFRL2_len EQU 4
GPIO_AFRL_AFRL1 EQU 0x000000f0 ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL1_ofs EQU 4
GPIO_AFRL_AFRL1_len EQU 4
GPIO_AFRL_AFRL0 EQU 0x0000000f ; Alternate function selection for port x bit y (y = 0..7)
GPIO_AFRL_AFRL0_ofs EQU 0
GPIO_AFRL_AFRL0_len EQU 4
; GPIOA_AFRH fields:
GPIO_AFRH_AFRH15 EQU 0xf0000000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH15_ofs EQU 28
GPIO_AFRH_AFRH15_len EQU 4
GPIO_AFRH_AFRH14 EQU 0x0f000000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH14_ofs EQU 24
GPIO_AFRH_AFRH14_len EQU 4
GPIO_AFRH_AFRH13 EQU 0x00f00000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH13_ofs EQU 20
GPIO_AFRH_AFRH13_len EQU 4
GPIO_AFRH_AFRH12 EQU 0x000f0000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH12_ofs EQU 16
GPIO_AFRH_AFRH12_len EQU 4
GPIO_AFRH_AFRH11 EQU 0x0000f000 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH11_ofs EQU 12
GPIO_AFRH_AFRH11_len EQU 4
GPIO_AFRH_AFRH10 EQU 0x00000f00 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH10_ofs EQU 8
GPIO_AFRH_AFRH10_len EQU 4
GPIO_AFRH_AFRH9 EQU 0x000000f0 ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH9_ofs EQU 4
GPIO_AFRH_AFRH9_len EQU 4
GPIO_AFRH_AFRH8 EQU 0x0000000f ; Alternate function selection for port x bit y (y = 8..15)
GPIO_AFRH_AFRH8_ofs EQU 0
GPIO_AFRH_AFRH8_len EQU 4
; GPIOA_BRR fields:
GPIO_BRR_BR0 EQU 0x00000001 ; Port x Reset bit y
GPIO_BRR_BR0_ofs EQU 0
GPIO_BRR_BR0_len EQU 1
GPIO_BRR_BR1 EQU 0x00000002 ; Port x Reset bit y
GPIO_BRR_BR1_ofs EQU 1
GPIO_BRR_BR1_len EQU 1
GPIO_BRR_BR2 EQU 0x00000004 ; Port x Reset bit y
GPIO_BRR_BR2_ofs EQU 2
GPIO_BRR_BR2_len EQU 1
GPIO_BRR_BR3 EQU 0x00000008 ; Port x Reset bit y
GPIO_BRR_BR3_ofs EQU 3
GPIO_BRR_BR3_len EQU 1
GPIO_BRR_BR4 EQU 0x00000010 ; Port x Reset bit y
GPIO_BRR_BR4_ofs EQU 4
GPIO_BRR_BR4_len EQU 1
GPIO_BRR_BR5 EQU 0x00000020 ; Port x Reset bit y
GPIO_BRR_BR5_ofs EQU 5
GPIO_BRR_BR5_len EQU 1
GPIO_BRR_BR6 EQU 0x00000040 ; Port x Reset bit y
GPIO_BRR_BR6_ofs EQU 6
GPIO_BRR_BR6_len EQU 1
GPIO_BRR_BR7 EQU 0x00000080 ; Port x Reset bit y
GPIO_BRR_BR7_ofs EQU 7
GPIO_BRR_BR7_len EQU 1
GPIO_BRR_BR8 EQU 0x00000100 ; Port x Reset bit y
GPIO_BRR_BR8_ofs EQU 8
GPIO_BRR_BR8_len EQU 1
GPIO_BRR_BR9 EQU 0x00000200 ; Port x Reset bit y
GPIO_BRR_BR9_ofs EQU 9
GPIO_BRR_BR9_len EQU 1
GPIO_BRR_BR10 EQU 0x00000400 ; Port x Reset bit y
GPIO_BRR_BR10_ofs EQU 10
GPIO_BRR_BR10_len EQU 1
GPIO_BRR_BR11 EQU 0x00000800 ; Port x Reset bit y
GPIO_BRR_BR11_ofs EQU 11
GPIO_BRR_BR11_len EQU 1
GPIO_BRR_BR12 EQU 0x00001000 ; Port x Reset bit y
GPIO_BRR_BR12_ofs EQU 12
GPIO_BRR_BR12_len EQU 1
GPIO_BRR_BR13 EQU 0x00002000 ; Port x Reset bit y
GPIO_BRR_BR13_ofs EQU 13
GPIO_BRR_BR13_len EQU 1
GPIO_BRR_BR14 EQU 0x00004000 ; Port x Reset bit y
GPIO_BRR_BR14_ofs EQU 14
GPIO_BRR_BR14_len EQU 1
GPIO_BRR_BR15 EQU 0x00008000 ; Port x Reset bit y
GPIO_BRR_BR15_ofs EQU 15
GPIO_BRR_BR15_len EQU 1
; ---- GPIOB -------------------------------------------------
; Desc: General-purpose I/Os
; GPIOB base address:
GPIOB_BASE EQU 0x48000400
; GPIOB registers:
GPIOB_MODER EQU (GPIOB_BASE + 0x0) ; GPIO port mode register
GPIOB_OTYPER EQU (GPIOB_BASE + 0x4) ; GPIO port output type register
GPIOB_OSPEEDR EQU (GPIOB_BASE + 0x8) ; GPIO port output speed register
GPIOB_PUPDR EQU (GPIOB_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOB_IDR EQU (GPIOB_BASE + 0x10) ; GPIO port input data register
GPIOB_ODR EQU (GPIOB_BASE + 0x14) ; GPIO port output data register
GPIOB_BSRR EQU (GPIOB_BASE + 0x18) ; GPIO port bit set/reset register
GPIOB_LCKR EQU (GPIOB_BASE + 0x1c) ; GPIO port configuration lock register
GPIOB_AFRL EQU (GPIOB_BASE + 0x20) ; GPIO alternate function low register
GPIOB_AFRH EQU (GPIOB_BASE + 0x24) ; GPIO alternate function high register
GPIOB_BRR EQU (GPIOB_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOC -------------------------------------------------
; Desc: None
; GPIOC base address:
GPIOC_BASE EQU 0x48000800
; GPIOC registers:
GPIOC_MODER EQU (GPIOC_BASE + 0x0) ; GPIO port mode register
GPIOC_OTYPER EQU (GPIOC_BASE + 0x4) ; GPIO port output type register
GPIOC_OSPEEDR EQU (GPIOC_BASE + 0x8) ; GPIO port output speed register
GPIOC_PUPDR EQU (GPIOC_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOC_IDR EQU (GPIOC_BASE + 0x10) ; GPIO port input data register
GPIOC_ODR EQU (GPIOC_BASE + 0x14) ; GPIO port output data register
GPIOC_BSRR EQU (GPIOC_BASE + 0x18) ; GPIO port bit set/reset register
GPIOC_LCKR EQU (GPIOC_BASE + 0x1c) ; GPIO port configuration lock register
GPIOC_AFRL EQU (GPIOC_BASE + 0x20) ; GPIO alternate function low register
GPIOC_AFRH EQU (GPIOC_BASE + 0x24) ; GPIO alternate function high register
GPIOC_BRR EQU (GPIOC_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOD -------------------------------------------------
; Desc: None
; GPIOD base address:
GPIOD_BASE EQU 0x48000c00
; GPIOD registers:
GPIOD_MODER EQU (GPIOD_BASE + 0x0) ; GPIO port mode register
GPIOD_OTYPER EQU (GPIOD_BASE + 0x4) ; GPIO port output type register
GPIOD_OSPEEDR EQU (GPIOD_BASE + 0x8) ; GPIO port output speed register
GPIOD_PUPDR EQU (GPIOD_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOD_IDR EQU (GPIOD_BASE + 0x10) ; GPIO port input data register
GPIOD_ODR EQU (GPIOD_BASE + 0x14) ; GPIO port output data register
GPIOD_BSRR EQU (GPIOD_BASE + 0x18) ; GPIO port bit set/reset register
GPIOD_LCKR EQU (GPIOD_BASE + 0x1c) ; GPIO port configuration lock register
GPIOD_AFRL EQU (GPIOD_BASE + 0x20) ; GPIO alternate function low register
GPIOD_AFRH EQU (GPIOD_BASE + 0x24) ; GPIO alternate function high register
GPIOD_BRR EQU (GPIOD_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOE -------------------------------------------------
; Desc: None
; GPIOE base address:
GPIOE_BASE EQU 0x48001000
; GPIOE registers:
GPIOE_MODER EQU (GPIOE_BASE + 0x0) ; GPIO port mode register
GPIOE_OTYPER EQU (GPIOE_BASE + 0x4) ; GPIO port output type register
GPIOE_OSPEEDR EQU (GPIOE_BASE + 0x8) ; GPIO port output speed register
GPIOE_PUPDR EQU (GPIOE_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOE_IDR EQU (GPIOE_BASE + 0x10) ; GPIO port input data register
GPIOE_ODR EQU (GPIOE_BASE + 0x14) ; GPIO port output data register
GPIOE_BSRR EQU (GPIOE_BASE + 0x18) ; GPIO port bit set/reset register
GPIOE_LCKR EQU (GPIOE_BASE + 0x1c) ; GPIO port configuration lock register
GPIOE_AFRL EQU (GPIOE_BASE + 0x20) ; GPIO alternate function low register
GPIOE_AFRH EQU (GPIOE_BASE + 0x24) ; GPIO alternate function high register
GPIOE_BRR EQU (GPIOE_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- GPIOF -------------------------------------------------
; Desc: None
; GPIOF base address:
GPIOF_BASE EQU 0x48001400
; GPIOF registers:
GPIOF_MODER EQU (GPIOF_BASE + 0x0) ; GPIO port mode register
GPIOF_OTYPER EQU (GPIOF_BASE + 0x4) ; GPIO port output type register
GPIOF_OSPEEDR EQU (GPIOF_BASE + 0x8) ; GPIO port output speed register
GPIOF_PUPDR EQU (GPIOF_BASE + 0xc) ; GPIO port pull-up/pull-down register
GPIOF_IDR EQU (GPIOF_BASE + 0x10) ; GPIO port input data register
GPIOF_ODR EQU (GPIOF_BASE + 0x14) ; GPIO port output data register
GPIOF_BSRR EQU (GPIOF_BASE + 0x18) ; GPIO port bit set/reset register
GPIOF_LCKR EQU (GPIOF_BASE + 0x1c) ; GPIO port configuration lock register
GPIOF_AFRL EQU (GPIOF_BASE + 0x20) ; GPIO alternate function low register
GPIOF_AFRH EQU (GPIOF_BASE + 0x24) ; GPIO alternate function high register
GPIOF_BRR EQU (GPIOF_BASE + 0x28) ; Port bit reset register
; Fields the same as in the first instance.
; ---- TSC ---------------------------------------------------
; Desc: Touch sensing controller
; TSC base address:
TSC_BASE EQU 0x40024000
; TSC registers:
TSC_CR EQU (TSC_BASE + 0x0) ; control register
TSC_IER EQU (TSC_BASE + 0x4) ; interrupt enable register
TSC_ICR EQU (TSC_BASE + 0x8) ; interrupt clear register
TSC_ISR EQU (TSC_BASE + 0xc) ; interrupt status register
TSC_IOHCR EQU (TSC_BASE + 0x10) ; I/O hysteresis control register
TSC_IOASCR EQU (TSC_BASE + 0x18) ; I/O analog switch control register
TSC_IOSCR EQU (TSC_BASE + 0x20) ; I/O sampling control register
TSC_IOCCR EQU (TSC_BASE + 0x28) ; I/O channel control register
TSC_IOGCSR EQU (TSC_BASE + 0x30) ; I/O group control status register
TSC_IOG1CR EQU (TSC_BASE + 0x34) ; I/O group x counter register
TSC_IOG2CR EQU (TSC_BASE + 0x38) ; I/O group x counter register
TSC_IOG3CR EQU (TSC_BASE + 0x3c) ; I/O group x counter register
TSC_IOG4CR EQU (TSC_BASE + 0x40) ; I/O group x counter register
TSC_IOG5CR EQU (TSC_BASE + 0x44) ; I/O group x counter register
TSC_IOG6CR EQU (TSC_BASE + 0x48) ; I/O group x counter register
TSC_IOG7CR EQU (TSC_BASE + 0x4c) ; I/O group x counter register
TSC_IOG8CR EQU (TSC_BASE + 0x50) ; I/O group x counter register
; TSC_CR fields:
TSC_CR_CTPH EQU 0xf0000000 ; Charge transfer pulse high
TSC_CR_CTPH_ofs EQU 28
TSC_CR_CTPH_len EQU 4
TSC_CR_CTPL EQU 0x0f000000 ; Charge transfer pulse low
TSC_CR_CTPL_ofs EQU 24
TSC_CR_CTPL_len EQU 4
TSC_CR_SSD EQU 0x00fe0000 ; Spread spectrum deviation
TSC_CR_SSD_ofs EQU 17
TSC_CR_SSD_len EQU 7
TSC_CR_SSE EQU 0x00010000 ; Spread spectrum enable
TSC_CR_SSE_ofs EQU 16
TSC_CR_SSE_len EQU 1
TSC_CR_SSPSC EQU 0x00008000 ; Spread spectrum prescaler
TSC_CR_SSPSC_ofs EQU 15
TSC_CR_SSPSC_len EQU 1
TSC_CR_PGPSC EQU 0x00007000 ; pulse generator prescaler
TSC_CR_PGPSC_ofs EQU 12
TSC_CR_PGPSC_len EQU 3
TSC_CR_MCV EQU 0x000000e0 ; Max count value
TSC_CR_MCV_ofs EQU 5
TSC_CR_MCV_len EQU 3
TSC_CR_IODEF EQU 0x00000010 ; I/O Default mode
TSC_CR_IODEF_ofs EQU 4
TSC_CR_IODEF_len EQU 1
TSC_CR_SYNCPOL EQU 0x00000008 ; Synchronization pin polarity
TSC_CR_SYNCPOL_ofs EQU 3
TSC_CR_SYNCPOL_len EQU 1
TSC_CR_AM EQU 0x00000004 ; Acquisition mode
TSC_CR_AM_ofs EQU 2
TSC_CR_AM_len EQU 1
TSC_CR_START EQU 0x00000002 ; Start a new acquisition
TSC_CR_START_ofs EQU 1
TSC_CR_START_len EQU 1
TSC_CR_TSCE EQU 0x00000001 ; Touch sensing controller enable
TSC_CR_TSCE_ofs EQU 0
TSC_CR_TSCE_len EQU 1
; TSC_IER fields:
TSC_IER_MCEIE EQU 0x00000002 ; Max count error interrupt enable
TSC_IER_MCEIE_ofs EQU 1
TSC_IER_MCEIE_len EQU 1
TSC_IER_EOAIE EQU 0x00000001 ; End of acquisition interrupt enable
TSC_IER_EOAIE_ofs EQU 0
TSC_IER_EOAIE_len EQU 1
; TSC_ICR fields:
TSC_ICR_MCEIC EQU 0x00000002 ; Max count error interrupt clear
TSC_ICR_MCEIC_ofs EQU 1
TSC_ICR_MCEIC_len EQU 1
TSC_ICR_EOAIC EQU 0x00000001 ; End of acquisition interrupt clear
TSC_ICR_EOAIC_ofs EQU 0
TSC_ICR_EOAIC_len EQU 1
; TSC_ISR fields:
TSC_ISR_MCEF EQU 0x00000002 ; Max count error flag
TSC_ISR_MCEF_ofs EQU 1
TSC_ISR_MCEF_len EQU 1
TSC_ISR_EOAF EQU 0x00000001 ; End of acquisition flag
TSC_ISR_EOAF_ofs EQU 0
TSC_ISR_EOAF_len EQU 1
; TSC_IOHCR fields:
TSC_IOHCR_G1_IO1 EQU 0x00000001 ; G1_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO1_ofs EQU 0
TSC_IOHCR_G1_IO1_len EQU 1
TSC_IOHCR_G1_IO2 EQU 0x00000002 ; G1_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO2_ofs EQU 1
TSC_IOHCR_G1_IO2_len EQU 1
TSC_IOHCR_G1_IO3 EQU 0x00000004 ; G1_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO3_ofs EQU 2
TSC_IOHCR_G1_IO3_len EQU 1
TSC_IOHCR_G1_IO4 EQU 0x00000008 ; G1_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G1_IO4_ofs EQU 3
TSC_IOHCR_G1_IO4_len EQU 1
TSC_IOHCR_G2_IO1 EQU 0x00000010 ; G2_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO1_ofs EQU 4
TSC_IOHCR_G2_IO1_len EQU 1
TSC_IOHCR_G2_IO2 EQU 0x00000020 ; G2_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO2_ofs EQU 5
TSC_IOHCR_G2_IO2_len EQU 1
TSC_IOHCR_G2_IO3 EQU 0x00000040 ; G2_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO3_ofs EQU 6
TSC_IOHCR_G2_IO3_len EQU 1
TSC_IOHCR_G2_IO4 EQU 0x00000080 ; G2_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G2_IO4_ofs EQU 7
TSC_IOHCR_G2_IO4_len EQU 1
TSC_IOHCR_G3_IO1 EQU 0x00000100 ; G3_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO1_ofs EQU 8
TSC_IOHCR_G3_IO1_len EQU 1
TSC_IOHCR_G3_IO2 EQU 0x00000200 ; G3_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO2_ofs EQU 9
TSC_IOHCR_G3_IO2_len EQU 1
TSC_IOHCR_G3_IO3 EQU 0x00000400 ; G3_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO3_ofs EQU 10
TSC_IOHCR_G3_IO3_len EQU 1
TSC_IOHCR_G3_IO4 EQU 0x00000800 ; G3_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G3_IO4_ofs EQU 11
TSC_IOHCR_G3_IO4_len EQU 1
TSC_IOHCR_G4_IO1 EQU 0x00001000 ; G4_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO1_ofs EQU 12
TSC_IOHCR_G4_IO1_len EQU 1
TSC_IOHCR_G4_IO2 EQU 0x00002000 ; G4_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO2_ofs EQU 13
TSC_IOHCR_G4_IO2_len EQU 1
TSC_IOHCR_G4_IO3 EQU 0x00004000 ; G4_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO3_ofs EQU 14
TSC_IOHCR_G4_IO3_len EQU 1
TSC_IOHCR_G4_IO4 EQU 0x00008000 ; G4_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G4_IO4_ofs EQU 15
TSC_IOHCR_G4_IO4_len EQU 1
TSC_IOHCR_G5_IO1 EQU 0x00010000 ; G5_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO1_ofs EQU 16
TSC_IOHCR_G5_IO1_len EQU 1
TSC_IOHCR_G5_IO2 EQU 0x00020000 ; G5_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO2_ofs EQU 17
TSC_IOHCR_G5_IO2_len EQU 1
TSC_IOHCR_G5_IO3 EQU 0x00040000 ; G5_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO3_ofs EQU 18
TSC_IOHCR_G5_IO3_len EQU 1
TSC_IOHCR_G5_IO4 EQU 0x00080000 ; G5_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G5_IO4_ofs EQU 19
TSC_IOHCR_G5_IO4_len EQU 1
TSC_IOHCR_G6_IO1 EQU 0x00100000 ; G6_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO1_ofs EQU 20
TSC_IOHCR_G6_IO1_len EQU 1
TSC_IOHCR_G6_IO2 EQU 0x00200000 ; G6_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO2_ofs EQU 21
TSC_IOHCR_G6_IO2_len EQU 1
TSC_IOHCR_G6_IO3 EQU 0x00400000 ; G6_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO3_ofs EQU 22
TSC_IOHCR_G6_IO3_len EQU 1
TSC_IOHCR_G6_IO4 EQU 0x00800000 ; G6_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G6_IO4_ofs EQU 23
TSC_IOHCR_G6_IO4_len EQU 1
TSC_IOHCR_G7_IO1 EQU 0x01000000 ; G7_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO1_ofs EQU 24
TSC_IOHCR_G7_IO1_len EQU 1
TSC_IOHCR_G7_IO2 EQU 0x02000000 ; G7_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO2_ofs EQU 25
TSC_IOHCR_G7_IO2_len EQU 1
TSC_IOHCR_G7_IO3 EQU 0x04000000 ; G7_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO3_ofs EQU 26
TSC_IOHCR_G7_IO3_len EQU 1
TSC_IOHCR_G7_IO4 EQU 0x08000000 ; G7_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G7_IO4_ofs EQU 27
TSC_IOHCR_G7_IO4_len EQU 1
TSC_IOHCR_G8_IO1 EQU 0x10000000 ; G8_IO1 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO1_ofs EQU 28
TSC_IOHCR_G8_IO1_len EQU 1
TSC_IOHCR_G8_IO2 EQU 0x20000000 ; G8_IO2 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO2_ofs EQU 29
TSC_IOHCR_G8_IO2_len EQU 1
TSC_IOHCR_G8_IO3 EQU 0x40000000 ; G8_IO3 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO3_ofs EQU 30
TSC_IOHCR_G8_IO3_len EQU 1
TSC_IOHCR_G8_IO4 EQU 0x80000000 ; G8_IO4 Schmitt trigger hysteresis mode
TSC_IOHCR_G8_IO4_ofs EQU 31
TSC_IOHCR_G8_IO4_len EQU 1
; TSC_IOASCR fields:
TSC_IOASCR_G1_IO1 EQU 0x00000001 ; G1_IO1 analog switch enable
TSC_IOASCR_G1_IO1_ofs EQU 0
TSC_IOASCR_G1_IO1_len EQU 1
TSC_IOASCR_G1_IO2 EQU 0x00000002 ; G1_IO2 analog switch enable
TSC_IOASCR_G1_IO2_ofs EQU 1
TSC_IOASCR_G1_IO2_len EQU 1
TSC_IOASCR_G1_IO3 EQU 0x00000004 ; G1_IO3 analog switch enable
TSC_IOASCR_G1_IO3_ofs EQU 2
TSC_IOASCR_G1_IO3_len EQU 1
TSC_IOASCR_G1_IO4 EQU 0x00000008 ; G1_IO4 analog switch enable
TSC_IOASCR_G1_IO4_ofs EQU 3
TSC_IOASCR_G1_IO4_len EQU 1
TSC_IOASCR_G2_IO1 EQU 0x00000010 ; G2_IO1 analog switch enable
TSC_IOASCR_G2_IO1_ofs EQU 4
TSC_IOASCR_G2_IO1_len EQU 1
TSC_IOASCR_G2_IO2 EQU 0x00000020 ; G2_IO2 analog switch enable
TSC_IOASCR_G2_IO2_ofs EQU 5
TSC_IOASCR_G2_IO2_len EQU 1
TSC_IOASCR_G2_IO3 EQU 0x00000040 ; G2_IO3 analog switch enable
TSC_IOASCR_G2_IO3_ofs EQU 6
TSC_IOASCR_G2_IO3_len EQU 1
TSC_IOASCR_G2_IO4 EQU 0x00000080 ; G2_IO4 analog switch enable
TSC_IOASCR_G2_IO4_ofs EQU 7
TSC_IOASCR_G2_IO4_len EQU 1
TSC_IOASCR_G3_IO1 EQU 0x00000100 ; G3_IO1 analog switch enable
TSC_IOASCR_G3_IO1_ofs EQU 8
TSC_IOASCR_G3_IO1_len EQU 1
TSC_IOASCR_G3_IO2 EQU 0x00000200 ; G3_IO2 analog switch enable
TSC_IOASCR_G3_IO2_ofs EQU 9
TSC_IOASCR_G3_IO2_len EQU 1
TSC_IOASCR_G3_IO3 EQU 0x00000400 ; G3_IO3 analog switch enable
TSC_IOASCR_G3_IO3_ofs EQU 10
TSC_IOASCR_G3_IO3_len EQU 1
TSC_IOASCR_G3_IO4 EQU 0x00000800 ; G3_IO4 analog switch enable
TSC_IOASCR_G3_IO4_ofs EQU 11
TSC_IOASCR_G3_IO4_len EQU 1
TSC_IOASCR_G4_IO1 EQU 0x00001000 ; G4_IO1 analog switch enable
TSC_IOASCR_G4_IO1_ofs EQU 12
TSC_IOASCR_G4_IO1_len EQU 1
TSC_IOASCR_G4_IO2 EQU 0x00002000 ; G4_IO2 analog switch enable
TSC_IOASCR_G4_IO2_ofs EQU 13
TSC_IOASCR_G4_IO2_len EQU 1
TSC_IOASCR_G4_IO3 EQU 0x00004000 ; G4_IO3 analog switch enable
TSC_IOASCR_G4_IO3_ofs EQU 14
TSC_IOASCR_G4_IO3_len EQU 1
TSC_IOASCR_G4_IO4 EQU 0x00008000 ; G4_IO4 analog switch enable
TSC_IOASCR_G4_IO4_ofs EQU 15
TSC_IOASCR_G4_IO4_len EQU 1
TSC_IOASCR_G5_IO1 EQU 0x00010000 ; G5_IO1 analog switch enable
TSC_IOASCR_G5_IO1_ofs EQU 16
TSC_IOASCR_G5_IO1_len EQU 1
TSC_IOASCR_G5_IO2 EQU 0x00020000 ; G5_IO2 analog switch enable
TSC_IOASCR_G5_IO2_ofs EQU 17
TSC_IOASCR_G5_IO2_len EQU 1
TSC_IOASCR_G5_IO3 EQU 0x00040000 ; G5_IO3 analog switch enable
TSC_IOASCR_G5_IO3_ofs EQU 18
TSC_IOASCR_G5_IO3_len EQU 1
TSC_IOASCR_G5_IO4 EQU 0x00080000 ; G5_IO4 analog switch enable
TSC_IOASCR_G5_IO4_ofs EQU 19
TSC_IOASCR_G5_IO4_len EQU 1
TSC_IOASCR_G6_IO1 EQU 0x00100000 ; G6_IO1 analog switch enable
TSC_IOASCR_G6_IO1_ofs EQU 20
TSC_IOASCR_G6_IO1_len EQU 1
TSC_IOASCR_G6_IO2 EQU 0x00200000 ; G6_IO2 analog switch enable
TSC_IOASCR_G6_IO2_ofs EQU 21
TSC_IOASCR_G6_IO2_len EQU 1
TSC_IOASCR_G6_IO3 EQU 0x00400000 ; G6_IO3 analog switch enable
TSC_IOASCR_G6_IO3_ofs EQU 22
TSC_IOASCR_G6_IO3_len EQU 1
TSC_IOASCR_G6_IO4 EQU 0x00800000 ; G6_IO4 analog switch enable
TSC_IOASCR_G6_IO4_ofs EQU 23
TSC_IOASCR_G6_IO4_len EQU 1
TSC_IOASCR_G7_IO1 EQU 0x01000000 ; G7_IO1 analog switch enable
TSC_IOASCR_G7_IO1_ofs EQU 24
TSC_IOASCR_G7_IO1_len EQU 1
TSC_IOASCR_G7_IO2 EQU 0x02000000 ; G7_IO2 analog switch enable
TSC_IOASCR_G7_IO2_ofs EQU 25
TSC_IOASCR_G7_IO2_len EQU 1
TSC_IOASCR_G7_IO3 EQU 0x04000000 ; G7_IO3 analog switch enable
TSC_IOASCR_G7_IO3_ofs EQU 26
TSC_IOASCR_G7_IO3_len EQU 1
TSC_IOASCR_G7_IO4 EQU 0x08000000 ; G7_IO4 analog switch enable
TSC_IOASCR_G7_IO4_ofs EQU 27
TSC_IOASCR_G7_IO4_len EQU 1
TSC_IOASCR_G8_IO1 EQU 0x10000000 ; G8_IO1 analog switch enable
TSC_IOASCR_G8_IO1_ofs EQU 28
TSC_IOASCR_G8_IO1_len EQU 1
TSC_IOASCR_G8_IO2 EQU 0x20000000 ; G8_IO2 analog switch enable
TSC_IOASCR_G8_IO2_ofs EQU 29
TSC_IOASCR_G8_IO2_len EQU 1
TSC_IOASCR_G8_IO3 EQU 0x40000000 ; G8_IO3 analog switch enable
TSC_IOASCR_G8_IO3_ofs EQU 30
TSC_IOASCR_G8_IO3_len EQU 1
TSC_IOASCR_G8_IO4 EQU 0x80000000 ; G8_IO4 analog switch enable
TSC_IOASCR_G8_IO4_ofs EQU 31
TSC_IOASCR_G8_IO4_len EQU 1
; TSC_IOSCR fields:
TSC_IOSCR_G1_IO1 EQU 0x00000001 ; G1_IO1 sampling mode
TSC_IOSCR_G1_IO1_ofs EQU 0
TSC_IOSCR_G1_IO1_len EQU 1
TSC_IOSCR_G1_IO2 EQU 0x00000002 ; G1_IO2 sampling mode
TSC_IOSCR_G1_IO2_ofs EQU 1
TSC_IOSCR_G1_IO2_len EQU 1
TSC_IOSCR_G1_IO3 EQU 0x00000004 ; G1_IO3 sampling mode
TSC_IOSCR_G1_IO3_ofs EQU 2
TSC_IOSCR_G1_IO3_len EQU 1
TSC_IOSCR_G1_IO4 EQU 0x00000008 ; G1_IO4 sampling mode
TSC_IOSCR_G1_IO4_ofs EQU 3
TSC_IOSCR_G1_IO4_len EQU 1
TSC_IOSCR_G2_IO1 EQU 0x00000010 ; G2_IO1 sampling mode
TSC_IOSCR_G2_IO1_ofs EQU 4
TSC_IOSCR_G2_IO1_len EQU 1
TSC_IOSCR_G2_IO2 EQU 0x00000020 ; G2_IO2 sampling mode
TSC_IOSCR_G2_IO2_ofs EQU 5
TSC_IOSCR_G2_IO2_len EQU 1
TSC_IOSCR_G2_IO3 EQU 0x00000040 ; G2_IO3 sampling mode
TSC_IOSCR_G2_IO3_ofs EQU 6
TSC_IOSCR_G2_IO3_len EQU 1
TSC_IOSCR_G2_IO4 EQU 0x00000080 ; G2_IO4 sampling mode
TSC_IOSCR_G2_IO4_ofs EQU 7
TSC_IOSCR_G2_IO4_len EQU 1
TSC_IOSCR_G3_IO1 EQU 0x00000100 ; G3_IO1 sampling mode
TSC_IOSCR_G3_IO1_ofs EQU 8
TSC_IOSCR_G3_IO1_len EQU 1
TSC_IOSCR_G3_IO2 EQU 0x00000200 ; G3_IO2 sampling mode
TSC_IOSCR_G3_IO2_ofs EQU 9
TSC_IOSCR_G3_IO2_len EQU 1
TSC_IOSCR_G3_IO3 EQU 0x00000400 ; G3_IO3 sampling mode
TSC_IOSCR_G3_IO3_ofs EQU 10
TSC_IOSCR_G3_IO3_len EQU 1
TSC_IOSCR_G3_IO4 EQU 0x00000800 ; G3_IO4 sampling mode
TSC_IOSCR_G3_IO4_ofs EQU 11
TSC_IOSCR_G3_IO4_len EQU 1
TSC_IOSCR_G4_IO1 EQU 0x00001000 ; G4_IO1 sampling mode
TSC_IOSCR_G4_IO1_ofs EQU 12
TSC_IOSCR_G4_IO1_len EQU 1
TSC_IOSCR_G4_IO2 EQU 0x00002000 ; G4_IO2 sampling mode
TSC_IOSCR_G4_IO2_ofs EQU 13
TSC_IOSCR_G4_IO2_len EQU 1
TSC_IOSCR_G4_IO3 EQU 0x00004000 ; G4_IO3 sampling mode
TSC_IOSCR_G4_IO3_ofs EQU 14
TSC_IOSCR_G4_IO3_len EQU 1
TSC_IOSCR_G4_IO4 EQU 0x00008000 ; G4_IO4 sampling mode
TSC_IOSCR_G4_IO4_ofs EQU 15
TSC_IOSCR_G4_IO4_len EQU 1
TSC_IOSCR_G5_IO1 EQU 0x00010000 ; G5_IO1 sampling mode
TSC_IOSCR_G5_IO1_ofs EQU 16
TSC_IOSCR_G5_IO1_len EQU 1
TSC_IOSCR_G5_IO2 EQU 0x00020000 ; G5_IO2 sampling mode
TSC_IOSCR_G5_IO2_ofs EQU 17
TSC_IOSCR_G5_IO2_len EQU 1
TSC_IOSCR_G5_IO3 EQU 0x00040000 ; G5_IO3 sampling mode
TSC_IOSCR_G5_IO3_ofs EQU 18
TSC_IOSCR_G5_IO3_len EQU 1
TSC_IOSCR_G5_IO4 EQU 0x00080000 ; G5_IO4 sampling mode
TSC_IOSCR_G5_IO4_ofs EQU 19
TSC_IOSCR_G5_IO4_len EQU 1
TSC_IOSCR_G6_IO1 EQU 0x00100000 ; G6_IO1 sampling mode
TSC_IOSCR_G6_IO1_ofs EQU 20
TSC_IOSCR_G6_IO1_len EQU 1
TSC_IOSCR_G6_IO2 EQU 0x00200000 ; G6_IO2 sampling mode
TSC_IOSCR_G6_IO2_ofs EQU 21
TSC_IOSCR_G6_IO2_len EQU 1
TSC_IOSCR_G6_IO3 EQU 0x00400000 ; G6_IO3 sampling mode
TSC_IOSCR_G6_IO3_ofs EQU 22
TSC_IOSCR_G6_IO3_len EQU 1
TSC_IOSCR_G6_IO4 EQU 0x00800000 ; G6_IO4 sampling mode
TSC_IOSCR_G6_IO4_ofs EQU 23
TSC_IOSCR_G6_IO4_len EQU 1
TSC_IOSCR_G7_IO1 EQU 0x01000000 ; G7_IO1 sampling mode
TSC_IOSCR_G7_IO1_ofs EQU 24
TSC_IOSCR_G7_IO1_len EQU 1
TSC_IOSCR_G7_IO2 EQU 0x02000000 ; G7_IO2 sampling mode
TSC_IOSCR_G7_IO2_ofs EQU 25
TSC_IOSCR_G7_IO2_len EQU 1
TSC_IOSCR_G7_IO3 EQU 0x04000000 ; G7_IO3 sampling mode
TSC_IOSCR_G7_IO3_ofs EQU 26
TSC_IOSCR_G7_IO3_len EQU 1
TSC_IOSCR_G7_IO4 EQU 0x08000000 ; G7_IO4 sampling mode
TSC_IOSCR_G7_IO4_ofs EQU 27
TSC_IOSCR_G7_IO4_len EQU 1
TSC_IOSCR_G8_IO1 EQU 0x10000000 ; G8_IO1 sampling mode
TSC_IOSCR_G8_IO1_ofs EQU 28
TSC_IOSCR_G8_IO1_len EQU 1
TSC_IOSCR_G8_IO2 EQU 0x20000000 ; G8_IO2 sampling mode
TSC_IOSCR_G8_IO2_ofs EQU 29
TSC_IOSCR_G8_IO2_len EQU 1
TSC_IOSCR_G8_IO3 EQU 0x40000000 ; G8_IO3 sampling mode
TSC_IOSCR_G8_IO3_ofs EQU 30
TSC_IOSCR_G8_IO3_len EQU 1
TSC_IOSCR_G8_IO4 EQU 0x80000000 ; G8_IO4 sampling mode
TSC_IOSCR_G8_IO4_ofs EQU 31
TSC_IOSCR_G8_IO4_len EQU 1
; TSC_IOCCR fields:
TSC_IOCCR_G1_IO1 EQU 0x00000001 ; G1_IO1 channel mode
TSC_IOCCR_G1_IO1_ofs EQU 0
TSC_IOCCR_G1_IO1_len EQU 1
TSC_IOCCR_G1_IO2 EQU 0x00000002 ; G1_IO2 channel mode
TSC_IOCCR_G1_IO2_ofs EQU 1
TSC_IOCCR_G1_IO2_len EQU 1
TSC_IOCCR_G1_IO3 EQU 0x00000004 ; G1_IO3 channel mode
TSC_IOCCR_G1_IO3_ofs EQU 2
TSC_IOCCR_G1_IO3_len EQU 1
TSC_IOCCR_G1_IO4 EQU 0x00000008 ; G1_IO4 channel mode
TSC_IOCCR_G1_IO4_ofs EQU 3
TSC_IOCCR_G1_IO4_len EQU 1
TSC_IOCCR_G2_IO1 EQU 0x00000010 ; G2_IO1 channel mode
TSC_IOCCR_G2_IO1_ofs EQU 4
TSC_IOCCR_G2_IO1_len EQU 1
TSC_IOCCR_G2_IO2 EQU 0x00000020 ; G2_IO2 channel mode
TSC_IOCCR_G2_IO2_ofs EQU 5
TSC_IOCCR_G2_IO2_len EQU 1
TSC_IOCCR_G2_IO3 EQU 0x00000040 ; G2_IO3 channel mode
TSC_IOCCR_G2_IO3_ofs EQU 6
TSC_IOCCR_G2_IO3_len EQU 1
TSC_IOCCR_G2_IO4 EQU 0x00000080 ; G2_IO4 channel mode
TSC_IOCCR_G2_IO4_ofs EQU 7
TSC_IOCCR_G2_IO4_len EQU 1
TSC_IOCCR_G3_IO1 EQU 0x00000100 ; G3_IO1 channel mode
TSC_IOCCR_G3_IO1_ofs EQU 8
TSC_IOCCR_G3_IO1_len EQU 1
TSC_IOCCR_G3_IO2 EQU 0x00000200 ; G3_IO2 channel mode
TSC_IOCCR_G3_IO2_ofs EQU 9
TSC_IOCCR_G3_IO2_len EQU 1
TSC_IOCCR_G3_IO3 EQU 0x00000400 ; G3_IO3 channel mode
TSC_IOCCR_G3_IO3_ofs EQU 10
TSC_IOCCR_G3_IO3_len EQU 1
TSC_IOCCR_G3_IO4 EQU 0x00000800 ; G3_IO4 channel mode
TSC_IOCCR_G3_IO4_ofs EQU 11
TSC_IOCCR_G3_IO4_len EQU 1
TSC_IOCCR_G4_IO1 EQU 0x00001000 ; G4_IO1 channel mode
TSC_IOCCR_G4_IO1_ofs EQU 12
TSC_IOCCR_G4_IO1_len EQU 1
TSC_IOCCR_G4_IO2 EQU 0x00002000 ; G4_IO2 channel mode
TSC_IOCCR_G4_IO2_ofs EQU 13
TSC_IOCCR_G4_IO2_len EQU 1
TSC_IOCCR_G4_IO3 EQU 0x00004000 ; G4_IO3 channel mode
TSC_IOCCR_G4_IO3_ofs EQU 14
TSC_IOCCR_G4_IO3_len EQU 1
TSC_IOCCR_G4_IO4 EQU 0x00008000 ; G4_IO4 channel mode
TSC_IOCCR_G4_IO4_ofs EQU 15
TSC_IOCCR_G4_IO4_len EQU 1
TSC_IOCCR_G5_IO1 EQU 0x00010000 ; G5_IO1 channel mode
TSC_IOCCR_G5_IO1_ofs EQU 16
TSC_IOCCR_G5_IO1_len EQU 1
TSC_IOCCR_G5_IO2 EQU 0x00020000 ; G5_IO2 channel mode
TSC_IOCCR_G5_IO2_ofs EQU 17
TSC_IOCCR_G5_IO2_len EQU 1
TSC_IOCCR_G5_IO3 EQU 0x00040000 ; G5_IO3 channel mode
TSC_IOCCR_G5_IO3_ofs EQU 18
TSC_IOCCR_G5_IO3_len EQU 1
TSC_IOCCR_G5_IO4 EQU 0x00080000 ; G5_IO4 channel mode
TSC_IOCCR_G5_IO4_ofs EQU 19
TSC_IOCCR_G5_IO4_len EQU 1
TSC_IOCCR_G6_IO1 EQU 0x00100000 ; G6_IO1 channel mode
TSC_IOCCR_G6_IO1_ofs EQU 20
TSC_IOCCR_G6_IO1_len EQU 1
TSC_IOCCR_G6_IO2 EQU 0x00200000 ; G6_IO2 channel mode
TSC_IOCCR_G6_IO2_ofs EQU 21
TSC_IOCCR_G6_IO2_len EQU 1
TSC_IOCCR_G6_IO3 EQU 0x00400000 ; G6_IO3 channel mode
TSC_IOCCR_G6_IO3_ofs EQU 22
TSC_IOCCR_G6_IO3_len EQU 1
TSC_IOCCR_G6_IO4 EQU 0x00800000 ; G6_IO4 channel mode
TSC_IOCCR_G6_IO4_ofs EQU 23
TSC_IOCCR_G6_IO4_len EQU 1
TSC_IOCCR_G7_IO1 EQU 0x01000000 ; G7_IO1 channel mode
TSC_IOCCR_G7_IO1_ofs EQU 24
TSC_IOCCR_G7_IO1_len EQU 1
TSC_IOCCR_G7_IO2 EQU 0x02000000 ; G7_IO2 channel mode
TSC_IOCCR_G7_IO2_ofs EQU 25
TSC_IOCCR_G7_IO2_len EQU 1
TSC_IOCCR_G7_IO3 EQU 0x04000000 ; G7_IO3 channel mode
TSC_IOCCR_G7_IO3_ofs EQU 26
TSC_IOCCR_G7_IO3_len EQU 1
TSC_IOCCR_G7_IO4 EQU 0x08000000 ; G7_IO4 channel mode
TSC_IOCCR_G7_IO4_ofs EQU 27
TSC_IOCCR_G7_IO4_len EQU 1
TSC_IOCCR_G8_IO1 EQU 0x10000000 ; G8_IO1 channel mode
TSC_IOCCR_G8_IO1_ofs EQU 28
TSC_IOCCR_G8_IO1_len EQU 1
TSC_IOCCR_G8_IO2 EQU 0x20000000 ; G8_IO2 channel mode
TSC_IOCCR_G8_IO2_ofs EQU 29
TSC_IOCCR_G8_IO2_len EQU 1
TSC_IOCCR_G8_IO3 EQU 0x40000000 ; G8_IO3 channel mode
TSC_IOCCR_G8_IO3_ofs EQU 30
TSC_IOCCR_G8_IO3_len EQU 1
TSC_IOCCR_G8_IO4 EQU 0x80000000 ; G8_IO4 channel mode
TSC_IOCCR_G8_IO4_ofs EQU 31
TSC_IOCCR_G8_IO4_len EQU 1
; TSC_IOGCSR fields:
TSC_IOGCSR_G8S EQU 0x00800000 ; Analog I/O group x status
TSC_IOGCSR_G8S_ofs EQU 23
TSC_IOGCSR_G8S_len EQU 1
TSC_IOGCSR_G7S EQU 0x00400000 ; Analog I/O group x status
TSC_IOGCSR_G7S_ofs EQU 22
TSC_IOGCSR_G7S_len EQU 1
TSC_IOGCSR_G6S EQU 0x00200000 ; Analog I/O group x status
TSC_IOGCSR_G6S_ofs EQU 21
TSC_IOGCSR_G6S_len EQU 1
TSC_IOGCSR_G5S EQU 0x00100000 ; Analog I/O group x status
TSC_IOGCSR_G5S_ofs EQU 20
TSC_IOGCSR_G5S_len EQU 1
TSC_IOGCSR_G4S EQU 0x00080000 ; Analog I/O group x status
TSC_IOGCSR_G4S_ofs EQU 19
TSC_IOGCSR_G4S_len EQU 1
TSC_IOGCSR_G3S EQU 0x00040000 ; Analog I/O group x status
TSC_IOGCSR_G3S_ofs EQU 18
TSC_IOGCSR_G3S_len EQU 1
TSC_IOGCSR_G2S EQU 0x00020000 ; Analog I/O group x status
TSC_IOGCSR_G2S_ofs EQU 17
TSC_IOGCSR_G2S_len EQU 1
TSC_IOGCSR_G1S EQU 0x00010000 ; Analog I/O group x status
TSC_IOGCSR_G1S_ofs EQU 16
TSC_IOGCSR_G1S_len EQU 1
TSC_IOGCSR_G8E EQU 0x00000080 ; Analog I/O group x enable
TSC_IOGCSR_G8E_ofs EQU 7
TSC_IOGCSR_G8E_len EQU 1
TSC_IOGCSR_G7E EQU 0x00000040 ; Analog I/O group x enable
TSC_IOGCSR_G7E_ofs EQU 6
TSC_IOGCSR_G7E_len EQU 1
TSC_IOGCSR_G6E EQU 0x00000020 ; Analog I/O group x enable
TSC_IOGCSR_G6E_ofs EQU 5
TSC_IOGCSR_G6E_len EQU 1
TSC_IOGCSR_G5E EQU 0x00000010 ; Analog I/O group x enable
TSC_IOGCSR_G5E_ofs EQU 4
TSC_IOGCSR_G5E_len EQU 1
TSC_IOGCSR_G4E EQU 0x00000008 ; Analog I/O group x enable
TSC_IOGCSR_G4E_ofs EQU 3
TSC_IOGCSR_G4E_len EQU 1
TSC_IOGCSR_G3E EQU 0x00000004 ; Analog I/O group x enable
TSC_IOGCSR_G3E_ofs EQU 2
TSC_IOGCSR_G3E_len EQU 1
TSC_IOGCSR_G2E EQU 0x00000002 ; Analog I/O group x enable
TSC_IOGCSR_G2E_ofs EQU 1
TSC_IOGCSR_G2E_len EQU 1
TSC_IOGCSR_G1E EQU 0x00000001 ; Analog I/O group x enable
TSC_IOGCSR_G1E_ofs EQU 0
TSC_IOGCSR_G1E_len EQU 1
; TSC_IOG1CR fields:
TSC_IOG1CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG1CR_CNT_ofs EQU 0
TSC_IOG1CR_CNT_len EQU 14
; TSC_IOG2CR fields:
TSC_IOG2CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG2CR_CNT_ofs EQU 0
TSC_IOG2CR_CNT_len EQU 14
; TSC_IOG3CR fields:
TSC_IOG3CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG3CR_CNT_ofs EQU 0
TSC_IOG3CR_CNT_len EQU 14
; TSC_IOG4CR fields:
TSC_IOG4CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG4CR_CNT_ofs EQU 0
TSC_IOG4CR_CNT_len EQU 14
; TSC_IOG5CR fields:
TSC_IOG5CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG5CR_CNT_ofs EQU 0
TSC_IOG5CR_CNT_len EQU 14
; TSC_IOG6CR fields:
TSC_IOG6CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG6CR_CNT_ofs EQU 0
TSC_IOG6CR_CNT_len EQU 14
; TSC_IOG7CR fields:
TSC_IOG7CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG7CR_CNT_ofs EQU 0
TSC_IOG7CR_CNT_len EQU 14
; TSC_IOG8CR fields:
TSC_IOG8CR_CNT EQU 0x00003fff ; Counter value
TSC_IOG8CR_CNT_ofs EQU 0
TSC_IOG8CR_CNT_len EQU 14
; ---- CRC ---------------------------------------------------
; Desc: cyclic redundancy check calculation unit
; CRC base address:
CRC_BASE EQU 0x40023000
; CRC registers:
CRC_DR EQU (CRC_BASE + 0x0) ; Data register
CRC_IDR EQU (CRC_BASE + 0x4) ; Independent data register
CRC_CR EQU (CRC_BASE + 0x8) ; Control register
CRC_INIT EQU (CRC_BASE + 0x10) ; Initial CRC value
CRC_POL EQU (CRC_BASE + 0x14) ; CRC polynomial
; CRC_DR fields:
CRC_DR_DR EQU 0xffffffff ; Data register bits
CRC_DR_DR_ofs EQU 0
CRC_DR_DR_len EQU 32
; CRC_IDR fields:
CRC_IDR_IDR EQU 0x000000ff ; General-purpose 8-bit data register bits
CRC_IDR_IDR_ofs EQU 0
CRC_IDR_IDR_len EQU 8
; CRC_CR fields:
CRC_CR_RESET EQU 0x00000001 ; reset bit
CRC_CR_RESET_ofs EQU 0
CRC_CR_RESET_len EQU 1
CRC_CR_POLYSIZE EQU 0x00000018 ; Polynomial size
CRC_CR_POLYSIZE_ofs EQU 3
CRC_CR_POLYSIZE_len EQU 2
CRC_CR_REV_IN EQU 0x00000060 ; Reverse input data
CRC_CR_REV_IN_ofs EQU 5
CRC_CR_REV_IN_len EQU 2
CRC_CR_REV_OUT EQU 0x00000080 ; Reverse output data
CRC_CR_REV_OUT_ofs EQU 7
CRC_CR_REV_OUT_len EQU 1
; CRC_INIT fields:
CRC_INIT_INIT EQU 0xffffffff ; Programmable initial CRC value
CRC_INIT_INIT_ofs EQU 0
CRC_INIT_INIT_len EQU 32
; CRC_POL fields:
CRC_POL_POL EQU 0xffffffff ; Programmable polynomial
CRC_POL_POL_ofs EQU 0
CRC_POL_POL_len EQU 32
; ---- Flash -------------------------------------------------
; Desc: Flash
; Flash base address:
FLASH_BASE EQU 0x40022000
; Flash registers:
FLASH_ACR EQU (FLASH_BASE + 0x0) ; Flash access control register
FLASH_KEYR EQU (FLASH_BASE + 0x4) ; Flash key register
FLASH_OPTKEYR EQU (FLASH_BASE + 0x8) ; Flash option key register
FLASH_SR EQU (FLASH_BASE + 0xc) ; Flash status register
FLASH_CR EQU (FLASH_BASE + 0x10) ; Flash control register
FLASH_AR EQU (FLASH_BASE + 0x14) ; Flash address register
FLASH_OBR EQU (FLASH_BASE + 0x1c) ; Option byte register
FLASH_WRPR EQU (FLASH_BASE + 0x20) ; Write protection register
; FLASH_ACR fields:
FLASH_ACR_LATENCY EQU 0x00000007 ; LATENCY
FLASH_ACR_LATENCY_ofs EQU 0
FLASH_ACR_LATENCY_len EQU 3
FLASH_ACR_PRFTBE EQU 0x00000010 ; PRFTBE
FLASH_ACR_PRFTBE_ofs EQU 4
FLASH_ACR_PRFTBE_len EQU 1
FLASH_ACR_PRFTBS EQU 0x00000020 ; PRFTBS
FLASH_ACR_PRFTBS_ofs EQU 5
FLASH_ACR_PRFTBS_len EQU 1
; FLASH_KEYR fields:
FLASH_KEYR_FKEYR EQU 0xffffffff ; Flash Key
FLASH_KEYR_FKEYR_ofs EQU 0
FLASH_KEYR_FKEYR_len EQU 32
; FLASH_OPTKEYR fields:
FLASH_OPTKEYR_OPTKEYR EQU 0xffffffff ; Option byte key
FLASH_OPTKEYR_OPTKEYR_ofs EQU 0
FLASH_OPTKEYR_OPTKEYR_len EQU 32
; FLASH_SR fields:
FLASH_SR_EOP EQU 0x00000020 ; End of operation
FLASH_SR_EOP_ofs EQU 5
FLASH_SR_EOP_len EQU 1
FLASH_SR_WRPRT EQU 0x00000010 ; Write protection error
FLASH_SR_WRPRT_ofs EQU 4
FLASH_SR_WRPRT_len EQU 1
FLASH_SR_PGERR EQU 0x00000004 ; Programming error
FLASH_SR_PGERR_ofs EQU 2
FLASH_SR_PGERR_len EQU 1
FLASH_SR_BSY EQU 0x00000001 ; Busy
FLASH_SR_BSY_ofs EQU 0
FLASH_SR_BSY_len EQU 1
; FLASH_CR fields:
FLASH_CR_FORCE_OPTLOAD EQU 0x00002000 ; Force option byte loading
FLASH_CR_FORCE_OPTLOAD_ofs EQU 13
FLASH_CR_FORCE_OPTLOAD_len EQU 1
FLASH_CR_EOPIE EQU 0x00001000 ; End of operation interrupt enable
FLASH_CR_EOPIE_ofs EQU 12
FLASH_CR_EOPIE_len EQU 1
FLASH_CR_ERRIE EQU 0x00000400 ; Error interrupt enable
FLASH_CR_ERRIE_ofs EQU 10
FLASH_CR_ERRIE_len EQU 1
FLASH_CR_OPTWRE EQU 0x00000200 ; Option bytes write enable
FLASH_CR_OPTWRE_ofs EQU 9
FLASH_CR_OPTWRE_len EQU 1
FLASH_CR_LOCK EQU 0x00000080 ; Lock
FLASH_CR_LOCK_ofs EQU 7
FLASH_CR_LOCK_len EQU 1
FLASH_CR_STRT EQU 0x00000040 ; Start
FLASH_CR_STRT_ofs EQU 6
FLASH_CR_STRT_len EQU 1
FLASH_CR_OPTER EQU 0x00000020 ; Option byte erase
FLASH_CR_OPTER_ofs EQU 5
FLASH_CR_OPTER_len EQU 1
FLASH_CR_OPTPG EQU 0x00000010 ; Option byte programming
FLASH_CR_OPTPG_ofs EQU 4
FLASH_CR_OPTPG_len EQU 1
FLASH_CR_MER EQU 0x00000004 ; Mass erase
FLASH_CR_MER_ofs EQU 2
FLASH_CR_MER_len EQU 1
FLASH_CR_PER EQU 0x00000002 ; Page erase
FLASH_CR_PER_ofs EQU 1
FLASH_CR_PER_len EQU 1
FLASH_CR_PG EQU 0x00000001 ; Programming
FLASH_CR_PG_ofs EQU 0
FLASH_CR_PG_len EQU 1
; FLASH_AR fields:
FLASH_AR_FAR EQU 0xffffffff ; Flash address
FLASH_AR_FAR_ofs EQU 0
FLASH_AR_FAR_len EQU 32
; FLASH_OBR fields:
FLASH_OBR_OPTERR EQU 0x00000001 ; Option byte error
FLASH_OBR_OPTERR_ofs EQU 0
FLASH_OBR_OPTERR_len EQU 1
FLASH_OBR_LEVEL1_PROT EQU 0x00000002 ; Level 1 protection status
FLASH_OBR_LEVEL1_PROT_ofs EQU 1
FLASH_OBR_LEVEL1_PROT_len EQU 1
FLASH_OBR_LEVEL2_PROT EQU 0x00000004 ; Level 2 protection status
FLASH_OBR_LEVEL2_PROT_ofs EQU 2
FLASH_OBR_LEVEL2_PROT_len EQU 1
FLASH_OBR_WDG_SW EQU 0x00000100 ; WDG_SW
FLASH_OBR_WDG_SW_ofs EQU 8
FLASH_OBR_WDG_SW_len EQU 1
FLASH_OBR_nRST_STOP EQU 0x00000200 ; nRST_STOP
FLASH_OBR_nRST_STOP_ofs EQU 9
FLASH_OBR_nRST_STOP_len EQU 1
FLASH_OBR_nRST_STDBY EQU 0x00000400 ; nRST_STDBY
FLASH_OBR_nRST_STDBY_ofs EQU 10
FLASH_OBR_nRST_STDBY_len EQU 1
FLASH_OBR_BOOT1 EQU 0x00001000 ; BOOT1
FLASH_OBR_BOOT1_ofs EQU 12
FLASH_OBR_BOOT1_len EQU 1
FLASH_OBR_VDDA_MONITOR EQU 0x00002000 ; VDDA_MONITOR
FLASH_OBR_VDDA_MONITOR_ofs EQU 13
FLASH_OBR_VDDA_MONITOR_len EQU 1
FLASH_OBR_SRAM_PARITY_CHECK EQU 0x00004000 ; SRAM_PARITY_CHECK
FLASH_OBR_SRAM_PARITY_CHECK_ofs EQU 14
FLASH_OBR_SRAM_PARITY_CHECK_len EQU 1
FLASH_OBR_Data0 EQU 0x00ff0000 ; Data0
FLASH_OBR_Data0_ofs EQU 16
FLASH_OBR_Data0_len EQU 8
FLASH_OBR_Data1 EQU 0xff000000 ; Data1
FLASH_OBR_Data1_ofs EQU 24
FLASH_OBR_Data1_len EQU 8
; FLASH_WRPR fields:
FLASH_WRPR_WRP EQU 0xffffffff ; Write protect
FLASH_WRPR_WRP_ofs EQU 0
FLASH_WRPR_WRP_len EQU 32
; ---- RCC ---------------------------------------------------
; Desc: Reset and clock control
; RCC base address:
RCC_BASE EQU 0x40021000
; RCC registers:
RCC_CR EQU (RCC_BASE + 0x0) ; Clock control register
RCC_CFGR EQU (RCC_BASE + 0x4) ; Clock configuration register (RCC_CFGR)
RCC_CIR EQU (RCC_BASE + 0x8) ; Clock interrupt register (RCC_CIR)
RCC_APB2RSTR EQU (RCC_BASE + 0xc) ; APB2 peripheral reset register (RCC_APB2RSTR)
RCC_APB1RSTR EQU (RCC_BASE + 0x10) ; APB1 peripheral reset register (RCC_APB1RSTR)
RCC_AHBENR EQU (RCC_BASE + 0x14) ; AHB Peripheral Clock enable register (RCC_AHBENR)
RCC_APB2ENR EQU (RCC_BASE + 0x18) ; APB2 peripheral clock enable register (RCC_APB2ENR)
RCC_APB1ENR EQU (RCC_BASE + 0x1c) ; APB1 peripheral clock enable register (RCC_APB1ENR)
RCC_BDCR EQU (RCC_BASE + 0x20) ; Backup domain control register (RCC_BDCR)
RCC_CSR EQU (RCC_BASE + 0x24) ; Control/status register (RCC_CSR)
RCC_AHBRSTR EQU (RCC_BASE + 0x28) ; AHB peripheral reset register
RCC_CFGR2 EQU (RCC_BASE + 0x2c) ; Clock configuration register 2
RCC_CFGR3 EQU (RCC_BASE + 0x30) ; Clock configuration register 3
; RCC_CR fields:
RCC_CR_HSION EQU 0x00000001 ; Internal High Speed clock enable
RCC_CR_HSION_ofs EQU 0
RCC_CR_HSION_len EQU 1
RCC_CR_HSIRDY EQU 0x00000002 ; Internal High Speed clock ready flag
RCC_CR_HSIRDY_ofs EQU 1
RCC_CR_HSIRDY_len EQU 1
RCC_CR_HSITRIM EQU 0x000000f8 ; Internal High Speed clock trimming
RCC_CR_HSITRIM_ofs EQU 3
RCC_CR_HSITRIM_len EQU 5
RCC_CR_HSICAL EQU 0x0000ff00 ; Internal High Speed clock Calibration
RCC_CR_HSICAL_ofs EQU 8
RCC_CR_HSICAL_len EQU 8
RCC_CR_HSEON EQU 0x00010000 ; External High Speed clock enable
RCC_CR_HSEON_ofs EQU 16
RCC_CR_HSEON_len EQU 1
RCC_CR_HSERDY EQU 0x00020000 ; External High Speed clock ready flag
RCC_CR_HSERDY_ofs EQU 17
RCC_CR_HSERDY_len EQU 1
RCC_CR_HSEBYP EQU 0x00040000 ; External High Speed clock Bypass
RCC_CR_HSEBYP_ofs EQU 18
RCC_CR_HSEBYP_len EQU 1
RCC_CR_CSSON EQU 0x00080000 ; Clock Security System enable
RCC_CR_CSSON_ofs EQU 19
RCC_CR_CSSON_len EQU 1
RCC_CR_PLLON EQU 0x01000000 ; PLL enable
RCC_CR_PLLON_ofs EQU 24
RCC_CR_PLLON_len EQU 1
RCC_CR_PLLRDY EQU 0x02000000 ; PLL clock ready flag
RCC_CR_PLLRDY_ofs EQU 25
RCC_CR_PLLRDY_len EQU 1
; RCC_CFGR fields:
RCC_CFGR_SW EQU 0x00000003 ; System clock Switch
RCC_CFGR_SW_ofs EQU 0
RCC_CFGR_SW_len EQU 2
RCC_CFGR_SWS EQU 0x0000000c ; System Clock Switch Status
RCC_CFGR_SWS_ofs EQU 2
RCC_CFGR_SWS_len EQU 2
RCC_CFGR_HPRE EQU 0x000000f0 ; AHB prescaler
RCC_CFGR_HPRE_ofs EQU 4
RCC_CFGR_HPRE_len EQU 4
RCC_CFGR_PPRE1 EQU 0x00000700 ; APB Low speed prescaler (APB1)
RCC_CFGR_PPRE1_ofs EQU 8
RCC_CFGR_PPRE1_len EQU 3
RCC_CFGR_PPRE2 EQU 0x00003800 ; APB high speed prescaler (APB2)
RCC_CFGR_PPRE2_ofs EQU 11
RCC_CFGR_PPRE2_len EQU 3
RCC_CFGR_PLLSRC EQU 0x00010000 ; PLL entry clock source
RCC_CFGR_PLLSRC_ofs EQU 16
RCC_CFGR_PLLSRC_len EQU 1
RCC_CFGR_PLLXTPRE EQU 0x00020000 ; HSE divider for PLL entry
RCC_CFGR_PLLXTPRE_ofs EQU 17
RCC_CFGR_PLLXTPRE_len EQU 1
RCC_CFGR_PLLMUL EQU 0x003c0000 ; PLL Multiplication Factor
RCC_CFGR_PLLMUL_ofs EQU 18
RCC_CFGR_PLLMUL_len EQU 4
RCC_CFGR_USBPRES EQU 0x00400000 ; USB prescaler
RCC_CFGR_USBPRES_ofs EQU 22
RCC_CFGR_USBPRES_len EQU 1
RCC_CFGR_MCO EQU 0x07000000 ; Microcontroller clock output
RCC_CFGR_MCO_ofs EQU 24
RCC_CFGR_MCO_len EQU 3
RCC_CFGR_MCOF EQU 0x10000000 ; Microcontroller Clock Output Flag
RCC_CFGR_MCOF_ofs EQU 28
RCC_CFGR_MCOF_len EQU 1
RCC_CFGR_I2SSRC EQU 0x00800000 ; I2S external clock source selection
RCC_CFGR_I2SSRC_ofs EQU 23
RCC_CFGR_I2SSRC_len EQU 1
; RCC_CIR fields:
RCC_CIR_LSIRDYF EQU 0x00000001 ; LSI Ready Interrupt flag
RCC_CIR_LSIRDYF_ofs EQU 0
RCC_CIR_LSIRDYF_len EQU 1
RCC_CIR_LSERDYF EQU 0x00000002 ; LSE Ready Interrupt flag
RCC_CIR_LSERDYF_ofs EQU 1
RCC_CIR_LSERDYF_len EQU 1
RCC_CIR_HSIRDYF EQU 0x00000004 ; HSI Ready Interrupt flag
RCC_CIR_HSIRDYF_ofs EQU 2
RCC_CIR_HSIRDYF_len EQU 1
RCC_CIR_HSERDYF EQU 0x00000008 ; HSE Ready Interrupt flag
RCC_CIR_HSERDYF_ofs EQU 3
RCC_CIR_HSERDYF_len EQU 1
RCC_CIR_PLLRDYF EQU 0x00000010 ; PLL Ready Interrupt flag
RCC_CIR_PLLRDYF_ofs EQU 4
RCC_CIR_PLLRDYF_len EQU 1
RCC_CIR_CSSF EQU 0x00000080 ; Clock Security System Interrupt flag
RCC_CIR_CSSF_ofs EQU 7
RCC_CIR_CSSF_len EQU 1
RCC_CIR_LSIRDYIE EQU 0x00000100 ; LSI Ready Interrupt Enable
RCC_CIR_LSIRDYIE_ofs EQU 8
RCC_CIR_LSIRDYIE_len EQU 1
RCC_CIR_LSERDYIE EQU 0x00000200 ; LSE Ready Interrupt Enable
RCC_CIR_LSERDYIE_ofs EQU 9
RCC_CIR_LSERDYIE_len EQU 1
RCC_CIR_HSIRDYIE EQU 0x00000400 ; HSI Ready Interrupt Enable
RCC_CIR_HSIRDYIE_ofs EQU 10
RCC_CIR_HSIRDYIE_len EQU 1
RCC_CIR_HSERDYIE EQU 0x00000800 ; HSE Ready Interrupt Enable
RCC_CIR_HSERDYIE_ofs EQU 11
RCC_CIR_HSERDYIE_len EQU 1
RCC_CIR_PLLRDYIE EQU 0x00001000 ; PLL Ready Interrupt Enable
RCC_CIR_PLLRDYIE_ofs EQU 12
RCC_CIR_PLLRDYIE_len EQU 1
RCC_CIR_LSIRDYC EQU 0x00010000 ; LSI Ready Interrupt Clear
RCC_CIR_LSIRDYC_ofs EQU 16
RCC_CIR_LSIRDYC_len EQU 1
RCC_CIR_LSERDYC EQU 0x00020000 ; LSE Ready Interrupt Clear
RCC_CIR_LSERDYC_ofs EQU 17
RCC_CIR_LSERDYC_len EQU 1
RCC_CIR_HSIRDYC EQU 0x00040000 ; HSI Ready Interrupt Clear
RCC_CIR_HSIRDYC_ofs EQU 18
RCC_CIR_HSIRDYC_len EQU 1
RCC_CIR_HSERDYC EQU 0x00080000 ; HSE Ready Interrupt Clear
RCC_CIR_HSERDYC_ofs EQU 19
RCC_CIR_HSERDYC_len EQU 1
RCC_CIR_PLLRDYC EQU 0x00100000 ; PLL Ready Interrupt Clear
RCC_CIR_PLLRDYC_ofs EQU 20
RCC_CIR_PLLRDYC_len EQU 1
RCC_CIR_CSSC EQU 0x00800000 ; Clock security system interrupt clear
RCC_CIR_CSSC_ofs EQU 23
RCC_CIR_CSSC_len EQU 1
; RCC_APB2RSTR fields:
RCC_APB2RSTR_SYSCFGRST EQU 0x00000001 ; SYSCFG and COMP reset
RCC_APB2RSTR_SYSCFGRST_ofs EQU 0
RCC_APB2RSTR_SYSCFGRST_len EQU 1
RCC_APB2RSTR_TIM1RST EQU 0x00000800 ; TIM1 timer reset
RCC_APB2RSTR_TIM1RST_ofs EQU 11
RCC_APB2RSTR_TIM1RST_len EQU 1
RCC_APB2RSTR_SPI1RST EQU 0x00001000 ; SPI 1 reset
RCC_APB2RSTR_SPI1RST_ofs EQU 12
RCC_APB2RSTR_SPI1RST_len EQU 1
RCC_APB2RSTR_TIM8RST EQU 0x00002000 ; TIM8 timer reset
RCC_APB2RSTR_TIM8RST_ofs EQU 13
RCC_APB2RSTR_TIM8RST_len EQU 1
RCC_APB2RSTR_USART1RST EQU 0x00004000 ; USART1 reset
RCC_APB2RSTR_USART1RST_ofs EQU 14
RCC_APB2RSTR_USART1RST_len EQU 1
RCC_APB2RSTR_TIM15RST EQU 0x00010000 ; TIM15 timer reset
RCC_APB2RSTR_TIM15RST_ofs EQU 16
RCC_APB2RSTR_TIM15RST_len EQU 1
RCC_APB2RSTR_TIM16RST EQU 0x00020000 ; TIM16 timer reset
RCC_APB2RSTR_TIM16RST_ofs EQU 17
RCC_APB2RSTR_TIM16RST_len EQU 1
RCC_APB2RSTR_TIM17RST EQU 0x00040000 ; TIM17 timer reset
RCC_APB2RSTR_TIM17RST_ofs EQU 18
RCC_APB2RSTR_TIM17RST_len EQU 1
; RCC_APB1RSTR fields:
RCC_APB1RSTR_TIM2RST EQU 0x00000001 ; Timer 2 reset
RCC_APB1RSTR_TIM2RST_ofs EQU 0
RCC_APB1RSTR_TIM2RST_len EQU 1
RCC_APB1RSTR_TIM3RST EQU 0x00000002 ; Timer 3 reset
RCC_APB1RSTR_TIM3RST_ofs EQU 1
RCC_APB1RSTR_TIM3RST_len EQU 1
RCC_APB1RSTR_TIM4RST EQU 0x00000004 ; Timer 14 reset
RCC_APB1RSTR_TIM4RST_ofs EQU 2
RCC_APB1RSTR_TIM4RST_len EQU 1
RCC_APB1RSTR_TIM6RST EQU 0x00000010 ; Timer 6 reset
RCC_APB1RSTR_TIM6RST_ofs EQU 4
RCC_APB1RSTR_TIM6RST_len EQU 1
RCC_APB1RSTR_TIM7RST EQU 0x00000020 ; Timer 7 reset
RCC_APB1RSTR_TIM7RST_ofs EQU 5
RCC_APB1RSTR_TIM7RST_len EQU 1
RCC_APB1RSTR_WWDGRST EQU 0x00000800 ; Window watchdog reset
RCC_APB1RSTR_WWDGRST_ofs EQU 11
RCC_APB1RSTR_WWDGRST_len EQU 1
RCC_APB1RSTR_SPI2RST EQU 0x00004000 ; SPI2 reset
RCC_APB1RSTR_SPI2RST_ofs EQU 14
RCC_APB1RSTR_SPI2RST_len EQU 1
RCC_APB1RSTR_SPI3RST EQU 0x00008000 ; SPI3 reset
RCC_APB1RSTR_SPI3RST_ofs EQU 15
RCC_APB1RSTR_SPI3RST_len EQU 1
RCC_APB1RSTR_USART2RST EQU 0x00020000 ; USART 2 reset
RCC_APB1RSTR_USART2RST_ofs EQU 17
RCC_APB1RSTR_USART2RST_len EQU 1
RCC_APB1RSTR_USART3RST EQU 0x00040000 ; USART3 reset
RCC_APB1RSTR_USART3RST_ofs EQU 18
RCC_APB1RSTR_USART3RST_len EQU 1
RCC_APB1RSTR_UART4RST EQU 0x00080000 ; UART 4 reset
RCC_APB1RSTR_UART4RST_ofs EQU 19
RCC_APB1RSTR_UART4RST_len EQU 1
RCC_APB1RSTR_UART5RST EQU 0x00100000 ; UART 5 reset
RCC_APB1RSTR_UART5RST_ofs EQU 20
RCC_APB1RSTR_UART5RST_len EQU 1
RCC_APB1RSTR_I2C1RST EQU 0x00200000 ; I2C1 reset
RCC_APB1RSTR_I2C1RST_ofs EQU 21
RCC_APB1RSTR_I2C1RST_len EQU 1
RCC_APB1RSTR_I2C2RST EQU 0x00400000 ; I2C2 reset
RCC_APB1RSTR_I2C2RST_ofs EQU 22
RCC_APB1RSTR_I2C2RST_len EQU 1
RCC_APB1RSTR_USBRST EQU 0x00800000 ; USB reset
RCC_APB1RSTR_USBRST_ofs EQU 23
RCC_APB1RSTR_USBRST_len EQU 1
RCC_APB1RSTR_CANRST EQU 0x02000000 ; CAN reset
RCC_APB1RSTR_CANRST_ofs EQU 25
RCC_APB1RSTR_CANRST_len EQU 1
RCC_APB1RSTR_PWRRST EQU 0x10000000 ; Power interface reset
RCC_APB1RSTR_PWRRST_ofs EQU 28
RCC_APB1RSTR_PWRRST_len EQU 1
RCC_APB1RSTR_DACRST EQU 0x20000000 ; DAC interface reset
RCC_APB1RSTR_DACRST_ofs EQU 29
RCC_APB1RSTR_DACRST_len EQU 1
; RCC_AHBENR fields:
RCC_AHBENR_DMAEN EQU 0x00000001 ; DMA1 clock enable
RCC_AHBENR_DMAEN_ofs EQU 0
RCC_AHBENR_DMAEN_len EQU 1
RCC_AHBENR_DMA2EN EQU 0x00000002 ; DMA2 clock enable
RCC_AHBENR_DMA2EN_ofs EQU 1
RCC_AHBENR_DMA2EN_len EQU 1
RCC_AHBENR_SRAMEN EQU 0x00000004 ; SRAM interface clock enable
RCC_AHBENR_SRAMEN_ofs EQU 2
RCC_AHBENR_SRAMEN_len EQU 1
RCC_AHBENR_FLITFEN EQU 0x00000010 ; FLITF clock enable
RCC_AHBENR_FLITFEN_ofs EQU 4
RCC_AHBENR_FLITFEN_len EQU 1
RCC_AHBENR_CRCEN EQU 0x00000040 ; CRC clock enable
RCC_AHBENR_CRCEN_ofs EQU 6
RCC_AHBENR_CRCEN_len EQU 1
RCC_AHBENR_IOPAEN EQU 0x00020000 ; I/O port A clock enable
RCC_AHBENR_IOPAEN_ofs EQU 17
RCC_AHBENR_IOPAEN_len EQU 1
RCC_AHBENR_IOPBEN EQU 0x00040000 ; I/O port B clock enable
RCC_AHBENR_IOPBEN_ofs EQU 18
RCC_AHBENR_IOPBEN_len EQU 1
RCC_AHBENR_IOPCEN EQU 0x00080000 ; I/O port C clock enable
RCC_AHBENR_IOPCEN_ofs EQU 19
RCC_AHBENR_IOPCEN_len EQU 1
RCC_AHBENR_IOPDEN EQU 0x00100000 ; I/O port D clock enable
RCC_AHBENR_IOPDEN_ofs EQU 20
RCC_AHBENR_IOPDEN_len EQU 1
RCC_AHBENR_IOPEEN EQU 0x00200000 ; I/O port E clock enable
RCC_AHBENR_IOPEEN_ofs EQU 21
RCC_AHBENR_IOPEEN_len EQU 1
RCC_AHBENR_IOPFEN EQU 0x00400000 ; I/O port F clock enable
RCC_AHBENR_IOPFEN_ofs EQU 22
RCC_AHBENR_IOPFEN_len EQU 1
RCC_AHBENR_TSCEN EQU 0x01000000 ; Touch sensing controller clock enable
RCC_AHBENR_TSCEN_ofs EQU 24
RCC_AHBENR_TSCEN_len EQU 1
RCC_AHBENR_ADC12EN EQU 0x10000000 ; ADC1 and ADC2 clock enable
RCC_AHBENR_ADC12EN_ofs EQU 28
RCC_AHBENR_ADC12EN_len EQU 1
RCC_AHBENR_ADC34EN EQU 0x20000000 ; ADC3 and ADC4 clock enable
RCC_AHBENR_ADC34EN_ofs EQU 29
RCC_AHBENR_ADC34EN_len EQU 1
; RCC_APB2ENR fields:
RCC_APB2ENR_SYSCFGEN EQU 0x00000001 ; SYSCFG clock enable
RCC_APB2ENR_SYSCFGEN_ofs EQU 0
RCC_APB2ENR_SYSCFGEN_len EQU 1
RCC_APB2ENR_TIM1EN EQU 0x00000800 ; TIM1 Timer clock enable
RCC_APB2ENR_TIM1EN_ofs EQU 11
RCC_APB2ENR_TIM1EN_len EQU 1
RCC_APB2ENR_SPI1EN EQU 0x00001000 ; SPI 1 clock enable
RCC_APB2ENR_SPI1EN_ofs EQU 12
RCC_APB2ENR_SPI1EN_len EQU 1
RCC_APB2ENR_TIM8EN EQU 0x00002000 ; TIM8 Timer clock enable
RCC_APB2ENR_TIM8EN_ofs EQU 13
RCC_APB2ENR_TIM8EN_len EQU 1
RCC_APB2ENR_USART1EN EQU 0x00004000 ; USART1 clock enable
RCC_APB2ENR_USART1EN_ofs EQU 14
RCC_APB2ENR_USART1EN_len EQU 1
RCC_APB2ENR_TIM15EN EQU 0x00010000 ; TIM15 timer clock enable
RCC_APB2ENR_TIM15EN_ofs EQU 16
RCC_APB2ENR_TIM15EN_len EQU 1
RCC_APB2ENR_TIM16EN EQU 0x00020000 ; TIM16 timer clock enable
RCC_APB2ENR_TIM16EN_ofs EQU 17
RCC_APB2ENR_TIM16EN_len EQU 1
RCC_APB2ENR_TIM17EN EQU 0x00040000 ; TIM17 timer clock enable
RCC_APB2ENR_TIM17EN_ofs EQU 18
RCC_APB2ENR_TIM17EN_len EQU 1
; RCC_APB1ENR fields:
RCC_APB1ENR_TIM2EN EQU 0x00000001 ; Timer 2 clock enable
RCC_APB1ENR_TIM2EN_ofs EQU 0
RCC_APB1ENR_TIM2EN_len EQU 1
RCC_APB1ENR_TIM3EN EQU 0x00000002 ; Timer 3 clock enable
RCC_APB1ENR_TIM3EN_ofs EQU 1
RCC_APB1ENR_TIM3EN_len EQU 1
RCC_APB1ENR_TIM4EN EQU 0x00000004 ; Timer 4 clock enable
RCC_APB1ENR_TIM4EN_ofs EQU 2
RCC_APB1ENR_TIM4EN_len EQU 1
RCC_APB1ENR_TIM6EN EQU 0x00000010 ; Timer 6 clock enable
RCC_APB1ENR_TIM6EN_ofs EQU 4
RCC_APB1ENR_TIM6EN_len EQU 1
RCC_APB1ENR_TIM7EN EQU 0x00000020 ; Timer 7 clock enable
RCC_APB1ENR_TIM7EN_ofs EQU 5
RCC_APB1ENR_TIM7EN_len EQU 1
RCC_APB1ENR_WWDGEN EQU 0x00000800 ; Window watchdog clock enable
RCC_APB1ENR_WWDGEN_ofs EQU 11
RCC_APB1ENR_WWDGEN_len EQU 1
RCC_APB1ENR_SPI2EN EQU 0x00004000 ; SPI 2 clock enable
RCC_APB1ENR_SPI2EN_ofs EQU 14
RCC_APB1ENR_SPI2EN_len EQU 1
RCC_APB1ENR_SPI3EN EQU 0x00008000 ; SPI 3 clock enable
RCC_APB1ENR_SPI3EN_ofs EQU 15
RCC_APB1ENR_SPI3EN_len EQU 1
RCC_APB1ENR_USART2EN EQU 0x00020000 ; USART 2 clock enable
RCC_APB1ENR_USART2EN_ofs EQU 17
RCC_APB1ENR_USART2EN_len EQU 1
RCC_APB1ENR_I2C1EN EQU 0x00200000 ; I2C 1 clock enable
RCC_APB1ENR_I2C1EN_ofs EQU 21
RCC_APB1ENR_I2C1EN_len EQU 1
RCC_APB1ENR_I2C2EN EQU 0x00400000 ; I2C 2 clock enable
RCC_APB1ENR_I2C2EN_ofs EQU 22
RCC_APB1ENR_I2C2EN_len EQU 1
RCC_APB1ENR_USBEN EQU 0x00800000 ; USB clock enable
RCC_APB1ENR_USBEN_ofs EQU 23
RCC_APB1ENR_USBEN_len EQU 1
RCC_APB1ENR_CANEN EQU 0x02000000 ; CAN clock enable
RCC_APB1ENR_CANEN_ofs EQU 25
RCC_APB1ENR_CANEN_len EQU 1
RCC_APB1ENR_PWREN EQU 0x10000000 ; Power interface clock enable
RCC_APB1ENR_PWREN_ofs EQU 28
RCC_APB1ENR_PWREN_len EQU 1
RCC_APB1ENR_DACEN EQU 0x20000000 ; DAC interface clock enable
RCC_APB1ENR_DACEN_ofs EQU 29
RCC_APB1ENR_DACEN_len EQU 1
; RCC_BDCR fields:
RCC_BDCR_LSEON EQU 0x00000001 ; External Low Speed oscillator enable
RCC_BDCR_LSEON_ofs EQU 0
RCC_BDCR_LSEON_len EQU 1
RCC_BDCR_LSERDY EQU 0x00000002 ; External Low Speed oscillator ready
RCC_BDCR_LSERDY_ofs EQU 1
RCC_BDCR_LSERDY_len EQU 1
RCC_BDCR_LSEBYP EQU 0x00000004 ; External Low Speed oscillator bypass
RCC_BDCR_LSEBYP_ofs EQU 2
RCC_BDCR_LSEBYP_len EQU 1
RCC_BDCR_LSEDRV EQU 0x00000018 ; LSE oscillator drive capability
RCC_BDCR_LSEDRV_ofs EQU 3
RCC_BDCR_LSEDRV_len EQU 2
RCC_BDCR_RTCSEL EQU 0x00000300 ; RTC clock source selection
RCC_BDCR_RTCSEL_ofs EQU 8
RCC_BDCR_RTCSEL_len EQU 2
RCC_BDCR_RTCEN EQU 0x00008000 ; RTC clock enable
RCC_BDCR_RTCEN_ofs EQU 15
RCC_BDCR_RTCEN_len EQU 1
RCC_BDCR_BDRST EQU 0x00010000 ; Backup domain software reset
RCC_BDCR_BDRST_ofs EQU 16
RCC_BDCR_BDRST_len EQU 1
; RCC_CSR fields:
RCC_CSR_LSION EQU 0x00000001 ; Internal low speed oscillator enable
RCC_CSR_LSION_ofs EQU 0
RCC_CSR_LSION_len EQU 1
RCC_CSR_LSIRDY EQU 0x00000002 ; Internal low speed oscillator ready
RCC_CSR_LSIRDY_ofs EQU 1
RCC_CSR_LSIRDY_len EQU 1
RCC_CSR_RMVF EQU 0x01000000 ; Remove reset flag
RCC_CSR_RMVF_ofs EQU 24
RCC_CSR_RMVF_len EQU 1
RCC_CSR_OBLRSTF EQU 0x02000000 ; Option byte loader reset flag
RCC_CSR_OBLRSTF_ofs EQU 25
RCC_CSR_OBLRSTF_len EQU 1
RCC_CSR_PINRSTF EQU 0x04000000 ; PIN reset flag
RCC_CSR_PINRSTF_ofs EQU 26
RCC_CSR_PINRSTF_len EQU 1
RCC_CSR_PORRSTF EQU 0x08000000 ; POR/PDR reset flag
RCC_CSR_PORRSTF_ofs EQU 27
RCC_CSR_PORRSTF_len EQU 1
RCC_CSR_SFTRSTF EQU 0x10000000 ; Software reset flag
RCC_CSR_SFTRSTF_ofs EQU 28
RCC_CSR_SFTRSTF_len EQU 1
RCC_CSR_IWDGRSTF EQU 0x20000000 ; Independent watchdog reset flag
RCC_CSR_IWDGRSTF_ofs EQU 29
RCC_CSR_IWDGRSTF_len EQU 1
RCC_CSR_WWDGRSTF EQU 0x40000000 ; Window watchdog reset flag
RCC_CSR_WWDGRSTF_ofs EQU 30
RCC_CSR_WWDGRSTF_len EQU 1
RCC_CSR_LPWRRSTF EQU 0x80000000 ; Low-power reset flag
RCC_CSR_LPWRRSTF_ofs EQU 31
RCC_CSR_LPWRRSTF_len EQU 1
; RCC_AHBRSTR fields:
RCC_AHBRSTR_IOPARST EQU 0x00020000 ; I/O port A reset
RCC_AHBRSTR_IOPARST_ofs EQU 17
RCC_AHBRSTR_IOPARST_len EQU 1
RCC_AHBRSTR_IOPBRST EQU 0x00040000 ; I/O port B reset
RCC_AHBRSTR_IOPBRST_ofs EQU 18
RCC_AHBRSTR_IOPBRST_len EQU 1
RCC_AHBRSTR_IOPCRST EQU 0x00080000 ; I/O port C reset
RCC_AHBRSTR_IOPCRST_ofs EQU 19
RCC_AHBRSTR_IOPCRST_len EQU 1
RCC_AHBRSTR_IOPDRST EQU 0x00100000 ; I/O port D reset
RCC_AHBRSTR_IOPDRST_ofs EQU 20
RCC_AHBRSTR_IOPDRST_len EQU 1
RCC_AHBRSTR_IOPERST EQU 0x00200000 ; I/O port E reset
RCC_AHBRSTR_IOPERST_ofs EQU 21
RCC_AHBRSTR_IOPERST_len EQU 1
RCC_AHBRSTR_IOPFRST EQU 0x00400000 ; I/O port F reset
RCC_AHBRSTR_IOPFRST_ofs EQU 22
RCC_AHBRSTR_IOPFRST_len EQU 1
RCC_AHBRSTR_TSCRST EQU 0x01000000 ; Touch sensing controller reset
RCC_AHBRSTR_TSCRST_ofs EQU 24
RCC_AHBRSTR_TSCRST_len EQU 1
RCC_AHBRSTR_ADC12RST EQU 0x10000000 ; ADC1 and ADC2 reset
RCC_AHBRSTR_ADC12RST_ofs EQU 28
RCC_AHBRSTR_ADC12RST_len EQU 1
RCC_AHBRSTR_ADC34RST EQU 0x20000000 ; ADC3 and ADC4 reset
RCC_AHBRSTR_ADC34RST_ofs EQU 29
RCC_AHBRSTR_ADC34RST_len EQU 1
; RCC_CFGR2 fields:
RCC_CFGR2_PREDIV EQU 0x0000000f ; PREDIV division factor
RCC_CFGR2_PREDIV_ofs EQU 0
RCC_CFGR2_PREDIV_len EQU 4
RCC_CFGR2_ADC12PRES EQU 0x000001f0 ; ADC1 and ADC2 prescaler
RCC_CFGR2_ADC12PRES_ofs EQU 4
RCC_CFGR2_ADC12PRES_len EQU 5
RCC_CFGR2_ADC34PRES EQU 0x00003e00 ; ADC3 and ADC4 prescaler
RCC_CFGR2_ADC34PRES_ofs EQU 9
RCC_CFGR2_ADC34PRES_len EQU 5
; RCC_CFGR3 fields:
RCC_CFGR3_USART1SW EQU 0x00000003 ; USART1 clock source selection
RCC_CFGR3_USART1SW_ofs EQU 0
RCC_CFGR3_USART1SW_len EQU 2
RCC_CFGR3_I2C1SW EQU 0x00000010 ; I2C1 clock source selection
RCC_CFGR3_I2C1SW_ofs EQU 4
RCC_CFGR3_I2C1SW_len EQU 1
RCC_CFGR3_I2C2SW EQU 0x00000020 ; I2C2 clock source selection
RCC_CFGR3_I2C2SW_ofs EQU 5
RCC_CFGR3_I2C2SW_len EQU 1
RCC_CFGR3_USART2SW EQU 0x00030000 ; USART2 clock source selection
RCC_CFGR3_USART2SW_ofs EQU 16
RCC_CFGR3_USART2SW_len EQU 2
RCC_CFGR3_USART3SW EQU 0x000c0000 ; USART3 clock source selection
RCC_CFGR3_USART3SW_ofs EQU 18
RCC_CFGR3_USART3SW_len EQU 2
RCC_CFGR3_TIM1SW EQU 0x00000100 ; Timer1 clock source selection
RCC_CFGR3_TIM1SW_ofs EQU 8
RCC_CFGR3_TIM1SW_len EQU 1
RCC_CFGR3_TIM8SW EQU 0x00000200 ; Timer8 clock source selection
RCC_CFGR3_TIM8SW_ofs EQU 9
RCC_CFGR3_TIM8SW_len EQU 1
RCC_CFGR3_UART4SW EQU 0x00300000 ; UART4 clock source selection
RCC_CFGR3_UART4SW_ofs EQU 20
RCC_CFGR3_UART4SW_len EQU 2
RCC_CFGR3_UART5SW EQU 0x00c00000 ; UART5 clock source selection
RCC_CFGR3_UART5SW_ofs EQU 22
RCC_CFGR3_UART5SW_len EQU 2
; ---- DMA1 --------------------------------------------------
; Desc: DMA controller 1
; DMA1 base address:
DMA1_BASE EQU 0x40020000
; DMA1 registers:
DMA1_ISR EQU (DMA1_BASE + 0x0) ; DMA interrupt status register (DMA_ISR)
DMA1_IFCR EQU (DMA1_BASE + 0x4) ; DMA interrupt flag clear register (DMA_IFCR)
DMA1_CCR1 EQU (DMA1_BASE + 0x8) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR1 EQU (DMA1_BASE + 0xc) ; DMA channel 1 number of data register
DMA1_CPAR1 EQU (DMA1_BASE + 0x10) ; DMA channel 1 peripheral address register
DMA1_CMAR1 EQU (DMA1_BASE + 0x14) ; DMA channel 1 memory address register
DMA1_CCR2 EQU (DMA1_BASE + 0x1c) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR2 EQU (DMA1_BASE + 0x20) ; DMA channel 2 number of data register
DMA1_CPAR2 EQU (DMA1_BASE + 0x24) ; DMA channel 2 peripheral address register
DMA1_CMAR2 EQU (DMA1_BASE + 0x28) ; DMA channel 2 memory address register
DMA1_CCR3 EQU (DMA1_BASE + 0x30) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR3 EQU (DMA1_BASE + 0x34) ; DMA channel 3 number of data register
DMA1_CPAR3 EQU (DMA1_BASE + 0x38) ; DMA channel 3 peripheral address register
DMA1_CMAR3 EQU (DMA1_BASE + 0x3c) ; DMA channel 3 memory address register
DMA1_CCR4 EQU (DMA1_BASE + 0x44) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR4 EQU (DMA1_BASE + 0x48) ; DMA channel 4 number of data register
DMA1_CPAR4 EQU (DMA1_BASE + 0x4c) ; DMA channel 4 peripheral address register
DMA1_CMAR4 EQU (DMA1_BASE + 0x50) ; DMA channel 4 memory address register
DMA1_CCR5 EQU (DMA1_BASE + 0x58) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR5 EQU (DMA1_BASE + 0x5c) ; DMA channel 5 number of data register
DMA1_CPAR5 EQU (DMA1_BASE + 0x60) ; DMA channel 5 peripheral address register
DMA1_CMAR5 EQU (DMA1_BASE + 0x64) ; DMA channel 5 memory address register
DMA1_CCR6 EQU (DMA1_BASE + 0x6c) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR6 EQU (DMA1_BASE + 0x70) ; DMA channel 6 number of data register
DMA1_CPAR6 EQU (DMA1_BASE + 0x74) ; DMA channel 6 peripheral address register
DMA1_CMAR6 EQU (DMA1_BASE + 0x78) ; DMA channel 6 memory address register
DMA1_CCR7 EQU (DMA1_BASE + 0x80) ; DMA channel configuration register (DMA_CCR)
DMA1_CNDTR7 EQU (DMA1_BASE + 0x84) ; DMA channel 7 number of data register
DMA1_CPAR7 EQU (DMA1_BASE + 0x88) ; DMA channel 7 peripheral address register
DMA1_CMAR7 EQU (DMA1_BASE + 0x8c) ; DMA channel 7 memory address register
; DMA1_ISR fields:
DMA1_ISR_GIF1 EQU 0x00000001 ; Channel 1 Global interrupt flag
DMA1_ISR_GIF1_ofs EQU 0
DMA1_ISR_GIF1_len EQU 1
DMA1_ISR_TCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete flag
DMA1_ISR_TCIF1_ofs EQU 1
DMA1_ISR_TCIF1_len EQU 1
DMA1_ISR_HTIF1 EQU 0x00000004 ; Channel 1 Half Transfer Complete flag
DMA1_ISR_HTIF1_ofs EQU 2
DMA1_ISR_HTIF1_len EQU 1
DMA1_ISR_TEIF1 EQU 0x00000008 ; Channel 1 Transfer Error flag
DMA1_ISR_TEIF1_ofs EQU 3
DMA1_ISR_TEIF1_len EQU 1
DMA1_ISR_GIF2 EQU 0x00000010 ; Channel 2 Global interrupt flag
DMA1_ISR_GIF2_ofs EQU 4
DMA1_ISR_GIF2_len EQU 1
DMA1_ISR_TCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete flag
DMA1_ISR_TCIF2_ofs EQU 5
DMA1_ISR_TCIF2_len EQU 1
DMA1_ISR_HTIF2 EQU 0x00000040 ; Channel 2 Half Transfer Complete flag
DMA1_ISR_HTIF2_ofs EQU 6
DMA1_ISR_HTIF2_len EQU 1
DMA1_ISR_TEIF2 EQU 0x00000080 ; Channel 2 Transfer Error flag
DMA1_ISR_TEIF2_ofs EQU 7
DMA1_ISR_TEIF2_len EQU 1
DMA1_ISR_GIF3 EQU 0x00000100 ; Channel 3 Global interrupt flag
DMA1_ISR_GIF3_ofs EQU 8
DMA1_ISR_GIF3_len EQU 1
DMA1_ISR_TCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete flag
DMA1_ISR_TCIF3_ofs EQU 9
DMA1_ISR_TCIF3_len EQU 1
DMA1_ISR_HTIF3 EQU 0x00000400 ; Channel 3 Half Transfer Complete flag
DMA1_ISR_HTIF3_ofs EQU 10
DMA1_ISR_HTIF3_len EQU 1
DMA1_ISR_TEIF3 EQU 0x00000800 ; Channel 3 Transfer Error flag
DMA1_ISR_TEIF3_ofs EQU 11
DMA1_ISR_TEIF3_len EQU 1
DMA1_ISR_GIF4 EQU 0x00001000 ; Channel 4 Global interrupt flag
DMA1_ISR_GIF4_ofs EQU 12
DMA1_ISR_GIF4_len EQU 1
DMA1_ISR_TCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete flag
DMA1_ISR_TCIF4_ofs EQU 13
DMA1_ISR_TCIF4_len EQU 1
DMA1_ISR_HTIF4 EQU 0x00004000 ; Channel 4 Half Transfer Complete flag
DMA1_ISR_HTIF4_ofs EQU 14
DMA1_ISR_HTIF4_len EQU 1
DMA1_ISR_TEIF4 EQU 0x00008000 ; Channel 4 Transfer Error flag
DMA1_ISR_TEIF4_ofs EQU 15
DMA1_ISR_TEIF4_len EQU 1
DMA1_ISR_GIF5 EQU 0x00010000 ; Channel 5 Global interrupt flag
DMA1_ISR_GIF5_ofs EQU 16
DMA1_ISR_GIF5_len EQU 1
DMA1_ISR_TCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete flag
DMA1_ISR_TCIF5_ofs EQU 17
DMA1_ISR_TCIF5_len EQU 1
DMA1_ISR_HTIF5 EQU 0x00040000 ; Channel 5 Half Transfer Complete flag
DMA1_ISR_HTIF5_ofs EQU 18
DMA1_ISR_HTIF5_len EQU 1
DMA1_ISR_TEIF5 EQU 0x00080000 ; Channel 5 Transfer Error flag
DMA1_ISR_TEIF5_ofs EQU 19
DMA1_ISR_TEIF5_len EQU 1
DMA1_ISR_GIF6 EQU 0x00100000 ; Channel 6 Global interrupt flag
DMA1_ISR_GIF6_ofs EQU 20
DMA1_ISR_GIF6_len EQU 1
DMA1_ISR_TCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete flag
DMA1_ISR_TCIF6_ofs EQU 21
DMA1_ISR_TCIF6_len EQU 1
DMA1_ISR_HTIF6 EQU 0x00400000 ; Channel 6 Half Transfer Complete flag
DMA1_ISR_HTIF6_ofs EQU 22
DMA1_ISR_HTIF6_len EQU 1
DMA1_ISR_TEIF6 EQU 0x00800000 ; Channel 6 Transfer Error flag
DMA1_ISR_TEIF6_ofs EQU 23
DMA1_ISR_TEIF6_len EQU 1
DMA1_ISR_GIF7 EQU 0x01000000 ; Channel 7 Global interrupt flag
DMA1_ISR_GIF7_ofs EQU 24
DMA1_ISR_GIF7_len EQU 1
DMA1_ISR_TCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete flag
DMA1_ISR_TCIF7_ofs EQU 25
DMA1_ISR_TCIF7_len EQU 1
DMA1_ISR_HTIF7 EQU 0x04000000 ; Channel 7 Half Transfer Complete flag
DMA1_ISR_HTIF7_ofs EQU 26
DMA1_ISR_HTIF7_len EQU 1
DMA1_ISR_TEIF7 EQU 0x08000000 ; Channel 7 Transfer Error flag
DMA1_ISR_TEIF7_ofs EQU 27
DMA1_ISR_TEIF7_len EQU 1
; DMA1_IFCR fields:
DMA1_IFCR_CGIF1 EQU 0x00000001 ; Channel 1 Global interrupt clear
DMA1_IFCR_CGIF1_ofs EQU 0
DMA1_IFCR_CGIF1_len EQU 1
DMA1_IFCR_CTCIF1 EQU 0x00000002 ; Channel 1 Transfer Complete clear
DMA1_IFCR_CTCIF1_ofs EQU 1
DMA1_IFCR_CTCIF1_len EQU 1
DMA1_IFCR_CHTIF1 EQU 0x00000004 ; Channel 1 Half Transfer clear
DMA1_IFCR_CHTIF1_ofs EQU 2
DMA1_IFCR_CHTIF1_len EQU 1
DMA1_IFCR_CTEIF1 EQU 0x00000008 ; Channel 1 Transfer Error clear
DMA1_IFCR_CTEIF1_ofs EQU 3
DMA1_IFCR_CTEIF1_len EQU 1
DMA1_IFCR_CGIF2 EQU 0x00000010 ; Channel 2 Global interrupt clear
DMA1_IFCR_CGIF2_ofs EQU 4
DMA1_IFCR_CGIF2_len EQU 1
DMA1_IFCR_CTCIF2 EQU 0x00000020 ; Channel 2 Transfer Complete clear
DMA1_IFCR_CTCIF2_ofs EQU 5
DMA1_IFCR_CTCIF2_len EQU 1
DMA1_IFCR_CHTIF2 EQU 0x00000040 ; Channel 2 Half Transfer clear
DMA1_IFCR_CHTIF2_ofs EQU 6
DMA1_IFCR_CHTIF2_len EQU 1
DMA1_IFCR_CTEIF2 EQU 0x00000080 ; Channel 2 Transfer Error clear
DMA1_IFCR_CTEIF2_ofs EQU 7
DMA1_IFCR_CTEIF2_len EQU 1
DMA1_IFCR_CGIF3 EQU 0x00000100 ; Channel 3 Global interrupt clear
DMA1_IFCR_CGIF3_ofs EQU 8
DMA1_IFCR_CGIF3_len EQU 1
DMA1_IFCR_CTCIF3 EQU 0x00000200 ; Channel 3 Transfer Complete clear
DMA1_IFCR_CTCIF3_ofs EQU 9
DMA1_IFCR_CTCIF3_len EQU 1
DMA1_IFCR_CHTIF3 EQU 0x00000400 ; Channel 3 Half Transfer clear
DMA1_IFCR_CHTIF3_ofs EQU 10
DMA1_IFCR_CHTIF3_len EQU 1
DMA1_IFCR_CTEIF3 EQU 0x00000800 ; Channel 3 Transfer Error clear
DMA1_IFCR_CTEIF3_ofs EQU 11
DMA1_IFCR_CTEIF3_len EQU 1
DMA1_IFCR_CGIF4 EQU 0x00001000 ; Channel 4 Global interrupt clear
DMA1_IFCR_CGIF4_ofs EQU 12
DMA1_IFCR_CGIF4_len EQU 1
DMA1_IFCR_CTCIF4 EQU 0x00002000 ; Channel 4 Transfer Complete clear
DMA1_IFCR_CTCIF4_ofs EQU 13
DMA1_IFCR_CTCIF4_len EQU 1
DMA1_IFCR_CHTIF4 EQU 0x00004000 ; Channel 4 Half Transfer clear
DMA1_IFCR_CHTIF4_ofs EQU 14
DMA1_IFCR_CHTIF4_len EQU 1
DMA1_IFCR_CTEIF4 EQU 0x00008000 ; Channel 4 Transfer Error clear
DMA1_IFCR_CTEIF4_ofs EQU 15
DMA1_IFCR_CTEIF4_len EQU 1
DMA1_IFCR_CGIF5 EQU 0x00010000 ; Channel 5 Global interrupt clear
DMA1_IFCR_CGIF5_ofs EQU 16
DMA1_IFCR_CGIF5_len EQU 1
DMA1_IFCR_CTCIF5 EQU 0x00020000 ; Channel 5 Transfer Complete clear
DMA1_IFCR_CTCIF5_ofs EQU 17
DMA1_IFCR_CTCIF5_len EQU 1
DMA1_IFCR_CHTIF5 EQU 0x00040000 ; Channel 5 Half Transfer clear
DMA1_IFCR_CHTIF5_ofs EQU 18
DMA1_IFCR_CHTIF5_len EQU 1
DMA1_IFCR_CTEIF5 EQU 0x00080000 ; Channel 5 Transfer Error clear
DMA1_IFCR_CTEIF5_ofs EQU 19
DMA1_IFCR_CTEIF5_len EQU 1
DMA1_IFCR_CGIF6 EQU 0x00100000 ; Channel 6 Global interrupt clear
DMA1_IFCR_CGIF6_ofs EQU 20
DMA1_IFCR_CGIF6_len EQU 1
DMA1_IFCR_CTCIF6 EQU 0x00200000 ; Channel 6 Transfer Complete clear
DMA1_IFCR_CTCIF6_ofs EQU 21
DMA1_IFCR_CTCIF6_len EQU 1
DMA1_IFCR_CHTIF6 EQU 0x00400000 ; Channel 6 Half Transfer clear
DMA1_IFCR_CHTIF6_ofs EQU 22
DMA1_IFCR_CHTIF6_len EQU 1
DMA1_IFCR_CTEIF6 EQU 0x00800000 ; Channel 6 Transfer Error clear
DMA1_IFCR_CTEIF6_ofs EQU 23
DMA1_IFCR_CTEIF6_len EQU 1
DMA1_IFCR_CGIF7 EQU 0x01000000 ; Channel 7 Global interrupt clear
DMA1_IFCR_CGIF7_ofs EQU 24
DMA1_IFCR_CGIF7_len EQU 1
DMA1_IFCR_CTCIF7 EQU 0x02000000 ; Channel 7 Transfer Complete clear
DMA1_IFCR_CTCIF7_ofs EQU 25
DMA1_IFCR_CTCIF7_len EQU 1
DMA1_IFCR_CHTIF7 EQU 0x04000000 ; Channel 7 Half Transfer clear
DMA1_IFCR_CHTIF7_ofs EQU 26
DMA1_IFCR_CHTIF7_len EQU 1
DMA1_IFCR_CTEIF7 EQU 0x08000000 ; Channel 7 Transfer Error clear
DMA1_IFCR_CTEIF7_ofs EQU 27
DMA1_IFCR_CTEIF7_len EQU 1
; DMA1_CCR1 fields:
DMA1_CCR1_EN EQU 0x00000001 ; Channel enable
DMA1_CCR1_EN_ofs EQU 0
DMA1_CCR1_EN_len EQU 1
DMA1_CCR1_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR1_TCIE_ofs EQU 1
DMA1_CCR1_TCIE_len EQU 1
DMA1_CCR1_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR1_HTIE_ofs EQU 2
DMA1_CCR1_HTIE_len EQU 1
DMA1_CCR1_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR1_TEIE_ofs EQU 3
DMA1_CCR1_TEIE_len EQU 1
DMA1_CCR1_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR1_DIR_ofs EQU 4
DMA1_CCR1_DIR_len EQU 1
DMA1_CCR1_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR1_CIRC_ofs EQU 5
DMA1_CCR1_CIRC_len EQU 1
DMA1_CCR1_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR1_PINC_ofs EQU 6
DMA1_CCR1_PINC_len EQU 1
DMA1_CCR1_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR1_MINC_ofs EQU 7
DMA1_CCR1_MINC_len EQU 1
DMA1_CCR1_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR1_PSIZE_ofs EQU 8
DMA1_CCR1_PSIZE_len EQU 2
DMA1_CCR1_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR1_MSIZE_ofs EQU 10
DMA1_CCR1_MSIZE_len EQU 2
DMA1_CCR1_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR1_PL_ofs EQU 12
DMA1_CCR1_PL_len EQU 2
DMA1_CCR1_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR1_MEM2MEM_ofs EQU 14
DMA1_CCR1_MEM2MEM_len EQU 1
; DMA1_CNDTR1 fields:
DMA1_CNDTR1_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR1_NDT_ofs EQU 0
DMA1_CNDTR1_NDT_len EQU 16
; DMA1_CPAR1 fields:
DMA1_CPAR1_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR1_PA_ofs EQU 0
DMA1_CPAR1_PA_len EQU 32
; DMA1_CMAR1 fields:
DMA1_CMAR1_MA EQU 0xffffffff ; Memory address
DMA1_CMAR1_MA_ofs EQU 0
DMA1_CMAR1_MA_len EQU 32
; DMA1_CCR2 fields:
DMA1_CCR2_EN EQU 0x00000001 ; Channel enable
DMA1_CCR2_EN_ofs EQU 0
DMA1_CCR2_EN_len EQU 1
DMA1_CCR2_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR2_TCIE_ofs EQU 1
DMA1_CCR2_TCIE_len EQU 1
DMA1_CCR2_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR2_HTIE_ofs EQU 2
DMA1_CCR2_HTIE_len EQU 1
DMA1_CCR2_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR2_TEIE_ofs EQU 3
DMA1_CCR2_TEIE_len EQU 1
DMA1_CCR2_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR2_DIR_ofs EQU 4
DMA1_CCR2_DIR_len EQU 1
DMA1_CCR2_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR2_CIRC_ofs EQU 5
DMA1_CCR2_CIRC_len EQU 1
DMA1_CCR2_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR2_PINC_ofs EQU 6
DMA1_CCR2_PINC_len EQU 1
DMA1_CCR2_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR2_MINC_ofs EQU 7
DMA1_CCR2_MINC_len EQU 1
DMA1_CCR2_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR2_PSIZE_ofs EQU 8
DMA1_CCR2_PSIZE_len EQU 2
DMA1_CCR2_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR2_MSIZE_ofs EQU 10
DMA1_CCR2_MSIZE_len EQU 2
DMA1_CCR2_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR2_PL_ofs EQU 12
DMA1_CCR2_PL_len EQU 2
DMA1_CCR2_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR2_MEM2MEM_ofs EQU 14
DMA1_CCR2_MEM2MEM_len EQU 1
; DMA1_CNDTR2 fields:
DMA1_CNDTR2_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR2_NDT_ofs EQU 0
DMA1_CNDTR2_NDT_len EQU 16
; DMA1_CPAR2 fields:
DMA1_CPAR2_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR2_PA_ofs EQU 0
DMA1_CPAR2_PA_len EQU 32
; DMA1_CMAR2 fields:
DMA1_CMAR2_MA EQU 0xffffffff ; Memory address
DMA1_CMAR2_MA_ofs EQU 0
DMA1_CMAR2_MA_len EQU 32
; DMA1_CCR3 fields:
DMA1_CCR3_EN EQU 0x00000001 ; Channel enable
DMA1_CCR3_EN_ofs EQU 0
DMA1_CCR3_EN_len EQU 1
DMA1_CCR3_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR3_TCIE_ofs EQU 1
DMA1_CCR3_TCIE_len EQU 1
DMA1_CCR3_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR3_HTIE_ofs EQU 2
DMA1_CCR3_HTIE_len EQU 1
DMA1_CCR3_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR3_TEIE_ofs EQU 3
DMA1_CCR3_TEIE_len EQU 1
DMA1_CCR3_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR3_DIR_ofs EQU 4
DMA1_CCR3_DIR_len EQU 1
DMA1_CCR3_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR3_CIRC_ofs EQU 5
DMA1_CCR3_CIRC_len EQU 1
DMA1_CCR3_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR3_PINC_ofs EQU 6
DMA1_CCR3_PINC_len EQU 1
DMA1_CCR3_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR3_MINC_ofs EQU 7
DMA1_CCR3_MINC_len EQU 1
DMA1_CCR3_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR3_PSIZE_ofs EQU 8
DMA1_CCR3_PSIZE_len EQU 2
DMA1_CCR3_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR3_MSIZE_ofs EQU 10
DMA1_CCR3_MSIZE_len EQU 2
DMA1_CCR3_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR3_PL_ofs EQU 12
DMA1_CCR3_PL_len EQU 2
DMA1_CCR3_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR3_MEM2MEM_ofs EQU 14
DMA1_CCR3_MEM2MEM_len EQU 1
; DMA1_CNDTR3 fields:
DMA1_CNDTR3_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR3_NDT_ofs EQU 0
DMA1_CNDTR3_NDT_len EQU 16
; DMA1_CPAR3 fields:
DMA1_CPAR3_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR3_PA_ofs EQU 0
DMA1_CPAR3_PA_len EQU 32
; DMA1_CMAR3 fields:
DMA1_CMAR3_MA EQU 0xffffffff ; Memory address
DMA1_CMAR3_MA_ofs EQU 0
DMA1_CMAR3_MA_len EQU 32
; DMA1_CCR4 fields:
DMA1_CCR4_EN EQU 0x00000001 ; Channel enable
DMA1_CCR4_EN_ofs EQU 0
DMA1_CCR4_EN_len EQU 1
DMA1_CCR4_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR4_TCIE_ofs EQU 1
DMA1_CCR4_TCIE_len EQU 1
DMA1_CCR4_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR4_HTIE_ofs EQU 2
DMA1_CCR4_HTIE_len EQU 1
DMA1_CCR4_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR4_TEIE_ofs EQU 3
DMA1_CCR4_TEIE_len EQU 1
DMA1_CCR4_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR4_DIR_ofs EQU 4
DMA1_CCR4_DIR_len EQU 1
DMA1_CCR4_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR4_CIRC_ofs EQU 5
DMA1_CCR4_CIRC_len EQU 1
DMA1_CCR4_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR4_PINC_ofs EQU 6
DMA1_CCR4_PINC_len EQU 1
DMA1_CCR4_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR4_MINC_ofs EQU 7
DMA1_CCR4_MINC_len EQU 1
DMA1_CCR4_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR4_PSIZE_ofs EQU 8
DMA1_CCR4_PSIZE_len EQU 2
DMA1_CCR4_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR4_MSIZE_ofs EQU 10
DMA1_CCR4_MSIZE_len EQU 2
DMA1_CCR4_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR4_PL_ofs EQU 12
DMA1_CCR4_PL_len EQU 2
DMA1_CCR4_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR4_MEM2MEM_ofs EQU 14
DMA1_CCR4_MEM2MEM_len EQU 1
; DMA1_CNDTR4 fields:
DMA1_CNDTR4_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR4_NDT_ofs EQU 0
DMA1_CNDTR4_NDT_len EQU 16
; DMA1_CPAR4 fields:
DMA1_CPAR4_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR4_PA_ofs EQU 0
DMA1_CPAR4_PA_len EQU 32
; DMA1_CMAR4 fields:
DMA1_CMAR4_MA EQU 0xffffffff ; Memory address
DMA1_CMAR4_MA_ofs EQU 0
DMA1_CMAR4_MA_len EQU 32
; DMA1_CCR5 fields:
DMA1_CCR5_EN EQU 0x00000001 ; Channel enable
DMA1_CCR5_EN_ofs EQU 0
DMA1_CCR5_EN_len EQU 1
DMA1_CCR5_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR5_TCIE_ofs EQU 1
DMA1_CCR5_TCIE_len EQU 1
DMA1_CCR5_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR5_HTIE_ofs EQU 2
DMA1_CCR5_HTIE_len EQU 1
DMA1_CCR5_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR5_TEIE_ofs EQU 3
DMA1_CCR5_TEIE_len EQU 1
DMA1_CCR5_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR5_DIR_ofs EQU 4
DMA1_CCR5_DIR_len EQU 1
DMA1_CCR5_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR5_CIRC_ofs EQU 5
DMA1_CCR5_CIRC_len EQU 1
DMA1_CCR5_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR5_PINC_ofs EQU 6
DMA1_CCR5_PINC_len EQU 1
DMA1_CCR5_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR5_MINC_ofs EQU 7
DMA1_CCR5_MINC_len EQU 1
DMA1_CCR5_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR5_PSIZE_ofs EQU 8
DMA1_CCR5_PSIZE_len EQU 2
DMA1_CCR5_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR5_MSIZE_ofs EQU 10
DMA1_CCR5_MSIZE_len EQU 2
DMA1_CCR5_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR5_PL_ofs EQU 12
DMA1_CCR5_PL_len EQU 2
DMA1_CCR5_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR5_MEM2MEM_ofs EQU 14
DMA1_CCR5_MEM2MEM_len EQU 1
; DMA1_CNDTR5 fields:
DMA1_CNDTR5_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR5_NDT_ofs EQU 0
DMA1_CNDTR5_NDT_len EQU 16
; DMA1_CPAR5 fields:
DMA1_CPAR5_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR5_PA_ofs EQU 0
DMA1_CPAR5_PA_len EQU 32
; DMA1_CMAR5 fields:
DMA1_CMAR5_MA EQU 0xffffffff ; Memory address
DMA1_CMAR5_MA_ofs EQU 0
DMA1_CMAR5_MA_len EQU 32
; DMA1_CCR6 fields:
DMA1_CCR6_EN EQU 0x00000001 ; Channel enable
DMA1_CCR6_EN_ofs EQU 0
DMA1_CCR6_EN_len EQU 1
DMA1_CCR6_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR6_TCIE_ofs EQU 1
DMA1_CCR6_TCIE_len EQU 1
DMA1_CCR6_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR6_HTIE_ofs EQU 2
DMA1_CCR6_HTIE_len EQU 1
DMA1_CCR6_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR6_TEIE_ofs EQU 3
DMA1_CCR6_TEIE_len EQU 1
DMA1_CCR6_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR6_DIR_ofs EQU 4
DMA1_CCR6_DIR_len EQU 1
DMA1_CCR6_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR6_CIRC_ofs EQU 5
DMA1_CCR6_CIRC_len EQU 1
DMA1_CCR6_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR6_PINC_ofs EQU 6
DMA1_CCR6_PINC_len EQU 1
DMA1_CCR6_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR6_MINC_ofs EQU 7
DMA1_CCR6_MINC_len EQU 1
DMA1_CCR6_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR6_PSIZE_ofs EQU 8
DMA1_CCR6_PSIZE_len EQU 2
DMA1_CCR6_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR6_MSIZE_ofs EQU 10
DMA1_CCR6_MSIZE_len EQU 2
DMA1_CCR6_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR6_PL_ofs EQU 12
DMA1_CCR6_PL_len EQU 2
DMA1_CCR6_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR6_MEM2MEM_ofs EQU 14
DMA1_CCR6_MEM2MEM_len EQU 1
; DMA1_CNDTR6 fields:
DMA1_CNDTR6_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR6_NDT_ofs EQU 0
DMA1_CNDTR6_NDT_len EQU 16
; DMA1_CPAR6 fields:
DMA1_CPAR6_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR6_PA_ofs EQU 0
DMA1_CPAR6_PA_len EQU 32
; DMA1_CMAR6 fields:
DMA1_CMAR6_MA EQU 0xffffffff ; Memory address
DMA1_CMAR6_MA_ofs EQU 0
DMA1_CMAR6_MA_len EQU 32
; DMA1_CCR7 fields:
DMA1_CCR7_EN EQU 0x00000001 ; Channel enable
DMA1_CCR7_EN_ofs EQU 0
DMA1_CCR7_EN_len EQU 1
DMA1_CCR7_TCIE EQU 0x00000002 ; Transfer complete interrupt enable
DMA1_CCR7_TCIE_ofs EQU 1
DMA1_CCR7_TCIE_len EQU 1
DMA1_CCR7_HTIE EQU 0x00000004 ; Half Transfer interrupt enable
DMA1_CCR7_HTIE_ofs EQU 2
DMA1_CCR7_HTIE_len EQU 1
DMA1_CCR7_TEIE EQU 0x00000008 ; Transfer error interrupt enable
DMA1_CCR7_TEIE_ofs EQU 3
DMA1_CCR7_TEIE_len EQU 1
DMA1_CCR7_DIR EQU 0x00000010 ; Data transfer direction
DMA1_CCR7_DIR_ofs EQU 4
DMA1_CCR7_DIR_len EQU 1
DMA1_CCR7_CIRC EQU 0x00000020 ; Circular mode
DMA1_CCR7_CIRC_ofs EQU 5
DMA1_CCR7_CIRC_len EQU 1
DMA1_CCR7_PINC EQU 0x00000040 ; Peripheral increment mode
DMA1_CCR7_PINC_ofs EQU 6
DMA1_CCR7_PINC_len EQU 1
DMA1_CCR7_MINC EQU 0x00000080 ; Memory increment mode
DMA1_CCR7_MINC_ofs EQU 7
DMA1_CCR7_MINC_len EQU 1
DMA1_CCR7_PSIZE EQU 0x00000300 ; Peripheral size
DMA1_CCR7_PSIZE_ofs EQU 8
DMA1_CCR7_PSIZE_len EQU 2
DMA1_CCR7_MSIZE EQU 0x00000c00 ; Memory size
DMA1_CCR7_MSIZE_ofs EQU 10
DMA1_CCR7_MSIZE_len EQU 2
DMA1_CCR7_PL EQU 0x00003000 ; Channel Priority level
DMA1_CCR7_PL_ofs EQU 12
DMA1_CCR7_PL_len EQU 2
DMA1_CCR7_MEM2MEM EQU 0x00004000 ; Memory to memory mode
DMA1_CCR7_MEM2MEM_ofs EQU 14
DMA1_CCR7_MEM2MEM_len EQU 1
; DMA1_CNDTR7 fields:
DMA1_CNDTR7_NDT EQU 0x0000ffff ; Number of data to transfer
DMA1_CNDTR7_NDT_ofs EQU 0
DMA1_CNDTR7_NDT_len EQU 16
; DMA1_CPAR7 fields:
DMA1_CPAR7_PA EQU 0xffffffff ; Peripheral address
DMA1_CPAR7_PA_ofs EQU 0
DMA1_CPAR7_PA_len EQU 32
; DMA1_CMAR7 fields:
DMA1_CMAR7_MA EQU 0xffffffff ; Memory address
DMA1_CMAR7_MA_ofs EQU 0
DMA1_CMAR7_MA_len EQU 32
; ---- DMA2 --------------------------------------------------
; Desc: None
; DMA2 base address:
DMA2_BASE EQU 0x40020400
; DMA2 registers:
; ---- TIM2 --------------------------------------------------
; Desc: General purpose timer
; TIM2 base address:
TIM2_BASE EQU 0x40000000
; TIM2 registers:
TIM2_CR1 EQU (TIM2_BASE + 0x0) ; control register 1
TIM2_CR2 EQU (TIM2_BASE + 0x4) ; control register 2
TIM2_SMCR EQU (TIM2_BASE + 0x8) ; slave mode control register
TIM2_DIER EQU (TIM2_BASE + 0xc) ; DMA/Interrupt enable register
TIM2_SR EQU (TIM2_BASE + 0x10) ; status register
TIM2_EGR EQU (TIM2_BASE + 0x14) ; event generation register
TIM2_CCMR1_Output EQU (TIM2_BASE + 0x18) ; capture/compare mode register 1 (output mode)
TIM2_CCMR1_Input EQU (TIM2_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM2_CCMR2_Output EQU (TIM2_BASE + 0x1c) ; capture/compare mode register 2 (output mode)
TIM2_CCMR2_Input EQU (TIM2_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM2_CCER EQU (TIM2_BASE + 0x20) ; capture/compare enable register
TIM2_CNT EQU (TIM2_BASE + 0x24) ; counter
TIM2_PSC EQU (TIM2_BASE + 0x28) ; prescaler
TIM2_ARR EQU (TIM2_BASE + 0x2c) ; auto-reload register
TIM2_CCR1 EQU (TIM2_BASE + 0x34) ; capture/compare register 1
TIM2_CCR2 EQU (TIM2_BASE + 0x38) ; capture/compare register 2
TIM2_CCR3 EQU (TIM2_BASE + 0x3c) ; capture/compare register 3
TIM2_CCR4 EQU (TIM2_BASE + 0x40) ; capture/compare register 4
TIM2_DCR EQU (TIM2_BASE + 0x48) ; DMA control register
TIM2_DMAR EQU (TIM2_BASE + 0x4c) ; DMA address for full transfer
; TIM2_CR1 fields:
TIM2_CR1_CEN EQU 0x00000001 ; Counter enable
TIM2_CR1_CEN_ofs EQU 0
TIM2_CR1_CEN_len EQU 1
TIM2_CR1_UDIS EQU 0x00000002 ; Update disable
TIM2_CR1_UDIS_ofs EQU 1
TIM2_CR1_UDIS_len EQU 1
TIM2_CR1_URS EQU 0x00000004 ; Update request source
TIM2_CR1_URS_ofs EQU 2
TIM2_CR1_URS_len EQU 1
TIM2_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM2_CR1_OPM_ofs EQU 3
TIM2_CR1_OPM_len EQU 1
TIM2_CR1_DIR EQU 0x00000010 ; Direction
TIM2_CR1_DIR_ofs EQU 4
TIM2_CR1_DIR_len EQU 1
TIM2_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM2_CR1_CMS_ofs EQU 5
TIM2_CR1_CMS_len EQU 2
TIM2_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM2_CR1_ARPE_ofs EQU 7
TIM2_CR1_ARPE_len EQU 1
TIM2_CR1_CKD EQU 0x00000300 ; Clock division
TIM2_CR1_CKD_ofs EQU 8
TIM2_CR1_CKD_len EQU 2
TIM2_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM2_CR1_UIFREMAP_ofs EQU 11
TIM2_CR1_UIFREMAP_len EQU 1
; TIM2_CR2 fields:
TIM2_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM2_CR2_TI1S_ofs EQU 7
TIM2_CR2_TI1S_len EQU 1
TIM2_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM2_CR2_MMS_ofs EQU 4
TIM2_CR2_MMS_len EQU 3
TIM2_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM2_CR2_CCDS_ofs EQU 3
TIM2_CR2_CCDS_len EQU 1
; TIM2_SMCR fields:
TIM2_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM2_SMCR_SMS_ofs EQU 0
TIM2_SMCR_SMS_len EQU 3
TIM2_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM2_SMCR_OCCS_ofs EQU 3
TIM2_SMCR_OCCS_len EQU 1
TIM2_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM2_SMCR_TS_ofs EQU 4
TIM2_SMCR_TS_len EQU 3
TIM2_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM2_SMCR_MSM_ofs EQU 7
TIM2_SMCR_MSM_len EQU 1
TIM2_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM2_SMCR_ETF_ofs EQU 8
TIM2_SMCR_ETF_len EQU 4
TIM2_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM2_SMCR_ETPS_ofs EQU 12
TIM2_SMCR_ETPS_len EQU 2
TIM2_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM2_SMCR_ECE_ofs EQU 14
TIM2_SMCR_ECE_len EQU 1
TIM2_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM2_SMCR_ETP_ofs EQU 15
TIM2_SMCR_ETP_len EQU 1
TIM2_SMCR_SMS_3 EQU 0x00010000 ; Slave mode selection bit3
TIM2_SMCR_SMS_3_ofs EQU 16
TIM2_SMCR_SMS_3_len EQU 1
; TIM2_DIER fields:
TIM2_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM2_DIER_TDE_ofs EQU 14
TIM2_DIER_TDE_len EQU 1
TIM2_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM2_DIER_CC4DE_ofs EQU 12
TIM2_DIER_CC4DE_len EQU 1
TIM2_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM2_DIER_CC3DE_ofs EQU 11
TIM2_DIER_CC3DE_len EQU 1
TIM2_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM2_DIER_CC2DE_ofs EQU 10
TIM2_DIER_CC2DE_len EQU 1
TIM2_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM2_DIER_CC1DE_ofs EQU 9
TIM2_DIER_CC1DE_len EQU 1
TIM2_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM2_DIER_UDE_ofs EQU 8
TIM2_DIER_UDE_len EQU 1
TIM2_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM2_DIER_TIE_ofs EQU 6
TIM2_DIER_TIE_len EQU 1
TIM2_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM2_DIER_CC4IE_ofs EQU 4
TIM2_DIER_CC4IE_len EQU 1
TIM2_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM2_DIER_CC3IE_ofs EQU 3
TIM2_DIER_CC3IE_len EQU 1
TIM2_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM2_DIER_CC2IE_ofs EQU 2
TIM2_DIER_CC2IE_len EQU 1
TIM2_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM2_DIER_CC1IE_ofs EQU 1
TIM2_DIER_CC1IE_len EQU 1
TIM2_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM2_DIER_UIE_ofs EQU 0
TIM2_DIER_UIE_len EQU 1
; TIM2_SR fields:
TIM2_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM2_SR_CC4OF_ofs EQU 12
TIM2_SR_CC4OF_len EQU 1
TIM2_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM2_SR_CC3OF_ofs EQU 11
TIM2_SR_CC3OF_len EQU 1
TIM2_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM2_SR_CC2OF_ofs EQU 10
TIM2_SR_CC2OF_len EQU 1
TIM2_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM2_SR_CC1OF_ofs EQU 9
TIM2_SR_CC1OF_len EQU 1
TIM2_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM2_SR_TIF_ofs EQU 6
TIM2_SR_TIF_len EQU 1
TIM2_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM2_SR_CC4IF_ofs EQU 4
TIM2_SR_CC4IF_len EQU 1
TIM2_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM2_SR_CC3IF_ofs EQU 3
TIM2_SR_CC3IF_len EQU 1
TIM2_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM2_SR_CC2IF_ofs EQU 2
TIM2_SR_CC2IF_len EQU 1
TIM2_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM2_SR_CC1IF_ofs EQU 1
TIM2_SR_CC1IF_len EQU 1
TIM2_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM2_SR_UIF_ofs EQU 0
TIM2_SR_UIF_len EQU 1
; TIM2_EGR fields:
TIM2_EGR_TG EQU 0x00000040 ; Trigger generation
TIM2_EGR_TG_ofs EQU 6
TIM2_EGR_TG_len EQU 1
TIM2_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM2_EGR_CC4G_ofs EQU 4
TIM2_EGR_CC4G_len EQU 1
TIM2_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM2_EGR_CC3G_ofs EQU 3
TIM2_EGR_CC3G_len EQU 1
TIM2_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM2_EGR_CC2G_ofs EQU 2
TIM2_EGR_CC2G_len EQU 1
TIM2_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM2_EGR_CC1G_ofs EQU 1
TIM2_EGR_CC1G_len EQU 1
TIM2_EGR_UG EQU 0x00000001 ; Update generation
TIM2_EGR_UG_ofs EQU 0
TIM2_EGR_UG_len EQU 1
; TIM2_CCMR1_Output fields:
TIM2_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM2_CCMR1_Output_CC1S_ofs EQU 0
TIM2_CCMR1_Output_CC1S_len EQU 2
TIM2_CCMR1_Output_OC1FE EQU 0x00000004 ; Output compare 1 fast enable
TIM2_CCMR1_Output_OC1FE_ofs EQU 2
TIM2_CCMR1_Output_OC1FE_len EQU 1
TIM2_CCMR1_Output_OC1PE EQU 0x00000008 ; Output compare 1 preload enable
TIM2_CCMR1_Output_OC1PE_ofs EQU 3
TIM2_CCMR1_Output_OC1PE_len EQU 1
TIM2_CCMR1_Output_OC1M EQU 0x00000070 ; Output compare 1 mode
TIM2_CCMR1_Output_OC1M_ofs EQU 4
TIM2_CCMR1_Output_OC1M_len EQU 3
TIM2_CCMR1_Output_OC1CE EQU 0x00000080 ; Output compare 1 clear enable
TIM2_CCMR1_Output_OC1CE_ofs EQU 7
TIM2_CCMR1_Output_OC1CE_len EQU 1
TIM2_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM2_CCMR1_Output_CC2S_ofs EQU 8
TIM2_CCMR1_Output_CC2S_len EQU 2
TIM2_CCMR1_Output_OC2FE EQU 0x00000400 ; Output compare 2 fast enable
TIM2_CCMR1_Output_OC2FE_ofs EQU 10
TIM2_CCMR1_Output_OC2FE_len EQU 1
TIM2_CCMR1_Output_OC2PE EQU 0x00000800 ; Output compare 2 preload enable
TIM2_CCMR1_Output_OC2PE_ofs EQU 11
TIM2_CCMR1_Output_OC2PE_len EQU 1
TIM2_CCMR1_Output_OC2M EQU 0x00007000 ; Output compare 2 mode
TIM2_CCMR1_Output_OC2M_ofs EQU 12
TIM2_CCMR1_Output_OC2M_len EQU 3
TIM2_CCMR1_Output_OC2CE EQU 0x00008000 ; Output compare 2 clear enable
TIM2_CCMR1_Output_OC2CE_ofs EQU 15
TIM2_CCMR1_Output_OC2CE_len EQU 1
TIM2_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output compare 1 mode bit 3
TIM2_CCMR1_Output_OC1M_3_ofs EQU 16
TIM2_CCMR1_Output_OC1M_3_len EQU 1
TIM2_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output compare 2 mode bit 3
TIM2_CCMR1_Output_OC2M_3_ofs EQU 24
TIM2_CCMR1_Output_OC2M_3_len EQU 1
; TIM2_CCMR1_Input fields:
TIM2_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM2_CCMR1_Input_IC2F_ofs EQU 12
TIM2_CCMR1_Input_IC2F_len EQU 4
TIM2_CCMR1_Input_IC2PSC EQU 0x00000c00 ; Input capture 2 prescaler
TIM2_CCMR1_Input_IC2PSC_ofs EQU 10
TIM2_CCMR1_Input_IC2PSC_len EQU 2
TIM2_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/compare 2 selection
TIM2_CCMR1_Input_CC2S_ofs EQU 8
TIM2_CCMR1_Input_CC2S_len EQU 2
TIM2_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM2_CCMR1_Input_IC1F_ofs EQU 4
TIM2_CCMR1_Input_IC1F_len EQU 4
TIM2_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM2_CCMR1_Input_IC1PSC_ofs EQU 2
TIM2_CCMR1_Input_IC1PSC_len EQU 2
TIM2_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM2_CCMR1_Input_CC1S_ofs EQU 0
TIM2_CCMR1_Input_CC1S_len EQU 2
; TIM2_CCMR2_Output fields:
TIM2_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM2_CCMR2_Output_CC3S_ofs EQU 0
TIM2_CCMR2_Output_CC3S_len EQU 2
TIM2_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM2_CCMR2_Output_OC3FE_ofs EQU 2
TIM2_CCMR2_Output_OC3FE_len EQU 1
TIM2_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM2_CCMR2_Output_OC3PE_ofs EQU 3
TIM2_CCMR2_Output_OC3PE_len EQU 1
TIM2_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM2_CCMR2_Output_OC3M_ofs EQU 4
TIM2_CCMR2_Output_OC3M_len EQU 3
TIM2_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM2_CCMR2_Output_OC3CE_ofs EQU 7
TIM2_CCMR2_Output_OC3CE_len EQU 1
TIM2_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM2_CCMR2_Output_CC4S_ofs EQU 8
TIM2_CCMR2_Output_CC4S_len EQU 2
TIM2_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM2_CCMR2_Output_OC4FE_ofs EQU 10
TIM2_CCMR2_Output_OC4FE_len EQU 1
TIM2_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM2_CCMR2_Output_OC4PE_ofs EQU 11
TIM2_CCMR2_Output_OC4PE_len EQU 1
TIM2_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM2_CCMR2_Output_OC4M_ofs EQU 12
TIM2_CCMR2_Output_OC4M_len EQU 3
TIM2_CCMR2_Output_O24CE EQU 0x00008000 ; Output compare 4 clear enable
TIM2_CCMR2_Output_O24CE_ofs EQU 15
TIM2_CCMR2_Output_O24CE_len EQU 1
TIM2_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output compare 3 mode bit3
TIM2_CCMR2_Output_OC3M_3_ofs EQU 16
TIM2_CCMR2_Output_OC3M_3_len EQU 1
TIM2_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output compare 4 mode bit3
TIM2_CCMR2_Output_OC4M_3_ofs EQU 24
TIM2_CCMR2_Output_OC4M_3_len EQU 1
; TIM2_CCMR2_Input fields:
TIM2_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM2_CCMR2_Input_IC4F_ofs EQU 12
TIM2_CCMR2_Input_IC4F_len EQU 4
TIM2_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM2_CCMR2_Input_IC4PSC_ofs EQU 10
TIM2_CCMR2_Input_IC4PSC_len EQU 2
TIM2_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM2_CCMR2_Input_CC4S_ofs EQU 8
TIM2_CCMR2_Input_CC4S_len EQU 2
TIM2_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM2_CCMR2_Input_IC3F_ofs EQU 4
TIM2_CCMR2_Input_IC3F_len EQU 4
TIM2_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM2_CCMR2_Input_IC3PSC_ofs EQU 2
TIM2_CCMR2_Input_IC3PSC_len EQU 2
TIM2_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM2_CCMR2_Input_CC3S_ofs EQU 0
TIM2_CCMR2_Input_CC3S_len EQU 2
; TIM2_CCER fields:
TIM2_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM2_CCER_CC1E_ofs EQU 0
TIM2_CCER_CC1E_len EQU 1
TIM2_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM2_CCER_CC1P_ofs EQU 1
TIM2_CCER_CC1P_len EQU 1
TIM2_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM2_CCER_CC1NP_ofs EQU 3
TIM2_CCER_CC1NP_len EQU 1
TIM2_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM2_CCER_CC2E_ofs EQU 4
TIM2_CCER_CC2E_len EQU 1
TIM2_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM2_CCER_CC2P_ofs EQU 5
TIM2_CCER_CC2P_len EQU 1
TIM2_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM2_CCER_CC2NP_ofs EQU 7
TIM2_CCER_CC2NP_len EQU 1
TIM2_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM2_CCER_CC3E_ofs EQU 8
TIM2_CCER_CC3E_len EQU 1
TIM2_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC3P_ofs EQU 9
TIM2_CCER_CC3P_len EQU 1
TIM2_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC3NP_ofs EQU 11
TIM2_CCER_CC3NP_len EQU 1
TIM2_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM2_CCER_CC4E_ofs EQU 12
TIM2_CCER_CC4E_len EQU 1
TIM2_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC4P_ofs EQU 13
TIM2_CCER_CC4P_len EQU 1
TIM2_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 3 output Polarity
TIM2_CCER_CC4NP_ofs EQU 15
TIM2_CCER_CC4NP_len EQU 1
; TIM2_CNT fields:
TIM2_CNT_CNTL EQU 0x0000ffff ; Low counter value
TIM2_CNT_CNTL_ofs EQU 0
TIM2_CNT_CNTL_len EQU 16
TIM2_CNT_CNTH EQU 0x7fff0000 ; High counter value
TIM2_CNT_CNTH_ofs EQU 16
TIM2_CNT_CNTH_len EQU 15
TIM2_CNT_CNT_or_UIFCPY EQU 0x80000000 ; if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
TIM2_CNT_CNT_or_UIFCPY_ofs EQU 31
TIM2_CNT_CNT_or_UIFCPY_len EQU 1
; TIM2_PSC fields:
TIM2_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM2_PSC_PSC_ofs EQU 0
TIM2_PSC_PSC_len EQU 16
; TIM2_ARR fields:
TIM2_ARR_ARRL EQU 0x0000ffff ; Low Auto-reload value
TIM2_ARR_ARRL_ofs EQU 0
TIM2_ARR_ARRL_len EQU 16
TIM2_ARR_ARRH EQU 0xffff0000 ; High Auto-reload value
TIM2_ARR_ARRH_ofs EQU 16
TIM2_ARR_ARRH_len EQU 16
; TIM2_CCR1 fields:
TIM2_CCR1_CCR1L EQU 0x0000ffff ; Low Capture/Compare 1 value
TIM2_CCR1_CCR1L_ofs EQU 0
TIM2_CCR1_CCR1L_len EQU 16
TIM2_CCR1_CCR1H EQU 0xffff0000 ; High Capture/Compare 1 value (on TIM2)
TIM2_CCR1_CCR1H_ofs EQU 16
TIM2_CCR1_CCR1H_len EQU 16
; TIM2_CCR2 fields:
TIM2_CCR2_CCR2L EQU 0x0000ffff ; Low Capture/Compare 2 value
TIM2_CCR2_CCR2L_ofs EQU 0
TIM2_CCR2_CCR2L_len EQU 16
TIM2_CCR2_CCR2H EQU 0xffff0000 ; High Capture/Compare 2 value (on TIM2)
TIM2_CCR2_CCR2H_ofs EQU 16
TIM2_CCR2_CCR2H_len EQU 16
; TIM2_CCR3 fields:
TIM2_CCR3_CCR3L EQU 0x0000ffff ; Low Capture/Compare value
TIM2_CCR3_CCR3L_ofs EQU 0
TIM2_CCR3_CCR3L_len EQU 16
TIM2_CCR3_CCR3H EQU 0xffff0000 ; High Capture/Compare value (on TIM2)
TIM2_CCR3_CCR3H_ofs EQU 16
TIM2_CCR3_CCR3H_len EQU 16
; TIM2_CCR4 fields:
TIM2_CCR4_CCR4L EQU 0x0000ffff ; Low Capture/Compare value
TIM2_CCR4_CCR4L_ofs EQU 0
TIM2_CCR4_CCR4L_len EQU 16
TIM2_CCR4_CCR4H EQU 0xffff0000 ; High Capture/Compare value (on TIM2)
TIM2_CCR4_CCR4H_ofs EQU 16
TIM2_CCR4_CCR4H_len EQU 16
; TIM2_DCR fields:
TIM2_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM2_DCR_DBL_ofs EQU 8
TIM2_DCR_DBL_len EQU 5
TIM2_DCR_DBA EQU 0x0000001f ; DMA base address
TIM2_DCR_DBA_ofs EQU 0
TIM2_DCR_DBA_len EQU 5
; TIM2_DMAR fields:
TIM2_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM2_DMAR_DMAB_ofs EQU 0
TIM2_DMAR_DMAB_len EQU 16
; ---- TIM3 --------------------------------------------------
; Desc: None
; TIM3 base address:
TIM3_BASE EQU 0x40000400
; TIM3 registers:
; ---- TIM4 --------------------------------------------------
; Desc: None
; TIM4 base address:
TIM4_BASE EQU 0x40000800
; TIM4 registers:
; ---- TIM15 -------------------------------------------------
; Desc: General purpose timers
; TIM15 base address:
TIM15_BASE EQU 0x40014000
; TIM15 registers:
TIM15_CR1 EQU (TIM15_BASE + 0x0) ; control register 1
TIM15_CR2 EQU (TIM15_BASE + 0x4) ; control register 2
TIM15_SMCR EQU (TIM15_BASE + 0x8) ; slave mode control register
TIM15_DIER EQU (TIM15_BASE + 0xc) ; DMA/Interrupt enable register
TIM15_SR EQU (TIM15_BASE + 0x10) ; status register
TIM15_EGR EQU (TIM15_BASE + 0x14) ; event generation register
TIM15_CCMR1_Output EQU (TIM15_BASE + 0x18) ; capture/compare mode register (output mode)
TIM15_CCMR1_Input EQU (TIM15_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM15_CCER EQU (TIM15_BASE + 0x20) ; capture/compare enable register
TIM15_CNT EQU (TIM15_BASE + 0x24) ; counter
TIM15_PSC EQU (TIM15_BASE + 0x28) ; prescaler
TIM15_ARR EQU (TIM15_BASE + 0x2c) ; auto-reload register
TIM15_RCR EQU (TIM15_BASE + 0x30) ; repetition counter register
TIM15_CCR1 EQU (TIM15_BASE + 0x34) ; capture/compare register 1
TIM15_CCR2 EQU (TIM15_BASE + 0x38) ; capture/compare register 2
TIM15_BDTR EQU (TIM15_BASE + 0x44) ; break and dead-time register
TIM15_DCR EQU (TIM15_BASE + 0x48) ; DMA control register
TIM15_DMAR EQU (TIM15_BASE + 0x4c) ; DMA address for full transfer
; TIM15_CR1 fields:
TIM15_CR1_CEN EQU 0x00000001 ; Counter enable
TIM15_CR1_CEN_ofs EQU 0
TIM15_CR1_CEN_len EQU 1
TIM15_CR1_UDIS EQU 0x00000002 ; Update disable
TIM15_CR1_UDIS_ofs EQU 1
TIM15_CR1_UDIS_len EQU 1
TIM15_CR1_URS EQU 0x00000004 ; Update request source
TIM15_CR1_URS_ofs EQU 2
TIM15_CR1_URS_len EQU 1
TIM15_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM15_CR1_OPM_ofs EQU 3
TIM15_CR1_OPM_len EQU 1
TIM15_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM15_CR1_ARPE_ofs EQU 7
TIM15_CR1_ARPE_len EQU 1
TIM15_CR1_CKD EQU 0x00000300 ; Clock division
TIM15_CR1_CKD_ofs EQU 8
TIM15_CR1_CKD_len EQU 2
TIM15_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM15_CR1_UIFREMAP_ofs EQU 11
TIM15_CR1_UIFREMAP_len EQU 1
; TIM15_CR2 fields:
TIM15_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM15_CR2_CCPC_ofs EQU 0
TIM15_CR2_CCPC_len EQU 1
TIM15_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM15_CR2_CCUS_ofs EQU 2
TIM15_CR2_CCUS_len EQU 1
TIM15_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM15_CR2_CCDS_ofs EQU 3
TIM15_CR2_CCDS_len EQU 1
TIM15_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM15_CR2_MMS_ofs EQU 4
TIM15_CR2_MMS_len EQU 3
TIM15_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM15_CR2_TI1S_ofs EQU 7
TIM15_CR2_TI1S_len EQU 1
TIM15_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM15_CR2_OIS1_ofs EQU 8
TIM15_CR2_OIS1_len EQU 1
TIM15_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM15_CR2_OIS1N_ofs EQU 9
TIM15_CR2_OIS1N_len EQU 1
TIM15_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM15_CR2_OIS2_ofs EQU 10
TIM15_CR2_OIS2_len EQU 1
; TIM15_SMCR fields:
TIM15_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM15_SMCR_SMS_ofs EQU 0
TIM15_SMCR_SMS_len EQU 3
TIM15_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM15_SMCR_TS_ofs EQU 4
TIM15_SMCR_TS_len EQU 3
TIM15_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM15_SMCR_MSM_ofs EQU 7
TIM15_SMCR_MSM_len EQU 1
TIM15_SMCR_SMS_3 EQU 0x00010000 ; Slave mode selection bit 3
TIM15_SMCR_SMS_3_ofs EQU 16
TIM15_SMCR_SMS_3_len EQU 1
; TIM15_DIER fields:
TIM15_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM15_DIER_UIE_ofs EQU 0
TIM15_DIER_UIE_len EQU 1
TIM15_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM15_DIER_CC1IE_ofs EQU 1
TIM15_DIER_CC1IE_len EQU 1
TIM15_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM15_DIER_CC2IE_ofs EQU 2
TIM15_DIER_CC2IE_len EQU 1
TIM15_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM15_DIER_COMIE_ofs EQU 5
TIM15_DIER_COMIE_len EQU 1
TIM15_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM15_DIER_TIE_ofs EQU 6
TIM15_DIER_TIE_len EQU 1
TIM15_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM15_DIER_BIE_ofs EQU 7
TIM15_DIER_BIE_len EQU 1
TIM15_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM15_DIER_UDE_ofs EQU 8
TIM15_DIER_UDE_len EQU 1
TIM15_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM15_DIER_CC1DE_ofs EQU 9
TIM15_DIER_CC1DE_len EQU 1
TIM15_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM15_DIER_CC2DE_ofs EQU 10
TIM15_DIER_CC2DE_len EQU 1
TIM15_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM15_DIER_COMDE_ofs EQU 13
TIM15_DIER_COMDE_len EQU 1
TIM15_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM15_DIER_TDE_ofs EQU 14
TIM15_DIER_TDE_len EQU 1
; TIM15_SR fields:
TIM15_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM15_SR_CC2OF_ofs EQU 10
TIM15_SR_CC2OF_len EQU 1
TIM15_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM15_SR_CC1OF_ofs EQU 9
TIM15_SR_CC1OF_len EQU 1
TIM15_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM15_SR_BIF_ofs EQU 7
TIM15_SR_BIF_len EQU 1
TIM15_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM15_SR_TIF_ofs EQU 6
TIM15_SR_TIF_len EQU 1
TIM15_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM15_SR_COMIF_ofs EQU 5
TIM15_SR_COMIF_len EQU 1
TIM15_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM15_SR_CC2IF_ofs EQU 2
TIM15_SR_CC2IF_len EQU 1
TIM15_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM15_SR_CC1IF_ofs EQU 1
TIM15_SR_CC1IF_len EQU 1
TIM15_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM15_SR_UIF_ofs EQU 0
TIM15_SR_UIF_len EQU 1
; TIM15_EGR fields:
TIM15_EGR_BG EQU 0x00000080 ; Break generation
TIM15_EGR_BG_ofs EQU 7
TIM15_EGR_BG_len EQU 1
TIM15_EGR_TG EQU 0x00000040 ; Trigger generation
TIM15_EGR_TG_ofs EQU 6
TIM15_EGR_TG_len EQU 1
TIM15_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM15_EGR_COMG_ofs EQU 5
TIM15_EGR_COMG_len EQU 1
TIM15_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM15_EGR_CC2G_ofs EQU 2
TIM15_EGR_CC2G_len EQU 1
TIM15_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM15_EGR_CC1G_ofs EQU 1
TIM15_EGR_CC1G_len EQU 1
TIM15_EGR_UG EQU 0x00000001 ; Update generation
TIM15_EGR_UG_ofs EQU 0
TIM15_EGR_UG_len EQU 1
; TIM15_CCMR1_Output fields:
TIM15_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM15_CCMR1_Output_CC1S_ofs EQU 0
TIM15_CCMR1_Output_CC1S_len EQU 2
TIM15_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM15_CCMR1_Output_OC1FE_ofs EQU 2
TIM15_CCMR1_Output_OC1FE_len EQU 1
TIM15_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM15_CCMR1_Output_OC1PE_ofs EQU 3
TIM15_CCMR1_Output_OC1PE_len EQU 1
TIM15_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM15_CCMR1_Output_OC1M_ofs EQU 4
TIM15_CCMR1_Output_OC1M_len EQU 3
TIM15_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM15_CCMR1_Output_CC2S_ofs EQU 8
TIM15_CCMR1_Output_CC2S_len EQU 2
TIM15_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM15_CCMR1_Output_OC2FE_ofs EQU 10
TIM15_CCMR1_Output_OC2FE_len EQU 1
TIM15_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM15_CCMR1_Output_OC2PE_ofs EQU 11
TIM15_CCMR1_Output_OC2PE_len EQU 1
TIM15_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM15_CCMR1_Output_OC2M_ofs EQU 12
TIM15_CCMR1_Output_OC2M_len EQU 3
TIM15_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM15_CCMR1_Output_OC1M_3_ofs EQU 16
TIM15_CCMR1_Output_OC1M_3_len EQU 1
TIM15_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM15_CCMR1_Output_OC2M_3_ofs EQU 24
TIM15_CCMR1_Output_OC2M_3_len EQU 1
; TIM15_CCMR1_Input fields:
TIM15_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM15_CCMR1_Input_IC2F_ofs EQU 12
TIM15_CCMR1_Input_IC2F_len EQU 4
TIM15_CCMR1_Input_IC2PSC EQU 0x00000c00 ; Input capture 2 prescaler
TIM15_CCMR1_Input_IC2PSC_ofs EQU 10
TIM15_CCMR1_Input_IC2PSC_len EQU 2
TIM15_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM15_CCMR1_Input_CC2S_ofs EQU 8
TIM15_CCMR1_Input_CC2S_len EQU 2
TIM15_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM15_CCMR1_Input_IC1F_ofs EQU 4
TIM15_CCMR1_Input_IC1F_len EQU 4
TIM15_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM15_CCMR1_Input_IC1PSC_ofs EQU 2
TIM15_CCMR1_Input_IC1PSC_len EQU 2
TIM15_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM15_CCMR1_Input_CC1S_ofs EQU 0
TIM15_CCMR1_Input_CC1S_len EQU 2
; TIM15_CCER fields:
TIM15_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM15_CCER_CC2NP_ofs EQU 7
TIM15_CCER_CC2NP_len EQU 1
TIM15_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM15_CCER_CC2P_ofs EQU 5
TIM15_CCER_CC2P_len EQU 1
TIM15_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM15_CCER_CC2E_ofs EQU 4
TIM15_CCER_CC2E_len EQU 1
TIM15_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM15_CCER_CC1NP_ofs EQU 3
TIM15_CCER_CC1NP_len EQU 1
TIM15_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM15_CCER_CC1NE_ofs EQU 2
TIM15_CCER_CC1NE_len EQU 1
TIM15_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM15_CCER_CC1P_ofs EQU 1
TIM15_CCER_CC1P_len EQU 1
TIM15_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM15_CCER_CC1E_ofs EQU 0
TIM15_CCER_CC1E_len EQU 1
; TIM15_CNT fields:
TIM15_CNT_CNT EQU 0x0000ffff ; counter value
TIM15_CNT_CNT_ofs EQU 0
TIM15_CNT_CNT_len EQU 16
TIM15_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM15_CNT_UIFCPY_ofs EQU 31
TIM15_CNT_UIFCPY_len EQU 1
; TIM15_PSC fields:
TIM15_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM15_PSC_PSC_ofs EQU 0
TIM15_PSC_PSC_len EQU 16
; TIM15_ARR fields:
TIM15_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM15_ARR_ARR_ofs EQU 0
TIM15_ARR_ARR_len EQU 16
; TIM15_RCR fields:
TIM15_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM15_RCR_REP_ofs EQU 0
TIM15_RCR_REP_len EQU 8
; TIM15_CCR1 fields:
TIM15_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM15_CCR1_CCR1_ofs EQU 0
TIM15_CCR1_CCR1_len EQU 16
; TIM15_CCR2 fields:
TIM15_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM15_CCR2_CCR2_ofs EQU 0
TIM15_CCR2_CCR2_len EQU 16
; TIM15_BDTR fields:
TIM15_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM15_BDTR_MOE_ofs EQU 15
TIM15_BDTR_MOE_len EQU 1
TIM15_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM15_BDTR_AOE_ofs EQU 14
TIM15_BDTR_AOE_len EQU 1
TIM15_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM15_BDTR_BKP_ofs EQU 13
TIM15_BDTR_BKP_len EQU 1
TIM15_BDTR_BKE EQU 0x00001000 ; Break enable
TIM15_BDTR_BKE_ofs EQU 12
TIM15_BDTR_BKE_len EQU 1
TIM15_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM15_BDTR_OSSR_ofs EQU 11
TIM15_BDTR_OSSR_len EQU 1
TIM15_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM15_BDTR_OSSI_ofs EQU 10
TIM15_BDTR_OSSI_len EQU 1
TIM15_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM15_BDTR_LOCK_ofs EQU 8
TIM15_BDTR_LOCK_len EQU 2
TIM15_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM15_BDTR_DTG_ofs EQU 0
TIM15_BDTR_DTG_len EQU 8
TIM15_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM15_BDTR_BKF_ofs EQU 16
TIM15_BDTR_BKF_len EQU 4
; TIM15_DCR fields:
TIM15_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM15_DCR_DBL_ofs EQU 8
TIM15_DCR_DBL_len EQU 5
TIM15_DCR_DBA EQU 0x0000001f ; DMA base address
TIM15_DCR_DBA_ofs EQU 0
TIM15_DCR_DBA_len EQU 5
; TIM15_DMAR fields:
TIM15_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM15_DMAR_DMAB_ofs EQU 0
TIM15_DMAR_DMAB_len EQU 16
; ---- TIM16 -------------------------------------------------
; Desc: General-purpose-timers
; TIM16 base address:
TIM16_BASE EQU 0x40014400
; TIM16 registers:
TIM16_CR1 EQU (TIM16_BASE + 0x0) ; control register 1
TIM16_CR2 EQU (TIM16_BASE + 0x4) ; control register 2
TIM16_DIER EQU (TIM16_BASE + 0xc) ; DMA/Interrupt enable register
TIM16_SR EQU (TIM16_BASE + 0x10) ; status register
TIM16_EGR EQU (TIM16_BASE + 0x14) ; event generation register
TIM16_CCMR1_Output EQU (TIM16_BASE + 0x18) ; capture/compare mode register (output mode)
TIM16_CCMR1_Input EQU (TIM16_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM16_CCER EQU (TIM16_BASE + 0x20) ; capture/compare enable register
TIM16_CNT EQU (TIM16_BASE + 0x24) ; counter
TIM16_PSC EQU (TIM16_BASE + 0x28) ; prescaler
TIM16_ARR EQU (TIM16_BASE + 0x2c) ; auto-reload register
TIM16_RCR EQU (TIM16_BASE + 0x30) ; repetition counter register
TIM16_CCR1 EQU (TIM16_BASE + 0x34) ; capture/compare register 1
TIM16_BDTR EQU (TIM16_BASE + 0x44) ; break and dead-time register
TIM16_DCR EQU (TIM16_BASE + 0x48) ; DMA control register
TIM16_DMAR EQU (TIM16_BASE + 0x4c) ; DMA address for full transfer
TIM16_OR EQU (TIM16_BASE + 0x50) ; option register
; TIM16_CR1 fields:
TIM16_CR1_CEN EQU 0x00000001 ; Counter enable
TIM16_CR1_CEN_ofs EQU 0
TIM16_CR1_CEN_len EQU 1
TIM16_CR1_UDIS EQU 0x00000002 ; Update disable
TIM16_CR1_UDIS_ofs EQU 1
TIM16_CR1_UDIS_len EQU 1
TIM16_CR1_URS EQU 0x00000004 ; Update request source
TIM16_CR1_URS_ofs EQU 2
TIM16_CR1_URS_len EQU 1
TIM16_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM16_CR1_OPM_ofs EQU 3
TIM16_CR1_OPM_len EQU 1
TIM16_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM16_CR1_ARPE_ofs EQU 7
TIM16_CR1_ARPE_len EQU 1
TIM16_CR1_CKD EQU 0x00000300 ; Clock division
TIM16_CR1_CKD_ofs EQU 8
TIM16_CR1_CKD_len EQU 2
TIM16_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM16_CR1_UIFREMAP_ofs EQU 11
TIM16_CR1_UIFREMAP_len EQU 1
; TIM16_CR2 fields:
TIM16_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM16_CR2_OIS1N_ofs EQU 9
TIM16_CR2_OIS1N_len EQU 1
TIM16_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM16_CR2_OIS1_ofs EQU 8
TIM16_CR2_OIS1_len EQU 1
TIM16_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM16_CR2_CCDS_ofs EQU 3
TIM16_CR2_CCDS_len EQU 1
TIM16_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM16_CR2_CCUS_ofs EQU 2
TIM16_CR2_CCUS_len EQU 1
TIM16_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM16_CR2_CCPC_ofs EQU 0
TIM16_CR2_CCPC_len EQU 1
; TIM16_DIER fields:
TIM16_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM16_DIER_UIE_ofs EQU 0
TIM16_DIER_UIE_len EQU 1
TIM16_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM16_DIER_CC1IE_ofs EQU 1
TIM16_DIER_CC1IE_len EQU 1
TIM16_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM16_DIER_COMIE_ofs EQU 5
TIM16_DIER_COMIE_len EQU 1
TIM16_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM16_DIER_TIE_ofs EQU 6
TIM16_DIER_TIE_len EQU 1
TIM16_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM16_DIER_BIE_ofs EQU 7
TIM16_DIER_BIE_len EQU 1
TIM16_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM16_DIER_UDE_ofs EQU 8
TIM16_DIER_UDE_len EQU 1
TIM16_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM16_DIER_CC1DE_ofs EQU 9
TIM16_DIER_CC1DE_len EQU 1
TIM16_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM16_DIER_COMDE_ofs EQU 13
TIM16_DIER_COMDE_len EQU 1
TIM16_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM16_DIER_TDE_ofs EQU 14
TIM16_DIER_TDE_len EQU 1
; TIM16_SR fields:
TIM16_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM16_SR_CC1OF_ofs EQU 9
TIM16_SR_CC1OF_len EQU 1
TIM16_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM16_SR_BIF_ofs EQU 7
TIM16_SR_BIF_len EQU 1
TIM16_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM16_SR_TIF_ofs EQU 6
TIM16_SR_TIF_len EQU 1
TIM16_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM16_SR_COMIF_ofs EQU 5
TIM16_SR_COMIF_len EQU 1
TIM16_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM16_SR_CC1IF_ofs EQU 1
TIM16_SR_CC1IF_len EQU 1
TIM16_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM16_SR_UIF_ofs EQU 0
TIM16_SR_UIF_len EQU 1
; TIM16_EGR fields:
TIM16_EGR_BG EQU 0x00000080 ; Break generation
TIM16_EGR_BG_ofs EQU 7
TIM16_EGR_BG_len EQU 1
TIM16_EGR_TG EQU 0x00000040 ; Trigger generation
TIM16_EGR_TG_ofs EQU 6
TIM16_EGR_TG_len EQU 1
TIM16_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM16_EGR_COMG_ofs EQU 5
TIM16_EGR_COMG_len EQU 1
TIM16_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM16_EGR_CC1G_ofs EQU 1
TIM16_EGR_CC1G_len EQU 1
TIM16_EGR_UG EQU 0x00000001 ; Update generation
TIM16_EGR_UG_ofs EQU 0
TIM16_EGR_UG_len EQU 1
; TIM16_CCMR1_Output fields:
TIM16_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM16_CCMR1_Output_CC1S_ofs EQU 0
TIM16_CCMR1_Output_CC1S_len EQU 2
TIM16_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM16_CCMR1_Output_OC1FE_ofs EQU 2
TIM16_CCMR1_Output_OC1FE_len EQU 1
TIM16_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM16_CCMR1_Output_OC1PE_ofs EQU 3
TIM16_CCMR1_Output_OC1PE_len EQU 1
TIM16_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM16_CCMR1_Output_OC1M_ofs EQU 4
TIM16_CCMR1_Output_OC1M_len EQU 3
TIM16_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode
TIM16_CCMR1_Output_OC1M_3_ofs EQU 16
TIM16_CCMR1_Output_OC1M_3_len EQU 1
; TIM16_CCMR1_Input fields:
TIM16_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM16_CCMR1_Input_IC1F_ofs EQU 4
TIM16_CCMR1_Input_IC1F_len EQU 4
TIM16_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM16_CCMR1_Input_IC1PSC_ofs EQU 2
TIM16_CCMR1_Input_IC1PSC_len EQU 2
TIM16_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM16_CCMR1_Input_CC1S_ofs EQU 0
TIM16_CCMR1_Input_CC1S_len EQU 2
; TIM16_CCER fields:
TIM16_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM16_CCER_CC1NP_ofs EQU 3
TIM16_CCER_CC1NP_len EQU 1
TIM16_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM16_CCER_CC1NE_ofs EQU 2
TIM16_CCER_CC1NE_len EQU 1
TIM16_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM16_CCER_CC1P_ofs EQU 1
TIM16_CCER_CC1P_len EQU 1
TIM16_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM16_CCER_CC1E_ofs EQU 0
TIM16_CCER_CC1E_len EQU 1
; TIM16_CNT fields:
TIM16_CNT_CNT EQU 0x0000ffff ; counter value
TIM16_CNT_CNT_ofs EQU 0
TIM16_CNT_CNT_len EQU 16
TIM16_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM16_CNT_UIFCPY_ofs EQU 31
TIM16_CNT_UIFCPY_len EQU 1
; TIM16_PSC fields:
TIM16_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM16_PSC_PSC_ofs EQU 0
TIM16_PSC_PSC_len EQU 16
; TIM16_ARR fields:
TIM16_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM16_ARR_ARR_ofs EQU 0
TIM16_ARR_ARR_len EQU 16
; TIM16_RCR fields:
TIM16_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM16_RCR_REP_ofs EQU 0
TIM16_RCR_REP_len EQU 8
; TIM16_CCR1 fields:
TIM16_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM16_CCR1_CCR1_ofs EQU 0
TIM16_CCR1_CCR1_len EQU 16
; TIM16_BDTR fields:
TIM16_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM16_BDTR_DTG_ofs EQU 0
TIM16_BDTR_DTG_len EQU 8
TIM16_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM16_BDTR_LOCK_ofs EQU 8
TIM16_BDTR_LOCK_len EQU 2
TIM16_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM16_BDTR_OSSI_ofs EQU 10
TIM16_BDTR_OSSI_len EQU 1
TIM16_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM16_BDTR_OSSR_ofs EQU 11
TIM16_BDTR_OSSR_len EQU 1
TIM16_BDTR_BKE EQU 0x00001000 ; Break enable
TIM16_BDTR_BKE_ofs EQU 12
TIM16_BDTR_BKE_len EQU 1
TIM16_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM16_BDTR_BKP_ofs EQU 13
TIM16_BDTR_BKP_len EQU 1
TIM16_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM16_BDTR_AOE_ofs EQU 14
TIM16_BDTR_AOE_len EQU 1
TIM16_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM16_BDTR_MOE_ofs EQU 15
TIM16_BDTR_MOE_len EQU 1
TIM16_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM16_BDTR_BKF_ofs EQU 16
TIM16_BDTR_BKF_len EQU 4
; TIM16_DCR fields:
TIM16_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM16_DCR_DBL_ofs EQU 8
TIM16_DCR_DBL_len EQU 5
TIM16_DCR_DBA EQU 0x0000001f ; DMA base address
TIM16_DCR_DBA_ofs EQU 0
TIM16_DCR_DBA_len EQU 5
; TIM16_DMAR fields:
TIM16_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM16_DMAR_DMAB_ofs EQU 0
TIM16_DMAR_DMAB_len EQU 16
; TIM16_OR fields:
; ---- TIM17 -------------------------------------------------
; Desc: General purpose timer
; TIM17 base address:
TIM17_BASE EQU 0x40014800
; TIM17 registers:
TIM17_CR1 EQU (TIM17_BASE + 0x0) ; control register 1
TIM17_CR2 EQU (TIM17_BASE + 0x4) ; control register 2
TIM17_DIER EQU (TIM17_BASE + 0xc) ; DMA/Interrupt enable register
TIM17_SR EQU (TIM17_BASE + 0x10) ; status register
TIM17_EGR EQU (TIM17_BASE + 0x14) ; event generation register
TIM17_CCMR1_Output EQU (TIM17_BASE + 0x18) ; capture/compare mode register (output mode)
TIM17_CCMR1_Input EQU (TIM17_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM17_CCER EQU (TIM17_BASE + 0x20) ; capture/compare enable register
TIM17_CNT EQU (TIM17_BASE + 0x24) ; counter
TIM17_PSC EQU (TIM17_BASE + 0x28) ; prescaler
TIM17_ARR EQU (TIM17_BASE + 0x2c) ; auto-reload register
TIM17_RCR EQU (TIM17_BASE + 0x30) ; repetition counter register
TIM17_CCR1 EQU (TIM17_BASE + 0x34) ; capture/compare register 1
TIM17_BDTR EQU (TIM17_BASE + 0x44) ; break and dead-time register
TIM17_DCR EQU (TIM17_BASE + 0x48) ; DMA control register
TIM17_DMAR EQU (TIM17_BASE + 0x4c) ; DMA address for full transfer
; TIM17_CR1 fields:
TIM17_CR1_CEN EQU 0x00000001 ; Counter enable
TIM17_CR1_CEN_ofs EQU 0
TIM17_CR1_CEN_len EQU 1
TIM17_CR1_UDIS EQU 0x00000002 ; Update disable
TIM17_CR1_UDIS_ofs EQU 1
TIM17_CR1_UDIS_len EQU 1
TIM17_CR1_URS EQU 0x00000004 ; Update request source
TIM17_CR1_URS_ofs EQU 2
TIM17_CR1_URS_len EQU 1
TIM17_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM17_CR1_OPM_ofs EQU 3
TIM17_CR1_OPM_len EQU 1
TIM17_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM17_CR1_ARPE_ofs EQU 7
TIM17_CR1_ARPE_len EQU 1
TIM17_CR1_CKD EQU 0x00000300 ; Clock division
TIM17_CR1_CKD_ofs EQU 8
TIM17_CR1_CKD_len EQU 2
TIM17_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM17_CR1_UIFREMAP_ofs EQU 11
TIM17_CR1_UIFREMAP_len EQU 1
; TIM17_CR2 fields:
TIM17_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM17_CR2_OIS1N_ofs EQU 9
TIM17_CR2_OIS1N_len EQU 1
TIM17_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM17_CR2_OIS1_ofs EQU 8
TIM17_CR2_OIS1_len EQU 1
TIM17_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM17_CR2_CCDS_ofs EQU 3
TIM17_CR2_CCDS_len EQU 1
TIM17_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM17_CR2_CCUS_ofs EQU 2
TIM17_CR2_CCUS_len EQU 1
TIM17_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM17_CR2_CCPC_ofs EQU 0
TIM17_CR2_CCPC_len EQU 1
; TIM17_DIER fields:
TIM17_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM17_DIER_UIE_ofs EQU 0
TIM17_DIER_UIE_len EQU 1
TIM17_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM17_DIER_CC1IE_ofs EQU 1
TIM17_DIER_CC1IE_len EQU 1
TIM17_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM17_DIER_COMIE_ofs EQU 5
TIM17_DIER_COMIE_len EQU 1
TIM17_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM17_DIER_TIE_ofs EQU 6
TIM17_DIER_TIE_len EQU 1
TIM17_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM17_DIER_BIE_ofs EQU 7
TIM17_DIER_BIE_len EQU 1
TIM17_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM17_DIER_UDE_ofs EQU 8
TIM17_DIER_UDE_len EQU 1
TIM17_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM17_DIER_CC1DE_ofs EQU 9
TIM17_DIER_CC1DE_len EQU 1
TIM17_DIER_COMDE EQU 0x00002000 ; COM DMA request enable
TIM17_DIER_COMDE_ofs EQU 13
TIM17_DIER_COMDE_len EQU 1
TIM17_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM17_DIER_TDE_ofs EQU 14
TIM17_DIER_TDE_len EQU 1
; TIM17_SR fields:
TIM17_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM17_SR_CC1OF_ofs EQU 9
TIM17_SR_CC1OF_len EQU 1
TIM17_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM17_SR_BIF_ofs EQU 7
TIM17_SR_BIF_len EQU 1
TIM17_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM17_SR_TIF_ofs EQU 6
TIM17_SR_TIF_len EQU 1
TIM17_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM17_SR_COMIF_ofs EQU 5
TIM17_SR_COMIF_len EQU 1
TIM17_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM17_SR_CC1IF_ofs EQU 1
TIM17_SR_CC1IF_len EQU 1
TIM17_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM17_SR_UIF_ofs EQU 0
TIM17_SR_UIF_len EQU 1
; TIM17_EGR fields:
TIM17_EGR_BG EQU 0x00000080 ; Break generation
TIM17_EGR_BG_ofs EQU 7
TIM17_EGR_BG_len EQU 1
TIM17_EGR_TG EQU 0x00000040 ; Trigger generation
TIM17_EGR_TG_ofs EQU 6
TIM17_EGR_TG_len EQU 1
TIM17_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM17_EGR_COMG_ofs EQU 5
TIM17_EGR_COMG_len EQU 1
TIM17_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM17_EGR_CC1G_ofs EQU 1
TIM17_EGR_CC1G_len EQU 1
TIM17_EGR_UG EQU 0x00000001 ; Update generation
TIM17_EGR_UG_ofs EQU 0
TIM17_EGR_UG_len EQU 1
; TIM17_CCMR1_Output fields:
TIM17_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM17_CCMR1_Output_CC1S_ofs EQU 0
TIM17_CCMR1_Output_CC1S_len EQU 2
TIM17_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM17_CCMR1_Output_OC1FE_ofs EQU 2
TIM17_CCMR1_Output_OC1FE_len EQU 1
TIM17_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM17_CCMR1_Output_OC1PE_ofs EQU 3
TIM17_CCMR1_Output_OC1PE_len EQU 1
TIM17_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM17_CCMR1_Output_OC1M_ofs EQU 4
TIM17_CCMR1_Output_OC1M_len EQU 3
TIM17_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode
TIM17_CCMR1_Output_OC1M_3_ofs EQU 16
TIM17_CCMR1_Output_OC1M_3_len EQU 1
; TIM17_CCMR1_Input fields:
TIM17_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM17_CCMR1_Input_IC1F_ofs EQU 4
TIM17_CCMR1_Input_IC1F_len EQU 4
TIM17_CCMR1_Input_IC1PSC EQU 0x0000000c ; Input capture 1 prescaler
TIM17_CCMR1_Input_IC1PSC_ofs EQU 2
TIM17_CCMR1_Input_IC1PSC_len EQU 2
TIM17_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM17_CCMR1_Input_CC1S_ofs EQU 0
TIM17_CCMR1_Input_CC1S_len EQU 2
; TIM17_CCER fields:
TIM17_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM17_CCER_CC1NP_ofs EQU 3
TIM17_CCER_CC1NP_len EQU 1
TIM17_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM17_CCER_CC1NE_ofs EQU 2
TIM17_CCER_CC1NE_len EQU 1
TIM17_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM17_CCER_CC1P_ofs EQU 1
TIM17_CCER_CC1P_len EQU 1
TIM17_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM17_CCER_CC1E_ofs EQU 0
TIM17_CCER_CC1E_len EQU 1
; TIM17_CNT fields:
TIM17_CNT_CNT EQU 0x0000ffff ; counter value
TIM17_CNT_CNT_ofs EQU 0
TIM17_CNT_CNT_len EQU 16
TIM17_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM17_CNT_UIFCPY_ofs EQU 31
TIM17_CNT_UIFCPY_len EQU 1
; TIM17_PSC fields:
TIM17_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM17_PSC_PSC_ofs EQU 0
TIM17_PSC_PSC_len EQU 16
; TIM17_ARR fields:
TIM17_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM17_ARR_ARR_ofs EQU 0
TIM17_ARR_ARR_len EQU 16
; TIM17_RCR fields:
TIM17_RCR_REP EQU 0x000000ff ; Repetition counter value
TIM17_RCR_REP_ofs EQU 0
TIM17_RCR_REP_len EQU 8
; TIM17_CCR1 fields:
TIM17_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM17_CCR1_CCR1_ofs EQU 0
TIM17_CCR1_CCR1_len EQU 16
; TIM17_BDTR fields:
TIM17_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM17_BDTR_DTG_ofs EQU 0
TIM17_BDTR_DTG_len EQU 8
TIM17_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM17_BDTR_LOCK_ofs EQU 8
TIM17_BDTR_LOCK_len EQU 2
TIM17_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM17_BDTR_OSSI_ofs EQU 10
TIM17_BDTR_OSSI_len EQU 1
TIM17_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM17_BDTR_OSSR_ofs EQU 11
TIM17_BDTR_OSSR_len EQU 1
TIM17_BDTR_BKE EQU 0x00001000 ; Break enable
TIM17_BDTR_BKE_ofs EQU 12
TIM17_BDTR_BKE_len EQU 1
TIM17_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM17_BDTR_BKP_ofs EQU 13
TIM17_BDTR_BKP_len EQU 1
TIM17_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM17_BDTR_AOE_ofs EQU 14
TIM17_BDTR_AOE_len EQU 1
TIM17_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM17_BDTR_MOE_ofs EQU 15
TIM17_BDTR_MOE_len EQU 1
TIM17_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM17_BDTR_BKF_ofs EQU 16
TIM17_BDTR_BKF_len EQU 4
; TIM17_DCR fields:
TIM17_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM17_DCR_DBL_ofs EQU 8
TIM17_DCR_DBL_len EQU 5
TIM17_DCR_DBA EQU 0x0000001f ; DMA base address
TIM17_DCR_DBA_ofs EQU 0
TIM17_DCR_DBA_len EQU 5
; TIM17_DMAR fields:
TIM17_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM17_DMAR_DMAB_ofs EQU 0
TIM17_DMAR_DMAB_len EQU 16
; ---- USART1 ------------------------------------------------
; Desc: Universal synchronous asynchronous receiver transmitter
; USART1 base address:
USART1_BASE EQU 0x40013800
; USART1 registers:
USART1_CR1 EQU (USART1_BASE + 0x0) ; Control register 1
USART1_CR2 EQU (USART1_BASE + 0x4) ; Control register 2
USART1_CR3 EQU (USART1_BASE + 0x8) ; Control register 3
USART1_BRR EQU (USART1_BASE + 0xc) ; Baud rate register
USART1_GTPR EQU (USART1_BASE + 0x10) ; Guard time and prescaler register
USART1_RTOR EQU (USART1_BASE + 0x14) ; Receiver timeout register
USART1_RQR EQU (USART1_BASE + 0x18) ; Request register
USART1_ISR EQU (USART1_BASE + 0x1c) ; Interrupt & status register
USART1_ICR EQU (USART1_BASE + 0x20) ; Interrupt flag clear register
USART1_RDR EQU (USART1_BASE + 0x24) ; Receive data register
USART1_TDR EQU (USART1_BASE + 0x28) ; Transmit data register
; USART1_CR1 fields:
USART_CR1_EOBIE EQU 0x08000000 ; End of Block interrupt enable
USART_CR1_EOBIE_ofs EQU 27
USART_CR1_EOBIE_len EQU 1
USART_CR1_RTOIE EQU 0x04000000 ; Receiver timeout interrupt enable
USART_CR1_RTOIE_ofs EQU 26
USART_CR1_RTOIE_len EQU 1
USART_CR1_DEAT EQU 0x03e00000 ; Driver Enable assertion time
USART_CR1_DEAT_ofs EQU 21
USART_CR1_DEAT_len EQU 5
USART_CR1_DEDT EQU 0x001f0000 ; Driver Enable deassertion time
USART_CR1_DEDT_ofs EQU 16
USART_CR1_DEDT_len EQU 5
USART_CR1_OVER8 EQU 0x00008000 ; Oversampling mode
USART_CR1_OVER8_ofs EQU 15
USART_CR1_OVER8_len EQU 1
USART_CR1_CMIE EQU 0x00004000 ; Character match interrupt enable
USART_CR1_CMIE_ofs EQU 14
USART_CR1_CMIE_len EQU 1
USART_CR1_MME EQU 0x00002000 ; Mute mode enable
USART_CR1_MME_ofs EQU 13
USART_CR1_MME_len EQU 1
USART_CR1_M EQU 0x00001000 ; Word length
USART_CR1_M_ofs EQU 12
USART_CR1_M_len EQU 1
USART_CR1_WAKE EQU 0x00000800 ; Receiver wakeup method
USART_CR1_WAKE_ofs EQU 11
USART_CR1_WAKE_len EQU 1
USART_CR1_PCE EQU 0x00000400 ; Parity control enable
USART_CR1_PCE_ofs EQU 10
USART_CR1_PCE_len EQU 1
USART_CR1_PS EQU 0x00000200 ; Parity selection
USART_CR1_PS_ofs EQU 9
USART_CR1_PS_len EQU 1
USART_CR1_PEIE EQU 0x00000100 ; PE interrupt enable
USART_CR1_PEIE_ofs EQU 8
USART_CR1_PEIE_len EQU 1
USART_CR1_TXEIE EQU 0x00000080 ; interrupt enable
USART_CR1_TXEIE_ofs EQU 7
USART_CR1_TXEIE_len EQU 1
USART_CR1_TCIE EQU 0x00000040 ; Transmission complete interrupt enable
USART_CR1_TCIE_ofs EQU 6
USART_CR1_TCIE_len EQU 1
USART_CR1_RXNEIE EQU 0x00000020 ; RXNE interrupt enable
USART_CR1_RXNEIE_ofs EQU 5
USART_CR1_RXNEIE_len EQU 1
USART_CR1_IDLEIE EQU 0x00000010 ; IDLE interrupt enable
USART_CR1_IDLEIE_ofs EQU 4
USART_CR1_IDLEIE_len EQU 1
USART_CR1_TE EQU 0x00000008 ; Transmitter enable
USART_CR1_TE_ofs EQU 3
USART_CR1_TE_len EQU 1
USART_CR1_RE EQU 0x00000004 ; Receiver enable
USART_CR1_RE_ofs EQU 2
USART_CR1_RE_len EQU 1
USART_CR1_UESM EQU 0x00000002 ; USART enable in Stop mode
USART_CR1_UESM_ofs EQU 1
USART_CR1_UESM_len EQU 1
USART_CR1_UE EQU 0x00000001 ; USART enable
USART_CR1_UE_ofs EQU 0
USART_CR1_UE_len EQU 1
; USART1_CR2 fields:
USART_CR2_ADD4 EQU 0xf0000000 ; Address of the USART node
USART_CR2_ADD4_ofs EQU 28
USART_CR2_ADD4_len EQU 4
USART_CR2_ADD0 EQU 0x0f000000 ; Address of the USART node
USART_CR2_ADD0_ofs EQU 24
USART_CR2_ADD0_len EQU 4
USART_CR2_RTOEN EQU 0x00800000 ; Receiver timeout enable
USART_CR2_RTOEN_ofs EQU 23
USART_CR2_RTOEN_len EQU 1
USART_CR2_ABRMOD EQU 0x00600000 ; Auto baud rate mode
USART_CR2_ABRMOD_ofs EQU 21
USART_CR2_ABRMOD_len EQU 2
USART_CR2_ABREN EQU 0x00100000 ; Auto baud rate enable
USART_CR2_ABREN_ofs EQU 20
USART_CR2_ABREN_len EQU 1
USART_CR2_MSBFIRST EQU 0x00080000 ; Most significant bit first
USART_CR2_MSBFIRST_ofs EQU 19
USART_CR2_MSBFIRST_len EQU 1
USART_CR2_DATAINV EQU 0x00040000 ; Binary data inversion
USART_CR2_DATAINV_ofs EQU 18
USART_CR2_DATAINV_len EQU 1
USART_CR2_TXINV EQU 0x00020000 ; TX pin active level inversion
USART_CR2_TXINV_ofs EQU 17
USART_CR2_TXINV_len EQU 1
USART_CR2_RXINV EQU 0x00010000 ; RX pin active level inversion
USART_CR2_RXINV_ofs EQU 16
USART_CR2_RXINV_len EQU 1
USART_CR2_SWAP EQU 0x00008000 ; Swap TX/RX pins
USART_CR2_SWAP_ofs EQU 15
USART_CR2_SWAP_len EQU 1
USART_CR2_LINEN EQU 0x00004000 ; LIN mode enable
USART_CR2_LINEN_ofs EQU 14
USART_CR2_LINEN_len EQU 1
USART_CR2_STOP EQU 0x00003000 ; STOP bits
USART_CR2_STOP_ofs EQU 12
USART_CR2_STOP_len EQU 2
USART_CR2_CLKEN EQU 0x00000800 ; Clock enable
USART_CR2_CLKEN_ofs EQU 11
USART_CR2_CLKEN_len EQU 1
USART_CR2_CPOL EQU 0x00000400 ; Clock polarity
USART_CR2_CPOL_ofs EQU 10
USART_CR2_CPOL_len EQU 1
USART_CR2_CPHA EQU 0x00000200 ; Clock phase
USART_CR2_CPHA_ofs EQU 9
USART_CR2_CPHA_len EQU 1
USART_CR2_LBCL EQU 0x00000100 ; Last bit clock pulse
USART_CR2_LBCL_ofs EQU 8
USART_CR2_LBCL_len EQU 1
USART_CR2_LBDIE EQU 0x00000040 ; LIN break detection interrupt enable
USART_CR2_LBDIE_ofs EQU 6
USART_CR2_LBDIE_len EQU 1
USART_CR2_LBDL EQU 0x00000020 ; LIN break detection length
USART_CR2_LBDL_ofs EQU 5
USART_CR2_LBDL_len EQU 1
USART_CR2_ADDM7 EQU 0x00000010 ; 7-bit Address Detection/4-bit Address Detection
USART_CR2_ADDM7_ofs EQU 4
USART_CR2_ADDM7_len EQU 1
; USART1_CR3 fields:
USART_CR3_WUFIE EQU 0x00400000 ; Wakeup from Stop mode interrupt enable
USART_CR3_WUFIE_ofs EQU 22
USART_CR3_WUFIE_len EQU 1
USART_CR3_WUS EQU 0x00300000 ; Wakeup from Stop mode interrupt flag selection
USART_CR3_WUS_ofs EQU 20
USART_CR3_WUS_len EQU 2
USART_CR3_SCARCNT EQU 0x000e0000 ; Smartcard auto-retry count
USART_CR3_SCARCNT_ofs EQU 17
USART_CR3_SCARCNT_len EQU 3
USART_CR3_DEP EQU 0x00008000 ; Driver enable polarity selection
USART_CR3_DEP_ofs EQU 15
USART_CR3_DEP_len EQU 1
USART_CR3_DEM EQU 0x00004000 ; Driver enable mode
USART_CR3_DEM_ofs EQU 14
USART_CR3_DEM_len EQU 1
USART_CR3_DDRE EQU 0x00002000 ; DMA Disable on Reception Error
USART_CR3_DDRE_ofs EQU 13
USART_CR3_DDRE_len EQU 1
USART_CR3_OVRDIS EQU 0x00001000 ; Overrun Disable
USART_CR3_OVRDIS_ofs EQU 12
USART_CR3_OVRDIS_len EQU 1
USART_CR3_ONEBIT EQU 0x00000800 ; One sample bit method enable
USART_CR3_ONEBIT_ofs EQU 11
USART_CR3_ONEBIT_len EQU 1
USART_CR3_CTSIE EQU 0x00000400 ; CTS interrupt enable
USART_CR3_CTSIE_ofs EQU 10
USART_CR3_CTSIE_len EQU 1
USART_CR3_CTSE EQU 0x00000200 ; CTS enable
USART_CR3_CTSE_ofs EQU 9
USART_CR3_CTSE_len EQU 1
USART_CR3_RTSE EQU 0x00000100 ; RTS enable
USART_CR3_RTSE_ofs EQU 8
USART_CR3_RTSE_len EQU 1
USART_CR3_DMAT EQU 0x00000080 ; DMA enable transmitter
USART_CR3_DMAT_ofs EQU 7
USART_CR3_DMAT_len EQU 1
USART_CR3_DMAR EQU 0x00000040 ; DMA enable receiver
USART_CR3_DMAR_ofs EQU 6
USART_CR3_DMAR_len EQU 1
USART_CR3_SCEN EQU 0x00000020 ; Smartcard mode enable
USART_CR3_SCEN_ofs EQU 5
USART_CR3_SCEN_len EQU 1
USART_CR3_NACK EQU 0x00000010 ; Smartcard NACK enable
USART_CR3_NACK_ofs EQU 4
USART_CR3_NACK_len EQU 1
USART_CR3_HDSEL EQU 0x00000008 ; Half-duplex selection
USART_CR3_HDSEL_ofs EQU 3
USART_CR3_HDSEL_len EQU 1
USART_CR3_IRLP EQU 0x00000004 ; IrDA low-power
USART_CR3_IRLP_ofs EQU 2
USART_CR3_IRLP_len EQU 1
USART_CR3_IREN EQU 0x00000002 ; IrDA mode enable
USART_CR3_IREN_ofs EQU 1
USART_CR3_IREN_len EQU 1
USART_CR3_EIE EQU 0x00000001 ; Error interrupt enable
USART_CR3_EIE_ofs EQU 0
USART_CR3_EIE_len EQU 1
; USART1_BRR fields:
USART_BRR_DIV_Mantissa EQU 0x0000fff0 ; mantissa of USARTDIV
USART_BRR_DIV_Mantissa_ofs EQU 4
USART_BRR_DIV_Mantissa_len EQU 12
USART_BRR_DIV_Fraction EQU 0x0000000f ; fraction of USARTDIV
USART_BRR_DIV_Fraction_ofs EQU 0
USART_BRR_DIV_Fraction_len EQU 4
; USART1_GTPR fields:
USART_GTPR_GT EQU 0x0000ff00 ; Guard time value
USART_GTPR_GT_ofs EQU 8
USART_GTPR_GT_len EQU 8
USART_GTPR_PSC EQU 0x000000ff ; Prescaler value
USART_GTPR_PSC_ofs EQU 0
USART_GTPR_PSC_len EQU 8
; USART1_RTOR fields:
USART_RTOR_BLEN EQU 0xff000000 ; Block Length
USART_RTOR_BLEN_ofs EQU 24
USART_RTOR_BLEN_len EQU 8
USART_RTOR_RTO EQU 0x00ffffff ; Receiver timeout value
USART_RTOR_RTO_ofs EQU 0
USART_RTOR_RTO_len EQU 24
; USART1_RQR fields:
USART_RQR_TXFRQ EQU 0x00000010 ; Transmit data flush request
USART_RQR_TXFRQ_ofs EQU 4
USART_RQR_TXFRQ_len EQU 1
USART_RQR_RXFRQ EQU 0x00000008 ; Receive data flush request
USART_RQR_RXFRQ_ofs EQU 3
USART_RQR_RXFRQ_len EQU 1
USART_RQR_MMRQ EQU 0x00000004 ; Mute mode request
USART_RQR_MMRQ_ofs EQU 2
USART_RQR_MMRQ_len EQU 1
USART_RQR_SBKRQ EQU 0x00000002 ; Send break request
USART_RQR_SBKRQ_ofs EQU 1
USART_RQR_SBKRQ_len EQU 1
USART_RQR_ABRRQ EQU 0x00000001 ; Auto baud rate request
USART_RQR_ABRRQ_ofs EQU 0
USART_RQR_ABRRQ_len EQU 1
; USART1_ISR fields:
USART_ISR_REACK EQU 0x00400000 ; Receive enable acknowledge flag
USART_ISR_REACK_ofs EQU 22
USART_ISR_REACK_len EQU 1
USART_ISR_TEACK EQU 0x00200000 ; Transmit enable acknowledge flag
USART_ISR_TEACK_ofs EQU 21
USART_ISR_TEACK_len EQU 1
USART_ISR_WUF EQU 0x00100000 ; Wakeup from Stop mode flag
USART_ISR_WUF_ofs EQU 20
USART_ISR_WUF_len EQU 1
USART_ISR_RWU EQU 0x00080000 ; Receiver wakeup from Mute mode
USART_ISR_RWU_ofs EQU 19
USART_ISR_RWU_len EQU 1
USART_ISR_SBKF EQU 0x00040000 ; Send break flag
USART_ISR_SBKF_ofs EQU 18
USART_ISR_SBKF_len EQU 1
USART_ISR_CMF EQU 0x00020000 ; character match flag
USART_ISR_CMF_ofs EQU 17
USART_ISR_CMF_len EQU 1
USART_ISR_BUSY EQU 0x00010000 ; Busy flag
USART_ISR_BUSY_ofs EQU 16
USART_ISR_BUSY_len EQU 1
USART_ISR_ABRF EQU 0x00008000 ; Auto baud rate flag
USART_ISR_ABRF_ofs EQU 15
USART_ISR_ABRF_len EQU 1
USART_ISR_ABRE EQU 0x00004000 ; Auto baud rate error
USART_ISR_ABRE_ofs EQU 14
USART_ISR_ABRE_len EQU 1
USART_ISR_EOBF EQU 0x00001000 ; End of block flag
USART_ISR_EOBF_ofs EQU 12
USART_ISR_EOBF_len EQU 1
USART_ISR_RTOF EQU 0x00000800 ; Receiver timeout
USART_ISR_RTOF_ofs EQU 11
USART_ISR_RTOF_len EQU 1
USART_ISR_CTS EQU 0x00000400 ; CTS flag
USART_ISR_CTS_ofs EQU 10
USART_ISR_CTS_len EQU 1
USART_ISR_CTSIF EQU 0x00000200 ; CTS interrupt flag
USART_ISR_CTSIF_ofs EQU 9
USART_ISR_CTSIF_len EQU 1
USART_ISR_LBDF EQU 0x00000100 ; LIN break detection flag
USART_ISR_LBDF_ofs EQU 8
USART_ISR_LBDF_len EQU 1
USART_ISR_TXE EQU 0x00000080 ; Transmit data register empty
USART_ISR_TXE_ofs EQU 7
USART_ISR_TXE_len EQU 1
USART_ISR_TC EQU 0x00000040 ; Transmission complete
USART_ISR_TC_ofs EQU 6
USART_ISR_TC_len EQU 1
USART_ISR_RXNE EQU 0x00000020 ; Read data register not empty
USART_ISR_RXNE_ofs EQU 5
USART_ISR_RXNE_len EQU 1
USART_ISR_IDLE EQU 0x00000010 ; Idle line detected
USART_ISR_IDLE_ofs EQU 4
USART_ISR_IDLE_len EQU 1
USART_ISR_ORE EQU 0x00000008 ; Overrun error
USART_ISR_ORE_ofs EQU 3
USART_ISR_ORE_len EQU 1
USART_ISR_NF EQU 0x00000004 ; Noise detected flag
USART_ISR_NF_ofs EQU 2
USART_ISR_NF_len EQU 1
USART_ISR_FE EQU 0x00000002 ; Framing error
USART_ISR_FE_ofs EQU 1
USART_ISR_FE_len EQU 1
USART_ISR_PE EQU 0x00000001 ; Parity error
USART_ISR_PE_ofs EQU 0
USART_ISR_PE_len EQU 1
; USART1_ICR fields:
USART_ICR_WUCF EQU 0x00100000 ; Wakeup from Stop mode clear flag
USART_ICR_WUCF_ofs EQU 20
USART_ICR_WUCF_len EQU 1
USART_ICR_CMCF EQU 0x00020000 ; Character match clear flag
USART_ICR_CMCF_ofs EQU 17
USART_ICR_CMCF_len EQU 1
USART_ICR_EOBCF EQU 0x00001000 ; End of timeout clear flag
USART_ICR_EOBCF_ofs EQU 12
USART_ICR_EOBCF_len EQU 1
USART_ICR_RTOCF EQU 0x00000800 ; Receiver timeout clear flag
USART_ICR_RTOCF_ofs EQU 11
USART_ICR_RTOCF_len EQU 1
USART_ICR_CTSCF EQU 0x00000200 ; CTS clear flag
USART_ICR_CTSCF_ofs EQU 9
USART_ICR_CTSCF_len EQU 1
USART_ICR_LBDCF EQU 0x00000100 ; LIN break detection clear flag
USART_ICR_LBDCF_ofs EQU 8
USART_ICR_LBDCF_len EQU 1
USART_ICR_TCCF EQU 0x00000040 ; Transmission complete clear flag
USART_ICR_TCCF_ofs EQU 6
USART_ICR_TCCF_len EQU 1
USART_ICR_IDLECF EQU 0x00000010 ; Idle line detected clear flag
USART_ICR_IDLECF_ofs EQU 4
USART_ICR_IDLECF_len EQU 1
USART_ICR_ORECF EQU 0x00000008 ; Overrun error clear flag
USART_ICR_ORECF_ofs EQU 3
USART_ICR_ORECF_len EQU 1
USART_ICR_NCF EQU 0x00000004 ; Noise detected clear flag
USART_ICR_NCF_ofs EQU 2
USART_ICR_NCF_len EQU 1
USART_ICR_FECF EQU 0x00000002 ; Framing error clear flag
USART_ICR_FECF_ofs EQU 1
USART_ICR_FECF_len EQU 1
USART_ICR_PECF EQU 0x00000001 ; Parity error clear flag
USART_ICR_PECF_ofs EQU 0
USART_ICR_PECF_len EQU 1
; USART1_RDR fields:
USART_RDR_RDR EQU 0x000001ff ; Receive data value
USART_RDR_RDR_ofs EQU 0
USART_RDR_RDR_len EQU 9
; USART1_TDR fields:
USART_TDR_TDR EQU 0x000001ff ; Transmit data value
USART_TDR_TDR_ofs EQU 0
USART_TDR_TDR_len EQU 9
; ---- USART2 ------------------------------------------------
; Desc: None
; USART2 base address:
USART2_BASE EQU 0x40004400
; USART2 registers:
USART2_CR1 EQU (USART2_BASE + 0x0) ; Control register 1
USART2_CR2 EQU (USART2_BASE + 0x4) ; Control register 2
USART2_CR3 EQU (USART2_BASE + 0x8) ; Control register 3
USART2_BRR EQU (USART2_BASE + 0xc) ; Baud rate register
USART2_GTPR EQU (USART2_BASE + 0x10) ; Guard time and prescaler register
USART2_RTOR EQU (USART2_BASE + 0x14) ; Receiver timeout register
USART2_RQR EQU (USART2_BASE + 0x18) ; Request register
USART2_ISR EQU (USART2_BASE + 0x1c) ; Interrupt & status register
USART2_ICR EQU (USART2_BASE + 0x20) ; Interrupt flag clear register
USART2_RDR EQU (USART2_BASE + 0x24) ; Receive data register
USART2_TDR EQU (USART2_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- USART3 ------------------------------------------------
; Desc: None
; USART3 base address:
USART3_BASE EQU 0x40004800
; USART3 registers:
USART3_CR1 EQU (USART3_BASE + 0x0) ; Control register 1
USART3_CR2 EQU (USART3_BASE + 0x4) ; Control register 2
USART3_CR3 EQU (USART3_BASE + 0x8) ; Control register 3
USART3_BRR EQU (USART3_BASE + 0xc) ; Baud rate register
USART3_GTPR EQU (USART3_BASE + 0x10) ; Guard time and prescaler register
USART3_RTOR EQU (USART3_BASE + 0x14) ; Receiver timeout register
USART3_RQR EQU (USART3_BASE + 0x18) ; Request register
USART3_ISR EQU (USART3_BASE + 0x1c) ; Interrupt & status register
USART3_ICR EQU (USART3_BASE + 0x20) ; Interrupt flag clear register
USART3_RDR EQU (USART3_BASE + 0x24) ; Receive data register
USART3_TDR EQU (USART3_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- UART4 -------------------------------------------------
; Desc: None
; UART4 base address:
UART4_BASE EQU 0x40004c00
; UART4 registers:
; ---- UART5 -------------------------------------------------
; Desc: None
; UART5 base address:
UART5_BASE EQU 0x40005000
; UART5 registers:
; ---- SPI1 --------------------------------------------------
; Desc: Serial peripheral interface/Inter-IC sound
; SPI1 base address:
SPI1_BASE EQU 0x40013000
; SPI1 registers:
SPI1_CR1 EQU (SPI1_BASE + 0x0) ; control register 1
SPI1_CR2 EQU (SPI1_BASE + 0x4) ; control register 2
SPI1_SR EQU (SPI1_BASE + 0x8) ; status register
SPI1_DR EQU (SPI1_BASE + 0xc) ; data register
SPI1_CRCPR EQU (SPI1_BASE + 0x10) ; CRC polynomial register
SPI1_RXCRCR EQU (SPI1_BASE + 0x14) ; RX CRC register
SPI1_TXCRCR EQU (SPI1_BASE + 0x18) ; TX CRC register
SPI1_I2SCFGR EQU (SPI1_BASE + 0x1c) ; I2S configuration register
SPI1_I2SPR EQU (SPI1_BASE + 0x20) ; I2S prescaler register
; SPI1_CR1 fields:
SPI1_CR1_BIDIMODE EQU 0x00008000 ; Bidirectional data mode enable
SPI1_CR1_BIDIMODE_ofs EQU 15
SPI1_CR1_BIDIMODE_len EQU 1
SPI1_CR1_BIDIOE EQU 0x00004000 ; Output enable in bidirectional mode
SPI1_CR1_BIDIOE_ofs EQU 14
SPI1_CR1_BIDIOE_len EQU 1
SPI1_CR1_CRCEN EQU 0x00002000 ; Hardware CRC calculation enable
SPI1_CR1_CRCEN_ofs EQU 13
SPI1_CR1_CRCEN_len EQU 1
SPI1_CR1_CRCNEXT EQU 0x00001000 ; CRC transfer next
SPI1_CR1_CRCNEXT_ofs EQU 12
SPI1_CR1_CRCNEXT_len EQU 1
SPI1_CR1_DFF EQU 0x00000800 ; Data frame format
SPI1_CR1_DFF_ofs EQU 11
SPI1_CR1_DFF_len EQU 1
SPI1_CR1_RXONLY EQU 0x00000400 ; Receive only
SPI1_CR1_RXONLY_ofs EQU 10
SPI1_CR1_RXONLY_len EQU 1
SPI1_CR1_SSM EQU 0x00000200 ; Software slave management
SPI1_CR1_SSM_ofs EQU 9
SPI1_CR1_SSM_len EQU 1
SPI1_CR1_SSI EQU 0x00000100 ; Internal slave select
SPI1_CR1_SSI_ofs EQU 8
SPI1_CR1_SSI_len EQU 1
SPI1_CR1_LSBFIRST EQU 0x00000080 ; Frame format
SPI1_CR1_LSBFIRST_ofs EQU 7
SPI1_CR1_LSBFIRST_len EQU 1
SPI1_CR1_SPE EQU 0x00000040 ; SPI enable
SPI1_CR1_SPE_ofs EQU 6
SPI1_CR1_SPE_len EQU 1
SPI1_CR1_BR EQU 0x00000038 ; Baud rate control
SPI1_CR1_BR_ofs EQU 3
SPI1_CR1_BR_len EQU 3
SPI1_CR1_MSTR EQU 0x00000004 ; Master selection
SPI1_CR1_MSTR_ofs EQU 2
SPI1_CR1_MSTR_len EQU 1
SPI1_CR1_CPOL EQU 0x00000002 ; Clock polarity
SPI1_CR1_CPOL_ofs EQU 1
SPI1_CR1_CPOL_len EQU 1
SPI1_CR1_CPHA EQU 0x00000001 ; Clock phase
SPI1_CR1_CPHA_ofs EQU 0
SPI1_CR1_CPHA_len EQU 1
; SPI1_CR2 fields:
SPI1_CR2_RXDMAEN EQU 0x00000001 ; Rx buffer DMA enable
SPI1_CR2_RXDMAEN_ofs EQU 0
SPI1_CR2_RXDMAEN_len EQU 1
SPI1_CR2_TXDMAEN EQU 0x00000002 ; Tx buffer DMA enable
SPI1_CR2_TXDMAEN_ofs EQU 1
SPI1_CR2_TXDMAEN_len EQU 1
SPI1_CR2_SSOE EQU 0x00000004 ; SS output enable
SPI1_CR2_SSOE_ofs EQU 2
SPI1_CR2_SSOE_len EQU 1
SPI1_CR2_NSSP EQU 0x00000008 ; NSS pulse management
SPI1_CR2_NSSP_ofs EQU 3
SPI1_CR2_NSSP_len EQU 1
SPI1_CR2_FRF EQU 0x00000010 ; Frame format
SPI1_CR2_FRF_ofs EQU 4
SPI1_CR2_FRF_len EQU 1
SPI1_CR2_ERRIE EQU 0x00000020 ; Error interrupt enable
SPI1_CR2_ERRIE_ofs EQU 5
SPI1_CR2_ERRIE_len EQU 1
SPI1_CR2_RXNEIE EQU 0x00000040 ; RX buffer not empty interrupt enable
SPI1_CR2_RXNEIE_ofs EQU 6
SPI1_CR2_RXNEIE_len EQU 1
SPI1_CR2_TXEIE EQU 0x00000080 ; Tx buffer empty interrupt enable
SPI1_CR2_TXEIE_ofs EQU 7
SPI1_CR2_TXEIE_len EQU 1
SPI1_CR2_DS EQU 0x00000f00 ; Data size
SPI1_CR2_DS_ofs EQU 8
SPI1_CR2_DS_len EQU 4
SPI1_CR2_FRXTH EQU 0x00001000 ; FIFO reception threshold
SPI1_CR2_FRXTH_ofs EQU 12
SPI1_CR2_FRXTH_len EQU 1
SPI1_CR2_LDMA_RX EQU 0x00002000 ; Last DMA transfer for reception
SPI1_CR2_LDMA_RX_ofs EQU 13
SPI1_CR2_LDMA_RX_len EQU 1
SPI1_CR2_LDMA_TX EQU 0x00004000 ; Last DMA transfer for transmission
SPI1_CR2_LDMA_TX_ofs EQU 14
SPI1_CR2_LDMA_TX_len EQU 1
; SPI1_SR fields:
SPI1_SR_RXNE EQU 0x00000001 ; Receive buffer not empty
SPI1_SR_RXNE_ofs EQU 0
SPI1_SR_RXNE_len EQU 1
SPI1_SR_TXE EQU 0x00000002 ; Transmit buffer empty
SPI1_SR_TXE_ofs EQU 1
SPI1_SR_TXE_len EQU 1
SPI1_SR_CHSIDE EQU 0x00000004 ; Channel side
SPI1_SR_CHSIDE_ofs EQU 2
SPI1_SR_CHSIDE_len EQU 1
SPI1_SR_UDR EQU 0x00000008 ; Underrun flag
SPI1_SR_UDR_ofs EQU 3
SPI1_SR_UDR_len EQU 1
SPI1_SR_CRCERR EQU 0x00000010 ; CRC error flag
SPI1_SR_CRCERR_ofs EQU 4
SPI1_SR_CRCERR_len EQU 1
SPI1_SR_MODF EQU 0x00000020 ; Mode fault
SPI1_SR_MODF_ofs EQU 5
SPI1_SR_MODF_len EQU 1
SPI1_SR_OVR EQU 0x00000040 ; Overrun flag
SPI1_SR_OVR_ofs EQU 6
SPI1_SR_OVR_len EQU 1
SPI1_SR_BSY EQU 0x00000080 ; Busy flag
SPI1_SR_BSY_ofs EQU 7
SPI1_SR_BSY_len EQU 1
SPI1_SR_TIFRFE EQU 0x00000100 ; TI frame format error
SPI1_SR_TIFRFE_ofs EQU 8
SPI1_SR_TIFRFE_len EQU 1
SPI1_SR_FRLVL EQU 0x00000600 ; FIFO reception level
SPI1_SR_FRLVL_ofs EQU 9
SPI1_SR_FRLVL_len EQU 2
SPI1_SR_FTLVL EQU 0x00001800 ; FIFO transmission level
SPI1_SR_FTLVL_ofs EQU 11
SPI1_SR_FTLVL_len EQU 2
; SPI1_DR fields:
SPI1_DR_DR EQU 0x0000ffff ; Data register
SPI1_DR_DR_ofs EQU 0
SPI1_DR_DR_len EQU 16
; SPI1_CRCPR fields:
SPI1_CRCPR_CRCPOLY EQU 0x0000ffff ; CRC polynomial register
SPI1_CRCPR_CRCPOLY_ofs EQU 0
SPI1_CRCPR_CRCPOLY_len EQU 16
; SPI1_RXCRCR fields:
SPI1_RXCRCR_RxCRC EQU 0x0000ffff ; Rx CRC register
SPI1_RXCRCR_RxCRC_ofs EQU 0
SPI1_RXCRCR_RxCRC_len EQU 16
; SPI1_TXCRCR fields:
SPI1_TXCRCR_TxCRC EQU 0x0000ffff ; Tx CRC register
SPI1_TXCRCR_TxCRC_ofs EQU 0
SPI1_TXCRCR_TxCRC_len EQU 16
; SPI1_I2SCFGR fields:
SPI1_I2SCFGR_I2SMOD EQU 0x00000800 ; I2S mode selection
SPI1_I2SCFGR_I2SMOD_ofs EQU 11
SPI1_I2SCFGR_I2SMOD_len EQU 1
SPI1_I2SCFGR_I2SE EQU 0x00000400 ; I2S Enable
SPI1_I2SCFGR_I2SE_ofs EQU 10
SPI1_I2SCFGR_I2SE_len EQU 1
SPI1_I2SCFGR_I2SCFG EQU 0x00000300 ; I2S configuration mode
SPI1_I2SCFGR_I2SCFG_ofs EQU 8
SPI1_I2SCFGR_I2SCFG_len EQU 2
SPI1_I2SCFGR_PCMSYNC EQU 0x00000080 ; PCM frame synchronization
SPI1_I2SCFGR_PCMSYNC_ofs EQU 7
SPI1_I2SCFGR_PCMSYNC_len EQU 1
SPI1_I2SCFGR_I2SSTD EQU 0x00000030 ; I2S standard selection
SPI1_I2SCFGR_I2SSTD_ofs EQU 4
SPI1_I2SCFGR_I2SSTD_len EQU 2
SPI1_I2SCFGR_CKPOL EQU 0x00000008 ; Steady state clock polarity
SPI1_I2SCFGR_CKPOL_ofs EQU 3
SPI1_I2SCFGR_CKPOL_len EQU 1
SPI1_I2SCFGR_DATLEN EQU 0x00000006 ; Data length to be transferred
SPI1_I2SCFGR_DATLEN_ofs EQU 1
SPI1_I2SCFGR_DATLEN_len EQU 2
SPI1_I2SCFGR_CHLEN EQU 0x00000001 ; Channel length (number of bits per audio channel)
SPI1_I2SCFGR_CHLEN_ofs EQU 0
SPI1_I2SCFGR_CHLEN_len EQU 1
; SPI1_I2SPR fields:
SPI1_I2SPR_MCKOE EQU 0x00000200 ; Master clock output enable
SPI1_I2SPR_MCKOE_ofs EQU 9
SPI1_I2SPR_MCKOE_len EQU 1
SPI1_I2SPR_ODD EQU 0x00000100 ; Odd factor for the prescaler
SPI1_I2SPR_ODD_ofs EQU 8
SPI1_I2SPR_ODD_len EQU 1
SPI1_I2SPR_I2SDIV EQU 0x000000ff ; I2S Linear prescaler
SPI1_I2SPR_I2SDIV_ofs EQU 0
SPI1_I2SPR_I2SDIV_len EQU 8
; ---- SPI2 --------------------------------------------------
; Desc: None
; SPI2 base address:
SPI2_BASE EQU 0x40003800
; SPI2 registers:
; ---- SPI3 --------------------------------------------------
; Desc: None
; SPI3 base address:
SPI3_BASE EQU 0x40003c00
; SPI3 registers:
; ---- I2S2ext -----------------------------------------------
; Desc: None
; I2S2ext base address:
I2S2ext_BASE EQU 0x40003400
; I2S2ext registers:
; ---- I2S3ext -----------------------------------------------
; Desc: None
; I2S3ext base address:
I2S3ext_BASE EQU 0x40004000
; I2S3ext registers:
; ---- EXTI --------------------------------------------------
; Desc: External interrupt/event controller
; EXTI base address:
EXTI_BASE EQU 0x40010400
; EXTI registers:
EXTI_IMR1 EQU (EXTI_BASE + 0x0) ; Interrupt mask register
EXTI_EMR1 EQU (EXTI_BASE + 0x4) ; Event mask register
EXTI_RTSR1 EQU (EXTI_BASE + 0x8) ; Rising Trigger selection register
EXTI_FTSR1 EQU (EXTI_BASE + 0xc) ; Falling Trigger selection register
EXTI_SWIER1 EQU (EXTI_BASE + 0x10) ; Software interrupt event register
EXTI_PR1 EQU (EXTI_BASE + 0x14) ; Pending register
EXTI_IMR2 EQU (EXTI_BASE + 0x18) ; Interrupt mask register
EXTI_EMR2 EQU (EXTI_BASE + 0x1c) ; Event mask register
EXTI_RTSR2 EQU (EXTI_BASE + 0x20) ; Rising Trigger selection register
EXTI_FTSR2 EQU (EXTI_BASE + 0x24) ; Falling Trigger selection register
EXTI_SWIER2 EQU (EXTI_BASE + 0x28) ; Software interrupt event register
EXTI_PR2 EQU (EXTI_BASE + 0x2c) ; Pending register
; EXTI_IMR1 fields:
EXTI_IMR1_MR0 EQU 0x00000001 ; Interrupt Mask on line 0
EXTI_IMR1_MR0_ofs EQU 0
EXTI_IMR1_MR0_len EQU 1
EXTI_IMR1_MR1 EQU 0x00000002 ; Interrupt Mask on line 1
EXTI_IMR1_MR1_ofs EQU 1
EXTI_IMR1_MR1_len EQU 1
EXTI_IMR1_MR2 EQU 0x00000004 ; Interrupt Mask on line 2
EXTI_IMR1_MR2_ofs EQU 2
EXTI_IMR1_MR2_len EQU 1
EXTI_IMR1_MR3 EQU 0x00000008 ; Interrupt Mask on line 3
EXTI_IMR1_MR3_ofs EQU 3
EXTI_IMR1_MR3_len EQU 1
EXTI_IMR1_MR4 EQU 0x00000010 ; Interrupt Mask on line 4
EXTI_IMR1_MR4_ofs EQU 4
EXTI_IMR1_MR4_len EQU 1
EXTI_IMR1_MR5 EQU 0x00000020 ; Interrupt Mask on line 5
EXTI_IMR1_MR5_ofs EQU 5
EXTI_IMR1_MR5_len EQU 1
EXTI_IMR1_MR6 EQU 0x00000040 ; Interrupt Mask on line 6
EXTI_IMR1_MR6_ofs EQU 6
EXTI_IMR1_MR6_len EQU 1
EXTI_IMR1_MR7 EQU 0x00000080 ; Interrupt Mask on line 7
EXTI_IMR1_MR7_ofs EQU 7
EXTI_IMR1_MR7_len EQU 1
EXTI_IMR1_MR8 EQU 0x00000100 ; Interrupt Mask on line 8
EXTI_IMR1_MR8_ofs EQU 8
EXTI_IMR1_MR8_len EQU 1
EXTI_IMR1_MR9 EQU 0x00000200 ; Interrupt Mask on line 9
EXTI_IMR1_MR9_ofs EQU 9
EXTI_IMR1_MR9_len EQU 1
EXTI_IMR1_MR10 EQU 0x00000400 ; Interrupt Mask on line 10
EXTI_IMR1_MR10_ofs EQU 10
EXTI_IMR1_MR10_len EQU 1
EXTI_IMR1_MR11 EQU 0x00000800 ; Interrupt Mask on line 11
EXTI_IMR1_MR11_ofs EQU 11
EXTI_IMR1_MR11_len EQU 1
EXTI_IMR1_MR12 EQU 0x00001000 ; Interrupt Mask on line 12
EXTI_IMR1_MR12_ofs EQU 12
EXTI_IMR1_MR12_len EQU 1
EXTI_IMR1_MR13 EQU 0x00002000 ; Interrupt Mask on line 13
EXTI_IMR1_MR13_ofs EQU 13
EXTI_IMR1_MR13_len EQU 1
EXTI_IMR1_MR14 EQU 0x00004000 ; Interrupt Mask on line 14
EXTI_IMR1_MR14_ofs EQU 14
EXTI_IMR1_MR14_len EQU 1
EXTI_IMR1_MR15 EQU 0x00008000 ; Interrupt Mask on line 15
EXTI_IMR1_MR15_ofs EQU 15
EXTI_IMR1_MR15_len EQU 1
EXTI_IMR1_MR16 EQU 0x00010000 ; Interrupt Mask on line 16
EXTI_IMR1_MR16_ofs EQU 16
EXTI_IMR1_MR16_len EQU 1
EXTI_IMR1_MR17 EQU 0x00020000 ; Interrupt Mask on line 17
EXTI_IMR1_MR17_ofs EQU 17
EXTI_IMR1_MR17_len EQU 1
EXTI_IMR1_MR18 EQU 0x00040000 ; Interrupt Mask on line 18
EXTI_IMR1_MR18_ofs EQU 18
EXTI_IMR1_MR18_len EQU 1
EXTI_IMR1_MR19 EQU 0x00080000 ; Interrupt Mask on line 19
EXTI_IMR1_MR19_ofs EQU 19
EXTI_IMR1_MR19_len EQU 1
EXTI_IMR1_MR20 EQU 0x00100000 ; Interrupt Mask on line 20
EXTI_IMR1_MR20_ofs EQU 20
EXTI_IMR1_MR20_len EQU 1
EXTI_IMR1_MR21 EQU 0x00200000 ; Interrupt Mask on line 21
EXTI_IMR1_MR21_ofs EQU 21
EXTI_IMR1_MR21_len EQU 1
EXTI_IMR1_MR22 EQU 0x00400000 ; Interrupt Mask on line 22
EXTI_IMR1_MR22_ofs EQU 22
EXTI_IMR1_MR22_len EQU 1
EXTI_IMR1_MR23 EQU 0x00800000 ; Interrupt Mask on line 23
EXTI_IMR1_MR23_ofs EQU 23
EXTI_IMR1_MR23_len EQU 1
EXTI_IMR1_MR24 EQU 0x01000000 ; Interrupt Mask on line 24
EXTI_IMR1_MR24_ofs EQU 24
EXTI_IMR1_MR24_len EQU 1
EXTI_IMR1_MR25 EQU 0x02000000 ; Interrupt Mask on line 25
EXTI_IMR1_MR25_ofs EQU 25
EXTI_IMR1_MR25_len EQU 1
EXTI_IMR1_MR26 EQU 0x04000000 ; Interrupt Mask on line 26
EXTI_IMR1_MR26_ofs EQU 26
EXTI_IMR1_MR26_len EQU 1
EXTI_IMR1_MR27 EQU 0x08000000 ; Interrupt Mask on line 27
EXTI_IMR1_MR27_ofs EQU 27
EXTI_IMR1_MR27_len EQU 1
EXTI_IMR1_MR28 EQU 0x10000000 ; Interrupt Mask on line 28
EXTI_IMR1_MR28_ofs EQU 28
EXTI_IMR1_MR28_len EQU 1
EXTI_IMR1_MR29 EQU 0x20000000 ; Interrupt Mask on line 29
EXTI_IMR1_MR29_ofs EQU 29
EXTI_IMR1_MR29_len EQU 1
EXTI_IMR1_MR30 EQU 0x40000000 ; Interrupt Mask on line 30
EXTI_IMR1_MR30_ofs EQU 30
EXTI_IMR1_MR30_len EQU 1
EXTI_IMR1_MR31 EQU 0x80000000 ; Interrupt Mask on line 31
EXTI_IMR1_MR31_ofs EQU 31
EXTI_IMR1_MR31_len EQU 1
; EXTI_EMR1 fields:
EXTI_EMR1_MR0 EQU 0x00000001 ; Event Mask on line 0
EXTI_EMR1_MR0_ofs EQU 0
EXTI_EMR1_MR0_len EQU 1
EXTI_EMR1_MR1 EQU 0x00000002 ; Event Mask on line 1
EXTI_EMR1_MR1_ofs EQU 1
EXTI_EMR1_MR1_len EQU 1
EXTI_EMR1_MR2 EQU 0x00000004 ; Event Mask on line 2
EXTI_EMR1_MR2_ofs EQU 2
EXTI_EMR1_MR2_len EQU 1
EXTI_EMR1_MR3 EQU 0x00000008 ; Event Mask on line 3
EXTI_EMR1_MR3_ofs EQU 3
EXTI_EMR1_MR3_len EQU 1
EXTI_EMR1_MR4 EQU 0x00000010 ; Event Mask on line 4
EXTI_EMR1_MR4_ofs EQU 4
EXTI_EMR1_MR4_len EQU 1
EXTI_EMR1_MR5 EQU 0x00000020 ; Event Mask on line 5
EXTI_EMR1_MR5_ofs EQU 5
EXTI_EMR1_MR5_len EQU 1
EXTI_EMR1_MR6 EQU 0x00000040 ; Event Mask on line 6
EXTI_EMR1_MR6_ofs EQU 6
EXTI_EMR1_MR6_len EQU 1
EXTI_EMR1_MR7 EQU 0x00000080 ; Event Mask on line 7
EXTI_EMR1_MR7_ofs EQU 7
EXTI_EMR1_MR7_len EQU 1
EXTI_EMR1_MR8 EQU 0x00000100 ; Event Mask on line 8
EXTI_EMR1_MR8_ofs EQU 8
EXTI_EMR1_MR8_len EQU 1
EXTI_EMR1_MR9 EQU 0x00000200 ; Event Mask on line 9
EXTI_EMR1_MR9_ofs EQU 9
EXTI_EMR1_MR9_len EQU 1
EXTI_EMR1_MR10 EQU 0x00000400 ; Event Mask on line 10
EXTI_EMR1_MR10_ofs EQU 10
EXTI_EMR1_MR10_len EQU 1
EXTI_EMR1_MR11 EQU 0x00000800 ; Event Mask on line 11
EXTI_EMR1_MR11_ofs EQU 11
EXTI_EMR1_MR11_len EQU 1
EXTI_EMR1_MR12 EQU 0x00001000 ; Event Mask on line 12
EXTI_EMR1_MR12_ofs EQU 12
EXTI_EMR1_MR12_len EQU 1
EXTI_EMR1_MR13 EQU 0x00002000 ; Event Mask on line 13
EXTI_EMR1_MR13_ofs EQU 13
EXTI_EMR1_MR13_len EQU 1
EXTI_EMR1_MR14 EQU 0x00004000 ; Event Mask on line 14
EXTI_EMR1_MR14_ofs EQU 14
EXTI_EMR1_MR14_len EQU 1
EXTI_EMR1_MR15 EQU 0x00008000 ; Event Mask on line 15
EXTI_EMR1_MR15_ofs EQU 15
EXTI_EMR1_MR15_len EQU 1
EXTI_EMR1_MR16 EQU 0x00010000 ; Event Mask on line 16
EXTI_EMR1_MR16_ofs EQU 16
EXTI_EMR1_MR16_len EQU 1
EXTI_EMR1_MR17 EQU 0x00020000 ; Event Mask on line 17
EXTI_EMR1_MR17_ofs EQU 17
EXTI_EMR1_MR17_len EQU 1
EXTI_EMR1_MR18 EQU 0x00040000 ; Event Mask on line 18
EXTI_EMR1_MR18_ofs EQU 18
EXTI_EMR1_MR18_len EQU 1
EXTI_EMR1_MR19 EQU 0x00080000 ; Event Mask on line 19
EXTI_EMR1_MR19_ofs EQU 19
EXTI_EMR1_MR19_len EQU 1
EXTI_EMR1_MR20 EQU 0x00100000 ; Event Mask on line 20
EXTI_EMR1_MR20_ofs EQU 20
EXTI_EMR1_MR20_len EQU 1
EXTI_EMR1_MR21 EQU 0x00200000 ; Event Mask on line 21
EXTI_EMR1_MR21_ofs EQU 21
EXTI_EMR1_MR21_len EQU 1
EXTI_EMR1_MR22 EQU 0x00400000 ; Event Mask on line 22
EXTI_EMR1_MR22_ofs EQU 22
EXTI_EMR1_MR22_len EQU 1
EXTI_EMR1_MR23 EQU 0x00800000 ; Event Mask on line 23
EXTI_EMR1_MR23_ofs EQU 23
EXTI_EMR1_MR23_len EQU 1
EXTI_EMR1_MR24 EQU 0x01000000 ; Event Mask on line 24
EXTI_EMR1_MR24_ofs EQU 24
EXTI_EMR1_MR24_len EQU 1
EXTI_EMR1_MR25 EQU 0x02000000 ; Event Mask on line 25
EXTI_EMR1_MR25_ofs EQU 25
EXTI_EMR1_MR25_len EQU 1
EXTI_EMR1_MR26 EQU 0x04000000 ; Event Mask on line 26
EXTI_EMR1_MR26_ofs EQU 26
EXTI_EMR1_MR26_len EQU 1
EXTI_EMR1_MR27 EQU 0x08000000 ; Event Mask on line 27
EXTI_EMR1_MR27_ofs EQU 27
EXTI_EMR1_MR27_len EQU 1
EXTI_EMR1_MR28 EQU 0x10000000 ; Event Mask on line 28
EXTI_EMR1_MR28_ofs EQU 28
EXTI_EMR1_MR28_len EQU 1
EXTI_EMR1_MR29 EQU 0x20000000 ; Event Mask on line 29
EXTI_EMR1_MR29_ofs EQU 29
EXTI_EMR1_MR29_len EQU 1
EXTI_EMR1_MR30 EQU 0x40000000 ; Event Mask on line 30
EXTI_EMR1_MR30_ofs EQU 30
EXTI_EMR1_MR30_len EQU 1
EXTI_EMR1_MR31 EQU 0x80000000 ; Event Mask on line 31
EXTI_EMR1_MR31_ofs EQU 31
EXTI_EMR1_MR31_len EQU 1
; EXTI_RTSR1 fields:
EXTI_RTSR1_TR0 EQU 0x00000001 ; Rising trigger event configuration of line 0
EXTI_RTSR1_TR0_ofs EQU 0
EXTI_RTSR1_TR0_len EQU 1
EXTI_RTSR1_TR1 EQU 0x00000002 ; Rising trigger event configuration of line 1
EXTI_RTSR1_TR1_ofs EQU 1
EXTI_RTSR1_TR1_len EQU 1
EXTI_RTSR1_TR2 EQU 0x00000004 ; Rising trigger event configuration of line 2
EXTI_RTSR1_TR2_ofs EQU 2
EXTI_RTSR1_TR2_len EQU 1
EXTI_RTSR1_TR3 EQU 0x00000008 ; Rising trigger event configuration of line 3
EXTI_RTSR1_TR3_ofs EQU 3
EXTI_RTSR1_TR3_len EQU 1
EXTI_RTSR1_TR4 EQU 0x00000010 ; Rising trigger event configuration of line 4
EXTI_RTSR1_TR4_ofs EQU 4
EXTI_RTSR1_TR4_len EQU 1
EXTI_RTSR1_TR5 EQU 0x00000020 ; Rising trigger event configuration of line 5
EXTI_RTSR1_TR5_ofs EQU 5
EXTI_RTSR1_TR5_len EQU 1
EXTI_RTSR1_TR6 EQU 0x00000040 ; Rising trigger event configuration of line 6
EXTI_RTSR1_TR6_ofs EQU 6
EXTI_RTSR1_TR6_len EQU 1
EXTI_RTSR1_TR7 EQU 0x00000080 ; Rising trigger event configuration of line 7
EXTI_RTSR1_TR7_ofs EQU 7
EXTI_RTSR1_TR7_len EQU 1
EXTI_RTSR1_TR8 EQU 0x00000100 ; Rising trigger event configuration of line 8
EXTI_RTSR1_TR8_ofs EQU 8
EXTI_RTSR1_TR8_len EQU 1
EXTI_RTSR1_TR9 EQU 0x00000200 ; Rising trigger event configuration of line 9
EXTI_RTSR1_TR9_ofs EQU 9
EXTI_RTSR1_TR9_len EQU 1
EXTI_RTSR1_TR10 EQU 0x00000400 ; Rising trigger event configuration of line 10
EXTI_RTSR1_TR10_ofs EQU 10
EXTI_RTSR1_TR10_len EQU 1
EXTI_RTSR1_TR11 EQU 0x00000800 ; Rising trigger event configuration of line 11
EXTI_RTSR1_TR11_ofs EQU 11
EXTI_RTSR1_TR11_len EQU 1
EXTI_RTSR1_TR12 EQU 0x00001000 ; Rising trigger event configuration of line 12
EXTI_RTSR1_TR12_ofs EQU 12
EXTI_RTSR1_TR12_len EQU 1
EXTI_RTSR1_TR13 EQU 0x00002000 ; Rising trigger event configuration of line 13
EXTI_RTSR1_TR13_ofs EQU 13
EXTI_RTSR1_TR13_len EQU 1
EXTI_RTSR1_TR14 EQU 0x00004000 ; Rising trigger event configuration of line 14
EXTI_RTSR1_TR14_ofs EQU 14
EXTI_RTSR1_TR14_len EQU 1
EXTI_RTSR1_TR15 EQU 0x00008000 ; Rising trigger event configuration of line 15
EXTI_RTSR1_TR15_ofs EQU 15
EXTI_RTSR1_TR15_len EQU 1
EXTI_RTSR1_TR16 EQU 0x00010000 ; Rising trigger event configuration of line 16
EXTI_RTSR1_TR16_ofs EQU 16
EXTI_RTSR1_TR16_len EQU 1
EXTI_RTSR1_TR17 EQU 0x00020000 ; Rising trigger event configuration of line 17
EXTI_RTSR1_TR17_ofs EQU 17
EXTI_RTSR1_TR17_len EQU 1
EXTI_RTSR1_TR18 EQU 0x00040000 ; Rising trigger event configuration of line 18
EXTI_RTSR1_TR18_ofs EQU 18
EXTI_RTSR1_TR18_len EQU 1
EXTI_RTSR1_TR19 EQU 0x00080000 ; Rising trigger event configuration of line 19
EXTI_RTSR1_TR19_ofs EQU 19
EXTI_RTSR1_TR19_len EQU 1
EXTI_RTSR1_TR20 EQU 0x00100000 ; Rising trigger event configuration of line 20
EXTI_RTSR1_TR20_ofs EQU 20
EXTI_RTSR1_TR20_len EQU 1
EXTI_RTSR1_TR21 EQU 0x00200000 ; Rising trigger event configuration of line 21
EXTI_RTSR1_TR21_ofs EQU 21
EXTI_RTSR1_TR21_len EQU 1
EXTI_RTSR1_TR22 EQU 0x00400000 ; Rising trigger event configuration of line 22
EXTI_RTSR1_TR22_ofs EQU 22
EXTI_RTSR1_TR22_len EQU 1
EXTI_RTSR1_TR29 EQU 0x20000000 ; Rising trigger event configuration of line 29
EXTI_RTSR1_TR29_ofs EQU 29
EXTI_RTSR1_TR29_len EQU 1
EXTI_RTSR1_TR30 EQU 0x40000000 ; Rising trigger event configuration of line 30
EXTI_RTSR1_TR30_ofs EQU 30
EXTI_RTSR1_TR30_len EQU 1
EXTI_RTSR1_TR31 EQU 0x80000000 ; Rising trigger event configuration of line 31
EXTI_RTSR1_TR31_ofs EQU 31
EXTI_RTSR1_TR31_len EQU 1
; EXTI_FTSR1 fields:
EXTI_FTSR1_TR0 EQU 0x00000001 ; Falling trigger event configuration of line 0
EXTI_FTSR1_TR0_ofs EQU 0
EXTI_FTSR1_TR0_len EQU 1
EXTI_FTSR1_TR1 EQU 0x00000002 ; Falling trigger event configuration of line 1
EXTI_FTSR1_TR1_ofs EQU 1
EXTI_FTSR1_TR1_len EQU 1
EXTI_FTSR1_TR2 EQU 0x00000004 ; Falling trigger event configuration of line 2
EXTI_FTSR1_TR2_ofs EQU 2
EXTI_FTSR1_TR2_len EQU 1
EXTI_FTSR1_TR3 EQU 0x00000008 ; Falling trigger event configuration of line 3
EXTI_FTSR1_TR3_ofs EQU 3
EXTI_FTSR1_TR3_len EQU 1
EXTI_FTSR1_TR4 EQU 0x00000010 ; Falling trigger event configuration of line 4
EXTI_FTSR1_TR4_ofs EQU 4
EXTI_FTSR1_TR4_len EQU 1
EXTI_FTSR1_TR5 EQU 0x00000020 ; Falling trigger event configuration of line 5
EXTI_FTSR1_TR5_ofs EQU 5
EXTI_FTSR1_TR5_len EQU 1
EXTI_FTSR1_TR6 EQU 0x00000040 ; Falling trigger event configuration of line 6
EXTI_FTSR1_TR6_ofs EQU 6
EXTI_FTSR1_TR6_len EQU 1
EXTI_FTSR1_TR7 EQU 0x00000080 ; Falling trigger event configuration of line 7
EXTI_FTSR1_TR7_ofs EQU 7
EXTI_FTSR1_TR7_len EQU 1
EXTI_FTSR1_TR8 EQU 0x00000100 ; Falling trigger event configuration of line 8
EXTI_FTSR1_TR8_ofs EQU 8
EXTI_FTSR1_TR8_len EQU 1
EXTI_FTSR1_TR9 EQU 0x00000200 ; Falling trigger event configuration of line 9
EXTI_FTSR1_TR9_ofs EQU 9
EXTI_FTSR1_TR9_len EQU 1
EXTI_FTSR1_TR10 EQU 0x00000400 ; Falling trigger event configuration of line 10
EXTI_FTSR1_TR10_ofs EQU 10
EXTI_FTSR1_TR10_len EQU 1
EXTI_FTSR1_TR11 EQU 0x00000800 ; Falling trigger event configuration of line 11
EXTI_FTSR1_TR11_ofs EQU 11
EXTI_FTSR1_TR11_len EQU 1
EXTI_FTSR1_TR12 EQU 0x00001000 ; Falling trigger event configuration of line 12
EXTI_FTSR1_TR12_ofs EQU 12
EXTI_FTSR1_TR12_len EQU 1
EXTI_FTSR1_TR13 EQU 0x00002000 ; Falling trigger event configuration of line 13
EXTI_FTSR1_TR13_ofs EQU 13
EXTI_FTSR1_TR13_len EQU 1
EXTI_FTSR1_TR14 EQU 0x00004000 ; Falling trigger event configuration of line 14
EXTI_FTSR1_TR14_ofs EQU 14
EXTI_FTSR1_TR14_len EQU 1
EXTI_FTSR1_TR15 EQU 0x00008000 ; Falling trigger event configuration of line 15
EXTI_FTSR1_TR15_ofs EQU 15
EXTI_FTSR1_TR15_len EQU 1
EXTI_FTSR1_TR16 EQU 0x00010000 ; Falling trigger event configuration of line 16
EXTI_FTSR1_TR16_ofs EQU 16
EXTI_FTSR1_TR16_len EQU 1
EXTI_FTSR1_TR17 EQU 0x00020000 ; Falling trigger event configuration of line 17
EXTI_FTSR1_TR17_ofs EQU 17
EXTI_FTSR1_TR17_len EQU 1
EXTI_FTSR1_TR18 EQU 0x00040000 ; Falling trigger event configuration of line 18
EXTI_FTSR1_TR18_ofs EQU 18
EXTI_FTSR1_TR18_len EQU 1
EXTI_FTSR1_TR19 EQU 0x00080000 ; Falling trigger event configuration of line 19
EXTI_FTSR1_TR19_ofs EQU 19
EXTI_FTSR1_TR19_len EQU 1
EXTI_FTSR1_TR20 EQU 0x00100000 ; Falling trigger event configuration of line 20
EXTI_FTSR1_TR20_ofs EQU 20
EXTI_FTSR1_TR20_len EQU 1
EXTI_FTSR1_TR21 EQU 0x00200000 ; Falling trigger event configuration of line 21
EXTI_FTSR1_TR21_ofs EQU 21
EXTI_FTSR1_TR21_len EQU 1
EXTI_FTSR1_TR22 EQU 0x00400000 ; Falling trigger event configuration of line 22
EXTI_FTSR1_TR22_ofs EQU 22
EXTI_FTSR1_TR22_len EQU 1
EXTI_FTSR1_TR29 EQU 0x20000000 ; Falling trigger event configuration of line 29
EXTI_FTSR1_TR29_ofs EQU 29
EXTI_FTSR1_TR29_len EQU 1
EXTI_FTSR1_TR30 EQU 0x40000000 ; Falling trigger event configuration of line 30.
EXTI_FTSR1_TR30_ofs EQU 30
EXTI_FTSR1_TR30_len EQU 1
EXTI_FTSR1_TR31 EQU 0x80000000 ; Falling trigger event configuration of line 31
EXTI_FTSR1_TR31_ofs EQU 31
EXTI_FTSR1_TR31_len EQU 1
; EXTI_SWIER1 fields:
EXTI_SWIER1_SWIER0 EQU 0x00000001 ; Software Interrupt on line 0
EXTI_SWIER1_SWIER0_ofs EQU 0
EXTI_SWIER1_SWIER0_len EQU 1
EXTI_SWIER1_SWIER1 EQU 0x00000002 ; Software Interrupt on line 1
EXTI_SWIER1_SWIER1_ofs EQU 1
EXTI_SWIER1_SWIER1_len EQU 1
EXTI_SWIER1_SWIER2 EQU 0x00000004 ; Software Interrupt on line 2
EXTI_SWIER1_SWIER2_ofs EQU 2
EXTI_SWIER1_SWIER2_len EQU 1
EXTI_SWIER1_SWIER3 EQU 0x00000008 ; Software Interrupt on line 3
EXTI_SWIER1_SWIER3_ofs EQU 3
EXTI_SWIER1_SWIER3_len EQU 1
EXTI_SWIER1_SWIER4 EQU 0x00000010 ; Software Interrupt on line 4
EXTI_SWIER1_SWIER4_ofs EQU 4
EXTI_SWIER1_SWIER4_len EQU 1
EXTI_SWIER1_SWIER5 EQU 0x00000020 ; Software Interrupt on line 5
EXTI_SWIER1_SWIER5_ofs EQU 5
EXTI_SWIER1_SWIER5_len EQU 1
EXTI_SWIER1_SWIER6 EQU 0x00000040 ; Software Interrupt on line 6
EXTI_SWIER1_SWIER6_ofs EQU 6
EXTI_SWIER1_SWIER6_len EQU 1
EXTI_SWIER1_SWIER7 EQU 0x00000080 ; Software Interrupt on line 7
EXTI_SWIER1_SWIER7_ofs EQU 7
EXTI_SWIER1_SWIER7_len EQU 1
EXTI_SWIER1_SWIER8 EQU 0x00000100 ; Software Interrupt on line 8
EXTI_SWIER1_SWIER8_ofs EQU 8
EXTI_SWIER1_SWIER8_len EQU 1
EXTI_SWIER1_SWIER9 EQU 0x00000200 ; Software Interrupt on line 9
EXTI_SWIER1_SWIER9_ofs EQU 9
EXTI_SWIER1_SWIER9_len EQU 1
EXTI_SWIER1_SWIER10 EQU 0x00000400 ; Software Interrupt on line 10
EXTI_SWIER1_SWIER10_ofs EQU 10
EXTI_SWIER1_SWIER10_len EQU 1
EXTI_SWIER1_SWIER11 EQU 0x00000800 ; Software Interrupt on line 11
EXTI_SWIER1_SWIER11_ofs EQU 11
EXTI_SWIER1_SWIER11_len EQU 1
EXTI_SWIER1_SWIER12 EQU 0x00001000 ; Software Interrupt on line 12
EXTI_SWIER1_SWIER12_ofs EQU 12
EXTI_SWIER1_SWIER12_len EQU 1
EXTI_SWIER1_SWIER13 EQU 0x00002000 ; Software Interrupt on line 13
EXTI_SWIER1_SWIER13_ofs EQU 13
EXTI_SWIER1_SWIER13_len EQU 1
EXTI_SWIER1_SWIER14 EQU 0x00004000 ; Software Interrupt on line 14
EXTI_SWIER1_SWIER14_ofs EQU 14
EXTI_SWIER1_SWIER14_len EQU 1
EXTI_SWIER1_SWIER15 EQU 0x00008000 ; Software Interrupt on line 15
EXTI_SWIER1_SWIER15_ofs EQU 15
EXTI_SWIER1_SWIER15_len EQU 1
EXTI_SWIER1_SWIER16 EQU 0x00010000 ; Software Interrupt on line 16
EXTI_SWIER1_SWIER16_ofs EQU 16
EXTI_SWIER1_SWIER16_len EQU 1
EXTI_SWIER1_SWIER17 EQU 0x00020000 ; Software Interrupt on line 17
EXTI_SWIER1_SWIER17_ofs EQU 17
EXTI_SWIER1_SWIER17_len EQU 1
EXTI_SWIER1_SWIER18 EQU 0x00040000 ; Software Interrupt on line 18
EXTI_SWIER1_SWIER18_ofs EQU 18
EXTI_SWIER1_SWIER18_len EQU 1
EXTI_SWIER1_SWIER19 EQU 0x00080000 ; Software Interrupt on line 19
EXTI_SWIER1_SWIER19_ofs EQU 19
EXTI_SWIER1_SWIER19_len EQU 1
EXTI_SWIER1_SWIER20 EQU 0x00100000 ; Software Interrupt on line 20
EXTI_SWIER1_SWIER20_ofs EQU 20
EXTI_SWIER1_SWIER20_len EQU 1
EXTI_SWIER1_SWIER21 EQU 0x00200000 ; Software Interrupt on line 21
EXTI_SWIER1_SWIER21_ofs EQU 21
EXTI_SWIER1_SWIER21_len EQU 1
EXTI_SWIER1_SWIER22 EQU 0x00400000 ; Software Interrupt on line 22
EXTI_SWIER1_SWIER22_ofs EQU 22
EXTI_SWIER1_SWIER22_len EQU 1
EXTI_SWIER1_SWIER29 EQU 0x20000000 ; Software Interrupt on line 29
EXTI_SWIER1_SWIER29_ofs EQU 29
EXTI_SWIER1_SWIER29_len EQU 1
EXTI_SWIER1_SWIER30 EQU 0x40000000 ; Software Interrupt on line 309
EXTI_SWIER1_SWIER30_ofs EQU 30
EXTI_SWIER1_SWIER30_len EQU 1
EXTI_SWIER1_SWIER31 EQU 0x80000000 ; Software Interrupt on line 319
EXTI_SWIER1_SWIER31_ofs EQU 31
EXTI_SWIER1_SWIER31_len EQU 1
; EXTI_PR1 fields:
EXTI_PR1_PR0 EQU 0x00000001 ; Pending bit 0
EXTI_PR1_PR0_ofs EQU 0
EXTI_PR1_PR0_len EQU 1
EXTI_PR1_PR1 EQU 0x00000002 ; Pending bit 1
EXTI_PR1_PR1_ofs EQU 1
EXTI_PR1_PR1_len EQU 1
EXTI_PR1_PR2 EQU 0x00000004 ; Pending bit 2
EXTI_PR1_PR2_ofs EQU 2
EXTI_PR1_PR2_len EQU 1
EXTI_PR1_PR3 EQU 0x00000008 ; Pending bit 3
EXTI_PR1_PR3_ofs EQU 3
EXTI_PR1_PR3_len EQU 1
EXTI_PR1_PR4 EQU 0x00000010 ; Pending bit 4
EXTI_PR1_PR4_ofs EQU 4
EXTI_PR1_PR4_len EQU 1
EXTI_PR1_PR5 EQU 0x00000020 ; Pending bit 5
EXTI_PR1_PR5_ofs EQU 5
EXTI_PR1_PR5_len EQU 1
EXTI_PR1_PR6 EQU 0x00000040 ; Pending bit 6
EXTI_PR1_PR6_ofs EQU 6
EXTI_PR1_PR6_len EQU 1
EXTI_PR1_PR7 EQU 0x00000080 ; Pending bit 7
EXTI_PR1_PR7_ofs EQU 7
EXTI_PR1_PR7_len EQU 1
EXTI_PR1_PR8 EQU 0x00000100 ; Pending bit 8
EXTI_PR1_PR8_ofs EQU 8
EXTI_PR1_PR8_len EQU 1
EXTI_PR1_PR9 EQU 0x00000200 ; Pending bit 9
EXTI_PR1_PR9_ofs EQU 9
EXTI_PR1_PR9_len EQU 1
EXTI_PR1_PR10 EQU 0x00000400 ; Pending bit 10
EXTI_PR1_PR10_ofs EQU 10
EXTI_PR1_PR10_len EQU 1
EXTI_PR1_PR11 EQU 0x00000800 ; Pending bit 11
EXTI_PR1_PR11_ofs EQU 11
EXTI_PR1_PR11_len EQU 1
EXTI_PR1_PR12 EQU 0x00001000 ; Pending bit 12
EXTI_PR1_PR12_ofs EQU 12
EXTI_PR1_PR12_len EQU 1
EXTI_PR1_PR13 EQU 0x00002000 ; Pending bit 13
EXTI_PR1_PR13_ofs EQU 13
EXTI_PR1_PR13_len EQU 1
EXTI_PR1_PR14 EQU 0x00004000 ; Pending bit 14
EXTI_PR1_PR14_ofs EQU 14
EXTI_PR1_PR14_len EQU 1
EXTI_PR1_PR15 EQU 0x00008000 ; Pending bit 15
EXTI_PR1_PR15_ofs EQU 15
EXTI_PR1_PR15_len EQU 1
EXTI_PR1_PR16 EQU 0x00010000 ; Pending bit 16
EXTI_PR1_PR16_ofs EQU 16
EXTI_PR1_PR16_len EQU 1
EXTI_PR1_PR17 EQU 0x00020000 ; Pending bit 17
EXTI_PR1_PR17_ofs EQU 17
EXTI_PR1_PR17_len EQU 1
EXTI_PR1_PR18 EQU 0x00040000 ; Pending bit 18
EXTI_PR1_PR18_ofs EQU 18
EXTI_PR1_PR18_len EQU 1
EXTI_PR1_PR19 EQU 0x00080000 ; Pending bit 19
EXTI_PR1_PR19_ofs EQU 19
EXTI_PR1_PR19_len EQU 1
EXTI_PR1_PR20 EQU 0x00100000 ; Pending bit 20
EXTI_PR1_PR20_ofs EQU 20
EXTI_PR1_PR20_len EQU 1
EXTI_PR1_PR21 EQU 0x00200000 ; Pending bit 21
EXTI_PR1_PR21_ofs EQU 21
EXTI_PR1_PR21_len EQU 1
EXTI_PR1_PR22 EQU 0x00400000 ; Pending bit 22
EXTI_PR1_PR22_ofs EQU 22
EXTI_PR1_PR22_len EQU 1
EXTI_PR1_PR29 EQU 0x20000000 ; Pending bit 29
EXTI_PR1_PR29_ofs EQU 29
EXTI_PR1_PR29_len EQU 1
EXTI_PR1_PR30 EQU 0x40000000 ; Pending bit 30
EXTI_PR1_PR30_ofs EQU 30
EXTI_PR1_PR30_len EQU 1
EXTI_PR1_PR31 EQU 0x80000000 ; Pending bit 31
EXTI_PR1_PR31_ofs EQU 31
EXTI_PR1_PR31_len EQU 1
; EXTI_IMR2 fields:
EXTI_IMR2_MR32 EQU 0x00000001 ; Interrupt Mask on external/internal line 32
EXTI_IMR2_MR32_ofs EQU 0
EXTI_IMR2_MR32_len EQU 1
EXTI_IMR2_MR33 EQU 0x00000002 ; Interrupt Mask on external/internal line 33
EXTI_IMR2_MR33_ofs EQU 1
EXTI_IMR2_MR33_len EQU 1
EXTI_IMR2_MR34 EQU 0x00000004 ; Interrupt Mask on external/internal line 34
EXTI_IMR2_MR34_ofs EQU 2
EXTI_IMR2_MR34_len EQU 1
EXTI_IMR2_MR35 EQU 0x00000008 ; Interrupt Mask on external/internal line 35
EXTI_IMR2_MR35_ofs EQU 3
EXTI_IMR2_MR35_len EQU 1
; EXTI_EMR2 fields:
EXTI_EMR2_MR32 EQU 0x00000001 ; Event mask on external/internal line 32
EXTI_EMR2_MR32_ofs EQU 0
EXTI_EMR2_MR32_len EQU 1
EXTI_EMR2_MR33 EQU 0x00000002 ; Event mask on external/internal line 33
EXTI_EMR2_MR33_ofs EQU 1
EXTI_EMR2_MR33_len EQU 1
EXTI_EMR2_MR34 EQU 0x00000004 ; Event mask on external/internal line 34
EXTI_EMR2_MR34_ofs EQU 2
EXTI_EMR2_MR34_len EQU 1
EXTI_EMR2_MR35 EQU 0x00000008 ; Event mask on external/internal line 35
EXTI_EMR2_MR35_ofs EQU 3
EXTI_EMR2_MR35_len EQU 1
; EXTI_RTSR2 fields:
EXTI_RTSR2_TR32 EQU 0x00000001 ; Rising trigger event configuration bit of line 32
EXTI_RTSR2_TR32_ofs EQU 0
EXTI_RTSR2_TR32_len EQU 1
EXTI_RTSR2_TR33 EQU 0x00000002 ; Rising trigger event configuration bit of line 33
EXTI_RTSR2_TR33_ofs EQU 1
EXTI_RTSR2_TR33_len EQU 1
; EXTI_FTSR2 fields:
EXTI_FTSR2_TR32 EQU 0x00000001 ; Falling trigger event configuration bit of line 32
EXTI_FTSR2_TR32_ofs EQU 0
EXTI_FTSR2_TR32_len EQU 1
EXTI_FTSR2_TR33 EQU 0x00000002 ; Falling trigger event configuration bit of line 33
EXTI_FTSR2_TR33_ofs EQU 1
EXTI_FTSR2_TR33_len EQU 1
; EXTI_SWIER2 fields:
EXTI_SWIER2_SWIER32 EQU 0x00000001 ; Software interrupt on line 32
EXTI_SWIER2_SWIER32_ofs EQU 0
EXTI_SWIER2_SWIER32_len EQU 1
EXTI_SWIER2_SWIER33 EQU 0x00000002 ; Software interrupt on line 33
EXTI_SWIER2_SWIER33_ofs EQU 1
EXTI_SWIER2_SWIER33_len EQU 1
; EXTI_PR2 fields:
EXTI_PR2_PR32 EQU 0x00000001 ; Pending bit on line 32
EXTI_PR2_PR32_ofs EQU 0
EXTI_PR2_PR32_len EQU 1
EXTI_PR2_PR33 EQU 0x00000002 ; Pending bit on line 33
EXTI_PR2_PR33_ofs EQU 1
EXTI_PR2_PR33_len EQU 1
; ---- COMP --------------------------------------------------
; Desc: Comparator
; COMP base address:
COMP_BASE EQU 0x4001001c
; COMP registers:
COMP_COMP1_CSR EQU (COMP_BASE + 0x0) ; control and status register
COMP_COMP2_CSR EQU (COMP_BASE + 0x4) ; control and status register
COMP_COMP3_CSR EQU (COMP_BASE + 0x8) ; control and status register
COMP_COMP4_CSR EQU (COMP_BASE + 0xc) ; control and status register
COMP_COMP5_CSR EQU (COMP_BASE + 0x10) ; control and status register
COMP_COMP6_CSR EQU (COMP_BASE + 0x14) ; control and status register
COMP_COMP7_CSR EQU (COMP_BASE + 0x18) ; control and status register
; COMP_COMP1_CSR fields:
COMP_COMP1_CSR_COMP1EN EQU 0x00000001 ; Comparator 1 enable
COMP_COMP1_CSR_COMP1EN_ofs EQU 0
COMP_COMP1_CSR_COMP1EN_len EQU 1
COMP_COMP1_CSR_COMP1_INP_DAC EQU 0x00000002 ; COMP1_INP_DAC
COMP_COMP1_CSR_COMP1_INP_DAC_ofs EQU 1
COMP_COMP1_CSR_COMP1_INP_DAC_len EQU 1
COMP_COMP1_CSR_COMP1MODE EQU 0x0000000c ; Comparator 1 mode
COMP_COMP1_CSR_COMP1MODE_ofs EQU 2
COMP_COMP1_CSR_COMP1MODE_len EQU 2
COMP_COMP1_CSR_COMP1INSEL EQU 0x00000070 ; Comparator 1 inverting input selection
COMP_COMP1_CSR_COMP1INSEL_ofs EQU 4
COMP_COMP1_CSR_COMP1INSEL_len EQU 3
COMP_COMP1_CSR_COMP1_OUT_SEL EQU 0x00003c00 ; Comparator 1 output selection
COMP_COMP1_CSR_COMP1_OUT_SEL_ofs EQU 10
COMP_COMP1_CSR_COMP1_OUT_SEL_len EQU 4
COMP_COMP1_CSR_COMP1POL EQU 0x00008000 ; Comparator 1 output polarity
COMP_COMP1_CSR_COMP1POL_ofs EQU 15
COMP_COMP1_CSR_COMP1POL_len EQU 1
COMP_COMP1_CSR_COMP1HYST EQU 0x00030000 ; Comparator 1 hysteresis
COMP_COMP1_CSR_COMP1HYST_ofs EQU 16
COMP_COMP1_CSR_COMP1HYST_len EQU 2
COMP_COMP1_CSR_COMP1_BLANKING EQU 0x001c0000 ; Comparator 1 blanking source
COMP_COMP1_CSR_COMP1_BLANKING_ofs EQU 18
COMP_COMP1_CSR_COMP1_BLANKING_len EQU 3
COMP_COMP1_CSR_COMP1OUT EQU 0x40000000 ; Comparator 1 output
COMP_COMP1_CSR_COMP1OUT_ofs EQU 30
COMP_COMP1_CSR_COMP1OUT_len EQU 1
COMP_COMP1_CSR_COMP1LOCK EQU 0x80000000 ; Comparator 1 lock
COMP_COMP1_CSR_COMP1LOCK_ofs EQU 31
COMP_COMP1_CSR_COMP1LOCK_len EQU 1
; COMP_COMP2_CSR fields:
COMP_COMP2_CSR_COMP2EN EQU 0x00000001 ; Comparator 2 enable
COMP_COMP2_CSR_COMP2EN_ofs EQU 0
COMP_COMP2_CSR_COMP2EN_len EQU 1
COMP_COMP2_CSR_COMP2MODE EQU 0x0000000c ; Comparator 2 mode
COMP_COMP2_CSR_COMP2MODE_ofs EQU 2
COMP_COMP2_CSR_COMP2MODE_len EQU 2
COMP_COMP2_CSR_COMP2INSEL EQU 0x00000070 ; Comparator 2 inverting input selection
COMP_COMP2_CSR_COMP2INSEL_ofs EQU 4
COMP_COMP2_CSR_COMP2INSEL_len EQU 3
COMP_COMP2_CSR_COMP2INPSEL EQU 0x00000080 ; Comparator 2 non inverted input selection
COMP_COMP2_CSR_COMP2INPSEL_ofs EQU 7
COMP_COMP2_CSR_COMP2INPSEL_len EQU 1
COMP_COMP2_CSR_COMP2INMSEL EQU 0x00000200 ; Comparator 1inverting input selection
COMP_COMP2_CSR_COMP2INMSEL_ofs EQU 9
COMP_COMP2_CSR_COMP2INMSEL_len EQU 1
COMP_COMP2_CSR_COMP2_OUT_SEL EQU 0x00003c00 ; Comparator 2 output selection
COMP_COMP2_CSR_COMP2_OUT_SEL_ofs EQU 10
COMP_COMP2_CSR_COMP2_OUT_SEL_len EQU 4
COMP_COMP2_CSR_COMP2POL EQU 0x00008000 ; Comparator 2 output polarity
COMP_COMP2_CSR_COMP2POL_ofs EQU 15
COMP_COMP2_CSR_COMP2POL_len EQU 1
COMP_COMP2_CSR_COMP2HYST EQU 0x00030000 ; Comparator 2 hysteresis
COMP_COMP2_CSR_COMP2HYST_ofs EQU 16
COMP_COMP2_CSR_COMP2HYST_len EQU 2
COMP_COMP2_CSR_COMP2_BLANKING EQU 0x001c0000 ; Comparator 2 blanking source
COMP_COMP2_CSR_COMP2_BLANKING_ofs EQU 18
COMP_COMP2_CSR_COMP2_BLANKING_len EQU 3
COMP_COMP2_CSR_COMP2OUT EQU 0x40000000 ; Comparator 2 output
COMP_COMP2_CSR_COMP2OUT_ofs EQU 30
COMP_COMP2_CSR_COMP2OUT_len EQU 1
COMP_COMP2_CSR_COMP2LOCK EQU 0x80000000 ; Comparator 2 lock
COMP_COMP2_CSR_COMP2LOCK_ofs EQU 31
COMP_COMP2_CSR_COMP2LOCK_len EQU 1
; COMP_COMP3_CSR fields:
COMP_COMP3_CSR_COMP3EN EQU 0x00000001 ; Comparator 3 enable
COMP_COMP3_CSR_COMP3EN_ofs EQU 0
COMP_COMP3_CSR_COMP3EN_len EQU 1
COMP_COMP3_CSR_COMP3MODE EQU 0x0000000c ; Comparator 3 mode
COMP_COMP3_CSR_COMP3MODE_ofs EQU 2
COMP_COMP3_CSR_COMP3MODE_len EQU 2
COMP_COMP3_CSR_COMP3INSEL EQU 0x00000070 ; Comparator 3 inverting input selection
COMP_COMP3_CSR_COMP3INSEL_ofs EQU 4
COMP_COMP3_CSR_COMP3INSEL_len EQU 3
COMP_COMP3_CSR_COMP3INPSEL EQU 0x00000080 ; Comparator 3 non inverted input selection
COMP_COMP3_CSR_COMP3INPSEL_ofs EQU 7
COMP_COMP3_CSR_COMP3INPSEL_len EQU 1
COMP_COMP3_CSR_COMP3_OUT_SEL EQU 0x00003c00 ; Comparator 3 output selection
COMP_COMP3_CSR_COMP3_OUT_SEL_ofs EQU 10
COMP_COMP3_CSR_COMP3_OUT_SEL_len EQU 4
COMP_COMP3_CSR_COMP3POL EQU 0x00008000 ; Comparator 3 output polarity
COMP_COMP3_CSR_COMP3POL_ofs EQU 15
COMP_COMP3_CSR_COMP3POL_len EQU 1
COMP_COMP3_CSR_COMP3HYST EQU 0x00030000 ; Comparator 3 hysteresis
COMP_COMP3_CSR_COMP3HYST_ofs EQU 16
COMP_COMP3_CSR_COMP3HYST_len EQU 2
COMP_COMP3_CSR_COMP3_BLANKING EQU 0x001c0000 ; Comparator 3 blanking source
COMP_COMP3_CSR_COMP3_BLANKING_ofs EQU 18
COMP_COMP3_CSR_COMP3_BLANKING_len EQU 3
COMP_COMP3_CSR_COMP3OUT EQU 0x40000000 ; Comparator 3 output
COMP_COMP3_CSR_COMP3OUT_ofs EQU 30
COMP_COMP3_CSR_COMP3OUT_len EQU 1
COMP_COMP3_CSR_COMP3LOCK EQU 0x80000000 ; Comparator 3 lock
COMP_COMP3_CSR_COMP3LOCK_ofs EQU 31
COMP_COMP3_CSR_COMP3LOCK_len EQU 1
; COMP_COMP4_CSR fields:
COMP_COMP4_CSR_COMP4EN EQU 0x00000001 ; Comparator 4 enable
COMP_COMP4_CSR_COMP4EN_ofs EQU 0
COMP_COMP4_CSR_COMP4EN_len EQU 1
COMP_COMP4_CSR_COMP4MODE EQU 0x0000000c ; Comparator 4 mode
COMP_COMP4_CSR_COMP4MODE_ofs EQU 2
COMP_COMP4_CSR_COMP4MODE_len EQU 2
COMP_COMP4_CSR_COMP4INSEL EQU 0x00000070 ; Comparator 4 inverting input selection
COMP_COMP4_CSR_COMP4INSEL_ofs EQU 4
COMP_COMP4_CSR_COMP4INSEL_len EQU 3
COMP_COMP4_CSR_COMP4INPSEL EQU 0x00000080 ; Comparator 4 non inverted input selection
COMP_COMP4_CSR_COMP4INPSEL_ofs EQU 7
COMP_COMP4_CSR_COMP4INPSEL_len EQU 1
COMP_COMP4_CSR_COM4WINMODE EQU 0x00000200 ; Comparator 4 window mode
COMP_COMP4_CSR_COM4WINMODE_ofs EQU 9
COMP_COMP4_CSR_COM4WINMODE_len EQU 1
COMP_COMP4_CSR_COMP4_OUT_SEL EQU 0x00003c00 ; Comparator 4 output selection
COMP_COMP4_CSR_COMP4_OUT_SEL_ofs EQU 10
COMP_COMP4_CSR_COMP4_OUT_SEL_len EQU 4
COMP_COMP4_CSR_COMP4POL EQU 0x00008000 ; Comparator 4 output polarity
COMP_COMP4_CSR_COMP4POL_ofs EQU 15
COMP_COMP4_CSR_COMP4POL_len EQU 1
COMP_COMP4_CSR_COMP4HYST EQU 0x00030000 ; Comparator 4 hysteresis
COMP_COMP4_CSR_COMP4HYST_ofs EQU 16
COMP_COMP4_CSR_COMP4HYST_len EQU 2
COMP_COMP4_CSR_COMP4_BLANKING EQU 0x001c0000 ; Comparator 4 blanking source
COMP_COMP4_CSR_COMP4_BLANKING_ofs EQU 18
COMP_COMP4_CSR_COMP4_BLANKING_len EQU 3
COMP_COMP4_CSR_COMP4OUT EQU 0x40000000 ; Comparator 4 output
COMP_COMP4_CSR_COMP4OUT_ofs EQU 30
COMP_COMP4_CSR_COMP4OUT_len EQU 1
COMP_COMP4_CSR_COMP4LOCK EQU 0x80000000 ; Comparator 4 lock
COMP_COMP4_CSR_COMP4LOCK_ofs EQU 31
COMP_COMP4_CSR_COMP4LOCK_len EQU 1
; COMP_COMP5_CSR fields:
COMP_COMP5_CSR_COMP5EN EQU 0x00000001 ; Comparator 5 enable
COMP_COMP5_CSR_COMP5EN_ofs EQU 0
COMP_COMP5_CSR_COMP5EN_len EQU 1
COMP_COMP5_CSR_COMP5MODE EQU 0x0000000c ; Comparator 5 mode
COMP_COMP5_CSR_COMP5MODE_ofs EQU 2
COMP_COMP5_CSR_COMP5MODE_len EQU 2
COMP_COMP5_CSR_COMP5INSEL EQU 0x00000070 ; Comparator 5 inverting input selection
COMP_COMP5_CSR_COMP5INSEL_ofs EQU 4
COMP_COMP5_CSR_COMP5INSEL_len EQU 3
COMP_COMP5_CSR_COMP5INPSEL EQU 0x00000080 ; Comparator 5 non inverted input selection
COMP_COMP5_CSR_COMP5INPSEL_ofs EQU 7
COMP_COMP5_CSR_COMP5INPSEL_len EQU 1
COMP_COMP5_CSR_COMP5_OUT_SEL EQU 0x00003c00 ; Comparator 5 output selection
COMP_COMP5_CSR_COMP5_OUT_SEL_ofs EQU 10
COMP_COMP5_CSR_COMP5_OUT_SEL_len EQU 4
COMP_COMP5_CSR_COMP5POL EQU 0x00008000 ; Comparator 5 output polarity
COMP_COMP5_CSR_COMP5POL_ofs EQU 15
COMP_COMP5_CSR_COMP5POL_len EQU 1
COMP_COMP5_CSR_COMP5HYST EQU 0x00030000 ; Comparator 5 hysteresis
COMP_COMP5_CSR_COMP5HYST_ofs EQU 16
COMP_COMP5_CSR_COMP5HYST_len EQU 2
COMP_COMP5_CSR_COMP5_BLANKING EQU 0x001c0000 ; Comparator 5 blanking source
COMP_COMP5_CSR_COMP5_BLANKING_ofs EQU 18
COMP_COMP5_CSR_COMP5_BLANKING_len EQU 3
COMP_COMP5_CSR_COMP5OUT EQU 0x40000000 ; Comparator51 output
COMP_COMP5_CSR_COMP5OUT_ofs EQU 30
COMP_COMP5_CSR_COMP5OUT_len EQU 1
COMP_COMP5_CSR_COMP5LOCK EQU 0x80000000 ; Comparator 5 lock
COMP_COMP5_CSR_COMP5LOCK_ofs EQU 31
COMP_COMP5_CSR_COMP5LOCK_len EQU 1
; COMP_COMP6_CSR fields:
COMP_COMP6_CSR_COMP6EN EQU 0x00000001 ; Comparator 6 enable
COMP_COMP6_CSR_COMP6EN_ofs EQU 0
COMP_COMP6_CSR_COMP6EN_len EQU 1
COMP_COMP6_CSR_COMP6MODE EQU 0x0000000c ; Comparator 6 mode
COMP_COMP6_CSR_COMP6MODE_ofs EQU 2
COMP_COMP6_CSR_COMP6MODE_len EQU 2
COMP_COMP6_CSR_COMP6INSEL EQU 0x00000070 ; Comparator 6 inverting input selection
COMP_COMP6_CSR_COMP6INSEL_ofs EQU 4
COMP_COMP6_CSR_COMP6INSEL_len EQU 3
COMP_COMP6_CSR_COMP6INPSEL EQU 0x00000080 ; Comparator 6 non inverted input selection
COMP_COMP6_CSR_COMP6INPSEL_ofs EQU 7
COMP_COMP6_CSR_COMP6INPSEL_len EQU 1
COMP_COMP6_CSR_COM6WINMODE EQU 0x00000200 ; Comparator 6 window mode
COMP_COMP6_CSR_COM6WINMODE_ofs EQU 9
COMP_COMP6_CSR_COM6WINMODE_len EQU 1
COMP_COMP6_CSR_COMP6_OUT_SEL EQU 0x00003c00 ; Comparator 6 output selection
COMP_COMP6_CSR_COMP6_OUT_SEL_ofs EQU 10
COMP_COMP6_CSR_COMP6_OUT_SEL_len EQU 4
COMP_COMP6_CSR_COMP6POL EQU 0x00008000 ; Comparator 6 output polarity
COMP_COMP6_CSR_COMP6POL_ofs EQU 15
COMP_COMP6_CSR_COMP6POL_len EQU 1
COMP_COMP6_CSR_COMP6HYST EQU 0x00030000 ; Comparator 6 hysteresis
COMP_COMP6_CSR_COMP6HYST_ofs EQU 16
COMP_COMP6_CSR_COMP6HYST_len EQU 2
COMP_COMP6_CSR_COMP6_BLANKING EQU 0x001c0000 ; Comparator 6 blanking source
COMP_COMP6_CSR_COMP6_BLANKING_ofs EQU 18
COMP_COMP6_CSR_COMP6_BLANKING_len EQU 3
COMP_COMP6_CSR_COMP6OUT EQU 0x40000000 ; Comparator 6 output
COMP_COMP6_CSR_COMP6OUT_ofs EQU 30
COMP_COMP6_CSR_COMP6OUT_len EQU 1
COMP_COMP6_CSR_COMP6LOCK EQU 0x80000000 ; Comparator 6 lock
COMP_COMP6_CSR_COMP6LOCK_ofs EQU 31
COMP_COMP6_CSR_COMP6LOCK_len EQU 1
; COMP_COMP7_CSR fields:
COMP_COMP7_CSR_COMP7EN EQU 0x00000001 ; Comparator 7 enable
COMP_COMP7_CSR_COMP7EN_ofs EQU 0
COMP_COMP7_CSR_COMP7EN_len EQU 1
COMP_COMP7_CSR_COMP7MODE EQU 0x0000000c ; Comparator 7 mode
COMP_COMP7_CSR_COMP7MODE_ofs EQU 2
COMP_COMP7_CSR_COMP7MODE_len EQU 2
COMP_COMP7_CSR_COMP7INSEL EQU 0x00000070 ; Comparator 7 inverting input selection
COMP_COMP7_CSR_COMP7INSEL_ofs EQU 4
COMP_COMP7_CSR_COMP7INSEL_len EQU 3
COMP_COMP7_CSR_COMP7INPSEL EQU 0x00000080 ; Comparator 7 non inverted input selection
COMP_COMP7_CSR_COMP7INPSEL_ofs EQU 7
COMP_COMP7_CSR_COMP7INPSEL_len EQU 1
COMP_COMP7_CSR_COMP7_OUT_SEL EQU 0x00003c00 ; Comparator 7 output selection
COMP_COMP7_CSR_COMP7_OUT_SEL_ofs EQU 10
COMP_COMP7_CSR_COMP7_OUT_SEL_len EQU 4
COMP_COMP7_CSR_COMP7POL EQU 0x00008000 ; Comparator 7 output polarity
COMP_COMP7_CSR_COMP7POL_ofs EQU 15
COMP_COMP7_CSR_COMP7POL_len EQU 1
COMP_COMP7_CSR_COMP7HYST EQU 0x00030000 ; Comparator 7 hysteresis
COMP_COMP7_CSR_COMP7HYST_ofs EQU 16
COMP_COMP7_CSR_COMP7HYST_len EQU 2
COMP_COMP7_CSR_COMP7_BLANKING EQU 0x001c0000 ; Comparator 7 blanking source
COMP_COMP7_CSR_COMP7_BLANKING_ofs EQU 18
COMP_COMP7_CSR_COMP7_BLANKING_len EQU 3
COMP_COMP7_CSR_COMP7OUT EQU 0x40000000 ; Comparator 7 output
COMP_COMP7_CSR_COMP7OUT_ofs EQU 30
COMP_COMP7_CSR_COMP7OUT_len EQU 1
COMP_COMP7_CSR_COMP7LOCK EQU 0x80000000 ; Comparator 7 lock
COMP_COMP7_CSR_COMP7LOCK_ofs EQU 31
COMP_COMP7_CSR_COMP7LOCK_len EQU 1
; ---- PWR ---------------------------------------------------
; Desc: Power control
; PWR base address:
PWR_BASE EQU 0x40007000
; PWR registers:
PWR_CR EQU (PWR_BASE + 0x0) ; power control register
PWR_CSR EQU (PWR_BASE + 0x4) ; power control/status register
; PWR_CR fields:
PWR_CR_LPDS EQU 0x00000001 ; Low-power deep sleep
PWR_CR_LPDS_ofs EQU 0
PWR_CR_LPDS_len EQU 1
PWR_CR_PDDS EQU 0x00000002 ; Power down deepsleep
PWR_CR_PDDS_ofs EQU 1
PWR_CR_PDDS_len EQU 1
PWR_CR_CWUF EQU 0x00000004 ; Clear wakeup flag
PWR_CR_CWUF_ofs EQU 2
PWR_CR_CWUF_len EQU 1
PWR_CR_CSBF EQU 0x00000008 ; Clear standby flag
PWR_CR_CSBF_ofs EQU 3
PWR_CR_CSBF_len EQU 1
PWR_CR_PVDE EQU 0x00000010 ; Power voltage detector enable
PWR_CR_PVDE_ofs EQU 4
PWR_CR_PVDE_len EQU 1
PWR_CR_PLS EQU 0x000000e0 ; PVD level selection
PWR_CR_PLS_ofs EQU 5
PWR_CR_PLS_len EQU 3
PWR_CR_DBP EQU 0x00000100 ; Disable backup domain write protection
PWR_CR_DBP_ofs EQU 8
PWR_CR_DBP_len EQU 1
; PWR_CSR fields:
PWR_CSR_WUF EQU 0x00000001 ; Wakeup flag
PWR_CSR_WUF_ofs EQU 0
PWR_CSR_WUF_len EQU 1
PWR_CSR_SBF EQU 0x00000002 ; Standby flag
PWR_CSR_SBF_ofs EQU 1
PWR_CSR_SBF_len EQU 1
PWR_CSR_PVDO EQU 0x00000004 ; PVD output
PWR_CSR_PVDO_ofs EQU 2
PWR_CSR_PVDO_len EQU 1
PWR_CSR_EWUP1 EQU 0x00000100 ; Enable WKUP1 pin
PWR_CSR_EWUP1_ofs EQU 8
PWR_CSR_EWUP1_len EQU 1
PWR_CSR_EWUP2 EQU 0x00000200 ; Enable WKUP2 pin
PWR_CSR_EWUP2_ofs EQU 9
PWR_CSR_EWUP2_len EQU 1
; ---- CAN ---------------------------------------------------
; Desc: Controller area network
; CAN base address:
CAN_BASE EQU 0x40006400
; CAN registers:
CAN_MCR EQU (CAN_BASE + 0x0) ; master control register
CAN_MSR EQU (CAN_BASE + 0x4) ; master status register
CAN_TSR EQU (CAN_BASE + 0x8) ; transmit status register
CAN_RF0R EQU (CAN_BASE + 0xc) ; receive FIFO 0 register
CAN_RF1R EQU (CAN_BASE + 0x10) ; receive FIFO 1 register
CAN_IER EQU (CAN_BASE + 0x14) ; interrupt enable register
CAN_ESR EQU (CAN_BASE + 0x18) ; error status register
CAN_BTR EQU (CAN_BASE + 0x1c) ; bit timing register
CAN_TI0R EQU (CAN_BASE + 0x180) ; TX mailbox identifier register
CAN_TDT0R EQU (CAN_BASE + 0x184) ; mailbox data length control and time stamp register
CAN_TDL0R EQU (CAN_BASE + 0x188) ; mailbox data low register
CAN_TDH0R EQU (CAN_BASE + 0x18c) ; mailbox data high register
CAN_TI1R EQU (CAN_BASE + 0x190) ; TX mailbox identifier register
CAN_TDT1R EQU (CAN_BASE + 0x194) ; mailbox data length control and time stamp register
CAN_TDL1R EQU (CAN_BASE + 0x198) ; mailbox data low register
CAN_TDH1R EQU (CAN_BASE + 0x19c) ; mailbox data high register
CAN_TI2R EQU (CAN_BASE + 0x1a0) ; TX mailbox identifier register
CAN_TDT2R EQU (CAN_BASE + 0x1a4) ; mailbox data length control and time stamp register
CAN_TDL2R EQU (CAN_BASE + 0x1a8) ; mailbox data low register
CAN_TDH2R EQU (CAN_BASE + 0x1ac) ; mailbox data high register
CAN_RI0R EQU (CAN_BASE + 0x1b0) ; receive FIFO mailbox identifier register
CAN_RDT0R EQU (CAN_BASE + 0x1b4) ; receive FIFO mailbox data length control and time stamp register
CAN_RDL0R EQU (CAN_BASE + 0x1b8) ; receive FIFO mailbox data low register
CAN_RDH0R EQU (CAN_BASE + 0x1bc) ; receive FIFO mailbox data high register
CAN_RI1R EQU (CAN_BASE + 0x1c0) ; receive FIFO mailbox identifier register
CAN_RDT1R EQU (CAN_BASE + 0x1c4) ; receive FIFO mailbox data length control and time stamp register
CAN_RDL1R EQU (CAN_BASE + 0x1c8) ; receive FIFO mailbox data low register
CAN_RDH1R EQU (CAN_BASE + 0x1cc) ; receive FIFO mailbox data high register
CAN_FMR EQU (CAN_BASE + 0x200) ; filter master register
CAN_FM1R EQU (CAN_BASE + 0x204) ; filter mode register
CAN_FS1R EQU (CAN_BASE + 0x20c) ; filter scale register
CAN_FFA1R EQU (CAN_BASE + 0x214) ; filter FIFO assignment register
CAN_FA1R EQU (CAN_BASE + 0x21c) ; CAN filter activation register
CAN_F0R1 EQU (CAN_BASE + 0x240) ; Filter bank 0 register 1
CAN_F0R2 EQU (CAN_BASE + 0x244) ; Filter bank 0 register 2
CAN_F1R1 EQU (CAN_BASE + 0x248) ; Filter bank 1 register 1
CAN_F1R2 EQU (CAN_BASE + 0x24c) ; Filter bank 1 register 2
CAN_F2R1 EQU (CAN_BASE + 0x250) ; Filter bank 2 register 1
CAN_F2R2 EQU (CAN_BASE + 0x254) ; Filter bank 2 register 2
CAN_F3R1 EQU (CAN_BASE + 0x258) ; Filter bank 3 register 1
CAN_F3R2 EQU (CAN_BASE + 0x25c) ; Filter bank 3 register 2
CAN_F4R1 EQU (CAN_BASE + 0x260) ; Filter bank 4 register 1
CAN_F4R2 EQU (CAN_BASE + 0x264) ; Filter bank 4 register 2
CAN_F5R1 EQU (CAN_BASE + 0x268) ; Filter bank 5 register 1
CAN_F5R2 EQU (CAN_BASE + 0x26c) ; Filter bank 5 register 2
CAN_F6R1 EQU (CAN_BASE + 0x270) ; Filter bank 6 register 1
CAN_F6R2 EQU (CAN_BASE + 0x274) ; Filter bank 6 register 2
CAN_F7R1 EQU (CAN_BASE + 0x278) ; Filter bank 7 register 1
CAN_F7R2 EQU (CAN_BASE + 0x27c) ; Filter bank 7 register 2
CAN_F8R1 EQU (CAN_BASE + 0x280) ; Filter bank 8 register 1
CAN_F8R2 EQU (CAN_BASE + 0x284) ; Filter bank 8 register 2
CAN_F9R1 EQU (CAN_BASE + 0x288) ; Filter bank 9 register 1
CAN_F9R2 EQU (CAN_BASE + 0x28c) ; Filter bank 9 register 2
CAN_F10R1 EQU (CAN_BASE + 0x290) ; Filter bank 10 register 1
CAN_F10R2 EQU (CAN_BASE + 0x294) ; Filter bank 10 register 2
CAN_F11R1 EQU (CAN_BASE + 0x298) ; Filter bank 11 register 1
CAN_F11R2 EQU (CAN_BASE + 0x29c) ; Filter bank 11 register 2
CAN_F12R1 EQU (CAN_BASE + 0x2a0) ; Filter bank 4 register 1
CAN_F12R2 EQU (CAN_BASE + 0x2a4) ; Filter bank 12 register 2
CAN_F13R1 EQU (CAN_BASE + 0x2a8) ; Filter bank 13 register 1
CAN_F13R2 EQU (CAN_BASE + 0x2ac) ; Filter bank 13 register 2
CAN_F14R1 EQU (CAN_BASE + 0x2b0) ; Filter bank 14 register 1
CAN_F14R2 EQU (CAN_BASE + 0x2b4) ; Filter bank 14 register 2
CAN_F15R1 EQU (CAN_BASE + 0x2b8) ; Filter bank 15 register 1
CAN_F15R2 EQU (CAN_BASE + 0x2bc) ; Filter bank 15 register 2
CAN_F16R1 EQU (CAN_BASE + 0x2c0) ; Filter bank 16 register 1
CAN_F16R2 EQU (CAN_BASE + 0x2c4) ; Filter bank 16 register 2
CAN_F17R1 EQU (CAN_BASE + 0x2c8) ; Filter bank 17 register 1
CAN_F17R2 EQU (CAN_BASE + 0x2cc) ; Filter bank 17 register 2
CAN_F18R1 EQU (CAN_BASE + 0x2d0) ; Filter bank 18 register 1
CAN_F18R2 EQU (CAN_BASE + 0x2d4) ; Filter bank 18 register 2
CAN_F19R1 EQU (CAN_BASE + 0x2d8) ; Filter bank 19 register 1
CAN_F19R2 EQU (CAN_BASE + 0x2dc) ; Filter bank 19 register 2
CAN_F20R1 EQU (CAN_BASE + 0x2e0) ; Filter bank 20 register 1
CAN_F20R2 EQU (CAN_BASE + 0x2e4) ; Filter bank 20 register 2
CAN_F21R1 EQU (CAN_BASE + 0x2e8) ; Filter bank 21 register 1
CAN_F21R2 EQU (CAN_BASE + 0x2ec) ; Filter bank 21 register 2
CAN_F22R1 EQU (CAN_BASE + 0x2f0) ; Filter bank 22 register 1
CAN_F22R2 EQU (CAN_BASE + 0x2f4) ; Filter bank 22 register 2
CAN_F23R1 EQU (CAN_BASE + 0x2f8) ; Filter bank 23 register 1
CAN_F23R2 EQU (CAN_BASE + 0x2fc) ; Filter bank 23 register 2
CAN_F24R1 EQU (CAN_BASE + 0x300) ; Filter bank 24 register 1
CAN_F24R2 EQU (CAN_BASE + 0x304) ; Filter bank 24 register 2
CAN_F25R1 EQU (CAN_BASE + 0x308) ; Filter bank 25 register 1
CAN_F25R2 EQU (CAN_BASE + 0x30c) ; Filter bank 25 register 2
CAN_F26R1 EQU (CAN_BASE + 0x310) ; Filter bank 26 register 1
CAN_F26R2 EQU (CAN_BASE + 0x314) ; Filter bank 26 register 2
CAN_F27R1 EQU (CAN_BASE + 0x318) ; Filter bank 27 register 1
CAN_F27R2 EQU (CAN_BASE + 0x31c) ; Filter bank 27 register 2
; CAN_MCR fields:
CAN_MCR_DBF EQU 0x00010000 ; DBF
CAN_MCR_DBF_ofs EQU 16
CAN_MCR_DBF_len EQU 1
CAN_MCR_RESET EQU 0x00008000 ; RESET
CAN_MCR_RESET_ofs EQU 15
CAN_MCR_RESET_len EQU 1
CAN_MCR_TTCM EQU 0x00000080 ; TTCM
CAN_MCR_TTCM_ofs EQU 7
CAN_MCR_TTCM_len EQU 1
CAN_MCR_ABOM EQU 0x00000040 ; ABOM
CAN_MCR_ABOM_ofs EQU 6
CAN_MCR_ABOM_len EQU 1
CAN_MCR_AWUM EQU 0x00000020 ; AWUM
CAN_MCR_AWUM_ofs EQU 5
CAN_MCR_AWUM_len EQU 1
CAN_MCR_NART EQU 0x00000010 ; NART
CAN_MCR_NART_ofs EQU 4
CAN_MCR_NART_len EQU 1
CAN_MCR_RFLM EQU 0x00000008 ; RFLM
CAN_MCR_RFLM_ofs EQU 3
CAN_MCR_RFLM_len EQU 1
CAN_MCR_TXFP EQU 0x00000004 ; TXFP
CAN_MCR_TXFP_ofs EQU 2
CAN_MCR_TXFP_len EQU 1
CAN_MCR_SLEEP EQU 0x00000002 ; SLEEP
CAN_MCR_SLEEP_ofs EQU 1
CAN_MCR_SLEEP_len EQU 1
CAN_MCR_INRQ EQU 0x00000001 ; INRQ
CAN_MCR_INRQ_ofs EQU 0
CAN_MCR_INRQ_len EQU 1
; CAN_MSR fields:
CAN_MSR_RX EQU 0x00000800 ; RX
CAN_MSR_RX_ofs EQU 11
CAN_MSR_RX_len EQU 1
CAN_MSR_SAMP EQU 0x00000400 ; SAMP
CAN_MSR_SAMP_ofs EQU 10
CAN_MSR_SAMP_len EQU 1
CAN_MSR_RXM EQU 0x00000200 ; RXM
CAN_MSR_RXM_ofs EQU 9
CAN_MSR_RXM_len EQU 1
CAN_MSR_TXM EQU 0x00000100 ; TXM
CAN_MSR_TXM_ofs EQU 8
CAN_MSR_TXM_len EQU 1
CAN_MSR_SLAKI EQU 0x00000010 ; SLAKI
CAN_MSR_SLAKI_ofs EQU 4
CAN_MSR_SLAKI_len EQU 1
CAN_MSR_WKUI EQU 0x00000008 ; WKUI
CAN_MSR_WKUI_ofs EQU 3
CAN_MSR_WKUI_len EQU 1
CAN_MSR_ERRI EQU 0x00000004 ; ERRI
CAN_MSR_ERRI_ofs EQU 2
CAN_MSR_ERRI_len EQU 1
CAN_MSR_SLAK EQU 0x00000002 ; SLAK
CAN_MSR_SLAK_ofs EQU 1
CAN_MSR_SLAK_len EQU 1
CAN_MSR_INAK EQU 0x00000001 ; INAK
CAN_MSR_INAK_ofs EQU 0
CAN_MSR_INAK_len EQU 1
; CAN_TSR fields:
CAN_TSR_LOW2 EQU 0x80000000 ; Lowest priority flag for mailbox 2
CAN_TSR_LOW2_ofs EQU 31
CAN_TSR_LOW2_len EQU 1
CAN_TSR_LOW1 EQU 0x40000000 ; Lowest priority flag for mailbox 1
CAN_TSR_LOW1_ofs EQU 30
CAN_TSR_LOW1_len EQU 1
CAN_TSR_LOW0 EQU 0x20000000 ; Lowest priority flag for mailbox 0
CAN_TSR_LOW0_ofs EQU 29
CAN_TSR_LOW0_len EQU 1
CAN_TSR_TME2 EQU 0x10000000 ; Lowest priority flag for mailbox 2
CAN_TSR_TME2_ofs EQU 28
CAN_TSR_TME2_len EQU 1
CAN_TSR_TME1 EQU 0x08000000 ; Lowest priority flag for mailbox 1
CAN_TSR_TME1_ofs EQU 27
CAN_TSR_TME1_len EQU 1
CAN_TSR_TME0 EQU 0x04000000 ; Lowest priority flag for mailbox 0
CAN_TSR_TME0_ofs EQU 26
CAN_TSR_TME0_len EQU 1
CAN_TSR_CODE EQU 0x03000000 ; CODE
CAN_TSR_CODE_ofs EQU 24
CAN_TSR_CODE_len EQU 2
CAN_TSR_ABRQ2 EQU 0x00800000 ; ABRQ2
CAN_TSR_ABRQ2_ofs EQU 23
CAN_TSR_ABRQ2_len EQU 1
CAN_TSR_TERR2 EQU 0x00080000 ; TERR2
CAN_TSR_TERR2_ofs EQU 19
CAN_TSR_TERR2_len EQU 1
CAN_TSR_ALST2 EQU 0x00040000 ; ALST2
CAN_TSR_ALST2_ofs EQU 18
CAN_TSR_ALST2_len EQU 1
CAN_TSR_TXOK2 EQU 0x00020000 ; TXOK2
CAN_TSR_TXOK2_ofs EQU 17
CAN_TSR_TXOK2_len EQU 1
CAN_TSR_RQCP2 EQU 0x00010000 ; RQCP2
CAN_TSR_RQCP2_ofs EQU 16
CAN_TSR_RQCP2_len EQU 1
CAN_TSR_ABRQ1 EQU 0x00008000 ; ABRQ1
CAN_TSR_ABRQ1_ofs EQU 15
CAN_TSR_ABRQ1_len EQU 1
CAN_TSR_TERR1 EQU 0x00000800 ; TERR1
CAN_TSR_TERR1_ofs EQU 11
CAN_TSR_TERR1_len EQU 1
CAN_TSR_ALST1 EQU 0x00000400 ; ALST1
CAN_TSR_ALST1_ofs EQU 10
CAN_TSR_ALST1_len EQU 1
CAN_TSR_TXOK1 EQU 0x00000200 ; TXOK1
CAN_TSR_TXOK1_ofs EQU 9
CAN_TSR_TXOK1_len EQU 1
CAN_TSR_RQCP1 EQU 0x00000100 ; RQCP1
CAN_TSR_RQCP1_ofs EQU 8
CAN_TSR_RQCP1_len EQU 1
CAN_TSR_ABRQ0 EQU 0x00000080 ; ABRQ0
CAN_TSR_ABRQ0_ofs EQU 7
CAN_TSR_ABRQ0_len EQU 1
CAN_TSR_TERR0 EQU 0x00000008 ; TERR0
CAN_TSR_TERR0_ofs EQU 3
CAN_TSR_TERR0_len EQU 1
CAN_TSR_ALST0 EQU 0x00000004 ; ALST0
CAN_TSR_ALST0_ofs EQU 2
CAN_TSR_ALST0_len EQU 1
CAN_TSR_TXOK0 EQU 0x00000002 ; TXOK0
CAN_TSR_TXOK0_ofs EQU 1
CAN_TSR_TXOK0_len EQU 1
CAN_TSR_RQCP0 EQU 0x00000001 ; RQCP0
CAN_TSR_RQCP0_ofs EQU 0
CAN_TSR_RQCP0_len EQU 1
; CAN_RF0R fields:
CAN_RF0R_RFOM0 EQU 0x00000020 ; RFOM0
CAN_RF0R_RFOM0_ofs EQU 5
CAN_RF0R_RFOM0_len EQU 1
CAN_RF0R_FOVR0 EQU 0x00000010 ; FOVR0
CAN_RF0R_FOVR0_ofs EQU 4
CAN_RF0R_FOVR0_len EQU 1
CAN_RF0R_FULL0 EQU 0x00000008 ; FULL0
CAN_RF0R_FULL0_ofs EQU 3
CAN_RF0R_FULL0_len EQU 1
CAN_RF0R_FMP0 EQU 0x00000003 ; FMP0
CAN_RF0R_FMP0_ofs EQU 0
CAN_RF0R_FMP0_len EQU 2
; CAN_RF1R fields:
CAN_RF1R_RFOM1 EQU 0x00000020 ; RFOM1
CAN_RF1R_RFOM1_ofs EQU 5
CAN_RF1R_RFOM1_len EQU 1
CAN_RF1R_FOVR1 EQU 0x00000010 ; FOVR1
CAN_RF1R_FOVR1_ofs EQU 4
CAN_RF1R_FOVR1_len EQU 1
CAN_RF1R_FULL1 EQU 0x00000008 ; FULL1
CAN_RF1R_FULL1_ofs EQU 3
CAN_RF1R_FULL1_len EQU 1
CAN_RF1R_FMP1 EQU 0x00000003 ; FMP1
CAN_RF1R_FMP1_ofs EQU 0
CAN_RF1R_FMP1_len EQU 2
; CAN_IER fields:
CAN_IER_SLKIE EQU 0x00020000 ; SLKIE
CAN_IER_SLKIE_ofs EQU 17
CAN_IER_SLKIE_len EQU 1
CAN_IER_WKUIE EQU 0x00010000 ; WKUIE
CAN_IER_WKUIE_ofs EQU 16
CAN_IER_WKUIE_len EQU 1
CAN_IER_ERRIE EQU 0x00008000 ; ERRIE
CAN_IER_ERRIE_ofs EQU 15
CAN_IER_ERRIE_len EQU 1
CAN_IER_LECIE EQU 0x00000800 ; LECIE
CAN_IER_LECIE_ofs EQU 11
CAN_IER_LECIE_len EQU 1
CAN_IER_BOFIE EQU 0x00000400 ; BOFIE
CAN_IER_BOFIE_ofs EQU 10
CAN_IER_BOFIE_len EQU 1
CAN_IER_EPVIE EQU 0x00000200 ; EPVIE
CAN_IER_EPVIE_ofs EQU 9
CAN_IER_EPVIE_len EQU 1
CAN_IER_EWGIE EQU 0x00000100 ; EWGIE
CAN_IER_EWGIE_ofs EQU 8
CAN_IER_EWGIE_len EQU 1
CAN_IER_FOVIE1 EQU 0x00000040 ; FOVIE1
CAN_IER_FOVIE1_ofs EQU 6
CAN_IER_FOVIE1_len EQU 1
CAN_IER_FFIE1 EQU 0x00000020 ; FFIE1
CAN_IER_FFIE1_ofs EQU 5
CAN_IER_FFIE1_len EQU 1
CAN_IER_FMPIE1 EQU 0x00000010 ; FMPIE1
CAN_IER_FMPIE1_ofs EQU 4
CAN_IER_FMPIE1_len EQU 1
CAN_IER_FOVIE0 EQU 0x00000008 ; FOVIE0
CAN_IER_FOVIE0_ofs EQU 3
CAN_IER_FOVIE0_len EQU 1
CAN_IER_FFIE0 EQU 0x00000004 ; FFIE0
CAN_IER_FFIE0_ofs EQU 2
CAN_IER_FFIE0_len EQU 1
CAN_IER_FMPIE0 EQU 0x00000002 ; FMPIE0
CAN_IER_FMPIE0_ofs EQU 1
CAN_IER_FMPIE0_len EQU 1
CAN_IER_TMEIE EQU 0x00000001 ; TMEIE
CAN_IER_TMEIE_ofs EQU 0
CAN_IER_TMEIE_len EQU 1
; CAN_ESR fields:
CAN_ESR_REC EQU 0xff000000 ; REC
CAN_ESR_REC_ofs EQU 24
CAN_ESR_REC_len EQU 8
CAN_ESR_TEC EQU 0x00ff0000 ; TEC
CAN_ESR_TEC_ofs EQU 16
CAN_ESR_TEC_len EQU 8
CAN_ESR_LEC EQU 0x00000070 ; LEC
CAN_ESR_LEC_ofs EQU 4
CAN_ESR_LEC_len EQU 3
CAN_ESR_BOFF EQU 0x00000004 ; BOFF
CAN_ESR_BOFF_ofs EQU 2
CAN_ESR_BOFF_len EQU 1
CAN_ESR_EPVF EQU 0x00000002 ; EPVF
CAN_ESR_EPVF_ofs EQU 1
CAN_ESR_EPVF_len EQU 1
CAN_ESR_EWGF EQU 0x00000001 ; EWGF
CAN_ESR_EWGF_ofs EQU 0
CAN_ESR_EWGF_len EQU 1
; CAN_BTR fields:
CAN_BTR_SILM EQU 0x80000000 ; SILM
CAN_BTR_SILM_ofs EQU 31
CAN_BTR_SILM_len EQU 1
CAN_BTR_LBKM EQU 0x40000000 ; LBKM
CAN_BTR_LBKM_ofs EQU 30
CAN_BTR_LBKM_len EQU 1
CAN_BTR_SJW EQU 0x03000000 ; SJW
CAN_BTR_SJW_ofs EQU 24
CAN_BTR_SJW_len EQU 2
CAN_BTR_TS2 EQU 0x00700000 ; TS2
CAN_BTR_TS2_ofs EQU 20
CAN_BTR_TS2_len EQU 3
CAN_BTR_TS1 EQU 0x000f0000 ; TS1
CAN_BTR_TS1_ofs EQU 16
CAN_BTR_TS1_len EQU 4
CAN_BTR_BRP EQU 0x000003ff ; BRP
CAN_BTR_BRP_ofs EQU 0
CAN_BTR_BRP_len EQU 10
; CAN_TI0R fields:
CAN_TI0R_STID EQU 0xffe00000 ; STID
CAN_TI0R_STID_ofs EQU 21
CAN_TI0R_STID_len EQU 11
CAN_TI0R_EXID EQU 0x001ffff8 ; EXID
CAN_TI0R_EXID_ofs EQU 3
CAN_TI0R_EXID_len EQU 18
CAN_TI0R_IDE EQU 0x00000004 ; IDE
CAN_TI0R_IDE_ofs EQU 2
CAN_TI0R_IDE_len EQU 1
CAN_TI0R_RTR EQU 0x00000002 ; RTR
CAN_TI0R_RTR_ofs EQU 1
CAN_TI0R_RTR_len EQU 1
CAN_TI0R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI0R_TXRQ_ofs EQU 0
CAN_TI0R_TXRQ_len EQU 1
; CAN_TDT0R fields:
CAN_TDT0R_TIME EQU 0xffff0000 ; TIME
CAN_TDT0R_TIME_ofs EQU 16
CAN_TDT0R_TIME_len EQU 16
CAN_TDT0R_TGT EQU 0x00000100 ; TGT
CAN_TDT0R_TGT_ofs EQU 8
CAN_TDT0R_TGT_len EQU 1
CAN_TDT0R_DLC EQU 0x0000000f ; DLC
CAN_TDT0R_DLC_ofs EQU 0
CAN_TDT0R_DLC_len EQU 4
; CAN_TDL0R fields:
CAN_TDL0R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL0R_DATA3_ofs EQU 24
CAN_TDL0R_DATA3_len EQU 8
CAN_TDL0R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL0R_DATA2_ofs EQU 16
CAN_TDL0R_DATA2_len EQU 8
CAN_TDL0R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL0R_DATA1_ofs EQU 8
CAN_TDL0R_DATA1_len EQU 8
CAN_TDL0R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL0R_DATA0_ofs EQU 0
CAN_TDL0R_DATA0_len EQU 8
; CAN_TDH0R fields:
CAN_TDH0R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH0R_DATA7_ofs EQU 24
CAN_TDH0R_DATA7_len EQU 8
CAN_TDH0R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH0R_DATA6_ofs EQU 16
CAN_TDH0R_DATA6_len EQU 8
CAN_TDH0R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH0R_DATA5_ofs EQU 8
CAN_TDH0R_DATA5_len EQU 8
CAN_TDH0R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH0R_DATA4_ofs EQU 0
CAN_TDH0R_DATA4_len EQU 8
; CAN_TI1R fields:
CAN_TI1R_STID EQU 0xffe00000 ; STID
CAN_TI1R_STID_ofs EQU 21
CAN_TI1R_STID_len EQU 11
CAN_TI1R_EXID EQU 0x001ffff8 ; EXID
CAN_TI1R_EXID_ofs EQU 3
CAN_TI1R_EXID_len EQU 18
CAN_TI1R_IDE EQU 0x00000004 ; IDE
CAN_TI1R_IDE_ofs EQU 2
CAN_TI1R_IDE_len EQU 1
CAN_TI1R_RTR EQU 0x00000002 ; RTR
CAN_TI1R_RTR_ofs EQU 1
CAN_TI1R_RTR_len EQU 1
CAN_TI1R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI1R_TXRQ_ofs EQU 0
CAN_TI1R_TXRQ_len EQU 1
; CAN_TDT1R fields:
CAN_TDT1R_TIME EQU 0xffff0000 ; TIME
CAN_TDT1R_TIME_ofs EQU 16
CAN_TDT1R_TIME_len EQU 16
CAN_TDT1R_TGT EQU 0x00000100 ; TGT
CAN_TDT1R_TGT_ofs EQU 8
CAN_TDT1R_TGT_len EQU 1
CAN_TDT1R_DLC EQU 0x0000000f ; DLC
CAN_TDT1R_DLC_ofs EQU 0
CAN_TDT1R_DLC_len EQU 4
; CAN_TDL1R fields:
CAN_TDL1R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL1R_DATA3_ofs EQU 24
CAN_TDL1R_DATA3_len EQU 8
CAN_TDL1R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL1R_DATA2_ofs EQU 16
CAN_TDL1R_DATA2_len EQU 8
CAN_TDL1R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL1R_DATA1_ofs EQU 8
CAN_TDL1R_DATA1_len EQU 8
CAN_TDL1R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL1R_DATA0_ofs EQU 0
CAN_TDL1R_DATA0_len EQU 8
; CAN_TDH1R fields:
CAN_TDH1R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH1R_DATA7_ofs EQU 24
CAN_TDH1R_DATA7_len EQU 8
CAN_TDH1R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH1R_DATA6_ofs EQU 16
CAN_TDH1R_DATA6_len EQU 8
CAN_TDH1R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH1R_DATA5_ofs EQU 8
CAN_TDH1R_DATA5_len EQU 8
CAN_TDH1R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH1R_DATA4_ofs EQU 0
CAN_TDH1R_DATA4_len EQU 8
; CAN_TI2R fields:
CAN_TI2R_STID EQU 0xffe00000 ; STID
CAN_TI2R_STID_ofs EQU 21
CAN_TI2R_STID_len EQU 11
CAN_TI2R_EXID EQU 0x001ffff8 ; EXID
CAN_TI2R_EXID_ofs EQU 3
CAN_TI2R_EXID_len EQU 18
CAN_TI2R_IDE EQU 0x00000004 ; IDE
CAN_TI2R_IDE_ofs EQU 2
CAN_TI2R_IDE_len EQU 1
CAN_TI2R_RTR EQU 0x00000002 ; RTR
CAN_TI2R_RTR_ofs EQU 1
CAN_TI2R_RTR_len EQU 1
CAN_TI2R_TXRQ EQU 0x00000001 ; TXRQ
CAN_TI2R_TXRQ_ofs EQU 0
CAN_TI2R_TXRQ_len EQU 1
; CAN_TDT2R fields:
CAN_TDT2R_TIME EQU 0xffff0000 ; TIME
CAN_TDT2R_TIME_ofs EQU 16
CAN_TDT2R_TIME_len EQU 16
CAN_TDT2R_TGT EQU 0x00000100 ; TGT
CAN_TDT2R_TGT_ofs EQU 8
CAN_TDT2R_TGT_len EQU 1
CAN_TDT2R_DLC EQU 0x0000000f ; DLC
CAN_TDT2R_DLC_ofs EQU 0
CAN_TDT2R_DLC_len EQU 4
; CAN_TDL2R fields:
CAN_TDL2R_DATA3 EQU 0xff000000 ; DATA3
CAN_TDL2R_DATA3_ofs EQU 24
CAN_TDL2R_DATA3_len EQU 8
CAN_TDL2R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_TDL2R_DATA2_ofs EQU 16
CAN_TDL2R_DATA2_len EQU 8
CAN_TDL2R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_TDL2R_DATA1_ofs EQU 8
CAN_TDL2R_DATA1_len EQU 8
CAN_TDL2R_DATA0 EQU 0x000000ff ; DATA0
CAN_TDL2R_DATA0_ofs EQU 0
CAN_TDL2R_DATA0_len EQU 8
; CAN_TDH2R fields:
CAN_TDH2R_DATA7 EQU 0xff000000 ; DATA7
CAN_TDH2R_DATA7_ofs EQU 24
CAN_TDH2R_DATA7_len EQU 8
CAN_TDH2R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_TDH2R_DATA6_ofs EQU 16
CAN_TDH2R_DATA6_len EQU 8
CAN_TDH2R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_TDH2R_DATA5_ofs EQU 8
CAN_TDH2R_DATA5_len EQU 8
CAN_TDH2R_DATA4 EQU 0x000000ff ; DATA4
CAN_TDH2R_DATA4_ofs EQU 0
CAN_TDH2R_DATA4_len EQU 8
; CAN_RI0R fields:
CAN_RI0R_STID EQU 0xffe00000 ; STID
CAN_RI0R_STID_ofs EQU 21
CAN_RI0R_STID_len EQU 11
CAN_RI0R_EXID EQU 0x001ffff8 ; EXID
CAN_RI0R_EXID_ofs EQU 3
CAN_RI0R_EXID_len EQU 18
CAN_RI0R_IDE EQU 0x00000004 ; IDE
CAN_RI0R_IDE_ofs EQU 2
CAN_RI0R_IDE_len EQU 1
CAN_RI0R_RTR EQU 0x00000002 ; RTR
CAN_RI0R_RTR_ofs EQU 1
CAN_RI0R_RTR_len EQU 1
; CAN_RDT0R fields:
CAN_RDT0R_TIME EQU 0xffff0000 ; TIME
CAN_RDT0R_TIME_ofs EQU 16
CAN_RDT0R_TIME_len EQU 16
CAN_RDT0R_FMI EQU 0x0000ff00 ; FMI
CAN_RDT0R_FMI_ofs EQU 8
CAN_RDT0R_FMI_len EQU 8
CAN_RDT0R_DLC EQU 0x0000000f ; DLC
CAN_RDT0R_DLC_ofs EQU 0
CAN_RDT0R_DLC_len EQU 4
; CAN_RDL0R fields:
CAN_RDL0R_DATA3 EQU 0xff000000 ; DATA3
CAN_RDL0R_DATA3_ofs EQU 24
CAN_RDL0R_DATA3_len EQU 8
CAN_RDL0R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_RDL0R_DATA2_ofs EQU 16
CAN_RDL0R_DATA2_len EQU 8
CAN_RDL0R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_RDL0R_DATA1_ofs EQU 8
CAN_RDL0R_DATA1_len EQU 8
CAN_RDL0R_DATA0 EQU 0x000000ff ; DATA0
CAN_RDL0R_DATA0_ofs EQU 0
CAN_RDL0R_DATA0_len EQU 8
; CAN_RDH0R fields:
CAN_RDH0R_DATA7 EQU 0xff000000 ; DATA7
CAN_RDH0R_DATA7_ofs EQU 24
CAN_RDH0R_DATA7_len EQU 8
CAN_RDH0R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_RDH0R_DATA6_ofs EQU 16
CAN_RDH0R_DATA6_len EQU 8
CAN_RDH0R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_RDH0R_DATA5_ofs EQU 8
CAN_RDH0R_DATA5_len EQU 8
CAN_RDH0R_DATA4 EQU 0x000000ff ; DATA4
CAN_RDH0R_DATA4_ofs EQU 0
CAN_RDH0R_DATA4_len EQU 8
; CAN_RI1R fields:
CAN_RI1R_STID EQU 0xffe00000 ; STID
CAN_RI1R_STID_ofs EQU 21
CAN_RI1R_STID_len EQU 11
CAN_RI1R_EXID EQU 0x001ffff8 ; EXID
CAN_RI1R_EXID_ofs EQU 3
CAN_RI1R_EXID_len EQU 18
CAN_RI1R_IDE EQU 0x00000004 ; IDE
CAN_RI1R_IDE_ofs EQU 2
CAN_RI1R_IDE_len EQU 1
CAN_RI1R_RTR EQU 0x00000002 ; RTR
CAN_RI1R_RTR_ofs EQU 1
CAN_RI1R_RTR_len EQU 1
; CAN_RDT1R fields:
CAN_RDT1R_TIME EQU 0xffff0000 ; TIME
CAN_RDT1R_TIME_ofs EQU 16
CAN_RDT1R_TIME_len EQU 16
CAN_RDT1R_FMI EQU 0x0000ff00 ; FMI
CAN_RDT1R_FMI_ofs EQU 8
CAN_RDT1R_FMI_len EQU 8
CAN_RDT1R_DLC EQU 0x0000000f ; DLC
CAN_RDT1R_DLC_ofs EQU 0
CAN_RDT1R_DLC_len EQU 4
; CAN_RDL1R fields:
CAN_RDL1R_DATA3 EQU 0xff000000 ; DATA3
CAN_RDL1R_DATA3_ofs EQU 24
CAN_RDL1R_DATA3_len EQU 8
CAN_RDL1R_DATA2 EQU 0x00ff0000 ; DATA2
CAN_RDL1R_DATA2_ofs EQU 16
CAN_RDL1R_DATA2_len EQU 8
CAN_RDL1R_DATA1 EQU 0x0000ff00 ; DATA1
CAN_RDL1R_DATA1_ofs EQU 8
CAN_RDL1R_DATA1_len EQU 8
CAN_RDL1R_DATA0 EQU 0x000000ff ; DATA0
CAN_RDL1R_DATA0_ofs EQU 0
CAN_RDL1R_DATA0_len EQU 8
; CAN_RDH1R fields:
CAN_RDH1R_DATA7 EQU 0xff000000 ; DATA7
CAN_RDH1R_DATA7_ofs EQU 24
CAN_RDH1R_DATA7_len EQU 8
CAN_RDH1R_DATA6 EQU 0x00ff0000 ; DATA6
CAN_RDH1R_DATA6_ofs EQU 16
CAN_RDH1R_DATA6_len EQU 8
CAN_RDH1R_DATA5 EQU 0x0000ff00 ; DATA5
CAN_RDH1R_DATA5_ofs EQU 8
CAN_RDH1R_DATA5_len EQU 8
CAN_RDH1R_DATA4 EQU 0x000000ff ; DATA4
CAN_RDH1R_DATA4_ofs EQU 0
CAN_RDH1R_DATA4_len EQU 8
; CAN_FMR fields:
CAN_FMR_CAN2SB EQU 0x00003f00 ; CAN2 start bank
CAN_FMR_CAN2SB_ofs EQU 8
CAN_FMR_CAN2SB_len EQU 6
CAN_FMR_FINIT EQU 0x00000001 ; Filter init mode
CAN_FMR_FINIT_ofs EQU 0
CAN_FMR_FINIT_len EQU 1
; CAN_FM1R fields:
CAN_FM1R_FBM0 EQU 0x00000001 ; Filter mode
CAN_FM1R_FBM0_ofs EQU 0
CAN_FM1R_FBM0_len EQU 1
CAN_FM1R_FBM1 EQU 0x00000002 ; Filter mode
CAN_FM1R_FBM1_ofs EQU 1
CAN_FM1R_FBM1_len EQU 1
CAN_FM1R_FBM2 EQU 0x00000004 ; Filter mode
CAN_FM1R_FBM2_ofs EQU 2
CAN_FM1R_FBM2_len EQU 1
CAN_FM1R_FBM3 EQU 0x00000008 ; Filter mode
CAN_FM1R_FBM3_ofs EQU 3
CAN_FM1R_FBM3_len EQU 1
CAN_FM1R_FBM4 EQU 0x00000010 ; Filter mode
CAN_FM1R_FBM4_ofs EQU 4
CAN_FM1R_FBM4_len EQU 1
CAN_FM1R_FBM5 EQU 0x00000020 ; Filter mode
CAN_FM1R_FBM5_ofs EQU 5
CAN_FM1R_FBM5_len EQU 1
CAN_FM1R_FBM6 EQU 0x00000040 ; Filter mode
CAN_FM1R_FBM6_ofs EQU 6
CAN_FM1R_FBM6_len EQU 1
CAN_FM1R_FBM7 EQU 0x00000080 ; Filter mode
CAN_FM1R_FBM7_ofs EQU 7
CAN_FM1R_FBM7_len EQU 1
CAN_FM1R_FBM8 EQU 0x00000100 ; Filter mode
CAN_FM1R_FBM8_ofs EQU 8
CAN_FM1R_FBM8_len EQU 1
CAN_FM1R_FBM9 EQU 0x00000200 ; Filter mode
CAN_FM1R_FBM9_ofs EQU 9
CAN_FM1R_FBM9_len EQU 1
CAN_FM1R_FBM10 EQU 0x00000400 ; Filter mode
CAN_FM1R_FBM10_ofs EQU 10
CAN_FM1R_FBM10_len EQU 1
CAN_FM1R_FBM11 EQU 0x00000800 ; Filter mode
CAN_FM1R_FBM11_ofs EQU 11
CAN_FM1R_FBM11_len EQU 1
CAN_FM1R_FBM12 EQU 0x00001000 ; Filter mode
CAN_FM1R_FBM12_ofs EQU 12
CAN_FM1R_FBM12_len EQU 1
CAN_FM1R_FBM13 EQU 0x00002000 ; Filter mode
CAN_FM1R_FBM13_ofs EQU 13
CAN_FM1R_FBM13_len EQU 1
CAN_FM1R_FBM14 EQU 0x00004000 ; Filter mode
CAN_FM1R_FBM14_ofs EQU 14
CAN_FM1R_FBM14_len EQU 1
CAN_FM1R_FBM15 EQU 0x00008000 ; Filter mode
CAN_FM1R_FBM15_ofs EQU 15
CAN_FM1R_FBM15_len EQU 1
CAN_FM1R_FBM16 EQU 0x00010000 ; Filter mode
CAN_FM1R_FBM16_ofs EQU 16
CAN_FM1R_FBM16_len EQU 1
CAN_FM1R_FBM17 EQU 0x00020000 ; Filter mode
CAN_FM1R_FBM17_ofs EQU 17
CAN_FM1R_FBM17_len EQU 1
CAN_FM1R_FBM18 EQU 0x00040000 ; Filter mode
CAN_FM1R_FBM18_ofs EQU 18
CAN_FM1R_FBM18_len EQU 1
CAN_FM1R_FBM19 EQU 0x00080000 ; Filter mode
CAN_FM1R_FBM19_ofs EQU 19
CAN_FM1R_FBM19_len EQU 1
CAN_FM1R_FBM20 EQU 0x00100000 ; Filter mode
CAN_FM1R_FBM20_ofs EQU 20
CAN_FM1R_FBM20_len EQU 1
CAN_FM1R_FBM21 EQU 0x00200000 ; Filter mode
CAN_FM1R_FBM21_ofs EQU 21
CAN_FM1R_FBM21_len EQU 1
CAN_FM1R_FBM22 EQU 0x00400000 ; Filter mode
CAN_FM1R_FBM22_ofs EQU 22
CAN_FM1R_FBM22_len EQU 1
CAN_FM1R_FBM23 EQU 0x00800000 ; Filter mode
CAN_FM1R_FBM23_ofs EQU 23
CAN_FM1R_FBM23_len EQU 1
CAN_FM1R_FBM24 EQU 0x01000000 ; Filter mode
CAN_FM1R_FBM24_ofs EQU 24
CAN_FM1R_FBM24_len EQU 1
CAN_FM1R_FBM25 EQU 0x02000000 ; Filter mode
CAN_FM1R_FBM25_ofs EQU 25
CAN_FM1R_FBM25_len EQU 1
CAN_FM1R_FBM26 EQU 0x04000000 ; Filter mode
CAN_FM1R_FBM26_ofs EQU 26
CAN_FM1R_FBM26_len EQU 1
CAN_FM1R_FBM27 EQU 0x08000000 ; Filter mode
CAN_FM1R_FBM27_ofs EQU 27
CAN_FM1R_FBM27_len EQU 1
; CAN_FS1R fields:
CAN_FS1R_FSC0 EQU 0x00000001 ; Filter scale configuration
CAN_FS1R_FSC0_ofs EQU 0
CAN_FS1R_FSC0_len EQU 1
CAN_FS1R_FSC1 EQU 0x00000002 ; Filter scale configuration
CAN_FS1R_FSC1_ofs EQU 1
CAN_FS1R_FSC1_len EQU 1
CAN_FS1R_FSC2 EQU 0x00000004 ; Filter scale configuration
CAN_FS1R_FSC2_ofs EQU 2
CAN_FS1R_FSC2_len EQU 1
CAN_FS1R_FSC3 EQU 0x00000008 ; Filter scale configuration
CAN_FS1R_FSC3_ofs EQU 3
CAN_FS1R_FSC3_len EQU 1
CAN_FS1R_FSC4 EQU 0x00000010 ; Filter scale configuration
CAN_FS1R_FSC4_ofs EQU 4
CAN_FS1R_FSC4_len EQU 1
CAN_FS1R_FSC5 EQU 0x00000020 ; Filter scale configuration
CAN_FS1R_FSC5_ofs EQU 5
CAN_FS1R_FSC5_len EQU 1
CAN_FS1R_FSC6 EQU 0x00000040 ; Filter scale configuration
CAN_FS1R_FSC6_ofs EQU 6
CAN_FS1R_FSC6_len EQU 1
CAN_FS1R_FSC7 EQU 0x00000080 ; Filter scale configuration
CAN_FS1R_FSC7_ofs EQU 7
CAN_FS1R_FSC7_len EQU 1
CAN_FS1R_FSC8 EQU 0x00000100 ; Filter scale configuration
CAN_FS1R_FSC8_ofs EQU 8
CAN_FS1R_FSC8_len EQU 1
CAN_FS1R_FSC9 EQU 0x00000200 ; Filter scale configuration
CAN_FS1R_FSC9_ofs EQU 9
CAN_FS1R_FSC9_len EQU 1
CAN_FS1R_FSC10 EQU 0x00000400 ; Filter scale configuration
CAN_FS1R_FSC10_ofs EQU 10
CAN_FS1R_FSC10_len EQU 1
CAN_FS1R_FSC11 EQU 0x00000800 ; Filter scale configuration
CAN_FS1R_FSC11_ofs EQU 11
CAN_FS1R_FSC11_len EQU 1
CAN_FS1R_FSC12 EQU 0x00001000 ; Filter scale configuration
CAN_FS1R_FSC12_ofs EQU 12
CAN_FS1R_FSC12_len EQU 1
CAN_FS1R_FSC13 EQU 0x00002000 ; Filter scale configuration
CAN_FS1R_FSC13_ofs EQU 13
CAN_FS1R_FSC13_len EQU 1
CAN_FS1R_FSC14 EQU 0x00004000 ; Filter scale configuration
CAN_FS1R_FSC14_ofs EQU 14
CAN_FS1R_FSC14_len EQU 1
CAN_FS1R_FSC15 EQU 0x00008000 ; Filter scale configuration
CAN_FS1R_FSC15_ofs EQU 15
CAN_FS1R_FSC15_len EQU 1
CAN_FS1R_FSC16 EQU 0x00010000 ; Filter scale configuration
CAN_FS1R_FSC16_ofs EQU 16
CAN_FS1R_FSC16_len EQU 1
CAN_FS1R_FSC17 EQU 0x00020000 ; Filter scale configuration
CAN_FS1R_FSC17_ofs EQU 17
CAN_FS1R_FSC17_len EQU 1
CAN_FS1R_FSC18 EQU 0x00040000 ; Filter scale configuration
CAN_FS1R_FSC18_ofs EQU 18
CAN_FS1R_FSC18_len EQU 1
CAN_FS1R_FSC19 EQU 0x00080000 ; Filter scale configuration
CAN_FS1R_FSC19_ofs EQU 19
CAN_FS1R_FSC19_len EQU 1
CAN_FS1R_FSC20 EQU 0x00100000 ; Filter scale configuration
CAN_FS1R_FSC20_ofs EQU 20
CAN_FS1R_FSC20_len EQU 1
CAN_FS1R_FSC21 EQU 0x00200000 ; Filter scale configuration
CAN_FS1R_FSC21_ofs EQU 21
CAN_FS1R_FSC21_len EQU 1
CAN_FS1R_FSC22 EQU 0x00400000 ; Filter scale configuration
CAN_FS1R_FSC22_ofs EQU 22
CAN_FS1R_FSC22_len EQU 1
CAN_FS1R_FSC23 EQU 0x00800000 ; Filter scale configuration
CAN_FS1R_FSC23_ofs EQU 23
CAN_FS1R_FSC23_len EQU 1
CAN_FS1R_FSC24 EQU 0x01000000 ; Filter scale configuration
CAN_FS1R_FSC24_ofs EQU 24
CAN_FS1R_FSC24_len EQU 1
CAN_FS1R_FSC25 EQU 0x02000000 ; Filter scale configuration
CAN_FS1R_FSC25_ofs EQU 25
CAN_FS1R_FSC25_len EQU 1
CAN_FS1R_FSC26 EQU 0x04000000 ; Filter scale configuration
CAN_FS1R_FSC26_ofs EQU 26
CAN_FS1R_FSC26_len EQU 1
CAN_FS1R_FSC27 EQU 0x08000000 ; Filter scale configuration
CAN_FS1R_FSC27_ofs EQU 27
CAN_FS1R_FSC27_len EQU 1
; CAN_FFA1R fields:
CAN_FFA1R_FFA0 EQU 0x00000001 ; Filter FIFO assignment for filter 0
CAN_FFA1R_FFA0_ofs EQU 0
CAN_FFA1R_FFA0_len EQU 1
CAN_FFA1R_FFA1 EQU 0x00000002 ; Filter FIFO assignment for filter 1
CAN_FFA1R_FFA1_ofs EQU 1
CAN_FFA1R_FFA1_len EQU 1
CAN_FFA1R_FFA2 EQU 0x00000004 ; Filter FIFO assignment for filter 2
CAN_FFA1R_FFA2_ofs EQU 2
CAN_FFA1R_FFA2_len EQU 1
CAN_FFA1R_FFA3 EQU 0x00000008 ; Filter FIFO assignment for filter 3
CAN_FFA1R_FFA3_ofs EQU 3
CAN_FFA1R_FFA3_len EQU 1
CAN_FFA1R_FFA4 EQU 0x00000010 ; Filter FIFO assignment for filter 4
CAN_FFA1R_FFA4_ofs EQU 4
CAN_FFA1R_FFA4_len EQU 1
CAN_FFA1R_FFA5 EQU 0x00000020 ; Filter FIFO assignment for filter 5
CAN_FFA1R_FFA5_ofs EQU 5
CAN_FFA1R_FFA5_len EQU 1
CAN_FFA1R_FFA6 EQU 0x00000040 ; Filter FIFO assignment for filter 6
CAN_FFA1R_FFA6_ofs EQU 6
CAN_FFA1R_FFA6_len EQU 1
CAN_FFA1R_FFA7 EQU 0x00000080 ; Filter FIFO assignment for filter 7
CAN_FFA1R_FFA7_ofs EQU 7
CAN_FFA1R_FFA7_len EQU 1
CAN_FFA1R_FFA8 EQU 0x00000100 ; Filter FIFO assignment for filter 8
CAN_FFA1R_FFA8_ofs EQU 8
CAN_FFA1R_FFA8_len EQU 1
CAN_FFA1R_FFA9 EQU 0x00000200 ; Filter FIFO assignment for filter 9
CAN_FFA1R_FFA9_ofs EQU 9
CAN_FFA1R_FFA9_len EQU 1
CAN_FFA1R_FFA10 EQU 0x00000400 ; Filter FIFO assignment for filter 10
CAN_FFA1R_FFA10_ofs EQU 10
CAN_FFA1R_FFA10_len EQU 1
CAN_FFA1R_FFA11 EQU 0x00000800 ; Filter FIFO assignment for filter 11
CAN_FFA1R_FFA11_ofs EQU 11
CAN_FFA1R_FFA11_len EQU 1
CAN_FFA1R_FFA12 EQU 0x00001000 ; Filter FIFO assignment for filter 12
CAN_FFA1R_FFA12_ofs EQU 12
CAN_FFA1R_FFA12_len EQU 1
CAN_FFA1R_FFA13 EQU 0x00002000 ; Filter FIFO assignment for filter 13
CAN_FFA1R_FFA13_ofs EQU 13
CAN_FFA1R_FFA13_len EQU 1
CAN_FFA1R_FFA14 EQU 0x00004000 ; Filter FIFO assignment for filter 14
CAN_FFA1R_FFA14_ofs EQU 14
CAN_FFA1R_FFA14_len EQU 1
CAN_FFA1R_FFA15 EQU 0x00008000 ; Filter FIFO assignment for filter 15
CAN_FFA1R_FFA15_ofs EQU 15
CAN_FFA1R_FFA15_len EQU 1
CAN_FFA1R_FFA16 EQU 0x00010000 ; Filter FIFO assignment for filter 16
CAN_FFA1R_FFA16_ofs EQU 16
CAN_FFA1R_FFA16_len EQU 1
CAN_FFA1R_FFA17 EQU 0x00020000 ; Filter FIFO assignment for filter 17
CAN_FFA1R_FFA17_ofs EQU 17
CAN_FFA1R_FFA17_len EQU 1
CAN_FFA1R_FFA18 EQU 0x00040000 ; Filter FIFO assignment for filter 18
CAN_FFA1R_FFA18_ofs EQU 18
CAN_FFA1R_FFA18_len EQU 1
CAN_FFA1R_FFA19 EQU 0x00080000 ; Filter FIFO assignment for filter 19
CAN_FFA1R_FFA19_ofs EQU 19
CAN_FFA1R_FFA19_len EQU 1
CAN_FFA1R_FFA20 EQU 0x00100000 ; Filter FIFO assignment for filter 20
CAN_FFA1R_FFA20_ofs EQU 20
CAN_FFA1R_FFA20_len EQU 1
CAN_FFA1R_FFA21 EQU 0x00200000 ; Filter FIFO assignment for filter 21
CAN_FFA1R_FFA21_ofs EQU 21
CAN_FFA1R_FFA21_len EQU 1
CAN_FFA1R_FFA22 EQU 0x00400000 ; Filter FIFO assignment for filter 22
CAN_FFA1R_FFA22_ofs EQU 22
CAN_FFA1R_FFA22_len EQU 1
CAN_FFA1R_FFA23 EQU 0x00800000 ; Filter FIFO assignment for filter 23
CAN_FFA1R_FFA23_ofs EQU 23
CAN_FFA1R_FFA23_len EQU 1
CAN_FFA1R_FFA24 EQU 0x01000000 ; Filter FIFO assignment for filter 24
CAN_FFA1R_FFA24_ofs EQU 24
CAN_FFA1R_FFA24_len EQU 1
CAN_FFA1R_FFA25 EQU 0x02000000 ; Filter FIFO assignment for filter 25
CAN_FFA1R_FFA25_ofs EQU 25
CAN_FFA1R_FFA25_len EQU 1
CAN_FFA1R_FFA26 EQU 0x04000000 ; Filter FIFO assignment for filter 26
CAN_FFA1R_FFA26_ofs EQU 26
CAN_FFA1R_FFA26_len EQU 1
CAN_FFA1R_FFA27 EQU 0x08000000 ; Filter FIFO assignment for filter 27
CAN_FFA1R_FFA27_ofs EQU 27
CAN_FFA1R_FFA27_len EQU 1
; CAN_FA1R fields:
CAN_FA1R_FACT0 EQU 0x00000001 ; Filter active
CAN_FA1R_FACT0_ofs EQU 0
CAN_FA1R_FACT0_len EQU 1
CAN_FA1R_FACT1 EQU 0x00000002 ; Filter active
CAN_FA1R_FACT1_ofs EQU 1
CAN_FA1R_FACT1_len EQU 1
CAN_FA1R_FACT2 EQU 0x00000004 ; Filter active
CAN_FA1R_FACT2_ofs EQU 2
CAN_FA1R_FACT2_len EQU 1
CAN_FA1R_FACT3 EQU 0x00000008 ; Filter active
CAN_FA1R_FACT3_ofs EQU 3
CAN_FA1R_FACT3_len EQU 1
CAN_FA1R_FACT4 EQU 0x00000010 ; Filter active
CAN_FA1R_FACT4_ofs EQU 4
CAN_FA1R_FACT4_len EQU 1
CAN_FA1R_FACT5 EQU 0x00000020 ; Filter active
CAN_FA1R_FACT5_ofs EQU 5
CAN_FA1R_FACT5_len EQU 1
CAN_FA1R_FACT6 EQU 0x00000040 ; Filter active
CAN_FA1R_FACT6_ofs EQU 6
CAN_FA1R_FACT6_len EQU 1
CAN_FA1R_FACT7 EQU 0x00000080 ; Filter active
CAN_FA1R_FACT7_ofs EQU 7
CAN_FA1R_FACT7_len EQU 1
CAN_FA1R_FACT8 EQU 0x00000100 ; Filter active
CAN_FA1R_FACT8_ofs EQU 8
CAN_FA1R_FACT8_len EQU 1
CAN_FA1R_FACT9 EQU 0x00000200 ; Filter active
CAN_FA1R_FACT9_ofs EQU 9
CAN_FA1R_FACT9_len EQU 1
CAN_FA1R_FACT10 EQU 0x00000400 ; Filter active
CAN_FA1R_FACT10_ofs EQU 10
CAN_FA1R_FACT10_len EQU 1
CAN_FA1R_FACT11 EQU 0x00000800 ; Filter active
CAN_FA1R_FACT11_ofs EQU 11
CAN_FA1R_FACT11_len EQU 1
CAN_FA1R_FACT12 EQU 0x00001000 ; Filter active
CAN_FA1R_FACT12_ofs EQU 12
CAN_FA1R_FACT12_len EQU 1
CAN_FA1R_FACT13 EQU 0x00002000 ; Filter active
CAN_FA1R_FACT13_ofs EQU 13
CAN_FA1R_FACT13_len EQU 1
CAN_FA1R_FACT14 EQU 0x00004000 ; Filter active
CAN_FA1R_FACT14_ofs EQU 14
CAN_FA1R_FACT14_len EQU 1
CAN_FA1R_FACT15 EQU 0x00008000 ; Filter active
CAN_FA1R_FACT15_ofs EQU 15
CAN_FA1R_FACT15_len EQU 1
CAN_FA1R_FACT16 EQU 0x00010000 ; Filter active
CAN_FA1R_FACT16_ofs EQU 16
CAN_FA1R_FACT16_len EQU 1
CAN_FA1R_FACT17 EQU 0x00020000 ; Filter active
CAN_FA1R_FACT17_ofs EQU 17
CAN_FA1R_FACT17_len EQU 1
CAN_FA1R_FACT18 EQU 0x00040000 ; Filter active
CAN_FA1R_FACT18_ofs EQU 18
CAN_FA1R_FACT18_len EQU 1
CAN_FA1R_FACT19 EQU 0x00080000 ; Filter active
CAN_FA1R_FACT19_ofs EQU 19
CAN_FA1R_FACT19_len EQU 1
CAN_FA1R_FACT20 EQU 0x00100000 ; Filter active
CAN_FA1R_FACT20_ofs EQU 20
CAN_FA1R_FACT20_len EQU 1
CAN_FA1R_FACT21 EQU 0x00200000 ; Filter active
CAN_FA1R_FACT21_ofs EQU 21
CAN_FA1R_FACT21_len EQU 1
CAN_FA1R_FACT22 EQU 0x00400000 ; Filter active
CAN_FA1R_FACT22_ofs EQU 22
CAN_FA1R_FACT22_len EQU 1
CAN_FA1R_FACT23 EQU 0x00800000 ; Filter active
CAN_FA1R_FACT23_ofs EQU 23
CAN_FA1R_FACT23_len EQU 1
CAN_FA1R_FACT24 EQU 0x01000000 ; Filter active
CAN_FA1R_FACT24_ofs EQU 24
CAN_FA1R_FACT24_len EQU 1
CAN_FA1R_FACT25 EQU 0x02000000 ; Filter active
CAN_FA1R_FACT25_ofs EQU 25
CAN_FA1R_FACT25_len EQU 1
CAN_FA1R_FACT26 EQU 0x04000000 ; Filter active
CAN_FA1R_FACT26_ofs EQU 26
CAN_FA1R_FACT26_len EQU 1
CAN_FA1R_FACT27 EQU 0x08000000 ; Filter active
CAN_FA1R_FACT27_ofs EQU 27
CAN_FA1R_FACT27_len EQU 1
; CAN_F0R1 fields:
CAN_F0R1_FB0 EQU 0x00000001 ; Filter bits
CAN_F0R1_FB0_ofs EQU 0
CAN_F0R1_FB0_len EQU 1
CAN_F0R1_FB1 EQU 0x00000002 ; Filter bits
CAN_F0R1_FB1_ofs EQU 1
CAN_F0R1_FB1_len EQU 1
CAN_F0R1_FB2 EQU 0x00000004 ; Filter bits
CAN_F0R1_FB2_ofs EQU 2
CAN_F0R1_FB2_len EQU 1
CAN_F0R1_FB3 EQU 0x00000008 ; Filter bits
CAN_F0R1_FB3_ofs EQU 3
CAN_F0R1_FB3_len EQU 1
CAN_F0R1_FB4 EQU 0x00000010 ; Filter bits
CAN_F0R1_FB4_ofs EQU 4
CAN_F0R1_FB4_len EQU 1
CAN_F0R1_FB5 EQU 0x00000020 ; Filter bits
CAN_F0R1_FB5_ofs EQU 5
CAN_F0R1_FB5_len EQU 1
CAN_F0R1_FB6 EQU 0x00000040 ; Filter bits
CAN_F0R1_FB6_ofs EQU 6
CAN_F0R1_FB6_len EQU 1
CAN_F0R1_FB7 EQU 0x00000080 ; Filter bits
CAN_F0R1_FB7_ofs EQU 7
CAN_F0R1_FB7_len EQU 1
CAN_F0R1_FB8 EQU 0x00000100 ; Filter bits
CAN_F0R1_FB8_ofs EQU 8
CAN_F0R1_FB8_len EQU 1
CAN_F0R1_FB9 EQU 0x00000200 ; Filter bits
CAN_F0R1_FB9_ofs EQU 9
CAN_F0R1_FB9_len EQU 1
CAN_F0R1_FB10 EQU 0x00000400 ; Filter bits
CAN_F0R1_FB10_ofs EQU 10
CAN_F0R1_FB10_len EQU 1
CAN_F0R1_FB11 EQU 0x00000800 ; Filter bits
CAN_F0R1_FB11_ofs EQU 11
CAN_F0R1_FB11_len EQU 1
CAN_F0R1_FB12 EQU 0x00001000 ; Filter bits
CAN_F0R1_FB12_ofs EQU 12
CAN_F0R1_FB12_len EQU 1
CAN_F0R1_FB13 EQU 0x00002000 ; Filter bits
CAN_F0R1_FB13_ofs EQU 13
CAN_F0R1_FB13_len EQU 1
CAN_F0R1_FB14 EQU 0x00004000 ; Filter bits
CAN_F0R1_FB14_ofs EQU 14
CAN_F0R1_FB14_len EQU 1
CAN_F0R1_FB15 EQU 0x00008000 ; Filter bits
CAN_F0R1_FB15_ofs EQU 15
CAN_F0R1_FB15_len EQU 1
CAN_F0R1_FB16 EQU 0x00010000 ; Filter bits
CAN_F0R1_FB16_ofs EQU 16
CAN_F0R1_FB16_len EQU 1
CAN_F0R1_FB17 EQU 0x00020000 ; Filter bits
CAN_F0R1_FB17_ofs EQU 17
CAN_F0R1_FB17_len EQU 1
CAN_F0R1_FB18 EQU 0x00040000 ; Filter bits
CAN_F0R1_FB18_ofs EQU 18
CAN_F0R1_FB18_len EQU 1
CAN_F0R1_FB19 EQU 0x00080000 ; Filter bits
CAN_F0R1_FB19_ofs EQU 19
CAN_F0R1_FB19_len EQU 1
CAN_F0R1_FB20 EQU 0x00100000 ; Filter bits
CAN_F0R1_FB20_ofs EQU 20
CAN_F0R1_FB20_len EQU 1
CAN_F0R1_FB21 EQU 0x00200000 ; Filter bits
CAN_F0R1_FB21_ofs EQU 21
CAN_F0R1_FB21_len EQU 1
CAN_F0R1_FB22 EQU 0x00400000 ; Filter bits
CAN_F0R1_FB22_ofs EQU 22
CAN_F0R1_FB22_len EQU 1
CAN_F0R1_FB23 EQU 0x00800000 ; Filter bits
CAN_F0R1_FB23_ofs EQU 23
CAN_F0R1_FB23_len EQU 1
CAN_F0R1_FB24 EQU 0x01000000 ; Filter bits
CAN_F0R1_FB24_ofs EQU 24
CAN_F0R1_FB24_len EQU 1
CAN_F0R1_FB25 EQU 0x02000000 ; Filter bits
CAN_F0R1_FB25_ofs EQU 25
CAN_F0R1_FB25_len EQU 1
CAN_F0R1_FB26 EQU 0x04000000 ; Filter bits
CAN_F0R1_FB26_ofs EQU 26
CAN_F0R1_FB26_len EQU 1
CAN_F0R1_FB27 EQU 0x08000000 ; Filter bits
CAN_F0R1_FB27_ofs EQU 27
CAN_F0R1_FB27_len EQU 1
CAN_F0R1_FB28 EQU 0x10000000 ; Filter bits
CAN_F0R1_FB28_ofs EQU 28
CAN_F0R1_FB28_len EQU 1
CAN_F0R1_FB29 EQU 0x20000000 ; Filter bits
CAN_F0R1_FB29_ofs EQU 29
CAN_F0R1_FB29_len EQU 1
CAN_F0R1_FB30 EQU 0x40000000 ; Filter bits
CAN_F0R1_FB30_ofs EQU 30
CAN_F0R1_FB30_len EQU 1
CAN_F0R1_FB31 EQU 0x80000000 ; Filter bits
CAN_F0R1_FB31_ofs EQU 31
CAN_F0R1_FB31_len EQU 1
; CAN_F0R2 fields:
CAN_F0R2_FB0 EQU 0x00000001 ; Filter bits
CAN_F0R2_FB0_ofs EQU 0
CAN_F0R2_FB0_len EQU 1
CAN_F0R2_FB1 EQU 0x00000002 ; Filter bits
CAN_F0R2_FB1_ofs EQU 1
CAN_F0R2_FB1_len EQU 1
CAN_F0R2_FB2 EQU 0x00000004 ; Filter bits
CAN_F0R2_FB2_ofs EQU 2
CAN_F0R2_FB2_len EQU 1
CAN_F0R2_FB3 EQU 0x00000008 ; Filter bits
CAN_F0R2_FB3_ofs EQU 3
CAN_F0R2_FB3_len EQU 1
CAN_F0R2_FB4 EQU 0x00000010 ; Filter bits
CAN_F0R2_FB4_ofs EQU 4
CAN_F0R2_FB4_len EQU 1
CAN_F0R2_FB5 EQU 0x00000020 ; Filter bits
CAN_F0R2_FB5_ofs EQU 5
CAN_F0R2_FB5_len EQU 1
CAN_F0R2_FB6 EQU 0x00000040 ; Filter bits
CAN_F0R2_FB6_ofs EQU 6
CAN_F0R2_FB6_len EQU 1
CAN_F0R2_FB7 EQU 0x00000080 ; Filter bits
CAN_F0R2_FB7_ofs EQU 7
CAN_F0R2_FB7_len EQU 1
CAN_F0R2_FB8 EQU 0x00000100 ; Filter bits
CAN_F0R2_FB8_ofs EQU 8
CAN_F0R2_FB8_len EQU 1
CAN_F0R2_FB9 EQU 0x00000200 ; Filter bits
CAN_F0R2_FB9_ofs EQU 9
CAN_F0R2_FB9_len EQU 1
CAN_F0R2_FB10 EQU 0x00000400 ; Filter bits
CAN_F0R2_FB10_ofs EQU 10
CAN_F0R2_FB10_len EQU 1
CAN_F0R2_FB11 EQU 0x00000800 ; Filter bits
CAN_F0R2_FB11_ofs EQU 11
CAN_F0R2_FB11_len EQU 1
CAN_F0R2_FB12 EQU 0x00001000 ; Filter bits
CAN_F0R2_FB12_ofs EQU 12
CAN_F0R2_FB12_len EQU 1
CAN_F0R2_FB13 EQU 0x00002000 ; Filter bits
CAN_F0R2_FB13_ofs EQU 13
CAN_F0R2_FB13_len EQU 1
CAN_F0R2_FB14 EQU 0x00004000 ; Filter bits
CAN_F0R2_FB14_ofs EQU 14
CAN_F0R2_FB14_len EQU 1
CAN_F0R2_FB15 EQU 0x00008000 ; Filter bits
CAN_F0R2_FB15_ofs EQU 15
CAN_F0R2_FB15_len EQU 1
CAN_F0R2_FB16 EQU 0x00010000 ; Filter bits
CAN_F0R2_FB16_ofs EQU 16
CAN_F0R2_FB16_len EQU 1
CAN_F0R2_FB17 EQU 0x00020000 ; Filter bits
CAN_F0R2_FB17_ofs EQU 17
CAN_F0R2_FB17_len EQU 1
CAN_F0R2_FB18 EQU 0x00040000 ; Filter bits
CAN_F0R2_FB18_ofs EQU 18
CAN_F0R2_FB18_len EQU 1
CAN_F0R2_FB19 EQU 0x00080000 ; Filter bits
CAN_F0R2_FB19_ofs EQU 19
CAN_F0R2_FB19_len EQU 1
CAN_F0R2_FB20 EQU 0x00100000 ; Filter bits
CAN_F0R2_FB20_ofs EQU 20
CAN_F0R2_FB20_len EQU 1
CAN_F0R2_FB21 EQU 0x00200000 ; Filter bits
CAN_F0R2_FB21_ofs EQU 21
CAN_F0R2_FB21_len EQU 1
CAN_F0R2_FB22 EQU 0x00400000 ; Filter bits
CAN_F0R2_FB22_ofs EQU 22
CAN_F0R2_FB22_len EQU 1
CAN_F0R2_FB23 EQU 0x00800000 ; Filter bits
CAN_F0R2_FB23_ofs EQU 23
CAN_F0R2_FB23_len EQU 1
CAN_F0R2_FB24 EQU 0x01000000 ; Filter bits
CAN_F0R2_FB24_ofs EQU 24
CAN_F0R2_FB24_len EQU 1
CAN_F0R2_FB25 EQU 0x02000000 ; Filter bits
CAN_F0R2_FB25_ofs EQU 25
CAN_F0R2_FB25_len EQU 1
CAN_F0R2_FB26 EQU 0x04000000 ; Filter bits
CAN_F0R2_FB26_ofs EQU 26
CAN_F0R2_FB26_len EQU 1
CAN_F0R2_FB27 EQU 0x08000000 ; Filter bits
CAN_F0R2_FB27_ofs EQU 27
CAN_F0R2_FB27_len EQU 1
CAN_F0R2_FB28 EQU 0x10000000 ; Filter bits
CAN_F0R2_FB28_ofs EQU 28
CAN_F0R2_FB28_len EQU 1
CAN_F0R2_FB29 EQU 0x20000000 ; Filter bits
CAN_F0R2_FB29_ofs EQU 29
CAN_F0R2_FB29_len EQU 1
CAN_F0R2_FB30 EQU 0x40000000 ; Filter bits
CAN_F0R2_FB30_ofs EQU 30
CAN_F0R2_FB30_len EQU 1
CAN_F0R2_FB31 EQU 0x80000000 ; Filter bits
CAN_F0R2_FB31_ofs EQU 31
CAN_F0R2_FB31_len EQU 1
; CAN_F1R1 fields:
CAN_FiRx_FB0 EQU 0x00000001 ; Filter bits
CAN_FiRx_FB0_ofs EQU 0
CAN_FiRx_FB0_len EQU 1
CAN_FiRx_FB1 EQU 0x00000002 ; Filter bits
CAN_FiRx_FB1_ofs EQU 1
CAN_FiRx_FB1_len EQU 1
CAN_FiRx_FB2 EQU 0x00000004 ; Filter bits
CAN_FiRx_FB2_ofs EQU 2
CAN_FiRx_FB2_len EQU 1
CAN_FiRx_FB3 EQU 0x00000008 ; Filter bits
CAN_FiRx_FB3_ofs EQU 3
CAN_FiRx_FB3_len EQU 1
CAN_FiRx_FB4 EQU 0x00000010 ; Filter bits
CAN_FiRx_FB4_ofs EQU 4
CAN_FiRx_FB4_len EQU 1
CAN_FiRx_FB5 EQU 0x00000020 ; Filter bits
CAN_FiRx_FB5_ofs EQU 5
CAN_FiRx_FB5_len EQU 1
CAN_FiRx_FB6 EQU 0x00000040 ; Filter bits
CAN_FiRx_FB6_ofs EQU 6
CAN_FiRx_FB6_len EQU 1
CAN_FiRx_FB7 EQU 0x00000080 ; Filter bits
CAN_FiRx_FB7_ofs EQU 7
CAN_FiRx_FB7_len EQU 1
CAN_FiRx_FB8 EQU 0x00000100 ; Filter bits
CAN_FiRx_FB8_ofs EQU 8
CAN_FiRx_FB8_len EQU 1
CAN_FiRx_FB9 EQU 0x00000200 ; Filter bits
CAN_FiRx_FB9_ofs EQU 9
CAN_FiRx_FB9_len EQU 1
CAN_FiRx_FB10 EQU 0x00000400 ; Filter bits
CAN_FiRx_FB10_ofs EQU 10
CAN_FiRx_FB10_len EQU 1
CAN_FiRx_FB11 EQU 0x00000800 ; Filter bits
CAN_FiRx_FB11_ofs EQU 11
CAN_FiRx_FB11_len EQU 1
CAN_FiRx_FB12 EQU 0x00001000 ; Filter bits
CAN_FiRx_FB12_ofs EQU 12
CAN_FiRx_FB12_len EQU 1
CAN_FiRx_FB13 EQU 0x00002000 ; Filter bits
CAN_FiRx_FB13_ofs EQU 13
CAN_FiRx_FB13_len EQU 1
CAN_FiRx_FB14 EQU 0x00004000 ; Filter bits
CAN_FiRx_FB14_ofs EQU 14
CAN_FiRx_FB14_len EQU 1
CAN_FiRx_FB15 EQU 0x00008000 ; Filter bits
CAN_FiRx_FB15_ofs EQU 15
CAN_FiRx_FB15_len EQU 1
CAN_FiRx_FB16 EQU 0x00010000 ; Filter bits
CAN_FiRx_FB16_ofs EQU 16
CAN_FiRx_FB16_len EQU 1
CAN_FiRx_FB17 EQU 0x00020000 ; Filter bits
CAN_FiRx_FB17_ofs EQU 17
CAN_FiRx_FB17_len EQU 1
CAN_FiRx_FB18 EQU 0x00040000 ; Filter bits
CAN_FiRx_FB18_ofs EQU 18
CAN_FiRx_FB18_len EQU 1
CAN_FiRx_FB19 EQU 0x00080000 ; Filter bits
CAN_FiRx_FB19_ofs EQU 19
CAN_FiRx_FB19_len EQU 1
CAN_FiRx_FB20 EQU 0x00100000 ; Filter bits
CAN_FiRx_FB20_ofs EQU 20
CAN_FiRx_FB20_len EQU 1
CAN_FiRx_FB21 EQU 0x00200000 ; Filter bits
CAN_FiRx_FB21_ofs EQU 21
CAN_FiRx_FB21_len EQU 1
CAN_FiRx_FB22 EQU 0x00400000 ; Filter bits
CAN_FiRx_FB22_ofs EQU 22
CAN_FiRx_FB22_len EQU 1
CAN_FiRx_FB23 EQU 0x00800000 ; Filter bits
CAN_FiRx_FB23_ofs EQU 23
CAN_FiRx_FB23_len EQU 1
CAN_FiRx_FB24 EQU 0x01000000 ; Filter bits
CAN_FiRx_FB24_ofs EQU 24
CAN_FiRx_FB24_len EQU 1
CAN_FiRx_FB25 EQU 0x02000000 ; Filter bits
CAN_FiRx_FB25_ofs EQU 25
CAN_FiRx_FB25_len EQU 1
CAN_FiRx_FB26 EQU 0x04000000 ; Filter bits
CAN_FiRx_FB26_ofs EQU 26
CAN_FiRx_FB26_len EQU 1
CAN_FiRx_FB27 EQU 0x08000000 ; Filter bits
CAN_FiRx_FB27_ofs EQU 27
CAN_FiRx_FB27_len EQU 1
CAN_FiRx_FB28 EQU 0x10000000 ; Filter bits
CAN_FiRx_FB28_ofs EQU 28
CAN_FiRx_FB28_len EQU 1
CAN_FiRx_FB29 EQU 0x20000000 ; Filter bits
CAN_FiRx_FB29_ofs EQU 29
CAN_FiRx_FB29_len EQU 1
CAN_FiRx_FB30 EQU 0x40000000 ; Filter bits
CAN_FiRx_FB30_ofs EQU 30
CAN_FiRx_FB30_len EQU 1
CAN_FiRx_FB31 EQU 0x80000000 ; Filter bits
CAN_FiRx_FB31_ofs EQU 31
CAN_FiRx_FB31_len EQU 1
; ---- USB_FS ------------------------------------------------
; Desc: Universal serial bus full-speed device interface
; USB_FS base address:
USB_FS_BASE EQU 0x40005c00
; USB_FS registers:
USB_FS_USB_EP0R EQU (USB_FS_BASE + 0x0) ; endpoint 0 register
USB_FS_USB_EP1R EQU (USB_FS_BASE + 0x4) ; endpoint 1 register
USB_FS_USB_EP2R EQU (USB_FS_BASE + 0x8) ; endpoint 2 register
USB_FS_USB_EP3R EQU (USB_FS_BASE + 0xc) ; endpoint 3 register
USB_FS_USB_EP4R EQU (USB_FS_BASE + 0x10) ; endpoint 4 register
USB_FS_USB_EP5R EQU (USB_FS_BASE + 0x14) ; endpoint 5 register
USB_FS_USB_EP6R EQU (USB_FS_BASE + 0x18) ; endpoint 6 register
USB_FS_USB_EP7R EQU (USB_FS_BASE + 0x1c) ; endpoint 7 register
USB_FS_USB_CNTR EQU (USB_FS_BASE + 0x40) ; control register
USB_FS_ISTR EQU (USB_FS_BASE + 0x44) ; interrupt status register
USB_FS_FNR EQU (USB_FS_BASE + 0x48) ; frame number register
USB_FS_DADDR EQU (USB_FS_BASE + 0x4c) ; device address
USB_FS_BTABLE EQU (USB_FS_BASE + 0x50) ; Buffer table address
; USB_FS_USB_EP0R fields:
USB_FS_USB_EP0R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP0R_EA_ofs EQU 0
USB_FS_USB_EP0R_EA_len EQU 4
USB_FS_USB_EP0R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP0R_STAT_TX_ofs EQU 4
USB_FS_USB_EP0R_STAT_TX_len EQU 2
USB_FS_USB_EP0R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP0R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP0R_DTOG_TX_len EQU 1
USB_FS_USB_EP0R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP0R_CTR_TX_ofs EQU 7
USB_FS_USB_EP0R_CTR_TX_len EQU 1
USB_FS_USB_EP0R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP0R_EP_KIND_ofs EQU 8
USB_FS_USB_EP0R_EP_KIND_len EQU 1
USB_FS_USB_EP0R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP0R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP0R_EP_TYPE_len EQU 2
USB_FS_USB_EP0R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP0R_SETUP_ofs EQU 11
USB_FS_USB_EP0R_SETUP_len EQU 1
USB_FS_USB_EP0R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP0R_STAT_RX_ofs EQU 12
USB_FS_USB_EP0R_STAT_RX_len EQU 2
USB_FS_USB_EP0R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP0R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP0R_DTOG_RX_len EQU 1
USB_FS_USB_EP0R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP0R_CTR_RX_ofs EQU 15
USB_FS_USB_EP0R_CTR_RX_len EQU 1
; USB_FS_USB_EP1R fields:
USB_FS_USB_EP1R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP1R_EA_ofs EQU 0
USB_FS_USB_EP1R_EA_len EQU 4
USB_FS_USB_EP1R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP1R_STAT_TX_ofs EQU 4
USB_FS_USB_EP1R_STAT_TX_len EQU 2
USB_FS_USB_EP1R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP1R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP1R_DTOG_TX_len EQU 1
USB_FS_USB_EP1R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP1R_CTR_TX_ofs EQU 7
USB_FS_USB_EP1R_CTR_TX_len EQU 1
USB_FS_USB_EP1R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP1R_EP_KIND_ofs EQU 8
USB_FS_USB_EP1R_EP_KIND_len EQU 1
USB_FS_USB_EP1R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP1R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP1R_EP_TYPE_len EQU 2
USB_FS_USB_EP1R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP1R_SETUP_ofs EQU 11
USB_FS_USB_EP1R_SETUP_len EQU 1
USB_FS_USB_EP1R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP1R_STAT_RX_ofs EQU 12
USB_FS_USB_EP1R_STAT_RX_len EQU 2
USB_FS_USB_EP1R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP1R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP1R_DTOG_RX_len EQU 1
USB_FS_USB_EP1R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP1R_CTR_RX_ofs EQU 15
USB_FS_USB_EP1R_CTR_RX_len EQU 1
; USB_FS_USB_EP2R fields:
USB_FS_USB_EP2R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP2R_EA_ofs EQU 0
USB_FS_USB_EP2R_EA_len EQU 4
USB_FS_USB_EP2R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP2R_STAT_TX_ofs EQU 4
USB_FS_USB_EP2R_STAT_TX_len EQU 2
USB_FS_USB_EP2R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP2R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP2R_DTOG_TX_len EQU 1
USB_FS_USB_EP2R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP2R_CTR_TX_ofs EQU 7
USB_FS_USB_EP2R_CTR_TX_len EQU 1
USB_FS_USB_EP2R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP2R_EP_KIND_ofs EQU 8
USB_FS_USB_EP2R_EP_KIND_len EQU 1
USB_FS_USB_EP2R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP2R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP2R_EP_TYPE_len EQU 2
USB_FS_USB_EP2R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP2R_SETUP_ofs EQU 11
USB_FS_USB_EP2R_SETUP_len EQU 1
USB_FS_USB_EP2R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP2R_STAT_RX_ofs EQU 12
USB_FS_USB_EP2R_STAT_RX_len EQU 2
USB_FS_USB_EP2R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP2R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP2R_DTOG_RX_len EQU 1
USB_FS_USB_EP2R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP2R_CTR_RX_ofs EQU 15
USB_FS_USB_EP2R_CTR_RX_len EQU 1
; USB_FS_USB_EP3R fields:
USB_FS_USB_EP3R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP3R_EA_ofs EQU 0
USB_FS_USB_EP3R_EA_len EQU 4
USB_FS_USB_EP3R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP3R_STAT_TX_ofs EQU 4
USB_FS_USB_EP3R_STAT_TX_len EQU 2
USB_FS_USB_EP3R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP3R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP3R_DTOG_TX_len EQU 1
USB_FS_USB_EP3R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP3R_CTR_TX_ofs EQU 7
USB_FS_USB_EP3R_CTR_TX_len EQU 1
USB_FS_USB_EP3R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP3R_EP_KIND_ofs EQU 8
USB_FS_USB_EP3R_EP_KIND_len EQU 1
USB_FS_USB_EP3R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP3R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP3R_EP_TYPE_len EQU 2
USB_FS_USB_EP3R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP3R_SETUP_ofs EQU 11
USB_FS_USB_EP3R_SETUP_len EQU 1
USB_FS_USB_EP3R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP3R_STAT_RX_ofs EQU 12
USB_FS_USB_EP3R_STAT_RX_len EQU 2
USB_FS_USB_EP3R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP3R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP3R_DTOG_RX_len EQU 1
USB_FS_USB_EP3R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP3R_CTR_RX_ofs EQU 15
USB_FS_USB_EP3R_CTR_RX_len EQU 1
; USB_FS_USB_EP4R fields:
USB_FS_USB_EP4R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP4R_EA_ofs EQU 0
USB_FS_USB_EP4R_EA_len EQU 4
USB_FS_USB_EP4R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP4R_STAT_TX_ofs EQU 4
USB_FS_USB_EP4R_STAT_TX_len EQU 2
USB_FS_USB_EP4R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP4R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP4R_DTOG_TX_len EQU 1
USB_FS_USB_EP4R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP4R_CTR_TX_ofs EQU 7
USB_FS_USB_EP4R_CTR_TX_len EQU 1
USB_FS_USB_EP4R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP4R_EP_KIND_ofs EQU 8
USB_FS_USB_EP4R_EP_KIND_len EQU 1
USB_FS_USB_EP4R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP4R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP4R_EP_TYPE_len EQU 2
USB_FS_USB_EP4R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP4R_SETUP_ofs EQU 11
USB_FS_USB_EP4R_SETUP_len EQU 1
USB_FS_USB_EP4R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP4R_STAT_RX_ofs EQU 12
USB_FS_USB_EP4R_STAT_RX_len EQU 2
USB_FS_USB_EP4R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP4R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP4R_DTOG_RX_len EQU 1
USB_FS_USB_EP4R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP4R_CTR_RX_ofs EQU 15
USB_FS_USB_EP4R_CTR_RX_len EQU 1
; USB_FS_USB_EP5R fields:
USB_FS_USB_EP5R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP5R_EA_ofs EQU 0
USB_FS_USB_EP5R_EA_len EQU 4
USB_FS_USB_EP5R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP5R_STAT_TX_ofs EQU 4
USB_FS_USB_EP5R_STAT_TX_len EQU 2
USB_FS_USB_EP5R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP5R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP5R_DTOG_TX_len EQU 1
USB_FS_USB_EP5R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP5R_CTR_TX_ofs EQU 7
USB_FS_USB_EP5R_CTR_TX_len EQU 1
USB_FS_USB_EP5R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP5R_EP_KIND_ofs EQU 8
USB_FS_USB_EP5R_EP_KIND_len EQU 1
USB_FS_USB_EP5R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP5R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP5R_EP_TYPE_len EQU 2
USB_FS_USB_EP5R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP5R_SETUP_ofs EQU 11
USB_FS_USB_EP5R_SETUP_len EQU 1
USB_FS_USB_EP5R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP5R_STAT_RX_ofs EQU 12
USB_FS_USB_EP5R_STAT_RX_len EQU 2
USB_FS_USB_EP5R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP5R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP5R_DTOG_RX_len EQU 1
USB_FS_USB_EP5R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP5R_CTR_RX_ofs EQU 15
USB_FS_USB_EP5R_CTR_RX_len EQU 1
; USB_FS_USB_EP6R fields:
USB_FS_USB_EP6R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP6R_EA_ofs EQU 0
USB_FS_USB_EP6R_EA_len EQU 4
USB_FS_USB_EP6R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP6R_STAT_TX_ofs EQU 4
USB_FS_USB_EP6R_STAT_TX_len EQU 2
USB_FS_USB_EP6R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP6R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP6R_DTOG_TX_len EQU 1
USB_FS_USB_EP6R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP6R_CTR_TX_ofs EQU 7
USB_FS_USB_EP6R_CTR_TX_len EQU 1
USB_FS_USB_EP6R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP6R_EP_KIND_ofs EQU 8
USB_FS_USB_EP6R_EP_KIND_len EQU 1
USB_FS_USB_EP6R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP6R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP6R_EP_TYPE_len EQU 2
USB_FS_USB_EP6R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP6R_SETUP_ofs EQU 11
USB_FS_USB_EP6R_SETUP_len EQU 1
USB_FS_USB_EP6R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP6R_STAT_RX_ofs EQU 12
USB_FS_USB_EP6R_STAT_RX_len EQU 2
USB_FS_USB_EP6R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP6R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP6R_DTOG_RX_len EQU 1
USB_FS_USB_EP6R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP6R_CTR_RX_ofs EQU 15
USB_FS_USB_EP6R_CTR_RX_len EQU 1
; USB_FS_USB_EP7R fields:
USB_FS_USB_EP7R_EA EQU 0x0000000f ; Endpoint address
USB_FS_USB_EP7R_EA_ofs EQU 0
USB_FS_USB_EP7R_EA_len EQU 4
USB_FS_USB_EP7R_STAT_TX EQU 0x00000030 ; Status bits, for transmission transfers
USB_FS_USB_EP7R_STAT_TX_ofs EQU 4
USB_FS_USB_EP7R_STAT_TX_len EQU 2
USB_FS_USB_EP7R_DTOG_TX EQU 0x00000040 ; Data Toggle, for transmission transfers
USB_FS_USB_EP7R_DTOG_TX_ofs EQU 6
USB_FS_USB_EP7R_DTOG_TX_len EQU 1
USB_FS_USB_EP7R_CTR_TX EQU 0x00000080 ; Correct Transfer for transmission
USB_FS_USB_EP7R_CTR_TX_ofs EQU 7
USB_FS_USB_EP7R_CTR_TX_len EQU 1
USB_FS_USB_EP7R_EP_KIND EQU 0x00000100 ; Endpoint kind
USB_FS_USB_EP7R_EP_KIND_ofs EQU 8
USB_FS_USB_EP7R_EP_KIND_len EQU 1
USB_FS_USB_EP7R_EP_TYPE EQU 0x00000600 ; Endpoint type
USB_FS_USB_EP7R_EP_TYPE_ofs EQU 9
USB_FS_USB_EP7R_EP_TYPE_len EQU 2
USB_FS_USB_EP7R_SETUP EQU 0x00000800 ; Setup transaction completed
USB_FS_USB_EP7R_SETUP_ofs EQU 11
USB_FS_USB_EP7R_SETUP_len EQU 1
USB_FS_USB_EP7R_STAT_RX EQU 0x00003000 ; Status bits, for reception transfers
USB_FS_USB_EP7R_STAT_RX_ofs EQU 12
USB_FS_USB_EP7R_STAT_RX_len EQU 2
USB_FS_USB_EP7R_DTOG_RX EQU 0x00004000 ; Data Toggle, for reception transfers
USB_FS_USB_EP7R_DTOG_RX_ofs EQU 14
USB_FS_USB_EP7R_DTOG_RX_len EQU 1
USB_FS_USB_EP7R_CTR_RX EQU 0x00008000 ; Correct transfer for reception
USB_FS_USB_EP7R_CTR_RX_ofs EQU 15
USB_FS_USB_EP7R_CTR_RX_len EQU 1
; USB_FS_USB_CNTR fields:
USB_FS_USB_CNTR_FRES EQU 0x00000001 ; Force USB Reset
USB_FS_USB_CNTR_FRES_ofs EQU 0
USB_FS_USB_CNTR_FRES_len EQU 1
USB_FS_USB_CNTR_PDWN EQU 0x00000002 ; Power down
USB_FS_USB_CNTR_PDWN_ofs EQU 1
USB_FS_USB_CNTR_PDWN_len EQU 1
USB_FS_USB_CNTR_LPMODE EQU 0x00000004 ; Low-power mode
USB_FS_USB_CNTR_LPMODE_ofs EQU 2
USB_FS_USB_CNTR_LPMODE_len EQU 1
USB_FS_USB_CNTR_FSUSP EQU 0x00000008 ; Force suspend
USB_FS_USB_CNTR_FSUSP_ofs EQU 3
USB_FS_USB_CNTR_FSUSP_len EQU 1
USB_FS_USB_CNTR_RESUME EQU 0x00000010 ; Resume request
USB_FS_USB_CNTR_RESUME_ofs EQU 4
USB_FS_USB_CNTR_RESUME_len EQU 1
USB_FS_USB_CNTR_ESOFM EQU 0x00000100 ; Expected start of frame interrupt mask
USB_FS_USB_CNTR_ESOFM_ofs EQU 8
USB_FS_USB_CNTR_ESOFM_len EQU 1
USB_FS_USB_CNTR_SOFM EQU 0x00000200 ; Start of frame interrupt mask
USB_FS_USB_CNTR_SOFM_ofs EQU 9
USB_FS_USB_CNTR_SOFM_len EQU 1
USB_FS_USB_CNTR_RESETM EQU 0x00000400 ; USB reset interrupt mask
USB_FS_USB_CNTR_RESETM_ofs EQU 10
USB_FS_USB_CNTR_RESETM_len EQU 1
USB_FS_USB_CNTR_SUSPM EQU 0x00000800 ; Suspend mode interrupt mask
USB_FS_USB_CNTR_SUSPM_ofs EQU 11
USB_FS_USB_CNTR_SUSPM_len EQU 1
USB_FS_USB_CNTR_WKUPM EQU 0x00001000 ; Wakeup interrupt mask
USB_FS_USB_CNTR_WKUPM_ofs EQU 12
USB_FS_USB_CNTR_WKUPM_len EQU 1
USB_FS_USB_CNTR_ERRM EQU 0x00002000 ; Error interrupt mask
USB_FS_USB_CNTR_ERRM_ofs EQU 13
USB_FS_USB_CNTR_ERRM_len EQU 1
USB_FS_USB_CNTR_PMAOVRM EQU 0x00004000 ; Packet memory area over / underrun interrupt mask
USB_FS_USB_CNTR_PMAOVRM_ofs EQU 14
USB_FS_USB_CNTR_PMAOVRM_len EQU 1
USB_FS_USB_CNTR_CTRM EQU 0x00008000 ; Correct transfer interrupt mask
USB_FS_USB_CNTR_CTRM_ofs EQU 15
USB_FS_USB_CNTR_CTRM_len EQU 1
; USB_FS_ISTR fields:
USB_FS_ISTR_EP_ID EQU 0x0000000f ; Endpoint Identifier
USB_FS_ISTR_EP_ID_ofs EQU 0
USB_FS_ISTR_EP_ID_len EQU 4
USB_FS_ISTR_DIR EQU 0x00000010 ; Direction of transaction
USB_FS_ISTR_DIR_ofs EQU 4
USB_FS_ISTR_DIR_len EQU 1
USB_FS_ISTR_ESOF EQU 0x00000100 ; Expected start frame
USB_FS_ISTR_ESOF_ofs EQU 8
USB_FS_ISTR_ESOF_len EQU 1
USB_FS_ISTR_SOF EQU 0x00000200 ; start of frame
USB_FS_ISTR_SOF_ofs EQU 9
USB_FS_ISTR_SOF_len EQU 1
USB_FS_ISTR_RESET EQU 0x00000400 ; reset request
USB_FS_ISTR_RESET_ofs EQU 10
USB_FS_ISTR_RESET_len EQU 1
USB_FS_ISTR_SUSP EQU 0x00000800 ; Suspend mode request
USB_FS_ISTR_SUSP_ofs EQU 11
USB_FS_ISTR_SUSP_len EQU 1
USB_FS_ISTR_WKUP EQU 0x00001000 ; Wakeup
USB_FS_ISTR_WKUP_ofs EQU 12
USB_FS_ISTR_WKUP_len EQU 1
USB_FS_ISTR_ERR EQU 0x00002000 ; Error
USB_FS_ISTR_ERR_ofs EQU 13
USB_FS_ISTR_ERR_len EQU 1
USB_FS_ISTR_PMAOVR EQU 0x00004000 ; Packet memory area over / underrun
USB_FS_ISTR_PMAOVR_ofs EQU 14
USB_FS_ISTR_PMAOVR_len EQU 1
USB_FS_ISTR_CTR EQU 0x00008000 ; Correct transfer
USB_FS_ISTR_CTR_ofs EQU 15
USB_FS_ISTR_CTR_len EQU 1
; USB_FS_FNR fields:
USB_FS_FNR_FN EQU 0x000007ff ; Frame number
USB_FS_FNR_FN_ofs EQU 0
USB_FS_FNR_FN_len EQU 11
USB_FS_FNR_LSOF EQU 0x00001800 ; Lost SOF
USB_FS_FNR_LSOF_ofs EQU 11
USB_FS_FNR_LSOF_len EQU 2
USB_FS_FNR_LCK EQU 0x00002000 ; Locked
USB_FS_FNR_LCK_ofs EQU 13
USB_FS_FNR_LCK_len EQU 1
USB_FS_FNR_RXDM EQU 0x00004000 ; Receive data - line status
USB_FS_FNR_RXDM_ofs EQU 14
USB_FS_FNR_RXDM_len EQU 1
USB_FS_FNR_RXDP EQU 0x00008000 ; Receive data + line status
USB_FS_FNR_RXDP_ofs EQU 15
USB_FS_FNR_RXDP_len EQU 1
; USB_FS_DADDR fields:
USB_FS_DADDR_ADD EQU 0x00000001 ; Device address
USB_FS_DADDR_ADD_ofs EQU 0
USB_FS_DADDR_ADD_len EQU 1
USB_FS_DADDR_ADD1 EQU 0x00000002 ; Device address
USB_FS_DADDR_ADD1_ofs EQU 1
USB_FS_DADDR_ADD1_len EQU 1
USB_FS_DADDR_ADD2 EQU 0x00000004 ; Device address
USB_FS_DADDR_ADD2_ofs EQU 2
USB_FS_DADDR_ADD2_len EQU 1
USB_FS_DADDR_ADD3 EQU 0x00000008 ; Device address
USB_FS_DADDR_ADD3_ofs EQU 3
USB_FS_DADDR_ADD3_len EQU 1
USB_FS_DADDR_ADD4 EQU 0x00000010 ; Device address
USB_FS_DADDR_ADD4_ofs EQU 4
USB_FS_DADDR_ADD4_len EQU 1
USB_FS_DADDR_ADD5 EQU 0x00000020 ; Device address
USB_FS_DADDR_ADD5_ofs EQU 5
USB_FS_DADDR_ADD5_len EQU 1
USB_FS_DADDR_ADD6 EQU 0x00000040 ; Device address
USB_FS_DADDR_ADD6_ofs EQU 6
USB_FS_DADDR_ADD6_len EQU 1
USB_FS_DADDR_EF EQU 0x00000080 ; Enable function
USB_FS_DADDR_EF_ofs EQU 7
USB_FS_DADDR_EF_len EQU 1
; USB_FS_BTABLE fields:
USB_FS_BTABLE_BTABLE EQU 0x0000fff8 ; Buffer table
USB_FS_BTABLE_BTABLE_ofs EQU 3
USB_FS_BTABLE_BTABLE_len EQU 13
; ---- I2C1 --------------------------------------------------
; Desc: Inter-integrated circuit
; I2C1 base address:
I2C1_BASE EQU 0x40005400
; I2C1 registers:
I2C1_CR1 EQU (I2C1_BASE + 0x0) ; Control register 1
I2C1_CR2 EQU (I2C1_BASE + 0x4) ; Control register 2
I2C1_OAR1 EQU (I2C1_BASE + 0x8) ; Own address register 1
I2C1_OAR2 EQU (I2C1_BASE + 0xc) ; Own address register 2
I2C1_TIMINGR EQU (I2C1_BASE + 0x10) ; Timing register
I2C1_TIMEOUTR EQU (I2C1_BASE + 0x14) ; Status register 1
I2C1_ISR EQU (I2C1_BASE + 0x18) ; Interrupt and Status register
I2C1_ICR EQU (I2C1_BASE + 0x1c) ; Interrupt clear register
I2C1_PECR EQU (I2C1_BASE + 0x20) ; PEC register
I2C1_RXDR EQU (I2C1_BASE + 0x24) ; Receive data register
I2C1_TXDR EQU (I2C1_BASE + 0x28) ; Transmit data register
; I2C1_CR1 fields:
I2C_CR1_PE EQU 0x00000001 ; Peripheral enable
I2C_CR1_PE_ofs EQU 0
I2C_CR1_PE_len EQU 1
I2C_CR1_TXIE EQU 0x00000002 ; TX Interrupt enable
I2C_CR1_TXIE_ofs EQU 1
I2C_CR1_TXIE_len EQU 1
I2C_CR1_RXIE EQU 0x00000004 ; RX Interrupt enable
I2C_CR1_RXIE_ofs EQU 2
I2C_CR1_RXIE_len EQU 1
I2C_CR1_ADDRIE EQU 0x00000008 ; Address match interrupt enable (slave only)
I2C_CR1_ADDRIE_ofs EQU 3
I2C_CR1_ADDRIE_len EQU 1
I2C_CR1_NACKIE EQU 0x00000010 ; Not acknowledge received interrupt enable
I2C_CR1_NACKIE_ofs EQU 4
I2C_CR1_NACKIE_len EQU 1
I2C_CR1_STOPIE EQU 0x00000020 ; STOP detection Interrupt enable
I2C_CR1_STOPIE_ofs EQU 5
I2C_CR1_STOPIE_len EQU 1
I2C_CR1_TCIE EQU 0x00000040 ; Transfer Complete interrupt enable
I2C_CR1_TCIE_ofs EQU 6
I2C_CR1_TCIE_len EQU 1
I2C_CR1_ERRIE EQU 0x00000080 ; Error interrupts enable
I2C_CR1_ERRIE_ofs EQU 7
I2C_CR1_ERRIE_len EQU 1
I2C_CR1_DNF EQU 0x00000f00 ; Digital noise filter
I2C_CR1_DNF_ofs EQU 8
I2C_CR1_DNF_len EQU 4
I2C_CR1_ANFOFF EQU 0x00001000 ; Analog noise filter OFF
I2C_CR1_ANFOFF_ofs EQU 12
I2C_CR1_ANFOFF_len EQU 1
I2C_CR1_SWRST EQU 0x00002000 ; Software reset
I2C_CR1_SWRST_ofs EQU 13
I2C_CR1_SWRST_len EQU 1
I2C_CR1_TXDMAEN EQU 0x00004000 ; DMA transmission requests enable
I2C_CR1_TXDMAEN_ofs EQU 14
I2C_CR1_TXDMAEN_len EQU 1
I2C_CR1_RXDMAEN EQU 0x00008000 ; DMA reception requests enable
I2C_CR1_RXDMAEN_ofs EQU 15
I2C_CR1_RXDMAEN_len EQU 1
I2C_CR1_SBC EQU 0x00010000 ; Slave byte control
I2C_CR1_SBC_ofs EQU 16
I2C_CR1_SBC_len EQU 1
I2C_CR1_NOSTRETCH EQU 0x00020000 ; Clock stretching disable
I2C_CR1_NOSTRETCH_ofs EQU 17
I2C_CR1_NOSTRETCH_len EQU 1
I2C_CR1_WUPEN EQU 0x00040000 ; Wakeup from STOP enable
I2C_CR1_WUPEN_ofs EQU 18
I2C_CR1_WUPEN_len EQU 1
I2C_CR1_GCEN EQU 0x00080000 ; General call enable
I2C_CR1_GCEN_ofs EQU 19
I2C_CR1_GCEN_len EQU 1
I2C_CR1_SMBHEN EQU 0x00100000 ; SMBus Host address enable
I2C_CR1_SMBHEN_ofs EQU 20
I2C_CR1_SMBHEN_len EQU 1
I2C_CR1_SMBDEN EQU 0x00200000 ; SMBus Device Default address enable
I2C_CR1_SMBDEN_ofs EQU 21
I2C_CR1_SMBDEN_len EQU 1
I2C_CR1_ALERTEN EQU 0x00400000 ; SMBUS alert enable
I2C_CR1_ALERTEN_ofs EQU 22
I2C_CR1_ALERTEN_len EQU 1
I2C_CR1_PECEN EQU 0x00800000 ; PEC enable
I2C_CR1_PECEN_ofs EQU 23
I2C_CR1_PECEN_len EQU 1
; I2C1_CR2 fields:
I2C_CR2_PECBYTE EQU 0x04000000 ; Packet error checking byte
I2C_CR2_PECBYTE_ofs EQU 26
I2C_CR2_PECBYTE_len EQU 1
I2C_CR2_AUTOEND EQU 0x02000000 ; Automatic end mode (master mode)
I2C_CR2_AUTOEND_ofs EQU 25
I2C_CR2_AUTOEND_len EQU 1
I2C_CR2_RELOAD EQU 0x01000000 ; NBYTES reload mode
I2C_CR2_RELOAD_ofs EQU 24
I2C_CR2_RELOAD_len EQU 1
I2C_CR2_NBYTES EQU 0x00ff0000 ; Number of bytes
I2C_CR2_NBYTES_ofs EQU 16
I2C_CR2_NBYTES_len EQU 8
I2C_CR2_NACK EQU 0x00008000 ; NACK generation (slave mode)
I2C_CR2_NACK_ofs EQU 15
I2C_CR2_NACK_len EQU 1
I2C_CR2_STOP EQU 0x00004000 ; Stop generation (master mode)
I2C_CR2_STOP_ofs EQU 14
I2C_CR2_STOP_len EQU 1
I2C_CR2_START EQU 0x00002000 ; Start generation
I2C_CR2_START_ofs EQU 13
I2C_CR2_START_len EQU 1
I2C_CR2_HEAD10R EQU 0x00001000 ; 10-bit address header only read direction (master receiver mode)
I2C_CR2_HEAD10R_ofs EQU 12
I2C_CR2_HEAD10R_len EQU 1
I2C_CR2_ADD10 EQU 0x00000800 ; 10-bit addressing mode (master mode)
I2C_CR2_ADD10_ofs EQU 11
I2C_CR2_ADD10_len EQU 1
I2C_CR2_RD_WRN EQU 0x00000400 ; Transfer direction (master mode)
I2C_CR2_RD_WRN_ofs EQU 10
I2C_CR2_RD_WRN_len EQU 1
I2C_CR2_SADD8 EQU 0x00000300 ; Slave address bit 9:8 (master mode)
I2C_CR2_SADD8_ofs EQU 8
I2C_CR2_SADD8_len EQU 2
I2C_CR2_SADD1 EQU 0x000000fe ; Slave address bit 7:1 (master mode)
I2C_CR2_SADD1_ofs EQU 1
I2C_CR2_SADD1_len EQU 7
I2C_CR2_SADD0 EQU 0x00000001 ; Slave address bit 0 (master mode)
I2C_CR2_SADD0_ofs EQU 0
I2C_CR2_SADD0_len EQU 1
; I2C1_OAR1 fields:
I2C_OAR1_OA1_0 EQU 0x00000001 ; Interface address
I2C_OAR1_OA1_0_ofs EQU 0
I2C_OAR1_OA1_0_len EQU 1
I2C_OAR1_OA1_1 EQU 0x000000fe ; Interface address
I2C_OAR1_OA1_1_ofs EQU 1
I2C_OAR1_OA1_1_len EQU 7
I2C_OAR1_OA1_8 EQU 0x00000300 ; Interface address
I2C_OAR1_OA1_8_ofs EQU 8
I2C_OAR1_OA1_8_len EQU 2
I2C_OAR1_OA1MODE EQU 0x00000400 ; Own Address 1 10-bit mode
I2C_OAR1_OA1MODE_ofs EQU 10
I2C_OAR1_OA1MODE_len EQU 1
I2C_OAR1_OA1EN EQU 0x00008000 ; Own Address 1 enable
I2C_OAR1_OA1EN_ofs EQU 15
I2C_OAR1_OA1EN_len EQU 1
; I2C1_OAR2 fields:
I2C_OAR2_OA2 EQU 0x000000fe ; Interface address
I2C_OAR2_OA2_ofs EQU 1
I2C_OAR2_OA2_len EQU 7
I2C_OAR2_OA2MSK EQU 0x00000700 ; Own Address 2 masks
I2C_OAR2_OA2MSK_ofs EQU 8
I2C_OAR2_OA2MSK_len EQU 3
I2C_OAR2_OA2EN EQU 0x00008000 ; Own Address 2 enable
I2C_OAR2_OA2EN_ofs EQU 15
I2C_OAR2_OA2EN_len EQU 1
; I2C1_TIMINGR fields:
I2C_TIMINGR_SCLL EQU 0x000000ff ; SCL low period (master mode)
I2C_TIMINGR_SCLL_ofs EQU 0
I2C_TIMINGR_SCLL_len EQU 8
I2C_TIMINGR_SCLH EQU 0x0000ff00 ; SCL high period (master mode)
I2C_TIMINGR_SCLH_ofs EQU 8
I2C_TIMINGR_SCLH_len EQU 8
I2C_TIMINGR_SDADEL EQU 0x000f0000 ; Data hold time
I2C_TIMINGR_SDADEL_ofs EQU 16
I2C_TIMINGR_SDADEL_len EQU 4
I2C_TIMINGR_SCLDEL EQU 0x00f00000 ; Data setup time
I2C_TIMINGR_SCLDEL_ofs EQU 20
I2C_TIMINGR_SCLDEL_len EQU 4
I2C_TIMINGR_PRESC EQU 0xf0000000 ; Timing prescaler
I2C_TIMINGR_PRESC_ofs EQU 28
I2C_TIMINGR_PRESC_len EQU 4
; I2C1_TIMEOUTR fields:
I2C_TIMEOUTR_TIMEOUTA EQU 0x00000fff ; Bus timeout A
I2C_TIMEOUTR_TIMEOUTA_ofs EQU 0
I2C_TIMEOUTR_TIMEOUTA_len EQU 12
I2C_TIMEOUTR_TIDLE EQU 0x00001000 ; Idle clock timeout detection
I2C_TIMEOUTR_TIDLE_ofs EQU 12
I2C_TIMEOUTR_TIDLE_len EQU 1
I2C_TIMEOUTR_TIMOUTEN EQU 0x00008000 ; Clock timeout enable
I2C_TIMEOUTR_TIMOUTEN_ofs EQU 15
I2C_TIMEOUTR_TIMOUTEN_len EQU 1
I2C_TIMEOUTR_TIMEOUTB EQU 0x0fff0000 ; Bus timeout B
I2C_TIMEOUTR_TIMEOUTB_ofs EQU 16
I2C_TIMEOUTR_TIMEOUTB_len EQU 12
I2C_TIMEOUTR_TEXTEN EQU 0x80000000 ; Extended clock timeout enable
I2C_TIMEOUTR_TEXTEN_ofs EQU 31
I2C_TIMEOUTR_TEXTEN_len EQU 1
; I2C1_ISR fields:
I2C_ISR_ADDCODE EQU 0x00fe0000 ; Address match code (Slave mode)
I2C_ISR_ADDCODE_ofs EQU 17
I2C_ISR_ADDCODE_len EQU 7
I2C_ISR_DIR EQU 0x00010000 ; Transfer direction (Slave mode)
I2C_ISR_DIR_ofs EQU 16
I2C_ISR_DIR_len EQU 1
I2C_ISR_BUSY EQU 0x00008000 ; Bus busy
I2C_ISR_BUSY_ofs EQU 15
I2C_ISR_BUSY_len EQU 1
I2C_ISR_ALERT EQU 0x00002000 ; SMBus alert
I2C_ISR_ALERT_ofs EQU 13
I2C_ISR_ALERT_len EQU 1
I2C_ISR_TIMEOUT EQU 0x00001000 ; Timeout or t_low detection flag
I2C_ISR_TIMEOUT_ofs EQU 12
I2C_ISR_TIMEOUT_len EQU 1
I2C_ISR_PECERR EQU 0x00000800 ; PEC Error in reception
I2C_ISR_PECERR_ofs EQU 11
I2C_ISR_PECERR_len EQU 1
I2C_ISR_OVR EQU 0x00000400 ; Overrun/Underrun (slave mode)
I2C_ISR_OVR_ofs EQU 10
I2C_ISR_OVR_len EQU 1
I2C_ISR_ARLO EQU 0x00000200 ; Arbitration lost
I2C_ISR_ARLO_ofs EQU 9
I2C_ISR_ARLO_len EQU 1
I2C_ISR_BERR EQU 0x00000100 ; Bus error
I2C_ISR_BERR_ofs EQU 8
I2C_ISR_BERR_len EQU 1
I2C_ISR_TCR EQU 0x00000080 ; Transfer Complete Reload
I2C_ISR_TCR_ofs EQU 7
I2C_ISR_TCR_len EQU 1
I2C_ISR_TC EQU 0x00000040 ; Transfer Complete (master mode)
I2C_ISR_TC_ofs EQU 6
I2C_ISR_TC_len EQU 1
I2C_ISR_STOPF EQU 0x00000020 ; Stop detection flag
I2C_ISR_STOPF_ofs EQU 5
I2C_ISR_STOPF_len EQU 1
I2C_ISR_NACKF EQU 0x00000010 ; Not acknowledge received flag
I2C_ISR_NACKF_ofs EQU 4
I2C_ISR_NACKF_len EQU 1
I2C_ISR_ADDR EQU 0x00000008 ; Address matched (slave mode)
I2C_ISR_ADDR_ofs EQU 3
I2C_ISR_ADDR_len EQU 1
I2C_ISR_RXNE EQU 0x00000004 ; Receive data register not empty (receivers)
I2C_ISR_RXNE_ofs EQU 2
I2C_ISR_RXNE_len EQU 1
I2C_ISR_TXIS EQU 0x00000002 ; Transmit interrupt status (transmitters)
I2C_ISR_TXIS_ofs EQU 1
I2C_ISR_TXIS_len EQU 1
I2C_ISR_TXE EQU 0x00000001 ; Transmit data register empty (transmitters)
I2C_ISR_TXE_ofs EQU 0
I2C_ISR_TXE_len EQU 1
; I2C1_ICR fields:
I2C_ICR_ALERTCF EQU 0x00002000 ; Alert flag clear
I2C_ICR_ALERTCF_ofs EQU 13
I2C_ICR_ALERTCF_len EQU 1
I2C_ICR_TIMOUTCF EQU 0x00001000 ; Timeout detection flag clear
I2C_ICR_TIMOUTCF_ofs EQU 12
I2C_ICR_TIMOUTCF_len EQU 1
I2C_ICR_PECCF EQU 0x00000800 ; PEC Error flag clear
I2C_ICR_PECCF_ofs EQU 11
I2C_ICR_PECCF_len EQU 1
I2C_ICR_OVRCF EQU 0x00000400 ; Overrun/Underrun flag clear
I2C_ICR_OVRCF_ofs EQU 10
I2C_ICR_OVRCF_len EQU 1
I2C_ICR_ARLOCF EQU 0x00000200 ; Arbitration lost flag clear
I2C_ICR_ARLOCF_ofs EQU 9
I2C_ICR_ARLOCF_len EQU 1
I2C_ICR_BERRCF EQU 0x00000100 ; Bus error flag clear
I2C_ICR_BERRCF_ofs EQU 8
I2C_ICR_BERRCF_len EQU 1
I2C_ICR_STOPCF EQU 0x00000020 ; Stop detection flag clear
I2C_ICR_STOPCF_ofs EQU 5
I2C_ICR_STOPCF_len EQU 1
I2C_ICR_NACKCF EQU 0x00000010 ; Not Acknowledge flag clear
I2C_ICR_NACKCF_ofs EQU 4
I2C_ICR_NACKCF_len EQU 1
I2C_ICR_ADDRCF EQU 0x00000008 ; Address Matched flag clear
I2C_ICR_ADDRCF_ofs EQU 3
I2C_ICR_ADDRCF_len EQU 1
; I2C1_PECR fields:
I2C_PECR_PEC EQU 0x000000ff ; Packet error checking register
I2C_PECR_PEC_ofs EQU 0
I2C_PECR_PEC_len EQU 8
; I2C1_RXDR fields:
I2C_RXDR_RXDATA EQU 0x000000ff ; 8-bit receive data
I2C_RXDR_RXDATA_ofs EQU 0
I2C_RXDR_RXDATA_len EQU 8
; I2C1_TXDR fields:
I2C_TXDR_TXDATA EQU 0x000000ff ; 8-bit transmit data
I2C_TXDR_TXDATA_ofs EQU 0
I2C_TXDR_TXDATA_len EQU 8
; ---- I2C2 --------------------------------------------------
; Desc: None
; I2C2 base address:
I2C2_BASE EQU 0x40005800
; I2C2 registers:
I2C2_CR1 EQU (I2C2_BASE + 0x0) ; Control register 1
I2C2_CR2 EQU (I2C2_BASE + 0x4) ; Control register 2
I2C2_OAR1 EQU (I2C2_BASE + 0x8) ; Own address register 1
I2C2_OAR2 EQU (I2C2_BASE + 0xc) ; Own address register 2
I2C2_TIMINGR EQU (I2C2_BASE + 0x10) ; Timing register
I2C2_TIMEOUTR EQU (I2C2_BASE + 0x14) ; Status register 1
I2C2_ISR EQU (I2C2_BASE + 0x18) ; Interrupt and Status register
I2C2_ICR EQU (I2C2_BASE + 0x1c) ; Interrupt clear register
I2C2_PECR EQU (I2C2_BASE + 0x20) ; PEC register
I2C2_RXDR EQU (I2C2_BASE + 0x24) ; Receive data register
I2C2_TXDR EQU (I2C2_BASE + 0x28) ; Transmit data register
; Fields the same as in the first instance.
; ---- IWDG --------------------------------------------------
; Desc: Independent watchdog
; IWDG base address:
IWDG_BASE EQU 0x40003000
; IWDG registers:
IWDG_KR EQU (IWDG_BASE + 0x0) ; Key register
IWDG_PR EQU (IWDG_BASE + 0x4) ; Prescaler register
IWDG_RLR EQU (IWDG_BASE + 0x8) ; Reload register
IWDG_SR EQU (IWDG_BASE + 0xc) ; Status register
IWDG_WINR EQU (IWDG_BASE + 0x10) ; Window register
; IWDG_KR fields:
IWDG_KR_KEY EQU 0x0000ffff ; Key value
IWDG_KR_KEY_ofs EQU 0
IWDG_KR_KEY_len EQU 16
; IWDG_PR fields:
IWDG_PR_PR EQU 0x00000007 ; Prescaler divider
IWDG_PR_PR_ofs EQU 0
IWDG_PR_PR_len EQU 3
; IWDG_RLR fields:
IWDG_RLR_RL EQU 0x00000fff ; Watchdog counter reload value
IWDG_RLR_RL_ofs EQU 0
IWDG_RLR_RL_len EQU 12
; IWDG_SR fields:
IWDG_SR_PVU EQU 0x00000001 ; Watchdog prescaler value update
IWDG_SR_PVU_ofs EQU 0
IWDG_SR_PVU_len EQU 1
IWDG_SR_RVU EQU 0x00000002 ; Watchdog counter reload value update
IWDG_SR_RVU_ofs EQU 1
IWDG_SR_RVU_len EQU 1
IWDG_SR_WVU EQU 0x00000004 ; Watchdog counter window value update
IWDG_SR_WVU_ofs EQU 2
IWDG_SR_WVU_len EQU 1
; IWDG_WINR fields:
IWDG_WINR_WIN EQU 0x00000fff ; Watchdog counter window value
IWDG_WINR_WIN_ofs EQU 0
IWDG_WINR_WIN_len EQU 12
; ---- WWDG --------------------------------------------------
; Desc: Window watchdog
; WWDG base address:
WWDG_BASE EQU 0x40002c00
; WWDG registers:
WWDG_CR EQU (WWDG_BASE + 0x0) ; Control register
WWDG_CFR EQU (WWDG_BASE + 0x4) ; Configuration register
WWDG_SR EQU (WWDG_BASE + 0x8) ; Status register
; WWDG_CR fields:
WWDG_CR_T EQU 0x0000007f ; 7-bit counter
WWDG_CR_T_ofs EQU 0
WWDG_CR_T_len EQU 7
WWDG_CR_WDGA EQU 0x00000080 ; Activation bit
WWDG_CR_WDGA_ofs EQU 7
WWDG_CR_WDGA_len EQU 1
; WWDG_CFR fields:
WWDG_CFR_EWI EQU 0x00000200 ; Early wakeup interrupt
WWDG_CFR_EWI_ofs EQU 9
WWDG_CFR_EWI_len EQU 1
WWDG_CFR_WDGTB EQU 0x00000180 ; Timer base
WWDG_CFR_WDGTB_ofs EQU 7
WWDG_CFR_WDGTB_len EQU 2
WWDG_CFR_W EQU 0x0000007f ; 7-bit window value
WWDG_CFR_W_ofs EQU 0
WWDG_CFR_W_len EQU 7
; WWDG_SR fields:
WWDG_SR_EWIF EQU 0x00000001 ; Early wakeup interrupt flag
WWDG_SR_EWIF_ofs EQU 0
WWDG_SR_EWIF_len EQU 1
; ---- RTC ---------------------------------------------------
; Desc: Real-time clock
; RTC base address:
RTC_BASE EQU 0x40002800
; RTC registers:
RTC_TR EQU (RTC_BASE + 0x0) ; time register
RTC_DR EQU (RTC_BASE + 0x4) ; date register
RTC_CR EQU (RTC_BASE + 0x8) ; control register
RTC_ISR EQU (RTC_BASE + 0xc) ; initialization and status register
RTC_PRER EQU (RTC_BASE + 0x10) ; prescaler register
RTC_WUTR EQU (RTC_BASE + 0x14) ; wakeup timer register
RTC_ALRMAR EQU (RTC_BASE + 0x1c) ; alarm A register
RTC_ALRMBR EQU (RTC_BASE + 0x20) ; alarm B register
RTC_WPR EQU (RTC_BASE + 0x24) ; write protection register
RTC_SSR EQU (RTC_BASE + 0x28) ; sub second register
RTC_SHIFTR EQU (RTC_BASE + 0x2c) ; shift control register
RTC_TSTR EQU (RTC_BASE + 0x30) ; time stamp time register
RTC_TSDR EQU (RTC_BASE + 0x34) ; time stamp date register
RTC_TSSSR EQU (RTC_BASE + 0x38) ; timestamp sub second register
RTC_CALR EQU (RTC_BASE + 0x3c) ; calibration register
RTC_TAFCR EQU (RTC_BASE + 0x40) ; tamper and alternate function configuration register
RTC_ALRMASSR EQU (RTC_BASE + 0x44) ; alarm A sub second register
RTC_ALRMBSSR EQU (RTC_BASE + 0x48) ; alarm B sub second register
RTC_BKP0R EQU (RTC_BASE + 0x50) ; backup register
RTC_BKP1R EQU (RTC_BASE + 0x54) ; backup register
RTC_BKP2R EQU (RTC_BASE + 0x58) ; backup register
RTC_BKP3R EQU (RTC_BASE + 0x5c) ; backup register
RTC_BKP4R EQU (RTC_BASE + 0x60) ; backup register
RTC_BKP5R EQU (RTC_BASE + 0x64) ; backup register
RTC_BKP6R EQU (RTC_BASE + 0x68) ; backup register
RTC_BKP7R EQU (RTC_BASE + 0x6c) ; backup register
RTC_BKP8R EQU (RTC_BASE + 0x70) ; backup register
RTC_BKP9R EQU (RTC_BASE + 0x74) ; backup register
RTC_BKP10R EQU (RTC_BASE + 0x78) ; backup register
RTC_BKP11R EQU (RTC_BASE + 0x7c) ; backup register
RTC_BKP12R EQU (RTC_BASE + 0x80) ; backup register
RTC_BKP13R EQU (RTC_BASE + 0x84) ; backup register
RTC_BKP14R EQU (RTC_BASE + 0x88) ; backup register
RTC_BKP15R EQU (RTC_BASE + 0x8c) ; backup register
RTC_BKP16R EQU (RTC_BASE + 0x90) ; backup register
RTC_BKP17R EQU (RTC_BASE + 0x94) ; backup register
RTC_BKP18R EQU (RTC_BASE + 0x98) ; backup register
RTC_BKP19R EQU (RTC_BASE + 0x9c) ; backup register
RTC_BKP20R EQU (RTC_BASE + 0xa0) ; backup register
RTC_BKP21R EQU (RTC_BASE + 0xa4) ; backup register
RTC_BKP22R EQU (RTC_BASE + 0xa8) ; backup register
RTC_BKP23R EQU (RTC_BASE + 0xac) ; backup register
RTC_BKP24R EQU (RTC_BASE + 0xb0) ; backup register
RTC_BKP25R EQU (RTC_BASE + 0xb4) ; backup register
RTC_BKP26R EQU (RTC_BASE + 0xb8) ; backup register
RTC_BKP27R EQU (RTC_BASE + 0xbc) ; backup register
RTC_BKP28R EQU (RTC_BASE + 0xc0) ; backup register
RTC_BKP29R EQU (RTC_BASE + 0xc4) ; backup register
RTC_BKP30R EQU (RTC_BASE + 0xc8) ; backup register
RTC_BKP31R EQU (RTC_BASE + 0xcc) ; backup register
; RTC_TR fields:
RTC_TR_PM EQU 0x00400000 ; AM/PM notation
RTC_TR_PM_ofs EQU 22
RTC_TR_PM_len EQU 1
RTC_TR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_TR_HT_ofs EQU 20
RTC_TR_HT_len EQU 2
RTC_TR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_TR_HU_ofs EQU 16
RTC_TR_HU_len EQU 4
RTC_TR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_TR_MNT_ofs EQU 12
RTC_TR_MNT_len EQU 3
RTC_TR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_TR_MNU_ofs EQU 8
RTC_TR_MNU_len EQU 4
RTC_TR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_TR_ST_ofs EQU 4
RTC_TR_ST_len EQU 3
RTC_TR_SU EQU 0x0000000f ; Second units in BCD format
RTC_TR_SU_ofs EQU 0
RTC_TR_SU_len EQU 4
; RTC_DR fields:
RTC_DR_YT EQU 0x00f00000 ; Year tens in BCD format
RTC_DR_YT_ofs EQU 20
RTC_DR_YT_len EQU 4
RTC_DR_YU EQU 0x000f0000 ; Year units in BCD format
RTC_DR_YU_ofs EQU 16
RTC_DR_YU_len EQU 4
RTC_DR_WDU EQU 0x0000e000 ; Week day units
RTC_DR_WDU_ofs EQU 13
RTC_DR_WDU_len EQU 3
RTC_DR_MT EQU 0x00001000 ; Month tens in BCD format
RTC_DR_MT_ofs EQU 12
RTC_DR_MT_len EQU 1
RTC_DR_MU EQU 0x00000f00 ; Month units in BCD format
RTC_DR_MU_ofs EQU 8
RTC_DR_MU_len EQU 4
RTC_DR_DT EQU 0x00000030 ; Date tens in BCD format
RTC_DR_DT_ofs EQU 4
RTC_DR_DT_len EQU 2
RTC_DR_DU EQU 0x0000000f ; Date units in BCD format
RTC_DR_DU_ofs EQU 0
RTC_DR_DU_len EQU 4
; RTC_CR fields:
RTC_CR_WCKSEL EQU 0x00000007 ; Wakeup clock selection
RTC_CR_WCKSEL_ofs EQU 0
RTC_CR_WCKSEL_len EQU 3
RTC_CR_TSEDGE EQU 0x00000008 ; Time-stamp event active edge
RTC_CR_TSEDGE_ofs EQU 3
RTC_CR_TSEDGE_len EQU 1
RTC_CR_REFCKON EQU 0x00000010 ; Reference clock detection enable (50 or 60 Hz)
RTC_CR_REFCKON_ofs EQU 4
RTC_CR_REFCKON_len EQU 1
RTC_CR_BYPSHAD EQU 0x00000020 ; Bypass the shadow registers
RTC_CR_BYPSHAD_ofs EQU 5
RTC_CR_BYPSHAD_len EQU 1
RTC_CR_FMT EQU 0x00000040 ; Hour format
RTC_CR_FMT_ofs EQU 6
RTC_CR_FMT_len EQU 1
RTC_CR_ALRAE EQU 0x00000100 ; Alarm A enable
RTC_CR_ALRAE_ofs EQU 8
RTC_CR_ALRAE_len EQU 1
RTC_CR_ALRBE EQU 0x00000200 ; Alarm B enable
RTC_CR_ALRBE_ofs EQU 9
RTC_CR_ALRBE_len EQU 1
RTC_CR_WUTE EQU 0x00000400 ; Wakeup timer enable
RTC_CR_WUTE_ofs EQU 10
RTC_CR_WUTE_len EQU 1
RTC_CR_TSE EQU 0x00000800 ; Time stamp enable
RTC_CR_TSE_ofs EQU 11
RTC_CR_TSE_len EQU 1
RTC_CR_ALRAIE EQU 0x00001000 ; Alarm A interrupt enable
RTC_CR_ALRAIE_ofs EQU 12
RTC_CR_ALRAIE_len EQU 1
RTC_CR_ALRBIE EQU 0x00002000 ; Alarm B interrupt enable
RTC_CR_ALRBIE_ofs EQU 13
RTC_CR_ALRBIE_len EQU 1
RTC_CR_WUTIE EQU 0x00004000 ; Wakeup timer interrupt enable
RTC_CR_WUTIE_ofs EQU 14
RTC_CR_WUTIE_len EQU 1
RTC_CR_TSIE EQU 0x00008000 ; Time-stamp interrupt enable
RTC_CR_TSIE_ofs EQU 15
RTC_CR_TSIE_len EQU 1
RTC_CR_ADD1H EQU 0x00010000 ; Add 1 hour (summer time change)
RTC_CR_ADD1H_ofs EQU 16
RTC_CR_ADD1H_len EQU 1
RTC_CR_SUB1H EQU 0x00020000 ; Subtract 1 hour (winter time change)
RTC_CR_SUB1H_ofs EQU 17
RTC_CR_SUB1H_len EQU 1
RTC_CR_BKP EQU 0x00040000 ; Backup
RTC_CR_BKP_ofs EQU 18
RTC_CR_BKP_len EQU 1
RTC_CR_COSEL EQU 0x00080000 ; Calibration output selection
RTC_CR_COSEL_ofs EQU 19
RTC_CR_COSEL_len EQU 1
RTC_CR_POL EQU 0x00100000 ; Output polarity
RTC_CR_POL_ofs EQU 20
RTC_CR_POL_len EQU 1
RTC_CR_OSEL EQU 0x00600000 ; Output selection
RTC_CR_OSEL_ofs EQU 21
RTC_CR_OSEL_len EQU 2
RTC_CR_COE EQU 0x00800000 ; Calibration output enable
RTC_CR_COE_ofs EQU 23
RTC_CR_COE_len EQU 1
; RTC_ISR fields:
RTC_ISR_ALRAWF EQU 0x00000001 ; Alarm A write flag
RTC_ISR_ALRAWF_ofs EQU 0
RTC_ISR_ALRAWF_len EQU 1
RTC_ISR_ALRBWF EQU 0x00000002 ; Alarm B write flag
RTC_ISR_ALRBWF_ofs EQU 1
RTC_ISR_ALRBWF_len EQU 1
RTC_ISR_WUTWF EQU 0x00000004 ; Wakeup timer write flag
RTC_ISR_WUTWF_ofs EQU 2
RTC_ISR_WUTWF_len EQU 1
RTC_ISR_SHPF EQU 0x00000008 ; Shift operation pending
RTC_ISR_SHPF_ofs EQU 3
RTC_ISR_SHPF_len EQU 1
RTC_ISR_INITS EQU 0x00000010 ; Initialization status flag
RTC_ISR_INITS_ofs EQU 4
RTC_ISR_INITS_len EQU 1
RTC_ISR_RSF EQU 0x00000020 ; Registers synchronization flag
RTC_ISR_RSF_ofs EQU 5
RTC_ISR_RSF_len EQU 1
RTC_ISR_INITF EQU 0x00000040 ; Initialization flag
RTC_ISR_INITF_ofs EQU 6
RTC_ISR_INITF_len EQU 1
RTC_ISR_INIT EQU 0x00000080 ; Initialization mode
RTC_ISR_INIT_ofs EQU 7
RTC_ISR_INIT_len EQU 1
RTC_ISR_ALRAF EQU 0x00000100 ; Alarm A flag
RTC_ISR_ALRAF_ofs EQU 8
RTC_ISR_ALRAF_len EQU 1
RTC_ISR_ALRBF EQU 0x00000200 ; Alarm B flag
RTC_ISR_ALRBF_ofs EQU 9
RTC_ISR_ALRBF_len EQU 1
RTC_ISR_WUTF EQU 0x00000400 ; Wakeup timer flag
RTC_ISR_WUTF_ofs EQU 10
RTC_ISR_WUTF_len EQU 1
RTC_ISR_TSF EQU 0x00000800 ; Time-stamp flag
RTC_ISR_TSF_ofs EQU 11
RTC_ISR_TSF_len EQU 1
RTC_ISR_TSOVF EQU 0x00001000 ; Time-stamp overflow flag
RTC_ISR_TSOVF_ofs EQU 12
RTC_ISR_TSOVF_len EQU 1
RTC_ISR_TAMP1F EQU 0x00002000 ; Tamper detection flag
RTC_ISR_TAMP1F_ofs EQU 13
RTC_ISR_TAMP1F_len EQU 1
RTC_ISR_TAMP2F EQU 0x00004000 ; RTC_TAMP2 detection flag
RTC_ISR_TAMP2F_ofs EQU 14
RTC_ISR_TAMP2F_len EQU 1
RTC_ISR_TAMP3F EQU 0x00008000 ; RTC_TAMP3 detection flag
RTC_ISR_TAMP3F_ofs EQU 15
RTC_ISR_TAMP3F_len EQU 1
RTC_ISR_RECALPF EQU 0x00010000 ; Recalibration pending Flag
RTC_ISR_RECALPF_ofs EQU 16
RTC_ISR_RECALPF_len EQU 1
; RTC_PRER fields:
RTC_PRER_PREDIV_A EQU 0x007f0000 ; Asynchronous prescaler factor
RTC_PRER_PREDIV_A_ofs EQU 16
RTC_PRER_PREDIV_A_len EQU 7
RTC_PRER_PREDIV_S EQU 0x00007fff ; Synchronous prescaler factor
RTC_PRER_PREDIV_S_ofs EQU 0
RTC_PRER_PREDIV_S_len EQU 15
; RTC_WUTR fields:
RTC_WUTR_WUT EQU 0x0000ffff ; Wakeup auto-reload value bits
RTC_WUTR_WUT_ofs EQU 0
RTC_WUTR_WUT_len EQU 16
; RTC_ALRMAR fields:
RTC_ALRMAR_MSK4 EQU 0x80000000 ; Alarm A date mask
RTC_ALRMAR_MSK4_ofs EQU 31
RTC_ALRMAR_MSK4_len EQU 1
RTC_ALRMAR_WDSEL EQU 0x40000000 ; Week day selection
RTC_ALRMAR_WDSEL_ofs EQU 30
RTC_ALRMAR_WDSEL_len EQU 1
RTC_ALRMAR_DT EQU 0x30000000 ; Date tens in BCD format
RTC_ALRMAR_DT_ofs EQU 28
RTC_ALRMAR_DT_len EQU 2
RTC_ALRMAR_DU EQU 0x0f000000 ; Date units or day in BCD format
RTC_ALRMAR_DU_ofs EQU 24
RTC_ALRMAR_DU_len EQU 4
RTC_ALRMAR_MSK3 EQU 0x00800000 ; Alarm A hours mask
RTC_ALRMAR_MSK3_ofs EQU 23
RTC_ALRMAR_MSK3_len EQU 1
RTC_ALRMAR_PM EQU 0x00400000 ; AM/PM notation
RTC_ALRMAR_PM_ofs EQU 22
RTC_ALRMAR_PM_len EQU 1
RTC_ALRMAR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_ALRMAR_HT_ofs EQU 20
RTC_ALRMAR_HT_len EQU 2
RTC_ALRMAR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_ALRMAR_HU_ofs EQU 16
RTC_ALRMAR_HU_len EQU 4
RTC_ALRMAR_MSK2 EQU 0x00008000 ; Alarm A minutes mask
RTC_ALRMAR_MSK2_ofs EQU 15
RTC_ALRMAR_MSK2_len EQU 1
RTC_ALRMAR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_ALRMAR_MNT_ofs EQU 12
RTC_ALRMAR_MNT_len EQU 3
RTC_ALRMAR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_ALRMAR_MNU_ofs EQU 8
RTC_ALRMAR_MNU_len EQU 4
RTC_ALRMAR_MSK1 EQU 0x00000080 ; Alarm A seconds mask
RTC_ALRMAR_MSK1_ofs EQU 7
RTC_ALRMAR_MSK1_len EQU 1
RTC_ALRMAR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_ALRMAR_ST_ofs EQU 4
RTC_ALRMAR_ST_len EQU 3
RTC_ALRMAR_SU EQU 0x0000000f ; Second units in BCD format
RTC_ALRMAR_SU_ofs EQU 0
RTC_ALRMAR_SU_len EQU 4
; RTC_ALRMBR fields:
RTC_ALRMBR_MSK4 EQU 0x80000000 ; Alarm B date mask
RTC_ALRMBR_MSK4_ofs EQU 31
RTC_ALRMBR_MSK4_len EQU 1
RTC_ALRMBR_WDSEL EQU 0x40000000 ; Week day selection
RTC_ALRMBR_WDSEL_ofs EQU 30
RTC_ALRMBR_WDSEL_len EQU 1
RTC_ALRMBR_DT EQU 0x30000000 ; Date tens in BCD format
RTC_ALRMBR_DT_ofs EQU 28
RTC_ALRMBR_DT_len EQU 2
RTC_ALRMBR_DU EQU 0x0f000000 ; Date units or day in BCD format
RTC_ALRMBR_DU_ofs EQU 24
RTC_ALRMBR_DU_len EQU 4
RTC_ALRMBR_MSK3 EQU 0x00800000 ; Alarm B hours mask
RTC_ALRMBR_MSK3_ofs EQU 23
RTC_ALRMBR_MSK3_len EQU 1
RTC_ALRMBR_PM EQU 0x00400000 ; AM/PM notation
RTC_ALRMBR_PM_ofs EQU 22
RTC_ALRMBR_PM_len EQU 1
RTC_ALRMBR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_ALRMBR_HT_ofs EQU 20
RTC_ALRMBR_HT_len EQU 2
RTC_ALRMBR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_ALRMBR_HU_ofs EQU 16
RTC_ALRMBR_HU_len EQU 4
RTC_ALRMBR_MSK2 EQU 0x00008000 ; Alarm B minutes mask
RTC_ALRMBR_MSK2_ofs EQU 15
RTC_ALRMBR_MSK2_len EQU 1
RTC_ALRMBR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_ALRMBR_MNT_ofs EQU 12
RTC_ALRMBR_MNT_len EQU 3
RTC_ALRMBR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_ALRMBR_MNU_ofs EQU 8
RTC_ALRMBR_MNU_len EQU 4
RTC_ALRMBR_MSK1 EQU 0x00000080 ; Alarm B seconds mask
RTC_ALRMBR_MSK1_ofs EQU 7
RTC_ALRMBR_MSK1_len EQU 1
RTC_ALRMBR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_ALRMBR_ST_ofs EQU 4
RTC_ALRMBR_ST_len EQU 3
RTC_ALRMBR_SU EQU 0x0000000f ; Second units in BCD format
RTC_ALRMBR_SU_ofs EQU 0
RTC_ALRMBR_SU_len EQU 4
; RTC_WPR fields:
RTC_WPR_KEY EQU 0x000000ff ; Write protection key
RTC_WPR_KEY_ofs EQU 0
RTC_WPR_KEY_len EQU 8
; RTC_SSR fields:
RTC_SSR_SS EQU 0x0000ffff ; Sub second value
RTC_SSR_SS_ofs EQU 0
RTC_SSR_SS_len EQU 16
; RTC_SHIFTR fields:
RTC_SHIFTR_ADD1S EQU 0x80000000 ; Add one second
RTC_SHIFTR_ADD1S_ofs EQU 31
RTC_SHIFTR_ADD1S_len EQU 1
RTC_SHIFTR_SUBFS EQU 0x00007fff ; Subtract a fraction of a second
RTC_SHIFTR_SUBFS_ofs EQU 0
RTC_SHIFTR_SUBFS_len EQU 15
; RTC_TSTR fields:
RTC_TSTR_SU EQU 0x0000000f ; Second units in BCD format
RTC_TSTR_SU_ofs EQU 0
RTC_TSTR_SU_len EQU 4
RTC_TSTR_ST EQU 0x00000070 ; Second tens in BCD format
RTC_TSTR_ST_ofs EQU 4
RTC_TSTR_ST_len EQU 3
RTC_TSTR_MNU EQU 0x00000f00 ; Minute units in BCD format
RTC_TSTR_MNU_ofs EQU 8
RTC_TSTR_MNU_len EQU 4
RTC_TSTR_MNT EQU 0x00007000 ; Minute tens in BCD format
RTC_TSTR_MNT_ofs EQU 12
RTC_TSTR_MNT_len EQU 3
RTC_TSTR_HU EQU 0x000f0000 ; Hour units in BCD format
RTC_TSTR_HU_ofs EQU 16
RTC_TSTR_HU_len EQU 4
RTC_TSTR_HT EQU 0x00300000 ; Hour tens in BCD format
RTC_TSTR_HT_ofs EQU 20
RTC_TSTR_HT_len EQU 2
RTC_TSTR_PM EQU 0x00400000 ; AM/PM notation
RTC_TSTR_PM_ofs EQU 22
RTC_TSTR_PM_len EQU 1
; RTC_TSDR fields:
RTC_TSDR_WDU EQU 0x0000e000 ; Week day units
RTC_TSDR_WDU_ofs EQU 13
RTC_TSDR_WDU_len EQU 3
RTC_TSDR_MT EQU 0x00001000 ; Month tens in BCD format
RTC_TSDR_MT_ofs EQU 12
RTC_TSDR_MT_len EQU 1
RTC_TSDR_MU EQU 0x00000f00 ; Month units in BCD format
RTC_TSDR_MU_ofs EQU 8
RTC_TSDR_MU_len EQU 4
RTC_TSDR_DT EQU 0x00000030 ; Date tens in BCD format
RTC_TSDR_DT_ofs EQU 4
RTC_TSDR_DT_len EQU 2
RTC_TSDR_DU EQU 0x0000000f ; Date units in BCD format
RTC_TSDR_DU_ofs EQU 0
RTC_TSDR_DU_len EQU 4
; RTC_TSSSR fields:
RTC_TSSSR_SS EQU 0x0000ffff ; Sub second value
RTC_TSSSR_SS_ofs EQU 0
RTC_TSSSR_SS_len EQU 16
; RTC_CALR fields:
RTC_CALR_CALP EQU 0x00008000 ; Increase frequency of RTC by 488.5 ppm
RTC_CALR_CALP_ofs EQU 15
RTC_CALR_CALP_len EQU 1
RTC_CALR_CALW8 EQU 0x00004000 ; Use an 8-second calibration cycle period
RTC_CALR_CALW8_ofs EQU 14
RTC_CALR_CALW8_len EQU 1
RTC_CALR_CALW16 EQU 0x00002000 ; Use a 16-second calibration cycle period
RTC_CALR_CALW16_ofs EQU 13
RTC_CALR_CALW16_len EQU 1
RTC_CALR_CALM EQU 0x000001ff ; Calibration minus
RTC_CALR_CALM_ofs EQU 0
RTC_CALR_CALM_len EQU 9
; RTC_TAFCR fields:
RTC_TAFCR_TAMP1E EQU 0x00000001 ; Tamper 1 detection enable
RTC_TAFCR_TAMP1E_ofs EQU 0
RTC_TAFCR_TAMP1E_len EQU 1
RTC_TAFCR_TAMP1TRG EQU 0x00000002 ; Active level for tamper 1
RTC_TAFCR_TAMP1TRG_ofs EQU 1
RTC_TAFCR_TAMP1TRG_len EQU 1
RTC_TAFCR_TAMPIE EQU 0x00000004 ; Tamper interrupt enable
RTC_TAFCR_TAMPIE_ofs EQU 2
RTC_TAFCR_TAMPIE_len EQU 1
RTC_TAFCR_TAMP2E EQU 0x00000008 ; Tamper 2 detection enable
RTC_TAFCR_TAMP2E_ofs EQU 3
RTC_TAFCR_TAMP2E_len EQU 1
RTC_TAFCR_TAMP2TRG EQU 0x00000010 ; Active level for tamper 2
RTC_TAFCR_TAMP2TRG_ofs EQU 4
RTC_TAFCR_TAMP2TRG_len EQU 1
RTC_TAFCR_TAMP3E EQU 0x00000020 ; Tamper 3 detection enable
RTC_TAFCR_TAMP3E_ofs EQU 5
RTC_TAFCR_TAMP3E_len EQU 1
RTC_TAFCR_TAMP3TRG EQU 0x00000040 ; Active level for tamper 3
RTC_TAFCR_TAMP3TRG_ofs EQU 6
RTC_TAFCR_TAMP3TRG_len EQU 1
RTC_TAFCR_TAMPTS EQU 0x00000080 ; Activate timestamp on tamper detection event
RTC_TAFCR_TAMPTS_ofs EQU 7
RTC_TAFCR_TAMPTS_len EQU 1
RTC_TAFCR_TAMPFREQ EQU 0x00000700 ; Tamper sampling frequency
RTC_TAFCR_TAMPFREQ_ofs EQU 8
RTC_TAFCR_TAMPFREQ_len EQU 3
RTC_TAFCR_TAMPFLT EQU 0x00001800 ; Tamper filter count
RTC_TAFCR_TAMPFLT_ofs EQU 11
RTC_TAFCR_TAMPFLT_len EQU 2
RTC_TAFCR_TAMPPRCH EQU 0x00006000 ; Tamper precharge duration
RTC_TAFCR_TAMPPRCH_ofs EQU 13
RTC_TAFCR_TAMPPRCH_len EQU 2
RTC_TAFCR_TAMPPUDIS EQU 0x00008000 ; TAMPER pull-up disable
RTC_TAFCR_TAMPPUDIS_ofs EQU 15
RTC_TAFCR_TAMPPUDIS_len EQU 1
RTC_TAFCR_PC13VALUE EQU 0x00040000 ; PC13 value
RTC_TAFCR_PC13VALUE_ofs EQU 18
RTC_TAFCR_PC13VALUE_len EQU 1
RTC_TAFCR_PC13MODE EQU 0x00080000 ; PC13 mode
RTC_TAFCR_PC13MODE_ofs EQU 19
RTC_TAFCR_PC13MODE_len EQU 1
RTC_TAFCR_PC14VALUE EQU 0x00100000 ; PC14 value
RTC_TAFCR_PC14VALUE_ofs EQU 20
RTC_TAFCR_PC14VALUE_len EQU 1
RTC_TAFCR_PC14MODE EQU 0x00200000 ; PC 14 mode
RTC_TAFCR_PC14MODE_ofs EQU 21
RTC_TAFCR_PC14MODE_len EQU 1
RTC_TAFCR_PC15VALUE EQU 0x00400000 ; PC15 value
RTC_TAFCR_PC15VALUE_ofs EQU 22
RTC_TAFCR_PC15VALUE_len EQU 1
RTC_TAFCR_PC15MODE EQU 0x00800000 ; PC15 mode
RTC_TAFCR_PC15MODE_ofs EQU 23
RTC_TAFCR_PC15MODE_len EQU 1
; RTC_ALRMASSR fields:
RTC_ALRMASSR_MASKSS EQU 0x0f000000 ; Mask the most-significant bits starting at this bit
RTC_ALRMASSR_MASKSS_ofs EQU 24
RTC_ALRMASSR_MASKSS_len EQU 4
RTC_ALRMASSR_SS EQU 0x00007fff ; Sub seconds value
RTC_ALRMASSR_SS_ofs EQU 0
RTC_ALRMASSR_SS_len EQU 15
; RTC_ALRMBSSR fields:
RTC_ALRMBSSR_MASKSS EQU 0x0f000000 ; Mask the most-significant bits starting at this bit
RTC_ALRMBSSR_MASKSS_ofs EQU 24
RTC_ALRMBSSR_MASKSS_len EQU 4
RTC_ALRMBSSR_SS EQU 0x00007fff ; Sub seconds value
RTC_ALRMBSSR_SS_ofs EQU 0
RTC_ALRMBSSR_SS_len EQU 15
; RTC_BKP0R fields:
RTC_BKP0R_BKP EQU 0xffffffff ; BKP
RTC_BKP0R_BKP_ofs EQU 0
RTC_BKP0R_BKP_len EQU 32
; RTC_BKP1R fields:
RTC_BKP1R_BKP EQU 0xffffffff ; BKP
RTC_BKP1R_BKP_ofs EQU 0
RTC_BKP1R_BKP_len EQU 32
; RTC_BKP2R fields:
RTC_BKP2R_BKP EQU 0xffffffff ; BKP
RTC_BKP2R_BKP_ofs EQU 0
RTC_BKP2R_BKP_len EQU 32
; RTC_BKP3R fields:
RTC_BKP3R_BKP EQU 0xffffffff ; BKP
RTC_BKP3R_BKP_ofs EQU 0
RTC_BKP3R_BKP_len EQU 32
; RTC_BKP4R fields:
RTC_BKP4R_BKP EQU 0xffffffff ; BKP
RTC_BKP4R_BKP_ofs EQU 0
RTC_BKP4R_BKP_len EQU 32
; RTC_BKP5R fields:
RTC_BKP5R_BKP EQU 0xffffffff ; BKP
RTC_BKP5R_BKP_ofs EQU 0
RTC_BKP5R_BKP_len EQU 32
; RTC_BKP6R fields:
RTC_BKP6R_BKP EQU 0xffffffff ; BKP
RTC_BKP6R_BKP_ofs EQU 0
RTC_BKP6R_BKP_len EQU 32
; RTC_BKP7R fields:
RTC_BKP7R_BKP EQU 0xffffffff ; BKP
RTC_BKP7R_BKP_ofs EQU 0
RTC_BKP7R_BKP_len EQU 32
; RTC_BKP8R fields:
RTC_BKP8R_BKP EQU 0xffffffff ; BKP
RTC_BKP8R_BKP_ofs EQU 0
RTC_BKP8R_BKP_len EQU 32
; RTC_BKP9R fields:
RTC_BKP9R_BKP EQU 0xffffffff ; BKP
RTC_BKP9R_BKP_ofs EQU 0
RTC_BKP9R_BKP_len EQU 32
; RTC_BKP10R fields:
RTC_BKP10R_BKP EQU 0xffffffff ; BKP
RTC_BKP10R_BKP_ofs EQU 0
RTC_BKP10R_BKP_len EQU 32
; RTC_BKP11R fields:
RTC_BKP11R_BKP EQU 0xffffffff ; BKP
RTC_BKP11R_BKP_ofs EQU 0
RTC_BKP11R_BKP_len EQU 32
; RTC_BKP12R fields:
RTC_BKP12R_BKP EQU 0xffffffff ; BKP
RTC_BKP12R_BKP_ofs EQU 0
RTC_BKP12R_BKP_len EQU 32
; RTC_BKP13R fields:
RTC_BKP13R_BKP EQU 0xffffffff ; BKP
RTC_BKP13R_BKP_ofs EQU 0
RTC_BKP13R_BKP_len EQU 32
; RTC_BKP14R fields:
RTC_BKP14R_BKP EQU 0xffffffff ; BKP
RTC_BKP14R_BKP_ofs EQU 0
RTC_BKP14R_BKP_len EQU 32
; RTC_BKP15R fields:
RTC_BKP15R_BKP EQU 0xffffffff ; BKP
RTC_BKP15R_BKP_ofs EQU 0
RTC_BKP15R_BKP_len EQU 32
; RTC_BKP16R fields:
RTC_BKP16R_BKP EQU 0xffffffff ; BKP
RTC_BKP16R_BKP_ofs EQU 0
RTC_BKP16R_BKP_len EQU 32
; RTC_BKP17R fields:
RTC_BKP17R_BKP EQU 0xffffffff ; BKP
RTC_BKP17R_BKP_ofs EQU 0
RTC_BKP17R_BKP_len EQU 32
; RTC_BKP18R fields:
RTC_BKP18R_BKP EQU 0xffffffff ; BKP
RTC_BKP18R_BKP_ofs EQU 0
RTC_BKP18R_BKP_len EQU 32
; RTC_BKP19R fields:
RTC_BKP19R_BKP EQU 0xffffffff ; BKP
RTC_BKP19R_BKP_ofs EQU 0
RTC_BKP19R_BKP_len EQU 32
; RTC_BKP20R fields:
RTC_BKP20R_BKP EQU 0xffffffff ; BKP
RTC_BKP20R_BKP_ofs EQU 0
RTC_BKP20R_BKP_len EQU 32
; RTC_BKP21R fields:
RTC_BKP21R_BKP EQU 0xffffffff ; BKP
RTC_BKP21R_BKP_ofs EQU 0
RTC_BKP21R_BKP_len EQU 32
; RTC_BKP22R fields:
RTC_BKP22R_BKP EQU 0xffffffff ; BKP
RTC_BKP22R_BKP_ofs EQU 0
RTC_BKP22R_BKP_len EQU 32
; RTC_BKP23R fields:
RTC_BKP23R_BKP EQU 0xffffffff ; BKP
RTC_BKP23R_BKP_ofs EQU 0
RTC_BKP23R_BKP_len EQU 32
; RTC_BKP24R fields:
RTC_BKP24R_BKP EQU 0xffffffff ; BKP
RTC_BKP24R_BKP_ofs EQU 0
RTC_BKP24R_BKP_len EQU 32
; RTC_BKP25R fields:
RTC_BKP25R_BKP EQU 0xffffffff ; BKP
RTC_BKP25R_BKP_ofs EQU 0
RTC_BKP25R_BKP_len EQU 32
; RTC_BKP26R fields:
RTC_BKP26R_BKP EQU 0xffffffff ; BKP
RTC_BKP26R_BKP_ofs EQU 0
RTC_BKP26R_BKP_len EQU 32
; RTC_BKP27R fields:
RTC_BKP27R_BKP EQU 0xffffffff ; BKP
RTC_BKP27R_BKP_ofs EQU 0
RTC_BKP27R_BKP_len EQU 32
; RTC_BKP28R fields:
RTC_BKP28R_BKP EQU 0xffffffff ; BKP
RTC_BKP28R_BKP_ofs EQU 0
RTC_BKP28R_BKP_len EQU 32
; RTC_BKP29R fields:
RTC_BKP29R_BKP EQU 0xffffffff ; BKP
RTC_BKP29R_BKP_ofs EQU 0
RTC_BKP29R_BKP_len EQU 32
; RTC_BKP30R fields:
RTC_BKP30R_BKP EQU 0xffffffff ; BKP
RTC_BKP30R_BKP_ofs EQU 0
RTC_BKP30R_BKP_len EQU 32
; RTC_BKP31R fields:
RTC_BKP31R_BKP EQU 0xffffffff ; BKP
RTC_BKP31R_BKP_ofs EQU 0
RTC_BKP31R_BKP_len EQU 32
; ---- TIM6 --------------------------------------------------
; Desc: Basic timers
; TIM6 base address:
TIM6_BASE EQU 0x40001000
; TIM6 registers:
TIM6_CR1 EQU (TIM6_BASE + 0x0) ; control register 1
TIM6_CR2 EQU (TIM6_BASE + 0x4) ; control register 2
TIM6_DIER EQU (TIM6_BASE + 0xc) ; DMA/Interrupt enable register
TIM6_SR EQU (TIM6_BASE + 0x10) ; status register
TIM6_EGR EQU (TIM6_BASE + 0x14) ; event generation register
TIM6_CNT EQU (TIM6_BASE + 0x24) ; counter
TIM6_PSC EQU (TIM6_BASE + 0x28) ; prescaler
TIM6_ARR EQU (TIM6_BASE + 0x2c) ; auto-reload register
; TIM6_CR1 fields:
TIM6_CR1_CEN EQU 0x00000001 ; Counter enable
TIM6_CR1_CEN_ofs EQU 0
TIM6_CR1_CEN_len EQU 1
TIM6_CR1_UDIS EQU 0x00000002 ; Update disable
TIM6_CR1_UDIS_ofs EQU 1
TIM6_CR1_UDIS_len EQU 1
TIM6_CR1_URS EQU 0x00000004 ; Update request source
TIM6_CR1_URS_ofs EQU 2
TIM6_CR1_URS_len EQU 1
TIM6_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM6_CR1_OPM_ofs EQU 3
TIM6_CR1_OPM_len EQU 1
TIM6_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM6_CR1_ARPE_ofs EQU 7
TIM6_CR1_ARPE_len EQU 1
TIM6_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM6_CR1_UIFREMAP_ofs EQU 11
TIM6_CR1_UIFREMAP_len EQU 1
; TIM6_CR2 fields:
TIM6_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM6_CR2_MMS_ofs EQU 4
TIM6_CR2_MMS_len EQU 3
; TIM6_DIER fields:
TIM6_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM6_DIER_UDE_ofs EQU 8
TIM6_DIER_UDE_len EQU 1
TIM6_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM6_DIER_UIE_ofs EQU 0
TIM6_DIER_UIE_len EQU 1
; TIM6_SR fields:
TIM6_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM6_SR_UIF_ofs EQU 0
TIM6_SR_UIF_len EQU 1
; TIM6_EGR fields:
TIM6_EGR_UG EQU 0x00000001 ; Update generation
TIM6_EGR_UG_ofs EQU 0
TIM6_EGR_UG_len EQU 1
; TIM6_CNT fields:
TIM6_CNT_CNT EQU 0x0000ffff ; Low counter value
TIM6_CNT_CNT_ofs EQU 0
TIM6_CNT_CNT_len EQU 16
TIM6_CNT_UIFCPY EQU 0x80000000 ; UIF Copy
TIM6_CNT_UIFCPY_ofs EQU 31
TIM6_CNT_UIFCPY_len EQU 1
; TIM6_PSC fields:
TIM6_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM6_PSC_PSC_ofs EQU 0
TIM6_PSC_PSC_len EQU 16
; TIM6_ARR fields:
TIM6_ARR_ARR EQU 0x0000ffff ; Low Auto-reload value
TIM6_ARR_ARR_ofs EQU 0
TIM6_ARR_ARR_len EQU 16
; ---- TIM7 --------------------------------------------------
; Desc: None
; TIM7 base address:
TIM7_BASE EQU 0x40001400
; TIM7 registers:
; ---- DAC ---------------------------------------------------
; Desc: Digital-to-analog converter
; DAC base address:
DAC_BASE EQU 0x40007400
; DAC registers:
DAC_CR EQU (DAC_BASE + 0x0) ; control register
DAC_SWTRIGR EQU (DAC_BASE + 0x4) ; software trigger register
DAC_DHR12R1 EQU (DAC_BASE + 0x8) ; channel1 12-bit right-aligned data holding register
DAC_DHR12L1 EQU (DAC_BASE + 0xc) ; channel1 12-bit left aligned data holding register
DAC_DHR8R1 EQU (DAC_BASE + 0x10) ; channel1 8-bit right aligned data holding register
DAC_DHR12R2 EQU (DAC_BASE + 0x14) ; channel2 12-bit right aligned data holding register
DAC_DHR12L2 EQU (DAC_BASE + 0x18) ; channel2 12-bit left aligned data holding register
DAC_DHR8R2 EQU (DAC_BASE + 0x1c) ; channel2 8-bit right-aligned data holding register
DAC_DHR12RD EQU (DAC_BASE + 0x20) ; Dual DAC 12-bit right-aligned data holding register
DAC_DHR12LD EQU (DAC_BASE + 0x24) ; DUAL DAC 12-bit left aligned data holding register
DAC_DHR8RD EQU (DAC_BASE + 0x28) ; DUAL DAC 8-bit right aligned data holding register
DAC_DOR1 EQU (DAC_BASE + 0x2c) ; channel1 data output register
DAC_DOR2 EQU (DAC_BASE + 0x30) ; channel2 data output register
DAC_SR EQU (DAC_BASE + 0x34) ; status register
; DAC_CR fields:
DAC_CR_DMAUDRIE2 EQU 0x20000000 ; DAC channel2 DMA underrun interrupt enable
DAC_CR_DMAUDRIE2_ofs EQU 29
DAC_CR_DMAUDRIE2_len EQU 1
DAC_CR_DMAEN2 EQU 0x10000000 ; DAC channel2 DMA enable
DAC_CR_DMAEN2_ofs EQU 28
DAC_CR_DMAEN2_len EQU 1
DAC_CR_MAMP2 EQU 0x0f000000 ; DAC channel2 mask/amplitude selector
DAC_CR_MAMP2_ofs EQU 24
DAC_CR_MAMP2_len EQU 4
DAC_CR_WAVE2 EQU 0x00c00000 ; DAC channel2 noise/triangle wave generation enable
DAC_CR_WAVE2_ofs EQU 22
DAC_CR_WAVE2_len EQU 2
DAC_CR_TSEL2 EQU 0x00380000 ; DAC channel2 trigger selection
DAC_CR_TSEL2_ofs EQU 19
DAC_CR_TSEL2_len EQU 3
DAC_CR_TEN2 EQU 0x00040000 ; DAC channel2 trigger enable
DAC_CR_TEN2_ofs EQU 18
DAC_CR_TEN2_len EQU 1
DAC_CR_BOFF2 EQU 0x00020000 ; DAC channel2 output buffer disable
DAC_CR_BOFF2_ofs EQU 17
DAC_CR_BOFF2_len EQU 1
DAC_CR_EN2 EQU 0x00010000 ; DAC channel2 enable
DAC_CR_EN2_ofs EQU 16
DAC_CR_EN2_len EQU 1
DAC_CR_DMAUDRIE1 EQU 0x00002000 ; DAC channel1 DMA Underrun Interrupt enable
DAC_CR_DMAUDRIE1_ofs EQU 13
DAC_CR_DMAUDRIE1_len EQU 1
DAC_CR_DMAEN1 EQU 0x00001000 ; DAC channel1 DMA enable
DAC_CR_DMAEN1_ofs EQU 12
DAC_CR_DMAEN1_len EQU 1
DAC_CR_MAMP1 EQU 0x00000f00 ; DAC channel1 mask/amplitude selector
DAC_CR_MAMP1_ofs EQU 8
DAC_CR_MAMP1_len EQU 4
DAC_CR_WAVE1 EQU 0x000000c0 ; DAC channel1 noise/triangle wave generation enable
DAC_CR_WAVE1_ofs EQU 6
DAC_CR_WAVE1_len EQU 2
DAC_CR_TSEL1 EQU 0x00000038 ; DAC channel1 trigger selection
DAC_CR_TSEL1_ofs EQU 3
DAC_CR_TSEL1_len EQU 3
DAC_CR_TEN1 EQU 0x00000004 ; DAC channel1 trigger enable
DAC_CR_TEN1_ofs EQU 2
DAC_CR_TEN1_len EQU 1
DAC_CR_BOFF1 EQU 0x00000002 ; DAC channel1 output buffer disable
DAC_CR_BOFF1_ofs EQU 1
DAC_CR_BOFF1_len EQU 1
DAC_CR_EN1 EQU 0x00000001 ; DAC channel1 enable
DAC_CR_EN1_ofs EQU 0
DAC_CR_EN1_len EQU 1
; DAC_SWTRIGR fields:
DAC_SWTRIGR_SWTRIG2 EQU 0x00000002 ; DAC channel2 software trigger
DAC_SWTRIGR_SWTRIG2_ofs EQU 1
DAC_SWTRIGR_SWTRIG2_len EQU 1
DAC_SWTRIGR_SWTRIG1 EQU 0x00000001 ; DAC channel1 software trigger
DAC_SWTRIGR_SWTRIG1_ofs EQU 0
DAC_SWTRIGR_SWTRIG1_len EQU 1
; DAC_DHR12R1 fields:
DAC_DHR12R1_DACC1DHR EQU 0x00000fff ; DAC channel1 12-bit right-aligned data
DAC_DHR12R1_DACC1DHR_ofs EQU 0
DAC_DHR12R1_DACC1DHR_len EQU 12
; DAC_DHR12L1 fields:
DAC_DHR12L1_DACC1DHR EQU 0x0000fff0 ; DAC channel1 12-bit left-aligned data
DAC_DHR12L1_DACC1DHR_ofs EQU 4
DAC_DHR12L1_DACC1DHR_len EQU 12
; DAC_DHR8R1 fields:
DAC_DHR8R1_DACC1DHR EQU 0x000000ff ; DAC channel1 8-bit right-aligned data
DAC_DHR8R1_DACC1DHR_ofs EQU 0
DAC_DHR8R1_DACC1DHR_len EQU 8
; DAC_DHR12R2 fields:
DAC_DHR12R2_DACC2DHR EQU 0x00000fff ; DAC channel2 12-bit right-aligned data
DAC_DHR12R2_DACC2DHR_ofs EQU 0
DAC_DHR12R2_DACC2DHR_len EQU 12
; DAC_DHR12L2 fields:
DAC_DHR12L2_DACC2DHR EQU 0x0000fff0 ; DAC channel2 12-bit left-aligned data
DAC_DHR12L2_DACC2DHR_ofs EQU 4
DAC_DHR12L2_DACC2DHR_len EQU 12
; DAC_DHR8R2 fields:
DAC_DHR8R2_DACC2DHR EQU 0x000000ff ; DAC channel2 8-bit right-aligned data
DAC_DHR8R2_DACC2DHR_ofs EQU 0
DAC_DHR8R2_DACC2DHR_len EQU 8
; DAC_DHR12RD fields:
DAC_DHR12RD_DACC2DHR EQU 0x0fff0000 ; DAC channel2 12-bit right-aligned data
DAC_DHR12RD_DACC2DHR_ofs EQU 16
DAC_DHR12RD_DACC2DHR_len EQU 12
DAC_DHR12RD_DACC1DHR EQU 0x00000fff ; DAC channel1 12-bit right-aligned data
DAC_DHR12RD_DACC1DHR_ofs EQU 0
DAC_DHR12RD_DACC1DHR_len EQU 12
; DAC_DHR12LD fields:
DAC_DHR12LD_DACC2DHR EQU 0xfff00000 ; DAC channel2 12-bit left-aligned data
DAC_DHR12LD_DACC2DHR_ofs EQU 20
DAC_DHR12LD_DACC2DHR_len EQU 12
DAC_DHR12LD_DACC1DHR EQU 0x0000fff0 ; DAC channel1 12-bit left-aligned data
DAC_DHR12LD_DACC1DHR_ofs EQU 4
DAC_DHR12LD_DACC1DHR_len EQU 12
; DAC_DHR8RD fields:
DAC_DHR8RD_DACC2DHR EQU 0x0000ff00 ; DAC channel2 8-bit right-aligned data
DAC_DHR8RD_DACC2DHR_ofs EQU 8
DAC_DHR8RD_DACC2DHR_len EQU 8
DAC_DHR8RD_DACC1DHR EQU 0x000000ff ; DAC channel1 8-bit right-aligned data
DAC_DHR8RD_DACC1DHR_ofs EQU 0
DAC_DHR8RD_DACC1DHR_len EQU 8
; DAC_DOR1 fields:
DAC_DOR1_DACC1DOR EQU 0x00000fff ; DAC channel1 data output
DAC_DOR1_DACC1DOR_ofs EQU 0
DAC_DOR1_DACC1DOR_len EQU 12
; DAC_DOR2 fields:
DAC_DOR2_DACC2DOR EQU 0x00000fff ; DAC channel2 data output
DAC_DOR2_DACC2DOR_ofs EQU 0
DAC_DOR2_DACC2DOR_len EQU 12
; DAC_SR fields:
DAC_SR_DMAUDR2 EQU 0x20000000 ; DAC channel2 DMA underrun flag
DAC_SR_DMAUDR2_ofs EQU 29
DAC_SR_DMAUDR2_len EQU 1
DAC_SR_DMAUDR1 EQU 0x00002000 ; DAC channel1 DMA underrun flag
DAC_SR_DMAUDR1_ofs EQU 13
DAC_SR_DMAUDR1_len EQU 1
; ---- NVIC --------------------------------------------------
; Desc: Nested Vectored Interrupt Controller
; NVIC base address:
NVIC_BASE EQU 0xe000e000
; NVIC registers:
NVIC_ICTR EQU (NVIC_BASE + 0x4) ; Interrupt Controller Type Register
NVIC_STIR EQU (NVIC_BASE + 0xf00) ; Software Triggered Interrupt Register
NVIC_ISER0 EQU (NVIC_BASE + 0x100) ; Interrupt Set-Enable Register
NVIC_ISER1 EQU (NVIC_BASE + 0x104) ; Interrupt Set-Enable Register
NVIC_ISER2 EQU (NVIC_BASE + 0x108) ; Interrupt Set-Enable Register
NVIC_ICER0 EQU (NVIC_BASE + 0x180) ; Interrupt Clear-Enable Register
NVIC_ICER1 EQU (NVIC_BASE + 0x184) ; Interrupt Clear-Enable Register
NVIC_ICER2 EQU (NVIC_BASE + 0x188) ; Interrupt Clear-Enable Register
NVIC_ISPR0 EQU (NVIC_BASE + 0x200) ; Interrupt Set-Pending Register
NVIC_ISPR1 EQU (NVIC_BASE + 0x204) ; Interrupt Set-Pending Register
NVIC_ISPR2 EQU (NVIC_BASE + 0x208) ; Interrupt Set-Pending Register
NVIC_ICPR0 EQU (NVIC_BASE + 0x280) ; Interrupt Clear-Pending Register
NVIC_ICPR1 EQU (NVIC_BASE + 0x284) ; Interrupt Clear-Pending Register
NVIC_ICPR2 EQU (NVIC_BASE + 0x288) ; Interrupt Clear-Pending Register
NVIC_IABR0 EQU (NVIC_BASE + 0x300) ; Interrupt Active Bit Register
NVIC_IABR1 EQU (NVIC_BASE + 0x304) ; Interrupt Active Bit Register
NVIC_IABR2 EQU (NVIC_BASE + 0x308) ; Interrupt Active Bit Register
NVIC_IPR0 EQU (NVIC_BASE + 0x400) ; Interrupt Priority Register
NVIC_IPR1 EQU (NVIC_BASE + 0x404) ; Interrupt Priority Register
NVIC_IPR2 EQU (NVIC_BASE + 0x408) ; Interrupt Priority Register
NVIC_IPR3 EQU (NVIC_BASE + 0x40c) ; Interrupt Priority Register
NVIC_IPR4 EQU (NVIC_BASE + 0x410) ; Interrupt Priority Register
NVIC_IPR5 EQU (NVIC_BASE + 0x414) ; Interrupt Priority Register
NVIC_IPR6 EQU (NVIC_BASE + 0x418) ; Interrupt Priority Register
NVIC_IPR7 EQU (NVIC_BASE + 0x41c) ; Interrupt Priority Register
NVIC_IPR8 EQU (NVIC_BASE + 0x420) ; Interrupt Priority Register
NVIC_IPR9 EQU (NVIC_BASE + 0x424) ; Interrupt Priority Register
NVIC_IPR10 EQU (NVIC_BASE + 0x428) ; Interrupt Priority Register
NVIC_IPR11 EQU (NVIC_BASE + 0x42c) ; Interrupt Priority Register
NVIC_IPR12 EQU (NVIC_BASE + 0x430) ; Interrupt Priority Register
NVIC_IPR13 EQU (NVIC_BASE + 0x434) ; Interrupt Priority Register
NVIC_IPR14 EQU (NVIC_BASE + 0x438) ; Interrupt Priority Register
NVIC_IPR15 EQU (NVIC_BASE + 0x43c) ; Interrupt Priority Register
NVIC_IPR16 EQU (NVIC_BASE + 0x440) ; Interrupt Priority Register
NVIC_IPR17 EQU (NVIC_BASE + 0x444) ; Interrupt Priority Register
NVIC_IPR18 EQU (NVIC_BASE + 0x448) ; Interrupt Priority Register
NVIC_IPR19 EQU (NVIC_BASE + 0x44c) ; Interrupt Priority Register
NVIC_IPR20 EQU (NVIC_BASE + 0x450) ; Interrupt Priority Register
; NVIC_ICTR fields:
NVIC_ICTR_INTLINESNUM EQU 0x0000000f ; Total number of interrupt lines in groups
NVIC_ICTR_INTLINESNUM_ofs EQU 0
NVIC_ICTR_INTLINESNUM_len EQU 4
; NVIC_STIR fields:
NVIC_STIR_INTID EQU 0x000001ff ; interrupt to be triggered
NVIC_STIR_INTID_ofs EQU 0
NVIC_STIR_INTID_len EQU 9
; NVIC_ISERx fields:
NVIC_ISERx_SETENA EQU 0xffffffff ; SETENA
NVIC_ISERx_SETENA_ofs EQU 0
NVIC_ISERx_SETENA_len EQU 32
; NVIC_ICERx fields:
NVIC_ICERx_CLRENA EQU 0xffffffff ; CLRENA
NVIC_ICERx_CLRENA_ofs EQU 0
NVIC_ICERx_CLRENA_len EQU 32
; NVIC_ISPR0 fields:
NVIC_ISPRx_SETPEND EQU 0xffffffff ; SETPEND
NVIC_ISPRx_SETPEND_ofs EQU 0
NVIC_ISPRx_SETPEND_len EQU 32
; NVIC_ICPRx fields:
NVIC_ICPRx_CLRPEND EQU 0xffffffff ; CLRPEND
NVIC_ICPRx_CLRPEND_ofs EQU 0
NVIC_ICPRx_CLRPEND_len EQU 32
; NVIC_IABRx fields:
NVIC_IABRx_ACTIVE EQU 0xffffffff ; ACTIVE
NVIC_IABRx_ACTIVE_ofs EQU 0
NVIC_IABRx_ACTIVE_len EQU 32
; NVIC_IPRx fields:
NVIC_IPRx_IPR_N0 EQU 0x000000ff ; IPR_N0
NVIC_IPRx_IPR_N0_ofs EQU 0
NVIC_IPRx_IPR_N0_len EQU 8
NVIC_IPRx_IPR_N1 EQU 0x0000ff00 ; IPR_N1
NVIC_IPRx_IPR_N1_ofs EQU 8
NVIC_IPRx_IPR_N1_len EQU 8
NVIC_IPRx_IPR_N2 EQU 0x00ff0000 ; IPR_N2
NVIC_IPRx_IPR_N2_ofs EQU 16
NVIC_IPRx_IPR_N2_len EQU 8
NVIC_IPRx_IPR_N3 EQU 0xff000000 ; IPR_N3
NVIC_IPRx_IPR_N3_ofs EQU 24
NVIC_IPRx_IPR_N3_len EQU 8
; ---- FPU ---------------------------------------------------
; Desc: Floting point unit
; FPU base address:
FPU_BASE EQU 0xe000ed88
; FPU registers:
FPU_CPACR EQU (FPU_BASE + 0x0) ; Coprocessor Access Control Register
FPU_FPCCR EQU (FPU_BASE + 0x1ac) ; FP Context Control Register
FPU_FPCAR EQU (FPU_BASE + 0x1b0) ; FP Context Address Register
FPU_FPDSCR EQU (FPU_BASE + 0x1b4) ; FP Default Status Control Register
FPU_MVFR0 EQU (FPU_BASE + 0x1b8) ; Media and VFP Feature Register 0
FPU_MVFR1 EQU (FPU_BASE + 0x1bc) ; Media and VFP Feature Register 1
; FPU_CPACR fields:
FPU_CPACR_CP0 EQU 0x00000001 ; Access privileges for coprocessor 0
FPU_CPACR_CP0_ofs EQU 0
FPU_CPACR_CP0_len EQU 1
FPU_CPACR_CP1 EQU 0x00000004 ; Access privileges for coprocessor 1
FPU_CPACR_CP1_ofs EQU 2
FPU_CPACR_CP1_len EQU 1
FPU_CPACR_CP2 EQU 0x00000010 ; Access privileges for coprocessor 2
FPU_CPACR_CP2_ofs EQU 4
FPU_CPACR_CP2_len EQU 1
FPU_CPACR_CP3 EQU 0x00000040 ; Access privileges for coprocessor 3
FPU_CPACR_CP3_ofs EQU 6
FPU_CPACR_CP3_len EQU 1
FPU_CPACR_CP4 EQU 0x00000100 ; Access privileges for coprocessor 4
FPU_CPACR_CP4_ofs EQU 8
FPU_CPACR_CP4_len EQU 1
FPU_CPACR_CP5 EQU 0x00000400 ; Access privileges for coprocessor 5
FPU_CPACR_CP5_ofs EQU 10
FPU_CPACR_CP5_len EQU 1
FPU_CPACR_CP6 EQU 0x00003000 ; Access privileges for coprocessor 6
FPU_CPACR_CP6_ofs EQU 12
FPU_CPACR_CP6_len EQU 2
FPU_CPACR_CP7 EQU 0x00004000 ; Access privileges for coprocessor 7
FPU_CPACR_CP7_ofs EQU 14
FPU_CPACR_CP7_len EQU 1
FPU_CPACR_CP10 EQU 0x00100000 ; Access privileges for coprocessor 10
FPU_CPACR_CP10_ofs EQU 20
FPU_CPACR_CP10_len EQU 1
FPU_CPACR_CP11 EQU 0x00400000 ; Access privileges for coprocessor 11
FPU_CPACR_CP11_ofs EQU 22
FPU_CPACR_CP11_len EQU 1
; FPU_FPCCR fields:
FPU_FPCCR_LSPACT EQU 0x00000001 ; LSPACT
FPU_FPCCR_LSPACT_ofs EQU 0
FPU_FPCCR_LSPACT_len EQU 1
FPU_FPCCR_USER EQU 0x00000002 ; USER
FPU_FPCCR_USER_ofs EQU 1
FPU_FPCCR_USER_len EQU 1
FPU_FPCCR_THREAD EQU 0x00000008 ; THREAD
FPU_FPCCR_THREAD_ofs EQU 3
FPU_FPCCR_THREAD_len EQU 1
FPU_FPCCR_HFRDY EQU 0x00000010 ; HFRDY
FPU_FPCCR_HFRDY_ofs EQU 4
FPU_FPCCR_HFRDY_len EQU 1
FPU_FPCCR_MMRDY EQU 0x00000020 ; MMRDY
FPU_FPCCR_MMRDY_ofs EQU 5
FPU_FPCCR_MMRDY_len EQU 1
FPU_FPCCR_BFRDY EQU 0x00000040 ; BFRDY
FPU_FPCCR_BFRDY_ofs EQU 6
FPU_FPCCR_BFRDY_len EQU 1
FPU_FPCCR_MONRDY EQU 0x00000100 ; MONRDY
FPU_FPCCR_MONRDY_ofs EQU 8
FPU_FPCCR_MONRDY_len EQU 1
FPU_FPCCR_LSPEN EQU 0x40000000 ; LSPEN
FPU_FPCCR_LSPEN_ofs EQU 30
FPU_FPCCR_LSPEN_len EQU 1
FPU_FPCCR_ASPEN EQU 0x80000000 ; ASPEN
FPU_FPCCR_ASPEN_ofs EQU 31
FPU_FPCCR_ASPEN_len EQU 1
; FPU_FPCAR fields:
FPU_FPCAR_ADDRESS EQU 0xfffffff8 ; ADDRESS
FPU_FPCAR_ADDRESS_ofs EQU 3
FPU_FPCAR_ADDRESS_len EQU 29
; FPU_FPDSCR fields:
FPU_FPDSCR_RMode EQU 0x00c00000 ; RMode
FPU_FPDSCR_RMode_ofs EQU 22
FPU_FPDSCR_RMode_len EQU 2
FPU_FPDSCR_FZ EQU 0x01000000 ; FZ
FPU_FPDSCR_FZ_ofs EQU 24
FPU_FPDSCR_FZ_len EQU 1
FPU_FPDSCR_DN EQU 0x02000000 ; DN
FPU_FPDSCR_DN_ofs EQU 25
FPU_FPDSCR_DN_len EQU 1
FPU_FPDSCR_AHP EQU 0x04000000 ; AHP
FPU_FPDSCR_AHP_ofs EQU 26
FPU_FPDSCR_AHP_len EQU 1
; FPU_MVFR0 fields:
FPU_MVFR0_A_SIMD EQU 0x0000000f ; A_SIMD registers
FPU_MVFR0_A_SIMD_ofs EQU 0
FPU_MVFR0_A_SIMD_len EQU 4
FPU_MVFR0_Single_precision EQU 0x000000f0 ; Single_precision
FPU_MVFR0_Single_precision_ofs EQU 4
FPU_MVFR0_Single_precision_len EQU 4
FPU_MVFR0_Double_precision EQU 0x00000f00 ; Double_precision
FPU_MVFR0_Double_precision_ofs EQU 8
FPU_MVFR0_Double_precision_len EQU 4
FPU_MVFR0_FP_exception_trapping EQU 0x0000f000 ; FP exception trapping
FPU_MVFR0_FP_exception_trapping_ofs EQU 12
FPU_MVFR0_FP_exception_trapping_len EQU 4
FPU_MVFR0_Divide EQU 0x000f0000 ; Divide
FPU_MVFR0_Divide_ofs EQU 16
FPU_MVFR0_Divide_len EQU 4
FPU_MVFR0_Square_root EQU 0x00f00000 ; Square root
FPU_MVFR0_Square_root_ofs EQU 20
FPU_MVFR0_Square_root_len EQU 4
FPU_MVFR0_Short_vectors EQU 0x0f000000 ; Short vectors
FPU_MVFR0_Short_vectors_ofs EQU 24
FPU_MVFR0_Short_vectors_len EQU 4
FPU_MVFR0_FP_rounding_modes EQU 0xf0000000 ; FP rounding modes
FPU_MVFR0_FP_rounding_modes_ofs EQU 28
FPU_MVFR0_FP_rounding_modes_len EQU 4
; FPU_MVFR1 fields:
FPU_MVFR1_FtZ_mode EQU 0x0000000f ; FtZ mode
FPU_MVFR1_FtZ_mode_ofs EQU 0
FPU_MVFR1_FtZ_mode_len EQU 4
FPU_MVFR1_D_NaN_mode EQU 0x000000f0 ; D_NaN mode
FPU_MVFR1_D_NaN_mode_ofs EQU 4
FPU_MVFR1_D_NaN_mode_len EQU 4
FPU_MVFR1_FP_HPFP EQU 0x0f000000 ; FP HPFP
FPU_MVFR1_FP_HPFP_ofs EQU 24
FPU_MVFR1_FP_HPFP_len EQU 4
FPU_MVFR1_FP_fused_MAC EQU 0xf0000000 ; FP fused MAC
FPU_MVFR1_FP_fused_MAC_ofs EQU 28
FPU_MVFR1_FP_fused_MAC_len EQU 4
; ---- DBGMCU ------------------------------------------------
; Desc: Debug support
; DBGMCU base address:
DBGMCU_BASE EQU 0xe0042000
; DBGMCU registers:
DBGMCU_IDCODE EQU (DBGMCU_BASE + 0x0) ; MCU Device ID Code Register
DBGMCU_CR EQU (DBGMCU_BASE + 0x4) ; Debug MCU Configuration Register
DBGMCU_APB1FZ EQU (DBGMCU_BASE + 0x8) ; APB Low Freeze Register
DBGMCU_APB2FZ EQU (DBGMCU_BASE + 0xc) ; APB High Freeze Register
; DBGMCU_IDCODE fields:
DBGMCU_IDCODE_DEV_ID EQU 0x00000fff ; Device Identifier
DBGMCU_IDCODE_DEV_ID_ofs EQU 0
DBGMCU_IDCODE_DEV_ID_len EQU 12
DBGMCU_IDCODE_REV_ID EQU 0xffff0000 ; Revision Identifier
DBGMCU_IDCODE_REV_ID_ofs EQU 16
DBGMCU_IDCODE_REV_ID_len EQU 16
; DBGMCU_CR fields:
DBGMCU_CR_DBG_SLEEP EQU 0x00000001 ; Debug Sleep mode
DBGMCU_CR_DBG_SLEEP_ofs EQU 0
DBGMCU_CR_DBG_SLEEP_len EQU 1
DBGMCU_CR_DBG_STOP EQU 0x00000002 ; Debug Stop Mode
DBGMCU_CR_DBG_STOP_ofs EQU 1
DBGMCU_CR_DBG_STOP_len EQU 1
DBGMCU_CR_DBG_STANDBY EQU 0x00000004 ; Debug Standby Mode
DBGMCU_CR_DBG_STANDBY_ofs EQU 2
DBGMCU_CR_DBG_STANDBY_len EQU 1
DBGMCU_CR_TRACE_IOEN EQU 0x00000020 ; Trace pin assignment control
DBGMCU_CR_TRACE_IOEN_ofs EQU 5
DBGMCU_CR_TRACE_IOEN_len EQU 1
DBGMCU_CR_TRACE_MODE EQU 0x000000c0 ; Trace pin assignment control
DBGMCU_CR_TRACE_MODE_ofs EQU 6
DBGMCU_CR_TRACE_MODE_len EQU 2
; DBGMCU_APB1FZ fields:
DBGMCU_APB1FZ_DBG_TIM2_STOP EQU 0x00000001 ; Debug Timer 2 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM2_STOP_ofs EQU 0
DBGMCU_APB1FZ_DBG_TIM2_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM3_STOP EQU 0x00000002 ; Debug Timer 3 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM3_STOP_ofs EQU 1
DBGMCU_APB1FZ_DBG_TIM3_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM4_STOP EQU 0x00000004 ; Debug Timer 4 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM4_STOP_ofs EQU 2
DBGMCU_APB1FZ_DBG_TIM4_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM5_STOP EQU 0x00000008 ; Debug Timer 5 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM5_STOP_ofs EQU 3
DBGMCU_APB1FZ_DBG_TIM5_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM6_STOP EQU 0x00000010 ; Debug Timer 6 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM6_STOP_ofs EQU 4
DBGMCU_APB1FZ_DBG_TIM6_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM7_STOP EQU 0x00000020 ; Debug Timer 7 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM7_STOP_ofs EQU 5
DBGMCU_APB1FZ_DBG_TIM7_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM12_STOP EQU 0x00000040 ; Debug Timer 12 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM12_STOP_ofs EQU 6
DBGMCU_APB1FZ_DBG_TIM12_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM13_STOP EQU 0x00000080 ; Debug Timer 13 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM13_STOP_ofs EQU 7
DBGMCU_APB1FZ_DBG_TIM13_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIMER14_STOP EQU 0x00000100 ; Debug Timer 14 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIMER14_STOP_ofs EQU 8
DBGMCU_APB1FZ_DBG_TIMER14_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_TIM18_STOP EQU 0x00000200 ; Debug Timer 18 stopped when Core is halted
DBGMCU_APB1FZ_DBG_TIM18_STOP_ofs EQU 9
DBGMCU_APB1FZ_DBG_TIM18_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_RTC_STOP EQU 0x00000400 ; Debug RTC stopped when Core is halted
DBGMCU_APB1FZ_DBG_RTC_STOP_ofs EQU 10
DBGMCU_APB1FZ_DBG_RTC_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_WWDG_STOP EQU 0x00000800 ; Debug Window Wachdog stopped when Core is halted
DBGMCU_APB1FZ_DBG_WWDG_STOP_ofs EQU 11
DBGMCU_APB1FZ_DBG_WWDG_STOP_len EQU 1
DBGMCU_APB1FZ_DBG_IWDG_STOP EQU 0x00001000 ; Debug Independent Wachdog stopped when Core is halted
DBGMCU_APB1FZ_DBG_IWDG_STOP_ofs EQU 12
DBGMCU_APB1FZ_DBG_IWDG_STOP_len EQU 1
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT EQU 0x00200000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT_ofs EQU 21
DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT_len EQU 1
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT EQU 0x00400000 ; SMBUS timeout mode stopped when Core is halted
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT_ofs EQU 22
DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT_len EQU 1
DBGMCU_APB1FZ_DBG_CAN_STOP EQU 0x02000000 ; Debug CAN stopped when core is halted
DBGMCU_APB1FZ_DBG_CAN_STOP_ofs EQU 25
DBGMCU_APB1FZ_DBG_CAN_STOP_len EQU 1
; DBGMCU_APB2FZ fields:
DBGMCU_APB2FZ_DBG_TIM15_STOP EQU 0x00000004 ; Debug Timer 15 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM15_STOP_ofs EQU 2
DBGMCU_APB2FZ_DBG_TIM15_STOP_len EQU 1
DBGMCU_APB2FZ_DBG_TIM16_STOP EQU 0x00000008 ; Debug Timer 16 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM16_STOP_ofs EQU 3
DBGMCU_APB2FZ_DBG_TIM16_STOP_len EQU 1
DBGMCU_APB2FZ_DBG_TIM17_STO EQU 0x00000010 ; Debug Timer 17 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM17_STO_ofs EQU 4
DBGMCU_APB2FZ_DBG_TIM17_STO_len EQU 1
DBGMCU_APB2FZ_DBG_TIM19_STOP EQU 0x00000020 ; Debug Timer 19 stopped when Core is halted
DBGMCU_APB2FZ_DBG_TIM19_STOP_ofs EQU 5
DBGMCU_APB2FZ_DBG_TIM19_STOP_len EQU 1
; ---- TIM1 --------------------------------------------------
; Desc: Advanced timer
; TIM1 base address:
TIM1_BASE EQU 0x40012c00
; TIM1 registers:
TIM1_CR1 EQU (TIM1_BASE + 0x0) ; control register 1
TIM1_CR2 EQU (TIM1_BASE + 0x4) ; control register 2
TIM1_SMCR EQU (TIM1_BASE + 0x8) ; slave mode control register
TIM1_DIER EQU (TIM1_BASE + 0xc) ; DMA/Interrupt enable register
TIM1_SR EQU (TIM1_BASE + 0x10) ; status register
TIM1_EGR EQU (TIM1_BASE + 0x14) ; event generation register
TIM1_CCMR1_Output EQU (TIM1_BASE + 0x18) ; capture/compare mode register (output mode)
TIM1_CCMR1_Input EQU (TIM1_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM1_CCMR2_Output EQU (TIM1_BASE + 0x1c) ; capture/compare mode register (output mode)
TIM1_CCMR2_Input EQU (TIM1_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM1_CCER EQU (TIM1_BASE + 0x20) ; capture/compare enable register
TIM1_CNT EQU (TIM1_BASE + 0x24) ; counter
TIM1_PSC EQU (TIM1_BASE + 0x28) ; prescaler
TIM1_ARR EQU (TIM1_BASE + 0x2c) ; auto-reload register
TIM1_RCR EQU (TIM1_BASE + 0x30) ; repetition counter register
TIM1_CCR1 EQU (TIM1_BASE + 0x34) ; capture/compare register 1
TIM1_CCR2 EQU (TIM1_BASE + 0x38) ; capture/compare register 2
TIM1_CCR3 EQU (TIM1_BASE + 0x3c) ; capture/compare register 3
TIM1_CCR4 EQU (TIM1_BASE + 0x40) ; capture/compare register 4
TIM1_BDTR EQU (TIM1_BASE + 0x44) ; break and dead-time register
TIM1_DCR EQU (TIM1_BASE + 0x48) ; DMA control register
TIM1_DMAR EQU (TIM1_BASE + 0x4c) ; DMA address for full transfer
TIM1_CCMR3_Output EQU (TIM1_BASE + 0x54) ; capture/compare mode register 3 (output mode)
TIM1_CCR5 EQU (TIM1_BASE + 0x58) ; capture/compare register 5
TIM1_CCR6 EQU (TIM1_BASE + 0x5c) ; capture/compare register 6
TIM1_OR EQU (TIM1_BASE + 0x60) ; option registers
; TIM1_CR1 fields:
TIM1_CR1_CEN EQU 0x00000001 ; Counter enable
TIM1_CR1_CEN_ofs EQU 0
TIM1_CR1_CEN_len EQU 1
TIM1_CR1_UDIS EQU 0x00000002 ; Update disable
TIM1_CR1_UDIS_ofs EQU 1
TIM1_CR1_UDIS_len EQU 1
TIM1_CR1_URS EQU 0x00000004 ; Update request source
TIM1_CR1_URS_ofs EQU 2
TIM1_CR1_URS_len EQU 1
TIM1_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM1_CR1_OPM_ofs EQU 3
TIM1_CR1_OPM_len EQU 1
TIM1_CR1_DIR EQU 0x00000010 ; Direction
TIM1_CR1_DIR_ofs EQU 4
TIM1_CR1_DIR_len EQU 1
TIM1_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM1_CR1_CMS_ofs EQU 5
TIM1_CR1_CMS_len EQU 2
TIM1_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM1_CR1_ARPE_ofs EQU 7
TIM1_CR1_ARPE_len EQU 1
TIM1_CR1_CKD EQU 0x00000300 ; Clock division
TIM1_CR1_CKD_ofs EQU 8
TIM1_CR1_CKD_len EQU 2
TIM1_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM1_CR1_UIFREMAP_ofs EQU 11
TIM1_CR1_UIFREMAP_len EQU 1
; TIM1_CR2 fields:
TIM1_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM1_CR2_CCPC_ofs EQU 0
TIM1_CR2_CCPC_len EQU 1
TIM1_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM1_CR2_CCUS_ofs EQU 2
TIM1_CR2_CCUS_len EQU 1
TIM1_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM1_CR2_CCDS_ofs EQU 3
TIM1_CR2_CCDS_len EQU 1
TIM1_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM1_CR2_MMS_ofs EQU 4
TIM1_CR2_MMS_len EQU 3
TIM1_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM1_CR2_TI1S_ofs EQU 7
TIM1_CR2_TI1S_len EQU 1
TIM1_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM1_CR2_OIS1_ofs EQU 8
TIM1_CR2_OIS1_len EQU 1
TIM1_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM1_CR2_OIS1N_ofs EQU 9
TIM1_CR2_OIS1N_len EQU 1
TIM1_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM1_CR2_OIS2_ofs EQU 10
TIM1_CR2_OIS2_len EQU 1
TIM1_CR2_OIS2N EQU 0x00000800 ; Output Idle state 2
TIM1_CR2_OIS2N_ofs EQU 11
TIM1_CR2_OIS2N_len EQU 1
TIM1_CR2_OIS3 EQU 0x00001000 ; Output Idle state 3
TIM1_CR2_OIS3_ofs EQU 12
TIM1_CR2_OIS3_len EQU 1
TIM1_CR2_OIS3N EQU 0x00002000 ; Output Idle state 3
TIM1_CR2_OIS3N_ofs EQU 13
TIM1_CR2_OIS3N_len EQU 1
TIM1_CR2_OIS4 EQU 0x00004000 ; Output Idle state 4
TIM1_CR2_OIS4_ofs EQU 14
TIM1_CR2_OIS4_len EQU 1
TIM1_CR2_OIS5 EQU 0x00010000 ; Output Idle state 5
TIM1_CR2_OIS5_ofs EQU 16
TIM1_CR2_OIS5_len EQU 1
TIM1_CR2_OIS6 EQU 0x00040000 ; Output Idle state 6
TIM1_CR2_OIS6_ofs EQU 18
TIM1_CR2_OIS6_len EQU 1
TIM1_CR2_MMS2 EQU 0x00f00000 ; Master mode selection 2
TIM1_CR2_MMS2_ofs EQU 20
TIM1_CR2_MMS2_len EQU 4
; TIM1_SMCR fields:
TIM1_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM1_SMCR_SMS_ofs EQU 0
TIM1_SMCR_SMS_len EQU 3
TIM1_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM1_SMCR_OCCS_ofs EQU 3
TIM1_SMCR_OCCS_len EQU 1
TIM1_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM1_SMCR_TS_ofs EQU 4
TIM1_SMCR_TS_len EQU 3
TIM1_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM1_SMCR_MSM_ofs EQU 7
TIM1_SMCR_MSM_len EQU 1
TIM1_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM1_SMCR_ETF_ofs EQU 8
TIM1_SMCR_ETF_len EQU 4
TIM1_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM1_SMCR_ETPS_ofs EQU 12
TIM1_SMCR_ETPS_len EQU 2
TIM1_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM1_SMCR_ECE_ofs EQU 14
TIM1_SMCR_ECE_len EQU 1
TIM1_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM1_SMCR_ETP_ofs EQU 15
TIM1_SMCR_ETP_len EQU 1
TIM1_SMCR_SMS3 EQU 0x00010000 ; Slave mode selection bit 3
TIM1_SMCR_SMS3_ofs EQU 16
TIM1_SMCR_SMS3_len EQU 1
; TIM1_DIER fields:
TIM1_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM1_DIER_TDE_ofs EQU 14
TIM1_DIER_TDE_len EQU 1
TIM1_DIER_COMDE EQU 0x00002000 ; Reserved
TIM1_DIER_COMDE_ofs EQU 13
TIM1_DIER_COMDE_len EQU 1
TIM1_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM1_DIER_CC4DE_ofs EQU 12
TIM1_DIER_CC4DE_len EQU 1
TIM1_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM1_DIER_CC3DE_ofs EQU 11
TIM1_DIER_CC3DE_len EQU 1
TIM1_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM1_DIER_CC2DE_ofs EQU 10
TIM1_DIER_CC2DE_len EQU 1
TIM1_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM1_DIER_CC1DE_ofs EQU 9
TIM1_DIER_CC1DE_len EQU 1
TIM1_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM1_DIER_UDE_ofs EQU 8
TIM1_DIER_UDE_len EQU 1
TIM1_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM1_DIER_BIE_ofs EQU 7
TIM1_DIER_BIE_len EQU 1
TIM1_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM1_DIER_TIE_ofs EQU 6
TIM1_DIER_TIE_len EQU 1
TIM1_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM1_DIER_COMIE_ofs EQU 5
TIM1_DIER_COMIE_len EQU 1
TIM1_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM1_DIER_CC4IE_ofs EQU 4
TIM1_DIER_CC4IE_len EQU 1
TIM1_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM1_DIER_CC3IE_ofs EQU 3
TIM1_DIER_CC3IE_len EQU 1
TIM1_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM1_DIER_CC2IE_ofs EQU 2
TIM1_DIER_CC2IE_len EQU 1
TIM1_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM1_DIER_CC1IE_ofs EQU 1
TIM1_DIER_CC1IE_len EQU 1
TIM1_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM1_DIER_UIE_ofs EQU 0
TIM1_DIER_UIE_len EQU 1
; TIM1_SR fields:
TIM1_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM1_SR_UIF_ofs EQU 0
TIM1_SR_UIF_len EQU 1
TIM1_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM1_SR_CC1IF_ofs EQU 1
TIM1_SR_CC1IF_len EQU 1
TIM1_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM1_SR_CC2IF_ofs EQU 2
TIM1_SR_CC2IF_len EQU 1
TIM1_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM1_SR_CC3IF_ofs EQU 3
TIM1_SR_CC3IF_len EQU 1
TIM1_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM1_SR_CC4IF_ofs EQU 4
TIM1_SR_CC4IF_len EQU 1
TIM1_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM1_SR_COMIF_ofs EQU 5
TIM1_SR_COMIF_len EQU 1
TIM1_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM1_SR_TIF_ofs EQU 6
TIM1_SR_TIF_len EQU 1
TIM1_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM1_SR_BIF_ofs EQU 7
TIM1_SR_BIF_len EQU 1
TIM1_SR_B2IF EQU 0x00000100 ; Break 2 interrupt flag
TIM1_SR_B2IF_ofs EQU 8
TIM1_SR_B2IF_len EQU 1
TIM1_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM1_SR_CC1OF_ofs EQU 9
TIM1_SR_CC1OF_len EQU 1
TIM1_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM1_SR_CC2OF_ofs EQU 10
TIM1_SR_CC2OF_len EQU 1
TIM1_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM1_SR_CC3OF_ofs EQU 11
TIM1_SR_CC3OF_len EQU 1
TIM1_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM1_SR_CC4OF_ofs EQU 12
TIM1_SR_CC4OF_len EQU 1
TIM1_SR_C5IF EQU 0x00010000 ; Capture/Compare 5 interrupt flag
TIM1_SR_C5IF_ofs EQU 16
TIM1_SR_C5IF_len EQU 1
TIM1_SR_C6IF EQU 0x00020000 ; Capture/Compare 6 interrupt flag
TIM1_SR_C6IF_ofs EQU 17
TIM1_SR_C6IF_len EQU 1
; TIM1_EGR fields:
TIM1_EGR_UG EQU 0x00000001 ; Update generation
TIM1_EGR_UG_ofs EQU 0
TIM1_EGR_UG_len EQU 1
TIM1_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM1_EGR_CC1G_ofs EQU 1
TIM1_EGR_CC1G_len EQU 1
TIM1_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM1_EGR_CC2G_ofs EQU 2
TIM1_EGR_CC2G_len EQU 1
TIM1_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM1_EGR_CC3G_ofs EQU 3
TIM1_EGR_CC3G_len EQU 1
TIM1_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM1_EGR_CC4G_ofs EQU 4
TIM1_EGR_CC4G_len EQU 1
TIM1_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM1_EGR_COMG_ofs EQU 5
TIM1_EGR_COMG_len EQU 1
TIM1_EGR_TG EQU 0x00000040 ; Trigger generation
TIM1_EGR_TG_ofs EQU 6
TIM1_EGR_TG_len EQU 1
TIM1_EGR_BG EQU 0x00000080 ; Break generation
TIM1_EGR_BG_ofs EQU 7
TIM1_EGR_BG_len EQU 1
TIM1_EGR_B2G EQU 0x00000100 ; Break 2 generation
TIM1_EGR_B2G_ofs EQU 8
TIM1_EGR_B2G_len EQU 1
; TIM1_CCMR1_Output fields:
TIM1_CCMR1_Output_OC2CE EQU 0x00008000 ; Output Compare 2 clear enable
TIM1_CCMR1_Output_OC2CE_ofs EQU 15
TIM1_CCMR1_Output_OC2CE_len EQU 1
TIM1_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM1_CCMR1_Output_OC2M_ofs EQU 12
TIM1_CCMR1_Output_OC2M_len EQU 3
TIM1_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM1_CCMR1_Output_OC2PE_ofs EQU 11
TIM1_CCMR1_Output_OC2PE_len EQU 1
TIM1_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM1_CCMR1_Output_OC2FE_ofs EQU 10
TIM1_CCMR1_Output_OC2FE_len EQU 1
TIM1_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM1_CCMR1_Output_CC2S_ofs EQU 8
TIM1_CCMR1_Output_CC2S_len EQU 2
TIM1_CCMR1_Output_OC1CE EQU 0x00000080 ; Output Compare 1 clear enable
TIM1_CCMR1_Output_OC1CE_ofs EQU 7
TIM1_CCMR1_Output_OC1CE_len EQU 1
TIM1_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM1_CCMR1_Output_OC1M_ofs EQU 4
TIM1_CCMR1_Output_OC1M_len EQU 3
TIM1_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM1_CCMR1_Output_OC1PE_ofs EQU 3
TIM1_CCMR1_Output_OC1PE_len EQU 1
TIM1_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM1_CCMR1_Output_OC1FE_ofs EQU 2
TIM1_CCMR1_Output_OC1FE_len EQU 1
TIM1_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM1_CCMR1_Output_CC1S_ofs EQU 0
TIM1_CCMR1_Output_CC1S_len EQU 2
TIM1_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM1_CCMR1_Output_OC1M_3_ofs EQU 16
TIM1_CCMR1_Output_OC1M_3_len EQU 1
TIM1_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM1_CCMR1_Output_OC2M_3_ofs EQU 24
TIM1_CCMR1_Output_OC2M_3_len EQU 1
; TIM1_CCMR1_Input fields:
TIM1_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM1_CCMR1_Input_IC2F_ofs EQU 12
TIM1_CCMR1_Input_IC2F_len EQU 4
TIM1_CCMR1_Input_IC2PCS EQU 0x00000c00 ; Input capture 2 prescaler
TIM1_CCMR1_Input_IC2PCS_ofs EQU 10
TIM1_CCMR1_Input_IC2PCS_len EQU 2
TIM1_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM1_CCMR1_Input_CC2S_ofs EQU 8
TIM1_CCMR1_Input_CC2S_len EQU 2
TIM1_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM1_CCMR1_Input_IC1F_ofs EQU 4
TIM1_CCMR1_Input_IC1F_len EQU 4
TIM1_CCMR1_Input_IC1PCS EQU 0x0000000c ; Input capture 1 prescaler
TIM1_CCMR1_Input_IC1PCS_ofs EQU 2
TIM1_CCMR1_Input_IC1PCS_len EQU 2
TIM1_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM1_CCMR1_Input_CC1S_ofs EQU 0
TIM1_CCMR1_Input_CC1S_len EQU 2
; TIM1_CCMR2_Output fields:
TIM1_CCMR2_Output_OC4CE EQU 0x00008000 ; Output compare 4 clear enable
TIM1_CCMR2_Output_OC4CE_ofs EQU 15
TIM1_CCMR2_Output_OC4CE_len EQU 1
TIM1_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM1_CCMR2_Output_OC4M_ofs EQU 12
TIM1_CCMR2_Output_OC4M_len EQU 3
TIM1_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM1_CCMR2_Output_OC4PE_ofs EQU 11
TIM1_CCMR2_Output_OC4PE_len EQU 1
TIM1_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM1_CCMR2_Output_OC4FE_ofs EQU 10
TIM1_CCMR2_Output_OC4FE_len EQU 1
TIM1_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM1_CCMR2_Output_CC4S_ofs EQU 8
TIM1_CCMR2_Output_CC4S_len EQU 2
TIM1_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM1_CCMR2_Output_OC3CE_ofs EQU 7
TIM1_CCMR2_Output_OC3CE_len EQU 1
TIM1_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM1_CCMR2_Output_OC3M_ofs EQU 4
TIM1_CCMR2_Output_OC3M_len EQU 3
TIM1_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM1_CCMR2_Output_OC3PE_ofs EQU 3
TIM1_CCMR2_Output_OC3PE_len EQU 1
TIM1_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM1_CCMR2_Output_OC3FE_ofs EQU 2
TIM1_CCMR2_Output_OC3FE_len EQU 1
TIM1_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM1_CCMR2_Output_CC3S_ofs EQU 0
TIM1_CCMR2_Output_CC3S_len EQU 2
TIM1_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output Compare 3 mode bit 3
TIM1_CCMR2_Output_OC3M_3_ofs EQU 16
TIM1_CCMR2_Output_OC3M_3_len EQU 1
TIM1_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output Compare 4 mode bit 3
TIM1_CCMR2_Output_OC4M_3_ofs EQU 24
TIM1_CCMR2_Output_OC4M_3_len EQU 1
; TIM1_CCMR2_Input fields:
TIM1_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM1_CCMR2_Input_IC4F_ofs EQU 12
TIM1_CCMR2_Input_IC4F_len EQU 4
TIM1_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM1_CCMR2_Input_IC4PSC_ofs EQU 10
TIM1_CCMR2_Input_IC4PSC_len EQU 2
TIM1_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM1_CCMR2_Input_CC4S_ofs EQU 8
TIM1_CCMR2_Input_CC4S_len EQU 2
TIM1_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM1_CCMR2_Input_IC3F_ofs EQU 4
TIM1_CCMR2_Input_IC3F_len EQU 4
TIM1_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM1_CCMR2_Input_IC3PSC_ofs EQU 2
TIM1_CCMR2_Input_IC3PSC_len EQU 2
TIM1_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/compare 3 selection
TIM1_CCMR2_Input_CC3S_ofs EQU 0
TIM1_CCMR2_Input_CC3S_len EQU 2
; TIM1_CCER fields:
TIM1_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM1_CCER_CC1E_ofs EQU 0
TIM1_CCER_CC1E_len EQU 1
TIM1_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM1_CCER_CC1P_ofs EQU 1
TIM1_CCER_CC1P_len EQU 1
TIM1_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM1_CCER_CC1NE_ofs EQU 2
TIM1_CCER_CC1NE_len EQU 1
TIM1_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM1_CCER_CC1NP_ofs EQU 3
TIM1_CCER_CC1NP_len EQU 1
TIM1_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM1_CCER_CC2E_ofs EQU 4
TIM1_CCER_CC2E_len EQU 1
TIM1_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM1_CCER_CC2P_ofs EQU 5
TIM1_CCER_CC2P_len EQU 1
TIM1_CCER_CC2NE EQU 0x00000040 ; Capture/Compare 2 complementary output enable
TIM1_CCER_CC2NE_ofs EQU 6
TIM1_CCER_CC2NE_len EQU 1
TIM1_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM1_CCER_CC2NP_ofs EQU 7
TIM1_CCER_CC2NP_len EQU 1
TIM1_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM1_CCER_CC3E_ofs EQU 8
TIM1_CCER_CC3E_len EQU 1
TIM1_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC3P_ofs EQU 9
TIM1_CCER_CC3P_len EQU 1
TIM1_CCER_CC3NE EQU 0x00000400 ; Capture/Compare 3 complementary output enable
TIM1_CCER_CC3NE_ofs EQU 10
TIM1_CCER_CC3NE_len EQU 1
TIM1_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC3NP_ofs EQU 11
TIM1_CCER_CC3NP_len EQU 1
TIM1_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM1_CCER_CC4E_ofs EQU 12
TIM1_CCER_CC4E_len EQU 1
TIM1_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM1_CCER_CC4P_ofs EQU 13
TIM1_CCER_CC4P_len EQU 1
TIM1_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 4 output Polarity
TIM1_CCER_CC4NP_ofs EQU 15
TIM1_CCER_CC4NP_len EQU 1
TIM1_CCER_CC5E EQU 0x00010000 ; Capture/Compare 5 output enable
TIM1_CCER_CC5E_ofs EQU 16
TIM1_CCER_CC5E_len EQU 1
TIM1_CCER_CC5P EQU 0x00020000 ; Capture/Compare 5 output Polarity
TIM1_CCER_CC5P_ofs EQU 17
TIM1_CCER_CC5P_len EQU 1
TIM1_CCER_CC6E EQU 0x00100000 ; Capture/Compare 6 output enable
TIM1_CCER_CC6E_ofs EQU 20
TIM1_CCER_CC6E_len EQU 1
TIM1_CCER_CC6P EQU 0x00200000 ; Capture/Compare 6 output Polarity
TIM1_CCER_CC6P_ofs EQU 21
TIM1_CCER_CC6P_len EQU 1
; TIM1_CNT fields:
TIM1_CNT_CNT EQU 0x0000ffff ; counter value
TIM1_CNT_CNT_ofs EQU 0
TIM1_CNT_CNT_len EQU 16
TIM1_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM1_CNT_UIFCPY_ofs EQU 31
TIM1_CNT_UIFCPY_len EQU 1
; TIM1_PSC fields:
TIM1_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM1_PSC_PSC_ofs EQU 0
TIM1_PSC_PSC_len EQU 16
; TIM1_ARR fields:
TIM1_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM1_ARR_ARR_ofs EQU 0
TIM1_ARR_ARR_len EQU 16
; TIM1_RCR fields:
TIM1_RCR_REP EQU 0x0000ffff ; Repetition counter value
TIM1_RCR_REP_ofs EQU 0
TIM1_RCR_REP_len EQU 16
; TIM1_CCR1 fields:
TIM1_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM1_CCR1_CCR1_ofs EQU 0
TIM1_CCR1_CCR1_len EQU 16
; TIM1_CCR2 fields:
TIM1_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM1_CCR2_CCR2_ofs EQU 0
TIM1_CCR2_CCR2_len EQU 16
; TIM1_CCR3 fields:
TIM1_CCR3_CCR3 EQU 0x0000ffff ; Capture/Compare 3 value
TIM1_CCR3_CCR3_ofs EQU 0
TIM1_CCR3_CCR3_len EQU 16
; TIM1_CCR4 fields:
TIM1_CCR4_CCR4 EQU 0x0000ffff ; Capture/Compare 3 value
TIM1_CCR4_CCR4_ofs EQU 0
TIM1_CCR4_CCR4_len EQU 16
; TIM1_BDTR fields:
TIM1_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM1_BDTR_DTG_ofs EQU 0
TIM1_BDTR_DTG_len EQU 8
TIM1_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM1_BDTR_LOCK_ofs EQU 8
TIM1_BDTR_LOCK_len EQU 2
TIM1_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM1_BDTR_OSSI_ofs EQU 10
TIM1_BDTR_OSSI_len EQU 1
TIM1_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM1_BDTR_OSSR_ofs EQU 11
TIM1_BDTR_OSSR_len EQU 1
TIM1_BDTR_BKE EQU 0x00001000 ; Break enable
TIM1_BDTR_BKE_ofs EQU 12
TIM1_BDTR_BKE_len EQU 1
TIM1_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM1_BDTR_BKP_ofs EQU 13
TIM1_BDTR_BKP_len EQU 1
TIM1_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM1_BDTR_AOE_ofs EQU 14
TIM1_BDTR_AOE_len EQU 1
TIM1_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM1_BDTR_MOE_ofs EQU 15
TIM1_BDTR_MOE_len EQU 1
TIM1_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM1_BDTR_BKF_ofs EQU 16
TIM1_BDTR_BKF_len EQU 4
TIM1_BDTR_BK2F EQU 0x00f00000 ; Break 2 filter
TIM1_BDTR_BK2F_ofs EQU 20
TIM1_BDTR_BK2F_len EQU 4
TIM1_BDTR_BK2E EQU 0x01000000 ; Break 2 enable
TIM1_BDTR_BK2E_ofs EQU 24
TIM1_BDTR_BK2E_len EQU 1
TIM1_BDTR_BK2P EQU 0x02000000 ; Break 2 polarity
TIM1_BDTR_BK2P_ofs EQU 25
TIM1_BDTR_BK2P_len EQU 1
; TIM1_DCR fields:
TIM1_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM1_DCR_DBL_ofs EQU 8
TIM1_DCR_DBL_len EQU 5
TIM1_DCR_DBA EQU 0x0000001f ; DMA base address
TIM1_DCR_DBA_ofs EQU 0
TIM1_DCR_DBA_len EQU 5
; TIM1_DMAR fields:
TIM1_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM1_DMAR_DMAB_ofs EQU 0
TIM1_DMAR_DMAB_len EQU 16
; TIM1_CCMR3_Output fields:
TIM1_CCMR3_Output_OC5FE EQU 0x00000004 ; Output compare 5 fast enable
TIM1_CCMR3_Output_OC5FE_ofs EQU 2
TIM1_CCMR3_Output_OC5FE_len EQU 1
TIM1_CCMR3_Output_OC5PE EQU 0x00000008 ; Output compare 5 preload enable
TIM1_CCMR3_Output_OC5PE_ofs EQU 3
TIM1_CCMR3_Output_OC5PE_len EQU 1
TIM1_CCMR3_Output_OC5M EQU 0x00000070 ; Output compare 5 mode
TIM1_CCMR3_Output_OC5M_ofs EQU 4
TIM1_CCMR3_Output_OC5M_len EQU 3
TIM1_CCMR3_Output_OC5CE EQU 0x00000080 ; Output compare 5 clear enable
TIM1_CCMR3_Output_OC5CE_ofs EQU 7
TIM1_CCMR3_Output_OC5CE_len EQU 1
TIM1_CCMR3_Output_OC6FE EQU 0x00000400 ; Output compare 6 fast enable
TIM1_CCMR3_Output_OC6FE_ofs EQU 10
TIM1_CCMR3_Output_OC6FE_len EQU 1
TIM1_CCMR3_Output_OC6PE EQU 0x00000800 ; Output compare 6 preload enable
TIM1_CCMR3_Output_OC6PE_ofs EQU 11
TIM1_CCMR3_Output_OC6PE_len EQU 1
TIM1_CCMR3_Output_OC6M EQU 0x00007000 ; Output compare 6 mode
TIM1_CCMR3_Output_OC6M_ofs EQU 12
TIM1_CCMR3_Output_OC6M_len EQU 3
TIM1_CCMR3_Output_OC6CE EQU 0x00008000 ; Output compare 6 clear enable
TIM1_CCMR3_Output_OC6CE_ofs EQU 15
TIM1_CCMR3_Output_OC6CE_len EQU 1
TIM1_CCMR3_Output_OC5M_3 EQU 0x00010000 ; Outout Compare 5 mode bit 3
TIM1_CCMR3_Output_OC5M_3_ofs EQU 16
TIM1_CCMR3_Output_OC5M_3_len EQU 1
TIM1_CCMR3_Output_OC6M_3 EQU 0x01000000 ; Outout Compare 6 mode bit 3
TIM1_CCMR3_Output_OC6M_3_ofs EQU 24
TIM1_CCMR3_Output_OC6M_3_len EQU 1
; TIM1_CCR5 fields:
TIM1_CCR5_CCR5 EQU 0x0000ffff ; Capture/Compare 5 value
TIM1_CCR5_CCR5_ofs EQU 0
TIM1_CCR5_CCR5_len EQU 16
TIM1_CCR5_GC5C1 EQU 0x20000000 ; Group Channel 5 and Channel 1
TIM1_CCR5_GC5C1_ofs EQU 29
TIM1_CCR5_GC5C1_len EQU 1
TIM1_CCR5_GC5C2 EQU 0x40000000 ; Group Channel 5 and Channel 2
TIM1_CCR5_GC5C2_ofs EQU 30
TIM1_CCR5_GC5C2_len EQU 1
TIM1_CCR5_GC5C3 EQU 0x80000000 ; Group Channel 5 and Channel 3
TIM1_CCR5_GC5C3_ofs EQU 31
TIM1_CCR5_GC5C3_len EQU 1
; TIM1_CCR6 fields:
TIM1_CCR6_CCR6 EQU 0x0000ffff ; Capture/Compare 6 value
TIM1_CCR6_CCR6_ofs EQU 0
TIM1_CCR6_CCR6_len EQU 16
; TIM1_OR fields:
TIM1_OR_TIM1_ETR_ADC1_RMP EQU 0x00000003 ; TIM1_ETR_ADC1 remapping capability
TIM1_OR_TIM1_ETR_ADC1_RMP_ofs EQU 0
TIM1_OR_TIM1_ETR_ADC1_RMP_len EQU 2
TIM1_OR_TIM1_ETR_ADC4_RMP EQU 0x0000000c ; TIM1_ETR_ADC4 remapping capability
TIM1_OR_TIM1_ETR_ADC4_RMP_ofs EQU 2
TIM1_OR_TIM1_ETR_ADC4_RMP_len EQU 2
; ---- TIM8 --------------------------------------------------
; Desc: Advanced-timers
; TIM8 base address:
TIM8_BASE EQU 0x40013400
; TIM8 registers:
TIM8_CR1 EQU (TIM8_BASE + 0x0) ; control register 1
TIM8_CR2 EQU (TIM8_BASE + 0x4) ; control register 2
TIM8_SMCR EQU (TIM8_BASE + 0x8) ; slave mode control register
TIM8_DIER EQU (TIM8_BASE + 0xc) ; DMA/Interrupt enable register
TIM8_SR EQU (TIM8_BASE + 0x10) ; status register
TIM8_EGR EQU (TIM8_BASE + 0x14) ; event generation register
TIM8_CCMR1_Output EQU (TIM8_BASE + 0x18) ; capture/compare mode register (output mode)
TIM8_CCMR1_Input EQU (TIM8_BASE + 0x18) ; capture/compare mode register 1 (input mode)
TIM8_CCMR2_Output EQU (TIM8_BASE + 0x1c) ; capture/compare mode register (output mode)
TIM8_CCMR2_Input EQU (TIM8_BASE + 0x1c) ; capture/compare mode register 2 (input mode)
TIM8_CCER EQU (TIM8_BASE + 0x20) ; capture/compare enable register
TIM8_CNT EQU (TIM8_BASE + 0x24) ; counter
TIM8_PSC EQU (TIM8_BASE + 0x28) ; prescaler
TIM8_ARR EQU (TIM8_BASE + 0x2c) ; auto-reload register
TIM8_RCR EQU (TIM8_BASE + 0x30) ; repetition counter register
TIM8_CCR1 EQU (TIM8_BASE + 0x34) ; capture/compare register 1
TIM8_CCR2 EQU (TIM8_BASE + 0x38) ; capture/compare register 2
TIM8_CCR3 EQU (TIM8_BASE + 0x3c) ; capture/compare register 3
TIM8_CCR4 EQU (TIM8_BASE + 0x40) ; capture/compare register 4
TIM8_BDTR EQU (TIM8_BASE + 0x44) ; break and dead-time register
TIM8_DCR EQU (TIM8_BASE + 0x48) ; DMA control register
TIM8_DMAR EQU (TIM8_BASE + 0x4c) ; DMA address for full transfer
TIM8_CCMR3_Output EQU (TIM8_BASE + 0x54) ; capture/compare mode register 3 (output mode)
TIM8_CCR5 EQU (TIM8_BASE + 0x58) ; capture/compare register 5
TIM8_CCR6 EQU (TIM8_BASE + 0x5c) ; capture/compare register 6
TIM8_OR EQU (TIM8_BASE + 0x60) ; option registers
; TIM8_CR1 fields:
TIM8_CR1_CEN EQU 0x00000001 ; Counter enable
TIM8_CR1_CEN_ofs EQU 0
TIM8_CR1_CEN_len EQU 1
TIM8_CR1_UDIS EQU 0x00000002 ; Update disable
TIM8_CR1_UDIS_ofs EQU 1
TIM8_CR1_UDIS_len EQU 1
TIM8_CR1_URS EQU 0x00000004 ; Update request source
TIM8_CR1_URS_ofs EQU 2
TIM8_CR1_URS_len EQU 1
TIM8_CR1_OPM EQU 0x00000008 ; One-pulse mode
TIM8_CR1_OPM_ofs EQU 3
TIM8_CR1_OPM_len EQU 1
TIM8_CR1_DIR EQU 0x00000010 ; Direction
TIM8_CR1_DIR_ofs EQU 4
TIM8_CR1_DIR_len EQU 1
TIM8_CR1_CMS EQU 0x00000060 ; Center-aligned mode selection
TIM8_CR1_CMS_ofs EQU 5
TIM8_CR1_CMS_len EQU 2
TIM8_CR1_ARPE EQU 0x00000080 ; Auto-reload preload enable
TIM8_CR1_ARPE_ofs EQU 7
TIM8_CR1_ARPE_len EQU 1
TIM8_CR1_CKD EQU 0x00000300 ; Clock division
TIM8_CR1_CKD_ofs EQU 8
TIM8_CR1_CKD_len EQU 2
TIM8_CR1_UIFREMAP EQU 0x00000800 ; UIF status bit remapping
TIM8_CR1_UIFREMAP_ofs EQU 11
TIM8_CR1_UIFREMAP_len EQU 1
; TIM8_CR2 fields:
TIM8_CR2_CCPC EQU 0x00000001 ; Capture/compare preloaded control
TIM8_CR2_CCPC_ofs EQU 0
TIM8_CR2_CCPC_len EQU 1
TIM8_CR2_CCUS EQU 0x00000004 ; Capture/compare control update selection
TIM8_CR2_CCUS_ofs EQU 2
TIM8_CR2_CCUS_len EQU 1
TIM8_CR2_CCDS EQU 0x00000008 ; Capture/compare DMA selection
TIM8_CR2_CCDS_ofs EQU 3
TIM8_CR2_CCDS_len EQU 1
TIM8_CR2_MMS EQU 0x00000070 ; Master mode selection
TIM8_CR2_MMS_ofs EQU 4
TIM8_CR2_MMS_len EQU 3
TIM8_CR2_TI1S EQU 0x00000080 ; TI1 selection
TIM8_CR2_TI1S_ofs EQU 7
TIM8_CR2_TI1S_len EQU 1
TIM8_CR2_OIS1 EQU 0x00000100 ; Output Idle state 1
TIM8_CR2_OIS1_ofs EQU 8
TIM8_CR2_OIS1_len EQU 1
TIM8_CR2_OIS1N EQU 0x00000200 ; Output Idle state 1
TIM8_CR2_OIS1N_ofs EQU 9
TIM8_CR2_OIS1N_len EQU 1
TIM8_CR2_OIS2 EQU 0x00000400 ; Output Idle state 2
TIM8_CR2_OIS2_ofs EQU 10
TIM8_CR2_OIS2_len EQU 1
TIM8_CR2_OIS2N EQU 0x00000800 ; Output Idle state 2
TIM8_CR2_OIS2N_ofs EQU 11
TIM8_CR2_OIS2N_len EQU 1
TIM8_CR2_OIS3 EQU 0x00001000 ; Output Idle state 3
TIM8_CR2_OIS3_ofs EQU 12
TIM8_CR2_OIS3_len EQU 1
TIM8_CR2_OIS3N EQU 0x00002000 ; Output Idle state 3
TIM8_CR2_OIS3N_ofs EQU 13
TIM8_CR2_OIS3N_len EQU 1
TIM8_CR2_OIS4 EQU 0x00004000 ; Output Idle state 4
TIM8_CR2_OIS4_ofs EQU 14
TIM8_CR2_OIS4_len EQU 1
TIM8_CR2_OIS5 EQU 0x00010000 ; Output Idle state 5
TIM8_CR2_OIS5_ofs EQU 16
TIM8_CR2_OIS5_len EQU 1
TIM8_CR2_OIS6 EQU 0x00040000 ; Output Idle state 6
TIM8_CR2_OIS6_ofs EQU 18
TIM8_CR2_OIS6_len EQU 1
TIM8_CR2_MMS2 EQU 0x00f00000 ; Master mode selection 2
TIM8_CR2_MMS2_ofs EQU 20
TIM8_CR2_MMS2_len EQU 4
; TIM8_SMCR fields:
TIM8_SMCR_SMS EQU 0x00000007 ; Slave mode selection
TIM8_SMCR_SMS_ofs EQU 0
TIM8_SMCR_SMS_len EQU 3
TIM8_SMCR_OCCS EQU 0x00000008 ; OCREF clear selection
TIM8_SMCR_OCCS_ofs EQU 3
TIM8_SMCR_OCCS_len EQU 1
TIM8_SMCR_TS EQU 0x00000070 ; Trigger selection
TIM8_SMCR_TS_ofs EQU 4
TIM8_SMCR_TS_len EQU 3
TIM8_SMCR_MSM EQU 0x00000080 ; Master/Slave mode
TIM8_SMCR_MSM_ofs EQU 7
TIM8_SMCR_MSM_len EQU 1
TIM8_SMCR_ETF EQU 0x00000f00 ; External trigger filter
TIM8_SMCR_ETF_ofs EQU 8
TIM8_SMCR_ETF_len EQU 4
TIM8_SMCR_ETPS EQU 0x00003000 ; External trigger prescaler
TIM8_SMCR_ETPS_ofs EQU 12
TIM8_SMCR_ETPS_len EQU 2
TIM8_SMCR_ECE EQU 0x00004000 ; External clock enable
TIM8_SMCR_ECE_ofs EQU 14
TIM8_SMCR_ECE_len EQU 1
TIM8_SMCR_ETP EQU 0x00008000 ; External trigger polarity
TIM8_SMCR_ETP_ofs EQU 15
TIM8_SMCR_ETP_len EQU 1
TIM8_SMCR_SMS3 EQU 0x00010000 ; Slave mode selection bit 3
TIM8_SMCR_SMS3_ofs EQU 16
TIM8_SMCR_SMS3_len EQU 1
; TIM8_DIER fields:
TIM8_DIER_TDE EQU 0x00004000 ; Trigger DMA request enable
TIM8_DIER_TDE_ofs EQU 14
TIM8_DIER_TDE_len EQU 1
TIM8_DIER_COMDE EQU 0x00002000 ; Reserved
TIM8_DIER_COMDE_ofs EQU 13
TIM8_DIER_COMDE_len EQU 1
TIM8_DIER_CC4DE EQU 0x00001000 ; Capture/Compare 4 DMA request enable
TIM8_DIER_CC4DE_ofs EQU 12
TIM8_DIER_CC4DE_len EQU 1
TIM8_DIER_CC3DE EQU 0x00000800 ; Capture/Compare 3 DMA request enable
TIM8_DIER_CC3DE_ofs EQU 11
TIM8_DIER_CC3DE_len EQU 1
TIM8_DIER_CC2DE EQU 0x00000400 ; Capture/Compare 2 DMA request enable
TIM8_DIER_CC2DE_ofs EQU 10
TIM8_DIER_CC2DE_len EQU 1
TIM8_DIER_CC1DE EQU 0x00000200 ; Capture/Compare 1 DMA request enable
TIM8_DIER_CC1DE_ofs EQU 9
TIM8_DIER_CC1DE_len EQU 1
TIM8_DIER_UDE EQU 0x00000100 ; Update DMA request enable
TIM8_DIER_UDE_ofs EQU 8
TIM8_DIER_UDE_len EQU 1
TIM8_DIER_BIE EQU 0x00000080 ; Break interrupt enable
TIM8_DIER_BIE_ofs EQU 7
TIM8_DIER_BIE_len EQU 1
TIM8_DIER_TIE EQU 0x00000040 ; Trigger interrupt enable
TIM8_DIER_TIE_ofs EQU 6
TIM8_DIER_TIE_len EQU 1
TIM8_DIER_COMIE EQU 0x00000020 ; COM interrupt enable
TIM8_DIER_COMIE_ofs EQU 5
TIM8_DIER_COMIE_len EQU 1
TIM8_DIER_CC4IE EQU 0x00000010 ; Capture/Compare 4 interrupt enable
TIM8_DIER_CC4IE_ofs EQU 4
TIM8_DIER_CC4IE_len EQU 1
TIM8_DIER_CC3IE EQU 0x00000008 ; Capture/Compare 3 interrupt enable
TIM8_DIER_CC3IE_ofs EQU 3
TIM8_DIER_CC3IE_len EQU 1
TIM8_DIER_CC2IE EQU 0x00000004 ; Capture/Compare 2 interrupt enable
TIM8_DIER_CC2IE_ofs EQU 2
TIM8_DIER_CC2IE_len EQU 1
TIM8_DIER_CC1IE EQU 0x00000002 ; Capture/Compare 1 interrupt enable
TIM8_DIER_CC1IE_ofs EQU 1
TIM8_DIER_CC1IE_len EQU 1
TIM8_DIER_UIE EQU 0x00000001 ; Update interrupt enable
TIM8_DIER_UIE_ofs EQU 0
TIM8_DIER_UIE_len EQU 1
; TIM8_SR fields:
TIM8_SR_UIF EQU 0x00000001 ; Update interrupt flag
TIM8_SR_UIF_ofs EQU 0
TIM8_SR_UIF_len EQU 1
TIM8_SR_CC1IF EQU 0x00000002 ; Capture/compare 1 interrupt flag
TIM8_SR_CC1IF_ofs EQU 1
TIM8_SR_CC1IF_len EQU 1
TIM8_SR_CC2IF EQU 0x00000004 ; Capture/Compare 2 interrupt flag
TIM8_SR_CC2IF_ofs EQU 2
TIM8_SR_CC2IF_len EQU 1
TIM8_SR_CC3IF EQU 0x00000008 ; Capture/Compare 3 interrupt flag
TIM8_SR_CC3IF_ofs EQU 3
TIM8_SR_CC3IF_len EQU 1
TIM8_SR_CC4IF EQU 0x00000010 ; Capture/Compare 4 interrupt flag
TIM8_SR_CC4IF_ofs EQU 4
TIM8_SR_CC4IF_len EQU 1
TIM8_SR_COMIF EQU 0x00000020 ; COM interrupt flag
TIM8_SR_COMIF_ofs EQU 5
TIM8_SR_COMIF_len EQU 1
TIM8_SR_TIF EQU 0x00000040 ; Trigger interrupt flag
TIM8_SR_TIF_ofs EQU 6
TIM8_SR_TIF_len EQU 1
TIM8_SR_BIF EQU 0x00000080 ; Break interrupt flag
TIM8_SR_BIF_ofs EQU 7
TIM8_SR_BIF_len EQU 1
TIM8_SR_B2IF EQU 0x00000100 ; Break 2 interrupt flag
TIM8_SR_B2IF_ofs EQU 8
TIM8_SR_B2IF_len EQU 1
TIM8_SR_CC1OF EQU 0x00000200 ; Capture/Compare 1 overcapture flag
TIM8_SR_CC1OF_ofs EQU 9
TIM8_SR_CC1OF_len EQU 1
TIM8_SR_CC2OF EQU 0x00000400 ; Capture/compare 2 overcapture flag
TIM8_SR_CC2OF_ofs EQU 10
TIM8_SR_CC2OF_len EQU 1
TIM8_SR_CC3OF EQU 0x00000800 ; Capture/Compare 3 overcapture flag
TIM8_SR_CC3OF_ofs EQU 11
TIM8_SR_CC3OF_len EQU 1
TIM8_SR_CC4OF EQU 0x00001000 ; Capture/Compare 4 overcapture flag
TIM8_SR_CC4OF_ofs EQU 12
TIM8_SR_CC4OF_len EQU 1
TIM8_SR_C5IF EQU 0x00010000 ; Capture/Compare 5 interrupt flag
TIM8_SR_C5IF_ofs EQU 16
TIM8_SR_C5IF_len EQU 1
TIM8_SR_C6IF EQU 0x00020000 ; Capture/Compare 6 interrupt flag
TIM8_SR_C6IF_ofs EQU 17
TIM8_SR_C6IF_len EQU 1
; TIM8_EGR fields:
TIM8_EGR_UG EQU 0x00000001 ; Update generation
TIM8_EGR_UG_ofs EQU 0
TIM8_EGR_UG_len EQU 1
TIM8_EGR_CC1G EQU 0x00000002 ; Capture/compare 1 generation
TIM8_EGR_CC1G_ofs EQU 1
TIM8_EGR_CC1G_len EQU 1
TIM8_EGR_CC2G EQU 0x00000004 ; Capture/compare 2 generation
TIM8_EGR_CC2G_ofs EQU 2
TIM8_EGR_CC2G_len EQU 1
TIM8_EGR_CC3G EQU 0x00000008 ; Capture/compare 3 generation
TIM8_EGR_CC3G_ofs EQU 3
TIM8_EGR_CC3G_len EQU 1
TIM8_EGR_CC4G EQU 0x00000010 ; Capture/compare 4 generation
TIM8_EGR_CC4G_ofs EQU 4
TIM8_EGR_CC4G_len EQU 1
TIM8_EGR_COMG EQU 0x00000020 ; Capture/Compare control update generation
TIM8_EGR_COMG_ofs EQU 5
TIM8_EGR_COMG_len EQU 1
TIM8_EGR_TG EQU 0x00000040 ; Trigger generation
TIM8_EGR_TG_ofs EQU 6
TIM8_EGR_TG_len EQU 1
TIM8_EGR_BG EQU 0x00000080 ; Break generation
TIM8_EGR_BG_ofs EQU 7
TIM8_EGR_BG_len EQU 1
TIM8_EGR_B2G EQU 0x00000100 ; Break 2 generation
TIM8_EGR_B2G_ofs EQU 8
TIM8_EGR_B2G_len EQU 1
; TIM8_CCMR1_Output fields:
TIM8_CCMR1_Output_OC2CE EQU 0x00008000 ; Output Compare 2 clear enable
TIM8_CCMR1_Output_OC2CE_ofs EQU 15
TIM8_CCMR1_Output_OC2CE_len EQU 1
TIM8_CCMR1_Output_OC2M EQU 0x00007000 ; Output Compare 2 mode
TIM8_CCMR1_Output_OC2M_ofs EQU 12
TIM8_CCMR1_Output_OC2M_len EQU 3
TIM8_CCMR1_Output_OC2PE EQU 0x00000800 ; Output Compare 2 preload enable
TIM8_CCMR1_Output_OC2PE_ofs EQU 11
TIM8_CCMR1_Output_OC2PE_len EQU 1
TIM8_CCMR1_Output_OC2FE EQU 0x00000400 ; Output Compare 2 fast enable
TIM8_CCMR1_Output_OC2FE_ofs EQU 10
TIM8_CCMR1_Output_OC2FE_len EQU 1
TIM8_CCMR1_Output_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM8_CCMR1_Output_CC2S_ofs EQU 8
TIM8_CCMR1_Output_CC2S_len EQU 2
TIM8_CCMR1_Output_OC1CE EQU 0x00000080 ; Output Compare 1 clear enable
TIM8_CCMR1_Output_OC1CE_ofs EQU 7
TIM8_CCMR1_Output_OC1CE_len EQU 1
TIM8_CCMR1_Output_OC1M EQU 0x00000070 ; Output Compare 1 mode
TIM8_CCMR1_Output_OC1M_ofs EQU 4
TIM8_CCMR1_Output_OC1M_len EQU 3
TIM8_CCMR1_Output_OC1PE EQU 0x00000008 ; Output Compare 1 preload enable
TIM8_CCMR1_Output_OC1PE_ofs EQU 3
TIM8_CCMR1_Output_OC1PE_len EQU 1
TIM8_CCMR1_Output_OC1FE EQU 0x00000004 ; Output Compare 1 fast enable
TIM8_CCMR1_Output_OC1FE_ofs EQU 2
TIM8_CCMR1_Output_OC1FE_len EQU 1
TIM8_CCMR1_Output_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM8_CCMR1_Output_CC1S_ofs EQU 0
TIM8_CCMR1_Output_CC1S_len EQU 2
TIM8_CCMR1_Output_OC1M_3 EQU 0x00010000 ; Output Compare 1 mode bit 3
TIM8_CCMR1_Output_OC1M_3_ofs EQU 16
TIM8_CCMR1_Output_OC1M_3_len EQU 1
TIM8_CCMR1_Output_OC2M_3 EQU 0x01000000 ; Output Compare 2 mode bit 3
TIM8_CCMR1_Output_OC2M_3_ofs EQU 24
TIM8_CCMR1_Output_OC2M_3_len EQU 1
; TIM8_CCMR1_Input fields:
TIM8_CCMR1_Input_IC2F EQU 0x0000f000 ; Input capture 2 filter
TIM8_CCMR1_Input_IC2F_ofs EQU 12
TIM8_CCMR1_Input_IC2F_len EQU 4
TIM8_CCMR1_Input_IC2PCS EQU 0x00000c00 ; Input capture 2 prescaler
TIM8_CCMR1_Input_IC2PCS_ofs EQU 10
TIM8_CCMR1_Input_IC2PCS_len EQU 2
TIM8_CCMR1_Input_CC2S EQU 0x00000300 ; Capture/Compare 2 selection
TIM8_CCMR1_Input_CC2S_ofs EQU 8
TIM8_CCMR1_Input_CC2S_len EQU 2
TIM8_CCMR1_Input_IC1F EQU 0x000000f0 ; Input capture 1 filter
TIM8_CCMR1_Input_IC1F_ofs EQU 4
TIM8_CCMR1_Input_IC1F_len EQU 4
TIM8_CCMR1_Input_IC1PCS EQU 0x0000000c ; Input capture 1 prescaler
TIM8_CCMR1_Input_IC1PCS_ofs EQU 2
TIM8_CCMR1_Input_IC1PCS_len EQU 2
TIM8_CCMR1_Input_CC1S EQU 0x00000003 ; Capture/Compare 1 selection
TIM8_CCMR1_Input_CC1S_ofs EQU 0
TIM8_CCMR1_Input_CC1S_len EQU 2
; TIM8_CCMR2_Output fields:
TIM8_CCMR2_Output_OC4CE EQU 0x00008000 ; Output compare 4 clear enable
TIM8_CCMR2_Output_OC4CE_ofs EQU 15
TIM8_CCMR2_Output_OC4CE_len EQU 1
TIM8_CCMR2_Output_OC4M EQU 0x00007000 ; Output compare 4 mode
TIM8_CCMR2_Output_OC4M_ofs EQU 12
TIM8_CCMR2_Output_OC4M_len EQU 3
TIM8_CCMR2_Output_OC4PE EQU 0x00000800 ; Output compare 4 preload enable
TIM8_CCMR2_Output_OC4PE_ofs EQU 11
TIM8_CCMR2_Output_OC4PE_len EQU 1
TIM8_CCMR2_Output_OC4FE EQU 0x00000400 ; Output compare 4 fast enable
TIM8_CCMR2_Output_OC4FE_ofs EQU 10
TIM8_CCMR2_Output_OC4FE_len EQU 1
TIM8_CCMR2_Output_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM8_CCMR2_Output_CC4S_ofs EQU 8
TIM8_CCMR2_Output_CC4S_len EQU 2
TIM8_CCMR2_Output_OC3CE EQU 0x00000080 ; Output compare 3 clear enable
TIM8_CCMR2_Output_OC3CE_ofs EQU 7
TIM8_CCMR2_Output_OC3CE_len EQU 1
TIM8_CCMR2_Output_OC3M EQU 0x00000070 ; Output compare 3 mode
TIM8_CCMR2_Output_OC3M_ofs EQU 4
TIM8_CCMR2_Output_OC3M_len EQU 3
TIM8_CCMR2_Output_OC3PE EQU 0x00000008 ; Output compare 3 preload enable
TIM8_CCMR2_Output_OC3PE_ofs EQU 3
TIM8_CCMR2_Output_OC3PE_len EQU 1
TIM8_CCMR2_Output_OC3FE EQU 0x00000004 ; Output compare 3 fast enable
TIM8_CCMR2_Output_OC3FE_ofs EQU 2
TIM8_CCMR2_Output_OC3FE_len EQU 1
TIM8_CCMR2_Output_CC3S EQU 0x00000003 ; Capture/Compare 3 selection
TIM8_CCMR2_Output_CC3S_ofs EQU 0
TIM8_CCMR2_Output_CC3S_len EQU 2
TIM8_CCMR2_Output_OC3M_3 EQU 0x00010000 ; Output Compare 3 mode bit 3
TIM8_CCMR2_Output_OC3M_3_ofs EQU 16
TIM8_CCMR2_Output_OC3M_3_len EQU 1
TIM8_CCMR2_Output_OC4M_3 EQU 0x01000000 ; Output Compare 4 mode bit 3
TIM8_CCMR2_Output_OC4M_3_ofs EQU 24
TIM8_CCMR2_Output_OC4M_3_len EQU 1
; TIM8_CCMR2_Input fields:
TIM8_CCMR2_Input_IC4F EQU 0x0000f000 ; Input capture 4 filter
TIM8_CCMR2_Input_IC4F_ofs EQU 12
TIM8_CCMR2_Input_IC4F_len EQU 4
TIM8_CCMR2_Input_IC4PSC EQU 0x00000c00 ; Input capture 4 prescaler
TIM8_CCMR2_Input_IC4PSC_ofs EQU 10
TIM8_CCMR2_Input_IC4PSC_len EQU 2
TIM8_CCMR2_Input_CC4S EQU 0x00000300 ; Capture/Compare 4 selection
TIM8_CCMR2_Input_CC4S_ofs EQU 8
TIM8_CCMR2_Input_CC4S_len EQU 2
TIM8_CCMR2_Input_IC3F EQU 0x000000f0 ; Input capture 3 filter
TIM8_CCMR2_Input_IC3F_ofs EQU 4
TIM8_CCMR2_Input_IC3F_len EQU 4
TIM8_CCMR2_Input_IC3PSC EQU 0x0000000c ; Input capture 3 prescaler
TIM8_CCMR2_Input_IC3PSC_ofs EQU 2
TIM8_CCMR2_Input_IC3PSC_len EQU 2
TIM8_CCMR2_Input_CC3S EQU 0x00000003 ; Capture/compare 3 selection
TIM8_CCMR2_Input_CC3S_ofs EQU 0
TIM8_CCMR2_Input_CC3S_len EQU 2
; TIM8_CCER fields:
TIM8_CCER_CC1E EQU 0x00000001 ; Capture/Compare 1 output enable
TIM8_CCER_CC1E_ofs EQU 0
TIM8_CCER_CC1E_len EQU 1
TIM8_CCER_CC1P EQU 0x00000002 ; Capture/Compare 1 output Polarity
TIM8_CCER_CC1P_ofs EQU 1
TIM8_CCER_CC1P_len EQU 1
TIM8_CCER_CC1NE EQU 0x00000004 ; Capture/Compare 1 complementary output enable
TIM8_CCER_CC1NE_ofs EQU 2
TIM8_CCER_CC1NE_len EQU 1
TIM8_CCER_CC1NP EQU 0x00000008 ; Capture/Compare 1 output Polarity
TIM8_CCER_CC1NP_ofs EQU 3
TIM8_CCER_CC1NP_len EQU 1
TIM8_CCER_CC2E EQU 0x00000010 ; Capture/Compare 2 output enable
TIM8_CCER_CC2E_ofs EQU 4
TIM8_CCER_CC2E_len EQU 1
TIM8_CCER_CC2P EQU 0x00000020 ; Capture/Compare 2 output Polarity
TIM8_CCER_CC2P_ofs EQU 5
TIM8_CCER_CC2P_len EQU 1
TIM8_CCER_CC2NE EQU 0x00000040 ; Capture/Compare 2 complementary output enable
TIM8_CCER_CC2NE_ofs EQU 6
TIM8_CCER_CC2NE_len EQU 1
TIM8_CCER_CC2NP EQU 0x00000080 ; Capture/Compare 2 output Polarity
TIM8_CCER_CC2NP_ofs EQU 7
TIM8_CCER_CC2NP_len EQU 1
TIM8_CCER_CC3E EQU 0x00000100 ; Capture/Compare 3 output enable
TIM8_CCER_CC3E_ofs EQU 8
TIM8_CCER_CC3E_len EQU 1
TIM8_CCER_CC3P EQU 0x00000200 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC3P_ofs EQU 9
TIM8_CCER_CC3P_len EQU 1
TIM8_CCER_CC3NE EQU 0x00000400 ; Capture/Compare 3 complementary output enable
TIM8_CCER_CC3NE_ofs EQU 10
TIM8_CCER_CC3NE_len EQU 1
TIM8_CCER_CC3NP EQU 0x00000800 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC3NP_ofs EQU 11
TIM8_CCER_CC3NP_len EQU 1
TIM8_CCER_CC4E EQU 0x00001000 ; Capture/Compare 4 output enable
TIM8_CCER_CC4E_ofs EQU 12
TIM8_CCER_CC4E_len EQU 1
TIM8_CCER_CC4P EQU 0x00002000 ; Capture/Compare 3 output Polarity
TIM8_CCER_CC4P_ofs EQU 13
TIM8_CCER_CC4P_len EQU 1
TIM8_CCER_CC4NP EQU 0x00008000 ; Capture/Compare 4 output Polarity
TIM8_CCER_CC4NP_ofs EQU 15
TIM8_CCER_CC4NP_len EQU 1
TIM8_CCER_CC5E EQU 0x00010000 ; Capture/Compare 5 output enable
TIM8_CCER_CC5E_ofs EQU 16
TIM8_CCER_CC5E_len EQU 1
TIM8_CCER_CC5P EQU 0x00020000 ; Capture/Compare 5 output Polarity
TIM8_CCER_CC5P_ofs EQU 17
TIM8_CCER_CC5P_len EQU 1
TIM8_CCER_CC6E EQU 0x00100000 ; Capture/Compare 6 output enable
TIM8_CCER_CC6E_ofs EQU 20
TIM8_CCER_CC6E_len EQU 1
TIM8_CCER_CC6P EQU 0x00200000 ; Capture/Compare 6 output Polarity
TIM8_CCER_CC6P_ofs EQU 21
TIM8_CCER_CC6P_len EQU 1
; TIM8_CNT fields:
TIM8_CNT_CNT EQU 0x0000ffff ; counter value
TIM8_CNT_CNT_ofs EQU 0
TIM8_CNT_CNT_len EQU 16
TIM8_CNT_UIFCPY EQU 0x80000000 ; UIF copy
TIM8_CNT_UIFCPY_ofs EQU 31
TIM8_CNT_UIFCPY_len EQU 1
; TIM8_PSC fields:
TIM8_PSC_PSC EQU 0x0000ffff ; Prescaler value
TIM8_PSC_PSC_ofs EQU 0
TIM8_PSC_PSC_len EQU 16
; TIM8_ARR fields:
TIM8_ARR_ARR EQU 0x0000ffff ; Auto-reload value
TIM8_ARR_ARR_ofs EQU 0
TIM8_ARR_ARR_len EQU 16
; TIM8_RCR fields:
TIM8_RCR_REP EQU 0x0000ffff ; Repetition counter value
TIM8_RCR_REP_ofs EQU 0
TIM8_RCR_REP_len EQU 16
; TIM8_CCR1 fields:
TIM8_CCR1_CCR1 EQU 0x0000ffff ; Capture/Compare 1 value
TIM8_CCR1_CCR1_ofs EQU 0
TIM8_CCR1_CCR1_len EQU 16
; TIM8_CCR2 fields:
TIM8_CCR2_CCR2 EQU 0x0000ffff ; Capture/Compare 2 value
TIM8_CCR2_CCR2_ofs EQU 0
TIM8_CCR2_CCR2_len EQU 16
; TIM8_CCR3 fields:
TIM8_CCR3_CCR3 EQU 0x0000ffff ; Capture/Compare 3 value
TIM8_CCR3_CCR3_ofs EQU 0
TIM8_CCR3_CCR3_len EQU 16
; TIM8_CCR4 fields:
TIM8_CCR4_CCR4 EQU 0x0000ffff ; Capture/Compare 3 value
TIM8_CCR4_CCR4_ofs EQU 0
TIM8_CCR4_CCR4_len EQU 16
; TIM8_BDTR fields:
TIM8_BDTR_DTG EQU 0x000000ff ; Dead-time generator setup
TIM8_BDTR_DTG_ofs EQU 0
TIM8_BDTR_DTG_len EQU 8
TIM8_BDTR_LOCK EQU 0x00000300 ; Lock configuration
TIM8_BDTR_LOCK_ofs EQU 8
TIM8_BDTR_LOCK_len EQU 2
TIM8_BDTR_OSSI EQU 0x00000400 ; Off-state selection for Idle mode
TIM8_BDTR_OSSI_ofs EQU 10
TIM8_BDTR_OSSI_len EQU 1
TIM8_BDTR_OSSR EQU 0x00000800 ; Off-state selection for Run mode
TIM8_BDTR_OSSR_ofs EQU 11
TIM8_BDTR_OSSR_len EQU 1
TIM8_BDTR_BKE EQU 0x00001000 ; Break enable
TIM8_BDTR_BKE_ofs EQU 12
TIM8_BDTR_BKE_len EQU 1
TIM8_BDTR_BKP EQU 0x00002000 ; Break polarity
TIM8_BDTR_BKP_ofs EQU 13
TIM8_BDTR_BKP_len EQU 1
TIM8_BDTR_AOE EQU 0x00004000 ; Automatic output enable
TIM8_BDTR_AOE_ofs EQU 14
TIM8_BDTR_AOE_len EQU 1
TIM8_BDTR_MOE EQU 0x00008000 ; Main output enable
TIM8_BDTR_MOE_ofs EQU 15
TIM8_BDTR_MOE_len EQU 1
TIM8_BDTR_BKF EQU 0x000f0000 ; Break filter
TIM8_BDTR_BKF_ofs EQU 16
TIM8_BDTR_BKF_len EQU 4
TIM8_BDTR_BK2F EQU 0x00f00000 ; Break 2 filter
TIM8_BDTR_BK2F_ofs EQU 20
TIM8_BDTR_BK2F_len EQU 4
TIM8_BDTR_BK2E EQU 0x01000000 ; Break 2 enable
TIM8_BDTR_BK2E_ofs EQU 24
TIM8_BDTR_BK2E_len EQU 1
TIM8_BDTR_BK2P EQU 0x02000000 ; Break 2 polarity
TIM8_BDTR_BK2P_ofs EQU 25
TIM8_BDTR_BK2P_len EQU 1
; TIM8_DCR fields:
TIM8_DCR_DBL EQU 0x00001f00 ; DMA burst length
TIM8_DCR_DBL_ofs EQU 8
TIM8_DCR_DBL_len EQU 5
TIM8_DCR_DBA EQU 0x0000001f ; DMA base address
TIM8_DCR_DBA_ofs EQU 0
TIM8_DCR_DBA_len EQU 5
; TIM8_DMAR fields:
TIM8_DMAR_DMAB EQU 0x0000ffff ; DMA register for burst accesses
TIM8_DMAR_DMAB_ofs EQU 0
TIM8_DMAR_DMAB_len EQU 16
; TIM8_CCMR3_Output fields:
TIM8_CCMR3_Output_OC5FE EQU 0x00000004 ; Output compare 5 fast enable
TIM8_CCMR3_Output_OC5FE_ofs EQU 2
TIM8_CCMR3_Output_OC5FE_len EQU 1
TIM8_CCMR3_Output_OC5PE EQU 0x00000008 ; Output compare 5 preload enable
TIM8_CCMR3_Output_OC5PE_ofs EQU 3
TIM8_CCMR3_Output_OC5PE_len EQU 1
TIM8_CCMR3_Output_OC5M EQU 0x00000070 ; Output compare 5 mode
TIM8_CCMR3_Output_OC5M_ofs EQU 4
TIM8_CCMR3_Output_OC5M_len EQU 3
TIM8_CCMR3_Output_OC5CE EQU 0x00000080 ; Output compare 5 clear enable
TIM8_CCMR3_Output_OC5CE_ofs EQU 7
TIM8_CCMR3_Output_OC5CE_len EQU 1
TIM8_CCMR3_Output_OC6FE EQU 0x00000400 ; Output compare 6 fast enable
TIM8_CCMR3_Output_OC6FE_ofs EQU 10
TIM8_CCMR3_Output_OC6FE_len EQU 1
TIM8_CCMR3_Output_OC6PE EQU 0x00000800 ; Output compare 6 preload enable
TIM8_CCMR3_Output_OC6PE_ofs EQU 11
TIM8_CCMR3_Output_OC6PE_len EQU 1
TIM8_CCMR3_Output_OC6M EQU 0x00007000 ; Output compare 6 mode
TIM8_CCMR3_Output_OC6M_ofs EQU 12
TIM8_CCMR3_Output_OC6M_len EQU 3
TIM8_CCMR3_Output_OC6CE EQU 0x00008000 ; Output compare 6 clear enable
TIM8_CCMR3_Output_OC6CE_ofs EQU 15
TIM8_CCMR3_Output_OC6CE_len EQU 1
TIM8_CCMR3_Output_OC5M_3 EQU 0x00010000 ; Outout Compare 5 mode bit 3
TIM8_CCMR3_Output_OC5M_3_ofs EQU 16
TIM8_CCMR3_Output_OC5M_3_len EQU 1
TIM8_CCMR3_Output_OC6M_3 EQU 0x01000000 ; Outout Compare 6 mode bit 3
TIM8_CCMR3_Output_OC6M_3_ofs EQU 24
TIM8_CCMR3_Output_OC6M_3_len EQU 1
; TIM8_CCR5 fields:
TIM8_CCR5_CCR5 EQU 0x0000ffff ; Capture/Compare 5 value
TIM8_CCR5_CCR5_ofs EQU 0
TIM8_CCR5_CCR5_len EQU 16
TIM8_CCR5_GC5C1 EQU 0x20000000 ; Group Channel 5 and Channel 1
TIM8_CCR5_GC5C1_ofs EQU 29
TIM8_CCR5_GC5C1_len EQU 1
TIM8_CCR5_GC5C2 EQU 0x40000000 ; Group Channel 5 and Channel 2
TIM8_CCR5_GC5C2_ofs EQU 30
TIM8_CCR5_GC5C2_len EQU 1
TIM8_CCR5_GC5C3 EQU 0x80000000 ; Group Channel 5 and Channel 3
TIM8_CCR5_GC5C3_ofs EQU 31
TIM8_CCR5_GC5C3_len EQU 1
; TIM8_CCR6 fields:
TIM8_CCR6_CCR6 EQU 0x0000ffff ; Capture/Compare 6 value
TIM8_CCR6_CCR6_ofs EQU 0
TIM8_CCR6_CCR6_len EQU 16
; TIM8_OR fields:
TIM8_OR_TIM8_ETR_ADC2_RMP EQU 0x00000003 ; TIM8_ETR_ADC2 remapping capability
TIM8_OR_TIM8_ETR_ADC2_RMP_ofs EQU 0
TIM8_OR_TIM8_ETR_ADC2_RMP_len EQU 2
TIM8_OR_TIM8_ETR_ADC3_RMP EQU 0x0000000c ; TIM8_ETR_ADC3 remapping capability
TIM8_OR_TIM8_ETR_ADC3_RMP_ofs EQU 2
TIM8_OR_TIM8_ETR_ADC3_RMP_len EQU 2
; ---- ADC1 --------------------------------------------------
; Desc: Analog-to-Digital Converter
; ADC1 base address:
ADC1_BASE EQU 0x50000000
; ADC1 registers:
ADC1_ISR EQU (ADC1_BASE + 0x0) ; interrupt and status register
ADC1_IER EQU (ADC1_BASE + 0x4) ; interrupt enable register
ADC1_CR EQU (ADC1_BASE + 0x8) ; control register
ADC1_CFGR EQU (ADC1_BASE + 0xc) ; configuration register
ADC1_SMPR1 EQU (ADC1_BASE + 0x14) ; sample time register 1
ADC1_SMPR2 EQU (ADC1_BASE + 0x18) ; sample time register 2
ADC1_TR1 EQU (ADC1_BASE + 0x20) ; watchdog threshold register 1
ADC1_TR2 EQU (ADC1_BASE + 0x24) ; watchdog threshold register
ADC1_TR3 EQU (ADC1_BASE + 0x28) ; watchdog threshold register 3
ADC1_SQR1 EQU (ADC1_BASE + 0x30) ; regular sequence register 1
ADC1_SQR2 EQU (ADC1_BASE + 0x34) ; regular sequence register 2
ADC1_SQR3 EQU (ADC1_BASE + 0x38) ; regular sequence register 3
ADC1_SQR4 EQU (ADC1_BASE + 0x3c) ; regular sequence register 4
ADC1_DR EQU (ADC1_BASE + 0x40) ; regular Data Register
ADC1_JSQR EQU (ADC1_BASE + 0x4c) ; injected sequence register
ADC1_OFR1 EQU (ADC1_BASE + 0x60) ; offset register 1
ADC1_OFR2 EQU (ADC1_BASE + 0x64) ; offset register 2
ADC1_OFR3 EQU (ADC1_BASE + 0x68) ; offset register 3
ADC1_OFR4 EQU (ADC1_BASE + 0x6c) ; offset register 4
ADC1_JDR1 EQU (ADC1_BASE + 0x80) ; injected data register 1
ADC1_JDR2 EQU (ADC1_BASE + 0x84) ; injected data register 2
ADC1_JDR3 EQU (ADC1_BASE + 0x88) ; injected data register 3
ADC1_JDR4 EQU (ADC1_BASE + 0x8c) ; injected data register 4
ADC1_AWD2CR EQU (ADC1_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC1_AWD3CR EQU (ADC1_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC1_DIFSEL EQU (ADC1_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC1_CALFACT EQU (ADC1_BASE + 0xb4) ; Calibration Factors
; ADC1_ISR fields:
ADC1_ISR_JQOVF EQU 0x00000400 ; JQOVF
ADC1_ISR_JQOVF_ofs EQU 10
ADC1_ISR_JQOVF_len EQU 1
ADC1_ISR_AWD3 EQU 0x00000200 ; AWD3
ADC1_ISR_AWD3_ofs EQU 9
ADC1_ISR_AWD3_len EQU 1
ADC1_ISR_AWD2 EQU 0x00000100 ; AWD2
ADC1_ISR_AWD2_ofs EQU 8
ADC1_ISR_AWD2_len EQU 1
ADC1_ISR_AWD1 EQU 0x00000080 ; AWD1
ADC1_ISR_AWD1_ofs EQU 7
ADC1_ISR_AWD1_len EQU 1
ADC1_ISR_JEOS EQU 0x00000040 ; JEOS
ADC1_ISR_JEOS_ofs EQU 6
ADC1_ISR_JEOS_len EQU 1
ADC1_ISR_JEOC EQU 0x00000020 ; JEOC
ADC1_ISR_JEOC_ofs EQU 5
ADC1_ISR_JEOC_len EQU 1
ADC1_ISR_OVR EQU 0x00000010 ; OVR
ADC1_ISR_OVR_ofs EQU 4
ADC1_ISR_OVR_len EQU 1
ADC1_ISR_EOS EQU 0x00000008 ; EOS
ADC1_ISR_EOS_ofs EQU 3
ADC1_ISR_EOS_len EQU 1
ADC1_ISR_EOC EQU 0x00000004 ; EOC
ADC1_ISR_EOC_ofs EQU 2
ADC1_ISR_EOC_len EQU 1
ADC1_ISR_EOSMP EQU 0x00000002 ; EOSMP
ADC1_ISR_EOSMP_ofs EQU 1
ADC1_ISR_EOSMP_len EQU 1
ADC1_ISR_ADRDY EQU 0x00000001 ; ADRDY
ADC1_ISR_ADRDY_ofs EQU 0
ADC1_ISR_ADRDY_len EQU 1
; ADC1_IER fields:
ADC1_IER_JQOVFIE EQU 0x00000400 ; JQOVFIE
ADC1_IER_JQOVFIE_ofs EQU 10
ADC1_IER_JQOVFIE_len EQU 1
ADC1_IER_AWD3IE EQU 0x00000200 ; AWD3IE
ADC1_IER_AWD3IE_ofs EQU 9
ADC1_IER_AWD3IE_len EQU 1
ADC1_IER_AWD2IE EQU 0x00000100 ; AWD2IE
ADC1_IER_AWD2IE_ofs EQU 8
ADC1_IER_AWD2IE_len EQU 1
ADC1_IER_AWD1IE EQU 0x00000080 ; AWD1IE
ADC1_IER_AWD1IE_ofs EQU 7
ADC1_IER_AWD1IE_len EQU 1
ADC1_IER_JEOSIE EQU 0x00000040 ; JEOSIE
ADC1_IER_JEOSIE_ofs EQU 6
ADC1_IER_JEOSIE_len EQU 1
ADC1_IER_JEOCIE EQU 0x00000020 ; JEOCIE
ADC1_IER_JEOCIE_ofs EQU 5
ADC1_IER_JEOCIE_len EQU 1
ADC1_IER_OVRIE EQU 0x00000010 ; OVRIE
ADC1_IER_OVRIE_ofs EQU 4
ADC1_IER_OVRIE_len EQU 1
ADC1_IER_EOSIE EQU 0x00000008 ; EOSIE
ADC1_IER_EOSIE_ofs EQU 3
ADC1_IER_EOSIE_len EQU 1
ADC1_IER_EOCIE EQU 0x00000004 ; EOCIE
ADC1_IER_EOCIE_ofs EQU 2
ADC1_IER_EOCIE_len EQU 1
ADC1_IER_EOSMPIE EQU 0x00000002 ; EOSMPIE
ADC1_IER_EOSMPIE_ofs EQU 1
ADC1_IER_EOSMPIE_len EQU 1
ADC1_IER_ADRDYIE EQU 0x00000001 ; ADRDYIE
ADC1_IER_ADRDYIE_ofs EQU 0
ADC1_IER_ADRDYIE_len EQU 1
; ADC1_CR fields:
ADC1_CR_ADCAL EQU 0x80000000 ; ADCAL
ADC1_CR_ADCAL_ofs EQU 31
ADC1_CR_ADCAL_len EQU 1
ADC1_CR_ADCALDIF EQU 0x40000000 ; ADCALDIF
ADC1_CR_ADCALDIF_ofs EQU 30
ADC1_CR_ADCALDIF_len EQU 1
ADC1_CR_DEEPPWD EQU 0x20000000 ; DEEPPWD
ADC1_CR_DEEPPWD_ofs EQU 29
ADC1_CR_DEEPPWD_len EQU 1
ADC1_CR_ADVREGEN EQU 0x10000000 ; ADVREGEN
ADC1_CR_ADVREGEN_ofs EQU 28
ADC1_CR_ADVREGEN_len EQU 1
ADC1_CR_JADSTP EQU 0x00000020 ; JADSTP
ADC1_CR_JADSTP_ofs EQU 5
ADC1_CR_JADSTP_len EQU 1
ADC1_CR_ADSTP EQU 0x00000010 ; ADSTP
ADC1_CR_ADSTP_ofs EQU 4
ADC1_CR_ADSTP_len EQU 1
ADC1_CR_JADSTART EQU 0x00000008 ; JADSTART
ADC1_CR_JADSTART_ofs EQU 3
ADC1_CR_JADSTART_len EQU 1
ADC1_CR_ADSTART EQU 0x00000004 ; ADSTART
ADC1_CR_ADSTART_ofs EQU 2
ADC1_CR_ADSTART_len EQU 1
ADC1_CR_ADDIS EQU 0x00000002 ; ADDIS
ADC1_CR_ADDIS_ofs EQU 1
ADC1_CR_ADDIS_len EQU 1
ADC1_CR_ADEN EQU 0x00000001 ; ADEN
ADC1_CR_ADEN_ofs EQU 0
ADC1_CR_ADEN_len EQU 1
; ADC1_CFGR fields:
ADC1_CFGR_AWDCH1CH EQU 0x7c000000 ; AWDCH1CH
ADC1_CFGR_AWDCH1CH_ofs EQU 26
ADC1_CFGR_AWDCH1CH_len EQU 5
ADC1_CFGR_JAUTO EQU 0x02000000 ; JAUTO
ADC1_CFGR_JAUTO_ofs EQU 25
ADC1_CFGR_JAUTO_len EQU 1
ADC1_CFGR_JAWD1EN EQU 0x01000000 ; JAWD1EN
ADC1_CFGR_JAWD1EN_ofs EQU 24
ADC1_CFGR_JAWD1EN_len EQU 1
ADC1_CFGR_AWD1EN EQU 0x00800000 ; AWD1EN
ADC1_CFGR_AWD1EN_ofs EQU 23
ADC1_CFGR_AWD1EN_len EQU 1
ADC1_CFGR_AWD1SGL EQU 0x00400000 ; AWD1SGL
ADC1_CFGR_AWD1SGL_ofs EQU 22
ADC1_CFGR_AWD1SGL_len EQU 1
ADC1_CFGR_JQM EQU 0x00200000 ; JQM
ADC1_CFGR_JQM_ofs EQU 21
ADC1_CFGR_JQM_len EQU 1
ADC1_CFGR_JDISCEN EQU 0x00100000 ; JDISCEN
ADC1_CFGR_JDISCEN_ofs EQU 20
ADC1_CFGR_JDISCEN_len EQU 1
ADC1_CFGR_DISCNUM EQU 0x000e0000 ; DISCNUM
ADC1_CFGR_DISCNUM_ofs EQU 17
ADC1_CFGR_DISCNUM_len EQU 3
ADC1_CFGR_DISCEN EQU 0x00010000 ; DISCEN
ADC1_CFGR_DISCEN_ofs EQU 16
ADC1_CFGR_DISCEN_len EQU 1
ADC1_CFGR_AUTOFF EQU 0x00008000 ; AUTOFF
ADC1_CFGR_AUTOFF_ofs EQU 15
ADC1_CFGR_AUTOFF_len EQU 1
ADC1_CFGR_AUTDLY EQU 0x00004000 ; AUTDLY
ADC1_CFGR_AUTDLY_ofs EQU 14
ADC1_CFGR_AUTDLY_len EQU 1
ADC1_CFGR_CONT EQU 0x00002000 ; CONT
ADC1_CFGR_CONT_ofs EQU 13
ADC1_CFGR_CONT_len EQU 1
ADC1_CFGR_OVRMOD EQU 0x00001000 ; OVRMOD
ADC1_CFGR_OVRMOD_ofs EQU 12
ADC1_CFGR_OVRMOD_len EQU 1
ADC1_CFGR_EXTEN EQU 0x00000c00 ; EXTEN
ADC1_CFGR_EXTEN_ofs EQU 10
ADC1_CFGR_EXTEN_len EQU 2
ADC1_CFGR_EXTSEL EQU 0x000003c0 ; EXTSEL
ADC1_CFGR_EXTSEL_ofs EQU 6
ADC1_CFGR_EXTSEL_len EQU 4
ADC1_CFGR_ALIGN EQU 0x00000020 ; ALIGN
ADC1_CFGR_ALIGN_ofs EQU 5
ADC1_CFGR_ALIGN_len EQU 1
ADC1_CFGR_RES EQU 0x00000018 ; RES
ADC1_CFGR_RES_ofs EQU 3
ADC1_CFGR_RES_len EQU 2
ADC1_CFGR_DMACFG EQU 0x00000002 ; DMACFG
ADC1_CFGR_DMACFG_ofs EQU 1
ADC1_CFGR_DMACFG_len EQU 1
ADC1_CFGR_DMAEN EQU 0x00000001 ; DMAEN
ADC1_CFGR_DMAEN_ofs EQU 0
ADC1_CFGR_DMAEN_len EQU 1
; ADC1_SMPR1 fields:
ADC1_SMPR1_SMP9 EQU 0x38000000 ; SMP9
ADC1_SMPR1_SMP9_ofs EQU 27
ADC1_SMPR1_SMP9_len EQU 3
ADC1_SMPR1_SMP8 EQU 0x07000000 ; SMP8
ADC1_SMPR1_SMP8_ofs EQU 24
ADC1_SMPR1_SMP8_len EQU 3
ADC1_SMPR1_SMP7 EQU 0x00e00000 ; SMP7
ADC1_SMPR1_SMP7_ofs EQU 21
ADC1_SMPR1_SMP7_len EQU 3
ADC1_SMPR1_SMP6 EQU 0x001c0000 ; SMP6
ADC1_SMPR1_SMP6_ofs EQU 18
ADC1_SMPR1_SMP6_len EQU 3
ADC1_SMPR1_SMP5 EQU 0x00038000 ; SMP5
ADC1_SMPR1_SMP5_ofs EQU 15
ADC1_SMPR1_SMP5_len EQU 3
ADC1_SMPR1_SMP4 EQU 0x00007000 ; SMP4
ADC1_SMPR1_SMP4_ofs EQU 12
ADC1_SMPR1_SMP4_len EQU 3
ADC1_SMPR1_SMP3 EQU 0x00000e00 ; SMP3
ADC1_SMPR1_SMP3_ofs EQU 9
ADC1_SMPR1_SMP3_len EQU 3
ADC1_SMPR1_SMP2 EQU 0x000001c0 ; SMP2
ADC1_SMPR1_SMP2_ofs EQU 6
ADC1_SMPR1_SMP2_len EQU 3
ADC1_SMPR1_SMP1 EQU 0x00000038 ; SMP1
ADC1_SMPR1_SMP1_ofs EQU 3
ADC1_SMPR1_SMP1_len EQU 3
; ADC1_SMPR2 fields:
ADC1_SMPR2_SMP18 EQU 0x07000000 ; SMP18
ADC1_SMPR2_SMP18_ofs EQU 24
ADC1_SMPR2_SMP18_len EQU 3
ADC1_SMPR2_SMP17 EQU 0x00e00000 ; SMP17
ADC1_SMPR2_SMP17_ofs EQU 21
ADC1_SMPR2_SMP17_len EQU 3
ADC1_SMPR2_SMP16 EQU 0x001c0000 ; SMP16
ADC1_SMPR2_SMP16_ofs EQU 18
ADC1_SMPR2_SMP16_len EQU 3
ADC1_SMPR2_SMP15 EQU 0x00038000 ; SMP15
ADC1_SMPR2_SMP15_ofs EQU 15
ADC1_SMPR2_SMP15_len EQU 3
ADC1_SMPR2_SMP14 EQU 0x00007000 ; SMP14
ADC1_SMPR2_SMP14_ofs EQU 12
ADC1_SMPR2_SMP14_len EQU 3
ADC1_SMPR2_SMP13 EQU 0x00000e00 ; SMP13
ADC1_SMPR2_SMP13_ofs EQU 9
ADC1_SMPR2_SMP13_len EQU 3
ADC1_SMPR2_SMP12 EQU 0x000001c0 ; SMP12
ADC1_SMPR2_SMP12_ofs EQU 6
ADC1_SMPR2_SMP12_len EQU 3
ADC1_SMPR2_SMP11 EQU 0x00000038 ; SMP11
ADC1_SMPR2_SMP11_ofs EQU 3
ADC1_SMPR2_SMP11_len EQU 3
ADC1_SMPR2_SMP10 EQU 0x00000007 ; SMP10
ADC1_SMPR2_SMP10_ofs EQU 0
ADC1_SMPR2_SMP10_len EQU 3
; ADC1_TR1 fields:
ADC1_TR1_HT1 EQU 0x0fff0000 ; HT1
ADC1_TR1_HT1_ofs EQU 16
ADC1_TR1_HT1_len EQU 12
ADC1_TR1_LT1 EQU 0x00000fff ; LT1
ADC1_TR1_LT1_ofs EQU 0
ADC1_TR1_LT1_len EQU 12
; ADC1_TR2 fields:
ADC1_TR2_HT2 EQU 0x00ff0000 ; HT2
ADC1_TR2_HT2_ofs EQU 16
ADC1_TR2_HT2_len EQU 8
ADC1_TR2_LT2 EQU 0x000000ff ; LT2
ADC1_TR2_LT2_ofs EQU 0
ADC1_TR2_LT2_len EQU 8
; ADC1_TR3 fields:
ADC1_TR3_HT3 EQU 0x00ff0000 ; HT3
ADC1_TR3_HT3_ofs EQU 16
ADC1_TR3_HT3_len EQU 8
ADC1_TR3_LT3 EQU 0x000000ff ; LT3
ADC1_TR3_LT3_ofs EQU 0
ADC1_TR3_LT3_len EQU 8
; ADC1_SQR1 fields:
ADC1_SQR1_SQ4 EQU 0x1f000000 ; SQ4
ADC1_SQR1_SQ4_ofs EQU 24
ADC1_SQR1_SQ4_len EQU 5
ADC1_SQR1_SQ3 EQU 0x007c0000 ; SQ3
ADC1_SQR1_SQ3_ofs EQU 18
ADC1_SQR1_SQ3_len EQU 5
ADC1_SQR1_SQ2 EQU 0x0001f000 ; SQ2
ADC1_SQR1_SQ2_ofs EQU 12
ADC1_SQR1_SQ2_len EQU 5
ADC1_SQR1_SQ1 EQU 0x000007c0 ; SQ1
ADC1_SQR1_SQ1_ofs EQU 6
ADC1_SQR1_SQ1_len EQU 5
ADC1_SQR1_L3 EQU 0x0000000f ; L3
ADC1_SQR1_L3_ofs EQU 0
ADC1_SQR1_L3_len EQU 4
; ADC1_SQR2 fields:
ADC1_SQR2_SQ9 EQU 0x1f000000 ; SQ9
ADC1_SQR2_SQ9_ofs EQU 24
ADC1_SQR2_SQ9_len EQU 5
ADC1_SQR2_SQ8 EQU 0x007c0000 ; SQ8
ADC1_SQR2_SQ8_ofs EQU 18
ADC1_SQR2_SQ8_len EQU 5
ADC1_SQR2_SQ7 EQU 0x0001f000 ; SQ7
ADC1_SQR2_SQ7_ofs EQU 12
ADC1_SQR2_SQ7_len EQU 5
ADC1_SQR2_SQ6 EQU 0x000007c0 ; SQ6
ADC1_SQR2_SQ6_ofs EQU 6
ADC1_SQR2_SQ6_len EQU 5
ADC1_SQR2_SQ5 EQU 0x0000001f ; SQ5
ADC1_SQR2_SQ5_ofs EQU 0
ADC1_SQR2_SQ5_len EQU 5
; ADC1_SQR3 fields:
ADC1_SQR3_SQ14 EQU 0x1f000000 ; SQ14
ADC1_SQR3_SQ14_ofs EQU 24
ADC1_SQR3_SQ14_len EQU 5
ADC1_SQR3_SQ13 EQU 0x007c0000 ; SQ13
ADC1_SQR3_SQ13_ofs EQU 18
ADC1_SQR3_SQ13_len EQU 5
ADC1_SQR3_SQ12 EQU 0x0001f000 ; SQ12
ADC1_SQR3_SQ12_ofs EQU 12
ADC1_SQR3_SQ12_len EQU 5
ADC1_SQR3_SQ11 EQU 0x000007c0 ; SQ11
ADC1_SQR3_SQ11_ofs EQU 6
ADC1_SQR3_SQ11_len EQU 5
ADC1_SQR3_SQ10 EQU 0x0000001f ; SQ10
ADC1_SQR3_SQ10_ofs EQU 0
ADC1_SQR3_SQ10_len EQU 5
; ADC1_SQR4 fields:
ADC1_SQR4_SQ16 EQU 0x000007c0 ; SQ16
ADC1_SQR4_SQ16_ofs EQU 6
ADC1_SQR4_SQ16_len EQU 5
ADC1_SQR4_SQ15 EQU 0x0000001f ; SQ15
ADC1_SQR4_SQ15_ofs EQU 0
ADC1_SQR4_SQ15_len EQU 5
; ADC1_DR fields:
ADC1_DR_regularDATA EQU 0x0000ffff ; regularDATA
ADC1_DR_regularDATA_ofs EQU 0
ADC1_DR_regularDATA_len EQU 16
; ADC1_JSQR fields:
ADC1_JSQR_JSQ4 EQU 0x7c000000 ; JSQ4
ADC1_JSQR_JSQ4_ofs EQU 26
ADC1_JSQR_JSQ4_len EQU 5
ADC1_JSQR_JSQ3 EQU 0x01f00000 ; JSQ3
ADC1_JSQR_JSQ3_ofs EQU 20
ADC1_JSQR_JSQ3_len EQU 5
ADC1_JSQR_JSQ2 EQU 0x0007c000 ; JSQ2
ADC1_JSQR_JSQ2_ofs EQU 14
ADC1_JSQR_JSQ2_len EQU 5
ADC1_JSQR_JSQ1 EQU 0x00001f00 ; JSQ1
ADC1_JSQR_JSQ1_ofs EQU 8
ADC1_JSQR_JSQ1_len EQU 5
ADC1_JSQR_JEXTEN EQU 0x000000c0 ; JEXTEN
ADC1_JSQR_JEXTEN_ofs EQU 6
ADC1_JSQR_JEXTEN_len EQU 2
ADC1_JSQR_JEXTSEL EQU 0x0000003c ; JEXTSEL
ADC1_JSQR_JEXTSEL_ofs EQU 2
ADC1_JSQR_JEXTSEL_len EQU 4
ADC1_JSQR_JL EQU 0x00000003 ; JL
ADC1_JSQR_JL_ofs EQU 0
ADC1_JSQR_JL_len EQU 2
; ADC1_OFR1 fields:
ADC1_OFR1_OFFSET1_EN EQU 0x80000000 ; OFFSET1_EN
ADC1_OFR1_OFFSET1_EN_ofs EQU 31
ADC1_OFR1_OFFSET1_EN_len EQU 1
ADC1_OFR1_OFFSET1_CH EQU 0x7c000000 ; OFFSET1_CH
ADC1_OFR1_OFFSET1_CH_ofs EQU 26
ADC1_OFR1_OFFSET1_CH_len EQU 5
ADC1_OFR1_OFFSET1 EQU 0x00000fff ; OFFSET1
ADC1_OFR1_OFFSET1_ofs EQU 0
ADC1_OFR1_OFFSET1_len EQU 12
; ADC1_OFR2 fields:
ADC1_OFR2_OFFSET2_EN EQU 0x80000000 ; OFFSET2_EN
ADC1_OFR2_OFFSET2_EN_ofs EQU 31
ADC1_OFR2_OFFSET2_EN_len EQU 1
ADC1_OFR2_OFFSET2_CH EQU 0x7c000000 ; OFFSET2_CH
ADC1_OFR2_OFFSET2_CH_ofs EQU 26
ADC1_OFR2_OFFSET2_CH_len EQU 5
ADC1_OFR2_OFFSET2 EQU 0x00000fff ; OFFSET2
ADC1_OFR2_OFFSET2_ofs EQU 0
ADC1_OFR2_OFFSET2_len EQU 12
; ADC1_OFR3 fields:
ADC1_OFR3_OFFSET3_EN EQU 0x80000000 ; OFFSET3_EN
ADC1_OFR3_OFFSET3_EN_ofs EQU 31
ADC1_OFR3_OFFSET3_EN_len EQU 1
ADC1_OFR3_OFFSET3_CH EQU 0x7c000000 ; OFFSET3_CH
ADC1_OFR3_OFFSET3_CH_ofs EQU 26
ADC1_OFR3_OFFSET3_CH_len EQU 5
ADC1_OFR3_OFFSET3 EQU 0x00000fff ; OFFSET3
ADC1_OFR3_OFFSET3_ofs EQU 0
ADC1_OFR3_OFFSET3_len EQU 12
; ADC1_OFR4 fields:
ADC1_OFR4_OFFSET4_EN EQU 0x80000000 ; OFFSET4_EN
ADC1_OFR4_OFFSET4_EN_ofs EQU 31
ADC1_OFR4_OFFSET4_EN_len EQU 1
ADC1_OFR4_OFFSET4_CH EQU 0x7c000000 ; OFFSET4_CH
ADC1_OFR4_OFFSET4_CH_ofs EQU 26
ADC1_OFR4_OFFSET4_CH_len EQU 5
ADC1_OFR4_OFFSET4 EQU 0x00000fff ; OFFSET4
ADC1_OFR4_OFFSET4_ofs EQU 0
ADC1_OFR4_OFFSET4_len EQU 12
; ADC1_JDR1 fields:
ADC1_JDR1_JDATA1 EQU 0x0000ffff ; JDATA1
ADC1_JDR1_JDATA1_ofs EQU 0
ADC1_JDR1_JDATA1_len EQU 16
; ADC1_JDR2 fields:
ADC1_JDR2_JDATA2 EQU 0x0000ffff ; JDATA2
ADC1_JDR2_JDATA2_ofs EQU 0
ADC1_JDR2_JDATA2_len EQU 16
; ADC1_JDR3 fields:
ADC1_JDR3_JDATA3 EQU 0x0000ffff ; JDATA3
ADC1_JDR3_JDATA3_ofs EQU 0
ADC1_JDR3_JDATA3_len EQU 16
; ADC1_JDR4 fields:
ADC1_JDR4_JDATA4 EQU 0x0000ffff ; JDATA4
ADC1_JDR4_JDATA4_ofs EQU 0
ADC1_JDR4_JDATA4_len EQU 16
; ADC1_AWD2CR fields:
ADC1_AWD2CR_AWD2CH EQU 0x0007fffe ; AWD2CH
ADC1_AWD2CR_AWD2CH_ofs EQU 1
ADC1_AWD2CR_AWD2CH_len EQU 18
; ADC1_AWD3CR fields:
ADC1_AWD3CR_AWD3CH EQU 0x0007fffe ; AWD3CH
ADC1_AWD3CR_AWD3CH_ofs EQU 1
ADC1_AWD3CR_AWD3CH_len EQU 18
; ADC1_DIFSEL fields:
ADC1_DIFSEL_DIFSEL_1_15 EQU 0x0000fffe ; Differential mode for channels 15 to 1
ADC1_DIFSEL_DIFSEL_1_15_ofs EQU 1
ADC1_DIFSEL_DIFSEL_1_15_len EQU 15
ADC1_DIFSEL_DIFSEL_16_18 EQU 0x00070000 ; Differential mode for channels 18 to 16
ADC1_DIFSEL_DIFSEL_16_18_ofs EQU 16
ADC1_DIFSEL_DIFSEL_16_18_len EQU 3
; ADC1_CALFACT fields:
ADC1_CALFACT_CALFACT_D EQU 0x007f0000 ; CALFACT_D
ADC1_CALFACT_CALFACT_D_ofs EQU 16
ADC1_CALFACT_CALFACT_D_len EQU 7
ADC1_CALFACT_CALFACT_S EQU 0x0000007f ; CALFACT_S
ADC1_CALFACT_CALFACT_S_ofs EQU 0
ADC1_CALFACT_CALFACT_S_len EQU 7
; ---- ADC2 --------------------------------------------------
; Desc: None
; ADC2 base address:
ADC2_BASE EQU 0x50000100
; ADC2 registers:
ADC2_ISR EQU (ADC2_BASE + 0x0) ; interrupt and status register
ADC2_IER EQU (ADC2_BASE + 0x4) ; interrupt enable register
ADC2_CR EQU (ADC2_BASE + 0x8) ; control register
ADC2_CFGR EQU (ADC2_BASE + 0xc) ; configuration register
ADC2_SMPR1 EQU (ADC2_BASE + 0x14) ; sample time register 1
ADC2_SMPR2 EQU (ADC2_BASE + 0x18) ; sample time register 2
ADC2_TR1 EQU (ADC2_BASE + 0x20) ; watchdog threshold register 1
ADC2_TR2 EQU (ADC2_BASE + 0x24) ; watchdog threshold register
ADC2_TR3 EQU (ADC2_BASE + 0x28) ; watchdog threshold register 3
ADC2_SQR1 EQU (ADC2_BASE + 0x30) ; regular sequence register 1
ADC2_SQR2 EQU (ADC2_BASE + 0x34) ; regular sequence register 2
ADC2_SQR3 EQU (ADC2_BASE + 0x38) ; regular sequence register 3
ADC2_SQR4 EQU (ADC2_BASE + 0x3c) ; regular sequence register 4
ADC2_DR EQU (ADC2_BASE + 0x40) ; regular Data Register
ADC2_JSQR EQU (ADC2_BASE + 0x4c) ; injected sequence register
ADC2_OFR1 EQU (ADC2_BASE + 0x60) ; offset register 1
ADC2_OFR2 EQU (ADC2_BASE + 0x64) ; offset register 2
ADC2_OFR3 EQU (ADC2_BASE + 0x68) ; offset register 3
ADC2_OFR4 EQU (ADC2_BASE + 0x6c) ; offset register 4
ADC2_JDR1 EQU (ADC2_BASE + 0x80) ; injected data register 1
ADC2_JDR2 EQU (ADC2_BASE + 0x84) ; injected data register 2
ADC2_JDR3 EQU (ADC2_BASE + 0x88) ; injected data register 3
ADC2_JDR4 EQU (ADC2_BASE + 0x8c) ; injected data register 4
ADC2_AWD2CR EQU (ADC2_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC2_AWD3CR EQU (ADC2_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC2_DIFSEL EQU (ADC2_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC2_CALFACT EQU (ADC2_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC3 --------------------------------------------------
; Desc: None
; ADC3 base address:
ADC3_BASE EQU 0x50000400
; ADC3 registers:
ADC3_ISR EQU (ADC3_BASE + 0x0) ; interrupt and status register
ADC3_IER EQU (ADC3_BASE + 0x4) ; interrupt enable register
ADC3_CR EQU (ADC3_BASE + 0x8) ; control register
ADC3_CFGR EQU (ADC3_BASE + 0xc) ; configuration register
ADC3_SMPR1 EQU (ADC3_BASE + 0x14) ; sample time register 1
ADC3_SMPR2 EQU (ADC3_BASE + 0x18) ; sample time register 2
ADC3_TR1 EQU (ADC3_BASE + 0x20) ; watchdog threshold register 1
ADC3_TR2 EQU (ADC3_BASE + 0x24) ; watchdog threshold register
ADC3_TR3 EQU (ADC3_BASE + 0x28) ; watchdog threshold register 3
ADC3_SQR1 EQU (ADC3_BASE + 0x30) ; regular sequence register 1
ADC3_SQR2 EQU (ADC3_BASE + 0x34) ; regular sequence register 2
ADC3_SQR3 EQU (ADC3_BASE + 0x38) ; regular sequence register 3
ADC3_SQR4 EQU (ADC3_BASE + 0x3c) ; regular sequence register 4
ADC3_DR EQU (ADC3_BASE + 0x40) ; regular Data Register
ADC3_JSQR EQU (ADC3_BASE + 0x4c) ; injected sequence register
ADC3_OFR1 EQU (ADC3_BASE + 0x60) ; offset register 1
ADC3_OFR2 EQU (ADC3_BASE + 0x64) ; offset register 2
ADC3_OFR3 EQU (ADC3_BASE + 0x68) ; offset register 3
ADC3_OFR4 EQU (ADC3_BASE + 0x6c) ; offset register 4
ADC3_JDR1 EQU (ADC3_BASE + 0x80) ; injected data register 1
ADC3_JDR2 EQU (ADC3_BASE + 0x84) ; injected data register 2
ADC3_JDR3 EQU (ADC3_BASE + 0x88) ; injected data register 3
ADC3_JDR4 EQU (ADC3_BASE + 0x8c) ; injected data register 4
ADC3_AWD2CR EQU (ADC3_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC3_AWD3CR EQU (ADC3_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC3_DIFSEL EQU (ADC3_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC3_CALFACT EQU (ADC3_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC4 --------------------------------------------------
; Desc: None
; ADC4 base address:
ADC4_BASE EQU 0x50000500
; ADC4 registers:
ADC4_ISR EQU (ADC4_BASE + 0x0) ; interrupt and status register
ADC4_IER EQU (ADC4_BASE + 0x4) ; interrupt enable register
ADC4_CR EQU (ADC4_BASE + 0x8) ; control register
ADC4_CFGR EQU (ADC4_BASE + 0xc) ; configuration register
ADC4_SMPR1 EQU (ADC4_BASE + 0x14) ; sample time register 1
ADC4_SMPR2 EQU (ADC4_BASE + 0x18) ; sample time register 2
ADC4_TR1 EQU (ADC4_BASE + 0x20) ; watchdog threshold register 1
ADC4_TR2 EQU (ADC4_BASE + 0x24) ; watchdog threshold register
ADC4_TR3 EQU (ADC4_BASE + 0x28) ; watchdog threshold register 3
ADC4_SQR1 EQU (ADC4_BASE + 0x30) ; regular sequence register 1
ADC4_SQR2 EQU (ADC4_BASE + 0x34) ; regular sequence register 2
ADC4_SQR3 EQU (ADC4_BASE + 0x38) ; regular sequence register 3
ADC4_SQR4 EQU (ADC4_BASE + 0x3c) ; regular sequence register 4
ADC4_DR EQU (ADC4_BASE + 0x40) ; regular Data Register
ADC4_JSQR EQU (ADC4_BASE + 0x4c) ; injected sequence register
ADC4_OFR1 EQU (ADC4_BASE + 0x60) ; offset register 1
ADC4_OFR2 EQU (ADC4_BASE + 0x64) ; offset register 2
ADC4_OFR3 EQU (ADC4_BASE + 0x68) ; offset register 3
ADC4_OFR4 EQU (ADC4_BASE + 0x6c) ; offset register 4
ADC4_JDR1 EQU (ADC4_BASE + 0x80) ; injected data register 1
ADC4_JDR2 EQU (ADC4_BASE + 0x84) ; injected data register 2
ADC4_JDR3 EQU (ADC4_BASE + 0x88) ; injected data register 3
ADC4_JDR4 EQU (ADC4_BASE + 0x8c) ; injected data register 4
ADC4_AWD2CR EQU (ADC4_BASE + 0xa0) ; Analog Watchdog 2 Configuration Register
ADC4_AWD3CR EQU (ADC4_BASE + 0xa4) ; Analog Watchdog 3 Configuration Register
ADC4_DIFSEL EQU (ADC4_BASE + 0xb0) ; Differential Mode Selection Register 2
ADC4_CALFACT EQU (ADC4_BASE + 0xb4) ; Calibration Factors
; Fields the same as in the first instance.
; ---- ADC12 -------------------------------------------------
; Desc: Analog-to-Digital Converter
; ADC12 base address:
ADC12_BASE EQU 0x50000300
; ADC12 registers:
ADC12_CSR EQU (ADC12_BASE + 0x0) ; ADC Common status register
ADC12_CCR EQU (ADC12_BASE + 0x8) ; ADC common control register
ADC12_CDR EQU (ADC12_BASE + 0xc) ; ADC common regular data register for dual and triple modes
; ADC12_CSR fields:
ADCC_CSR_ADDRDY_MST EQU 0x00000001 ; ADDRDY_MST
ADCC_CSR_ADDRDY_MST_ofs EQU 0
ADCC_CSR_ADDRDY_MST_len EQU 1
ADCC_CSR_EOSMP_MST EQU 0x00000002 ; EOSMP_MST
ADCC_CSR_EOSMP_MST_ofs EQU 1
ADCC_CSR_EOSMP_MST_len EQU 1
ADCC_CSR_EOC_MST EQU 0x00000004 ; EOC_MST
ADCC_CSR_EOC_MST_ofs EQU 2
ADCC_CSR_EOC_MST_len EQU 1
ADCC_CSR_EOS_MST EQU 0x00000008 ; EOS_MST
ADCC_CSR_EOS_MST_ofs EQU 3
ADCC_CSR_EOS_MST_len EQU 1
ADCC_CSR_OVR_MST EQU 0x00000010 ; OVR_MST
ADCC_CSR_OVR_MST_ofs EQU 4
ADCC_CSR_OVR_MST_len EQU 1
ADCC_CSR_JEOC_MST EQU 0x00000020 ; JEOC_MST
ADCC_CSR_JEOC_MST_ofs EQU 5
ADCC_CSR_JEOC_MST_len EQU 1
ADCC_CSR_JEOS_MST EQU 0x00000040 ; JEOS_MST
ADCC_CSR_JEOS_MST_ofs EQU 6
ADCC_CSR_JEOS_MST_len EQU 1
ADCC_CSR_AWD1_MST EQU 0x00000080 ; AWD1_MST
ADCC_CSR_AWD1_MST_ofs EQU 7
ADCC_CSR_AWD1_MST_len EQU 1
ADCC_CSR_AWD2_MST EQU 0x00000100 ; AWD2_MST
ADCC_CSR_AWD2_MST_ofs EQU 8
ADCC_CSR_AWD2_MST_len EQU 1
ADCC_CSR_AWD3_MST EQU 0x00000200 ; AWD3_MST
ADCC_CSR_AWD3_MST_ofs EQU 9
ADCC_CSR_AWD3_MST_len EQU 1
ADCC_CSR_JQOVF_MST EQU 0x00000400 ; JQOVF_MST
ADCC_CSR_JQOVF_MST_ofs EQU 10
ADCC_CSR_JQOVF_MST_len EQU 1
ADCC_CSR_ADRDY_SLV EQU 0x00010000 ; ADRDY_SLV
ADCC_CSR_ADRDY_SLV_ofs EQU 16
ADCC_CSR_ADRDY_SLV_len EQU 1
ADCC_CSR_EOSMP_SLV EQU 0x00020000 ; EOSMP_SLV
ADCC_CSR_EOSMP_SLV_ofs EQU 17
ADCC_CSR_EOSMP_SLV_len EQU 1
ADCC_CSR_EOC_SLV EQU 0x00040000 ; End of regular conversion of the slave ADC
ADCC_CSR_EOC_SLV_ofs EQU 18
ADCC_CSR_EOC_SLV_len EQU 1
ADCC_CSR_EOS_SLV EQU 0x00080000 ; End of regular sequence flag of the slave ADC
ADCC_CSR_EOS_SLV_ofs EQU 19
ADCC_CSR_EOS_SLV_len EQU 1
ADCC_CSR_OVR_SLV EQU 0x00100000 ; Overrun flag of the slave ADC
ADCC_CSR_OVR_SLV_ofs EQU 20
ADCC_CSR_OVR_SLV_len EQU 1
ADCC_CSR_JEOC_SLV EQU 0x00200000 ; End of injected conversion flag of the slave ADC
ADCC_CSR_JEOC_SLV_ofs EQU 21
ADCC_CSR_JEOC_SLV_len EQU 1
ADCC_CSR_JEOS_SLV EQU 0x00400000 ; End of injected sequence flag of the slave ADC
ADCC_CSR_JEOS_SLV_ofs EQU 22
ADCC_CSR_JEOS_SLV_len EQU 1
ADCC_CSR_AWD1_SLV EQU 0x00800000 ; Analog watchdog 1 flag of the slave ADC
ADCC_CSR_AWD1_SLV_ofs EQU 23
ADCC_CSR_AWD1_SLV_len EQU 1
ADCC_CSR_AWD2_SLV EQU 0x01000000 ; Analog watchdog 2 flag of the slave ADC
ADCC_CSR_AWD2_SLV_ofs EQU 24
ADCC_CSR_AWD2_SLV_len EQU 1
ADCC_CSR_AWD3_SLV EQU 0x02000000 ; Analog watchdog 3 flag of the slave ADC
ADCC_CSR_AWD3_SLV_ofs EQU 25
ADCC_CSR_AWD3_SLV_len EQU 1
ADCC_CSR_JQOVF_SLV EQU 0x04000000 ; Injected Context Queue Overflow flag of the slave ADC
ADCC_CSR_JQOVF_SLV_ofs EQU 26
ADCC_CSR_JQOVF_SLV_len EQU 1
; ADC12_CCR fields:
ADCC_CCR_MULT EQU 0x0000001f ; Multi ADC mode selection
ADCC_CCR_MULT_ofs EQU 0
ADCC_CCR_MULT_len EQU 5
ADCC_CCR_DELAY EQU 0x00000f00 ; Delay between 2 sampling phases
ADCC_CCR_DELAY_ofs EQU 8
ADCC_CCR_DELAY_len EQU 4
ADCC_CCR_DMACFG EQU 0x00002000 ; DMA configuration (for multi-ADC mode)
ADCC_CCR_DMACFG_ofs EQU 13
ADCC_CCR_DMACFG_len EQU 1
ADCC_CCR_MDMA EQU 0x0000c000 ; Direct memory access mode for multi ADC mode
ADCC_CCR_MDMA_ofs EQU 14
ADCC_CCR_MDMA_len EQU 2
ADCC_CCR_CKMODE EQU 0x00030000 ; ADC clock mode
ADCC_CCR_CKMODE_ofs EQU 16
ADCC_CCR_CKMODE_len EQU 2
ADCC_CCR_VREFEN EQU 0x00400000 ; VREFINT enable
ADCC_CCR_VREFEN_ofs EQU 22
ADCC_CCR_VREFEN_len EQU 1
ADCC_CCR_TSEN EQU 0x00800000 ; Temperature sensor enable
ADCC_CCR_TSEN_ofs EQU 23
ADCC_CCR_TSEN_len EQU 1
ADCC_CCR_VBATEN EQU 0x01000000 ; VBAT enable
ADCC_CCR_VBATEN_ofs EQU 24
ADCC_CCR_VBATEN_len EQU 1
; ADC12_CDR fields:
ADCC_CDR_RDATA_SLV EQU 0xffff0000 ; Regular data of the slave ADC
ADCC_CDR_RDATA_SLV_ofs EQU 16
ADCC_CDR_RDATA_SLV_len EQU 16
ADCC_CDR_RDATA_MST EQU 0x0000ffff ; Regular data of the master ADC
ADCC_CDR_RDATA_MST_ofs EQU 0
ADCC_CDR_RDATA_MST_len EQU 16
; ---- ADC34 -------------------------------------------------
; Desc: None
; ADC34 base address:
ADC34_BASE EQU 0x50000700
; ADC34 registers:
ADC34_CSR EQU (ADC34_BASE + 0x0) ; ADC Common status register
ADC34_CCR EQU (ADC34_BASE + 0x8) ; ADC common control register
ADC34_CDR EQU (ADC34_BASE + 0xc) ; ADC common regular data register for dual and triple modes
; Fields the same as in the first instance.
; ---- SYSCFG ------------------------------------------------
; Desc: System configuration controller
; SYSCFG base address:
SYSCFG_BASE EQU 0x40010000
; SYSCFG registers:
SYSCFG_CFGR1 EQU (SYSCFG_BASE + 0x0) ; configuration register 1
SYSCFG_EXTICR1 EQU (SYSCFG_BASE + 0x8) ; external interrupt configuration register 1
SYSCFG_EXTICR2 EQU (SYSCFG_BASE + 0xc) ; external interrupt configuration register 2
SYSCFG_EXTICR3 EQU (SYSCFG_BASE + 0x10) ; external interrupt configuration register 3
SYSCFG_EXTICR4 EQU (SYSCFG_BASE + 0x14) ; external interrupt configuration register 4
SYSCFG_CFGR2 EQU (SYSCFG_BASE + 0x18) ; configuration register 2
SYSCFG_RCR EQU (SYSCFG_BASE + 0x4) ; CCM SRAM protection register
; SYSCFG_CFGR1 fields:
SYSCFG_CFGR1_MEM_MODE EQU 0x00000003 ; Memory mapping selection bits
SYSCFG_CFGR1_MEM_MODE_ofs EQU 0
SYSCFG_CFGR1_MEM_MODE_len EQU 2
SYSCFG_CFGR1_USB_IT_RMP EQU 0x00000020 ; USB interrupt remap
SYSCFG_CFGR1_USB_IT_RMP_ofs EQU 5
SYSCFG_CFGR1_USB_IT_RMP_len EQU 1
SYSCFG_CFGR1_TIM1_ITR_RMP EQU 0x00000040 ; Timer 1 ITR3 selection
SYSCFG_CFGR1_TIM1_ITR_RMP_ofs EQU 6
SYSCFG_CFGR1_TIM1_ITR_RMP_len EQU 1
SYSCFG_CFGR1_DAC_TRIG_RMP EQU 0x00000080 ; DAC trigger remap (when TSEL = 001)
SYSCFG_CFGR1_DAC_TRIG_RMP_ofs EQU 7
SYSCFG_CFGR1_DAC_TRIG_RMP_len EQU 1
SYSCFG_CFGR1_ADC24_DMA_RMP EQU 0x00000100 ; ADC24 DMA remapping bit
SYSCFG_CFGR1_ADC24_DMA_RMP_ofs EQU 8
SYSCFG_CFGR1_ADC24_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM16_DMA_RMP EQU 0x00000800 ; TIM16 DMA request remapping bit
SYSCFG_CFGR1_TIM16_DMA_RMP_ofs EQU 11
SYSCFG_CFGR1_TIM16_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM17_DMA_RMP EQU 0x00001000 ; TIM17 DMA request remapping bit
SYSCFG_CFGR1_TIM17_DMA_RMP_ofs EQU 12
SYSCFG_CFGR1_TIM17_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP EQU 0x00002000 ; TIM6 and DAC1 DMA request remapping bit
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP_ofs EQU 13
SYSCFG_CFGR1_TIM6_DAC1_DMA_RMP_len EQU 1
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP EQU 0x00004000 ; TIM7 and DAC2 DMA request remapping bit
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP_ofs EQU 14
SYSCFG_CFGR1_TIM7_DAC2_DMA_RMP_len EQU 1
SYSCFG_CFGR1_I2C_PB6_FM EQU 0x00010000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB6_FM_ofs EQU 16
SYSCFG_CFGR1_I2C_PB6_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB7_FM EQU 0x00020000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB7_FM_ofs EQU 17
SYSCFG_CFGR1_I2C_PB7_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB8_FM EQU 0x00040000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB8_FM_ofs EQU 18
SYSCFG_CFGR1_I2C_PB8_FM_len EQU 1
SYSCFG_CFGR1_I2C_PB9_FM EQU 0x00080000 ; Fast Mode Plus (FM+) driving capability activation bits.
SYSCFG_CFGR1_I2C_PB9_FM_ofs EQU 19
SYSCFG_CFGR1_I2C_PB9_FM_len EQU 1
SYSCFG_CFGR1_I2C1_FM EQU 0x00100000 ; I2C1 Fast Mode Plus
SYSCFG_CFGR1_I2C1_FM_ofs EQU 20
SYSCFG_CFGR1_I2C1_FM_len EQU 1
SYSCFG_CFGR1_I2C2_FM EQU 0x00200000 ; I2C2 Fast Mode Plus
SYSCFG_CFGR1_I2C2_FM_ofs EQU 21
SYSCFG_CFGR1_I2C2_FM_len EQU 1
SYSCFG_CFGR1_ENCODER_MODE EQU 0x00c00000 ; Encoder mode
SYSCFG_CFGR1_ENCODER_MODE_ofs EQU 22
SYSCFG_CFGR1_ENCODER_MODE_len EQU 2
SYSCFG_CFGR1_FPU_IT EQU 0xfc000000 ; Interrupt enable bits from FPU
SYSCFG_CFGR1_FPU_IT_ofs EQU 26
SYSCFG_CFGR1_FPU_IT_len EQU 6
; SYSCFG_EXTICR1 fields:
SYSCFG_EXTICR1_EXTI3 EQU 0x0000f000 ; EXTI 3 configuration bits
SYSCFG_EXTICR1_EXTI3_ofs EQU 12
SYSCFG_EXTICR1_EXTI3_len EQU 4
SYSCFG_EXTICR1_EXTI2 EQU 0x00000f00 ; EXTI 2 configuration bits
SYSCFG_EXTICR1_EXTI2_ofs EQU 8
SYSCFG_EXTICR1_EXTI2_len EQU 4
SYSCFG_EXTICR1_EXTI1 EQU 0x000000f0 ; EXTI 1 configuration bits
SYSCFG_EXTICR1_EXTI1_ofs EQU 4
SYSCFG_EXTICR1_EXTI1_len EQU 4
SYSCFG_EXTICR1_EXTI0 EQU 0x0000000f ; EXTI 0 configuration bits
SYSCFG_EXTICR1_EXTI0_ofs EQU 0
SYSCFG_EXTICR1_EXTI0_len EQU 4
; SYSCFG_EXTICR2 fields:
SYSCFG_EXTICR2_EXTI7 EQU 0x0000f000 ; EXTI 7 configuration bits
SYSCFG_EXTICR2_EXTI7_ofs EQU 12
SYSCFG_EXTICR2_EXTI7_len EQU 4
SYSCFG_EXTICR2_EXTI6 EQU 0x00000f00 ; EXTI 6 configuration bits
SYSCFG_EXTICR2_EXTI6_ofs EQU 8
SYSCFG_EXTICR2_EXTI6_len EQU 4
SYSCFG_EXTICR2_EXTI5 EQU 0x000000f0 ; EXTI 5 configuration bits
SYSCFG_EXTICR2_EXTI5_ofs EQU 4
SYSCFG_EXTICR2_EXTI5_len EQU 4
SYSCFG_EXTICR2_EXTI4 EQU 0x0000000f ; EXTI 4 configuration bits
SYSCFG_EXTICR2_EXTI4_ofs EQU 0
SYSCFG_EXTICR2_EXTI4_len EQU 4
; SYSCFG_EXTICR3 fields:
SYSCFG_EXTICR3_EXTI11 EQU 0x0000f000 ; EXTI 11 configuration bits
SYSCFG_EXTICR3_EXTI11_ofs EQU 12
SYSCFG_EXTICR3_EXTI11_len EQU 4
SYSCFG_EXTICR3_EXTI10 EQU 0x00000f00 ; EXTI 10 configuration bits
SYSCFG_EXTICR3_EXTI10_ofs EQU 8
SYSCFG_EXTICR3_EXTI10_len EQU 4
SYSCFG_EXTICR3_EXTI9 EQU 0x000000f0 ; EXTI 9 configuration bits
SYSCFG_EXTICR3_EXTI9_ofs EQU 4
SYSCFG_EXTICR3_EXTI9_len EQU 4
SYSCFG_EXTICR3_EXTI8 EQU 0x0000000f ; EXTI 8 configuration bits
SYSCFG_EXTICR3_EXTI8_ofs EQU 0
SYSCFG_EXTICR3_EXTI8_len EQU 4
; SYSCFG_EXTICR4 fields:
SYSCFG_EXTICR4_EXTI15 EQU 0x0000f000 ; EXTI 15 configuration bits
SYSCFG_EXTICR4_EXTI15_ofs EQU 12
SYSCFG_EXTICR4_EXTI15_len EQU 4
SYSCFG_EXTICR4_EXTI14 EQU 0x00000f00 ; EXTI 14 configuration bits
SYSCFG_EXTICR4_EXTI14_ofs EQU 8
SYSCFG_EXTICR4_EXTI14_len EQU 4
SYSCFG_EXTICR4_EXTI13 EQU 0x000000f0 ; EXTI 13 configuration bits
SYSCFG_EXTICR4_EXTI13_ofs EQU 4
SYSCFG_EXTICR4_EXTI13_len EQU 4
SYSCFG_EXTICR4_EXTI12 EQU 0x0000000f ; EXTI 12 configuration bits
SYSCFG_EXTICR4_EXTI12_ofs EQU 0
SYSCFG_EXTICR4_EXTI12_len EQU 4
; SYSCFG_CFGR2 fields:
SYSCFG_CFGR2_LOCUP_LOCK EQU 0x00000001 ; Cortex-M0 LOCKUP bit enable bit
SYSCFG_CFGR2_LOCUP_LOCK_ofs EQU 0
SYSCFG_CFGR2_LOCUP_LOCK_len EQU 1
SYSCFG_CFGR2_SRAM_PARITY_LOCK EQU 0x00000002 ; SRAM parity lock bit
SYSCFG_CFGR2_SRAM_PARITY_LOCK_ofs EQU 1
SYSCFG_CFGR2_SRAM_PARITY_LOCK_len EQU 1
SYSCFG_CFGR2_PVD_LOCK EQU 0x00000004 ; PVD lock enable bit
SYSCFG_CFGR2_PVD_LOCK_ofs EQU 2
SYSCFG_CFGR2_PVD_LOCK_len EQU 1
SYSCFG_CFGR2_BYP_ADD_PAR EQU 0x00000010 ; Bypass address bit 29 in parity calculation
SYSCFG_CFGR2_BYP_ADD_PAR_ofs EQU 4
SYSCFG_CFGR2_BYP_ADD_PAR_len EQU 1
SYSCFG_CFGR2_SRAM_PEF EQU 0x00000100 ; SRAM parity flag
SYSCFG_CFGR2_SRAM_PEF_ofs EQU 8
SYSCFG_CFGR2_SRAM_PEF_len EQU 1
; SYSCFG_RCR fields:
SYSCFG_RCR_PAGE0_WP EQU 0x00000001 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE0_WP_ofs EQU 0
SYSCFG_RCR_PAGE0_WP_len EQU 1
SYSCFG_RCR_PAGE1_WP EQU 0x00000002 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE1_WP_ofs EQU 1
SYSCFG_RCR_PAGE1_WP_len EQU 1
SYSCFG_RCR_PAGE2_WP EQU 0x00000004 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE2_WP_ofs EQU 2
SYSCFG_RCR_PAGE2_WP_len EQU 1
SYSCFG_RCR_PAGE3_WP EQU 0x00000008 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE3_WP_ofs EQU 3
SYSCFG_RCR_PAGE3_WP_len EQU 1
SYSCFG_RCR_PAGE4_WP EQU 0x00000010 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE4_WP_ofs EQU 4
SYSCFG_RCR_PAGE4_WP_len EQU 1
SYSCFG_RCR_PAGE5_WP EQU 0x00000020 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE5_WP_ofs EQU 5
SYSCFG_RCR_PAGE5_WP_len EQU 1
SYSCFG_RCR_PAGE6_WP EQU 0x00000040 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE6_WP_ofs EQU 6
SYSCFG_RCR_PAGE6_WP_len EQU 1
SYSCFG_RCR_PAGE7_WP EQU 0x00000080 ; CCM SRAM page write protection bit
SYSCFG_RCR_PAGE7_WP_ofs EQU 7
SYSCFG_RCR_PAGE7_WP_len EQU 1
; ---- OPAMP -------------------------------------------------
; Desc: Operational amplifier
; OPAMP base address:
OPAMP_BASE EQU 0x40010038
; OPAMP registers:
OPAMP1_CR EQU (OPAMP_BASE + 0x0) ; OPAMP1 control register
OPAMP2_CR EQU (OPAMP_BASE + 0x4) ; OPAMP2 control register
OPAMP3_CR EQU (OPAMP_BASE + 0x8) ; OPAMP3 control register
OPAMP4_CR EQU (OPAMP_BASE + 0xc) ; OPAMP4 control register
; OPAMP_OPAMP1_CR fields:
OPAMPx_CR_EN EQU 0x00000001 ; OPAMPx enable
OPAMPx_CR_EN_ofs EQU 0
OPAMPx_CR_EN_len EQU 1
OPAMPx_CR_FORCE_VP EQU 0x00000002 ; FORCE_VP
OPAMPx_CR_FORCE_VP_ofs EQU 1
OPAMPx_CR_FORCE_VP_len EQU 1
OPAMPx_CR_VP_SEL EQU 0x0000000c ; OPAMPx Non inverting input selection
OPAMPx_CR_VP_SEL_ofs EQU 2
OPAMPx_CR_VP_SEL_len EQU 2
OPAMPx_CR_VM_SEL EQU 0x00000060 ; OPAMPx inverting input selection
OPAMPx_CR_VM_SEL_ofs EQU 5
OPAMPx_CR_VM_SEL_len EQU 2
OPAMPx_CR_TCM_EN EQU 0x00000080 ; Timer controlled Mux mode enable
OPAMPx_CR_TCM_EN_ofs EQU 7
OPAMPx_CR_TCM_EN_len EQU 1
OPAMPx_CR_VMS_SEL EQU 0x00000100 ; OPAMPx inverting input secondary selection
OPAMPx_CR_VMS_SEL_ofs EQU 8
OPAMPx_CR_VMS_SEL_len EQU 1
OPAMPx_CR_VPS_SEL EQU 0x00000600 ; OPAMPx Non inverting input secondary selection
OPAMPx_CR_VPS_SEL_ofs EQU 9
OPAMPx_CR_VPS_SEL_len EQU 2
OPAMPx_CR_CALON EQU 0x00000800 ; Calibration mode enable
OPAMPx_CR_CALON_ofs EQU 11
OPAMPx_CR_CALON_len EQU 1
OPAMPx_CR_CALSEL EQU 0x00003000 ; Calibration selection
OPAMPx_CR_CALSEL_ofs EQU 12
OPAMPx_CR_CALSEL_len EQU 2
OPAMPx_CR_PGA_GAIN EQU 0x0003c000 ; Gain in PGA mode
OPAMPx_CR_PGA_GAIN_ofs EQU 14
OPAMPx_CR_PGA_GAIN_len EQU 4
OPAMPx_CR_USER_TRIM EQU 0x00040000 ; User trimming enable
OPAMPx_CR_USER_TRIM_ofs EQU 18
OPAMPx_CR_USER_TRIM_len EQU 1
OPAMPx_CR_TRIMOFFSETP EQU 0x00f80000 ; Offset trimming value (PMOS)
OPAMPx_CR_TRIMOFFSETP_ofs EQU 19
OPAMPx_CR_TRIMOFFSETP_len EQU 5
OPAMPx_CR_TRIMOFFSETN EQU 0x1f000000 ; Offset trimming value (NMOS)
OPAMPx_CR_TRIMOFFSETN_ofs EQU 24
OPAMPx_CR_TRIMOFFSETN_len EQU 5
OPAMPx_CR_TSTREF EQU 0x20000000 ; TSTREF
OPAMPx_CR_TSTREF_ofs EQU 29
OPAMPx_CR_TSTREF_len EQU 1
OPAMPx_CR_OUTCAL EQU 0x40000000 ; OPAMPx ouput status flag
OPAMPx_CR_OUTCAL_ofs EQU 30
OPAMPx_CR_OUTCAL_len EQU 1
OPAMPx_CR_LOCK EQU 0x80000000 ; OPAMPx lock
OPAMPx_CR_LOCK_ofs EQU 31
OPAMPx_CR_LOCK_len EQU 1
END
| MightyPork/stm32-asm-examples | registers/sfr_f30x.asm | Assembly | mit | 495,370 |
SECTION "Startham map", ROMX
StarthamMap::
db 0 ; Exterior map
db MUSIC_OVERWORLD ; Music ID
db 0 ; Tileset is fixed
db TILESET_OVERWORLD ; Tileset
dw NO_SCRIPT ; Script (none)
map_size 29, 18 ; Width, height
dw NO_SCRIPT ; Loading script (none)
StarthamInteractions::
db 13
db WALK_LOADZONE
load_zone $0048, $0000, 25, 21, THREAD2_LOADINGWALKLEFT, 0, MAP_STARTHAM_FOREST, SFX_NONE
db WALK_INTERACT
interaction $FFF8, $013E, 16, 5, StarthamUnfinishedNorthConnection
db WALK_INTERACT
interaction $0100, $013E, 16, 5, StarthamUnfinishedSouthConnection
db BTN_LOADZONE
load_zone $009F, $0052, 1, 12, THREAD2_OPENDOOR, 0, MAP_PLAYER_HOUSE, SFX_DOOR_OPEN
db BTN_LOADZONE
load_zone $004F, $0092, 1, 12, THREAD2_OPENDOOR, 0, MAP_TEST_HOUSE, SFX_DOOR_OPEN
db BTN_LOADZONE
load_zone $004F, $0042, 1, 12, THREAD2_OPENDOOR, 0, MAP_STARTHAM_HOUSE_2, SFX_DOOR_OPEN
db BTN_LOADZONE | FLAG_DEP
flag_dep FLAG_SET, FLAG_STARTHAM_LARGE_HOUSE_UNLOCKED
load_zone $005F, $00D2, 1, 12, THREAD2_OPENDOOR, 0, MAP_STARTHAM_LARGE_HOUSE, SFX_DOOR_OPEN
db BTN_INTERACT | FLAG_DEP
flag_dep FLAG_RESET, FLAG_STARTHAM_LARGE_HOUSE_UNLOCKED
interaction $005F, $00D2, 1, 12, StarthamLockedHouseText
db BTN_INTERACT
interaction $0090, $0130, 16, 16, StarthamSignText
db BTN_INTERACT
interaction $0060, $00E0, 16, 16, StarthamHouseForSaleSign
db BTN_INTERACT
interaction $0050, $0050, 16, 16, StarthamEmptySign
db BTN_INTERACT
interaction $00A0, $0040, 16, 16, StarthamDevEdTestScript
db WALK_INTERACT | FLAG_DEP
flag_dep FLAG_RESET, FLAG_STARTHAM_SIBLING_ENTERED
interaction $0098, $0050, 1, 1, StarthamMeetSiblingCutscene
StarthamNPCs::
db 3 ; Number of NPCs
dw NO_FLAG_DEP ; No flag dependency
npc $00B3, $00D8, 16, 16, 1, $01, DIR_DOWN, 1, 1, 1, 1, $F4, 1 ; Generic inhabitant
dw NO_FLAG_DEP
npc $0110, $01C0, 16, 16, 0, $01, DIR_DOWN, 1, 1, 1, 1, 0, 0 ; Parzival
flag_dep FLAG_RESET, FLAG_STARTHAM_SIBLING_ENTERED
npc $0098, $0060, 0, 0, 0, 2, DIR_UP, 2, 2, 2, 2, 0, 0 ; Sibling (cutscene-only)
db $02 ; Number of NPC scripts
dw StarthamNPCScripts
db 3 ; Number of NPC tile sets
full_ptr GenericBoyATiles
db 0
full_ptr KasumiTiles
StarthamPalettes::
dw GenericBoyAPalette
dw 0
dw 0
dw 0
dw 0
dw 0
dw 0
StarthamWarpToPoints::
db 5 ; Number of warp-to points
warp_to $0048, $0090, DIR_DOWN, NO_WALKING, 0, THREAD2_DISABLED, NO_SCRIPT ; Test house
warp_to $FFF8, $0140, DIR_DOWN, NO_WALKING, 0, THREAD2_DISABLED, NO_SCRIPT ; Old intro entry point
warp_to $0055, $001E, DIR_RIGHT, KEEP_WALKING, 0, THREAD2_AFTERLOADINGWALKRIGHT, NO_SCRIPT ; Startham forest
warp_to $0098, $0050, DIR_DOWN, NO_WALKING, 0, THREAD2_DISABLED, NO_SCRIPT ; Player house
warp_to $0048, $0040, DIR_DOWN, NO_WALKING, 0, THREAD2_DISABLED, NO_SCRIPT ; Startham house 2
StarthamBlocks::
INCBIN "maps/startham.blk"
StarthamNPCScripts::
dw StarthamNPC0Script
dw StarthamGenericBoyAScript
set_text_prefix StarthamParzival
StarthamNPC0Script::
print_name
print_line_id 0
wait_user
print_line_id 1
wait_user
print_line_id 2
print_line_id 3
wait_user
print_line_id 4
print_line_id 5
wait_user
clear_box
delay 60
print_line_id 6
delay 60
print_line_id 7
print_line_id 8
print_line_id 9
wait_user
clear_box
print_line_id 10
delay 60
print_line_id 11
print_line_id 12
wait_user
print_line_id 13
wait_user
done
set_text_prefix StarthamGenericBoyAScript
StarthamGenericBoyAScript::
disp_box
print_line_id 0
print_line_id 1
wait_user
print_line_id 2
print_line_id 3
print_line_id 4
wait_user
clear_box
print_line_id 5
print_line_id 6
wait_user
done
set_text_prefix StarthamLockedHouseText
StarthamLockedHouseText::
disp_box
print_line_id 0
print_line_id 1
wait_user
print_line_id 2
print_line_id 3
print_line_id 4
wait_user
clear_box
print_line_id 5
print_line_id 6
print_line_id 7
wait_user
done
set_text_prefix StarthamSign
StarthamSignText::
disp_box
print_line_id 0
wait_user
clear_box
print_line_id 1
print_line_id 2
print_line_id 3
wait_user
clear_box
print_line_id 4
delay 20
print_line_id 5
wait_user
done
set_text_prefix StarthamHouseForSaleSign
StarthamHouseForSaleSign::
disp_box
print_line_id 0
wait_user
print_line_id 1
print_line_id 2
wait_user
clear_box
print_line_id 3
delay 20
print_line_id 4
wait_user
clear_box
print_line_id 5
print_line_id 6
print_line_id 7
wait_user
done
set_text_prefix StarthamEmptySign
StarthamEmptySign::
disp_box
print_line_id 0
print_line_id 1
wait_user
print_line_id 2
wait_user
done
set_text_prefix StarthamMeetSiblingCutscene
StarthamMeetSiblingCutscene::
delay 20
turn_npc 2, DIR_LEFT
delay 10
print_name
print_line_id 0
delay 20
turn_player DIR_RIGHT
delay 40
print_line_id 1
print_line_id 2
wait_user
clear_box
print_line_id 3
print_line_id 4
print_line_id 5
wait_user
clear_box
print_line_id 6
print_line_id 7
wait_user
close_box
delay 20
turn_player DIR_UP
play_sfx SFX_DOOR_OPEN
text_lda_imm THREAD2_OPENDOOR ; Start door-opening animation
text_sta hThread2ID
text_lda_imm $FF
text_sta wCameramanID ; Freeze camera in place
delay 30
text_sta wYPos + 1
make_npc_walk 2, DIR_LEFT, 16, 1
delay 10
turn_npc 2, DIR_UP
delay 5
text_lda_imm $FF
text_sta wNPC3_ypos + 1
text_asmcall ProcessNPCs
delay 20
text_asmcall RedrawMap ; Make door close
delay 10
text_set_flag FLAG_LOAD_CUTSCENE_NPCS
load_map MAP_PLAYER_HOUSE, 0
text_reset_flag FLAG_LOAD_CUTSCENE_NPCS
; The cutscene continues, but in the house
delay 5
turn_player DIR_DOWN
delay 10
make_player_walk DIR_UP | ROTATE_45, 20, 1
turn_player DIR_RIGHT
delay 5
make_npc_walk 1, DIR_UP, 66, 1
turn_npc 1, DIR_RIGHT
delay 20
turn_npc 1, DIR_LEFT
delay 20
turn_npc 1, DIR_DOWN
delay 10
clear_box
print_name
print_line_id 8
print_line_id 9
make_player_walk DIR_UP, 20, 1
turn_player DIR_RIGHT
wait_user
print_line_id 10
print_line_id 11
print_line_id 12
wait_user
clear_box
turn_npc 1, DIR_LEFT
delay 10
print_line_id 13
print_line_id 14
wait_user
print_line_id 15
print_line_id 16
wait_user
clear_box
delay 60
print_line_id 17
delay 30
print_line_id 18
wait_user
print_line_id 19
print_line_id 20
wait_user
print_line_id 21
print_line_id 22
wait_user
close_box
delay 10
make_npc_walk 1, DIR_UP | ROTATE_45 | ROTATE_CW, 21, 1
make_npc_walk 1, DIR_RIGHT, 35, 1
turn_npc 1, DIR_UP
text_set_flag FLAG_SIBLING_WATCHING_TV
text_set_flag FLAG_STARTHAM_SIBLING_ENTERED
done
set_text_prefix StarthamUnfinishedMapText
StarthamUnfinishedNorthConnection::
disp_box
print_line_id 0
print_line_id 1
wait_user
print_line_id 2
print_line_id 3
wait_user
clear_box
print_line_id 4
print_line_id 5
wait_user
print_line_id 6
print_line_id 7
wait_user
clear_box
print_line_id 8
print_line_id 9
delay 30
print_line_id 10
wait_user
close_box
make_player_walk DIR_DOWN, 5, 1
done
set_text_prefix StarthamUnfinishedMapText
StarthamUnfinishedSouthConnection::
disp_box
print_line_id 0
print_line_id 1
wait_user
print_line_id 2
print_line_id 3
wait_user
clear_box
print_line_id 4
print_line_id 5
wait_user
print_line_id 6
print_line_id 7
wait_user
clear_box
print_line_id 8
print_line_id 9
delay 30
print_line_id 10
wait_user
close_box
make_player_walk DIR_UP, 5, 1
done
set_text_prefix DevEdTestScript
StarthamDevEdTestScript::
play_sfx SFX_PHONE_RINGING
wait_sfx
delay 30
disp_box
print_line_id 0
print_line_id 1
print_line_id 2
wait_user
clear_box
print_line_id 3
print_line_id 4
fake_choice YesNoChoice
clear_box
delay 30
text_lda_imm 2
text_sta hScreenShakeAmplitude
play_sfx SFX_BATTLE_THUD
start_animation 0, PlayerJumpingAnimation
play_animations $F8 | 0
text_lda_imm 0
text_sta hScreenShakeAmplitude
wait_sfx
delay 120
print_line_id 5
print_line_id 6
print_line_id 7
wait_user
wait_sfx
play_sfx SFX_PHONE_HANG_UP
print_line_id 8
delay 60
done
SECTION "Player jumping animation", ROMX
PlayerJumpingAnimation::
db 2
anim_copy_tiles ShadowTile, 1, $7F, 1
anim_set_tiles 0, 2, $7F, 0
anim_set_pos 0, 2, 60, 60
anim_set_attribs 0, 2, $08, $60
; sorry about the mess! - DevEd
.movePlayer
anim_move_player -3, 0
pause 1
anim_move_player -3, 0
pause 1
anim_move_player -2, 0
pause 1
anim_move_player -2, 0
pause 1
anim_move_player -1, 0
pause 1
anim_move_player -1, 0
pause 3
anim_move_player 1, 0
pause 1
anim_move_player 1, 0
pause 1
anim_move_player 2, 0
pause 1
anim_move_player 2, 0
pause 1
anim_move_player 3, 0
pause 1
anim_move_player 3, 0
done
| ISSOtm/Aevilia-GB | maps/startham.asm | Assembly | apache-2.0 | 9,089 |
.386P
if @Version gt 510
.model FLAT
else
_TEXT SEGMENT PARA USE32 PUBLIC 'CODE'
_TEXT ENDS
_DATA SEGMENT DWORD USE32 PUBLIC 'DATA'
_DATA ENDS
CONST SEGMENT DWORD USE32 PUBLIC 'CONST'
CONST ENDS
_BSS SEGMENT DWORD USE32 PUBLIC 'BSS'
_BSS ENDS
_TLS SEGMENT DWORD USE32 PUBLIC 'TLS'
_TLS ENDS
FLAT GROUP _DATA, CONST, _BSS
ASSUME CS: FLAT, DS: FLAT, SS: FLAT
endif
PUBLIC _main ;main
EXTRN _printf:NEAR ;printf
EXTRN _getchar:NEAR ;getchar
_TEXT SEGMENT
_nl$ = -4
_nw$ = -8
_EOF$ = -12
_state$ = -16
_c$ = -20
_OUT$ = -24
_nc$ = -28
_IN$ = -32
_main PROC NEAR ;main
push ebp
mov ebp, esp
sub esp, 32
push 1 ; 1
mov eax, DWORD PTR [esp]
mov DWORD PTR _IN$[ebp], eax
pop eax
push -1 ; -1
mov eax, DWORD PTR [esp]
mov DWORD PTR _EOF$[ebp], eax
pop eax
push 0 ; 0
mov eax, DWORD PTR [esp]
mov DWORD PTR _OUT$[ebp], eax
pop eax
push DWORD PTR _OUT$[ebp]
mov eax, DWORD PTR [esp]
mov DWORD PTR _state$[ebp], eax
pop eax
push 0 ; 0
mov eax, DWORD PTR [esp]
mov DWORD PTR _nc$[ebp], eax
mov eax, DWORD PTR [esp]
mov DWORD PTR _nw$[ebp], eax
mov eax, DWORD PTR [esp]
mov DWORD PTR _nl$[ebp], eax
pop eax
$2:
call _getchar
add esp, 0
push eax
mov eax, DWORD PTR [esp]
mov DWORD PTR _c$[ebp], eax
push DWORD PTR _EOF$[ebp]
pop eax
pop ebx
cmp eax, ebx
je $1
$0:
lea eax, DWORD PTR _nc$[ebp]
push eax
pop eax
inc dword ptr [eax]
push eax
pop eax
push DWORD PTR _c$[ebp]
push 10 ; 10
pop eax
pop ebx
cmp eax, ebx
jne $3
lea eax, DWORD PTR _nl$[ebp]
push eax
pop eax
inc dword ptr [eax]
push eax
pop eax
$3:
push DWORD PTR _c$[ebp]
push 32 ; 32
pop eax
pop ebx
cmp eax, ebx
je $4
push DWORD PTR _c$[ebp]
push 10 ; 10
pop eax
pop ebx
cmp eax, ebx
je $4
push DWORD PTR _c$[ebp]
push 9 ; 9
pop eax
pop ebx
cmp eax, ebx
jne $6
$4:
$5:
push DWORD PTR _OUT$[ebp]
mov eax, DWORD PTR [esp]
mov DWORD PTR _state$[ebp], eax
pop eax
jmp $8
$6:
push DWORD PTR _state$[ebp]
push DWORD PTR _OUT$[ebp]
pop eax
pop ebx
cmp eax, ebx
jne $7
push DWORD PTR _IN$[ebp]
mov eax, DWORD PTR [esp]
mov DWORD PTR _state$[ebp], eax
pop eax
lea eax, DWORD PTR _nw$[ebp]
push eax
pop eax
inc dword ptr [eax]
push eax
pop eax
$7:
$8:
jmp $2
$1:
push DWORD PTR _nc$[ebp]
push DWORD PTR _nw$[ebp]
push DWORD PTR _nl$[ebp]
push OFFSET FLAT:$SG0
call _printf
add esp, 16
$uscita:
mov esp, ebp
pop ebp
ret
_main ENDP ;main
_TEXT ENDS
_DATA SEGMENT
$SG0 DB '%d %d %d', 0AH, 00H
_DATA ENDS
END | eruffaldi/cmm | test/ker2.asm | Assembly | apache-2.0 | 6,026 |
%include 'head.inc'
EntryPoint:
push handler
push dword [fs:0]
mov [fs:0], esp
_
int 3
_
push 42
call [__imp__ExitProcess]
_c
handler:
push Msg
call [__imp__printf]
add esp, 1 * 4
_
push 0
call [__imp__ExitProcess]
_c
Msg db " * BREAKPOINT exception trigger int 3 (CD 03)", 0ah, 0
_d
ALIGN FILEALIGN, db 0 | angea/corkami | wip/Exceptions/trig_bpint_3.asm | Assembly | bsd-2-clause | 378 |
; Generated at 3/12/2016 8:37:32 PM
DebugStub_DebugBPs TIMES 256 dd 0
DebugStub_MaxBPId dd 0
DebugStub_Init:
Call DebugStub_Cls
Call DebugStub_DisplayWaitMsg
Call DebugStub_InitSerial
Call DebugStub_WaitForDbgHandshake
Call DebugStub_Cls
DebugStub_Init_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_Init_Exit
Ret
DebugStub_WaitForSignature:
Mov EBX, 0
DebugStub_WaitForSignature_Block1_Begin:
Cmp EBX, DebugStub_Const_Signature
JE DebugStub_WaitForSignature_Block1_End
Call DebugStub_ComReadAL
Mov BL, AL
ROR EBX, 8
jmp DebugStub_WaitForSignature_Block1_Begin
DebugStub_WaitForSignature_Block1_End:
DebugStub_WaitForSignature_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_WaitForSignature_Exit
Ret
DebugStub_WaitForDbgHandshake:
Mov AL, 0
Call DebugStub_ComWriteAL
Mov AL, 0
Call DebugStub_ComWriteAL
Mov AL, 0
Call DebugStub_ComWriteAL
Push dword DebugStub_Const_Signature
Mov ESI, ESP
Call DebugStub_ComWrite32
Pop EAX
Mov AL, DebugStub_Const_Ds2Vs_Started
Call DebugStub_ComWriteAL
Call DebugStub_WaitForSignature
Call DebugStub_ProcessCommandBatch
Call DebugStub_Hook_OnHandshakeCompleted
DebugStub_WaitForDbgHandshake_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_WaitForDbgHandshake_Exit
Ret
%ifndef Exclude_Dummy_Hooks
DebugStub_Hook_OnHandshakeCompleted:
DebugStub_Hook_OnHandshakeCompleted_Exit:
mov dword [static_field__Cosmos_Core_INTs_mLastKnownAddress], DebugStub_Hook_OnHandshakeCompleted_Exit
Ret
%endif
| Cyber4/Cosmos | source/Cosmos.Debug.DebugStub/Init.asm | Assembly | bsd-3-clause | 1,593 |
; Generated at 28-7-2015 17:33:40
DebugStub_Const_Signature equ 0x19740807
DebugStub_Const_Tracing_Off equ 0
DebugStub_Const_Tracing_On equ 1
DebugStub_Const_Status_Run equ 0
DebugStub_Const_Status_Break equ 1
DebugStub_Const_StepTrigger_None equ 0
DebugStub_Const_StepTrigger_Into equ 1
DebugStub_Const_StepTrigger_Over equ 2
DebugStub_Const_StepTrigger_Out equ 3
DebugStub_Const_Vs2Ds_Noop equ 0
DebugStub_Const_Vs2Ds_TraceOff equ 1
DebugStub_Const_Vs2Ds_TraceOn equ 2
DebugStub_Const_Vs2Ds_Break equ 3
DebugStub_Const_Vs2Ds_Continue equ 4
DebugStub_Const_Vs2Ds_BreakOnAddress equ 6
DebugStub_Const_Vs2Ds_BatchBegin equ 7
DebugStub_Const_Vs2Ds_BatchEnd equ 8
DebugStub_Const_Vs2Ds_StepInto equ 5
DebugStub_Const_Vs2Ds_StepOver equ 11
DebugStub_Const_Vs2Ds_StepOut equ 12
DebugStub_Const_Vs2Ds_SendMethodContext equ 9
DebugStub_Const_Vs2Ds_SendMemory equ 10
DebugStub_Const_Vs2Ds_SendRegisters equ 13
DebugStub_Const_Vs2Ds_SendFrame equ 14
DebugStub_Const_Vs2Ds_SendStack equ 15
DebugStub_Const_Vs2Ds_SetAsmBreak equ 16
DebugStub_Const_Vs2Ds_Ping equ 17
DebugStub_Const_Vs2Ds_AsmStepInto equ 18
DebugStub_Const_Vs2Ds_SetINT3 equ 19
DebugStub_Const_Vs2Ds_ClearINT3 equ 20
DebugStub_Const_Vs2Ds_Max equ 21
DebugStub_Const_Ds2Vs_Noop equ 0
DebugStub_Const_Ds2Vs_TracePoint equ 1
DebugStub_Const_Ds2Vs_Message equ 192
DebugStub_Const_Ds2Vs_BreakPoint equ 3
DebugStub_Const_Ds2Vs_Error equ 4
DebugStub_Const_Ds2Vs_Pointer equ 5
DebugStub_Const_Ds2Vs_Started equ 6
DebugStub_Const_Ds2Vs_MethodContext equ 7
DebugStub_Const_Ds2Vs_MemoryData equ 8
DebugStub_Const_Ds2Vs_CmdCompleted equ 9
DebugStub_Const_Ds2Vs_Registers equ 10
DebugStub_Const_Ds2Vs_Frame equ 11
DebugStub_Const_Ds2Vs_Stack equ 12
DebugStub_Const_Ds2Vs_Pong equ 13
DebugStub_Const_Ds2Vs_BreakPointAsm equ 14
DebugStub_Const_Ds2Vs_StackCorruptionOccurred equ 15
DebugStub_Const_Ds2Vs_MessageBox equ 16
DebugStub_Const_Ds2Vs_NullReferenceOccurred equ 17
DebugStub_Const_Ds2Vs_SimpleNumber equ 18
| MetSystem/Cosmos | source/Cosmos.Debug.DebugStub/Consts.asm | Assembly | bsd-3-clause | 2,023 |
; Copyright 2005-2014 Intel Corporation. All Rights Reserved.
;
; This file is part of Threading Building Blocks. Threading Building Blocks is free software;
; you can redistribute it and/or modify it under the terms of the GNU General Public License
; version 2 as published by the Free Software Foundation. Threading Building Blocks is
; distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
; implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
; See the GNU General Public License for more details. You should have received a copy of
; the GNU General Public License along with Threading Building Blocks; if not, write to the
; Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
;
; As a special exception, you may use this file as part of a free software library without
; restriction. Specifically, if other files instantiate templates or use macros or inline
; functions from this file, or you compile this file and link it with other files to produce
; an executable, this file does not by itself cause the resulting executable to be covered
; by the GNU General Public License. This exception does not however invalidate any other
; reasons why the executable file might be covered by the GNU General Public License.
.code
ALIGN 8
PUBLIC __TBB_get_cpu_ctl_env
__TBB_get_cpu_ctl_env:
stmxcsr [rcx]
fstcw [rcx+4]
ret
.code
ALIGN 8
PUBLIC __TBB_set_cpu_ctl_env
__TBB_set_cpu_ctl_env:
ldmxcsr [rcx]
fldcw [rcx+4]
ret
end
| rutgers-apl/TaskProf | tprof-tbb-lib/src/tbb/intel64-masm/intel64_misc.asm | Assembly | mit | 1,568 |
;
; MACROs for common tasks and repeating parts of code
;
;
;
;
; -----------------------------------------------------------------------------
; MACRO for writing a line. Use with ".invoke print <address>" where
; <address> is the first byte of the string in 16 bit. As a "write"
; command, the string has to be terminated by a zero-byte ('\0')
.macro print
lda #<_1
sta K_STRING_L
lda #>_1
sta K_STRING_H
jsr j_wstr
.macend
; -----------------------------------------------------------------------------
; MACRO for writing a linefeed. Use with ".invoke linefeed"
.macro linefeed
lda #LINE_END
jsr j_wchr
.macend
; -----------------------------------------------------------------------------
; MACRO for writing a space. Use with ".invoke space"
.macro space
lda #32
jsr j_wchr
.macend
| mkeller0815/MOUSE2Go | M-OS-6502/MIOS_macros.asm | Assembly | mit | 807 |
; Declare constants for the multiboot header.
MBALIGN equ 1<<0 ; align loaded modules on page boundaries
MEMINFO equ 1<<1 ; provide memory map
GFXINFO equ 1<<2
FLAGS equ MBALIGN | MEMINFO ; this is the Multiboot 'flag' field
MAGIC equ 0x1BADB002 ; 'magic number' lets bootloader find the header
CHECKSUM equ -(MAGIC + FLAGS) ; checksum of above, to prove we are multiboot
; Declare a multiboot header that marks the program as a kernel. These are magic
; values that are documented in the multiboot standard. The bootloader will
; search for this signature in the first 8 KiB of the kernel file, aligned at a
; 32-bit boundary. The signature is in its own section so the header can be
; forced to be within the first 8 KiB of the kernel file.
section .multiboot_header
align 4
dd MAGIC
dd FLAGS
dd CHECKSUM
dd 0
dd 0
dd 0
dd 0
dd 0 ; addr fields
dd 0 ; width
dd 0 ; height
dd 0 ; graphics mode
| LugosFingite/LudOS | kern/i686/pc/multiboot.asm | Assembly | mit | 1,032 |
; name: LABELS - Memory addresses
; code: "909090908B1E1600891E0100A10100C78701000200909090909090668B1D4800000066891D1800000066A118000000668B84811800000066898481180000006667C78718001900909090909090668B1C257900000066891C254A00000066C7814A0000004B0066678B8481180000006667898481180000009090"
[bits 16]
nop
tommilabel1:
nop
tommilabel2:
nop
nop
mov bx, [ tommilabel3 ]
mov word [ tommilabel1 ], bx
mov ax, [ tommilabel1 ]
mov word [ tommilabel1 + bx ], tommilabel2
nop
tommilabel3:
nop
[bits 32]
nop
tommilabel4:
nop
tommilabel5:
nop
nop
mov bx, [ tommilabel6 ]
mov word [ tommilabel4 ], bx
mov ax, [ tommilabel4 ]
mov ax, [ eax*4 + ecx + tommilabel4 ]
mov word [ eax*4 + ecx + tommilabel4 ], ax
mov word [ tommilabel4 + bx ], tommilabel5
nop
tommilabel6:
nop
[bits 64]
nop
tommilabel7:
nop
tommilabel8:
nop
nop
mov bx, [ tommilabel9 ]
mov word [ tommilabel7 ], bx
mov word [ tommilabel7 + rcx ], tommilabel8
mov ax, [ eax*4 + ecx + tommilabel4 ]
mov word [ eax*4 + ecx + tommilabel4 ], ax
nop
tommilabel9:
nop
| tpisto/pasm | tests/016_LABELS_-_Memory_addresses.asm | Assembly | mit | 1,023 |
;;----------------------------------------------------------------------------;;
;; Hacks for overlay 12 for arm9
;; Copyright 2014 Benito Palacios (aka pleonex)
;;
;; Licensed under the Apache License, Version 2.0 (the "License");
;; you may not use this file except in compliance with the License.
;; You may obtain a copy of the License at
;;
;; http://www.apache.org/licenses/LICENSE-2.0
;;
;; Unless required by applicable law or agreed to in writing, software
;; distributed under the License is distributed on an "AS IS" BASIS,
;; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;; See the License for the specific language governing permissions and
;; limitations under the License.
;;----------------------------------------------------------------------------;;
.nds
.open overlay9_12.bin, 0x02079F80
.relativeinclude on
.erroronwarning on
.include font\fillnumber_ov12.asm
.include textbox\moya.asm
.close
; EOF ;
| pleonex/Ninokuni | Assembly/overlay9_12.asm | Assembly | apache-2.0 | 968 |
//===========================================================================//
// GLOSS - Generic Loader for Operating System Software //
// An extensible and configurable bootloader. //
//---------------------------------------------------------------------------//
// Copyright (C) 2013-2016 ~ Adrian J. Collado <acollado@polaritech.com> //
// All Rights Reserved //
//===========================================================================//
// Seeing as how AT&T syntax is much more obscure and difficult to read (IMO)
// than Intel syntax, the assembly language code in this project for x86 based
// architectures will be using Intel syntax.
.intel_syntax noprefix
// This code will be executed in a 16 bit real mode environment.
.code16
// This code is located in the .TEXT (executable) section of the executable.
.section .text
// This function initializes the first serial port (COM1) at 9600 baud with no
// parity, one stop bit, and eight data bits.
.global I8086.IO.Serial.Init
I8086.IO.Serial.Init:
xor dx, dx
mov ax, 0x00e3
int 0x14
or word ptr [BSS.IO.Serial.Flags], 0x0001
ret
| SlickOS/SlickOS | Modules/Gloss/Arch/x86_64/Source/IO/Serial/Init.asm | Assembly | mit | 1,231 |
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