code stringlengths 2 1.05M | repo_name stringlengths 5 101 | path stringlengths 4 991 | language stringclasses 3 values | license stringclasses 5 values | size int64 2 1.05M |
|---|---|---|---|---|---|
; ToriX - TORres Interactive eXecution
; Copyright (c) 2008 Devin Torres
; Licensed under the MIT license.
[bits 32]
[global start]
%ifdef CYGWIN
[extern _main]
%else
[extern main]
%endif
[section .data]
; The Global Descriptor Table (GDT); this tells us where all the segments (now
; selectors) are:
gdt:
; Null descriptor:
dw 0 ; limit 15:0
dw 0 ; base 15:0
db 0 ; base 23:0
db 0 ; type
db 0 ; limit 19:16, flags
db 0 ; base 31: 24
; Unused descriptor:
dw 0
dw 0
db 0
db 0
db 0
db 0
; Data segment descriptor:
DATA_SELECTOR equ $-gdt ; The data selector; an index into the GDT.
dw 0xFFFF ; limit of 4GB
dw 0 ; base 0
db 0
db 0x92 ; present, ring 0, data, expand-up, writable
db 0xCF ; page-granular, 32-bit
db 0
; Code segment descriptor:
CODE_SELECTOR equ $-gdt ; The code selector; an index into the GDT.
dw 0xFFFF ; limit of 4GB
dw 0 ; base 0
db 0
db 0x9A ; present, ring 0, code, non-conforming, readable
db 0xCF ; page-granular, 32-bit
db 0
gdt_end:
; Pointer to the GDT:
gdtr:
dw gdt_end - gdt - 1 ; Size of the GDT
dd gdt ; Linear address of GDT base
[section .text]
start:
; Load the new GDT:
lgdt [gdtr]
; Call the kernel and let it take over:
%ifdef CYGWIN
call _main
%else
call main
%endif
; If the kernel wasn't loaded, freeze:
jmp $
| devinus/torix | src/kernel/start.asm | Assembly | mit | 1,309 |
dc.w word_4A08C-Map_PachinkoEnergyTrap
word_4A08C: dc.w 2 ; DATA XREF: ROM:0004A08Ao
dc.b $E8, 6, 0, 0, $FF, $F8
dc.b 0, 6, $10, 0, $FF, $F8
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/Levels/Pachinko/Misc Object Data/Map - Energy Trap.asm | Assembly | apache-2.0 | 161 |
%define ARCH_AARCH64 0
%define ARCH_ALPHA 0
%define ARCH_ARM 0
%define ARCH_AVR32 0
%define ARCH_AVR32_AP 0
%define ARCH_AVR32_UC 0
%define ARCH_BFIN 0
%define ARCH_IA64 0
%define ARCH_M68K 0
%define ARCH_MIPS 0
%define ARCH_MIPS64 0
%define ARCH_PARISC 0
%define ARCH_PPC 0
%define ARCH_PPC64 0
%define ARCH_S390 0
%define ARCH_SH4 0
%define ARCH_SPARC 0
%define ARCH_SPARC64 0
%define ARCH_TILEGX 0
%define ARCH_TILEPRO 0
%define ARCH_TOMI 0
%define ARCH_X86 1
%define ARCH_X86_32 1
%define ARCH_X86_64 0
%define HAVE_ARMV5TE 0
%define HAVE_ARMV6 0
%define HAVE_ARMV6T2 0
%define HAVE_NEON 0
%define HAVE_VFP 0
%define HAVE_VFPV3 0
%define HAVE_AMD3DNOW 1
%define HAVE_AMD3DNOWEXT 1
%define HAVE_AVX 1
%define HAVE_FMA4 1
%define HAVE_MMX 1
%define HAVE_MMXEXT 1
%define HAVE_SSE 1
%define HAVE_SSE2 1
%define HAVE_SSE3 1
%define HAVE_SSE4 1
%define HAVE_SSE42 1
%define HAVE_SSSE3 1
%define HAVE_ALTIVEC 0
%define HAVE_PPC4XX 0
%define HAVE_VIS 0
%define HAVE_MIPSFPU 0
%define HAVE_MIPS32R2 0
%define HAVE_MIPSDSPR1 0
%define HAVE_MIPSDSPR2 0
%define HAVE_ARMV5TE_EXTERNAL 0
%define HAVE_ARMV6_EXTERNAL 0
%define HAVE_ARMV6T2_EXTERNAL 0
%define HAVE_NEON_EXTERNAL 0
%define HAVE_VFP_EXTERNAL 0
%define HAVE_VFPV3_EXTERNAL 0
%define HAVE_AMD3DNOW_EXTERNAL 1
%define HAVE_AMD3DNOWEXT_EXTERNAL 1
%define HAVE_AVX_EXTERNAL 1
%define HAVE_FMA4_EXTERNAL 1
%define HAVE_MMX_EXTERNAL 1
%define HAVE_MMXEXT_EXTERNAL 1
%define HAVE_SSE_EXTERNAL 1
%define HAVE_SSE2_EXTERNAL 1
%define HAVE_SSE3_EXTERNAL 1
%define HAVE_SSE4_EXTERNAL 1
%define HAVE_SSE42_EXTERNAL 1
%define HAVE_SSSE3_EXTERNAL 1
%define HAVE_ALTIVEC_EXTERNAL 0
%define HAVE_PPC4XX_EXTERNAL 0
%define HAVE_VIS_EXTERNAL 0
%define HAVE_MIPSFPU_EXTERNAL 0
%define HAVE_MIPS32R2_EXTERNAL 0
%define HAVE_MIPSDSPR1_EXTERNAL 0
%define HAVE_MIPSDSPR2_EXTERNAL 0
%define HAVE_ARMV5TE_INLINE 0
%define HAVE_ARMV6_INLINE 0
%define HAVE_ARMV6T2_INLINE 0
%define HAVE_NEON_INLINE 0
%define HAVE_VFP_INLINE 0
%define HAVE_VFPV3_INLINE 0
%define HAVE_AMD3DNOW_INLINE 1
%define HAVE_AMD3DNOWEXT_INLINE 1
%define HAVE_AVX_INLINE 1
%define HAVE_FMA4_INLINE 1
%define HAVE_MMX_INLINE 1
%define HAVE_MMXEXT_INLINE 1
%define HAVE_SSE_INLINE 1
%define HAVE_SSE2_INLINE 1
%define HAVE_SSE3_INLINE 1
%define HAVE_SSE4_INLINE 1
%define HAVE_SSE42_INLINE 1
%define HAVE_SSSE3_INLINE 1
%define HAVE_ALTIVEC_INLINE 0
%define HAVE_PPC4XX_INLINE 0
%define HAVE_VIS_INLINE 0
%define HAVE_MIPSFPU_INLINE 0
%define HAVE_MIPS32R2_INLINE 0
%define HAVE_MIPSDSPR1_INLINE 0
%define HAVE_MIPSDSPR2_INLINE 0
%define HAVE_INLINE_ASM 1
%define HAVE_SYMVER 1
%define HAVE_YASM 1
%define HAVE_BIGENDIAN 0
%define HAVE_FAST_UNALIGNED 1
%define HAVE_INCOMPATIBLE_FORK_ABI 0
%define HAVE_PTHREADS 1
%define HAVE_W32THREADS 0
%define HAVE_OS2THREADS 0
%define HAVE_ATOMICS_GCC 1
%define HAVE_ATOMICS_SUNCC 0
%define HAVE_ATOMICS_WIN32 0
%define HAVE_ATANF 1
%define HAVE_ATAN2F 1
%define HAVE_CBRT 1
%define HAVE_CBRTF 1
%define HAVE_COSF 1
%define HAVE_EXP2 1
%define HAVE_EXP2F 1
%define HAVE_EXPF 1
%define HAVE_ISINF 1
%define HAVE_ISNAN 1
%define HAVE_LDEXPF 1
%define HAVE_LLRINT 1
%define HAVE_LLRINTF 1
%define HAVE_LOG2 1
%define HAVE_LOG2F 1
%define HAVE_LOG10F 1
%define HAVE_LRINT 1
%define HAVE_LRINTF 1
%define HAVE_POWF 1
%define HAVE_RINT 1
%define HAVE_ROUND 1
%define HAVE_ROUNDF 1
%define HAVE_SINF 1
%define HAVE_TRUNC 1
%define HAVE_TRUNCF 1
%define HAVE_ACCESS 1
%define HAVE_ALIGNED_MALLOC 0
%define HAVE_ALIGNED_STACK 1
%define HAVE_ALSA_ASOUNDLIB_H 0
%define HAVE_ALTIVEC_H 0
%define HAVE_ARPA_INET_H 0
%define HAVE_ASM_MOD_Q 0
%define HAVE_ASM_MOD_Y 0
%define HAVE_ASM_TYPES_H 1
%define HAVE_ATOMIC_CAS_PTR 0
%define HAVE_ATOMICS_NATIVE 1
%define HAVE_ATTRIBUTE_MAY_ALIAS 1
%define HAVE_ATTRIBUTE_PACKED 1
%define HAVE_CDIO_PARANOIA_H 0
%define HAVE_CDIO_PARANOIA_PARANOIA_H 0
%define HAVE_CLOCK_GETTIME 1
%define HAVE_CLOSESOCKET 0
%define HAVE_CMOV 0
%define HAVE_COMMANDLINETOARGVW 0
%define HAVE_CPUNOP 1
%define HAVE_CRYPTGENRANDOM 0
%define HAVE_DCBZL 0
%define HAVE_DEV_BKTR_IOCTL_BT848_H 0
%define HAVE_DEV_BKTR_IOCTL_METEOR_H 0
%define HAVE_DEV_IC_BT8XX_H 0
%define HAVE_DEV_VIDEO_BKTR_IOCTL_BT848_H 0
%define HAVE_DEV_VIDEO_METEOR_IOCTL_METEOR_H 0
%define HAVE_DIRECT_H 0
%define HAVE_DLFCN_H 1
%define HAVE_DLOPEN 1
%define HAVE_DOS_PATHS 0
%define HAVE_DXVA_H 0
%define HAVE_EBP_AVAILABLE 1
%define HAVE_EBX_AVAILABLE 0
%define HAVE_FAST_64BIT 0
%define HAVE_FAST_CLZ 1
%define HAVE_FAST_CMOV 0
%define HAVE_FCNTL 1
%define HAVE_FORK 1
%define HAVE_GETADDRINFO 0
%define HAVE_GETHRTIME 0
%define HAVE_GETOPT 1
%define HAVE_GETPROCESSAFFINITYMASK 0
%define HAVE_GETPROCESSMEMORYINFO 0
%define HAVE_GETPROCESSTIMES 0
%define HAVE_GETSYSTEMTIMEASFILETIME 0
%define HAVE_GETRUSAGE 1
%define HAVE_GETSERVBYPORT 0
%define HAVE_GETTIMEOFDAY 1
%define HAVE_GLOB 1
%define HAVE_GNU_AS 1
%define HAVE_GSM_H 0
%define HAVE_IBM_ASM 0
%define HAVE_INET_ATON 1
%define HAVE_IO_H 0
%define HAVE_ISATTY 1
%define HAVE_JACK_PORT_GET_LATENCY_RANGE 0
%define HAVE_KBHIT 0
%define HAVE_LDBRX 0
%define HAVE_LIBDC1394_1 0
%define HAVE_LIBDC1394_2 0
%define HAVE_LOCAL_ALIGNED_16 1
%define HAVE_LOCAL_ALIGNED_8 1
%define HAVE_LOCALTIME_R 1
%define HAVE_LOONGSON 0
%define HAVE_LZO1X_999_COMPRESS 0
%define HAVE_MACHINE_IOCTL_BT848_H 0
%define HAVE_MACHINE_IOCTL_METEOR_H 0
%define HAVE_MACHINE_RW_BARRIER 0
%define HAVE_MAKEINFO 0
%define HAVE_MALLOC_H 1
%define HAVE_MAPVIEWOFFILE 0
%define HAVE_MEMALIGN 1
%define HAVE_MEMORYBARRIER 0
%define HAVE_MKSTEMP 1
%define HAVE_MM_EMPTY 0
%define HAVE_MMAP 1
%define HAVE_MPROTECT 1
%define HAVE_MSVCRT 0
%define HAVE_NANOSLEEP 1
%define HAVE_OPENJPEG_1_5_OPENJPEG_H 0
%define HAVE_PEEKNAMEDPIPE 0
%define HAVE_PERL 1
%define HAVE_POD2MAN 1
%define HAVE_POLL_H 1
%define HAVE_POSIX_MEMALIGN 1
%define HAVE_PTHREAD_CANCEL 1
%define HAVE_RDTSC 0
%define HAVE_RSYNC_CONTIMEOUT 1
%define HAVE_SCHED_GETAFFINITY 1
%define HAVE_SDL 0
%define HAVE_SETCONSOLETEXTATTRIBUTE 0
%define HAVE_SETMODE 0
%define HAVE_SETRLIMIT 1
%define HAVE_SLEEP 0
%define HAVE_SNDIO_H 0
%define HAVE_SOCKLEN_T 0
%define HAVE_SOUNDCARD_H 0
%define HAVE_STRERROR_R 1
%define HAVE_STRUCT_ADDRINFO 0
%define HAVE_STRUCT_GROUP_SOURCE_REQ 0
%define HAVE_STRUCT_IP_MREQ_SOURCE 0
%define HAVE_STRUCT_IPV6_MREQ 0
%define HAVE_STRUCT_POLLFD 0
%define HAVE_STRUCT_RUSAGE_RU_MAXRSS 1
%define HAVE_STRUCT_SCTP_EVENT_SUBSCRIBE 0
%define HAVE_STRUCT_SOCKADDR_IN6 0
%define HAVE_STRUCT_SOCKADDR_SA_LEN 0
%define HAVE_STRUCT_SOCKADDR_STORAGE 0
%define HAVE_STRUCT_V4L2_FRMIVALENUM_DISCRETE 1
%define HAVE_SYMVER_ASM_LABEL 0
%define HAVE_SYMVER_GNU_ASM 1
%define HAVE_SYNC_VAL_COMPARE_AND_SWAP 1
%define HAVE_SYSCONF 1
%define HAVE_SYSCTL 1
%define HAVE_SYS_MMAN_H 1
%define HAVE_SYS_PARAM_H 1
%define HAVE_SYS_RESOURCE_H 1
%define HAVE_SYS_SELECT_H 1
%define HAVE_SYS_SOUNDCARD_H 1
%define HAVE_SYS_TIME_H 1
%define HAVE_SYS_VIDEOIO_H 0
%define HAVE_TERMIOS_H 1
%define HAVE_TEXI2HTML 0
%define HAVE_THREADS 1
%define HAVE_UNISTD_H 1
%define HAVE_USLEEP 1
%define HAVE_VFP_ARGS 0
%define HAVE_VIRTUALALLOC 0
%define HAVE_WINDOWS_H 0
%define HAVE_WINSOCK2_H 0
%define HAVE_XFORM_ASM 0
%define HAVE_XMM_CLOBBERS 0
%define CONFIG_BSFS 0
%define CONFIG_DECODERS 1
%define CONFIG_DEMUXERS 1
%define CONFIG_ENCODERS 0
%define CONFIG_FILTERS 0
%define CONFIG_HWACCELS 0
%define CONFIG_INDEVS 0
%define CONFIG_MUXERS 0
%define CONFIG_OUTDEVS 0
%define CONFIG_PARSERS 1
%define CONFIG_PROTOCOLS 0
%define CONFIG_DOC 0
%define CONFIG_HTMLPAGES 0
%define CONFIG_MANPAGES 1
%define CONFIG_PODPAGES 1
%define CONFIG_TXTPAGES 0
%define CONFIG_AVISYNTH 0
%define CONFIG_BZLIB 0
%define CONFIG_CRYSTALHD 0
%define CONFIG_FONTCONFIG 0
%define CONFIG_FREI0R 0
%define CONFIG_GNUTLS 0
%define CONFIG_ICONV 0
%define CONFIG_LIBAACPLUS 0
%define CONFIG_LIBASS 0
%define CONFIG_LIBBLURAY 0
%define CONFIG_LIBCACA 0
%define CONFIG_LIBCDIO 0
%define CONFIG_LIBCELT 0
%define CONFIG_LIBDC1394 0
%define CONFIG_LIBFAAC 0
%define CONFIG_LIBFDK_AAC 0
%define CONFIG_LIBFLITE 0
%define CONFIG_LIBFREETYPE 0
%define CONFIG_LIBGSM 0
%define CONFIG_LIBIEC61883 0
%define CONFIG_LIBILBC 0
%define CONFIG_LIBMODPLUG 0
%define CONFIG_LIBMP3LAME 0
%define CONFIG_LIBNUT 0
%define CONFIG_LIBOPENCORE_AMRNB 0
%define CONFIG_LIBOPENCORE_AMRWB 0
%define CONFIG_LIBOPENCV 0
%define CONFIG_LIBOPENJPEG 0
%define CONFIG_LIBOPUS 0
%define CONFIG_LIBPULSE 0
%define CONFIG_LIBQUVI 0
%define CONFIG_LIBRTMP 0
%define CONFIG_LIBSCHROEDINGER 0
%define CONFIG_LIBSHINE 0
%define CONFIG_LIBSOXR 0
%define CONFIG_LIBSPEEX 0
%define CONFIG_LIBSTAGEFRIGHT_H264 0
%define CONFIG_LIBTHEORA 0
%define CONFIG_LIBTWOLAME 0
%define CONFIG_LIBUTVIDEO 0
%define CONFIG_LIBV4L2 0
%define CONFIG_LIBVIDSTAB 0
%define CONFIG_LIBVO_AACENC 0
%define CONFIG_LIBVO_AMRWBENC 0
%define CONFIG_LIBVORBIS 0
%define CONFIG_LIBVPX 0
%define CONFIG_LIBX264 0
%define CONFIG_LIBXAVS 0
%define CONFIG_LIBXVID 0
%define CONFIG_OPENAL 0
%define CONFIG_OPENCL 0
%define CONFIG_OPENSSL 0
%define CONFIG_X11GRAB 0
%define CONFIG_ZLIB 0
%define CONFIG_DXVA2 0
%define CONFIG_VAAPI 0
%define CONFIG_VDA 0
%define CONFIG_VDPAU 0
%define CONFIG_AVCODEC 1
%define CONFIG_AVDEVICE 0
%define CONFIG_AVFILTER 0
%define CONFIG_AVFORMAT 1
%define CONFIG_AVRESAMPLE 0
%define CONFIG_AVUTIL 1
%define CONFIG_POSTPROC 0
%define CONFIG_SWRESAMPLE 0
%define CONFIG_SWSCALE 0
%define CONFIG_FFPLAY 0
%define CONFIG_FFPROBE 0
%define CONFIG_FFSERVER 0
%define CONFIG_FFMPEG 0
%define CONFIG_DCT 0
%define CONFIG_DWT 0
%define CONFIG_ERROR_RESILIENCE 0
%define CONFIG_FAST_UNALIGNED 1
%define CONFIG_FFT 1
%define CONFIG_FTRAPV 0
%define CONFIG_GPL 0
%define CONFIG_GRAY 0
%define CONFIG_HARDCODED_TABLES 0
%define CONFIG_INCOMPATIBLE_FORK_ABI 0
%define CONFIG_LSP 0
%define CONFIG_LZO 0
%define CONFIG_MDCT 1
%define CONFIG_MEMALIGN_HACK 0
%define CONFIG_MEMORY_POISONING 0
%define CONFIG_NETWORK 0
%define CONFIG_NONFREE 0
%define CONFIG_PIC 1
%define CONFIG_RDFT 1
%define CONFIG_RUNTIME_CPUDETECT 1
%define CONFIG_SAFE_BITSTREAM_READER 1
%define CONFIG_SHARED 1
%define CONFIG_SMALL 0
%define CONFIG_SRAM 0
%define CONFIG_STATIC 1
%define CONFIG_SWSCALE_ALPHA 1
%define CONFIG_THUMB 0
%define CONFIG_VERSION3 0
%define CONFIG_XMM_CLOBBER_TEST 0
%define CONFIG_AANDCTTABLES 0
%define CONFIG_AC3DSP 0
%define CONFIG_AUDIO_FRAME_QUEUE 0
%define CONFIG_DSPUTIL 0
%define CONFIG_FRAME_THREAD_ENCODER 0
%define CONFIG_GCRYPT 0
%define CONFIG_GOLOMB 1
%define CONFIG_GPLV3 0
%define CONFIG_H264CHROMA 0
%define CONFIG_H264DSP 0
%define CONFIG_H264PRED 1
%define CONFIG_H264QPEL 0
%define CONFIG_HPELDSP 1
%define CONFIG_HUFFMAN 0
%define CONFIG_LGPLV3 0
%define CONFIG_LPC 0
%define CONFIG_MPEGAUDIO 0
%define CONFIG_MPEGAUDIODSP 0
%define CONFIG_MPEGVIDEO 0
%define CONFIG_MPEGVIDEOENC 0
%define CONFIG_NETTLE 0
%define CONFIG_RANGECODER 0
%define CONFIG_RTPDEC 0
%define CONFIG_RTPENC_CHAIN 0
%define CONFIG_SINEWIN 0
%define CONFIG_VIDEODSP 1
%define CONFIG_VP3DSP 1
%define CONFIG_AAC_ADTSTOASC_BSF 0
%define CONFIG_CHOMP_BSF 0
%define CONFIG_DUMP_EXTRADATA_BSF 0
%define CONFIG_H264_MP4TOANNEXB_BSF 0
%define CONFIG_IMX_DUMP_HEADER_BSF 0
%define CONFIG_MJPEG2JPEG_BSF 0
%define CONFIG_MJPEGA_DUMP_HEADER_BSF 0
%define CONFIG_MP3_HEADER_COMPRESS_BSF 0
%define CONFIG_MP3_HEADER_DECOMPRESS_BSF 0
%define CONFIG_MOV2TEXTSUB_BSF 0
%define CONFIG_NOISE_BSF 0
%define CONFIG_REMOVE_EXTRADATA_BSF 0
%define CONFIG_TEXT2MOVSUB_BSF 0
%define CONFIG_AASC_DECODER 0
%define CONFIG_AMV_DECODER 0
%define CONFIG_ANM_DECODER 0
%define CONFIG_ANSI_DECODER 0
%define CONFIG_ASV1_DECODER 0
%define CONFIG_ASV2_DECODER 0
%define CONFIG_AURA_DECODER 0
%define CONFIG_AURA2_DECODER 0
%define CONFIG_AVRP_DECODER 0
%define CONFIG_AVRN_DECODER 0
%define CONFIG_AVS_DECODER 0
%define CONFIG_AVUI_DECODER 0
%define CONFIG_AYUV_DECODER 0
%define CONFIG_BETHSOFTVID_DECODER 0
%define CONFIG_BFI_DECODER 0
%define CONFIG_BINK_DECODER 0
%define CONFIG_BMP_DECODER 0
%define CONFIG_BMV_VIDEO_DECODER 0
%define CONFIG_BRENDER_PIX_DECODER 0
%define CONFIG_C93_DECODER 0
%define CONFIG_CAVS_DECODER 0
%define CONFIG_CDGRAPHICS_DECODER 0
%define CONFIG_CDXL_DECODER 0
%define CONFIG_CINEPAK_DECODER 0
%define CONFIG_CLJR_DECODER 0
%define CONFIG_CLLC_DECODER 0
%define CONFIG_COMFORTNOISE_DECODER 0
%define CONFIG_CPIA_DECODER 0
%define CONFIG_CSCD_DECODER 0
%define CONFIG_CYUV_DECODER 0
%define CONFIG_DFA_DECODER 0
%define CONFIG_DIRAC_DECODER 0
%define CONFIG_DNXHD_DECODER 0
%define CONFIG_DPX_DECODER 0
%define CONFIG_DSICINVIDEO_DECODER 0
%define CONFIG_DVVIDEO_DECODER 0
%define CONFIG_DXA_DECODER 0
%define CONFIG_DXTORY_DECODER 0
%define CONFIG_EACMV_DECODER 0
%define CONFIG_EAMAD_DECODER 0
%define CONFIG_EATGQ_DECODER 0
%define CONFIG_EATGV_DECODER 0
%define CONFIG_EATQI_DECODER 0
%define CONFIG_EIGHTBPS_DECODER 0
%define CONFIG_EIGHTSVX_EXP_DECODER 0
%define CONFIG_EIGHTSVX_FIB_DECODER 0
%define CONFIG_ESCAPE124_DECODER 0
%define CONFIG_ESCAPE130_DECODER 0
%define CONFIG_EXR_DECODER 0
%define CONFIG_FFV1_DECODER 0
%define CONFIG_FFVHUFF_DECODER 0
%define CONFIG_FLASHSV_DECODER 0
%define CONFIG_FLASHSV2_DECODER 0
%define CONFIG_FLIC_DECODER 0
%define CONFIG_FLV_DECODER 0
%define CONFIG_FOURXM_DECODER 0
%define CONFIG_FRAPS_DECODER 0
%define CONFIG_FRWU_DECODER 0
%define CONFIG_GIF_DECODER 0
%define CONFIG_H261_DECODER 0
%define CONFIG_H263_DECODER 0
%define CONFIG_H263I_DECODER 0
%define CONFIG_H263P_DECODER 0
%define CONFIG_H264_DECODER 0
%define CONFIG_H264_CRYSTALHD_DECODER 0
%define CONFIG_H264_VDA_DECODER 0
%define CONFIG_H264_VDPAU_DECODER 0
%define CONFIG_HUFFYUV_DECODER 0
%define CONFIG_IDCIN_DECODER 0
%define CONFIG_IFF_BYTERUN1_DECODER 0
%define CONFIG_IFF_ILBM_DECODER 0
%define CONFIG_INDEO2_DECODER 0
%define CONFIG_INDEO3_DECODER 0
%define CONFIG_INDEO4_DECODER 0
%define CONFIG_INDEO5_DECODER 0
%define CONFIG_INTERPLAY_VIDEO_DECODER 0
%define CONFIG_J2K_DECODER 0
%define CONFIG_JPEG2000_DECODER 0
%define CONFIG_JPEGLS_DECODER 0
%define CONFIG_JV_DECODER 0
%define CONFIG_KGV1_DECODER 0
%define CONFIG_KMVC_DECODER 0
%define CONFIG_LAGARITH_DECODER 0
%define CONFIG_LOCO_DECODER 0
%define CONFIG_MDEC_DECODER 0
%define CONFIG_MIMIC_DECODER 0
%define CONFIG_MJPEG_DECODER 0
%define CONFIG_MJPEGB_DECODER 0
%define CONFIG_MMVIDEO_DECODER 0
%define CONFIG_MOTIONPIXELS_DECODER 0
%define CONFIG_MPEG_XVMC_DECODER 0
%define CONFIG_MPEG1VIDEO_DECODER 0
%define CONFIG_MPEG2VIDEO_DECODER 0
%define CONFIG_MPEG4_DECODER 0
%define CONFIG_MPEG4_CRYSTALHD_DECODER 0
%define CONFIG_MPEG4_VDPAU_DECODER 0
%define CONFIG_MPEGVIDEO_DECODER 0
%define CONFIG_MPEG_VDPAU_DECODER 0
%define CONFIG_MPEG1_VDPAU_DECODER 0
%define CONFIG_MPEG2_CRYSTALHD_DECODER 0
%define CONFIG_MSA1_DECODER 0
%define CONFIG_MSMPEG4_CRYSTALHD_DECODER 0
%define CONFIG_MSMPEG4V1_DECODER 0
%define CONFIG_MSMPEG4V2_DECODER 0
%define CONFIG_MSMPEG4V3_DECODER 0
%define CONFIG_MSRLE_DECODER 0
%define CONFIG_MSS1_DECODER 0
%define CONFIG_MSS2_DECODER 0
%define CONFIG_MSVIDEO1_DECODER 0
%define CONFIG_MSZH_DECODER 0
%define CONFIG_MTS2_DECODER 0
%define CONFIG_MVC1_DECODER 0
%define CONFIG_MVC2_DECODER 0
%define CONFIG_MXPEG_DECODER 0
%define CONFIG_NUV_DECODER 0
%define CONFIG_PAF_VIDEO_DECODER 0
%define CONFIG_PAM_DECODER 0
%define CONFIG_PBM_DECODER 0
%define CONFIG_PCX_DECODER 0
%define CONFIG_PGM_DECODER 0
%define CONFIG_PGMYUV_DECODER 0
%define CONFIG_PICTOR_DECODER 0
%define CONFIG_PNG_DECODER 0
%define CONFIG_PPM_DECODER 0
%define CONFIG_PRORES_DECODER 0
%define CONFIG_PRORES_LGPL_DECODER 0
%define CONFIG_PTX_DECODER 0
%define CONFIG_QDRAW_DECODER 0
%define CONFIG_QPEG_DECODER 0
%define CONFIG_QTRLE_DECODER 0
%define CONFIG_R10K_DECODER 0
%define CONFIG_R210_DECODER 0
%define CONFIG_RAWVIDEO_DECODER 0
%define CONFIG_RL2_DECODER 0
%define CONFIG_ROQ_DECODER 0
%define CONFIG_RPZA_DECODER 0
%define CONFIG_RV10_DECODER 0
%define CONFIG_RV20_DECODER 0
%define CONFIG_RV30_DECODER 0
%define CONFIG_RV40_DECODER 0
%define CONFIG_S302M_DECODER 0
%define CONFIG_SANM_DECODER 0
%define CONFIG_SGI_DECODER 0
%define CONFIG_SGIRLE_DECODER 0
%define CONFIG_SMACKER_DECODER 0
%define CONFIG_SMC_DECODER 0
%define CONFIG_SNOW_DECODER 0
%define CONFIG_SP5X_DECODER 0
%define CONFIG_SUNRAST_DECODER 0
%define CONFIG_SVQ1_DECODER 0
%define CONFIG_SVQ3_DECODER 0
%define CONFIG_TARGA_DECODER 0
%define CONFIG_TARGA_Y216_DECODER 0
%define CONFIG_THEORA_DECODER 1
%define CONFIG_THP_DECODER 0
%define CONFIG_TIERTEXSEQVIDEO_DECODER 0
%define CONFIG_TIFF_DECODER 0
%define CONFIG_TMV_DECODER 0
%define CONFIG_TRUEMOTION1_DECODER 0
%define CONFIG_TRUEMOTION2_DECODER 0
%define CONFIG_TSCC_DECODER 0
%define CONFIG_TSCC2_DECODER 0
%define CONFIG_TXD_DECODER 0
%define CONFIG_ULTI_DECODER 0
%define CONFIG_UTVIDEO_DECODER 0
%define CONFIG_V210_DECODER 0
%define CONFIG_V210X_DECODER 0
%define CONFIG_V308_DECODER 0
%define CONFIG_V408_DECODER 0
%define CONFIG_V410_DECODER 0
%define CONFIG_VB_DECODER 0
%define CONFIG_VBLE_DECODER 0
%define CONFIG_VC1_DECODER 0
%define CONFIG_VC1_CRYSTALHD_DECODER 0
%define CONFIG_VC1_VDPAU_DECODER 0
%define CONFIG_VC1IMAGE_DECODER 0
%define CONFIG_VCR1_DECODER 0
%define CONFIG_VMDVIDEO_DECODER 0
%define CONFIG_VMNC_DECODER 0
%define CONFIG_VP3_DECODER 1
%define CONFIG_VP5_DECODER 0
%define CONFIG_VP6_DECODER 0
%define CONFIG_VP6A_DECODER 0
%define CONFIG_VP6F_DECODER 0
%define CONFIG_VP8_DECODER 1
%define CONFIG_VQA_DECODER 0
%define CONFIG_WEBP_DECODER 0
%define CONFIG_WMV1_DECODER 0
%define CONFIG_WMV2_DECODER 0
%define CONFIG_WMV3_DECODER 0
%define CONFIG_WMV3_CRYSTALHD_DECODER 0
%define CONFIG_WMV3_VDPAU_DECODER 0
%define CONFIG_WMV3IMAGE_DECODER 0
%define CONFIG_WNV1_DECODER 0
%define CONFIG_XAN_WC3_DECODER 0
%define CONFIG_XAN_WC4_DECODER 0
%define CONFIG_XBM_DECODER 0
%define CONFIG_XFACE_DECODER 0
%define CONFIG_XL_DECODER 0
%define CONFIG_XWD_DECODER 0
%define CONFIG_Y41P_DECODER 0
%define CONFIG_YOP_DECODER 0
%define CONFIG_YUV4_DECODER 0
%define CONFIG_ZERO12V_DECODER 0
%define CONFIG_ZEROCODEC_DECODER 0
%define CONFIG_ZLIB_DECODER 0
%define CONFIG_ZMBV_DECODER 0
%define CONFIG_AAC_DECODER 0
%define CONFIG_AAC_LATM_DECODER 0
%define CONFIG_AC3_DECODER 0
%define CONFIG_ALAC_DECODER 0
%define CONFIG_ALS_DECODER 0
%define CONFIG_AMRNB_DECODER 0
%define CONFIG_AMRWB_DECODER 0
%define CONFIG_APE_DECODER 0
%define CONFIG_ATRAC1_DECODER 0
%define CONFIG_ATRAC3_DECODER 0
%define CONFIG_BINKAUDIO_DCT_DECODER 0
%define CONFIG_BINKAUDIO_RDFT_DECODER 0
%define CONFIG_BMV_AUDIO_DECODER 0
%define CONFIG_COOK_DECODER 0
%define CONFIG_DCA_DECODER 0
%define CONFIG_DSICINAUDIO_DECODER 0
%define CONFIG_EAC3_DECODER 0
%define CONFIG_EVRC_DECODER 0
%define CONFIG_FFWAVESYNTH_DECODER 0
%define CONFIG_FLAC_DECODER 0
%define CONFIG_G723_1_DECODER 0
%define CONFIG_G729_DECODER 0
%define CONFIG_GSM_DECODER 0
%define CONFIG_GSM_MS_DECODER 0
%define CONFIG_IAC_DECODER 0
%define CONFIG_IMC_DECODER 0
%define CONFIG_MACE3_DECODER 0
%define CONFIG_MACE6_DECODER 0
%define CONFIG_MLP_DECODER 0
%define CONFIG_MP1_DECODER 0
%define CONFIG_MP1FLOAT_DECODER 0
%define CONFIG_MP2_DECODER 0
%define CONFIG_MP2FLOAT_DECODER 0
%define CONFIG_MP3_DECODER 0
%define CONFIG_MP3FLOAT_DECODER 0
%define CONFIG_MP3ADU_DECODER 0
%define CONFIG_MP3ADUFLOAT_DECODER 0
%define CONFIG_MP3ON4_DECODER 0
%define CONFIG_MP3ON4FLOAT_DECODER 0
%define CONFIG_MPC7_DECODER 0
%define CONFIG_MPC8_DECODER 0
%define CONFIG_NELLYMOSER_DECODER 0
%define CONFIG_PAF_AUDIO_DECODER 0
%define CONFIG_QCELP_DECODER 0
%define CONFIG_QDM2_DECODER 0
%define CONFIG_RA_144_DECODER 0
%define CONFIG_RA_288_DECODER 0
%define CONFIG_RALF_DECODER 0
%define CONFIG_SHORTEN_DECODER 0
%define CONFIG_SIPR_DECODER 0
%define CONFIG_SMACKAUD_DECODER 0
%define CONFIG_SONIC_DECODER 0
%define CONFIG_TAK_DECODER 0
%define CONFIG_TRUEHD_DECODER 0
%define CONFIG_TRUESPEECH_DECODER 0
%define CONFIG_TTA_DECODER 0
%define CONFIG_TWINVQ_DECODER 0
%define CONFIG_VMDAUDIO_DECODER 0
%define CONFIG_VORBIS_DECODER 1
%define CONFIG_WAVPACK_DECODER 0
%define CONFIG_WMALOSSLESS_DECODER 0
%define CONFIG_WMAPRO_DECODER 0
%define CONFIG_WMAV1_DECODER 0
%define CONFIG_WMAV2_DECODER 0
%define CONFIG_WMAVOICE_DECODER 0
%define CONFIG_WS_SND1_DECODER 0
%define CONFIG_PCM_ALAW_DECODER 0
%define CONFIG_PCM_BLURAY_DECODER 0
%define CONFIG_PCM_DVD_DECODER 0
%define CONFIG_PCM_F32BE_DECODER 0
%define CONFIG_PCM_F32LE_DECODER 1
%define CONFIG_PCM_F64BE_DECODER 0
%define CONFIG_PCM_F64LE_DECODER 0
%define CONFIG_PCM_LXF_DECODER 0
%define CONFIG_PCM_MULAW_DECODER 0
%define CONFIG_PCM_S8_DECODER 0
%define CONFIG_PCM_S8_PLANAR_DECODER 0
%define CONFIG_PCM_S16BE_DECODER 1
%define CONFIG_PCM_S16BE_PLANAR_DECODER 0
%define CONFIG_PCM_S16LE_DECODER 1
%define CONFIG_PCM_S16LE_PLANAR_DECODER 0
%define CONFIG_PCM_S24BE_DECODER 1
%define CONFIG_PCM_S24DAUD_DECODER 0
%define CONFIG_PCM_S24LE_DECODER 1
%define CONFIG_PCM_S24LE_PLANAR_DECODER 0
%define CONFIG_PCM_S32BE_DECODER 0
%define CONFIG_PCM_S32LE_DECODER 0
%define CONFIG_PCM_S32LE_PLANAR_DECODER 0
%define CONFIG_PCM_U8_DECODER 1
%define CONFIG_PCM_U16BE_DECODER 0
%define CONFIG_PCM_U16LE_DECODER 0
%define CONFIG_PCM_U24BE_DECODER 0
%define CONFIG_PCM_U24LE_DECODER 0
%define CONFIG_PCM_U32BE_DECODER 0
%define CONFIG_PCM_U32LE_DECODER 0
%define CONFIG_PCM_ZORK_DECODER 0
%define CONFIG_INTERPLAY_DPCM_DECODER 0
%define CONFIG_ROQ_DPCM_DECODER 0
%define CONFIG_SOL_DPCM_DECODER 0
%define CONFIG_XAN_DPCM_DECODER 0
%define CONFIG_ADPCM_4XM_DECODER 0
%define CONFIG_ADPCM_ADX_DECODER 0
%define CONFIG_ADPCM_AFC_DECODER 0
%define CONFIG_ADPCM_CT_DECODER 0
%define CONFIG_ADPCM_EA_DECODER 0
%define CONFIG_ADPCM_EA_MAXIS_XA_DECODER 0
%define CONFIG_ADPCM_EA_R1_DECODER 0
%define CONFIG_ADPCM_EA_R2_DECODER 0
%define CONFIG_ADPCM_EA_R3_DECODER 0
%define CONFIG_ADPCM_EA_XAS_DECODER 0
%define CONFIG_ADPCM_G722_DECODER 0
%define CONFIG_ADPCM_G726_DECODER 0
%define CONFIG_ADPCM_IMA_AMV_DECODER 0
%define CONFIG_ADPCM_IMA_APC_DECODER 0
%define CONFIG_ADPCM_IMA_DK3_DECODER 0
%define CONFIG_ADPCM_IMA_DK4_DECODER 0
%define CONFIG_ADPCM_IMA_EA_EACS_DECODER 0
%define CONFIG_ADPCM_IMA_EA_SEAD_DECODER 0
%define CONFIG_ADPCM_IMA_ISS_DECODER 0
%define CONFIG_ADPCM_IMA_OKI_DECODER 0
%define CONFIG_ADPCM_IMA_QT_DECODER 0
%define CONFIG_ADPCM_IMA_SMJPEG_DECODER 0
%define CONFIG_ADPCM_IMA_WAV_DECODER 0
%define CONFIG_ADPCM_IMA_WS_DECODER 0
%define CONFIG_ADPCM_MS_DECODER 0
%define CONFIG_ADPCM_SBPRO_2_DECODER 0
%define CONFIG_ADPCM_SBPRO_3_DECODER 0
%define CONFIG_ADPCM_SBPRO_4_DECODER 0
%define CONFIG_ADPCM_SWF_DECODER 0
%define CONFIG_ADPCM_THP_DECODER 0
%define CONFIG_ADPCM_XA_DECODER 0
%define CONFIG_ADPCM_YAMAHA_DECODER 0
%define CONFIG_VIMA_DECODER 0
%define CONFIG_SSA_DECODER 0
%define CONFIG_ASS_DECODER 0
%define CONFIG_DVBSUB_DECODER 0
%define CONFIG_DVDSUB_DECODER 0
%define CONFIG_JACOSUB_DECODER 0
%define CONFIG_MICRODVD_DECODER 0
%define CONFIG_MOVTEXT_DECODER 0
%define CONFIG_MPL2_DECODER 0
%define CONFIG_PGSSUB_DECODER 0
%define CONFIG_PJS_DECODER 0
%define CONFIG_REALTEXT_DECODER 0
%define CONFIG_SAMI_DECODER 0
%define CONFIG_SRT_DECODER 0
%define CONFIG_SUBRIP_DECODER 0
%define CONFIG_SUBVIEWER_DECODER 0
%define CONFIG_SUBVIEWER1_DECODER 0
%define CONFIG_TEXT_DECODER 0
%define CONFIG_VPLAYER_DECODER 0
%define CONFIG_WEBVTT_DECODER 0
%define CONFIG_XSUB_DECODER 0
%define CONFIG_LIBCELT_DECODER 0
%define CONFIG_LIBGSM_DECODER 0
%define CONFIG_LIBGSM_MS_DECODER 0
%define CONFIG_LIBILBC_DECODER 0
%define CONFIG_LIBOPENCORE_AMRNB_DECODER 0
%define CONFIG_LIBOPENCORE_AMRWB_DECODER 0
%define CONFIG_LIBOPENJPEG_DECODER 0
%define CONFIG_LIBOPUS_DECODER 0
%define CONFIG_LIBSCHROEDINGER_DECODER 0
%define CONFIG_LIBSPEEX_DECODER 0
%define CONFIG_LIBSTAGEFRIGHT_H264_DECODER 0
%define CONFIG_LIBUTVIDEO_DECODER 0
%define CONFIG_LIBVORBIS_DECODER 0
%define CONFIG_LIBVPX_VP8_DECODER 0
%define CONFIG_LIBVPX_VP9_DECODER 0
%define CONFIG_BINTEXT_DECODER 0
%define CONFIG_XBIN_DECODER 0
%define CONFIG_IDF_DECODER 0
%define CONFIG_AAC_DEMUXER 0
%define CONFIG_AC3_DEMUXER 0
%define CONFIG_ACT_DEMUXER 0
%define CONFIG_ADF_DEMUXER 0
%define CONFIG_ADX_DEMUXER 0
%define CONFIG_AEA_DEMUXER 0
%define CONFIG_AFC_DEMUXER 0
%define CONFIG_AIFF_DEMUXER 0
%define CONFIG_AMR_DEMUXER 0
%define CONFIG_ANM_DEMUXER 0
%define CONFIG_APC_DEMUXER 0
%define CONFIG_APE_DEMUXER 0
%define CONFIG_AQTITLE_DEMUXER 0
%define CONFIG_ASF_DEMUXER 0
%define CONFIG_ASS_DEMUXER 0
%define CONFIG_AST_DEMUXER 0
%define CONFIG_AU_DEMUXER 0
%define CONFIG_AVI_DEMUXER 0
%define CONFIG_AVISYNTH_DEMUXER 0
%define CONFIG_AVR_DEMUXER 0
%define CONFIG_AVS_DEMUXER 0
%define CONFIG_BETHSOFTVID_DEMUXER 0
%define CONFIG_BFI_DEMUXER 0
%define CONFIG_BINTEXT_DEMUXER 0
%define CONFIG_BINK_DEMUXER 0
%define CONFIG_BIT_DEMUXER 0
%define CONFIG_BMV_DEMUXER 0
%define CONFIG_BRSTM_DEMUXER 0
%define CONFIG_C93_DEMUXER 0
%define CONFIG_CAF_DEMUXER 0
%define CONFIG_CAVSVIDEO_DEMUXER 0
%define CONFIG_CDG_DEMUXER 0
%define CONFIG_CDXL_DEMUXER 0
%define CONFIG_CONCAT_DEMUXER 0
%define CONFIG_DAUD_DEMUXER 0
%define CONFIG_DFA_DEMUXER 0
%define CONFIG_DIRAC_DEMUXER 0
%define CONFIG_DNXHD_DEMUXER 0
%define CONFIG_DSICIN_DEMUXER 0
%define CONFIG_DTS_DEMUXER 0
%define CONFIG_DTSHD_DEMUXER 0
%define CONFIG_DV_DEMUXER 0
%define CONFIG_DXA_DEMUXER 0
%define CONFIG_EA_DEMUXER 0
%define CONFIG_EA_CDATA_DEMUXER 0
%define CONFIG_EAC3_DEMUXER 0
%define CONFIG_EPAF_DEMUXER 0
%define CONFIG_FFM_DEMUXER 0
%define CONFIG_FFMETADATA_DEMUXER 0
%define CONFIG_FILMSTRIP_DEMUXER 0
%define CONFIG_FLAC_DEMUXER 0
%define CONFIG_FLIC_DEMUXER 0
%define CONFIG_FLV_DEMUXER 0
%define CONFIG_FOURXM_DEMUXER 0
%define CONFIG_FRM_DEMUXER 0
%define CONFIG_G722_DEMUXER 0
%define CONFIG_G723_1_DEMUXER 0
%define CONFIG_G729_DEMUXER 0
%define CONFIG_GIF_DEMUXER 0
%define CONFIG_GSM_DEMUXER 0
%define CONFIG_GXF_DEMUXER 0
%define CONFIG_H261_DEMUXER 0
%define CONFIG_H263_DEMUXER 0
%define CONFIG_H264_DEMUXER 0
%define CONFIG_HLS_DEMUXER 0
%define CONFIG_ICO_DEMUXER 0
%define CONFIG_IDCIN_DEMUXER 0
%define CONFIG_IDF_DEMUXER 0
%define CONFIG_IFF_DEMUXER 0
%define CONFIG_ILBC_DEMUXER 0
%define CONFIG_IMAGE2_DEMUXER 0
%define CONFIG_IMAGE2PIPE_DEMUXER 0
%define CONFIG_INGENIENT_DEMUXER 0
%define CONFIG_IPMOVIE_DEMUXER 0
%define CONFIG_IRCAM_DEMUXER 0
%define CONFIG_ISS_DEMUXER 0
%define CONFIG_IV8_DEMUXER 0
%define CONFIG_IVF_DEMUXER 0
%define CONFIG_JACOSUB_DEMUXER 0
%define CONFIG_JV_DEMUXER 0
%define CONFIG_LATM_DEMUXER 0
%define CONFIG_LMLM4_DEMUXER 0
%define CONFIG_LOAS_DEMUXER 0
%define CONFIG_LVF_DEMUXER 0
%define CONFIG_LXF_DEMUXER 0
%define CONFIG_M4V_DEMUXER 0
%define CONFIG_MATROSKA_DEMUXER 1
%define CONFIG_MGSTS_DEMUXER 0
%define CONFIG_MICRODVD_DEMUXER 0
%define CONFIG_MJPEG_DEMUXER 0
%define CONFIG_MLP_DEMUXER 0
%define CONFIG_MM_DEMUXER 0
%define CONFIG_MMF_DEMUXER 0
%define CONFIG_MOV_DEMUXER 0
%define CONFIG_MP3_DEMUXER 0
%define CONFIG_MPC_DEMUXER 0
%define CONFIG_MPC8_DEMUXER 0
%define CONFIG_MPEGPS_DEMUXER 0
%define CONFIG_MPEGTS_DEMUXER 0
%define CONFIG_MPEGTSRAW_DEMUXER 0
%define CONFIG_MPEGVIDEO_DEMUXER 0
%define CONFIG_MPL2_DEMUXER 0
%define CONFIG_MPSUB_DEMUXER 0
%define CONFIG_MSNWC_TCP_DEMUXER 0
%define CONFIG_MTV_DEMUXER 0
%define CONFIG_MV_DEMUXER 0
%define CONFIG_MVI_DEMUXER 0
%define CONFIG_MXF_DEMUXER 0
%define CONFIG_MXG_DEMUXER 0
%define CONFIG_NC_DEMUXER 0
%define CONFIG_NISTSPHERE_DEMUXER 0
%define CONFIG_NSV_DEMUXER 0
%define CONFIG_NUT_DEMUXER 0
%define CONFIG_NUV_DEMUXER 0
%define CONFIG_OGG_DEMUXER 1
%define CONFIG_OMA_DEMUXER 0
%define CONFIG_PAF_DEMUXER 0
%define CONFIG_PCM_ALAW_DEMUXER 0
%define CONFIG_PCM_MULAW_DEMUXER 0
%define CONFIG_PCM_F64BE_DEMUXER 0
%define CONFIG_PCM_F64LE_DEMUXER 0
%define CONFIG_PCM_F32BE_DEMUXER 0
%define CONFIG_PCM_F32LE_DEMUXER 0
%define CONFIG_PCM_S32BE_DEMUXER 0
%define CONFIG_PCM_S32LE_DEMUXER 0
%define CONFIG_PCM_S24BE_DEMUXER 0
%define CONFIG_PCM_S24LE_DEMUXER 0
%define CONFIG_PCM_S16BE_DEMUXER 0
%define CONFIG_PCM_S16LE_DEMUXER 0
%define CONFIG_PCM_S8_DEMUXER 0
%define CONFIG_PCM_U32BE_DEMUXER 0
%define CONFIG_PCM_U32LE_DEMUXER 0
%define CONFIG_PCM_U24BE_DEMUXER 0
%define CONFIG_PCM_U24LE_DEMUXER 0
%define CONFIG_PCM_U16BE_DEMUXER 0
%define CONFIG_PCM_U16LE_DEMUXER 0
%define CONFIG_PCM_U8_DEMUXER 0
%define CONFIG_PJS_DEMUXER 0
%define CONFIG_PMP_DEMUXER 0
%define CONFIG_PVA_DEMUXER 0
%define CONFIG_PVF_DEMUXER 0
%define CONFIG_QCP_DEMUXER 0
%define CONFIG_R3D_DEMUXER 0
%define CONFIG_RAWVIDEO_DEMUXER 0
%define CONFIG_REALTEXT_DEMUXER 0
%define CONFIG_RL2_DEMUXER 0
%define CONFIG_RM_DEMUXER 0
%define CONFIG_ROQ_DEMUXER 0
%define CONFIG_RPL_DEMUXER 0
%define CONFIG_RSO_DEMUXER 0
%define CONFIG_RTP_DEMUXER 0
%define CONFIG_RTSP_DEMUXER 0
%define CONFIG_SAMI_DEMUXER 0
%define CONFIG_SAP_DEMUXER 0
%define CONFIG_SBG_DEMUXER 0
%define CONFIG_SDP_DEMUXER 0
%define CONFIG_SEGAFILM_DEMUXER 0
%define CONFIG_SHORTEN_DEMUXER 0
%define CONFIG_SIFF_DEMUXER 0
%define CONFIG_SMACKER_DEMUXER 0
%define CONFIG_SMJPEG_DEMUXER 0
%define CONFIG_SMUSH_DEMUXER 0
%define CONFIG_SOL_DEMUXER 0
%define CONFIG_SOX_DEMUXER 0
%define CONFIG_SPDIF_DEMUXER 0
%define CONFIG_SRT_DEMUXER 0
%define CONFIG_STR_DEMUXER 0
%define CONFIG_SUBVIEWER1_DEMUXER 0
%define CONFIG_SUBVIEWER_DEMUXER 0
%define CONFIG_SWF_DEMUXER 0
%define CONFIG_TAK_DEMUXER 0
%define CONFIG_TEDCAPTIONS_DEMUXER 0
%define CONFIG_THP_DEMUXER 0
%define CONFIG_TIERTEXSEQ_DEMUXER 0
%define CONFIG_TMV_DEMUXER 0
%define CONFIG_TRUEHD_DEMUXER 0
%define CONFIG_TTA_DEMUXER 0
%define CONFIG_TXD_DEMUXER 0
%define CONFIG_TTY_DEMUXER 0
%define CONFIG_VC1_DEMUXER 0
%define CONFIG_VC1T_DEMUXER 0
%define CONFIG_VIVO_DEMUXER 0
%define CONFIG_VMD_DEMUXER 0
%define CONFIG_VOBSUB_DEMUXER 0
%define CONFIG_VOC_DEMUXER 0
%define CONFIG_VPLAYER_DEMUXER 0
%define CONFIG_VQF_DEMUXER 0
%define CONFIG_W64_DEMUXER 0
%define CONFIG_WAV_DEMUXER 1
%define CONFIG_WC3_DEMUXER 0
%define CONFIG_WEBVTT_DEMUXER 0
%define CONFIG_WSAUD_DEMUXER 0
%define CONFIG_WSVQA_DEMUXER 0
%define CONFIG_WTV_DEMUXER 0
%define CONFIG_WV_DEMUXER 0
%define CONFIG_XA_DEMUXER 0
%define CONFIG_XBIN_DEMUXER 0
%define CONFIG_XMV_DEMUXER 0
%define CONFIG_XWMA_DEMUXER 0
%define CONFIG_YOP_DEMUXER 0
%define CONFIG_YUV4MPEGPIPE_DEMUXER 0
%define CONFIG_LIBMODPLUG_DEMUXER 0
%define CONFIG_LIBNUT_DEMUXER 0
%define CONFIG_LIBQUVI_DEMUXER 0
%define CONFIG_A64MULTI_ENCODER 0
%define CONFIG_A64MULTI5_ENCODER 0
%define CONFIG_AMV_ENCODER 0
%define CONFIG_ASV1_ENCODER 0
%define CONFIG_ASV2_ENCODER 0
%define CONFIG_AVRP_ENCODER 0
%define CONFIG_AVUI_ENCODER 0
%define CONFIG_AYUV_ENCODER 0
%define CONFIG_BMP_ENCODER 0
%define CONFIG_CLJR_ENCODER 0
%define CONFIG_COMFORTNOISE_ENCODER 0
%define CONFIG_DNXHD_ENCODER 0
%define CONFIG_DPX_ENCODER 0
%define CONFIG_DVVIDEO_ENCODER 0
%define CONFIG_FFV1_ENCODER 0
%define CONFIG_FFVHUFF_ENCODER 0
%define CONFIG_FLASHSV_ENCODER 0
%define CONFIG_FLASHSV2_ENCODER 0
%define CONFIG_FLV_ENCODER 0
%define CONFIG_GIF_ENCODER 0
%define CONFIG_H261_ENCODER 0
%define CONFIG_H263_ENCODER 0
%define CONFIG_H263P_ENCODER 0
%define CONFIG_HUFFYUV_ENCODER 0
%define CONFIG_J2K_ENCODER 0
%define CONFIG_JPEGLS_ENCODER 0
%define CONFIG_LJPEG_ENCODER 0
%define CONFIG_MJPEG_ENCODER 0
%define CONFIG_MPEG1VIDEO_ENCODER 0
%define CONFIG_MPEG2VIDEO_ENCODER 0
%define CONFIG_MPEG4_ENCODER 0
%define CONFIG_MSMPEG4V2_ENCODER 0
%define CONFIG_MSMPEG4V3_ENCODER 0
%define CONFIG_MSVIDEO1_ENCODER 0
%define CONFIG_PAM_ENCODER 0
%define CONFIG_PBM_ENCODER 0
%define CONFIG_PCX_ENCODER 0
%define CONFIG_PGM_ENCODER 0
%define CONFIG_PGMYUV_ENCODER 0
%define CONFIG_PNG_ENCODER 0
%define CONFIG_PPM_ENCODER 0
%define CONFIG_PRORES_ENCODER 0
%define CONFIG_PRORES_AW_ENCODER 0
%define CONFIG_PRORES_KS_ENCODER 0
%define CONFIG_QTRLE_ENCODER 0
%define CONFIG_R10K_ENCODER 0
%define CONFIG_R210_ENCODER 0
%define CONFIG_RAWVIDEO_ENCODER 0
%define CONFIG_ROQ_ENCODER 0
%define CONFIG_RV10_ENCODER 0
%define CONFIG_RV20_ENCODER 0
%define CONFIG_SGI_ENCODER 0
%define CONFIG_SNOW_ENCODER 0
%define CONFIG_SUNRAST_ENCODER 0
%define CONFIG_SVQ1_ENCODER 0
%define CONFIG_TARGA_ENCODER 0
%define CONFIG_TIFF_ENCODER 0
%define CONFIG_UTVIDEO_ENCODER 0
%define CONFIG_V210_ENCODER 0
%define CONFIG_V308_ENCODER 0
%define CONFIG_V408_ENCODER 0
%define CONFIG_V410_ENCODER 0
%define CONFIG_WMV1_ENCODER 0
%define CONFIG_WMV2_ENCODER 0
%define CONFIG_XBM_ENCODER 0
%define CONFIG_XFACE_ENCODER 0
%define CONFIG_XWD_ENCODER 0
%define CONFIG_Y41P_ENCODER 0
%define CONFIG_YUV4_ENCODER 0
%define CONFIG_ZLIB_ENCODER 0
%define CONFIG_ZMBV_ENCODER 0
%define CONFIG_AAC_ENCODER 0
%define CONFIG_AC3_ENCODER 0
%define CONFIG_AC3_FIXED_ENCODER 0
%define CONFIG_ALAC_ENCODER 0
%define CONFIG_DCA_ENCODER 0
%define CONFIG_EAC3_ENCODER 0
%define CONFIG_FLAC_ENCODER 0
%define CONFIG_G723_1_ENCODER 0
%define CONFIG_MP2_ENCODER 0
%define CONFIG_NELLYMOSER_ENCODER 0
%define CONFIG_RA_144_ENCODER 0
%define CONFIG_SONIC_ENCODER 0
%define CONFIG_SONIC_LS_ENCODER 0
%define CONFIG_VORBIS_ENCODER 0
%define CONFIG_WMAV1_ENCODER 0
%define CONFIG_WMAV2_ENCODER 0
%define CONFIG_PCM_ALAW_ENCODER 0
%define CONFIG_PCM_F32BE_ENCODER 0
%define CONFIG_PCM_F32LE_ENCODER 0
%define CONFIG_PCM_F64BE_ENCODER 0
%define CONFIG_PCM_F64LE_ENCODER 0
%define CONFIG_PCM_MULAW_ENCODER 0
%define CONFIG_PCM_S8_ENCODER 0
%define CONFIG_PCM_S8_PLANAR_ENCODER 0
%define CONFIG_PCM_S16BE_ENCODER 0
%define CONFIG_PCM_S16BE_PLANAR_ENCODER 0
%define CONFIG_PCM_S16LE_ENCODER 0
%define CONFIG_PCM_S16LE_PLANAR_ENCODER 0
%define CONFIG_PCM_S24BE_ENCODER 0
%define CONFIG_PCM_S24DAUD_ENCODER 0
%define CONFIG_PCM_S24LE_ENCODER 0
%define CONFIG_PCM_S24LE_PLANAR_ENCODER 0
%define CONFIG_PCM_S32BE_ENCODER 0
%define CONFIG_PCM_S32LE_ENCODER 0
%define CONFIG_PCM_S32LE_PLANAR_ENCODER 0
%define CONFIG_PCM_U8_ENCODER 0
%define CONFIG_PCM_U16BE_ENCODER 0
%define CONFIG_PCM_U16LE_ENCODER 0
%define CONFIG_PCM_U24BE_ENCODER 0
%define CONFIG_PCM_U24LE_ENCODER 0
%define CONFIG_PCM_U32BE_ENCODER 0
%define CONFIG_PCM_U32LE_ENCODER 0
%define CONFIG_ROQ_DPCM_ENCODER 0
%define CONFIG_ADPCM_ADX_ENCODER 0
%define CONFIG_ADPCM_G722_ENCODER 0
%define CONFIG_ADPCM_G726_ENCODER 0
%define CONFIG_ADPCM_IMA_QT_ENCODER 0
%define CONFIG_ADPCM_IMA_WAV_ENCODER 0
%define CONFIG_ADPCM_MS_ENCODER 0
%define CONFIG_ADPCM_SWF_ENCODER 0
%define CONFIG_ADPCM_YAMAHA_ENCODER 0
%define CONFIG_SSA_ENCODER 0
%define CONFIG_ASS_ENCODER 0
%define CONFIG_DVBSUB_ENCODER 0
%define CONFIG_DVDSUB_ENCODER 0
%define CONFIG_MOVTEXT_ENCODER 0
%define CONFIG_SRT_ENCODER 0
%define CONFIG_SUBRIP_ENCODER 0
%define CONFIG_XSUB_ENCODER 0
%define CONFIG_LIBFAAC_ENCODER 0
%define CONFIG_LIBFDK_AAC_ENCODER 0
%define CONFIG_LIBGSM_ENCODER 0
%define CONFIG_LIBGSM_MS_ENCODER 0
%define CONFIG_LIBILBC_ENCODER 0
%define CONFIG_LIBMP3LAME_ENCODER 0
%define CONFIG_LIBOPENCORE_AMRNB_ENCODER 0
%define CONFIG_LIBOPENJPEG_ENCODER 0
%define CONFIG_LIBOPUS_ENCODER 0
%define CONFIG_LIBSCHROEDINGER_ENCODER 0
%define CONFIG_LIBSHINE_ENCODER 0
%define CONFIG_LIBSPEEX_ENCODER 0
%define CONFIG_LIBTHEORA_ENCODER 0
%define CONFIG_LIBTWOLAME_ENCODER 0
%define CONFIG_LIBUTVIDEO_ENCODER 0
%define CONFIG_LIBVO_AACENC_ENCODER 0
%define CONFIG_LIBVO_AMRWBENC_ENCODER 0
%define CONFIG_LIBVORBIS_ENCODER 0
%define CONFIG_LIBVPX_VP8_ENCODER 0
%define CONFIG_LIBVPX_VP9_ENCODER 0
%define CONFIG_LIBX264_ENCODER 0
%define CONFIG_LIBX264RGB_ENCODER 0
%define CONFIG_LIBXAVS_ENCODER 0
%define CONFIG_LIBXVID_ENCODER 0
%define CONFIG_LIBAACPLUS_ENCODER 0
%define CONFIG_ACONVERT_FILTER 0
%define CONFIG_AFADE_FILTER 0
%define CONFIG_AFORMAT_FILTER 0
%define CONFIG_AINTERLEAVE_FILTER 0
%define CONFIG_ALLPASS_FILTER 0
%define CONFIG_AMERGE_FILTER 0
%define CONFIG_AMIX_FILTER 0
%define CONFIG_ANULL_FILTER 0
%define CONFIG_APAD_FILTER 0
%define CONFIG_APERMS_FILTER 0
%define CONFIG_APHASER_FILTER 0
%define CONFIG_ARESAMPLE_FILTER 0
%define CONFIG_ASELECT_FILTER 0
%define CONFIG_ASENDCMD_FILTER 0
%define CONFIG_ASETNSAMPLES_FILTER 0
%define CONFIG_ASETPTS_FILTER 0
%define CONFIG_ASETRATE_FILTER 0
%define CONFIG_ASETTB_FILTER 0
%define CONFIG_ASHOWINFO_FILTER 0
%define CONFIG_ASPLIT_FILTER 0
%define CONFIG_ASTREAMSYNC_FILTER 0
%define CONFIG_ASYNCTS_FILTER 0
%define CONFIG_ATEMPO_FILTER 0
%define CONFIG_BANDPASS_FILTER 0
%define CONFIG_BANDREJECT_FILTER 0
%define CONFIG_BASS_FILTER 0
%define CONFIG_BIQUAD_FILTER 0
%define CONFIG_CHANNELMAP_FILTER 0
%define CONFIG_CHANNELSPLIT_FILTER 0
%define CONFIG_EARWAX_FILTER 0
%define CONFIG_EBUR128_FILTER 0
%define CONFIG_EQUALIZER_FILTER 0
%define CONFIG_HIGHPASS_FILTER 0
%define CONFIG_JOIN_FILTER 0
%define CONFIG_LOWPASS_FILTER 0
%define CONFIG_PAN_FILTER 0
%define CONFIG_RESAMPLE_FILTER 0
%define CONFIG_SILENCEDETECT_FILTER 0
%define CONFIG_TREBLE_FILTER 0
%define CONFIG_VOLUME_FILTER 0
%define CONFIG_VOLUMEDETECT_FILTER 0
%define CONFIG_AEVALSRC_FILTER 0
%define CONFIG_ANULLSRC_FILTER 0
%define CONFIG_FLITE_FILTER 0
%define CONFIG_SINE_FILTER 0
%define CONFIG_ANULLSINK_FILTER 0
%define CONFIG_ALPHAEXTRACT_FILTER 0
%define CONFIG_ALPHAMERGE_FILTER 0
%define CONFIG_ASS_FILTER 0
%define CONFIG_BBOX_FILTER 0
%define CONFIG_BLACKDETECT_FILTER 0
%define CONFIG_BLACKFRAME_FILTER 0
%define CONFIG_BLEND_FILTER 0
%define CONFIG_BOXBLUR_FILTER 0
%define CONFIG_COLORBALANCE_FILTER 0
%define CONFIG_COLORCHANNELMIXER_FILTER 0
%define CONFIG_COLORMATRIX_FILTER 0
%define CONFIG_COPY_FILTER 0
%define CONFIG_CROP_FILTER 0
%define CONFIG_CROPDETECT_FILTER 0
%define CONFIG_CURVES_FILTER 0
%define CONFIG_DECIMATE_FILTER 0
%define CONFIG_DELOGO_FILTER 0
%define CONFIG_DESHAKE_FILTER 0
%define CONFIG_DRAWBOX_FILTER 0
%define CONFIG_DRAWTEXT_FILTER 0
%define CONFIG_EDGEDETECT_FILTER 0
%define CONFIG_FADE_FILTER 0
%define CONFIG_FIELD_FILTER 0
%define CONFIG_FIELDMATCH_FILTER 0
%define CONFIG_FIELDORDER_FILTER 0
%define CONFIG_FORMAT_FILTER 0
%define CONFIG_FPS_FILTER 0
%define CONFIG_FRAMESTEP_FILTER 0
%define CONFIG_FREI0R_FILTER 0
%define CONFIG_GEQ_FILTER 0
%define CONFIG_GRADFUN_FILTER 0
%define CONFIG_HFLIP_FILTER 0
%define CONFIG_HISTEQ_FILTER 0
%define CONFIG_HISTOGRAM_FILTER 0
%define CONFIG_HQDN3D_FILTER 0
%define CONFIG_HUE_FILTER 0
%define CONFIG_IDET_FILTER 0
%define CONFIG_IL_FILTER 0
%define CONFIG_INTERLACE_FILTER 0
%define CONFIG_INTERLEAVE_FILTER 0
%define CONFIG_KERNDEINT_FILTER 0
%define CONFIG_LUT_FILTER 0
%define CONFIG_LUTRGB_FILTER 0
%define CONFIG_LUTYUV_FILTER 0
%define CONFIG_MP_FILTER 0
%define CONFIG_MPDECIMATE_FILTER 0
%define CONFIG_NEGATE_FILTER 0
%define CONFIG_NOFORMAT_FILTER 0
%define CONFIG_NOISE_FILTER 0
%define CONFIG_NULL_FILTER 0
%define CONFIG_OCV_FILTER 0
%define CONFIG_OVERLAY_FILTER 0
%define CONFIG_PAD_FILTER 0
%define CONFIG_PERMS_FILTER 0
%define CONFIG_PIXDESCTEST_FILTER 0
%define CONFIG_PP_FILTER 0
%define CONFIG_REMOVELOGO_FILTER 0
%define CONFIG_SCALE_FILTER 0
%define CONFIG_SELECT_FILTER 0
%define CONFIG_SENDCMD_FILTER 0
%define CONFIG_SEPARATEFIELDS_FILTER 0
%define CONFIG_SETDAR_FILTER 0
%define CONFIG_SETFIELD_FILTER 0
%define CONFIG_SETPTS_FILTER 0
%define CONFIG_SETSAR_FILTER 0
%define CONFIG_SETTB_FILTER 0
%define CONFIG_SHOWINFO_FILTER 0
%define CONFIG_SMARTBLUR_FILTER 0
%define CONFIG_SPLIT_FILTER 0
%define CONFIG_STEREO3D_FILTER 0
%define CONFIG_SUBTITLES_FILTER 0
%define CONFIG_SUPER2XSAI_FILTER 0
%define CONFIG_SWAPUV_FILTER 0
%define CONFIG_TELECINE_FILTER 0
%define CONFIG_THUMBNAIL_FILTER 0
%define CONFIG_TILE_FILTER 0
%define CONFIG_TINTERLACE_FILTER 0
%define CONFIG_TRANSPOSE_FILTER 0
%define CONFIG_UNSHARP_FILTER 0
%define CONFIG_VFLIP_FILTER 0
%define CONFIG_VIDSTABDETECT_FILTER 0
%define CONFIG_VIDSTABTRANSFORM_FILTER 0
%define CONFIG_YADIF_FILTER 0
%define CONFIG_CELLAUTO_FILTER 0
%define CONFIG_COLOR_FILTER 0
%define CONFIG_FREI0R_SRC_FILTER 0
%define CONFIG_LIFE_FILTER 0
%define CONFIG_MANDELBROT_FILTER 0
%define CONFIG_MPTESTSRC_FILTER 0
%define CONFIG_NULLSRC_FILTER 0
%define CONFIG_RGBTESTSRC_FILTER 0
%define CONFIG_SMPTEBARS_FILTER 0
%define CONFIG_SMPTEHDBARS_FILTER 0
%define CONFIG_TESTSRC_FILTER 0
%define CONFIG_NULLSINK_FILTER 0
%define CONFIG_CONCAT_FILTER 0
%define CONFIG_SHOWSPECTRUM_FILTER 0
%define CONFIG_SHOWWAVES_FILTER 0
%define CONFIG_AMOVIE_FILTER 0
%define CONFIG_MOVIE_FILTER 0
%define CONFIG_H263_VAAPI_HWACCEL 0
%define CONFIG_H263_VDPAU_HWACCEL 0
%define CONFIG_H264_DXVA2_HWACCEL 0
%define CONFIG_H264_VAAPI_HWACCEL 0
%define CONFIG_H264_VDA_HWACCEL 0
%define CONFIG_H264_VDPAU_HWACCEL 0
%define CONFIG_MPEG1_VDPAU_HWACCEL 0
%define CONFIG_MPEG2_DXVA2_HWACCEL 0
%define CONFIG_MPEG2_VAAPI_HWACCEL 0
%define CONFIG_MPEG2_VDPAU_HWACCEL 0
%define CONFIG_MPEG4_VAAPI_HWACCEL 0
%define CONFIG_MPEG4_VDPAU_HWACCEL 0
%define CONFIG_VC1_DXVA2_HWACCEL 0
%define CONFIG_VC1_VAAPI_HWACCEL 0
%define CONFIG_VC1_VDPAU_HWACCEL 0
%define CONFIG_WMV3_DXVA2_HWACCEL 0
%define CONFIG_WMV3_VAAPI_HWACCEL 0
%define CONFIG_WMV3_VDPAU_HWACCEL 0
%define CONFIG_ALSA_INDEV 0
%define CONFIG_BKTR_INDEV 0
%define CONFIG_DSHOW_INDEV 0
%define CONFIG_DV1394_INDEV 0
%define CONFIG_FBDEV_INDEV 0
%define CONFIG_IEC61883_INDEV 0
%define CONFIG_JACK_INDEV 0
%define CONFIG_LAVFI_INDEV 0
%define CONFIG_OPENAL_INDEV 0
%define CONFIG_OSS_INDEV 0
%define CONFIG_PULSE_INDEV 0
%define CONFIG_SNDIO_INDEV 0
%define CONFIG_V4L2_INDEV 0
%define CONFIG_VFWCAP_INDEV 0
%define CONFIG_X11GRAB_INDEV 0
%define CONFIG_LIBCDIO_INDEV 0
%define CONFIG_LIBDC1394_INDEV 0
%define CONFIG_A64_MUXER 0
%define CONFIG_AC3_MUXER 0
%define CONFIG_ADTS_MUXER 0
%define CONFIG_ADX_MUXER 0
%define CONFIG_AIFF_MUXER 0
%define CONFIG_AMR_MUXER 0
%define CONFIG_ASF_MUXER 0
%define CONFIG_ASS_MUXER 0
%define CONFIG_AST_MUXER 0
%define CONFIG_ASF_STREAM_MUXER 0
%define CONFIG_AU_MUXER 0
%define CONFIG_AVI_MUXER 0
%define CONFIG_AVM2_MUXER 0
%define CONFIG_BIT_MUXER 0
%define CONFIG_CAF_MUXER 0
%define CONFIG_CAVSVIDEO_MUXER 0
%define CONFIG_CRC_MUXER 0
%define CONFIG_DAUD_MUXER 0
%define CONFIG_DIRAC_MUXER 0
%define CONFIG_DNXHD_MUXER 0
%define CONFIG_DTS_MUXER 0
%define CONFIG_DV_MUXER 0
%define CONFIG_EAC3_MUXER 0
%define CONFIG_F4V_MUXER 0
%define CONFIG_FFM_MUXER 0
%define CONFIG_FFMETADATA_MUXER 0
%define CONFIG_FILMSTRIP_MUXER 0
%define CONFIG_FLAC_MUXER 0
%define CONFIG_FLV_MUXER 0
%define CONFIG_FRAMECRC_MUXER 0
%define CONFIG_FRAMEMD5_MUXER 0
%define CONFIG_G722_MUXER 0
%define CONFIG_G723_1_MUXER 0
%define CONFIG_GIF_MUXER 0
%define CONFIG_GXF_MUXER 0
%define CONFIG_H261_MUXER 0
%define CONFIG_H263_MUXER 0
%define CONFIG_H264_MUXER 0
%define CONFIG_HLS_MUXER 0
%define CONFIG_ICO_MUXER 0
%define CONFIG_ILBC_MUXER 0
%define CONFIG_IMAGE2_MUXER 0
%define CONFIG_IMAGE2PIPE_MUXER 0
%define CONFIG_IPOD_MUXER 0
%define CONFIG_IRCAM_MUXER 0
%define CONFIG_ISMV_MUXER 0
%define CONFIG_IVF_MUXER 0
%define CONFIG_JACOSUB_MUXER 0
%define CONFIG_LATM_MUXER 0
%define CONFIG_M4V_MUXER 0
%define CONFIG_MD5_MUXER 0
%define CONFIG_MATROSKA_MUXER 0
%define CONFIG_MATROSKA_AUDIO_MUXER 0
%define CONFIG_MICRODVD_MUXER 0
%define CONFIG_MJPEG_MUXER 0
%define CONFIG_MLP_MUXER 0
%define CONFIG_MMF_MUXER 0
%define CONFIG_MOV_MUXER 0
%define CONFIG_MP2_MUXER 0
%define CONFIG_MP3_MUXER 0
%define CONFIG_MP4_MUXER 0
%define CONFIG_MPEG1SYSTEM_MUXER 0
%define CONFIG_MPEG1VCD_MUXER 0
%define CONFIG_MPEG1VIDEO_MUXER 0
%define CONFIG_MPEG2DVD_MUXER 0
%define CONFIG_MPEG2SVCD_MUXER 0
%define CONFIG_MPEG2VIDEO_MUXER 0
%define CONFIG_MPEG2VOB_MUXER 0
%define CONFIG_MPEGTS_MUXER 0
%define CONFIG_MPJPEG_MUXER 0
%define CONFIG_MXF_MUXER 0
%define CONFIG_MXF_D10_MUXER 0
%define CONFIG_NULL_MUXER 0
%define CONFIG_NUT_MUXER 0
%define CONFIG_OGG_MUXER 0
%define CONFIG_OMA_MUXER 0
%define CONFIG_PCM_ALAW_MUXER 0
%define CONFIG_PCM_MULAW_MUXER 0
%define CONFIG_PCM_F64BE_MUXER 0
%define CONFIG_PCM_F64LE_MUXER 0
%define CONFIG_PCM_F32BE_MUXER 0
%define CONFIG_PCM_F32LE_MUXER 0
%define CONFIG_PCM_S32BE_MUXER 0
%define CONFIG_PCM_S32LE_MUXER 0
%define CONFIG_PCM_S24BE_MUXER 0
%define CONFIG_PCM_S24LE_MUXER 0
%define CONFIG_PCM_S16BE_MUXER 0
%define CONFIG_PCM_S16LE_MUXER 0
%define CONFIG_PCM_S8_MUXER 0
%define CONFIG_PCM_U32BE_MUXER 0
%define CONFIG_PCM_U32LE_MUXER 0
%define CONFIG_PCM_U24BE_MUXER 0
%define CONFIG_PCM_U24LE_MUXER 0
%define CONFIG_PCM_U16BE_MUXER 0
%define CONFIG_PCM_U16LE_MUXER 0
%define CONFIG_PCM_U8_MUXER 0
%define CONFIG_PSP_MUXER 0
%define CONFIG_RAWVIDEO_MUXER 0
%define CONFIG_RM_MUXER 0
%define CONFIG_ROQ_MUXER 0
%define CONFIG_RSO_MUXER 0
%define CONFIG_RTP_MUXER 0
%define CONFIG_RTSP_MUXER 0
%define CONFIG_SAP_MUXER 0
%define CONFIG_SEGMENT_MUXER 0
%define CONFIG_STREAM_SEGMENT_MUXER 0
%define CONFIG_SMJPEG_MUXER 0
%define CONFIG_SMOOTHSTREAMING_MUXER 0
%define CONFIG_SOX_MUXER 0
%define CONFIG_SPDIF_MUXER 0
%define CONFIG_SRT_MUXER 0
%define CONFIG_SWF_MUXER 0
%define CONFIG_TEE_MUXER 0
%define CONFIG_TG2_MUXER 0
%define CONFIG_TGP_MUXER 0
%define CONFIG_MKVTIMESTAMP_V2_MUXER 0
%define CONFIG_TRUEHD_MUXER 0
%define CONFIG_VC1_MUXER 0
%define CONFIG_VC1T_MUXER 0
%define CONFIG_VOC_MUXER 0
%define CONFIG_W64_MUXER 0
%define CONFIG_WAV_MUXER 0
%define CONFIG_WEBM_MUXER 0
%define CONFIG_WTV_MUXER 0
%define CONFIG_WV_MUXER 0
%define CONFIG_YUV4MPEGPIPE_MUXER 0
%define CONFIG_LIBNUT_MUXER 0
%define CONFIG_ALSA_OUTDEV 0
%define CONFIG_CACA_OUTDEV 0
%define CONFIG_OSS_OUTDEV 0
%define CONFIG_SDL_OUTDEV 0
%define CONFIG_SNDIO_OUTDEV 0
%define CONFIG_AAC_PARSER 0
%define CONFIG_AAC_LATM_PARSER 0
%define CONFIG_AC3_PARSER 0
%define CONFIG_ADX_PARSER 0
%define CONFIG_BMP_PARSER 0
%define CONFIG_CAVSVIDEO_PARSER 0
%define CONFIG_COOK_PARSER 0
%define CONFIG_DCA_PARSER 0
%define CONFIG_DIRAC_PARSER 0
%define CONFIG_DNXHD_PARSER 0
%define CONFIG_DVBSUB_PARSER 0
%define CONFIG_DVDSUB_PARSER 0
%define CONFIG_DVD_NAV_PARSER 0
%define CONFIG_FLAC_PARSER 0
%define CONFIG_GSM_PARSER 0
%define CONFIG_H261_PARSER 0
%define CONFIG_H263_PARSER 0
%define CONFIG_H264_PARSER 0
%define CONFIG_MJPEG_PARSER 0
%define CONFIG_MLP_PARSER 0
%define CONFIG_MPEG4VIDEO_PARSER 0
%define CONFIG_MPEGAUDIO_PARSER 0
%define CONFIG_MPEGVIDEO_PARSER 0
%define CONFIG_PNG_PARSER 0
%define CONFIG_PNM_PARSER 0
%define CONFIG_RV30_PARSER 0
%define CONFIG_RV40_PARSER 0
%define CONFIG_TAK_PARSER 0
%define CONFIG_VC1_PARSER 0
%define CONFIG_VORBIS_PARSER 1
%define CONFIG_VP3_PARSER 1
%define CONFIG_VP8_PARSER 1
%define CONFIG_BLURAY_PROTOCOL 0
%define CONFIG_CACHE_PROTOCOL 0
%define CONFIG_CONCAT_PROTOCOL 0
%define CONFIG_CRYPTO_PROTOCOL 0
%define CONFIG_DATA_PROTOCOL 0
%define CONFIG_FFRTMPCRYPT_PROTOCOL 0
%define CONFIG_FFRTMPHTTP_PROTOCOL 0
%define CONFIG_FILE_PROTOCOL 0
%define CONFIG_GOPHER_PROTOCOL 0
%define CONFIG_HLS_PROTOCOL 0
%define CONFIG_HTTP_PROTOCOL 0
%define CONFIG_HTTPPROXY_PROTOCOL 0
%define CONFIG_HTTPS_PROTOCOL 0
%define CONFIG_MMSH_PROTOCOL 0
%define CONFIG_MMST_PROTOCOL 0
%define CONFIG_MD5_PROTOCOL 0
%define CONFIG_PIPE_PROTOCOL 0
%define CONFIG_RTMP_PROTOCOL 0
%define CONFIG_RTMPE_PROTOCOL 0
%define CONFIG_RTMPS_PROTOCOL 0
%define CONFIG_RTMPT_PROTOCOL 0
%define CONFIG_RTMPTE_PROTOCOL 0
%define CONFIG_RTMPTS_PROTOCOL 0
%define CONFIG_RTP_PROTOCOL 0
%define CONFIG_SCTP_PROTOCOL 0
%define CONFIG_SRTP_PROTOCOL 0
%define CONFIG_TCP_PROTOCOL 0
%define CONFIG_TLS_PROTOCOL 0
%define CONFIG_UDP_PROTOCOL 0
%define CONFIG_LIBRTMP_PROTOCOL 0
%define CONFIG_LIBRTMPE_PROTOCOL 0
%define CONFIG_LIBRTMPS_PROTOCOL 0
%define CONFIG_LIBRTMPT_PROTOCOL 0
%define CONFIG_LIBRTMPTE_PROTOCOL 0
| espadrine/opera | chromium/src/third_party/ffmpeg/chromium/config/Chromium/linux/ia32/config.asm | Assembly | bsd-3-clause | 46,983 |
g(): # @g()
push rax
call qword ptr [rip + _ZN3foo3bazE+8]
xor eax, eax
pop rcx
ret | mattgodbolt/compiler-explorer | test/demangle-cases/bug-1468e.asm | Assembly | bsd-2-clause | 170 |
INCLUDE kxarm.h
area js_msvc, code, readonly
MACRO
FUNC_HEADER $Name
FuncName SETS VBar:CC:"$Name":CC:VBar
PrologName SETS VBar:CC:"$Name":CC:"_Prolog":CC:VBar
FuncEndName SETS VBar:CC:"$Name":CC:"_end":CC:VBar
AREA |.pdata|,ALIGN=2,PDATA
DCD $FuncName
DCD (($PrologName-$FuncName)/4) :OR: ((($FuncEndName-$FuncName)/4):SHL:8) :OR: 0x40000000
AREA $AreaName,CODE,READONLY
ALIGN 2
GLOBAL $FuncName
EXPORT $FuncName
$FuncName
ROUT
$PrologName
MEND
;; -------- Functions to test processor features.
export js_arm_try_thumb_op
export js_arm_try_armv6t2_op
export js_arm_try_armv7_op
export js_arm_try_armv6_op
export js_arm_try_armv5_op
export js_arm_try_vfp_op
;; Test for Thumb support.
FUNC_HEADER js_arm_try_thumb_op
bx lr
mov pc, lr
ENTRY_END
endp
;; I'm not smart enough to figure out which flags to pass to armasm to get it
;; to understand movt and fmdrr/vmov; the disassembler figures them out just fine!
;; Test for Thumb2 support.
FUNC_HEADER js_arm_try_armv6t2_op
;; movt r0,#0xFFFF
DCD 0xE34F0FFF
mov pc,lr
ENTRY_END
endp
;; Test for VFP support.
FUNC_HEADER js_arm_try_vfp_op
;; fmdrr d0, r0, r1
DCD 0xEC410B10
mov pc,lr
ENTRY_END
endp
;; Tests for each architecture version.
FUNC_HEADER js_arm_try_armv7_op
;; pli pc, #0
DCD 0xF45FF000
mov pc, lr
ENTRY_END
endp
FUNC_HEADER js_arm_try_armv6_op
;; rev ip, ip
DCD 0xE6BFCF3C
mov pc, lr
ENTRY_END
endp
FUNC_HEADER js_arm_try_armv5_op
;; clz ip, ip
DCD 0xE16FCF1C
mov pc, lr
ENTRY_END
endp
;; --------
end
| glycerine/vj | src/js-1.8.5/js/src/jswince.asm | Assembly | apache-2.0 | 1,748 |
; Copyright © 2018, VideoLAN and dav1d authors
; Copyright © 2018, Two Orioles, LLC
; Copyright © 2018, VideoLabs
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "ext/x86/x86inc.asm"
SECTION_RODATA 16
; dav1d_obmc_masks[] with 64-x interleaved
obmc_masks: db 0, 0, 0, 0
; 2 @4
db 45, 19, 64, 0
; 4 @8
db 39, 25, 50, 14, 59, 5, 64, 0
; 8 @16
db 36, 28, 42, 22, 48, 16, 53, 11, 57, 7, 61, 3, 64, 0, 64, 0
; 16 @32
db 34, 30, 37, 27, 40, 24, 43, 21, 46, 18, 49, 15, 52, 12, 54, 10
db 56, 8, 58, 6, 60, 4, 61, 3, 64, 0, 64, 0, 64, 0, 64, 0
; 32 @64
db 33, 31, 35, 29, 36, 28, 38, 26, 40, 24, 41, 23, 43, 21, 44, 20
db 45, 19, 47, 17, 48, 16, 50, 14, 51, 13, 52, 12, 53, 11, 55, 9
db 56, 8, 57, 7, 58, 6, 59, 5, 60, 4, 60, 4, 61, 3, 62, 2
warp_8x8_shufA: db 0, 2, 4, 6, 1, 3, 5, 7, 1, 3, 5, 7, 2, 4, 6, 8
warp_8x8_shufB: db 4, 6, 8, 10, 5, 7, 9, 11, 5, 7, 9, 11, 6, 8, 10, 12
warp_8x8_shufC: db 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9, 4, 6, 8, 10
warp_8x8_shufD: db 6, 8, 10, 12, 7, 9, 11, 13, 7, 9, 11, 13, 8, 10, 12, 14
blend_shuf: db 0, 1, 0, 1, 0, 1, 0, 1, 2, 3, 2, 3, 2, 3, 2, 3
subpel_h_shuf4: db 0, 1, 2, 3, 1, 2, 3, 4, 8, 9, 10, 11, 9, 10, 11, 12
db 2, 3, 4, 5, 3, 4, 5, 6, 10, 11, 12, 13, 11, 12, 13, 14
subpel_h_shufA: db 0, 1, 2, 3, 1, 2, 3, 4, 2, 3, 4, 5, 3, 4, 5, 6
subpel_h_shufB: db 4, 5, 6, 7, 5, 6, 7, 8, 6, 7, 8, 9, 7, 8, 9, 10
subpel_h_shufC: db 8, 9, 10, 11, 9, 10, 11, 12, 10, 11, 12, 13, 11, 12, 13, 14
bilin_h_shuf4: db 1, 0, 2, 1, 3, 2, 4, 3, 9, 8, 10, 9, 11, 10, 12, 11
bilin_h_shuf8: db 1, 0, 2, 1, 3, 2, 4, 3, 5, 4, 6, 5, 7, 6, 8, 7
pb_64: times 16 db 64
pw_8: times 8 dw 8
pw_26: times 8 dw 26
pw_34: times 8 dw 34
pw_512: times 8 dw 512
pw_1024: times 8 dw 1024
pw_2048: times 8 dw 2048
pw_6903: times 8 dw 6903
pw_8192: times 8 dw 8192
pd_32: times 4 dd 32
pd_512: times 4 dd 512
pd_16384: times 4 dd 16484
pd_32768: times 4 dd 32768
pd_262144:times 4 dd 262144
pw_258: times 2 dw 258
cextern mc_subpel_filters
%define subpel_filters (mangle(private_prefix %+ _mc_subpel_filters)-8)
%macro BIDIR_JMP_TABLE 1-*
;evaluated at definition time (in loop below)
%xdefine %1_table (%%table - 2*%2)
%xdefine %%base %1_table
%xdefine %%prefix mangle(private_prefix %+ _%1)
; dynamically generated label
%%table:
%rep %0 - 1 ; repeat for num args
dd %%prefix %+ .w%2 - %%base
%rotate 1
%endrep
%endmacro
BIDIR_JMP_TABLE avg_ssse3, 4, 8, 16, 32, 64, 128
BIDIR_JMP_TABLE w_avg_ssse3, 4, 8, 16, 32, 64, 128
BIDIR_JMP_TABLE mask_ssse3, 4, 8, 16, 32, 64, 128
BIDIR_JMP_TABLE w_mask_420_ssse3, 4, 8, 16, 16, 16, 16
BIDIR_JMP_TABLE blend_ssse3, 4, 8, 16, 32
BIDIR_JMP_TABLE blend_v_ssse3, 2, 4, 8, 16, 32
BIDIR_JMP_TABLE blend_h_ssse3, 2, 4, 8, 16, 16, 16, 16
%macro BASE_JMP_TABLE 3-*
%xdefine %1_%2_table (%%table - %3)
%xdefine %%base %1_%2
%%table:
%rep %0 - 2
dw %%base %+ _w%3 - %%base
%rotate 1
%endrep
%endmacro
%xdefine put_ssse3 mangle(private_prefix %+ _put_bilin_ssse3.put)
%xdefine prep_ssse3 mangle(private_prefix %+ _prep_bilin_ssse3.prep)
BASE_JMP_TABLE put, ssse3, 2, 4, 8, 16, 32, 64, 128
BASE_JMP_TABLE prep, ssse3, 4, 8, 16, 32, 64, 128
%macro HV_JMP_TABLE 5-*
%xdefine %%prefix mangle(private_prefix %+ _%1_%2_%3)
%xdefine %%base %1_%3
%assign %%types %4
%if %%types & 1
%xdefine %1_%2_h_%3_table (%%h - %5)
%%h:
%rep %0 - 4
dw %%prefix %+ .h_w%5 - %%base
%rotate 1
%endrep
%rotate 4
%endif
%if %%types & 2
%xdefine %1_%2_v_%3_table (%%v - %5)
%%v:
%rep %0 - 4
dw %%prefix %+ .v_w%5 - %%base
%rotate 1
%endrep
%rotate 4
%endif
%if %%types & 4
%xdefine %1_%2_hv_%3_table (%%hv - %5)
%%hv:
%rep %0 - 4
dw %%prefix %+ .hv_w%5 - %%base
%rotate 1
%endrep
%endif
%endmacro
HV_JMP_TABLE put, 8tap, ssse3, 3, 2, 4, 8, 16, 32, 64, 128
HV_JMP_TABLE prep, 8tap, ssse3, 1, 4, 8, 16, 32, 64, 128
HV_JMP_TABLE put, bilin, ssse3, 7, 2, 4, 8, 16, 32, 64, 128
HV_JMP_TABLE prep, bilin, ssse3, 7, 4, 8, 16, 32, 64, 128
%define table_offset(type, fn) type %+ fn %+ SUFFIX %+ _table - type %+ SUFFIX
cextern mc_warp_filter
SECTION .text
INIT_XMM ssse3
%if ARCH_X86_32
DECLARE_REG_TMP 1
%define base t0-put_ssse3
%else
DECLARE_REG_TMP 7
%define base 0
%endif
;
%macro RESTORE_DSQ_32 1
%if ARCH_X86_32
mov %1, dsm ; restore dsq
%endif
%endmacro
;
cglobal put_bilin, 4, 8, 0, dst, ds, src, ss, w, h, mxy, bak
movifnidn mxyd, r6m ; mx
LEA t0, put_ssse3
tzcnt wd, wm
mov hd, hm
test mxyd, mxyd
jnz .h
mov mxyd, r7m ; my
test mxyd, mxyd
jnz .v
.put:
movzx wd, word [t0+wq*2+table_offset(put,)]
add wq, t0
RESTORE_DSQ_32 t0
jmp wq
.put_w2:
movzx r4d, word [srcq+ssq*0]
movzx r6d, word [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
mov [dstq+dsq*0], r4w
mov [dstq+dsq*1], r6w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .put_w2
RET
.put_w4:
mov r4d, [srcq+ssq*0]
mov r6d, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
mov [dstq+dsq*0], r4d
mov [dstq+dsq*1], r6d
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .put_w4
RET
.put_w8:
movq m0, [srcq+ssq*0]
movq m1, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
movq [dstq+dsq*0], m0
movq [dstq+dsq*1], m1
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .put_w8
RET
.put_w16:
movu m0, [srcq+ssq*0]
movu m1, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
mova [dstq+dsq*0], m0
mova [dstq+dsq*1], m1
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .put_w16
RET
.put_w32:
movu m0, [srcq+ssq*0+16*0]
movu m1, [srcq+ssq*0+16*1]
movu m2, [srcq+ssq*1+16*0]
movu m3, [srcq+ssq*1+16*1]
lea srcq, [srcq+ssq*2]
mova [dstq+dsq*0+16*0], m0
mova [dstq+dsq*0+16*1], m1
mova [dstq+dsq*1+16*0], m2
mova [dstq+dsq*1+16*1], m3
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .put_w32
RET
.put_w64:
movu m0, [srcq+16*0]
movu m1, [srcq+16*1]
movu m2, [srcq+16*2]
movu m3, [srcq+16*3]
add srcq, ssq
mova [dstq+16*0], m0
mova [dstq+16*1], m1
mova [dstq+16*2], m2
mova [dstq+16*3], m3
add dstq, dsq
dec hd
jg .put_w64
RET
.put_w128:
movu m0, [srcq+16*0]
movu m1, [srcq+16*1]
movu m2, [srcq+16*2]
movu m3, [srcq+16*3]
mova [dstq+16*0], m0
mova [dstq+16*1], m1
mova [dstq+16*2], m2
mova [dstq+16*3], m3
movu m0, [srcq+16*4]
movu m1, [srcq+16*5]
movu m2, [srcq+16*6]
movu m3, [srcq+16*7]
mova [dstq+16*4], m0
mova [dstq+16*5], m1
mova [dstq+16*6], m2
mova [dstq+16*7], m3
add srcq, ssq
add dstq, dsq
dec hd
jg .put_w128
RET
.h:
; (16 * src[x] + (mx * (src[x + 1] - src[x])) + 8) >> 4
; = ((16 - mx) * src[x] + mx * src[x + 1] + 8) >> 4
imul mxyd, 0xff01
mova m4, [base+bilin_h_shuf8]
mova m0, [base+bilin_h_shuf4]
add mxyd, 16 << 8
movd m5, mxyd
mov mxyd, r7m ; my
pshuflw m5, m5, q0000
punpcklqdq m5, m5
test mxyd, mxyd
jnz .hv
movzx wd, word [t0+wq*2+table_offset(put, _bilin_h)]
mova m3, [base+pw_2048]
add wq, t0
RESTORE_DSQ_32 t0
jmp wq
.h_w2:
pshufd m4, m4, q3120 ; m4 = {1, 0, 2, 1, 5, 4, 6, 5}
.h_w2_loop:
movd m0, [srcq+ssq*0]
movd m1, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
punpckldq m0, m1
pshufb m0, m4
pmaddubsw m0, m5
pmulhrsw m0, m3
packuswb m0, m0
movd r6d, m0
mov [dstq+dsq*0], r6w
shr r6d, 16
mov [dstq+dsq*1], r6w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .h_w2_loop
RET
.h_w4:
movq m4, [srcq+ssq*0]
movhps m4, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
pshufb m4, m0
pmaddubsw m4, m5
pmulhrsw m4, m3
packuswb m4, m4
movd [dstq+dsq*0], m4
psrlq m4, 32
movd [dstq+dsq*1], m4
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .h_w4
RET
.h_w8:
movu m0, [srcq+ssq*0]
movu m1, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmulhrsw m0, m3
pmulhrsw m1, m3
packuswb m0, m1
movq [dstq+dsq*0], m0
movhps [dstq+dsq*1], m0
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .h_w8
RET
.h_w16:
movu m0, [srcq+8*0]
movu m1, [srcq+8*1]
add srcq, ssq
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmulhrsw m0, m3
pmulhrsw m1, m3
packuswb m0, m1
mova [dstq], m0
add dstq, dsq
dec hd
jg .h_w16
RET
.h_w32:
movu m0, [srcq+mmsize*0+8*0]
movu m1, [srcq+mmsize*0+8*1]
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmulhrsw m0, m3
pmulhrsw m1, m3
packuswb m0, m1
movu m1, [srcq+mmsize*1+8*0]
movu m2, [srcq+mmsize*1+8*1]
add srcq, ssq
pshufb m1, m4
pshufb m2, m4
pmaddubsw m1, m5
pmaddubsw m2, m5
pmulhrsw m1, m3
pmulhrsw m2, m3
packuswb m1, m2
mova [dstq+16*0], m0
mova [dstq+16*1], m1
add dstq, dsq
dec hd
jg .h_w32
RET
.h_w64:
mov r6, -16*3
.h_w64_loop:
movu m0, [srcq+r6+16*3+8*0]
movu m1, [srcq+r6+16*3+8*1]
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmulhrsw m0, m3
pmulhrsw m1, m3
packuswb m0, m1
mova [dstq+r6+16*3], m0
add r6, 16
jle .h_w64_loop
add srcq, ssq
add dstq, dsq
dec hd
jg .h_w64
RET
.h_w128:
mov r6, -16*7
.h_w128_loop:
movu m0, [srcq+r6+16*7+8*0]
movu m1, [srcq+r6+16*7+8*1]
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmulhrsw m0, m3
pmulhrsw m1, m3
packuswb m0, m1
mova [dstq+r6+16*7], m0
add r6, 16
jle .h_w128_loop
add srcq, ssq
add dstq, dsq
dec hd
jg .h_w128
RET
.v:
movzx wd, word [t0+wq*2+table_offset(put, _bilin_v)]
imul mxyd, 0xff01
mova m5, [base+pw_2048]
add mxyd, 16 << 8
add wq, t0
movd m4, mxyd
pshuflw m4, m4, q0000
punpcklqdq m4, m4
RESTORE_DSQ_32 t0
jmp wq
.v_w2:
movd m0, [srcq+ssq*0]
.v_w2_loop:
pinsrw m0, [srcq+ssq*1], 1 ; 0 1
lea srcq, [srcq+ssq*2]
pshuflw m2, m0, q2301
pinsrw m0, [srcq+ssq*0], 0 ; 2 1
punpcklbw m1, m0, m2
pmaddubsw m1, m4
pmulhrsw m1, m5
packuswb m1, m1
movd r6d, m1
mov [dstq+dsq*1], r6w
shr r6d, 16
mov [dstq+dsq*0], r6w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .v_w2_loop
RET
.v_w4:
movd m0, [srcq+ssq*0]
.v_w4_loop:
movd m1, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
punpckldq m2, m0, m1 ; 0 1
movd m0, [srcq+ssq*0]
punpckldq m1, m0 ; 1 2
punpcklbw m1, m2
pmaddubsw m1, m4
pmulhrsw m1, m5
packuswb m1, m1
movd [dstq+dsq*0], m1
psrlq m1, 32
movd [dstq+dsq*1], m1
;
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .v_w4_loop
RET
.v_w8:
movq m0, [srcq+ssq*0]
.v_w8_loop:
movq m3, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
punpcklbw m1, m3, m0
movq m0, [srcq+ssq*0]
punpcklbw m2, m0, m3
pmaddubsw m1, m4
pmaddubsw m2, m4
pmulhrsw m1, m5
pmulhrsw m2, m5
packuswb m1, m2
movq [dstq+dsq*0], m1
movhps [dstq+dsq*1], m1
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .v_w8_loop
RET
;
%macro PUT_BILIN_V_W16 0
movu m0, [srcq+ssq*0]
%%loop:
movu m3, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
punpcklbw m1, m3, m0
punpckhbw m2, m3, m0
movu m0, [srcq+ssq*0]
pmaddubsw m1, m4
pmaddubsw m2, m4
pmulhrsw m1, m5
pmulhrsw m2, m5
packuswb m1, m2
mova [dstq+dsq*0], m1
punpcklbw m1, m0, m3
punpckhbw m2, m0, m3
pmaddubsw m1, m4
pmaddubsw m2, m4
pmulhrsw m1, m5
pmulhrsw m2, m5
packuswb m1, m2
mova [dstq+dsq*1], m1
lea dstq, [dstq+dsq*2]
sub hd, 2
jg %%loop
%endmacro
;
.v_w16:
PUT_BILIN_V_W16
RET
.v_w16gt:
mov r4, dstq
mov r6, srcq
.v_w16gt_loop:
%if ARCH_X86_32
mov bakm, t0q
RESTORE_DSQ_32 t0
PUT_BILIN_V_W16
mov t0q, bakm
%else
PUT_BILIN_V_W16
%endif
mov hw, t0w
add r4, mmsize
add r6, mmsize
mov dstq, r4
mov srcq, r6
sub t0d, 1<<16
jg .v_w16gt
RET
.v_w32:
lea t0d, [hq+(1<<16)]
jmp .v_w16gt
.v_w64:
lea t0d, [hq+(3<<16)]
jmp .v_w16gt
.v_w128:
lea t0d, [hq+(7<<16)]
jmp .v_w16gt
.hv:
; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 128) >> 8
; = (src[x] + ((my * (src[x + src_stride] - src[x])) >> 4) + 8) >> 4
movzx wd, word [t0+wq*2+table_offset(put, _bilin_hv)]
WIN64_SPILL_XMM 8
shl mxyd, 11 ; can't shift by 12 due to signed overflow
mova m7, [base+pw_2048]
movd m6, mxyd
add wq, t0
pshuflw m6, m6, q0000
punpcklqdq m6, m6
jmp wq
.hv_w2:
RESTORE_DSQ_32 t0
movd m0, [srcq+ssq*0]
pshufd m0, m0, q0000 ; src[x - src_stride]
pshufb m0, m4
pmaddubsw m0, m5
.hv_w2_loop:
movd m1, [srcq+ssq*1] ; src[x]
lea srcq, [srcq+ssq*2]
movhps m1, [srcq+ssq*0] ; src[x + src_stride]
pshufd m1, m1, q3120
pshufb m1, m4
pmaddubsw m1, m5 ; 1 _ 2 _
shufps m2, m0, m1, q1032 ; 0 _ 1 _
mova m0, m1
psubw m1, m2 ; src[x + src_stride] - src[x]
paddw m1, m1
pmulhw m1, m6 ; (my * (src[x + src_stride] - src[x])
paddw m1, m2 ; src[x] + (my * (src[x + src_stride] - src[x])
pmulhrsw m1, m7
packuswb m1, m1
%if ARCH_X86_64
movq r6, m1
%else
pshuflw m1, m1, q2020
movd r6d, m1
%endif
mov [dstq+dsq*0], r6w
shr r6, gprsize*4
mov [dstq+dsq*1], r6w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .hv_w2_loop
RET
.hv_w4:
mova m4, [base+bilin_h_shuf4]
RESTORE_DSQ_32 t0
movddup xm0, [srcq+ssq*0]
pshufb m0, m4
pmaddubsw m0, m5
.hv_w4_loop:
movq m1, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
movhps m1, [srcq+ssq*0]
pshufb m1, m4
pmaddubsw m1, m5 ; 1 2
shufps m2, m0, m1, q1032 ; 0 1
mova m0, m1
psubw m1, m2
paddw m1, m1
pmulhw m1, m6
paddw m1, m2
pmulhrsw m1, m7
packuswb m1, m1
movd [dstq+dsq*0], m1
psrlq m1, 32
movd [dstq+dsq*1], m1
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .hv_w4_loop
RET
.hv_w8:
RESTORE_DSQ_32 t0
movu m0, [srcq+ssq*0+8*0]
pshufb m0, m4
pmaddubsw m0, m5
.hv_w8_loop:
movu m2, [srcq+ssq*1+8*0]
lea srcq, [srcq+ssq*2]
pshufb m2, m4
pmaddubsw m2, m5
psubw m1, m2, m0
paddw m1, m1
pmulhw m1, m6
paddw m1, m0
movu m0, [srcq+ssq*0+8*0]
pshufb m0, m4
pmaddubsw m0, m5
psubw m3, m0, m2
paddw m3, m3
pmulhw m3, m6
paddw m3, m2
pmulhrsw m1, m7
pmulhrsw m3, m7
packuswb m1, m3
movq [dstq+dsq*0], m1
movhps [dstq+dsq*1], m1
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .hv_w8_loop
RET
.hv_w16:
xor t0d, t0d
.hv_w16gt:
mov r4, dstq
mov r6, srcq
%if WIN64
movaps r4m, xmm8
%endif
.hv_w16_loop0:
movu m0, [srcq+8*0]
movu m1, [srcq+8*1]
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
.hv_w16_loop:
%if ARCH_X86_32
%define m0tmp [dstq]
%else
%define m0tmp m8
%endif
add srcq, ssq
movu m2, [srcq+8*0]
movu m3, [srcq+8*1]
pshufb m2, m4
pshufb m3, m4
pmaddubsw m2, m5
pmaddubsw m3, m5
mova m0tmp, m2
psubw m2, m0
paddw m2, m2
pmulhw m2, m6
paddw m2, m0
mova m0, m3
psubw m3, m1
paddw m3, m3
pmulhw m3, m6
paddw m3, m1
mova m1, m0
mova m0, m0tmp
pmulhrsw m2, m7
pmulhrsw m3, m7
packuswb m2, m3
mova [dstq], m2
add dstq, dsmp
dec hd
jg .hv_w16_loop
movzx hd, t0w
add r4, mmsize
add r6, mmsize
mov dstq, r4
mov srcq, r6
sub t0d, 1<<16
jg .hv_w16_loop0
%if WIN64
movaps xmm8, r4m
%endif
RET
.hv_w32:
lea t0d, [hq+(1<<16)]
jmp .hv_w16gt
.hv_w64:
lea t0d, [hq+(3<<16)]
jmp .hv_w16gt
.hv_w128:
lea t0d, [hq+(7<<16)]
jmp .hv_w16gt
DECLARE_REG_TMP 3, 5, 6
%if ARCH_X86_32
%define base t2-prep_ssse3
%else
%define base 0
%endif
cglobal prep_bilin, 3, 7, 0, tmp, src, stride, w, h, mxy, stride3
movifnidn mxyd, r5m ; mx
LEA t2, prep_ssse3
tzcnt wd, wm
movifnidn hd, hm
test mxyd, mxyd
jnz .h
mov mxyd, r6m ; my
test mxyd, mxyd
jnz .v
.prep:
movzx wd, word [t2+wq*2+table_offset(prep,)]
add wq, t2
lea stride3q, [strideq*3]
jmp wq
.prep_w4:
movd m0, [srcq+strideq*0]
movd m1, [srcq+strideq*1]
movd m2, [srcq+strideq*2]
movd m3, [srcq+stride3q ]
punpckldq m0, m1
punpckldq m2, m3
lea srcq, [srcq+strideq*4]
pxor m1, m1
punpcklbw m0, m1
punpcklbw m2, m1
psllw m0, 4
psllw m2, 4
mova [tmpq+mmsize*0], m0
mova [tmpq+mmsize*1], m2
add tmpq, 32
sub hd, 4
jg .prep_w4
RET
.prep_w8:
movq m0, [srcq+strideq*0]
movq m1, [srcq+strideq*1]
movq m2, [srcq+strideq*2]
movq m3, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
pxor m4, m4
punpcklbw m0, m4
punpcklbw m1, m4
punpcklbw m2, m4
punpcklbw m3, m4
psllw m0, 4
psllw m1, 4
psllw m2, 4
psllw m3, 4
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
mova [tmpq+16*2], m2
mova [tmpq+16*3], m3
add tmpq, 16*4
sub hd, 4
jg .prep_w8
RET
.prep_w16:
movq m0, [srcq+strideq*0+8*0]
movq m1, [srcq+strideq*0+8*1]
movq m2, [srcq+strideq*1+8*0]
movq m3, [srcq+strideq*1+8*1]
lea srcq, [srcq+strideq*2]
pxor m4, m4
punpcklbw m0, m4
punpcklbw m1, m4
punpcklbw m2, m4
punpcklbw m3, m4
psllw m0, 4
psllw m1, 4
psllw m2, 4
psllw m3, 4
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
mova [tmpq+16*2], m2
mova [tmpq+16*3], m3
add tmpq, 16*4
sub hd, 2
jg .prep_w16
RET
.prep_w16gt:
mov t1q, srcq
mov r3q, t2q
.prep_w16gt_hloop:
movq m0, [t1q+8*0]
movq m1, [t1q+8*1]
movq m2, [t1q+8*2]
movq m3, [t1q+8*3]
pxor m4, m4
punpcklbw m0, m4
punpcklbw m1, m4
punpcklbw m2, m4
punpcklbw m3, m4
psllw m0, 4
psllw m1, 4
psllw m2, 4
psllw m3, 4
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
mova [tmpq+16*2], m2
mova [tmpq+16*3], m3
add tmpq, 16*4
add t1q, 32
sub r3q, 1
jg .prep_w16gt_hloop
lea srcq, [srcq+strideq]
sub hd, 1
jg .prep_w16gt
RET
.prep_w32:
mov t2q, 1
jmp .prep_w16gt
.prep_w64:
mov t2q, 2
jmp .prep_w16gt
.prep_w128:
mov t2q, 4
jmp .prep_w16gt
.h:
; 16 * src[x] + (mx * (src[x + 1] - src[x]))
; = (16 - mx) * src[x] + mx * src[x + 1]
imul mxyd, 0xff01
mova m4, [base+bilin_h_shuf8]
add mxyd, 16 << 8
movd xm5, mxyd
mov mxyd, r6m ; my
pshuflw m5, m5, q0000
punpcklqdq m5, m5
test mxyd, mxyd
jnz .hv
%if ARCH_X86_32
mov t1, t2 ; save base reg for w4
%endif
movzx wd, word [t2+wq*2+table_offset(prep, _bilin_h)]
add wq, t2
lea stride3q, [strideq*3]
jmp wq
.h_w4:
%if ARCH_X86_32
mova m4, [t1-prep_ssse3+bilin_h_shuf4]
%else
mova m4, [bilin_h_shuf4]
%endif
.h_w4_loop:
movq m0, [srcq+strideq*0]
movhps m0, [srcq+strideq*1]
movq m1, [srcq+strideq*2]
movhps m1, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
pshufb m0, m4
pmaddubsw m0, m5
pshufb m1, m4
pmaddubsw m1, m5
mova [tmpq+0 ], m0
mova [tmpq+16], m1
add tmpq, 32
sub hd, 4
jg .h_w4_loop
RET
.h_w8:
movu m0, [srcq+strideq*0]
movu m1, [srcq+strideq*1]
movu m2, [srcq+strideq*2]
movu m3, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
pshufb m0, m4
pshufb m1, m4
pshufb m2, m4
pshufb m3, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m3, m5
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
mova [tmpq+16*2], m2
mova [tmpq+16*3], m3
add tmpq, 16*4
sub hd, 4
jg .h_w8
RET
.h_w16:
movu m0, [srcq+strideq*0+8*0]
movu m1, [srcq+strideq*0+8*1]
movu m2, [srcq+strideq*1+8*0]
movu m3, [srcq+strideq*1+8*1]
lea srcq, [srcq+strideq*2]
pshufb m0, m4
pshufb m1, m4
pshufb m2, m4
pshufb m3, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m3, m5
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
mova [tmpq+16*2], m2
mova [tmpq+16*3], m3
add tmpq, 16*4
sub hd, 2
jg .h_w16
RET
.h_w16gt:
mov t1q, srcq
mov r3q, t2q
.h_w16gt_hloop:
movu m0, [t1q+8*0]
movu m1, [t1q+8*1]
movu m2, [t1q+8*2]
movu m3, [t1q+8*3]
pshufb m0, m4
pshufb m1, m4
pshufb m2, m4
pshufb m3, m4
pmaddubsw m0, m5
pmaddubsw m1, m5
pmaddubsw m2, m5
pmaddubsw m3, m5
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
mova [tmpq+16*2], m2
mova [tmpq+16*3], m3
add tmpq, 16*4
add t1q, 32
sub r3q, 1
jg .h_w16gt_hloop
lea srcq, [srcq+strideq]
sub hd, 1
jg .h_w16gt
RET
.h_w32:
mov t2q, 1
jmp .h_w16gt
.h_w64:
mov t2q, 2
jmp .h_w16gt
.h_w128:
mov t2q, 4
jmp .h_w16gt
.v:
movzx wd, word [t2+wq*2+table_offset(prep, _bilin_v)]
imul mxyd, 0xff01
add mxyd, 16 << 8
add wq, t2
lea stride3q, [strideq*3]
movd m5, mxyd
pshuflw m5, m5, q0000
punpcklqdq m5, m5
jmp wq
.v_w4:
movd m0, [srcq+strideq*0]
.v_w4_loop:
movd m1, [srcq+strideq*1]
movd m2, [srcq+strideq*2]
movd m3, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
punpcklwd m0, m1 ; 0 1 _ _
punpcklwd m1, m2 ; 1 2 _ _
punpcklbw m1, m0
pmaddubsw m1, m5
pshufd m1, m1, q3120
mova [tmpq+16*0], m1
movd m0, [srcq+strideq*0]
punpcklwd m2, m3 ; 2 3 _ _
punpcklwd m3, m0 ; 3 4 _ _
punpcklbw m3, m2
pmaddubsw m3, m5
pshufd m3, m3, q3120
mova [tmpq+16*1], m3
add tmpq, 32
sub hd, 4
jg .v_w4_loop
RET
.v_w8:
movq m0, [srcq+strideq*0]
.v_w8_loop:
movq m1, [srcq+strideq*2]
movq m2, [srcq+strideq*1]
movq m3, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
shufpd m4, m0, m1, 0x0c ; 0 2
movq m0, [srcq+strideq*0]
shufpd m2, m3, 0x0c ; 1 3
shufpd m1, m0, 0x0c ; 2 4
punpcklbw m3, m2, m4
pmaddubsw m3, m5
mova [tmpq+16*0], m3
punpckhbw m3, m2, m4
pmaddubsw m3, m5
mova [tmpq+16*2], m3
punpcklbw m3, m1, m2
punpckhbw m1, m2
pmaddubsw m3, m5
pmaddubsw m1, m5
mova [tmpq+16*1], m3
mova [tmpq+16*3], m1
add tmpq, 16*4
sub hd, 4
jg .v_w8_loop
RET
.v_w16:
movu m0, [srcq+strideq*0]
.v_w16_loop:
movu m1, [srcq+strideq*1]
movu m2, [srcq+strideq*2]
punpcklbw m3, m1, m0
punpckhbw m4, m1, m0
pmaddubsw m3, m5
pmaddubsw m4, m5
mova [tmpq+16*0], m3
mova [tmpq+16*1], m4
punpcklbw m3, m2, m1
punpckhbw m4, m2, m1
pmaddubsw m3, m5
pmaddubsw m4, m5
mova [tmpq+16*2], m3
mova [tmpq+16*3], m4
movu m3, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
movu m0, [srcq+strideq*0]
add tmpq, 16*8
punpcklbw m1, m3, m2
punpckhbw m4, m3, m2
pmaddubsw m1, m5
pmaddubsw m4, m5
mova [tmpq-16*4], m1
mova [tmpq-16*3], m4
punpcklbw m1, m0, m3
punpckhbw m2, m0, m3
pmaddubsw m1, m5
pmaddubsw m2, m5
mova [tmpq-16*2], m1
mova [tmpq-16*1], m2
sub hd, 4
jg .v_w16_loop
RET
.v_w32:
lea t2d, [hq+(0<<16)]
mov t0d, 64
.v_w32_start:
%if ARCH_X86_64
%if WIN64
PUSH r7
%endif
mov r7, tmpq
%endif
mov t1, srcq
.v_w32_loop_h:
movu m0, [srcq+strideq*0+16*0] ; 0L
movu m1, [srcq+strideq*0+16*1] ; 0U
.v_w32_loop_v:
movu m2, [srcq+strideq*1+16*0] ; 1L
movu m3, [srcq+strideq*1+16*1] ; 1U
lea srcq, [srcq+strideq*2]
punpcklbw m4, m2, m0
pmaddubsw m4, m5
mova [tmpq+16*0], m4
punpckhbw m4, m2, m0
pmaddubsw m4, m5
mova [tmpq+16*1], m4
punpcklbw m4, m3, m1
pmaddubsw m4, m5
mova [tmpq+16*2], m4
punpckhbw m4, m3, m1
pmaddubsw m4, m5
mova [tmpq+16*3], m4
add tmpq, t0q
movu m0, [srcq+strideq*0+16*0] ; 2L
movu m1, [srcq+strideq*0+16*1] ; 2U
punpcklbw m4, m0, m2
pmaddubsw m4, m5
mova [tmpq+16*0], m4
punpckhbw m4, m0, m2
pmaddubsw m4, m5
mova [tmpq+16*1], m4
punpcklbw m4, m1, m3
pmaddubsw m4, m5
mova [tmpq+16*2], m4
punpckhbw m4, m1, m3
pmaddubsw m4, m5
mova [tmpq+16*3], m4
add tmpq, t0q
sub hd, 2
jg .v_w32_loop_v
movzx hd, t2w
add t1, 32
mov srcq, t1
%if ARCH_X86_64
add r7, 2*16*2
mov tmpq, r7
%else
mov tmpq, tmpmp
add tmpq, 2*16*2
mov tmpmp, tmpq
%endif
sub t2d, 1<<16
jg .v_w32_loop_h
%if WIN64
POP r7
%endif
RET
.v_w64:
lea t2d, [hq+(1<<16)]
mov t0d, 128
jmp .v_w32_start
.v_w128:
lea t2d, [hq+(3<<16)]
mov t0d, 256
jmp .v_w32_start
.hv:
; (16 * src[x] + (my * (src[x + src_stride] - src[x])) + 8) >> 4
; = src[x] + (((my * (src[x + src_stride] - src[x])) + 8) >> 4)
%assign stack_offset stack_offset - stack_size_padded
WIN64_SPILL_XMM 8
movzx wd, word [t2+wq*2+table_offset(prep, _bilin_hv)]
shl mxyd, 11
movd xm6, mxyd
add wq, t2
pshuflw m6, m6, q0000
punpcklqdq m6, m6
%if ARCH_X86_32
mov t1, t2 ; save base reg for w4
%endif
lea stride3q, [strideq*3]
jmp wq
.hv_w4:
%if ARCH_X86_32
mova m4, [t1-prep_ssse3+bilin_h_shuf4]
%else
mova m4, [bilin_h_shuf4]
%endif
movq m0, [srcq+strideq*0] ; 0 _
punpcklqdq m0, m0
pshufb m0, m4
pmaddubsw m0, m5
.hv_w4_loop:
movq m1, [srcq+strideq*1]
movhps m1, [srcq+strideq*2] ; 1 _ 2 _
movq m2, [srcq+stride3q ]
lea srcq, [srcq+strideq*4]
movhps m2, [srcq+strideq*0] ; 3 _ 4 _
pshufb m1, m4
pshufb m2, m4
pmaddubsw m1, m5 ; 1 + 2 +
shufpd m3, m0, m1, 0x01 ; 0 + 1 +
pmaddubsw m0, m2, m5 ; 3 + 4 +
shufpd m2, m1, m0, 0x01 ; 2 + 3 +
psubw m1, m3
pmulhrsw m1, m6
paddw m1, m3
psubw m3, m0, m2
pmulhrsw m3, m6
paddw m3, m2
mova [tmpq+16*0], m1
mova [tmpq+16*1], m3
add tmpq, 32
sub hd, 4
jg .hv_w4_loop
RET
.hv_w8:
movu m0, [srcq+strideq*0]
pshufb m0, m4
pmaddubsw m0, m5 ; 0 +
.hv_w8_loop:
movu m1, [srcq+strideq*1] ; 1
movu m2, [srcq+strideq*2] ; 2
pshufb m1, m4
pshufb m2, m4
pmaddubsw m1, m5 ; 1 +
pmaddubsw m2, m5 ; 2 +
psubw m3, m1, m0 ; 1-0
pmulhrsw m3, m6
paddw m3, m0
psubw m7, m2, m1 ; 2-1
pmulhrsw m7, m6
paddw m7, m1
mova [tmpq+16*0], m3
mova [tmpq+16*1], m7
movu m1, [srcq+stride3q ] ; 3
lea srcq, [srcq+strideq*4]
movu m0, [srcq+strideq*0] ; 4
pshufb m1, m4
pshufb m0, m4
pmaddubsw m1, m5 ; 3 +
pmaddubsw m0, m5 ; 4 +
psubw m3, m1, m2 ; 3-2
pmulhrsw m3, m6
paddw m3, m2
psubw m7, m0, m1 ; 4-3
pmulhrsw m7, m6
paddw m7, m1
mova [tmpq+16*2], m3
mova [tmpq+16*3], m7
add tmpq, 16*4
sub hd, 4
jg .hv_w8_loop
RET
.hv_w16:
lea t2d, [hq+(0<<16)]
mov t0d, 32
.hv_w16_start:
%if ARCH_X86_64
%if WIN64
PUSH r7
%endif
mov r7, tmpq
%endif
mov t1, srcq
.hv_w16_loop_h:
movu m0, [srcq+strideq*0+8*0] ; 0L
movu m1, [srcq+strideq*0+8*1] ; 0U
pshufb m0, m4
pshufb m1, m4
pmaddubsw m0, m5 ; 0L +
pmaddubsw m1, m5 ; 0U +
.hv_w16_loop_v:
movu m2, [srcq+strideq*1+8*0] ; 1L
pshufb m2, m4
pmaddubsw m2, m5 ; 1L +
psubw m3, m2, m0 ; 1L-0L
pmulhrsw m3, m6
paddw m3, m0
mova [tmpq+16*0], m3
movu m3, [srcq+strideq*1+8*1] ; 1U
lea srcq, [srcq+strideq*2]
pshufb m3, m4
pmaddubsw m3, m5 ; 1U +
psubw m0, m3, m1 ; 1U-0U
pmulhrsw m0, m6
paddw m0, m1
mova [tmpq+16*1], m0
add tmpq, t0q
movu m0, [srcq+strideq*0+8*0] ; 2L
pshufb m0, m4
pmaddubsw m0, m5 ; 2L +
psubw m1, m0, m2 ; 2L-1L
pmulhrsw m1, m6
paddw m1, m2
mova [tmpq+16*0], m1
movu m1, [srcq+strideq*0+8*1] ; 2U
pshufb m1, m4
pmaddubsw m1, m5 ; 2U +
psubw m2, m1, m3 ; 2U-1U
pmulhrsw m2, m6
paddw m2, m3
mova [tmpq+16*1], m2
add tmpq, t0q
sub hd, 2
jg .hv_w16_loop_v
movzx hd, t2w
add t1, 16
mov srcq, t1
%if ARCH_X86_64
add r7, 2*16
mov tmpq, r7
%else
mov tmpq, tmpmp
add tmpq, 2*16
mov tmpmp, tmpq
%endif
sub t2d, 1<<16
jg .hv_w16_loop_h
%if WIN64
POP r7
%endif
RET
.hv_w32:
lea t2d, [hq+(1<<16)]
mov t0d, 64
jmp .hv_w16_start
.hv_w64:
lea t2d, [hq+(3<<16)]
mov t0d, 128
jmp .hv_w16_start
.hv_w128:
lea t2d, [hq+(7<<16)]
mov t0d, 256
jmp .hv_w16_start
; int8_t subpel_filters[5][15][8]
%assign FILTER_REGULAR (0*15 << 16) | 3*15
%assign FILTER_SMOOTH (1*15 << 16) | 4*15
%assign FILTER_SHARP (2*15 << 16) | 3*15
%if ARCH_X86_32
DECLARE_REG_TMP 1, 2
%elif WIN64
DECLARE_REG_TMP 4, 5
%else
DECLARE_REG_TMP 7, 8
%endif
%macro PUT_8TAP_FN 3 ; type, type_h, type_v
cglobal put_8tap_%1
mov t0d, FILTER_%2
mov t1d, FILTER_%3
%ifnidn %1, sharp_smooth ; skip the jump in the last filter
jmp mangle(private_prefix %+ _put_8tap %+ SUFFIX)
%endif
%endmacro
PUT_8TAP_FN regular, REGULAR, REGULAR
PUT_8TAP_FN regular_sharp, REGULAR, SHARP
PUT_8TAP_FN regular_smooth, REGULAR, SMOOTH
PUT_8TAP_FN smooth_regular, SMOOTH, REGULAR
PUT_8TAP_FN smooth, SMOOTH, SMOOTH
PUT_8TAP_FN smooth_sharp, SMOOTH, SHARP
PUT_8TAP_FN sharp_regular, SHARP, REGULAR
PUT_8TAP_FN sharp, SHARP, SHARP
PUT_8TAP_FN sharp_smooth, SHARP, SMOOTH
%if ARCH_X86_32
%define base_reg r1
%define base base_reg-put_ssse3
%define W32_RESTORE_DSQ mov dsq, dsm
%define W32_RESTORE_SSQ mov ssq, ssm
%else
%define base_reg r8
%define base 0
%define W32_RESTORE_DSQ
%define W32_RESTORE_SSQ
%endif
cglobal put_8tap, 1, 9, 0, dst, ds, src, ss, w, h, mx, my, ss3
%assign org_stack_offset stack_offset
imul mxd, mxm, 0x010101
add mxd, t0d ; 8tap_h, mx, 4tap_h
%if ARCH_X86_64
imul myd, mym, 0x010101
add myd, t1d ; 8tap_v, my, 4tap_v
%else
imul ssd, mym, 0x010101
add ssd, t1d ; 8tap_v, my, 4tap_v
mov srcq, srcm
%endif
mov wd, wm
movifnidn hd, hm
LEA base_reg, put_ssse3
test mxd, 0xf00
jnz .h
%if ARCH_X86_32
test ssd, 0xf00
%else
test myd, 0xf00
%endif
jnz .v
tzcnt wd, wd
movzx wd, word [base_reg+wq*2+table_offset(put,)]
add wq, base_reg
; put_bilin mangling jump
%assign stack_offset org_stack_offset
%if ARCH_X86_32
mov dsq, dsm
mov ssq, ssm
%elif WIN64
pop r8
%endif
lea r6, [ssq*3]
jmp wq
.h:
%if ARCH_X86_32
test ssd, 0xf00
%else
test myd, 0xf00
%endif
jnz .hv
W32_RESTORE_SSQ
WIN64_SPILL_XMM 12
cmp wd, 4
jl .h_w2
je .h_w4
tzcnt wd, wd
%if ARCH_X86_64
mova m10, [base+subpel_h_shufA]
mova m11, [base+subpel_h_shufB]
mova m9, [base+subpel_h_shufC]
%endif
shr mxd, 16
sub srcq, 3
movzx wd, word [base_reg+wq*2+table_offset(put, _8tap_h)]
movd m5, [base_reg+mxq*8+subpel_filters-put_ssse3+0]
pshufd m5, m5, q0000
movd m6, [base_reg+mxq*8+subpel_filters-put_ssse3+4]
pshufd m6, m6, q0000
mova m7, [base+pw_34] ; 2 + (8 << 2)
add wq, base_reg
jmp wq
.h_w2:
%if ARCH_X86_32
and mxd, 0xff
%else
movzx mxd, mxb
%endif
dec srcq
mova m4, [base+subpel_h_shuf4]
movd m3, [base_reg+mxq*8+subpel_filters-put_ssse3+2]
pshufd m3, m3, q0000
mova m5, [base+pw_34] ; 2 + (8 << 2)
W32_RESTORE_DSQ
.h_w2_loop:
movq m0, [srcq+ssq*0]
movhps m0, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
pshufb m0, m4
pmaddubsw m0, m3
phaddw m0, m0
paddw m0, m5 ; pw34
psraw m0, 6
packuswb m0, m0
movd r4d, m0
mov [dstq+dsq*0], r4w
shr r4d, 16
mov [dstq+dsq*1], r4w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .h_w2_loop
RET
.h_w4:
%if ARCH_X86_32
and mxd, 0xff
%else
movzx mxd, mxb
%endif
dec srcq
movd m3, [base_reg+mxq*8+subpel_filters-put_ssse3+2]
pshufd m3, m3, q0000
mova m5, [base+pw_34] ; 2 + (8 << 2)
mova m6, [base+subpel_h_shufA]
W32_RESTORE_DSQ
.h_w4_loop:
movq m0, [srcq+ssq*0] ; 1
movq m1, [srcq+ssq*1] ; 2
lea srcq, [srcq+ssq*2]
pshufb m0, m6 ; subpel_h_shufA
pshufb m1, m6 ; subpel_h_shufA
pmaddubsw m0, m3 ; subpel_filters
pmaddubsw m1, m3 ; subpel_filters
phaddw m0, m1
paddw m0, m5 ; pw34
psraw m0, 6
packuswb m0, m0
movd [dstq+dsq*0], m0
psrlq m0, 32
movd [dstq+dsq*1], m0
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .h_w4_loop
RET
;
%macro PUT_8TAP_H 4 ; dst/src, tmp[1-3]
%if ARCH_X86_32
pshufb %2, %1, [base+subpel_h_shufB]
pshufb %3, %1, [base+subpel_h_shufC]
pshufb %1, [base+subpel_h_shufA]
%else
pshufb %2, %1, m11; subpel_h_shufB
pshufb %3, %1, m9 ; subpel_h_shufC
pshufb %1, m10 ; subpel_h_shufA
%endif
pmaddubsw %4, %2, m5 ; subpel +0 B0
pmaddubsw %2, m6 ; subpel +4 B4
pmaddubsw %3, m6 ; C4
pmaddubsw %1, m5 ; A0
paddw %3, %4 ; C4+B0
paddw %1, %2 ; A0+B4
phaddw %1, %3
paddw %1, m7 ; pw34
psraw %1, 6
%endmacro
;
.h_w8:
movu m0, [srcq+ssq*0]
movu m1, [srcq+ssq*1]
PUT_8TAP_H m0, m2, m3, m4
lea srcq, [srcq+ssq*2]
PUT_8TAP_H m1, m2, m3, m4
packuswb m0, m1
%if ARCH_X86_32
movq [dstq ], m0
add dstq, dsm
movhps [dstq ], m0
add dstq, dsm
%else
movq [dstq+dsq*0], m0
movhps [dstq+dsq*1], m0
lea dstq, [dstq+dsq*2]
%endif
sub hd, 2
jg .h_w8
RET
.h_w16:
xor r6d, r6d
jmp .h_start
.h_w32:
mov r6, -16*1
jmp .h_start
.h_w64:
mov r6, -16*3
jmp .h_start
.h_w128:
mov r6, -16*7
.h_start:
sub srcq, r6
sub dstq, r6
mov r4, r6
.h_loop:
movu m0, [srcq+r6+8*0]
movu m1, [srcq+r6+8*1]
PUT_8TAP_H m0, m2, m3, m4
PUT_8TAP_H m1, m2, m3, m4
packuswb m0, m1
mova [dstq+r6], m0
add r6, mmsize
jle .h_loop
add srcq, ssq
%if ARCH_X86_32
add dstq, dsm
%else
add dstq, dsq
%endif
mov r6, r4
dec hd
jg .h_loop
RET
.v:
%if ARCH_X86_32
movzx mxd, ssb
shr ssd, 16
cmp hd, 4
cmovle ssd, mxd
lea ssq, [base_reg+ssq*8+subpel_filters-put_ssse3]
%else
%assign stack_offset org_stack_offset
WIN64_SPILL_XMM 16
movzx mxd, myb
shr myd, 16
cmp hd, 4
cmovle myd, mxd
lea myq, [base_reg+myq*8+subpel_filters-put_ssse3]
%endif
tzcnt r6d, wd
movzx r6d, word [base_reg+r6*2+table_offset(put, _8tap_v)]
mova m7, [base+pw_512]
psrlw m2, m7, 1 ; 0x0100
add r6, base_reg
%if ARCH_X86_32
%define subpel0 [rsp+mmsize*0]
%define subpel1 [rsp+mmsize*1]
%define subpel2 [rsp+mmsize*2]
%define subpel3 [rsp+mmsize*3]
%assign regs_used 2 ; use r1 (ds) as tmp for stack alignment if needed
ALLOC_STACK -mmsize*4
%assign regs_used 7
movd m0, [ssq+0]
pshufb m0, m2
mova subpel0, m0
movd m0, [ssq+2]
pshufb m0, m2
mova subpel1, m0
movd m0, [ssq+4]
pshufb m0, m2
mova subpel2, m0
movd m0, [ssq+6]
pshufb m0, m2
mova subpel3, m0
mov ssq, [rstk+stack_offset+gprsize*4]
lea ssq, [ssq*3]
sub srcq, ssq
mov ssq, [rstk+stack_offset+gprsize*4]
mov dsq, [rstk+stack_offset+gprsize*2]
%else
%define subpel0 m8
%define subpel1 m9
%define subpel2 m10
%define subpel3 m11
movd subpel0, [myq+0]
pshufb subpel0, m2
movd subpel1, [myq+2]
pshufb subpel1, m2
movd subpel2, [myq+4]
pshufb subpel2, m2
movd subpel3, [myq+6]
pshufb subpel3, m2
lea ss3q, [ssq*3]
sub srcq, ss3q
%endif
jmp r6
.v_w2:
movd m2, [srcq+ssq*0] ; 0
pinsrw m2, [srcq+ssq*1], 2 ; 0 1
pinsrw m2, [srcq+ssq*2], 4 ; 0 1 2
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
pinsrw m2, [srcq+ssq*0], 6 ; 0 1 2 3
add srcq, ssq
%else
pinsrw m2, [srcq+ss3q ], 6 ; 0 1 2 3
lea srcq, [srcq+ssq*4]
%endif
movd m3, [srcq+ssq*0] ; 4
movd m1, [srcq+ssq*1] ; 5
movd m0, [srcq+ssq*2] ; 6
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
%else
add srcq, ss3q
%endif
punpckldq m3, m1 ; 4 5 _ _
punpckldq m1, m0 ; 5 6 _ _
palignr m4, m3, m2, 4 ; 1 2 3 4
punpcklbw m3, m1 ; 45 56
punpcklbw m1, m2, m4 ; 01 12
punpckhbw m2, m4 ; 23 34
.v_w2_loop:
pmaddubsw m5, m1, subpel0 ; a0 b0
mova m1, m2
pmaddubsw m2, subpel1 ; a1 b1
paddw m5, m2
mova m2, m3
pmaddubsw m3, subpel2 ; a2 b2
paddw m5, m3
movd m4, [srcq+ssq*0] ; 7
punpckldq m3, m0, m4 ; 6 7 _ _
movd m0, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
punpckldq m4, m0 ; 7 8 _ _
punpcklbw m3, m4 ; 67 78
pmaddubsw m4, m3, subpel3 ; a3 b3
paddw m5, m4
pmulhrsw m5, m7
packuswb m5, m5
pshuflw m5, m5, q2020
movd r6d, m5
mov [dstq+dsq*0], r6w
shr r6d, 16
mov [dstq+dsq*1], r6w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .v_w2_loop
RET
.v_w4:
%if ARCH_X86_32
.v_w8:
.v_w16:
.v_w32:
.v_w64:
.v_w128:
%endif ; ARCH_X86_32
lea r6d, [wq - 4] ; horizontal loop
mov r4, dstq
%if ARCH_X86_32
%if STACK_ALIGNMENT < mmsize
%define srcm [rsp+mmsize*4+gprsize]
%endif
mov srcm, srcq
%else
mov r7, srcq
%endif
shl r6d, (16 - 2) ; (wq / 4) << 16
mov r6w, hw
.v_w4_loop0:
movd m2, [srcq+ssq*0] ; 0
movhps m2, [srcq+ssq*2] ; 0 _ 2
movd m3, [srcq+ssq*1] ; 1
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
movhps m3, [srcq+ssq*0] ; 1 _ 3
lea srcq, [srcq+ssq*1]
%else
movhps m3, [srcq+ss3q ] ; 1 _ 3
lea srcq, [srcq+ssq*4]
%endif
pshufd m2, m2, q2020 ; 0 2 0 2
pshufd m3, m3, q2020 ; 1 3 1 3
punpckldq m2, m3 ; 0 1 2 3
movd m3, [srcq+ssq*0] ; 4
movd m1, [srcq+ssq*1] ; 5
movd m0, [srcq+ssq*2] ; 6
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
%else
add srcq, ss3q
%endif
punpckldq m3, m1 ; 4 5 _ _
punpckldq m1, m0 ; 5 6 _ _
palignr m4, m3, m2, 4 ; 1 2 3 4
punpcklbw m3, m1 ; 45 56
punpcklbw m1, m2, m4 ; 01 12
punpckhbw m2, m4 ; 23 34
.v_w4_loop:
pmaddubsw m5, m1, subpel0 ; a0 b0
mova m1, m2
pmaddubsw m2, subpel1 ; a1 b1
paddw m5, m2
mova m2, m3
pmaddubsw m3, subpel2 ; a2 b2
paddw m5, m3
movd m4, [srcq+ssq*0]
punpckldq m3, m0, m4 ; 6 7 _ _
movd m0, [srcq+ssq*1]
lea srcq, [srcq+ssq*2]
punpckldq m4, m0 ; 7 8 _ _
punpcklbw m3, m4 ; 67 78
pmaddubsw m4, m3, subpel3 ; a3 b3
paddw m5, m4
pmulhrsw m5, m7
packuswb m5, m5
movd [dstq+dsq*0], m5
pshufd m5, m5, q0101
movd [dstq+dsq*1], m5
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .v_w4_loop
mov hw, r6w ; reset vertical loop
add r4, 4
mov dstq, r4
%if ARCH_X86_32
mov srcq, srcm
add srcq, 4
mov srcm, srcq
%else
add r7, 4
mov srcq, r7
%endif
sub r6d, 1<<16 ; horizontal--
jg .v_w4_loop0
RET
%if ARCH_X86_64
.v_w8:
.v_w16:
.v_w32:
.v_w64:
.v_w128:
lea r6d, [wq - 8] ; horizontal loop
mov r4, dstq
mov r7, srcq
shl r6d, 8 - 3; (wq / 8) << 8
mov r6b, hb
.v_w8_loop0:
movq m4, [srcq+ssq*0] ; 0
movq m5, [srcq+ssq*1] ; 1
lea srcq, [srcq+ssq*2]
movq m6, [srcq+ssq*0] ; 2
movq m0, [srcq+ssq*1] ; 3
lea srcq, [srcq+ssq*2]
movq m1, [srcq+ssq*0] ; 4
movq m2, [srcq+ssq*1] ; 5
lea srcq, [srcq+ssq*2] ;
movq m3, [srcq+ssq*0] ; 6
shufpd m4, m0, 0x0c
shufpd m5, m1, 0x0c
punpcklbw m1, m4, m5 ; 01
punpckhbw m4, m5 ; 34
shufpd m6, m2, 0x0c
punpcklbw m2, m5, m6 ; 12
punpckhbw m5, m6 ; 45
shufpd m0, m3, 0x0c
punpcklbw m3, m6, m0 ; 23
punpckhbw m6, m0 ; 56
.v_w8_loop:
movq m12, [srcq+ssq*1] ; 8
lea srcq, [srcq+ssq*2]
movq m13, [srcq+ssq*0] ; 9
pmaddubsw m14, m1, subpel0 ; a0
pmaddubsw m15, m2, subpel0 ; b0
mova m1, m3
mova m2, m4
pmaddubsw m3, subpel1 ; a1
pmaddubsw m4, subpel1 ; b1
paddw m14, m3
paddw m15, m4
mova m3, m5
mova m4, m6
pmaddubsw m5, subpel2 ; a2
pmaddubsw m6, subpel2 ; b2
paddw m14, m5
paddw m15, m6
shufpd m6, m0, m12, 0x0d
shufpd m0, m12, m13, 0x0c
punpcklbw m5, m6, m0 ; 67
punpckhbw m6, m0 ; 78
pmaddubsw m12, m5, subpel3 ; a3
pmaddubsw m13, m6, subpel3 ; b3
paddw m14, m12
paddw m15, m13
pmulhrsw m14, m7
pmulhrsw m15, m7
packuswb m14, m15
movq [dstq+dsq*0], xm14
movhps [dstq+dsq*1], xm14
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .v_w8_loop
movzx hd, r6b ; reset vertical loop
add r4, 8
add r7, 8
mov dstq, r4
mov srcq, r7
sub r6d, 1<<8 ; horizontal--
jg .v_w8_loop0
RET
%endif ;ARCH_X86_64
%undef subpel0
%undef subpel1
%undef subpel2
%undef subpel3
.hv:
%assign stack_offset org_stack_offset
cmp wd, 4
jg .hv_w8
and mxd, 0xff
dec srcq
movd m1, [base_reg+mxq*8+subpel_filters-put_ssse3+2]
%if ARCH_X86_32
movzx mxd, ssb
shr ssd, 16
cmp hd, 4
cmovle ssd, mxd
movq m0, [base_reg+ssq*8+subpel_filters-put_ssse3]
W32_RESTORE_SSQ
lea r6, [ssq*3]
sub srcq, r6
%define base_reg r6
mov r6, r1; use as new base
%assign regs_used 2
ALLOC_STACK -mmsize*14
%assign regs_used 7
mov dsq, [rstk+stack_offset+gprsize*2]
%define subpelv0 [rsp+mmsize*0]
%define subpelv1 [rsp+mmsize*1]
%define subpelv2 [rsp+mmsize*2]
%define subpelv3 [rsp+mmsize*3]
punpcklqdq m0, m0
punpcklbw m0, m0
psraw m0, 8 ; sign-extend
pshufd m6, m0, q0000
mova subpelv0, m6
pshufd m6, m0, q1111
mova subpelv1, m6
pshufd m6, m0, q2222
mova subpelv2, m6
pshufd m6, m0, q3333
mova subpelv3, m6
%else
movzx mxd, myb
shr myd, 16
cmp hd, 4
cmovle myd, mxd
movq m0, [base_reg+myq*8+subpel_filters-put_ssse3]
ALLOC_STACK mmsize*14, 14
lea ss3q, [ssq*3]
sub srcq, ss3q
%define subpelv0 m10
%define subpelv1 m11
%define subpelv2 m12
%define subpelv3 m13
punpcklqdq m0, m0
punpcklbw m0, m0
psraw m0, 8 ; sign-extend
mova m8, [base+pw_8192]
mova m9, [base+pd_512]
pshufd m10, m0, q0000
pshufd m11, m0, q1111
pshufd m12, m0, q2222
pshufd m13, m0, q3333
%endif
pshufd m7, m1, q0000
cmp wd, 4
je .hv_w4
.hv_w2:
mova m6, [base+subpel_h_shuf4]
;
movq m2, [srcq+ssq*0] ; 0
movhps m2, [srcq+ssq*1] ; 0 _ 1
movq m0, [srcq+ssq*2] ; 2
%if ARCH_X86_32
%define w8192reg [base+pw_8192]
%define d512reg [base+pd_512]
lea srcq, [srcq+ssq*2]
add srcq, ssq
movhps m0, [srcq+ssq*0] ; 2 _ 3
lea srcq, [srcq+ssq*1]
%else
%define w8192reg m8
%define d512reg m9
movhps m0, [srcq+ss3q ] ; 2 _ 3
lea srcq, [srcq+ssq*4]
%endif
pshufb m2, m6 ; 0 ~ 1 ~
pshufb m0, m6 ; 2 ~ 3 ~
pmaddubsw m2, m7 ; subpel_filters
pmaddubsw m0, m7 ; subpel_filters
phaddw m2, m0 ; 0 1 2 3
pmulhrsw m2, w8192reg
;
movq m3, [srcq+ssq*0] ; 4
movhps m3, [srcq+ssq*1] ; 4 _ 5
movq m0, [srcq+ssq*2] ; 6
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
%else
add srcq, ss3q
%endif
pshufb m3, m6 ; 4 ~ 5 ~
pshufb m0, m6 ; 6 ~
pmaddubsw m3, m7 ; subpel_filters
pmaddubsw m0, m7 ; subpel_filters
phaddw m3, m0 ; 4 5 6 _
pmulhrsw m3, w8192reg
;
palignr m4, m3, m2, 4; V 1 2 3 4
punpcklwd m1, m2, m4 ; V 01 12 0 1 1 2
punpckhwd m2, m4 ; V 23 34 2 3 3 4
pshufd m0, m3, q2121; V 5 6 5 6
punpcklwd m3, m0 ; V 45 56 4 5 5 6
.hv_w2_loop:
pmaddwd m5, m1, subpelv0; V a0 b0
mova m1, m2 ; V
pmaddwd m2, subpelv1 ; V a1 b1
paddd m5, m2 ; V
mova m2, m3 ; V
pmaddwd m3, subpelv2 ; a2 b2
paddd m5, m3 ; V
movq m4, [srcq+ssq*0] ; V 7
movhps m4, [srcq+ssq*1] ; V 7 8
lea srcq, [srcq+ssq*2] ; V
pshufb m4, m6
pmaddubsw m4, m7
phaddw m4, m4
pmulhrsw m4, w8192reg
palignr m3, m4, m0, 12
mova m0, m4
punpcklwd m3, m0 ; V 67 78
pmaddwd m4, m3, subpelv3 ; V a3 b3
paddd m5, d512reg
paddd m5, m4
psrad m5, 10
packssdw m5, m5
packuswb m5, m5
movd r4d, m5
mov [dstq+dsq*0], r4w
shr r4d, 16
mov [dstq+dsq*1], r4w
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .hv_w2_loop
RET
%undef w8192reg
%undef d512reg
;
.hv_w4:
%define hv4_line_0_0 4
%define hv4_line_0_1 5
%define hv4_line_0_2 6
%define hv4_line_0_3 7
%define hv4_line_0_4 8
%define hv4_line_0_5 9
%define hv4_line_1_0 10
%define hv4_line_1_1 11
%define hv4_line_1_2 12
%define hv4_line_1_3 13
;
%macro SAVELINE_W4 3
mova [rsp+mmsize*hv4_line_%3_%2], %1
%endmacro
%macro RESTORELINE_W4 3
mova %1, [rsp+mmsize*hv4_line_%3_%2]
%endmacro
;
%if ARCH_X86_32
%define w8192reg [base+pw_8192]
%define d512reg [base+pd_512]
%else
%define w8192reg m8
%define d512reg m9
%endif
; lower shuffle 0 1 2 3 4
mova m6, [base+subpel_h_shuf4]
movq m5, [srcq+ssq*0] ; 0 _ _ _
movhps m5, [srcq+ssq*1] ; 0 _ 1 _
movq m4, [srcq+ssq*2] ; 2 _ _ _
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
movhps m4, [srcq+ssq*0] ; 2 _ 3 _
add srcq, ssq
%else
movhps m4, [srcq+ss3q ] ; 2 _ 3 _
lea srcq, [srcq+ssq*4]
%endif
pshufb m2, m5, m6 ;H subpel_h_shuf4 0 ~ 1 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 2 ~ 3 ~
pmaddubsw m2, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m2, m0 ;H 0 1 2 3
pmulhrsw m2, w8192reg ;H pw_8192
SAVELINE_W4 m2, 2, 0
; upper shuffle 2 3 4 5 6
mova m6, [base+subpel_h_shuf4+16]
pshufb m2, m5, m6 ;H subpel_h_shuf4 0 ~ 1 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 2 ~ 3 ~
pmaddubsw m2, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m2, m0 ;H 0 1 2 3
pmulhrsw m2, w8192reg ;H pw_8192
;
; lower shuffle
mova m6, [base+subpel_h_shuf4]
movq m5, [srcq+ssq*0] ; 4 _ _ _
movhps m5, [srcq+ssq*1] ; 4 _ 5 _
movq m4, [srcq+ssq*2] ; 6 _ _ _
pshufb m3, m5, m6 ;H subpel_h_shuf4 4 ~ 5 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 6 ~ 6 ~
pmaddubsw m3, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m3, m0 ;H 4 5 6 7
pmulhrsw m3, w8192reg ;H pw_8192
SAVELINE_W4 m3, 3, 0
; upper shuffle
mova m6, [base+subpel_h_shuf4+16]
pshufb m3, m5, m6 ;H subpel_h_shuf4 4 ~ 5 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 6 ~ 6 ~
pmaddubsw m3, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m3, m0 ;H 4 5 6 7
pmulhrsw m3, w8192reg ;H pw_8192
;
%if ARCH_X86_32
lea srcq, [srcq+ssq*2]
add srcq, ssq
%else
add srcq, ss3q
%endif
;process high
palignr m4, m3, m2, 4;V 1 2 3 4
punpcklwd m1, m2, m4 ; V 01 12
punpckhwd m2, m4 ; V 23 34
pshufd m0, m3, q2121;V 5 6 5 6
punpcklwd m3, m0 ; V 45 56
SAVELINE_W4 m0, 0, 1
SAVELINE_W4 m1, 1, 1
SAVELINE_W4 m2, 2, 1
SAVELINE_W4 m3, 3, 1
;process low
RESTORELINE_W4 m2, 2, 0
RESTORELINE_W4 m3, 3, 0
palignr m4, m3, m2, 4;V 1 2 3 4
punpcklwd m1, m2, m4 ; V 01 12
punpckhwd m2, m4 ; V 23 34
pshufd m0, m3, q2121;V 5 6 5 6
punpcklwd m3, m0 ; V 45 56
.hv_w4_loop:
;process low
pmaddwd m5, m1, subpelv0 ; V a0 b0
mova m1, m2
pmaddwd m2, subpelv1; V a1 b1
paddd m5, m2
mova m2, m3
pmaddwd m3, subpelv2; V a2 b2
paddd m5, m3
;
mova m6, [base+subpel_h_shuf4]
movq m4, [srcq+ssq*0] ; 7
movhps m4, [srcq+ssq*1] ; 7 _ 8 _
pshufb m4, m6 ;H subpel_h_shuf4 7 ~ 8 ~
pmaddubsw m4, m7 ;H subpel_filters
phaddw m4, m4 ;H 7 8 7 8
pmulhrsw m4, w8192reg ;H pw_8192
palignr m3, m4, m0, 12 ; 6 7 8 7
mova m0, m4
punpcklwd m3, m4 ; 67 78
pmaddwd m4, m3, subpelv3; a3 b3
paddd m5, d512reg ; pd_512
paddd m5, m4
psrad m5, 10
SAVELINE_W4 m0, 0, 0
SAVELINE_W4 m1, 1, 0
SAVELINE_W4 m2, 2, 0
SAVELINE_W4 m3, 3, 0
SAVELINE_W4 m5, 5, 0
;process high
RESTORELINE_W4 m0, 0, 1
RESTORELINE_W4 m1, 1, 1
RESTORELINE_W4 m2, 2, 1
RESTORELINE_W4 m3, 3, 1
pmaddwd m5, m1, subpelv0; V a0 b0
mova m1, m2
pmaddwd m2, subpelv1; V a1 b1
paddd m5, m2
mova m2, m3
pmaddwd m3, subpelv2; V a2 b2
paddd m5, m3
;
mova m6, [base+subpel_h_shuf4+16]
movq m4, [srcq+ssq*0] ; 7
movhps m4, [srcq+ssq*1] ; 7 _ 8 _
pshufb m4, m6 ;H subpel_h_shuf4 7 ~ 8 ~
pmaddubsw m4, m7 ;H subpel_filters
phaddw m4, m4 ;H 7 8 7 8
pmulhrsw m4, w8192reg ;H pw_8192
palignr m3, m4, m0, 12 ; 6 7 8 7
mova m0, m4
punpcklwd m3, m4 ; 67 78
pmaddwd m4, m3, subpelv3; a3 b3
paddd m5, d512reg ; pd_512
paddd m5, m4
psrad m4, m5, 10
;
RESTORELINE_W4 m5, 5, 0
packssdw m5, m4 ; d -> w
packuswb m5, m5 ; w -> b
pshuflw m5, m5, q3120
lea srcq, [srcq+ssq*2]
movd [dstq+dsq*0], m5
psrlq m5, 32
movd [dstq+dsq*1], m5
lea dstq, [dstq+dsq*2]
sub hd, 2
SAVELINE_W4 m0, 0, 1
SAVELINE_W4 m1, 1, 1
SAVELINE_W4 m2, 2, 1
SAVELINE_W4 m3, 3, 1
RESTORELINE_W4 m0, 0, 0
RESTORELINE_W4 m1, 1, 0
RESTORELINE_W4 m2, 2, 0
RESTORELINE_W4 m3, 3, 0
jg .hv_w4_loop
RET
%undef subpelv0
%undef subpelv1
%undef subpelv2
%undef subpelv3
;
.hv_w8:
%assign stack_offset org_stack_offset
%define hv8_line_1 0
%define hv8_line_2 1
%define hv8_line_3 2
%define hv8_line_4 3
%define hv8_line_6 4
%macro SAVELINE_W8 2
mova [rsp+hv8_line_%1*mmsize], %2
%endmacro
%macro RESTORELINE_W8 2
mova %2, [rsp+hv8_line_%1*mmsize]
%endmacro
shr mxd, 16
sub srcq, 3
%if ARCH_X86_32
%define base_reg r1
%define subpelh0 [rsp+mmsize*5]
%define subpelh1 [rsp+mmsize*6]
%define subpelv0 [rsp+mmsize*7]
%define subpelv1 [rsp+mmsize*8]
%define subpelv2 [rsp+mmsize*9]
%define subpelv3 [rsp+mmsize*10]
%define accuv0 [rsp+mmsize*11]
%define accuv1 [rsp+mmsize*12]
movq m1, [base_reg+mxq*8+subpel_filters-put_ssse3]
movzx mxd, ssb
shr ssd, 16
cmp hd, 4
cmovle ssd, mxd
movq m5, [base_reg+ssq*8+subpel_filters-put_ssse3]
mov ssq, ssmp
ALLOC_STACK -mmsize*13
%if STACK_ALIGNMENT < 16
%define srcm [rsp+mmsize*13+gprsize*1]
%define dsm [rsp+mmsize*13+gprsize*2]
mov r6, [rstk+stack_offset+gprsize*2]
mov dsm, r6
%endif
pshufd m0, m1, q0000
pshufd m1, m1, q1111
punpcklbw m5, m5
psraw m5, 8 ; sign-extend
pshufd m2, m5, q0000
pshufd m3, m5, q1111
pshufd m4, m5, q2222
pshufd m5, m5, q3333
mova subpelh0, m0
mova subpelh1, m1
mova subpelv0, m2
mova subpelv1, m3
mova subpelv2, m4
mova subpelv3, m5
lea r6, [ssq*3]
sub srcq, r6
mov srcm, srcq
%else
ALLOC_STACK mmsize*5, 16
%define subpelh0 m10
%define subpelh1 m11
%define subpelv0 m12
%define subpelv1 m13
%define subpelv2 m14
%define subpelv3 m15
%define accuv0 m8
%define accuv1 m9
movq m0, [base_reg+mxq*8+subpel_filters-put_ssse3]
movzx mxd, myb
shr myd, 16
cmp hd, 4
cmovle myd, mxd
movq m1, [base_reg+myq*8+subpel_filters-put_ssse3]
pshufd subpelh0, m0, q0000
pshufd subpelh1, m0, q1111
punpcklqdq m1, m1
punpcklbw m1, m1
psraw m1, 8 ; sign-extend
pshufd subpelv0, m1, q0000
pshufd subpelv1, m1, q1111
pshufd subpelv2, m1, q2222
pshufd subpelv3, m1, q3333
lea ss3q, [ssq*3]
sub srcq, ss3q
mov r7, srcq
%endif
lea r6d, [wq-4]
mov r4, dstq
shl r6d, (16 - 2)
mov r6w, hw
.hv_w8_loop0:
movu m4, [srcq+ssq*0] ; 0 = _ _
movu m5, [srcq+ssq*1] ; 1 = _ _
lea srcq, [srcq+ssq*2]
;
%macro HV_H_W8 4-7 ; src/dst, tmp[1-3], shuf[1-3]
%if ARCH_X86_32
pshufb %3, %1, [base+subpel_h_shufB]
pshufb %4, %1, [base+subpel_h_shufC]
pshufb %1, [base+subpel_h_shufA]
%else
pshufb %3, %1, %6 ; subpel_h_shufB
pshufb %4, %1, %7 ; subpel_h_shufC
pshufb %1, %5 ; subpel_h_shufA
%endif
pmaddubsw %2, %3, subpelh0 ; subpel +0 C0
pmaddubsw %4, subpelh1; subpel +4 B4
pmaddubsw %3, subpelh1; C4
pmaddubsw %1, subpelh0; A0
paddw %2, %4 ; C0+B4
paddw %1, %3 ; A0+C4
phaddw %1, %2
%endmacro
;
%if ARCH_X86_64
mova m7, [base+subpel_h_shufA]
mova m8, [base+subpel_h_shufB]
mova m9, [base+subpel_h_shufC]
%endif
HV_H_W8 m4, m1, m2, m3, m7, m8, m9 ; 0 ~ ~ ~
HV_H_W8 m5, m1, m2, m3, m7, m8, m9 ; 1 ~ ~ ~
movu m6, [srcq+ssq*0] ; 2 = _ _
movu m0, [srcq+ssq*1] ; 3 = _ _
lea srcq, [srcq+ssq*2]
HV_H_W8 m6, m1, m2, m3, m7, m8, m9 ; 2 ~ ~ ~
HV_H_W8 m0, m1, m2, m3, m7, m8, m9 ; 3 ~ ~ ~
;
mova m7, [base+pw_8192]
pmulhrsw m4, m7 ; H pw_8192
pmulhrsw m5, m7 ; H pw_8192
pmulhrsw m6, m7 ; H pw_8192
pmulhrsw m0, m7 ; H pw_8192
punpcklwd m1, m4, m5 ; 0 1 ~
punpcklwd m2, m5, m6 ; 1 2 ~
punpcklwd m3, m6, m0 ; 2 3 ~
SAVELINE_W8 1, m1
SAVELINE_W8 2, m2
SAVELINE_W8 3, m3
;
mova m7, [base+subpel_h_shufA]
movu m4, [srcq+ssq*0] ; 4 = _ _
movu m5, [srcq+ssq*1] ; 5 = _ _
lea srcq, [srcq+ssq*2]
movu m6, [srcq+ssq*0] ; 6 = _ _
HV_H_W8 m4, m1, m2, m3, m7, m8, m9 ; 4 ~ ~ ~
HV_H_W8 m5, m1, m2, m3, m7, m8, m9 ; 5 ~ ~ ~
HV_H_W8 m6, m1, m2, m3, m7, m8, m9 ; 6 ~ ~ ~
mova m7, [base+pw_8192]
pmulhrsw m1, m4, m7 ; H pw_8192 4 ~
pmulhrsw m2, m5, m7 ; H pw_8192 5 ~
pmulhrsw m3, m6, m7 ; H pw_8192 6 ~
punpcklwd m4, m0, m1 ; 3 4 ~
punpcklwd m5, m1, m2 ; 4 5 ~
punpcklwd m6, m2, m3 ; 5 6 ~
;
SAVELINE_W8 6, m3
RESTORELINE_W8 1, m1
RESTORELINE_W8 2, m2
RESTORELINE_W8 3, m3
.hv_w8_loop:
; m8 accu for V a
; m9 accu for V b
SAVELINE_W8 1, m3
SAVELINE_W8 2, m4
SAVELINE_W8 3, m5
SAVELINE_W8 4, m6
%if ARCH_X86_32
pmaddwd m0, m1, subpelv0 ; a0
pmaddwd m7, m2, subpelv0 ; b0
pmaddwd m3, subpelv1 ; a1
pmaddwd m4, subpelv1 ; b1
paddd m0, m3
paddd m7, m4
pmaddwd m5, subpelv2 ; a2
pmaddwd m6, subpelv2 ; b2
paddd m0, m5
paddd m7, m6
mova m5, [base+pd_512]
paddd m0, m5 ; pd_512
paddd m7, m5 ; pd_512
mova accuv0, m0
mova accuv1, m7
%else
pmaddwd m8, m1, subpelv0 ; a0
pmaddwd m9, m2, subpelv0 ; b0
pmaddwd m3, subpelv1 ; a1
pmaddwd m4, subpelv1 ; b1
paddd m8, m3
paddd m9, m4
pmaddwd m5, subpelv2 ; a2
pmaddwd m6, subpelv2 ; b2
paddd m8, m5
paddd m9, m6
mova m7, [base+pd_512]
paddd m8, m7 ; pd_512
paddd m9, m7 ; pd_512
mova m7, [base+subpel_h_shufB]
mova m6, [base+subpel_h_shufC]
mova m5, [base+subpel_h_shufA]
%endif
movu m0, [srcq+ssq*1] ; 7
movu m4, [srcq+ssq*2] ; 8
lea srcq, [srcq+ssq*2]
HV_H_W8 m0, m1, m2, m3, m5, m7, m6
HV_H_W8 m4, m1, m2, m3, m5, m7, m6
mova m5, [base+pw_8192]
pmulhrsw m0, m5 ; H pw_8192
pmulhrsw m4, m5 ; H pw_8192
RESTORELINE_W8 6, m6
punpcklwd m5, m6, m0 ; 6 7 ~
punpcklwd m6, m0, m4 ; 7 8 ~
pmaddwd m1, m5, subpelv3 ; a3
paddd m2, m1, accuv0
pmaddwd m1, m6, subpelv3 ; b3
paddd m1, m1, accuv1 ; H + V
psrad m2, 10
psrad m1, 10
packssdw m2, m1 ; d -> w
packuswb m2, m1 ; w -> b
movd [dstq+dsq*0], m2
psrlq m2, 32
%if ARCH_X86_32
add dstq, dsm
movd [dstq+dsq*0], m2
add dstq, dsm
%else
movd [dstq+dsq*1], m2
lea dstq, [dstq+dsq*2]
%endif
sub hd, 2
jle .hv_w8_outer
SAVELINE_W8 6, m4
RESTORELINE_W8 1, m1
RESTORELINE_W8 2, m2
RESTORELINE_W8 3, m3
RESTORELINE_W8 4, m4
jmp .hv_w8_loop
.hv_w8_outer:
movzx hd, r6w
add r4, 4
mov dstq, r4
%if ARCH_X86_32
mov srcq, srcm
add srcq, 4
mov srcm, srcq
%else
add r7, 4
mov srcq, r7
%endif
sub r6d, 1<<16
jg .hv_w8_loop0
RET
%if ARCH_X86_32
DECLARE_REG_TMP 1, 2
%elif WIN64
DECLARE_REG_TMP 6, 4
%else
DECLARE_REG_TMP 6, 7
%endif
%macro PREP_8TAP_FN 3 ; type, type_h, type_v
cglobal prep_8tap_%1
mov t0d, FILTER_%2
mov t1d, FILTER_%3
%ifnidn %1, sharp_smooth ; skip the jump in the last filter
jmp mangle(private_prefix %+ _prep_8tap %+ SUFFIX)
%endif
%endmacro
PREP_8TAP_FN regular, REGULAR, REGULAR
PREP_8TAP_FN regular_sharp, REGULAR, SHARP
PREP_8TAP_FN regular_smooth, REGULAR, SMOOTH
PREP_8TAP_FN smooth_regular, SMOOTH, REGULAR
PREP_8TAP_FN smooth, SMOOTH, SMOOTH
PREP_8TAP_FN smooth_sharp, SMOOTH, SHARP
PREP_8TAP_FN sharp_regular, SHARP, REGULAR
PREP_8TAP_FN sharp, SHARP, SHARP
PREP_8TAP_FN sharp_smooth, SHARP, SMOOTH
%if ARCH_X86_32
%define base_reg r2
%define base base_reg-prep_ssse3
%define W32_RESTORE_SSQ mov strideq, stridem
%else
%define base_reg r7
%define base 0
%define W32_RESTORE_SSQ
%endif
cglobal prep_8tap, 1, 9, 0, tmp, src, stride, w, h, mx, my, stride3
%assign org_stack_offset stack_offset
imul mxd, mxm, 0x010101
add mxd, t0d ; 8tap_h, mx, 4tap_h
imul myd, mym, 0x010101
add myd, t1d ; 8tap_v, my, 4tap_v
movsxd wq, wm
movifnidn srcd, srcm
movifnidn hd, hm
LEA base_reg, prep_ssse3
test mxd, 0xf00
jnz .h
test myd, 0xf00
jnz .v
tzcnt wd, wd
movzx wd, word [base_reg+wq*2+table_offset(prep,)]
add wq, base_reg
movifnidn strided, stridem
lea r6, [strideq*3]
%assign stack_offset org_stack_offset
%if WIN64
pop r8
pop r7
%endif
jmp wq
.h:
test myd, 0xf00
jnz .hv
WIN64_SPILL_XMM 12
cmp wd, 4
je .h_w4
tzcnt wd, wd
%if ARCH_X86_64
mova m10, [base+subpel_h_shufA]
mova m11, [base+subpel_h_shufB]
mova m9, [base+subpel_h_shufC]
%endif
shr mxd, 16
sub srcq, 3
movzx wd, word [base_reg+wq*2+table_offset(prep, _8tap_h)]
movd m5, [base_reg+mxq*8+subpel_filters-prep_ssse3+0]
pshufd m5, m5, q0000
movd m6, [base_reg+mxq*8+subpel_filters-prep_ssse3+4]
pshufd m6, m6, q0000
mova m7, [base+pw_8192]
add wq, base_reg
jmp wq
.h_w4:
%if ARCH_X86_32
and mxd, 0xff
%else
movzx mxd, mxb
%endif
dec srcq
movd m4, [base_reg+mxq*8+subpel_filters-prep_ssse3+2]
pshufd m4, m4, q0000
mova m6, [base+pw_8192]
mova m5, [base+subpel_h_shufA]
W32_RESTORE_SSQ
%if ARCH_X86_64
lea stride3q, [strideq*3]
%endif
.h_w4_loop:
movq m0, [srcq+strideq*0] ; 0
movq m1, [srcq+strideq*1] ; 1
%if ARCH_X86_32
lea srcq, [srcq+strideq*2]
movq m2, [srcq+strideq*0] ; 2
movq m3, [srcq+strideq*1] ; 3
lea srcq, [srcq+strideq*2]
%else
movq m2, [srcq+strideq*2] ; 2
movq m3, [srcq+stride3q ] ; 3
lea srcq, [srcq+strideq*4]
%endif
pshufb m0, m5 ; subpel_h_shufA
pshufb m1, m5
pshufb m2, m5
pshufb m3, m5
pmaddubsw m0, m4 ; subpel_filters + 2
pmaddubsw m1, m4
pmaddubsw m2, m4
pmaddubsw m3, m4
phaddw m0, m1
phaddw m2, m3
pmulhrsw m0, m6 ; pw_8192
pmulhrsw m2, m6 ; pw_8192
mova [tmpq+16*0], m0
mova [tmpq+16*1], m2
add tmpq, 32
sub hd, 4
jg .h_w4_loop
RET
;
%macro PREP_8TAP_H 4 ; dst/src, tmp[1-3]
%if ARCH_X86_32
pshufb %2, %1, [base+subpel_h_shufB]
pshufb %3, %1, [base+subpel_h_shufC]
pshufb %1, [base+subpel_h_shufA]
%else
pshufb %2, %1, m11; subpel_h_shufB
pshufb %3, %1, m9 ; subpel_h_shufC
pshufb %1, m10 ; subpel_h_shufA
%endif
pmaddubsw %4, %2, m5 ; subpel +0 B0
pmaddubsw %2, m6 ; subpel +4 B4
pmaddubsw %3, m6 ; subpel +4 C4
pmaddubsw %1, m5 ; subpel +0 A0
paddw %3, %4
paddw %1, %2
phaddw %1, %3
pmulhrsw %1, m7 ; 8192
%endmacro
;
.h_w8:
%if ARCH_X86_32
mov r3, r2
%define base_reg r3
W32_RESTORE_SSQ
%endif
.h_w8_loop:
movu m0, [srcq+strideq*0]
movu m1, [srcq+strideq*1]
lea srcq, [srcq+strideq*2]
PREP_8TAP_H m0, m2, m3, m4
PREP_8TAP_H m1, m2, m3, m4
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
add tmpq, 32
sub hd, 2
jg .h_w8_loop
RET
.h_w16:
xor r6d, r6d
jmp .h_start
.h_w32:
mov r6, -16*1
jmp .h_start
.h_w64:
mov r6, -16*3
jmp .h_start
.h_w128:
mov r6, -16*7
.h_start:
%if ARCH_X86_32
mov r3, r2
%define base_reg r3
%endif
sub srcq, r6
mov r5, r6
W32_RESTORE_SSQ
.h_loop:
movu m0, [srcq+r6+8*0]
movu m1, [srcq+r6+8*1]
PREP_8TAP_H m0, m2, m3, m4
PREP_8TAP_H m1, m2, m3, m4
mova [tmpq+16*0], m0
mova [tmpq+16*1], m1
add tmpq, 32
add r6, 16
jle .h_loop
add srcq, strideq
mov r6, r5
dec hd
jg .h_loop
RET
%if ARCH_X86_32
%define base_reg r2
%endif
.v:
%if ARCH_X86_32
mov mxd, myd
and mxd, 0xff
%else
%assign stack_offset org_stack_offset
WIN64_SPILL_XMM 16
movzx mxd, myb
%endif
shr myd, 16
cmp hd, 4
cmovle myd, mxd
lea myq, [base_reg+myq*8+subpel_filters-prep_ssse3]
mova m2, [base+pw_512]
psrlw m2, m2, 1 ; 0x0100
mova m7, [base+pw_8192]
%if ARCH_X86_32
%define subpel0 [rsp+mmsize*0]
%define subpel1 [rsp+mmsize*1]
%define subpel2 [rsp+mmsize*2]
%define subpel3 [rsp+mmsize*3]
%assign regs_used 2 ; use r1 (src) as tmp for stack alignment if needed
ALLOC_STACK -mmsize*4
%assign regs_used 7
movd m0, [myq+0]
pshufb m0, m2
mova subpel0, m0
movd m0, [myq+2]
pshufb m0, m2
mova subpel1, m0
movd m0, [myq+4]
pshufb m0, m2
mova subpel2, m0
movd m0, [myq+6]
pshufb m0, m2
mova subpel3, m0
mov strideq, [rstk+stack_offset+gprsize*3]
lea strideq, [strideq*3]
sub [rstk+stack_offset+gprsize*2], strideq
mov strideq, [rstk+stack_offset+gprsize*3]
mov srcq, [rstk+stack_offset+gprsize*2]
%else
%define subpel0 m8
%define subpel1 m9
%define subpel2 m10
%define subpel3 m11
movd subpel0, [myq+0]
pshufb subpel0, m2
movd subpel1, [myq+2]
pshufb subpel1, m2
movd subpel2, [myq+4]
pshufb subpel2, m2
movd subpel3, [myq+6]
pshufb subpel3, m2
lea stride3q, [strideq*3]
sub srcq, stride3q
cmp wd, 8
jg .v_w16
je .v_w8
%endif
.v_w4:
%if ARCH_X86_32
%if STACK_ALIGNMENT < mmsize
%define srcm [rsp+mmsize*4+gprsize*1]
%define tmpm [rsp+mmsize*4+gprsize*2]
%endif
mov tmpm, tmpq
mov srcm, srcq
lea r5d, [wq - 4] ; horizontal loop
shl r5d, (16 - 2) ; (wq / 4) << 16
mov r5w, hw
.v_w4_loop0:
%endif
movd m2, [srcq+strideq*0] ; 0
movhps m2, [srcq+strideq*2] ; 0 _ 2
movd m3, [srcq+strideq*1] ; 1
%if ARCH_X86_32
lea srcq, [srcq+strideq*2]
movhps m3, [srcq+strideq*1] ; 1 _ 3
lea srcq, [srcq+strideq*2]
%else
movhps m3, [srcq+stride3q ] ; 1 _ 3
lea srcq, [srcq+strideq*4]
%endif
pshufd m2, m2, q2020 ; 0 2 0 2
pshufd m3, m3, q2020 ; 1 3 1 3
punpckldq m2, m3 ; 0 1 2 3
movd m3, [srcq+strideq*0] ; 4
movd m1, [srcq+strideq*1] ; 5
movd m0, [srcq+strideq*2] ; 6
%if ARCH_X86_32
lea srcq, [srcq+strideq*2]
add srcq, strideq
%else
add srcq, stride3q
%endif
punpckldq m3, m1 ; 4 5 _ _
punpckldq m1, m0 ; 5 6 _ _
palignr m4, m3, m2, 4 ; 1 2 3 4
punpcklbw m3, m1 ; 45 56
punpcklbw m1, m2, m4 ; 01 12
punpckhbw m2, m4 ; 23 34
.v_w4_loop:
pmaddubsw m5, m1, subpel0 ; a0 b0
mova m1, m2
pmaddubsw m2, subpel1 ; a1 b1
paddw m5, m2
mova m2, m3
pmaddubsw m3, subpel2 ; a2 b2
paddw m5, m3
movd m4, [srcq+strideq*0]
punpckldq m3, m0, m4 ; 6 7 _ _
movd m0, [srcq+strideq*1]
lea srcq, [srcq+strideq*2]
punpckldq m4, m0 ; 7 8 _ _
punpcklbw m3, m4 ; 67 78
pmaddubsw m4, m3, subpel3 ; a3 b3
paddw m5, m4
pmulhrsw m5, m7
movq [tmpq+wq*0], m5
movhps [tmpq+wq*2], m5
lea tmpq, [tmpq+wq*4]
sub hd, 2
jg .v_w4_loop
%if ARCH_X86_32
mov hw, r5w ; reset vertical loop
mov tmpq, tmpm
mov srcq, srcm
add tmpq, 8
add srcq, 4
mov tmpm, tmpq
mov srcm, srcq
sub r5d, 1<<16 ; horizontal--
jg .v_w4_loop0
%endif
RET
%if ARCH_X86_64
.v_w8:
.v_w16:
lea r5d, [wq - 8] ; horizontal loop
mov r8, tmpq
mov r6, srcq
shl r5d, 8 - 3; (wq / 8) << 8
mov r5b, hb
.v_w8_loop0:
movq m4, [srcq+strideq*0] ; 0
movq m5, [srcq+strideq*1] ; 1
lea srcq, [srcq+strideq*2]
movq m6, [srcq+strideq*0] ; 2
movq m0, [srcq+strideq*1] ; 3
lea srcq, [srcq+strideq*2]
movq m1, [srcq+strideq*0] ; 4
movq m2, [srcq+strideq*1] ; 5
lea srcq, [srcq+strideq*2] ;
movq m3, [srcq+strideq*0] ; 6
shufpd m4, m0, 0x0c
shufpd m5, m1, 0x0c
punpcklbw m1, m4, m5 ; 01
punpckhbw m4, m5 ; 34
shufpd m6, m2, 0x0c
punpcklbw m2, m5, m6 ; 12
punpckhbw m5, m6 ; 45
shufpd m0, m3, 0x0c
punpcklbw m3, m6, m0 ; 23
punpckhbw m6, m0 ; 56
.v_w8_loop:
movq m12, [srcq+strideq*1] ; 8
lea srcq, [srcq+strideq*2]
movq m13, [srcq+strideq*0] ; 9
pmaddubsw m14, m1, subpel0 ; a0
pmaddubsw m15, m2, subpel0 ; b0
mova m1, m3
mova m2, m4
pmaddubsw m3, subpel1 ; a1
pmaddubsw m4, subpel1 ; b1
paddw m14, m3
paddw m15, m4
mova m3, m5
mova m4, m6
pmaddubsw m5, subpel2 ; a2
pmaddubsw m6, subpel2 ; b2
paddw m14, m5
paddw m15, m6
shufpd m6, m0, m12, 0x0d
shufpd m0, m12, m13, 0x0c
punpcklbw m5, m6, m0 ; 67
punpckhbw m6, m0 ; 78
pmaddubsw m12, m5, subpel3 ; a3
pmaddubsw m13, m6, subpel3 ; b3
paddw m14, m12
paddw m15, m13
pmulhrsw m14, m7
pmulhrsw m15, m7
movu [tmpq+wq*0], xm14
movu [tmpq+wq*2], xm15
lea tmpq, [tmpq+wq*4]
sub hd, 2
jg .v_w8_loop
movzx hd, r5b ; reset vertical loop
add r8, 16
add r6, 8
mov tmpq, r8
mov srcq, r6
sub r5d, 1<<8 ; horizontal--
jg .v_w8_loop0
RET
%endif ;ARCH_X86_64
%undef subpel0
%undef subpel1
%undef subpel2
%undef subpel3
.hv:
%assign stack_offset org_stack_offset
cmp wd, 4
jg .hv_w8
and mxd, 0xff
movd m1, [base_reg+mxq*8+subpel_filters-prep_ssse3+2]
%if ARCH_X86_32
mov mxd, myd
and mxd, 0xff
shr myd, 16
cmp hd, 4
cmovle myd, mxd
movq m0, [base_reg+myq*8+subpel_filters-prep_ssse3]
mov r5, r2; use as new base
%define base_reg r5
%assign regs_used 2
ALLOC_STACK -mmsize*14
%assign regs_used 7
mov strideq, [rstk+stack_offset+gprsize*3]
lea strideq, [strideq*3 + 1]
sub [rstk+stack_offset+gprsize*2], strideq
mov strideq, [rstk+stack_offset+gprsize*3]
mov srcq, [rstk+stack_offset+gprsize*2]
%define subpelv0 [rsp+mmsize*0]
%define subpelv1 [rsp+mmsize*1]
%define subpelv2 [rsp+mmsize*2]
%define subpelv3 [rsp+mmsize*3]
punpcklbw m0, m0
psraw m0, 8 ; sign-extend
pshufd m6, m0, q0000
mova subpelv0, m6
pshufd m6, m0, q1111
mova subpelv1, m6
pshufd m6, m0, q2222
mova subpelv2, m6
pshufd m6, m0, q3333
mova subpelv3, m6
%else
movzx mxd, myb
shr myd, 16
cmp hd, 4
cmovle myd, mxd
movq m0, [base_reg+myq*8+subpel_filters-prep_ssse3]
ALLOC_STACK mmsize*14, 14
lea stride3q, [strideq*3]
sub srcq, stride3q
dec srcq
%define subpelv0 m10
%define subpelv1 m11
%define subpelv2 m12
%define subpelv3 m13
punpcklbw m0, m0
psraw m0, 8 ; sign-extend
mova m8, [base+pw_8192]
mova m9, [base+pd_32]
pshufd m10, m0, q0000
pshufd m11, m0, q1111
pshufd m12, m0, q2222
pshufd m13, m0, q3333
%endif
pshufd m7, m1, q0000
.hv_w4:
%define hv4_line_0_0 4
%define hv4_line_0_1 5
%define hv4_line_0_2 6
%define hv4_line_0_3 7
%define hv4_line_0_4 8
%define hv4_line_0_5 9
%define hv4_line_1_0 10
%define hv4_line_1_1 11
%define hv4_line_1_2 12
%define hv4_line_1_3 13
;
;
%if ARCH_X86_32
%define w8192reg [base+pw_8192]
%define d32reg [base+pd_32]
%else
%define w8192reg m8
%define d32reg m9
%endif
; lower shuffle 0 1 2 3 4
mova m6, [base+subpel_h_shuf4]
movq m5, [srcq+strideq*0] ; 0 _ _ _
movhps m5, [srcq+strideq*1] ; 0 _ 1 _
movq m4, [srcq+strideq*2] ; 2 _ _ _
%if ARCH_X86_32
lea srcq, [srcq+strideq*2]
add srcq, strideq
movhps m4, [srcq+strideq*0] ; 2 _ 3 _
add srcq, strideq
%else
movhps m4, [srcq+stride3q ] ; 2 _ 3 _
lea srcq, [srcq+strideq*4]
%endif
pshufb m2, m5, m6 ;H subpel_h_shuf4 0 ~ 1 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 2 ~ 3 ~
pmaddubsw m2, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m2, m0 ;H 0 1 2 3
pmulhrsw m2, w8192reg ;H pw_8192
SAVELINE_W4 m2, 2, 0
; upper shuffle 2 3 4 5 6
mova m6, [base+subpel_h_shuf4+16]
pshufb m2, m5, m6 ;H subpel_h_shuf4 0 ~ 1 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 2 ~ 3 ~
pmaddubsw m2, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m2, m0 ;H 0 1 2 3
pmulhrsw m2, w8192reg ;H pw_8192
;
; lower shuffle
mova m6, [base+subpel_h_shuf4]
movq m5, [srcq+strideq*0] ; 4 _ _ _
movhps m5, [srcq+strideq*1] ; 4 _ 5 _
movq m4, [srcq+strideq*2] ; 6 _ _ _
pshufb m3, m5, m6 ;H subpel_h_shuf4 4 ~ 5 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 6 ~ 6 ~
pmaddubsw m3, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m3, m0 ;H 4 5 6 7
pmulhrsw m3, w8192reg ;H pw_8192
SAVELINE_W4 m3, 3, 0
; upper shuffle
mova m6, [base+subpel_h_shuf4+16]
pshufb m3, m5, m6 ;H subpel_h_shuf4 4 ~ 5 ~
pshufb m0, m4, m6 ;H subpel_h_shuf4 6 ~ 6 ~
pmaddubsw m3, m7 ;H subpel_filters
pmaddubsw m0, m7 ;H subpel_filters
phaddw m3, m0 ;H 4 5 6 7
pmulhrsw m3, w8192reg ;H pw_8192
;
%if ARCH_X86_32
lea srcq, [srcq+strideq*2]
add srcq, strideq
%else
add srcq, stride3q
%endif
;process high
palignr m4, m3, m2, 4;V 1 2 3 4
punpcklwd m1, m2, m4 ; V 01 12
punpckhwd m2, m4 ; V 23 34
pshufd m0, m3, q2121;V 5 6 5 6
punpcklwd m3, m0 ; V 45 56
SAVELINE_W4 m0, 0, 1
SAVELINE_W4 m1, 1, 1
SAVELINE_W4 m2, 2, 1
SAVELINE_W4 m3, 3, 1
;process low
RESTORELINE_W4 m2, 2, 0
RESTORELINE_W4 m3, 3, 0
palignr m4, m3, m2, 4;V 1 2 3 4
punpcklwd m1, m2, m4 ; V 01 12
punpckhwd m2, m4 ; V 23 34
pshufd m0, m3, q2121;V 5 6 5 6
punpcklwd m3, m0 ; V 45 56
.hv_w4_loop:
;process low
pmaddwd m5, m1, subpelv0 ; V a0 b0
mova m1, m2
pmaddwd m2, subpelv1; V a1 b1
paddd m5, m2
mova m2, m3
pmaddwd m3, subpelv2; V a2 b2
paddd m5, m3
;
mova m6, [base+subpel_h_shuf4]
movq m4, [srcq+strideq*0] ; 7
movhps m4, [srcq+strideq*1] ; 7 _ 8 _
pshufb m4, m6 ;H subpel_h_shuf4 7 ~ 8 ~
pmaddubsw m4, m7 ;H subpel_filters
phaddw m4, m4 ;H 7 8 7 8
pmulhrsw m4, w8192reg ;H pw_8192
palignr m3, m4, m0, 12 ; 6 7 8 7
mova m0, m4
punpcklwd m3, m4 ; 67 78
pmaddwd m4, m3, subpelv3; a3 b3
paddd m5, d32reg ; pd_32
paddd m5, m4
psrad m5, 6
SAVELINE_W4 m0, 0, 0
SAVELINE_W4 m1, 1, 0
SAVELINE_W4 m2, 2, 0
SAVELINE_W4 m3, 3, 0
SAVELINE_W4 m5, 5, 0
;process high
RESTORELINE_W4 m0, 0, 1
RESTORELINE_W4 m1, 1, 1
RESTORELINE_W4 m2, 2, 1
RESTORELINE_W4 m3, 3, 1
pmaddwd m5, m1, subpelv0; V a0 b0
mova m1, m2
pmaddwd m2, subpelv1; V a1 b1
paddd m5, m2
mova m2, m3
pmaddwd m3, subpelv2; V a2 b2
paddd m5, m3
;
mova m6, [base+subpel_h_shuf4+16]
movq m4, [srcq+strideq*0] ; 7
movhps m4, [srcq+strideq*1] ; 7 _ 8 _
pshufb m4, m6 ;H subpel_h_shuf4 7 ~ 8 ~
pmaddubsw m4, m7 ;H subpel_filters
phaddw m4, m4 ;H 7 8 7 8
pmulhrsw m4, w8192reg ;H pw_8192
palignr m3, m4, m0, 12 ; 6 7 8 7
mova m0, m4
punpcklwd m3, m4 ; 67 78
pmaddwd m4, m3, subpelv3; a3 b3
paddd m5, d32reg ; pd_32
paddd m5, m4
psrad m4, m5, 6
;
RESTORELINE_W4 m5, 5, 0
packssdw m5, m4
pshufd m5, m5, q3120
movu [tmpq], m5
lea srcq, [srcq+strideq*2]
add tmpq, 16
sub hd, 2
SAVELINE_W4 m0, 0, 1
SAVELINE_W4 m1, 1, 1
SAVELINE_W4 m2, 2, 1
SAVELINE_W4 m3, 3, 1
RESTORELINE_W4 m0, 0, 0
RESTORELINE_W4 m1, 1, 0
RESTORELINE_W4 m2, 2, 0
RESTORELINE_W4 m3, 3, 0
jg .hv_w4_loop
RET
%undef subpelv0
%undef subpelv1
%undef subpelv2
%undef subpelv3
;
.hv_w8:
%assign stack_offset org_stack_offset
%define hv8_line_1 0
%define hv8_line_2 1
%define hv8_line_3 2
%define hv8_line_4 3
%define hv8_line_6 4
shr mxd, 16
%if ARCH_X86_32
%define base_reg r2
%define subpelh0 [rsp+mmsize*5]
%define subpelh1 [rsp+mmsize*6]
%define subpelv0 [rsp+mmsize*7]
%define subpelv1 [rsp+mmsize*8]
%define subpelv2 [rsp+mmsize*9]
%define subpelv3 [rsp+mmsize*10]
%define accuv0 [rsp+mmsize*11]
%define accuv1 [rsp+mmsize*12]
movq m1, [base_reg+mxq*8+subpel_filters-prep_ssse3]
movzx mxd, myw
and mxd, 0xff
shr myd, 16
cmp hd, 4
cmovle myd, mxd
movq m5, [base_reg+myq*8+subpel_filters-prep_ssse3]
ALLOC_STACK -mmsize*13
%if STACK_ALIGNMENT < mmsize
mov rstk, r2m
%define tmpm [rsp+mmsize*13+gprsize*1]
%define srcm [rsp+mmsize*13+gprsize*2]
%define stridem [rsp+mmsize*13+gprsize*3]
mov stridem, rstk
%endif
mov r6, r2
%define base_reg r6
pshufd m0, m1, q0000
pshufd m1, m1, q1111
punpcklbw m5, m5
psraw m5, 8 ; sign-extend
pshufd m2, m5, q0000
pshufd m3, m5, q1111
pshufd m4, m5, q2222
pshufd m5, m5, q3333
mova subpelh0, m0
mova subpelh1, m1
mova subpelv0, m2
mova subpelv1, m3
mova subpelv2, m4
mova subpelv3, m5
W32_RESTORE_SSQ
lea strided, [strided*3]
sub srcd, strided
sub srcd, 3
mov srcm, srcd
W32_RESTORE_SSQ
%else
ALLOC_STACK mmsize*5, 16
%define subpelh0 m10
%define subpelh1 m11
%define subpelv0 m12
%define subpelv1 m13
%define subpelv2 m14
%define subpelv3 m15
%define accuv0 m8
%define accuv1 m9
movq m0, [base_reg+mxq*8+subpel_filters-prep_ssse3]
movzx mxd, myb
shr myd, 16
cmp hd, 4
cmovle myd, mxd
movq m1, [base_reg+myq*8+subpel_filters-prep_ssse3]
pshufd subpelh0, m0, q0000
pshufd subpelh1, m0, q1111
punpcklbw m1, m1
psraw m1, 8 ; sign-extend
pshufd subpelv0, m1, q0000
pshufd subpelv1, m1, q1111
pshufd subpelv2, m1, q2222
pshufd subpelv3, m1, q3333
lea stride3q, [strideq*3]
sub srcq, 3
sub srcq, stride3q
mov r6, srcq
%endif
lea r5d, [wq-4]
%if ARCH_X86_64
mov r8, tmpq
%else
mov tmpm, tmpq
%endif
shl r5d, (16 - 2)
mov r5w, hw
.hv_w8_loop0:
movu m4, [srcq+strideq*0] ; 0 = _ _
movu m5, [srcq+strideq*1] ; 1 = _ _
lea srcq, [srcq+strideq*2]
%if ARCH_X86_64
mova m7, [base+subpel_h_shufA]
mova m8, [base+subpel_h_shufB]
mova m9, [base+subpel_h_shufC]
%endif
HV_H_W8 m4, m1, m2, m3, m7, m8, m9 ; 0 ~ ~ ~
HV_H_W8 m5, m1, m2, m3, m7, m8, m9 ; 1 ~ ~ ~
movu m6, [srcq+strideq*0] ; 2 = _ _
movu m0, [srcq+strideq*1] ; 3 = _ _
lea srcq, [srcq+strideq*2]
HV_H_W8 m6, m1, m2, m3, m7, m8, m9 ; 2 ~ ~ ~
HV_H_W8 m0, m1, m2, m3, m7, m8, m9 ; 3 ~ ~ ~
;
mova m7, [base+pw_8192]
pmulhrsw m4, m7 ; H pw_8192
pmulhrsw m5, m7 ; H pw_8192
pmulhrsw m6, m7 ; H pw_8192
pmulhrsw m0, m7 ; H pw_8192
punpcklwd m1, m4, m5 ; 0 1 ~
punpcklwd m2, m5, m6 ; 1 2 ~
punpcklwd m3, m6, m0 ; 2 3 ~
SAVELINE_W8 1, m1
SAVELINE_W8 2, m2
SAVELINE_W8 3, m3
;
mova m7, [base+subpel_h_shufA]
movu m4, [srcq+strideq*0] ; 4 = _ _
movu m5, [srcq+strideq*1] ; 5 = _ _
lea srcq, [srcq+strideq*2]
movu m6, [srcq+strideq*0] ; 6 = _ _
HV_H_W8 m4, m1, m2, m3, m7, m8, m9 ; 4 ~ ~ ~
HV_H_W8 m5, m1, m2, m3, m7, m8, m9 ; 5 ~ ~ ~
HV_H_W8 m6, m1, m2, m3, m7, m8, m9 ; 6 ~ ~ ~
mova m7, [base+pw_8192]
pmulhrsw m1, m4, m7 ; H pw_8192 4 ~
pmulhrsw m2, m5, m7 ; H pw_8192 5 ~
pmulhrsw m3, m6, m7 ; H pw_8192 6 ~
punpcklwd m4, m0, m1 ; 3 4 ~
punpcklwd m5, m1, m2 ; 4 5 ~
punpcklwd m6, m2, m3 ; 5 6 ~
;
SAVELINE_W8 6, m3
RESTORELINE_W8 1, m1
RESTORELINE_W8 2, m2
RESTORELINE_W8 3, m3
.hv_w8_loop:
; m8 accu for V a
; m9 accu for V b
SAVELINE_W8 1, m3
SAVELINE_W8 2, m4
SAVELINE_W8 3, m5
SAVELINE_W8 4, m6
%if ARCH_X86_32
pmaddwd m0, m1, subpelv0 ; a0
pmaddwd m7, m2, subpelv0 ; b0
pmaddwd m3, subpelv1 ; a1
pmaddwd m4, subpelv1 ; b1
paddd m0, m3
paddd m7, m4
pmaddwd m5, subpelv2 ; a2
pmaddwd m6, subpelv2 ; b2
paddd m0, m5
paddd m7, m6
mova m5, [base+pd_32]
paddd m0, m5 ; pd_512
paddd m7, m5 ; pd_512
mova accuv0, m0
mova accuv1, m7
%else
pmaddwd m8, m1, subpelv0 ; a0
pmaddwd m9, m2, subpelv0 ; b0
pmaddwd m3, subpelv1 ; a1
pmaddwd m4, subpelv1 ; b1
paddd m8, m3
paddd m9, m4
pmaddwd m5, subpelv2 ; a2
pmaddwd m6, subpelv2 ; b2
paddd m8, m5
paddd m9, m6
mova m7, [base+pd_32]
paddd m8, m7 ; pd_512
paddd m9, m7 ; pd_512
mova m7, [base+subpel_h_shufB]
mova m6, [base+subpel_h_shufC]
mova m5, [base+subpel_h_shufA]
%endif
movu m0, [srcq+strideq*1] ; 7
movu m4, [srcq+strideq*2] ; 8
lea srcq, [srcq+strideq*2]
HV_H_W8 m0, m1, m2, m3, m5, m7, m6
HV_H_W8 m4, m1, m2, m3, m5, m7, m6
mova m5, [base+pw_8192]
pmulhrsw m0, m5 ; H pw_8192
pmulhrsw m4, m5 ; H pw_8192
RESTORELINE_W8 6, m6
punpcklwd m5, m6, m0 ; 6 7 ~
punpcklwd m6, m0, m4 ; 7 8 ~
pmaddwd m1, m5, subpelv3 ; a3
paddd m2, m1, accuv0
pmaddwd m1, m6, subpelv3 ; b3
paddd m1, m1, accuv1 ; H + V
psrad m2, 6
psrad m1, 6
packssdw m2, m1 ; d -> w
movq [tmpq+wq*0], m2
movhps [tmpq+wq*2], m2
lea tmpq, [tmpq+wq*4]
sub hd, 2
jle .hv_w8_outer
SAVELINE_W8 6, m4
RESTORELINE_W8 1, m1
RESTORELINE_W8 2, m2
RESTORELINE_W8 3, m3
RESTORELINE_W8 4, m4
jmp .hv_w8_loop
.hv_w8_outer:
movzx hd, r5w
%if ARCH_X86_32
add dword tmpm, 8
mov tmpq, tmpm
mov srcq, srcm
add srcq, 4
mov srcm, srcq
%else
add r8, 8
mov tmpq, r8
add r6, 4
mov srcq, r6
%endif
sub r5d, 1<<16
jg .hv_w8_loop0
RET
%if ARCH_X86_32
%macro SAVE_ALPHA_BETA 0
mov alpham, alphad
mov betam, betad
%endmacro
%macro SAVE_DELTA_GAMMA 0
mov deltam, deltad
mov gammam, gammad
%endmacro
%macro LOAD_ALPHA_BETA_MX 0
mov mym, myd
mov alphad, alpham
mov betad, betam
mov mxd, mxm
%endmacro
%macro LOAD_DELTA_GAMMA_MY 0
mov mxm, mxd
mov deltad, deltam
mov gammad, gammam
mov myd, mym
%endmacro
%define PIC_reg r2
%define PIC_base_offset $$
%define PIC_sym(sym) (PIC_reg+(sym)-PIC_base_offset)
%else
%define SAVE_ALPHA_BETA
%define SAVE_DELTA_GAMMA
%define PIC_sym(sym) sym
%endif
%if ARCH_X86_32
%if STACK_ALIGNMENT < required_stack_alignment
%assign copy_args 8*4
%else
%assign copy_args 0
%endif
%endif
%macro RELOC_ARGS 0
%if copy_args
mov r0, r0m
mov r1, r1m
mov r2, r2m
mov r3, r3m
mov r5, r5m
mov dstm, r0
mov dsm, r1
mov srcm, r2
mov ssm, r3
mov mxm, r5
mov r0, r6m
mov mym, r0
%endif
%endmacro
%macro BLENDHWDW 2 ; blend high words from dwords, src1, src2
%if cpuflag(sse4)
pblendw %1, %2, 0xAA
%else
pand %2, m10
por %1, %2
%endif
%endmacro
%macro WARP_V 10 ; dst0, dst1, 0, 2, 4, 6, 1, 3, 5, 7
; Can be done using gathers, but that's terribly slow on many CPU:s
%if ARCH_X86_32
%define m8 m4
%define m9 m5
%define m14 m6
%define m15 m7
%define m11 m7
%endif
%if notcpuflag(ssse3) || ARCH_X86_32
pxor m11, m11
%endif
lea tmp1d, [myq+deltaq*4]
lea tmp2d, [myq+deltaq*1]
shr myd, 10
shr tmp1d, 10
movq m2, [filterq+myq *8] ; a
movq m8, [filterq+tmp1q*8] ; e
lea tmp1d, [tmp2q+deltaq*4]
lea myd, [tmp2q+deltaq*1]
shr tmp2d, 10
shr tmp1d, 10
movq m3, [filterq+tmp2q*8] ; b
movq m0, [filterq+tmp1q*8] ; f
punpcklwd m2, m3
punpcklwd m8, m0
lea tmp1d, [myq+deltaq*4]
lea tmp2d, [myq+deltaq*1]
shr myd, 10
shr tmp1d, 10
movq m0, [filterq+myq *8] ; c
movq m9, [filterq+tmp1q*8] ; g
lea tmp1d, [tmp2q+deltaq*4]
lea myd, [tmp2q+gammaq] ; my += gamma
shr tmp2d, 10
shr tmp1d, 10
movq m3, [filterq+tmp2q*8] ; d
movq m1, [filterq+tmp1q*8] ; h
punpcklwd m0, m3
punpcklwd m9, m1
punpckldq m1, m2, m0
punpckhdq m2, m0
punpcklbw m0, m11, m1 ; a0 a2 b0 b2 c0 c2 d0 d2 << 8
punpckhbw m3, m11, m1 ; a4 a6 b4 b6 c4 c6 d4 d6 << 8
punpcklbw m1, m11, m2 ; a1 a3 b1 b3 c1 c3 d1 d3 << 8
punpckhbw m14, m11, m2 ; a5 a7 b5 b7 c5 c7 d5 d7 << 8
pmaddwd m0, %3
pmaddwd m3, %5
pmaddwd m1, %7
pmaddwd m14, %9
paddd m0, m3
paddd m1, m14
paddd m0, m1
mova %1, m0
%if ARCH_X86_64
SWAP m3, m14
%endif
punpckldq m0, m8, m9
punpckhdq m8, m9
punpcklbw m1, m11, m0 ; e0 e2 f0 f2 g0 g2 h0 h2 << 8
punpckhbw m14, m11, m0 ; e4 e6 f4 f6 g4 g6 h4 h6 << 8
punpcklbw m2, m11, m8 ; e1 e3 f1 f3 g1 g3 h1 h3 << 8
punpckhbw m15, m11, m8 ; e5 e7 f5 f7 g5 g7 h5 h7 << 8
pmaddwd m1, %4
pmaddwd m14, %6
pmaddwd m2, %8
pmaddwd m15, %10
paddd m1, m14
paddd m2, m15
paddd m1, m2
mova %2, m1
%if ARCH_X86_64
SWAP m14, m3
%endif
%endmacro
%if ARCH_X86_64
%define counterd r4d
%else
%if copy_args == 0
%define counterd dword r4m
%else
%define counterd dword [esp+stack_size-4*7]
%endif
%endif
%macro WARP_AFFINE_8X8T 0
%if ARCH_X86_64
cglobal warp_affine_8x8t, 6, 14, 16, 0x90, tmp, ts
%else
cglobal warp_affine_8x8t, 0, 7, 16, -0x130-copy_args, tmp, ts
%if copy_args
%define tmpm [esp+stack_size-4*1]
%define tsm [esp+stack_size-4*2]
%endif
%endif
call mangle(private_prefix %+ _warp_affine_8x8_%+cpuname).main
.loop:
%if ARCH_X86_32
%define m12 m4
%define m13 m5
%define m14 m6
%define m15 m7
mova m12, [esp+0xC0]
mova m13, [esp+0xD0]
mova m14, [esp+0xE0]
mova m15, [esp+0xF0]
%endif
%if cpuflag(ssse3)
psrad m12, 13
psrad m13, 13
psrad m14, 13
psrad m15, 13
packssdw m12, m13
packssdw m14, m15
mova m13, [PIC_sym(pw_8192)]
pmulhrsw m12, m13 ; (x + (1 << 6)) >> 7
pmulhrsw m14, m13
%else
%if ARCH_X86_32
%define m10 m0
%endif
mova m10, [PIC_sym(pd_16384)]
paddd m12, m10
paddd m13, m10
paddd m14, m10
paddd m15, m10
psrad m12, 15
psrad m13, 15
psrad m14, 15
psrad m15, 15
packssdw m12, m13
packssdw m14, m15
%endif
mova [tmpq+tsq*0], m12
mova [tmpq+tsq*2], m14
dec counterd
jz mangle(private_prefix %+ _warp_affine_8x8_%+cpuname).end
%if ARCH_X86_32
mov tmpm, tmpd
mov r0, [esp+0x100]
mov r1, [esp+0x104]
%endif
call mangle(private_prefix %+ _warp_affine_8x8_%+cpuname).main2
lea tmpq, [tmpq+tsq*4]
jmp .loop
%endmacro
%macro WARP_AFFINE_8X8 0
%if ARCH_X86_64
cglobal warp_affine_8x8, 6, 14, 16, 0x90, \
dst, ds, src, ss, abcd, mx, tmp2, alpha, beta, \
filter, tmp1, delta, my, gamma
%else
cglobal warp_affine_8x8, 0, 7, 16, -0x130-copy_args, \
dst, ds, src, ss, abcd, mx, tmp2, alpha, beta, \
filter, tmp1, delta, my, gamma
%define alphaq r0
%define alphad r0
%define alpham [esp+gprsize+0x100]
%define betaq r1
%define betad r1
%define betam [esp+gprsize+0x104]
%define deltaq r0
%define deltad r0
%define deltam [esp+gprsize+0x108]
%define gammaq r1
%define gammad r1
%define gammam [esp+gprsize+0x10C]
%define filterq r3
%define tmp1q r4
%define tmp1d r4
%define tmp1m [esp+gprsize+0x110]
%define myq r5
%define myd r5
%define mym r6m
%if copy_args
%define dstm [esp+stack_size-4*1]
%define dsm [esp+stack_size-4*2]
%define srcm [esp+stack_size-4*3]
%define ssm [esp+stack_size-4*4]
%define mxm [esp+stack_size-4*5]
%define mym [esp+stack_size-4*6]
%endif
%endif
call .main
jmp .start
.loop:
%if ARCH_X86_32
mov dstm, dstd
mov alphad, [esp+0x100]
mov betad, [esp+0x104]
%endif
call .main2
lea dstq, [dstq+dsq*2]
.start:
%if notcpuflag(sse4)
%if cpuflag(ssse3)
%define roundval pw_8192
%else
%define roundval pd_262144
%endif
%if ARCH_X86_64
mova m10, [PIC_sym(roundval)]
%else
%define m10 [PIC_sym(roundval)]
%endif
%endif
%if ARCH_X86_32
%define m12 m5
%define m13 m6
mova m12, [esp+0xC0]
mova m13, [esp+0xD0]
%endif
%if cpuflag(sse4)
%if ARCH_X86_32
%define m11 m4
pxor m11, m11
%endif
psrad m12, 18
psrad m13, 18
packusdw m12, m13
pavgw m12, m11 ; (x + (1 << 10)) >> 11
%else
%if cpuflag(ssse3)
psrad m12, 17
psrad m13, 17
packssdw m12, m13
pmulhrsw m12, m10
%else
paddd m12, m10
paddd m13, m10
psrad m12, 19
psrad m13, 19
packssdw m12, m13
%endif
%endif
%if ARCH_X86_32
%define m14 m6
%define m15 m7
mova m14, [esp+0xE0]
mova m15, [esp+0xF0]
%endif
%if cpuflag(sse4)
psrad m14, 18
psrad m15, 18
packusdw m14, m15
pavgw m14, m11 ; (x + (1 << 10)) >> 11
%else
%if cpuflag(ssse3)
psrad m14, 17
psrad m15, 17
packssdw m14, m15
pmulhrsw m14, m10
%else
paddd m14, m10
paddd m15, m10
psrad m14, 19
psrad m15, 19
packssdw m14, m15
%endif
%endif
packuswb m12, m14
movq [dstq+dsq*0], m12
movhps [dstq+dsq*1], m12
dec counterd
jg .loop
.end:
RET
ALIGN function_align
.main:
%assign stack_offset stack_offset+gprsize
%if ARCH_X86_32
%assign stack_size stack_size+4
%if copy_args
%assign stack_offset stack_offset-4
%endif
RELOC_ARGS
LEA PIC_reg, $$
%define PIC_mem [esp+gprsize+0x114]
mov abcdd, abcdm
%if copy_args == 0
mov ssd, ssm
mov mxd, mxm
%endif
mov PIC_mem, PIC_reg
mov srcd, srcm
%endif
movsx deltad, word [abcdq+2*2]
movsx gammad, word [abcdq+2*3]
lea tmp1d, [deltaq*3]
sub gammad, tmp1d ; gamma -= delta*3
SAVE_DELTA_GAMMA
%if ARCH_X86_32
mov abcdd, abcdm
%endif
movsx alphad, word [abcdq+2*0]
movsx betad, word [abcdq+2*1]
lea tmp1q, [ssq*3+3]
add mxd, 512+(64<<10)
lea tmp2d, [alphaq*3]
sub srcq, tmp1q ; src -= src_stride*3 + 3
%if ARCH_X86_32
mov srcm, srcd
mov PIC_reg, PIC_mem
%endif
sub betad, tmp2d ; beta -= alpha*3
lea filterq, [PIC_sym(mc_warp_filter)]
%if ARCH_X86_64
mov myd, r6m
%if cpuflag(ssse3)
pxor m11, m11
%endif
%endif
call .h
psrld m2, m0, 16
psrld m3, m1, 16
%if ARCH_X86_32
%if notcpuflag(ssse3)
mova [esp+gprsize+0x00], m2
%endif
mova [esp+gprsize+0x10], m3
%endif
call .h
psrld m4, m0, 16
psrld m5, m1, 16
%if ARCH_X86_32
mova [esp+gprsize+0x20], m4
mova [esp+gprsize+0x30], m5
%endif
call .h
%if ARCH_X86_64
%define blendmask [rsp+gprsize+0x80]
%else
%if notcpuflag(ssse3)
mova m2, [esp+gprsize+0x00]
%endif
mova m3, [esp+gprsize+0x10]
%define blendmask [esp+gprsize+0x120]
%define m10 m7
%endif
pcmpeqd m10, m10
pslld m10, 16
mova blendmask, m10
BLENDHWDW m2, m0 ; 0
BLENDHWDW m3, m1 ; 2
mova [rsp+gprsize+0x00], m2
mova [rsp+gprsize+0x10], m3
call .h
%if ARCH_X86_32
mova m4, [esp+gprsize+0x20]
mova m5, [esp+gprsize+0x30]
%endif
mova m10, blendmask
BLENDHWDW m4, m0 ; 1
BLENDHWDW m5, m1 ; 3
mova [rsp+gprsize+0x20], m4
mova [rsp+gprsize+0x30], m5
call .h
%if ARCH_X86_32
%if notcpuflag(ssse3)
mova m2, [esp+gprsize+0x00]
%endif
mova m3, [esp+gprsize+0x10]
%define m10 m5
%endif
psrld m6, m2, 16
psrld m7, m3, 16
mova m10, blendmask
BLENDHWDW m6, m0 ; 2
BLENDHWDW m7, m1 ; 4
mova [rsp+gprsize+0x40], m6
mova [rsp+gprsize+0x50], m7
call .h
%if ARCH_X86_32
mova m4, [esp+gprsize+0x20]
mova m5, [esp+gprsize+0x30]
%endif
psrld m2, m4, 16
psrld m3, m5, 16
mova m10, blendmask
BLENDHWDW m2, m0 ; 3
BLENDHWDW m3, m1 ; 5
mova [rsp+gprsize+0x60], m2
mova [rsp+gprsize+0x70], m3
call .h
%if ARCH_X86_32
mova m6, [esp+gprsize+0x40]
mova m7, [esp+gprsize+0x50]
%define m10 m7
%endif
psrld m4, m6, 16
psrld m5, m7, 16
mova m10, blendmask
BLENDHWDW m4, m0 ; 4
BLENDHWDW m5, m1 ; 6
%if ARCH_X86_64
add myd, 512+(64<<10)
mova m6, m2
mova m7, m3
%else
mova [esp+gprsize+0x80], m4
mova [esp+gprsize+0x90], m5
add dword mym, 512+(64<<10)
%endif
mov counterd, 4
SAVE_ALPHA_BETA
.main2:
call .h
%if ARCH_X86_32
mova m6, [esp+gprsize+0x60]
mova m7, [esp+gprsize+0x70]
%define m10 m5
%endif
psrld m6, 16
psrld m7, 16
mova m10, blendmask
BLENDHWDW m6, m0 ; 5
BLENDHWDW m7, m1 ; 7
%if ARCH_X86_64
WARP_V m12, m13, [rsp+gprsize+0x00], [rsp+gprsize+0x10], \
m4, m5, \
[rsp+gprsize+0x20], [rsp+gprsize+0x30], \
m6, m7
%else
mova [esp+gprsize+0xA0], m6
mova [esp+gprsize+0xB0], m7
LOAD_DELTA_GAMMA_MY
WARP_V [esp+gprsize+0xC0], [esp+gprsize+0xD0], \
[esp+gprsize+0x00], [esp+gprsize+0x10], \
[esp+gprsize+0x80], [esp+gprsize+0x90], \
[esp+gprsize+0x20], [esp+gprsize+0x30], \
[esp+gprsize+0xA0], [esp+gprsize+0xB0]
LOAD_ALPHA_BETA_MX
%endif
call .h
mova m2, [rsp+gprsize+0x40]
mova m3, [rsp+gprsize+0x50]
%if ARCH_X86_32
mova m4, [rsp+gprsize+0x80]
mova m5, [rsp+gprsize+0x90]
%define m10 m7
%endif
mova [rsp+gprsize+0x00], m2
mova [rsp+gprsize+0x10], m3
mova [rsp+gprsize+0x40], m4
mova [rsp+gprsize+0x50], m5
psrld m4, 16
psrld m5, 16
mova m10, blendmask
BLENDHWDW m4, m0 ; 6
BLENDHWDW m5, m1 ; 8
%if ARCH_X86_64
WARP_V m14, m15, [rsp+gprsize+0x20], [rsp+gprsize+0x30], \
m6, m7, \
[rsp+gprsize+0x00], [rsp+gprsize+0x10], \
m4, m5
%else
mova [esp+gprsize+0x80], m4
mova [esp+gprsize+0x90], m5
LOAD_DELTA_GAMMA_MY
WARP_V [esp+gprsize+0xE0], [esp+gprsize+0xF0], \
[esp+gprsize+0x20], [esp+gprsize+0x30], \
[esp+gprsize+0xA0], [esp+gprsize+0xB0], \
[esp+gprsize+0x00], [esp+gprsize+0x10], \
[esp+gprsize+0x80], [esp+gprsize+0x90]
mov mym, myd
mov dstd, dstm
mov dsd, dsm
mov mxd, mxm
%endif
mova m2, [rsp+gprsize+0x60]
mova m3, [rsp+gprsize+0x70]
%if ARCH_X86_32
mova m6, [esp+gprsize+0xA0]
mova m7, [esp+gprsize+0xB0]
%endif
mova [rsp+gprsize+0x20], m2
mova [rsp+gprsize+0x30], m3
mova [rsp+gprsize+0x60], m6
mova [rsp+gprsize+0x70], m7
ret
ALIGN function_align
.h:
%if ARCH_X86_32
%define m8 m3
%define m9 m4
%define m10 m5
%define m14 m6
%define m15 m7
%endif
lea tmp1d, [mxq+alphaq*4]
lea tmp2d, [mxq+alphaq*1]
%if ARCH_X86_32
%assign stack_offset stack_offset+4
%assign stack_size stack_size+4
%define PIC_mem [esp+gprsize*2+0x114]
mov PIC_mem, PIC_reg
mov srcd, srcm
%endif
movu m10, [srcq]
%if ARCH_X86_32
add srcd, ssm
mov srcm, srcd
mov PIC_reg, PIC_mem
%else
add srcq, ssq
%endif
shr mxd, 10
shr tmp1d, 10
movq m1, [filterq+mxq *8] ; 0 X
movq m8, [filterq+tmp1q*8] ; 4 X
lea tmp1d, [tmp2q+alphaq*4]
lea mxd, [tmp2q+alphaq*1]
shr tmp2d, 10
shr tmp1d, 10
movhps m1, [filterq+tmp2q*8] ; 0 1
movhps m8, [filterq+tmp1q*8] ; 4 5
lea tmp1d, [mxq+alphaq*4]
lea tmp2d, [mxq+alphaq*1]
shr mxd, 10
shr tmp1d, 10
%if cpuflag(ssse3)
movq m14, [filterq+mxq *8] ; 2 X
movq m9, [filterq+tmp1q*8] ; 6 X
lea tmp1d, [tmp2q+alphaq*4]
lea mxd, [tmp2q+betaq] ; mx += beta
shr tmp2d, 10
shr tmp1d, 10
movhps m14, [filterq+tmp2q*8] ; 2 3
movhps m9, [filterq+tmp1q*8] ; 6 7
pshufb m0, m10, [PIC_sym(warp_8x8_shufA)]
pmaddubsw m0, m1
pshufb m1, m10, [PIC_sym(warp_8x8_shufB)]
pmaddubsw m1, m8
pshufb m15, m10, [PIC_sym(warp_8x8_shufC)]
pmaddubsw m15, m14
pshufb m10, m10, [PIC_sym(warp_8x8_shufD)]
pmaddubsw m10, m9
phaddw m0, m15
phaddw m1, m10
%else
%if ARCH_X86_32
%define m11 m2
%endif
pcmpeqw m0, m0
psrlw m14, m0, 8
psrlw m15, m10, 8 ; 01 03 05 07 09 11 13 15
pand m14, m10 ; 00 02 04 06 08 10 12 14
packuswb m14, m15 ; 00 02 04 06 08 10 12 14 01 03 05 07 09 11 13 15
psrldq m9, m0, 4
pshufd m0, m14, q0220
pand m0, m9
psrldq m14, 1 ; 02 04 06 08 10 12 14 01 03 05 07 09 11 13 15 __
pslldq m15, m14, 12
por m0, m15 ; shufA
psrlw m15, m0, 8
psraw m11, m1, 8
psllw m0, 8
psllw m1, 8
psrlw m0, 8
psraw m1, 8
pmullw m15, m11
pmullw m0, m1
paddw m0, m15 ; pmaddubsw m0, m1
pshufd m15, m14, q0220
pand m15, m9
psrldq m14, 1 ; 04 06 08 10 12 14 01 03 05 07 09 11 13 15 __ __
pslldq m1, m14, 12
por m15, m1 ; shufC
pshufd m1, m14, q0220
pand m1, m9
psrldq m14, 1 ; 06 08 10 12 14 01 03 05 07 09 11 13 15 __ __ __
pslldq m11, m14, 12
por m1, m11 ; shufB
pshufd m10, m14, q0220
pand m10, m9
psrldq m14, 1 ; 08 10 12 14 01 03 05 07 09 11 13 15 __ __ __ __
pslldq m14, m14, 12
por m10, m14 ; shufD
psrlw m9, m1, 8
psraw m11, m8, 8
psllw m1, 8
psllw m8, 8
psrlw m1, 8
psraw m8, 8
pmullw m9, m11
pmullw m1, m8
paddw m1, m9 ; pmaddubsw m1, m8
movq m14, [filterq+mxq *8] ; 2 X
movq m9, [filterq+tmp1q*8] ; 6 X
lea tmp1d, [tmp2q+alphaq*4]
lea mxd, [tmp2q+betaq] ; mx += beta
shr tmp2d, 10
shr tmp1d, 10
movhps m14, [filterq+tmp2q*8] ; 2 3
movhps m9, [filterq+tmp1q*8] ; 6 7
psrlw m8, m15, 8
psraw m11, m14, 8
psllw m15, 8
psllw m14, 8
psrlw m15, 8
psraw m14, 8
pmullw m8, m11
pmullw m15, m14
paddw m15, m8 ; pmaddubsw m15, m14
psrlw m8, m10, 8
psraw m11, m9, 8
psllw m10, 8
psllw m9, 8
psrlw m10, 8
psraw m9, 8
pmullw m8, m11
pmullw m10, m9
paddw m10, m8 ; pmaddubsw m10, m9
pslld m8, m0, 16
pslld m9, m1, 16
pslld m14, m15, 16
pslld m11, m10, 16
paddw m0, m8
paddw m1, m9
paddw m15, m14
paddw m10, m11
psrad m0, 16
psrad m1, 16
psrad m15, 16
psrad m10, 16
packssdw m0, m15 ; phaddw m0, m15
packssdw m1, m10 ; phaddw m1, m10
%endif
mova m14, [PIC_sym(pw_8192)]
mova m9, [PIC_sym(pd_32768)]
pmaddwd m0, m14 ; 17-bit intermediate, upshifted by 13
pmaddwd m1, m14
paddd m0, m9 ; rounded 14-bit result in upper 16 bits of dword
paddd m1, m9
ret
%endmacro
INIT_XMM sse4
WARP_AFFINE_8X8
WARP_AFFINE_8X8T
INIT_XMM ssse3
WARP_AFFINE_8X8
WARP_AFFINE_8X8T
INIT_XMM sse2
WARP_AFFINE_8X8
WARP_AFFINE_8X8T
INIT_XMM ssse3
%if WIN64
DECLARE_REG_TMP 6, 4
%else
DECLARE_REG_TMP 6, 7
%endif
%macro BIDIR_FN 1 ; op
%1 0
lea stride3q, [strideq*3]
jmp wq
.w4_loop:
%1_INC_PTR 2
%1 0
lea dstq, [dstq+strideq*4]
.w4: ; tile 4x
movd [dstq ], m0 ; copy dw[0]
pshuflw m1, m0, q1032 ; swap dw[1] and dw[0]
movd [dstq+strideq*1], m1 ; copy dw[1]
punpckhqdq m0, m0 ; swap dw[3,2] with dw[1,0]
movd [dstq+strideq*2], m0 ; dw[2]
psrlq m0, 32 ; shift right in dw[3]
movd [dstq+stride3q ], m0 ; copy
sub hd, 4
jg .w4_loop
RET
.w8_loop:
%1_INC_PTR 2
%1 0
lea dstq, [dstq+strideq*2]
.w8:
movq [dstq ], m0
movhps [dstq+strideq*1], m0
sub hd, 2
jg .w8_loop
RET
.w16_loop:
%1_INC_PTR 2
%1 0
lea dstq, [dstq+strideq]
.w16:
mova [dstq ], m0
dec hd
jg .w16_loop
RET
.w32_loop:
%1_INC_PTR 4
%1 0
lea dstq, [dstq+strideq]
.w32:
mova [dstq ], m0
%1 2
mova [dstq + 16 ], m0
dec hd
jg .w32_loop
RET
.w64_loop:
%1_INC_PTR 8
%1 0
add dstq, strideq
.w64:
%assign i 0
%rep 4
mova [dstq + i*16 ], m0
%assign i i+1
%if i < 4
%1 2*i
%endif
%endrep
dec hd
jg .w64_loop
RET
.w128_loop:
%1_INC_PTR 16
%1 0
add dstq, strideq
.w128:
%assign i 0
%rep 8
mova [dstq + i*16 ], m0
%assign i i+1
%if i < 8
%1 2*i
%endif
%endrep
dec hd
jg .w128_loop
RET
%endmacro
%macro AVG 1 ; src_offset
; writes AVG of tmp1 tmp2 uint16 coeffs into uint8 pixel
mova m0, [tmp1q+(%1+0)*mmsize] ; load 8 coef(2bytes) from tmp1
paddw m0, [tmp2q+(%1+0)*mmsize] ; load/add 8 coef(2bytes) tmp2
mova m1, [tmp1q+(%1+1)*mmsize]
paddw m1, [tmp2q+(%1+1)*mmsize]
pmulhrsw m0, m2
pmulhrsw m1, m2
packuswb m0, m1 ; pack/trunc 16 bits from m0 & m1 to 8 bit
%endmacro
%macro AVG_INC_PTR 1
add tmp1q, %1*mmsize
add tmp2q, %1*mmsize
%endmacro
cglobal avg, 4, 7, 3, dst, stride, tmp1, tmp2, w, h, stride3
LEA r6, avg_ssse3_table
tzcnt wd, wm ; leading zeros
movifnidn hd, hm ; move h(stack) to h(register) if not already that register
movsxd wq, dword [r6+wq*4] ; push table entry matching the tile width (tzcnt) in widen reg
mova m2, [pw_1024+r6-avg_ssse3_table] ; fill m2 with shift/align
add wq, r6
BIDIR_FN AVG
%macro W_AVG 1 ; src_offset
; (a * weight + b * (16 - weight) + 128) >> 8
; = ((a - b) * weight + (b << 4) + 128) >> 8
; = ((((a - b) * ((weight-16) << 12)) >> 16) + a + 8) >> 4
; = ((((b - a) * (-weight << 12)) >> 16) + b + 8) >> 4
mova m2, [tmp1q+(%1+0)*mmsize]
mova m0, m2
psubw m2, [tmp2q+(%1+0)*mmsize]
mova m3, [tmp1q+(%1+1)*mmsize]
mova m1, m3
psubw m3, [tmp2q+(%1+1)*mmsize]
pmulhw m2, m4
pmulhw m3, m4
paddw m0, m2
paddw m1, m3
pmulhrsw m0, m5
pmulhrsw m1, m5
packuswb m0, m1
%endmacro
%define W_AVG_INC_PTR AVG_INC_PTR
cglobal w_avg, 4, 7, 6, dst, stride, tmp1, tmp2, w, h, stride3
LEA r6, w_avg_ssse3_table
tzcnt wd, wm
movd m4, r6m
movifnidn hd, hm
pxor m0, m0
movsxd wq, dword [r6+wq*4]
mova m5, [pw_2048+r6-w_avg_ssse3_table]
pshufb m4, m0
psllw m4, 12 ; (weight-16) << 12 when interpreted as signed
add wq, r6
cmp dword r6m, 7
jg .weight_gt7
mov r6, tmp1q
psubw m0, m4
mov tmp1q, tmp2q
mova m4, m0 ; -weight
mov tmp2q, r6
.weight_gt7:
BIDIR_FN W_AVG
%macro MASK 1 ; src_offset
; (a * m + b * (64 - m) + 512) >> 10
; = ((a - b) * m + (b << 6) + 512) >> 10
; = ((((b - a) * (-m << 10)) >> 16) + b + 8) >> 4
mova m3, [maskq+(%1+0)*(mmsize/2)]
mova m0, [tmp2q+(%1+0)*mmsize] ; b
psubw m1, m0, [tmp1q+(%1+0)*mmsize] ; b - a
mova m6, m3 ; m
psubb m3, m4, m6 ; -m
paddw m1, m1 ; (b - a) << 1
paddb m3, m3 ; -m << 1
punpcklbw m2, m4, m3 ; -m << 9 (<< 8 when ext as uint16)
pmulhw m1, m2 ; (-m * (b - a)) << 10
paddw m0, m1 ; + b
mova m1, [tmp2q+(%1+1)*mmsize] ; b
psubw m2, m1, [tmp1q+(%1+1)*mmsize] ; b - a
paddw m2, m2 ; (b - a) << 1
mova m6, m3 ; (-m << 1)
punpckhbw m3, m4, m6 ; (-m << 9)
pmulhw m2, m3 ; (-m << 9)
paddw m1, m2 ; (-m * (b - a)) << 10
pmulhrsw m0, m5 ; round
pmulhrsw m1, m5 ; round
packuswb m0, m1 ; interleave 16 -> 8
%endmacro
%macro MASK_INC_PTR 1
add maskq, %1*mmsize/2
add tmp1q, %1*mmsize
add tmp2q, %1*mmsize
%endmacro
%if ARCH_X86_64
cglobal mask, 4, 8, 7, dst, stride, tmp1, tmp2, w, h, mask, stride3
movifnidn hd, hm
%else
cglobal mask, 4, 7, 7, dst, stride, tmp1, tmp2, w, mask, stride3
%define hd dword r5m
%endif
%define base r6-mask_ssse3_table
LEA r6, mask_ssse3_table
tzcnt wd, wm
movsxd wq, dword [r6+wq*4]
pxor m4, m4
mova m5, [base+pw_2048]
add wq, r6
mov maskq, r6m
BIDIR_FN MASK
%undef hd
%macro W_MASK_420_B 2 ; src_offset in bytes, mask_out
;**** do m0 = u16.dst[7..0], m%2 = u16.m[7..0] ****
mova m0, [tmp1q+(%1)]
mova m1, [tmp2q+(%1)]
mova m2, reg_pw_6903
psubw m1, m0
pabsw m%2, m1 ; abs(tmp1 - tmp2)
mova m3, m2
psubusw m2, m%2
psrlw m2, 8 ; 64 - m
mova m%2, m2
psllw m2, 10
pmulhw m1, m2 ; tmp2 * ()
paddw m0, m1 ; tmp1 + ()
;**** do m1 = u16.dst[7..0], m%2 = u16.m[7..0] ****
mova m1, [tmp1q+(%1)+mmsize]
mova m2, [tmp2q+(%1)+mmsize]
psubw m2, m1
pabsw m7, m2 ; abs(tmp1 - tmp2)
psubusw m3, m7
psrlw m3, 8 ; 64 - m
phaddw m%2, m3 ; pack both u16.m[8..0]runs as u8.m [15..0]
psllw m3, 10
pmulhw m2, m3
%if ARCH_X86_32
mova reg_pw_2048, [base+pw_2048]
%endif
paddw m1, m2
pmulhrsw m0, reg_pw_2048 ; round/scale 2048
pmulhrsw m1, reg_pw_2048 ; round/scale 2048
packuswb m0, m1 ; concat m0 = u8.dst[15..0]
%endmacro
%macro W_MASK_420 2
W_MASK_420_B (%1*16), %2
%endmacro
%define base r6-w_mask_420_ssse3_table
%if ARCH_X86_64
%define reg_pw_6903 m8
%define reg_pw_2048 m9
; args: dst, stride, tmp1, tmp2, w, h, mask, sign
cglobal w_mask_420, 4, 8, 10, dst, stride, tmp1, tmp2, w, h, mask
lea r6, [w_mask_420_ssse3_table]
mov wd, wm
tzcnt r7d, wd
movd m0, r7m ; sign
movifnidn hd, hm
movsxd r7, [r6+r7*4]
mova reg_pw_6903, [base+pw_6903] ; ((64 - 38) << 8) + 255 - 8
mova reg_pw_2048, [base+pw_2048]
movd m6, [base+pw_258] ; 64 * 4 + 2
add r7, r6
mov maskq, maskmp
psubw m6, m0
pshuflw m6, m6, q0000
punpcklqdq m6, m6
W_MASK_420 0, 4
jmp r7
%define loop_w r7d
%else
%define reg_pw_6903 [base+pw_6903]
%define reg_pw_2048 m3
cglobal w_mask_420, 4, 7, 8, dst, stride, tmp1, tmp2, w, mask
tzcnt wd, wm
LEA r6, w_mask_420_ssse3_table
movd m0, r7m ; sign
mov maskq, r6mp
mov wd, [r6+wq*4]
movd m6, [base+pw_258]
add wq, r6
psubw m6, m0
pshuflw m6, m6, q0000
punpcklqdq m6, m6
W_MASK_420 0, 4
jmp wd
%define loop_w dword r0m
%define hd dword r5m
%endif
.w4_loop:
add tmp1q, 2*16
add tmp2q, 2*16
W_MASK_420 0, 4
lea dstq, [dstq+strideq*2]
add maskq, 4
.w4:
movd [dstq ], m0 ; copy m0[0]
pshuflw m1, m0, q1032
movd [dstq+strideq*1], m1 ; copy m0[1]
lea dstq, [dstq+strideq*2]
punpckhqdq m0, m0
movd [dstq+strideq*0], m0 ; copy m0[2]
psrlq m0, 32
movd [dstq+strideq*1], m0 ; copy m0[3]
psubw m1, m6, m4 ; a _ c _
psrlq m4, 32 ; b _ d _
psubw m1, m4
psrlw m1, 2
packuswb m1, m1
pshuflw m1, m1, q2020
movd [maskq], m1
sub hd, 4
jg .w4_loop
RET
.w8_loop:
add tmp1q, 2*16
add tmp2q, 2*16
W_MASK_420 0, 4
lea dstq, [dstq+strideq*2]
add maskq, 4
.w8:
movq [dstq ], m0
movhps [dstq+strideq*1], m0
psubw m0, m6, m4
punpckhqdq m4, m4
psubw m0, m4
psrlw m0, 2
packuswb m0, m0
movd [maskq], m0
sub hd, 2
jg .w8_loop
RET
.w16: ; w32/64/128
%if ARCH_X86_32
mov wd, wm ; because we altered it in 32bit setup
%endif
mov loop_w, wd ; use width as counter
jmp .w16ge_inner_loop_first
.w16ge_loop:
lea tmp1q, [tmp1q+wq*2] ; skip even line pixels
lea tmp2q, [tmp2q+wq*2] ; skip even line pixels
sub dstq, wq
mov loop_w, wd
lea dstq, [dstq+strideq*2]
.w16ge_inner_loop:
W_MASK_420_B 0, 4
.w16ge_inner_loop_first:
mova [dstq ], m0
W_MASK_420_B wq*2, 5 ; load matching even line (offset = widthpx * (16+16))
mova [dstq+strideq*1], m0
psubw m1, m6, m4 ; m9 == 64 * 4 + 2
psubw m1, m5 ; - odd line mask
psrlw m1, 2 ; >> 2
packuswb m1, m1
movq [maskq], m1
add tmp1q, 2*16
add tmp2q, 2*16
add maskq, 8
add dstq, 16
sub loop_w, 16
jg .w16ge_inner_loop
sub hd, 2
jg .w16ge_loop
RET
%undef reg_pw_6903
%undef reg_pw_2048
%undef dst_bak
%undef loop_w
%undef orig_w
%undef hd
%macro BLEND_64M 4; a, b, mask1, mask2
punpcklbw m0, %1, %2; {b;a}[7..0]
punpckhbw %1, %2 ; {b;a}[15..8]
pmaddubsw m0, %3 ; {b*m[0] + (64-m[0])*a}[7..0] u16
pmaddubsw %1, %4 ; {b*m[1] + (64-m[1])*a}[15..8] u16
pmulhrsw m0, m5 ; {((b*m[0] + (64-m[0])*a) + 1) / 32}[7..0] u16
pmulhrsw %1, m5 ; {((b*m[1] + (64-m[0])*a) + 1) / 32}[15..8] u16
packuswb m0, %1 ; {blendpx}[15..0] u8
%endmacro
%macro BLEND 2; a, b
psubb m3, m4, m0 ; m3 = (64 - m)
punpcklbw m2, m3, m0 ; {m;(64-m)}[7..0]
punpckhbw m3, m0 ; {m;(64-m)}[15..8]
BLEND_64M %1, %2, m2, m3
%endmacro
cglobal blend, 3, 7, 7, dst, ds, tmp, w, h, mask
%define base r6-blend_ssse3_table
LEA r6, blend_ssse3_table
tzcnt wd, wm
movifnidn hd, hm
movifnidn maskq, maskmp
movsxd wq, dword [r6+wq*4]
mova m4, [base+pb_64]
mova m5, [base+pw_512]
add wq, r6
lea r6, [dsq*3]
jmp wq
.w4:
movq m0, [maskq]; m
movd m1, [dstq+dsq*0] ; a
movd m6, [dstq+dsq*1]
punpckldq m1, m6
movq m6, [tmpq] ; b
psubb m3, m4, m0 ; m3 = (64 - m)
punpcklbw m2, m3, m0 ; {m;(64-m)}[7..0]
punpcklbw m1, m6 ; {b;a}[7..0]
pmaddubsw m1, m2 ; {b*m[0] + (64-m[0])*a}[7..0] u16
pmulhrsw m1, m5 ; {((b*m[0] + (64-m[0])*a) + 1) / 32}[7..0] u16
packuswb m1, m0 ; {blendpx}[15..0] u8
movd [dstq+dsq*0], m1
psrlq m1, 32
movd [dstq+dsq*1], m1
add maskq, 8
add tmpq, 8
lea dstq, [dstq+dsq*2] ; dst_stride * 2
sub hd, 2
jg .w4
RET
.w8:
mova m0, [maskq]; m
movq m1, [dstq+dsq*0] ; a
movhps m1, [dstq+dsq*1]
mova m6, [tmpq] ; b
BLEND m1, m6
movq [dstq+dsq*0], m0
movhps [dstq+dsq*1], m0
add maskq, 16
add tmpq, 16
lea dstq, [dstq+dsq*2] ; dst_stride * 2
sub hd, 2
jg .w8
RET
.w16:
mova m0, [maskq]; m
mova m1, [dstq] ; a
mova m6, [tmpq] ; b
BLEND m1, m6
mova [dstq], m0
add maskq, 16
add tmpq, 16
add dstq, dsq ; dst_stride
dec hd
jg .w16
RET
.w32:
%assign i 0
%rep 2
mova m0, [maskq+16*i]; m
mova m1, [dstq+16*i] ; a
mova m6, [tmpq+16*i] ; b
BLEND m1, m6
mova [dstq+i*16], m0
%assign i i+1
%endrep
add maskq, 32
add tmpq, 32
add dstq, dsq ; dst_stride
dec hd
jg .w32
RET
cglobal blend_v, 3, 6, 6, dst, ds, tmp, w, h, mask
%define base r5-blend_v_ssse3_table
LEA r5, blend_v_ssse3_table
tzcnt wd, wm
movifnidn hd, hm
movsxd wq, dword [r5+wq*4]
mova m5, [base+pw_512]
add wq, r5
add maskq, obmc_masks-blend_v_ssse3_table
jmp wq
.w2:
movd m3, [maskq+4]
punpckldq m3, m3
; 2 mask blend is provided for 4 pixels / 2 lines
.w2_loop:
movd m1, [dstq+dsq*0] ; a {..;a;a}
pinsrw m1, [dstq+dsq*1], 1
movd m2, [tmpq] ; b
punpcklbw m0, m1, m2; {b;a}[7..0]
pmaddubsw m0, m3 ; {b*m + (64-m)*a}[7..0] u16
pmulhrsw m0, m5 ; {((b*m + (64-m)*a) + 1) / 32}[7..0] u16
packuswb m0, m1 ; {blendpx}[8..0] u8
movd r3d, m0
mov [dstq+dsq*0], r3w
shr r3d, 16
mov [dstq+dsq*1], r3w
add tmpq, 2*2
lea dstq, [dstq + dsq * 2]
sub hd, 2
jg .w2_loop
RET
.w4:
movddup m3, [maskq+8]
; 4 mask blend is provided for 8 pixels / 2 lines
.w4_loop:
movd m1, [dstq+dsq*0] ; a
movd m2, [dstq+dsq*1] ;
punpckldq m1, m2
movq m2, [tmpq] ; b
punpcklbw m1, m2 ; {b;a}[7..0]
pmaddubsw m1, m3 ; {b*m + (64-m)*a}[7..0] u16
pmulhrsw m1, m5 ; {((b*m + (64-m)*a) + 1) / 32}[7..0] u16
packuswb m1, m1 ; {blendpx}[8..0] u8
movd [dstq], m1
psrlq m1, 32
movd [dstq+dsq*1], m1
add tmpq, 2*4
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .w4_loop
RET
.w8:
mova m3, [maskq+16]
; 8 mask blend is provided for 16 pixels
.w8_loop:
movq m1, [dstq+dsq*0] ; a
movhps m1, [dstq+dsq*1]
mova m2, [tmpq]; b
BLEND_64M m1, m2, m3, m3
movq [dstq+dsq*0], m0
movhps [dstq+dsq*1], m0
add tmpq, 16
lea dstq, [dstq+dsq*2]
sub hd, 2
jg .w8_loop
RET
.w16:
; 16 mask blend is provided for 32 pixels
mova m3, [maskq+32] ; obmc_masks_16[0] (64-m[0])
mova m4, [maskq+48] ; obmc_masks_16[1] (64-m[1])
.w16_loop:
mova m1, [dstq] ; a
mova m2, [tmpq] ; b
BLEND_64M m1, m2, m3, m4
mova [dstq], m0
add tmpq, 16
add dstq, dsq
dec hd
jg .w16_loop
RET
.w32:
%if WIN64
mova [rsp+8], xmm6
%endif
mova m3, [maskq+64] ; obmc_masks_32[0] (64-m[0])
mova m4, [maskq+80] ; obmc_masks_32[1] (64-m[1])
mova m6, [maskq+96] ; obmc_masks_32[2] (64-m[2])
; 16 mask blend is provided for 64 pixels
.w32_loop:
mova m1, [dstq+16*0] ; a
mova m2, [tmpq+16*0] ; b
BLEND_64M m1, m2, m3, m4
movq m1, [dstq+16*1] ; a
punpcklbw m1, [tmpq+16*1] ; b
pmaddubsw m1, m6
pmulhrsw m1, m5
packuswb m1, m1
mova [dstq+16*0], m0
movq [dstq+16*1], m1
add tmpq, 32
add dstq, dsq
dec hd
jg .w32_loop
%if WIN64
mova xmm6, [rsp+8]
%endif
RET
cglobal blend_h, 3, 7, 6, dst, ds, tmp, w, h, mask
%define base t0-blend_h_ssse3_table
%if ARCH_X86_32
; We need to keep the PIC pointer for w4, reload wd from stack instead
DECLARE_REG_TMP 6
%else
DECLARE_REG_TMP 5
mov r6d, wd
%endif
LEA t0, blend_h_ssse3_table
tzcnt wd, wm
mov hd, hm
movsxd wq, dword [t0+wq*4]
mova m5, [base+pw_512]
add wq, t0
lea maskq, [base+obmc_masks+hq*2]
lea hd, [hq*3]
shr hd, 2 ; h * 3/4
lea maskq, [maskq+hq*2]
neg hq
jmp wq
.w2:
movd m0, [dstq+dsq*0]
pinsrw m0, [dstq+dsq*1], 1
movd m2, [maskq+hq*2]
movd m1, [tmpq]
punpcklwd m2, m2
punpcklbw m0, m1
pmaddubsw m0, m2
pmulhrsw m0, m5
packuswb m0, m0
movd r3d, m0
mov [dstq+dsq*0], r3w
shr r3d, 16
mov [dstq+dsq*1], r3w
lea dstq, [dstq+dsq*2]
add tmpq, 2*2
add hq, 2
jl .w2
RET
.w4:
%if ARCH_X86_32
mova m3, [base+blend_shuf]
%else
mova m3, [blend_shuf]
%endif
.w4_loop:
movd m0, [dstq+dsq*0]
movd m2, [dstq+dsq*1]
punpckldq m0, m2 ; a
movq m1, [tmpq] ; b
movq m2, [maskq+hq*2] ; m
pshufb m2, m3
punpcklbw m0, m1
pmaddubsw m0, m2
pmulhrsw m0, m5
packuswb m0, m0
movd [dstq+dsq*0], m0
psrlq m0, 32
movd [dstq+dsq*1], m0
lea dstq, [dstq+dsq*2]
add tmpq, 4*2
add hq, 2
jl .w4_loop
RET
.w8:
movd m4, [maskq+hq*2]
punpcklwd m4, m4
pshufd m3, m4, q0000
pshufd m4, m4, q1111
movq m1, [dstq+dsq*0] ; a
movhps m1, [dstq+dsq*1]
mova m2, [tmpq]
BLEND_64M m1, m2, m3, m4
movq [dstq+dsq*0], m0
movhps [dstq+dsq*1], m0
lea dstq, [dstq+dsq*2]
add tmpq, 8*2
add hq, 2
jl .w8
RET
; w16/w32/w64/w128
.w16:
%if ARCH_X86_32
mov r6d, wm
%endif
sub dsq, r6
.w16_loop0:
movd m3, [maskq+hq*2]
pshuflw m3, m3, q0000
punpcklqdq m3, m3
mov wd, r6d
.w16_loop:
mova m1, [dstq] ; a
mova m2, [tmpq] ; b
BLEND_64M m1, m2, m3, m3
mova [dstq], m0
add dstq, 16
add tmpq, 16
sub wd, 16
jg .w16_loop
add dstq, dsq
inc hq
jl .w16_loop0
RET
; emu_edge args:
; const intptr_t bw, const intptr_t bh, const intptr_t iw, const intptr_t ih,
; const intptr_t x, const intptr_t y, pixel *dst, const ptrdiff_t dst_stride,
; const pixel *ref, const ptrdiff_t ref_stride
;
; bw, bh total filled size
; iw, ih, copied block -> fill bottom, right
; x, y, offset in bw/bh -> fill top, left
cglobal emu_edge, 10, 13, 2, bw, bh, iw, ih, x, \
y, dst, dstride, src, sstride, \
bottomext, rightext, blk
; we assume that the buffer (stride) is larger than width, so we can
; safely overwrite by a few bytes
pxor m1, m1
%if ARCH_X86_64
%define reg_zero r12q
%define reg_tmp r10
%define reg_src srcq
%define reg_bottomext bottomextq
%define reg_rightext rightextq
%define reg_blkm r9m
%else
%define reg_zero r6
%define reg_tmp r0
%define reg_src r1
%define reg_bottomext r0
%define reg_rightext r1
%define reg_blkm r2m
%endif
;
; ref += iclip(y, 0, ih - 1) * PXSTRIDE(ref_stride)
xor reg_zero, reg_zero
lea reg_tmp, [ihq-1]
cmp yq, ihq
cmovl reg_tmp, yq
test yq, yq
cmovl reg_tmp, reg_zero
%if ARCH_X86_64
imul reg_tmp, sstrideq
add srcq, reg_tmp
%else
imul reg_tmp, sstridem
mov reg_src, srcm
add reg_src, reg_tmp
%endif
;
; ref += iclip(x, 0, iw - 1)
lea reg_tmp, [iwq-1]
cmp xq, iwq
cmovl reg_tmp, xq
test xq, xq
cmovl reg_tmp, reg_zero
add reg_src, reg_tmp
%if ARCH_X86_32
mov srcm, reg_src
%endif
;
; bottom_ext = iclip(y + bh - ih, 0, bh - 1)
%if ARCH_X86_32
mov r1, r1m ; restore bh
%endif
lea reg_bottomext, [yq+bhq]
sub reg_bottomext, ihq
lea r3, [bhq-1]
cmovl reg_bottomext, reg_zero
;
DEFINE_ARGS bw, bh, iw, ih, x, \
topext, dst, dstride, src, sstride, \
bottomext, rightext, blk
; top_ext = iclip(-y, 0, bh - 1)
neg topextq
cmovl topextq, reg_zero
cmp reg_bottomext, bhq
cmovge reg_bottomext, r3
cmp topextq, bhq
cmovg topextq, r3
%if ARCH_X86_32
mov r4m, reg_bottomext
;
; right_ext = iclip(x + bw - iw, 0, bw - 1)
mov r0, r0m ; restore bw
%endif
lea reg_rightext, [xq+bwq]
sub reg_rightext, iwq
lea r2, [bwq-1]
cmovl reg_rightext, reg_zero
DEFINE_ARGS bw, bh, iw, ih, leftext, \
topext, dst, dstride, src, sstride, \
bottomext, rightext, blk
; left_ext = iclip(-x, 0, bw - 1)
neg leftextq
cmovl leftextq, reg_zero
cmp reg_rightext, bwq
cmovge reg_rightext, r2
%if ARCH_X86_32
mov r3m, r1
%endif
cmp leftextq, bwq
cmovge leftextq, r2
%undef reg_zero
%undef reg_tmp
%undef reg_src
%undef reg_bottomext
%undef reg_rightext
DEFINE_ARGS bw, centerh, centerw, dummy, leftext, \
topext, dst, dstride, src, sstride, \
bottomext, rightext, blk
; center_h = bh - top_ext - bottom_ext
%if ARCH_X86_64
lea r3, [bottomextq+topextq]
sub centerhq, r3
%else
mov r1, centerhm ; restore r1
sub centerhq, topextq
sub centerhq, r4m
mov r1m, centerhq
%endif
;
; blk += top_ext * PXSTRIDE(dst_stride)
mov r2, topextq
%if ARCH_X86_64
imul r2, dstrideq
%else
mov r6, r6m ; restore dstq
imul r2, dstridem
%endif
add dstq, r2
mov reg_blkm, dstq ; save pointer for ext
;
; center_w = bw - left_ext - right_ext
mov centerwq, bwq
%if ARCH_X86_64
lea r3, [rightextq+leftextq]
sub centerwq, r3
%else
sub centerwq, r3m
sub centerwq, leftextq
%endif
; vloop Macro
%macro v_loop 3 ; need_left_ext, need_right_ext, suffix
%if ARCH_X86_64
%define reg_tmp r12
%else
%define reg_tmp r0
%endif
.v_loop_%3:
%if ARCH_X86_32
mov r0, r0m
mov r1, r1m
%endif
%if %1
test leftextq, leftextq
jz .body_%3
; left extension
%if ARCH_X86_64
movd m0, [srcq]
%else
mov r3, srcm
movd m0, [r3]
%endif
pshufb m0, m1
xor r3, r3
.left_loop_%3:
mova [dstq+r3], m0
add r3, mmsize
cmp r3, leftextq
jl .left_loop_%3
; body
.body_%3:
lea reg_tmp, [dstq+leftextq]
%endif
xor r3, r3
.body_loop_%3:
%if ARCH_X86_64
movu m0, [srcq+r3]
%else
mov r1, srcm
movu m0, [r1+r3]
%endif
%if %1
movu [reg_tmp+r3], m0
%else
movu [dstq+r3], m0
%endif
add r3, mmsize
cmp r3, centerwq
jl .body_loop_%3
%if %2
; right extension
%if ARCH_X86_64
test rightextq, rightextq
%else
mov r1, r3m
test r1, r1
%endif
jz .body_loop_end_%3
%if %1
add reg_tmp, centerwq
%else
lea reg_tmp, [dstq+centerwq]
%endif
%if ARCH_X86_64
movd m0, [srcq+centerwq-1]
%else
mov r3, srcm
movd m0, [r3+centerwq-1]
%endif
pshufb m0, m1
xor r3, r3
.right_loop_%3:
movu [reg_tmp+r3], m0
add r3, mmsize
%if ARCH_X86_64
cmp r3, rightextq
%else
cmp r3, r3m
%endif
jl .right_loop_%3
.body_loop_end_%3:
%endif
%if ARCH_X86_64
add dstq, dstrideq
add srcq, sstrideq
dec centerhq
jg .v_loop_%3
%else
add dstq, dstridem
mov r0, sstridem
add srcm, r0
sub dword centerhm, 1
jg .v_loop_%3
mov r0, r0m ; restore r0
%endif
%endmacro ; vloop MACRO
test leftextq, leftextq
jnz .need_left_ext
%if ARCH_X86_64
test rightextq, rightextq
jnz .need_right_ext
%else
cmp leftextq, r3m ; leftextq == 0
jne .need_right_ext
%endif
v_loop 0, 0, 0
jmp .body_done
;left right extensions
.need_left_ext:
%if ARCH_X86_64
test rightextq, rightextq
%else
mov r3, r3m
test r3, r3
%endif
jnz .need_left_right_ext
v_loop 1, 0, 1
jmp .body_done
.need_left_right_ext:
v_loop 1, 1, 2
jmp .body_done
.need_right_ext:
v_loop 0, 1, 3
.body_done:
; r0 ; bw
; r1 ;; x loop
; r4 ;; y loop
; r5 ; topextq
; r6 ;dstq
; r7 ;dstrideq
; r8 ; srcq
%if ARCH_X86_64
%define reg_dstride dstrideq
%else
%define reg_dstride r2
%endif
;
; bottom edge extension
%if ARCH_X86_64
test bottomextq, bottomextq
jz .top
%else
xor r1, r1
cmp r1, r4m
je .top
%endif
;
%if ARCH_X86_64
mov srcq, dstq
sub srcq, dstrideq
xor r1, r1
%else
mov r3, dstq
mov reg_dstride, dstridem
sub r3, reg_dstride
mov srcm, r3
%endif
;
.bottom_x_loop:
%if ARCH_X86_64
mova m0, [srcq+r1]
lea r3, [dstq+r1]
mov r4, bottomextq
%else
mov r3, srcm
mova m0, [r3+r1]
lea r3, [dstq+r1]
mov r4, r4m
%endif
;
.bottom_y_loop:
mova [r3], m0
add r3, reg_dstride
dec r4
jg .bottom_y_loop
add r1, mmsize
cmp r1, bwq
jl .bottom_x_loop
.top:
; top edge extension
test topextq, topextq
jz .end
%if ARCH_X86_64
mov srcq, reg_blkm
%else
mov r3, reg_blkm
mov reg_dstride, dstridem
%endif
mov dstq, dstm
xor r1, r1
;
.top_x_loop:
%if ARCH_X86_64
mova m0, [srcq+r1]
%else
mov r3, reg_blkm
mova m0, [r3+r1]
%endif
lea r3, [dstq+r1]
mov r4, topextq
;
.top_y_loop:
mova [r3], m0
add r3, reg_dstride
dec r4
jg .top_y_loop
add r1, mmsize
cmp r1, bwq
jl .top_x_loop
.end:
RET
%undef reg_dstride
%undef reg_blkm
%undef reg_tmp
| youtube/cobalt | third_party/libdav1d/src/x86/mc_ssse3.asm | Assembly | bsd-3-clause | 165,213 |
section .bss
popStr: resb 64
popStrLen: resb 64
section .text
global _start
_start:
call _proc_print_stckpop
call _proc_exit
_proc_print_stckpop:
mov eax, 4 ; The syscall for write
mov ebx, 1 ; File descriptor 1 - stdout
pop ecx ; put value from top of stack to ecx
mov [popStr], ecx ; load content to var popStr
mov edx, [$-popStr]
;mov [popStrLen], 0 ; fill var popStrLen with 0
;sub popStrLen, byte[popStr] ; substrsct popStr from popStrLen
call _proc_syscall
ret
_proc_exit:
mov eax, 1 ; Syscall for exit (sys_exit)
mov ebx, 0 ; rturn code 0
call _proc_syscall
ret
_proc_syscall:
int 80h
ret | kije/assembly_experiments | test4.asm | Assembly | bsd-3-clause | 670 |
_Z1gv:
subq $8, %rsp
call *_ZN3foo3bazE+8(%rip)
xorl %eax, %eax
addq $8, %rsp
ret | mattgodbolt/compiler-explorer | test/demangle-cases/bug-1468b.asm | Assembly | bsd-2-clause | 133 |
; TGBL time functions and macros
; Time periods in sysclock ticks
t_second equ 18
t_minute equ 1092
t_hour equ 65543
; Sleep
; Args: milliseconds to sleep
; Spoils: AX, CX, DX
%macro tgblm_sleep 1
mov cx, ((%1) * 1000) / 0xFFFF
mov dx, ((%1) * 1000) % 0xFFFF
mov ah, 86h
int 15h
%endmacro
; Get system time (in clock ticks)
; Returns: CX:DX = number of clock ticks since midnight
; AL = midnight flag, nonzero if midnight passed since time last read
; ~18.2 clock ticks per second, 0xFFFF ticks per hour
; Spoils: AH
%macro tgblm_getSysTime 0
xor ah, ah
int 1Ah
%endmacro
tgbl_getSysTime:
tgblm_getSysTime
ret
; Save system time (without hours) in word variable
; Args: address where to store ticks count (2 bytes)
; Spoils: AH, CX, DX
%macro tgblm_saveSysTimeMS 1
tgblm_getSysTime
mov [%1], dx
%endmacro
; Save system time (with hours) in dword variable
; Args: address where to store ticks count (4 bytes)
; Spoils: AH, CX, DX
%macro tgblm_saveSysTimeHMS 1
tgblm_saveSysTimeMS %1
mov [%1 + 2], cx
%endmacro
; Get number of ticks passed from last system time save
; Spoils: AH, CX, DX
; WITHOUT HOURS:
; Args: address of ticks count stored (2 bytes)
; Returns: DX = number of clock ticks since last systime save
%macro tgblm_getDeltaTimeMS 1
tgblm_getSysTime
sub dx, [%1]
%endmacro
; WITH HOURS:
; Args: address of ticks count stored (4 bytes)
; Returns: CX:DX = number of clock ticks since last systime save
%macro tgblm_getDeltaTimeHMS 1
tgblm_getDeltaTimeMS %1
sbb cx, [%1 + 2]
%endmacro
; Simple timer implementation: call X every Y ticks (Y < 0xFFFF)
; Args: function to call, period (in ticks, ~18.2 ticks per second, 0xFFFF ticks per hour),
; address of ticks count stored
; Spoils: AH, CX, DX
%macro tgblm_timer 3
tgblm_getDeltaTimeMS %3
cmp dx, %2
jb %%endIteration
call %1
tgblm_saveSysTimeMS %3
%%endIteration:
%endmacro
| trexxet/tgbl | lib/tgbl_time.asm | Assembly | mit | 1,874 |
PLC_361A78: dc.w Frame_361A8E-PLC_361A78
dc.w Frame_361A92-PLC_361A78
dc.w Frame_361A96-PLC_361A78
dc.w Frame_361A9A-PLC_361A78
dc.w Frame_361A9E-PLC_361A78
dc.w Frame_361AA2-PLC_361A78
dc.w Frame_361AA6-PLC_361A78
dc.w Frame_361AAA-PLC_361A78
dc.w Frame_361AB0-PLC_361A78
dc.w Frame_361AB4-PLC_361A78
dc.w Frame_361AB8-PLC_361A78
Frame_361A8E: dc.w 0
dc.w $F
Frame_361A92: dc.w 0
dc.w $10F
Frame_361A96: dc.w 0
dc.w $20B
Frame_361A9A: dc.w 0
dc.w $2CB
Frame_361A9E: dc.w 0
dc.w $38B
Frame_361AA2: dc.w 0
dc.w $44F
Frame_361AA6: dc.w 0
dc.w $54F
Frame_361AAA: dc.w 1
dc.w $641
dc.w $66F
Frame_361AB0: dc.w 0
dc.w $76F
Frame_361AB4: dc.w 0
dc.w $863
Frame_361AB8: dc.w 0
dc.w $F
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/General/Sprites/Clamer/DPLC - Clamer.asm | Assembly | apache-2.0 | 722 |
xor r0,r0,r0
xor r1,r1,r1
xor r2,r2,r2
xor r3,r3,r3
xor r4,r4,r4
xor r5,r5,r5
xor r6,r6,r6
ldl $-1
lsr r0,r7,r0
ldl #main
jmp r0,r7,r0
nop r0,r0,r0
>main
nop r0,r0,r0
ldl $30
and r7,r7,r1
ldl $27
and r7,r7,r2
nop r0,r0,r0
ldl #mult
call r0,r7,r0
nop r0,r0,r0
ldl #outVal
load r0,r7,r2
nop r0,r0,r0
ldl #drawhex
call r0,r7,r0
nop r0,r0,r0
hlt
hlt
nop r0,r0,r0
>mult
nop r0,r0,r0
ldl $0
and r7,r7,r3
ldl $1
and r7,r7,r4
sub r2,r4,r2
ldl $0
and r7,r7,r4
>loop0
add r3,r1,r3
cmp r4,r2,r0
ldl #loopend1
je r0,r7,r0
ldl $1
add r7,r4,r4
ldl #loop0
jmp r0,r7,r0
nop r0,r0,r0
>loopend1
ldl #outVal
store r0,r7,r3
ret
nop r0,r0,r0
>drawhex
nop r0,r0,r0
ldl $12
and r7,r7,r5
ldl $4
and r7,r7,r4
ldl $0
and r7,r7,r3
>loop2
add r1,r3,r3
ldl $8000
store r0,r7,r3
sub r3,r1,r3
ldl $15
and r7,r7,r6
bsl r6,r5,r6
and r6,r2,r6
bsr r6,r5,r6
ldl #hexDat
and r7,r7,r4
add r4,r6,r4
load r0,r4,r6
ldl $8002
store r0,r7,r6
ldl $4
and r7,r7,r4
sub r5,r4,r5
ldl $3
cmp r3,r7,r0
ldl #loopend3
je r0,r7,r0
ldl $1
add r7,r3,r3
ldl #loop2
jmp r0,r7,r0
nop r0,r0,r0
>loopend3
ret
>hexDat
. 48,49,50,51,52,53,54,55,56,57,65,66,67,68,69,70
>times
. 42
>equals
. 61
>outVal
. 0
| mgohde/MiniMicroII | Assembler/MKAsmWrapper/dist/multhextest.asm | Assembly | bsd-2-clause | 1,144 |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; ScanMem8.Asm
;
; Abstract:
;
; ScanMem8 function
;
; Notes:
;
; The following BaseMemoryLib instances contain the same copy of this file:
;
; BaseMemoryLibRepStr
; BaseMemoryLibMmx
; BaseMemoryLibSse2
; BaseMemoryLibOptDxe
; BaseMemoryLibOptPei
;
;------------------------------------------------------------------------------
.686
.model flat,C
.code
;------------------------------------------------------------------------------
; CONST VOID *
; EFIAPI
; InternalMemScanMem8 (
; IN CONST VOID *Buffer,
; IN UINTN Length,
; IN UINT8 Value
; );
;------------------------------------------------------------------------------
InternalMemScanMem8 PROC USES edi
mov ecx, [esp + 12]
mov edi, [esp + 8]
mov al, [esp + 16]
repne scasb
lea eax, [edi - 1]
jz @F
mov eax, ecx
@@:
ret
InternalMemScanMem8 ENDP
END
| intel/ipmctl | MdePkg/Library/BaseMemoryLibRepStr/Ia32/ScanMem8.asm | Assembly | bsd-3-clause | 1,603 |
;
; jccolext.asm - colorspace conversion (MMX)
;
; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
; Copyright (C) 2016, D. R. Commander.
;
; Based on the x86 SIMD extension for IJG JPEG library
; Copyright (C) 1999-2006, MIYASAKA Masaru.
; For conditions of distribution and use, see copyright notice in jsimdext.inc
;
; This file should be assembled with NASM (Netwide Assembler),
; can *not* be assembled with Microsoft's MASM or any compatible
; assembler (including Borland's Turbo Assembler).
; NASM is available from http://nasm.sourceforge.net/ or
; http://sourceforge.net/project/showfiles.php?group_id=6208
;
; [TAB8]
%include "jcolsamp.inc"
; --------------------------------------------------------------------------
;
; Convert some rows of samples to the output colorspace.
;
; GLOBAL(void)
; jsimd_rgb_ycc_convert_mmx (JDIMENSION img_width,
; JSAMPARRAY input_buf, JSAMPIMAGE output_buf,
; JDIMENSION output_row, int num_rows);
;
%define img_width(b) (b)+8 ; JDIMENSION img_width
%define input_buf(b) (b)+12 ; JSAMPARRAY input_buf
%define output_buf(b) (b)+16 ; JSAMPIMAGE output_buf
%define output_row(b) (b)+20 ; JDIMENSION output_row
%define num_rows(b) (b)+24 ; int num_rows
%define original_ebp ebp+0
%define wk(i) ebp-(WK_NUM-(i))*SIZEOF_MMWORD ; mmword wk[WK_NUM]
%define WK_NUM 8
%define gotptr wk(0)-SIZEOF_POINTER ; void * gotptr
align 32
global EXTN(jsimd_rgb_ycc_convert_mmx)
EXTN(jsimd_rgb_ycc_convert_mmx):
push ebp
mov eax,esp ; eax = original ebp
sub esp, byte 4
and esp, byte (-SIZEOF_MMWORD) ; align to 64 bits
mov [esp],eax
mov ebp,esp ; ebp = aligned ebp
lea esp, [wk(0)]
pushpic eax ; make a room for GOT address
push ebx
; push ecx ; need not be preserved
; push edx ; need not be preserved
push esi
push edi
get_GOT ebx ; get GOT address
movpic POINTER [gotptr], ebx ; save GOT address
mov ecx, JDIMENSION [img_width(eax)] ; num_cols
test ecx,ecx
jz near .return
push ecx
mov esi, JSAMPIMAGE [output_buf(eax)]
mov ecx, JDIMENSION [output_row(eax)]
mov edi, JSAMPARRAY [esi+0*SIZEOF_JSAMPARRAY]
mov ebx, JSAMPARRAY [esi+1*SIZEOF_JSAMPARRAY]
mov edx, JSAMPARRAY [esi+2*SIZEOF_JSAMPARRAY]
lea edi, [edi+ecx*SIZEOF_JSAMPROW]
lea ebx, [ebx+ecx*SIZEOF_JSAMPROW]
lea edx, [edx+ecx*SIZEOF_JSAMPROW]
pop ecx
mov esi, JSAMPARRAY [input_buf(eax)]
mov eax, INT [num_rows(eax)]
test eax,eax
jle near .return
alignx 16,7
.rowloop:
pushpic eax
push edx
push ebx
push edi
push esi
push ecx ; col
mov esi, JSAMPROW [esi] ; inptr
mov edi, JSAMPROW [edi] ; outptr0
mov ebx, JSAMPROW [ebx] ; outptr1
mov edx, JSAMPROW [edx] ; outptr2
movpic eax, POINTER [gotptr] ; load GOT address (eax)
cmp ecx, byte SIZEOF_MMWORD
jae short .columnloop
alignx 16,7
%if RGB_PIXELSIZE == 3 ; ---------------
.column_ld1:
push eax
push edx
lea ecx,[ecx+ecx*2] ; imul ecx,RGB_PIXELSIZE
test cl, SIZEOF_BYTE
jz short .column_ld2
sub ecx, byte SIZEOF_BYTE
xor eax,eax
mov al, BYTE [esi+ecx]
.column_ld2:
test cl, SIZEOF_WORD
jz short .column_ld4
sub ecx, byte SIZEOF_WORD
xor edx,edx
mov dx, WORD [esi+ecx]
shl eax, WORD_BIT
or eax,edx
.column_ld4:
movd mmA,eax
pop edx
pop eax
test cl, SIZEOF_DWORD
jz short .column_ld8
sub ecx, byte SIZEOF_DWORD
movd mmG, DWORD [esi+ecx]
psllq mmA, DWORD_BIT
por mmA,mmG
.column_ld8:
test cl, SIZEOF_MMWORD
jz short .column_ld16
movq mmG,mmA
movq mmA, MMWORD [esi+0*SIZEOF_MMWORD]
mov ecx, SIZEOF_MMWORD
jmp short .rgb_ycc_cnv
.column_ld16:
test cl, 2*SIZEOF_MMWORD
mov ecx, SIZEOF_MMWORD
jz short .rgb_ycc_cnv
movq mmF,mmA
movq mmA, MMWORD [esi+0*SIZEOF_MMWORD]
movq mmG, MMWORD [esi+1*SIZEOF_MMWORD]
jmp short .rgb_ycc_cnv
alignx 16,7
.columnloop:
movq mmA, MMWORD [esi+0*SIZEOF_MMWORD]
movq mmG, MMWORD [esi+1*SIZEOF_MMWORD]
movq mmF, MMWORD [esi+2*SIZEOF_MMWORD]
.rgb_ycc_cnv:
; mmA=(00 10 20 01 11 21 02 12)
; mmG=(22 03 13 23 04 14 24 05)
; mmF=(15 25 06 16 26 07 17 27)
movq mmD,mmA
psllq mmA,4*BYTE_BIT ; mmA=(-- -- -- -- 00 10 20 01)
psrlq mmD,4*BYTE_BIT ; mmD=(11 21 02 12 -- -- -- --)
punpckhbw mmA,mmG ; mmA=(00 04 10 14 20 24 01 05)
psllq mmG,4*BYTE_BIT ; mmG=(-- -- -- -- 22 03 13 23)
punpcklbw mmD,mmF ; mmD=(11 15 21 25 02 06 12 16)
punpckhbw mmG,mmF ; mmG=(22 26 03 07 13 17 23 27)
movq mmE,mmA
psllq mmA,4*BYTE_BIT ; mmA=(-- -- -- -- 00 04 10 14)
psrlq mmE,4*BYTE_BIT ; mmE=(20 24 01 05 -- -- -- --)
punpckhbw mmA,mmD ; mmA=(00 02 04 06 10 12 14 16)
psllq mmD,4*BYTE_BIT ; mmD=(-- -- -- -- 11 15 21 25)
punpcklbw mmE,mmG ; mmE=(20 22 24 26 01 03 05 07)
punpckhbw mmD,mmG ; mmD=(11 13 15 17 21 23 25 27)
pxor mmH,mmH
movq mmC,mmA
punpcklbw mmA,mmH ; mmA=(00 02 04 06)
punpckhbw mmC,mmH ; mmC=(10 12 14 16)
movq mmB,mmE
punpcklbw mmE,mmH ; mmE=(20 22 24 26)
punpckhbw mmB,mmH ; mmB=(01 03 05 07)
movq mmF,mmD
punpcklbw mmD,mmH ; mmD=(11 13 15 17)
punpckhbw mmF,mmH ; mmF=(21 23 25 27)
%else ; RGB_PIXELSIZE == 4 ; -----------
.column_ld1:
test cl, SIZEOF_MMWORD/8
jz short .column_ld2
sub ecx, byte SIZEOF_MMWORD/8
movd mmA, DWORD [esi+ecx*RGB_PIXELSIZE]
.column_ld2:
test cl, SIZEOF_MMWORD/4
jz short .column_ld4
sub ecx, byte SIZEOF_MMWORD/4
movq mmF,mmA
movq mmA, MMWORD [esi+ecx*RGB_PIXELSIZE]
.column_ld4:
test cl, SIZEOF_MMWORD/2
mov ecx, SIZEOF_MMWORD
jz short .rgb_ycc_cnv
movq mmD,mmA
movq mmC,mmF
movq mmA, MMWORD [esi+0*SIZEOF_MMWORD]
movq mmF, MMWORD [esi+1*SIZEOF_MMWORD]
jmp short .rgb_ycc_cnv
alignx 16,7
.columnloop:
movq mmA, MMWORD [esi+0*SIZEOF_MMWORD]
movq mmF, MMWORD [esi+1*SIZEOF_MMWORD]
movq mmD, MMWORD [esi+2*SIZEOF_MMWORD]
movq mmC, MMWORD [esi+3*SIZEOF_MMWORD]
.rgb_ycc_cnv:
; mmA=(00 10 20 30 01 11 21 31)
; mmF=(02 12 22 32 03 13 23 33)
; mmD=(04 14 24 34 05 15 25 35)
; mmC=(06 16 26 36 07 17 27 37)
movq mmB,mmA
punpcklbw mmA,mmF ; mmA=(00 02 10 12 20 22 30 32)
punpckhbw mmB,mmF ; mmB=(01 03 11 13 21 23 31 33)
movq mmG,mmD
punpcklbw mmD,mmC ; mmD=(04 06 14 16 24 26 34 36)
punpckhbw mmG,mmC ; mmG=(05 07 15 17 25 27 35 37)
movq mmE,mmA
punpcklwd mmA,mmD ; mmA=(00 02 04 06 10 12 14 16)
punpckhwd mmE,mmD ; mmE=(20 22 24 26 30 32 34 36)
movq mmH,mmB
punpcklwd mmB,mmG ; mmB=(01 03 05 07 11 13 15 17)
punpckhwd mmH,mmG ; mmH=(21 23 25 27 31 33 35 37)
pxor mmF,mmF
movq mmC,mmA
punpcklbw mmA,mmF ; mmA=(00 02 04 06)
punpckhbw mmC,mmF ; mmC=(10 12 14 16)
movq mmD,mmB
punpcklbw mmB,mmF ; mmB=(01 03 05 07)
punpckhbw mmD,mmF ; mmD=(11 13 15 17)
movq mmG,mmE
punpcklbw mmE,mmF ; mmE=(20 22 24 26)
punpckhbw mmG,mmF ; mmG=(30 32 34 36)
punpcklbw mmF,mmH
punpckhbw mmH,mmH
psrlw mmF,BYTE_BIT ; mmF=(21 23 25 27)
psrlw mmH,BYTE_BIT ; mmH=(31 33 35 37)
%endif ; RGB_PIXELSIZE ; ---------------
; mm0=(R0 R2 R4 R6)=RE, mm2=(G0 G2 G4 G6)=GE, mm4=(B0 B2 B4 B6)=BE
; mm1=(R1 R3 R5 R7)=RO, mm3=(G1 G3 G5 G7)=GO, mm5=(B1 B3 B5 B7)=BO
; (Original)
; Y = 0.29900 * R + 0.58700 * G + 0.11400 * B
; Cb = -0.16874 * R - 0.33126 * G + 0.50000 * B + CENTERJSAMPLE
; Cr = 0.50000 * R - 0.41869 * G - 0.08131 * B + CENTERJSAMPLE
;
; (This implementation)
; Y = 0.29900 * R + 0.33700 * G + 0.11400 * B + 0.25000 * G
; Cb = -0.16874 * R - 0.33126 * G + 0.50000 * B + CENTERJSAMPLE
; Cr = 0.50000 * R - 0.41869 * G - 0.08131 * B + CENTERJSAMPLE
movq MMWORD [wk(0)], mm0 ; wk(0)=RE
movq MMWORD [wk(1)], mm1 ; wk(1)=RO
movq MMWORD [wk(2)], mm4 ; wk(2)=BE
movq MMWORD [wk(3)], mm5 ; wk(3)=BO
movq mm6,mm1
punpcklwd mm1,mm3
punpckhwd mm6,mm3
movq mm7,mm1
movq mm4,mm6
pmaddwd mm1,[GOTOFF(eax,PW_F0299_F0337)] ; mm1=ROL*FIX(0.299)+GOL*FIX(0.337)
pmaddwd mm6,[GOTOFF(eax,PW_F0299_F0337)] ; mm6=ROH*FIX(0.299)+GOH*FIX(0.337)
pmaddwd mm7,[GOTOFF(eax,PW_MF016_MF033)] ; mm7=ROL*-FIX(0.168)+GOL*-FIX(0.331)
pmaddwd mm4,[GOTOFF(eax,PW_MF016_MF033)] ; mm4=ROH*-FIX(0.168)+GOH*-FIX(0.331)
movq MMWORD [wk(4)], mm1 ; wk(4)=ROL*FIX(0.299)+GOL*FIX(0.337)
movq MMWORD [wk(5)], mm6 ; wk(5)=ROH*FIX(0.299)+GOH*FIX(0.337)
pxor mm1,mm1
pxor mm6,mm6
punpcklwd mm1,mm5 ; mm1=BOL
punpckhwd mm6,mm5 ; mm6=BOH
psrld mm1,1 ; mm1=BOL*FIX(0.500)
psrld mm6,1 ; mm6=BOH*FIX(0.500)
movq mm5,[GOTOFF(eax,PD_ONEHALFM1_CJ)] ; mm5=[PD_ONEHALFM1_CJ]
paddd mm7,mm1
paddd mm4,mm6
paddd mm7,mm5
paddd mm4,mm5
psrld mm7,SCALEBITS ; mm7=CbOL
psrld mm4,SCALEBITS ; mm4=CbOH
packssdw mm7,mm4 ; mm7=CbO
movq mm1, MMWORD [wk(2)] ; mm1=BE
movq mm6,mm0
punpcklwd mm0,mm2
punpckhwd mm6,mm2
movq mm5,mm0
movq mm4,mm6
pmaddwd mm0,[GOTOFF(eax,PW_F0299_F0337)] ; mm0=REL*FIX(0.299)+GEL*FIX(0.337)
pmaddwd mm6,[GOTOFF(eax,PW_F0299_F0337)] ; mm6=REH*FIX(0.299)+GEH*FIX(0.337)
pmaddwd mm5,[GOTOFF(eax,PW_MF016_MF033)] ; mm5=REL*-FIX(0.168)+GEL*-FIX(0.331)
pmaddwd mm4,[GOTOFF(eax,PW_MF016_MF033)] ; mm4=REH*-FIX(0.168)+GEH*-FIX(0.331)
movq MMWORD [wk(6)], mm0 ; wk(6)=REL*FIX(0.299)+GEL*FIX(0.337)
movq MMWORD [wk(7)], mm6 ; wk(7)=REH*FIX(0.299)+GEH*FIX(0.337)
pxor mm0,mm0
pxor mm6,mm6
punpcklwd mm0,mm1 ; mm0=BEL
punpckhwd mm6,mm1 ; mm6=BEH
psrld mm0,1 ; mm0=BEL*FIX(0.500)
psrld mm6,1 ; mm6=BEH*FIX(0.500)
movq mm1,[GOTOFF(eax,PD_ONEHALFM1_CJ)] ; mm1=[PD_ONEHALFM1_CJ]
paddd mm5,mm0
paddd mm4,mm6
paddd mm5,mm1
paddd mm4,mm1
psrld mm5,SCALEBITS ; mm5=CbEL
psrld mm4,SCALEBITS ; mm4=CbEH
packssdw mm5,mm4 ; mm5=CbE
psllw mm7,BYTE_BIT
por mm5,mm7 ; mm5=Cb
movq MMWORD [ebx], mm5 ; Save Cb
movq mm0, MMWORD [wk(3)] ; mm0=BO
movq mm6, MMWORD [wk(2)] ; mm6=BE
movq mm1, MMWORD [wk(1)] ; mm1=RO
movq mm4,mm0
punpcklwd mm0,mm3
punpckhwd mm4,mm3
movq mm7,mm0
movq mm5,mm4
pmaddwd mm0,[GOTOFF(eax,PW_F0114_F0250)] ; mm0=BOL*FIX(0.114)+GOL*FIX(0.250)
pmaddwd mm4,[GOTOFF(eax,PW_F0114_F0250)] ; mm4=BOH*FIX(0.114)+GOH*FIX(0.250)
pmaddwd mm7,[GOTOFF(eax,PW_MF008_MF041)] ; mm7=BOL*-FIX(0.081)+GOL*-FIX(0.418)
pmaddwd mm5,[GOTOFF(eax,PW_MF008_MF041)] ; mm5=BOH*-FIX(0.081)+GOH*-FIX(0.418)
movq mm3,[GOTOFF(eax,PD_ONEHALF)] ; mm3=[PD_ONEHALF]
paddd mm0, MMWORD [wk(4)]
paddd mm4, MMWORD [wk(5)]
paddd mm0,mm3
paddd mm4,mm3
psrld mm0,SCALEBITS ; mm0=YOL
psrld mm4,SCALEBITS ; mm4=YOH
packssdw mm0,mm4 ; mm0=YO
pxor mm3,mm3
pxor mm4,mm4
punpcklwd mm3,mm1 ; mm3=ROL
punpckhwd mm4,mm1 ; mm4=ROH
psrld mm3,1 ; mm3=ROL*FIX(0.500)
psrld mm4,1 ; mm4=ROH*FIX(0.500)
movq mm1,[GOTOFF(eax,PD_ONEHALFM1_CJ)] ; mm1=[PD_ONEHALFM1_CJ]
paddd mm7,mm3
paddd mm5,mm4
paddd mm7,mm1
paddd mm5,mm1
psrld mm7,SCALEBITS ; mm7=CrOL
psrld mm5,SCALEBITS ; mm5=CrOH
packssdw mm7,mm5 ; mm7=CrO
movq mm3, MMWORD [wk(0)] ; mm3=RE
movq mm4,mm6
punpcklwd mm6,mm2
punpckhwd mm4,mm2
movq mm1,mm6
movq mm5,mm4
pmaddwd mm6,[GOTOFF(eax,PW_F0114_F0250)] ; mm6=BEL*FIX(0.114)+GEL*FIX(0.250)
pmaddwd mm4,[GOTOFF(eax,PW_F0114_F0250)] ; mm4=BEH*FIX(0.114)+GEH*FIX(0.250)
pmaddwd mm1,[GOTOFF(eax,PW_MF008_MF041)] ; mm1=BEL*-FIX(0.081)+GEL*-FIX(0.418)
pmaddwd mm5,[GOTOFF(eax,PW_MF008_MF041)] ; mm5=BEH*-FIX(0.081)+GEH*-FIX(0.418)
movq mm2,[GOTOFF(eax,PD_ONEHALF)] ; mm2=[PD_ONEHALF]
paddd mm6, MMWORD [wk(6)]
paddd mm4, MMWORD [wk(7)]
paddd mm6,mm2
paddd mm4,mm2
psrld mm6,SCALEBITS ; mm6=YEL
psrld mm4,SCALEBITS ; mm4=YEH
packssdw mm6,mm4 ; mm6=YE
psllw mm0,BYTE_BIT
por mm6,mm0 ; mm6=Y
movq MMWORD [edi], mm6 ; Save Y
pxor mm2,mm2
pxor mm4,mm4
punpcklwd mm2,mm3 ; mm2=REL
punpckhwd mm4,mm3 ; mm4=REH
psrld mm2,1 ; mm2=REL*FIX(0.500)
psrld mm4,1 ; mm4=REH*FIX(0.500)
movq mm0,[GOTOFF(eax,PD_ONEHALFM1_CJ)] ; mm0=[PD_ONEHALFM1_CJ]
paddd mm1,mm2
paddd mm5,mm4
paddd mm1,mm0
paddd mm5,mm0
psrld mm1,SCALEBITS ; mm1=CrEL
psrld mm5,SCALEBITS ; mm5=CrEH
packssdw mm1,mm5 ; mm1=CrE
psllw mm7,BYTE_BIT
por mm1,mm7 ; mm1=Cr
movq MMWORD [edx], mm1 ; Save Cr
sub ecx, byte SIZEOF_MMWORD
add esi, byte RGB_PIXELSIZE*SIZEOF_MMWORD ; inptr
add edi, byte SIZEOF_MMWORD ; outptr0
add ebx, byte SIZEOF_MMWORD ; outptr1
add edx, byte SIZEOF_MMWORD ; outptr2
cmp ecx, byte SIZEOF_MMWORD
jae near .columnloop
test ecx,ecx
jnz near .column_ld1
pop ecx ; col
pop esi
pop edi
pop ebx
pop edx
poppic eax
add esi, byte SIZEOF_JSAMPROW ; input_buf
add edi, byte SIZEOF_JSAMPROW
add ebx, byte SIZEOF_JSAMPROW
add edx, byte SIZEOF_JSAMPROW
dec eax ; num_rows
jg near .rowloop
emms ; empty MMX state
.return:
pop edi
pop esi
; pop edx ; need not be preserved
; pop ecx ; need not be preserved
pop ebx
mov esp,ebp ; esp <- aligned ebp
pop esp ; esp <- original ebp
pop ebp
ret
; For some reason, the OS X linker does not honor the request to align the
; segment unless we do this.
align 32
| openpnp/openpnp-capture | linux/contrib/libjpeg-turbo-dev/simd/i386/jccolext-mmx.asm | Assembly | mit | 17,275 |
#define lcd_cs1 portd, 5
#define lcd_res portd, 6
#define lcd_a0 portd, 7
#define lcd_scl portd, 4
#define lcd_si portd, 1
#define LedOn sbi portb, 3
#define LedOff cbi portb, 3
#define LedToggle sbi pinb, 3
#define BuzzerOn sbi portb, 1
#define BuzzerOff cbi portb, 1
#define OutputPin1 portc, 6
#define OutputPin2 portc, 4
#define OutputPin3 portc, 2
#define OutputPin4 portc, 3
#define OutputPin5 porta, 4
#define OutputPin6 porta, 5
#define OutputPin7 portc, 5
#define OutputPin8 portc, 7
//#define DebugOutputPin portb, 0
#define LvaOutputPin portb, 2
#define DigitalOutPin portb, 0
| daltonmatos/avrgcc-mixed-with-avrasm2 | experiments/beep/hardware.asm | Assembly | bsd-3-clause | 632 |
020077A0 B570 push r4-r6,r14
020077A2 B08E add sp,-38h
020077A4 489A ldr r0,=27E00FCh
020077A6 6800 ldr r0,[r0]
020077A8 2800 cmp r0,0h
020077AA D100 bne 20077AEh
020077AC E12E b 2007A0Ch
020077AE 2801 cmp r0,1h
020077B0 D001 beq 20077B6h
020077B2 2804 cmp r0,4h
020077B4 D103 bne 20077BEh
020077B6 4896 ldr r0,=27E00FCh
020077B8 6801 ldr r1,[r0]
020077BA 1C49 add r1,r1,1
020077BC 6001 str r1,[r0]
020077BE 4894 ldr r0,=27E00FCh
020077C0 6800 ldr r0,[r0]
020077C2 2803 cmp r0,3h
020077C4 D001 beq 20077CAh
020077C6 2806 cmp r0,6h
020077C8 D103 bne 20077D2h
020077CA F7FFFD99 bl 2007300h
020077CE B00E add sp,38h
020077D0 BD70 pop r4-r6,r15
020077D2 2000 mov r0,0h
020077D4 9008 str r0,[sp,20h]
020077D6 488F ldr r0,=27E027Ch
020077D8 6880 ldr r0,[r0,8h]
020077DA F0B6EADC blx 20BDD94h
020077DE 2800 cmp r0,0h
020077E0 D105 bne 20077EEh
020077E2 488B ldr r0,=27E00FCh
020077E4 6801 ldr r1,[r0]
020077E6 1C49 add r1,r1,1
020077E8 6001 str r1,[r0]
020077EA B00E add sp,38h
020077EC BD70 pop r4-r6,r15
020077EE 4889 ldr r0,=27E027Ch
020077F0 6880 ldr r0,[r0,8h]
020077F2 F0B6EAB4 blx 20BDD5Ch
020077F6 4887 ldr r0,=27E027Ch
020077F8 6B41 ldr r1,[r0,34h]
020077FA 1C49 add r1,r1,1
020077FC 6341 str r1,[r0,34h]
020077FE 6880 ldr r0,[r0,8h]
02007800 F0B6EA5E blx 20BDCC0h
02007804 9007 str r0,[sp,1Ch]
02007806 2000 mov r0,0h
02007808 9006 str r0,[sp,18h]
0200780A 9807 ldr r0,[sp,1Ch]
0200780C 2800 cmp r0,0h
0200780E D940 bls 2007892h
02007810 4C80 ldr r4,=27E027Ch
02007812 9806 ldr r0,[sp,18h]
02007814 900D str r0,[sp,34h]
02007816 900A str r0,[sp,28h]
02007818 900C str r0,[sp,30h]
0200781A 487F ldr r0,=27E029Ch
0200781C 7EC0 ldrb r0,[r0,1Bh]
0200781E 07C0 lsl r0,r0,1Fh
02007820 0FC0 lsr r0,r0,1Fh
02007822 2800 cmp r0,0h
02007824 D015 beq 2007852h
02007826 69E0 ldr r0,[r4,1Ch]
02007828 9009 str r0,[sp,24h]
0200782A 6960 ldr r0,[r4,14h]
0200782C 0A00 lsr r0,r0,8h
0200782E 900B str r0,[sp,2Ch]
02007830 6A22 ldr r2,[r4,20h]
02007832 6A61 ldr r1,[r4,24h]
02007834 9809 ldr r0,[sp,24h]
02007836 1A83 sub r3,r0,r2
02007838 9A0A ldr r2,[sp,28h]
0200783A 418A sbc r2,r1
0200783C 980B ldr r0,[sp,2Ch]
0200783E 1AC5 sub r5,r0,r3
02007840 9E0C ldr r6,[sp,30h]
02007842 4196 sbc r6,r2
02007844 2200 mov r2,0h
02007846 1C31 mov r1,r6
02007848 4051 eor r1,r2
0200784A 1C28 mov r0,r5
0200784C 4050 eor r0,r2
0200784E 4301 orr r1,r0
02007850 D0EE beq 2007830h
02007852 68A0 ldr r0,[r4,8h]
02007854 68E2 ldr r2,[r4,0Ch]
02007856 69A1 ldr r1,[r4,18h]
02007858 0049 lsl r1,r1,1h
0200785A 1851 add r1,r2,r1
0200785C F0B6EA14 blx 20BDC88h
02007860 68E1 ldr r1,[r4,0Ch]
02007862 69A0 ldr r0,[r4,18h]
02007864 0040 lsl r0,r0,1h
02007866 1808 add r0,r1,r0
02007868 496C ldr r1,=100h
0200786A F0A2E8CA blx 20A9A00h
0200786E 69A1 ldr r1,[r4,18h]
02007870 3180 add r1,80h
02007872 61A1 str r1,[r4,18h]
02007874 6960 ldr r0,[r4,14h]
02007876 0840 lsr r0,r0,1h
02007878 4281 cmp r1,r0
0200787A D101 bne 2007880h
0200787C 980D ldr r0,[sp,34h]
0200787E 61A0 str r0,[r4,18h]
02007880 69E0 ldr r0,[r4,1Ch]
02007882 1C40 add r0,r0,1
02007884 61E0 str r0,[r4,1Ch]
02007886 9806 ldr r0,[sp,18h]
02007888 1C41 add r1,r0,1
0200788A 9106 str r1,[sp,18h]
0200788C 9807 ldr r0,[sp,1Ch]
0200788E 4281 cmp r1,r0
02007890 D3C3 bcc 200781Ah
02007892 485F ldr r0,=27E00FCh
02007894 6800 ldr r0,[r0]
02007896 2805 cmp r0,5h
02007898 D111 bne 20078BEh
0200789A 485F ldr r0,=27E029Ch
0200789C 7EC0 ldrb r0,[r0,1Bh]
0200789E 07C0 lsl r0,r0,1Fh
020078A0 0FC0 lsr r0,r0,1Fh
020078A2 2800 cmp r0,0h
020078A4 D00B beq 20078BEh
020078A6 495B ldr r1,=27E027Ch
020078A8 6948 ldr r0,[r1,14h]
020078AA 0A40 lsr r0,r0,9h
020078AC 2200 mov r2,0h
020078AE 1B40 sub r0,r0,r5
020078B0 41B2 sbc r2,r6
020078B2 D204 bcs 20078BEh
020078B4 6888 ldr r0,[r1,8h]
020078B6 F0B6EA1A blx 20BDCECh
020078BA 2001 mov r0,1h
020078BC 9008 str r0,[sp,20h]
020078BE 9808 ldr r0,[sp,20h]
020078C0 2800 cmp r0,0h
020078C2 D186 bne 20077D2h
020078C4 4953 ldr r1,=27E027Ch
020078C6 6B48 ldr r0,[r1,34h]
020078C8 2804 cmp r0,4h
020078CA D382 bcc 20077D2h
020078CC 4852 ldr r0,=27E029Ch
020078CE 7EC0 ldrb r0,[r0,1Bh]
020078D0 07C0 lsl r0,r0,1Fh
020078D2 0FC0 lsr r0,r0,1Fh
020078D4 2800 cmp r0,0h
020078D6 D13C bne 2007952h
020078D8 6888 ldr r0,[r1,8h]
020078DA F0B6EA8E blx 20BDDF8h
020078DE 1C01 mov r1,r0
020078E0 484F ldr r0,=0FFB0FFh
020078E2 F0B2EB5E blx 20B9FA0h
020078E6 1C04 mov r4,r0
020078E8 484A ldr r0,=27E027Ch
020078EA 6880 ldr r0,[r0,8h]
020078EC F0B6EA84 blx 20BDDF8h
020078F0 2100 mov r1,0h
020078F2 9100 str r1,[sp]
020078F4 4A47 ldr r2,=27E027Ch
020078F6 6951 ldr r1,[r2,14h]
020078F8 0849 lsr r1,r1,1h
020078FA 9101 str r1,[sp,4h]
020078FC 9002 str r0,[sp,8h]
020078FE 207F mov r0,7Fh
02007900 9003 str r0,[sp,0Ch]
02007902 4848 ldr r0,=8000h
02007904 9004 str r0,[sp,10h]
02007906 2040 mov r0,40h
02007908 9005 str r0,[sp,14h]
0200790A 6A90 ldr r0,[r2,28h]
0200790C 2101 mov r1,1h
0200790E 68D2 ldr r2,[r2,0Ch]
02007910 1C0B mov r3,r1
02007912 F0B3EA72 blx 20BADF8h
02007916 F0B3E992 blx 20BAC3Ch
0200791A 4A3E ldr r2,=27E027Ch
0200791C 62D0 str r0,[r2,2Ch]
0200791E 00A1 lsl r1,r4,2h
02007920 2000 mov r0,0h
02007922 9000 str r0,[sp]
02007924 6AD0 ldr r0,[r2,2Ch]
02007926 1C0A mov r2,r1
02007928 4B3F ldr r3,=20072D1h
0200792A F0A4EF8C blx 20AC844h
0200792E 2001 mov r0,1h
02007930 2100 mov r1,0h
02007932 4A38 ldr r2,=27E027Ch
02007934 6AD3 ldr r3,[r2,2Ch]
02007936 1C02 mov r2,r0
02007938 409A lsl r2,r3
0200793A 1C0B mov r3,r1
0200793C F0A4EFDC blx 20AC8F8h
02007940 2001 mov r0,1h
02007942 F0A5EA56 blx 20ACDF0h
02007946 4934 ldr r1,=27E029Ch
02007948 7ECA ldrb r2,[r1,1Bh]
0200794A 2001 mov r0,1h
0200794C 4382 bic r2,r0
0200794E 4302 orr r2,r0
02007950 76CA strb r2,[r1,1Bh]
02007952 482F ldr r0,=27E00FCh
02007954 6800 ldr r0,[r0]
02007956 2805 cmp r0,5h
02007958 D052 beq 2007A00h
0200795A 482F ldr r0,=27E029Ch
0200795C 7E00 ldrb r0,[r0,18h]
0200795E 2800 cmp r0,0h
02007960 D114 bne 200798Ch
02007962 4A2C ldr r2,=27E027Ch
02007964 69D4 ldr r4,[r2,1Ch]
02007966 2000 mov r0,0h
02007968 6A13 ldr r3,[r2,20h]
0200796A 6A51 ldr r1,[r2,24h]
0200796C 1AE5 sub r5,r4,r3
0200796E 4188 sbc r0,r1
02007970 6914 ldr r4,[r2,10h]
02007972 2103 mov r1,3h
02007974 434C mul r4,r1
02007976 17E3 asr r3,r4,1Fh
02007978 1B61 sub r1,r4,r5
0200797A 4183 sbc r3,r0
0200797C D306 bcc 200798Ch
0200797E 6890 ldr r0,[r2,8h]
02007980 F0B6E9B4 blx 20BDCECh
02007984 2101 mov r1,1h
02007986 4824 ldr r0,=27E029Ch
02007988 7601 strb r1,[r0,18h]
0200798A E03D b 2007A08h
0200798C 4A22 ldr r2,=27E029Ch
0200798E 7ED0 ldrb r0,[r2,1Bh]
02007990 0780 lsl r0,r0,1Eh
02007992 0FC0 lsr r0,r0,1Fh
02007994 2800 cmp r0,0h
02007996 D0F9 beq 200798Ch
02007998 7ED1 ldrb r1,[r2,1Bh]
0200799A 2002 mov r0,2h
0200799C 4381 bic r1,r0
0200799E 76D1 strb r1,[r2,1Bh]
020079A0 7E91 ldrb r1,[r2,1Ah]
020079A2 7E50 ldrb r0,[r2,19h]
020079A4 4281 cmp r1,r0
020079A6 D1FB bne 20079A0h
020079A8 4820 ldr r0,=20F89B0h
020079AA 6804 ldr r4,[r0]
020079AC 2100 mov r1,0h
020079AE 6001 str r1,[r0]
020079B0 4D1F ldr r5,=20F8930h
020079B2 018B lsl r3,r1,6h
020079B4 18EB add r3,r5,r3
020079B6 6043 str r3,[r0,4h]
020079B8 7E50 ldrb r0,[r2,19h]
020079BA 2800 cmp r0,0h
020079BC D100 bne 20079C0h
020079BE 2101 mov r1,1h
020079C0 4814 ldr r0,=27E027Ch
020079C2 6880 ldr r0,[r0,8h]
020079C4 4A1B ldr r2,=18000h
020079C6 4351 mul r1,r2
020079C8 4A1B ldr r2,=6000000h
020079CA 1889 add r1,r1,r2
020079CC 4A13 ldr r2,=100h
020079CE F0B6E9AA blx 20BDD24h
020079D2 4916 ldr r1,=20F89B0h
020079D4 684B ldr r3,[r1,4h]
020079D6 681A ldr r2,[r3]
020079D8 4818 ldr r0,=400h
020079DA 4302 orr r2,r0
020079DC 601A str r2,[r3]
020079DE 600C str r4,[r1]
020079E0 4A13 ldr r2,=20F8930h
020079E2 01A0 lsl r0,r4,6h
020079E4 1810 add r0,r2,r0
020079E6 6048 str r0,[r1,4h]
020079E8 490B ldr r1,=27E029Ch
020079EA 7E4A ldrb r2,[r1,19h]
020079EC 2001 mov r0,1h
020079EE 4042 eor r2,r0
020079F0 764A strb r2,[r1,19h]
020079F2 4808 ldr r0,=27E027Ch
020079F4 6B02 ldr r2,[r0,30h]
020079F6 1C52 add r2,r2,1
020079F8 6302 str r2,[r0,30h]
020079FA 2000 mov r0,0h
020079FC 7608 strb r0,[r1,18h]
020079FE E003 b 2007A08h
02007A00 4804 ldr r0,=27E027Ch
02007A02 6880 ldr r0,[r0,8h]
02007A04 F0B6E972 blx 20BDCECh
02007A08 F0B3E884 blx 20BAB14h
02007A0C B00E add sp,38h
02007A0E BD70 pop r4-r6,r15
.pool
02007A40 B500 push r14
02007A42 B081 add sp,-4h
02007A44 F7FFFC5C bl 2007300h
02007A48 2100 mov r1,0h
02007A4A 4804 ldr r0,=27E00FCh
02007A4C 6001 str r1,[r0]
02007A4E 4804 ldr r0,=27E027Ch
02007A50 6301 str r1,[r0,30h]
02007A52 4804 ldr r0,=27E029Ch
02007A54 7641 strb r1,[r0,19h]
02007A56 B001 add sp,4h
02007A58 BD00 pop r15
.pool
02007A68 B5F0 push r4-r7,r14
02007A6A B081 add sp,-4h
02007A6C 1C05 mov r5,r0
02007A6E 1C0C mov r4,r1
02007A70 1C16 mov r6,r2
02007A72 1C1F mov r7,r3
02007A74 F0A2ECBA blx 20AA3ECh
02007A78 F0A2EEC8 blx 20AA80Ch
02007A7C 4905 ldr r1,=27E00FCh
02007A7E 604D str r5,[r1,4h]
02007A80 4805 ldr r0,=27E01FCh
02007A82 6084 str r4,[r0,8h]
02007A84 60C6 str r6,[r0,0Ch]
02007A86 6107 str r7,[r0,10h]
02007A88 2000 mov r0,0h
02007A8A 6008 str r0,[r1]
02007A8C F7FFFFD8 bl 2007A40h
02007A90 B001 add sp,4h
02007A92 BDF0 pop r4-r7,r15
.pool | leomontenegro6/megaman-zx-traducao-ptbr | asm/subtitles/originais/020077a0_eu.asm | Assembly | mit | 11,524 |
; ------------------------------------------------------------------------------
;
; This is Sophia8 kernel code
;
; Contains:
;
; * definitions
; * memory mappings
; * kernel methods
;
;-------------------------------------------------------------------------------
DEF __VIDEO_MEM, 0xC000
DEF __COLOR_MEM, 0xDF40
DEF __CONSOLE_X, 0xE000
DEF __CONSOLE_Y, 0xE001
DEF __CURSOR_ON, 0xE002
DEF __VIDEO_MODE, 0xE003
DEF __KEY_BUF_SIZE, 0xE004
DEF __KEY_BUFFER, 0xE005
DEF __CHAR_MEM, 0xE069
DEF __COLUMNS, 40
DEF __ROWS, 20
DEF __VIDEO_WIDTH, 320
DEF __VIDEO_HEIGHT, 200
DEF __KEY_BUF_MAX_SIZE, 100
DEF __BLACK, 0
DEF __MARON, 1
DEF __GREEN, 2
DEF __OLIVE, 3
DEF __NAVY, 4
DEF __PURPLE, 5
DEF __TEAL, 6
DEF __SILVER, 7
DEF __GRAY, 8
DEF __RED, 9
DEF __LIME, 10
DEF __YELLOW, 11
DEF __BLUE, 12
DEF __FUCHSIA, 13
DEF __AQUA, 14
DEF __WHITE, 15
DEF __TEXT_MODE, 0
DEF __BW_MODE, 1
DEF __COLOR_MODE, 2
__VIDEO_MEM: DB 0[8000] ; video memory 320 * 200 (BW)
__COLOR_MEM: DB __WHITE[1000] ; Color Information 8x8 blocks
; 0x00001111 - foreground color
; 0x11110000 - background color
__CONSOLE_X: DB 0 ; Console cursor position X
__CONSOLE_Y: DB 0 ; Console cursor position Y
__CURSOR_ON: DB 0 ; Cursor ON/OFF
__VIDEO_MODE: DB __TEXT_MODE ; video mode:
; 0-text (40/25)
; 1-BW graphics (320/200)
; 2-Color Graphics (320/200)
__KEY_BUF_SIZE: DB 0 ; keyboard buffer size
__KEY_BUFFER: DB 0[100] ; keyboard buffer
__CHAR_MEM: DB 0[2048] ; characters memory 8*8*256
; character set include
#include "charset.asm"
; console input/output methods
__kbhit: RET ; determines if key was pressed
__cgets: RET ; reads a string directly from console
__cscanf: RET ; reads formated values directly from console
__putch: RET ; writes a character to a console
__cputs: RET ; writes a string to a console
__cprintf: RET ; writes formated string to console
__clrsrc: RET ; clears screen
__getch: RET ; reads character from keyboard
| mozdren/Sophia8 | kernel.asm | Assembly | mit | 3,442 |
; ==================================================================
; The input file must contain 2 input entries.
; The input entries are finally stored in the registers "F" and "G"
; ==================================================================
; Initialize the Output Port C & D to 0
MOV XL, 0
OUT C
OUT D
; ====================================
; Read the 1st byte from Input Port A
; ====================================
; Wait until the Ready-Bit is set at Input Port B
:WAIT_FOR_READY_BIT
IN B
MOV D, XL
MOV E, 00000001b
AND D, E
JZ :WAIT_FOR_READY_BIT
; Retrieve the input from Input Port A and process it
IN A
MOV F, XL
; Acknowledge the requested data by setting/resetting the ACK bit
MOV XL, 00000001b
OUT D
MOV XL, 00000000b
OUT D
; ====================================
; Read the 2nd byte from Input Port A
; ====================================
; Wait until the Ready-Bit is set at Input Port B
:WAIT_FOR_READY_BIT_TWO
IN B
MOV D, XL
MOV E, 00000001b
AND D, E
JZ :WAIT_FOR_READY_BIT_TWO
; Retrieve the input from Input Port A and process it
IN A
MOV G, XL
; Acknowledge the requested data by setting/resetting the ACK bit
MOV XL, 00000001b
OUT D
MOV XL, 00000000b
OUT D
HLT | KPU-RISC/KPU | Assembler/AssemblyCode/IN_OUT.asm | Assembly | mit | 1,202 |
BITS 16
start:
mov ax, 07C0h ; Set up 4K stack space after this bootloader
add ax, 288 ; (4096 + 512) / 16 bytes per paragraph
mov ss, ax
mov sp, 4096
mov ax, 07C0h ; Set data segment to where we're loaded
mov ds, ax
jmp keep
keep:
mov si, text_string ; Put string position into SI
call print_string ; Call our string-printing routine
jmp $ ; Jump here - infinite loop!
text_string db 'This is my cool new OS!', 0
print_string: ; Routine: output string in SI to screen
mov ah, 0Eh ; int 10h 'print char' function
.repeat:
lodsb ; Get character from string
cmp al, 0
je .done ; If char is zero, end of string
int 10h ; Otherwise, print it
jmp .repeat
.done:
ret
times 510-($-$$) db 0 ; Pad remainder of boot sector with 0s
dw 0xAA55 ; The standard PC boot signature
| geremyCohen/gecOS | myfirst.asm | Assembly | mit | 820 |
$include(system_includes.asm)
; @author Jos Ahrens
; @date 14/05/2014
start: MOV A,P0 ; Read the switch
JMP case4 ; Select which case to run.
case0: ; CASE 0 -- add 18 to P0 and put it in P1. Compiles & works
ADD A,#18 ; Add 18 to A
JMP eop ; Go to end of program
case1: ; CASE 1 -- multiply P0 by 2, and minus 10, put it in P1. Compiles & works
MOV B,P0 ; Move P0 into B
ADD A,B ; Multiply A by A (B == A)
SUBB A,#10 ; Subtract 10 from A
JMP eop ; Go to end of program
case2: ; CASE 2 -- Multiply P0+5 by 3.
ADD A,#5 ; Add 3 to A
MOV B,A ; B = A
ADD A,B ; Multiply B by 3
ADD A,B ; Straightforward. We add B to A twice (therefore: * 3)
JMP eop ; Go to end of program
case3: ; CASE 3 -- P0 to the power of 2.
MOV B,A ; B = A
MUL AB ; A to the power of 2 is simply A * A
JMP eop ; Go to end of program
case4: ; CASE 4 -- P0 + 256
ADD A,#128 ; Add 256 to A
ADD A,#128
JMP eop ; Go to end of program
eop:
MOV P1,A ; A on the exit port. - Avoid duplicate code by doing it at the end of the program
JMP start ; restart the loop
END ; end the program | Zarthus/School | Year 3 (2014-09 to 2015-02)/Assembly/assignment_4.4.asm | Assembly | mit | 1,097 |
; Listing generated by Microsoft (R) Optimizing Compiler Version 19.15.26504.0
TITLE C:\Source\compiler-explorer\test\cases\vc-regex-example.cpp
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB LIBCMT
INCLUDELIB OLDNAMES
; only here to exercise bug https://github.com/mattgodbolt/compiler-explorer/issues/1337
1234
END
| mattgodbolt/compiler-explorer | test/cases/vc-numbers.asm | Assembly | bsd-2-clause | 333 |
.386p
_DATA segment use32 dword public 'DATA' ;IGNORE
var1 db 2,5,6
var2 dw 4,6,9
var3 dd 11,-11,2,4
var4 db 100 dup (1)
var5 dd 10 dup (?)
_DATA ends ;IGNORE
_TEXT segment use32 dword public 'CODE' ;IGNORE
assume cs:_TEXT,ds:_DATA
start: ;IGNORE
add word ptr [var5+2],50
cmp word ptr [var5+2],50
jne failure
sub word ptr [var5+2],25
cmp word ptr [var5+2],25
jne failure
cmp word ptr var5,0
jne failure
;sub word ptr [liste_bombe+ebp+4+5*4+xy_adder],ou
mov eax,3
mov ebx,2
sub ebx,eax
JA failure
mov eax,2
mov ebx,3
sub ebx,eax
JB failure
cmp ebx,1
jne failure
cmp ebx,2
JA failure
cmp ebx,0
JB failure
cmp ebx,1
JB failure
JA failure
mov eax,-1-(-2+3)
cmp eax,-2
jne failure
mov ebx,2
cmp eax,ebx
jb failure
mov dl,'c'
sub dl,'a'
cmp dl,2
jne failure
xor edi,edi
add edi,14*320
MOV al,0
JMP exitLabel
failure:
mov al,1
exitLabel:
mov ah,4ch ; AH=4Ch - Exit To DOS
int 21h
_TEXT ends ;IGNORE
stackseg segment para stack 'STACK' ;IGNORE
db 1000h dup(?)
stackseg ends ;IGNORE
end start ;IGNORE
| frranck/asm2c | asmTests/addsub.asm | Assembly | mit | 1,042 |
;===============================================================================
; Copyright 2015-2020 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;===============================================================================
;
;
; Purpose: Cryptography Primitive.
; Big Number Operations
;
; Content:
; cpMontRedAdc_BNU()
;
;
; History:
; Extra reduction (R=A-M) has been added to perform MontReduction safe
;
;
%include "asmdefs.inc"
%include "ia_32e.inc"
%include "pcpbnumulschool.inc"
%include "pcpvariant.inc"
%if (_ADCOX_NI_ENABLING_ == _FEATURE_OFF_) || (_ADCOX_NI_ENABLING_ == _FEATURE_TICKTOCK_)
%if (_IPP32E >= _IPP32E_M7) && (_IPP32E < _IPP32E_L9)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; fixed size reduction
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%macro MREDUCE_FIX_STEP 12.nolist
%xdefine %%mSize %1
%xdefine %%X7 %2
%xdefine %%X6 %3
%xdefine %%X5 %4
%xdefine %%X4 %5
%xdefine %%X3 %6
%xdefine %%X2 %7
%xdefine %%X1 %8
%xdefine %%X0 %9
%xdefine %%rSrc %10
%xdefine %%U %11
%xdefine %%rCarry %12
%if %%mSize > 0
mul %%U
xor %%rCarry, %%rCarry
add %%X0, rax
%if %%mSize > 1
mov rax, qword [%%rSrc+sizeof(qword)]
adc %%rCarry, rdx
mul %%U
add %%X1, %%rCarry
adc rdx, 0
xor %%rCarry, %%rCarry
add %%X1, rax
%if %%mSize > 2
mov rax, qword [%%rSrc+sizeof(qword)*2]
adc %%rCarry, rdx
mul %%U
add %%X2, %%rCarry
adc rdx, 0
xor %%rCarry, %%rCarry
add %%X2, rax
%if %%mSize > 3
mov rax, qword [%%rSrc+sizeof(qword)*3]
adc %%rCarry, rdx
mul %%U
add %%X3, %%rCarry
adc rdx, 0
xor %%rCarry, %%rCarry
add %%X3, rax
%if %%mSize == 4
adc %%X4, rdx
adc %%rCarry, 0
add %%X4, qword [rsp+carry]
%endif
%endif ;; mSize==4
%if %%mSize == 3
adc %%X3, rdx
adc %%rCarry, 0
add %%X3, qword [rsp+carry]
%endif
%endif ;; mSize==3
%if %%mSize == 2
adc %%X2, rdx
adc %%rCarry, 0
add %%X2, qword [rsp+carry]
%endif
%endif ;; mSize==2
%if %%mSize == 1
adc %%X1, rdx
adc %%rCarry, 0
add %%X1, qword [rsp+carry]
%endif
%endif ;; mSize==1
adc %%rCarry, 0
mov qword [rsp+carry], %%rCarry
%endmacro
%macro MREDUCE_FIX 14.nolist
%xdefine %%mSize %1
%xdefine %%rDst %2
%xdefine %%rSrc %3
%xdefine %%M0 %4
%xdefine %%X7 %5
%xdefine %%X6 %6
%xdefine %%X5 %7
%xdefine %%X4 %8
%xdefine %%X3 %9
%xdefine %%X2 %10
%xdefine %%X1 %11
%xdefine %%X0 %12
%xdefine %%U %13
%xdefine %%rCarry %14
%if %%mSize > 0
mov %%U, %%X0
imul %%U, %%M0
mov rax, qword [%%rSrc]
MREDUCE_FIX_STEP %%mSize, %%X7,%%X6,%%X5,%%X4,%%X3,%%X2,%%X1,%%X0, %%rSrc, %%U, %%rCarry
%if %%mSize > 1
mov %%U, %%X1
imul %%U, %%M0
mov rax, qword [%%rSrc]
MREDUCE_FIX_STEP %%mSize, %%X0,%%X7,%%X6,%%X5,%%X4,%%X3,%%X2,%%X1, %%rSrc, %%U, %%rCarry
%if %%mSize > 2
mov %%U, %%X2
imul %%U, %%M0
mov rax, qword [%%rSrc]
MREDUCE_FIX_STEP %%mSize, %%X1,%%X0,%%X7,%%X6,%%X5,%%X4,%%X3,%%X2, %%rSrc, %%U, %%rCarry
%if %%mSize > 3 ; mSize == 4
mov %%U, %%X3
imul %%U, %%M0
mov rax, qword [%%rSrc]
MREDUCE_FIX_STEP %%mSize, %%X2,%%X1,%%X0,%%X7,%%X6,%%X5,%%X4,%%X3, %%rSrc, %%U, %%rCarry
mov %%X0, %%X4 ; {X3:X2:X1:X0} = {X7:X6:X5:X4}
sub %%X4, qword [%%rSrc] ; {X7:X6:X5:X4}-= modulus
mov %%X1, %%X5
sbb %%X5, qword [%%rSrc+sizeof(qword)]
mov %%X2, %%X6
sbb %%X6, qword [%%rSrc+sizeof(qword)*2]
mov %%X3, %%X7
sbb %%X7, qword [%%rSrc+sizeof(qword)*3]
sbb %%rCarry, 0
cmovc %%X4, %%X0 ; dst = borrow? {X3:X2:X1:X0} : {X7:X6:X5:X4}
mov qword [%%rDst], %%X4
cmovc %%X5, %%X1
mov qword [%%rDst+sizeof(qword)], %%X5
cmovc %%X6, %%X2
mov qword [%%rDst+sizeof(qword)*2], %%X6
cmovc %%X7, %%X3
mov qword [%%rDst+sizeof(qword)*3], %%X7
%endif
%endif
%endif
%endif
%if %%mSize == 3
mov %%X0, %%X3 ; {X2:X1:X0} = {X5:X4:X3}
sub %%X3, qword [%%rSrc] ; {X5:X4:X3}-= modulus
mov %%X1, %%X4
sbb %%X4, qword [%%rSrc+sizeof(qword)]
mov %%X2, %%X5
sbb %%X5, qword [%%rSrc+sizeof(qword)*2]
sbb %%rCarry, 0
cmovc %%X3, %%X0 ; dst = borrow? {X2:X1:X0} : {X5:X4:X3}
mov qword [%%rDst], %%X3
cmovc %%X4, %%X1
mov qword [%%rDst+sizeof(qword)], %%X4
cmovc %%X5, %%X2
mov qword [%%rDst+sizeof(qword)*2], %%X5
%endif ; mSize==3
%if %%mSize == 2
mov %%X0, %%X2 ; {X1:X0} = {X3:X2}
sub %%X2, qword [%%rSrc] ; {X3:X2}-= modulus
mov %%X1, %%X3
sbb %%X3, qword [%%rSrc+sizeof(qword)]
sbb %%rCarry, 0
cmovc %%X2, %%X0 ; dst = borrow? {X1:X0} : {X3:X2}
mov qword [%%rDst], %%X2
cmovc %%X3, %%X1
mov qword [%%rDst+sizeof(qword)], %%X3
%endif ; mSize==2
%if %%mSize == 1
mov %%X0, %%X1 ; X1 = X0
sub %%X1, qword [%%rSrc] ; X1 -= modulus
sbb %%rCarry, 0
cmovc %%X1, %%X0 ; dst = borrow? X0 : X1
mov qword [%%rDst], %%X1
%endif ; mSize==1
%endmacro
%if (_IPP32E <= _IPP32E_Y8)
;;
;; Pre- Sandy Brige specific code
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; product = + modulus * U0
;; main body: product = + modulus * U0
%macro MLAx1 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
ALIGN IPP_ALIGN_FACTOR
%%L_1:
mul %%U0
xor %%T2, %%T2
add %%T0, qword [%%rDst+%%idx*sizeof(qword)-sizeof(qword)]
adc %%T1, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)]
adc %%T2, rdx
mov qword [%%rDst+%%idx*sizeof(qword)-sizeof(qword)], %%T0
mul %%U0
xor %%T3, %%T3
add %%T1, qword [%%rDst+%%idx*sizeof(qword)]
adc %%T2, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)*2]
adc %%T3, rdx
mov qword [%%rDst+%%idx*sizeof(qword)], %%T1
mul %%U0
xor %%T0, %%T0
add %%T2, qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)]
adc %%T3, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)*3]
adc %%T0, rdx
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)], %%T2
mul %%U0
xor %%T1, %%T1
add %%T3, qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*2]
adc %%T0, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)*4]
adc %%T1, rdx
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*2], %%T3
add %%idx, 4
jnc %%L_1
%endmacro
;; elipogue: product = modulus * U0, (srcLen=4*n+1)
%macro MM_MLAx1_4N_1_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov rax, qword [%%rSrc+sizeof(qword)]
mov %%idx, qword [rsp+counter]
mul %%U0
xor %%T3, %%T3
add %%T1, qword [%%rDst]
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*2]
adc %%T3, rdx
mov qword [%%rDst], %%T1
mul %%U0
xor %%T0, %%T0
add %%T2, qword [%%rDst+sizeof(qword)]
adc %%T3, rax
mov rax, qword [%%rSrc+sizeof(qword)*3]
adc %%T0, rdx
mov qword [%%rDst+sizeof(qword)], %%T2
mul %%U0
add %%T3, qword [%%rDst+sizeof(qword)*2]
adc %%T0, rax
adc rdx, 0
xor rax, rax
mov qword [%%rDst+sizeof(qword)*2], %%T3
add %%T0, qword [%%rDst+sizeof(qword)*3]
adc rdx, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T0
mov qword [%%rDst+sizeof(qword)*4], rdx
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
;; elipogue: product = modulus * U0, (srcLen=4*n+4)
%macro MM_MLAx1_4N_4_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov rax, qword [%%rSrc+sizeof(qword)*2]
mov %%idx, qword [rsp+counter]
mul %%U0
xor %%T3, %%T0
add %%T1, qword [%%rDst+sizeof(qword)]
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*3]
adc %%T3, rdx
mov qword [%%rDst+sizeof(qword)], %%T1
mul %%U0
add %%T2, qword [%%rDst+sizeof(qword)*2]
adc %%T3, rax
adc rdx, 0
xor rax, rax
mov qword [%%rDst+sizeof(qword)*2], %%T2
add %%T3, qword [%%rDst+sizeof(qword)*3]
adc rdx, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T3
mov qword [%%rDst+sizeof(qword)*4], rdx
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
;; elipogue: product = modulus * U0, (srcLen=4*n+3)
%macro MM_MLAx1_4N_3_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov rax, qword [%%rSrc+sizeof(qword)*3]
mov %%idx, qword [rsp+counter]
mul %%U0
add %%T1, qword [%%rDst+sizeof(qword)*2]
adc %%T2, rax
adc rdx, 0
xor rax, rax
mov qword [%%rDst+sizeof(qword)*2], %%T1
add %%T2, qword [%%rDst+sizeof(qword)*3]
adc rdx, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T2
mov qword [%%rDst+sizeof(qword)*4], rdx
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
;; elipogue: product = modulus * U0, (srcLen=4*n+2)
%macro MM_MLAx1_4N_2_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov %%idx, qword [rsp+counter]
xor rax, rax
add %%T1, qword [%%rDst+sizeof(qword)*3]
adc %%T2, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T1
mov qword [%%rDst+sizeof(qword)*4], %%T2
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
%endif
%if (_IPP32E >= _IPP32E_E9)
;;
;; Sandy Brige specific code
;;
%macro MLAx1 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
ALIGN IPP_ALIGN_FACTOR
%%L_1:
mul %%U0
xor %%T2, %%T2
add %%T0, qword [%%rDst+%%idx*sizeof(qword)-sizeof(qword)]
mov qword [%%rDst+%%idx*sizeof(qword)-sizeof(qword)], %%T0
adc %%T1, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)]
adc %%T2, rdx
mul %%U0
xor %%T3, %%T3
add %%T1, qword [%%rDst+%%idx*sizeof(qword)]
mov qword [%%rDst+%%idx*sizeof(qword)], %%T1
adc %%T2, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)*2]
adc %%T3, rdx
mul %%U0
xor %%T0, %%T0
add %%T2, qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)]
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)], %%T2
adc %%T3, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)*3]
adc %%T0, rdx
mul %%U0
xor %%T1, %%T1
add %%T3, qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*2]
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*2], %%T3
adc %%T0, rax
mov rax, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)*4]
adc %%T1, rdx
add %%idx, 4
jnc %%L_1
%endmacro
%macro MM_MLAx1_4N_1_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov rax, qword [%%rSrc+sizeof(qword)]
mov %%idx, qword [rsp+counter]
mul %%U0
xor %%T3, %%T3
add %%T1, qword [%%rDst]
mov qword [%%rDst], %%T1
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*2]
adc %%T3, rdx
mul %%U0
xor %%T0, %%T0
add %%T2, qword [%%rDst+sizeof(qword)]
mov qword [%%rDst+sizeof(qword)], %%T2
adc %%T3, rax
mov rax, qword [%%rSrc+sizeof(qword)*3]
adc %%T0, rdx
mul %%U0
add %%T3, qword [%%rDst+sizeof(qword)*2]
mov qword [%%rDst+sizeof(qword)*2], %%T3
adc %%T0, rax
adc rdx, 0
xor rax, rax
add %%T0, qword [%%rDst+sizeof(qword)*3]
adc rdx, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T0
mov qword [%%rDst+sizeof(qword)*4], rdx
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
%macro MM_MLAx1_4N_4_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov rax, qword [%%rSrc+sizeof(qword)*2]
mov %%idx, qword [rsp+counter]
mul %%U0
xor %%T3, %%T0
add %%T1, qword [%%rDst+sizeof(qword)]
mov qword [%%rDst+sizeof(qword)], %%T1
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*3]
adc %%T3, rdx
mul %%U0
add %%T2, qword [%%rDst+sizeof(qword)*2]
mov qword [%%rDst+sizeof(qword)*2], %%T2
adc %%T3, rax
adc rdx, 0
xor rax, rax
add %%T3, qword [%%rDst+sizeof(qword)*3]
adc rdx, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T3
mov qword [%%rDst+sizeof(qword)*4], rdx
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
%macro MM_MLAx1_4N_3_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov rax, qword [%%rSrc+sizeof(qword)*3]
mov %%idx, qword [rsp+counter]
mul %%U0
add %%T1, qword [%%rDst+sizeof(qword)*2]
mov qword [%%rDst+sizeof(qword)*2], %%T1
adc %%T2, rax
adc rdx, 0
xor rax, rax
add %%T2, qword [%%rDst+sizeof(qword)*3]
adc rdx, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T2
mov qword [%%rDst+sizeof(qword)*4], rdx
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
%macro MM_MLAx1_4N_2_ELOG 8.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
mov %%idx, qword [rsp+counter]
xor rax, rax
add %%T1, qword [%%rDst+sizeof(qword)*3]
adc %%T2, qword [%%rDst+sizeof(qword)*4]
adc rax, 0
mov qword [%%rDst+sizeof(qword)*3], %%T1
mov qword [%%rDst+sizeof(qword)*4], %%T2
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)
%endmacro
%endif
;
; prologue:
; pre-compute:
; - u0 = product[0]*m0
; - u1 = (product[1] + LO(modulo[1]*u0) + HI(modulo[0]*u0) carry(product[0]+LO(modulo[0]*u0)))*m0
;
%macro MMx2_PLOG 10.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%m0 %4
%xdefine %%U0 %5
%xdefine %%U1 %6
%xdefine %%T0 %7
%xdefine %%T1 %8
%xdefine %%T2 %9
%xdefine %%T3 %10
mov %%U0, qword [%%rDst+%%idx*sizeof(qword)] ; product[0]
imul %%U0, %%m0 ; u0 = product[0]*m0
mov rax, qword [%%rSrc+%%idx*sizeof(qword)] ; modulo[0]*u0
mul %%U0
mov %%U1, qword [%%rSrc+%%idx*sizeof(qword)+sizeof(qword)] ; modulo[1]*u0
imul %%U1, %%U0
mov %%T0, rax ; save modulo[0]*u0
mov %%T1, rdx
add rax, qword [rdi+%%idx*sizeof(qword)] ; a[1] = product[1] + LO(modulo[1]*u0)
adc rdx, qword [rdi+%%idx*sizeof(qword)+sizeof(qword)] ; + HI(modulo[0]*u0)
add %%U1, rdx ; + carry(product[0]+LO(modulo[0]*u0))
imul %%U1, %%m0 ; u1 = a[1]*m0
mov rax, qword [%%rSrc+%%idx*sizeof(qword)]
xor %%T2, %%T2
%endmacro
%if (_IPP32E <= _IPP32E_Y8)
;;
;; Pre- Sandy Brige specific code
;;
%macro MM_MLAx2_4N_1_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += modulus[mSize-1]*U1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T0, qword [%%rDst+sizeof(qword)*3]
adc %%T1, rax
mov qword [%%rDst+sizeof(qword)*3], %%T0
adc %%T2, rdx
xor rax, rax
add %%T1, qword [%%rDst+sizeof(qword)*4]
adc %%T2, qword [%%rDst+sizeof(qword)*5]
adc rax, 0
add %%T1, qword [rsp+carry]
adc %%T2, 0
adc rax, 0
mov qword [%%rDst+sizeof(qword)*4], %%T1
mov qword [%%rDst+sizeof(qword)*5], %%T2
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%macro MM_MLAx2_4N_2_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += a[mSize-2]*U1
xor %%T3, %%T3
add %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T2, rdx
mul %%U0 ; {T3:T2:T1} += a[mSize-1]*U0 + r[mSize-2]
add %%T0, qword [%%rDst+sizeof(qword)*2]
adc %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T2, rdx
mov qword [%%rDst+sizeof(qword)*2], %%T0
adc %%T3, 0
mul %%U1 ; {T3:T2} += a[mSize-1]*B1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T1, qword [%%rDst+sizeof(qword)*3]
adc %%T2, rax
mov qword [%%rDst+sizeof(qword)*3], %%T1
adc %%T3, rdx
xor rax, rax
add %%T2, qword [%%rDst+sizeof(qword)*4]
adc %%T3, qword [%%rDst+sizeof(qword)*5]
adc rax, 0
add %%T2, qword [rsp+carry]
adc %%T3, 0
adc rax, 0
mov qword [%%rDst+sizeof(qword)*4], %%T2
mov qword [%%rDst+sizeof(qword)*5], %%T3
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%macro MM_MLAx2_4N_3_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += a[mSize-3]*U1
xor %%T3, %%T3
add %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a[mSize-2]
adc %%T2, rdx
mul %%U0 ; {T3:T2:T1} += a[mSize-2]*U0 + r[mSize-3]
add %%T0, qword [%%rDst+sizeof(qword)]
adc %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a[mSize-2]
adc %%T2, rdx
mov qword [%%rDst+sizeof(qword)], %%T0
adc %%T3, 0
mul %%U1 ; {T3:T2} += a[mSize-2]*U1
xor %%T0, %%T0
add %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T3, rdx
mul %%U0 ; {T0:T3:T2} += a[mSize-1]*U0 + r[mSize-2]
add %%T1, qword [rdi+sizeof(qword)*2]
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T3, rdx
mov qword [rdi+sizeof(qword)*2], %%T1
adc %%T0, 0
mul %%U1 ; {T0:T3} += a[mSize-1]*U1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T2, qword [rdi+sizeof(qword)*3]
adc %%T3, rax
mov qword [rdi+sizeof(qword)*3], %%T2
adc %%T0, rdx
xor rax, rax
add %%T3, qword [rdi+sizeof(qword)*4]
adc %%T0, qword [rdi+sizeof(qword)*5]
adc rax, 0
add %%T3, qword [rsp+carry]
adc %%T0, 0
adc rax, 0
mov qword [rdi+sizeof(qword)*4], %%T3
mov qword [rdi+sizeof(qword)*5], %%T0
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%macro MM_MLAx2_4N_4_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += a[mSize-4]*U1
xor %%T3, %%T3
add %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)] ; a[lenA-3]
adc %%T2, rdx
mul %%U0 ; {T3:T2:T1} += a[mSize-3]*U0 + r[mSize-4]
add %%T0, qword [%%rDst]
adc %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)] ; a[mSize-3]
adc %%T2, rdx
mov qword [%%rDst], %%T0
adc %%T3, 0
mul %%U1 ; {T3:T2} += a[mSize-3]*U1
xor %%T0, %%T0
add %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a[mSize-2]
adc %%T3, rdx
mul %%U0 ; {T0:T3:T2} += a[mSize-2]*U0 + r[mSize-3]
add %%T1, qword [%%rDst+sizeof(qword)]
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a{lenA-2]
adc %%T3, rdx
mov qword [%%rDst+sizeof(qword)], %%T1
adc %%T0, 0
mul %%U1 ; {T0:T3} += a[mSize-2]*U1
xor %%T1, %%T1
add %%T3, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T0, rdx
mul %%U0 ; {T1:T0:T3} += a[mSize-1]*U0 + r[mSize-2]
add %%T2, qword [%%rDst+sizeof(qword)*2]
adc %%T3, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T0, rdx
mov qword [%%rDst+sizeof(qword)*2], %%T2
adc %%T1, 0
mul %%U1 ; {T1:T0} += a[mSize-1]*U1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T3, qword [%%rDst+sizeof(qword)*3]
adc %%T0, rax
mov qword [%%rDst+sizeof(qword)*3], %%T3
adc %%T1, rdx
xor rax, rax
add %%T0, qword [%%rDst+sizeof(qword)*4]
adc %%T1, qword [%%rDst+sizeof(qword)*5]
adc rax, 0
add %%T0, qword [rsp+carry]
adc %%T1, 0
adc rax, 0
mov qword [%%rDst+sizeof(qword)*4], %%T0
mov qword [%%rDst+sizeof(qword)*5], %%T1
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%endif
%if (_IPP32E >= _IPP32E_E9)
;;
;; Sandy Brige specific code
;;
%macro MM_MLAx2_4N_1_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += modulus[mSize-1]*U1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T0, qword [%%rDst+sizeof(qword)*3]
mov qword [%%rDst+sizeof(qword)*3], %%T0
adc %%T1, rax
adc %%T2, rdx
xor rax, rax
add %%T1, qword [%%rDst+sizeof(qword)*4]
adc %%T2, qword [%%rDst+sizeof(qword)*5]
adc rax, 0
add %%T1, qword [rsp+carry]
adc %%T2, 0
adc rax, 0
mov qword [%%rDst+sizeof(qword)*4], %%T1
mov qword [%%rDst+sizeof(qword)*5], %%T2
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%macro MM_MLAx2_4N_2_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += a[mSize-2]*U1
xor %%T3, %%T3
add %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T2, rdx
mul %%U0 ; {T3:T2:T1} += a[mSize-1]*U0 + r[mSize-2]
add %%T0, qword [%%rDst+sizeof(qword)*2]
mov qword [%%rDst+sizeof(qword)*2], %%T0
adc %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T2, rdx
adc %%T3, 0
mul %%U1 ; {T3:T2} += a[mSize-1]*B1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T1, qword [%%rDst+sizeof(qword)*3]
mov qword [%%rDst+sizeof(qword)*3], %%T1
adc %%T2, rax
adc %%T3, rdx
xor rax, rax
add %%T2, qword [%%rDst+sizeof(qword)*4]
adc %%T3, qword [%%rDst+sizeof(qword)*5]
adc rax, 0
add %%T2, qword [rsp+carry]
adc %%T3, 0
adc rax, 0
mov qword [%%rDst+sizeof(qword)*4], %%T2
mov qword [%%rDst+sizeof(qword)*5], %%T3
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%macro MM_MLAx2_4N_3_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += a[mSize-3]*U1
xor %%T3, %%T3
add %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a[mSize-2]
adc %%T2, rdx
mul %%U0 ; {T3:T2:T1} += a[mSize-2]*U0 + r[mSize-3]
add %%T0, qword [%%rDst+sizeof(qword)]
mov qword [%%rDst+sizeof(qword)], %%T0
adc %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a[mSize-2]
adc %%T2, rdx
adc %%T3, 0
mul %%U1 ; {T3:T2} += a[mSize-2]*U1
xor %%T0, %%T0
add %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T3, rdx
mul %%U0 ; {T0:T3:T2} += a[mSize-1]*U0 + r[mSize-2]
add %%T1, qword [rdi+sizeof(qword)*2]
mov qword [rdi+sizeof(qword)*2], %%T1
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T3, rdx
adc %%T0, 0
mul %%U1 ; {T0:T3} += a[mSize-1]*U1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T2, qword [rdi+sizeof(qword)*3]
mov qword [rdi+sizeof(qword)*3], %%T2
adc %%T3, rax
adc %%T0, rdx
xor rax, rax
add %%T3, qword [rdi+sizeof(qword)*4]
adc %%T0, qword [rdi+sizeof(qword)*5]
adc rax, 0
add %%T3, qword [rsp+carry]
adc %%T0, 0
adc rax, 0
mov qword [rdi+sizeof(qword)*4], %%T3
mov qword [rdi+sizeof(qword)*5], %%T0
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%macro MM_MLAx2_4N_4_ELOG 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc %2
%xdefine %%idx %3
%xdefine %%U0 %4
%xdefine %%U1 %5
%xdefine %%T0 %6
%xdefine %%T1 %7
%xdefine %%T2 %8
%xdefine %%T3 %9
mul %%U1 ; {T2:T1} += a[mSize-4]*U1
xor %%T3, %%T3
add %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)] ; a[lenA-3]
adc %%T2, rdx
mul %%U0 ; {T3:T2:T1} += a[mSize-3]*U0 + r[mSize-4]
add %%T0, qword [%%rDst]
mov qword [%%rDst], %%T0
adc %%T1, rax
mov rax, qword [%%rSrc+sizeof(qword)] ; a[mSize-3]
adc %%T2, rdx
adc %%T3, 0
mul %%U1 ; {T3:T2} += a[mSize-3]*U1
xor %%T0, %%T0
add %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a[mSize-2]
adc %%T3, rdx
mul %%U0 ; {T0:T3:T2} += a[mSize-2]*U0 + r[mSize-3]
add %%T1, qword [%%rDst+sizeof(qword)]
mov qword [%%rDst+sizeof(qword)], %%T1
adc %%T2, rax
mov rax, qword [%%rSrc+sizeof(qword)*2] ; a{lenA-2]
adc %%T3, rdx
adc %%T0, 0
mul %%U1 ; {T0:T3} += a[mSize-2]*U1
xor %%T1, %%T1
add %%T3, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T0, rdx
mul %%U0 ; {T1:T0:T3} += a[mSize-1]*U0 + r[mSize-2]
add %%T2, qword [%%rDst+sizeof(qword)*2]
mov qword [%%rDst+sizeof(qword)*2], %%T2
adc %%T3, rax
mov rax, qword [%%rSrc+sizeof(qword)*3] ; a[mSize-1]
adc %%T0, rdx
adc %%T1, 0
mul %%U1 ; {T1:T0} += a[mSize-1]*U1 + r[mSize-1]
mov %%idx, qword [rsp+counter]
add %%T3, qword [%%rDst+sizeof(qword)*3]
mov qword [%%rDst+sizeof(qword)*3], %%T3
adc %%T0, rax
adc %%T1, rdx
xor rax, rax
add %%T0, qword [%%rDst+sizeof(qword)*4]
adc %%T1, qword [%%rDst+sizeof(qword)*5]
adc rax, 0
add %%T0, qword [rsp+carry]
adc %%T1, 0
adc rax, 0
mov qword [%%rDst+sizeof(qword)*4], %%T0
mov qword [%%rDst+sizeof(qword)*5], %%T1
mov qword [rsp+carry], rax
add %%rDst, sizeof(qword)*2
%endmacro
%endif
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%macro SBB_x4 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc1 %2
%xdefine %%rSrc2 %3
%xdefine %%idx %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
%xdefine %%rcf %9
ALIGN IPP_ALIGN_FACTOR
%%L_1:
add %%rcf, %%rcf ; restore cf
mov %%T0, qword [%%rSrc1+%%idx*sizeof(qword)]
sbb %%T0, qword [%%rSrc2+%%idx*sizeof(qword)]
mov qword [%%rDst+%%idx*sizeof(qword)], %%T0
mov %%T1, qword [%%rSrc1+%%idx*sizeof(qword)+sizeof(qword)]
sbb %%T1, qword [%%rSrc2+%%idx*sizeof(qword)+sizeof(qword)]
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)], %%T1
mov %%T2, qword [%%rSrc1+%%idx*sizeof(qword)+sizeof(qword)*2]
sbb %%T2, qword [%%rSrc2+%%idx*sizeof(qword)+sizeof(qword)*2]
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*2], %%T2
mov %%T3, qword [%%rSrc1+%%idx*sizeof(qword)+sizeof(qword)*3]
sbb %%T3, qword [%%rSrc2+%%idx*sizeof(qword)+sizeof(qword)*3]
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*3], %%T3
sbb %%rcf, %%rcf ; save cf
add %%idx, 4
jnc %%L_1
%endmacro
%macro SBB_TAIL 9.nolist
%xdefine %%N %1
%xdefine %%rDst %2
%xdefine %%rSrc1 %3
%xdefine %%rSrc2 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
%xdefine %%rcf %9
add %%rcf, %%rcf ; restore cf
mov idx, qword [rsp+counter] ; restore counter
%if %%N > 3
mov %%T0, qword [%%rSrc1]
sbb %%T0, qword [%%rSrc2]
mov qword [%%rDst], %%T0
%endif
%if %%N > 2
mov %%T1, qword [%%rSrc1+sizeof(qword)]
sbb %%T1, qword [%%rSrc2+sizeof(qword)]
mov qword [%%rDst+sizeof(qword)], %%T1
%endif
%if %%N > 1
mov %%T2, qword [%%rSrc1+sizeof(qword)*2]
sbb %%T2, qword [%%rSrc2+sizeof(qword)*2]
mov qword [%%rDst+sizeof(qword)*2], %%T2
%endif
%if %%N > 0
mov %%T3, qword [%%rSrc1+sizeof(qword)*3]
sbb %%T3, qword [%%rSrc2+sizeof(qword)*3]
mov qword [%%rDst+sizeof(qword)*3], %%T3
%endif
sbb rax, 0
sbb %%rcf, %%rcf ; set cf
%endmacro
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; dst[] = cf? src1[] : src2[]
%macro CMOV_x4 9.nolist
%xdefine %%rDst %1
%xdefine %%rSrc1 %2
%xdefine %%rSrc2 %3
%xdefine %%idx %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
%xdefine %%rcf %9
mov %%T3, %%rcf ; copy cf
ALIGN IPP_ALIGN_FACTOR
%%L_1:
add %%T3, %%T3 ; restore cf
mov %%T0, qword [%%rSrc2+%%idx*sizeof(qword)]
mov %%T1, qword [%%rSrc1+%%idx*sizeof(qword)]
mov %%T2, qword [%%rSrc2+%%idx*sizeof(qword)+sizeof(qword)]
mov %%T3, qword [%%rSrc1+%%idx*sizeof(qword)+sizeof(qword)]
cmovc %%T0, %%T1
mov qword [%%rDst+%%idx*sizeof(qword)], %%T0
cmovc %%T2, %%T3
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)], %%T2
mov %%T0, qword [%%rSrc2+%%idx*sizeof(qword)+sizeof(qword)*2]
mov %%T1, qword [%%rSrc1+%%idx*sizeof(qword)+sizeof(qword)*2]
mov %%T2, qword [%%rSrc2+%%idx*sizeof(qword)+sizeof(qword)*3]
mov %%T3, qword [%%rSrc1+%%idx*sizeof(qword)+sizeof(qword)*3]
cmovc %%T0, %%T1
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*2], %%T0
cmovc %%T2, %%T3
mov qword [%%rDst+%%idx*sizeof(qword)+sizeof(qword)*3], %%T2
mov %%T3, %%rcf ; copy cf
add %%idx, 4
jnc %%L_1
%endmacro
%macro CMOV_TAIL 9.nolist
%xdefine %%N %1
%xdefine %%rDst %2
%xdefine %%rSrc1 %3
%xdefine %%rSrc2 %4
%xdefine %%T0 %5
%xdefine %%T1 %6
%xdefine %%T2 %7
%xdefine %%T3 %8
%xdefine %%rcf %9
add %%rcf, %%rcf ; restore cf
mov idx, qword [rsp+counter] ; restore counter
%if %%N > 3
mov %%T0, qword [%%rSrc2]
mov %%T1, qword [%%rSrc1]
cmovc %%T0, %%T1
mov qword [%%rDst], %%T0
%endif
%if %%N > 2
mov %%T2, qword [%%rSrc2+sizeof(qword)]
mov %%T3, qword [%%rSrc1+sizeof(qword)]
cmovc %%T2, %%T3
mov qword [%%rDst+sizeof(qword)], %%T2
%endif
%if %%N > 1
mov %%T0, qword [%%rSrc2+sizeof(qword)*2]
mov %%T1, qword [%%rSrc1+sizeof(qword)*2]
cmovc %%T0, %%T1
mov qword [%%rDst+sizeof(qword)*2], %%T0
%endif
%if %%N > 0
mov %%T2, qword [%%rSrc2+sizeof(qword)*3]
mov %%T3, qword [%%rSrc1+sizeof(qword)*3]
cmovc %%T2, %%T3
mov qword [%%rDst+sizeof(qword)*3], %%T2
%endif
%endmacro
segment .text align=IPP_ALIGN_FACTOR
;*************************************************************
;* void cpMontRedAdc_BNU(Ipp64u* pR,
;* Ipp64u* pBuffer,
;* const Ipp64u* pModulo, int mSize, Ipp64u m0)
;*
;*************************************************************
;;
;; Lib = M7
;;
;; Caller = ippsMontMul
;;
align IPP_ALIGN_FACTOR
IPPASM cpMontRedAdc_BNU,PUBLIC
%assign LOCAL_FRAME (1+1+1+1)*sizeof(qword)
USES_GPR rbx,rbp,rsi,rdi,r12,r13,r14,r15
USES_XMM
COMP_ABI 5
;pR (rdi) address of the reduction
;pBuffer (rsi) address of the temporary product
;pModulo (rdx) address of the modulus
;mSize (rcx) size of the modulus
;m0 (r8) helper
;;
;; stack structure:
%assign pR (0) ; reduction address
%assign mSize (pR+sizeof(qword)) ; modulus length (qwords)
%assign carry (mSize+sizeof(qword)) ; carry from previous MLAx1 or MLAx2 operation
%assign counter (carry+sizeof(qword)) ; counter = 4-mSize
mov qword [rsp+carry], 0 ; clear carry
movsxd rcx, ecx ; expand modulus length
mov r15, r8 ; helper m0
cmp rcx, 5
jge .general_case
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; reducer of the fixed sizes
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
cmp rcx, 3
ja .mSize_4 ; rcx=4
jz .mSize_3 ; rcx=3
jp .mSize_2 ; rcx=2
; mSize_1 ; rcx=1
%xdefine X0 r8
%xdefine X1 r9
%xdefine X2 r10
%xdefine X3 r11
%xdefine X4 r12
%xdefine X5 r13
%xdefine X6 r14
%xdefine X7 rcx
align IPP_ALIGN_FACTOR
.mSize_1:
mov X0, qword [rsi]
mov X1, qword [rsi+sizeof(qword)]
mov rsi, rdx
; rDst,rSrc, U, M0, T0
MREDUCE_FIX 1, rdi, rsi, r15, X7, X6, X5, X4, X3, X2, X1,X0, rbp,rbx
jmp .quit
align IPP_ALIGN_FACTOR
.mSize_2:
mov X0, qword [rsi]
mov X1, qword [rsi+sizeof(qword)]
mov X2, qword [rsi+sizeof(qword)*2]
mov X3, qword [rsi+sizeof(qword)*3]
mov rsi, rdx
MREDUCE_FIX 2, rdi, rsi, r15, X7, X6, X5, X4, X3, X2, X1,X0, rbp,rbx
jmp .quit
align IPP_ALIGN_FACTOR
.mSize_3:
mov X0, qword [rsi]
mov X1, qword [rsi+sizeof(qword)]
mov X2, qword [rsi+sizeof(qword)*2]
mov X3, qword [rsi+sizeof(qword)*3]
mov X4, qword [rsi+sizeof(qword)*4]
mov X5, qword [rsi+sizeof(qword)*5]
mov rsi, rdx
MREDUCE_FIX 3, rdi, rsi, r15, X7, X6, X5, X4, X3, X2, X1,X0, rbp,rbx
jmp .quit
align IPP_ALIGN_FACTOR
.mSize_4:
mov X0, qword [rsi]
mov X1, qword [rsi+sizeof(qword)]
mov X2, qword [rsi+sizeof(qword)*2]
mov X3, qword [rsi+sizeof(qword)*3]
mov X4, qword [rsi+sizeof(qword)*4]
mov X5, qword [rsi+sizeof(qword)*5]
mov X6, qword [rsi+sizeof(qword)*6]
mov X7, qword [rsi+sizeof(qword)*7]
mov rsi, rdx
MREDUCE_FIX 4, rdi, rsi, r15, X7, X6, X5, X4, X3, X2, X1,X0, rbp,rbx
jmp .quit
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; general case reducer
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%xdefine U0 r9 ; u0, u1
%xdefine U1 r10
%xdefine T0 r11 ; temporary
%xdefine T1 r12
%xdefine T2 r13
%xdefine T3 r14
%xdefine idx rbx ; index
%xdefine rDst rdi
%xdefine rSrc rsi
align IPP_ALIGN_FACTOR
.general_case:
lea rdi, [rdi+rcx*sizeof(qword)-sizeof(qword)*4] ; save pR+mSzie-4
mov qword [rsp+pR], rdi ; save pR
;mov qword [rsp+mSize], rcx ; save length of modulus
mov rdi, rsi ; rdi = pBuffer
mov rsi, rdx ; rsi = pModulo
lea rdi, [rdi+rcx*sizeof(qword)-sizeof(qword)*4] ; rdi = pBuffer
lea rsi, [rsi+rcx*sizeof(qword)-sizeof(qword)*4] ; rsi = pModulus
mov idx, dword 4 ; init negative counter
sub idx, rcx
mov qword [rsp+counter], idx
mov rdx, dword 3
and rdx, rcx
test rcx,1
jz .even_len_Modulus
;
; modulus of odd length
;
.odd_len_Modulus:
mov U0, qword [rDst+idx*sizeof(qword)] ; pBuffer[0]
imul U0, r15 ; u0 = pBuffer[0]*m0
mov rax, qword [rSrc+idx*sizeof(qword)] ; pModulo[0]
mul U0 ; prologue
mov T0, rax
mov rax, qword [rSrc+idx*sizeof(qword)+sizeof(qword)]
mov T1, rdx
add idx, 1
jz .skip_mlax1
MLAx1 rdi, rsi, idx, U0, T0,T1,T2,T3 ; pBuffer[] += pModulo[]*u
.skip_mlax1:
mul U0
xor T2, T2
add qword [rDst+idx*sizeof(qword)-sizeof(qword)], T0
adc T1, rax
adc T2, rdx
cmp idx, 2
ja .fin_mla1x4n_2 ; idx=3
jz .fin_mla1x4n_3 ; idx=2
jp .fin_mla1x4n_4 ; idx=1
; fin_mla1x4n_1 ; idx=0
.fin_mla1x4n_1:
MM_MLAx1_4N_1_ELOG rdi, rsi, idx, U0, T0,T1,T2,T3 ; [rsp+carry] = rax = cf = pBuffer[]+pModulo[]*u
sub rcx, 1
jmp .mla2x4n_1
.fin_mla1x4n_4:
MM_MLAx1_4N_4_ELOG rdi, rsi, idx, U0, T0,T1,T2,T3 ; [rsp+carry] = rax = cf = pBuffer[]+pModulo[]*u
sub rcx, 1
jmp .mla2x4n_4
.fin_mla1x4n_3:
MM_MLAx1_4N_3_ELOG rdi, rsi, idx, U0, T0,T1,T2,T3 ; [rsp+carry] = rax = cf = pBuffer[]+pModulo[]*u
sub rcx, 1
jmp .mla2x4n_3
.fin_mla1x4n_2:
MM_MLAx1_4N_2_ELOG rdi, rsi, idx, U0, T0,T1,T2,T3 ; [rsp+carry] = rax = cf = pBuffer[]+pModulo[]*u
sub rcx, 1
jmp .mla2x4n_2
align IPP_ALIGN_FACTOR
;
; modulus of even length
;
.even_len_Modulus:
xor rax, rax ; clear carry
cmp rdx, 2
ja .mla2x4n_1 ; rdx=1
jz .mla2x4n_2 ; rdx=2
jp .mla2x4n_3 ; rdx=3
; mla2x4n_4 ; rdx=0
align IPP_ALIGN_FACTOR
.mla2x4n_4:
MMx2_PLOG rdi, rsi, idx, r15, U0,U1,T0,T1,T2,T3 ; pre-compute u0 and u1
MLAx2 rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; rax = cf = product[]+modulo[]*{u1:u0}
MM_MLAx2_4N_4_ELOG rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; [rsp+carry] = rax = cf
sub rcx, 2
jnz .mla2x4n_4
; (borrow, pR) = (carry,product) - modulo
mov rdx, qword [rsp+pR]
xor rcx, rcx
SBB_x4 rdx, rdi, rsi, idx, T0,T1,T2,T3, rcx
SBB_TAIL 4, rdx, rdi, rsi, T0,T1,T2,T3, rcx
; pR = borrow? product : pR
CMOV_x4 rdx, rdi, rdx, idx, T0,T1,T2,T3, rcx
CMOV_TAIL 4, rdx, rdi, rdx, T0,T1,T2,T3, rcx
jmp .quit
align IPP_ALIGN_FACTOR
.mla2x4n_3:
MMx2_PLOG rdi, rsi, idx, r15, U0,U1,T0,T1,T2,T3 ; pre-compute u0 and u1
MLAx2 rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; rax = cf = product[]+modulo[]*{u1:u0}
MM_MLAx2_4N_3_ELOG rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; [rsp+carry] = rax = cf
sub rcx, 2
jnz .mla2x4n_3
; (borrow, pR) = (carry,product) - modulo
mov rdx, qword [rsp+pR]
xor rcx, rcx
SBB_x4 rdx, rdi, rsi, idx, T0,T1,T2,T3, rcx
SBB_TAIL 3, rdx, rdi, rsi, T0,T1,T2,T3, rcx
; pR = borrow? product : pR
CMOV_x4 rdx, rdi, rdx, idx, T0,T1,T2,T3, rcx
CMOV_TAIL 3, rdx, rdi, rdx, T0,T1,T2,T3, rcx
jmp .quit
align IPP_ALIGN_FACTOR
.mla2x4n_2:
MMx2_PLOG rdi, rsi, idx, r15, U0,U1,T0,T1,T2,T3 ; pre-compute u0 and u1
MLAx2 rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; rax = cf = product[]+modulo[]*{u1:u0}
MM_MLAx2_4N_2_ELOG rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; [rsp+carry] = rax = cf
sub rcx, 2
jnz .mla2x4n_2
; (borrow, pR) = (carry,product) - modulo
mov rdx, qword [rsp+pR]
xor rcx, rcx
SBB_x4 rdx, rdi, rsi, idx, T0,T1,T2,T3, rcx
SBB_TAIL 2, rdx, rdi, rsi, T0,T1,T2,T3, rcx
; pR = borrow? product : pR
CMOV_x4 rdx, rdi, rdx, idx, T0,T1,T2,T3, rcx
CMOV_TAIL 2, rdx, rdi, rdx, T0,T1,T2,T3, rcx
jmp .quit
align IPP_ALIGN_FACTOR
.mla2x4n_1:
MMx2_PLOG rdi, rsi, idx, r15, U0,U1,T0,T1,T2,T3 ; pre-compute u0 and u1
MLAx2 rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; rax = cf = product[]+modulo[]*{u1:u0}
MM_MLAx2_4N_1_ELOG rdi, rsi, idx, U0,U1, T0,T1,T2,T3 ; [rsp+carry] = rax = cf
sub rcx, 2
jnz .mla2x4n_1
; (borrow, pR) = (carry,product) - modulo
mov rdx, qword [rsp+pR]
xor rcx, rcx
SBB_x4 rdx, rdi, rsi, idx, T0,T1,T2,T3, rcx
SBB_TAIL 1, rdx, rdi, rsi, T0,T1,T2,T3, rcx
; pR = borrow? product : pR
CMOV_x4 rdx, rdi, rdx, idx, T0,T1,T2,T3, rcx
CMOV_TAIL 1, rdx, rdi, rdx, T0,T1,T2,T3, rcx
.quit:
REST_XMM
REST_GPR
ret
ENDFUNC cpMontRedAdc_BNU
%endif
%endif ;; _ADCOX_NI_ENABLING_
| Intel-EPID-SDK/epid-sdk | ext/ipp-crypto/sources/ippcp/asm_intel64/pcpmontreductionm7as.asm | Assembly | apache-2.0 | 43,457 |
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//------------------------------------------------------------------------------
#include <AsmMacroIoLib.h>
#include <Library/PcdLib.h>
#include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc
IMPORT CEntryPoint
EXPORT _ModuleEntryPoint
PRESERVE8
AREA ModuleEntryPoint, CODE, READONLY
_ModuleEntryPoint
//Disable L2 cache
mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
bic r0, r0, #0x00000002 // disable L2 cache
mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
//Enable Strict alignment checking & Instruction cache
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0
// Enable NEON register in case folks want to use them for optimizations (CopyMem)
mrc p15, 0, r0, c1, c0, 2
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
mcr p15, 0, r0, c1, c0, 2
mov r0, #0x40000000 // Set EN bit in FPEXC
msr FPEXC,r0
// Set CPU vectors to start of DRAM
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
mcr p15, 0, r0, c12, c0, 0
isb // Sync changes to control registers
// Fill vector table with branchs to current pc (jmp $)
ldr r1, ShouldNeverGetHere
movs r2, #0
FillVectors
str r1, [r0, r2]
adds r2, r2, #4
cmp r2, #32
bne FillVectors
/* before we call C code, lets setup the stack pointer in internal RAM */
stack_pointer_setup
//
// Set stack based on PCD values. Need to do it this way to make C code work
// when it runs from FLASH.
//
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2
LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3
add r4, r2, r3
//Enter SVC mode and set up SVC stack pointer
mov r5,#0x13|0x80|0x40
msr CPSR_c,r5
mov r13,r4
// Call C entry point
LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1
LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0
blx CEntryPoint // Assume C code is thumb
ShouldNeverGetHere
/* _CEntryPoint should never return */
b ShouldNeverGetHere
END
| MarvellEmbeddedProcessors/edk2-open-platform | Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ModuleEntryPoint.asm | Assembly | bsd-2-clause | 3,197 |
;Testname=test; Arguments=-fbin -ofpu.bin; Files=stdout stderr fpu.bin
; relaxed encodings for FPU instructions, which NASM should support
; -----------------------------------------------------------------
%define void
%define reg_fpu0 st0
%define reg_fpu st1
; no operands instead of one operand:
; F(U)COM(P), FCOM2, FCOMP3, FCOMP5
FCOM void
FCOMP void
FUCOM void
FUCOMP void
; FCOM2 void
; FCOMP3 void
; FCOMP5 void
; FLD, FST, FSTP, FSTP1, FSTP8, FSTP9
FLD void
FST void
FSTP void
; FSTP1 void
; FSTP8 void
; FSTP9 void
; FXCH, FXCH4, FXCH7, FFREE, FFREEP
FXCH void
; FXCH4 void
; FXCH7 void
FFREE void
FFREEP void
; no operands instead of two operands:
; FADD(P), FMUL(P), FSUBR(P), FSUB(P), FDIVR(P), FDIV(P)
FADD void
FADDP void
FMUL void
FMULP void
FSUBR void
FSUBRP void
FSUB void
FSUBP void
FDIVR void
FDIVRP void
FDIV void
FDIVP void
; one operand instead of two operands:
; FADD, FMUL, FSUB, FSUBR, FDIV, FDIVR
FADD reg_fpu
FMUL reg_fpu
FSUB reg_fpu
FSUBR reg_fpu
FDIV reg_fpu
FDIVR reg_fpu
; FADD, FMUL, FSUBR, FSUB, FDIVR, FDIV (with TO qualifier)
FADD to reg_fpu
FMUL to reg_fpu
FSUBR to reg_fpu
FSUB to reg_fpu
FDIVR to reg_fpu
FDIV to reg_fpu
; FADDP, FMULP, FSUBRP, FSUBP, FDIVRP, FDIVP
FADDP reg_fpu
FMULP reg_fpu
FSUBRP reg_fpu
FSUBP reg_fpu
FDIVRP reg_fpu
FDIVP reg_fpu
; FCMOV(N)B, FCMOV(N)E, FCMOV(N)BE, FCMOV(N)U, and F(U)COMI(P)
FCMOVB reg_fpu
FCMOVNB reg_fpu
FCMOVE reg_fpu
FCMOVNE reg_fpu
FCMOVBE reg_fpu
FCMOVNBE reg_fpu
FCMOVU reg_fpu
FCMOVNU reg_fpu
FCOMI reg_fpu
FCOMIP reg_fpu
FUCOMI reg_fpu
FUCOMIP reg_fpu
; two operands instead of one operand:
; these don't really exist, and thus are _NOT_ supported:
; FCOM reg_fpu,reg_fpu0
; FCOM reg_fpu0,reg_fpu
; FUCOM reg_fpu,reg_fpu0
; FUCOM reg_fpu0,reg_fpu
; FCOMP reg_fpu,reg_fpu0
; FCOMP reg_fpu0,reg_fpu
; FUCOMP reg_fpu,reg_fpu0
; FUCOMP reg_fpu0,reg_fpu
; FCOM2 reg_fpu,reg_fpu0
; FCOM2 reg_fpu0,reg_fpu
; FCOMP3 reg_fpu,reg_fpu0
; FCOMP3 reg_fpu0,reg_fpu
; FCOMP5 reg_fpu,reg_fpu0
; FCOMP5 reg_fpu0,reg_fpu
; FXCH reg_fpu,reg_fpu0
; FXCH reg_fpu0,reg_fpu
; FXCH4 reg_fpu,reg_fpu0
; FXCH4 reg_fpu0,reg_fpu
; FXCH7 reg_fpu,reg_fpu0
; FXCH7 reg_fpu0,reg_fpu
; EOF
| endlessm/chromium-browser | third_party/nasm/test/fpu.asm | Assembly | bsd-3-clause | 3,254 |
;
; Copyright (C) 2019 Assured Information Security, Inc.
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in all
; copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
bits 64
default rel
section .text
global _read_es
_read_es:
xor rax, rax
mov ax, es
ret
global _write_es
_write_es:
xor rax, rax
mov es, di
ret
global _read_cs
_read_cs:
xor rax, rax
mov ax, cs
ret
global _write_cs
_write_cs:
; The added 0x48 is an undocumented issue with NASM. Basically, even though
; BITS 64 is used, and we are compiling for 64bit, NASM does not add the
; REX prefix to the retf instruction. As a result, we need to hand jam it
; in otherwise NASM will compile a 32bit instruction, and the data on the
; stack will be wrong
pop rax
push di
push rax
db 0x48
retf
global _read_ss
_read_ss:
xor rax, rax
mov ax, ss
ret
global _write_ss
_write_ss:
mov ss, di
ret
global _read_ds
_read_ds:
xor rax, rax
mov ax, ds
ret
global _write_ds
_write_ds:
mov ds, di
ret
global _read_fs
_read_fs:
xor rax, rax
mov ax, fs
ret
global _write_fs
_write_fs:
mov fs, di
ret
global _read_gs
_read_gs:
xor rax, rax
mov ax, gs
ret
global _write_gs
_write_gs:
mov gs, di
ret
global _read_ldtr
_read_ldtr:
xor rax, rax
sldt ax
ret
global _write_ldtr
_write_ldtr:
lldt di
ret
global _read_tr
_read_tr:
xor rax, rax
str ax
ret
global _write_tr
_write_tr:
ltr di
ret
| connojd/hypervisor | bfintrinsics/src/arch/x64/srs.asm | Assembly | mit | 2,490 |
;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.3.0 #8604 (Dec 30 2013) (Linux)
; This file was generated Fri Jul 17 14:56:21 2015
;--------------------------------------------------------
.module parameters
.optsdcc -mmcs51 --model-large
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _parameter_info
.globl _radio_get_transmit_power
.globl _radio_set_transmit_power
.globl _flash_write_scratch
.globl _flash_read_scratch
.globl _flash_erase_scratch
.globl _serial_device_valid_speed
.globl _strcmp
.globl _SDN
.globl _NSS1
.globl _IRQ
.globl _BUTTON_DOWN
.globl _BUTTON_UP
.globl _BUTTON_ENTER
.globl _LED_GREEN
.globl _LED_RED
.globl _SPI0EN
.globl _TXBMT0
.globl _NSS0MD0
.globl _NSS0MD1
.globl _RXOVRN0
.globl _MODF0
.globl _WCOL0
.globl _SPIF0
.globl _AD0CM0
.globl _AD0CM1
.globl _AD0CM2
.globl _AD0WINT
.globl _AD0BUSY
.globl _AD0INT
.globl _BURSTEN
.globl _AD0EN
.globl _CCF0
.globl _CCF1
.globl _CCF2
.globl _CCF3
.globl _CCF4
.globl _CCF5
.globl _CR
.globl _CF
.globl _P
.globl _F1
.globl _OV
.globl _RS0
.globl _RS1
.globl _F0
.globl _AC
.globl _CY
.globl _T2XCLK
.globl _T2RCLK
.globl _TR2
.globl _T2SPLIT
.globl _TF2CEN
.globl _TF2LEN
.globl _TF2L
.globl _TF2H
.globl _SI
.globl _ACK
.globl _ARBLOST
.globl _ACKRQ
.globl _STO
.globl _STA
.globl _TXMODE
.globl _MASTER
.globl _PX0
.globl _PT0
.globl _PX1
.globl _PT1
.globl _PS0
.globl _PT2
.globl _PSPI0
.globl _SPI1EN
.globl _TXBMT1
.globl _NSS1MD0
.globl _NSS1MD1
.globl _RXOVRN1
.globl _MODF1
.globl _WCOL1
.globl _SPIF1
.globl _EX0
.globl _ET0
.globl _EX1
.globl _ET1
.globl _ES0
.globl _ET2
.globl _ESPI0
.globl _EA
.globl _RI0
.globl _TI0
.globl _RB80
.globl _TB80
.globl _REN0
.globl _MCE0
.globl _S0MODE
.globl _CRC0VAL
.globl _CRC0INIT
.globl _CRC0SEL
.globl _IT0
.globl _IE0
.globl _IT1
.globl _IE1
.globl _TR0
.globl _TF0
.globl _TR1
.globl _TF1
.globl _PCA0CP4
.globl _PCA0CP0
.globl _PCA0
.globl _PCA0CP3
.globl _PCA0CP2
.globl _PCA0CP1
.globl _PCA0CP5
.globl _TMR2
.globl _TMR2RL
.globl _ADC0LT
.globl _ADC0GT
.globl _ADC0
.globl _TMR3
.globl _TMR3RL
.globl _TOFF
.globl _DP
.globl _VDM0CN
.globl _PCA0CPH4
.globl _PCA0CPL4
.globl _PCA0CPH0
.globl _PCA0CPL0
.globl _PCA0H
.globl _PCA0L
.globl _SPI0CN
.globl _EIP2
.globl _EIP1
.globl _SMB0ADM
.globl _SMB0ADR
.globl _P2MDIN
.globl _P1MDIN
.globl _P0MDIN
.globl _B
.globl _RSTSRC
.globl _PCA0CPH3
.globl _PCA0CPL3
.globl _PCA0CPH2
.globl _PCA0CPL2
.globl _PCA0CPH1
.globl _PCA0CPL1
.globl _ADC0CN
.globl _EIE2
.globl _EIE1
.globl _FLWR
.globl _IT01CF
.globl _XBR2
.globl _XBR1
.globl _XBR0
.globl _ACC
.globl _PCA0PWM
.globl _PCA0CPM4
.globl _PCA0CPM3
.globl _PCA0CPM2
.globl _PCA0CPM1
.globl _PCA0CPM0
.globl _PCA0MD
.globl _PCA0CN
.globl _P0MAT
.globl _P2SKIP
.globl _P1SKIP
.globl _P0SKIP
.globl _PCA0CPH5
.globl _PCA0CPL5
.globl _REF0CN
.globl _PSW
.globl _P1MAT
.globl _PCA0CPM5
.globl _TMR2H
.globl _TMR2L
.globl _TMR2RLH
.globl _TMR2RLL
.globl _REG0CN
.globl _TMR2CN
.globl _P0MASK
.globl _ADC0LTH
.globl _ADC0LTL
.globl _ADC0GTH
.globl _ADC0GTL
.globl _SMB0DAT
.globl _SMB0CF
.globl _SMB0CN
.globl _P1MASK
.globl _ADC0H
.globl _ADC0L
.globl _ADC0TK
.globl _ADC0CF
.globl _ADC0MX
.globl _ADC0PWR
.globl _ADC0AC
.globl _IREF0CN
.globl _IP
.globl _FLKEY
.globl _FLSCL
.globl _PMU0CF
.globl _OSCICL
.globl _OSCICN
.globl _OSCXCN
.globl _SPI1CN
.globl _ONESHOT
.globl _EMI0TC
.globl _RTC0KEY
.globl _RTC0DAT
.globl _RTC0ADR
.globl _EMI0CF
.globl _EMI0CN
.globl _CLKSEL
.globl _IE
.globl _SFRPAGE
.globl _P2DRV
.globl _P2MDOUT
.globl _P1DRV
.globl _P1MDOUT
.globl _P0DRV
.globl _P0MDOUT
.globl _SPI0DAT
.globl _SPI0CKR
.globl _SPI0CFG
.globl _P2
.globl _CPT0MX
.globl _CPT1MX
.globl _CPT0MD
.globl _CPT1MD
.globl _CPT0CN
.globl _CPT1CN
.globl _SBUF0
.globl _SCON0
.globl _CRC0CNT
.globl _DC0CN
.globl _CRC0AUTO
.globl _DC0CF
.globl _TMR3H
.globl _CRC0FLIP
.globl _TMR3L
.globl _CRC0IN
.globl _TMR3RLH
.globl _CRC0CN
.globl _TMR3RLL
.globl _CRC0DAT
.globl _TMR3CN
.globl _P1
.globl _PSCTL
.globl _CKCON
.globl _TH1
.globl _TH0
.globl _TL1
.globl _TL0
.globl _TMOD
.globl _TCON
.globl _PCON
.globl _TOFFH
.globl _SPI1DAT
.globl _TOFFL
.globl _SPI1CKR
.globl _SPI1CFG
.globl _DPH
.globl _DPL
.globl _SP
.globl _P0
.globl _parameter_values
.globl _constrain_PARM_3
.globl _constrain_PARM_2
.globl _param_set_PARM_2
.globl _param_set
.globl _param_get
.globl _param_load
.globl _param_save
.globl _param_default
.globl _param_id
.globl _param_name
.globl _constrain
;--------------------------------------------------------
; special function registers
;--------------------------------------------------------
.area RSEG (ABS,DATA)
.org 0x0000
_P0 = 0x0080
_SP = 0x0081
_DPL = 0x0082
_DPH = 0x0083
_SPI1CFG = 0x0084
_SPI1CKR = 0x0085
_TOFFL = 0x0085
_SPI1DAT = 0x0086
_TOFFH = 0x0086
_PCON = 0x0087
_TCON = 0x0088
_TMOD = 0x0089
_TL0 = 0x008a
_TL1 = 0x008b
_TH0 = 0x008c
_TH1 = 0x008d
_CKCON = 0x008e
_PSCTL = 0x008f
_P1 = 0x0090
_TMR3CN = 0x0091
_CRC0DAT = 0x0091
_TMR3RLL = 0x0092
_CRC0CN = 0x0092
_TMR3RLH = 0x0093
_CRC0IN = 0x0093
_TMR3L = 0x0094
_CRC0FLIP = 0x0095
_TMR3H = 0x0095
_DC0CF = 0x0096
_CRC0AUTO = 0x0096
_DC0CN = 0x0097
_CRC0CNT = 0x0097
_SCON0 = 0x0098
_SBUF0 = 0x0099
_CPT1CN = 0x009a
_CPT0CN = 0x009b
_CPT1MD = 0x009c
_CPT0MD = 0x009d
_CPT1MX = 0x009e
_CPT0MX = 0x009f
_P2 = 0x00a0
_SPI0CFG = 0x00a1
_SPI0CKR = 0x00a2
_SPI0DAT = 0x00a3
_P0MDOUT = 0x00a4
_P0DRV = 0x00a4
_P1MDOUT = 0x00a5
_P1DRV = 0x00a5
_P2MDOUT = 0x00a6
_P2DRV = 0x00a6
_SFRPAGE = 0x00a7
_IE = 0x00a8
_CLKSEL = 0x00a9
_EMI0CN = 0x00aa
_EMI0CF = 0x00ab
_RTC0ADR = 0x00ac
_RTC0DAT = 0x00ad
_RTC0KEY = 0x00ae
_EMI0TC = 0x00af
_ONESHOT = 0x00af
_SPI1CN = 0x00b0
_OSCXCN = 0x00b1
_OSCICN = 0x00b2
_OSCICL = 0x00b3
_PMU0CF = 0x00b5
_FLSCL = 0x00b6
_FLKEY = 0x00b7
_IP = 0x00b8
_IREF0CN = 0x00b9
_ADC0AC = 0x00ba
_ADC0PWR = 0x00ba
_ADC0MX = 0x00bb
_ADC0CF = 0x00bc
_ADC0TK = 0x00bd
_ADC0L = 0x00bd
_ADC0H = 0x00be
_P1MASK = 0x00bf
_SMB0CN = 0x00c0
_SMB0CF = 0x00c1
_SMB0DAT = 0x00c2
_ADC0GTL = 0x00c3
_ADC0GTH = 0x00c4
_ADC0LTL = 0x00c5
_ADC0LTH = 0x00c6
_P0MASK = 0x00c7
_TMR2CN = 0x00c8
_REG0CN = 0x00c9
_TMR2RLL = 0x00ca
_TMR2RLH = 0x00cb
_TMR2L = 0x00cc
_TMR2H = 0x00cd
_PCA0CPM5 = 0x00ce
_P1MAT = 0x00cf
_PSW = 0x00d0
_REF0CN = 0x00d1
_PCA0CPL5 = 0x00d2
_PCA0CPH5 = 0x00d3
_P0SKIP = 0x00d4
_P1SKIP = 0x00d5
_P2SKIP = 0x00d6
_P0MAT = 0x00d7
_PCA0CN = 0x00d8
_PCA0MD = 0x00d9
_PCA0CPM0 = 0x00da
_PCA0CPM1 = 0x00db
_PCA0CPM2 = 0x00dc
_PCA0CPM3 = 0x00dd
_PCA0CPM4 = 0x00de
_PCA0PWM = 0x00df
_ACC = 0x00e0
_XBR0 = 0x00e1
_XBR1 = 0x00e2
_XBR2 = 0x00e3
_IT01CF = 0x00e4
_FLWR = 0x00e5
_EIE1 = 0x00e6
_EIE2 = 0x00e7
_ADC0CN = 0x00e8
_PCA0CPL1 = 0x00e9
_PCA0CPH1 = 0x00ea
_PCA0CPL2 = 0x00eb
_PCA0CPH2 = 0x00ec
_PCA0CPL3 = 0x00ed
_PCA0CPH3 = 0x00ee
_RSTSRC = 0x00ef
_B = 0x00f0
_P0MDIN = 0x00f1
_P1MDIN = 0x00f2
_P2MDIN = 0x00f3
_SMB0ADR = 0x00f4
_SMB0ADM = 0x00f5
_EIP1 = 0x00f6
_EIP2 = 0x00f7
_SPI0CN = 0x00f8
_PCA0L = 0x00f9
_PCA0H = 0x00fa
_PCA0CPL0 = 0x00fb
_PCA0CPH0 = 0x00fc
_PCA0CPL4 = 0x00fd
_PCA0CPH4 = 0x00fe
_VDM0CN = 0x00ff
_DP = 0x8382
_TOFF = 0x8685
_TMR3RL = 0x9392
_TMR3 = 0x9594
_ADC0 = 0xbebd
_ADC0GT = 0xc4c3
_ADC0LT = 0xc6c5
_TMR2RL = 0xcbca
_TMR2 = 0xcdcc
_PCA0CP5 = 0xd3d2
_PCA0CP1 = 0xeae9
_PCA0CP2 = 0xeceb
_PCA0CP3 = 0xeeed
_PCA0 = 0xfaf9
_PCA0CP0 = 0xfcfb
_PCA0CP4 = 0xfefd
;--------------------------------------------------------
; special function bits
;--------------------------------------------------------
.area RSEG (ABS,DATA)
.org 0x0000
_TF1 = 0x008f
_TR1 = 0x008e
_TF0 = 0x008d
_TR0 = 0x008c
_IE1 = 0x008b
_IT1 = 0x008a
_IE0 = 0x0089
_IT0 = 0x0088
_CRC0SEL = 0x0096
_CRC0INIT = 0x0095
_CRC0VAL = 0x0094
_S0MODE = 0x009f
_MCE0 = 0x009d
_REN0 = 0x009c
_TB80 = 0x009b
_RB80 = 0x009a
_TI0 = 0x0099
_RI0 = 0x0098
_EA = 0x00af
_ESPI0 = 0x00ae
_ET2 = 0x00ad
_ES0 = 0x00ac
_ET1 = 0x00ab
_EX1 = 0x00aa
_ET0 = 0x00a9
_EX0 = 0x00a8
_SPIF1 = 0x00b7
_WCOL1 = 0x00b6
_MODF1 = 0x00b5
_RXOVRN1 = 0x00b4
_NSS1MD1 = 0x00b3
_NSS1MD0 = 0x00b2
_TXBMT1 = 0x00b1
_SPI1EN = 0x00b0
_PSPI0 = 0x00be
_PT2 = 0x00bd
_PS0 = 0x00bc
_PT1 = 0x00bb
_PX1 = 0x00ba
_PT0 = 0x00b9
_PX0 = 0x00b8
_MASTER = 0x00c7
_TXMODE = 0x00c6
_STA = 0x00c5
_STO = 0x00c4
_ACKRQ = 0x00c3
_ARBLOST = 0x00c2
_ACK = 0x00c1
_SI = 0x00c0
_TF2H = 0x00cf
_TF2L = 0x00ce
_TF2LEN = 0x00cd
_TF2CEN = 0x00cc
_T2SPLIT = 0x00cb
_TR2 = 0x00ca
_T2RCLK = 0x00c9
_T2XCLK = 0x00c8
_CY = 0x00d7
_AC = 0x00d6
_F0 = 0x00d5
_RS1 = 0x00d4
_RS0 = 0x00d3
_OV = 0x00d2
_F1 = 0x00d1
_P = 0x00d0
_CF = 0x00df
_CR = 0x00de
_CCF5 = 0x00dd
_CCF4 = 0x00dc
_CCF3 = 0x00db
_CCF2 = 0x00da
_CCF1 = 0x00d9
_CCF0 = 0x00d8
_AD0EN = 0x00ef
_BURSTEN = 0x00ee
_AD0INT = 0x00ed
_AD0BUSY = 0x00ec
_AD0WINT = 0x00eb
_AD0CM2 = 0x00ea
_AD0CM1 = 0x00e9
_AD0CM0 = 0x00e8
_SPIF0 = 0x00ff
_WCOL0 = 0x00fe
_MODF0 = 0x00fd
_RXOVRN0 = 0x00fc
_NSS0MD1 = 0x00fb
_NSS0MD0 = 0x00fa
_TXBMT0 = 0x00f9
_SPI0EN = 0x00f8
_LED_RED = 0x00a0
_LED_GREEN = 0x00a5
_BUTTON_ENTER = 0x0086
_BUTTON_UP = 0x0095
_BUTTON_DOWN = 0x0096
_IRQ = 0x0087
_NSS1 = 0x0094
_SDN = 0x00a6
;--------------------------------------------------------
; overlayable register banks
;--------------------------------------------------------
.area REG_BANK_0 (REL,OVR,DATA)
.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
.area DSEG (DATA)
_param_check_PARM_2:
.ds 4
;--------------------------------------------------------
; overlayable items in internal ram
;--------------------------------------------------------
.area OSEG (OVR,DATA)
.area OSEG (OVR,DATA)
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
.area ISEG (DATA)
;--------------------------------------------------------
; absolute internal ram data
;--------------------------------------------------------
.area IABS (ABS,DATA)
.area IABS (ABS,DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
.area BSEG (BIT)
_param_check_sloc0_1_0:
.ds 1
;--------------------------------------------------------
; paged external ram data
;--------------------------------------------------------
.area PSEG (PAG,XDATA)
_param_set_PARM_2:
.ds 4
_constrain_PARM_2:
.ds 4
_constrain_PARM_3:
.ds 4
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
.area XSEG (XDATA)
_parameter_values::
.ds 64
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area XABS (ABS,XDATA)
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
.area XISEG (XDATA)
.area HOME (CODE)
.area GSINIT0 (CODE)
.area GSINIT1 (CODE)
.area GSINIT2 (CODE)
.area GSINIT3 (CODE)
.area GSINIT4 (CODE)
.area GSINIT5 (CODE)
.area GSINIT (CODE)
.area GSFINAL (CODE)
.area CSEG (CODE)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME (CODE)
.area GSINIT (CODE)
.area GSFINAL (CODE)
.area GSINIT (CODE)
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME (CODE)
.area HOME (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CSEG (CODE)
;------------------------------------------------------------
;Allocation info for local variables in function 'param_check'
;------------------------------------------------------------
;val Allocated with name '_param_check_PARM_2'
;------------------------------------------------------------
; radio/parameters.c:84: param_check(__pdata enum ParamID id, __data uint32_t val)
; -----------------------------------------
; function param_check
; -----------------------------------------
_param_check:
ar7 = 0x07
ar6 = 0x06
ar5 = 0x05
ar4 = 0x04
ar3 = 0x03
ar2 = 0x02
ar1 = 0x01
ar0 = 0x00
mov r7,dpl
; radio/parameters.c:87: if (id >= PARAM_MAX)
cjne r7,#0x10,00147$
00147$:
; radio/parameters.c:88: return false;
jc 00102$
ret
00102$:
; radio/parameters.c:90: switch (id) {
mov a,r7
add a,#0xff - 0x0F
jnc 00149$
ljmp 00123$
00149$:
mov a,r7
add a,r7
add a,r7
mov dptr,#00150$
jmp @a+dptr
00150$:
ljmp 00103$
ljmp 00104$
ljmp 00105$
ljmp 00108$
ljmp 00109$
ljmp 00112$
ljmp 00116$
ljmp 00113$
ljmp 00122$
ljmp 00122$
ljmp 00122$
ljmp 00122$
ljmp 00122$
ljmp 00122$
ljmp 00122$
ljmp 00119$
; radio/parameters.c:91: case PARAM_FORMAT:
00103$:
; radio/parameters.c:92: return false;
clr c
; radio/parameters.c:94: case PARAM_SERIAL_SPEED:
ret
00104$:
; radio/parameters.c:95: return serial_device_valid_speed(val);
mov r7,_param_check_PARM_2
mov dpl,r7
lcall _serial_device_valid_speed
mov _param_check_sloc0_1_0,c
; radio/parameters.c:97: case PARAM_AIR_SPEED:
ret
00105$:
; radio/parameters.c:98: if (val > 256)
clr c
clr a
subb a,_param_check_PARM_2
mov a,#0x01
subb a,(_param_check_PARM_2 + 1)
clr a
subb a,(_param_check_PARM_2 + 2)
clr a
subb a,(_param_check_PARM_2 + 3)
jnc 00123$
; radio/parameters.c:99: return false;
clr c
; radio/parameters.c:102: case PARAM_NETID:
ret
00108$:
; radio/parameters.c:104: return true;
setb c
; radio/parameters.c:106: case PARAM_TXPOWER:
ret
00109$:
; radio/parameters.c:107: if (val > BOARD_MAXTXPOWER)
clr c
mov a,#0x14
subb a,_param_check_PARM_2
clr a
subb a,(_param_check_PARM_2 + 1)
clr a
subb a,(_param_check_PARM_2 + 2)
clr a
subb a,(_param_check_PARM_2 + 3)
jnc 00123$
; radio/parameters.c:108: return false;
clr c
; radio/parameters.c:111: case PARAM_ECC:
ret
00112$:
; radio/parameters.c:112: case PARAM_OPPRESEND:
00113$:
; radio/parameters.c:114: if (val > 1)
clr c
mov a,#0x01
subb a,_param_check_PARM_2
clr a
subb a,(_param_check_PARM_2 + 1)
clr a
subb a,(_param_check_PARM_2 + 2)
clr a
subb a,(_param_check_PARM_2 + 3)
jnc 00123$
; radio/parameters.c:115: return false;
clr c
; radio/parameters.c:118: case PARAM_MAVLINK:
ret
00116$:
; radio/parameters.c:119: if (val > 2)
clr c
mov a,#0x02
subb a,_param_check_PARM_2
clr a
subb a,(_param_check_PARM_2 + 1)
clr a
subb a,(_param_check_PARM_2 + 2)
clr a
subb a,(_param_check_PARM_2 + 3)
jnc 00123$
; radio/parameters.c:120: return false;
clr c
; radio/parameters.c:123: case PARAM_MAX_WINDOW:
ret
00119$:
; radio/parameters.c:127: if (val > 131)
clr c
mov a,#0x83
subb a,_param_check_PARM_2
clr a
subb a,(_param_check_PARM_2 + 1)
clr a
subb a,(_param_check_PARM_2 + 2)
clr a
subb a,(_param_check_PARM_2 + 3)
jnc 00123$
; radio/parameters.c:128: return false;
clr c
; radio/parameters.c:131: default:
ret
00122$:
; radio/parameters.c:134: }
00123$:
; radio/parameters.c:135: return true;
setb c
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'param_set'
;------------------------------------------------------------
;param Allocated to registers r7
;------------------------------------------------------------
; radio/parameters.c:139: param_set(__data enum ParamID param, __pdata param_t value)
; -----------------------------------------
; function param_set
; -----------------------------------------
_param_set:
mov r7,dpl
; radio/parameters.c:142: if (!param_check(param, value))
mov r0,#_param_set_PARM_2
movx a,@r0
mov _param_check_PARM_2,a
inc r0
movx a,@r0
mov (_param_check_PARM_2 + 1),a
inc r0
movx a,@r0
mov (_param_check_PARM_2 + 2),a
inc r0
movx a,@r0
mov (_param_check_PARM_2 + 3),a
mov dpl,r7
push ar7
lcall _param_check
pop ar7
; radio/parameters.c:143: return false;
jc 00102$
ret
00102$:
; radio/parameters.c:146: switch (param) {
cjne r7,#0x04,00150$
sjmp 00103$
00150$:
cjne r7,#0x06,00151$
ljmp 00108$
00151$:
cjne r7,#0x07,00152$
ljmp 00109$
00152$:
cjne r7,#0x0B,00153$
sjmp 00104$
00153$:
cjne r7,#0x0C,00154$
sjmp 00105$
00154$:
cjne r7,#0x0E,00155$
ljmp 00110$
00155$:
ljmp 00112$
; radio/parameters.c:147: case PARAM_TXPOWER:
00103$:
; radio/parameters.c:150: radio_set_transmit_power(value);
mov r0,#_param_set_PARM_2
movx a,@r0
mov dpl,a
push ar7
lcall _radio_set_transmit_power
; radio/parameters.c:151: value = radio_get_transmit_power();
lcall _radio_get_transmit_power
mov r6,dpl
pop ar7
mov r0,#_param_set_PARM_2
mov a,r6
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
; radio/parameters.c:152: break;
ljmp 00112$
; radio/parameters.c:154: case PARAM_DUTY_CYCLE:
00104$:
; radio/parameters.c:156: value = constrain(value, 0, 100);
mov r0,#_constrain_PARM_2
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
mov r0,#_constrain_PARM_3
mov a,#0x64
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
mov r0,#_param_set_PARM_2
movx a,@r0
mov dpl,a
inc r0
movx a,@r0
mov dph,a
inc r0
movx a,@r0
mov b,a
inc r0
movx a,@r0
push ar7
lcall _constrain
mov r3,dpl
mov r4,dph
mov r5,b
mov r6,a
pop ar7
mov r0,#_param_set_PARM_2
mov a,r3
movx @r0,a
inc r0
mov a,r4
movx @r0,a
inc r0
mov a,r5
movx @r0,a
inc r0
mov a,r6
movx @r0,a
; radio/parameters.c:157: duty_cycle = value;
mov r0,#_duty_cycle
mov a,r3
movx @r0,a
; radio/parameters.c:158: break;
ljmp 00112$
; radio/parameters.c:160: case PARAM_LBT_RSSI:
00105$:
; radio/parameters.c:162: if (value != 0) {
mov r0,#_param_set_PARM_2
movx a,@r0
mov b,a
inc r0
movx a,@r0
orl b,a
inc r0
movx a,@r0
orl b,a
inc r0
movx a,@r0
orl a,b
jz 00107$
; radio/parameters.c:163: value = constrain(value, 25, 220);
mov r0,#_constrain_PARM_2
mov a,#0x19
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
mov r0,#_constrain_PARM_3
mov a,#0xDC
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
mov r0,#_param_set_PARM_2
movx a,@r0
mov dpl,a
inc r0
movx a,@r0
mov dph,a
inc r0
movx a,@r0
mov b,a
inc r0
movx a,@r0
push ar7
lcall _constrain
mov r3,dpl
mov r4,dph
mov r5,b
mov r6,a
pop ar7
mov r0,#_param_set_PARM_2
mov a,r3
movx @r0,a
inc r0
mov a,r4
movx @r0,a
inc r0
mov a,r5
movx @r0,a
inc r0
mov a,r6
movx @r0,a
00107$:
; radio/parameters.c:165: lbt_rssi = value;
mov r0,#_param_set_PARM_2
mov r1,#_lbt_rssi
movx a,@r0
movx @r1,a
; radio/parameters.c:166: break;
; radio/parameters.c:168: case PARAM_MAVLINK:
sjmp 00112$
00108$:
; radio/parameters.c:169: feature_mavlink_framing = (uint8_t) value;
mov r0,#_param_set_PARM_2
movx a,@r0
mov r6,a
mov dptr,#_feature_mavlink_framing
movx @dptr,a
; radio/parameters.c:170: value = feature_mavlink_framing;
mov r0,#_param_set_PARM_2
mov a,r6
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
; radio/parameters.c:171: break;
; radio/parameters.c:173: case PARAM_OPPRESEND:
sjmp 00112$
00109$:
; radio/parameters.c:174: feature_opportunistic_resend = value?true:false;
mov r0,#_param_set_PARM_2
movx a,@r0
mov b,a
inc r0
movx a,@r0
orl b,a
inc r0
movx a,@r0
orl b,a
inc r0
movx a,@r0
orl a,b
add a,#0xff
; radio/parameters.c:175: value = feature_opportunistic_resend?1:0;
mov _feature_opportunistic_resend,c
jnc 00115$
mov r6,#0x01
sjmp 00116$
00115$:
mov r6,#0x00
00116$:
mov r0,#_param_set_PARM_2
mov a,r6
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
; radio/parameters.c:176: break;
; radio/parameters.c:178: case PARAM_RTSCTS:
sjmp 00112$
00110$:
; radio/parameters.c:179: feature_rtscts = value?true:false;
mov r0,#_param_set_PARM_2
movx a,@r0
mov b,a
inc r0
movx a,@r0
orl b,a
inc r0
movx a,@r0
orl b,a
inc r0
movx a,@r0
orl a,b
add a,#0xff
; radio/parameters.c:180: value = feature_rtscts?1:0;
mov _feature_rtscts,c
jnc 00117$
mov r6,#0x01
sjmp 00118$
00117$:
mov r6,#0x00
00118$:
mov r0,#_param_set_PARM_2
mov a,r6
movx @r0,a
inc r0
clr a
movx @r0,a
inc r0
movx @r0,a
inc r0
movx @r0,a
; radio/parameters.c:185: }
00112$:
; radio/parameters.c:187: parameter_values[param].val = value;
mov a,r7
mov b,#0x04
mul ab
add a,#_parameter_values
mov dpl,a
mov a,#(_parameter_values >> 8)
addc a,b
mov dph,a
mov r0,#_param_set_PARM_2
movx a,@r0
movx @dptr,a
inc r0
movx a,@r0
inc dptr
movx @dptr,a
inc r0
movx a,@r0
inc dptr
movx @dptr,a
inc r0
movx a,@r0
inc dptr
movx @dptr,a
; radio/parameters.c:189: return true;
setb c
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'param_get'
;------------------------------------------------------------
;param Allocated to registers r7
;------------------------------------------------------------
; radio/parameters.c:193: param_get(__data enum ParamID param)
; -----------------------------------------
; function param_get
; -----------------------------------------
_param_get:
mov r7,dpl
; radio/parameters.c:195: if (param >= PARAM_MAX)
cjne r7,#0x10,00108$
00108$:
jc 00102$
; radio/parameters.c:196: return 0;
mov dptr,#(0x00&0x00ff)
clr a
mov b,a
ret
00102$:
; radio/parameters.c:197: return parameter_values[param].val;
mov a,r7
mov b,#0x04
mul ab
add a,#_parameter_values
mov dpl,a
mov a,#(_parameter_values >> 8)
addc a,b
mov dph,a
movx a,@dptr
mov r4,a
inc dptr
movx a,@dptr
mov r5,a
inc dptr
movx a,@dptr
mov r6,a
inc dptr
movx a,@dptr
mov dpl,r4
mov dph,r5
mov b,r6
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'param_load'
;------------------------------------------------------------
; radio/parameters.c:201: param_load(void)
; -----------------------------------------
; function param_load
; -----------------------------------------
_param_load:
setb c
jbc ea,00155$
clr c
00155$:
push psw
; radio/parameters.c:209: for (i = 0; i < sizeof(parameter_values); i++) {
mov r7,#0x00
00113$:
; radio/parameters.c:210: parameter_values[i].val = parameter_info[i].default_value;
mov a,r7
mov b,#0x04
mul ab
add a,#_parameter_values
mov r5,a
mov a,#(_parameter_values >> 8)
addc a,b
mov r6,a
mov a,r7
mov b,#0x07
mul ab
add a,#_parameter_info
mov r3,a
mov a,#(_parameter_info >> 8)
addc a,b
mov r4,a
mov dpl,r3
mov dph,r4
inc dptr
inc dptr
inc dptr
clr a
movc a,@a+dptr
mov r1,a
inc dptr
clr a
movc a,@a+dptr
mov r2,a
inc dptr
clr a
movc a,@a+dptr
mov r3,a
inc dptr
clr a
movc a,@a+dptr
mov r4,a
mov dpl,r5
mov dph,r6
mov a,r1
movx @dptr,a
mov a,r2
inc dptr
movx @dptr,a
mov a,r3
inc dptr
movx @dptr,a
mov a,r4
inc dptr
movx @dptr,a
; radio/parameters.c:209: for (i = 0; i < sizeof(parameter_values); i++) {
inc r7
cjne r7,#0x40,00156$
00156$:
jc 00113$
; radio/parameters.c:214: sum = 0;
mov r7,#0x00
; radio/parameters.c:215: count = flash_read_scratch(0);
mov dptr,#0x0000
push ar7
lcall _flash_read_scratch
mov r6,dpl
pop ar7
; radio/parameters.c:216: if (count > sizeof(parameter_values) ||
mov a,r6
add a,#0xff - 0x40
jc 00102$
; radio/parameters.c:217: count < 12*sizeof(param_t)) {
cjne r6,#0x30,00159$
00159$:
jnc 00126$
00102$:
; radio/parameters.c:218: return false;
clr c
ljmp 00120$
; radio/parameters.c:222: for (i = 0; i < count; i ++) {
00126$:
mov r5,#0x00
00116$:
clr c
mov a,r5
subb a,r6
jnc 00105$
; radio/parameters.c:223: d = flash_read_scratch(i+1);
mov ar3,r5
mov r4,#0x00
inc r3
cjne r3,#0x00,00162$
inc r4
00162$:
mov dpl,r3
mov dph,r4
push ar7
push ar6
push ar5
lcall _flash_read_scratch
mov r4,dpl
pop ar5
pop ar6
pop ar7
; radio/parameters.c:224: parameter_values[0].bytes[i] = d;
mov a,r5
add a,#_parameter_values
mov dpl,a
clr a
addc a,#(_parameter_values >> 8)
mov dph,a
mov a,r4
movx @dptr,a
; radio/parameters.c:225: sum ^= d;
mov a,r4
xrl ar7,a
; radio/parameters.c:222: for (i = 0; i < count; i ++) {
inc r5
sjmp 00116$
00105$:
; radio/parameters.c:229: d = flash_read_scratch(i+1);
mov r6,#0x00
inc r5
cjne r5,#0x00,00163$
inc r6
00163$:
mov dpl,r5
mov dph,r6
push ar7
lcall _flash_read_scratch
mov r4,dpl
pop ar7
; radio/parameters.c:230: if (sum != d)
mov a,r7
cjne a,ar4,00164$
sjmp 00107$
00164$:
; radio/parameters.c:231: return false;
clr c
ljmp 00120$
00107$:
; radio/parameters.c:234: if (param_get(PARAM_FORMAT) != PARAM_FORMAT_CURRENT) {
mov dpl,#0x00
lcall _param_get
mov r4,dpl
mov r5,dph
mov r6,b
mov r7,a
cjne r4,#0x19,00165$
cjne r5,#0x00,00165$
cjne r6,#0x00,00165$
cjne r7,#0x00,00165$
sjmp 00130$
00165$:
; radio/parameters.c:236: return false;
clr c
; radio/parameters.c:239: for (i = 0; i < sizeof(parameter_values); i++) {
sjmp 00120$
00130$:
mov r7,#0x00
00118$:
; radio/parameters.c:240: if (!param_check(i, parameter_values[i].val)) {
mov a,r7
mov b,#0x04
mul ab
add a,#_parameter_values
mov r5,a
mov a,#(_parameter_values >> 8)
addc a,b
mov r6,a
mov dpl,r5
mov dph,r6
movx a,@dptr
mov _param_check_PARM_2,a
inc dptr
movx a,@dptr
mov (_param_check_PARM_2 + 1),a
inc dptr
movx a,@dptr
mov (_param_check_PARM_2 + 2),a
inc dptr
movx a,@dptr
mov (_param_check_PARM_2 + 3),a
mov dpl,r7
push ar7
push ar6
push ar5
lcall _param_check
pop ar5
pop ar6
pop ar7
jc 00119$
; radio/parameters.c:241: parameter_values[i].val = parameter_info[i].default_value;
mov a,r7
mov b,#0x07
mul ab
add a,#_parameter_info
mov r3,a
mov a,#(_parameter_info >> 8)
addc a,b
mov r4,a
mov dpl,r3
mov dph,r4
inc dptr
inc dptr
inc dptr
clr a
movc a,@a+dptr
mov r1,a
inc dptr
clr a
movc a,@a+dptr
mov r2,a
inc dptr
clr a
movc a,@a+dptr
mov r3,a
inc dptr
clr a
movc a,@a+dptr
mov r4,a
mov dpl,r5
mov dph,r6
mov a,r1
movx @dptr,a
mov a,r2
inc dptr
movx @dptr,a
mov a,r3
inc dptr
movx @dptr,a
mov a,r4
inc dptr
movx @dptr,a
00119$:
; radio/parameters.c:239: for (i = 0; i < sizeof(parameter_values); i++) {
inc r7
cjne r7,#0x40,00167$
00167$:
jc 00118$
; radio/parameters.c:245: return true;
setb c
00120$:
rlc a
pop psw
mov ea,c
rrc a
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'param_save'
;------------------------------------------------------------
;d Allocated to registers r5
;i Allocated to registers r6
;sum Allocated to registers r7
;------------------------------------------------------------
; radio/parameters.c:249: param_save(void)
; -----------------------------------------
; function param_save
; -----------------------------------------
_param_save:
; radio/parameters.c:256: parameter_values[PARAM_FORMAT].val = PARAM_FORMAT_CURRENT;
mov dptr,#_parameter_values
mov a,#0x19
movx @dptr,a
clr a
inc dptr
movx @dptr,a
clr a
inc dptr
movx @dptr,a
clr a
inc dptr
movx @dptr,a
; radio/parameters.c:259: flash_erase_scratch();
lcall _flash_erase_scratch
; radio/parameters.c:262: sum = 0;
mov r7,#0x00
; radio/parameters.c:263: flash_write_scratch(0, sizeof(parameter_values));
mov r0,#_flash_write_scratch_PARM_2
mov a,#0x40
movx @r0,a
mov dptr,#0x0000
push ar7
lcall _flash_write_scratch
pop ar7
; radio/parameters.c:266: for (i = 0; i < sizeof(parameter_values); i++) {
mov r6,#0x00
00102$:
; radio/parameters.c:267: d = parameter_values[0].bytes[i]; // byte we are going to write
mov a,r6
add a,#_parameter_values
mov dpl,a
clr a
addc a,#(_parameter_values >> 8)
mov dph,a
movx a,@dptr
; radio/parameters.c:268: sum ^= d;
mov r5,a
xrl ar7,a
; radio/parameters.c:269: flash_write_scratch(i+1, d);
mov ar3,r6
mov r4,#0x00
inc r3
cjne r3,#0x00,00113$
inc r4
00113$:
mov r0,#_flash_write_scratch_PARM_2
mov a,r5
movx @r0,a
mov dpl,r3
mov dph,r4
push ar7
push ar6
lcall _flash_write_scratch
pop ar6
pop ar7
; radio/parameters.c:266: for (i = 0; i < sizeof(parameter_values); i++) {
inc r6
cjne r6,#0x40,00114$
00114$:
jc 00102$
; radio/parameters.c:273: flash_write_scratch(i+1, sum);
mov r5,#0x00
inc r6
cjne r6,#0x00,00116$
inc r5
00116$:
mov r0,#_flash_write_scratch_PARM_2
mov a,r7
movx @r0,a
mov dpl,r6
mov dph,r5
ljmp _flash_write_scratch
;------------------------------------------------------------
;Allocation info for local variables in function 'param_default'
;------------------------------------------------------------
; radio/parameters.c:277: param_default(void)
; -----------------------------------------
; function param_default
; -----------------------------------------
_param_default:
; radio/parameters.c:282: for (i = 0; i < PARAM_MAX; i++) {
mov r7,#0x00
00102$:
; radio/parameters.c:283: parameter_values[i].val = parameter_info[i].default_value;
mov a,r7
mov b,#0x04
mul ab
add a,#_parameter_values
mov r5,a
mov a,#(_parameter_values >> 8)
addc a,b
mov r6,a
mov a,r7
mov b,#0x07
mul ab
add a,#_parameter_info
mov r3,a
mov a,#(_parameter_info >> 8)
addc a,b
mov r4,a
mov dpl,r3
mov dph,r4
inc dptr
inc dptr
inc dptr
clr a
movc a,@a+dptr
mov r1,a
inc dptr
clr a
movc a,@a+dptr
mov r2,a
inc dptr
clr a
movc a,@a+dptr
mov r3,a
inc dptr
clr a
movc a,@a+dptr
mov r4,a
mov dpl,r5
mov dph,r6
mov a,r1
movx @dptr,a
mov a,r2
inc dptr
movx @dptr,a
mov a,r3
inc dptr
movx @dptr,a
mov a,r4
inc dptr
movx @dptr,a
; radio/parameters.c:282: for (i = 0; i < PARAM_MAX; i++) {
inc r7
cjne r7,#0x10,00110$
00110$:
jc 00102$
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'param_id'
;------------------------------------------------------------
; radio/parameters.c:288: param_id(__data char * __pdata name)
; -----------------------------------------
; function param_id
; -----------------------------------------
_param_id:
mov r7,dpl
; radio/parameters.c:292: for (i = 0; i < PARAM_MAX; i++) {
mov r6,#0x00
00104$:
; radio/parameters.c:293: if (!strcmp(name, parameter_info[i].name))
mov ar3,r7
mov r4,#0x00
mov r5,#0x40
mov a,r6
mov b,#0x07
mul ab
add a,#_parameter_info
mov dpl,a
mov a,#(_parameter_info >> 8)
addc a,b
mov dph,a
clr a
movc a,@a+dptr
mov r0,a
inc dptr
clr a
movc a,@a+dptr
mov r1,a
inc dptr
clr a
movc a,@a+dptr
mov r2,a
mov dptr,#_strcmp_PARM_2
mov a,r0
movx @dptr,a
mov a,r1
inc dptr
movx @dptr,a
mov a,r2
inc dptr
movx @dptr,a
mov dpl,r3
mov dph,r4
mov b,r5
push ar7
push ar6
lcall _strcmp
mov a,dpl
mov b,dph
pop ar6
pop ar7
orl a,b
jz 00103$
; radio/parameters.c:292: for (i = 0; i < PARAM_MAX; i++) {
inc r6
cjne r6,#0x10,00116$
00116$:
jc 00104$
00103$:
; radio/parameters.c:296: return i;
mov dpl,r6
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'param_name'
;------------------------------------------------------------
;param Allocated to registers r7
;------------------------------------------------------------
; radio/parameters.c:300: param_name(__data enum ParamID param)
; -----------------------------------------
; function param_name
; -----------------------------------------
_param_name:
mov r7,dpl
; radio/parameters.c:302: if (param < PARAM_MAX) {
cjne r7,#0x10,00108$
00108$:
jnc 00102$
; radio/parameters.c:303: return parameter_info[param].name;
mov a,r7
mov b,#0x07
mul ab
add a,#_parameter_info
mov dpl,a
mov a,#(_parameter_info >> 8)
addc a,b
mov dph,a
clr a
movc a,@a+dptr
mov r5,a
inc dptr
clr a
movc a,@a+dptr
mov r6,a
inc dptr
clr a
movc a,@a+dptr
mov r7,a
mov dpl,r5
mov dph,r6
mov b,r7
ret
00102$:
; radio/parameters.c:305: return 0;
mov dptr,#0x0000
mov b,#0x00
ret
;------------------------------------------------------------
;Allocation info for local variables in function 'constrain'
;------------------------------------------------------------
; radio/parameters.c:309: uint32_t constrain(__pdata uint32_t v, __pdata uint32_t min, __pdata uint32_t max)
; -----------------------------------------
; function constrain
; -----------------------------------------
_constrain:
mov r4,dpl
mov r5,dph
mov r6,b
mov r7,a
; radio/parameters.c:311: if (v < min) v = min;
mov r0,#_constrain_PARM_2
clr c
movx a,@r0
mov b,a
mov a,r4
subb a,b
inc r0
movx a,@r0
mov b,a
mov a,r5
subb a,b
inc r0
movx a,@r0
mov b,a
mov a,r6
subb a,b
inc r0
movx a,@r0
mov b,a
mov a,r7
subb a,b
jnc 00102$
mov r0,#_constrain_PARM_2
movx a,@r0
mov r4,a
inc r0
movx a,@r0
mov r5,a
inc r0
movx a,@r0
mov r6,a
inc r0
movx a,@r0
mov r7,a
00102$:
; radio/parameters.c:312: if (v > max) v = max;
mov r0,#_constrain_PARM_3
clr c
movx a,@r0
subb a,r4
inc r0
movx a,@r0
subb a,r5
inc r0
movx a,@r0
subb a,r6
inc r0
movx a,@r0
subb a,r7
jnc 00104$
mov r0,#_constrain_PARM_3
movx a,@r0
mov r4,a
inc r0
movx a,@r0
mov r5,a
inc r0
movx a,@r0
mov r6,a
inc r0
movx a,@r0
mov r7,a
00104$:
; radio/parameters.c:313: return v;
mov dpl,r4
mov dph,r5
mov b,r6
mov a,r7
ret
.area CSEG (CODE)
.area CONST (CODE)
_parameter_info:
.byte _str_0,(_str_0 >> 8),#0x80
.byte #0x19,#0x00,#0x00,#0x00 ; 25
.byte _str_1,(_str_1 >> 8),#0x80
.byte #0x39,#0x00,#0x00,#0x00 ; 57
.byte _str_2,(_str_2 >> 8),#0x80
.byte #0x40,#0x00,#0x00,#0x00 ; 64
.byte _str_3,(_str_3 >> 8),#0x80
.byte #0x19,#0x00,#0x00,#0x00 ; 25
.byte _str_4,(_str_4 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_5,(_str_5 >> 8),#0x80
.byte #0x01,#0x00,#0x00,#0x00 ; 1
.byte _str_6,(_str_6 >> 8),#0x80
.byte #0x01,#0x00,#0x00,#0x00 ; 1
.byte _str_7,(_str_7 >> 8),#0x80
.byte #0x01,#0x00,#0x00,#0x00 ; 1
.byte _str_8,(_str_8 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_9,(_str_9 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_10,(_str_10 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_11,(_str_11 >> 8),#0x80
.byte #0x64,#0x00,#0x00,#0x00 ; 100
.byte _str_12,(_str_12 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_13,(_str_13 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_14,(_str_14 >> 8),#0x80
.byte #0x00,#0x00,#0x00,#0x00 ; 0
.byte _str_15,(_str_15 >> 8),#0x80
.byte #0x83,#0x00,#0x00,#0x00 ; 131
_str_0:
.ascii "FORMAT"
.db 0x00
_str_1:
.ascii "SERIAL_SPEED"
.db 0x00
_str_2:
.ascii "AIR_SPEED"
.db 0x00
_str_3:
.ascii "NETID"
.db 0x00
_str_4:
.ascii "TXPOWER"
.db 0x00
_str_5:
.ascii "ECC"
.db 0x00
_str_6:
.ascii "MAVLINK"
.db 0x00
_str_7:
.ascii "OPPRESEND"
.db 0x00
_str_8:
.ascii "MIN_FREQ"
.db 0x00
_str_9:
.ascii "MAX_FREQ"
.db 0x00
_str_10:
.ascii "NUM_CHANNELS"
.db 0x00
_str_11:
.ascii "DUTY_CYCLE"
.db 0x00
_str_12:
.ascii "LBT_RSSI"
.db 0x00
_str_13:
.ascii "MANCHESTER"
.db 0x00
_str_14:
.ascii "RTSCTS"
.db 0x00
_str_15:
.ascii "MAX_WINDOW"
.db 0x00
.area XINIT (CODE)
.area CABS (ABS,CODE)
| YifanJiangPolyU/SiK-master-Yifan-TDMA | Firmware-bk/obj/rf50/radio~rf50/parameters.asm | Assembly | bsd-2-clause | 35,494 |
diff16 'tp-popup.asm',0,$
;POP_WIDTH = (popup_text.max_title+popup_text.max_accel+6)*6
POP_IHEIGHT = 16
POP_SHEIGHT = 2
;POP_HEIGHT = popup_text.cnt_item*POP_IHEIGHT+popup_text.cnt_sep*4+4
popup_thread_start:
mov [popup_active],1
mov [pi_cur],0
mov ebp,[esp]
mcall 14
movzx ebx,ax
shr eax,16
movzx ecx,[ebp+POPUP.x]
add cx,[ebp+POPUP.width]
cmp ecx,eax
jle @f
mov cx,[ebp+POPUP.width]
sub [ebp+POPUP.x],cx
@@: movzx ecx,[ebp+POPUP.y]
add cx,[ebp+POPUP.height]
cmp ecx,ebx
jle @f
mov cx,[ebp+POPUP.height]
sub [ebp+POPUP.y],cx
@@: mcall 40,01100111b ; ipc mouse button key redraw
cmp [mi_cur],0
jl .2
sub esp,32-16
push 0 0 8 0
mcall 60,1,esp,32
.2: call draw_popup_wnd
still_popup:
cmp [main_closed],1
je close_popup
mcall 10
cmp eax,1
je popup_thread_start.2
cmp eax,2
je key_popup
cmp eax,3
je button_popup
cmp eax,6
je mouse_popup
cmp eax,7
jne still_popup
mov ebp,[POPUP_STACK]
mov dword[POPUP_STACK-32+4],8
movzx ebx,[ebp+POPUP.x]
movzx ecx,[ebp+POPUP.y]
movzx edx,[ebp+POPUP.width]
movzx esi,[ebp+POPUP.height]
mcall 67
jmp still_popup
mouse_popup:
mov ecx,mst2
call get_mouse_event
cmp al,MEV_LDOWN
je check_popup_click
cmp al,MEV_MOVE
je check_popup_move
mcall 9,p_info2,-1
cmp ax,[p_info2.window_stack_position]
jne close_popup
jmp still_popup
check_popup_click:
mov eax,[pi_cur]
or al,al
js close_popup
jz still_popup
mov ebx,[ebp+POPUP.actions]
mov [just_from_popup],1
call dword[ebx+eax*4-4]
inc [just_from_popup]
jmp close_popup
check_popup_move:
mov eax,[pi_cur]
call get_active_popup_item
cmp eax,[pi_cur]
je still_popup
call draw_popup_wnd
jmp still_popup
key_popup:
mcall ;2
cmp ah,27
jne still_popup
button_popup:
mcall 17
close_popup:
mcall 18,3,[p_info.PID]
mov [popup_active],0
mov [mi_cur],0
mcall -1
func draw_popup_wnd
mcall 12,1
mov ebx,dword[ebp+POPUP.x-2]
mov bx,[ebp+POPUP.width]
mov ecx,dword[ebp+POPUP.y-2]
mov cx,[ebp+POPUP.height]
mcall 0,,,0x01000000,0x01000000
movzx ebx,bx
movzx ecx,cx
pushd 0 0 ebx ecx
call draw_3d_panel
mov [pi_sel],0
mov eax,4
mpack ebx,3*6,3
mov ecx,[sc.work_text]
mov edx,[ebp+POPUP.data]
@@: inc [pi_sel]
inc edx
movzx esi,byte[edx-1]
cmp byte[edx],'-'
jne .lp1
pushad
mov ecx,ebx
shl ecx,16
mov cx,bx
movzx ebx,[ebp+POPUP.width]
add ebx,0x00010000-1
add ecx,0x00010001
mcall 38,,,[cl_3d_inset]
add ecx,0x00010001
mcall ,,,[cl_3d_outset]
popad
add ebx,4
jmp .lp2
.lp1: mov edi,[pi_sel]
cmp edi,[pi_cur]
jne .lp3
test byte[ebp+edi-1],0x01
jz .lp3
pushad
movzx ecx,bx
shl ecx,16
mov cl,POP_IHEIGHT-1
movzx ebx,[ebp+POPUP.width]
add ebx,0x00010000-1
mcall 13,,,[cl_3d_pushed]
rol ecx,16
mov ax,cx
rol ecx,16
mov cx,ax
mcall 38,,,[cl_3d_inset]
add ecx,(POP_IHEIGHT-1)*65536+POP_IHEIGHT-1
mcall ,,,[cl_3d_outset]
popad
.lp3: add ebx,(POP_IHEIGHT-7)/2
pushad
test byte[ebp+edi-1],0x02
jz .lp8
movzx ecx,bx
shr ebx,16
add ebx,-11
add ecx,2
mov edx,[sc.work_text]
call draw_check
.lp8: popad
mov ecx,[sc.work_text]
test byte[ebp+edi-1],0x01
jnz .lp5
add ebx,0x00010001
mov ecx,[cl_3d_outset]
mcall
sub ebx,0x00010001
mov ecx,[cl_3d_inset]
.lp5: mcall
push ebx
add edx,esi
inc edx
movzx esi,byte[edx-1]
add ebx,[ebp+POPUP.acc_ofs]
cmp edi,[pi_cur]
je .lp4
mov ecx,[cl_3d_inset]
.lp4: test byte[ebp+edi-1],0x01
jnz .lp6
add ebx,0x00010001
mov ecx,[cl_3d_outset]
mcall
sub ebx,0x00010001
mov ecx,[cl_3d_inset]
.lp6: mcall
pop ebx
add ebx,POP_IHEIGHT-(POP_IHEIGHT-7)/2
.lp2: add edx,esi
cmp byte[edx],0
jne @b
.exit:
mcall 12,2
ret
endf
func setup_main_menu_popup
mov ebx,[p_info.box.left]
add ebx,[p_info.client_box.left]
@@: dec ecx
jz @f
add edx,8+1
movzx esi,byte[edx-1]
add edx,esi
jmp @b
@@: movzx ecx,word[edx+2]
add ebx,ecx
mov [eax+POPUP.x],bx
mov ebx,[p_info.box.top]
add ebx,[p_info.client_box.top]
add ebx,ATOPH-1
mov [eax+POPUP.y],bx
mov [POPUP_STACK],eax
ret
endf
onshow:
.file:
or byte[mm.File+3],0x01
cmp [f_info.length],0
jne @f
and byte[mm.File+3],0xFE
@@: ret
.edit:
or byte[mm.Edit+2],0x01
call check_clipboard_for_popup
cmp [popup_valid_text],0
jne @f
and byte[mm.Edit+2],0xFE
@@: or dword[mm.Edit+0],0x01000101
cmp [sel.selected],0
jne @f
and dword[mm.Edit+0],0xFEFFFEFE
@@: ret
.search:
mov byte[mm.Search+0],0
ret
.run:
ret
.recode:
ret
.options:
;mov word[mm.Options+0],0
mov byte[mm.Options+5],0
or byte[mm.Options+2],0x02
test [secure_sel],1
jnz @f
and byte[mm.Options+2],0xFD
@@: or byte[mm.Options+3],0x02
test [auto_braces],1
jnz @f
and byte[mm.Options+3],0xFD
@@: or byte[mm.Options+4],0x02
test [auto_indent],1
jnz @f
and byte[mm.Options+4],0xFD
@@: or byte[mm.Options+6],0x02
test [optim_save],1
jnz @f
and byte[mm.Options+6],0xFD
@@: or byte[mm.Options+8],0x02
test [line_nums],1
jnz @f
and byte[mm.Options+8],0xFD
@@: ret
pi_sel dd ?
pi_cur dd ?
p_pos dd ?
popup_active db 0
| devlato/kolibrios-llvm | programs/develop/tinypad/trunk/tp-popup.asm | Assembly | mit | 5,002 |
;Testname=unoptimized; Arguments=-O0 -fbin -oa32offs.bin; Files=a32offs.bin stdout stderr
;Testname=optimized; Arguments=-Ox -fbin -oa32offs.bin; Files=a32offs.bin stdout stderr
bits 16
foo: a32 loop foo
bar: loop bar, ecx
bits 32
baz: a16 loop baz
qux: loop qux, cx
| endlessm/chromium-browser | third_party/nasm/test/a32offs.asm | Assembly | bsd-3-clause | 273 |
;================================================================================
; Dialog Pointer Override
;--------------------------------------------------------------------------------
EndingSequenceTableOverride:
PHY
PHX
TYX
LDA.l EndingSequenceText, X
PLX
STA $1008, X
PLY
RTL
;--------------------------------------------------------------------------------
EndingSequenceTableLookupOverride:
PHY
PHX
TYX
LDA.l EndingSequenceText, X : AND #$00FF
PLX
PLY
RTL
;--------------------------------------------------------------------------------
| mmxbass/z3randomizer | endingsequence.asm | Assembly | mit | 561 |
.nds
.relativeinclude on
.erroronwarning on
; The water splashing particles at the bottom of the waterwheel room in the Tower of Death have a bug in vanilla where they don't check if another particle entity is null or not.
; This bug causes the game to crash if all particle type entity slots (81-EF) are used up.
@Overlay119Start equ 0x02308EC0
@FreeSpace equ @Overlay119Start + 0x4AC
.open "ftc/overlay9_86", 022E8820h
.org 0x022EAE08
b @CheckWaterParticleIsNull
.close
.open "ftc/overlay9_119", @Overlay119Start
.org @FreeSpace
@CheckWaterParticleIsNull:
; If the particle is null, skip the code that uses it.
cmp r4, 0h
beq 0x022EAE40
; Otherwise continue with the normal code.
add r3, r4, 30h ; Replace the line we overwrote to jump here
b 0x022EAE0C
.close
| LagoLunatic/DSVEdit | asm/por_fix_waterwheel_particle_crash.asm | Assembly | mit | 789 |
[bits 16]
extractps eax, xmm1, 5 ; out: 66 0f 3a 17 c8 05
vextractps eax, xmm1, 5 ; out: c4 e3 79 17 c8 05
pextrb eax, xmm1, 5 ; out: 66 0f 3a 14 c8 05
vpextrb eax, xmm1, 5 ; out: c4 e3 79 14 c8 05
pextrw eax, xmm1, 5 ; out: 66 0f c5 c1 05
vpextrw eax, xmm1, 5 ; out: c5 f9 c5 c1 05
pextrd eax, xmm1, 5 ; out: 66 0f 3a 16 c8 05
vpextrd eax, xmm1, 5 ; out: c4 e3 79 16 c8 05
vpinsrd xmm1, xmm2, eax, 5 ; out: c4 e3 69 22 c8 05
| 13xforever/x86-assembly-textmate-bundle | Tests/yasm-regression/avx16.asm | Assembly | mit | 434 |
; Copyright 2005-2008 Intel Corporation. All Rights Reserved.
;
; This file is part of Threading Building Blocks.
;
; Threading Building Blocks is free software; you can redistribute it
; and/or modify it under the terms of the GNU General Public License
; version 2 as published by the Free Software Foundation.
;
; Threading Building Blocks is distributed in the hope that it will be
; useful, but WITHOUT ANY WARRANTY; without even the implied warranty
; of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with Threading Building Blocks; if not, write to the Free Software
; Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
;
; As a special exception, you may use this file as part of a free software
; library without restriction. Specifically, if other files instantiate
; templates or use macros or inline functions from this file, or you compile
; this file and link it with other files to produce an executable, this
; file does not by itself cause the resulting executable to be covered by
; the GNU General Public License. This exception does not however
; invalidate any other reasons why the executable file might be covered by
; the GNU General Public License.
; DO NOT EDIT - AUTOMATICALLY GENERATED FROM .s FILE
.code
ALIGN 8
PUBLIC __TBB_machine_fetchadd1
__TBB_machine_fetchadd1:
mov rax,rdx
lock xadd [rcx],al
ret
.code
ALIGN 8
PUBLIC __TBB_machine_fetchstore1
__TBB_machine_fetchstore1:
mov rax,rdx
lock xchg [rcx],al
ret
.code
ALIGN 8
PUBLIC __TBB_machine_cmpswp1
__TBB_machine_cmpswp1:
mov rax,r8
lock cmpxchg [rcx],dl
ret
.code
ALIGN 8
PUBLIC __TBB_machine_fetchadd2
__TBB_machine_fetchadd2:
mov rax,rdx
lock xadd [rcx],ax
ret
.code
ALIGN 8
PUBLIC __TBB_machine_fetchstore2
__TBB_machine_fetchstore2:
mov rax,rdx
lock xchg [rcx],ax
ret
.code
ALIGN 8
PUBLIC __TBB_machine_cmpswp2
__TBB_machine_cmpswp2:
mov rax,r8
lock cmpxchg [rcx],dx
ret
.code
ALIGN 8
PUBLIC __TBB_machine_pause
__TBB_machine_pause:
L1:
dw 090f3H; pause
add ecx,-1
jne L1
ret
end
| anasazi/POP-REU-Project | pkgs/libs/tbblib/src/src/tbb/em64t-masm/atomic_support.asm | Assembly | bsd-3-clause | 2,224 |
/*
* Intra predict 8x8 chroma block
* Copyright © <2010>, Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* This file was originally licensed under the following license
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#if !defined(__INTRA_PRED_CHROMA__) // Make sure this is only included once
#define __INTRA_PRED_CHROMA__
// Module name: intra_Pred_Chroma.asm
//
// Intra predict 8x8 chroma block
//
shr (1) PINTRAPRED_UV<1>:w REG_INTRA_CHROMA_PRED_MODE<0;1,0>:ub INTRA_CHROMA_PRED_MODE_SHIFT:w // Bits 1:0 = intra chroma pred mode
// WA for "jmpi" restriction
mov (1) REG_INTRA_TEMP_1<1>:d r[PINTRAPRED_UV, INTRA_CHROMA_OFFSET]:b
jmpi (1) REG_INTRA_TEMP_1<0;1,0>:d
// Mode 0
INTRA_CHROMA_DC:
and.nz.f0.0 (8) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_UP_AVAIL_FLAG:ud // Top macroblock available for intra prediction?
// Calculate DC values for sub-block 0 and 3
//
// Rearrange reference samples for unified DC prediction code
// Need to check INTRA_PRED_LEFT_TH_AVAIL_FLAG for blk0 and INTRA_PRED_LEFT_BH_AVAIL_FLAG for blk3
//
(-f0.0.any8h) mov (8) INTRA_REF_TOP_W(0)<1> 0x8080:uw // Up not available
and.nz.f0.1 (4) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG:ud
(-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0)<2> INTRA_REF_TOP_W(0)REGION(4,1) // Left top half macroblock not available for intra prediction
and.nz.f0.1 (4) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_BH_AVAIL_FLAG:ud
(-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0,8)<2> INTRA_REF_TOP_W(0,4)REGION(4,1) // Left bottom half macroblock not available for intra prediction
(-f0.0.any8h) mov (8) INTRA_REF_TOP_W(0)<1> INTRA_REF_LEFT_W(0)REGION(8,2) // Up not available
// Calculate DC prediction
//
add (16) PRED_UVW(0)<1> INTRA_REF_TOP(0)REGION(16,1) INTRA_REF_LEFT_UV(0)<4;2,1> // Sum of top and left reference
add (8) PRED_UVW(0)<1> PRED_UVW(0)<4;2,1> PRED_UVW(0,2)<4;2,1> // Sum of first half (blk #0) and second half (blk #3)
add (8) PRED_UVW(9)<1> PRED_UVW(0)<0;2,1> PRED_UVW(0,2)<0;2,1> // Sum of blk #0
add (8) PRED_UVW(11,8)<1> PRED_UVW(0,4)<0;2,1> PRED_UVW(0,6)<0;2,1> // Sum of blk #3
// Calculate DC values for sub-block 1 and 2
//
// Rearrange reference samples for unified DC prediction code
//
// Blk #2
(-f0.0.any4h) mov (4) INTRA_REF_TOP_W(0)<1> 0x8080:uw
(f0.1.any4h) mov (4) INTRA_REF_TOP_W(0)<1> INTRA_REF_LEFT_W(0,8)REGION(4,2) // Always use available left reference
(-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0,8)<2> INTRA_REF_TOP_W(0)REGION(4,1)
// Blk #1
and.nz.f0.1 (4) NULLREG REG_INTRA_PRED_AVAIL_FLAG INTRA_PRED_LEFT_TH_AVAIL_FLAG:ud
(-f0.1.any4h) mov (4) INTRA_REF_LEFT_W(0)<2> 0x8080:uw
(f0.0.any4h) mov (4) INTRA_REF_LEFT_W(0)<2> INTRA_REF_TOP_W(0,4)REGION(4,1) // Always use available top reference
(-f0.0.any4h) mov (4) INTRA_REF_TOP_W(0,4)<1> INTRA_REF_LEFT_W(0)REGION(4,2)
// Calculate DC prediction
//
add (8) PRED_UVW(0)<1> INTRA_REF_TOP(0)REGION(8,1) INTRA_REF_LEFT_UV(0,16)<4;2,1> // Sum of top and left reference for blk #2
add (8) PRED_UVW(0,8)<1> INTRA_REF_LEFT_UV(0)<4;2,1> INTRA_REF_TOP(0,8)REGION(8,1) // Sum of top and left reference for blk #1
add (8) PRED_UVW(0)<1> PRED_UVW(0)<4;2,1> PRED_UVW(0,2)<4;2,1> // Sum of first half (blk #2) and second half (blk #1)
add (8) PRED_UVW(9,8)<1> PRED_UVW(0,4)<0;2,1> PRED_UVW(0,6)<0;2,1> // Sum of blk #1
add (8) PRED_UVW(11)<1> PRED_UVW(0)<0;2,1> PRED_UVW(0,2)<0;2,1> // Sum of blk #2
// Now, PRED_UVW(9) holds sums for blks #0 and #1 and PRED_UVW(11) holds sums for blks #2 and #3
//
add (32) acc0<1>:w PRED_UVW(9)REGION(16,1) 4:w {Compr} // Add rounder
$for(0; <4; 2) {
shr (32) PRED_UVW(%1)<1> acc0:w 3:w {Compr}
}
add (32) acc0<1>:w PRED_UVW(11)REGION(16,1) 4:w {Compr} // Add rounder
$for(4; <8; 2) {
shr (32) PRED_UVW(%1)<1> acc0:w 3:w {Compr}
}
jmpi (1) End_of_intra_Pred_Chroma
// Mode 1
INTRA_CHROMA_HORIZONTAL:
mov (1) PREF_LEFT_UD<1>:ud INTRA_REF_LEFT_ID*GRFWIB*0x00010001+0x00040000:ud // Set address registers for instruction compression
$for(0,0; <8; 2,8) {
mov (32) PRED_UVW(%1)<1> r[PREF_LEFT,%2+2]<0;2,1>:ub {Compr} // Actual left column reference data start at offset 2
}
jmpi (1) End_of_intra_Pred_Chroma
// Mode 2
INTRA_CHROMA_VERTICAL:
$for(0; <8; 2) {
mov (32) PRED_UVW(%1)<1> INTRA_REF_TOP(0) {Compr}
}
jmpi (1) End_of_intra_Pred_Chroma
// Mode 3
INTRA_Chroma_PLANE:
// Refer to H.264/AVC spec Section 8.3.4.4
#undef C
#define A REG_INTRA_TEMP_2.0 // All are WORD type
#define B REG_INTRA_TEMP_3.0 // B[U] & B[V]
#define C REG_INTRA_TEMP_3.2 // C[U] & C[V]
#define YP REG_INTRA_TEMP_0 // Store intermediate results of c*(y-3). Make sure it's an even GRF
#define YP1 REG_INTRA_TEMP_1 // Store intermediate results of c*(y-3). Make sure it's an odd GRF
#define XP REG_INTRA_TEMP_5 // Store intermediate results of a+b*(x-3)+16. Make sure it's an odd GRF
// First Calculate constants H and V
// H1 = sum((x'+1)*p[4+x',-1]), x'=0,1,2,3
// H2 = sum((-x'-1)*p[2-x',-1]), x'=3,2,1,0
// H = H1 + H2
// The same calculation holds for V
//
mul (8) H1(0)<1> INTRA_REF_TOP(0,8)REGION(8,1) 0x44332211:v
mul (8) H2(0)<1> INTRA_REF_TOP(0,-2)REGION(8,1) 0xFFEEDDCC:v
mul (8) V1(0)<1> INTRA_REF_LEFT_UV(0,4*4)<4;2,1> 0x44332211:v
mul (8) V2(0)<1> INTRA_REF_LEFT_UV(0)<4;2,1> 0x00FFEEDD:v
mul (2) V2(0,6)<1> INTRA_REF_TOP(0,-2)REGION(2,1) -4:w // Replace 0*p[-1,3] with -4*p[-1,-1]
// Now, REG_INTRA_TEMP_0 holds [H2, H1] and REG_INTRA_TEMP_1 holds [V2, V1]
// Sum up [H2, H1] and [V2, V1] using instruction compression
// ExecSize = 16 is restricted by B-spec for instruction compression
// Actual intermediate results are in lower sub-registers after each summing step
add (16) H1(0)<1> H1(0) H2(0) {Compr} // Results in lower 8 WORDs
add (16) H1(0)<1> H1(0) H1(0,4) {Compr} // Results in lower 4 WORDs
add (16) H1(0)<1> H1(0) H1(0,2) {Compr} // Results in lower 2 WORDs
// Calculate a, b, c and further derivations
mov (16) acc0<1>:w 32:w
mac (4) acc0<1>:w H1(0)<16;2,1> 34:w
shr (4) B<1>:w acc0:w 6:w // Done b,c
mov (16) acc0<1>:w 16:w
mac (16) acc0<1>:w INTRA_REF_TOP(0,7*2)<0;2,1> 16:w
mac (16) A<1>:w INTRA_REF_LEFT_UV(0,7*4)<0;2,1> 16:w // A = a+16
mac (16) XP<1>:w B<0;2,1>:w XY_3<1;2,0>:b // XP = A+b*(x-3)
mul (8) YP<1>:w C<0;2,1>:w XY_3<2;2,0>:b // YP = c*(y-3), Even portion
mul (8) YP1<1>:w C<0;2,1>:w XY_3_1<2;2,0>:b // YP = c*(y-3), Odd portion
// Finally the intra_Chroma plane prediction
$for(0; <8; 2) {
add (32) acc0<1>:w XP<16;16,1>:w YP.%1<0;2,1>:w {Compr}
shr.sat (32) PRED_UV(%1)<2> acc0<16;16,1>:w 5:w {Compr}
}
End_of_intra_Pred_Chroma:
// End of intra_Pred_Chroma
#endif // !defined(__INTRA_PRED_CHROMA__)
| uartie/vaapi-intel-driver | src/shaders/h264/mc/intra_Pred_Chroma.asm | Assembly | mit | 8,470 |
; name: 16-bit mode - Using 32-bit memory addressing in 16-bit mode.
; code: "678B80FF000000678B9C43FF00000066678B80FF00000066678B9C43FF000000678980FF00000067899C43FF00000066678980FF0000006667899C43FF000000"
[bits 16]
mov ax,[eax+0xff]
mov bx,[eax*2+ebx+0xff]
mov eax,[eax+0xff]
mov ebx,[eax*2+ebx+0xff]
mov [eax+0xff],ax
mov [eax*2+ebx+0xff],bx
mov [eax+0xff],eax
mov [eax*2+ebx+0xff],ebx
| tpisto/pasm | tests/013_16-bit_mode_-_Using_32-bit_memory_addressing_in_16-bit_mode.asm | Assembly | mit | 391 |
; places 10^n on TOS
; cx contains n for 10^n
; bx contains addr for word containing 10
getmul proc
push cx
fld1
jcxz getmul_cleanup
getmul_1:
fimul word ptr [bx]
loop getmul_1
getmul_cleanup:
pop cx
ret
getmul endp
| UtkarshRay/MASM_8086 | getmul.asm | Assembly | mit | 260 |
; Copyright © 2021, VideoLAN and dav1d authors
; Copyright © 2021, Two Orioles, LLC
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%include "config.asm"
%include "ext/x86/x86inc.asm"
SECTION_RODATA 16
%if ARCH_X86_64
%define PIC_sym(a) a
%else
%define PIC_base $$
%define PIC_sym(a) pic_regq+a-PIC_base
%endif
pb_4x1_4x5_4x9_4x13: times 4 db 0, 1
times 4 db 8, 9
pw_1: times 8 dw 1
pw_2: times 8 dw 2
pw_3: times 8 dw 3
; 4 and 16 need to be next to each other since they are used as alternates
; depending on whether bitdepth is 10 or 12
pw_4: times 8 dw 4
pw_16: times 8 dw 16
pw_8: times 8 dw 8
pw_4096: times 8 dw 4096
pb_mask: dd 1, 1, 2, 2
SECTION .text
%if ARCH_X86_32
%if STACK_ALIGNMENT < 16
%define extra_stack 2
%else
%define extra_stack 0
%endif
%endif
%macro RELOC_ARGS 2 ; h/v, off
ASSERT ARCH_X86_32
%if STACK_ALIGNMENT < 16
mov r5d, [rstk + stack_offset + 4*4 + 4]
%define lstridem [esp+%2+0*gprsize]
mov lstridem, r5d
mov r5d, [rstk + stack_offset + 4*5 + 4]
%define lutm [esp+%2+1*gprsize]
mov lutm, r5d
mov r5d, [rstk + stack_offset + 4*6 + 4]
%ifidn %1, v
%define wm [esp+%2+2*gprsize]
mov wm, r5d
mov r5d, [rstk + stack_offset + 4*3 + 4]
%define lm [esp+%2+3*gprsize]
mov lm, r5d
%else ; %1 == h
%define hm [esp+%2+2*gprsize]
mov hm, r5d
%endif ; %1==v
mov r5d, r7m
%define bdmulm [esp+%2+4*gprsize]
mov bdmulm, r5d
%else
%define lstridem r4m
%define lutm r5m
%ifidn %1, v
%define wm r6m
%define lm r3m
%else
%define hm r6m
%endif
%define bdmulm r7m
%endif ; STACK_ALIGNMENT
%endmacro
%macro UNRELOC_ARGS 0
%if ARCH_X86_32
%undef lm
%undef lstridem
%undef wm
%undef hm
%undef lutm
%endif
%endmacro
%macro SPLATD 2
movd %1, %2
pshufd %1, %1, q0000
%endmacro
%macro SPLATW 2
movd %1, %2
pshuflw %1, %1, q0000
punpcklqdq %1, %1
%endmacro
; in: out:
; mm%1 a b c d a e i m
; mm%2 e f g h b f j n
; mm%3 i j k l -> c g k o
; mm%4 m n o p d h l p
%macro TRANSPOSE4X4W 5
punpcklwd m%5, m%1, m%2
punpckhwd m%1, m%2
punpcklwd m%2, m%3, m%4
punpckhwd m%3, m%4
punpckldq m%4, m%5, m%2
punpckhdq m%5, m%2
punpckldq m%2, m%1, m%3
punpckhdq m%1, m%3
SWAP %1, %4
SWAP %2, %5, %3
%endmacro
; in: out:
; m%1 a b c d e f g h a i q y 6 E M U
; m%2 i j k l m n o p b j r z 7 F N V
; m%3 q r s t u v w x c k s 0 8 G O W
; m%4 y z 0 1 2 3 4 5 d l t 1 9 H P X
; m%5 6 7 8 9 A B C D -> e m u 2 A I Q Y
; m%6 E F G H I J K L f n v 3 B J R Z
; m%7 M N O P Q R S T g o w 4 C K S +
; m%8 U V W X Y Z + = h p x 5 D L T =
%if ARCH_X86_64
%macro TRANSPOSE8X8W 9
; m%1 a b c d e f g h a i q y b j r z
; m%2 i j k l m n o p c k s 0 d l t 1
; m%3 q r s t u v w x -> e m u 2 f n v 3
; m%4 y z 0 1 2 3 4 5 g o w 4 h p x 5
TRANSPOSE4X4W %1, %2, %3, %4, %9
; m%5 6 7 8 9 A B C D 6 E M U 7 F N V
; m%6 E F G H I J K L 8 G O W 9 H P X
; m%7 M N O P Q R S T -> A I Q Y B J R Z
; m%8 U V W X Y Z + = C K S + D L T =
TRANSPOSE4X4W %5, %6, %7, %8, %9
; m%1 a i q y b j r z a i q y 6 E M U
; m%2 c k s 0 d l t 1 b j r z 7 F N V
; m%3 e m u 2 f n v 3 c k s 0 8 G O W
; m%4 g o w 4 h p x 5 d l t 1 9 H P X
; m%5 6 E M U 7 F N V -> e m u 2 A I Q Y
; m%6 8 G O W 9 H P X f n v 3 B J R Z
; m%7 A I Q Y B J R Z g o w 4 C K S +
; m%8 C K S + D L T = h p x 5 D L T =
punpckhqdq m%9, m%1, m%5
punpcklqdq m%1, m%5
punpckhqdq m%5, m%2, m%6
punpcklqdq m%2, m%6
punpckhqdq m%6, m%3, m%7
punpcklqdq m%3, m%7
punpckhqdq m%7, m%4, m%8
punpcklqdq m%4, m%8
SWAP %8, %7, %4, %5, %3, %2, %9
%endmacro
%else ; x86-32
; input: 1-7 in registers, 8 in first memory [read-only]
; second memory is scratch, and may overlap with first or third memory
; output: 1-5,7-8 in registers, 6 in third memory [write-only]
%macro TRANSPOSE8X8W 13 ; regs [8x], mem [3x], a/u [in/out alignment [2x]
TRANSPOSE4X4W %1, %2, %3, %4, %8
%ifnidn %9, ""
mov%12 m%8, %9
%else
mova m%8, %10
%endif
mova %10, m%4
TRANSPOSE4X4W %5, %6, %7, %8, %4
punpckhqdq m%4, m%1, m%5
punpcklqdq m%1, m%5
punpckhqdq m%5, m%2, m%6
punpcklqdq m%2, m%6
punpckhqdq m%6, m%3, m%7
punpcklqdq m%3, m%7
mova m%7, %10
%ifnidn %11, ""
mov%13 %11, m%6
%else
mova %10, m%6
%endif
punpckhqdq m%6, m%7, m%8
punpcklqdq m%7, m%8
; 1,4,2,5,3,8,7,6 -> 1,2,3,4,5,6,7,8
SWAP %2, %4, %5, %3
SWAP %6, %8
%endmacro
%endif ; x86-32/64
; transpose and write m8-11, everything else is scratch
%macro TRANSPOSE_8x4_AND_WRITE_4x8 5 ; p1, p0, q0, q1, tmp
; transpose 8x4
punpcklwd %5, %1, %2
punpckhwd %1, %2
punpcklwd %2, %3, %4
punpckhwd %3, %4
punpckldq %4, %5, %2
punpckhdq %5, %2
punpckldq %2, %1, %3
punpckhdq %1, %3
; write out
movq [dstq+strideq*0-4], %4
movhps [dstq+strideq*1-4], %4
movq [dstq+strideq*2-4], %5
movhps [dstq+stride3q -4], %5
lea dstq, [dstq+strideq*4]
movq [dstq+strideq*0-4], %2
movhps [dstq+strideq*1-4], %2
movq [dstq+strideq*2-4], %1
movhps [dstq+stride3q -4], %1
lea dstq, [dstq+strideq*4]
%endmacro
%macro FILTER 2 ; width [4/6/8/16], dir [h/v]
; load data
%ifidn %2, v
%if %1 == 4
%if ARCH_X86_64
%define P1 m8
%define P0 m9
%define Q0 m10
%define Q1 m11
mova P1, [dstq+mstrideq*2] ; p1
mova P0, [dstq+mstrideq*1] ; p0
mova Q0, [dstq+strideq*0] ; q0
mova Q1, [dstq+strideq*1] ; q1
%else ; x86-32
%define P1 [dstq+mstrideq*2]
%define P0 [dstq+mstrideq*1]
%define Q0 [dstq+strideq*0]
%define Q1 [dstq+strideq*1]
%endif ; x86-32/64
%else ; %1 != 4
; load 6-8 pixels, remainder (for wd=16) will be read inline
lea tmpq, [dstq+mstrideq*4]
%if ARCH_X86_64
; we load p3 later
%define P2 m13
%define P1 m8
%define P0 m9
%define Q0 m10
%define Q1 m11
%define Q2 m14
mova P2, [tmpq+strideq*1]
mova P1, [tmpq+strideq*2]
mova P0, [tmpq+stride3q]
mova Q0, [dstq+strideq*0]
mova Q1, [dstq+strideq*1]
mova Q2, [dstq+strideq*2]
%if %1 != 6
%define P3 [tmpq+strideq*0]
%define Q3 m15
mova Q3, [dstq+stride3q]
%endif ; %1 != 6
%else ; x86-32
%define P2 [tmpq+strideq*1]
%define P1 [dstq+mstrideq*2]
%define P0 [dstq+mstrideq*1]
%define Q0 [dstq+strideq*0]
%define Q1 [dstq+strideq*1]
%define Q2 [dstq+strideq*2]
%if %1 != 6
%define P3 [dstq+mstrideq*4]
%define Q3 [dstq+stride3q]
%endif ; %1 != 6
%endif ; x86-32/64
%endif ; %1 ==/!= 4
%else ; %2 != v
; load lines
%if %1 == 4
movq m0, [dstq+strideq*0-4]
movq m2, [dstq+strideq*1-4]
movq m4, [dstq+strideq*2-4]
movq m5, [dstq+stride3q -4]
lea tmpq, [dstq+strideq*4]
movq m3, [tmpq+strideq*0-4]
movq m6, [tmpq+strideq*1-4]
movq m1, [tmpq+strideq*2-4]
movq m7, [tmpq+stride3q -4]
; transpose 4x8
; m0: A-D0
; m2: A-D1
; m4: A-D2
; m5: A-D3
; m3: A-D4
; m6: A-D5
; m1: A-D6
; m7: A-D7
punpcklwd m0, m2
punpcklwd m4, m5
punpcklwd m3, m6
punpcklwd m1, m7
; m0: A0-1,B0-1,C0-1,D0-1
; m4: A2-3,B2-3,C2-3,D2-3
; m3: A4-5,B4-5,C4-5,D4-5
; m1: A6-7,B6-7,C6-7,D6-7
punpckhdq m2, m0, m4
punpckldq m0, m4
punpckhdq m4, m3, m1
punpckldq m3, m1
; m0: A0-3,B0-3
; m2: C0-3,D0-3
; m3: A4-7,B4-7
; m4: C4-7,D4-7
punpckhqdq m1, m0, m3
punpcklqdq m0, m3
punpckhqdq m3, m2, m4
punpcklqdq m2, m4
; m0: A0-7
; m1: B0-7
; m2: C0-7
; m3: D0-7
%if ARCH_X86_64
SWAP 0, 8
SWAP 1, 9
SWAP 2, 10
SWAP 3, 11
%define P1 m8
%define P0 m9
%define Q0 m10
%define Q1 m11
%else
%define P1 [esp+3*mmsize]
%define P0 [esp+4*mmsize]
%define Q0 [esp+5*mmsize]
%define Q1 [esp+6*mmsize]
mova P1, m0
mova P0, m1
mova Q0, m2
mova Q1, m3
%endif
%elif %1 == 6 || %1 == 8
movu m0, [dstq+strideq*0-8]
movu m1, [dstq+strideq*1-8]
movu m2, [dstq+strideq*2-8]
movu m3, [dstq+stride3q -8]
lea tmpq, [dstq+strideq*4]
movu m4, [tmpq+strideq*0-8]
movu m5, [tmpq+strideq*1-8]
movu m6, [tmpq+strideq*2-8]
%if ARCH_X86_64
movu m7, [tmpq+stride3q -8]
%endif
; transpose 8x16
; m0: A-H0,A-H8
; m1: A-H1,A-H9
; m2: A-H2,A-H10
; m3: A-H3,A-H11
; m4: A-H4,A-H12
; m5: A-H5,A-H13
; m6: A-H6,A-H14
; m7: A-H7,A-H15
%if ARCH_X86_64
punpcklwd m8, m0, m1
%else
punpcklwd m7, m0, m1
%endif
punpckhwd m0, m1
punpcklwd m1, m2, m3
punpckhwd m2, m3
punpcklwd m3, m4, m5
punpckhwd m4, m5
%if ARCH_X86_64
punpcklwd m5, m6, m7
punpckhwd m6, m7
%else
mova [rsp+3*16], m4
movu m4, [tmpq+stride3q -8]
punpcklwd m5, m6, m4
punpckhwd m6, m4
%endif
; m8: A0-1,B0-1,C0-1,D0-1 [m7 on x86-32]
; m0: E0-1,F0-1,G0-1,H0-1
; m1: A2-3,B2-3,C2-3,D2-3
; m2: E2-3,F2-3,G2-3,H2-3
; m3: A4-5,B4-5,C4-5,D4-5
; m4: E4-5,F4-5,G4-5,H4-5 [r3 on x86-32]
; m5: A6-7,B6-7,C6-7,D6-7
; m6: E6-7,F6-7,G6-7,H6-7
%if ARCH_X86_64
punpckldq m7, m8, m1
punpckhdq m8, m1
%else
punpckldq m4, m7, m1
punpckhdq m7, m1
%endif
punpckldq m1, m0, m2
punpckhdq m0, m2
punpckldq m2, m3, m5
punpckhdq m3, m5
%if ARCH_X86_64
punpckldq m5, m4, m6
punpckhdq m4, m6
%else
mova [rsp+4*16], m3
mova m3, [rsp+3*16]
punpckldq m5, m3, m6
punpckhdq m3, m6
%endif
; m7: A0-3,B0-3 [m4 on x86-32]
; m8: C0-3,D0-3 [m7 on x86-32]
; m1: E0-3,F0-3
; m0: G0-3,H0-3
; m2: A4-7,B4-7
; m3: C4-7,D4-7 [r4 on x86-32]
; m5: E4-7,F4-7
; m4: G4-7,H4-7 [m3 on x86-32]
%if ARCH_X86_64
%if %1 != 6
punpcklqdq m6, m7, m2
%endif
punpckhqdq m7, m2
punpcklqdq m2, m8, m3
punpckhqdq m8, m3
punpcklqdq m3, m1, m5
punpckhqdq m1, m5
%if %1 != 6
punpckhqdq m5, m0, m4
%endif
punpcklqdq m0, m4
%if %1 == 8
mova [rsp+1*16], m6
%define P3 [rsp+1*16]
%endif
; 7,2,8,3,1,0,5 -> 13,8,9,10,11,14,15
SWAP 7, 13
SWAP 8, 2, 9
SWAP 3, 10
SWAP 1, 11
SWAP 0, 14
SWAP 5, 15
%define P2 m13
%define P1 m8
%define P0 m9
%define Q0 m10
%define Q1 m11
%define Q2 m14
%if %1 == 8
%define Q3 m15
%endif
%else ; x86-32
%if %1 == 8
%define P3 [rsp+ 6*16]
punpcklqdq m6, m4, m2
mova P3, m6
%endif
mova m6, [rsp+4*16]
punpckhqdq m4, m2
punpcklqdq m2, m7, m6
punpckhqdq m7, m6
punpcklqdq m6, m1, m5
punpckhqdq m1, m5
%if %1 == 8
%define Q3 [rsp+24*16]
punpckhqdq m5, m0, m3
mova Q3, m5
%endif
punpcklqdq m0, m3
%if %1 == 8
%define P2 [rsp+18*16]
%define P1 [rsp+19*16]
%define P0 [rsp+20*16]
%define Q0 [rsp+21*16]
%define Q1 [rsp+22*16]
%define Q2 [rsp+23*16]
%else
%define P2 [rsp+3*16]
%define P1 [rsp+4*16]
%define P0 [rsp+5*16]
%define Q0 [rsp+6*16]
%define Q1 [rsp+7*16]
%define Q2 [rsp+8*16]
%endif
mova P2, m4
mova P1, m2
mova P0, m7
mova Q0, m6
mova Q1, m1
mova Q2, m0
%endif ; x86-32/64
%else ; %1 == 16
; We only use 14 pixels but we'll need the remainder at the end for
; the second transpose
mova m0, [dstq+strideq*0-16]
mova m1, [dstq+strideq*1-16]
mova m2, [dstq+strideq*2-16]
mova m3, [dstq+stride3q -16]
lea tmpq, [dstq+strideq*4]
mova m4, [tmpq+strideq*0-16]
mova m5, [tmpq+strideq*1-16]
mova m6, [tmpq+strideq*2-16]
%if ARCH_X86_64
mova m7, [tmpq+stride3q -16]
TRANSPOSE8X8W 0, 1, 2, 3, 4, 5, 6, 7, 8
SWAP 5, 13
SWAP 6, 8
SWAP 7, 9
%define P2 m13
%define P1 m8
%define P0 m9
%else ; x86-32
%define P2 [esp+18*16]
%define P1 [esp+19*16]
%define P0 [esp+20*16]
TRANSPOSE8X8W 0, 1, 2, 3, 4, 5, 6, 7, \
[tmpq+stride3q -16], P2, "", a, a
mova P1, m6
mova P0, m7
%endif ; x86-32/64
mova [rsp+ 7*16], m0
mova [rsp+ 8*16], m1
mova [rsp+ 9*16], m2
mova [rsp+10*16], m3
%define P3 [rsp+6*16]
mova P3, m4
mova m0, [dstq+strideq*0]
mova m1, [dstq+strideq*1]
mova m2, [dstq+strideq*2]
mova m3, [dstq+stride3q ]
lea tmpq, [dstq+strideq*4]
mova m4, [tmpq+strideq*0]
mova m5, [tmpq+strideq*1]
mova m6, [tmpq+strideq*2]
%if ARCH_X86_64
mova m7, [tmpq+stride3q ]
TRANSPOSE8X8W 0, 1, 2, 3, 4, 5, 6, 7, 10
SWAP 0, 10
SWAP 1, 11
SWAP 2, 14
SWAP 3, 15
%define Q0 m10
%define Q1 m11
%define Q2 m14
%define Q3 m15
%else ; x86-32
TRANSPOSE8X8W 0, 1, 2, 3, 4, 5, 6, 7, \
[tmpq+stride3q ], [rsp+12*16], "", a, a
%define Q0 [esp+21*16]
%define Q1 [esp+22*16]
%define Q2 [esp+23*16]
%define Q3 [esp+24*16]
mova Q0, m0
mova Q1, m1
mova Q2, m2
mova Q3, m3
%endif ; x86-32/64
mova [rsp+11*16], m4
%if ARCH_X86_64
mova [rsp+12*16], m5
%endif
mova [rsp+13*16], m6
mova [rsp+14*16], m7
%endif ; %1 == 4/6/8/16
%endif ; %2 ==/!= v
; load L/E/I/H
%if ARCH_X86_32
%define l_strideq r5
mov l_strideq, dword lstridem
%ifidn %2, v
%define lq r3
mov lq, dword lm
%endif
%endif
%ifidn %2, v
%if cpuflag(sse4)
pmovzxbw m1, [lq]
pmovzxbw m0, [lq+l_strideq]
pxor m2, m2
%else ; ssse3
movq m1, [lq]
movq m0, [lq+l_strideq]
pxor m2, m2
REPX {punpcklbw x, m2}, m1, m0
%endif ; ssse3/sse4
%else ; %2 != v
movq m0, [lq] ; l0, l1
movq m1, [lq+l_strideq] ; l2, l3
punpckldq m0, m1 ; l0, l2, l1, l3
pxor m2, m2
punpcklbw m1, m0, m2 ; l0, l2
punpckhbw m0, m2 ; l1, l3
%endif ; %2==/!=v
%if ARCH_X86_32
%ifidn %2, v
%undef lq
mov mstrideq, mstridem
%endif
%endif
pcmpeqw m5, m2, m0
pand m1, m5
por m0, m1 ; l[x][] ? l[x][] : l[x-stride][]
pshufb m0, [PIC_sym(pb_4x1_4x5_4x9_4x13)] ; l[x][1]
pcmpeqw m5, m2, m0 ; !L
psrlw m5, 1
%if ARCH_X86_64
psrlw m2, m0, [lutq+128]
SPLATW m1, [lutq+136]
%else ; x86-32
mov r5, lutm
psrlw m2, m0, [r5+128]
SPLATW m1, [r5+136]
%endif ; x86-32/64
pminsw m2, m1
pmaxsw m2, [PIC_sym(pw_1)] ; I
psrlw m1, m0, 4 ; H
paddw m0, [PIC_sym(pw_2)]
paddw m0, m0
paddw m0, m2 ; E
REPX {pmullw x, [bdmulq]}, m0, m1, m2
%if ARCH_X86_32
%undef l_strideq
lea stride3q, [strideq*3]
%endif
psubw m3, P1, P0 ; p1-p0
psubw m4, Q0, Q1 ; q0-q1
REPX {pabsw x, x}, m3, m4
pmaxsw m3, m5
pmaxsw m3, m4
pcmpgtw m7, m3, m1 ; hev
%if %1 != 4
psubw m4, P2, P0 ; p2-p0
pabsw m4, m4
pmaxsw m4, m3
%if %1 != 6
mova m6, P3 ; p3
psubw m5, m6, P0 ; p3-p0
pabsw m5, m5
pmaxsw m4, m5
%endif ; %1 != 6
psubw m5, Q0, Q2 ; q0-q2
pabsw m5, m5
pmaxsw m4, m5
%if %1 != 6
psubw m5, Q0, Q3 ; q0-q3
pabsw m5, m5
pmaxsw m4, m5
%endif ; %1 != 6
pcmpgtw m4, [bdmulq] ; !flat8in
psubw m5, P2, P1 ; p2-p1
pabsw m5, m5
%if %1 != 6
psubw m6, P2 ; p3-p2
pabsw m6, m6
pmaxsw m5, m6
psubw m6, Q2, Q3 ; q2-q3
pabsw m6, m6
pmaxsw m5, m6
%endif ; %1 != 6
psubw m6, Q2, Q1 ; q2-q1
pabsw m6, m6
pmaxsw m5, m6
%if %1 == 16
SPLATD m6, [maskq+8]
SPLATD m1, [maskq+4]
por m6, m1
pand m6, m12
pcmpeqd m6, m12
pand m5, m6
%else ; %1 != 16
SPLATD m6, [maskq+4]
pand m6, m12
pcmpeqd m6, m12
pand m5, m6 ; only apply fm-wide to wd>4 blocks
%endif ; %1==/!=16
pmaxsw m3, m5
%endif ; %1 != 4
pcmpgtw m3, m2
psubw m5, P1, Q1 ; p1-q1
psubw m6, P0, Q0 ; p0-q0
REPX {pabsw x, x}, m5, m6
paddw m6, m6
psrlw m5, 1
paddw m5, m6 ; abs(p0-q0)*2+(abs(p1-q1)>>1)
pcmpgtw m5, m0 ; abs(p0-q0)*2+(abs(p1-q1)>>1) > E
por m3, m5
%if %1 == 16
%ifidn %2, v
lea tmpq, [dstq+mstrideq*8]
mova m0, [tmpq+strideq*1]
mova m1, [tmpq+strideq*2]
mova m2, [tmpq+stride3q]
%else ; %2 != v
mova m0, [rsp+ 8*16]
mova m1, [rsp+ 9*16]
mova m2, [rsp+10*16]
%endif ; %2==/!=v
REPX {psubw x, P0}, m0, m1, m2
REPX {pabsw x, x}, m0, m1, m2
pmaxsw m1, m0
pmaxsw m1, m2
%ifidn %2, v
lea tmpq, [dstq+strideq*4]
mova m0, [tmpq+strideq*0]
mova m2, [tmpq+strideq*1]
mova m5, [tmpq+strideq*2]
%else ; %2 != v
mova m0, [rsp+11*16]
mova m2, [rsp+12*16]
mova m5, [rsp+13*16]
%endif ; %2==/!=v
REPX {psubw x, Q0}, m0, m2, m5
REPX {pabsw x, x}, m0, m2, m5
pmaxsw m0, m2
pmaxsw m1, m5
pmaxsw m1, m0
pcmpgtw m1, [bdmulq] ; !flat8out
por m1, m4 ; !flat8in | !flat8out
SPLATD m2, [maskq+8]
pand m5, m2, m12
pcmpeqd m5, m12
pandn m1, m5 ; flat16
pandn m5, m3, m1 ; flat16 & fm
SWAP 1, 5
SPLATD m5, [maskq+4]
por m5, m2
pand m2, m5, m12
pcmpeqd m2, m12
pandn m4, m2 ; flat8in
pandn m2, m3, m4
SWAP 2, 4
SPLATD m2, [maskq+0]
por m2, m5
pand m2, m12
pcmpeqd m2, m12
pandn m3, m2
pandn m0, m4, m3 ; fm & !flat8 & !flat16
SWAP 0, 3
pandn m0, m1, m4 ; flat8 & !flat16
SWAP 0, 4
%elif %1 != 4
SPLATD m0, [maskq+4]
pand m2, m0, m12
pcmpeqd m2, m12
pandn m4, m2
pandn m2, m3, m4 ; flat8 & fm
SWAP 2, 4
SPLATD m2, [maskq+0]
por m0, m2
pand m0, m12
pcmpeqd m0, m12
pandn m3, m0
pandn m0, m4, m3 ; fm & !flat8
SWAP 0, 3
%else ; %1 == 4
SPLATD m0, [maskq+0]
pand m0, m12
pcmpeqd m0, m12
pandn m3, m0 ; fm
%endif ; %1==/!=4
; short filter
%if ARCH_X86_64
SPLATW m0, r7m
%else
SPLATW m0, bdmulm
%endif
pcmpeqw m2, m2
psrlw m0, 1 ; 511 or 2047
pxor m2, m0 ; -512 or -2048
psubw m5, Q0, P0 ; q0-p0
paddw m6, m5, m5
paddw m6, m5 ; 3*(q0-p0)
psubw m5, P1, Q1 ; iclip_diff(p1-q1)
pminsw m5, m0
pmaxsw m5, m2
pand m5, m7 ; f=iclip_diff(p1-q1)&hev
paddw m5, m6 ; f=iclip_diff(3*(q0-p0)+f)
pminsw m5, m0
pmaxsw m5, m2
pand m3, m5 ; f&=fm
paddw m5, m3, [PIC_sym(pw_3)]
paddw m3, [PIC_sym(pw_4)]
REPX {pminsw x, m0}, m5, m3
psraw m5, 3 ; f2
psraw m3, 3 ; f1
psubw m0, m2 ; 1023 or 4095
pxor m2, m2
%if ARCH_X86_64
paddw P0, m5
psubw Q0, m3
%else
paddw m5, P0
psubw m6, Q0, m3
REPX {pminsw x, m0}, m5, m6
REPX {pmaxsw x, m2}, m5, m6
%endif
paddw m3, [PIC_sym(pw_1)]
psraw m3, 1 ; f=(f1+1)>>1
pandn m7, m3 ; f&=!hev
SWAP 7, 3
%if ARCH_X86_64
paddw P1, m3
psubw Q1, m3
REPX {pminsw x, m0}, P1, P0, Q0, Q1
REPX {pmaxsw x, m2}, P1, P0, Q0, Q1
%else
psubw m7, Q1, m3
paddw m3, P1
REPX {pminsw x, m0}, m7, m3
REPX {pmaxsw x, m2}, m7, m3
%if %1 > 4
mova P1, m3
mova P0, m5
mova Q0, m6
mova Q1, m7
%endif
%endif
%if %1 == 16
; m8-11 = p1/p0/q0/q1, m4=flat8, m1=flat16
; m12=filter bits mask
; m13-15=p2/q2/q3
; m0,2-3,5-7 = free
; flat16 filter
%ifidn %2, v
lea tmpq, [dstq+mstrideq*8]
mova m0, [tmpq+strideq*1] ; p6
mova m2, [tmpq+strideq*2] ; p5
mova m7, [tmpq+stride3q] ; p4
mova m6, [tmpq+strideq*4] ; p3
lea tmpq, [dstq+mstrideq*4]
%else ; %2 != v
mova m0, [rsp+ 8*16]
mova m2, [rsp+ 9*16]
mova m7, [rsp+10*16]
mova m6, [rsp+ 6*16]
%endif ; %2==/!=v
mova [rsp+ 0*16], m4
; p6*7+p5*2+p4*2+p3+p2+p1+p0+q0
psllw m3, m0, 3 ; p6*8
paddw m3, [PIC_sym(pw_8)]
paddw m5, m2, m7 ; p5+p4
psubw m3, m0
paddw m5, m5 ; (p5+p4)*2
paddw m3, m6 ; p6*7+p3
paddw m5, P2 ; (p5+p4)*2+p2
paddw m3, P1 ; p6*7+p3+p1
paddw m5, P0 ; (p5+p4)*2+p2+p0
paddw m3, Q0 ; p6*7+p3+p1+q0
paddw m3, m5 ; p6*7+p5*2+p4*2+p3+p2+p1+p0+q0
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, m2
por m5, m4
%ifidn %2, v
mova [tmpq+mstrideq*2], m5 ; p5
%else ; %2 != v
mova [rsp+9*16], m5
%endif ; %2==/!=v
; sub p6*2, add p3/q1
paddw m3, m6
paddw m5, m0, m0
paddw m3, Q1
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, m7
por m5, m4
%ifidn %2, v
mova [tmpq+mstrideq*1], m5 ; p4
%else ; %2 != v
mova [rsp+10*16], m5
%endif ; %2==/!=v
; sub p6/p5, add p2/q2
psubw m3, m0
paddw m5, P2, Q2
psubw m3, m2
paddw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, m6
por m5, m4
%ifidn %2, v
mova [tmpq+strideq*0], m5 ; p3
%else ; %2 != v
mova [rsp+6*16], m5
%endif ; %2==/!=v
%define WRITE_IN_PLACE 0
%ifidn %2, v
%if ARCH_X86_64
%define WRITE_IN_PLACE 1
%endif
%endif
; sub p6/p4, add p1/q3
paddw m3, P1
paddw m5, m0, m7
paddw m3, Q3
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, P2
por m5, m4
%if WRITE_IN_PLACE
mova [tmpq+strideq*1], m5
%else
mova [rsp+1*16], m5 ; don't clobber p2/m13
%endif
; sub p6/p3, add p0/q4
paddw m3, P0
paddw m5, m0, m6
%ifidn %2, v
paddw m3, [dstq+strideq*4]
%else ; %2 != v
paddw m3, [rsp+11*16]
%endif ; %2==/!=v
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, P1
por m5, m4
%if WRITE_IN_PLACE
mova [dstq+mstrideq*2], m5
%else
mova [rsp+2*16], m5 ; don't clobber p1/m3
%endif
; sub p6/p2, add q0/q5
paddw m3, Q0
paddw m5, m0, P2
%ifidn %2, v
%if ARCH_X86_32
lea r4, P2
%endif
lea tmpq, [dstq+strideq*4]
paddw m3, [tmpq+strideq*1]
%else ; %2 != v
paddw m3, [rsp+12*16]
%endif ; %2==/!=v
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, P0
por m5, m4
%if WRITE_IN_PLACE
mova [dstq+mstrideq*1], m5
%else
mova [rsp+3*16], m5 ; don't clobber p0/m4
%endif
; sub p6/p1, add q1/q6
paddw m3, Q1
paddw m5, m0, P1
%ifidn %2, v
mova m0, [tmpq+strideq*2] ; q6
%else ; %2 != v
mova m0, [rsp+13*16] ; q6
%endif ; %2==/!=v
paddw m3, m0
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, Q0
por m5, m4
%if WRITE_IN_PLACE
mova [dstq], m5
%else
mova [rsp+4*16], m5 ; don't clobber q0/m5
%endif
; sub p5/p0, add q2/q6
paddw m3, Q2
paddw m5, m2, P0
paddw m3, m0
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
pandn m4, m1, Q1
por m2, m5, m4 ; don't clobber q1/m6
; sub p4/q0, add q3/q6
paddw m3, Q3
paddw m7, Q0
paddw m3, m0
psubw m3, m7
psrlw m7, m3, 4
pand m7, m1
pandn m4, m1, Q2
por m7, m4 ; don't clobber q2/m14
; sub p3/q1, add q4/q6
%ifidn %2, v
paddw m3, [tmpq+strideq*0]
%else ; %2 != v
paddw m3, [rsp+11*16]
%endif ; %2==/!=v
paddw m6, Q1
paddw m3, m0
psubw m3, m6
psrlw m6, m3, 4
pand m6, m1
pandn m4, m1, Q3
por m6, m4
%if WRITE_IN_PLACE
mova [tmpq+mstrideq], m6 ; q3
%else ; %2 != v
mova [rsp+5*16], m6
%endif ; %2==/!=v
; sub p2/q2, add q5/q6
%ifidn %2, v
paddw m3, [tmpq+strideq*1]
%if ARCH_X86_64
paddw m5, P2, Q2
%else
; because tmpq is clobbered, so we use a backup pointer for P2 instead
paddw m5, [r4], Q2
mov pic_regq, pic_regm
%endif
%else ; %2 != v
paddw m3, [rsp+12*16]
paddw m5, P2, Q2
%endif ; %2==/!=v
paddw m3, m0
psubw m3, m5
psrlw m5, m3, 4
pand m5, m1
%ifidn %2, v
pandn m4, m1, [tmpq+strideq*0]
%else ; %2 != v
pandn m4, m1, [rsp+11*16]
%endif ; %2==/!=v
por m5, m4
%ifidn %2, v
mova [tmpq+strideq*0], m5 ; q4
%else ; %2 != v
mova [rsp+11*16], m5
%endif ; %2==/!=v
; sub p1/q3, add q6*2
psubw m3, P1
paddw m0, m0
psubw m3, Q3
paddw m3, m0
psrlw m5, m3, 4
pand m5, m1
%ifidn %2, v
pandn m4, m1, [tmpq+strideq*1]
%else ; %2 != v
pandn m4, m1, [rsp+12*16]
%endif ; %2==/!=v
por m5, m4
%ifidn %2, v
mova [tmpq+strideq*1], m5 ; q5
%else ; %2 != v
mova [rsp+12*16], m5
%endif ; %2==/!=v
mova m4, [rsp+0*16]
%ifidn %2, v
lea tmpq, [dstq+mstrideq*4]
%endif
%if ARCH_X86_64
SWAP 2, 11
SWAP 7, 14
SWAP 6, 15
%else ; x86-32
mova Q1, m2
mova Q2, m7
%endif ; x86-32/64
%if WRITE_IN_PLACE
mova P2, [tmpq+strideq*1]
mova P1, [tmpq+strideq*2]
mova P0, [tmpq+stride3q]
mova Q0, [dstq]
%elif ARCH_X86_64
mova P2, [rsp+1*16]
mova P1, [rsp+2*16]
mova P0, [rsp+3*16]
mova Q0, [rsp+4*16]
%else ; !WRITE_IN_PLACE & x86-32
mova m0, [rsp+1*16]
mova m1, [rsp+2*16]
mova m2, [rsp+3*16]
mova m3, [rsp+4*16]
mova m7, [rsp+5*16]
mova P2, m0
mova P1, m1
mova P0, m2
mova Q0, m3
mova Q3, m7
%endif ; WRITE_IN_PLACE / x86-32/64
%undef WRITE_IN_PLACE
%endif ; %1 == 16
%if %1 >= 8
; flat8 filter
mova m0, P3 ; p3
paddw m1, m0, P2 ; p3+p2
paddw m2, P1, P0 ; p1+p0
paddw m3, m1, m1 ; 2*(p3+p2)
paddw m2, m0 ; p1+p0+p3
paddw m3, Q0 ; 2*(p3+p2)+q0
paddw m2, m3 ; 3*p3+2*p2+p1+p0+q0
pmulhrsw m7, m2, [PIC_sym(pw_4096)]
psubw m7, P2
pand m7, m4
paddw m3, P1, Q1 ; p1+q1
psubw m2, m1 ; 2*p3+p2+p1+p0+q0
paddw m2, m3 ; 2*p3+p2+2*p1+p0+q0+q1
pmulhrsw m3, m2, [PIC_sym(pw_4096)]
psubw m3, P1
pand m3, m4
paddw m5, m0, P1 ; p3+p1
paddw m6, P0, Q2 ; p0+q2
psubw m2, m5 ; p3+p2+p1+p0+q0+q1
paddw m2, m6 ; p3+p2+p1+2*p0+q0+q1+q2
pmulhrsw m5, m2, [PIC_sym(pw_4096)]
psubw m5, P0
pand m5, m4
paddw m6, m0, P0 ; p3+p0
paddw m1, Q0, Q3 ; q0+q3
psubw m2, m6 ; p2+p1+p0+q0+q1+q2
paddw m2, m1 ; p2+p1+p0+2*q0+q1+q2+q3
pmulhrsw m6, m2, [PIC_sym(pw_4096)]
psubw m6, Q0
pand m6, m4
paddw m2, Q1 ; p2+p1+p0+2*q0+2*q1+q2+q3
paddw m2, Q3 ; p2+p1+p0+2*q0+2*q1+q2+2*q3
paddw m1, P2, Q0 ; p2+q0
psubw m2, m1 ; p1+p0+q0+2*q1+q2+2*q3
pmulhrsw m1, m2, [PIC_sym(pw_4096)]
psubw m1, Q1
pand m1, m4
psubw m2, P1 ; p0+q0+2*q1+q2+2*q3
psubw m2, Q1 ; p0+q0+q1+q2+2*q3
paddw m0, Q3, Q2 ; q3+q2
paddw m2, m0 ; p0+q0+q1+2*q2+3*q3
pmulhrsw m2, [PIC_sym(pw_4096)]
psubw m2, Q2
pand m2, m4
paddw m7, P2
paddw m3, P1
paddw m5, P0
paddw m6, Q0
paddw m1, Q1
paddw m2, Q2
%ifidn %2, v
mova [tmpq+strideq*1], m7 ; p2
mova [tmpq+strideq*2], m3 ; p1
mova [tmpq+stride3q ], m5 ; p0
mova [dstq+strideq*0], m6 ; q0
mova [dstq+strideq*1], m1 ; q1
mova [dstq+strideq*2], m2 ; q2
%else ; %2 != v
mova m0, P3
%if %1 == 8
lea tmpq, [dstq+strideq*4]
%if ARCH_X86_64
SWAP 4, 15
TRANSPOSE8X8W 0, 7, 3, 5, 6, 1, 2, 4, 8
%else
TRANSPOSE8X8W 0, 7, 3, 5, 6, 1, 2, 4, "", \
Q3, [tmpq+strideq*1-8], a, u
%endif
; write 8x8
movu [dstq+strideq*0-8], m0
movu [dstq+strideq*1-8], m7
movu [dstq+strideq*2-8], m3
movu [dstq+stride3q -8], m5
movu [tmpq+strideq*0-8], m6
%if ARCH_X86_64
movu [tmpq+strideq*1-8], m1
%endif
movu [tmpq+strideq*2-8], m2
movu [tmpq+stride3q -8], m4
lea dstq, [dstq+strideq*8]
%else ; %1 != 8
%if ARCH_X86_64
SWAP 6, 8
SWAP 1, 9
SWAP 2, 10
%else
mova [rsp+1*16], m6
mova [rsp+2*16], m1
mova [rsp+3*16], m2
%endif
mova m1, [rsp+ 7*16]
mova m2, [rsp+ 8*16]
mova m4, [rsp+ 9*16]
mova m6, [rsp+10*16]
lea tmpq, [dstq+strideq*4]
%if ARCH_X86_64
TRANSPOSE8X8W 1, 2, 4, 6, 0, 7, 3, 5, 11
%else
mova [rsp+7*16], m5
TRANSPOSE8X8W 1, 2, 4, 6, 0, 7, 3, 5, "", \
[rsp+7*16], [tmpq+strideq*1-16], a, a
%endif
mova [dstq+strideq*0-16], m1
mova [dstq+strideq*1-16], m2
mova [dstq+strideq*2-16], m4
mova [dstq+stride3q -16], m6
mova [tmpq+strideq*0-16], m0
%if ARCH_X86_64
mova [tmpq+strideq*1-16], m7
%endif
mova [tmpq+strideq*2-16], m3
mova [tmpq+stride3q -16], m5
%if ARCH_X86_64
SWAP 6, 8
SWAP 1, 9
SWAP 2, 10
SWAP 4, 15
%else
mova m6, [rsp+1*16]
mova m1, [rsp+2*16]
mova m2, [rsp+3*16]
mova m4, Q3
%endif
mova m0, [rsp+11*16]
mova m3, [rsp+12*16]
mova m5, [rsp+13*16]
%if ARCH_X86_64
mova m7, [rsp+14*16]
TRANSPOSE8X8W 6, 1, 2, 4, 0, 3, 5, 7, 8
%else
TRANSPOSE8X8W 6, 1, 2, 4, 0, 3, 5, 7, "", \
[rsp+14*16], [tmpq+strideq*1], a, a
%endif
mova [dstq+strideq*0], m6
mova [dstq+strideq*1], m1
mova [dstq+strideq*2], m2
mova [dstq+stride3q ], m4
mova [tmpq+strideq*0], m0
%if ARCH_X86_64
mova [tmpq+strideq*1], m3
%endif
mova [tmpq+strideq*2], m5
mova [tmpq+stride3q ], m7
lea dstq, [dstq+strideq*8]
%endif ; %1==/!=8
%endif ; %2==/!=v
%elif %1 == 6
; flat6 filter
paddw m3, P1, P0 ; p1+p0
paddw m3, P2 ; p2+p1+p0
paddw m6, P2, Q0 ; p2+q0
paddw m3, m3 ; 2*(p2+p1+p0)
paddw m3, m6 ; p2+2*(p2+p1+p0)+q0
pmulhrsw m2, m3, [PIC_sym(pw_4096)]
psubw m2, P1
pand m2, m4
paddw m3, Q0 ; p2+2*(p2+p1+p0+q0)
paddw m6, P2, P2 ; 2*p2
paddw m3, Q1 ; p2+2*(p2+p1+p0+q0)+q1
psubw m3, m6 ; p2+2*(p1+p0+q0)+q1
pmulhrsw m5, m3, [PIC_sym(pw_4096)]
psubw m5, P0
pand m5, m4
paddw m3, Q1 ; p2+2*(p1+p0+q0+q1)
paddw m6, P2, P1 ; p2+p1
paddw m3, Q2 ; p2+2*(p1+p0+q0+q1)+q2
psubw m3, m6 ; p1+2*(p0+q0+q1)+q2
pmulhrsw m6, m3, [PIC_sym(pw_4096)]
psubw m6, Q0
pand m6, m4
psubw m3, P1 ; 2*(p0+q0+q1)+q2
%if ARCH_X86_64
paddw Q2, Q2 ; q2*2
%else
mova m0, Q2
paddw m0, m0
%endif
psubw m3, P0 ; p0+2*(q0+q1)+q2
%if ARCH_X86_64
paddw m3, Q2 ; p0+q*(q0+q1+q2)+q2
%else
paddw m3, m0
%endif
pmulhrsw m3, [PIC_sym(pw_4096)]
psubw m3, Q1
pand m3, m4
paddw m2, P1
paddw m5, P0
paddw m6, Q0
paddw m3, Q1
%ifidn %2, v
mova [dstq+mstrideq*2], m2 ; p1
mova [dstq+mstrideq*1], m5 ; p0
mova [dstq+strideq*0], m6 ; q0
mova [dstq+strideq*1], m3 ; q1
%else ; %2 != v
TRANSPOSE_8x4_AND_WRITE_4x8 m2, m5, m6, m3, m0
%endif ; %2==/!=v
%else ; %1 == 4
%if ARCH_X86_64
%ifidn %2, v
mova [dstq+mstrideq*2], P1 ; p1
mova [dstq+mstrideq*1], P0 ; p0
mova [dstq+strideq*0], Q0 ; q0
mova [dstq+strideq*1], Q1 ; q1
%else ; %2 != v
TRANSPOSE_8x4_AND_WRITE_4x8 P1, P0, Q0, Q1, m0
%endif ; %2==/!=v
%else ; x86-32
%ifidn %2, v
mova [dstq+mstrideq*2], m3
mova [dstq+mstrideq*1], m5
mova [dstq+strideq*0], m6
mova [dstq+strideq*1], m7
%else ; %2 != v
TRANSPOSE_8x4_AND_WRITE_4x8 m3, m5, m6, m7, m0
%endif ; %2==/!=v
%endif ; x86-32/64
%endif ; %1
%undef P3
%undef P2
%undef P1
%undef P0
%undef Q0
%undef Q1
%undef Q2
%undef Q3
%endmacro
INIT_XMM ssse3
; stack layout:
; r0 - flat8 backup inside flat16 code
%if ARCH_X86_64
cglobal lpf_v_sb_y_16bpc, 6, 12, 16, -16 * 1, \
dst, stride, mask, l, l_stride, lut, \
w, stride3, mstride, tmp, mask_bits, bdmul
mov r6d, r7m
sar r6d, 7
and r6d, 16 ; 0 for 10bpc, 16 for 12bpc
lea bdmulq, [pw_4]
add bdmulq, r6
mov wd, wm
shl l_strideq, 2
sub lq, l_strideq
%else
; stack layout [32bit only]:
; r1-4 - p2-q0 post-filter16
; r5 - p3
; r6 - q3 post-filter16
; r7 - GPRs [mask_bitsm, mstridem]
; r8 - m12/pb_mask
; r9 - bdmulq
cglobal lpf_v_sb_y_16bpc, 4, 7, 8, -16 * (10 + extra_stack), \
dst, stride, mask, mstride, pic_reg, stride3, tmp
RELOC_ARGS v, 10*16
%if STACK_ALIGNMENT >= 16
mov r5d, r7m
%endif
sar r5d, 7
and r5d, 16 ; 0 for 10bpc, 16 for 12bpc
LEA pic_regq, PIC_base
%define pic_regm dword [esp+7*16+2*gprsize]
mov pic_regm, pic_regq
mova m0, [PIC_sym(pw_4)+r5]
%define bdmulq esp+9*16
mova [bdmulq], m0
shl dword lstridem, 2
sub r3, dword lstridem
mov dword lm, r3
%endif
mov mstrideq, strideq
neg mstrideq
lea stride3q, [strideq*3]
%if ARCH_X86_64
mov mask_bitsd, 0x3
mova m12, [pb_mask]
%else
%define mstridem dword [esp+7*16+1*gprsize]
mov mstridem, mstrideq
%define mask_bitsm dword [esp+7*16+0*gprsize]
mov mask_bitsm, 0x3
mova m0, [PIC_sym(pb_mask)]
%define m12 [esp+8*16]
mova m12, m0
%endif
.loop:
%if ARCH_X86_64
test [maskq+8], mask_bitsd ; vmask[2]
%else
mov r6d, mask_bitsm
test [maskq+8], r6d
%endif
jz .no_flat16
FILTER 16, v
jmp .end
.no_flat16:
%if ARCH_X86_64
test [maskq+4], mask_bitsd ; vmask[1]
%else
test [maskq+4], r6d
%endif
jz .no_flat
FILTER 8, v
jmp .end
.no_flat:
%if ARCH_X86_64
test [maskq+0], mask_bitsd ; vmask[0]
%else
test [maskq+0], r6d
%endif
jz .end
FILTER 4, v
.end:
%if ARCH_X86_64
pslld m12, 2
add lq, 8
%else
mova m0, m12
pslld m0, 2
mova m12, m0
add dword lm, 8
%endif
add dstq, 16
%if ARCH_X86_64
shl mask_bitsd, 2
sub wd, 2
%else
shl mask_bitsm, 2
sub dword wm, 2
%endif
jg .loop
%undef mask_bitsm
%undef bdmulq
UNRELOC_ARGS
RET
INIT_XMM ssse3
; stack layout:
; r0 - flat8 backup inside flat16
; r1-4 - p2-q0 post-filter16 backup
; r5 - q3 post-filter16 backup
; r6 - p3
; r7-10 - p7-4
; r11-14 - q4-7
%if ARCH_X86_64
cglobal lpf_h_sb_y_16bpc, 6, 11, 16, -16 * 15, \
dst, stride, mask, l, l_stride, lut, \
h, stride3, tmp, mask_bits, bdmul
mov r6d, r7m
sar r6d, 7
and r6d, 16 ; 0 for 10bpc, 16 for 12bpc
lea bdmulq, [pw_4]
add bdmulq, r6
mov hd, hm
shl l_strideq, 2
%else
; stack layout [32bit only]:
; r15 - GPRs [mask_bitsm]
; r16 - m12/pb_mask
; r17 - bdmulq
; r18-24 - p2-q3
cglobal lpf_h_sb_y_16bpc, 4, 7, 8, -16 * (25 + extra_stack), \
dst, stride, mask, l, pic_reg, stride3, tmp
RELOC_ARGS h, 25*16
%if STACK_ALIGNMENT >= 16
mov r5d, r7m
%endif
sar r5d, 7
and r5d, 16 ; 0 for 10bpc, 16 for 12bpc
LEA pic_regq, PIC_base
mova m0, [PIC_sym(pw_4)+r5]
%define bdmulq esp+17*16
mova [bdmulq], m0
shl dword lstridem, 2
%endif
sub lq, 4
lea stride3q, [strideq*3]
%if ARCH_X86_64
mov mask_bitsd, 0x3
mova m12, [pb_mask]
%else
%define mask_bitsm dword [esp+15*16+0*gprsize]
mov mask_bitsm, 0x3
mova m0, [PIC_sym(pb_mask)]
%define m12 [esp+16*16]
mova m12, m0
%endif
.loop:
%if ARCH_X86_64
test [maskq+8], mask_bitsd ; vmask[2]
%else
mov r6d, mask_bitsm
test [maskq+8], r6d
%endif
jz .no_flat16
FILTER 16, h
jmp .end
.no_flat16:
%if ARCH_X86_64
test [maskq+4], mask_bitsd ; vmask[1]
%else
test [maskq+4], r6d
%endif
jz .no_flat
FILTER 8, h
jmp .end
.no_flat:
%if ARCH_X86_64
test [maskq+0], mask_bitsd ; vmask[0]
%else
test [maskq+0], r6d
%endif
jz .no_filter
FILTER 4, h
jmp .end
.no_filter:
lea dstq, [dstq+strideq*8]
.end:
%if ARCH_X86_64
pslld m12, 2
lea lq, [lq+l_strideq*2]
shl mask_bitsd, 2
sub hd, 2
%else
mova m0, m12
pslld m0, 2
mova m12, m0
add lq, dword lstridem
add lq, dword lstridem
shl mask_bitsm, 2
sub dword hm, 2
%endif
jg .loop
%undef mask_bitsm
%undef bdmulq
UNRELOC_ARGS
RET
INIT_XMM ssse3
%if ARCH_X86_64
cglobal lpf_v_sb_uv_16bpc, 6, 12, 16, \
dst, stride, mask, l, l_stride, lut, \
w, stride3, mstride, tmp, mask_bits, bdmul
mov r6d, r7m
sar r6d, 7
and r6d, 16 ; 0 for 10bpc, 16 for 12bpc
lea bdmulq, [pw_4]
add bdmulq, r6
mov wd, wm
shl l_strideq, 2
sub lq, l_strideq
%else
; stack layout [32bit only]:
; r0 - GPRs [mask_bitsm, mstridem]
; r1 - m12/pb_mask
; r2 - bdmulq
cglobal lpf_v_sb_uv_16bpc, 4, 7, 8, -16 * (3 + extra_stack), \
dst, stride, mask, mstride, pic_reg, stride3, tmp
RELOC_ARGS v, 3*16
%if STACK_ALIGNMENT >= 16
mov r5d, r7m
%endif
sar r5d, 7
and r5d, 16 ; 0 for 10bpc, 16 for 12bpc
LEA pic_regq, PIC_base
mova m0, [PIC_sym(pw_4)+r5]
%define bdmulq esp+2*16
mova [bdmulq], m0
shl dword lstridem, 2
sub r3, dword lstridem
mov dword lm, r3
%endif
mov mstrideq, strideq
neg mstrideq
lea stride3q, [strideq*3]
%if ARCH_X86_64
mov mask_bitsd, 0x3
mova m12, [pb_mask]
%else
%define mask_bitsm dword [esp+0*gprsize]
%define mstridem dword [esp+1*gprsize]
mov mask_bitsm, 0x3
mov mstridem, mstrideq
mova m0, [PIC_sym(pb_mask)]
%define m12 [esp+1*16]
mova m12, m0
%endif
.loop:
%if ARCH_X86_64
test [maskq+4], mask_bitsd ; vmask[1]
%else
mov r6d, mask_bitsm
test [maskq+4], r6d
%endif
jz .no_flat
FILTER 6, v
jmp .end
.no_flat:
%if ARCH_X86_64
test [maskq+0], mask_bitsd ; vmask[0]
%else
test [maskq+0], r6d
%endif
jz .end
FILTER 4, v
.end:
%if ARCH_X86_64
pslld m12, 2
add lq, 8
%else
mova m0, m12
pslld m0, 2
mova m12, m0
add dword lm, 8
%endif
add dstq, 16
%if ARCH_X86_64
shl mask_bitsd, 2
sub wd, 2
%else
shl mask_bitsm, 2
sub dword wm, 2
%endif
jg .loop
%undef mask_bitsm
%undef bdmulq
UNRELOC_ARGS
RET
INIT_XMM ssse3
%if ARCH_X86_64
cglobal lpf_h_sb_uv_16bpc, 6, 11, 16, \
dst, stride, mask, l, l_stride, lut, \
h, stride3, tmp, mask_bits, bdmul
mov r6d, r7m
sar r6d, 7
and r6d, 16 ; 0 for 10bpc, 16 for 12bpc
lea bdmulq, [pw_4]
add bdmulq, r6
mov hd, hm
shl l_strideq, 2
%else
; stack layout [32bit only]:
; r0 - GPRs [mask_bitsm]
; r1 - m12/pb_mask
; r2 - bdmulq
; r3-8 - p2-q2
cglobal lpf_h_sb_uv_16bpc, 4, 7, 8, -16 * (9 + extra_stack), \
dst, stride, mask, l, pic_reg, stride3, tmp
RELOC_ARGS h, 9*16
%if STACK_ALIGNMENT >= 16
mov r5d, r7m
%endif
sar r5d, 7
and r5d, 16 ; 0 for 10bpc, 16 for 12bpc
LEA pic_regq, PIC_base
mova m0, [PIC_sym(pw_4)+r5]
%define bdmulq esp+2*16
mova [bdmulq], m0
shl dword lstridem, 2
%endif
sub lq, 4
lea stride3q, [strideq*3]
%if ARCH_X86_64
mov mask_bitsd, 0x3
mova m12, [pb_mask]
%else
%define mask_bitsm dword [esp+0*gprsize]
mov mask_bitsm, 0x3
mova m0, [PIC_sym(pb_mask)]
%define m12 [esp+1*16]
mova m12, m0
%endif
.loop:
%if ARCH_X86_64
test [maskq+4], mask_bitsd ; vmask[1]
%else
mov r6d, mask_bitsm
test [maskq+4], r6d
%endif
jz .no_flat
FILTER 6, h
jmp .end
.no_flat:
%if ARCH_X86_64
test [maskq+0], mask_bitsd ; vmask[0]
%else
test [maskq+0], r6d
%endif
jz .no_filter
FILTER 4, h
jmp .end
.no_filter:
lea dstq, [dstq+strideq*8]
.end:
%if ARCH_X86_64
pslld m12, 2
lea lq, [lq+l_strideq*2]
shl mask_bitsd, 2
sub hd, 2
%else
mova m0, m12
pslld m0, 2
mova m12, m0
add lq, dword lstridem
add lq, dword lstridem
shl mask_bitsm, 2
sub dword hm, 2
%endif
jg .loop
%undef mask_bitsm
%undef bdmulq
UNRELOC_ARGS
RET
| videolan/dav1d | src/x86/loopfilter16_sse.asm | Assembly | bsd-2-clause | 48,703 |
NROF_DEFINED_EXCS: equ 21
extern panic
extern printk
extern mapIdtEntry
extern lapicBase
extern tssSetIST
extern idtSetIST
extern idtSetDPL
extern excPF
extern kthreadExit
extern excExit
global initExceptions:function
global undefinedInterrupt:function
global dummyInterrupt:function
SECTION .text
initExceptions:
push rbx
push r12
xor ebx, ebx
mov r12, excList
.start:
cmp ebx, NROF_DEFINED_EXCS
jae .end
xor edx, edx
mov esi, ebx
mov rdi, [r12]
call mapIdtEntry
add r12, 8
inc ebx
jmp .start
.end:
mov rdi, 3
mov esi, 1
call idtSetDPL
pop r12
pop rbx
ret
excBaseErrorCode:
xchg bx, bx
push rax ;rsp+8 = irq num, +16 = error
mov rax, [rsp + 8]
xchg [rsp + 16], rax ;error becomes irq num
xchg [rsp], rax ;store error in temp, load old rax
mov [rsp + 8], rax ;store old rax
pop rax ;load error in rax
jmp __excBase
excBase:
xchg bx, bx
push rax
xor eax, eax
__excBase: ;error code in rax
sub rsp, 0x40
mov [rsp + 0x38], rcx
mov [rsp + 0x30], rdx
mov [rsp + 0x28], rdi
mov [rsp + 0x20], rsi
mov [rsp + 0x18], r8
mov [rsp + 0x10], r9
mov [rsp + 0x08], r10
mov [rsp], r11
test [rsp + 0x54], dword 0x80000000
jnz .noswapgs
swapgs
or [rsp + 0x68], dword 3
.noswapgs:
mov r10, [rsp + 0x48]
mov rdi, excMessageBase
mov rsi, [excMsgList + r10 * 8]
mov rdx, rax
mov rcx, [rsp + 0x50]
call printk
cmp [rsp + 0x48], dword 3
je .return
;sti
xchg bx, bx
mov rax, [gs:8]
test rax, rax
jz .kThread
cmp [rax + 0x20], dword 0
jne .userThread
.kThread:
;call kthreadExit
call panic
jmp .halt
.userThread:
mov rdi, [rsp + 0x48]
mov rsi, [rsp + 0x50]
call excExit
.halt:
cli
hlt
jmp .halt
.return:
test [rsp + 0x54], dword 0x80000000
jnz .noswapgs2
swapgs
.noswapgs2:
mov rax, [rsp + 0x40]
mov rcx, [rsp + 0x38]
mov rdx, [rsp + 0x30]
mov rdi, [rsp + 0x28]
mov rsi, [rsp + 0x20]
mov r8, [rsp + 0x18]
mov r9, [rsp + 0x10]
mov r10, [rsp + 0x08]
mov r11, [rsp]
add rsp, 0x50
iretq
excDE:
push 0
jmp excBase
excDB:
push 1
jmp excBase
excNMI:
iretq
excBP:
push 3
jmp excBase
excOF:
push 4
jmp excBase
excBR:
push 5
jmp excBase
excUD:
push 6
jmp excBase
excNM:
;push 7
;jmp excBase
;Enable SSE for this thread
or [rsp + 0x20], dword 3
push rax
swapgs
clts
mov rax, [gs:8]
cmp [rax + 0x28], dword 0
jne .rstor
;initialize sse regs
mov [rax + 0x28], dword 1 ;set thread->floatsUsed
ldmxcsr [defaultMxcsr]
movaps xmm0, [sseZero]
movaps xmm1, [sseZero]
movaps xmm2, [sseZero]
movaps xmm3, [sseZero]
movaps xmm4, [sseZero]
movaps xmm5, [sseZero]
movaps xmm6, [sseZero]
movaps xmm7, [sseZero]
movaps xmm8, [sseZero]
movaps xmm9, [sseZero]
movaps xmm10, [sseZero]
movaps xmm11, [sseZero]
movaps xmm12, [sseZero]
movaps xmm13, [sseZero]
movaps xmm14, [sseZero]
movaps xmm15, [sseZero]
jmp .out
.rstor:
fxrstor [rax + 0x30]
.out:
swapgs
pop rax
iretq
excDF:
;push 8
;jmp excBaseErrorCode
xchg bx, bx
mov rdi, DFmsg
call panic
excCSO:
push 9
jmp excBase
excTS:
push 10
jmp excBaseErrorCode
excNP:
push 11
jmp excBaseErrorCode
excSS:
push 12
jmp excBaseErrorCode
excGP:
push 13
jmp excBaseErrorCode
excMF:
push 16
jmp excBase
excAC:
push 17
jmp excBaseErrorCode
excMC:
push 18
jmp excBase
excXM:
;iretq
push 19
jmp excBase
excVE:
push 20
jmp excBase
ALIGN 8
undefinedInterrupt:
iretq
ALIGN 8
dummyInterrupt:
push rax
mov rax, [lapicBase]
mov [rax + 0xB0], dword 0
pop rax
iretq
SECTION .rodata
ALIGN 16
sseZero: dq 0
dq 0
defaultMxcsr: dd 0x01100
excMessageBase: db 'CPU exception: %s', 10, 'Error code: %d', 10, 'At: %x', 10, 0
nullStr: db 0
ALIGN 8
excList:
dq excDE
dq excDB
dq excNMI
dq excBP
dq excOF
dq excBR
dq excUD
dq excNM
dq excDF
dq excCSO
dq excTS
dq excNP
dq excSS
dq excGP
dq excPF
dq undefinedInterrupt
dq excMF
dq excAC
dq excMC
dq excXM
dq excVE
excMsgList:
dq DEmsg
dq nullStr
dq DBmsg
dq BPmsg
dq OFmsg
dq BRmsg
dq UDmsg
dq NMmsg
dq DFmsg
dq CSOmsg
dq TSmsg
dq NPmsg
dq SSmsg
dq GPmsg
dq MFmsg
dq ACmsg
dq XMmsg
dq VEmsg
DEmsg: db 'Division error', 0
DBmsg: db 'Debug error', 0
BPmsg: db 'Breakpoint reached', 0
OFmsg: db 'Overflow', 0
BRmsg: db 'BOUND Range exceeded', 0
UDmsg: db 'Invalid opcode detected', 0
NMmsg: db 'Coprocessor not available', 0
DFmsg: db 'Double Fault', 0
CSOmsg: db 'Coprocessor segment overrun', 0
TSmsg: db 'Invalid TSS', 0
NPmsg: db 'Segment not present', 0
SSmsg: db 'Stack fault', 0
GPmsg: db 'General protection fault', 0
MFmsg: db 'Coprocessor error', 0
ACmsg: db 'Alignment check', 0
MCmsg: db 'Machine check', 0
XMmsg: db 'SIMD floating point error', 0
VEmsg: db 'Virtualization exception', 0 | racing19th/MiraiOS | kernel/arch/x86_64/irq/exception.asm | Assembly | mit | 4,759 |
0804869a <plain_res>:
804869a: push ebp
804869b: mov ebp,esp
804869d: sub esp,0x18
80486a0: mov DWORD PTR [ebp-0x18],0x0
80486a7: sub esp,0xc
80486aa: push 0x1
80486ac: call 8048330 <malloc@plt>
80486b1: add esp,0x10
80486b4: mov DWORD PTR [ebp-0x14],eax
80486b7: cmp DWORD PTR [ebp-0x14],0x0
80486bb: jne 80486c4 <plain_res+0x2a>
80486bd: mov DWORD PTR [ebp-0x18],0x1
80486c4: cmp DWORD PTR [ebp-0x18],0x0
80486c8: jne 80486df <plain_res+0x45>
80486ca: call 8048350 <rand@plt>
80486cf: mov DWORD PTR [ebp-0x10],eax
80486d2: cmp DWORD PTR [ebp-0x10],0x0
80486d6: jne 80486df <plain_res+0x45>
80486d8: mov DWORD PTR [ebp-0x18],0x2
80486df: cmp DWORD PTR [ebp-0x18],0x0
80486e3: jne 80486fa <plain_res+0x60>
80486e5: call 8048350 <rand@plt>
80486ea: mov DWORD PTR [ebp-0xc],eax
80486ed: cmp DWORD PTR [ebp-0xc],0x0
80486f1: jne 80486fa <plain_res+0x60>
80486f3: mov DWORD PTR [ebp-0x18],0x3
80486fa: cmp DWORD PTR [ebp-0x14],0x0
80486fe: je 804870e <plain_res+0x74>
8048700: sub esp,0xc
8048703: push DWORD PTR [ebp-0x14]
8048706: call 8048320 <free@plt>
804870b: add esp,0x10
804870e: mov eax,DWORD PTR [ebp-0x18]
8048711: leave
8048712: ret
| Kachalov/goto-report | disasm/plain_res.asm | Assembly | mit | 1,276 |
section .text
%include "context.inc"
global switch_context
switch_context:
;
; params: context_t ESP+4
;
; This function is not reentrant
;xchg bx, bx
cli
; save parameters in static space as we might switch esp
mov edi, iret_data
mov esi, [esp + 4]
mov ecx, context_t_size
rep movsb
; switch pagedir
mov eax, [iret_data + context_t.i_cr3]
mov cr3, eax
; Segment regs
mov eax, [iret_data + context_t.i_ds]
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
; iret stack layout
mov eax, [iret_data + context_t.i_cs]
and eax, 0x03
cmp eax, 0x03
jne .switch_stack
; if we are switching into ring3, we need to push esp and ss
push dword [iret_data + context_t.i_ss]
push dword [iret_data + context_t.i_esp]
jmp .continue_push
.switch_stack:
; Switch stack
mov eax, [iret_data + context_t.i_ds]
mov ss, eax
mov esp, [iret_data + context_t.i_esp]
.continue_push:
; push the rest of iret regs
push dword [iret_data + context_t.i_eflags]
push dword [iret_data + context_t.i_cs]
push dword [iret_data + context_t.i_eip]
; set general-purpose registers
mov edi, [iret_data + context_t.i_edi]
mov esi, [iret_data + context_t.i_esi]
mov edx, [iret_data + context_t.i_edx]
mov ecx, [iret_data + context_t.i_ecx]
mov ebx, [iret_data + context_t.i_ebx]
mov eax, [iret_data + context_t.i_eax]
mov ebp, [iret_data + context_t.i_ebp]
; perform iret
iret
section .bss
iret_data: resb context_t_size
| degaart/rastapopoulos | kernel/context.asm | Assembly | mit | 1,711 |
;=================================================================
; Memory and Constants Setup
;=================================================================
.equ STACK, 040h ; Bottom of the stack
.equ CNTH, 001h ; Delay high byte count
.equ CNTL, 040h ; Delay low byte count
; LED Image Bufer
.equ panel00, 4000h ; First byte containnig LED panel0 data
.equ panel01, 4001h ; First byte containnig LED panel0 data
.equ panel02, 4002h ; First byte containnig LED panel0 data
.equ panel03, 4003h ; First byte containnig LED panel0 data
.equ panel04, 4004h ; First byte containnig LED panel0 data
.equ panel05, 4005h ; First byte containnig LED panel0 data
.equ panel06, 4006h ; First byte containnig LED panel0 data
.equ panel07, 4007h ; First byte containnig LED panel0 data
.equ panel10, 4008h ; First byte contianing LED panel1 data
.equ panel11, 4009h ; First byte contianing LED panel1 data
.equ panel12, 400Ah ; First byte contianing LED panel1 data
.equ panel13, 400Bh ; First byte contianing LED panel1 data
.equ panel14, 400Ch ; First byte contianing LED panel1 data
.equ panel15, 400Dh ; First byte contianing LED panel1 data
.equ panel16, 400Eh ; First byte contianing LED panel1 data
.equ panel17, 400Fh ; First byte contianing LED panel1 data
.equ panel20, 4010h ; First byte containing LED panel2 data
.equ panel21, 4011h ; First byte containing LED panel2 data
.equ panel22, 4012h ; First byte containing LED panel2 data
.equ panel23, 4013h ; First byte containing LED panel2 data
.equ panel24, 4014h ; First byte containing LED panel2 data
.equ panel25, 4015h ; First byte containing LED panel2 data
.equ panel26, 4016h ; First byte containing LED panel2 data
.equ panel27, 4017h ; First byte containing LED panel2 data
.equ panel30, 4018h ; First byte containing LED panel3 data
.equ panel31, 4019h ; First byte containing LED panel3 data
.equ panel32, 401Ah ; First byte containing LED panel3 data
.equ panel33, 401Bh ; First byte containing LED panel3 data
.equ panel34, 401Ch ; First byte containing LED panel3 data
.equ panel35, 401Dh ; First byte containing LED panel3 data
.equ panel36, 401Eh ; First byte containing LED panel3 data
.equ panel37, 401Fh ; First byte containing LED panel3 data
.equ PTNADR, 7000h ; Location of the LED patternin memory
;=================================================================
; Main program loop
;=================================================================
.org 000h ; Power up and reset vector
ljmp start
.org 100h
start:
ljmp init ; Initialize program
main:
loop:
lcall updLED
lcall delay
sjmp loop
;=================================================================
; Subroutine init
; This routine initializes the program
;=================================================================
init:
mov sp, #STACK ; Update stack pointer
; Setup Interrupts for Sintab
; Setup Serial Communication
mov tmod, #020h ; set timer 1/2 for auto reload - mode 2
mov tcon, #041h ; run counter 1/0 and set edge trig ints
mov scon, #50h ; set serial control reg for 8 bit data and mode 1
mov th1, #0FDh ; set 9600 baud with xtal=11.059mhz
clr P1.2
lcall initMAX ; Initialize the MAX chips
ljmp main ; Start Main Program
;=================================================================
; Subroutine initMAX
; This routine initializes the MAX7219 chips
;=================================================================
initMAX:
mov R0, #00Ch ; Shutdown register
mov R1, #001h ; No shutdown
lcall sndMAX
mov R0, #00Ch ; Shutdown register
mov R1, #001h ; No shutdown
lcall sndMAX
mov R0, #00Ch ; Shutdown register
mov R1, #001h ; No shutdown
lcall sndMAX
mov R0, #00Ch ; Shutdown register
mov R1, #001h ; No shutdown
lcall sndMAX
lcall latchMAX
mov R0, #00Bh ; Scan mode register
mov R1, #007h ; Scan mode all
lcall sndMAX
mov R0, #00Bh ; Scan mode register
mov R1, #007h ; Scan mode all
lcall sndMAX
mov R0, #00Bh ; Scan mode register
mov R1, #007h ; Scan mode all
lcall sndMAX
mov R0, #00Bh ; Scan mode register
mov R1, #007h ; Scan mode all
lcall sndMAX
lcall latchMAX
mov R0, #009h ; Decode mode register
mov R1, #00h ; No decode mode
lcall sndMAX
mov R0, #009h ; Decode mode register
mov R1, #00h ; No decode mode
lcall sndMAX
mov R0, #009h ; Decode mode register
mov R1, #00h ; No decode mode
lcall sndMAX
mov R0, #009h ; Decode mode register
mov R1, #00h ; No decode mode
lcall sndMAX
lcall latchMAX
;mov R0, #00Fh ; Display test register
;mov R1, #000h ; No display test
;lcall sndMAX
;lcall latchMAX
mov R0, #00Ah ; Intensity register
mov R1, #00Fh ; Max intensity
lcall sndMAX
mov R0, #00Ah ; Intensity register
mov R1, #00Fh ; Max intensity
lcall sndMAX
mov R0, #00Ah ; Intensity register
mov R1, #00Fh ; Max intensity
lcall sndMAX
mov R0, #00Ah ; Intensity register
mov R1, #00Fh ; Max intensity
lcall sndMAX
lcall latchMAX
ret
;=================================================================
; Subroutine updLED
; Updates the LEDs attached to the MAX7219 serial interface
;=================================================================
updLED:
mov dptr, #panel00
movx a, @dptr
mov R1, a
mov R0, #001h
lcall sndmax
mov dptr, #panel10
movx a, @dptr
mov R1, a
mov R0, #001h
lcall sndmax
mov dptr, #panel20
movx a, @dptr
mov R1, a
mov R0, #001h
lcall sndmax
mov dptr, #panel30
movx a, @dptr
mov R1, a
mov R0, #001h
lcall sndmax
lcall latchMAX
mov dptr, #panel01
movx a, @dptr
mov R1, a
mov R0, #002h
lcall sndmax
mov dptr, #panel11
movx a, @dptr
mov R1, a
mov R0, #002h
lcall sndmax
mov dptr, #panel21
movx a, @dptr
mov R1, a
mov R0, #002h
lcall sndmax
mov dptr, #panel31
movx a, @dptr
mov R1, a
mov R0, #002h
lcall sndmax
lcall latchMAX
mov dptr, #panel02
movx a, @dptr
mov R1, a
mov R0, #003h
lcall sndmax
mov dptr, #panel12
movx a, @dptr
mov R1, a
mov R0, #003h
lcall sndmax
mov dptr, #panel22
movx a, @dptr
mov R1, a
mov R0, #003h
lcall sndmax
mov dptr, #panel32
movx a, @dptr
mov R1, a
mov R0, #003h
lcall sndmax
lcall latchMAX
mov dptr, #panel03
movx a, @dptr
mov R1, a
mov R0, #004h
lcall sndmax
mov dptr, #panel13
movx a, @dptr
mov R1, a
mov R0, #004h
lcall sndmax
mov dptr, #panel23
movx a, @dptr
mov R1, a
mov R0, #004h
lcall sndmax
mov dptr, #panel33
movx a, @dptr
mov R1, a
mov R0, #004h
lcall sndmax
lcall latchMAX
mov dptr, #panel04
movx a, @dptr
mov R1, a
mov R0, #005h
lcall sndmax
mov dptr, #panel14
movx a, @dptr
mov R1, a
mov R0, #005h
lcall sndmax
mov dptr, #panel24
movx a, @dptr
mov R1, a
mov R0, #005h
lcall sndmax
mov dptr, #panel34
movx a, @dptr
mov R1, a
mov R0, #005h
lcall sndmax
lcall latchMAX
mov dptr, #panel05
movx a, @dptr
mov R1, a
mov R0, #006h
lcall sndmax
mov dptr, #panel15
movx a, @dptr
mov R1, a
mov R0, #006h
lcall sndmax
mov dptr, #panel25
movx a, @dptr
mov R1, a
mov R0, #006h
lcall sndmax
mov dptr, #panel35
movx a, @dptr
mov R1, a
mov R0, #006h
lcall sndmax
lcall latchMAX
mov dptr, #panel06
movx a, @dptr
mov R1, a
mov R0, #007h
lcall sndmax
mov dptr, #panel16
movx a, @dptr
mov R1, a
mov R0, #007h
lcall sndmax
mov dptr, #panel26
movx a, @dptr
mov R1, a
mov R0, #007h
lcall sndmax
mov dptr, #panel36
movx a, @dptr
mov R1, a
mov R0, #007h
lcall sndmax
lcall latchMAX
mov dptr, #panel07
movx a, @dptr
mov R1, a
mov R0, #008h
lcall sndmax
mov dptr, #panel17
movx a, @dptr
mov R1, a
mov R0, #008h
lcall sndmax
mov dptr, #panel27
movx a, @dptr
mov R1, a
mov R0, #008h
lcall sndmax
mov dptr, #panel37
movx a, @dptr
mov R1, a
mov R0, #008h
lcall sndmax
lcall latchMAX
ret
;=================================================================
; Subroutine putbyte
; sends a byte out to the MAX7219 serial interface. Place byte
; to send in R0.
;=================================================================
putByte:
mov a, R0 ; Move byte to acc
mov R1, #008h ; We send 8 bits per byte
putByteLoop:
clr P1.1 ; Set CLK low
jnb acc.7, putByteLow ; If acc.7 is set, send a high,
; else, send a low out DIn
setb P1.0 ; Set DIn high
sjmp putByteEnd
putByteLow:
clr P1.0 ; Set DIn low
putByteEnd:
setb P1.1 ; Set CLK high
rl a ; Rotate acc to get to lesser bit
djnz R1, putByteLoop ; Loop till we've sent all bits
ret
;=================================================================
; Subroutine sndMAX
; sends a data out to the MAX7219 serial interface. Place Aaddres
; in R0 and data in R1
;=================================================================
sndMAX:
push 001h ; Push R1
lcall putByte ; Send Address
pop 000h ; Pop R1 into R0
lcall putByte ; Send data
ret
;=================================================================
; Subroutine latchMAX
; latches the serial data into the MAX7219
;=================================================================
latchMAX:
clr P1.2 ; Enable MAX
setb P1.2 ; Latch MAX
;clr P1.2
ret
;=================================================================
; Subroutine updPTN
; Updates the pattern stored in memory
;=================================================================
updPTN:
mov dptr, #PTNADR ; Get location of pattern
movx a, @dptr ; Copy the first value
mov R0, a ; Place first value into R0
mov R2, #007h ; Loop 7 times
updPTNLoop:
inc dptr ; Move DPTR to next address
movx a, @dptr ; Copy to be copied over
mov R1, a ; Save in R1
mov a, R0 ; Set up old value
movx @dptr, a ; Copy old value to new potion
mov R0, 001h ; Move new value to old value
djnz R2, updPTNLoop ; Loop till reach end
mov dptr, #PTNADR ; Get location of pattern
mov a, R0 ; Set up old value
movx @dptr, a ; Copy old value to new potion
ret
;=================================================================
; Subroutine delay
; This routine delays for some time
;=================================================================
delay:
; load R0 and R1 with 255
mov R0, #CNTH
mov R1, #CNTL
loop_internal:
djnz R1, loop_internal ; decrement R1
mov R1, #CNTL ; reload R1 in case we need to loop again.
djnz R0, loop_internal; decrement R0
ret
;===============================================================
; Subroutine sndchr
; This routine takes the chr in the R0 and sends it out the
; serial port.
;===============================================================
sndchr:
clr scon.1 ; clear the tx buffer full flag.
mov sbuf,R0 ; put chr in sbuf
txloop:
jnb scon.1, txloop ; wait till chr is sent
ret
;===============================================================
; Subroutine getchr
; This routine reads in a chr from the serial port and saves it
; in the R0.
;===============================================================
getchr:
jnb ri, getchr ; wait till character received
;mov a, sbuf ; get character
;anl a, #7Fh ; mask off 8th bit
;mov R0, a ; Move a into R0 for return
mov R0, sbuf
clr ri ; clear serial status bit
ret
;===============================================================
; Subroutine crlf
; crlf sends a carriage return line feed out the serial port
;===============================================================
crlf:
mov R0, #0Ah ; print lf
lcall sndchr
cret:
mov R0, #0Dh ; print cr
lcall sndchr
ret
;===============================================================
; Subroutine prthex
; This routine takes the contents of the R0 and prints it out
; as a 2 digit ascii hex number.
;===============================================================
prthex:
mov a, R0
push acc
lcall binasc ; convert acc to ascii
mov R0, a
lcall sndchr ; print first ascii hex digit
mov R0, 002h ; get second ascii hex digit
lcall sndchr ; print it
pop acc
ret
;===============================================================
; Subroutine binasc
; binasc takes the contents of the accumulator and converts it
; into two ascii hex numbers. the result is returned in the
; accumulator and r2.
;===============================================================
binasc:
mov r2, a ; save in r2
anl a, #0fh ; convert least sig digit.
add a, #0f6h ; adjust it
jnc noadj1 ; if a-f then readjust
add a, #07h
noadj1:
add a, #3ah ; make ascii
xch a, r2 ; put result in reg 2
swap a ; convert most sig digit
anl a, #0fh ; look at least sig half of acc
add a, #0f6h ; adjust it
jnc noadj2 ; if a-f then re-adjust
add a, #07h
noadj2:
add a, #3ah ; make ascii
ret
;=================================================================
; This routine serves as a lookup table for the sin wave values
; Place the sin tab address in ACC, then call
; this function to have the val_to_bar_low value placed in the ACC
;=================================================================
val_to_bar_low:
inc a
movc a, @a+pc
ret
.db 00000001b ; 0
.db 00000011b ; 1
.db 00000111b ; 2
.db 00001111b ; 3
.db 00011111b ; 4
.db 00111111b ; 5
.db 01111111b ; 6
.db 11111111b ; 7
.db 11111111b ; 8
.db 11111111b ; 9
.db 11111111b ; 10
.db 11111111b ; 11
.db 11111111b ; 12
.db 11111111b ; 13
.db 11111111b ; 14
.db 11111111b ; 15
;=================================================================
; This routine serves as a lookup table for the sin wave values
; Place the sin tab address in ACC, then call
; this function to have the val_to_bar_high value placed in the ACC
;=================================================================
val_to_bar_high:
inc a
movc a, @a+pc
ret
.db 00000000b ; 0
.db 00000000b ; 1
.db 00000000b ; 2
.db 00000000b ; 3
.db 00000000b ; 4
.db 00000000b ; 5
.db 00000000b ; 6
.db 00000000b ; 7
.db 00000001b ; 8
.db 00000011b ; 9
.db 00000111b ; 10
.db 00001111b ; 11
.db 00011111b ; 12
.db 00111111b ; 13
.db 01111111b ; 14
.db 11111111b ; 15
.end
| KoolJBlack/6.115-FinalProject | ZZZ/fix.asm | Assembly | mit | 14,093 |
SECTION "Tiles bank 0", VRAM[$8000],BANK[0]
v0Tiles0::
vPlayerTiles::
; dtile 4 * 3 Overlap
dtile 1
vFileSelectCornerTile::
dtile 1
vFileSelectConsoleTiles::
dtile 9
dtile 2 ; Last two vPlayerTiles
dtile $13
vDMGFontTiles::
dtile $3C
dtile $24
v0Tiles1::
dtile $80
v0Tiles2::
dtile 1
vBattleTextboxBorderTiles::
dtile 3
vPicTiles::
vPicTilesRow0::
dtile 3
vPicTilesRow1::
dtile 3
vPicTilesRow2::
dtile 3
vPicTilesRow3::
dtile 3
vTextboxBorderTiles::
dtile 3
dtile 13
vFontTiles::
dtile $3B
dtile $24
SECTION "Tiles bank 1", VRAM[$8000],BANK[1]
v1Tiles0::
vPlayerWalkingTiles::
dtile 4 * 3
dtile 112
vEmoteTiles::
dtile 4
v1Tiles1::
dtile $80
v1Tiles2::
dtile $20
vAlternateFontTiles::
dtile $3C
dtile $24
SECTION "Tile Maps", VRAM[$9800],BANK[0]
vTileMap0::
ds $400
vTileMap1::
ds $100
vTextboxTileMap::
ds 5
vTextboxName::
ds 27
ds 1
vTextboxPicRow0::
ds 3
ds 1
; No text line here
ds 27
ds 1
vTextboxPicRow1::
ds 3
ds 1
vTextboxLine0::
ds 27
ds 1
vTextboxPicRow2::
ds 3
ds 1
vTextboxLine1::
ds 27
ds 1
vTextboxPicRow3::
ds 3
ds 1
vTextboxLine2::
ds 27
vTextboxBottomBorder::
ds VRAM_ROW_SIZE
vFixedMap::
ds SCREEN_HEIGHT * VRAM_ROW_SIZE
SECTION "Attribute Maps", VRAM[$9800],BANK[1]
vAttrMap0::
ds $400
vAttrMap1::
ds $400
| ISSOtm/Aevilia-GB | main/vram.asm | Assembly | apache-2.0 | 1,485 |
org $00D65E
autoclean JSL hijack
NOP #6
freecode
hijack:
LDA.B #$01 ; \ Play sound effect
STA.W $1DFA ; / Jump IIRC
LDA $73
CMP #$00
BNE flip
LDA.W $00D2BD,X ; \ Oh look, the X speed determines the "gravity"
STA $7D ; /
RTL
freecode
flip:
PHK
PEA.w .jslrtsreturn-1
PEA.w $0084CF-1
JML $00FE4A
.jslrtsreturn
LDA #$94
STA $7D
LDA $76
CMP #$00
BEQ left
BRA right
left:
LDA #$05
STA $7B
RTL
right:
LDA #$FA
STA $7B | snuggles08/snuggles08.github.io | test/backflip.asm | Assembly | mit | 422 |
;******************************************************************************
;* x86 optimized Format Conversion Utils
;* Copyright (c) 2008 Loren Merritt
;*
;* This file is part of FFmpeg.
;*
;* FFmpeg is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* FFmpeg is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with FFmpeg; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
%include "libavutil/x86/x86util.asm"
SECTION_TEXT
%macro CVTPS2PI 2
%if cpuflag(sse)
cvtps2pi %1, %2
%elif cpuflag(3dnow)
pf2id %1, %2
%endif
%endmacro
;------------------------------------------------------------------------------
; void ff_int32_to_float_fmul_scalar(float *dst, const int32_t *src, float mul,
; int len);
;------------------------------------------------------------------------------
%macro INT32_TO_FLOAT_FMUL_SCALAR 1
%if UNIX64
cglobal int32_to_float_fmul_scalar, 3, 3, %1, dst, src, len
%else
cglobal int32_to_float_fmul_scalar, 4, 4, %1, dst, src, mul, len
%endif
%if WIN64
SWAP 0, 2
%elif ARCH_X86_32
movss m0, mulm
%endif
SPLATD m0
shl lenq, 2
add srcq, lenq
add dstq, lenq
neg lenq
.loop:
%if cpuflag(sse2)
cvtdq2ps m1, [srcq+lenq ]
cvtdq2ps m2, [srcq+lenq+16]
%else
cvtpi2ps m1, [srcq+lenq ]
cvtpi2ps m3, [srcq+lenq+ 8]
cvtpi2ps m2, [srcq+lenq+16]
cvtpi2ps m4, [srcq+lenq+24]
movlhps m1, m3
movlhps m2, m4
%endif
mulps m1, m0
mulps m2, m0
mova [dstq+lenq ], m1
mova [dstq+lenq+16], m2
add lenq, 32
jl .loop
REP_RET
%endmacro
INIT_XMM sse
INT32_TO_FLOAT_FMUL_SCALAR 5
INIT_XMM sse2
INT32_TO_FLOAT_FMUL_SCALAR 3
;------------------------------------------------------------------------------
; void ff_int32_to_float_fmul_array8(FmtConvertContext *c, float *dst, const int32_t *src,
; const float *mul, int len);
;------------------------------------------------------------------------------
%macro INT32_TO_FLOAT_FMUL_ARRAY8 0
cglobal int32_to_float_fmul_array8, 5, 5, 5, c, dst, src, mul, len
shl lend, 2
add srcq, lenq
add dstq, lenq
neg lenq
.loop:
movss m0, [mulq]
SPLATD m0
%if cpuflag(sse2)
cvtdq2ps m1, [srcq+lenq ]
cvtdq2ps m2, [srcq+lenq+16]
%else
cvtpi2ps m1, [srcq+lenq ]
cvtpi2ps m3, [srcq+lenq+ 8]
cvtpi2ps m2, [srcq+lenq+16]
cvtpi2ps m4, [srcq+lenq+24]
movlhps m1, m3
movlhps m2, m4
%endif
mulps m1, m0
mulps m2, m0
mova [dstq+lenq ], m1
mova [dstq+lenq+16], m2
add mulq, 4
add lenq, 32
jl .loop
REP_RET
%endmacro
INIT_XMM sse
INT32_TO_FLOAT_FMUL_ARRAY8
INIT_XMM sse2
INT32_TO_FLOAT_FMUL_ARRAY8
;------------------------------------------------------------------------------
; void ff_float_to_int16(int16_t *dst, const float *src, long len);
;------------------------------------------------------------------------------
%macro FLOAT_TO_INT16 1
cglobal float_to_int16, 3, 3, %1, dst, src, len
add lenq, lenq
lea srcq, [srcq+2*lenq]
add dstq, lenq
neg lenq
.loop:
%if cpuflag(sse2)
cvtps2dq m0, [srcq+2*lenq ]
cvtps2dq m1, [srcq+2*lenq+16]
packssdw m0, m1
mova [dstq+lenq], m0
%else
CVTPS2PI m0, [srcq+2*lenq ]
CVTPS2PI m1, [srcq+2*lenq+ 8]
CVTPS2PI m2, [srcq+2*lenq+16]
CVTPS2PI m3, [srcq+2*lenq+24]
packssdw m0, m1
packssdw m2, m3
mova [dstq+lenq ], m0
mova [dstq+lenq+8], m2
%endif
add lenq, 16
js .loop
%if mmsize == 8
emms
%endif
REP_RET
%endmacro
INIT_XMM sse2
FLOAT_TO_INT16 2
INIT_MMX sse
FLOAT_TO_INT16 0
INIT_MMX 3dnow
FLOAT_TO_INT16 0
;------------------------------------------------------------------------------
; void ff_float_to_int16_step(int16_t *dst, const float *src, long len, long step);
;------------------------------------------------------------------------------
%macro FLOAT_TO_INT16_STEP 1
cglobal float_to_int16_step, 4, 7, %1, dst, src, len, step, step3, v1, v2
add lenq, lenq
lea srcq, [srcq+2*lenq]
lea step3q, [stepq*3]
neg lenq
.loop:
%if cpuflag(sse2)
cvtps2dq m0, [srcq+2*lenq ]
cvtps2dq m1, [srcq+2*lenq+16]
packssdw m0, m1
movd v1d, m0
psrldq m0, 4
movd v2d, m0
psrldq m0, 4
mov [dstq], v1w
mov [dstq+stepq*4], v2w
shr v1d, 16
shr v2d, 16
mov [dstq+stepq*2], v1w
mov [dstq+step3q*2], v2w
lea dstq, [dstq+stepq*8]
movd v1d, m0
psrldq m0, 4
movd v2d, m0
mov [dstq], v1w
mov [dstq+stepq*4], v2w
shr v1d, 16
shr v2d, 16
mov [dstq+stepq*2], v1w
mov [dstq+step3q*2], v2w
lea dstq, [dstq+stepq*8]
%else
CVTPS2PI m0, [srcq+2*lenq ]
CVTPS2PI m1, [srcq+2*lenq+ 8]
CVTPS2PI m2, [srcq+2*lenq+16]
CVTPS2PI m3, [srcq+2*lenq+24]
packssdw m0, m1
packssdw m2, m3
movd v1d, m0
psrlq m0, 32
movd v2d, m0
mov [dstq], v1w
mov [dstq+stepq*4], v2w
shr v1d, 16
shr v2d, 16
mov [dstq+stepq*2], v1w
mov [dstq+step3q*2], v2w
lea dstq, [dstq+stepq*8]
movd v1d, m2
psrlq m2, 32
movd v2d, m2
mov [dstq], v1w
mov [dstq+stepq*4], v2w
shr v1d, 16
shr v2d, 16
mov [dstq+stepq*2], v1w
mov [dstq+step3q*2], v2w
lea dstq, [dstq+stepq*8]
%endif
add lenq, 16
js .loop
%if mmsize == 8
emms
%endif
REP_RET
%endmacro
INIT_XMM sse2
FLOAT_TO_INT16_STEP 2
INIT_MMX sse
FLOAT_TO_INT16_STEP 0
INIT_MMX 3dnow
FLOAT_TO_INT16_STEP 0
;-------------------------------------------------------------------------------
; void ff_float_to_int16_interleave2(int16_t *dst, const float **src, long len);
;-------------------------------------------------------------------------------
%macro FLOAT_TO_INT16_INTERLEAVE2 0
cglobal float_to_int16_interleave2, 3, 4, 2, dst, src0, src1, len
lea lenq, [4*r2q]
mov src1q, [src0q+gprsize]
mov src0q, [src0q]
add dstq, lenq
add src0q, lenq
add src1q, lenq
neg lenq
.loop:
%if cpuflag(sse2)
cvtps2dq m0, [src0q+lenq]
cvtps2dq m1, [src1q+lenq]
packssdw m0, m1
movhlps m1, m0
punpcklwd m0, m1
mova [dstq+lenq], m0
%else
CVTPS2PI m0, [src0q+lenq ]
CVTPS2PI m1, [src0q+lenq+8]
CVTPS2PI m2, [src1q+lenq ]
CVTPS2PI m3, [src1q+lenq+8]
packssdw m0, m1
packssdw m2, m3
mova m1, m0
punpcklwd m0, m2
punpckhwd m1, m2
mova [dstq+lenq ], m0
mova [dstq+lenq+8], m1
%endif
add lenq, 16
js .loop
%if mmsize == 8
emms
%endif
REP_RET
%endmacro
INIT_MMX 3dnow
FLOAT_TO_INT16_INTERLEAVE2
INIT_MMX sse
FLOAT_TO_INT16_INTERLEAVE2
INIT_XMM sse2
FLOAT_TO_INT16_INTERLEAVE2
;-----------------------------------------------------------------------------
; void ff_float_to_int16_interleave6(int16_t *dst, const float **src, int len)
;-----------------------------------------------------------------------------
%macro FLOAT_TO_INT16_INTERLEAVE6 0
cglobal float_to_int16_interleave6, 2, 8, 0, dst, src, src1, src2, src3, src4, src5, len
%if ARCH_X86_64
mov lend, r2d
%else
%define lend dword r2m
%endif
mov src1q, [srcq+1*gprsize]
mov src2q, [srcq+2*gprsize]
mov src3q, [srcq+3*gprsize]
mov src4q, [srcq+4*gprsize]
mov src5q, [srcq+5*gprsize]
mov srcq, [srcq]
sub src1q, srcq
sub src2q, srcq
sub src3q, srcq
sub src4q, srcq
sub src5q, srcq
.loop:
CVTPS2PI mm0, [srcq]
CVTPS2PI mm1, [srcq+src1q]
CVTPS2PI mm2, [srcq+src2q]
CVTPS2PI mm3, [srcq+src3q]
CVTPS2PI mm4, [srcq+src4q]
CVTPS2PI mm5, [srcq+src5q]
packssdw mm0, mm3
packssdw mm1, mm4
packssdw mm2, mm5
PSWAPD mm3, mm0
punpcklwd mm0, mm1
punpckhwd mm1, mm2
punpcklwd mm2, mm3
PSWAPD mm3, mm0
punpckldq mm0, mm2
punpckhdq mm2, mm1
punpckldq mm1, mm3
movq [dstq ], mm0
movq [dstq+16], mm2
movq [dstq+ 8], mm1
add srcq, 8
add dstq, 24
sub lend, 2
jg .loop
emms
RET
%endmacro ; FLOAT_TO_INT16_INTERLEAVE6
INIT_MMX sse
FLOAT_TO_INT16_INTERLEAVE6
INIT_MMX 3dnow
FLOAT_TO_INT16_INTERLEAVE6
INIT_MMX 3dnowext
FLOAT_TO_INT16_INTERLEAVE6
;-----------------------------------------------------------------------------
; void ff_float_interleave6(float *dst, const float **src, unsigned int len);
;-----------------------------------------------------------------------------
%macro FLOAT_INTERLEAVE6 1
cglobal float_interleave6, 2, 8, %1, dst, src, src1, src2, src3, src4, src5, len
%if ARCH_X86_64
mov lend, r2d
%else
%define lend dword r2m
%endif
mov src1q, [srcq+1*gprsize]
mov src2q, [srcq+2*gprsize]
mov src3q, [srcq+3*gprsize]
mov src4q, [srcq+4*gprsize]
mov src5q, [srcq+5*gprsize]
mov srcq, [srcq]
sub src1q, srcq
sub src2q, srcq
sub src3q, srcq
sub src4q, srcq
sub src5q, srcq
.loop:
%if cpuflag(sse)
movaps m0, [srcq]
movaps m1, [srcq+src1q]
movaps m2, [srcq+src2q]
movaps m3, [srcq+src3q]
movaps m4, [srcq+src4q]
movaps m5, [srcq+src5q]
SBUTTERFLYPS 0, 1, 6
SBUTTERFLYPS 2, 3, 6
SBUTTERFLYPS 4, 5, 6
movaps m6, m4
shufps m4, m0, 0xe4
movlhps m0, m2
movhlps m6, m2
movaps [dstq ], m0
movaps [dstq+16], m4
movaps [dstq+32], m6
movaps m6, m5
shufps m5, m1, 0xe4
movlhps m1, m3
movhlps m6, m3
movaps [dstq+48], m1
movaps [dstq+64], m5
movaps [dstq+80], m6
%else ; mmx
movq m0, [srcq]
movq m1, [srcq+src1q]
movq m2, [srcq+src2q]
movq m3, [srcq+src3q]
movq m4, [srcq+src4q]
movq m5, [srcq+src5q]
SBUTTERFLY dq, 0, 1, 6
SBUTTERFLY dq, 2, 3, 6
SBUTTERFLY dq, 4, 5, 6
movq [dstq ], m0
movq [dstq+ 8], m2
movq [dstq+16], m4
movq [dstq+24], m1
movq [dstq+32], m3
movq [dstq+40], m5
%endif
add srcq, mmsize
add dstq, mmsize*6
sub lend, mmsize/4
jg .loop
%if mmsize == 8
emms
%endif
REP_RET
%endmacro
INIT_MMX mmx
FLOAT_INTERLEAVE6 0
INIT_XMM sse
FLOAT_INTERLEAVE6 7
;-----------------------------------------------------------------------------
; void ff_float_interleave2(float *dst, const float **src, unsigned int len);
;-----------------------------------------------------------------------------
%macro FLOAT_INTERLEAVE2 1
cglobal float_interleave2, 3, 4, %1, dst, src, len, src1
mov src1q, [srcq+gprsize]
mov srcq, [srcq ]
sub src1q, srcq
.loop:
mova m0, [srcq ]
mova m1, [srcq+src1q ]
mova m3, [srcq +mmsize]
mova m4, [srcq+src1q+mmsize]
mova m2, m0
PUNPCKLDQ m0, m1
PUNPCKHDQ m2, m1
mova m1, m3
PUNPCKLDQ m3, m4
PUNPCKHDQ m1, m4
mova [dstq ], m0
mova [dstq+1*mmsize], m2
mova [dstq+2*mmsize], m3
mova [dstq+3*mmsize], m1
add srcq, mmsize*2
add dstq, mmsize*4
sub lend, mmsize/2
jg .loop
%if mmsize == 8
emms
%endif
REP_RET
%endmacro
INIT_MMX mmx
%define PUNPCKLDQ punpckldq
%define PUNPCKHDQ punpckhdq
FLOAT_INTERLEAVE2 0
INIT_XMM sse
%define PUNPCKLDQ unpcklps
%define PUNPCKHDQ unpckhps
FLOAT_INTERLEAVE2 5
| CTSRD-SOAAP/chromium-42.0.2311.135 | third_party/ffmpeg/libavcodec/x86/fmtconvert.asm | Assembly | bsd-3-clause | 12,343 |
#MULT INSTRUCTION
#1 NEGATIVE A, POSITIVE B: A=0x80000_0000-0xFFFF_0000, B=0x0000_0000-0x0000_7FFF
lui $1 0x8000
ori $1 0x0000
lui $2 0x0000
ori $2 0x0000
lui $3 0x0000
ori $3 0x0000
lui $4 0x0000
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xC000
ori $1 0x0000
lui $2 0x0000
ori $2 0x0001
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0xC000
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xE000
ori $1 0x0000
lui $2 0x0000
ori $2 0x0003
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0xA000
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xF000
ori $1 0x0000
lui $2 0x0000
ori $2 0x0007
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x9000
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xF800
ori $1 0x0000
lui $2 0x0000
ori $2 0x000F
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8800
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFC00
ori $1 0x0000
lui $2 0x0000
ori $2 0x001F
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8400
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFE00
ori $1 0x0000
lui $2 0x0000
ori $2 0x003F
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8200
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFF00
ori $1 0x0000
lui $2 0x0000
ori $2 0x007F
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8100
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFF80
ori $1 0x0000
lui $2 0x0000
ori $2 0x00FF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8080
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFC0
ori $1 0x0000
lui $2 0x0000
ori $2 0x01FF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8040
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFE0
ori $1 0x0000
lui $2 0x0000
ori $2 0x03FF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8020
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFF0
ori $1 0x0000
lui $2 0x0000
ori $2 0x07FF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8010
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFF8
ori $1 0x0000
lui $2 0x0000
ori $2 0x0FFF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8008
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFFC
ori $1 0x0000
lui $2 0x0000
ori $2 0x1FFF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8004
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFFE
ori $1 0x0000
lui $2 0x0000
ori $2 0x3FFF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8002
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0xFFFF
ori $1 0x0000
lui $2 0x0000
ori $2 0x7FFF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8001
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
#2 POSITIVE A, POSITIVE B: A=0x7FFF_0000-0x7FFF_FFFE, B=0x0000_FFFF-0x7FFF_FFFF
lui $1 0x7FFF
ori $1 0x0000
lui $2 0x0000
ori $2 0xFFFF
lui $3 0x0000
ori $3 0x7FFE
lui $4 0x8001
ori $4 0x0000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0x8000
lui $2 0x0001
ori $2 0xFFFF
lui $3 0x0000
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x8000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xC000
lui $2 0x0003
ori $2 0xFFFF
lui $3 0x0001
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x4000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xE000
lui $2 0x0007
ori $2 0xFFFF
lui $3 0x0003
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x2000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xF000
lui $2 0x000F
ori $2 0xFFFF
lui $3 0x0007
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x1000
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xF800
lui $2 0x001F
ori $2 0xFFFF
lui $3 0x000F
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0800
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFC00
lui $2 0x003F
ori $2 0xFFFF
lui $3 0x001F
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0400
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFE00
lui $2 0x007F
ori $2 0xFFFF
lui $3 0x003F
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0200
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFF00
lui $2 0x00FF
ori $2 0xFFFF
lui $3 0x007F
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0100
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFF80
lui $2 0x01FF
ori $2 0xFFFF
lui $3 0x00FF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0080
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFFC0
lui $2 0x03FF
ori $2 0xFFFF
lui $3 0x01FF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0040
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFFE0
lui $2 0x07FF
ori $2 0xFFFF
lui $3 0x03FF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0020
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFFF0
lui $2 0x0FFF
ori $2 0xFFFF
lui $3 0x07FF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0010
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFFF8
lui $2 0x1FFF
ori $2 0xFFFF
lui $3 0x0FFF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0008
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFFFC
lui $2 0x3FFF
ori $2 0xFFFF
lui $3 0x1FFF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0004
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
lui $1 0x7FFF
ori $1 0xFFFE
lui $2 0x7FFF
ori $2 0xFFFF
lui $3 0x3FFF
ori $3 0xFFFE
lui $4 0x8000
ori $4 0x0002
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
#3 POSITIVE A, NEGATIVE B
lui $1 0x7FFF
ori $1 0xFFFF
lui $2 0xFFFF
ori $2 0xFFFF
lui $3 0xFFFF
ori $3 0xFFFF
lui $4 0x8000
ori $4 0x0001
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
#4 NEGATIVE A, NEGATIVE B
lui $1 0xFFFF
ori $1 0xFFFF
lui $2 0xFFFF
ori $2 0xFFFF
lui $3 0x0000
ori $3 0x0000
lui $4 0x0000
ori $4 0x0001
mult $1 $2
mfhi $5
mflo $6
bne $3 $5 fail
sll $0 $0 0
bne $4 $6 fail
sll $0 $0 0
| mshaklunov/mips_onemore | tb/tprog/asm/test.mult.asm | Assembly | mit | 7,390 |
@********************************************************************
@* *
@* THIS FILE IS PART OF THE OggTheora SOFTWARE CODEC SOURCE CODE. *
@* USE, DISTRIBUTION AND REPRODUCTION OF THIS LIBRARY SOURCE IS *
@* GOVERNED BY A BSD-STYLE SOURCE LICENSE INCLUDED WITH THIS SOURCE *
@* IN 'COPYING'. PLEASE READ THESE TERMS BEFORE DISTRIBUTING. *
@* *
@* THE Theora SOURCE CODE IS COPYRIGHT (C) 2002-2010 *
@* by the Xiph.Org Foundation and contributors http://www.xiph.org/ *
@* *
@********************************************************************
@ Original implementation:
@ Copyright (C) 2009 Robin Watts for Pinknoise Productions Ltd
@ last mod: $Id:
@********************************************************************
.text; .p2align 2
.include "armopts-gnu.S"
.global oc_loop_filter_frag_rows_arm
@ Which bit this is depends on the order of packing within a bitfield.
@ Hopefully that doesn't change among any of the relevant compilers.
.set OC_FRAG_CODED_FLAG, 1
@ Vanilla ARM v4 version
.type loop_filter_h_arm, %function; loop_filter_h_arm: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
STMFD r13!,{r3-r6,r14}
MOV r14,#8
MOV r6, #255
lfh_arm_lp:
LDRB r3, [r0, #-2] @ r3 = _pix[0]
LDRB r12,[r0, #1] @ r12= _pix[3]
LDRB r4, [r0, #-1] @ r4 = _pix[1]
LDRB r5, [r0] @ r5 = _pix[2]
SUB r3, r3, r12 @ r3 = _pix[0]-_pix[3]+4
ADD r3, r3, #4
SUB r12,r5, r4 @ r12= _pix[2]-_pix[1]
ADD r12,r12,r12,LSL #1 @ r12= 3*(_pix[2]-_pix[1])
ADD r12,r12,r3 @ r12= _pix[0]-_pix[3]+3*(_pix[2]-_pix[1])+4
MOV r12,r12,ASR #3
LDRSB r12,[r2, r12]
@ Stall (2 on Xscale)
ADDS r4, r4, r12
CMPGT r6, r4
EORLT r4, r6, r4, ASR #32
SUBS r5, r5, r12
CMPGT r6, r5
EORLT r5, r6, r5, ASR #32
STRB r4, [r0, #-1]
STRB r5, [r0], r1
SUBS r14,r14,#1
BGT lfh_arm_lp
SUB r0, r0, r1, LSL #3
LDMFD r13!,{r3-r6,PC}
.size loop_filter_h_arm, .-loop_filter_h_arm @ ENDP
.type loop_filter_v_arm, %function; loop_filter_v_arm: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
STMFD r13!,{r3-r6,r14}
MOV r14,#8
MOV r6, #255
lfv_arm_lp:
LDRB r3, [r0, -r1, LSL #1] @ r3 = _pix[0]
LDRB r12,[r0, r1] @ r12= _pix[3]
LDRB r4, [r0, -r1] @ r4 = _pix[1]
LDRB r5, [r0] @ r5 = _pix[2]
SUB r3, r3, r12 @ r3 = _pix[0]-_pix[3]+4
ADD r3, r3, #4
SUB r12,r5, r4 @ r12= _pix[2]-_pix[1]
ADD r12,r12,r12,LSL #1 @ r12= 3*(_pix[2]-_pix[1])
ADD r12,r12,r3 @ r12= _pix[0]-_pix[3]+3*(_pix[2]-_pix[1])+4
MOV r12,r12,ASR #3
LDRSB r12,[r2, r12]
@ Stall (2 on Xscale)
ADDS r4, r4, r12
CMPGT r6, r4
EORLT r4, r6, r4, ASR #32
SUBS r5, r5, r12
CMPGT r6, r5
EORLT r5, r6, r5, ASR #32
STRB r4, [r0, -r1]
STRB r5, [r0], #1
SUBS r14,r14,#1
BGT lfv_arm_lp
SUB r0, r0, #8
LDMFD r13!,{r3-r6,PC}
.size loop_filter_v_arm, .-loop_filter_v_arm @ ENDP
.type oc_loop_filter_frag_rows_arm, %function; oc_loop_filter_frag_rows_arm: @ PROC
@ r0 = _ref_frame_data
@ r1 = _ystride
@ r2 = _bv
@ r3 = _frags
@ r4 = _fragi0
@ r5 = _fragi0_end
@ r6 = _fragi_top
@ r7 = _fragi_bot
@ r8 = _frag_buf_offs
@ r9 = _nhfrags
MOV r12,r13
STMFD r13!,{r0,r4-r11,r14}
LDMFD r12,{r4-r9}
ADD r2, r2, #127 @ _bv += 127
CMP r4, r5 @ if(_fragi0>=_fragi0_end)
BGE oslffri_arm_end @ bail
SUBS r9, r9, #1 @ r9 = _nhfrags-1 if (r9<=0)
BLE oslffri_arm_end @ bail
ADD r3, r3, r4, LSL #2 @ r3 = &_frags[fragi]
ADD r8, r8, r4, LSL #2 @ r8 = &_frag_buf_offs[fragi]
SUB r7, r7, r9 @ _fragi_bot -= _nhfrags;
oslffri_arm_lp1:
MOV r10,r4 @ r10= fragi = _fragi0
ADD r11,r4, r9 @ r11= fragi_end-1=fragi+_nhfrags-1
oslffri_arm_lp2:
LDR r14,[r3], #4 @ r14= _frags[fragi] _frags++
LDR r0, [r13] @ r0 = _ref_frame_data
LDR r12,[r8], #4 @ r12= _frag_buf_offs[fragi] _frag_buf_offs++
TST r14,#OC_FRAG_CODED_FLAG
BEQ oslffri_arm_uncoded
CMP r10,r4 @ if (fragi>_fragi0)
ADD r0, r0, r12 @ r0 = _ref_frame_data + _frag_buf_offs[fragi]
BLGT loop_filter_h_arm
CMP r4, r6 @ if (_fragi0>_fragi_top)
BLGT loop_filter_v_arm
CMP r10,r11 @ if(fragi+1<fragi_end)===(fragi<fragi_end-1)
LDRLT r12,[r3] @ r12 = _frags[fragi+1]
ADD r0, r0, #8
ADD r10,r10,#1 @ r10 = fragi+1;
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG @ && _frags[fragi+1].coded==0
BLLT loop_filter_h_arm
CMP r10,r7 @ if (fragi<_fragi_bot)
LDRLT r12,[r3, r9, LSL #2] @ r12 = _frags[fragi+1+_nhfrags-1]
SUB r0, r0, #8
ADD r0, r0, r1, LSL #3
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG
BLLT loop_filter_v_arm
CMP r10,r11 @ while(fragi<=fragi_end-1)
BLE oslffri_arm_lp2
MOV r4, r10 @ r4 = fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_arm_lp1
oslffri_arm_end:
LDMFD r13!,{r0,r4-r11,PC}
oslffri_arm_uncoded:
ADD r10,r10,#1
CMP r10,r11
BLE oslffri_arm_lp2
MOV r4, r10 @ r4 = _fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_arm_lp1
LDMFD r13!,{r0,r4-r11,PC}
.size oc_loop_filter_frag_rows_arm, .-oc_loop_filter_frag_rows_arm @ ENDP
.if OC_ARM_ASM_MEDIA
.global oc_loop_filter_init_v6
.global oc_loop_filter_frag_rows_v6
.type oc_loop_filter_init_v6, %function; oc_loop_filter_init_v6: @ PROC
@ r0 = _bv
@ r1 = _flimit (=L from the spec)
MVN r1, r1, LSL #1 @ r1 = <0xFFFFFF|255-2*L>
AND r1, r1, #255 @ r1 = ll=r10x0xFF
ORR r1, r1, r1, LSL #8 @ r1 = <ll|ll>
PKHBT r1, r1, r1, LSL #16 @ r1 = <ll|ll|ll|ll>
STR r1, [r0]
MOV PC,r14
.size oc_loop_filter_init_v6, .-oc_loop_filter_init_v6 @ ENDP
@ We could use the same strategy as the v filter below, but that would require
@ 40 instructions to load the data and transpose it into columns and another
@ 32 to write out the results at the end, plus the 52 instructions to do the
@ filtering itself.
@ This is slightly less, and less code, even assuming we could have shared the
@ 52 instructions in the middle with the other function.
@ It executes slightly fewer instructions than the ARMv6 approach David Conrad
@ proposed for FFmpeg, but not by much:
@ http://lists.mplayerhq.hu/pipermail/ffmpeg-devel/2010-February/083141.html
@ His is a lot less code, though, because it only does two rows at once instead
@ of four.
.type loop_filter_h_v6, %function; loop_filter_h_v6: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int _ll
@ preserves r0-r3
STMFD r13!,{r4-r11,r14}
LDR r12,=0x10003
BL loop_filter_h_core_v6
ADD r0, r0, r1, LSL #2
BL loop_filter_h_core_v6
SUB r0, r0, r1, LSL #2
LDMFD r13!,{r4-r11,PC}
.size loop_filter_h_v6, .-loop_filter_h_v6 @ ENDP
.type loop_filter_h_core_v6, %function; loop_filter_h_core_v6: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int _ll
@ r12= 0x10003
@ Preserves r0-r3, r12; Clobbers r4-r11.
LDR r4,[r0, #-2]! @ r4 = <p3|p2|p1|p0>
@ Single issue
LDR r5,[r0, r1]! @ r5 = <q3|q2|q1|q0>
UXTB16 r6, r4, ROR #16 @ r6 = <p0|p2>
UXTB16 r4, r4, ROR #8 @ r4 = <p3|p1>
UXTB16 r7, r5, ROR #16 @ r7 = <q0|q2>
UXTB16 r5, r5, ROR #8 @ r5 = <q3|q1>
PKHBT r8, r4, r5, LSL #16 @ r8 = <__|q1|__|p1>
PKHBT r9, r6, r7, LSL #16 @ r9 = <__|q2|__|p2>
SSUB16 r6, r4, r6 @ r6 = <p3-p0|p1-p2>
SMLAD r6, r6, r12,r12 @ r6 = <????|(p3-p0)+3*(p1-p2)+3>
SSUB16 r7, r5, r7 @ r7 = <q3-q0|q1-q2>
SMLAD r7, r7, r12,r12 @ r7 = <????|(q0-q3)+3*(q2-q1)+4>
LDR r4,[r0, r1]! @ r4 = <r3|r2|r1|r0>
MOV r6, r6, ASR #3 @ r6 = <??????|(p3-p0)+3*(p1-p2)+3>>3>
LDR r5,[r0, r1]! @ r5 = <s3|s2|s1|s0>
PKHBT r11,r6, r7, LSL #13 @ r11= <??|-R_q|??|-R_p>
UXTB16 r6, r4, ROR #16 @ r6 = <r0|r2>
UXTB16 r11,r11 @ r11= <__|-R_q|__|-R_p>
UXTB16 r4, r4, ROR #8 @ r4 = <r3|r1>
UXTB16 r7, r5, ROR #16 @ r7 = <s0|s2>
PKHBT r10,r6, r7, LSL #16 @ r10= <__|s2|__|r2>
SSUB16 r6, r4, r6 @ r6 = <r3-r0|r1-r2>
UXTB16 r5, r5, ROR #8 @ r5 = <s3|s1>
SMLAD r6, r6, r12,r12 @ r6 = <????|(r3-r0)+3*(r2-r1)+3>
SSUB16 r7, r5, r7 @ r7 = <r3-r0|r1-r2>
SMLAD r7, r7, r12,r12 @ r7 = <????|(s0-s3)+3*(s2-s1)+4>
ORR r9, r9, r10, LSL #8 @ r9 = <s2|q2|r2|p2>
MOV r6, r6, ASR #3 @ r6 = <??????|(r0-r3)+3*(r2-r1)+4>>3>
PKHBT r10,r4, r5, LSL #16 @ r10= <__|s1|__|r1>
PKHBT r6, r6, r7, LSL #13 @ r6 = <??|-R_s|??|-R_r>
ORR r8, r8, r10, LSL #8 @ r8 = <s1|q1|r1|p1>
UXTB16 r6, r6 @ r6 = <__|-R_s|__|-R_r>
MOV r10,#0
ORR r6, r11,r6, LSL #8 @ r6 = <-R_s|-R_q|-R_r|-R_p>
@ Single issue
@ There's no min, max or abs instruction.
@ SSUB8 and SEL will work for abs, and we can do all the rest with
@ unsigned saturated adds, which means the GE flags are still all
@ set when we're done computing lflim(abs(R_i),L).
@ This allows us to both add and subtract, and split the results by
@ the original sign of R_i.
SSUB8 r7, r10,r6
@ Single issue
SEL r7, r7, r6 @ r7 = abs(R_i)
@ Single issue
UQADD8 r4, r7, r2 @ r4 = 255-max(2*L-abs(R_i),0)
@ Single issue
UQADD8 r7, r7, r4
@ Single issue
UQSUB8 r7, r7, r4 @ r7 = min(abs(R_i),max(2*L-abs(R_i),0))
@ Single issue
UQSUB8 r4, r8, r7
UQADD8 r5, r9, r7
UQADD8 r8, r8, r7
UQSUB8 r9, r9, r7
SEL r8, r8, r4 @ r8 = p1+lflim(R_i,L)
SEL r9, r9, r5 @ r9 = p2-lflim(R_i,L)
MOV r5, r9, LSR #24 @ r5 = s2
STRB r5, [r0,#2]!
MOV r4, r8, LSR #24 @ r4 = s1
STRB r4, [r0,#-1]
MOV r5, r9, LSR #8 @ r5 = r2
STRB r5, [r0,-r1]!
MOV r4, r8, LSR #8 @ r4 = r1
STRB r4, [r0,#-1]
MOV r5, r9, LSR #16 @ r5 = q2
STRB r5, [r0,-r1]!
MOV r4, r8, LSR #16 @ r4 = q1
STRB r4, [r0,#-1]
@ Single issue
STRB r9, [r0,-r1]!
@ Single issue
STRB r8, [r0,#-1]
MOV PC,r14
.size loop_filter_h_core_v6, .-loop_filter_h_core_v6 @ ENDP
@ This uses the same strategy as the MMXEXT version for x86, except that UHADD8
@ computes (a+b>>1) instead of (a+b+1>>1) like PAVGB.
@ This works just as well, with the following procedure for computing the
@ filter value, f:
@ u = ~UHADD8(p1,~p2);
@ v = UHADD8(~p1,p2);
@ m = v-u;
@ a = m^UHADD8(m^p0,m^~p3);
@ f = UHADD8(UHADD8(a,u1),v1);
@ where f = 127+R, with R in [-127,128] defined as in the spec.
@ This is exactly the same amount of arithmetic as the version that uses PAVGB
@ as the basic operator.
@ It executes about 2/3 the number of instructions of David Conrad's approach,
@ but requires more code, because it does all eight columns at once, instead
@ of four at a time.
.type loop_filter_v_v6, %function; loop_filter_v_v6: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int _ll
@ preserves r0-r11
STMFD r13!,{r4-r11,r14}
LDRD r6, [r0, -r1]! @ r7, r6 = <p5|p1>
LDRD r4, [r0, -r1] @ r5, r4 = <p4|p0>
LDRD r8, [r0, r1]! @ r9, r8 = <p6|p2>
MVN r14,r6 @ r14= ~p1
LDRD r10,[r0, r1] @ r11,r10= <p7|p3>
@ Filter the first four columns.
MVN r12,r8 @ r12= ~p2
UHADD8 r14,r14,r8 @ r14= v1=~p1+p2>>1
UHADD8 r12,r12,r6 @ r12= p1+~p2>>1
MVN r10, r10 @ r10=~p3
MVN r12,r12 @ r12= u1=~p1+p2+1>>1
SSUB8 r14,r14,r12 @ r14= m1=v1-u1
@ Single issue
EOR r4, r4, r14 @ r4 = m1^p0
EOR r10,r10,r14 @ r10= m1^~p3
UHADD8 r4, r4, r10 @ r4 = (m1^p0)+(m1^~p3)>>1
@ Single issue
EOR r4, r4, r14 @ r4 = a1=m1^((m1^p0)+(m1^~p3)>>1)
SADD8 r14,r14,r12 @ r14= v1=m1+u1
UHADD8 r4, r4, r12 @ r4 = a1+u1>>1
MVN r12,r9 @ r12= ~p6
UHADD8 r4, r4, r14 @ r4 = f1=(a1+u1>>1)+v1>>1
@ Filter the second four columns.
MVN r14,r7 @ r14= ~p5
UHADD8 r12,r12,r7 @ r12= p5+~p6>>1
UHADD8 r14,r14,r9 @ r14= v2=~p5+p6>>1
MVN r12,r12 @ r12= u2=~p5+p6+1>>1
MVN r11,r11 @ r11=~p7
SSUB8 r10,r14,r12 @ r10= m2=v2-u2
@ Single issue
EOR r5, r5, r10 @ r5 = m2^p4
EOR r11,r11,r10 @ r11= m2^~p7
UHADD8 r5, r5, r11 @ r5 = (m2^p4)+(m2^~p7)>>1
@ Single issue
EOR r5, r5, r10 @ r5 = a2=m2^((m2^p4)+(m2^~p7)>>1)
@ Single issue
UHADD8 r5, r5, r12 @ r5 = a2+u2>>1
LDR r12,=0x7F7F7F7F @ r12 = {127}x4
UHADD8 r5, r5, r14 @ r5 = f2=(a2+u2>>1)+v2>>1
@ Now split f[i] by sign.
@ There's no min or max instruction.
@ We could use SSUB8 and SEL, but this is just as many instructions and
@ dual issues more (for v7 without NEON).
UQSUB8 r10,r4, r12 @ r10= R_i>0?R_i:0
UQSUB8 r4, r12,r4 @ r4 = R_i<0?-R_i:0
UQADD8 r11,r10,r2 @ r11= 255-max(2*L-abs(R_i<0),0)
UQADD8 r14,r4, r2 @ r14= 255-max(2*L-abs(R_i>0),0)
UQADD8 r10,r10,r11
UQADD8 r4, r4, r14
UQSUB8 r10,r10,r11 @ r10= min(abs(R_i<0),max(2*L-abs(R_i<0),0))
UQSUB8 r4, r4, r14 @ r4 = min(abs(R_i>0),max(2*L-abs(R_i>0),0))
UQSUB8 r11,r5, r12 @ r11= R_i>0?R_i:0
UQADD8 r6, r6, r10
UQSUB8 r8, r8, r10
UQSUB8 r5, r12,r5 @ r5 = R_i<0?-R_i:0
UQSUB8 r6, r6, r4 @ r6 = p1+lflim(R_i,L)
UQADD8 r8, r8, r4 @ r8 = p2-lflim(R_i,L)
UQADD8 r10,r11,r2 @ r10= 255-max(2*L-abs(R_i<0),0)
UQADD8 r14,r5, r2 @ r14= 255-max(2*L-abs(R_i>0),0)
UQADD8 r11,r11,r10
UQADD8 r5, r5, r14
UQSUB8 r11,r11,r10 @ r11= min(abs(R_i<0),max(2*L-abs(R_i<0),0))
UQSUB8 r5, r5, r14 @ r5 = min(abs(R_i>0),max(2*L-abs(R_i>0),0))
UQADD8 r7, r7, r11
UQSUB8 r9, r9, r11
UQSUB8 r7, r7, r5 @ r7 = p5+lflim(R_i,L)
STRD r6, [r0, -r1] @ [p5:p1] = [r7: r6]
UQADD8 r9, r9, r5 @ r9 = p6-lflim(R_i,L)
STRD r8, [r0] @ [p6:p2] = [r9: r8]
LDMFD r13!,{r4-r11,PC}
.size loop_filter_v_v6, .-loop_filter_v_v6 @ ENDP
.type oc_loop_filter_frag_rows_v6, %function; oc_loop_filter_frag_rows_v6: @ PROC
@ r0 = _ref_frame_data
@ r1 = _ystride
@ r2 = _bv
@ r3 = _frags
@ r4 = _fragi0
@ r5 = _fragi0_end
@ r6 = _fragi_top
@ r7 = _fragi_bot
@ r8 = _frag_buf_offs
@ r9 = _nhfrags
MOV r12,r13
STMFD r13!,{r0,r4-r11,r14}
LDMFD r12,{r4-r9}
LDR r2, [r2] @ ll = *(int *)_bv
CMP r4, r5 @ if(_fragi0>=_fragi0_end)
BGE oslffri_v6_end @ bail
SUBS r9, r9, #1 @ r9 = _nhfrags-1 if (r9<=0)
BLE oslffri_v6_end @ bail
ADD r3, r3, r4, LSL #2 @ r3 = &_frags[fragi]
ADD r8, r8, r4, LSL #2 @ r8 = &_frag_buf_offs[fragi]
SUB r7, r7, r9 @ _fragi_bot -= _nhfrags;
oslffri_v6_lp1:
MOV r10,r4 @ r10= fragi = _fragi0
ADD r11,r4, r9 @ r11= fragi_end-1=fragi+_nhfrags-1
oslffri_v6_lp2:
LDR r14,[r3], #4 @ r14= _frags[fragi] _frags++
LDR r0, [r13] @ r0 = _ref_frame_data
LDR r12,[r8], #4 @ r12= _frag_buf_offs[fragi] _frag_buf_offs++
TST r14,#OC_FRAG_CODED_FLAG
BEQ oslffri_v6_uncoded
CMP r10,r4 @ if (fragi>_fragi0)
ADD r0, r0, r12 @ r0 = _ref_frame_data + _frag_buf_offs[fragi]
BLGT loop_filter_h_v6
CMP r4, r6 @ if (fragi0>_fragi_top)
BLGT loop_filter_v_v6
CMP r10,r11 @ if(fragi+1<fragi_end)===(fragi<fragi_end-1)
LDRLT r12,[r3] @ r12 = _frags[fragi+1]
ADD r0, r0, #8
ADD r10,r10,#1 @ r10 = fragi+1;
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG @ && _frags[fragi+1].coded==0
BLLT loop_filter_h_v6
CMP r10,r7 @ if (fragi<_fragi_bot)
LDRLT r12,[r3, r9, LSL #2] @ r12 = _frags[fragi+1+_nhfrags-1]
SUB r0, r0, #8
ADD r0, r0, r1, LSL #3
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG
BLLT loop_filter_v_v6
CMP r10,r11 @ while(fragi<=fragi_end-1)
BLE oslffri_v6_lp2
MOV r4, r10 @ r4 = fragi0 += nhfrags
CMP r4, r5
BLT oslffri_v6_lp1
oslffri_v6_end:
LDMFD r13!,{r0,r4-r11,PC}
oslffri_v6_uncoded:
ADD r10,r10,#1
CMP r10,r11
BLE oslffri_v6_lp2
MOV r4, r10 @ r4 = fragi0 += nhfrags
CMP r4, r5
BLT oslffri_v6_lp1
LDMFD r13!,{r0,r4-r11,PC}
.size oc_loop_filter_frag_rows_v6, .-oc_loop_filter_frag_rows_v6 @ ENDP
.endif
.if OC_ARM_ASM_NEON
.global oc_loop_filter_init_neon
.global oc_loop_filter_frag_rows_neon
.type oc_loop_filter_init_neon, %function; oc_loop_filter_init_neon: @ PROC
@ r0 = _bv
@ r1 = _flimit (=L from the spec)
MOV r1, r1, LSL #1 @ r1 = 2*L
VDUP.S16 Q15, r1 @ Q15= 2L in U16s
VST1.64 {D30,D31}, [r0,:128]
MOV PC,r14
.size oc_loop_filter_init_neon, .-oc_loop_filter_init_neon @ ENDP
.type loop_filter_h_neon, %function; loop_filter_h_neon: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
@ We assume Q15= 2*L in U16s
@ My best guesses at cycle counts (and latency)--vvv
SUB r12,r0, #2
@ Doing a 2-element structure load saves doing two VTRN's below, at the
@ cost of using two more slower single-lane loads vs. the faster
@ all-lane loads.
@ It's less code this way, though, and benches a hair faster, but it
@ leaves D2 and D4 swapped.
VLD2.16 {D0[],D2[]}, [r12], r1 @ D0 = ____________1100 2,1
@ D2 = ____________3322
VLD2.16 {D4[],D6[]}, [r12], r1 @ D4 = ____________5544 2,1
@ D6 = ____________7766
VLD2.16 {D0[1],D2[1]},[r12], r1 @ D0 = ________99881100 3,1
@ D2 = ________BBAA3322
VLD2.16 {D4[1],D6[1]},[r12], r1 @ D4 = ________DDCC5544 3,1
@ D6 = ________FFEE7766
VLD2.16 {D0[2],D2[2]},[r12], r1 @ D0 = ____GGHH99881100 3,1
@ D2 = ____JJIIBBAA3322
VLD2.16 {D4[2],D6[2]},[r12], r1 @ D4 = ____KKLLDDCC5544 3,1
@ D6 = ____NNMMFFEE7766
VLD2.16 {D0[3],D2[3]},[r12], r1 @ D0 = PPOOGGHH99881100 3,1
@ D2 = RRQQJJIIBBAA3322
VLD2.16 {D4[3],D6[3]},[r12], r1 @ D4 = TTSSKKLLDDCC5544 3,1
@ D6 = VVUUNNMMFFEE7766
VTRN.8 D0, D4 @ D0 = SSOOKKGGCC884400 D4 = TTPPLLHHDD995511 1,1
VTRN.8 D2, D6 @ D2 = UUQQMMIIEEAA6622 D6 = VVRRNNJJFFBB7733 1,1
VSUBL.U8 Q0, D0, D6 @ Q0 = 00 - 33 in S16s 1,3
VSUBL.U8 Q8, D2, D4 @ Q8 = 22 - 11 in S16s 1,3
ADD r12,r0, #8
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12]
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12,r1]
VADD.S16 Q0, Q0, Q8 @ Q0 = [0-3]+3*[2-1] 1,3
PLD [r12,r1, LSL #1]
VRSHR.S16 Q0, Q0, #3 @ Q0 = f = ([0-3]+3*[2-1]+4)>>3 1,4
ADD r12,r12,r1, LSL #2
@ We want to do
@ f = CLAMP(MIN(-2L-f,0), f, MAX(2L-f,0))
@ = ((f >= 0) ? MIN( f ,MAX(2L- f ,0)) : MAX( f , MIN(-2L- f ,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) : MAX(-|f|, MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|,-MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|, MAX( 2L-|f|,0)))
@ So we've reduced the left and right hand terms to be the same, except
@ for a negation.
@ Stall x3
VABS.S16 Q9, Q0 @ Q9 = |f| in U16s 1,4
PLD [r12,-r1]
VSHR.S16 Q0, Q0, #15 @ Q0 = -1 or 0 according to sign 1,3
PLD [r12]
VQSUB.U16 Q10,Q15,Q9 @ Q10= MAX(2L-|f|,0) in U16s 1,4
PLD [r12,r1]
VMOVL.U8 Q1, D2 @ Q2 = __UU__QQ__MM__II__EE__AA__66__22 2,3
PLD [r12,r1,LSL #1]
VMIN.U16 Q9, Q10,Q9 @ Q9 = MIN(|f|,MAX(2L-|f|)) 1,4
ADD r12,r12,r1, LSL #2
@ Now we need to correct for the sign of f.
@ For negative elements of Q0, we want to subtract the appropriate
@ element of Q9. For positive elements we want to add them. No NEON
@ instruction exists to do this, so we need to negate the negative
@ elements, and we can then just add them. a-b = a-(1+!b) = a-1+!b
VADD.S16 Q9, Q9, Q0 @ 1,3
PLD [r12,-r1]
VEOR.S16 Q9, Q9, Q0 @ Q9 = real value of f 1,3
@ Bah. No VRSBW.U8
@ Stall (just 1 as Q9 not needed to second pipeline stage. I think.)
VADDW.U8 Q2, Q9, D4 @ Q1 = xxTTxxPPxxLLxxHHxxDDxx99xx55xx11 1,3
VSUB.S16 Q1, Q1, Q9 @ Q2 = xxUUxxQQxxMMxxIIxxEExxAAxx66xx22 1,3
VQMOVUN.S16 D4, Q2 @ D4 = TTPPLLHHDD995511 1,1
VQMOVUN.S16 D2, Q1 @ D2 = UUQQMMIIEEAA6622 1,1
SUB r12,r0, #1
VTRN.8 D4, D2 @ D4 = QQPPIIHHAA992211 D2 = MMLLEEDD6655 1,1
VST1.16 {D4[0]}, [r12], r1
VST1.16 {D2[0]}, [r12], r1
VST1.16 {D4[1]}, [r12], r1
VST1.16 {D2[1]}, [r12], r1
VST1.16 {D4[2]}, [r12], r1
VST1.16 {D2[2]}, [r12], r1
VST1.16 {D4[3]}, [r12], r1
VST1.16 {D2[3]}, [r12], r1
MOV PC,r14
.size loop_filter_h_neon, .-loop_filter_h_neon @ ENDP
.type loop_filter_v_neon, %function; loop_filter_v_neon: @ PROC
@ r0 = unsigned char *_pix
@ r1 = int _ystride
@ r2 = int *_bv
@ preserves r0-r3
@ We assume Q15= 2*L in U16s
@ My best guesses at cycle counts (and latency)--vvv
SUB r12,r0, r1, LSL #1
VLD1.64 {D0}, [r12,:64], r1 @ D0 = SSOOKKGGCC884400 2,1
VLD1.64 {D2}, [r12,:64], r1 @ D2 = TTPPLLHHDD995511 2,1
VLD1.64 {D4}, [r12,:64], r1 @ D4 = UUQQMMIIEEAA6622 2,1
VLD1.64 {D6}, [r12,:64] @ D6 = VVRRNNJJFFBB7733 2,1
VSUBL.U8 Q8, D4, D2 @ Q8 = 22 - 11 in S16s 1,3
VSUBL.U8 Q0, D0, D6 @ Q0 = 00 - 33 in S16s 1,3
ADD r12, #8
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12]
VADD.S16 Q0, Q0, Q8 @ 1,3
PLD [r12,r1]
VADD.S16 Q0, Q0, Q8 @ Q0 = [0-3]+3*[2-1] 1,3
SUB r12, r0, r1
VRSHR.S16 Q0, Q0, #3 @ Q0 = f = ([0-3]+3*[2-1]+4)>>3 1,4
@ We want to do
@ f = CLAMP(MIN(-2L-f,0), f, MAX(2L-f,0))
@ = ((f >= 0) ? MIN( f ,MAX(2L- f ,0)) : MAX( f , MIN(-2L- f ,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) : MAX(-|f|, MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|,-MIN(-2L+|f|,0)))
@ = ((f >= 0) ? MIN(|f|,MAX(2L-|f|,0)) :-MIN( |f|, MAX( 2L-|f|,0)))
@ So we've reduced the left and right hand terms to be the same, except
@ for a negation.
@ Stall x3
VABS.S16 Q9, Q0 @ Q9 = |f| in U16s 1,4
VSHR.S16 Q0, Q0, #15 @ Q0 = -1 or 0 according to sign 1,3
@ Stall x2
VQSUB.U16 Q10,Q15,Q9 @ Q10= MAX(2L-|f|,0) in U16s 1,4
VMOVL.U8 Q2, D4 @ Q2 = __UU__QQ__MM__II__EE__AA__66__22 2,3
@ Stall x2
VMIN.U16 Q9, Q10,Q9 @ Q9 = MIN(|f|,MAX(2L-|f|)) 1,4
@ Now we need to correct for the sign of f.
@ For negative elements of Q0, we want to subtract the appropriate
@ element of Q9. For positive elements we want to add them. No NEON
@ instruction exists to do this, so we need to negate the negative
@ elements, and we can then just add them. a-b = a-(1+!b) = a-1+!b
@ Stall x3
VADD.S16 Q9, Q9, Q0 @ 1,3
@ Stall x2
VEOR.S16 Q9, Q9, Q0 @ Q9 = real value of f 1,3
@ Bah. No VRSBW.U8
@ Stall (just 1 as Q9 not needed to second pipeline stage. I think.)
VADDW.U8 Q1, Q9, D2 @ Q1 = xxTTxxPPxxLLxxHHxxDDxx99xx55xx11 1,3
VSUB.S16 Q2, Q2, Q9 @ Q2 = xxUUxxQQxxMMxxIIxxEExxAAxx66xx22 1,3
VQMOVUN.S16 D2, Q1 @ D2 = TTPPLLHHDD995511 1,1
VQMOVUN.S16 D4, Q2 @ D4 = UUQQMMIIEEAA6622 1,1
VST1.64 {D2}, [r12,:64], r1
VST1.64 {D4}, [r12,:64], r1
MOV PC,r14
.size loop_filter_v_neon, .-loop_filter_v_neon @ ENDP
.type oc_loop_filter_frag_rows_neon, %function; oc_loop_filter_frag_rows_neon: @ PROC
@ r0 = _ref_frame_data
@ r1 = _ystride
@ r2 = _bv
@ r3 = _frags
@ r4 = _fragi0
@ r5 = _fragi0_end
@ r6 = _fragi_top
@ r7 = _fragi_bot
@ r8 = _frag_buf_offs
@ r9 = _nhfrags
MOV r12,r13
STMFD r13!,{r0,r4-r11,r14}
LDMFD r12,{r4-r9}
CMP r4, r5 @ if(_fragi0>=_fragi0_end)
BGE oslffri_neon_end@ bail
SUBS r9, r9, #1 @ r9 = _nhfrags-1 if (r9<=0)
BLE oslffri_neon_end @ bail
VLD1.64 {D30,D31}, [r2,:128] @ Q15= 2L in U16s
ADD r3, r3, r4, LSL #2 @ r3 = &_frags[fragi]
ADD r8, r8, r4, LSL #2 @ r8 = &_frag_buf_offs[fragi]
SUB r7, r7, r9 @ _fragi_bot -= _nhfrags;
oslffri_neon_lp1:
MOV r10,r4 @ r10= fragi = _fragi0
ADD r11,r4, r9 @ r11= fragi_end-1=fragi+_nhfrags-1
oslffri_neon_lp2:
LDR r14,[r3], #4 @ r14= _frags[fragi] _frags++
LDR r0, [r13] @ r0 = _ref_frame_data
LDR r12,[r8], #4 @ r12= _frag_buf_offs[fragi] _frag_buf_offs++
TST r14,#OC_FRAG_CODED_FLAG
BEQ oslffri_neon_uncoded
CMP r10,r4 @ if (fragi>_fragi0)
ADD r0, r0, r12 @ r0 = _ref_frame_data + _frag_buf_offs[fragi]
BLGT loop_filter_h_neon
CMP r4, r6 @ if (_fragi0>_fragi_top)
BLGT loop_filter_v_neon
CMP r10,r11 @ if(fragi+1<fragi_end)===(fragi<fragi_end-1)
LDRLT r12,[r3] @ r12 = _frags[fragi+1]
ADD r0, r0, #8
ADD r10,r10,#1 @ r10 = fragi+1;
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG @ && _frags[fragi+1].coded==0
BLLT loop_filter_h_neon
CMP r10,r7 @ if (fragi<_fragi_bot)
LDRLT r12,[r3, r9, LSL #2] @ r12 = _frags[fragi+1+_nhfrags-1]
SUB r0, r0, #8
ADD r0, r0, r1, LSL #3
ANDLT r12,r12,#OC_FRAG_CODED_FLAG
CMPLT r12,#OC_FRAG_CODED_FLAG
BLLT loop_filter_v_neon
CMP r10,r11 @ while(fragi<=fragi_end-1)
BLE oslffri_neon_lp2
MOV r4, r10 @ r4 = _fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_neon_lp1
oslffri_neon_end:
LDMFD r13!,{r0,r4-r11,PC}
oslffri_neon_uncoded:
ADD r10,r10,#1
CMP r10,r11
BLE oslffri_neon_lp2
MOV r4, r10 @ r4 = _fragi0 += _nhfrags
CMP r4, r5
BLT oslffri_neon_lp1
LDMFD r13!,{r0,r4-r11,PC}
.size oc_loop_filter_frag_rows_neon, .-oc_loop_filter_frag_rows_neon @ ENDP
.endif
@ END
.section .note.GNU-stack,"",%progbits
| blloyd75/theoraplayer | theora/lib/arm/armloop.asm | Assembly | bsd-3-clause | 24,454 |
;Testname=avx512cd; Arguments=-fbin -oavx512cd.bin -O0 -DSRC; Files=stdout stderr avx512cd.bin
; AVX-512CD testcases from gas
;------------------------
;
; This file is taken from there
; https://gnu.googlesource.com/binutils/+/master/gas/testsuite/gas/i386/x86-64-avx512cd-intel.d
; So the original author is "H.J. Lu" <hongjiu dot lu at intel dot com>
;
; Jin Kyu Song converted it for the nasm testing suite using gas2nasm.py
%macro testcase 2
%ifdef BIN
db %1
%endif
%ifdef SRC
%2
%endif
%endmacro
bits 64
testcase { 0x62, 0x02, 0x7d, 0x48, 0xc4, 0xf5 }, { vpconflictd zmm30,zmm29 }
testcase { 0x62, 0x02, 0x7d, 0x4f, 0xc4, 0xf5 }, { vpconflictd zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0x7d, 0xcf, 0xc4, 0xf5 }, { vpconflictd zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x31 }, { vpconflictd zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0x7d, 0x48, 0xc4, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vpconflictd zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x31 }, { vpconflictd zmm30,DWORD [rcx]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x72, 0x7f }, { vpconflictd zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vpconflictd zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0x72, 0x80 }, { vpconflictd zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0xc4, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vpconflictd zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x72, 0x7f }, { vpconflictd zmm30,DWORD [rdx+0x1fc]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vpconflictd zmm30,DWORD [rdx+0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0x72, 0x80 }, { vpconflictd zmm30,DWORD [rdx-0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0xc4, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vpconflictd zmm30,DWORD [rdx-0x204]{1to16} }
testcase { 0x62, 0x02, 0xfd, 0x48, 0xc4, 0xf5 }, { vpconflictq zmm30,zmm29 }
testcase { 0x62, 0x02, 0xfd, 0x4f, 0xc4, 0xf5 }, { vpconflictq zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0xfd, 0xcf, 0xc4, 0xf5 }, { vpconflictq zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x31 }, { vpconflictq zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0xfd, 0x48, 0xc4, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vpconflictq zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x31 }, { vpconflictq zmm30,QWORD [rcx]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x72, 0x7f }, { vpconflictq zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vpconflictq zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0x72, 0x80 }, { vpconflictq zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0xc4, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vpconflictq zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x72, 0x7f }, { vpconflictq zmm30,QWORD [rdx+0x3f8]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vpconflictq zmm30,QWORD [rdx+0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0x72, 0x80 }, { vpconflictq zmm30,QWORD [rdx-0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0xc4, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vpconflictq zmm30,QWORD [rdx-0x408]{1to8} }
testcase { 0x62, 0x02, 0x7d, 0x48, 0x44, 0xf5 }, { vplzcntd zmm30,zmm29 }
testcase { 0x62, 0x02, 0x7d, 0x4f, 0x44, 0xf5 }, { vplzcntd zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0x7d, 0xcf, 0x44, 0xf5 }, { vplzcntd zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x31 }, { vplzcntd zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0x7d, 0x48, 0x44, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vplzcntd zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x31 }, { vplzcntd zmm30,DWORD [rcx]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x72, 0x7f }, { vplzcntd zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vplzcntd zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0x72, 0x80 }, { vplzcntd zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0x7d, 0x48, 0x44, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vplzcntd zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x72, 0x7f }, { vplzcntd zmm30,DWORD [rdx+0x1fc]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0xb2, 0x00, 0x02, 0x00, 0x00 }, { vplzcntd zmm30,DWORD [rdx+0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0x72, 0x80 }, { vplzcntd zmm30,DWORD [rdx-0x200]{1to16} }
testcase { 0x62, 0x62, 0x7d, 0x58, 0x44, 0xb2, 0xfc, 0xfd, 0xff, 0xff }, { vplzcntd zmm30,DWORD [rdx-0x204]{1to16} }
testcase { 0x62, 0x02, 0xfd, 0x48, 0x44, 0xf5 }, { vplzcntq zmm30,zmm29 }
testcase { 0x62, 0x02, 0xfd, 0x4f, 0x44, 0xf5 }, { vplzcntq zmm30{k7},zmm29 }
testcase { 0x62, 0x02, 0xfd, 0xcf, 0x44, 0xf5 }, { vplzcntq zmm30{k7}{z},zmm29 }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x31 }, { vplzcntq zmm30,ZWORD [rcx] }
testcase { 0x62, 0x22, 0xfd, 0x48, 0x44, 0xb4, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vplzcntq zmm30,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x31 }, { vplzcntq zmm30,QWORD [rcx]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x72, 0x7f }, { vplzcntq zmm30,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0xb2, 0x00, 0x20, 0x00, 0x00 }, { vplzcntq zmm30,ZWORD [rdx+0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0x72, 0x80 }, { vplzcntq zmm30,ZWORD [rdx-0x2000] }
testcase { 0x62, 0x62, 0xfd, 0x48, 0x44, 0xb2, 0xc0, 0xdf, 0xff, 0xff }, { vplzcntq zmm30,ZWORD [rdx-0x2040] }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x72, 0x7f }, { vplzcntq zmm30,QWORD [rdx+0x3f8]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0xb2, 0x00, 0x04, 0x00, 0x00 }, { vplzcntq zmm30,QWORD [rdx+0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0x72, 0x80 }, { vplzcntq zmm30,QWORD [rdx-0x400]{1to8} }
testcase { 0x62, 0x62, 0xfd, 0x58, 0x44, 0xb2, 0xf8, 0xfb, 0xff, 0xff }, { vplzcntq zmm30,QWORD [rdx-0x408]{1to8} }
testcase { 0x62, 0x92, 0x16, 0x40, 0x27, 0xec }, { vptestnmd k5,zmm29,zmm28 }
testcase { 0x62, 0x92, 0x16, 0x47, 0x27, 0xec }, { vptestnmd k5{k7},zmm29,zmm28 }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x29 }, { vptestnmd k5,zmm29,ZWORD [rcx] }
testcase { 0x62, 0xb2, 0x16, 0x40, 0x27, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vptestnmd k5,zmm29,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x29 }, { vptestnmd k5,zmm29,DWORD [rcx]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x6a, 0x7f }, { vptestnmd k5,zmm29,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0xaa, 0x00, 0x20, 0x00, 0x00 }, { vptestnmd k5,zmm29,ZWORD [rdx+0x2000] }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0x6a, 0x80 }, { vptestnmd k5,zmm29,ZWORD [rdx-0x2000] }
testcase { 0x62, 0xf2, 0x16, 0x40, 0x27, 0xaa, 0xc0, 0xdf, 0xff, 0xff }, { vptestnmd k5,zmm29,ZWORD [rdx-0x2040] }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x6a, 0x7f }, { vptestnmd k5,zmm29,DWORD [rdx+0x1fc]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0xaa, 0x00, 0x02, 0x00, 0x00 }, { vptestnmd k5,zmm29,DWORD [rdx+0x200]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0x6a, 0x80 }, { vptestnmd k5,zmm29,DWORD [rdx-0x200]{1to16} }
testcase { 0x62, 0xf2, 0x16, 0x50, 0x27, 0xaa, 0xfc, 0xfd, 0xff, 0xff }, { vptestnmd k5,zmm29,DWORD [rdx-0x204]{1to16} }
testcase { 0x62, 0x92, 0x96, 0x40, 0x27, 0xec }, { vptestnmq k5,zmm29,zmm28 }
testcase { 0x62, 0x92, 0x96, 0x47, 0x27, 0xec }, { vptestnmq k5{k7},zmm29,zmm28 }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x29 }, { vptestnmq k5,zmm29,ZWORD [rcx] }
testcase { 0x62, 0xb2, 0x96, 0x40, 0x27, 0xac, 0xf0, 0x23, 0x01, 0x00, 0x00 }, { vptestnmq k5,zmm29,ZWORD [rax+r14*8+0x123] }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x29 }, { vptestnmq k5,zmm29,QWORD [rcx]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x6a, 0x7f }, { vptestnmq k5,zmm29,ZWORD [rdx+0x1fc0] }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0xaa, 0x00, 0x20, 0x00, 0x00 }, { vptestnmq k5,zmm29,ZWORD [rdx+0x2000] }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0x6a, 0x80 }, { vptestnmq k5,zmm29,ZWORD [rdx-0x2000] }
testcase { 0x62, 0xf2, 0x96, 0x40, 0x27, 0xaa, 0xc0, 0xdf, 0xff, 0xff }, { vptestnmq k5,zmm29,ZWORD [rdx-0x2040] }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x6a, 0x7f }, { vptestnmq k5,zmm29,QWORD [rdx+0x3f8]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0xaa, 0x00, 0x04, 0x00, 0x00 }, { vptestnmq k5,zmm29,QWORD [rdx+0x400]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0x6a, 0x80 }, { vptestnmq k5,zmm29,QWORD [rdx-0x400]{1to8} }
testcase { 0x62, 0xf2, 0x96, 0x50, 0x27, 0xaa, 0xf8, 0xfb, 0xff, 0xff }, { vptestnmq k5,zmm29,QWORD [rdx-0x408]{1to8} }
testcase { 0x62, 0x62, 0x7e, 0x48, 0x3a, 0xf6 }, { vpbroadcastmw2d zmm30,k6 }
testcase { 0x62, 0x62, 0xfe, 0x48, 0x2a, 0xf6 }, { vpbroadcastmb2q zmm30,k6 }
| endlessm/chromium-browser | third_party/nasm/test/avx512cd.asm | Assembly | bsd-3-clause | 13,126 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright(c) 2011-2018 Intel Corporation All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; * Neither the name of Intel Corporation nor the names of its
; contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
default rel
%include "reg_sizes.asm"
%define DECOMP_OK 0
%define END_INPUT 1
%define OUT_OVERFLOW 2
%define INVALID_BLOCK -1
%define INVALID_SYMBOL -2
%define INVALID_LOOKBACK -3
%define ISAL_DECODE_LONG_BITS 12
%define ISAL_DECODE_SHORT_BITS 10
%define COPY_SIZE 16
%define COPY_LEN_MAX 258
%define IN_BUFFER_SLOP 8
%define OUT_BUFFER_SLOP COPY_SIZE + COPY_LEN_MAX
%include "inflate_data_structs.asm"
%include "stdmac.asm"
extern rfc1951_lookup_table
%define LARGE_SHORT_SYM_LEN 25
%define LARGE_SHORT_SYM_MASK ((1 << LARGE_SHORT_SYM_LEN) - 1)
%define LARGE_LONG_SYM_LEN 10
%define LARGE_LONG_SYM_MASK ((1 << LARGE_LONG_SYM_LEN) - 1)
%define LARGE_SHORT_CODE_LEN_OFFSET 28
%define LARGE_LONG_CODE_LEN_OFFSET 10
%define LARGE_FLAG_BIT_OFFSET 25
%define LARGE_FLAG_BIT (1 << LARGE_FLAG_BIT_OFFSET)
%define LARGE_SYM_COUNT_OFFSET 26
%define LARGE_SYM_COUNT_LEN 2
%define LARGE_SYM_COUNT_MASK ((1 << LARGE_SYM_COUNT_LEN) - 1)
%define LARGE_SHORT_MAX_LEN_OFFSET 26
%define SMALL_SHORT_SYM_LEN 9
%define SMALL_SHORT_SYM_MASK ((1 << SMALL_SHORT_SYM_LEN) - 1)
%define SMALL_LONG_SYM_LEN 9
%define SMALL_LONG_SYM_MASK ((1 << SMALL_LONG_SYM_LEN) - 1)
%define SMALL_SHORT_CODE_LEN_OFFSET 11
%define SMALL_LONG_CODE_LEN_OFFSET 10
%define SMALL_FLAG_BIT_OFFSET 10
%define SMALL_FLAG_BIT (1 << SMALL_FLAG_BIT_OFFSET)
%define DIST_SYM_OFFSET 0
%define DIST_SYM_LEN 5
%define DIST_SYM_MASK ((1 << DIST_SYM_LEN) - 1)
%define DIST_SYM_EXTRA_OFFSET 5
%define DIST_SYM_EXTRA_LEN 4
%define DIST_SYM_EXTRA_MASK ((1 << DIST_SYM_EXTRA_LEN) - 1)
;; rax
%define tmp3 rax
%define read_in_2 rax
%define look_back_dist rax
;; rcx
;; rdx arg3
%define next_sym2 rdx
%define copy_start rdx
%define tmp4 rdx
;; rdi arg1
%define tmp1 rdi
%define look_back_dist2 rdi
%define next_bits2 rdi
%define next_sym3 rdi
;; rsi arg2
%define tmp2 rsi
%define next_sym_num rsi
%define next_bits rsi
;; rbx ; Saved
%define next_in rbx
;; rbp ; Saved
%define end_in rbp
;; r8
%define repeat_length r8
;; r9
%define read_in r9
;; r10
%define read_in_length r10
;; r11
%define state r11
;; r12 ; Saved
%define next_out r12
;; r13 ; Saved
%define end_out r13
;; r14 ; Saved
%define next_sym r14
;; r15 ; Saved
%define rfc_lookup r15
start_out_mem_offset equ 0
read_in_mem_offset equ 8
read_in_length_mem_offset equ 16
next_out_mem_offset equ 24
gpr_save_mem_offset equ 32
stack_size equ 4 * 8 + 8 * 8
%define _dist_extra_bit_count 264
%define _dist_start _dist_extra_bit_count + 1*32
%define _len_extra_bit_count _dist_start + 4*32
%define _len_start _len_extra_bit_count + 1*32
%ifidn __OUTPUT_FORMAT__, elf64
%define arg0 rdi
%define arg1 rsi
%macro FUNC_SAVE 0
%ifdef ALIGN_STACK
push rbp
mov rbp, rsp
sub rsp, stack_size
and rsp, ~15
%else
sub rsp, stack_size
%endif
mov [rsp + gpr_save_mem_offset + 0*8], rbx
mov [rsp + gpr_save_mem_offset + 1*8], rbp
mov [rsp + gpr_save_mem_offset + 2*8], r12
mov [rsp + gpr_save_mem_offset + 3*8], r13
mov [rsp + gpr_save_mem_offset + 4*8], r14
mov [rsp + gpr_save_mem_offset + 5*8], r15
%endm
%macro FUNC_RESTORE 0
mov rbx, [rsp + gpr_save_mem_offset + 0*8]
mov rbp, [rsp + gpr_save_mem_offset + 1*8]
mov r12, [rsp + gpr_save_mem_offset + 2*8]
mov r13, [rsp + gpr_save_mem_offset + 3*8]
mov r14, [rsp + gpr_save_mem_offset + 4*8]
mov r15, [rsp + gpr_save_mem_offset + 5*8]
%ifndef ALIGN_STACK
add rsp, stack_size
%else
mov rsp, rbp
pop rbp
%endif
%endm
%endif
%ifidn __OUTPUT_FORMAT__, win64
%define arg0 rcx
%define arg1 rdx
%macro FUNC_SAVE 0
%ifdef ALIGN_STACK
push rbp
mov rbp, rsp
sub rsp, stack_size
and rsp, ~15
%else
sub rsp, stack_size
%endif
mov [rsp + gpr_save_mem_offset + 0*8], rbx
mov [rsp + gpr_save_mem_offset + 1*8], rsi
mov [rsp + gpr_save_mem_offset + 2*8], rdi
mov [rsp + gpr_save_mem_offset + 3*8], rbp
mov [rsp + gpr_save_mem_offset + 4*8], r12
mov [rsp + gpr_save_mem_offset + 5*8], r13
mov [rsp + gpr_save_mem_offset + 6*8], r14
mov [rsp + gpr_save_mem_offset + 7*8], r15
%endm
%macro FUNC_RESTORE 0
mov rbx, [rsp + gpr_save_mem_offset + 0*8]
mov rsi, [rsp + gpr_save_mem_offset + 1*8]
mov rdi, [rsp + gpr_save_mem_offset + 2*8]
mov rbp, [rsp + gpr_save_mem_offset + 3*8]
mov r12, [rsp + gpr_save_mem_offset + 4*8]
mov r13, [rsp + gpr_save_mem_offset + 5*8]
mov r14, [rsp + gpr_save_mem_offset + 6*8]
mov r15, [rsp + gpr_save_mem_offset + 7*8]
%ifndef ALIGN_STACK
add rsp, stack_size
%else
mov rsp, rbp
pop rbp
%endif
%endm
%endif
;; Load read_in and updated in_buffer accordingly
;; when there are at least 8 bytes in the in buffer
;; Clobbers rcx, unless rcx is %%read_in_length
%macro inflate_in_load 6
%define %%next_in %1
%define %%end_in %2
%define %%read_in %3
%define %%read_in_length %4
%define %%tmp1 %5 ; Tmp registers
%define %%tmp2 %6
SHLX %%tmp1, [%%next_in], %%read_in_length
or %%read_in, %%tmp1
mov %%tmp1, 64
sub %%tmp1, %%read_in_length
shr %%tmp1, 3
add %%next_in, %%tmp1
lea %%read_in_length, [%%read_in_length + 8 * %%tmp1]
%%end:
%endm
;; Load read_in and updated in_buffer accordingly
;; Clobbers rcx, unless rcx is %%read_in_length
%macro inflate_in_small_load 6
%define %%next_in %1
%define %%end_in %2
%define %%read_in %3
%define %%read_in_length %4
%define %%avail_in %5 ; Tmp registers
%define %%tmp1 %5
%define %%loop_count %6
mov %%avail_in, %%end_in
sub %%avail_in, %%next_in
%ifnidn %%read_in_length, rcx
mov rcx, %%read_in_length
%endif
mov %%loop_count, 64
sub %%loop_count, %%read_in_length
shr %%loop_count, 3
cmp %%loop_count, %%avail_in
cmovg %%loop_count, %%avail_in
cmp %%loop_count, 0
je %%end
%%load_byte:
xor %%tmp1, %%tmp1
mov %%tmp1 %+ b, byte [%%next_in]
SHLX %%tmp1, %%tmp1, rcx
or %%read_in, %%tmp1
add rcx, 8
add %%next_in, 1
sub %%loop_count, 1
jg %%load_byte
%ifnidn %%read_in_length, rcx
mov %%read_in_length, rcx
%endif
%%end:
%endm
;; Clears all bits at index %%bit_count and above in %%next_bits
;; May clobber rcx and %%bit_count
%macro CLEAR_HIGH_BITS 3
%define %%next_bits %1
%define %%bit_count %2
%define %%lookup_size %3
sub %%bit_count, 0x40 + %%lookup_size
;; Extract the 15-DECODE_LOOKUP_SIZE bits beyond the first DECODE_LOOKUP_SIZE bits.
%ifdef USE_HSWNI
and %%bit_count, 0x1F
bzhi %%next_bits, %%next_bits, %%bit_count
%else
%ifnidn %%bit_count, rcx
mov rcx, %%bit_count
%endif
neg rcx
shl %%next_bits, cl
shr %%next_bits, cl
%endif
%endm
;; Decode next symbol
;; Clobber rcx
%macro decode_next_lit_len 8
%define %%state %1 ; State structure associated with compressed stream
%define %%lookup_size %2 ; Number of bits used for small lookup
%define %%state_offset %3 ; Type of huff code, should be either LIT or DIST
%define %%read_in %4 ; Bits read in from compressed stream
%define %%read_in_length %5 ; Number of valid bits in read_in
%define %%next_sym %6 ; Returned symbols
%define %%next_sym_num %7 ; Returned symbols count
%define %%next_bits %8
mov %%next_sym_num, %%next_sym
mov rcx, %%next_sym
shr rcx, LARGE_SHORT_CODE_LEN_OFFSET
jz invalid_symbol
and %%next_sym_num, LARGE_SYM_COUNT_MASK << LARGE_SYM_COUNT_OFFSET
shr %%next_sym_num, LARGE_SYM_COUNT_OFFSET
;; Check if symbol or hint was looked up
and %%next_sym, LARGE_FLAG_BIT | LARGE_SHORT_SYM_MASK
test %%next_sym, LARGE_FLAG_BIT
jz %%end
shl rcx, LARGE_SYM_COUNT_LEN
or rcx, %%next_sym_num
;; Save length associated with symbol
mov %%next_bits, %%read_in
shr %%next_bits, %%lookup_size
;; Extract the bits beyond the first %%lookup_size bits.
CLEAR_HIGH_BITS %%next_bits, rcx, %%lookup_size
and %%next_sym, LARGE_SHORT_SYM_MASK
add %%next_sym, %%next_bits
;; Lookup actual next symbol
movzx %%next_sym, word [%%state + LARGE_LONG_CODE_SIZE * %%next_sym + %%state_offset + LARGE_SHORT_CODE_SIZE * (1 << %%lookup_size)]
mov %%next_sym_num, 1
;; Save length associated with symbol
mov rcx, %%next_sym
shr rcx, LARGE_LONG_CODE_LEN_OFFSET
jz invalid_symbol
and %%next_sym, LARGE_LONG_SYM_MASK
%%end:
;; Updated read_in to reflect the bits which were decoded
SHRX %%read_in, %%read_in, rcx
sub %%read_in_length, rcx
%endm
;; Decode next symbol
;; Clobber rcx
%macro decode_next_lit_len_with_load 8
%define %%state %1 ; State structure associated with compressed stream
%define %%lookup_size %2 ; Number of bits used for small lookup
%define %%state_offset %3
%define %%read_in %4 ; Bits read in from compressed stream
%define %%read_in_length %5 ; Number of valid bits in read_in
%define %%next_sym %6 ; Returned symbols
%define %%next_sym_num %7 ; Returned symbols count
%define %%next_bits %8
;; Lookup possible next symbol
mov %%next_bits, %%read_in
and %%next_bits, (1 << %%lookup_size) - 1
mov %%next_sym %+ d, dword [%%state + %%state_offset + LARGE_SHORT_CODE_SIZE * %%next_bits]
decode_next_lit_len %%state, %%lookup_size, %%state_offset, %%read_in, %%read_in_length, %%next_sym, %%next_sym_num, %%next_bits
%endm
;; Decode next symbol
;; Clobber rcx
%macro decode_next_dist 8
%define %%state %1 ; State structure associated with compressed stream
%define %%lookup_size %2 ; Number of bits used for small lookup
%define %%state_offset %3 ; Type of huff code, should be either LIT or DIST
%define %%read_in %4 ; Bits read in from compressed stream
%define %%read_in_length %5 ; Number of valid bits in read_in
%define %%next_sym %6 ; Returned symobl
%define %%next_extra_bits %7
%define %%next_bits %8
mov rcx, %%next_sym
shr rcx, SMALL_SHORT_CODE_LEN_OFFSET
jz invalid_dist_symbol_ %+ %%next_sym
;; Check if symbol or hint was looked up
and %%next_sym, SMALL_FLAG_BIT | SMALL_SHORT_SYM_MASK
test %%next_sym, SMALL_FLAG_BIT
jz %%end
;; Save length associated with symbol
mov %%next_bits, %%read_in
shr %%next_bits, %%lookup_size
;; Extract the 15-DECODE_LOOKUP_SIZE bits beyond the first %%lookup_size bits.
lea %%next_sym, [%%state + SMALL_LONG_CODE_SIZE * %%next_sym]
CLEAR_HIGH_BITS %%next_bits, rcx, %%lookup_size
;; Lookup actual next symbol
movzx %%next_sym, word [%%next_sym + %%state_offset + SMALL_LONG_CODE_SIZE * %%next_bits + SMALL_SHORT_CODE_SIZE * (1 << %%lookup_size) - SMALL_LONG_CODE_SIZE * SMALL_FLAG_BIT]
;; Save length associated with symbol
mov rcx, %%next_sym
shr rcx, SMALL_LONG_CODE_LEN_OFFSET
jz invalid_dist_symbol_ %+ %%next_sym
and %%next_sym, SMALL_SHORT_SYM_MASK
%%end:
;; Updated read_in to reflect the bits which were decoded
SHRX %%read_in, %%read_in, rcx
sub %%read_in_length, rcx
mov rcx, %%next_sym
shr rcx, DIST_SYM_EXTRA_OFFSET
and %%next_sym, DIST_SYM_MASK
%endm
;; Decode next symbol
;; Clobber rcx
%macro decode_next_dist_with_load 8
%define %%state %1 ; State structure associated with compressed stream
%define %%lookup_size %2 ; Number of bits used for small lookup
%define %%state_offset %3
%define %%read_in %4 ; Bits read in from compressed stream
%define %%read_in_length %5 ; Number of valid bits in read_in
%define %%next_sym %6 ; Returned symobl
%define %%next_extra_bits %7
%define %%next_bits %8
;; Lookup possible next symbol
mov %%next_bits, %%read_in
and %%next_bits, (1 << %%lookup_size) - 1
movzx %%next_sym, word [%%state + %%state_offset + SMALL_SHORT_CODE_SIZE * %%next_bits]
decode_next_dist %%state, %%lookup_size, %%state_offset, %%read_in, %%read_in_length, %%next_sym, %%next_extra_bits, %%next_bits
%endm
[bits 64]
default rel
section .text
global decode_huffman_code_block_stateless_ %+ ARCH
decode_huffman_code_block_stateless_ %+ ARCH %+ :
endbranch
FUNC_SAVE
mov state, arg0
mov [rsp + start_out_mem_offset], arg1
lea rfc_lookup, [rfc1951_lookup_table]
mov read_in,[state + _read_in]
mov read_in_length %+ d, dword [state + _read_in_length]
mov next_out, [state + _next_out]
mov end_out %+ d, dword [state + _avail_out]
add end_out, next_out
mov next_in, [state + _next_in]
mov end_in %+ d, dword [state + _avail_in]
add end_in, next_in
mov dword [state + _copy_overflow_len], 0
mov dword [state + _copy_overflow_dist], 0
sub end_out, OUT_BUFFER_SLOP
sub end_in, IN_BUFFER_SLOP
cmp next_in, end_in
jg end_loop_block_pre
cmp read_in_length, 64
je skip_load
inflate_in_load next_in, end_in, read_in, read_in_length, tmp1, tmp2
skip_load:
mov tmp3, read_in
and tmp3, (1 << ISAL_DECODE_LONG_BITS) - 1
mov next_sym %+ d, dword [state + _lit_huff_code + LARGE_SHORT_CODE_SIZE * tmp3]
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Main Loop
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
loop_block:
;; Check if near end of in buffer or out buffer
cmp next_in, end_in
jg end_loop_block_pre
cmp next_out, end_out
jg end_loop_block_pre
;; Decode next symbol and reload the read_in buffer
decode_next_lit_len state, ISAL_DECODE_LONG_BITS, _lit_huff_code, read_in, read_in_length, next_sym, next_sym_num, tmp1
;; Specutively write next_sym if it is a literal
mov [next_out], next_sym
add next_out, next_sym_num
lea next_sym2, [8 * next_sym_num - 8]
SHRX next_sym2, next_sym, next_sym2
;; Find index to specutively preload next_sym from
mov tmp3, (1 << ISAL_DECODE_LONG_BITS) - 1
and tmp3, read_in
;; Start reloading read_in
mov tmp1, [next_in]
SHLX tmp1, tmp1, read_in_length
or read_in, tmp1
;; Specutively load data associated with length symbol
lea repeat_length, [next_sym2 - 254]
;; Test for end of block symbol
cmp next_sym2, 256
je end_symbol_pre
;; Specutively load next_sym for next loop if a literal was decoded
mov next_sym %+ d, dword [state + _lit_huff_code + LARGE_SHORT_CODE_SIZE * tmp3]
;; Finish updating read_in_length for read_in
mov tmp1, 64
sub tmp1, read_in_length
shr tmp1, 3
add next_in, tmp1
lea read_in_length, [read_in_length + 8 * tmp1]
;; Specultively load next dist code
mov next_bits2, (1 << ISAL_DECODE_SHORT_BITS) - 1
and next_bits2, read_in
movzx next_sym3, word [state + _dist_huff_code + SMALL_SHORT_CODE_SIZE * next_bits2]
;; Check if next_sym2 is a literal, length, or end of block symbol
cmp next_sym2, 256
jl loop_block
decode_len_dist:
;; Determine next_out after the copy is finished
lea next_out, [next_out + repeat_length - 1]
;; Decode distance code
decode_next_dist state, ISAL_DECODE_SHORT_BITS, _dist_huff_code, read_in, read_in_length, next_sym3, rcx, tmp2
mov look_back_dist2 %+ d, [rfc_lookup + _dist_start + 4 * next_sym3]
; ;; Load distance code extra bits
mov next_bits, read_in
;; Calculate the look back distance
BZHI next_bits, next_bits, rcx, tmp4
SHRX read_in, read_in, rcx
;; Setup next_sym, read_in, and read_in_length for next loop
mov read_in_2, (1 << ISAL_DECODE_LONG_BITS) - 1
and read_in_2, read_in
mov next_sym %+ d, dword [state + _lit_huff_code + LARGE_SHORT_CODE_SIZE * read_in_2]
sub read_in_length, rcx
;; Copy distance in len/dist pair
add look_back_dist2, next_bits
;; Find beginning of copy
mov copy_start, next_out
sub copy_start, repeat_length
sub copy_start, look_back_dist2
;; Check if a valid look back distances was decoded
cmp copy_start, [rsp + start_out_mem_offset]
jl invalid_look_back_distance
MOVDQU xmm1, [copy_start]
;; Set tmp2 to be the minimum of COPY_SIZE and repeat_length
;; This is to decrease use of small_byte_copy branch
mov tmp2, COPY_SIZE
cmp tmp2, repeat_length
cmovg tmp2, repeat_length
;; Check for overlapping memory in the copy
cmp look_back_dist2, tmp2
jl small_byte_copy_pre
large_byte_copy:
;; Copy length distance pair when memory overlap is not an issue
MOVDQU [copy_start + look_back_dist2], xmm1
sub repeat_length, COPY_SIZE
jle loop_block
add copy_start, COPY_SIZE
MOVDQU xmm1, [copy_start]
jmp large_byte_copy
small_byte_copy_pre:
;; Copy length distance pair when source and destination overlap
add repeat_length, look_back_dist2
small_byte_copy:
MOVDQU [copy_start + look_back_dist2], xmm1
shl look_back_dist2, 1
MOVDQU xmm1, [copy_start]
cmp look_back_dist2, COPY_SIZE
jl small_byte_copy
sub repeat_length, look_back_dist2
jge large_byte_copy
jmp loop_block
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Finish Main Loop
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
end_loop_block_pre:
;; Fix up in buffer and out buffer to reflect the actual buffer end
add end_out, OUT_BUFFER_SLOP
add end_in, IN_BUFFER_SLOP
end_loop_block:
;; Load read in buffer and decode next lit/len symbol
inflate_in_small_load next_in, end_in, read_in, read_in_length, tmp1, tmp2
mov [rsp + read_in_mem_offset], read_in
mov [rsp + read_in_length_mem_offset], read_in_length
mov [rsp + next_out_mem_offset], next_out
decode_next_lit_len_with_load state, ISAL_DECODE_LONG_BITS, _lit_huff_code, read_in, read_in_length, next_sym, next_sym_num, tmp1
;; Check that enough input was available to decode symbol
cmp read_in_length, 0
jl end_of_input
multi_symbol_start:
cmp next_sym_num, 1
jg decode_literal
cmp next_sym, 256
jl decode_literal
je end_symbol
decode_len_dist_2:
lea repeat_length, [next_sym - 254]
;; Decode distance code
decode_next_dist_with_load state, ISAL_DECODE_SHORT_BITS, _dist_huff_code, read_in, read_in_length, next_sym, rcx, tmp1
;; Load distance code extra bits
mov next_bits, read_in
mov look_back_dist %+ d, [rfc_lookup + _dist_start + 4 * next_sym]
;; Calculate the look back distance and check for enough input
BZHI next_bits, next_bits, rcx, tmp1
SHRX read_in, read_in, rcx
add look_back_dist, next_bits
sub read_in_length, rcx
jl end_of_input
;; Setup code for byte copy using rep movsb
mov rsi, next_out
mov rdi, rsi
mov rcx, repeat_length
sub rsi, look_back_dist
;; Check if a valid look back distance was decoded
cmp rsi, [rsp + start_out_mem_offset]
jl invalid_look_back_distance
;; Check for out buffer overflow
add repeat_length, next_out
cmp repeat_length, end_out
jg out_buffer_overflow_repeat
mov next_out, repeat_length
rep movsb
jmp end_loop_block
decode_literal:
;; Store literal decoded from the input stream
cmp next_out, end_out
jge out_buffer_overflow_lit
add next_out, 1
mov byte [next_out - 1], next_sym %+ b
sub next_sym_num, 1
jz end_loop_block
shr next_sym, 8
jmp multi_symbol_start
;; Set exit codes
end_of_input:
mov read_in, [rsp + read_in_mem_offset]
mov read_in_length, [rsp + read_in_length_mem_offset]
mov next_out, [rsp + next_out_mem_offset]
xor tmp1, tmp1
mov dword [state + _write_overflow_lits], tmp1 %+ d
mov dword [state + _write_overflow_len], tmp1 %+ d
mov rax, END_INPUT
jmp end
out_buffer_overflow_repeat:
mov rcx, end_out
sub rcx, next_out
sub repeat_length, rcx
sub repeat_length, next_out
rep movsb
mov [state + _copy_overflow_len], repeat_length %+ d
mov [state + _copy_overflow_dist], look_back_dist %+ d
mov next_out, end_out
mov rax, OUT_OVERFLOW
jmp end
out_buffer_overflow_lit:
mov dword [state + _write_overflow_lits], next_sym %+ d
mov dword [state + _write_overflow_len], next_sym_num %+ d
sub next_sym_num, 1
shl next_sym_num, 3
SHRX next_sym, next_sym, next_sym_num
mov rax, OUT_OVERFLOW
shr next_sym_num, 3
cmp next_sym, 256
jl end
mov dword [state + _write_overflow_len], next_sym_num %+ d
jg decode_len_dist_2
jmp end_state
invalid_look_back_distance:
mov rax, INVALID_LOOKBACK
jmp end
invalid_dist_symbol_ %+ next_sym:
cmp read_in_length, next_sym
jl end_of_input
jmp invalid_symbol
invalid_dist_symbol_ %+ next_sym3:
cmp read_in_length, next_sym3
jl end_of_input
invalid_symbol:
mov rax, INVALID_SYMBOL
jmp end
end_symbol_pre:
;; Fix up in buffer and out buffer to reflect the actual buffer
sub next_out, 1
add end_out, OUT_BUFFER_SLOP
add end_in, IN_BUFFER_SLOP
end_symbol:
xor rax, rax
end_state:
;; Set flag identifying a new block is required
mov byte [state + _block_state], ISAL_BLOCK_NEW_HDR
cmp dword [state + _bfinal], 0
je end
mov byte [state + _block_state], ISAL_BLOCK_INPUT_DONE
end:
;; Save current buffer states
mov [state + _read_in], read_in
mov [state + _read_in_length], read_in_length %+ d
;; Set avail_out
sub end_out, next_out
mov dword [state + _avail_out], end_out %+ d
;; Set total_out
mov tmp1, next_out
sub tmp1, [state + _next_out]
add [state + _total_out], tmp1 %+ d
;; Set next_out
mov [state + _next_out], next_out
;; Set next_in
mov [state + _next_in], next_in
;; Set avail_in
sub end_in, next_in
mov [state + _avail_in], end_in %+ d
FUNC_RESTORE
ret
| Intel-HLS/GKL | src/main/native/compression/isa-l-master/igzip/igzip_decode_block_stateless.asm | Assembly | mit | 22,135 |
org 0100h
BaseOfStack equ 0100h
BaseOfKernelFile equ 08000h ; KERNEL.BIN 被加载到的位置 ---- 段地址
OffsetOfKernelFile equ 0h ; KERNEL.BIN 被加载到的位置 ---- 偏移地址
jmp LABEL_START ; Start
; 下面是 FAT12 磁盘的头, 之所以包含它是因为下面用到了磁盘的一些信息
%include "fat12hdr.inc"
LABEL_START: ; <--- 从这里开始 *************
mov ax, cs
mov ds, ax
mov es, ax
mov ss, ax
mov sp, BaseOfStack
mov dh, 0 ; "Loading "
call DispStr ; 显示字符串
; 下面在 A 盘的根目录寻找 KERNEL.BIN
mov word [wSectorNo], SectorNoOfRootDirectory
xor ah, ah ; `.
xor dl, dl ; | 软驱复位
int 13h ; /
LABEL_SEARCH_IN_ROOT_DIR_BEGIN:
cmp word [wRootDirSizeForLoop], 0 ; `.
jz LABEL_NO_KERNELBIN ; | 判断根目录区是不是已经读完,
dec word [wRootDirSizeForLoop] ; / 读完表示没有找到 KERNEL.BIN
mov ax, BaseOfKernelFile
mov es, ax ; es <- BaseOfKernelFile
mov bx, OffsetOfKernelFile ; bx <- OffsetOfKernelFile
mov ax, [wSectorNo] ; ax <- Root Directory 中的某 Sector 号
mov cl, 1
call ReadSector
mov si, KernelFileName ; ds:si -> "KERNEL BIN"
mov di, OffsetOfKernelFile
cld
mov dx, 10h
LABEL_SEARCH_FOR_KERNELBIN:
cmp dx, 0 ; `.
jz LABEL_GOTO_NEXT_SECTOR_IN_ROOT_DIR; | 循环次数控制, 如果已经读完
dec dx ; / 了一个 Sector, 就跳到下一个
mov cx, 11
LABEL_CMP_FILENAME:
cmp cx, 0 ; `.
jz LABEL_FILENAME_FOUND ; | 循环次数控制, 如果比较了 11 个字符都
dec cx ; / 相等, 表示找到
lodsb ; ds:si -> al
cmp al, byte [es:di] ; if al == es:di
jz LABEL_GO_ON
jmp LABEL_DIFFERENT
LABEL_GO_ON:
inc di
jmp LABEL_CMP_FILENAME ; 继续循环
LABEL_DIFFERENT:
and di, 0FFE0h ; else`. 让 di 是 20h 的倍数
add di, 20h ; |
mov si, KernelFileName ; | di += 20h 下一个目录条目
jmp LABEL_SEARCH_FOR_KERNELBIN; /
LABEL_GOTO_NEXT_SECTOR_IN_ROOT_DIR:
add word [wSectorNo], 1
jmp LABEL_SEARCH_IN_ROOT_DIR_BEGIN
LABEL_NO_KERNELBIN:
mov dh, 2 ; "No KERNEL."
call DispStr ; 显示字符串
%ifdef _LOADER_DEBUG_
mov ax, 4c00h ; `.
int 21h ; / 没有找到 KERNEL.BIN, 回到 DOS
%else
jmp $ ; 没有找到 KERNEL.BIN, 死循环在这里
%endif
LABEL_FILENAME_FOUND: ; 找到 KERNEL.BIN 后便来到这里继续
mov ax, RootDirSectors
and di, 0FFF0h ; di -> 当前条目的开始
push eax
mov eax, [es : di + 01Ch] ; `.
mov dword [dwKernelSize], eax ; / 保存 KERNEL.BIN 文件大小
pop eax
add di, 01Ah ; di -> 首 Sector
mov cx, word [es:di]
push cx ; 保存此 Sector 在 FAT 中的序号
add cx, ax
add cx, DeltaSectorNo ; cl <- LOADER.BIN 的起始扇区号(0-based)
mov ax, BaseOfKernelFile
mov es, ax ; es <- BaseOfKernelFile
mov bx, OffsetOfKernelFile ; bx <- OffsetOfKernelFile
mov ax, cx ; ax <- Sector 号
LABEL_GOON_LOADING_FILE:
push ax ; `.
push bx ; |
mov ah, 0Eh ; | 每读一个扇区就在 "Loading " 后面
mov al, '.' ; | 打一个点, 形成这样的效果:
mov bl, 0Fh ; | Loading ......
int 10h ; |
pop bx ; |
pop ax ; /
mov cl, 1
call ReadSector
pop ax ; 取出此 Sector 在 FAT 中的序号
call GetFATEntry
cmp ax, 0FFFh
jz LABEL_FILE_LOADED
push ax ; 保存 Sector 在 FAT 中的序号
mov dx, RootDirSectors
add ax, dx
add ax, DeltaSectorNo
add bx, [BPB_BytsPerSec]
jmp LABEL_GOON_LOADING_FILE
LABEL_FILE_LOADED:
call KillMotor ; 关闭软驱马达
mov dh, 1 ; "Ready."
call DispStr ; 显示字符串
jmp $
;============================================================================
;变量
;----------------------------------------------------------------------------
wRootDirSizeForLoop dw RootDirSectors ; Root Directory 占用的扇区数
wSectorNo dw 0 ; 要读取的扇区号
bOdd db 0 ; 奇数还是偶数
dwKernelSize dd 0 ; KERNEL.BIN 文件大小
;============================================================================
;字符串
;----------------------------------------------------------------------------
KernelFileName db "KERNEL BIN", 0 ; KERNEL.BIN 之文件名
; 为简化代码, 下面每个字符串的长度均为 MessageLength
MessageLength equ 9
LoadMessage: db "Loading "
Message1 db "Ready. "
Message2 db "No KERNEL"
;============================================================================
;----------------------------------------------------------------------------
; 函数名: DispStr
;----------------------------------------------------------------------------
; 作用:
; 显示一个字符串, 函数开始时 dh 中应该是字符串序号(0-based)
DispStr:
mov ax, MessageLength
mul dh
add ax, LoadMessage
mov bp, ax ; ┓
mov ax, ds ; ┣ ES:BP = 串地址
mov es, ax ; ┛
mov cx, MessageLength ; CX = 串长度
mov ax, 01301h ; AH = 13, AL = 01h
mov bx, 0007h ; 页号为0(BH = 0) 黑底白字(BL = 07h)
mov dl, 0
add dh, 3 ; 从第 3 行往下显示
int 10h ; int 10h
ret
;----------------------------------------------------------------------------
; 函数名: ReadSector
;----------------------------------------------------------------------------
; 作用:
; 从序号(Directory Entry 中的 Sector 号)为 ax 的的 Sector 开始, 将 cl 个 Sector 读入 es:bx 中
ReadSector:
; -----------------------------------------------------------------------
; 怎样由扇区号求扇区在磁盘中的位置 (扇区号 -> 柱面号, 起始扇区, 磁头号)
; -----------------------------------------------------------------------
; 设扇区号为 x
; ┌ 柱面号 = y >> 1
; x ┌ 商 y ┤
; -------------- => ┤ └ 磁头号 = y & 1
; 每磁道扇区数 │
; └ 余 z => 起始扇区号 = z + 1
push bp
mov bp, sp
sub esp, 2 ; 辟出两个字节的堆栈区域保存要读的扇区数: byte [bp-2]
mov byte [bp-2], cl
push bx ; 保存 bx
mov bl, [BPB_SecPerTrk] ; bl: 除数
div bl ; y 在 al 中, z 在 ah 中
inc ah ; z ++
mov cl, ah ; cl <- 起始扇区号
mov dh, al ; dh <- y
shr al, 1 ; y >> 1 (其实是 y/BPB_NumHeads, 这里BPB_NumHeads=2)
mov ch, al ; ch <- 柱面号
and dh, 1 ; dh & 1 = 磁头号
pop bx ; 恢复 bx
; 至此, "柱面号, 起始扇区, 磁头号" 全部得到 ^^^^^^^^^^^^^^^^^^^^^^^^
mov dl, [BS_DrvNum] ; 驱动器号 (0 表示 A 盘)
.GoOnReading:
mov ah, 2 ; 读
mov al, byte [bp-2] ; 读 al 个扇区
int 13h
jc .GoOnReading ; 如果读取错误 CF 会被置为 1, 这时就不停地读, 直到正确为止
add esp, 2
pop bp
ret
;----------------------------------------------------------------------------
; 函数名: GetFATEntry
;----------------------------------------------------------------------------
; 作用:
; 找到序号为 ax 的 Sector 在 FAT 中的条目, 结果放在 ax 中
; 需要注意的是, 中间需要读 FAT 的扇区到 es:bx 处, 所以函数一开始保存了 es 和 bx
GetFATEntry:
push es
push bx
push ax
mov ax, BaseOfKernelFile ; ┓
sub ax, 0100h ; ┣ 在 BaseOfKernelFile 后面留出 4K 空间用于存放 FAT
mov es, ax ; ┛
pop ax
mov byte [bOdd], 0
mov bx, 3
mul bx ; dx:ax = ax * 3
mov bx, 2
div bx ; dx:ax / 2 ==> ax <- 商, dx <- 余数
cmp dx, 0
jz LABEL_EVEN
mov byte [bOdd], 1
LABEL_EVEN:;偶数
xor dx, dx ; 现在 ax 中是 FATEntry 在 FAT 中的偏移量. 下面来计算 FATEntry 在哪个扇区中(FAT占用不止一个扇区)
mov bx, [BPB_BytsPerSec]
div bx ; dx:ax / BPB_BytsPerSec ==> ax <- 商 (FATEntry 所在的扇区相对于 FAT 来说的扇区号)
; dx <- 余数 (FATEntry 在扇区内的偏移)。
push dx
mov bx, 0 ; bx <- 0 于是, es:bx = (BaseOfKernelFile - 100):00 = (BaseOfKernelFile - 100) * 10h
add ax, SectorNoOfFAT1 ; 此句执行之后的 ax 就是 FATEntry 所在的扇区号
mov cl, 2
call ReadSector ; 读取 FATEntry 所在的扇区, 一次读两个, 避免在边界发生错误, 因为一个 FATEntry 可能跨越两个扇区
pop dx
add bx, dx
mov ax, [es:bx]
cmp byte [bOdd], 1
jnz LABEL_EVEN_2
shr ax, 4
LABEL_EVEN_2:
and ax, 0FFFh
LABEL_GET_FAT_ENRY_OK:
pop bx
pop es
ret
;----------------------------------------------------------------------------
;----------------------------------------------------------------------------
; 函数名: KillMotor
;----------------------------------------------------------------------------
; 作用:
; 关闭软驱马达
KillMotor:
push dx
mov dx, 03F2h
mov al, 0
out dx, al
pop dx
ret
;----------------------------------------------------------------------------
| RongbinZhuang/simpleOS | ver0/reference/chapter5/c/loader.asm | Assembly | mit | 8,676 |
_text segment para public 'CODE' use32
sub_test proc near
push ebp
mov ebp, esp
call fastcall_func
and eax, 0
pop ebp
retn
sub_test endp
_text ends
; vim:expandtab
| notaz/ia32rtools | tests/reg_call1.asm | Assembly | bsd-3-clause | 316 |
INCLUDE "hardware.inc"
INCLUDE "header.inc"
SECTION "Main",HOME
;--------------------------------------------------------------------------
;- Main() -
;--------------------------------------------------------------------------
Main:
ld a,$00
ld [rP1],a
ld a,$0A
ld [$0000],a
ld hl,$A000
VALUE SET 0
REPT 256
db $10 ; stop
db VALUE
ld a,VALUE
ld [hl+],a
push hl
ld [hl],$12
inc hl
ld [hl],$12
inc hl
ld [hl],$12
inc hl
ld [hl],$12
pop hl
VALUE SET VALUE+1
ENDR
ld a,$00
ld [$0000],a
;--------------------------------
.endloop:
halt
jr .endloop
| AntonioND/gbc-hw-tests | cpu/corrupted_stop_2/main.asm | Assembly | mit | 662 |
; Zadanie [VM:not-so-simple-calc]
; Autor: Adam Bac (abac00s)
;
;The MIT License (MIT)
;Copyright (c) 2016 Adam Bac
;
;Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation file
;(the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge,
;publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do
;so, subject to the following conditions:
;
;The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;
;THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
;MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
;FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
;WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
%include "vm.inc"
vxor r2, r2
;1 komunikat ---------------------------------
vset r0, com1
vset r1, 1
vxor r3, r3
loop1:
vldb r2, r0
vcmp r2, r3
vje endloop1
voutb 0x20, r2
vadd r0, r1
vjmp loop1
endloop1:
;---------------------------------------------
;wczytaj 1 liczbe ----------------------------
vxor r3, r3
loop2:
vinb 0x21, r2
vcmp r2, r3
vje loop2
vxor r10, r10
vset r3, 0xa
vset r1, 0x30
vset r4, 10
loop3:
vinb 0x20, r2
vcmp r2, r3
vje endloop3
vsub r2, r1
vmul r10, r4
vadd r10, r2
vjmp loop3
endloop3:
;---------------------------------------------
;2 komunikat ---------------------------------
vset r0, com2
vset r1, 1
vxor r3, r3
loop4:
vldb r2, r0
vcmp r2, r3
vje endloop4
voutb 0x20, r2
vadd r0, r1
vjmp loop4
endloop4:
;---------------------------------------------
;wczytaj 2 liczbe ----------------------------
vxor r3, r3
loop5:
vinb 0x21, r2
vcmp r2, r3
vje loop5
vxor r11, r11
vset r3, 0xa
vset r1, 0x30
vset r4, 10
loop6:
vinb 0x20, r2
vcmp r2, r3
vje endloop6
vsub r2, r1
vmul r11, r4
vadd r11, r2
vjmp loop6
endloop6:
;---------------------------------------------
vadd r10, r11
;wypisz wynik --------------------------------
vset r0, wynik
vset r4, 10
vset r5, 1
vxor r3, r3
loop7:
vmov r2, r10
vmod r2, r4
vadd r2, r1
vstb r0, r2
vadd r0, r5
vdiv r10, r4
vcmp r10, r3
vjne loop7
vsub r0, r5
vxor r2, r2
loop8:
vldb r2, r0
vsub r0, r5
vcmp r2, r3
vje endloop8
voutb 0x20, r2
vjmp loop8
endloop8:
vset r2, 0xa
voutb 0x20, r2
;---------------------------------------------
voff
com1:
db "Podaj pierwszą liczbe: ", 0
com2:
db "Podaj drugą liczbe: ", 0
;tu przygotowywany jest wynik (zakladam max 10 cyfr)
wynik:
times 10 db 0
| gynvael/zrozumiec-programowanie-cwiczenia | VM-not-so-simple-calc/abac00s/VM-not-so-simple-calc.asm | Assembly | mit | 2,867 |
@ This file was created from a .asm file
@ using the ads2gas.pl script.
.equ DO1STROUNDING, 0
.equ ARCH_ARM , 1
.equ ARCH_MIPS , 0
.equ ARCH_X86 , 0
.equ ARCH_X86_64 , 0
.equ HAVE_EDSP , 0
.equ HAVE_MEDIA , 1
.equ HAVE_NEON , 0
.equ HAVE_NEON_ASM , 0
.equ HAVE_MIPS32 , 0
.equ HAVE_DSPR2 , 0
.equ HAVE_MSA , 0
.equ HAVE_MIPS64 , 0
.equ HAVE_MMX , 0
.equ HAVE_SSE , 0
.equ HAVE_SSE2 , 0
.equ HAVE_SSE3 , 0
.equ HAVE_SSSE3 , 0
.equ HAVE_SSE4_1 , 0
.equ HAVE_AVX , 0
.equ HAVE_AVX2 , 0
.equ HAVE_VPX_PORTS , 1
.equ HAVE_STDINT_H , 1
.equ HAVE_PTHREAD_H , 1
.equ HAVE_SYS_MMAN_H , 1
.equ HAVE_UNISTD_H , 0
.equ CONFIG_DEPENDENCY_TRACKING , 1
.equ CONFIG_EXTERNAL_BUILD , 1
.equ CONFIG_INSTALL_DOCS , 0
.equ CONFIG_INSTALL_BINS , 0
.equ CONFIG_INSTALL_LIBS , 0
.equ CONFIG_INSTALL_SRCS , 0
.equ CONFIG_USE_X86INC , 0
.equ CONFIG_DEBUG , 0
.equ CONFIG_GPROF , 0
.equ CONFIG_GCOV , 0
.equ CONFIG_RVCT , 0
.equ CONFIG_GCC , 1
.equ CONFIG_MSVS , 0
.equ CONFIG_PIC , 1
.equ CONFIG_BIG_ENDIAN , 0
.equ CONFIG_CODEC_SRCS , 0
.equ CONFIG_DEBUG_LIBS , 0
.equ CONFIG_DEQUANT_TOKENS , 0
.equ CONFIG_DC_RECON , 0
.equ CONFIG_RUNTIME_CPU_DETECT , 0
.equ CONFIG_POSTPROC , 1
.equ CONFIG_VP9_POSTPROC , 1
.equ CONFIG_MULTITHREAD , 1
.equ CONFIG_INTERNAL_STATS , 0
.equ CONFIG_VP8_ENCODER , 1
.equ CONFIG_VP8_DECODER , 1
.equ CONFIG_VP9_ENCODER , 1
.equ CONFIG_VP9_DECODER , 1
.equ CONFIG_VP10_ENCODER , 0
.equ CONFIG_VP10_DECODER , 0
.equ CONFIG_VP8 , 1
.equ CONFIG_VP9 , 1
.equ CONFIG_VP10 , 0
.equ CONFIG_ENCODERS , 1
.equ CONFIG_DECODERS , 1
.equ CONFIG_STATIC_MSVCRT , 0
.equ CONFIG_SPATIAL_RESAMPLING , 1
.equ CONFIG_REALTIME_ONLY , 1
.equ CONFIG_ONTHEFLY_BITPACKING , 0
.equ CONFIG_ERROR_CONCEALMENT , 0
.equ CONFIG_SHARED , 0
.equ CONFIG_STATIC , 1
.equ CONFIG_SMALL , 0
.equ CONFIG_POSTPROC_VISUALIZER , 0
.equ CONFIG_OS_SUPPORT , 1
.equ CONFIG_UNIT_TESTS , 0
.equ CONFIG_WEBM_IO , 1
.equ CONFIG_LIBYUV , 1
.equ CONFIG_DECODE_PERF_TESTS , 0
.equ CONFIG_ENCODE_PERF_TESTS , 0
.equ CONFIG_MULTI_RES_ENCODING , 1
.equ CONFIG_TEMPORAL_DENOISING , 1
.equ CONFIG_VP9_TEMPORAL_DENOISING , 1
.equ CONFIG_COEFFICIENT_RANGE_CHECKING , 0
.equ CONFIG_VP9_HIGHBITDEPTH , 0
.equ CONFIG_EXPERIMENTAL , 0
.equ CONFIG_SIZE_LIMIT , 1
.equ CONFIG_SPATIAL_SVC , 0
.equ CONFIG_FP_MB_STATS , 0
.equ CONFIG_EMULATE_HARDWARE , 0
.equ DECODE_WIDTH_LIMIT , 16384
.equ DECODE_HEIGHT_LIMIT , 16384
.section .note.GNU-stack,"",%progbits
| Teamxrtc/webrtc-streaming-node | third_party/webrtc/src/chromium/src/third_party/libvpx/source/config/linux/arm/vpx_config.asm | Assembly | mit | 2,486 |
;;================================================================================================;;
;;//// ico.asm //// (c) mike.dld, 2007-2008, (c) diamond, 2009 ///////////////////////////////////;;
;;================================================================================================;;
;; ;;
;; This file is part of Common development libraries (Libs-Dev). ;;
;; ;;
;; Libs-Dev is free software: you can redistribute it and/or modify it under the terms of the GNU ;;
;; Lesser General Public License as published by the Free Software Foundation, either version 2.1 ;;
;; of the License, or (at your option) any later version. ;;
;; ;;
;; Libs-Dev is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without ;;
;; even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ;;
;; Lesser General Public License for more details. ;;
;; ;;
;; You should have received a copy of the GNU Lesser General Public License along with Libs-Dev. ;;
;; If not, see <http://www.gnu.org/licenses/>. ;;
;; ;;
;;================================================================================================;;
;; ;;
;; References: ;;
;; 1. "Icons in Win32" ;;
;; by John Hornick, Microsoft Corporation ;;
;; http://msdn2.microsoft.com/en-us/library/ms997538.aspx ;;
;; ;;
;;================================================================================================;;
include 'ico_cur.inc'
;;================================================================================================;;
;;proc img.is.ico _data, _length ;////////////////////////////////////////////////////////////////;;
img.is.ico:
mov edx, 0x00010000 ; icon type = 1
jmp @f
img.is.cur:
mov edx, 0x00020000 ; cursor type = 2
@@:
;;------------------------------------------------------------------------------------------------;;
;? Determine if raw data could be decoded (is in ICO format) ;;
;;------------------------------------------------------------------------------------------------;;
;> _data = raw data as read from file/stream ;;
;> _length = data length ;;
;;------------------------------------------------------------------------------------------------;;
;< eax = false / true ;;
;;================================================================================================;;
; test 1 (length of data): data must contain FileHeader
mov ecx, [esp+8]
sub ecx, sizeof.ico.FileHeader
jb .nope
; test 2: signature
mov eax, [esp+4]
cmp dword [eax], edx ; Reserved & Type
jne .nope
; test 3: count must be non-zero
movzx eax, [eax + ico.FileHeader.Count]
test eax, eax
jz .nope
; test 4 (length of data): data must containt Count dir entries
shl eax, 4
sub ecx, eax
jae .yep
.nope:
xor eax, eax
ret 8
.yep:
xor eax, eax
inc eax
ret 8
;endp
;;================================================================================================;;
proc img.decode.ico_cur _data, _length, _options ;////////////////////////////////////////////////;;
;;------------------------------------------------------------------------------------------------;;
;? Decode data into image if it contains correctly formed raw data in ICO/CUR format ;;
;;------------------------------------------------------------------------------------------------;;
;> _data = raw data as read from file/stream ;;
;> _length = data length ;;
;> _options = options for decoding (e.g. background color) ;;
;;------------------------------------------------------------------------------------------------;;
;< eax = 0 (error) or pointer to image ;;
;;================================================================================================;;
locals
count dd ?
img dd ?
main_img dd ?
endl
push ebx esi edi
; img.is.ico has been already called by img.decode
; stdcall img.is.ico, [_data], [_length]
; or eax, eax
; jz .error
mov ebx, [_data]
movzx eax, [ebx + ico.FileHeader.Count]
mov [count], eax
and [img], 0
and [main_img], 0
.loop:
mov ecx, [ebx + sizeof.ico.FileHeader + ico.DirEntry.ByteSize]
mov edx, [ebx + sizeof.ico.FileHeader + ico.DirEntry.ImageOffset]
mov eax, [_length]
sub eax, edx
jb .skip
cmp eax, ecx
jb .skip
cmp ecx, 12 ; length test, see img.is.bmp
jb .skip
add edx, [_data]
push [_options]
push ecx
push edx
call img.decode.ico._.decode_icon_data
test eax, eax
jz .skip
push 0xFFFFFF ; set bgr to white if no given
mov edx, [_options]
test edx, edx
jz @f
cmp [edx + ImageDecodeOptions.UsedSize], ImageDecodeOptions.BackgroundColor + 4
jb @f
add esp, 4
push [edx + ImageDecodeOptions.BackgroundColor]
@@:
call img.decode.ico._.decode_icon_mask
test eax, eax
jz .skip
mov edx, [img]
test edx, edx
jz .first
mov [edx + Image.Next], eax
mov [eax + Image.Previous], edx
jmp @f
.first:
mov [main_img], eax
@@:
mov [img], eax
.skip:
add ebx, sizeof.ico.DirEntry
dec [count]
jnz .loop
mov eax, [main_img]
pop edi esi ebx
ret
endp
;;================================================================================================;;
img.encode.cur:
proc img.encode.ico _img, _p_length, _options ;///////////////////////////////////////////////////;;
;;------------------------------------------------------------------------------------------------;;
;? Encode image into raw data in ICO format ;;
;;------------------------------------------------------------------------------------------------;;
;> _img = pointer to image ;;
;;------------------------------------------------------------------------------------------------;;
;< eax = 0 (error) or pointer to encoded data ;;
;< _p_length = encoded data length ;;
;;================================================================================================;;
xor eax, eax
ret
endp
;;================================================================================================;;
;;////////////////////////////////////////////////////////////////////////////////////////////////;;
;;================================================================================================;;
;! Below are private procs you should never call directly from your code ;;
;;================================================================================================;;
;;////////////////////////////////////////////////////////////////////////////////////////////////;;
;;================================================================================================;;
img.decode.ico._.decode_icon_data:
; create stack frame and jump to common BMP+ICO code
push ebp
mov ebp, esp
sub esp, 12
mov byte [ebp - 3], 1 ; bIsIco
jmp img.decode.bmp.common
img.decode.ico._.decode_icon_mask:
mov edx, [eax + Image.Width]
add edx, 31
shr edx, 3
and edx, not 3
push edx
imul edx, [eax + Image.Height]
cmp ecx, edx
pop edx
jb .error.free
mov edi, [eax + Image.Data]
push ebp ebx eax
xor ebp, ebp
mov ebx, [eax + Image.Extended]
cmp [ebx + bmp.Image.info.Height], 0
js @f
push edx
imul edx, [eax + Image.Height]
add esi, edx
pop edx
lea ebp, [edx+edx]
sub esi, edx
@@:
mov ebx, [eax + Image.Height]
mov ecx, [eax + Image.Width]
; for now, BMP code produces only 8 and 32 bpp images
cmp [eax + Image.Type], Image.bpp8i
jz .bpp8
.bpp32:
mov edx, [esp+16] ; get background color
.bpp32.extloop:
push ecx
.bpp32.innloop:
lodsd
bswap eax
push 32
.bpp32.dwordloop:
add eax, eax
jnc @f
mov [edi], edx
@@:
add edi, 4
dec ecx
jz @f
dec dword [esp]
jnz .bpp32.dwordloop
@@:
pop eax
test ecx, ecx
jnz .bpp32.innloop
sub esi, ebp
pop ecx
dec ebx
jnz .bpp32.extloop
pop eax ebx ebp
ret 4
.bpp8:
push edi
mov edi, [eax + Image.Palette]
mov eax, [esp+20] ; get background color
; if palette already has index for bgr color, use it
push ecx
mov ecx, 256
repnz scasd
jnz .bpp8.notfound
not cl ; cl = index
pop edx
pop edi
.bpp8.extloop:
push edx
.bpp8.innloop:
lodsd
bswap eax
push 32
.bpp8.dwordloop:
add eax, eax
jnc @f
mov [edi], cl
@@:
inc edi
dec edx
jz @f
dec dword [esp]
jnz .bpp8.dwordloop
@@:
pop eax
test edx, edx
jnz .bpp8.innloop
sub esi, ebp
pop edx
dec ebx
jnz .bpp8.extloop
pop eax ebx ebp
ret 4
.bpp8.notfound:
; get maximum used color; if index < 255, then we can add one color to palette
pop ecx
pop edi
pop eax
mov edx, [eax + Image.Width]
imul edx, ebx
mov edi, [eax + Image.Data]
xor ecx, ecx
.bpp8.scanloop:
cmp [edi], cl
jb @f
mov cl, [edi]
@@:
inc edi
dec edx
jnz .bpp8.scanloop
inc cl
jz .bpp8.nospace
mov edx, [esp+8]
mov edi, [eax + Image.Palette]
mov [edi+ecx*4], edx ; set palette color
mov edi, [eax + Image.Data]
mov edx, [eax + Image.Width]
push eax
jmp .bpp8.extloop
.bpp8.nospace:
; convert to 24 bpp
mov edx, [eax + Image.Width]
imul edx, ebx
lea edx, [edx*3]
push eax
invoke mem.alloc, edx
mov edi, eax
pop eax
test edi, edi
jz .error.free2
push eax esi edi
mov esi, eax
call img._.do_rgb
pop edi esi eax
xchg edi, [eax + Image.Data]
mov byte [eax + Image.Type], Image.bpp24
push eax
invoke mem.free, edi
pop eax
push eax
mov ecx, [eax + Image.Width]
mov edi, [eax + Image.Data]
.bpp24:
mov edx, [esp+16] ; get background color
.bpp24.extloop:
push ecx
.bpp24.innloop:
lodsd
bswap eax
push 32
.bpp24.dwordloop:
add eax, eax
jnc @f
mov [edi], dx
ror edx, 16
mov [edi+2], dl
ror edx, 16
@@:
add edi, 3
dec ecx
jz @f
dec dword [esp]
jnz .bpp24.dwordloop
@@:
pop eax
test ecx, ecx
jnz .bpp24.innloop
sub esi, ebp
pop ecx
dec ebx
jnz .bpp24.extloop
pop eax ebx ebp
ret 4
.error.free2:
pop ebx ebp
.error.free:
stdcall img._.delete, eax
xor eax, eax
ret 4
;;================================================================================================;;
;;////////////////////////////////////////////////////////////////////////////////////////////////;;
;;================================================================================================;;
;! Below is private data you should never use directly from your code ;;
;;================================================================================================;;
;;////////////////////////////////////////////////////////////////////////////////////////////////;;
;;================================================================================================;;
;
| devlato/kolibrios-llvm | programs/develop/libraries/libs-dev/libimg/ico_cur/ico_cur.asm | Assembly | mit | 12,137 |
/*
* I2C Master Module
*
* org: 6/22/2014
* auth: Nels "Chip" Pearson
*
* Target: I2C Demo Board w/ display and keypad I/O, 20MHz
*
* Usage:
* .include i2c_master.asm
*
*/
.equ SLAVE_ADRS = (0x57) ; default
.equ START = 0x08
.equ REPT_START = 0x10 ; Repeated START sent..treat as START
.equ ARB_LOST = 0x30 ; Arbitration Lost..FATAL ERROR
.equ MT_SLA_ACK = 0x18 ; SLA+W sent, ACK recv'd
.equ MT_SLA_NACK = 0x20 ; SLA+W sent, NACK recv'd
.equ MT_DATA_ACK = 0x28 ; Data sent, ACK recv'd
.equ MT_DATA_NACK = 0x30 ; Data sent, NACK recv'd
.equ MR_SLA_ACK = 0x40 ; SLA+R sent, ACK recv'd
.equ MR_SLA_NACK = 0x48 ; SLA+R sent, NACK recv'd
.equ MR_DATA_ACK = 0x50 ; Data recv'd, ACK recv'd
.equ MR_DATA_NACK = 0x58 ; Data recv'd, NACK recv'd on last byte?
.equ I2C_OP_WRITE = 0 ; Write Adrs->Data, ...->CKSUM
.equ I2C_OP_READ = 1 ; Read Adrs<-Data, ... <-CKSUM
.DSEG
i2c_delay: .BYTE 1
i2c_status: .BYTE 1 ; current I2C status
; b0: 0=Idle, 1=Busy. Executing a Write or Read operation.
; b1: Input buffer. 0=Empty, 1=Has data .. read header for size.
; b2: Output buffer. 0=Empty, 1=Has data .. read header for size.
; b7: 0=Ok, 1=No ACKs .. Failing due to no Slave ACKs.
;
i2c_state: .BYTE 1 ; current I2C state
; 0=Idle
; 1=START sent..wait for (0x08) START sent
; 2=SLA_W sent..wait for (0x18) ACK, or (0x20) NACK, (0x38) Arb Lost.FAIL
; 3=Data sent.. wait for (0x28) ACK, or (0x30) NACK, (0x38) Arb Lost.FAIL
; b7 - Operation: 0=SLA_W..1=SLA_R
;
;
i2c_error: .BYTE 1 ; error flag..b0:OV
; 0xFF..ARB ERROR CODE
;
i2c_test: .BYTE 1
// Resume coding
.CSEG
/*
* Initialize the TWI to support I2C interface as a Master
* This is an interrupt driven system.
*
* input reg: none
* output reg: none
*
* I2C rate = CPU/(16 + 2(TWBR)*(4^TWPS0:1)) = 1^6Hz / 20 = 100kHz
* 20Mhz / 200 = 100kHz .. 16 + (2*92)*1) = 200
*/
i2c_init_master:
ldi R16, 92
sts TWBR, R16
;
ldi R16, 0 ; Prescale TWPS1:0 = 00 .. 4^0 = 1
sts TWSR, R16
;
lds R16, TWCR
ori R16, (1<<TWIE)|(1<<TWEN) ; enable intr on TWI state change.
sts TWCR, R16
;
clr R16
sts i2c_state, R16
sts i2c_error, R16
sts i2c_buff_in_cnt, R16
sts i2c_buff_out_cnt, R16
;
ret
/*
* Service I2C Master
*
* input reg: R17 Mode I2C_OP_WRITE (0) I2C_OP_READ (1)
* i2c_buffer_out: Data to send
* i2c_buffer_out_cnt: Number of Data Bytes (max 15)
*
* i2c_buffer_in: Data recv'd
* i2c_buffer_in_cnt: Expected number of Data Bytes (max 15)
*
* output reg: none
* resources:
*
*
*/
i2c_service:
tst R17 ; I2C_OP_WRITE (0)
brne i2c_skip00
; Write Adrs->Data, ...->CKSUM
ldi R17, (SLAVE_ADRS<<1)|0x00 ; send to Slave Adrs 0xXX+WRITE(b0=0)
call i2c_write
ret
;
i2c_skip00: ; I2C_OP_READ (1)
; Read Adrs<-Data, ... <-CKSUM
ldi R17, (SLAVE_ADRS<<1)|0x01 ; send to Slave Adrs 0xXX+READ(b0=1)
lds R18, i2c_buff_in_cnt ; max data. _cnt is decremented during read intr process
call i2c_read
;
i2c_skip03:
ret
/*
* Master has control of data transmissions.
* Buffer data: SLA_W, (Type+Nbytes), Data, ..., CKSUM
*
* input reg: R17 - Slave Address
* output reg: none
* resources: R16, X
*
*/
i2c_write:
// Load Slave Address (R17<<1)|(CTRL)) into TWDR Register.
ldi XL, LOW(i2c_buff_out) ; R26
ldi XH, HIGH(i2c_buff_out) ; R27
; update X for use by intr service
sts i2c_XL, XL
sts i2c_XH, XH
st X+, R17
; Get byte count
ld R18, X ; Leave X -> Header byte.
andi R18, 0x0F
inc R18 ; adj for added CKSUM byte.
sts i2c_buff_out_cnt, R18 ; Decremented by intr for byte count.
dec R18 ; adj back to data count only.
call util_cksum ; Calculate CKSUM = (CKSUM ^ Data) ROL 1..Includes Header
; X returns pointing to CKSUM location in buffer.
st X, R17 ; store CKSUM at end of buffer.
// Issues START condition
ldi R16, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)|(1<<TWIE)
sts TWCR, R16
;
ret
/*
* Master has control of data transmissions.
* input reg: R18 - Slave Address
* output reg: R17 - Data
* R18 - error state 0:ok
* resources: R16 (R16)
*
*/
i2c_read:
// Issues START condition
ldi R16, (1<<TWINT)|(1<<TWSTA)|(1<<TWEN)|(1<<TWIE)
sts TWCR, R16
// This indicates that the START condition has been transmitted.
i2c_rd_wait1:
lds R16, TWCR
sbrs R16, TWINT
rjmp i2c_rd_wait1
// Check value of TWI Status Register. Mask prescaler bits.
// If status different from START go to ERROR.
lds R16, TWSR
andi R16, 0xF8
cpi R16, START
brne i2c_rd_ERROR
// Load Slave Address (R18<<1)|(CTRL)) into TWDR Register.
// Clear TWINT bit in TWCR to start transmission of address.
sts TWDR, R18
ldi R16, (1<<TWINT) | (1<<TWEN)|(1<<TWIE)
sts TWCR, R16
// Wait for TWINT Flag set. This indicates that the SLA+R has been
// transmitted, and ACK/NACK has been received.
i2c_rd_wait2:
lds R16, TWCR
sbrs R16, TWINT
rjmp i2c_rd_wait2
// Check value of TWI Status Register.
// Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR
lds R16, TWSR
andi R16, 0xF8
cpi R16, MR_SLA_ACK
brne i2c_rd_ERROR
// Get Data (R17) from TWDR Register.
// Clear TWINT bit in TWCR to start transmission of data.
ldi R16, (1<<TWINT) | (1<<TWEN)|(1<<TWIE)
sts TWCR, R16
// Wait for TWINT Flag set. This indicates that the DATA has been
// transmitted, and ACK/NACK has been received.
i2c_rd_wait3:
lds R16, TWCR
sbrs R16, TWINT
rjmp i2c_rd_wait3
// Check value of TWI Status Register.
// Mask prescaler bits. If status different from MR_DATA_ACK go to ERROR
lds R16, TWSR
andi R16, 0xF8
cpi R16, MR_DATA_ACK ; 0x50
cpi R16, MR_DATA_NACK ; 0x58..ok also
;
; mov dsp_buff, R16 ; 0x58 NACK??
;
; HACK brne i2c_rd_ERROR
lds R17, TWDR
// Transmit STOP condition
ldi R16, (1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
sts TWCR, R16
// EXIT..ok
clr R18
; clean up?
ldi R16, 0xFF
sts TWDR, R16
;
ret
// EXIT..error
i2c_rd_ERROR:
// Transmit STOP condition. Should always clean up.
ldi R16, (1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
sts TWCR, R16
// set error state
ldi R18, $FF
ret
/*
* Master has control of data transmissions.
* input reg: none
* output reg: R17 - Data
* R18 - Data valid. 0:valid..1:no data
* R19 - Error code. 0:pass..1:read errors
*/
i2c_get_data:
call fifo_get
ret
/*
* Clear error flag
* input reg: none
* output reg: none
*/
i2c_clear:
clr R16
sts i2c_error, R16
ret
/*
* I2C interrupt service
*
* resources: i2c_buff - data buffer
*
*/
// Define a data buffer.
.equ I2C_BUFF_IN_SIZE = 18 ; read Slave data into here.
.equ I2C_BUFF_OUT_SIZE = 18 ; write Slave data from here.
;
.DSEG
i2c_XH: .BYTE 1
i2c_XL: .BYTE 1
;
i2c_buff_in_cnt: .BYTE 1
i2c_buff_in: .BYTE I2C_BUFF_IN_SIZE ; dec to zero while receiving data
;
i2c_buff_out_cnt: .BYTE 1 ; dec to zero while sending data.
i2c_buff_out: .BYTE I2C_BUFF_OUT_SIZE
.CSEG
/*
* I2C Interrupt Service
* Supports both Write to Slave and Read from Slave
* input reg:
* output reg:
*
* Clear TWCR.TWINT by setting it to 1.
*/
ii_skip35:
rjmp ii_skip35e
ii_skip40:
rjmp ii_skip40e
ii_skip45:
rjmp ii_skip45e
ii_skip50:
rjmp ii_skip50e
i2c_intr:
; Save SREG
push R0
in R0, SREG
push R0
;
push R16
push XL
push XH
;
lds R16, TWSR ; get status
andi R16, 0xF8 ; mask out bits
; System level status words
cpi R16, START ; 0x08..START sent
breq ii_skip00
cpi R16, REPT_START ; 0x10..Repeated START sent..treat as START
breq ii_skip00
cpi R16, ARB_LOST ; 0x38..Arbitration Lost..FATAL ERROR
breq ii_skip10
; Transmit status words
cpi R16, MT_SLA_ACK ; 0x18..SLA+W sent, ACK recv'd
breq ii_skip15
cpi R16, MT_SLA_NACK ; 0x20..SLA+W sent, NACK recv'd
breq ii_skip20
cpi R16, MT_DATA_ACK ; 0x28..Data sent, ACK recv'd
breq ii_skip25
cpi R16, MT_DATA_NACK ; 0x30..Data sent, NACK recv'd
breq ii_skip30
; Receive status words
cpi R16, MR_SLA_ACK ; 0x40..SLA+R sent, ACK recv'd
breq ii_skip35
cpi R16, MR_SLA_NACK ; 0x48..SLA+R sent, NACK recv'd
breq ii_skip40
cpi R16, MR_DATA_ACK ; 0x50..Data recv'd, ACK recv'd
breq ii_skip45
cpi R16, MR_DATA_NACK ; 0x58..Data recv'd, NACK recv'd on last byte?
breq ii_skip50
; DEFAULT..error
rjmp ii_reset_intr ; Unexpected Status byte..FATAL Error
;
ii_skip00:
; START sent correctly. I2C lines are under Master control. Ok to send SLA_W or SLA_R.
lds XL, i2c_XL
lds XH, i2c_XH
; no need to check state
ld R16, X+
sts TWDR, R16 ; load SLA_W or SLA_R adrs
ldi R16, (1<<TWINT) | (1<<TWEN)|(1<<TWIE)
sts TWCR, R16 ; trigger to send adrs
; update X
sts i2c_XL, XL
sts i2c_XH, XH
;
rjmp ii_exit
;
ii_skip10:
; Arbitration Lost. Master no longer has control on I2C lines.
ldi R16, 0xFF ; ARB ERROR CODE
sts i2c_error, R16
;
rjmp ii_reset_intr
;
; Write operations
ii_skip15:
; Adrs sent, ACK recv'd..Sending data
lds XL, i2c_XL
lds XH, i2c_XH
ii_bkup00:
ld R16, X+
sts TWDR, R16 ; load data
ldi R16, (1<<TWINT) | (1<<TWEN)|(1<<TWIE)
sts TWCR, R16 ; trigger to send data
; update X
sts i2c_XL, XL
sts i2c_XH, XH
;
rjmp ii_exit
;
ii_skip20:
; Adrs sent, NACK recv'd..Resend data
ii_skip30:
; Data sent, NACK recv'd..Resend data
;; TEST
ldi R16, 9
sts dsp_buff, R16
;; TEST
lds XL, i2c_XL
lds XH, i2c_XH
ld R16, -X ; adjust X
rjmp ii_bkup00 ; resend
;
ii_skip25:
; Data sent, ACK recv'd..Sending data
lds R16, i2c_buff_out_cnt ; track data bytes sent.
dec R16
sts i2c_buff_out_cnt, R16
breq ii_skip_26 ; done?
; no
rjmp ii_skip15 ; send next byte.
;
ii_reset_intr:
; Error clean up is STOP and FLUSH.
ii_skip_26:
; yes..send STOP
ldi R16, (1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
sts TWCR, R16
; clean up
ldi R16, 0xFF
sts TWDR, R16
;
rjmp ii_exit
;
; Read Operaions
ii_skip35e:
ii_skip40e:
ii_skip45e:
ii_skip50e:
rjmp ii_reset_intr ; Temp reset for now.
;
ii_exit:
pop XH
pop XL
pop R16
; Restore SREG
pop R0
out SREG, R0
pop R0
;
reti
.DSEG
i2c_head: .BYTE 1
i2c_tail: .BYTE 1
.CSEG
.equ FIFO_SIZE = I2C_BUFF_IN_SIZE
/* Utilites */
/*
* Get one byte from FIFO
* input reg: none
* output reg: R17
* R18 - Data valid. 0:valid..1:no data
* resources: i2c_buff - FIFO data buffer
* FIFO_SIZE - numbytes in FIFO
* i2c_head - in index to FIFO
* i2c_tail - out index to FIFO
*/
fifo_get:
// setup FIFO address pointer - X reg
ldi XL, LOW(i2c_buff_in) ; R26
ldi XH, HIGH(i2c_buff_in) ; R27
lds R17, i2c_head
lds R18, i2c_tail
cp R17, R18 ; test for empty
brne fg001 ; skip if data
ldi R18, $1 ; no data
ret ; EXIT
fg001:
// 16 bit add..X + i2c_tail
clc
adc XL, R18
clr R16
adc XH, R16
ld R17, X ; get data
// Update i2c_tail
inc R18
sts i2c_tail, R18
// check for wrap around
ldi R16, FIFO_SIZE
cp R18, R16
brne fg002
// at end
clr R18
sts i2c_tail, R18 ; reset to begining
fg002:
clr R18
ret
/*
* Put one byte into FIFO
* NOTE: Overflow tested. If FULL, don't store. Set i2c_error OV=1.
* input reg: R17
* output reg: none
* resources: i2c_buff - FIFO data buffer
* FIFO_SIZE - numbytes in FIFO
* i2c_error - error flags
* i2c_head - in index to FIFO
* i2c_tail - out index to FIFO
*
* NOTE: Called from INTR service routine. SAVE regs.
*/
fifo_put:
push R16
push XL
push XH
;
// setup FIFO address pointer - X reg
ldi XL, LOW(i2c_buff_in)
ldi XH, HIGH(i2c_buff_in)
// 16 bit add..X + i2c_head
lds R16, i2c_head
adc XL, R16
clr R16
adc XH, R16
st X, R17 ; put data
// Update i2c_tail
lds R17, i2c_head ; save in case of ov.
inc R17
sts i2c_head, R17
// check for wrap around
ldi R16, FIFO_SIZE
cp R17, R16
brne fp001
// at end
clr R17
sts i2c_head, R17 ; reset
fp001:
lds R16, i2c_tail
cp R17, R16 ; test for overflow
brne fp002 ; skip if ov
sts i2c_head, R17 ; restore i2c_head
ldi R16, $1
sts i2c_error, R16
fp002:
pop XH
pop XL
pop R16
;
ret
| CmdrZin/chips_avr_examples | I2C_Master_Code_Dev/I2C_DemoBoard/src/i2c_master.asm | Assembly | mit | 12,090 |
include 'a32.inc'
_start:
LOAD_R0 1.0
LOAD_R1 1.0
.iloop:
; push r0
PUSH R0
; calculate factorial
F_FACT
; pop factorial into r3
POP R3
; do a 1 / factorial
PUSH 1.0
PUSH R3
F_DIV
; pop result into r2
POP R2
; add it to r1
PUSH R1
PUSH R2
F_ADD
POP R1
; increment r0
PUSH 1.0
PUSH R0
F_ADD
; store increment result
POP R0
VM_DEBUG
; r0 = 8.0?
CMPR R0, 16.0
JMPF_E .done
JMPF .iloop
.done:
VM_CALL 4
VM_EXIT
_end_start:
_data:
_end_data:
_bss:
_end_bss:
| Benderx2/FVM | examples/fpu.asm | Assembly | bsd-2-clause | 490 |
; The MIT License (MIT)
;
; Copyright (c) 2014 Microsoft
;
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included in all
; copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
; SOFTWARE.
;
; Author: Mark Gottscho <mgottscho@ucla.edu>
.code
win_x86_64_asm_dummy_forwStride8Loop_Word256 proc
; Arguments:
; rcx is address of the first 256-bit word in the array
; rdx is address of the last 256-bit word in the array
; rax holds number of words accessed
; rcx holds the first 256-bit word address
; rdx holds the target total number of words to access
; xmm0 holds result from reading the memory 256-bit wide
xor rax,rax ; initialize number of words accessed to 0
sub rdx,rcx ; Get total number of 256-bit words between starting and ending addresses
shr rdx,5
cmp rax,rdx ; have we completed the target total number of words to access?
jae done ; if the number of words accessed >= the target number, then we are done
myloop:
add rax,16 ; Just did 16 accesses
cmp rax,rdx ; have we completed the target number of accesses in total yet?
jb myloop ; make another unrolled pass on the memory
done:
xor eax,eax ; return 0
ret
win_x86_64_asm_dummy_forwStride8Loop_Word256 endp
end
| Microsoft/X-Mem | src/win/x86_64/win_x86_64_asm_dummy_forwStride8Loop_Word256.asm | Assembly | mit | 2,198 |
;Este es un comentario, se le antecede un punto y coma
list p=18f4550 ;Modelo del microcontrolador
#include <p18f4550.inc> ;Llamada a la librería de nombre de los registros
;Directivas de preprocesador o bits de configuración
CONFIG PLLDIV = 1 ; PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))
CONFIG CPUDIV = OSC1_PLL2 ; System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
CONFIG FOSC = XT_XT ; Oscillator Selection bits (XT oscillator (XT))
CONFIG PWRT = ON ; Power-up Timer Enable bit (PWRT enabled)
CONFIG BOR = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG CCP2MX = ON ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
CONFIG MCLRE = ON ; MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
org 0x0000 ;Vector de RESET
goto init_conf
org 0x0008 ;Vector de interrupción
org 0x0020 ;Zona de programa de usuario
init_conf:
end ;Fin del programa | tocache/picomones | UPC Microcontroladores 2020-1/Semana 01/20201-OR.X/newplantilla.asm | Assembly | cc0-1.0 | 1,474 |
; Copyright Oliver Kowalke 2009.
; Distributed under the Boost Software License, Version 1.0.
; (See accompanying file LICENSE_1_0.txt or copy at
; http://www.boost.org/LICENSE_1_0.txt)
; ----------------------------------------------------------------------------------
; | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
; ----------------------------------------------------------------------------------
; | 0x0 | 0x4 | 0x8 | 0xc | 0x10 | 0x14 | 0x18 | 0x1c |
; ----------------------------------------------------------------------------------
; | R12 | R13 | R14 | R15 |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
; ----------------------------------------------------------------------------------
; | 0x20 | 0x24 | 0x28 | 0x2c | 0x30 | 0x34 | 0x38 | 0x3c |
; ----------------------------------------------------------------------------------
; | RDI | RSI | RBX | RBP |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 16 | 17 | 18 | 19 | |
; ----------------------------------------------------------------------------------
; | 0x40 | 0x44 | 0x48 | 0x4c | |
; ----------------------------------------------------------------------------------
; | RSP | RIP | |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 20 | 21 | 22 | 23 | 24 | 25 | |
; ----------------------------------------------------------------------------------
; | 0x50 | 0x54 | 0x58 | 0x5c | 0x60 | 0x64 | |
; ----------------------------------------------------------------------------------
; | sp | size | limit | |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 26 | 27 | |
; ----------------------------------------------------------------------------------
; | 0x68 | 0x6c | |
; ----------------------------------------------------------------------------------
; | fbr_strg | |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
; ----------------------------------------------------------------------------------
; | 0x70 | 0x74 | 0x78 | 0x7c | 0x80 | 0x84 | 0x88 | 0x8c |
; ----------------------------------------------------------------------------------
; | fc_mxcsr|fc_x87_cw| fc_xmm | SEE registers (XMM6-XMM15) |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 |
; ----------------------------------------------------------------------------------
; | 0x90 | 0x94 | 0x98 | 0x9c | 0xa0 | 0xa4 | 0xa8 | 0xac |
; ----------------------------------------------------------------------------------
; | SEE registers (XMM6-XMM15) |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 |
; ----------------------------------------------------------------------------------
; | 0xb0 | 0xb4 | 0xb8 | 0xbc | 0xc0 | 0xc4 | 0xc8 | 0xcc |
; ----------------------------------------------------------------------------------
; | SEE registers (XMM6-XMM15) |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 |
; ----------------------------------------------------------------------------------
; | 0xd0 | 0xd4 | 0xd8 | 0xdc | 0xe0 | 0xe4 | 0xe8 | 0xec |
; ----------------------------------------------------------------------------------
; | SEE registers (XMM6-XMM15) |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 |
; ----------------------------------------------------------------------------------
; | 0xf0 | 0xf4 | 0xf8 | 0xfc | 0x100 | 0x104 | 0x108 | 0x10c |
; ----------------------------------------------------------------------------------
; | SEE registers (XMM6-XMM15) |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 |
; ----------------------------------------------------------------------------------
; | 0x110 | 0x114 | 0x118 | 0x11c | 0x120 | 0x124 | 0x128 | 0x12c |
; ----------------------------------------------------------------------------------
; | SEE registers (XMM6-XMM15) |
; ----------------------------------------------------------------------------------
; ----------------------------------------------------------------------------------
; | 76 | 77 | |
; ----------------------------------------------------------------------------------
; | 0x130 | 0x134 | |
; ----------------------------------------------------------------------------------
; | fc_dealloc | |
; ----------------------------------------------------------------------------------
EXTERN _exit:PROC ; standard C library function
.code
jump_fcontext PROC EXPORT FRAME
.endprolog
mov [rcx], r12 ; save R12
mov [rcx+08h], r13 ; save R13
mov [rcx+010h], r14 ; save R14
mov [rcx+018h], r15 ; save R15
mov [rcx+020h], rdi ; save RDI
mov [rcx+028h], rsi ; save RSI
mov [rcx+030h], rbx ; save RBX
mov [rcx+038h], rbp ; save RBP
mov r10, gs:[030h] ; load NT_TIB
mov rax, [r10+08h] ; load current stack base
mov [rcx+050h], rax ; save current stack base
mov rax, [r10+010h] ; load current stack limit
mov [rcx+060h], rax ; save current stack limit
mov rax, [r10+01478h] ; load current deallocation stack
mov [rcx+0130h], rax ; save current deallocation stack
mov rax, [r10+018h] ; load fiber local storage
mov [rcx+068h], rax ; save fiber local storage
test r9, r9
je nxt
stmxcsr [rcx+070h] ; save MMX control and status word
fnstcw [rcx+074h] ; save x87 control word
; save XMM storage
; save start address of SSE register block in R10
lea r10, [rcx+090h]
; shift address in R10 to lower 16 byte boundary
; == pointer to SEE register block
and r10, -16
movaps [r10], xmm6
movaps [r10+010h], xmm7
movaps [r10+020h], xmm8
movaps [r10+030h], xmm9
movaps [r10+040h], xmm10
movaps [r10+050h], xmm11
movaps [r10+060h], xmm12
movaps [r10+070h], xmm13
movaps [r10+080h], xmm14
movaps [r10+090h], xmm15
ldmxcsr [rdx+070h] ; restore MMX control and status word
fldcw [rdx+074h] ; restore x87 control word
; restore XMM storage
; save start address of SSE register block in R10
lea r10, [rdx+090h]
; shift address in R10 to lower 16 byte boundary
; == pointer to SEE register block
and r10, -16
movaps xmm6, [r10]
movaps xmm7, [r10+010h]
movaps xmm8, [r10+020h]
movaps xmm9, [r10+030h]
movaps xmm10, [r10+040h]
movaps xmm11, [r10+050h]
movaps xmm12, [r10+060h]
movaps xmm13, [r10+070h]
movaps xmm14, [r10+080h]
movaps xmm15, [r10+090h]
nxt:
lea rax, [rsp+08h] ; exclude the return address
mov [rcx+040h], rax ; save as stack pointer
mov rax, [rsp] ; load return address
mov [rcx+048h], rax ; save return address
mov r12, [rdx] ; restore R12
mov r13, [rdx+08h] ; restore R13
mov r14, [rdx+010h] ; restore R14
mov r15, [rdx+018h] ; restore R15
mov rdi, [rdx+020h] ; restore RDI
mov rsi, [rdx+028h] ; restore RSI
mov rbx, [rdx+030h] ; restore RBX
mov rbp, [rdx+038h] ; restore RBP
mov r10, gs:[030h] ; load NT_TIB
mov rax, [rdx+050h] ; load stack base
mov [r10+08h], rax ; restore stack base
mov rax, [rdx+060h] ; load stack limit
mov [r10+010h], rax ; restore stack limit
mov rax, [rdx+0130h] ; load deallocation stack
mov [r10+01478h], rax ; restore deallocation stack
mov rax, [rdx+068h] ; load fiber local storage
mov [r10+018h], rax ; restore fiber local storage
mov rsp, [rdx+040h] ; restore RSP
mov r10, [rdx+048h] ; fetch the address to returned to
mov rax, r8 ; use third arg as return value after jump
mov rcx, r8 ; use third arg as first arg in context function
jmp r10 ; indirect jump to caller
jump_fcontext ENDP
END
| NixaSoftware/CVis | venv/bin/libs/context/src/asm/jump_x86_64_ms_pe_masm.asm | Assembly | apache-2.0 | 11,548 |
; Scrolls repeating hello world strings across the screen
; to compile with z88dk to a tap file, use
; z80asm +zx hello_world_3.asm
; make sure you're using a recent version of z88dk - tested with nightly build
; which can be downloaded from http://nightly.z88dk.org/
; Alternate build method:
; z80asm -b -o=program.bin -r=33000 hello_world_3.asm
; appmake +zx -b program.bin --org 33000
; to run this program using Spin, assemble, push into memory @ location 33000
; and then run the following basic
; 10 randomize usr 33000
; Set the screen and ink colour
ld a, 49 ; blue ink (1) on yellow paper (6*8)
ld (23693), a ; set the screen colours
call 3503 ; clear the screen
; set the border colour
ld a, 2 ; red (2)
out (254), a ; write to port 254 - least significant bytes set color
; set the channel
ld a, 2 ; upper screen (use 1 for lower)
call 5633 ; open channel
; repeatedly print the string
loopx: ; loop vertically
loopy: ; loop horizontally
call setxy
call printstr
call shortpause
; clear the first character (to clean up after earlier prints)
; but don't clear if at the end of the line
ld hl, ypos
ld a, (hl)
cp 32-eostr+string ; compare to 32 (width of the screen - string length)
jr z, noerase ; don't erase if zero
call setxy ; set the print position
ld a, 32 ; code for SPACE
rst 16 ; print
noerase:
; increment ypos
ld hl, ypos ; load ypos addr
inc (hl) ; increment ypos
ld a, (hl) ; load ypos value into a
cp 33-eostr+string ; compare 33 (width of the screen + 1 - string length)
jr nz, loopy ; not equal? loop
; reached the end of the screen
ld (hl), 0 ; reset ypos
; increment xpos
ld hl, xpos ; load xpos addr
inc (hl) ; increment xpos
ld a, (hl) ; load xpos value into a
cp 22 ; compare to the chat height of the screen
jr nz, loopx
call longpause
; program complete
ret
;
; subroutines
;
;
; short pause
;
shortpause:
ld b, 1 ; time to pause (1/50 sec)
shortpauseloop:
halt ; wait for interrupt
djnz shortpauseloop ; repeat if b not 0
ret
;
; long pause
;
longpause:
ld b, 100 ; time to pause (50 per second)
longpauseloop:
halt ; wait for interrupt
djnz longpauseloop ; repeat if b not 0
ret
;
; print the string
;
printstr:
ld de, string ; address of string
ld bc, eostr-string ; length of string to print
call 8252 ; print the string
ret
;
; set the x and y position for text writing
;
setxy:
ld a, 22 ; control code for AT command
rst 16 ; 'print' AT command
ld a, (xpos) ; load the x position
rst 16 ; print
ld a, (ypos) ; load the y position
rst 16 ; print
ret ; position set, return
;
; data
;
string:
defb "Hello world" ; string to print
eostr:
xpos:
defb 0
ypos:
defb 0
| mjohnsullivan/zxspectrum | hello_world_asm/hello_world_3.asm | Assembly | apache-2.0 | 3,343 |
;
; Copyright (c) 2016, Alliance for Open Media. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia.org/license/software. If the Alliance for Open
; Media Patent License 1.0 was not distributed with this source code in the
; PATENTS file, you can obtain it at www.aomedia.org/license/patent.
;
;
%include "third_party/x86inc/x86inc.asm"
SECTION_RODATA
pw_4: times 8 dw 4
pw_8: times 8 dw 8
pw_16: times 8 dw 16
pw_32: times 8 dw 32
dc_128: times 16 db 128
pw2_4: times 8 dw 2
pw2_8: times 8 dw 4
pw2_16: times 8 dw 8
pw2_32: times 8 dw 16
SECTION .text
INIT_XMM sse2
cglobal dc_predictor_4x4, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
movd m2, [leftq]
movd m0, [aboveq]
pxor m1, m1
punpckldq m0, m2
psadbw m0, m1
paddw m0, [GLOBAL(pw_4)]
psraw m0, 3
pshuflw m0, m0, 0x0
packuswb m0, m0
movd [dstq ], m0
movd [dstq+strideq], m0
lea dstq, [dstq+strideq*2]
movd [dstq ], m0
movd [dstq+strideq], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_left_predictor_4x4, 2, 5, 2, dst, stride, above, left, goffset
movifnidn leftq, leftmp
GET_GOT goffsetq
pxor m1, m1
movd m0, [leftq]
psadbw m0, m1
paddw m0, [GLOBAL(pw2_4)]
psraw m0, 2
pshuflw m0, m0, 0x0
packuswb m0, m0
movd [dstq ], m0
movd [dstq+strideq], m0
lea dstq, [dstq+strideq*2]
movd [dstq ], m0
movd [dstq+strideq], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_top_predictor_4x4, 3, 5, 2, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
movd m0, [aboveq]
psadbw m0, m1
paddw m0, [GLOBAL(pw2_4)]
psraw m0, 2
pshuflw m0, m0, 0x0
packuswb m0, m0
movd [dstq ], m0
movd [dstq+strideq], m0
lea dstq, [dstq+strideq*2]
movd [dstq ], m0
movd [dstq+strideq], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_predictor_8x8, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
movq m0, [aboveq]
movq m2, [leftq]
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
psadbw m0, m1
psadbw m2, m1
paddw m0, m2
paddw m0, [GLOBAL(pw_8)]
psraw m0, 4
punpcklbw m0, m0
pshuflw m0, m0, 0x0
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_top_predictor_8x8, 3, 5, 2, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
movq m0, [aboveq]
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
psadbw m0, m1
paddw m0, [GLOBAL(pw2_8)]
psraw m0, 3
punpcklbw m0, m0
pshuflw m0, m0, 0x0
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_left_predictor_8x8, 2, 5, 2, dst, stride, above, left, goffset
movifnidn leftq, leftmp
GET_GOT goffsetq
pxor m1, m1
movq m0, [leftq]
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
psadbw m0, m1
paddw m0, [GLOBAL(pw2_8)]
psraw m0, 3
punpcklbw m0, m0
pshuflw m0, m0, 0x0
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_128_predictor_4x4, 2, 5, 1, dst, stride, above, left, goffset
GET_GOT goffsetq
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
movd m0, [GLOBAL(dc_128)]
movd [dstq ], m0
movd [dstq+strideq ], m0
movd [dstq+strideq*2], m0
movd [dstq+stride3q ], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_128_predictor_8x8, 2, 5, 1, dst, stride, above, left, goffset
GET_GOT goffsetq
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
movq m0, [GLOBAL(dc_128)]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_predictor_16x16, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
mova m0, [aboveq]
mova m2, [leftq]
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 4
psadbw m0, m1
psadbw m2, m1
paddw m0, m2
movhlps m2, m0
paddw m0, m2
paddw m0, [GLOBAL(pw_16)]
psraw m0, 5
pshuflw m0, m0, 0x0
punpcklqdq m0, m0
packuswb m0, m0
.loop:
mova [dstq ], m0
mova [dstq+strideq ], m0
mova [dstq+strideq*2], m0
mova [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
REP_RET
INIT_XMM sse2
cglobal dc_top_predictor_16x16, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
mova m0, [aboveq]
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 4
psadbw m0, m1
movhlps m2, m0
paddw m0, m2
paddw m0, [GLOBAL(pw2_16)]
psraw m0, 4
pshuflw m0, m0, 0x0
punpcklqdq m0, m0
packuswb m0, m0
.loop:
mova [dstq ], m0
mova [dstq+strideq ], m0
mova [dstq+strideq*2], m0
mova [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
REP_RET
INIT_XMM sse2
cglobal dc_left_predictor_16x16, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
mova m0, [leftq]
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 4
psadbw m0, m1
movhlps m2, m0
paddw m0, m2
paddw m0, [GLOBAL(pw2_16)]
psraw m0, 4
pshuflw m0, m0, 0x0
punpcklqdq m0, m0
packuswb m0, m0
.loop:
mova [dstq ], m0
mova [dstq+strideq ], m0
mova [dstq+strideq*2], m0
mova [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
REP_RET
INIT_XMM sse2
cglobal dc_128_predictor_16x16, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 4
mova m0, [GLOBAL(dc_128)]
.loop:
mova [dstq ], m0
mova [dstq+strideq ], m0
mova [dstq+strideq*2], m0
mova [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
RET
INIT_XMM sse2
cglobal dc_predictor_32x32, 4, 5, 5, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
mova m0, [aboveq]
mova m2, [aboveq+16]
mova m3, [leftq]
mova m4, [leftq+16]
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 8
psadbw m0, m1
psadbw m2, m1
psadbw m3, m1
psadbw m4, m1
paddw m0, m2
paddw m0, m3
paddw m0, m4
movhlps m2, m0
paddw m0, m2
paddw m0, [GLOBAL(pw_32)]
psraw m0, 6
pshuflw m0, m0, 0x0
punpcklqdq m0, m0
packuswb m0, m0
.loop:
mova [dstq ], m0
mova [dstq +16], m0
mova [dstq+strideq ], m0
mova [dstq+strideq +16], m0
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m0
mova [dstq+stride3q ], m0
mova [dstq+stride3q +16], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
REP_RET
INIT_XMM sse2
cglobal dc_top_predictor_32x32, 4, 5, 5, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
mova m0, [aboveq]
mova m2, [aboveq+16]
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 8
psadbw m0, m1
psadbw m2, m1
paddw m0, m2
movhlps m2, m0
paddw m0, m2
paddw m0, [GLOBAL(pw2_32)]
psraw m0, 5
pshuflw m0, m0, 0x0
punpcklqdq m0, m0
packuswb m0, m0
.loop:
mova [dstq ], m0
mova [dstq +16], m0
mova [dstq+strideq ], m0
mova [dstq+strideq +16], m0
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m0
mova [dstq+stride3q ], m0
mova [dstq+stride3q +16], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
REP_RET
INIT_XMM sse2
cglobal dc_left_predictor_32x32, 4, 5, 5, dst, stride, above, left, goffset
GET_GOT goffsetq
pxor m1, m1
mova m0, [leftq]
mova m2, [leftq+16]
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 8
psadbw m0, m1
psadbw m2, m1
paddw m0, m2
movhlps m2, m0
paddw m0, m2
paddw m0, [GLOBAL(pw2_32)]
psraw m0, 5
pshuflw m0, m0, 0x0
punpcklqdq m0, m0
packuswb m0, m0
.loop:
mova [dstq ], m0
mova [dstq +16], m0
mova [dstq+strideq ], m0
mova [dstq+strideq +16], m0
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m0
mova [dstq+stride3q ], m0
mova [dstq+stride3q +16], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
REP_RET
INIT_XMM sse2
cglobal dc_128_predictor_32x32, 4, 5, 3, dst, stride, above, left, goffset
GET_GOT goffsetq
DEFINE_ARGS dst, stride, stride3, lines4
lea stride3q, [strideq*3]
mov lines4d, 8
mova m0, [GLOBAL(dc_128)]
.loop:
mova [dstq ], m0
mova [dstq +16], m0
mova [dstq+strideq ], m0
mova [dstq+strideq +16], m0
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m0
mova [dstq+stride3q ], m0
mova [dstq+stride3q +16], m0
lea dstq, [dstq+strideq*4]
dec lines4d
jnz .loop
RESTORE_GOT
RET
INIT_XMM sse2
cglobal v_predictor_4x4, 3, 3, 1, dst, stride, above
movd m0, [aboveq]
movd [dstq ], m0
movd [dstq+strideq], m0
lea dstq, [dstq+strideq*2]
movd [dstq ], m0
movd [dstq+strideq], m0
RET
INIT_XMM sse2
cglobal v_predictor_8x8, 3, 3, 1, dst, stride, above
movq m0, [aboveq]
DEFINE_ARGS dst, stride, stride3
lea stride3q, [strideq*3]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
movq [dstq ], m0
movq [dstq+strideq ], m0
movq [dstq+strideq*2], m0
movq [dstq+stride3q ], m0
RET
INIT_XMM sse2
cglobal v_predictor_16x16, 3, 4, 1, dst, stride, above
mova m0, [aboveq]
DEFINE_ARGS dst, stride, stride3, nlines4
lea stride3q, [strideq*3]
mov nlines4d, 4
.loop:
mova [dstq ], m0
mova [dstq+strideq ], m0
mova [dstq+strideq*2], m0
mova [dstq+stride3q ], m0
lea dstq, [dstq+strideq*4]
dec nlines4d
jnz .loop
REP_RET
INIT_XMM sse2
cglobal v_predictor_32x32, 3, 4, 2, dst, stride, above
mova m0, [aboveq]
mova m1, [aboveq+16]
DEFINE_ARGS dst, stride, stride3, nlines4
lea stride3q, [strideq*3]
mov nlines4d, 8
.loop:
mova [dstq ], m0
mova [dstq +16], m1
mova [dstq+strideq ], m0
mova [dstq+strideq +16], m1
mova [dstq+strideq*2 ], m0
mova [dstq+strideq*2+16], m1
mova [dstq+stride3q ], m0
mova [dstq+stride3q +16], m1
lea dstq, [dstq+strideq*4]
dec nlines4d
jnz .loop
REP_RET
INIT_XMM sse2
cglobal h_predictor_4x4, 2, 4, 4, dst, stride, line, left
movifnidn leftq, leftmp
movd m0, [leftq]
punpcklbw m0, m0
punpcklbw m0, m0
pshufd m1, m0, 0x1
movd [dstq ], m0
movd [dstq+strideq], m1
pshufd m2, m0, 0x2
lea dstq, [dstq+strideq*2]
pshufd m3, m0, 0x3
movd [dstq ], m2
movd [dstq+strideq], m3
RET
INIT_XMM sse2
cglobal h_predictor_8x8, 2, 5, 3, dst, stride, line, left
movifnidn leftq, leftmp
mov lineq, -2
DEFINE_ARGS dst, stride, line, left, stride3
lea stride3q, [strideq*3]
movq m0, [leftq ]
punpcklbw m0, m0 ; l1 l1 l2 l2 ... l8 l8
.loop:
pshuflw m1, m0, 0x0 ; l1 l1 l1 l1 l1 l1 l1 l1
pshuflw m2, m0, 0x55 ; l2 l2 l2 l2 l2 l2 l2 l2
movq [dstq ], m1
movq [dstq+strideq], m2
pshuflw m1, m0, 0xaa
pshuflw m2, m0, 0xff
movq [dstq+strideq*2], m1
movq [dstq+stride3q ], m2
pshufd m0, m0, 0xe ; [63:0] l5 l5 l6 l6 l7 l7 l8 l8
inc lineq
lea dstq, [dstq+strideq*4]
jnz .loop
REP_RET
INIT_XMM sse2
cglobal h_predictor_16x16, 2, 5, 3, dst, stride, line, left
movifnidn leftq, leftmp
mov lineq, -4
DEFINE_ARGS dst, stride, line, left, stride3
lea stride3q, [strideq*3]
.loop:
movd m0, [leftq]
punpcklbw m0, m0
punpcklbw m0, m0 ; l1 to l4 each repeated 4 times
pshufd m1, m0, 0x0 ; l1 repeated 16 times
pshufd m2, m0, 0x55 ; l2 repeated 16 times
mova [dstq ], m1
mova [dstq+strideq ], m2
pshufd m1, m0, 0xaa
pshufd m2, m0, 0xff
mova [dstq+strideq*2], m1
mova [dstq+stride3q ], m2
inc lineq
lea leftq, [leftq+4 ]
lea dstq, [dstq+strideq*4]
jnz .loop
REP_RET
INIT_XMM sse2
cglobal h_predictor_32x32, 2, 5, 3, dst, stride, line, left
movifnidn leftq, leftmp
mov lineq, -8
DEFINE_ARGS dst, stride, line, left, stride3
lea stride3q, [strideq*3]
.loop:
movd m0, [leftq]
punpcklbw m0, m0
punpcklbw m0, m0 ; l1 to l4 each repeated 4 times
pshufd m1, m0, 0x0 ; l1 repeated 16 times
pshufd m2, m0, 0x55 ; l2 repeated 16 times
mova [dstq ], m1
mova [dstq+16 ], m1
mova [dstq+strideq ], m2
mova [dstq+strideq+16 ], m2
pshufd m1, m0, 0xaa
pshufd m2, m0, 0xff
mova [dstq+strideq*2 ], m1
mova [dstq+strideq*2+16], m1
mova [dstq+stride3q ], m2
mova [dstq+stride3q+16 ], m2
inc lineq
lea leftq, [leftq+4 ]
lea dstq, [dstq+strideq*4]
jnz .loop
REP_RET
INIT_XMM sse2
cglobal tm_predictor_4x4, 4, 4, 5, dst, stride, above, left
pxor m1, m1
movq m0, [aboveq-1]; [63:0] tl t1 t2 t3 t4 x x x
punpcklbw m0, m1
pshuflw m2, m0, 0x0 ; [63:0] tl tl tl tl [word]
psrldq m0, 2
psubw m0, m2 ; [63:0] t1-tl t2-tl t3-tl t4-tl [word]
movd m2, [leftq]
punpcklbw m2, m1
pshuflw m4, m2, 0x0 ; [63:0] l1 l1 l1 l1 [word]
pshuflw m3, m2, 0x55 ; [63:0] l2 l2 l2 l2 [word]
paddw m4, m0
paddw m3, m0
packuswb m4, m4
packuswb m3, m3
movd [dstq ], m4
movd [dstq+strideq], m3
lea dstq, [dstq+strideq*2]
pshuflw m4, m2, 0xaa
pshuflw m3, m2, 0xff
paddw m4, m0
paddw m3, m0
packuswb m4, m4
packuswb m3, m3
movd [dstq ], m4
movd [dstq+strideq], m3
RET
INIT_XMM sse2
cglobal tm_predictor_8x8, 4, 4, 5, dst, stride, above, left
pxor m1, m1
movd m2, [aboveq-1]
movq m0, [aboveq]
punpcklbw m2, m1
punpcklbw m0, m1 ; t1 t2 t3 t4 t5 t6 t7 t8 [word]
pshuflw m2, m2, 0x0 ; [63:0] tl tl tl tl [word]
DEFINE_ARGS dst, stride, line, left
mov lineq, -4
punpcklqdq m2, m2 ; tl tl tl tl tl tl tl tl [word]
psubw m0, m2 ; t1-tl t2-tl ... t8-tl [word]
movq m2, [leftq]
punpcklbw m2, m1 ; l1 l2 l3 l4 l5 l6 l7 l8 [word]
.loop
pshuflw m4, m2, 0x0 ; [63:0] l1 l1 l1 l1 [word]
pshuflw m3, m2, 0x55 ; [63:0] l2 l2 l2 l2 [word]
punpcklqdq m4, m4 ; l1 l1 l1 l1 l1 l1 l1 l1 [word]
punpcklqdq m3, m3 ; l2 l2 l2 l2 l2 l2 l2 l2 [word]
paddw m4, m0
paddw m3, m0
packuswb m4, m3
movq [dstq ], m4
movhps [dstq+strideq], m4
lea dstq, [dstq+strideq*2]
psrldq m2, 4
inc lineq
jnz .loop
REP_RET
INIT_XMM sse2
cglobal tm_predictor_16x16, 4, 5, 8, dst, stride, above, left
pxor m1, m1
mova m2, [aboveq-16];
mova m0, [aboveq] ; t1 t2 ... t16 [byte]
punpckhbw m2, m1 ; [127:112] tl [word]
punpckhbw m4, m0, m1
punpcklbw m0, m1 ; m0:m4 t1 t2 ... t16 [word]
DEFINE_ARGS dst, stride, line, left, stride8
mov lineq, -8
pshufhw m2, m2, 0xff
mova m3, [leftq] ; l1 l2 ... l16 [byte]
punpckhqdq m2, m2 ; tl repeated 8 times [word]
psubw m0, m2
psubw m4, m2 ; m0:m4 t1-tl t2-tl ... t16-tl [word]
punpckhbw m5, m3, m1
punpcklbw m3, m1 ; m3:m5 l1 l2 ... l16 [word]
lea stride8q, [strideq*8]
.loop:
pshuflw m6, m3, 0x0
pshuflw m7, m5, 0x0
punpcklqdq m6, m6 ; l1 repeated 8 times [word]
punpcklqdq m7, m7 ; l8 repeated 8 times [word]
paddw m1, m6, m0
paddw m6, m4 ; m1:m6 ti-tl+l1 [i=1,15] [word]
psrldq m5, 2
packuswb m1, m6
mova [dstq ], m1
paddw m1, m7, m0
paddw m7, m4 ; m1:m7 ti-tl+l8 [i=1,15] [word]
psrldq m3, 2
packuswb m1, m7
mova [dstq+stride8q], m1
inc lineq
lea dstq, [dstq+strideq]
jnz .loop
REP_RET
INIT_XMM sse2
cglobal tm_predictor_32x32, 4, 4, 8, dst, stride, above, left
pxor m1, m1
movd m2, [aboveq-1]
mova m0, [aboveq]
mova m4, [aboveq+16]
punpcklbw m2, m1
punpckhbw m3, m0, m1
punpckhbw m5, m4, m1
punpcklbw m0, m1
punpcklbw m4, m1
pshuflw m2, m2, 0x0
DEFINE_ARGS dst, stride, line, left
mov lineq, -16
punpcklqdq m2, m2
add leftq, 32
psubw m0, m2
psubw m3, m2
psubw m4, m2
psubw m5, m2
.loop:
movd m2, [leftq+lineq*2]
pxor m1, m1
punpcklbw m2, m1
pshuflw m7, m2, 0x55
pshuflw m2, m2, 0x0
punpcklqdq m2, m2
punpcklqdq m7, m7
paddw m6, m2, m3
paddw m1, m2, m0
packuswb m1, m6
mova [dstq ], m1
paddw m6, m2, m5
paddw m1, m2, m4
packuswb m1, m6
mova [dstq+16 ], m1
paddw m6, m7, m3
paddw m1, m7, m0
packuswb m1, m6
mova [dstq+strideq ], m1
paddw m6, m7, m5
paddw m1, m7, m4
packuswb m1, m6
mova [dstq+strideq+16], m1
lea dstq, [dstq+strideq*2]
inc lineq
jnz .loop
REP_RET
| thdav/aom | aom_dsp/x86/intrapred_sse2.asm | Assembly | bsd-2-clause | 23,139 |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; string.asm
;
; This file contains all x86_64 "fast path" implementations of string.h
; functions.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Define section as 64 bit area and export all labels, which needs to
; be accessed in c programming language. All labels not listed as "global"
; won't be accessable outside of this file.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
[BITS 64]
[GLOBAL memcmp_sse2_entry]
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; This is the entry point of the SSE2 version of memcmp. It can be executed on
; any x86_64 cpu. It doesn't matter which generation it is, because every
; x86_64 system needs to support at least SSE2.
;
; This implementation takes advantage of using the movdqa / movdqu instructions
; available in SSE2 as far as pcmpeqb and pmovmskb. Take a look at the comments
; for more information.
;
; Input registers:
;
; - rsi: Pointer to first memory region
; - rdi: Pointer to second memory region
; - rdx: Number of bytes to compare
;
;
; Return values:
;
; - The return value (difference of code points) will be stored in rax
;
;
; Affected / trashed registers:
;
; This routine uses (and modifies!) the registers: rax, rcx, rdx, rsi, rdi
; r8, r10, r11, xmm0 and xmm1. Don't store data in these registers you need
; to rely on later.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
memcmp_sse2_entry:
test rdx, rdx ; Let's see if length is zero -> quit
jz memcmp_zero_result
cmp rdx, 0x01 ; Is there only on byte to compare?
jle memcmp_single_byte ; If so, no SSE2, just simple instructions
sub rsi, rdi ; Calculate difference of pointers. We use this later
mov r10, rdx ; for indirect addressing. So just one pointer needs to be
; incremented.
cmp r10, 0x20 ; Check, if we have at least one chunk of 32 bytes
jge perform_sse2_memcmp ; If so, use SSE2!
memcmp_chunk_size_left_detection:
test r10, 0x01 ; More than one byte left? -> Jump to faster version
jz memcmp_more_than_one_byte_left
movzx eax, byte [rdi] ; Load both bytes into registers and compare them
movzx edx, byte [rdi + rsi]
sub r10, 0x01
je memcmp_single_byte_exit
add rdi, 0x01
sub eax, edx
ret
memcmp_zero_result:
xor rax, rax ; Ensure return value is zero
ret ; Leave memcmp operation
memcmp_single_byte:
movzx eax, byte [rdi] ; Move byte value from adress to register and zero extend it
movzx edx, byte [rsi] ; see above
memcmp_single_byte_exit:
sub dword eax, edx ; Calculate difference of both bytes
ret ; and return
memcmp_more_than_one_byte_left:
test r10, 0x02 ; More than two bytes left? -> Jump to faster version
jz memcmp_more_than_two_bytes_left
movzx eax, word [rdi] ; Load both words (= 2 bytes) into registers and compare them
movzx edx, word [rdi + rsi]
sub r10, 0x02
je final_calculation
add rdi, 0x02
cmp eax, edx
jnz final_calculation
memcmp_more_than_two_bytes_left:
test r10, 0x04 ; More than four bytes left? -> Jump to faster version
jz memcmp_more_than_four_bytes_left
mov eax, dword [rdi] ; Load both dwords (= 4 bytes) into registers and
mov edx, dword [rdi + rsi] ; compare them
sub r10, 0x04
je final_calculation
add rdi, 0x04
cmp eax, edx
jnz final_calculation
memcmp_more_than_four_bytes_left:
test r8, 0x08 ; More than eight bytes left? -> Use MMX instructions!
jz perform_mmx_memcmp
mov rax, qword [rdi] ; Load both qwords (= 8 bytes) into registers and
mov rdx, qword [rdi + rsi] ; compare them
sub r10, 0x08
je final_calculation
add rdi, 0x08
cmp rax, rbx
jnz final_calculation
perform_mmx_memcmp: ; Here it get's fast (but not fastest)!
movdqu xmm1, [rdi] ; Move Unaligned Double Quad Word
movdqu xmm0, [rdi + rsi] ; Load both ywords (= 16 bytes) into MMX registers
pcmpeqb xmm1, xmm0 ; Packed Compare For Equal
pmovmskb edx, xmm1 ; Move Byte Mask
xor eax, eax ; Reset eax and check if we're done right now!
sub edx, 0xFFFF
jz memcmp_result_return
bsf dword ecx, edx ; If not, Bit Scan Forward and do further compares
lea rcx, [rdi + rcx]
movzx eax, byte [rcx] ; Load values left to non mmx Registers
movzx edx, byte [rsi + rcx]
sub eax, edx ; Calculate difference and return
ret
perform_sse2_memcmp: ; Okay, this is the real deal for fast comparisons!
mov r11 ,rdx
add r11, rdi
mov r8, rdi ; If alignment is okay, we can use faster instructions
and r8, 0x0F
jz sse2_pointer_alignment_okay_16
movdqu xmm1, [rdi] ; If not, do the "normal" MMX compare (see above)
movdqu xmm0, [rdi + rsi]
pcmpeqb xmm1, xmm0
pmovmskb edx, xmm1
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
neg r8
lea rdi, [16 + rdi + r8] ; Load aligned part of given pointer(s)
sse2_pointer_alignment_okay_16:
test rsi, 0x0F ; Check for another fast path we could take
jz sse2_memcmp_fast
test rdi, 0x10 ; Check if we even could take 32 bit aligned fast path
jz sse2_pointer_alignment_okay_32
movdqu xmm0, [rdi + rsi] ; Compare using MMX registers (see above)
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Increment pointer
sse2_pointer_alignment_okay_32:
mov r10, r11
and r10, -0x20
cmp rdi, r10
jge sse2_match_16_memcmp ; Check if we even could take 64 bit aligned fast path
test rdi, 0x20
jz sse2_pointer_alignment_okay_64
movdqu xmm0, [rdi + rsi] ; If not, break down into single ywords and compare using
pcmpeqb xmm0, [rdi] ; mmx registers
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Increment pointer and analyze next 16 bytes
movdqu xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Increment pointer
sse2_pointer_alignment_okay_64:
mov r10, r11
and r10, -0x40
cmp rdi, r10
jge sse2_match_32_memcmp ; Can we take a faster path or do we need to unrole?
perform_aligned_64_memcmp:
movdqu xmm0, [rdi + rsi] ; Break down into four segments and compare using mmx
pcmpeqb xmm0, [rdi] ; registers
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10
movdqu xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10
movdqu xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10
movdqu xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10
cmp r10, rdi
jne perform_aligned_64_memcmp ; Not compared everything yet? Move forward...
sse2_match_32_memcmp:
mov r10, r11
and r10, -0x20
cmp rdi, r10 ; Should we use the 32 or 16 bit path?
jge sse2_match_16_memcmp
sse2_perform_32_memcmp:
movdqu xmm0, [rdi + rsi] ; Break down into four segments and compare using mmx
pcmpeqb xmm0, [rdi] ; registers
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Move to next 16 bytes
movdqu xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10
cmp r10, rdi
jne sse2_perform_32_memcmp ; Not compared everything yet? Move forward...
sse2_match_16_memcmp:
sub r11, rdi
je memcmp_zero_result ; If everything was equal, return 0
mov r10, r11 ; Not finished yet! Calc chunk size left and start all over
jmp memcmp_chunk_size_left_detection
sse2_memcmp_fast:
mov r10, r11
and r10, -0x20
cmp rdi, r10
jge sse2_match_16_memcmp
test rdi, 0x10
jz sse2_memcmp_fast_32
movdqa xmm0, [rdi + rsi] ; Move Unaligned Double Quad Word. Better than unaligned
pcmpeqb xmm0, [rdi] ; version used in slower paths
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
cmp r10, rdi
je sse2_match_16_memcmp
sse2_memcmp_fast_32: ; If you've read until here, you should know all the patterns
; occuring in this listing
mov r10, r11
and r10, -0x40
test rdi, 0x20
jz sse2_memcmp_fast_64
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
sse2_memcmp_fast_64:
cmp r10, rdi
je sse2_match_32_memcmp
sse2_memcmp_fast_64_perform:
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
cmp r10, rdi
jne sse2_memcmp_fast_64_perform
mov r10, r11
and r10, -0x20
cmp rdi, r10
jge sse2_match_16_memcmp
sse2_memcmp_fast_result:
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
movdqa xmm0, [rdi + rsi]
pcmpeqb xmm0, [rdi]
pmovmskb edx, xmm0
sub edx, 0xFFFF
jnz sse2_prestage_memcmp_mismatch ; Missmatch detected?
add rdi, 0x10 ; Incremente pointer and continue
cmp rdi, r10
jne sse2_memcmp_fast_result
sub r11, rdi
je memcmp_zero_result ; Everything equal? Let's get out of here...
mov r10, r11 ; Not finished yet! Calc chunk size left and start all over
jmp memcmp_chunk_size_left_detection
sse2_prestage_memcmp_mismatch: ; Missmatch occured! Calculate difference and return
bsf dword ecx, edx
movzx eax, byte [rdi + rcx]
add rsi, rdi
movzx edx, byte [rsi + rcx]
sub dword eax, edx
ret
memcmp_result_return:
ret ; Leave memcmp operation
final_calculation: ; Let's check, which byte failed during comparison
cmp rax, rdx
jz memcmp_zero_result ; Everything equal? Let's get out of here...
mov r11, rax
sub r11, rdx
bsf qword rcx, r11 ; Bit Scan Forward and shift through the whole qword
sar qword rcx, 0x03 ; to find non matching parts!
sal qword rcx, 0x03
sar qword rax, cl ; Load first byte to calculate difference
movzx eax, byte al
sar qword rdx, cl ; Load second byte to calculate difference
movzx edx, byte dl
sub eax, edx ; Calculate difference and return
ret
| TatsuMaster/Tatsu-Development-Kit | sdk/posix/string.asm | Assembly | mit | 14,122 |
; Listing generated by Microsoft (R) Optimizing Compiler Version 16.00.40219.01
TITLE D:\Projects\TaintAnalysis\AntiTaint\Epilog\src\struct.c
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB MSVCRT
INCLUDELIB OLDNAMES
_DATA SEGMENT
$SG3571 DB '%d %d %d', 00H
ORG $+3
$SG3580 DB '%s %d %d %d', 0aH, 00H
_DATA ENDS
PUBLIC _fill
EXTRN __imp__scanf:PROC
; Function compile flags: /Odtp
; File d:\projects\taintanalysis\antitaint\epilog\src\struct.c
_TEXT SEGMENT
_c$ = -12 ; size = 4
_b$ = -8 ; size = 4
_a$ = -4 ; size = 4
_s$ = 8 ; size = 4
_fill PROC
; 14 : {
push ebp
mov ebp, esp
sub esp, 12 ; 0000000cH
; 15 : int a, b, c;
; 16 : scanf("%d %d %d", &a, &b, &c);
lea eax, DWORD PTR _c$[ebp]
push eax
lea ecx, DWORD PTR _b$[ebp]
push ecx
lea edx, DWORD PTR _a$[ebp]
push edx
push OFFSET $SG3571
call DWORD PTR __imp__scanf
add esp, 16 ; 00000010H
; 17 : s->a = a;
mov eax, DWORD PTR _a$[ebp]
cdq
mov ecx, DWORD PTR _s$[ebp]
mov DWORD PTR [ecx], eax
mov DWORD PTR [ecx+4], edx
; 18 : s->b = b;
mov eax, DWORD PTR _b$[ebp]
cdq
mov ecx, DWORD PTR _s$[ebp]
mov DWORD PTR [ecx+8], eax
mov DWORD PTR [ecx+12], edx
; 19 : s->c = c;
mov eax, DWORD PTR _c$[ebp]
cdq
mov ecx, DWORD PTR _s$[ebp]
mov DWORD PTR [ecx+16], eax
mov DWORD PTR [ecx+20], edx
; 20 : }
mov esp, ebp
pop ebp
ret 0
_fill ENDP
_TEXT ENDS
PUBLIC __$ArrayPad$
PUBLIC _func
EXTRN __imp__printf:PROC
EXTRN __imp__gets:PROC
EXTRN ___security_cookie:DWORD
EXTRN @__security_check_cookie@4:PROC
; Function compile flags: /Odtp
_TEXT SEGMENT
_buf$ = -40 ; size = 8
_s$ = -32 ; size = 24
__$ArrayPad$ = -4 ; size = 4
_func PROC
; 23 : {
push ebp
mov ebp, esp
sub esp, 40 ; 00000028H
mov eax, DWORD PTR ___security_cookie
xor eax, ebp
mov DWORD PTR __$ArrayPad$[ebp], eax
; 24 : struct S s;
; 25 : char buf[8];
; 26 : gets(buf);
lea eax, DWORD PTR _buf$[ebp]
push eax
call DWORD PTR __imp__gets
add esp, 4
; 27 : fill(&s);
lea ecx, DWORD PTR _s$[ebp]
push ecx
call _fill
add esp, 4
; 28 : printf("%s %d %d %d\n", buf, (int)s.a, (int)s.b, (int)s.c);
mov edx, DWORD PTR _s$[ebp+16]
push edx
mov eax, DWORD PTR _s$[ebp+8]
push eax
mov ecx, DWORD PTR _s$[ebp]
push ecx
lea edx, DWORD PTR _buf$[ebp]
push edx
push OFFSET $SG3580
call DWORD PTR __imp__printf
add esp, 20 ; 00000014H
; 29 : }
mov ecx, DWORD PTR __$ArrayPad$[ebp]
xor ecx, ebp
call @__security_check_cookie@4
mov esp, ebp
pop ebp
ret 0
_func ENDP
_TEXT ENDS
PUBLIC _main
; Function compile flags: /Odtp
_TEXT SEGMENT
_main PROC
; 32 : {
push ebp
mov ebp, esp
; 33 : func();
call _func
; 34 : return 0;
xor eax, eax
; 35 : }
pop ebp
ret 0
_main ENDP
_TEXT ENDS
END
| Dovgalyuk/AntiTaint | Epilog/asm/MSVC2010/struct-stackp.asm | Assembly | apache-2.0 | 2,960 |
ivpu_immediateJump:
test r12, 0x10 #Check the architecture of the current instruction.
cmovz ebx, dword ptr [r13 + rdi + 4] #If the result of the check is 0, then this is a 32 bit instruction. As such, the instruction is only 4 bytes, se we use ebx to move the address in instruction part 2.
cmovnz rbx, qword ptr [r13 + rdi + 8] #If the result of the check is 1, then this is a 64 bit instruction, which is a full 8 bytes. We use ebx to move the address in instruction part 2.
mov rdi, rbx
jmp ivpu_fetch
| ozdevguy/Ditto | VM/src/Linux/VPU/x86_64/organized/bak/immjmp.asm | Assembly | apache-2.0 | 524 |
;===============================================================================
; Copyright 2015-2020 Intel Corporation
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;===============================================================================
;
;
; Purpose: Cryptography Primitive.
; Message block processing according to SHA1
;
; Content:
; UpdateSHA1
;
;
%include "asmdefs.inc"
%include "ia_32e.inc"
%include "pcpvariant.inc"
%if (_ENABLE_ALG_SHA1_)
%if (_SHA_NI_ENABLING_ == _FEATURE_OFF_) || (_SHA_NI_ENABLING_ == _FEATURE_TICKTOCK_)
;;%if (_IPP32E >= _IPP32E_E9 )
%if (_IPP32E == _IPP32E_E9 )
;;
;; SHA1 constants K[i]
%xdefine SHA1_K1 (05a827999h)
%xdefine SHA1_K2 (06ed9eba1h)
%xdefine SHA1_K3 (08f1bbcdch)
%xdefine SHA1_K4 (0ca62c1d6h)
;;
;; Magic functions defined in FIPS 180-1
;;
;; F1, F2, F3 and F4 assumes, that
;; - T1 returns function value
;; - T2 is the temporary
;;
%macro F1 3.nolist
%xdefine %%B %1
%xdefine %%C %2
%xdefine %%D %3
mov T1,%%C
xor T1,%%D
and T1,%%B
xor T1,%%D
%endmacro
%macro F2 3.nolist
%xdefine %%B %1
%xdefine %%C %2
%xdefine %%D %3
mov T1,%%D
xor T1,%%C
xor T1,%%B
%endmacro
%macro F3 3.nolist
%xdefine %%B %1
%xdefine %%C %2
%xdefine %%D %3
mov T1,%%C
mov T2,%%B
or T1,%%B
and T2,%%C
and T1,%%D
or T1,T2
%endmacro
%macro F4 3.nolist
%xdefine %%B %1
%xdefine %%C %2
%xdefine %%D %3
F2 %%B,%%C,%%D
%endmacro
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; rotations
;;
%macro ROL_5 1.nolist
%xdefine %%x %1
shld %%x,%%x, 5
%endmacro
%macro ROL_30 1.nolist
%xdefine %%x %1
shld %%x,%%x, 30
%endmacro
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; textual rotation of W array
;;
%macro ROTATE_W 0.nolist
%xdefine W_minus_32 W_minus_28
%xdefine W_minus_28 W_minus_24
%xdefine W_minus_24 W_minus_20
%xdefine W_minus_20 W_minus_16
%xdefine W_minus_16 W_minus_12
%xdefine W_minus_12 W_minus_08
%xdefine W_minus_08 W_minus_04
%xdefine W_minus_04 W
%xdefine W W_minus_32
%endmacro
;;
;; SHA1 update round:
;; - F1 magic is used (and imbedded into the macros directly)
;; - 16 bytes of input are swapped
;;
%macro SHA1_UPDATE_RND_F1_BSWAP 7.nolist
%xdefine %%A %1
%xdefine %%B %2
%xdefine %%C %3
%xdefine %%D %4
%xdefine %%E %5
%xdefine %%nr %6
%xdefine %%Wchunk %7
vpshufb W, %%Wchunk, XMM_SHUFB_BSWAP
vpaddd %%Wchunk, W, oword [K_XMM]
vmovdqa oword [rsp + (%%nr & 15)*4], %%Wchunk
mov T1,%%C ; F1
mov T2,%%A
xor T1,%%D ; F1
and T1,%%B ; F1
ROL_5 T2
xor T1,%%D ; F1
add %%E, T2
ROL_30 %%B
add T1, dword [rsp + (%%nr & 15)*4]
add %%E,T1
ROTATE_W
%endmacro
;;
;; SHA1 update round:
;; - F1 magic is used (and imbedded into the macros directly)
;;
%macro SHA1_UPDATE_RND_F1 6.nolist
%xdefine %%A %1
%xdefine %%B %2
%xdefine %%C %3
%xdefine %%D %4
%xdefine %%E %5
%xdefine %%nr %6
mov T1,%%C ; F1
mov T2,%%A
xor T1,%%D ; F1
ROL_5 T2
and T1,%%B ; F1
xor T1,%%D ; F1
add %%E, T2
ROL_30 %%B
add T1, dword [rsp + (%%nr & 15)*4]
add %%E,T1
%endmacro
;;
;; update W
;;
%macro W_CALC 1.nolist
%xdefine %%nr %1
%assign %%W_CALC_ahead 8
%assign %%i (%%nr + %%W_CALC_ahead)
%if (%%i < 20)
%xdefine K_XMM K_BASE
%elif (%%i < 40)
%xdefine K_XMM K_BASE+16
%elif (%%i < 60)
%xdefine K_XMM K_BASE+32
%else
%xdefine K_XMM K_BASE+48
%endif
%if (%%i < 32)
%if ((%%i & 3) == 0) ;; just scheduling to interleave with ALUs
vpalignr W, W_minus_12, W_minus_16, 8 ; w[i-14]
vpsrldq W_TMP, W_minus_04, 4 ; w[i-3]
vpxor W, W, W_minus_08
%elif ((%%i & 3) == 1)
vpxor W_TMP, W_TMP, W_minus_16
vpxor W, W, W_TMP
vpslldq W_TMP2, W, 12
%elif ((%%i & 3) == 2)
vpslld W_TMP, W, 1
vpsrld W, W, 31
vpor W_TMP, W_TMP, W
vpslld W, W_TMP2, 2
vpsrld W_TMP2, W_TMP2, 30
%elif ((%%i & 3) == 3)
vpxor W_TMP, W_TMP, W
vpxor W, W_TMP, W_TMP2
vpaddd W_TMP, W, oword [K_XMM]
vmovdqa oword [rsp + ((%%i & (~3)) & 15)*4],W_TMP
ROTATE_W
%endif
;; %elif (i < 83)
%elif (%%i < 80)
%if ((%%i & 3) == 0) ;; scheduling to interleave with ALUs
vpalignr W_TMP, W_minus_04, W_minus_08, 8
vpxor W, W, W_minus_28 ;; W == W_minus_32
%elif ((%%i & 3) == 1)
vpxor W_TMP, W_TMP, W_minus_16
vpxor W, W, W_TMP
%elif ((%%i & 3) == 2)
vpslld W_TMP, W, 2
vpsrld W, W, 30
vpor W, W_TMP, W
%elif ((%%i & 3) == 3)
vpaddd W_TMP, W, oword [K_XMM]
vmovdqa oword [rsp + ((%%i & (~3)) & 15)*4],W_TMP
ROTATE_W
%endif
%endif
%endmacro
;;
;; Regular hash update
;;
%macro SHA1_UPDATE_REGULAR 7.nolist
%xdefine %%A %1
%xdefine %%B %2
%xdefine %%C %3
%xdefine %%D %4
%xdefine %%E %5
%xdefine %%nr %6
%xdefine %%MagiF %7
W_CALC %%nr
add %%E, dword [rsp + (%%nr & 15)*4]
%%MagiF %%B,%%C,%%D
add %%D, dword [rsp +((%%nr+1) & 15)*4]
ROL_30 %%B
mov T3,%%A
add %%E, T1
ROL_5 T3
add T3, %%E
mov %%E, T3
W_CALC %%nr+1
ROL_5 T3
add %%D,T3
%%MagiF %%A,%%B,%%C
add %%D, T1
ROL_30 %%A
; write: %1, %2
; rotate: %1<=%4, %2<=%5, %3<=%1, %4<=%2, %5<=%3
%endmacro
;; update hash macro
%macro UPDATE_HASH 2.nolist
%xdefine %%hash0 %1
%xdefine %%hashAdd %2
add %%hashAdd, %%hash0
mov %%hash0, %%hashAdd
%endmacro
segment .text align=IPP_ALIGN_FACTOR
align IPP_ALIGN_FACTOR
K_XMM_AR dd SHA1_K1, SHA1_K1, SHA1_K1, SHA1_K1
dd SHA1_K2, SHA1_K2, SHA1_K2, SHA1_K2
dd SHA1_K3, SHA1_K3, SHA1_K3, SHA1_K3
dd SHA1_K4, SHA1_K4, SHA1_K4, SHA1_K4
shuffle_mask DD 00010203h
DD 04050607h
DD 08090a0bh
DD 0c0d0e0fh
;*****************************************************************************************
;* Purpose: Update internal digest according to message block
;*
;* void UpdateSHA1(DigestSHA1 digest, const Ipp32u* mblk, int mlen, const void* pParam)
;*
;*****************************************************************************************
;;
;; Lib = Y8
;;
;; Caller = ippsSHA1Update
;; Caller = ippsSHA1Final
;; Caller = ippsSHA1MessageDigest
;;
;; Caller = ippsHMACSHA1Update
;; Caller = ippsHMACSHA1Final
;; Caller = ippsHMACSHA1MessageDigest
;;
;; assign hash values to GPU registers
%xdefine A ecx
%xdefine B eax
%xdefine C edx
%xdefine D r8d
%xdefine E r9d
;; temporary
%xdefine T1 r10d
%xdefine T2 r11d
%xdefine T3 r13d
%xdefine T4 r13d
%xdefine W_TMP xmm0
%xdefine W_TMP2 xmm1
%xdefine W0 xmm2
%xdefine W4 xmm3
%xdefine W8 xmm4
%xdefine W12 xmm5
%xdefine W16 xmm6
%xdefine W20 xmm7
%xdefine W24 xmm8
%xdefine W28 xmm9
;; endianness swap constant
%xdefine XMM_SHUFB_BSWAP xmm10
;; K_BASE contains [K_XMM_AR] address
%xdefine K_BASE r12
align IPP_ALIGN_FACTOR
IPPASM UpdateSHA1,PUBLIC
%assign LOCAL_FRAME (16*4)
USES_GPR rdi,rsi,r12,r13,r14
USES_XMM_AVX xmm6,xmm7,xmm8,xmm9,xmm10
COMP_ABI 4
;;
;; rdi = digest ptr
;; rsi = data block ptr
;; rdx = data length
;; rcx = dummy
%xdefine MBS_SHA1 (64)
movsxd r14, edx
movdqa XMM_SHUFB_BSWAP, oword [rel shuffle_mask] ; load shuffle mask
lea K_BASE, [rel K_XMM_AR] ; SHA1 const array address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; process next data block
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
.sha1_block_loop:
mov A, dword [rdi] ; load initial hash value
mov B, dword [rdi+4]
mov C, dword [rdi+8]
mov D, dword [rdi+12]
mov E, dword [rdi+16]
movdqu W28, oword [rsi] ; load buffer content
movdqu W24, oword [rsi+16]
movdqu W20, oword [rsi+32]
movdqu W16, oword [rsi+48]
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;SHA1_MAIN_BODY
%xdefine W W0
%xdefine W_minus_04 W4
%xdefine W_minus_08 W8
%xdefine W_minus_12 W12
%xdefine W_minus_16 W16
%xdefine W_minus_20 W20
%xdefine W_minus_24 W24
%xdefine W_minus_28 W28
%xdefine W_minus_32 W
;; assignment
%xdefine K_XMM K_BASE
;;F textequ <F1>
SHA1_UPDATE_RND_F1_BSWAP A,B,C,D,E, 0, W28
SHA1_UPDATE_RND_F1 E,A,B,C,D, 1
SHA1_UPDATE_RND_F1 D,E,A,B,C, 2
SHA1_UPDATE_RND_F1 C,D,E,A,B, 3
SHA1_UPDATE_RND_F1_BSWAP B,C,D,E,A, 4, W24
SHA1_UPDATE_RND_F1 A,B,C,D,E, 5
SHA1_UPDATE_RND_F1 E,A,B,C,D, 6
SHA1_UPDATE_RND_F1 D,E,A,B,C, 7
SHA1_UPDATE_RND_F1_BSWAP C,D,E,A,B, 8, W20
SHA1_UPDATE_RND_F1 B,C,D,E,A, 9
SHA1_UPDATE_RND_F1 A,B,C,D,E, 10
SHA1_UPDATE_RND_F1 E,A,B,C,D, 11
SHA1_UPDATE_RND_F1_BSWAP D,E,A,B,C, 12, W16
W_CALC 8
W_CALC 9
W_CALC 10
SHA1_UPDATE_RND_F1 C,D,E,A,B, 13
W_CALC 11
W_CALC 12
SHA1_UPDATE_RND_F1 B,C,D,E,A, 14
W_CALC 13
W_CALC 14
W_CALC 15
SHA1_UPDATE_RND_F1 A,B,C,D,E, 15
SHA1_UPDATE_REGULAR E,A,B,C,D,16, F1
SHA1_UPDATE_REGULAR C,D,E,A,B,18, F1
;;F textequ <F2>
SHA1_UPDATE_REGULAR A,B,C,D,E,20, F2
SHA1_UPDATE_REGULAR D,E,A,B,C,22, F2
SHA1_UPDATE_REGULAR B,C,D,E,A,24, F2
SHA1_UPDATE_REGULAR E,A,B,C,D,26, F2
SHA1_UPDATE_REGULAR C,D,E,A,B,28, F2
SHA1_UPDATE_REGULAR A,B,C,D,E,30, F2
SHA1_UPDATE_REGULAR D,E,A,B,C,32, F2
SHA1_UPDATE_REGULAR B,C,D,E,A,34, F2
SHA1_UPDATE_REGULAR E,A,B,C,D,36, F2
SHA1_UPDATE_REGULAR C,D,E,A,B,38, F2
;;F textequ <F3>
SHA1_UPDATE_REGULAR A,B,C,D,E,40, F3
SHA1_UPDATE_REGULAR D,E,A,B,C,42, F3
SHA1_UPDATE_REGULAR B,C,D,E,A,44, F3
SHA1_UPDATE_REGULAR E,A,B,C,D,46, F3
SHA1_UPDATE_REGULAR C,D,E,A,B,48, F3
SHA1_UPDATE_REGULAR A,B,C,D,E,50, F3
SHA1_UPDATE_REGULAR D,E,A,B,C,52, F3
SHA1_UPDATE_REGULAR B,C,D,E,A,54, F3
SHA1_UPDATE_REGULAR E,A,B,C,D,56, F3
SHA1_UPDATE_REGULAR C,D,E,A,B,58, F3
;;F textequ <F4>
SHA1_UPDATE_REGULAR A,B,C,D,E,60, F4
SHA1_UPDATE_REGULAR D,E,A,B,C,62, F4
SHA1_UPDATE_REGULAR B,C,D,E,A,64, F4
SHA1_UPDATE_REGULAR E,A,B,C,D,66, F4
SHA1_UPDATE_REGULAR C,D,E,A,B,68, F4
SHA1_UPDATE_REGULAR A,B,C,D,E,70, F4
SHA1_UPDATE_REGULAR D,E,A,B,C,72, F4
SHA1_UPDATE_REGULAR B,C,D,E,A,74, F4
SHA1_UPDATE_REGULAR E,A,B,C,D,76, F4
SHA1_UPDATE_REGULAR C,D,E,A,B,78, F4
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
UPDATE_HASH dword [rdi], A
UPDATE_HASH dword [rdi+4], B
UPDATE_HASH dword [rdi+8], C
UPDATE_HASH dword [rdi+12],D
UPDATE_HASH dword [rdi+16],E
add rsi, MBS_SHA1
sub r14, MBS_SHA1
jg .sha1_block_loop
REST_XMM_AVX
REST_GPR
ret
ENDFUNC UpdateSHA1
%endif ;; _IPP32E >= _IPP32E_E9
%endif ;; _FEATURE_OFF_ / _FEATURE_TICKTOCK_
%endif ;; _ENABLE_ALG_SHA1_
| Intel-EPID-SDK/epid-sdk | ext/ipp-crypto/sources/ippcp/asm_intel64/pcpsha1e9as.asm | Assembly | apache-2.0 | 12,197 |
TITLE rc4-586.asm
IF @Version LT 800
ECHO MASM version 8.00 or later is strongly recommended.
ENDIF
.586
.MODEL FLAT
OPTION DOTNAME
IF @Version LT 800
.text$ SEGMENT PAGE 'CODE'
ELSE
.text$ SEGMENT ALIGN(64) 'CODE'
ENDIF
ALIGN 16
_RC4 PROC PUBLIC
$L_RC4_begin::
push ebp
push ebx
push esi
push edi
mov edi,DWORD PTR 20[esp]
mov edx,DWORD PTR 24[esp]
mov esi,DWORD PTR 28[esp]
mov ebp,DWORD PTR 32[esp]
xor eax,eax
xor ebx,ebx
cmp edx,0
je $L000abort
mov al,BYTE PTR [edi]
mov bl,BYTE PTR 4[edi]
add edi,8
lea ecx,DWORD PTR [edx*1+esi]
sub ebp,esi
mov DWORD PTR 24[esp],ecx
inc al
cmp DWORD PTR 256[edi],-1
je $L001RC4_CHAR
mov ecx,DWORD PTR [eax*4+edi]
and edx,-4
jz $L002loop1
lea edx,DWORD PTR [edx*1+esi-4]
mov DWORD PTR 28[esp],edx
mov DWORD PTR 32[esp],ebp
ALIGN 16
$L003loop4:
add bl,cl
mov edx,DWORD PTR [ebx*4+edi]
mov DWORD PTR [ebx*4+edi],ecx
mov DWORD PTR [eax*4+edi],edx
add edx,ecx
inc al
and edx,255
mov ecx,DWORD PTR [eax*4+edi]
mov ebp,DWORD PTR [edx*4+edi]
add bl,cl
mov edx,DWORD PTR [ebx*4+edi]
mov DWORD PTR [ebx*4+edi],ecx
mov DWORD PTR [eax*4+edi],edx
add edx,ecx
inc al
and edx,255
ror ebp,8
mov ecx,DWORD PTR [eax*4+edi]
or ebp,DWORD PTR [edx*4+edi]
add bl,cl
mov edx,DWORD PTR [ebx*4+edi]
mov DWORD PTR [ebx*4+edi],ecx
mov DWORD PTR [eax*4+edi],edx
add edx,ecx
inc al
and edx,255
ror ebp,8
mov ecx,DWORD PTR [eax*4+edi]
or ebp,DWORD PTR [edx*4+edi]
add bl,cl
mov edx,DWORD PTR [ebx*4+edi]
mov DWORD PTR [ebx*4+edi],ecx
mov DWORD PTR [eax*4+edi],edx
add edx,ecx
inc al
and edx,255
ror ebp,8
mov ecx,DWORD PTR 32[esp]
or ebp,DWORD PTR [edx*4+edi]
ror ebp,8
xor ebp,DWORD PTR [esi]
cmp esi,DWORD PTR 28[esp]
mov DWORD PTR [esi*1+ecx],ebp
lea esi,DWORD PTR 4[esi]
mov ecx,DWORD PTR [eax*4+edi]
jb $L003loop4
cmp esi,DWORD PTR 24[esp]
je $L004done
mov ebp,DWORD PTR 32[esp]
ALIGN 16
$L002loop1:
add bl,cl
mov edx,DWORD PTR [ebx*4+edi]
mov DWORD PTR [ebx*4+edi],ecx
mov DWORD PTR [eax*4+edi],edx
add edx,ecx
inc al
and edx,255
mov edx,DWORD PTR [edx*4+edi]
xor dl,BYTE PTR [esi]
lea esi,DWORD PTR 1[esi]
mov ecx,DWORD PTR [eax*4+edi]
cmp esi,DWORD PTR 24[esp]
mov BYTE PTR [esi*1+ebp-1],dl
jb $L002loop1
jmp $L004done
ALIGN 16
$L001RC4_CHAR:
movzx ecx,BYTE PTR [eax*1+edi]
$L005cloop1:
add bl,cl
movzx edx,BYTE PTR [ebx*1+edi]
mov BYTE PTR [ebx*1+edi],cl
mov BYTE PTR [eax*1+edi],dl
add dl,cl
movzx edx,BYTE PTR [edx*1+edi]
add al,1
xor dl,BYTE PTR [esi]
lea esi,DWORD PTR 1[esi]
movzx ecx,BYTE PTR [eax*1+edi]
cmp esi,DWORD PTR 24[esp]
mov BYTE PTR [esi*1+ebp-1],dl
jb $L005cloop1
$L004done:
dec al
mov BYTE PTR [edi-4],bl
mov BYTE PTR [edi-8],al
$L000abort:
pop edi
pop esi
pop ebx
pop ebp
ret
_RC4 ENDP
;EXTERN _OPENSSL_ia32cap_P:NEAR
ALIGN 16
_RC4_set_key PROC PUBLIC
$L_RC4_set_key_begin::
push ebp
push ebx
push esi
push edi
mov edi,DWORD PTR 20[esp]
mov ebp,DWORD PTR 24[esp]
mov esi,DWORD PTR 28[esp]
lea edx,DWORD PTR _OPENSSL_ia32cap_P
lea edi,DWORD PTR 8[edi]
lea esi,DWORD PTR [ebp*1+esi]
neg ebp
xor eax,eax
mov DWORD PTR [edi-4],ebp
bt DWORD PTR [edx],20
jc $L006c1stloop
ALIGN 16
$L007w1stloop:
mov DWORD PTR [eax*4+edi],eax
add al,1
jnc $L007w1stloop
xor ecx,ecx
xor edx,edx
ALIGN 16
$L008w2ndloop:
mov eax,DWORD PTR [ecx*4+edi]
add dl,BYTE PTR [ebp*1+esi]
add dl,al
add ebp,1
mov ebx,DWORD PTR [edx*4+edi]
jnz $L009wnowrap
mov ebp,DWORD PTR [edi-4]
$L009wnowrap:
mov DWORD PTR [edx*4+edi],eax
mov DWORD PTR [ecx*4+edi],ebx
add cl,1
jnc $L008w2ndloop
jmp $L010exit
ALIGN 16
$L006c1stloop:
mov BYTE PTR [eax*1+edi],al
add al,1
jnc $L006c1stloop
xor ecx,ecx
xor edx,edx
xor ebx,ebx
ALIGN 16
$L011c2ndloop:
mov al,BYTE PTR [ecx*1+edi]
add dl,BYTE PTR [ebp*1+esi]
add dl,al
add ebp,1
mov bl,BYTE PTR [edx*1+edi]
jnz $L012cnowrap
mov ebp,DWORD PTR [edi-4]
$L012cnowrap:
mov BYTE PTR [edx*1+edi],al
mov BYTE PTR [ecx*1+edi],bl
add cl,1
jnc $L011c2ndloop
mov DWORD PTR 256[edi],-1
$L010exit:
xor eax,eax
mov DWORD PTR [edi-8],eax
mov DWORD PTR [edi-4],eax
pop edi
pop esi
pop ebx
pop ebp
ret
_RC4_set_key ENDP
ALIGN 16
_RC4_options PROC PUBLIC
$L_RC4_options_begin::
call $L013pic_point
$L013pic_point:
pop eax
lea eax,DWORD PTR ($L014opts-$L013pic_point)[eax]
lea edx,DWORD PTR _OPENSSL_ia32cap_P
bt DWORD PTR [edx],20
jnc $L015skip
add eax,12
$L015skip:
ret
ALIGN 64
$L014opts:
DB 114,99,52,40,52,120,44,105,110,116,41,0
DB 114,99,52,40,49,120,44,99,104,97,114,41,0
DB 82,67,52,32,102,111,114,32,120,56,54,44,32,67,82,89
DB 80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114
DB 111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
ALIGN 64
_RC4_options ENDP
.text$ ENDS
.bss SEGMENT 'BSS'
COMM _OPENSSL_ia32cap_P:DWORD
.bss ENDS
END
| mosaic-cloud/mosaic-distribution-dependencies | dependencies/nodejs/0.8.22/deps/openssl/asm/x86-win32-masm/rc4/rc4-586.asm | Assembly | apache-2.0 | 4,745 |
# -*- tab-width : 4 -*-
#
#
.sect prog
start:
rts
| hirakuni45/glfw3_app | glfw3_app/rx_asm/test.asm | Assembly | bsd-3-clause | 54 |
;#**************************
;#* LIGHTS * Kolibri OS
;#************************** 15/10/2007
include 'main.inc'
include 'data.inc'
include 'macs.inc'
BeginProgram
main_loop
DATA_SECTION
EndProgram
| devlato/kolibrios-llvm | programs/games/lights/trunk/lights.asm | Assembly | mit | 228 |
;------------------------------------------------
;============Практическое задание================
;----Дана строка.
;----Поменять в ней прописные на заглавные и наоборот, заглавные на прописные
;@author Andrew Ushchenko (https://github.com/AndrewUshchenko) <andrew@uas-proger.net>
;-----Start code-----
formList segment 'code'
assume CS:formList, DS:data
;---Start process
begin: mov AX,data
mov DS,AX ;Not data->DS
mov AH, 09h
mov DX, offset helloMsg
int 21h ; приглашение на экран
mov AH, 0ah
lea DX,buf
int 21h ; вводим строку
mov AH, 09h
mov DX,offset resultMsg
int 21h ; Result string
mov DX, offset newLine
int 21h
lea SI, string ; адрес строки
mov DH, 0 ; предыдущий символ
mov BL,0
FOREACH:
inc BL
lodsb ; очередной
cmp AL, 0dh ; введенная строка заканчивается кодом 0dh
je exit
cmp BL,1
jle FOREACH
cmp AL, ' '
je PRINT
cmp AL, 'A'
jl FOREACH
cmp AL,'Z'
jle lowstr
cmp AL,'a'
jl FOREACH
cmp AL,'z'
jle upstr
lowstr:
add AL, 20h
jmp print
upstr:
sub AL,20h
jmp print
print:
mov AH,02h
mov DL,offset AL
int 21h ; и выведем
jmp FOREACH
exit:
mov AH, 09h
mov DX, offset endMsg
int 21h
mov AX, 4c00h
int 21h
formList ends ;End CodeSegment (CS)
data segment ;Here data (string message, value)
helloMsg db 10,'Hello, please enter string',10,'$'
newLine db 10,'$'
resultMsg db 10,'Result string: $'
endMsg db 10,'DONE!$'
buf db 128; буфер для приема строки с клавиатуры
string db 128
data ends ;End DataSegment
stk segment stack
dw 128 dup(0)
stk ends
end begin;End
| AndrewUshchenko/AsmScript | kr2.asm | Assembly | mit | 1,808 |
;*****************************************************************
;* - Description: Device definition file for RC Calibration
;* - File: m128.asm
;* - AppNote: AVR053 - Production calibration of the
;* RC oscillator
;*
;* - Author: Atmel Corporation: http://www.atmel.com
;* Support email: avr@atmel.com
;*
;* $Name$
;* $Revision: 56 $
;* $RCSfile$
;* $Date: 2006-02-16 17:44:45 +0100 (to, 16 feb 2006) $
;*****************************************************************
.include "m128def.inc"
.include "Common\memoryMap.inc"
.include "Device specific\m128_family_pinout.inc"
.equ OSC_VER = 3
| smart-electro/BMS_SLAVE_V2.0 | Software/AtTiny_programmer/RC calib Projekt/Device specific/m128.asm | Assembly | cc0-1.0 | 658 |
TITLE sha512-586.asm
IF @Version LT 800
ECHO MASM version 8.00 or later is strongly recommended.
ENDIF
.586
.MODEL FLAT
OPTION DOTNAME
IF @Version LT 800
.text$ SEGMENT PAGE 'CODE'
ELSE
.text$ SEGMENT ALIGN(64) 'CODE'
ENDIF
ALIGN 16
_sha512_block_data_order PROC PUBLIC
$L_sha512_block_data_order_begin::
push ebp
push ebx
push esi
push edi
mov esi,DWORD PTR 20[esp]
mov edi,DWORD PTR 24[esp]
mov eax,DWORD PTR 28[esp]
mov ebx,esp
call $L000pic_point
$L000pic_point:
pop ebp
lea ebp,DWORD PTR ($L001K512-$L000pic_point)[ebp]
sub esp,16
and esp,-64
shl eax,7
add eax,edi
mov DWORD PTR [esp],esi
mov DWORD PTR 4[esp],edi
mov DWORD PTR 8[esp],eax
mov DWORD PTR 12[esp],ebx
ALIGN 16
$L002loop_x86:
mov eax,DWORD PTR [edi]
mov ebx,DWORD PTR 4[edi]
mov ecx,DWORD PTR 8[edi]
mov edx,DWORD PTR 12[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 16[edi]
mov ebx,DWORD PTR 20[edi]
mov ecx,DWORD PTR 24[edi]
mov edx,DWORD PTR 28[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 32[edi]
mov ebx,DWORD PTR 36[edi]
mov ecx,DWORD PTR 40[edi]
mov edx,DWORD PTR 44[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 48[edi]
mov ebx,DWORD PTR 52[edi]
mov ecx,DWORD PTR 56[edi]
mov edx,DWORD PTR 60[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 64[edi]
mov ebx,DWORD PTR 68[edi]
mov ecx,DWORD PTR 72[edi]
mov edx,DWORD PTR 76[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 80[edi]
mov ebx,DWORD PTR 84[edi]
mov ecx,DWORD PTR 88[edi]
mov edx,DWORD PTR 92[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 96[edi]
mov ebx,DWORD PTR 100[edi]
mov ecx,DWORD PTR 104[edi]
mov edx,DWORD PTR 108[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
mov eax,DWORD PTR 112[edi]
mov ebx,DWORD PTR 116[edi]
mov ecx,DWORD PTR 120[edi]
mov edx,DWORD PTR 124[edi]
bswap eax
bswap ebx
bswap ecx
bswap edx
push eax
push ebx
push ecx
push edx
add edi,128
sub esp,72
mov DWORD PTR 204[esp],edi
lea edi,DWORD PTR 8[esp]
mov ecx,16
DD 2784229001
ALIGN 16
$L00300_15_x86:
mov ecx,DWORD PTR 40[esp]
mov edx,DWORD PTR 44[esp]
mov esi,ecx
shr ecx,9
mov edi,edx
shr edx,9
mov ebx,ecx
shl esi,14
mov eax,edx
shl edi,14
xor ebx,esi
shr ecx,5
xor eax,edi
shr edx,5
xor eax,ecx
shl esi,4
xor ebx,edx
shl edi,4
xor ebx,esi
shr ecx,4
xor eax,edi
shr edx,4
xor eax,ecx
shl esi,5
xor ebx,edx
shl edi,5
xor eax,esi
xor ebx,edi
mov ecx,DWORD PTR 48[esp]
mov edx,DWORD PTR 52[esp]
mov esi,DWORD PTR 56[esp]
mov edi,DWORD PTR 60[esp]
add eax,DWORD PTR 64[esp]
adc ebx,DWORD PTR 68[esp]
xor ecx,esi
xor edx,edi
and ecx,DWORD PTR 40[esp]
and edx,DWORD PTR 44[esp]
add eax,DWORD PTR 192[esp]
adc ebx,DWORD PTR 196[esp]
xor ecx,esi
xor edx,edi
mov esi,DWORD PTR [ebp]
mov edi,DWORD PTR 4[ebp]
add eax,ecx
adc ebx,edx
mov ecx,DWORD PTR 32[esp]
mov edx,DWORD PTR 36[esp]
add eax,esi
adc ebx,edi
mov DWORD PTR [esp],eax
mov DWORD PTR 4[esp],ebx
add eax,ecx
adc ebx,edx
mov ecx,DWORD PTR 8[esp]
mov edx,DWORD PTR 12[esp]
mov DWORD PTR 32[esp],eax
mov DWORD PTR 36[esp],ebx
mov esi,ecx
shr ecx,2
mov edi,edx
shr edx,2
mov ebx,ecx
shl esi,4
mov eax,edx
shl edi,4
xor ebx,esi
shr ecx,5
xor eax,edi
shr edx,5
xor ebx,ecx
shl esi,21
xor eax,edx
shl edi,21
xor eax,esi
shr ecx,21
xor ebx,edi
shr edx,21
xor eax,ecx
shl esi,5
xor ebx,edx
shl edi,5
xor eax,esi
xor ebx,edi
mov ecx,DWORD PTR 8[esp]
mov edx,DWORD PTR 12[esp]
mov esi,DWORD PTR 16[esp]
mov edi,DWORD PTR 20[esp]
add eax,DWORD PTR [esp]
adc ebx,DWORD PTR 4[esp]
or ecx,esi
or edx,edi
and ecx,DWORD PTR 24[esp]
and edx,DWORD PTR 28[esp]
and esi,DWORD PTR 8[esp]
and edi,DWORD PTR 12[esp]
or ecx,esi
or edx,edi
add eax,ecx
adc ebx,edx
mov DWORD PTR [esp],eax
mov DWORD PTR 4[esp],ebx
mov dl,BYTE PTR [ebp]
sub esp,8
lea ebp,DWORD PTR 8[ebp]
cmp dl,148
jne $L00300_15_x86
ALIGN 16
$L00416_79_x86:
mov ecx,DWORD PTR 312[esp]
mov edx,DWORD PTR 316[esp]
mov esi,ecx
shr ecx,1
mov edi,edx
shr edx,1
mov eax,ecx
shl esi,24
mov ebx,edx
shl edi,24
xor ebx,esi
shr ecx,6
xor eax,edi
shr edx,6
xor eax,ecx
shl esi,7
xor ebx,edx
shl edi,1
xor ebx,esi
shr ecx,1
xor eax,edi
shr edx,1
xor eax,ecx
shl edi,6
xor ebx,edx
xor eax,edi
mov DWORD PTR [esp],eax
mov DWORD PTR 4[esp],ebx
mov ecx,DWORD PTR 208[esp]
mov edx,DWORD PTR 212[esp]
mov esi,ecx
shr ecx,6
mov edi,edx
shr edx,6
mov eax,ecx
shl esi,3
mov ebx,edx
shl edi,3
xor eax,esi
shr ecx,13
xor ebx,edi
shr edx,13
xor eax,ecx
shl esi,10
xor ebx,edx
shl edi,10
xor ebx,esi
shr ecx,10
xor eax,edi
shr edx,10
xor ebx,ecx
shl edi,13
xor eax,edx
xor eax,edi
mov ecx,DWORD PTR 320[esp]
mov edx,DWORD PTR 324[esp]
add eax,DWORD PTR [esp]
adc ebx,DWORD PTR 4[esp]
mov esi,DWORD PTR 248[esp]
mov edi,DWORD PTR 252[esp]
add eax,ecx
adc ebx,edx
add eax,esi
adc ebx,edi
mov DWORD PTR 192[esp],eax
mov DWORD PTR 196[esp],ebx
mov ecx,DWORD PTR 40[esp]
mov edx,DWORD PTR 44[esp]
mov esi,ecx
shr ecx,9
mov edi,edx
shr edx,9
mov ebx,ecx
shl esi,14
mov eax,edx
shl edi,14
xor ebx,esi
shr ecx,5
xor eax,edi
shr edx,5
xor eax,ecx
shl esi,4
xor ebx,edx
shl edi,4
xor ebx,esi
shr ecx,4
xor eax,edi
shr edx,4
xor eax,ecx
shl esi,5
xor ebx,edx
shl edi,5
xor eax,esi
xor ebx,edi
mov ecx,DWORD PTR 48[esp]
mov edx,DWORD PTR 52[esp]
mov esi,DWORD PTR 56[esp]
mov edi,DWORD PTR 60[esp]
add eax,DWORD PTR 64[esp]
adc ebx,DWORD PTR 68[esp]
xor ecx,esi
xor edx,edi
and ecx,DWORD PTR 40[esp]
and edx,DWORD PTR 44[esp]
add eax,DWORD PTR 192[esp]
adc ebx,DWORD PTR 196[esp]
xor ecx,esi
xor edx,edi
mov esi,DWORD PTR [ebp]
mov edi,DWORD PTR 4[ebp]
add eax,ecx
adc ebx,edx
mov ecx,DWORD PTR 32[esp]
mov edx,DWORD PTR 36[esp]
add eax,esi
adc ebx,edi
mov DWORD PTR [esp],eax
mov DWORD PTR 4[esp],ebx
add eax,ecx
adc ebx,edx
mov ecx,DWORD PTR 8[esp]
mov edx,DWORD PTR 12[esp]
mov DWORD PTR 32[esp],eax
mov DWORD PTR 36[esp],ebx
mov esi,ecx
shr ecx,2
mov edi,edx
shr edx,2
mov ebx,ecx
shl esi,4
mov eax,edx
shl edi,4
xor ebx,esi
shr ecx,5
xor eax,edi
shr edx,5
xor ebx,ecx
shl esi,21
xor eax,edx
shl edi,21
xor eax,esi
shr ecx,21
xor ebx,edi
shr edx,21
xor eax,ecx
shl esi,5
xor ebx,edx
shl edi,5
xor eax,esi
xor ebx,edi
mov ecx,DWORD PTR 8[esp]
mov edx,DWORD PTR 12[esp]
mov esi,DWORD PTR 16[esp]
mov edi,DWORD PTR 20[esp]
add eax,DWORD PTR [esp]
adc ebx,DWORD PTR 4[esp]
or ecx,esi
or edx,edi
and ecx,DWORD PTR 24[esp]
and edx,DWORD PTR 28[esp]
and esi,DWORD PTR 8[esp]
and edi,DWORD PTR 12[esp]
or ecx,esi
or edx,edi
add eax,ecx
adc ebx,edx
mov DWORD PTR [esp],eax
mov DWORD PTR 4[esp],ebx
mov dl,BYTE PTR [ebp]
sub esp,8
lea ebp,DWORD PTR 8[ebp]
cmp dl,23
jne $L00416_79_x86
mov esi,DWORD PTR 840[esp]
mov edi,DWORD PTR 844[esp]
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov ecx,DWORD PTR 8[esi]
mov edx,DWORD PTR 12[esi]
add eax,DWORD PTR 8[esp]
adc ebx,DWORD PTR 12[esp]
mov DWORD PTR [esi],eax
mov DWORD PTR 4[esi],ebx
add ecx,DWORD PTR 16[esp]
adc edx,DWORD PTR 20[esp]
mov DWORD PTR 8[esi],ecx
mov DWORD PTR 12[esi],edx
mov eax,DWORD PTR 16[esi]
mov ebx,DWORD PTR 20[esi]
mov ecx,DWORD PTR 24[esi]
mov edx,DWORD PTR 28[esi]
add eax,DWORD PTR 24[esp]
adc ebx,DWORD PTR 28[esp]
mov DWORD PTR 16[esi],eax
mov DWORD PTR 20[esi],ebx
add ecx,DWORD PTR 32[esp]
adc edx,DWORD PTR 36[esp]
mov DWORD PTR 24[esi],ecx
mov DWORD PTR 28[esi],edx
mov eax,DWORD PTR 32[esi]
mov ebx,DWORD PTR 36[esi]
mov ecx,DWORD PTR 40[esi]
mov edx,DWORD PTR 44[esi]
add eax,DWORD PTR 40[esp]
adc ebx,DWORD PTR 44[esp]
mov DWORD PTR 32[esi],eax
mov DWORD PTR 36[esi],ebx
add ecx,DWORD PTR 48[esp]
adc edx,DWORD PTR 52[esp]
mov DWORD PTR 40[esi],ecx
mov DWORD PTR 44[esi],edx
mov eax,DWORD PTR 48[esi]
mov ebx,DWORD PTR 52[esi]
mov ecx,DWORD PTR 56[esi]
mov edx,DWORD PTR 60[esi]
add eax,DWORD PTR 56[esp]
adc ebx,DWORD PTR 60[esp]
mov DWORD PTR 48[esi],eax
mov DWORD PTR 52[esi],ebx
add ecx,DWORD PTR 64[esp]
adc edx,DWORD PTR 68[esp]
mov DWORD PTR 56[esi],ecx
mov DWORD PTR 60[esi],edx
add esp,840
sub ebp,640
cmp edi,DWORD PTR 8[esp]
jb $L002loop_x86
mov esp,DWORD PTR 12[esp]
pop edi
pop esi
pop ebx
pop ebp
ret
ALIGN 64
$L001K512:
DD 3609767458,1116352408
DD 602891725,1899447441
DD 3964484399,3049323471
DD 2173295548,3921009573
DD 4081628472,961987163
DD 3053834265,1508970993
DD 2937671579,2453635748
DD 3664609560,2870763221
DD 2734883394,3624381080
DD 1164996542,310598401
DD 1323610764,607225278
DD 3590304994,1426881987
DD 4068182383,1925078388
DD 991336113,2162078206
DD 633803317,2614888103
DD 3479774868,3248222580
DD 2666613458,3835390401
DD 944711139,4022224774
DD 2341262773,264347078
DD 2007800933,604807628
DD 1495990901,770255983
DD 1856431235,1249150122
DD 3175218132,1555081692
DD 2198950837,1996064986
DD 3999719339,2554220882
DD 766784016,2821834349
DD 2566594879,2952996808
DD 3203337956,3210313671
DD 1034457026,3336571891
DD 2466948901,3584528711
DD 3758326383,113926993
DD 168717936,338241895
DD 1188179964,666307205
DD 1546045734,773529912
DD 1522805485,1294757372
DD 2643833823,1396182291
DD 2343527390,1695183700
DD 1014477480,1986661051
DD 1206759142,2177026350
DD 344077627,2456956037
DD 1290863460,2730485921
DD 3158454273,2820302411
DD 3505952657,3259730800
DD 106217008,3345764771
DD 3606008344,3516065817
DD 1432725776,3600352804
DD 1467031594,4094571909
DD 851169720,275423344
DD 3100823752,430227734
DD 1363258195,506948616
DD 3750685593,659060556
DD 3785050280,883997877
DD 3318307427,958139571
DD 3812723403,1322822218
DD 2003034995,1537002063
DD 3602036899,1747873779
DD 1575990012,1955562222
DD 1125592928,2024104815
DD 2716904306,2227730452
DD 442776044,2361852424
DD 593698344,2428436474
DD 3733110249,2756734187
DD 2999351573,3204031479
DD 3815920427,3329325298
DD 3928383900,3391569614
DD 566280711,3515267271
DD 3454069534,3940187606
DD 4000239992,4118630271
DD 1914138554,116418474
DD 2731055270,174292421
DD 3203993006,289380356
DD 320620315,460393269
DD 587496836,685471733
DD 1086792851,852142971
DD 365543100,1017036298
DD 2618297676,1126000580
DD 3409855158,1288033470
DD 4234509866,1501505948
DD 987167468,1607167915
DD 1246189591,1816402316
_sha512_block_data_order ENDP
DB 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97
DB 110,115,102,111,114,109,32,102,111,114,32,120,56,54,44,32
DB 67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97
DB 112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103
DB 62,0
.text$ ENDS
END
| mosaic-cloud/mosaic-distribution-dependencies | dependencies/nodejs/0.8.22/deps/openssl/asm/x86-win32-masm/sha/sha512-586.asm | Assembly | apache-2.0 | 10,850 |
; complete Hello World PE example, as if compiled via MASM, including RichHeader, dos stubs, alignments...
%include '..\..\consts.asm'
%define iround(n, r) (((n + (r - 1)) / r) * r)
org IMAGEBASE
SECTIONALIGN EQU 1000h
FILEALIGN EQU 200h
DOS_HEADER:
.e_magic dw 'MZ'
.e_cblp dw 090h
.e_cp dw 3
.e_crlc dw 0
.e_cparhdr dw (dos_stub - DOS_HEADER) >> 4 ; defines MZ stub entry point
.e_minalloc dw 0
.e_maxalloc dw 0ffffh
.e_ss dw 0
.e_sp dw 0b8h
.e_csum dw 0
.e_ip dw 0
.e_cs dw 0
.e_lfarlc dw 040h
.e_ovno dw 0
.e_res dw 0,0,0,0
.e_oemid dw 0
.e_oeminfo dw 0
.e_res2 times 10 dw 0
align 03ch, db 0 ; in case we change things in DOS_HEADER
.e_lfanew dd NT_SIGNATURE - IMAGEBASE ; CRITICAL
align 010h, db 0
dos_stub:
bits 16
push cs
pop ds
mov dx, dos_msg - dos_stub
mov ah, 9
int 21h
mov ax, 4c01h
int 21h
dos_msg
db 'This program cannot be run in DOS mode.', 0dh, 0dh, 0ah, '$'
; db 'Win32 EXE!',7,0dh,0ah,'$'
align 16, db 0
RichHeader:
RichKey EQU 092033d19h
dd "DanS" ^ RichKey , 0 ^ RichKey, 0 ^ RichKey , 0 ^ RichKey
dd 0131f8eh ^ RichKey , 7 ^ RichKey, 01220fch ^ RichKey, 1 ^ RichKey
dd "Rich", 0 ^ RichKey , 0, 0
align 16, db 0
NT_SIGNATURE:
db 'PE',0,0
FILE_HEADER:
.Machine dw IMAGE_FILE_MACHINE_I386
.NumberOfSections dw NUMBEROFSECTIONS
.TimeDateStamp dd 04b51f504h ; 2010/1/16 5:19pm
.PointerToSymbolTable dd 0
.NumberOfSymbols dd 0
.SizeOfOptionalHeader dw SIZEOFOPTIONALHEADER
.Characteristics dw IMAGE_FILE_RELOCS_STRIPPED | IMAGE_FILE_EXECUTABLE_IMAGE| IMAGE_FILE_LINE_NUMS_STRIPPED | IMAGE_FILE_LOCAL_SYMS_STRIPPED | IMAGE_FILE_32BIT_MACHINE
OPTIONAL_HEADER:
.Magic dw IMAGE_NT_OPTIONAL_HDR32_MAGIC
.MajorLinkerVersion db 05h
.MinorLinkerVersion db 0ch
.SizeOfCode dd SIZEOFCODE
.SizeOfInitializedData dd SIZEOFINITIALIZEDDATA
.SizeOfUninitializedData dd SIZEOFUNINITIALIZEDDATA
.AddressOfEntryPoint dd EntryPoint - IMAGEBASE
.BaseOfCode dd base_of_code - IMAGEBASE
.BaseOfData dd base_of_data - IMAGEBASE
.ImageBase dd IMAGEBASE
.SectionAlignment dd SECTIONALIGN
.FileAlignment dd FILEALIGN
.MajorOperatingSystemVersion dw 04h
.MinorOperatingSystemVersion dw 0
.MajorImageVersion dw 0
.MinorImageVersion dw 0
.MajorSubsystemVersion dw 4
.MinorSubsystemVersion dw 0
.Win32VersionValue dd 0
.SizeOfImage dd SIZEOFIMAGE
.SizeOfHeaders dd SIZEOFHEADERS
.CheckSum dd 0
.Subsystem dw IMAGE_SUBSYSTEM_WINDOWS_GUI
.DllCharacteristics dw 0
.SizeOfStackReserve dd 100000H
.SizeOfStackCommit dd 1000H
.SizeOfHeapReserve dd 100000H
.SizeOfHeapCommit dd 1000H
.LoaderFlags dd 0
.NumberOfRvaAndSizes dd NUMBEROFRVAANDSIZES
DATA_DIRECTORY:
.DIRECTORY_ENTRY_EXPORT dd 0,0
.DIRECTORY_ENTRY_IMPORT dd IMPORT_DESCRIPTOR - IMAGEBASE, DIRECTORY_ENTRY_IMPORT_SIZE
.DIRECTORY_ENTRY_RESOURCE dd 0,0
.DIRECTORY_ENTRY_EXCEPTION dd 0,0
.DIRECTORY_ENTRY_SECURITY dd 0,0
.DIRECTORY_ENTRY_BASERELOC dd 0,0
.DIRECTORY_ENTRY_DEBUG dd 0,0
.DIRECTORY_ENTRY_COPYRIGHT dd 0,0
.DIRECTORY_ENTRY_GLOBALPTR dd 0,0
.DIRECTORY_ENTRY_TLS dd 0,0
.DIRECTORY_ENTRY_LOAD_CONFIG dd 0,0
.DIRECTORY_ENTRY_BOUND_IMPORT dd 0,0
.DIRECTORY_ENTRY_IAT dd ImportAddressTable - IMAGEBASE, IAT_size
.DIRECTORY_ENTRY_DELAY_IMPORT dd 0,0
.DIRECTORY_ENTRY_COM_DESCRIPTOR dd 0,0
.DIRECTORY_ENTRY_RESERVED dd 0,0
NUMBEROFRVAANDSIZES EQU ($ - DATA_DIRECTORY) / 8
SIZEOFOPTIONALHEADER EQU $ - OPTIONAL_HEADER
; DIRECTORY_ENTRY_DEBUG Size should be small, like 0x1000 or less
; Independantly of NumberOfRvaAndSizes. thus, Dword at DATA_DIRECTORY + 34h
SECTION_HEADER:
SECTION_0:
.Name db '.text'
times 8 - ($ - .Name) db (0)
.VirtualSize dd SECTION0VS; iround(SECTION0SIZE, SECTIONALIGN)
.VirtualAddress dd Section0Start - IMAGEBASE
.SizeOfRawData dd SECTION0SIZE
.PointerToRawData dd SECTION0OFFSET
.PointerToRelocations dd 0
.PointerToLinenumbers dd 0
.NumberOfRelocations dw 0
.NumberOfLinenumbers dw 0
.Characteristics dd IMAGE_SCN_CNT_CODE | IMAGE_SCN_MEM_EXECUTE | IMAGE_SCN_MEM_READ
SECTION_1:
.Name db '.rdata'
times 8 - ($ - .Name) db (0)
.VirtualSize dd SECTION1VS ; iround(SECTION1SIZE, SECTIONALIGN)
.VirtualAddress dd Section1Start - IMAGEBASE
.SizeOfRawData dd SECTION1SIZE
.PointerToRawData dd SECTION1OFFSET
.PointerToRelocations dd 0
.PointerToLinenumbers dd 0
.NumberOfRelocations dw 0
.NumberOfLinenumbers dw 0
.Characteristics dd IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_MEM_READ
SECTION_2:
.Name db '.data'
times 8 - ($ - .Name) db (0)
.VirtualSize dd SECTION2VS ; iround(SECTION2SIZE, SECTIONALIGN)
.VirtualAddress dd Section2Start - IMAGEBASE
.SizeOfRawData dd SECTION2SIZE
.PointerToRawData dd SECTION2OFFSET
.PointerToRelocations dd 0
.PointerToLinenumbers dd 0
.NumberOfRelocations dw 0
.NumberOfLinenumbers dw 0
.Characteristics dd IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_MEM_READ | IMAGE_SCN_MEM_WRITE
NUMBEROFSECTIONS EQU ($ - SECTION_HEADER) / 0x28
ALIGN FILEALIGN, db 0
SIZEOFHEADERS EQU $ - IMAGEBASE
SECTION0OFFSET EQU $ - IMAGEBASE
SECTION code valign = SECTIONALIGN
Section0Start:
bits 32
base_of_code:
EntryPoint:
push MB_ICONINFORMATION ; UINT uType
push tada ; LPCTSTR lpCaption
push helloworld ; LPCTSTR lpText
push 0 ; HWND hWnd
call MessageBoxA
push 0 ; UINT uExitCode
Call ExitProcess
;%IMPORT user32.dll!MessageBoxA
;%IMPORT kernel32.dll!ExitProcess
SECTION0VS equ $ - Section0Start
align FILEALIGN,db 0
SECTION0SIZE EQU $ - Section0Start
SIZEOFCODE equ $ - base_of_code
SECTION1OFFSET equ $ - Section0Start + SECTION0OFFSET
SECTION idata valign = SECTIONALIGN
Section1Start:
base_of_data:
;%IMPORTS
SECTION1VS equ $ - Section1Start
align FILEALIGN,db 0
SECTION1SIZE EQU $ - Section1Start
SECTION2OFFSET equ $ - Section1Start + SECTION1OFFSET
SECTION data valign = SECTIONALIGN
Section2Start:
tada db "Tada!", 0
helloworld db "Hello World!", 0
SECTION2VS equ $ - Section2Start
ALIGN FILEALIGN,db 0
SECTION2SIZE EQU $ - Section2Start
;SIZEOFINITIALIZEDDATA equ $ - base_of_data ; too complex
SIZEOFINITIALIZEDDATA equ SECTION2SIZE + SECTION1SIZE
uninit_data:
SIZEOFUNINITIALIZEDDATA equ $ - uninit_data
SIZEOFIMAGE EQU $ - IMAGEBASE
;Ange Albertini, Creative Commons BY, 2010 | angea/corkami | wip/MakePE/examples/PE/compiled.asm | Assembly | bsd-2-clause | 7,730 |
BITS 64
bndmk bnd1, [r11]
bndmk bnd1, [rax]
bndmk bnd1, [0x399]
bndmk bnd1, [r9+0x3]
bndmk bnd1, [rax+0x3]
bndmk bnd1, [3,1*r12]
bndmk bnd1, [rax+rcx]
bndmk bnd1, [r11+1*rax+0x3]
bndmk bnd1, [rbx+1*r9+0x3]
; bndmov
bndmov bnd1, [r11]
bndmov bnd1, [rax]
bndmov bnd1, [0x399]
bndmov bnd2, [r9+0x3]
bndmov bnd2, [rax+0x3]
bndmov bnd0, [1*r12+0x3]
bndmov bnd2, [rax+rdx]
bndmov bnd1, [r11+1*rax+0x3]
bndmov bnd1, [rbx+1*r9+0x3]
bndmov bnd0, bnd2
bndmov [r11], bnd1
bndmov [rax], bnd1
bndmov [0x399], bnd1
bndmov [r9+0x3], bnd2
bndmov [rax+0x3], bnd2
bndmov [1*r12+0x3], bnd0
bndmov [rax+rdx], bnd2
bndmov [r11+1*rax+0x3], bnd1
bndmov [rbx+1*r9+0x3], bnd1
bndmov bnd2, bnd0
; bndcl
bndcl bnd1, [r11]
bndcl bnd1, [rax]
bndcl bnd1, r11
bndcl bnd1, rcx
bndcl bnd1, [0x399]
bndcl bnd1, [r9+0x3]
bndcl bnd1, [rax+0x3]
bndcl bnd1, [1*r12+0x3]
bndcl bnd1, [rax+rcx]
bndcl bnd1, [r11+1*rax+0x3]
bndcl bnd1, [rbx+1*r9+0x3]
; bndcu
bndcu bnd1, [r11]
bndcu bnd1, [rax]
bndcu bnd1, r11
bndcu bnd1, rcx
bndcu bnd1, [0x399]
bndcu bnd1, [r9+0x3]
bndcu bnd1, [rax+0x3]
bndcu bnd1, [1*r12+0x3]
bndcu bnd1, [rax+rcx]
bndcu bnd1, [r11+1*rax+0x3]
bndcu bnd1, [rbx+1*r9+0x3]
; bndcn
bndcn bnd1, [r11]
bndcn bnd1, [rax]
bndcn bnd1, r11
bndcn bnd1, rcx
bndcn bnd1, [0x399]
bndcn bnd1, [r9+0x3]
bndcn bnd1, [rax+0x3]
bndcn bnd1, [1*r9+0x3]
bndcn bnd1, [rax+rcx]
bndcn bnd1, [r11+1*rax+0x3]
bndcn bnd1, [rbx+1*r9+0x3]
; bndstx
; next 5 lines should be parsed same
bndstx [rax+0x3,rbx], bnd0 ; NASM - split EA
bndstx [rax+rbx*1+0x3], bnd0 ; GAS
bndstx [rax+rbx+3], bnd0 ; GAS
bndstx [rax+0x3], bnd0, rbx ; ICC-1
bndstx [rax+0x3], rbx, bnd0 ; ICC-2
; next 5 lines should be parsed same
bndstx [,rcx*1], bnd2 ; NASM
bndstx [0,rcx*1], bnd2 ; NASM
bndstx [0], bnd2, rcx ; ICC-1
bndstx [0], rcx, bnd2 ; ICC-2
bndstx [rcx*1], bnd2 ; GAS - rcx is encoded as index only when it is mib
; next 3 lines should be parsed same
bndstx [3,1*r12], bnd2 ; NASM
bndstx [1*r12+3], bnd2 ; GAS
bndstx [3], r12, bnd2 ; ICC
bndstx [r12+0x399], bnd3
bndstx [r11+0x1234], bnd1
bndstx [rbx+0x1234], bnd2
bndstx [rdx], bnd1
; bndldx
bndldx bnd0, [rax+rbx*1+0x3]
bndldx bnd2, [rbx+rdx+3]
bndldx bnd3, [r12+0x399]
bndldx bnd1, [r11+0x1234]
bndldx bnd2, [rbx+0x1234]
bndldx bnd2, [1*rbx+3]
bndldx bnd2, [1*r12+3]
bndldx bnd1, [rdx]
; bnd
bnd ret
bnd call foo
bnd jmp foo ; when it becomes a Jb form - short jmp (eb),
; bnd prefix is silently dropped
bnd jmp near 0 ; near jmp (opcode e9)
; bnd jmp short 0 ; explicit short jmp (opcode eb) : error
bnd jno foo
foo: bnd ret
| techkey/nasm | travis/test/mpx-64.asm | Assembly | bsd-2-clause | 2,667 |
/*
* This file is a part of the open source stm32plus library.
* Copyright (c) 2011,2012 Andy Brown <www.andybrown.me.uk>
* Please see website for licensing terms.
*/
.global BulbPixels
.global BulbPixelsSize
.global AudioPixels
.global AudioPixelsSize
.global FlagPixels
.global FlagPixelsSize
.global DocPixels
.global DocPixelsSize
.global GlobePixels
.global GlobePixelsSize
BulbPixels:
.incbin "lzg/r61523/bulb.r61523.16.lzg"
BulbPixelsSize=.-BulbPixels
AudioPixels:
.incbin "lzg/r61523/audio.r61523.16.lzg"
AudioPixelsSize=.-AudioPixels
FlagPixels:
.incbin "lzg/r61523/flag.r61523.16.lzg"
FlagPixelsSize=.-FlagPixels
DocPixels:
.incbin "lzg/r61523/doc.r61523.16.lzg"
DocPixelsSize=.-DocPixels
GlobePixels:
.incbin "lzg/r61523/globe.r61523.16.lzg"
GlobePixelsSize=.-GlobePixels
| tokoro10g/stm32plus | examples/r61523/CompressedPixels.asm | Assembly | bsd-3-clause | 818 |
\\ MODE 7 Video routines
\\ 6502 include file
\\ Relies on defines in mode7_plot_pixel.h.asm
mode7_gif_anim_base_addr_HI = draw_buffer_addr
\ ******************************************************************
\ * "Animated GIF" playback based on mode7-video codec
\ *
\ * Called this animated GIF as doesn't do all the fancy streaming
\ * of tracks from disc or decompression in irq/event callback.
\ *
\ * Instead just takes uncompressed (for now) mode7-video codec data
\ * and decode the next frame to anywhere on the screen on update,
\ * with support for looping.
\ *
\ * Crappy toolchain exists to generate data from animated GIFs
\ * which are usually shorter than videos + loop.
\ ******************************************************************
\\ These can be simplified - don't need to be ZP
.mode7_gif_anim_num_deltas SKIP 2
.mode7_gif_anim_packed_delta SKIP 2
.mode7_gif_anim_shifted_bit SKIP 1
| bitshifters/teletextr | lib/mode7_gif_anim.h.asm | Assembly | mit | 931 |
// projects/08/ProgramFlow/FibonacciSeries/FibonacciSeries.vm
@1
D=A
@ARG
AD=D+M
D=M
@SP
A=M
M=D
@SP
AM=M+1
@1
D=A
@R3
AD=D+A
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
@0
D=A
@SP
A=M
M=D
@SP
AM=M+1
@0
D=A
@THAT
AD=D+M
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
@1
D=A
@SP
A=M
M=D
@SP
AM=M+1
@1
D=A
@THAT
AD=D+M
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
@0
D=A
@ARG
AD=D+M
D=M
@SP
A=M
M=D
@SP
AM=M+1
@2
D=A
@SP
A=M
M=D
@SP
AM=M+1
@SP
AM=M-1
D=M
@SP
AM=M-1
M=M-D
@SP
AM=M+1
@0
D=A
@ARG
AD=D+M
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
(MAIN_LOOP_START)
@0
D=A
@ARG
AD=D+M
D=M
@SP
A=M
M=D
@SP
AM=M+1
@SP
AM=M-1
D=M
@COMPUTE_ELEMENT
D;JNE
@END_PROGRAM
0;JMP
(COMPUTE_ELEMENT)
@0
D=A
@THAT
AD=D+M
D=M
@SP
A=M
M=D
@SP
AM=M+1
@1
D=A
@THAT
AD=D+M
D=M
@SP
A=M
M=D
@SP
AM=M+1
@SP
AM=M-1
D=M
@SP
AM=M-1
M=D+M
@SP
AM=M+1
@2
D=A
@THAT
AD=D+M
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
@1
D=A
@R3
AD=D+A
D=M
@SP
A=M
M=D
@SP
AM=M+1
@1
D=A
@SP
A=M
M=D
@SP
AM=M+1
@SP
AM=M-1
D=M
@SP
AM=M-1
M=D+M
@SP
AM=M+1
@1
D=A
@R3
AD=D+A
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
@0
D=A
@ARG
AD=D+M
D=M
@SP
A=M
M=D
@SP
AM=M+1
@1
D=A
@SP
A=M
M=D
@SP
AM=M+1
@SP
AM=M-1
D=M
@SP
AM=M-1
M=M-D
@SP
AM=M+1
@0
D=A
@ARG
AD=D+M
@R13
M=D
@SP
AM=M-1
D=M
@R13
A=M
M=D
@MAIN_LOOP_START
0;JMP
(END_PROGRAM)
(END)
@END
0;JMP
| skatsuta/nand2tetris | projects/08/ProgramFlow/FibonacciSeries/FibonacciSeries.asm | Assembly | mit | 1,247 |
.686
.model flat,stdcall
option casemap:none
include .\bnlib.inc
include .\bignum.inc
.code
_bn_adddw_ignoresign proc c; uses edi,esi,eax,ecx,edx
lea edx,[edi].BN.dwArray[0*4]
mov ecx,[edi].BN.dwSize
clc
.repeat
adc [edx],eax
mov eax,0
lea edx,[edx+4]
jnc @F
dec ecx
.until zero?
adc eax,eax
jz @F
call _bn_add_carry_dword
@@: ret
_bn_adddw_ignoresign endp
end
| FloydZ/Crypto-Hash | BigNum/Mod/Base/_bn_adddw_ignoresign.asm | Assembly | mit | 382 |
section .data
rows:
dw 25 * 0
dw 25 * 1
dw 25 * 2
dw 25 * 3
dw 25 * 4
dw 25 * 5
dw 25 * 6
dw 25 * 7
dw 25 * 8
dw 25 * 9
dw 25 * 10
dw 25 * 11
dw 25 * 12
dw 25 * 13
dw 25 * 14
dw 25 * 15
dw 25 * 16
dw 25 * 17
dw 25 * 18
dw 25 * 19
dw 25 * 20
dw 25 * 21
dw 25 * 22
dw 25 * 23
dw 25 * 24 | musicman89/DND-1-in-8086-Assembly | SourceFiles/Data/Constants/LookupTables.asm | Assembly | mit | 284 |
; Hello World for OSZ/DOS
; WTFPL/PUBLIC DOMAIN
[bits 16]
[org 0x0100]
xor bp, bp
mov ah, 9
mov dx, hello_msg
int 0x21
ret
hello_msg db "Hello, world!", 13, 10, "$"
| neri/osz | src/app/hello.asm | Assembly | bsd-2-clause | 171 |
;pracuje jako 5-ti bitovy binarni citac
;vystupy 3 a 4 jsou prohozene kvuli desce
.device attiny13
.def cnt=r18
.def cm0=r19
.def cm1=r20
.def cm2=r21
.def chc=r22
.def dirs=r23
.org 0x0000 ;RESET
RJMP RESET ;skok na start po resetu
.org 0x0006 ;TC0 overflow
RJMP CASOVAC
.org 0x0007
rjmp casovac
.org 0x0010
RESET:
ldi r16,low(RAMEND) ;nastavi stack pointer
out SPL,r16
cli ;zakazat vsechna preruseni
ldi r16,0b00011111 ;výstupní = 1
out DDRB,r16
ldi r16,0 ;vypnout PullUp
out PORTB,r16
ldi r16,0b00000011 ;TC0 prescaler na 64
out TCCR0B,r16 ;4800000/32
ldi r16,0b00000010 ;TC0 je v rezimu CTC
out TCCR0A,r16
ldi r16,20 ;overflow 22
out OCR0A,r16 ;
in r16, TIMSK0 ;interrupt enable
ORI r16, 0b00000100
out timsk0,r16
ldi cm0,32 ;R
ldi cm1,16 ;G
ldi cm2,0 ;B
clr cnt
clr chc
ldi dirs,0b00000000
sei ;zapnout globalne interrupt
LOOP:
rjmp LOOP ;skok na loop
CASOVAC:
inc cnt
cpi cnt,32
brne nov
clr cnt
cbi portb,0
cbi portb,1
cbi portb,2
inc chc
cpi chc,255
brne nov
nov:
cp cnt,cm0
brne not0
sbi portb,0
not0: cp cnt,cm1
brne not1
sbi portb,1
not1: cp cnt,cm2
brne not2
sbi portb,2
not2:
CASEND:
reti
| MightyPork/avr-projects | archive/000000_asm_old/utility/3-kanalova simulovana PWM/rgbdriv.asm | Assembly | mit | 1,313 |
%include "module.inc"
jmp $
| olsner/os | user/loop.asm | Assembly | mit | 30 |
format MS COFF
section '.text' code readable executable
public _memcpy
_memcpy:
push esi edi
mov edi, [esp+12]
mov esi, [esp+16]
mov ecx, [esp+20]
rep movsb
pop edi esi
ret
| devlato/kolibrios-llvm | programs/other/graph/memcpy.asm | Assembly | mit | 180 |
dc.w word_3C32A-Map_FBZPiston
word_3C32A: dc.w 4 ; DATA XREF: ROM:0003C328o
dc.b $E0, $F, 0, 0, $FF, $E0
dc.b $E0, $F, 8, 0, 0, 0
dc.b 0, $F, $10, 0, $FF, $E0
dc.b 0, $F, $18, 0, 0, 0
| TeamASM-Blur/Sonic-3-Blue-Balls-Edition | Working Disassembly/Levels/FBZ/Misc Object Data/Map - Piston.asm | Assembly | apache-2.0 | 221 |
; Listing generated by Microsoft (R) Optimizing Compiler Version 19.00.23506.0
TITLE D:\Projects\TaintAnalysis\AntiTaint\Epilog\src\func-alloca.c
.686P
.XMM
include listing.inc
.model flat
INCLUDELIB MSVCRT
INCLUDELIB OLDNAMES
_DATA SEGMENT
$SG5567 DB '%d', 00H
_DATA ENDS
PUBLIC ___local_stdio_printf_options
PUBLIC ___local_stdio_scanf_options
PUBLIC __vfprintf_l
PUBLIC _printf
PUBLIC __vfscanf_l
PUBLIC _scanf
PUBLIC _func
PUBLIC _main
EXTRN __imp____acrt_iob_func:PROC
EXTRN __imp____stdio_common_vfprintf:PROC
EXTRN __imp____stdio_common_vfscanf:PROC
EXTRN _gets:PROC
EXTRN __alloca_probe_16:PROC
_DATA SEGMENT
COMM ?_OptionsStorage@?1??__local_stdio_printf_options@@9@9:QWORD ; `__local_stdio_printf_options'::`2'::_OptionsStorage
COMM ?_OptionsStorage@?1??__local_stdio_scanf_options@@9@9:QWORD ; `__local_stdio_scanf_options'::`2'::_OptionsStorage
_DATA ENDS
; Function compile flags: /Odtpy
; File d:\projects\taintanalysis\antitaint\epilog\src\func-alloca.c
_TEXT SEGMENT
_main PROC
; 20 : {
push ebp
mov ebp, esp
; 21 : func();
call _func
; 22 : return 0;
xor eax, eax
; 23 : }
pop ebp
ret 0
_main ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File d:\projects\taintanalysis\antitaint\epilog\src\func-alloca.c
_TEXT SEGMENT
tv68 = -12 ; size = 4
_sz$ = -8 ; size = 4
_buf$ = -4 ; size = 4
_func PROC
; 10 : {
push ebp
mov ebp, esp
sub esp, 12 ; 0000000cH
; 11 : int sz;
; 12 : char *buf;
; 13 : scanf("%d", &sz);
lea eax, DWORD PTR _sz$[ebp]
push eax
push OFFSET $SG5567
call _scanf
add esp, 8
; 14 : buf = (char*)alloca(sz);
mov eax, DWORD PTR _sz$[ebp]
call __alloca_probe_16
mov DWORD PTR tv68[ebp], esp
mov ecx, DWORD PTR tv68[ebp]
mov DWORD PTR _buf$[ebp], ecx
; 15 : gets(buf);
mov edx, DWORD PTR _buf$[ebp]
push edx
call _gets
add esp, 4
; 16 : printf(buf);
mov eax, DWORD PTR _buf$[ebp]
push eax
call _printf
add esp, 4
; 17 : }
lea esp, DWORD PTR [ebp-12]
mov esp, ebp
pop ebp
ret 0
_func ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT _scanf
_TEXT SEGMENT
__Result$ = -8 ; size = 4
__ArgList$ = -4 ; size = 4
__Format$ = 8 ; size = 4
_scanf PROC ; COMDAT
; 1276 : {
push ebp
mov ebp, esp
sub esp, 8
; 1277 : int _Result;
; 1278 : va_list _ArgList;
; 1279 : __crt_va_start(_ArgList, _Format);
lea eax, DWORD PTR __Format$[ebp+4]
mov DWORD PTR __ArgList$[ebp], eax
; 1280 : _Result = _vfscanf_l(stdin, _Format, NULL, _ArgList);
mov ecx, DWORD PTR __ArgList$[ebp]
push ecx
push 0
mov edx, DWORD PTR __Format$[ebp]
push edx
push 0
call DWORD PTR __imp____acrt_iob_func
add esp, 4
push eax
call __vfscanf_l
add esp, 16 ; 00000010H
mov DWORD PTR __Result$[ebp], eax
; 1281 : __crt_va_end(_ArgList);
mov DWORD PTR __ArgList$[ebp], 0
; 1282 : return _Result;
mov eax, DWORD PTR __Result$[ebp]
; 1283 : }
mov esp, ebp
pop ebp
ret 0
_scanf ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT __vfscanf_l
_TEXT SEGMENT
__Stream$ = 8 ; size = 4
__Format$ = 12 ; size = 4
__Locale$ = 16 ; size = 4
__ArgList$ = 20 ; size = 4
__vfscanf_l PROC ; COMDAT
; 1058 : {
push ebp
mov ebp, esp
; 1059 : return __stdio_common_vfscanf(
mov eax, DWORD PTR __ArgList$[ebp]
push eax
mov ecx, DWORD PTR __Locale$[ebp]
push ecx
mov edx, DWORD PTR __Format$[ebp]
push edx
mov eax, DWORD PTR __Stream$[ebp]
push eax
call ___local_stdio_scanf_options
mov ecx, DWORD PTR [eax+4]
push ecx
mov edx, DWORD PTR [eax]
push edx
call DWORD PTR __imp____stdio_common_vfscanf
add esp, 24 ; 00000018H
; 1060 : _CRT_INTERNAL_LOCAL_SCANF_OPTIONS,
; 1061 : _Stream, _Format, _Locale, _ArgList);
; 1062 : }
pop ebp
ret 0
__vfscanf_l ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT _printf
_TEXT SEGMENT
__Result$ = -8 ; size = 4
__ArgList$ = -4 ; size = 4
__Format$ = 8 ; size = 4
_printf PROC ; COMDAT
; 950 : {
push ebp
mov ebp, esp
sub esp, 8
; 951 : int _Result;
; 952 : va_list _ArgList;
; 953 : __crt_va_start(_ArgList, _Format);
lea eax, DWORD PTR __Format$[ebp+4]
mov DWORD PTR __ArgList$[ebp], eax
; 954 : _Result = _vfprintf_l(stdout, _Format, NULL, _ArgList);
mov ecx, DWORD PTR __ArgList$[ebp]
push ecx
push 0
mov edx, DWORD PTR __Format$[ebp]
push edx
push 1
call DWORD PTR __imp____acrt_iob_func
add esp, 4
push eax
call __vfprintf_l
add esp, 16 ; 00000010H
mov DWORD PTR __Result$[ebp], eax
; 955 : __crt_va_end(_ArgList);
mov DWORD PTR __ArgList$[ebp], 0
; 956 : return _Result;
mov eax, DWORD PTR __Result$[ebp]
; 957 : }
mov esp, ebp
pop ebp
ret 0
_printf ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\stdio.h
; COMDAT __vfprintf_l
_TEXT SEGMENT
__Stream$ = 8 ; size = 4
__Format$ = 12 ; size = 4
__Locale$ = 16 ; size = 4
__ArgList$ = 20 ; size = 4
__vfprintf_l PROC ; COMDAT
; 638 : {
push ebp
mov ebp, esp
; 639 : return __stdio_common_vfprintf(_CRT_INTERNAL_LOCAL_PRINTF_OPTIONS, _Stream, _Format, _Locale, _ArgList);
mov eax, DWORD PTR __ArgList$[ebp]
push eax
mov ecx, DWORD PTR __Locale$[ebp]
push ecx
mov edx, DWORD PTR __Format$[ebp]
push edx
mov eax, DWORD PTR __Stream$[ebp]
push eax
call ___local_stdio_printf_options
mov ecx, DWORD PTR [eax+4]
push ecx
mov edx, DWORD PTR [eax]
push edx
call DWORD PTR __imp____stdio_common_vfprintf
add esp, 24 ; 00000018H
; 640 : }
pop ebp
ret 0
__vfprintf_l ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\corecrt_stdio_config.h
; COMDAT ___local_stdio_scanf_options
_TEXT SEGMENT
___local_stdio_scanf_options PROC ; COMDAT
; 82 : {
push ebp
mov ebp, esp
; 83 : static unsigned __int64 _OptionsStorage;
; 84 : return &_OptionsStorage;
mov eax, OFFSET ?_OptionsStorage@?1??__local_stdio_scanf_options@@9@9 ; `__local_stdio_scanf_options'::`2'::_OptionsStorage
; 85 : }
pop ebp
ret 0
___local_stdio_scanf_options ENDP
_TEXT ENDS
; Function compile flags: /Odtpy
; File c:\program files (x86)\windows kits\10\include\10.0.10240.0\ucrt\corecrt_stdio_config.h
; COMDAT ___local_stdio_printf_options
_TEXT SEGMENT
___local_stdio_printf_options PROC ; COMDAT
; 73 : {
push ebp
mov ebp, esp
; 74 : static unsigned __int64 _OptionsStorage;
; 75 : return &_OptionsStorage;
mov eax, OFFSET ?_OptionsStorage@?1??__local_stdio_printf_options@@9@9 ; `__local_stdio_printf_options'::`2'::_OptionsStorage
; 76 : }
pop ebp
ret 0
___local_stdio_printf_options ENDP
_TEXT ENDS
END
| Dovgalyuk/AntiTaint | Epilog/asm/MSVC2015/func-alloca-omitfp.asm | Assembly | apache-2.0 | 7,355 |
;**********************************
;** ZX SPECTRUM SYSTEM VARIABLES **
;**********************************
KSTATE_0 equ $5C00 ; 23552 ; (IY+$C6) ; Used in reading the keyboard.
KSTATE_4 equ $5C04 ; 23556 ; (IY+$CA)
LASTK equ $5C08 ; 23560 ; (IY+$CE) ; Stores newly pressed key.
REPDEL equ $5C09 ; 23561 ; (IY+$CF) ; Time (in 50ths of a second in 60ths of a second in N. America) that a key must be held down before it repeats. This starts off at 35, but you can POKE in other values.
REPPER equ $5C0A ; 23562 ; (IY+$D0) ; Delay (in 50ths of a second in 60ths of a second in N. America) between successive repeats of a key held down: initially 5.
DEFADD equ $5C0B ; 23563 ; (IY+$D1) ; Address of arguments of user defined function if one is being evaluated; otherwise 0.
KDATA equ $5C0D ; 23565 ; (IY+$D3) ; Stores 2nd byte of colour controls entered from keyboard .
TVDATA_LO equ $5C0E ; 23566 ; (IY+$D4) ; Stores bytes of colour, AT and TAB controls going to television.
TVDATA_HI equ $5C0F ; 23567 ; (IY+$D5)
STRMS_FD equ $5C10 ; 23568 ; (IY+$D6) ; Addresses of channels attached to streams.
STRMS_00 equ $5C16 ; 23574 ; (IY+$DC)
CHARS equ $5C36 ; 23606 ; (IY+$FC) ; 256 less than address of character set (which starts with space and carries on to the copyright symbol). Normally in ROM, but you can set up your own in RAM and make CHARS point to it.
RASP_PIP equ $5C38 ; 23608 ; (IY+$FE) ; Length of warning buzz.
ERR_NR equ $5C3A ; 23610 ; (IY+$00) ; 1 less than the report code. Starts off at 255 (for 1) so PEEK 23610 gives 255.
FLAGS equ $5C3B ; 23611 ; (IY+$01) ; Various flags to control the BASIC system. See *
TV_FLAG equ $5C3C ; 23612 ; (IY+$02) ; Flags associated with the television. See **
ERR_SP equ $5C3D ; 23613 ; (IY+$03) ; Address of item on machine stack to be used as error return.
LIST_SP equ $5C3F ; 23615 ; (IY+$05) ; Address of return address from automatic listing.
MODE equ $5C41 ; 23617 ; (IY+$07) ; Specifies K, L, C. E or G cursor.
NEWPPC equ $5C42 ; 23618 ; (IY+$08) ; Line to be jumped to.
NSPPC equ $5C44 ; 23620 ; (IY+$0A) ; Statement number in line to be jumped to. Poking first NEWPPC and then NSPPC forces a jump to a specified statement in a line.
PPC equ $5C45 ; 23621 ; (IY+$0B) ; Line number of statement currently being executed.
SUBPPC equ $5C47 ; 23623 ; (IY+$0D) ; Number within line of statement being executed.
BORDCR equ $5C48 ; 23624 ; (IY+$0E) ; Border colour * 8; also contains the attributes normally used for the lower half of the screen.
E_PPC equ $5C49 ; 23625 ; (IY+$0F) ; Number of current line (with program cursor).
E_PPC_HI equ $5C4A ; 23626 ; (IY+$10)
VARS equ $5C4B ; 23627 ; (IY+$11) ; Address of variables.
DEST equ $5C4D ; 23629 ; (IY+$13) ; Address of variable in assignment.
CHANS equ $5C4F ; 23631 ; (IY+$15) ; Address of channel data.
CURCHL equ $5C51 ; 23633 ; (IY+$17) ; Address of information currently being used for input and output.
PROG equ $5C53 ; 23635 ; (IY+$19) ; Address of BASIC program.
NXTLIN equ $5C55 ; 23637 ; (IY+$1B) ; Address of next line in program.
DATADD equ $5C57 ; 23639 ; (IY+$1D) ; Address of terminator of last DATA item.
E_LINE equ $5C59 ; 23641 ; (IY+$1F) ; Address of command being typed in.
K_CUR equ $5C5B ; 23643 ; (IY+$21) ; Address of cursor.
CH_ADD equ $5C5D ; 23645 ; (IY+$23) ; Address of the next character to be interpreted: the character after the argument of PEEK, or the NEWLINE at the end of a POKE statement.
X_PTR equ $5C5F ; 23647 ; (IY+$25) ; Address of the character after the ? marker.
WORKSP equ $5C61 ; 23649 ; (IY+$27) ; Address of temporary work space.
STKBOT equ $5C63 ; 23651 ; (IY+$29) ; Address of bottom of calculator stack.
STKEND equ $5C65 ; 23653 ; (IY+$2B) ; Address of start of spare space.
STKEND_HI equ $5C66 ; 23654 ; (IY+$2C)
BREG equ $5C67 ; 23655 ; (IY+$2D) ; Calculator's b register.
MEM equ $5C68 ; 23656 ; (IY+$2E) ; Address of area used for calculator's memory. (Usually MEMBOT, but not always.)
FLAGS2 equ $5C6A ; 23658 ; (IY+$30) ; More flags. See ***
DF_SZ equ $5C6B ; 23659 ; (IY+$31) ; The number of lines (including one blank line) in the lower part of the screen.
S_TOP equ $5C6C ; 23660 ; (IY+$32) ; The number of the top program line in automatic listings.
OLDPPC equ $5C6E ; 23662 ; (IY+$34) ; Line number to which CONTINUE jumps.
OSPPC equ $5C70 ; 23664 ; (IY+$36) ; Number within line of statement to which CONTINUE jumps.
FLAGX equ $5C71 ; 23665 ; (IY+$37) ; Various flags. See ****
STRLEN equ $5C72 ; 23666 ; (IY+$38) ; Length of string type destination in assignment.
T_ADDR equ $5C74 ; 23668 ; (IY+$3A) ; Address of next item in syntax table (very unlikely to be useful).
SEED equ $5C76 ; 23670 ; (IY+$3C) ; The seed for RND. This is the variable that is set by RANDOMIZE.
FRAMES1 equ $5C78 ; 23672 ; (IY+$3E) ; 3 byte (least significant first), frame counter. Incremented every 20ms.
UDG equ $5C7B ; 23675 ; (IY+$41) ; Address of 1st user defined graphic You can change this for instance to save space by having fewer user defined graphics.
COORDS equ $5C7D ; 23677 ; (IY+$43) ; x-coordinate of last point plotted.
COORDS_Y equ $5C7E ; 23678 ; (IY+$44) ; y-coordinate of last point plotted.
PR_CC equ $5C80 ; 23680 ; (IY+$46) ; Full address of next position for LPRINT to print at (in ZX printer buffer). Legal values $5B00 - $5B1F. [Not used in 128K mode or when certain peripherals are attached]
ECHO_E equ $5C82 ; 23682 ; (IY+$48) ; 33 column number and 24 line number (in lower half) of end of input buffer.
DF_CC equ $5C84 ; 23684 ; (IY+$4A) ; Address in display file of PRINT position.
DFCCL equ $5C86 ; 23686 ; (IY+$4C) ; Like DF_CC for lower part of screen.
S_POSN equ $5C88 ; 23688 ; (IY+$4E) ; 33 column number for PRINT position
S_POSN_HI equ $5C89 ; 23689 ; (IY+$4F) ; 24 line number for PRINT position.
SPOSNL equ $5C8A ; 23690 ; (IY+$50) ; Like S_POSN for lower part
SPOSNL_HI equ $5C8B ; 23691 ; (IY+$51)
SCR_CT equ $5C8C ; 23692 ; (IY+$52) ; Counts scrolls: it is always 1 more than the number of scrolls that will be done before stopping with scroll? If you keep poking this with a number bigger than 1 (say 255), the screen will scroll on and on without asking you.
ATTRP_MASKP equ $5C8D ; 23693 ; (IY+$53) ; Permanent current colours, etc (as set up by colour statements).
ATTRT_MASKT equ $5C8F ; 23695 ; (IY+$55) ; Temporary current colours, etc (as set up by colour items).
MASK_T equ $5C90 ; 23696 ; (IY+$56) ; Like MASK_P, but temporary.
P_FLAG equ $5C91 ; 23697 ; (IY+$57) ; More flags.
MEM_0 equ $5C92 ; 23698 ; (IY+$58) ; Calculator's memory area; used to store numbers that cannot conveniently be put on the calculator stack.
MEM_3 equ $5CA1 ; 23713 ; (IY+$67)
MEM_4 equ $5CA6 ; 23718 ; (IY+$6C)
MEM_4_4 equ $5CAA ; 23722 ; (IY+$70)
MEM_5_0 equ $5CAB ; 23723 ; (IY+$71)
MEM_5_1 equ $5CAC ; 23724 ; (IY+$72)
NMIADD equ $5CB0 ; 23728 ; (IY+$76) ; This is the address of a user supplied NMI address which is read by the standard ROM when a peripheral activates the NMI. Probably intentionally disabled so that the effect is to perform a reset if both locations hold zero, but do nothing if the locations hold a non-zero value. Interface 1's with serial number greater than 87315 will initialize these locations to 0 and 80 to allow the RS232 "T" channel to use a variable line width. 23728 is the current print position and 23729 the width - default 80.
RAMTOP equ $5CB2 ; 23730 ; (IY+$78) ; Address of last byte of BASIC system area.
P_RAMT equ $5CB4 ; 23732 ; (IY+$7A) ; Address of last byte of physical RAM.
; *
; FLAGS equ $5C3B ; 23611 ; (IY+$01) ; BASIC flags, particular bits meaning:
; ; 0 ... 1 = supress leading space for tokens
; ; 1 ... 1 = listing to ZX Printer
; ; 2 ... 1 = listing in mode 'L', 0 = listing in mode 'K'
; ; 3 ... 1 = keyboard mode 'L', 0 = keyboard mode 'K'
; ; 4 ... 48k: unused, 128k: 0 = basic48, 1 = basic128
; ; 5 ... 1= new key was pressed on
; ; 6 ... 1= numeric result of the operation, 0=string result of the operation (SCANN is set)
; ; 7 ... 1= syntax checking off, 0=syntax checking on
;
; **
; TV_FLAG equ $5C3C ; 23612 ; (IY+$02) ; PRINT routine flags, particular bits meaning:
; ; 0 ... 1=lower part of screen
; ; 3 ... 1=mode change in EDIT
; ; 4 ... 1=Autolist
; ; 5 ... 1=screen is clear
;
; ***
; FLAGS2 equ $5C6A ; 23658 ; (IY+$30) ; BASIC flags, particular bits meaning:
; ; 0 ... 1=screen is clear
; ; 1 ... 1=ZX Printeru buffer is not empty
; ; 2 ... 1=quotation mode during string processing
; ; 3 ... 1=caps lock
; ; 4 ... 1=channel 'K'
; ; 5 ... 1=new key was pressed on
; ; 6 ... unused
; ; 7 ... unused
;
; ****
; FLAGX equ $5C71 ; 23665 ; (IY+$37) ; BASIC flags, particular bits meaning:
; ; 0 ... 1=remove string from variable before new string assign
; ; 1 ... 1=create variable at LET, 0=variable already exists
; ; 5 ... 1=INPUT mode, 0=EDIT BASIC line
; ; 6 ... 1=numeric variable in INPUT, 0=string variable in INPUT mode
; ; 7 ... 1=input line
| z00m128/sjasmplus | tests/integration/zx-spectrum-rom/zx-spectrum-rom-sysvars.i.asm | Assembly | bsd-3-clause | 9,171 |
; flat assembler interface for DOS
; Copyright (c) 1999-2015, Tomasz Grysztar.
; All rights reserved.
format MZ
heap 0
stack 8000h
entry main:start
include 'modes.inc'
segment main use16
start:
mov ax,ds
mov dx,[2Ch]
push cs cs
pop ds es
mov [psp_segment],ax
mov [environment_segment],dx
mov dx,_logo
mov ah,9
int 21h
cld
call go32
use32
call get_params
jc information
call init_memory
mov esi,_memory_prefix
call display_string
mov eax,[memory_end]
sub eax,[memory_start]
add eax,[additional_memory_end]
sub eax,[additional_memory]
shr eax,10
call display_number
mov esi,_memory_suffix
call display_string
xor ah,ah
int 1Ah
mov ax,cx
shl eax,16
mov ax,dx
mov [start_time],eax
cmp [mode],dpmi
je compile
jmp main+(first_segment shr 4):first_gate-first_segment
compile:
call preprocessor
call parser
call assembler
call formatter
finish:
call display_user_messages
movzx eax,[current_pass]
inc eax
call display_number
mov esi,_passes_suffix
call display_string
xor ah,ah
int 1Ah
mov ax,cx
shl eax,16
mov ax,dx
sub eax,[start_time]
mov ebx,100
mul ebx
mov ebx,182
div ebx
or eax,eax
jz display_bytes_count
xor edx,edx
mov ebx,10
div ebx
push edx
call display_number
mov ah,2
mov dl,'.'
int 21h
pop eax
call display_number
mov esi,_seconds_suffix
call display_string
display_bytes_count:
mov eax,[written_size]
call display_number
mov esi,_bytes_suffix
call display_string
xor al,al
jmp exit_program
information:
mov esi,_usage
call display_string
mov al,1
jmp exit_program
get_params:
mov [input_file],0
mov [output_file],0
mov [symbols_file],0
mov [memory_setting],0
mov [passes_limit],100
mov [definitions_pointer],predefinitions
push ds
mov ds,[psp_segment]
mov esi,81h
mov edi,params
find_param:
lodsb
cmp al,20h
je find_param
cmp al,'-'
je option_param
cmp al,0Dh
je all_params
or al,al
jz all_params
cmp [es:input_file],0
jne get_output_file
mov [es:input_file],edi
jmp process_param
get_output_file:
cmp [es:output_file],0
jne bad_params
mov [es:output_file],edi
process_param:
cmp al,22h
je string_param
copy_param:
stosb
lodsb
cmp al,20h
je param_end
cmp al,0Dh
je param_end
or al,al
jz param_end
jmp copy_param
string_param:
lodsb
cmp al,22h
je string_param_end
cmp al,0Dh
je param_end
or al,al
jz param_end
stosb
jmp string_param
option_param:
lodsb
cmp al,'m'
je memory_option
cmp al,'M'
je memory_option
cmp al,'p'
je passes_option
cmp al,'P'
je passes_option
cmp al,'d'
je definition_option
cmp al,'D'
je definition_option
cmp al,'s'
je symbols_option
cmp al,'S'
je symbols_option
invalid_option:
pop ds
stc
ret
get_option_value:
xor eax,eax
mov edx,eax
get_option_digit:
lodsb
cmp al,20h
je option_value_ok
cmp al,0Dh
je option_value_ok
or al,al
jz option_value_ok
sub al,30h
jc bad_params_value
cmp al,9
ja bad_params_value
imul edx,10
jo bad_params_value
add edx,eax
jc bad_params_value
jmp get_option_digit
option_value_ok:
dec esi
clc
ret
bad_params_value:
stc
ret
memory_option:
lodsb
cmp al,20h
je memory_option
cmp al,0Dh
je invalid_option
or al,al
jz invalid_option
dec esi
call get_option_value
jc invalid_option
or edx,edx
jz invalid_option
cmp edx,1 shl (32-10)
jae invalid_option
mov [es:memory_setting],edx
jmp find_param
passes_option:
lodsb
cmp al,20h
je passes_option
cmp al,0Dh
je invalid_option
or al,al
jz invalid_option
dec esi
call get_option_value
jc bad_params
or edx,edx
jz invalid_option
cmp edx,10000h
ja invalid_option
mov [es:passes_limit],dx
jmp find_param
definition_option:
lodsb
cmp al,20h
je definition_option
cmp al,0Dh
je bad_params
or al,al
jz bad_params
dec esi
push edi
mov edi,[es:definitions_pointer]
call convert_definition_option
mov [es:definitions_pointer],edi
pop edi
jc invalid_option
jmp find_param
symbols_option:
mov [es:symbols_file],edi
find_symbols_file_name:
lodsb
cmp al,20h
jne process_param
jmp find_symbols_file_name
param_end:
dec esi
string_param_end:
xor al,al
stosb
jmp find_param
all_params:
xor al,al
stosb
pop ds
cmp [input_file],0
je no_input_file
mov eax,[definitions_pointer]
mov byte [eax],0
mov [initial_definitions],predefinitions
clc
ret
bad_params:
pop ds
no_input_file:
stc
ret
convert_definition_option:
mov ecx,edi
xor al,al
stosb
copy_definition_name:
lodsb
cmp al,'='
je copy_definition_value
cmp al,20h
je bad_definition_option
cmp al,0Dh
je bad_definition_option
or al,al
jz bad_definition_option
stosb
inc byte [es:ecx]
jnz copy_definition_name
bad_definition_option:
stc
ret
copy_definition_value:
lodsb
cmp al,20h
je definition_value_end
cmp al,0Dh
je definition_value_end
or al,al
jz definition_value_end
cmp al,'\'
jne definition_value_character
cmp byte [esi],20h
jne definition_value_character
lodsb
definition_value_character:
stosb
jmp copy_definition_value
definition_value_end:
dec esi
xor al,al
stosb
clc
ret
include '..\version.inc'
_logo db 'flat assembler version ',VERSION_STRING,24h
_copyright db 'Copyright (c) 1999-2015, Tomasz Grysztar',0Dh,0Ah,0
_usage db 0Dh,0Ah
db 'usage: fasm <source> [output]',0Dh,0Ah
db 'optional settings:',0Dh,0Ah
db ' -m <limit> set the limit in kilobytes for the available memory',0Dh,0Ah
db ' -p <limit> set the maximum allowed number of passes',0Dh,0Ah
db ' -d <name>=<value> define symbolic variable',0Dh,0Ah
db ' -s <file> dump symbolic information for debugging',0Dh,0Ah
db 0
_memory_prefix db ' (',0
_memory_suffix db ' kilobytes memory)',0Dh,0Ah,0
_passes_suffix db ' passes, ',0
_seconds_suffix db ' seconds, ',0
_bytes_suffix db ' bytes.',0Dh,0Ah,0
error_prefix db 'error: ',0
error_suffix db '.'
cr_lf db 0Dh,0Ah,0
line_number_start db ' [',0
line_data_start db ':',0Dh,0Ah,0
align 16
first_segment:
include '..\preproce.inc'
include '..\parser.inc'
include '..\exprpars.inc'
align 16
second_segment:
include '..\exprcalc.inc'
include '..\errors.inc'
include '..\symbdump.inc'
include 'system.inc'
first_gate:
call preprocessor
call parser
jmp main+(second_segment shr 4):second_gate-second_segment
first_segment_top = $ - first_segment
include '..\assemble.inc'
include '..\formats.inc'
include '..\x86_64.inc'
include '..\avx.inc'
second_gate:
call assembler
call formatter
jmp main:finish
second_segment_top = $ - second_segment
if first_segment_top>=10000h | second_segment_top>=10000h
if UNREAL_ENABLED>0
UNREAL_ENABLED = -1
else
UNREAL_ENABLED = 0
end if
else
if UNREAL_ENABLED<0
UNREAL_ENABLED = -1
else
UNREAL_ENABLED = 1
end if
end if
include '..\tables.inc'
include '..\messages.inc'
align 4
include '..\variable.inc'
memory_setting dd ?
start_time dd ?
definitions_pointer dd ?
params rb 100h
predefinitions rb 100h
mode dw ?
real_mode_segment dw ?
displayed_count dd ?
last_displayed rb 2
segment buffer
rb 1000h
| gunmetal313/ExePacker | fasm/fasm17139_linux/source/DOS/fasm.asm | Assembly | bsd-3-clause | 7,115 |
;##########################################################################
;# BSrom140 - Modified ZX Spectrum ROM - (c) Busy soft - Release 22.04.97 #
;##########################################################################
; Original ROM: (c) Amstrad
OUTPUT "bsrom140.bin"
VERZIA: EQU 140
VERA: EQU VERZIA/100
VERB: EQU VERA*100
VERC: EQU VERZIA-VERB
VERD: EQU VERC/10
VERE: EQU VERD*10
VERF: EQU VERC-VERE
VER1: EQU '0'+VERA
VER2: EQU '0'+VERD
VER3: EQU '0'+VERF
ORG #0000
; RST #00
START: DI
XOR A
LD DE,#FFFF
JP NMI_MENU ; BSROM - jumps to NMI menu instead of START_NEW
; Error restart
; RST #08
ERROR_1: LD HL,(#5C5D)
CALL TOERR ; BSROM - cursor jumps to error
JR ERROR_2
; Print a character
; RST #10
PRINT_A: JP PRINT_A_2
; Unused bytes
DW #FFFF
DW #FFFF
DB #FF
; Collect a character
; RST #18
GET_CHAR: LD HL,(#5C5D)
LD A,(HL)
TEST_CHAR: CALL SKIP_OVER
RET NC
NEXT_CHAR: CALL CH_ADD_1
JR TEST_CHAR
; Unused bytes
DW #FFFF
DB #FF
; Calculator restart
; RST #28
JP CALCULATE
; Unused bytes
DW #FFFF
DW #FFFF
DB #FF
; Create free locations in work space
; RST #30
BC_SPACES: PUSH BC
LD HL,(#5C61)
PUSH HL
JP RESERVE
; Maskable interrupt routine
; RST #38
MASK_INT: PUSH AF
PUSH HL
LD HL,(#5C78)
INC HL
LD (#5C78),HL
LD A,H
OR L
JR NZ,KEY_INT
INC (IY+#40)
KEY_INT: PUSH BC
PUSH DE
CALL KEYBOARD
POP DE
POP BC
POP HL
POP AF
EI
RET
; A continuation of the code at #0008
ERROR_2: POP HL
LD L,(HL)
ERROR_3: LD (IY+#00),L
LD SP,(#5C3D)
JP SET_STK
; Unused bytes
DW #FFFF
DW #FFFF
DW #FFFF
DB #FF
; Non-maskable interrupt routine
; RST #66
RESET: JP NMI_MENU ; BSROM - jumps to NMI menu
DB #B0 ; Looks like this is unused torso
DB #5C ; of the original RESET routine.
DB #7C ;
DB #B5 ;
DB #20, #01 ;
DB #E9 ;
DB #E1 ;
DB #F1 ;
DB #ED, #45 ; End of unused bytes.
; Fetch the next immediate character following the current valid character address
; and update the associated system variable.
CH_ADD_1: LD HL,(#5C5D)
TEMP_PTR1: INC HL
TEMP_PTR2: LD (#5C5D),HL
LD A,(HL)
RET
; Skip over white-space and other characters irrelevant to the parsing of a basic line
SKIP_OVER: CP #21
RET NC
CP #0D
RET Z
CP #10
RET C
CP #18
CCF
RET C
INC HL
CP #16
JR C,SKIPS
INC HL
SKIPS: SCF
LD (#5C5D),HL
RET
; Six look-up tables for keyboard reading routine to decode the key values.
; Table for tokenized characters (134d-255d).
; Begins with function type words without a leading space.
; The last byte of a token is inverted to denote the end of the word.
TKN_TABLE: DC "?"
DC "RND"
DC "INKEY$"
DC "PI"
DC "FN"
DC "POINT"
DC "SCREEN$"
DC "ATTR"
DC "AT"
DC "TAB"
DC "VAL$"
DC "CODE"
DC "VAL"
DC "LEN"
DC "SIN"
DC "COS"
DC "TAN"
DC "ASN"
DC "ACS"
DC "ATN"
DC "LN"
DC "EXP"
DC "INT"
DC "SQR"
DC "SGN"
DC "ABS"
DC "PEEK"
DC "IN"
DC "USR"
DC "STR$"
DC "CHR$"
DC "NOT"
DC "BIN"
; Function type words with a leading space
; if they begin with a letter.
DC "OR"
DC "AND"
DC "<="
DC ">="
DC "<>"
DC "LINE"
DC "THEN"
DC "TO"
DC "STEP"
DC "DEF FN"
DC "CAT"
DC "FORMAT"
DC "MOVE"
DC "ERASE"
DC "OPEN #"
DC "CLOSE #"
DC "MERGE"
DC "VERIFY"
DC "BEEP"
DC "CIRCLE"
DC "INK"
DC "PAPER"
DC "FLASH"
DC "BRIGHT"
DC "INVERSE"
DC "OVER"
DC "OUT"
DC "LPRINT"
DC "LLIST"
DC "STOP"
DC "READ"
DC "DATA"
DC "RESTORE"
DC "NEW"
DC "BORDER"
DC "CONTINUE"
DC "DIM"
DC "REM"
DC "FOR"
DC "GO TO"
DC "GO SUB"
DC "INPUT"
DC "LOAD"
DC "LIST"
DC "LET"
DC "PAUSE"
DC "NEXT"
DC "POKE"
DC "PRINT"
DC "PLOT"
DC "RUN"
DC "SAVE"
DC "RANDOMIZE"
DC "IF"
DC "CLS"
DC "DRAW"
DC "CLEAR"
DC "RETURN"
DC "COPY"
; maps for the standard 40-key ZX Spectrum keyboard
; SHIFT (#27) is read directly.
MAIN_KEYS: DB #42 ;B
DB #48 ;H
DB #59 ;Y
DB #36 ;6
DB #35 ;5
DB #54 ;T
DB #47 ;G
DB #56 ;V
DB #4E ;N
DB #4A ;J
DB #55 ;U
DB #37 ;7
DB #34 ;4
DB #52 ;R
DB #46 ;F
DB #43 ;C
DB #4D ;M
DB #4B ;K
DB #49 ;I
DB #38 ;8
DB #33 ;3
DB #45 ;E
DB #44 ;D
DB #58 ;X
DB #0E ;Symbol shift
DB #4C ;L
DB #4F ;O
DB #39 ;9
DB #32 ;2
DB #57 ;W
DB #53 ;S
DB #5A ;Z
DB #20 ;Space
DB #0D ;Enter
DB #50 ;P
DB #30 ;0
DB #31 ;1
DB #51 ;Q
DB #41 ;A
; Unshifted extended mode keys.
; The green keywords on the original keyboard.
E_UNSHIFT: DB #E3 ;READ
DB #C4 ;BIN
DB #E0 ;LPRINT
DB #E4 ;DATA
DB #B4 ;TAN
DB #BC ;SGN
DB #BD ;ABS
DB #BB ;SQR
DB #AF ;CODE
DB #B0 ;VAL
DB #B1 ;LEN
DB #C0 ;USR
DB #A7 ;PI
DB #A6 ;INKEY$
DB #BE ;PEEK
DB #AD ;TAB
DB #B2 ;SIN
DB #BA ;INT
DB #E5 ;RESTORE
DB #A5 ;RND
DB #C2 ;CHR$
DB #E1 ;LLIST
DB #B3 ;COS
DB #B9 ;EXP
DB #C1 ;STR$
DB #B8 ;LN
; Shifted extended mode keys.
; The red keywords below keys on the original keyboard.
EXT_SHIFT: DB #7E ;~
DB #DC ;BRIGHT
DB #DA ;PAPER
DB #5C ;\
DB #B7 ;ATN
DB #7B ;{
DB #7D ;}
DB #D8 ;CIRCLE
DB #BF ;IN
DB #AE ;VAL$
DB #AA ;SCREEN$
DB #AB ;ATTR
DB #DD ;INVERSE
DB #DE ;OVER
DB #DF ;OUT
DB #7F ;(c)
DB #B5 ;ASN
DB #D6 ;VERIFY
DB #7C ;|
DB #D5 ;MERGE
DB #5D ;]
DB #DB ;FLASH
DB #B6 ;ACS
DB #D9 ;INK
DB #5B ;[
DB #D7 ;BEEP
; Shift key control codes assigned to the digits.
; White labels above the number characters on the digits keys on the orig. keyboard.
CTL_CODES: DB #0C ;DELETE
DB #07 ;EDIT
DB #06 ;Caps lock
DB #04 ;True video
DB #05 ;Inverse video
DB #08 ;Cursor left
DB #0A ;Cursor down
DB #0B ;Cursor up
DB #09 ;Cursor right
DB #0F ;GRAPH
; Keys shifted with Symbol shift.
; Red symbols on the alphabetic characters on the original keyboard.
SYM_CODES: DB #E2 ;STOP
DB #2A ;*
DB #3F ;?
DB #CD ;STEP
DB #C8 ;>=
DB #CC ;TO
DB #CB ;THEN
DB #5E ;^
DB #AC ;AT
DB #2D ;-
DB #2B ;+
DB #3D ;=
DB #2E ;.
DB #2C ;,
DB #3B ;;
DB #22 ;"
DB #C7 ;<=
DB #3C ;<
DB #C3 ;NOT
DB #3E ;>
DB #C5 ;OR
DB #2F ;/
DB #C9 ;<>
DB #60 ;£
DB #C6 ;AND
DB #3A ;:
; Keywords assigned to the digits in extended mode.
; On the original keyboard those are remaining red keywords below the keys.
E_DIGITS: DB #D0 ;FORMAT
DB #CE ;DEF FN
DB #A8 ;FN
DB #CA ;LINE
DB #D3 ;OPEN #
DB #D4 ;CLOSE #
DB #D1 ;MOVE
DB #D2 ;ERASE
DB #A9 ;POINT
DB #CF ;CAT
; Keyboard scanning
; returns 1 or 2 keys in DE
KEY_SCAN: LD L,#2F
LD DE,#FFFF
LD BC,#FEFE
KEY_LINE: IN A,(C)
CPL
AND #1F
JR Z,KEY_DONE
LD H,A
LD A,L
KEY_3KEYS: INC D
RET NZ
KEY_BITS: SUB #08
SRL H
JR NC,KEY_BITS
LD D,E
LD E,A
JR NZ,KEY_3KEYS
KEY_DONE: DEC L
RLC B
JR C,KEY_LINE
LD A,D
INC A
RET Z
CP #28
RET Z
CP #19
RET Z
LD A,E
LD E,D
LD D,A
CP #18
RET
; Scan keyboard and decode value
KEYBOARD: CALL KEY_SCAN
RET NZ
LD HL,#5C00
K_ST_LOOP: BIT 7,(HL)
JR NZ,K_CH_SET
INC HL
DEC (HL)
DEC HL
JR NZ,K_CH_SET
LD (HL),#FF
K_CH_SET: LD A,L
LD HL,#5C04
CP L
JR NZ,K_ST_LOOP
CALL K_TEST
RET NC
LD HL,#5C00
CP (HL)
JR Z,K_REPEAT
EX DE,HL
LD HL,#5C04
CP (HL)
JR Z,K_REPEAT
BIT 7,(HL)
JR NZ,K_NEW
EX DE,HL
BIT 7,(HL)
RET Z
K_NEW: LD E,A
LD (HL),A
INC HL
LD (HL),#05
INC HL
LD A,(#5C09)
LD (HL),A
INC HL
LD C,(IY+#07)
LD D,(IY+#01)
PUSH HL
CALL K_DECODE
POP HL
LD (HL),A
K_END: LD (#5C08),A
SET 5,(IY+#01)
RET
; Repeat key routine
K_REPEAT: INC HL
LD (HL),#05
INC HL
DEC (HL)
RET NZ
LD A,(#5C0A)
LD (HL),A
INC HL
LD A,(HL)
JR K_END
; Test key value
K_TEST: LD B,D
LD D,#00
LD A,E
CP #27
RET NC
CP #18
JR NZ,K_MAIN
BIT 7,B
RET NZ
K_MAIN: LD HL,MAIN_KEYS
ADD HL,DE
LD A,(HL)
SCF
RET
; Keyboard decoding
K_DECODE: LD A,E
CP #3A
JR C,K_DIGIT
DEC C
JP M,K_KLC_LET
JR Z,K_E_LET
ADD A,#4F
RET
; Test if B is empty (i.e. not a shift)
; forward to K_LOOK_UP if neither shift
K_E_LET: LD HL,#01EB ;E_UNSHIFT-#41
INC B
JR Z,K_LOOK_UP
LD HL,#0205 ;EXT_SHIFT-#41
; Prepare to index
K_LOOK_UP: LD D,#00
ADD HL,DE
LD A,(HL)
RET
; Prepare base of SYM_CODES
K_KLC_LET: LD HL,#0229 ;SYM_CODES-#41
BIT 0,B
JR Z,K_LOOK_UP
BIT 3,D
JR Z,K_TOKENS
BIT 3,(IY+#30)
RET NZ
INC B
RET NZ
ADD A,#20
RET
; Add offset to main code to get tokens
K_TOKENS: ADD A,#A5
RET
; Digits, space, enter and symbol shift decoding
K_DIGIT: CP #30
RET C
DEC C
JP M,K_KLC_DGT
JR NZ,K_GRA_DGT
LD HL,#0254 ;E_DIGITS-#30
BIT 5,B
JR Z,K_LOOK_UP
CP #38
JR NC,K_8_AND_9
SUB #20
INC B
RET Z
ADD A,#08
RET
; Digits 8 and 9 decoding
K_8_AND_9: SUB #36
INC B
RET Z
ADD A,#FE
RET
; Graphics mode with digits
K_GRA_DGT: LD HL,#0230 ;CTL_CODES-#30
CP #39
JR Z,K_LOOK_UP
CP #30
JR Z,K_LOOK_UP
AND #07
ADD A,#80
INC B
RET Z
XOR #0F
RET
; Digits in 'KLC' mode
K_KLC_DGT: INC B
RET Z
BIT 5,B
LD HL,#0230 ;CTL_CODES-#30
JR NZ,K_LOOK_UP
SUB #10
CP #22
JR Z,K_AT_CHAR
CP #20
RET NZ
LD A,#5F
RET
; Substitute ascii '@'
K_AT_CHAR: LD A,#40
RET
; Routine to control loudspeaker
BEEPER: DI
LD A,L
SRL L
SRL L
CPL
AND #03
LD C,A
LD B,#00
LD IX,BE_IX_3
ADD IX,BC
LD A,(#5C48)
AND #38
RRCA
RRCA
RRCA
OR #08
BE_IX_3: NOP
NOP
NOP
INC B
INC C
BE_HL_LP: DEC C
JR NZ,BE_HL_LP
LD C,#3F
DEC B
JP NZ,BE_HL_LP
XOR #10
OUT (#FE),A
LD B,H
LD C,A
BIT 4,A
JR NZ,BE_AGAIN
LD A,D
OR E
JR Z,BE_END
LD A,C
LD C,L
DEC DE
L_03F0: JP (IX)
BE_AGAIN: LD C,L
INC C
JP (IX)
BE_END: EI
RET
; Handle BEEP command
BEEP: RST #28 ;FP_CALC
DB #31 ;DUPLICATE - duplicate pitch
DB #27 ;INT - convert to integer
DB #C0 ;ST_MEM_0 - store integer pitch to memory 0
DB #03 ;SUBTRACT - calculate fractional part of pitch = fp_pitch - int_pitch
DB #34 ;STK_DATA - push constant
DB #EC ;Exponent: #7C, Bytes: 4 - constant = 0.05762265
DB #6C,#98,#1F,#F5 ;(#6C,#98,#1F,#F5)
DB #04 ;MULTIPLY - compute:
DB #A1 ;STK_ONE - 1 + 0.05762265 * fraction_part(pitch)
DB #0F ;ADDITION
DB #38 ;END_CALC - leave on calc stack
LD HL,#5C92
LD A,(HL)
AND A
JR NZ,REPORT_B
INC HL
LD C,(HL)
INC HL
LD B,(HL)
LD A,B
RLA
SBC A,A
CP C
JR NZ,REPORT_B
INC HL
CP (HL)
JR NZ,REPORT_B
LD A,B
ADD A,#3C
JP P,BE_I_OK
JP PO,REPORT_B
BE_I_OK: LD B,#FA
BE_OCTAVE: INC B
SUB #0C
JR NC,BE_OCTAVE
ADD A,#0C
PUSH BC
LD HL,SEMI_TONE
CALL LOC_MEM
CALL STACK_NUM
RST #28 ;FP_CALC
DB #04 ;MULTIPLY
DB #38 ;END_CALC
POP AF
ADD A,(HL)
LD (HL),A
RST #28 ;FP_CALC
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #31 ;DUPLICATE
DB #38 ;END_CALC
CALL FIND_INT1
CP #0B
JR NC,REPORT_B
RST #28 ;FP_CALC
DB #E0 ;GET_MEM_0
DB #04 ;MULTIPLY
DB #E0 ;GET_MEM_0
DB #34 ;STK_DATA
DB #80 ;Exponent #93, Bytes: 3
DB #43, #55, #9F, #80
DB #01 ;EXCHANGE
DB #05 ;DIVISION
DB #34 ;STK_DATA
DB #35 ;Exponent: #85, Bytes: 1
DB #71
DB #03 ;SUBTRACT
DB #38 ;END_CALC
CALL FIND_INT2
PUSH BC
CALL FIND_INT2
POP HL
LD D,B
LD E,C
LD A,D
OR E
RET Z
DEC DE
JP BEEPER
REPORT_B: RST #08 ; Error report
DB #0A ; Integer out of range
; Semi-tone table.
; Holds frequencies corresponding to semitones in middle octave.
SEMI_TONE: DB #89, #02, #D0, #12, #86
DB #89, #0A, #97, #60, #75
DB #89, #12, #D5, #17, #1F
DB #89, #1B, #90, #41, #02
DB #89, #24, #D0, #53, #CA
DB #89, #2E, #9D, #36, #B1
DB #89, #38, #FF, #49, #3E
DB #89, #43, #FF, #6A, #73
DB #89, #4F, #A7, #00, #54
DB #89, #5C, #00, #00, #00
DB #89, #69, #14, #F6, #24
DB #89, #76, #F1, #10, #05
; BSROM - file name is optional now.
; There was ZX81_NAME routine at this place, but it was not used anyway.
NONAME: RST #18
LD HL,NNTAB
LD BC,#0005
CPIR
JP NZ,EXPT_EXP
LD C,#00
JP SL_OVER1
NNTAB: DB #3A
DW #AA0D
DW #E4AF
DW #0000
; Save header and program or data
SA_BYTES: LD HL,SA_LD_RET
PUSH HL
SA_BYTES1: LD HL,#1F80
BIT 7,A
JR Z,SA_FLAG
LD HL,#0C98
SA_FLAG: EX AF,AF'
INC DE
DEC IX
DI
LD A,#02
LD B,A
SA_LEADER: DJNZ SA_LEADER
OUT (#FE),A
XOR #0F
LD B,#A4
DEC L
JR NZ,SA_LEADER
DEC B
DEC H
JP P,SA_LEADER
LD B,#2F
SA_SYNC_1: DJNZ SA_SYNC_1
OUT (#FE),A
LD A,#0D
LD B,#37
SA_SYNC_2: DJNZ SA_SYNC_2
OUT (#FE),A
LD BC,#3B0E ; B=#3B time; C=#0E YELLOW, MIC OFF.
EX AF,AF'
LD L,A
JP SA_START
SA_LOOP: LD A,D
OR E
JR Z,SA_PARITY
LD L,(IX+#00)
SA_LOOP_P: LD A,H
XOR L
SA_START: LD H,A
LD A,#01
SCF
JP SA_8_BITS
SA_PARITY: LD L,H
JR SA_LOOP_P
SA_BIT_2: LD A,C
BIT 7,B
SA_BIT_1: DJNZ SA_BIT_1
JR NC,SA_OUT
LD B,#42
SA_SET: DJNZ SA_SET
SA_OUT: OUT (#FE),A
LD B,#3E
JR NZ,SA_BIT_2
DEC B
XOR A
INC A
SA_8_BITS: RL L
JP NZ,SA_BIT_1
DEC DE
INC IX
LD B,#31
LD A,#7F
IN A,(#FE)
RRA
RET NC
LD A,D
INC A
JP NZ,SA_LOOP
LD B,#3B
SA_DELAY: DJNZ SA_DELAY
RET
; Reset border nad check BREAK for LOAD and SAVE
SA_LD_RET: PUSH AF
LD A,(#5C48)
AND #38
RRCA
RRCA
RRCA
OUT (#FE),A
LD A,#7F
IN A,(#FE)
RRA
EI
JR C,SA_LD_END
REPORT_DA: RST #08 ; Error report
DB #0C ; BREAK - CONT repeats
SA_LD_END: POP AF
RET
; Load header or data
LD_BYTES: INC D
EX AF,AF'
DEC D
DI
LD A,#0F
OUT (#FE),A
LD HL,SA_LD_RET
PUSH HL
IN A,(#FE)
RRA
LD_BYTES1: AND #20
OR #02
LD C,A
CP A
LD_BREAK: RET NZ
LD_START: CALL LD_EDGE_1
JR NC,LD_BREAK
LD HL,#0115 ; BSROM - short delay (was #0415 in orig. ROM)
LD_WAIT: DJNZ LD_WAIT
DEC HL
LD A,H
OR L
JR NZ,LD_WAIT
CALL LD_EDGE_2
JR NC,LD_BREAK
LD_LEADER: LD B,#9C
CALL LD_EDGE_2
JR NC,LD_BREAK
LD A,#C6
CP B
JR NC,LD_START
INC H
JR NZ,LD_LEADER
LD_SYNC: LD B,#C9
CALL LD_EDGE_1
JR NC,LD_BREAK
LD A,B
CP #D4
JR NC,LD_SYNC
CALL LD_EDGE_1
RET NC
LD A,C
XOR #03
LD C,A
LD H,#00
LD B,#B0
JR LD_MARKER
LD_LOOP: EX AF,AF'
JR NZ,LD_FLAG
JR NC,LD_VERIFY
LD (IX+#00),L
JR LD_NEXT
LD_FLAG: RL C
XOR L
RET NZ
LD A,C
RRA
LD C,A
INC DE
JR LD_DEC
LD_VERIFY: LD A,(IX+#00)
XOR L
RET NZ
LD_NEXT: INC IX
LD_DEC: DEC DE
EX AF,AF'
LD B,#B2
LD_MARKER: LD L,#01
LD_8_BITS: CALL LD_EDGE_2
RET NC
LD A,#CB
CP B
RL L
LD B,#B0
JP NC,LD_8_BITS
LD A,H
XOR L
LD H,A
LD A,D
OR E
JR NZ,LD_LOOP
LD A,H
CP #01
RET
; Check signal being loaded
LD_EDGE_2: CALL LD_EDGE_1
RET NC
LD_EDGE_1: LD A,#16
LD_DELAY: DEC A
JR NZ,LD_DELAY
AND A
LD_SAMPLE: INC B
RET Z
LD A,#7F
IN A,(#FE)
RRA
RET NC
XOR C
AND #20
JR Z,LD_SAMPLE
LD A,C
CPL
LD C,A
AND #07
OR #08
OUT (#FE),A
SCF
RET
; Entry point for tape commands
SAVE_ETC: POP AF
LD A,(#5C74)
SUB #E0
LD (#5C74),A
CALL NONAME ; BSROM - file name is optional now
CALL SYNTAX_Z
JR Z,SA_DATA
LD BC,#0011
LD A,(#5C74)
AND A
JR Z,SA_SPACE
LD C,#22
SA_SPACE: RST #30
PUSH DE
POP IX
LD B,#0B
LD A,#20
SA_BLANK: LD (DE),A
INC DE
DJNZ SA_BLANK
LD (IX+#01),#FF
CALL STK_FETCH
LD HL,#FFF6
DEC BC
ADD HL,BC
INC BC
JR NC,SA_NAME
LD A,(#5C74)
AND A
JR NZ,SA_NULL
REPORT_FA: RST #08 ; Error report
DB #0E ; Invalid file name
SA_NULL: LD A,B
OR C
JR Z,SA_DATA
LD BC,#000A
SA_NAME: PUSH IX
POP HL
INC HL
EX DE,HL
LDIR
SA_DATA: RST #18
CP #E4
JR NZ,SA_SCR
LD A,(#5C74)
CP #03
JP Z,REPORT_C
RST #20
CALL LOOK_VARS
SET 7,C
JR NC,SA_V_OLD
LD HL,#0000
LD A,(#5C74)
DEC A
JR Z,SA_V_NEW
REPORT_2A: RST #08 ; Error report
DB #01 ; Variable not found
SA_V_OLD: JP NZ,REPORT_C
CALL SYNTAX_Z
JR Z,SA_DATA_1
INC HL
LD A,(HL)
LD (IX+#0B),A
INC HL
LD A,(HL)
LD (IX+#0C),A
INC HL
SA_V_NEW: LD (IX+#0E),C
LD A,#01
BIT 6,C
JR Z,SA_V_TYPE
INC A
SA_V_TYPE: LD (IX+#00),A
SA_DATA_1: EX DE,HL
RST #20
CP #29
JR NZ,SA_V_OLD
RST #20
CALL CHECK_END
EX DE,HL
JP SA_ALL
SA_SCR: CP #AA
JR NZ,SA_CODE
LD A,(#5C74)
CP #03
JP Z,REPORT_C
RST #20
CALL CHECK_END
LD (IX+#0B),#00
LD (IX+#0C),#1B
LD HL,#4000
LD (IX+#0D),L
LD (IX+#0E),H
JR SA_TYPE_3
SA_CODE: CP #AF
JR NZ,SA_LINE
LD A,(#5C74)
CP #03
JP Z,REPORT_C
RST #20
CALL PR_ST_END
JR NZ,SA_CODE_1
LD A,(#5C74)
AND A
JP Z,REPORT_C
CALL USE_ZERO
JR SA_CODE_2
SA_CODE_1: CALL EXPT_1NUM
RST #18
CP #2C
JR Z,SA_CODE_3
LD A,(#5C74)
AND A
JP Z,REPORT_C
SA_CODE_2: CALL USE_ZERO
JR SA_CODE_4
SA_CODE_3: RST #20
CALL EXPT_1NUM
SA_CODE_4: CALL CHECK_END
CALL FIND_INT2
LD (IX+#0B),C
LD (IX+#0C),B
CALL FIND_INT2
LD (IX+#0D),C
LD (IX+#0E),B
LD H,B
LD L,C
SA_TYPE_3: LD (IX+#00),#03
JR SA_ALL
SA_LINE: CP #CA
JR Z,SA_LINE_1
CALL CHECK_END
LD (IX+#0E),#80
JR SA_TYPE_0
SA_LINE_1: LD A,(#5C74)
AND A
JP NZ,REPORT_C
RST #20
CALL EXPT_1NUM
CALL CHECK_END
CALL FIND_INT2
LD (IX+#0D),C
LD (IX+#0E),B
SA_TYPE_0: LD (IX+#00),#00
LD HL,(#5C59)
LD DE,(#5C53)
SCF
SBC HL,DE
LD (IX+#0B),L
LD (IX+#0C),H
LD HL,(#5C4B)
SBC HL,DE
LD (IX+#0F),L
LD (IX+#10),H
EX DE,HL
SA_ALL: LD A,(#5C74)
AND A
JP Z,SA_CONTRL
PUSH HL
LD BC,#0011
ADD IX,BC
LD_LOOK_H: PUSH IX
LD DE,#0011
XOR A
SCF
CALL LD_BYTES
POP IX
JR NC,LD_LOOK_H
LD A,#FE
CALL CHAN_OPEN
LD (IY+#52),#FF ; BSROM - fixed "scroll?" troubles when tape header is shown, was LD (IY+$52),$03
LD C,#80
LD A,(IX+#00)
CP (IX-#11)
JR NZ,LD_TYPE
LD C,#F6
LD_TYPE: CP #04
JR NC,LD_LOOK_H
LD DE,TAPE_MSGS2
PUSH BC
CALL PO_MSG
POP BC
PUSH IX
POP DE
LD HL,#FFF0
ADD HL,DE
LD B,#0A
LD A,(HL)
INC A
JR NZ,LD_NAME
LD A,C
ADD A,B
LD C,A
LD_NAME: INC DE
LD A,(DE)
CP (HL)
INC HL
JR NZ,LD_CH_PR
INC C
LD_CH_PR: RST #10
DJNZ LD_NAME
BIT 7,C
JR NZ,LD_LOOK_H
LD A,#0D
RST #10
POP HL
LD A,(IX+#00)
CP #03
JR Z,VR_CONTROL
LD A,(#5C74)
DEC A
JP Z,LD_CONTRL
CP #02
JP Z,ME_CONTRL
VR_CONTROL: PUSH HL ; Handle VERIFY control
LD L,(IX-#06)
LD H,(IX-#05)
LD E,(IX+#0B)
LD D,(IX+#0C)
LD A,H
OR L
JR Z,VR_CONT_1
SBC HL,DE
JR C,REPORT_R
JR Z,VR_CONT_1
LD A,(IX+#00)
CP #03
JR NZ,REPORT_R
VR_CONT_1: POP HL
LD A,H
OR L
JR NZ,VR_CONT_2
LD L,(IX+#0D)
LD H,(IX+#0E)
VR_CONT_2: PUSH HL
POP IX
LD A,(#5C74)
CP #02
SCF
JR NZ,VR_CONT_3
AND A
VR_CONT_3: LD A,#FF
LD_BLOCK: CALL LD_BYTES ; Load a block of data
RET C
REPORT_R: RST #08 ; Error report
DB #1A ; Tape loading error
LD_CONTRL: LD E,(IX+#0B) ; Handle LOAD control
LD D,(IX+#0C)
PUSH HL
LD A,H
OR L
JR NZ,LD_CONT_1
INC DE
INC DE
INC DE
EX DE,HL
JR LD_CONT_2
LD_CONT_1: LD L,(IX-#06)
LD H,(IX-#05)
EX DE,HL
SCF
SBC HL,DE
JR C,LD_DATA
LD_CONT_2: LD DE,#0005
ADD HL,DE
LD B,H
LD C,L
CALL TEST_ROOM
LD_DATA: POP HL
LD A,(IX+#00)
AND A
JR Z,LD_PROG
LD A,H
OR L
JR Z,LD_DATA_1
DEC HL
LD B,(HL)
DEC HL
LD C,(HL)
DEC HL
INC BC
INC BC
INC BC
LD (#5C5F),IX
CALL RECLAIM_2
LD IX,(#5C5F)
LD_DATA_1: LD HL,(#5C59)
DEC HL
LD C,(IX+#0B)
LD B,(IX+#0C)
PUSH BC
INC BC
INC BC
INC BC
LD A,(IX-#03)
PUSH AF
CALL MAKE_ROOM
INC HL
POP AF
LD (HL),A
POP DE
INC HL
LD (HL),E
INC HL
LD (HL),D
INC HL
PUSH HL
POP IX
SCF
LD A,#FF
JP LD_BLOCK
LD_PROG: EX DE,HL
LD HL,(#5C59)
DEC HL
LD (#5C5F),IX
LD C,(IX+#0B)
LD B,(IX+#0C)
PUSH BC
CALL RECLAIM_1
POP BC
PUSH HL
PUSH BC
CALL MAKE_ROOM
LD IX,(#5C5F)
INC HL
LD C,(IX+#0F)
LD B,(IX+#10)
ADD HL,BC
LD (#5C4B),HL
LD H,(IX+#0E)
LD A,H
AND #C0
JR NZ,LD_PROG_1
LD L,(IX+#0D)
LD (#5C42),HL
LD (IY+#0A),#00
LD_PROG_1: POP DE
POP IX
SCF
LD A,#FF
JP LD_BLOCK
; Handle MERGE control
ME_CONTRL: LD C,(IX+#0B)
LD B,(IX+#0C)
PUSH BC
INC BC
RST #30
LD (HL),#80
EX DE,HL
POP DE
PUSH HL
PUSH HL
POP IX
SCF
LD A,#FF
CALL LD_BLOCK
POP HL
LD DE,(#5C53)
ME_NEW_LP: LD A,(HL)
AND #C0
JR NZ,ME_VAR_LP
ME_OLD_LP: LD A,(DE)
INC DE
CP (HL)
INC HL
JR NZ,ME_OLD_L1
LD A,(DE)
CP (HL)
ME_OLD_L1: DEC DE
DEC HL
JR NC,ME_NEW_L2
PUSH HL
EX DE,HL
CALL NEXT_ONE
POP HL
JR ME_OLD_LP
ME_NEW_L2: CALL ME_ENTER
JR ME_NEW_LP
ME_VAR_LP: LD A,(HL)
LD C,A
CP #80
RET Z
PUSH HL
LD HL,(#5C4B)
ME_OLD_VP: LD A,(HL)
CP #80
JR Z,ME_VAR_L2
CP C
JR Z,ME_OLD_V2
ME_OLD_V1: PUSH BC
CALL NEXT_ONE
POP BC
EX DE,HL
JR ME_OLD_VP
ME_OLD_V2: AND #E0
CP #A0
JR NZ,ME_VAR_L1
POP DE
PUSH DE
PUSH HL
ME_OLD_V3: INC HL
INC DE
LD A,(DE)
CP (HL)
JR NZ,ME_OLD_V4
RLA
JR NC,ME_OLD_V3
POP HL
JR ME_VAR_L1
ME_OLD_V4: POP HL
JR ME_OLD_V1
ME_VAR_L1: LD A,#FF
ME_VAR_L2: POP DE
EX DE,HL
INC A
SCF
CALL ME_ENTER
JR ME_VAR_LP
; Merge a line or variable
ME_ENTER: JR NZ,ME_ENT_1
EX AF,AF'
LD (#5C5F),HL
EX DE,HL
CALL NEXT_ONE
CALL RECLAIM_2
EX DE,HL
LD HL,(#5C5F)
EX AF,AF'
ME_ENT_1: EX AF,AF'
PUSH DE
CALL NEXT_ONE
LD (#5C5F),HL
LD HL,(#5C53)
EX (SP),HL
PUSH BC
EX AF,AF'
JR C,ME_ENT_2
DEC HL
CALL MAKE_ROOM
INC HL
JR ME_ENT_3
ME_ENT_2: CALL MAKE_ROOM
ME_ENT_3: INC HL
POP BC
POP DE
LD (#5C53),DE
LD DE,(#5C5F)
PUSH BC
PUSH DE
EX DE,HL
LDIR
POP HL
POP BC
PUSH DE
CALL RECLAIM_2
POP DE
RET
; Handle SAVE control
SA_CONTRL: PUSH HL
LD A,#FD
CALL CHAN_OPEN
XOR A
LD DE,TAPE_MSGS
CALL PO_MSG
SET 5,(IY+#02)
CALL WAIT_KEY
PUSH IX
LD DE,#0011
XOR A
CALL SA_BYTES
POP IX
LD B,#32
SA_1_SEC: HALT
DJNZ SA_1_SEC
LD E,(IX+#0B)
LD D,(IX+#0C)
POP IX ; BSROM - LD A,#FF and POP IX swapped
LD A,#FF
JP SA_BYTES
; Tape mesages
TAPE_MSGS: DB #80
DC "Press REC & PLAY, then any key."
TAPE_MSGS2: EQU $-1
DB #0D
DC "Program: "
DB #0D
DC "Number array: "
DB #0D
DC "Character array: "
DB #0D
DC "Bytes: "
; Genereal PRINT routine
PRINT_OUT: CALL DISPL ; BSROM - disabled autolist of control codes
CP #1E
JP NC,PO_ABLE
CP #06
JR C,PO_QUEST
CP #18
JR NC,PO_QUEST
LD HL,CTLCHRTAB-6
LD E,A
LD D,#00
ADD HL,DE
LD E,(HL)
ADD HL,DE
PUSH HL
JP PO_FETCH
;Control character table
CTLCHRTAB: DB #4E ; PO_COMMA
DB #57 ; PO_QUEST
DB #10 ; PO_BACK_1
DB #29 ; PO_RIGHT
DB #54 ; PO_QUEST
DB #53 ; PO_QUEST
DB #52 ; PO_QUEST
DB #37 ; PO_ENTER
DB #50 ; PO_QUEST
DB #4F ; PO_QUEST
DB #5F ; PO_1_OPER
DB #5E ; PO_1_OPER
DB #5D ; PO_1_OPER
DB #5C ; PO_1_OPER
DB #5B ; PO_1_OPER
DB #5A ; PO_1_OPER
DB #54 ; PO_2_OPER
DB #53 ; PO_2_OPER
; Cursor left routine
PO_BACK_1: INC C
LD A,#22
CP C
JR NZ,PO_BACK_3
BIT 1,(IY+#01)
JR NZ,PO_BACK_2
INC B
LD C,#02
LD A,#19 ; BSROM - bugfix - was LD A,#18
CP B
JR NZ,PO_BACK_3
DEC B
PO_BACK_2: LD C,#21
PO_BACK_3: JP CL_SET
; Cursor right routine
PO_RIGHT: LD A,(#5C91)
PUSH AF
LD (IY+#57),#01
LD A,#20
CALL PO_ABLE ; BSROM - bugfix - was CALL PO_BACK
POP AF
LD (#5C91),A
RET
; Carriage return / Enter
PO_ENTER: BIT 1,(IY+#01)
JP NZ,COPY_BUFF
LD C,#21
CALL PO_SCR
DEC B
JP CL_SET
; Print comma
PO_COMMA: CALL PO_FETCH
LD A,C
DEC A
DEC A
AND #10
JR PO_FILL
; Print question mark
PO_QUEST: LD A,#3F
JR PO_ABLE
; Control characters with operands
PO_TV_2: LD DE,PO_CONT
LD (#5C0F),A
JR PO_CHANGE
PO_2_OPER: LD DE,PO_TV_2
JR PO_TV_1
PO_1_OPER: LD DE,PO_CONT
PO_TV_1: LD (#5C0E),A
PO_CHANGE: LD HL,(#5C51)
LD (HL),E
INC HL
LD (HL),D
RET
PO_CONT: LD DE,PRINT_OUT
CALL PO_CHANGE
LD HL,(#5C0E)
LD D,A
LD A,L
CP #16
JP C,CO_TEMP_5
JR NZ,PO_TAB
LD B,H
LD C,D
LD A,#1F
SUB C
JR C,PO_AT_ERR
ADD A,#02
LD C,A
BIT 1,(IY+#01)
JR NZ,PO_AT_SET
LD A,#16
SUB B
PO_AT_ERR: JP C,REPORT_BB
INC A
LD B,A
INC B
BIT 0,(IY+#02)
JP NZ,PO_SCR
CP (IY+#31)
JP C,REPORT_5
PO_AT_SET: JP CL_SET
PO_TAB: LD A,H
PO_FILL: CALL PO_FETCH
ADD A,C
DEC A
AND #1F
RET Z
LD D,A
SET 0,(IY+#01)
PO_SPACE: LD A,#20
CALL PO_SAVE
DEC D
JR NZ,PO_SPACE
RET
; Print printable character(s)
PO_ABLE: CALL PO_ANY
; Store line, column and pixel address
PO_STORE: BIT 1,(IY+#01)
JR NZ,PO_ST_PR
BIT 0,(IY+#02)
JR NZ,PO_ST_E
LD (#5C88),BC
LD (#5C84),HL
RET
PO_ST_E: LD (#5C8A),BC
LD (#5C82),BC
LD (#5C86),HL
RET
PO_ST_PR: LD (IY+#45),C
LD (#5C80),HL
RET
; Fetch position parameters
PO_FETCH: BIT 1,(IY+#01)
JR NZ,PO_F_FR
LD BC,(#5C88)
LD HL,(#5C84)
BIT 0,(IY+#02)
RET Z
LD BC,(#5C8A)
LD HL,(#5C86)
RET
PO_F_FR: LD C,(IY+#45)
LD HL,(#5C80)
RET
; Print any character
PO_ANY: CP #80
JR C,PO_CHAR
CP #90
JR NC,PO_T_UDG
LD B,A
CALL PO_GR_1
CALL PO_FETCH
LD DE,#5C92
JR PR_ALL
PO_GR_1: LD HL,#5C92
CALL PO_GR_2
PO_GR_2: RR B
SBC A,A
AND #0F
LD C,A
RR B
SBC A,A
AND #F0
OR C
LD C,#04
PO_GR_3: LD (HL),A
INC HL
DEC C
JR NZ,PO_GR_3
RET
PO_T_UDG: SUB #A5
JR NC,PO_T
ADD A,#15
PUSH BC
LD BC,(#5C7B)
JR PO_CHAR_2
PO_T: CALL PO_TOKENS
JP PO_FETCH
PO_CHAR: PUSH BC
LD BC,(#5C36)
PO_CHAR_2: EX DE,HL
LD HL,#5C3B
RES 0,(HL)
CP #20
JR NZ,PO_CHAR_3
SET 0,(HL)
PO_CHAR_3: LD H,#00
LD L,A
ADD HL,HL
ADD HL,HL
ADD HL,HL
ADD HL,BC
POP BC
EX DE,HL
PR_ALL: LD A,C ; Print all characters
DEC A
LD A,#21
JR NZ,PR_ALL_1
DEC B
LD C,A
BIT 1,(IY+#01)
JR Z,PR_ALL_1
PUSH DE
CALL COPY_BUFF
POP DE
LD A,C
PR_ALL_1: CP C
PUSH DE
CALL Z,PO_SCR
POP DE
PUSH BC
PUSH HL
LD A,(#5C91)
LD B,#FF
RRA
JR C,PR_ALL_2
INC B
PR_ALL_2: RRA
RRA
SBC A,A
LD C,A
LD A,#08
AND A
BIT 1,(IY+#01)
JR Z,PR_ALL_3
SET 1,(IY+#30)
SCF
PR_ALL_3: EX DE,HL
PR_ALL_4: EX AF,AF'
LD A,(DE)
AND B
XOR (HL)
XOR C
LD (DE),A
EX AF,AF'
JR C,PR_ALL_6
INC D
PR_ALL_5: INC HL
DEC A
JR NZ,PR_ALL_4
EX DE,HL
DEC H
BIT 1,(IY+#01)
CALL Z,PO_ATTR
POP HL
POP BC
DEC C
INC HL
RET
PR_ALL_6: EX AF,AF'
LD A,#20
ADD A,E
LD E,A
EX AF,AF'
JR PR_ALL_5
; Set attribute
PO_ATTR: LD A,H
RRCA
RRCA
RRCA
AND #03
OR #58
LD H,A
LD DE,(#5C8F)
LD A,(HL)
XOR E
AND D
XOR E
BIT 6,(IY+#57)
JR Z,PO_ATTR_1
AND #C7
BIT 2,A
JR NZ,PO_ATTR_1
XOR #38
PO_ATTR_1: BIT 4,(IY+#57)
JR Z,PO_ATTR_2
AND #F8
BIT 5,A
JR NZ,PO_ATTR_2
XOR #07
PO_ATTR_2: LD (HL),A
RET
; Message printing (boot-up, tape, scroll, error reports)
PO_MSG: PUSH HL
LD H,#00
EX (SP),HL
JR PO_TABLE
PO_TOKENS: LD DE,TKN_TABLE
PO_TOKENS1: PUSH AF
PO_TABLE: CALL PO_SEARCH
JR C,PO_EACH
LD A,#20
BIT 0,(IY+#01)
CALL Z,PO_SAVE
PO_EACH: LD A,(DE)
AND #7F
CALL PO_SAVE
LD A,(DE)
INC DE
ADD A,A
JR NC,PO_EACH
POP DE
CP #48
JR Z,PO_TR_SP
CP #82
RET C
PO_TR_SP: LD A,D
CP #03
RET C
LD A,#20
PO_SAVE: PUSH DE ; Handle recursive printing
EXX
RST #10
EXX
POP DE
RET
; Token table search
PO_SEARCH: PUSH AF
EX DE,HL
INC A
PO_STEP: BIT 7,(HL)
INC HL
JR Z,PO_STEP
DEC A
JR NZ,PO_STEP
EX DE,HL
POP AF
CP #20
RET C
LD A,(DE)
SUB #41
RET
; Test for scroll
PO_SCR: BIT 1,(IY+#01)
RET NZ
LD DE,CL_SET
PUSH DE
LD A,B
BIT 0,(IY+#02)
JP NZ,PO_SCR_4
CP (IY+#31)
JR C,REPORT_5
RET NZ
BIT 4,(IY+#02)
JR Z,PO_SCR_2
LD E,(IY+#2D)
DEC E
JR Z,PO_SCR_3
LD A,#00
CALL CHAN_OPEN
LD SP,(#5C3F)
RES 4,(IY+#02)
RET
REPORT_5: RST #08 ; Error report
DB #04 ; Out of screen
PO_SCR_2: DEC (IY+#52)
JR NZ,PO_SCR_3
LD A,#18
SUB B
LD (#5C8C),A
LD HL,(#5C8F)
PUSH HL
LD A,(#5C91)
PUSH AF
LD A,#FD
CALL CHAN_OPEN
XOR A
LD DE,SCRL_MSG
CALL PO_MSG
SET 5,(IY+#02)
LD HL,#5C3B
SET 3,(HL)
RES 5,(HL)
EXX
CALL WAIT_KEY
EXX
CP #20
JR Z,REPORT_D
CP #E2
JR Z,REPORT_D
OR #20
CP #6E
JR Z,REPORT_D
LD A,#FE
CALL CHAN_OPEN
POP AF
LD (#5C91),A
POP HL
LD (#5C8F),HL
PO_SCR_3: CALL CL_SC_ALL
LD B,(IY+#31)
INC B
LD C,#21
PUSH BC
CALL CL_ADDR
LD A,H
RRCA
RRCA
RRCA
AND #03
OR #58
LD H,A
LD DE,#5AE0
LD A,(DE)
LD C,(HL)
LD B,#20
EX DE,HL
PO_SCR_3A: LD (DE),A
LD (HL),C
INC DE
INC HL
DJNZ PO_SCR_3A
POP BC
RET
SCRL_MSG: DB #80
DC "scroll?"
REPORT_D: RST #08 ; Error report
DB #0C ; BREAK - CONT repeats
PO_SCR_4: CP #02
JR C,REPORT_5
ADD A,(IY+#31)
SUB #19
RET NC
NEG
PUSH BC
LD B,A
LD HL,(#5C8F)
PUSH HL
LD HL,(#5C91)
PUSH HL
CALL TEMPS
LD A,B
PO_SCR_4A: PUSH AF
LD HL,#5C6B
LD B,(HL)
LD A,B
INC A
LD (HL),A
LD HL,#5C89
CP (HL)
JR C,PO_SCR_4B
INC (HL)
LD B,#18
PO_SCR_4B: CALL CL_SCROLL
POP AF
DEC A
JR NZ,PO_SCR_4A
POP HL
LD (IY+#57),L
POP HL
LD (#5C8F),HL
LD BC,(#5C88)
RES 0,(IY+#02)
CALL CL_SET
SET 0,(IY+#02)
POP BC
RET
; Copy temporary items
TEMPS: XOR A
LD HL,(#5C8D)
BIT 0,(IY+#02)
JR Z,TEMPS_1
LD H,A
LD L,(IY+#0E)
TEMPS_1: LD (#5C8F),HL
LD HL,#5C91
JR NZ,TEMPS_2
LD A,(HL)
RRCA
TEMPS_2: XOR (HL)
AND #55
XOR (HL)
LD (HL),A
RET
; Handle CLS command
CLS: CALL CL_ALL
CLS_LOWER: LD HL,#5C3C
RES 5,(HL)
SET 0,(HL)
CALL TEMPS
LD B,(IY+#31)
CALL CL_LINE
LD HL,#5AC0
LD A,(#5C8D)
DEC B
JR CLS_3
CLS_1: LD C,#20
CLS_2: DEC HL
LD (HL),A
DEC C
JR NZ,CLS_2
CLS_3: DJNZ CLS_1
LD (IY+#31),#02
CL_CHAN: LD A,#FD
CALL CHAN_OPEN
LD HL,(#5C51)
LD DE,PRINT_OUT
AND A
CL_CHAN_A: LD (HL),E
INC HL
LD (HL),D
INC HL
LD DE,KEY_INPUT
CCF
JR C,CL_CHAN_A
LD BC,#1721
JR CL_SET
; Clear display area
CL_ALL: LD HL,#0000
LD (#5C7D),HL
RES 0,(IY+#30)
CALL CL_CHAN
LD A,#FE
CALL CHAN_OPEN
CALL TEMPS
LD B,#18
CALL CL_LINE
LD HL,(#5C51)
LD DE,PRINT_OUT
LD (HL),E
INC HL
LD (HL),D
LD (IY+#52),#01
LD BC,#1821
CL_SET: LD HL,#5B00 ; Set line and column numbers
BIT 1,(IY+#01)
JR NZ,CL_SET_2
LD A,B
BIT 0,(IY+#02)
JR Z,CL_SET_1
ADD A,(IY+#31)
SUB #18
CL_SET_1: PUSH BC
LD B,A
CALL CL_ADDR
POP BC
CL_SET_2: LD A,#21
SUB C
LD E,A
LD D,#00
ADD HL,DE
JP PO_STORE
; Scroll part or whole display
CL_SC_ALL: LD B,#17
CL_SCROLL: CALL CL_ADDR
LD C,#08
CL_SCR_1: PUSH BC
PUSH HL
LD A,B
AND #07
LD A,B
JR NZ,CL_SCR_3
CL_SCR_2: EX DE,HL
LD HL,#F8E0
ADD HL,DE
EX DE,HL
LD BC,#0020
DEC A
LDIR
CL_SCR_3: EX DE,HL
LD HL,#FFE0
ADD HL,DE
EX DE,HL
LD B,A
AND #07
RRCA
RRCA
RRCA
LD C,A
LD A,B
LD B,#00
LDIR
LD B,#07
ADD HL,BC
AND #F8
JR NZ,CL_SCR_2
POP HL
INC H
POP BC
DEC C
JR NZ,CL_SCR_1
CALL CL_ATTR
LD HL,#FFE0
ADD HL,DE
EX DE,HL
LDIR
LD B,#01
CL_LINE: PUSH BC ; Clear text lines at the bottom of display
CALL CL_ADDR
LD C,#08
CL_LINE_1: PUSH BC
PUSH HL
LD A,B
CL_LINE_2: AND #07
RRCA
RRCA
RRCA
LD C,A
LD A,B
LD B,#00
DEC C
LD D,H
LD E,L
LD (HL),#00
INC DE
LDIR
LD DE,#0701
ADD HL,DE
DEC A
AND #F8
LD B,A
JR NZ,CL_LINE_2
POP HL
INC H
POP BC
DEC C
JR NZ,CL_LINE_1
CALL CL_ATTR
LD H,D
LD L,E
INC DE
LD A,(#5C8D)
BIT 0,(IY+#02)
JR Z,CL_LINE_3
LD A,(#5C48)
CL_LINE_3: LD (HL),A
DEC BC
LDIR
POP BC
LD C,#21
RET
; Attribute handling
CL_ATTR: LD A,H
RRCA
RRCA
RRCA
DEC A
OR #50
LD H,A
EX DE,HL
LD H,C
LD L,B
ADD HL,HL
ADD HL,HL
ADD HL,HL
ADD HL,HL
ADD HL,HL
LD B,H
LD C,L
RET
; Handle display with line number
CL_ADDR: LD A,#18
SUB B
LD D,A
RRCA
RRCA
RRCA
AND #E0
LD L,A
LD A,D
AND #18
OR #40
LD H,A
RET
; Handle COPY command
COPY: DI
LD B,#B0
LD HL,#4000
COPY_1: PUSH HL
PUSH BC
CALL COPY_LINE
POP BC
POP HL
INC H
LD A,H
AND #07
JR NZ,COPY_2
LD A,L
ADD A,#20
LD L,A
CCF
SBC A,A
AND #F8
ADD A,H
LD H,A
COPY_2: DJNZ COPY_1
JR COPY_END
; Pass printer buffer to printer
COPY_BUFF: DI
LD HL,#5B00
LD B,#08
COPY_3: PUSH BC
CALL COPY_LINE
POP BC
DJNZ COPY_3
COPY_END: LD A,#04
OUT (#FB),A
EI
CLEAR_PRB: LD HL,#5B00 ; Clear printer buffer
LD (IY+#46),L
XOR A
LD B,A
PRB_BYTES: LD (HL),A
INC HL
DJNZ PRB_BYTES
RES 1,(IY+#30)
LD C,#21
JP CL_SET
; Output 32 bytes (line) to the printer
COPY_LINE: LD A,B
CP #03
SBC A,A
AND #02
OUT (#FB),A
LD D,A
COPY_L_1: CALL BREAK_KEY
JR C,COPY_L_2
LD A,#04
OUT (#FB),A
EI
CALL CLEAR_PRB
REPORT_DC: RST #08 ; Error report
DB #0C ; BREAK - CONT repeats
COPY_L_2: IN A,(#FB)
ADD A,A
RET M
JR NC,COPY_L_1
LD C,#20
COPY_L_3: LD E,(HL)
INC HL
LD B,#08
COPY_L_4: RL D
RL E
RR D
COPY_L_5: IN A,(#FB)
RRA
JR NC,COPY_L_5
LD A,D
OUT (#FB),A
DJNZ COPY_L_4
DEC C
JR NZ,COPY_L_3
RET
; The editor routine - prepare or edit BASIC line, or handle INPUT expression
EDITOR: LD HL,(#5C3D)
PUSH HL
ED_AGAIN: LD HL,ED_ERROR
PUSH HL
LD (#5C3D),SP
ED_LOOP: CALL WAIT_KEY
PUSH AF
LD D,#00
LD E,(IY-#01)
LD HL,#00C8
CALL BEEPER
POP AF
LD HL,ED_LOOP
PUSH HL
CP #18
JR NC,ADD_CHAR
CP #07
JR C,ADD_CHAR
CP #10
JR C,ED_KEYS
LD BC,#0002
LD D,A
CP #16
JR C,ED_CONTR
INC BC
BIT 7,(IY+#37)
JP Z,ED_IGNORE
CALL WAIT_KEY
LD E,A
ED_CONTR: CALL WAIT_KEY
PUSH DE
LD HL,(#5C5B)
RES 0,(IY+#07)
CALL MAKE_ROOM
POP BC
INC HL
LD (HL),B
INC HL
LD (HL),C
JR ADD_CH_1
; Add code to current line
ADD_CHAR: RES 0,(IY+#07)
LD HL,(#5C5B)
CALL ONE_SPACE
ADD_CH_1: LD (DE),A
INC DE
LD (#5C5B),DE
RET
ED_KEYS: LD E,A
LD D,#00
LD HL,ED_KEYS_T-7
ADD HL,DE
LD E,(HL)
ADD HL,DE
PUSH HL
LD HL,(#5C5B)
RET
; Editing keys table
ED_KEYS_T: DB #09 ; ED_EDIT
DB #66 ; ED_LEFT
DB #6A ; ED_RIGHT
DB #50 ; ED_DOWN
DB #B5 ; ED_UP
DB #70 ; ED_DELETE
DB #7E ; ED_ENTER
DB #CF ; ED_SYMBOL
DB #D4 ; ED_GRAPH
; Handle EDIT key
ED_EDIT: LD HL,(#5C49)
BIT 5,(IY+#37)
JP NZ,CLEAR_SP
CALL LINE_ADDR
CALL LIN2 ; BSROM - modified BASIC program presence test
AND #C0
JP NZ,CLEAR_SP
PUSH HL
INC HL
LD C,(HL)
INC HL
LD B,(HL)
LD HL,#000A
ADD HL,BC
LD B,H
LD C,L
CALL TEST_ROOM
CALL CLEAR_SP
LD HL,(#5C51)
EX (SP),HL
PUSH HL
LD A,#FF
CALL CHAN_OPEN
POP HL
DEC HL
CALL OUT_LINE ;BSROM - cursor placement after EDIT
LD DE,#0005
LD HL,(#5C59)
ADD HL,DE
LD (#5C5B),HL
POP HL
JP CHAN_FLAG
TOERR: LD (#5C5F),HL ; BSROM - cursor jumps to error
LD (#5C5B),HL
RET
; Cursor down editing
ED_DOWN: CALL DOLE ; BSROM - free cursor moving
BIT 5,(IY+#37)
RET NZ
NOP
CALL LN_FETCH
JR ED_LIST
ED_STOP: LD (IY+#00),#10
JR ED_ENTER
; Cursor left editing
ED_LEFT: CALL ED_EDGE
JR ED_CUR
; Cursor right editing
ED_RIGHT: LD A,(HL)
CP #0D
RET Z
INC HL
ED_CUR: LD (#5C5B),HL
RET
; Handling DELETE
ED_DELETE: CALL ED_EDGE
LD BC,#0001
JP RECLAIM_2
; Ignore next two codes from KEY_INPUT routine
ED_IGNORE: CALL WAIT_KEY
CALL WAIT_KEY
ED_ENTER: POP HL ; Handle ENTER
POP HL
ED_END: POP HL
LD (#5C3D),HL
BIT 7,(IY+#00)
RET NZ
LD SP,HL
RET
; Move cursor left when editing
ED_EDGE: SCF
CALL SET_DE
SBC HL,DE
ADD HL,DE
INC HL
POP BC
RET C
PUSH BC
LD B,H
LD C,L
ED_EDGE_1: LD H,D
LD L,E
INC HL
LD A,(DE)
AND #F0
CP #10
JR NZ,ED_EDGE_2
INC HL
LD A,(DE)
SUB #17
ADC A,#00
JR NZ,ED_EDGE_2
INC HL
ED_EDGE_2: AND A
SBC HL,BC
ADD HL,BC
EX DE,HL
JR C,ED_EDGE_1
RET
; Cursor up editing
ED_UP: CALL HORE ; BSROM - free cursor moving
BIT 5,(IY+#37)
RET NZ
CALL LINE_ADDR
EX DE,HL
CALL LINE_NO
LD HL,#5C4A
CALL LN_STORE
ED_LIST: CALL AUTO_LIST
ED_LIST_1: LD A,#00
JP CHAN_OPEN
; Use of symbol and graphic codes
ED_SYMBOL: BIT 7,(IY+#37)
JR Z,ED_ENTER
ED_GRAPH: JP ADD_CHAR
; Editor error handling
ED_ERROR: BIT 4,(IY+#30)
JR Z,ED_END
LD (IY+#00),#FF
LD D,#00
LD E,(IY-#02)
LD HL,#0190 ; BSROM - higher tone of error beep, was LD HL,#1A90
CALL BEEPER
JP ED_AGAIN
; Clear workspace
CLEAR_SP: PUSH HL
CALL SET_HL
DEC HL
CALL RECLAIM_1
LD (#5C5B),HL
LD (IY+#07),#00
POP HL
RET
; Handle keyboard input
KEY_INPUT: BIT 3,(IY+#02)
CALL NZ,ED_COPY
AND A
BIT 5,(IY+#01)
RET Z
LD A,(#5C08)
RES 5,(IY+#01)
PUSH AF
BIT 5,(IY+#02)
CALL NZ,CLS_LOWER
POP AF
CP #20
JR NC,KEY_DONE2
CP #10
JR NC,KEY_CONTR
CP #06
JR NC,KEY_M_CL
LD B,A
AND #01
LD C,A
LD A,B
RRA
ADD A,#12
JR KEY_DATA
; Separate caps lock
KEY_M_CL: JR NZ,KEY_MODE
LD HL,#5C6A
LD A,#08
XOR (HL)
LD (HL),A
JR KEY_FLAG
; Mode handling
KEY_MODE: CP #0E
RET C
SUB #0D
LD HL,#5C41
CP (HL)
LD (HL),A
JR NZ,KEY_FLAG
LD (HL),#00
KEY_FLAG: SET 3,(IY+#02)
CP A
RET
; Handle colour controls
KEY_CONTR: LD B,A
AND #07
LD C,A
LD A,#10
BIT 3,B
JR NZ,KEY_DATA
INC A
KEY_DATA: LD (IY-#2D),C
LD DE,KEY_NEXT
JR KEY_CHAN
KEY_NEXT: LD A,(#5C0D)
LD DE,KEY_INPUT
KEY_CHAN: LD HL,(#5C4F)
INC HL
INC HL
LD (HL),E
INC HL
LD (HL),D
KEY_DONE2: SCF
RET
; Print lower screen workspace
ED_COPY: CALL TEMPS
RES 3,(IY+#02)
RES 5,(IY+#02)
LD HL,(#5C8A)
PUSH HL
LD HL,(#5C3D)
PUSH HL
LD HL,ED_FULL
PUSH HL
LD (#5C3D),SP
LD HL,(#5C82)
PUSH HL
SCF
CALL SET_DE
EX DE,HL
CALL OUT_LINE2
EX DE,HL
CALL OUT_CURS
LD HL,(#5C8A)
EX (SP),HL
EX DE,HL
CALL TEMPS
ED_BLANK: LD A,(#5C8B)
SUB D
JR C,ED_C_DONE
JR NZ,ED_SPACES
LD A,E
SUB (IY+#50)
JR NC,ED_C_DONE
ED_SPACES: LD A,#20
PUSH DE
CALL PRINT_OUT
POP DE
JR ED_BLANK
; Error handling
ED_FULL: LD D,#00
LD E,(IY-#02)
LD HL,#0190 ; BSROM - higher tone of error beep, was LD HL,#1A90
CALL BEEPER
LD (IY+#00),#FF
LD DE,(#5C8A)
JR ED_C_END
ED_C_DONE: POP DE
POP HL
ED_C_END: POP HL
LD (#5C3D),HL
POP BC
PUSH DE
CALL CL_SET
POP HL
LD (#5C82),HL
LD (IY+#26),#00
RET
; Ensure that the proper pointers are selected for workspace
SET_HL: LD HL,(#5C61)
DEC HL
AND A
SET_DE: LD DE,(#5C59)
BIT 5,(IY+#37)
RET Z
LD DE,(#5C61)
RET C
LD HL,(#5C63)
RET
; Remove floating point from line
REMOVE_FP: LD A,(HL)
CP #0E
LD BC,#0006
CALL Z,RECLAIM_2
LD A,(HL)
INC HL
CP #0D
JR NZ,REMOVE_FP
RET
; Handle NEW command
NEW: DI
LD A,#FF
LD DE,(#5CB2)
NEW_1: EXX
LD BC,(#5CB4)
LD DE,(#5C38)
LD HL,(#5C7B)
EXX
START_NEW: LD B,A
XOR A ; BSROM - faster RAM clear, RAM is not tested for errors
LD I,A
LD C,A
LD H,D
LD L,E
LD A,B
LD B,C
LD SP,HL
CLSUJ: PUSH BC
PUSH BC
PUSH BC
PUSH BC
PUSH BC
PUSH BC
PUSH BC
PUSH BC
LD HL,#A7FF
ADD HL,SP
JR C,CLSUJ
EX DE,HL
JR RAM_DONE1
; Modified CONTINUE command
NEW_CONT: CALL FIND_INT2
LD A,B
OR C
JP Z,CONTINUE
PUSH BC
RET
; Remains of original RAM_DONE routine
RAM_DONE1: EXX
LD (#5CB4),BC
LD (#5C38),DE
LD (#5C7B),HL
EXX
INC A ; BSROM - changed for new NEW command, was INC B
JR Z,RAM_SET
RAM_DONE2: LD (#5CB4),HL
LD DE,#3EAF
LD BC,#00A8
EX DE,HL
LDDR
EX DE,HL
INC HL
LD (#5C7B),HL
DEC HL
LD BC,#0040
LD (#5C38),BC
RAM_SET: LD (#5CB2),HL
LD HL,#3C00
LD (#5C36),HL
LD HL,(#5CB2)
LD (HL),#3E
DEC HL
LD SP,HL
DEC HL
DEC HL
LD (#5C3D),HL
IM 1
LD IY,#5C3A
EI
LD HL,#5CB6
LD (#5C4F),HL
LD DE,INIT_CHAN
LD BC,#0015
EX DE,HL
LDIR
EX DE,HL
DEC HL
LD (#5C57),HL
INC HL
LD (#5C53),HL
LD (#5C4B),HL
LD (HL),#80
INC HL
LD (#5C59),HL
WARM_ST: LD (HL),#0D
INC HL
LD (HL),#80
INC HL
LD (#5C61),HL
LD (#5C63),HL
LD (#5C65),HL
LD A,#07 ; BSROM - changed colors, blue border, black paper, white ink
LD (#5C8D),A
LD (#5C8F),A
LD (#5C48),A
LD HL,#0114 ; BSROM - REPDEL and REPPER were changed, was #0523
LD (#5C09),HL
DEC (IY-#3A)
DEC (IY-#36)
LD HL,INIT_STRM
LD DE,#5C10
LD BC,#000E
LDIR
LD (IY+#31),#02 ; BSROM - printer vars initialization removed
LD (IY+#0E),#0F
CALL HARD ; reset AY, DMA, FDC
CALL SET_MIN
LD (IY+#00),#FF
CALL INFO ; copyright message replaced with status info
CALL SA_LD_RET
JP MAIN_4
; Main execution loop
MAIN_EXEC: LD (IY+#31),#02
CALL AUTO_LIST
MAIN_1: CALL SET_MIN
MAIN_2: LD A,#00
CALL CHAN_OPEN
CALL EDITOR
CALL LINE_SCAN
BIT 7,(IY+#00)
JR NZ,MAIN_3
BIT 4,(IY+#30)
JR Z,MAIN_4
LD HL,(#5C59)
CALL REMOVE_FP
LD (IY+#00),#FF
JR MAIN_2
MAIN_3: LD HL,(#5C59)
LD (#5C5D),HL
CALL LIN3 ; BSROM - modified test of number at the begin of BASIC line
NOP
NOP
JP NC,MAIN_ADD ; BSROM - don't test zero, so line 0 can be used and/or edited
RST #18
CP #0D
JR Z,MAIN_EXEC
BIT 0,(IY+#30)
CALL NZ,CL_ALL
CALL CLS_LOWER
LD A,#19
SUB (IY+#4F)
LD (#5C8C),A
SET 7,(IY+#01)
LD (IY+#00),#FF
LD (IY+#0A),#01
CALL LINE_RUN
MAIN_4: RST #38 ; BSROM - bugfix - was HALT
RES 5,(IY+#01)
BIT 1,(IY+#30)
CALL NZ,COPY_BUFF
LD A,(#5C3A)
INC A
MAIN_G: PUSH AF
LD HL,#0000
LD (IY+#37),H
LD (IY+#26),H
LD (#5C0B),HL
LD HL,#0001
LD (#5C16),HL
CALL SET_MIN
RES 5,(IY+#37)
CALL CLS_LOWER
SET 5,(IY+#02)
POP AF
LD B,A
CP #0A
JR C,MAIN_5
ADD A,#07
MAIN_5: CALL OUT_CODE
LD A,#20
RST #10
LD A,B
LD DE,RPT_MESGS
CALL PO_MSG
XOR A
LD DE,COMMA_SP-1
CALL PO_MSG
LD BC,(#5C45)
CALL OUT_NUM_1
LD A,#3A
RST #10
LD C,(IY+#0D)
LD B,#00
CALL OUT_NUM_1
CALL CLEAR_SP
LD A,(#5C3A)
INC A
JR Z,MAIN_9
CP #09
JR Z,MAIN_6
CP #15
JR NZ,MAIN_7
MAIN_6: INC (IY+#0D)
MAIN_7: LD BC,#0003
LD DE,#5C70
LD HL,#5C44
BIT 7,(HL)
JR Z,MAIN_8
ADD HL,BC
MAIN_8: LDDR
MAIN_9: LD (IY+#0A),#FF
RES 3,(IY+#01)
JP MAIN_2
;The error mesages, with last byte inverted.
;The first #80 entry is dummy entry.
RPT_MESGS: DB #80
DC "OK"
DC "NEXT without FOR"
DC "Variable not found"
DC "Subscript wrong"
DC "Out of memory"
DC "Out of screen"
DC "Number too big"
DC "RETURN without GOSUB"
DC "End of file"
DC "STOP statement"
DC "Invalid argument"
DC "Integer out of range"
DC "Nonsense in BASIC"
DC "BREAK - CONT repeats"
DC "Out of DATA"
DC "Invalid file name"
DC "No room for line"
DC "STOP in INPUT"
DC "FOR without NEXT"
DC "Invalid I/O device"
DC "Invalid colour"
DC "BREAK into program"
DC "RAMTOP no good"
DC "Statement lost"
DC "Invalid stream"
DC "FN without DEF"
DC "Parameter error"
DC "Tape loading error"
COMMA_SP: DC ", "
; BSROM - here was the copyright message in the original ZX Spectrum ROM.
COPYRIGHT: DC "Rom 140"
DC "Prog:"
DB #16
DB #00
DB #0B
DC "Vars:"
DB #16
DB #00
DB #16
DC "Free:"
; Out of memory handling
REPORT_G: LD A,#10
LD BC,#0000
JP MAIN_G
; Handle additon of BASIC line
MAIN_ADD: LD (#5C49),BC
LD HL,(#5C5D)
EX DE,HL
LD HL,REPORT_G
PUSH HL
LD HL,(#5C61)
SCF
SBC HL,DE
PUSH HL
LD H,B
LD L,C
CALL LINE_ADDR
JR NZ,MAIN_ADD1
CALL NEXT_ONE
CALL RECLAIM_2
MAIN_ADD1: POP BC
LD A,C
DEC A
OR B
JR Z,MAIN_ADD2
PUSH BC
INC BC
INC BC
INC BC
INC BC
DEC HL
LD DE,(#5C53)
PUSH DE
CALL MAKE_ROOM
POP HL
LD (#5C53),HL
POP BC
PUSH BC
INC DE
LD HL,(#5C61)
DEC HL
DEC HL
LDDR
LD HL,(#5C49)
EX DE,HL
POP BC
LD (HL),B
DEC HL
LD (HL),C
DEC HL
LD (HL),E
DEC HL
LD (HL),D
MAIN_ADD2: POP AF
JP MAIN_EXEC
; Initial channel information
INIT_CHAN: DW PRINT_OUT
DW KEY_INPUT
DB "K"
DW PRINT_OUT
DW REPORT_J
DB "S"
DW ADD_CHAR
DW REPORT_J
DB "R"
DW PRINT_OUT
DW REPORT_J
DB "P"
DB #80 ; End marker
REPORT_J: RST #08 ; Error report
DB #12 ; Invalid I/O device
; Initial stream data
INIT_STRM: DB #01, #00 ; stream #FD offset to channel 'K'
DB #06, #00 ; stream #FE offset to channel 'S'
DB #0B, #00 ; stream #FF offset to channel 'R'
DB #01, #00 ; stream #00 offset to channel 'K'
DB #01, #00 ; stream #01 offset to channel 'K'
DB #06, #00 ; stream #02 offset to channel 'S'
DB #10, #00 ; stream #03 offset to channel 'P'
; Control for input subroutine
WAIT_KEY: BIT 5,(IY+#02)
JR NZ,WAIT_KEY1
SET 3,(IY+#02)
WAIT_KEY1: CALL INPUT_AD
RET C
JR Z,WAIT_KEY1
REPORT_8: RST #08 ; Error report
DB #07 ; End of file
INPUT_AD: EXX
PUSH HL
LD HL,(#5C51)
INC HL
INC HL
JR CALL_SUB
; Print ascii equivalent of a value 0-9
OUT_CODE: LD E,#30
ADD A,E
PRINT_A_2: EXX
PUSH HL
LD HL,(#5C51)
CALL_SUB: LD E,(HL)
INC HL
LD D,(HL)
EX DE,HL
CALL CALL_JUMP
POP HL
EXX
RET
; Open a channel 'K', 'S', 'R' or 'P'
CHAN_OPEN: ADD A,A
ADD A,#16
LD L,A
LD H,#5C
LD E,(HL)
INC HL
LD D,(HL)
LD A,D
OR E
JR NZ,CHAN_OP_1
REPORT_OA: RST #08 ; Error report
DB #17 ; Invalid stream
CHAN_OP_1: DEC DE
LD HL,(#5C4F)
ADD HL,DE
CHAN_FLAG: LD (#5C51),HL ; Set channel flags
RES 4,(IY+#30)
INC HL
INC HL
INC HL
INC HL
LD C,(HL)
LD HL,CH_CD_LU
CALL INDEXER
RET NC
LD D,#00
LD E,(HL)
ADD HL,DE
CALL_JUMP: JP (HL)
; Channel code lookup table
CH_CD_LU: DB "K", #06 ; CHAN_K
DB "S", #12 ; CHAN_S
DB "P", #1B ; CHAN_P
DB #00 ; End marker
; Channel K flag
CHAN_K: SET 0,(IY+#02)
RES 5,(IY+#01)
SET 4,(IY+#30)
JR CHAN_S_1
; Channel S flag
CHAN_S: RES 0,(IY+#02)
CHAN_S_1: RES 1,(IY+#01)
JP TEMPS
; Channel P flag
CHAN_P: SET 1,(IY+#01)
RET
; Create a single space in workspace by ADD_CHAR
ONE_SPACE: LD BC,#0001
MAKE_ROOM: PUSH HL ; Create BC spaces in various areas
CALL TEST_ROOM
POP HL
CALL POINTERS
LD HL,(#5C65)
EX DE,HL
LDDR
RET
; Adjust pointers before making or reclaiming room
POINTERS: PUSH AF
PUSH HL
LD HL,#5C4B
LD A,#0E
PTR_NEXT: LD E,(HL)
INC HL
LD D,(HL)
EX (SP),HL
AND A
SBC HL,DE
ADD HL,DE
EX (SP),HL
JR NC,PTR_DONE
PUSH DE
EX DE,HL
ADD HL,BC
EX DE,HL
LD (HL),D
DEC HL
LD (HL),E
INC HL
POP DE
PTR_DONE: INC HL
DEC A
JR NZ,PTR_NEXT
EX DE,HL
POP DE
POP AF
AND A
SBC HL,DE
LD B,H
LD C,L
INC BC
ADD HL,DE
EX DE,HL
RET
; Collect line number
LINE_ZERO: DB #00, #00 ; Dummy line number for direct commands
LINE_NO_A: EX DE,HL
LD DE,LINE_ZERO
LINE_NO: LD A,(HL)
AND #C0
JR NZ,LINE_NO_A
LD D,(HL)
INC HL
LD E,(HL)
RET
; Handle reserve room, continuation of the restart BC_SPACES
RESERVE: LD HL,(#5C63)
DEC HL
CALL MAKE_ROOM
INC HL
INC HL
POP BC
LD (#5C61),BC
POP BC
EX DE,HL
INC HL
RET
; Clear editing areas
SET_MIN: LD HL,(#5C59)
LD (HL),#0D
LD (#5C5B),HL
INC HL
LD (HL),#80
INC HL
LD (#5C61),HL
SET_WORK: LD HL,(#5C61)
LD (#5C63),HL
SET_STK: LD HL,(#5C63)
LD (#5C65),HL
PUSH HL
LD HL,#5C92
LD (#5C68),HL
POP HL
RET
; Not used code, remains of ZX80/ZX81 legacy code
REC_EDIT: LD DE,(#5C59)
JP RECLAIM_1
; Table indexing routine
INDEXER_1: INC HL
INDEXER: LD A,(HL)
AND A
RET Z
CP C
INC HL
JR NZ,INDEXER_1
SCF
RET
; Handle CLOSE# command
CLOSE: CALL STR_DATA
CALL CLOSE_2
LD BC,#0000
LD DE,#A3E2
EX DE,HL
ADD HL,DE
JR C,CLOSE_1
LD BC,INIT_STRM+14
ADD HL,BC
LD C,(HL)
INC HL
LD B,(HL)
CLOSE_1: EX DE,HL
LD (HL),C
INC HL
LD (HL),B
RET
CLOSE_2: PUSH HL
LD HL,(#5C4F)
ADD HL,BC
INC HL
INC HL
INC HL
LD C,(HL)
EX DE,HL
LD HL,CL_STR_LU
CALL INDEXER
LD C,(HL)
LD B,#00
ADD HL,BC
JP (HL)
; Close stream lookup table
CL_STR_LU: DB "K", #05
DB "S", #03
DB "P", #01
CLOSE_STR: POP HL
RET
; Stream data
STR_DATA: CALL FIND_INT1
CP #10
JR C,STR_DATA1
REPORT_OB: RST #08 ; Error report
DB #17 ; Invalid stream
STR_DATA1: ADD A,#03
RLCA
LD HL,#5C10
LD C,A
LD B,#00
ADD HL,BC
LD C,(HL)
INC HL
LD B,(HL)
DEC HL
RET
; Handle OPEN# command
OPEN: RST #28 ;FP_CALC
DB #01 ;EXCHANGE
DB #38 ;END_CALC
CALL STR_DATA
LD A,B
OR C
JR Z,OPEN_1
EX DE,HL
LD HL,(#5C4F)
ADD HL,BC
INC HL
INC HL
INC HL
LD A,(HL)
EX DE,HL
CP #4B
JR Z,OPEN_1
CP #53
JR Z,OPEN_1
CP #50
JR NZ,REPORT_OB
OPEN_1: CALL OPEN_2
LD (HL),E
INC HL
LD (HL),D
RET
OPEN_2: PUSH HL
CALL STK_FETCH
LD A,B
OR C
JR NZ,OPEN_3
REPORT_F: RST #08 ; Error report
DB #0E ; Invalid file name
OPEN_3: PUSH BC
LD A,(DE)
AND #DF
LD C,A
LD HL,OP_STR_LU
CALL INDEXER
JR NC,REPORT_F
LD C,(HL)
LD B,#00
ADD HL,BC
POP BC
JP (HL)
; Open stream lookup table
OP_STR_LU: DB "K", #06 ; OPEN_K
DB "S", #08 ; OPEN_S
DB "P", #0A ; OPEN_P
DB #00 ; End marker
; Open keyboard stream
OPEN_K: LD E,#01
JR OPEN_END
; Open Screen stream
OPEN_S: LD E,#06
JR OPEN_END
; Open printer stream
OPEN_P: LD E,#10
OPEN_END: DEC BC
LD A,B
OR C
JR NZ,REPORT_F
LD D,A
POP HL
RET
; Handle CAT, ERASE, FORMAT and MOVE commands
CAT_ETC: JR REPORT_OB
; Automatic listing in the upper screen
AUTO_LIST: LD (#5C3F),SP
LD (IY+#02),#10
CALL CL_ALL
SET 0,(IY+#02)
LD B,(IY+#31)
CALL CL_LINE
RES 0,(IY+#02)
SET 0,(IY+#30)
LD HL,(#5C49)
LD DE,(#5C6C)
AND A
SBC HL,DE
ADD HL,DE
JR C,AUTO_L_2
PUSH DE
CALL LINE_ADDR
LD DE,#02C0
EX DE,HL
SBC HL,DE
EX (SP),HL
CALL LINE_ADDR
POP BC
AUTO_L_1: PUSH BC
CALL NEXT_ONE
POP BC
ADD HL,BC
JR C,AUTO_L_3
EX DE,HL
LD D,(HL)
INC HL
LD E,(HL)
DEC HL
LD (#5C6C),DE
JR AUTO_L_1
AUTO_L_2: LD (#5C6C),HL
AUTO_L_3: LD HL,(#5C6C)
CALL LINE_ADDR
JR Z,AUTO_L_4
EX DE,HL
AUTO_L_4: CALL LIST_ALL
RES 4,(IY+#02)
RET
; Handle LLIST command
LLIST: LD A,#03
JR LIST_1
; Handle LIST command
LIST: LD A,#02
LIST_1: LD (IY+#02),#00
CALL SYNTAX_Z
CALL NZ,CHAN_OPEN
RST #18
CALL STR_ALTER
JR C,LIST_4
RST #18
CP #3B
JR Z,LIST_2
CP #2C
JR NZ,LIST_3
LIST_2: RST #20
CALL EXPT_1NUM
JR LIST_5
LIST_3: CALL USE_ZERO
JR LIST_5
LIST_4: CALL FETCH_NUM
LIST_5: CALL CHECK_END
CALL FIND_INT2
LD A,B
AND #3F
LD H,A
LD L,C
LD (#5C49),HL
CALL LINE_ADDR
LIST_ALL: LD E,#01
LIST_ALL_2: CALL OUT_LINE
RST #10
BIT 4,(IY+#02)
JR Z,LIST_ALL_2
LD A,(#5C6B)
SUB (IY+#4F)
JR NZ,LIST_ALL_2
XOR E
RET Z
PUSH HL
PUSH DE
LD HL,#5C6C
CALL LN_FETCH
POP DE
POP HL
JR LIST_ALL_2
; Print a whole BASIC line
OUT_LINE: LD BC,(#5C49)
CALL CP_LINES
LD D,#2A ; BSROM - line cursor is "*" instead of ">"
JR Z,OUT_LINE1
LD DE,#2000 ; BSROM - " " instead of suppressing line cursor
RL E
OUT_LINE1: LD (IY+#2D),E
LD A,(HL)
CP #40
POP BC
RET NC
PUSH BC
CALL LIN4 ; BSROM - no cursor
INC HL
INC HL
INC HL
XOR A
XOR D
JR Z,OUT_LINE1A
RST #10
OUT_LINE1A: NOP ; remains of old code are replaced with NOPs
NOP
NOP
NOP
OUT_LINE2: SET 0,(IY+#01)
OUT_LINE3: PUSH DE
EX DE,HL
RES 2,(IY+#30)
LD HL,#5C3B
RES 2,(HL)
BIT 5,(IY+#37)
JR Z,OUT_LINE4
SET 2,(HL)
OUT_LINE4: LD HL,(#5C5F)
AND A
SBC HL,DE
JR NZ,OUT_LINE5
LD A,#3F
CALL OUT_FLASH
OUT_LINE5: CALL OUT_CURS
EX DE,HL
LD A,(HL)
CALL NUMBER
INC HL
CP #0D
JR Z,OUT_LINE6
EX DE,HL
CALL OUT_CHAR
JR OUT_LINE4
OUT_LINE6: POP DE
RET
; Check for a number marker
NUMBER: CP #0E
RET NZ
INC HL
INC HL
INC HL
INC HL
INC HL
INC HL
LD A,(HL)
RET
; Print a flashing character
OUT_FLASH: EXX
LD HL,(#5C8F)
PUSH HL
RES 7,H
SET 7,L
LD (#5C8F),HL
LD HL,#5C91
LD D,(HL)
PUSH DE
LD (HL),#00
CALL PRINT_OUT
POP HL
LD (IY+#57),H
POP HL
LD (#5C8F),HL
EXX
RET
; Print the cursor
OUT_CURS: LD HL,(#5C5B)
AND A
SBC HL,DE
RET NZ
LD A,(#5C41)
RLC A
JR Z,OUT_C_1
ADD A,#43
JR OUT_C_2
OUT_C_1: LD HL,#5C3B
RES 3,(HL)
LD A,#4B
BIT 2,(HL)
JR Z,OUT_C_2
SET 3,(HL)
INC A
BIT 3,(IY+#30)
JR Z,OUT_C_2
LD A,#43
OUT_C_2: PUSH DE
CALL OUT_FLASH
POP DE
RET
; Get line number of the next line
LN_FETCH: LD E,(HL)
INC HL
LD D,(HL)
PUSH HL
EX DE,HL
INC HL
CALL LINE_ADDR
CALL LINE_NO
POP HL
LN_STORE: BIT 5,(IY+#37)
RET NZ
LD (HL),D
DEC HL
LD (HL),E
RET
; Outputting numbers at start of BASIC line
OUT_SP_2: LD A,E
AND A
RET M
JR OUT_CHAR
OUT_SP_NO: XOR A
OUT_SP_1: ADD HL,BC
INC A
JR C,OUT_SP_1
SBC HL,BC
DEC A
JR Z,OUT_SP_2
JP OUT_CODE
; Outputting characters in a BASIC line
OUT_CHAR: CALL NUMERIC
JR NC,OUT_CH_3
CP #21
JR C,OUT_CH_3
RES 2,(IY+#01)
CP #CB
JR Z,OUT_CH_3
CP #3A
JR NZ,OUT_CH_1
BIT 5,(IY+#37)
JR NZ,OUT_CH_2
BIT 2,(IY+#30)
JR Z,OUT_CH_3
JR OUT_CH_2
OUT_CH_1: CP #22
JR NZ,OUT_CH_2
PUSH AF
LD A,(#5C6A)
XOR #04
LD (#5C6A),A
POP AF
OUT_CH_2: SET 2,(IY+#01)
OUT_CH_3: RST #10
RET
; Get starting address of line (or line after)
LINE_ADDR: PUSH HL
LD HL,(#5C53)
LD D,H
LD E,L
LINE_AD_1: POP BC
CALL LIN1 ; BSROM - modified line number test
RET NC
PUSH BC
CALL NEXT_ONE
EX DE,HL
JR LINE_AD_1
; Compare line numbers
CP_LINES: LD A,(HL)
CP B
RET NZ
INC HL
LD A,(HL)
DEC HL
CP C
RET
; Find each statement
INC HL ; 3x INC HL not used in this ROM
INC HL
INC HL
EACH_STMT: LD (#5C5D),HL
LD C,#00
EACH_S_1: DEC D
RET Z
RST #20
CP E
JR NZ,EACH_S_3
AND A
RET
EACH_S_2: INC HL
LD A,(HL)
EACH_S_3: CALL NUMBER
LD (#5C5D),HL
CP #22
JR NZ,EACH_S_4
DEC C
EACH_S_4: CP #3A
JR Z,EACH_S_5
CP #CB
JR NZ,EACH_S_6
EACH_S_5: BIT 0,C
JR Z,EACH_S_1
EACH_S_6: CP #0D
JR NZ,EACH_S_2
DEC D
SCF
RET
; Find the address of the next line in the program area,
; or the next variable in the variables area
NEXT_ONE: PUSH HL
LD A,(HL)
CP #40
JR C,NEXT_O_3
BIT 5,A
JR Z,NEXT_O_4
ADD A,A
JP M,NEXT_O_1
CCF
NEXT_O_1: LD BC,#0005
JR NC,NEXT_O_2
LD C,#12
NEXT_O_2: RLA
INC HL
LD A,(HL)
JR NC,NEXT_O_2
JR NEXT_O_5
NEXT_O_3: INC HL
NEXT_O_4: INC HL
LD C,(HL)
INC HL
LD B,(HL)
INC HL
NEXT_O_5: ADD HL,BC
POP DE
DIFFER: AND A
SBC HL,DE
LD B,H
LD C,L
ADD HL,DE
EX DE,HL
RET
; Handle reclaiming space
RECLAIM_1: CALL DIFFER
RECLAIM_2: PUSH BC
LD A,B
CPL
LD B,A
LD A,C
CPL
LD C,A
INC BC
CALL POINTERS
EX DE,HL
POP HL
ADD HL,DE
PUSH DE
LDIR
POP HL
RET
; Read line number of line editing area
E_LINE_NO: LD HL,(#5C59)
DEC HL
LD (#5C5D),HL
RST #20
LD HL,#5C92
LD (#5C65),HL
CALL INT_TO_FP
CALL FP_TO_BC
JR C,E_L_1
LD HL,#C000 ; BSROM - line number can be 0..16383 now, was LD HL,$D8F0 (max 9999 lines)
ADD HL,BC
E_L_1: JP C,REPORT_C
JP SET_STK
; Report and line number outputting
OUT_NUM_1: PUSH DE
PUSH HL
XOR A
BIT 7,B
JR NZ,OUT_NUM_4
LD H,B
LD E,#FF ;BSROM - lines 0..16383
JP NUMCOM
OUT_NUM_2: PUSH DE
LD D,(HL)
INC HL
LD E,(HL)
PUSH HL
EX DE,HL
LD E,#20
OUT_NUM_3: LD BC,#FC18
CALL OUT_SP_NO
LD BC,#FF9C
CALL OUT_SP_NO
LD C,#F6
CALL OUT_SP_NO
LD A,L
OUT_NUM_4: CALL OUT_CODE
POP HL
POP DE
RET
; The offset table for command interpretation
OFFST_TBL: DB #B1 ; P_DEF_FN
DB #CB ; P_CAT
DB #BC ; P_FORMAT
DB #BF ; P_MOVE
DB #C4 ; P_ERASE
DB #AF ; P_OPEN
DB #B4 ; P_CLOSE
DB #93 ; P_MERGE
DB #91 ; P_VERIFY
DB #92 ; P_BEEP
DB #95 ; P_CIRCLE
DB #98 ; P_INK
DB #98 ; P_PAPER
DB #98 ; P_FLASH
DB #98 ; P_BRIGHT
DB #98 ; P_INVERSE
DB #98 ; P_OVER
DB #98 ; P_OUT
DB #7F ; P_LPRINT
DB #81 ; P_LLIST
DB #2E ; P_STOP
DB #6C ; P_READ
DB #6E ; P_DATA
DB #70 ; P_RESTORE
DB #48 ; P_NEW
DB #94 ; P_BORDER
DB #56 ; P_CONT
DB #3F ; P_DIM
DB #41 ; P_REM
DB #2B ; P_FOR
DB #17 ; P_GO_TO
DB #1F ; P_GO_SUB
DB #37 ; P_INPUT
DB #77 ; P_LOAD
DB #44 ; P_LIST
DB #0F ; P_LET
DB #59 ; P_PAUSE
DB #2B ; P_NEXT
DB #43 ; P_POKE
DB #2D ; P_PRINT
DB #51 ; P_PLOT
DB #3A ; P_RUN
DB #6D ; P_SAVE
DB #42 ; P_RANDOM
DB #0D ; P_IF
DB #49 ; P_CLS
DB #5C ; P_DRAW
DB #44 ; P_CLEAR
DB #15 ; P_RETURN
DB #5D ; P_COPY
; The parameter table. List of parameters for commands.
P_LET: DB #01
DB "="
DB #02
P_GO_TO: DB #03 ; BSROM - enhanced GOTO command, parameter is optional
DW GO_TO
DB #00
P_IF: DB #06
DB #CB
DB #05
DW IF_CMD
P_GO_SUB: DB #03 ; BSROM - enhanced GOSUB command, parameter is optional
DW GO_SUB
DB #00
P_STOP: DB #00
DW STOP
P_RETURN: DB #00
DW RETURN
P_FOR: DB #04
DB "="
DB #06
DB #CC
DB #06
DB #05
DW FOR
P_NEXT: DB #04
DB #00
DW NEXT
P_PRINT: DB #05
DW PRINT
P_INPUT: DB #05
DW INPUT
P_DIM: DB #05
DW DIM
P_REM: DB #05
DW REM
P_NEW: DB #00
DW NEW
P_RUN: DB #03
DW RUN
P_LIST: DB #05
DW LIST
P_POKE: DB #06 ; BSROM - enhanced POKE comand, added more items
DB #05
DW NEW_POKE
P_RANDOM: DB #03
DW RANDOMIZE
P_CONT: DB #03 ; BSROM - enhanced CONTINUE command, added numeric parameter
DW NEW_CONT
P_CLEAR: DB #03
DW CLEAR
P_CLS: DB #03 ; BSROM - enhanced CLS command, added numeric parameter
DW NEW_CLS
P_PLOT: DB #09
DB #00
DW PLOT
P_PAUSE: DB #03 ; BSROM - enhanced PAUSE command, parameter is optional
DW PAUSE
DB #00
P_READ: DB #05
DW READ
P_DATA: DB #05
DW DATA
P_RESTORE: DB #03
DW RESTORE
P_DRAW: DB #09
DB #05
DW DRAW
P_COPY: DB #00
DW COPY
P_LPRINT: DB #05
DW LPRINT
P_LLIST: DB #05
DW LLIST
P_SAVE: DB #0B
P_LOAD: DB #0B
P_VERIFY: DB #0B
P_MERGE: DB #0B
P_BEEP: DB #08
DB #00
DW BEEP
P_CIRCLE: DB #09
DB #05
DW CIRCLE
P_INK: DB #07
P_PAPER: DB #07
P_FLASH: DB #07
P_BRIGHT: DB #07
P_INVERSE: DB #07
P_OVER: DB #07
P_OUT: DB #08
DB #00
DW OUT_CMD
P_BORDER: DB #03 ; BSROM - enhanced BORDER command, parameter s optional
DW BORDER
DB #00
P_DEF_FN: DB #05
DW DEF_FN
P_OPEN: DB #06
DB ","
DB #0A
DB #00
DW OPEN
P_CLOSE: DB #06
DB #00
DW CLOSE
P_FORMAT: DB #0A
DB #00
DW CAT_ETC
P_MOVE: DB #0A
DB ","
DB #0A
DB #00
DW CAT_ETC
P_ERASE: DB #0A
DB #00
DW CAT_ETC
P_CAT: DB #00
DW CAT_ETC
; Main parser of BASIC interpreter
LINE_SCAN: RES 7,(IY+#01)
CALL E_LINE_NO
XOR A
LD (#5C47),A
DEC A
LD (#5C3A),A
JR STMT_L_1
; Statement loop
STMT_LOOP: RST #20
STMT_L_1: CALL SET_WORK
INC (IY+#0D)
JP M,REPORT_C
RST #18
LD B,#00
CP #0D
JR Z,LINE_END
CP #3A
JR Z,STMT_LOOP
LD HL,STMT_RET
PUSH HL
CP #CE ;BSROM - automatic print
JP C,COMM
SUB #CE
LD C,A
RST #20
LD HL,OFFST_TBL
ADD HL,BC
LD C,(HL)
ADD HL,BC
JR GET_PARAM
; The main scanning loop
SCAN_LOOP: LD HL,(#5C74)
GET_PARAM: LD A,(HL)
INC HL
LD (#5C74),HL
LD BC,SCAN_LOOP
PUSH BC
LD C,A
CP #20
JR NC,SEPARATOR
LD HL,CLASS_TBL
LD B,#00
ADD HL,BC
LD C,(HL)
ADD HL,BC
PUSH HL
RST #18
DEC B
RET
; Verify that the mandatory separator is present in correct location
SEPARATOR: RST #18
CP C
JP NZ,REPORT_C
RST #20
RET
; Handle BREAK, return, and direct commands
STMT_RET: CALL BREAK_KEY
JR C,STMT_R_1
REPORT_L: RST #08 ; Error report
DB #14 ; BREAK into program
STMT_R_1: BIT 7,(IY+#0A)
JR NZ,STMT_NEXT
LD HL,(#5C42)
BIT 7,H
JR Z,LINE_NEW
LINE_RUN: LD HL,#FFFE
LD (#5C45),HL
LD HL,(#5C61)
DEC HL
LD DE,(#5C59)
DEC DE
LD A,(#5C44)
JR NEXT_LINE
; Find start address of a new line
LINE_NEW: CALL LINE_ADDR
LD A,(#5C44)
JR Z,LINE_USE
AND A
JR NZ,REPORT_N
LD B,A
LD A,(HL)
AND #C0
LD A,B
JR Z,LINE_USE
REPORT_0: RST #08 ; Error report
DB #FF ; OK
; REM command
REM: POP BC
; End of line test
LINE_END: CALL SYNTAX_Z
RET Z
LD HL,(#5C55)
LD A,#C0
AND (HL)
RET NZ
XOR A
LINE_USE: CP #01 ; General line checking
ADC A,#00
LD D,(HL)
INC HL
LD E,(HL)
LD (#5C45),DE
INC HL
LD E,(HL)
INC HL
LD D,(HL)
EX DE,HL
ADD HL,DE
INC HL
NEXT_LINE: LD (#5C55),HL
EX DE,HL
LD (#5C5D),HL
LD D,A
LD E,#00
LD (IY+#0A),#FF
DEC D
LD (IY+#0D),D
JP Z,STMT_LOOP
INC D
CALL EACH_STMT
JR Z,STMT_NEXT
REPORT_N: RST #08 ; Error report
DB #16 ; Statement lost
; End of statements
CHECK_END: CALL SYNTAX_Z
RET NZ
POP BC
POP BC
STMT_NEXT: RST #18 ; Go to next statement
CP #0D
JR Z,LINE_END
CP #3A
JP Z,STMT_LOOP
JP REPORT_C
; Command class table
CLASS_TBL: DB #0F ; CLASS_00
DB #1D ; CLASS_01
DB #4B ; CLASS_02
DB #09 ; CLASS_03
DB #67 ; CLASS_04
DB #0B ; CLASS_05
DB #7B ; CLASS_06
DB #8E ; CLASS_07
DB #71 ; CLASS_08
DB #B4 ; CLASS_09
DB #81 ; CLASS_0A
DB #CF ; CLASS_0B
; Command classes 00 - no operand, 03 - optional operand, 05 - variable syntax checked by routine
CLASS_03: CALL FETCH_NUM
CLASS_00: CP A
CLASS_05: POP BC
CALL Z,CHECK_END
EX DE,HL
LD HL,(#5C74)
LD C,(HL)
INC HL
LD B,(HL)
EX DE,HL
PUSH BC
RET
; Command classes
; 01 - variable is required
; 02 - expression is required
; 04 - single character variable is required
CLASS_01: CALL LOOK_VARS
VAR_A_1: LD (IY+#37),#00
JR NC,VAR_A_2
SET 1,(IY+#37)
JR NZ,VAR_A_3
REPORT_2: RST #08 ; Error report
DB #01 ; Variable not found;
VAR_A_2: CALL Z,STK_VAR
BIT 6,(IY+#01)
JR NZ,VAR_A_3
XOR A
CALL SYNTAX_Z
CALL NZ,STK_FETCH
LD HL,#5C71
OR (HL)
LD (HL),A
EX DE,HL
VAR_A_3: LD (#5C72),BC
LD (#5C4D),HL
RET
CLASS_02: POP BC
CALL VAL_FET_1
CALL CHECK_END
RET
; Fetch a value
VAL_FET_1: LD A,(#5C3B)
VAL_FET_2: PUSH AF
CALL SCANNING
POP AF
LD D,(IY+#01)
XOR D
AND #40
JR NZ,REPORT_C
BIT 7,D
JP NZ,LET
RET
CLASS_04: CALL LOOK_VARS
PUSH AF
LD A,C
OR #9F
INC A
JR NZ,REPORT_C
POP AF
JR VAR_A_1
; Command classes
; 06 - numeric expression is expected
; 08 - two numeric expressions separated by comma are expected
; 0A - string expression is expected
NEXT_2NUM: RST #20
EXPT_2NUM: CALL EXPT_1NUM ; CLASS_08
CP #2C
JR NZ,REPORT_C
RST #20
EXPT_1NUM: CALL SCANNING ; CLASS_06
BIT 6,(IY+#01)
RET NZ
REPORT_C: RST #08 ; Error report
DB #0B ; Nonsense in BASIC
EXPT_EXP: CALL SCANNING ; CLASS_0A
BIT 6,(IY+#01)
RET Z
JR REPORT_C
; Command class 07 - set permanent colors
CLASS_07: BIT 7,(IY+#01)
RES 0,(IY+#02)
CALL NZ,TEMPS
POP AF
LD A,(#5C74)
SUB #13
CALL CO_TEMP_4
CALL CHECK_END
LD HL,(#5C8F)
LD (#5C8D),HL
LD HL,#5C91
LD A,(HL)
RLCA
XOR (HL)
AND #AA
XOR (HL)
LD (HL),A
RET
; Command class 09 - two coordinates, could be preceded by embedded color commands
CLASS_09: CALL SYNTAX_Z
JR Z,CL_09_1
RES 0,(IY+#02)
CALL TEMPS
LD HL,#5C90
LD A,(HL)
OR #F8
LD (HL),A
RES 6,(IY+#57)
RST #18
CL_09_1: CALL CO_TEMP_2
JR EXPT_2NUM
; Command class 09 - four commands handling
JP SAVE_ETC
; Fetch a number
FETCH_NUM: CP #0D
JR Z,USE_ZERO
CP #3A
JR NZ,EXPT_1NUM
USE_ZERO: CALL SYNTAX_Z ; Place 0 on the calculator stack
RET Z
RST #28 ;FP_CALC
DB #A0 ;STK_ZERO
DB #38 ;END_CALC
RET
; Handle STOP command
STOP: RST #08 ; Error report
DB #08 ; STOP statement
; Handle IF command
IF_CMD: POP BC
CALL SYNTAX_Z
JR Z,IF_1
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #38 ;END_CALC
EX DE,HL
CALL TEST_ZERO
JP C,LINE_END
IF_1: JP STMT_L_1
; Handle FOR command
FOR: CP #CD
JR NZ,F_USE_1
RST #20
CALL EXPT_1NUM
CALL CHECK_END
JR F_REORDER
F_USE_1: CALL CHECK_END
RST #28 ;FP_CALC
DB #A1 ;STK_ONE
DB #38 ;END_CALC
F_REORDER: RST #28 ;FP_CALC
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #01 ;EXCHANGE
DB #E0 ;GET_MEM_0
DB #01 ;EXCHANGE
DB #38 ;END_CALC
CALL LET
LD (#5C68),HL
DEC HL
LD A,(HL)
SET 7,(HL)
LD BC,#0006
ADD HL,BC
RLCA
JR C,F_L_S
LD C,#0D
CALL MAKE_ROOM
INC HL
F_L_S: PUSH HL
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #02 ;DELETE
DB #38 ;END_CALC
POP HL
EX DE,HL
LD C,#0A
LDIR
LD HL,(#5C45)
EX DE,HL
LD (HL),E
INC HL
LD (HL),D
LD D,(IY+#0D)
INC D
INC HL
LD (HL),D
CALL NEXT_LOOP
RET NC
LD B,(IY+#38)
LD HL,(#5C45)
LD (#5C42),HL
LD A,(#5C47)
NEG
LD D,A
LD HL,(#5C5D)
LD E,#F3
F_LOOP: PUSH BC
LD BC,(#5C55)
CALL LOOK_PROG
LD (#5C55),BC
POP BC
JR C,REPORT_I
RST #20
OR #20
CP B
JR Z,F_FOUND
RST #20
JR F_LOOP
F_FOUND: RST #20
LD A,#01
SUB D
LD (#5C44),A
RET
REPORT_I: RST #08 ; Error report
DB #11 ; FOR without NEXT
; Search the program area for DATA, DEF FN or NEXT keywords
LOOK_PROG: LD A,(HL)
CP #3A
JR Z,LOOK_P_2
LOOK_P_1: INC HL
LD A,(HL)
AND #C0
SCF
RET NZ
LD B,(HL)
INC HL
LD C,(HL)
LD (#5C42),BC
INC HL
LD C,(HL)
INC HL
LD B,(HL)
PUSH HL
ADD HL,BC
LD B,H
LD C,L
POP HL
LD D,#00
LOOK_P_2: PUSH BC
CALL EACH_STMT
POP BC
RET NC
JR LOOK_P_1
; Handle NEXT command
NEXT: BIT 1,(IY+#37)
JP NZ,REPORT_2
LD HL,(#5C4D)
BIT 7,(HL)
JR Z,REPORT_1
INC HL
LD (#5C68),HL
RST #28 ;FP_CALC
DB #E0 ;GET_MEM_0
DB #E2 ;GET_MEM_2
DB #0F ;ADDITION
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #38 ;END_CALC
CALL NEXT_LOOP
RET C
LD HL,(#5C68)
LD DE,#000F
ADD HL,DE
LD E,(HL)
INC HL
LD D,(HL)
INC HL
LD H,(HL)
EX DE,HL
JP GO_TO_2
REPORT_1: RST #08 ; Error report
DB #00 ; NEXT withou FOR
; Test iterations for FOR command
NEXT_LOOP: RST #28 ;FP_CALC
DB #E1 ;GET_MEM_1
DB #E0 ;GET_MEM_0
DB #E2 ;GET_MEM_2
DB #36 ;LESS_0
DB #00 ;JUMP_TRUE
DB #02 ;NEXT_1 if step negative
DB #01 ;EXCHANGE
NEXT_1: DB #03 ;SUBTRACT
DB #37 ;GREATER_0
DB #00 ;JUMP_TRUE
DB #04 ;NEXT_2 if finished
DB #38 ;END_CALC
AND A
RET
NEXT_2: DB #38 ;END_CALC
SCF
RET
; Handle READ command
READ_3: RST #20
READ: CALL CLASS_01
CALL SYNTAX_Z
JR Z,READ_2
RST #18
LD (#5C5F),HL
LD HL,(#5C57)
LD A,(HL)
CP #2C
JR Z,READ_1
LD E,#E4
CALL LOOK_PROG
JR NC,READ_1
REPORT_E: RST #08 ; Error report
DB #0D ; Out of data
READ_1: CALL TEMP_PTR1
CALL VAL_FET_1
RST #18
LD (#5C57),HL
LD HL,(#5C5F)
LD (IY+#26),#00
CALL TEMP_PTR2
READ_2: RST #18
CP #2C
JR Z,READ_3
CALL CHECK_END
RET
; Handle DATA command
DATA: CALL SYNTAX_Z
JR NZ,DATA_2
DATA_1: CALL SCANNING
CP #2C
CALL NZ,CHECK_END
RST #20
JR DATA_1
DATA_2: LD A,#E4
PASS_BY: LD B,A
CPDR
LD DE,#0200
JP EACH_STMT
; Handle RESTORE command
RESTORE: CALL FIND_INT2
REST_RUN: LD H,B
LD L,C
CALL LINE_ADDR
DEC HL
LD (#5C57),HL
RET
; Handle RANDOMIZE command
RANDOMIZE: CALL FIND_INT2
LD A,B
OR C
JR NZ,RAND_1
LD BC,(#5C78)
RAND_1: LD (#5C76),BC
RET
; Handle CONTINUE command
CONTINUE: LD HL,(#5C6E)
LD D,(IY+#36)
JR GO_TO_2
; Handle GOTO command
GO_TO: CALL FIND_INT2
LD H,B
LD L,C
LD D,#00
LD A,H
CP #F0
JR NC,REPORT_BB
GO_TO_2: LD (#5C42),HL
LD (IY+#0A),D
RET
; Handle OUT command
OUT_CMD: CALL TWO_PARAM
OUT (C),A
RET
; BSROM - fix for rewriting first bytes of ROM
; was POKE command handling here originally
NO_RW_AT0: LD DE,(#5C65)
RET
; BSROM - extended command parameters
TWO_PARAM: CALL FP_TO_A
PUSH AF
CALL FIND_INT2
POP AF
ROZPAR: JR C,REPORT_BB
JR Z,ROZPAR_1
NEG
ROZPAR_1: RET
; Find integers
FIND_INT1: CALL FP_TO_A
JR ROZPAR
FIND_INT2: CALL FP_TO_BC
JR C,REPORT_BB
RET Z
REPORT_BB: RST #08 ; Error report
DB #0A ; Integer out of range
; Handle RUN command
RUN: CALL GO_TO
LD BC,#0000
CALL REST_RUN
JR CLEAR_RUN
; Handle CLEAR command
CLEAR: CALL FIND_INT2
CLEAR_RUN: LD A,B
OR C
JR NZ,CLEAR_1
LD BC,(#5CB2)
CLEAR_1: PUSH BC
LD DE,(#5C4B)
LD HL,(#5C59)
DEC HL
CALL RECLAIM_1
CALL CLS
LD HL,(#5C65)
LD DE,#0032
ADD HL,DE
POP DE
SBC HL,DE
JR NC,REPORT_M
LD HL,(#5CB4)
AND A
SBC HL,DE
JR NC,CLEAR_2
REPORT_M: RST #08 ; Error report
DB #15 ; RAMTOP no good
CLEAR_2: EX DE,HL
LD (#5CB2),HL
POP DE
POP BC
LD (HL),#3E
DEC HL
LD SP,HL
PUSH BC
LD (#5C3D),SP
EX DE,HL
JP (HL)
; Handle GO SUB command
GO_SUB: POP DE
LD H,(IY+#0D)
INC H
EX (SP),HL
INC SP
LD BC,(#5C45)
PUSH BC
PUSH HL
LD (#5C3D),SP
PUSH DE
CALL GO_TO
LD BC,#0014
TEST_ROOM: LD HL,(#5C65) ; Check available memory
ADD HL,BC
JR C,REPORT_4
EX DE,HL
LD HL,#0050
ADD HL,DE
JR C,REPORT_4
SBC HL,SP
RET C
REPORT_4: LD L,#03
JP ERROR_3
; Get free memory. Not used in ROM, but can be used by user
FREE_MEM: LD BC,#0000
CALL TEST_ROOM
LD B,H
LD C,L
RET
; Handle RETURN command
RETURN: POP BC
POP HL
POP DE
LD A,D
CP #3E
JR Z,REPORT_7
DEC SP
EX (SP),HL
EX DE,HL
LD (#5C3D),SP
PUSH BC
JP GO_TO_2
REPORT_7: PUSH DE
PUSH HL
RST #08 ; Error report
DB #06 ; RETURN without GOSUB
; Handle PAUSE command
PAUSE: CALL FIND_INT2
PAUSE_1: HALT
DEC BC
LD A,B
OR C
JR Z,PAUSE_END
LD A,B
AND C
INC A
JR NZ,PAUSE_2
INC BC
PAUSE_2: BIT 5,(IY+#01)
JR Z,PAUSE_1
PAUSE_END: RES 5,(IY+#01)
RET
; Check for BREAK key
BREAK_KEY: LD A,#7F
IN A,(#FE)
RRA
RET C
LD A,#FE
IN A,(#FE)
RRA
RET
; Handle DEF FN command
DEF_FN: CALL SYNTAX_Z
JR Z,DEF_FN_1
LD A,#CE
JP PASS_BY
DEF_FN_1: SET 6,(IY+#01)
CALL ALPHA
JR NC,DEF_FN_4
RST #20
CP #24
JR NZ,DEF_FN_2
RES 6,(IY+#01)
RST #20
DEF_FN_2: CP #28
JR NZ,DEF_FN_7
RST #20
CP #29
JR Z,DEF_FN_6
DEF_FN_3: CALL ALPHA
DEF_FN_4: JP NC,REPORT_C
EX DE,HL
RST #20
CP #24
JR NZ,DEF_FN_5
EX DE,HL
RST #20
DEF_FN_5: EX DE,HL
LD BC,#0006
CALL MAKE_ROOM
INC HL
INC HL
LD (HL),#0E
CP #2C
JR NZ,DEF_FN_6
RST #20
JR DEF_FN_3
DEF_FN_6: CP #29
JR NZ,DEF_FN_7
RST #20
CP #3D
JR NZ,DEF_FN_7
RST #20
LD A,(#5C3B)
PUSH AF
CALL SCANNING
POP AF
XOR (IY+#01)
AND #40
DEF_FN_7: JP NZ,REPORT_C
CALL CHECK_END
UNSTACK_Z: CALL SYNTAX_Z
POP HL
RET Z
JP (HL)
; Handle LPRINT command
LPRINT: LD A,#03
JR PRINT_1
; Handle PRINT command
PRINT: LD A,#02
PRINT_1: CALL SYNTAX_Z
CALL NZ,CHAN_OPEN
CALL TEMPS
CALL PRINT_2
CALL CHECK_END
RET
PRINT_2: RST #18
CALL PR_END_Z
JR Z,PRINT_4
PRINT_3: CALL PR_POSN_1
JR Z,PRINT_3
CALL PR_ITEM_1
CALL PR_POSN_1
JR Z,PRINT_3
PRINT_4: CP #29
RET Z
PRINT_CR: CALL UNSTACK_Z
PRINT_5: LD A,#0D
RST #10
RET
; Print items
PR_ITEM_1: RST #18
CP #AC
JR NZ,PR_ITEM_2
CALL NEXT_2NUM
CALL UNSTACK_Z
CALL STK_TO_BC
LD A,#16
JR PR_AT_TAB
PR_ITEM_2: CP #AD
JR NZ,PR_ITEM_3
RST #20
CALL EXPT_1NUM
CALL UNSTACK_Z
CALL FIND_INT2
LD A,#17
PR_AT_TAB: RST #10
LD A,C
RST #10
LD A,B
RST #10
RET
PR_ITEM_3: CALL CO_TEMP_3
RET NC
CALL STR_ALTER
RET NC
CALL SCANNING
CALL UNSTACK_Z
BIT 6,(IY+#01)
CALL Z,STK_FETCH
JP NZ,PRINT_FP
PR_STRING: LD A,B
OR C
DEC BC
RET Z
LD A,(DE)
INC DE
RST #10
JR PR_STRING
; End of printing
PR_END_Z: CP #29 ; ')'
RET Z
PR_ST_END: CP #0D ; carriage return
RET Z
CP #3A ; ':'
RET
; Consider print position by ';' or ',' or '''
PR_POSN_1: RST #18
CP #3B
JR Z,PR_POSN_3
CP #2C
JR NZ,PR_POSN_2
CALL SYNTAX_Z
JR Z,PR_POSN_3
LD A,#06
RST #10
JR PR_POSN_3
PR_POSN_2: CP #27
RET NZ
CALL PRINT_CR
PR_POSN_3: RST #20
CALL PR_END_Z
JR NZ,PR_POSN_4
POP BC
PR_POSN_4: CP A
RET
; Alter stream
STR_ALTER: CP #23
SCF
RET NZ
RST #20
CALL EXPT_1NUM
AND A
CALL UNSTACK_Z
CALL FIND_INT1
CP #10
JP NC,REPORT_OA
CALL CHAN_OPEN
AND A
RET
; Handle INPUT command
INPUT: CALL SYNTAX_Z
JR Z,INPUT_1
LD A,#01
CALL CHAN_OPEN
CALL CLS_LOWER
INPUT_1: LD (IY+#02),#01
CALL IN_ITEM_1
CALL CHECK_END
LD BC,(#5C88)
LD A,(#5C6B)
CP B
JR C,INPUT_2
LD C,#21
LD B,A
INPUT_2: LD (#5C88),BC
LD A,#19
SUB B
LD (#5C8C),A
RES 0,(IY+#02)
CALL CL_SET
JP CLS_LOWER
; Handle input items from the current input channel
IN_ITEM_1: CALL PR_POSN_1
JR Z,IN_ITEM_1
CP #28
JR NZ,IN_ITEM_2
RST #20
CALL PRINT_2
RST #18
CP #29
JP NZ,REPORT_C
RST #20
JP IN_NEXT_2
IN_ITEM_2: CP #CA
JR NZ,IN_ITEM_3
RST #20
CALL CLASS_01
SET 7,(IY+#37)
BIT 6,(IY+#01)
JP NZ,REPORT_C
JR IN_PROMPT
IN_ITEM_3: CALL ALPHA
JP NC,IN_NEXT_1
CALL CLASS_01
RES 7,(IY+#37)
IN_PROMPT: CALL SYNTAX_Z
JP Z,IN_NEXT_2
CALL SET_WORK
LD HL,#5C71
RES 6,(HL)
SET 5,(HL)
LD BC,#0001
BIT 7,(HL)
JR NZ,IN_PR_2
LD A,(#5C3B)
AND #40
JR NZ,IN_PR_1
LD C,#03
IN_PR_1: OR (HL)
LD (HL),A
IN_PR_2: RST #30
LD (HL),#0D
LD A,C
RRCA
RRCA
JR NC,IN_PR_3
LD A,#22
LD (DE),A
DEC HL
LD (HL),A
IN_PR_3: LD (#5C5B),HL
BIT 7,(IY+#37)
JR NZ,IN_VAR_3
LD HL,(#5C5D)
PUSH HL
LD HL,(#5C3D)
PUSH HL
IN_VAR_1: LD HL,IN_VAR_1
PUSH HL
BIT 4,(IY+#30)
JR Z,IN_VAR_2
LD (#5C3D),SP
IN_VAR_2: LD HL,(#5C61)
CALL REMOVE_FP
LD (IY+#00),#FF
CALL EDITOR
RES 7,(IY+#01)
CALL IN_ASSIGN
JR IN_VAR_4
IN_VAR_3: CALL EDITOR
IN_VAR_4: LD (IY+#22),#00
CALL IN_CHAN_K
JR NZ,IN_VAR_5
CALL ED_COPY
LD BC,(#5C82)
CALL CL_SET
IN_VAR_5: LD HL,#5C71
RES 5,(HL)
BIT 7,(HL)
RES 7,(HL)
JR NZ,IN_VAR_6
POP HL
POP HL
LD (#5C3D),HL
POP HL
LD (#5C5F),HL
SET 7,(IY+#01)
CALL IN_ASSIGN
LD HL,(#5C5F)
LD (IY+#26),#00
LD (#5C5D),HL
JR IN_NEXT_2
IN_VAR_6: LD HL,(#5C63)
LD DE,(#5C61)
SCF
SBC HL,DE
LD B,H
LD C,L
CALL STK_STO_D
CALL LET
JR IN_NEXT_2
IN_NEXT_1: CALL PR_ITEM_1
IN_NEXT_2: CALL PR_POSN_1
JP Z,IN_ITEM_1
RET
; INPUT sytax check and assignment
IN_ASSIGN: LD HL,(#5C61)
LD (#5C5D),HL
RST #18
CP #E2 ; STOP
JR Z,IN_STOP
LD A,(#5C71)
CALL VAL_FET_2
RST #18
CP #0D ; carriage return
RET Z
REPORT_CB: RST #08 ; Error report
DB #0B ; Nonsense in BASIC
IN_STOP: CALL SYNTAX_Z
RET Z
REPORT_H: RST #08 ; Error report
DB #10 ; STOP in INPUT
IN_CHAN_K: LD HL,(#5C51) ; Test for K channel
INC HL
INC HL
INC HL
INC HL
LD A,(HL)
CP #4B
RET
; Color item routines
CO_TEMP_1: RST #20
CO_TEMP_2: CALL CO_TEMP_3
RET C
RST #18
CP #2C
JR Z,CO_TEMP_1
CP #3B
JR Z,CO_TEMP_1
JP REPORT_C
CO_TEMP_3: CP #D9
RET C
CP #DF
CCF
RET C
PUSH AF
RST #20
POP AF
CO_TEMP_4: SUB #C9
PUSH AF
CALL EXPT_1NUM
POP AF
AND A
CALL UNSTACK_Z
PUSH AF
CALL FIND_INT1
LD D,A
POP AF
RST #10
LD A,D
RST #10
RET
; The color system variable handler
CO_TEMP_5: SUB #11
ADC A,#00
JR Z,CO_TEMP_7
SUB #02
ADC A,#00
JR Z,CO_TEMP_C
CP #01
LD A,D
LD B,#01
JR NZ,CO_TEMP_6
RLCA
RLCA
LD B,#04
CO_TEMP_6: LD C,A
LD A,D
CP #02
JR NC,REPORT_K
LD A,C
LD HL,#5C91
JR CO_CHANGE
CO_TEMP_7: LD A,D
LD B,#07
JR C,CO_TEMP_8
RLCA
RLCA
RLCA
LD B,#38
CO_TEMP_8: LD C,A
LD A,D
CP #0A
JR C,CO_TEMP_9
REPORT_K: RST #08 ; Error report
DB #13 ; Invalid colour
CO_TEMP_9: LD HL,#5C8F
CP #08
JR C,CO_TEMP_B
LD A,(HL)
JR Z,CO_TEMP_A
OR B
CPL
AND #24
JR Z,CO_TEMP_A
LD A,B
CO_TEMP_A: LD C,A
CO_TEMP_B: LD A,C
CALL CO_CHANGE
LD A,#07
CP D
SBC A,A
CALL CO_CHANGE
RLCA
RLCA
AND #50
LD B,A
LD A,#08
CP D
SBC A,A
; Handle change of color
CO_CHANGE: XOR (HL)
AND B
XOR (HL)
LD (HL),A
INC HL
LD A,B
RET
CO_TEMP_C: SBC A,A
LD A,D
RRCA
LD B,#80
JR NZ,CO_TEMP_D
RRCA
LD B,#40
CO_TEMP_D: LD C,A
LD A,D
CP #08
JR Z,CO_TEMP_E
CP #02
JR NC,REPORT_K
CO_TEMP_E: LD A,C
LD HL,#5C8F
CALL CO_CHANGE
LD A,C
RRCA
RRCA
RRCA
JR CO_CHANGE
; Handle BORDER command
BORDER: CALL FIND_INT1
CP #08
JR NC,REPORT_K
OUT (#FE),A
RLCA
RLCA
RLCA
BIT 5,A
JR NZ,BORDER_1
XOR #07
BORDER_1: LD (#5C48),A
RET
; Get pixel address
PIXEL_ADD: LD A,#AF
SUB B
JP C,REPORT_BC
LD B,A
AND A
RRA
SCF
RRA
AND A
RRA
XOR B
AND #F8
XOR B
LD H,A
LD A,C
RLCA
RLCA
RLCA
XOR B
AND #C7
XOR B
RLCA
RLCA
LD L,A
LD A,C
AND #07
RET
; Point subroutine
POINT_SUB: CALL STK_TO_BC
CALL PIXEL_ADD
LD B,A
INC B
LD A,(HL)
POINT_LP: RLCA
DJNZ POINT_LP
AND #01
JP STACK_A
; Handle PLOT command
PLOT: CALL STK_TO_BC
CALL PLOT_SUB
JP TEMPS
PLOT_SUB: LD (#5C7D),BC
CALL PIXEL_ADD
LD B,A
INC B
LD A,#FE
PLOT_LOOP: RRCA
DJNZ PLOT_LOOP
LD B,A
LD A,(HL)
LD C,(IY+#57)
BIT 0,C
JR NZ,PL_TST_IN
AND B
PL_TST_IN: BIT 2,C
JR NZ,PLOT_END
XOR B
CPL
PLOT_END: LD (HL),A
JP PO_ATTR
; Put two numbers in BC register
STK_TO_BC: CALL STK_TO_A
LD B,A
PUSH BC
CALL STK_TO_A
LD E,C
POP BC
LD D,C
LD C,A
RET
; Put the last value on the calc stack into the accumulator
STK_TO_A: CALL FP_TO_A
JP C,REPORT_BC
LD C,#01
RET Z
LD C,#FF
RET
; Handle CIRCLE command
CIRCLE: RST #18
CP #2C
JP NZ,REPORT_C
RST #20
CALL EXPT_1NUM
CALL CHECK_END
RST #28 ;FP_CALC
DB #2A ;ABS
DB #3D ;RE_STACK
DB #38 ;END_CALC
LD A,(HL)
CP #81
JR NC,C_R_GRE_1
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #38 ;END_CALC
JR PLOT
C_R_GRE_1: RST #28 ;FP_CALC
DB #A3 ;STK_PI_2
DB #38 ;END_CALC
LD (HL),#83
RST #28 ;FP_CALC
DB #C5 ;ST_MEM_5
DB #02 ;DELETE
DB #38 ;END_CALC
CALL CD_PRMS1
PUSH BC
RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #E1 ;GET_MEM_1
DB #04 ;MULTIPLY
DB #38 ;END_CALC
LD A,(HL)
CP #80
JR NC,C_ARC_GE1
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #02 ;DELETE
DB #38 ;END_CALC
POP BC
JP PLOT
C_ARC_GE1: RST #28 ;FP_CALC
DB #C2 ;ST_MEM_2
DB #01 ;EXCHANGE
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #03 ;SUBTRACT
DB #01 ;EXCHANGE
DB #E0 ;GET_MEM_0
DB #0F ;ADDITION
DB #C0 ;ST_MEM_0
DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #E0 ;GET_MEM_0
DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #E0 ;GET_MEM_0
DB #A0 ;STK_ZERO
DB #C1 ;ST_MEM_1
DB #02 ;DELETE
DB #38 ;END_CALC
INC (IY+#62)
CALL FIND_INT1
LD L,A
PUSH HL
CALL FIND_INT1
POP HL
LD H,A
LD (#5C7D),HL
POP BC
JP DRW_STEPS
; Handle DRAW command
DRAW: RST #18
CP #2C
JR Z,DR_3_PRMS
CALL CHECK_END
JP LINE_DRAW
DR_3_PRMS: RST #20
CALL EXPT_1NUM
CALL CHECK_END
RST #28 ;FP_CALC
DB #C5 ;ST_MEM_5
DB #A2 ;STK_HALF
DB #04 ;MULTIPLY
DB #1F ;SIN
DB #31 ;DUPLICATE
DB #30 ;NOT
DB #30 ;NOT
DB #00 ;JUMP_TRUE
DB #06 ;to DR_SIN_NZ
DB #02 ;DELETE
DB #38 ;END_CALC
JP LINE_DRAW
DR_SIN_NZ: DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #C1 ;ST_MEM_1
DB #02 ;DELETE
DB #31 ;DUPLICATE
DB #2A ;ABS
DB #E1 ;GET_MEM_1
DB #01 ;EXCHANGE
DB #E1 ;GET_MEM_1
DB #2A ;ABS
DB #0F ;ADDITION
DB #E0 ;GET_MEM_0
DB #05 ;DIVISION
DB #2A ;ABS
DB #E0 ;GET_MEM_0
DB #01 ;EXCHANGE
DB #3D ;RE_STACK
DB #38 ;END_CALC
LD A,(HL)
CP #81
JR NC,DR_PRMS
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #02 ;DELETE
DB #38 ;END_CALC
JP LINE_DRAW
DR_PRMS: CALL CD_PRMS1
PUSH BC
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #E1 ;GET_MEM_1
DB #01 ;EXCHANGE
DB #05 ;DIVISION
DB #C1 ;ST_MEM_1
DB #02 ;DELETE
DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #E1 ;GET_MEM_1
DB #04 ;MULTIPLY
DB #C2 ;ST_MEM_2
DB #02 ;DELETE
DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #E1 ;GET_MEM_1
DB #04 ;MULTIPLY
DB #E2 ;GET_MEM_2
DB #E5 ;GET_MEM_5
DB #E0 ;GET_MEM_0
DB #03 ;SUBTRACT
DB #A2 ;STK_HALF
DB #04 ;MULTIPLY
DB #31 ;DUPLICATE
DB #1F ;SIN
DB #C5 ;ST_MEM_5
DB #02 ;DELETE
DB #20 ;COS
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #C2 ;ST_MEM_2
DB #02 ;DELETE
DB #C1 ;ST_MEM_1
DB #E5 ;GET_MEM_5
DB #04 ;MULTIPLY
DB #E0 ;GET_MEM_0
DB #E2 ;GET_MEM_2
DB #04 ;MULTIPLY
DB #0F ;ADDITION
DB #E1 ;GET_MEM_1
DB #01 ;EXCHANGE
DB #C1 ;ST_MEM_1
DB #02 ;DELETE
DB #E0 ;GET_MEM_0
DB #04 ;MULTIPLY
DB #E2 ;GET_MEM_2
DB #E5 ;GET_MEM_5
DB #04 ;MULTIPLY
DB #03 ;SUBTRACT
DB #C2 ;ST_MEM_2
DB #2A ;ABS
DB #E1 ;GET_MEM_1
DB #2A ;ABS
DB #0F ;ADDITION
DB #02 ;DELETE
DB #38 ;END_CALC
LD A,(DE)
CP #81
POP BC
JP C,LINE_DRAW
PUSH BC
RST #28 ;FP_CALC
DB #01 ;EXCHANGE
DB #38 ;END_CALC
LD A,(#5C7D)
CALL STACK_A
RST #28 ;FP_CALC
DB #C0 ;ST_MEM_0
DB #0F ;ADDITION
DB #01 ;EXCHANGE
DB #38 ;END_CALC
LD A,(#5C7E)
CALL STACK_A
RST #28 ;FP_CALC
DB #C5 ;ST_MEM_5
DB #0F ;ADDITION
DB #E0 ;GET_MEM_0
DB #E5 ;GET_MEM_5
DB #38 ;END_CALC
POP BC
DRW_STEPS: DEC B
JR Z,ARC_END
JR ARC_START
ARC_LOOP: RST #28 ;FP_CALC
DB #E1 ;GET_MEM_1
DB #31 ;DUPLICATE
DB #E3 ;GET_MEM_3
DB #04 ;MULTIPLY
DB #E2 ;GET_MEM_2
DB #E4 ;GET_MEM_4
DB #04 ;MULTIPLY
DB #03 ;SUBTRACT
DB #C1 ;ST_MEM_1
DB #02 ;DELETE
DB #E4 ;GET_MEM_4
DB #04 ;MULTIPLY
DB #E2 ;GET_MEM_2
DB #E3 ;GET_MEM_3
DB #04 ;MULTIPLY
DB #0F ;ADDITION
DB #C2 ;ST_MEM_2
DB #02 ;DELETE
DB #38 ;END_CALC
ARC_START: PUSH BC
RST #28 ;FP_CALC
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #E1 ;GET_MEM_1
DB #0F ;ADDITION
DB #31 ;DUPLICATE
DB #38 ;END_CALC
LD A,(#5C7D)
CALL STACK_A
RST #28 ;FP_CALC
DB #03 ;SUBTRACT
DB #E0 ;GET_MEM_0
DB #E2 ;GET_MEM_2
DB #0F ;ADDITION
DB #C0 ;ST_MEM_0
DB #01 ;EXCHANGE
DB #E0 ;GET_MEM_0
DB #38 ;END_CALC
LD A,(#5C7E)
CALL STACK_A
RST #28 ;FP_CALC
DB #03 ;SUBTRACT
DB #38 ;END_CALC
CALL DRAW_LINE
POP BC
DJNZ ARC_LOOP
ARC_END: RST #28 ;FP_CALC
DB #02 ;DELETE
DB #02 ;DELETE
DB #01 ;EXCHANGE
DB #38 ;END_CALC
LD A,(#5C7D)
CALL STACK_A
RST #28 ;FP_CALC
DB #03 ;SUBTRACT
DB #01 ;EXCHANGE
DB #38 ;END_CALC
LD A,(#5C7E)
CALL STACK_A
RST #28 ;FP_CALC
DB #03 ;SUBTRACT
DB #38 ;END_CALC
LINE_DRAW: CALL DRAW_LINE
JP TEMPS
; Initial parameters
CD_PRMS1: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #28 ;SQR
DB #34 ;STK_DATA
DB #32 ;EXPONENT
DB #00 ;
DB #01 ;EXCHANGE
DB #05 ;DIVISION
DB #E5 ;GET_MEM_5
DB #01 ;EXCHANGE
DB #05 ;DIVISION
DB #2A ;ABS
DB #38 ;END_CALC
CALL FP_TO_A
JR C,USE_252
AND #FC
ADD A,#04
JR NC,DRAW_SAVE
USE_252: LD A,#FC
DRAW_SAVE: PUSH AF
CALL STACK_A
RST #28 ;FP_CALC
DB #E5 ;GET_MEM_5
DB #01 ;EXCHANGE
DB #05 ;DIVISION
DB #31 ;DUPLICATE
DB #1F ;SIN
DB #C4 ;ST_MEM_4
DB #02 ;DELETE
DB #31 ;DUPLICATE
DB #A2 ;STK_HALF
DB #04 ;MULTIPLY
DB #1F ;SIN
DB #C1 ;ST_MEM_1
DB #01 ;EXCHANGE
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #31 ;DUPLICATE
DB #04 ;MULTIPLY
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #1B ;NEGATE
DB #C3 ;ST_MEM_3
DB #02 ;DELETE
DB #38 ;END_CALC
POP BC
RET
; Line drawing
DRAW_LINE: CALL STK_TO_BC
LD A,C
CP B
JR NC,DL_X_GE_Y
LD L,C
PUSH DE
XOR A
LD E,A
JR DL_LARGER
DL_X_GE_Y: OR C
RET Z
LD L,B
LD B,C
PUSH DE
LD D,#00
DL_LARGER: LD H,B
LD A,B
RRA
D_L_LOOP: ADD A,L
JR C,D_L_DIAG
CP H
JR C,D_L_HR_VT
D_L_DIAG: SUB H
LD C,A
EXX
POP BC
PUSH BC
JR D_L_STEP
D_L_HR_VT: LD C,A
PUSH DE
EXX
POP BC
D_L_STEP: LD HL,(#5C7D)
LD A,B
ADD A,H
LD B,A
LD A,C
INC A
ADD A,L
JR C,D_L_RANGE
JR Z,REPORT_BC
D_L_PLOT: DEC A
LD C,A
CALL PLOT_SUB
EXX
LD A,C
DJNZ D_L_LOOP
POP DE
RET
D_L_RANGE: JR Z,D_L_PLOT
REPORT_BC: RST #08 ; Error report
DB #0A ; Integer out of range
; Scan expression or sub expression
SCANNING: RST #18
LD B,#00
PUSH BC
S_LOOP_1: LD C,A
CALL HEXA ; BSROM - hexadecimal numbers handling
CALL INDEXER
LD A,C
JP NC,S_ALPHNUM
LD B,#00
LD C,(HL)
ADD HL,BC
JP (HL)
S_QUOTE_S: CALL CH_ADD_1
INC BC
CP #0D
JP Z,REPORT_C
CP #22
JR NZ,S_QUOTE_S
CALL CH_ADD_1
CP #22
RET
S_2_COORD: RST #20
CP #28
JR NZ,S_RPORT_C
CALL NEXT_2NUM
RST #18
CP #29
S_RPORT_C: JP NZ,REPORT_C
; Check syntax
SYNTAX_Z: BIT 7,(IY+#01)
RET
; Scanning SCREEN$
S_SCRN_S: CALL STK_TO_BC
LD HL,(#5C36)
LD DE,#0100
ADD HL,DE
LD A,C
RRCA
RRCA
RRCA
AND #E0
XOR B
LD E,A
LD A,C
AND #18
XOR #40
LD D,A
LD B,#60
S_SCRN_LP: PUSH BC
PUSH DE
PUSH HL
LD A,(DE)
XOR (HL)
JR Z,S_SC_MTCH
INC A
JR NZ,S_SCR_NXT
DEC A
S_SC_MTCH: LD C,A
LD B,#07
S_SC_ROWS: INC D
INC HL
LD A,(DE)
XOR (HL)
XOR C
JR NZ,S_SCR_NXT
DJNZ S_SC_ROWS
POP BC
POP BC
POP BC
LD A,#80
SUB B
LD BC,#0001
RST #30
LD (DE),A
JR S_SCR_STO
S_SCR_NXT: POP HL
LD DE,#0008
ADD HL,DE
POP DE
POP BC
DJNZ S_SCRN_LP
LD C,B
S_SCR_STO: RET ; BSROM - bugfix - don't store string after SCREEN$
DB #B2,#2A ; remains of JP STK_STO_D (#2AB2)
; Scanning attributes
S_ATTR_S: CALL STK_TO_BC
LD A,C
RRCA
RRCA
RRCA
LD C,A
AND #E0
XOR B
LD L,A
LD A,C
AND #03
XOR #58
LD H,A
LD A,(HL)
JP STACK_A
; Scanning function table
SCAN_FUNC: DB #22, #1C ; S_QUOTE
DB #28, #4F ; S_BRACKET
DB #2E, #F2 ; S_DECIMAL
DB #2B, #12 ; S_U_PLUS
DB #A8, #56 ; S_FN
DB #A5, #57 ; S_RND
DB #A7, #84 ; S_PI
DB #A6, #8F ; S_INKEY
DB #C4, #E6 ; S_BIN
DB #AA, #BF ; S_SCREEN
DB #AB, #C7 ; S_ATTR
DB #A9, #CE ; S_POINT
DB #00 ; End marker
; Scanning function routines
S_U_PLUS: RST #20
JP S_LOOP_1
S_QUOTE: RST #18
INC HL
PUSH HL
LD BC,#0000
CALL S_QUOTE_S
JR NZ,S_Q_PRMS
S_Q_AGAIN: CALL S_QUOTE_S
JR Z,S_Q_AGAIN
CALL SYNTAX_Z
JR Z,S_Q_PRMS
RST #30
POP HL
PUSH DE
S_Q_COPY: LD A,(HL)
INC HL
LD (DE),A
INC DE
CP #22
JR NZ,S_Q_COPY
LD A,(HL)
INC HL
CP #22
JR Z,S_Q_COPY
S_Q_PRMS: DEC BC
POP DE
S_STRING: LD HL,#5C3B
RES 6,(HL)
BIT 7,(HL)
CALL NZ,STK_STO_D
JP S_CONT_2
S_BRACKET: RST #20
CALL SCANNING
CP #29
JP NZ,REPORT_C
RST #20
JP S_CONT_2
S_FN: JP S_FN_SBRN
S_RND: CALL SYNTAX_Z
JR Z,S_RND_END
LD BC,(#5C76)
CALL STACK_BC
RST #28 ;FP_CALC
DB #A1 ;STK_ONE
DB #0F ;ADDITION
DB #34 ;STK_DATA
DB #37 ;Exponent
DB #16 ;
DB #04 ;MULTIPLY
DB #34 ;STK_DATA
DB #80 ;
DB #41 ;Exponent
DB #00 ;
DB #00 ;
DB #80 ;
DB #32 ;N_MOD_M
DB #02 ;DELETE
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #31 ;DUPLICATE
DB #38 ;END_CALC
CALL FP_TO_BC
LD (#5C76),BC
LD A,(HL)
AND A
JR Z,S_RND_END
SUB #10
LD (HL),A
S_RND_END: JR S_PI_END
S_PI: CALL SYNTAX_Z
JR Z,S_PI_END
RST #28 ;FP_CALC
DB #A3 ;STK_PI_2
DB #38 ;END_CALC
INC (HL)
S_PI_END: RST #20
JP S_NUMERIC
S_INKEY: LD BC,#105A
RST #20
CP #23
JP Z,S_PUSH_PO
LD HL,#5C3B
RES 6,(HL)
BIT 7,(HL)
JR Z,S_INK_EN
CALL KEY_SCAN
LD C,#00
JR NZ,S_IK_STK
CALL K_TEST
JR NC,S_IK_STK
DEC D
LD E,A
CALL K_DECODE
PUSH AF
LD BC,#0001
RST #30
POP AF
LD (DE),A
LD C,#01
S_IK_STK: LD B,#00
CALL STK_STO_D
S_INK_EN: JP S_CONT_2
S_SCREEN: CALL S_2_COORD
CALL NZ,S_SCRN_S
RST #20
JP S_STRING
S_ATTR: CALL S_2_COORD
CALL NZ,S_ATTR_S
RST #20
JR S_NUMERIC
S_POINT: CALL S_2_COORD
CALL NZ,POINT_SUB
RST #20
JR S_NUMERIC
S_ALPHNUM: CALL ALPHANUM
JR NC,S_NEGATE
CP #41
JR NC,S_LETTER
S_DECIMAL:
S_BIN: CALL SYNTAX_Z
JR NZ,S_STK_DEC
CALL DEC_TO_FP
S_BIN_1: RST #18
LD BC,#0006
CALL MAKE_ROOM
INC HL
LD (HL),#0E
INC HL
EX DE,HL
LD HL,(#5C65)
LD C,#05
AND A
SBC HL,BC
LD (#5C65),HL
LDIR
EX DE,HL
DEC HL
CALL TEMP_PTR1
JR S_NUMERIC
S_STK_DEC: RST #18
S_SD_SKIP: INC HL
LD A,(HL)
CP #0E
JR NZ,S_SD_SKIP
INC HL
CALL STACK_NUM
LD (#5C5D),HL
S_NUMERIC: SET 6,(IY+#01)
JR S_CONT_1
; Scanning variable routines
S_LETTER: CALL LOOK_VARS
JP C,REPORT_2
CALL Z,STK_VAR
LD A,(#5C3B)
CP #C0
JR C,S_CONT_1
INC HL
CALL STACK_NUM
S_CONT_1: JR S_CONT_2
S_NEGATE: LD BC,#09DB
CP #2D
JR Z,S_PUSH_PO
LD BC,#1018
CP #AE
JR Z,S_PUSH_PO
SUB #AF
JP C,REPORT_C
LD BC,#04F0
CP #14
JR Z,S_PUSH_PO
JP NC,REPORT_C
LD B,#10
ADD A,#DC
LD C,A
CP #DF
JR NC,S_NO_TO
RES 6,C
S_NO_TO: CP #EE
JR C,S_PUSH_PO
RES 7,C
S_PUSH_PO: PUSH BC
RST #20
JP S_LOOP_1
S_CONT_2: RST #18
S_CONT_3: CP #28
JR NZ,S_OPERTR
BIT 6,(IY+#01)
JR NZ,S_LOOP
CALL SLICING
RST #20
JR S_CONT_3
S_OPERTR: LD B,#00
LD C,A
LD HL,TBL_OF_OPS
CALL INDEXER
JR NC,S_LOOP
LD C,(HL)
LD HL,#26ED
ADD HL,BC
LD B,(HL)
; Scanning main loop
S_LOOP: POP DE
LD A,D
CP B
JR C,S_TIGHTER
AND A
JP Z,GET_CHAR
PUSH BC
LD HL,#5C3B
LD A,E
CP #ED
JR NZ,S_STK_LST
BIT 6,(HL)
JR NZ,S_STK_LST
LD E,#99
S_STK_LST: PUSH DE
CALL SYNTAX_Z
JR Z,S_SYNTEST
LD A,E
AND #3F
LD B,A
RST #28 ;FP_CALC
DB #3B ;FP_CALC_2
DB #38 ;END_CALC
JR S_RUNTEST
S_SYNTEST: LD A,E
CALL VAL1 ; BSROM - enhanced VAL & VAL$
AND #40
S_RPORT_C2: JP NZ,REPORT_C
S_RUNTEST: POP DE
LD HL,#5C3B
SET 6,(HL)
BIT 7,E
JR NZ,S_LOOPEND
RES 6,(HL)
S_LOOPEND: POP BC
JR S_LOOP
S_TIGHTER: PUSH DE
LD A,C
BIT 6,(IY+#01)
JR NZ,S_NEXT
AND #3F
ADD A,#08
LD C,A
CP #10
JR NZ,S_NOT_AND
SET 6,C
JR S_NEXT
S_NOT_AND: JR C,S_RPORT_C2
CP #17
JR Z,S_NEXT
SET 7,C
S_NEXT: PUSH BC
RST #20
JP S_LOOP_1
; Table of operators
TBL_OF_OPS: DB "+", #CF ; ADDITION
DB "-", #C3 ; SUBTRACT
DB "*", #C4 ; MULTIPLY
DB "/", #C5 ; DIVISION
DB "^", #C6 ; TO_POWER
DB "=", #CE ; NOS_EQL
DB ">", #CC ; NO_GRTR
DB "<", #CD ; NO_LESS
DB #C7, #C9 ; NO_L_EQL '<='
DB #C8, #CA ; NO_GR_EQL '>='
DB #C9, #CB ; NOS_NEQL '<>'
DB #C5, #C7 ; OR
DB #C6, #C8 ; AND
DB #00 ; End marker
; Table of priorities
TBL_PRIORS: DB #06 ; '-'
DB #08 ; '*'
DB #08 ; '/'
DB #0A ; '^'
DB #02 ; OR
DB #03 ; AND
DB #05 ; '<='
DB #05 ; '>='
DB #05 ; '<>'
DB #05 ; '>'
DB #05 ; '<'
DB #05 ; '='
DB #06 ; '+'
; User defined functions handling
S_FN_SBRN: CALL SYNTAX_Z
JR NZ,SF_RUN
RST #20
CALL ALPHA
JP NC,REPORT_C
RST #20
CP #24
PUSH AF
JR NZ,SF_BRKT_1
RST #20
SF_BRKT_1: CP #28
JR NZ,SF_RPRT_C
RST #20
CP #29
JR Z,SF_FLAG_6
SF_ARGMTS: CALL SCANNING
RST #18
CP #2C
JR NZ,SF_BRKT_2
RST #20
JR SF_ARGMTS
SF_BRKT_2: CP #29
SF_RPRT_C: JP NZ,REPORT_C
SF_FLAG_6: RST #20
LD HL,#5C3B
RES 6,(HL)
POP AF
JR Z,SF_SYN_EN
SET 6,(HL)
SF_SYN_EN JP S_CONT_2
SF_RUN: RST #20
AND #DF
LD B,A
RST #20
SUB #24
LD C,A
JR NZ,SF_ARGMT1
RST #20
SF_ARGMT1: RST #20
PUSH HL
LD HL,(#5C53)
DEC HL
SF_FND_DF: LD DE,#00CE
PUSH BC
CALL LOOK_PROG
POP BC
JR NC,SF_CP_DEF
REPORT_P: RST #08 ; Error report
DB #18 ; FN without DEF
SF_CP_DEF: PUSH HL
CALL FN_SKPOVR
AND #DF
CP B
JR NZ,SF_NOT_FD
CALL FN_SKPOVR
SUB #24
CP C
JR Z,SF_VALUES
SF_NOT_FD: POP HL
DEC HL
LD DE,#0200
PUSH BC
CALL EACH_STMT
POP BC
JR SF_FND_DF
SF_VALUES: AND A
CALL Z,FN_SKPOVR
POP DE
POP DE
LD (#5C5D),DE
CALL FN_SKPOVR
PUSH HL
CP #29
JR Z,SF_R_BR_2
SF_ARG_LP: INC HL
LD A,(HL)
CP #0E
LD D,#40
JR Z,SF_ARG_VR
DEC HL
CALL FN_SKPOVR
INC HL
LD D,#00
SF_ARG_VR: INC HL
PUSH HL
PUSH DE
CALL SCANNING
POP AF
XOR (IY+#01)
AND #40
JR NZ,REPORT_Q
POP HL
EX DE,HL
LD HL,(#5C65)
LD BC,#0005
SBC HL,BC
LD (#5C65),HL
LDIR
EX DE,HL
DEC HL
CALL FN_SKPOVR
CP #29
JR Z,SF_R_BR_2
PUSH HL
RST #18
CP #2C
JR NZ,REPORT_Q
RST #20
POP HL
CALL FN_SKPOVR
JR SF_ARG_LP
SF_R_BR_2: PUSH HL
RST #18
CP #29
JR Z,SF_VALUE
REPORT_Q: RST #08 ; Error report
DB #19 ; Parameter error
SF_VALUE: POP DE
EX DE,HL
LD (#5C5D),HL
LD HL,(#5C0B)
EX (SP),HL
LD (#5C0B),HL
PUSH DE
RST #20
RST #20
CALL SCANNING
POP HL
LD (#5C5D),HL
POP HL
LD (#5C0B),HL
RST #20
JP S_CONT_2
; Skip spaces and color control codes in DEF FN
FN_SKPOVR: INC HL
LD A,(HL)
CP #21
JR C,FN_SKPOVR
RET
; Variables lookup
LOOK_VARS: SET 6,(IY+#01)
RST #18
CALL ALPHA
JP NC,REPORT_C
PUSH HL
AND #1F
LD C,A
RST #20
PUSH HL
CP #28
JR Z,V_RUN_SYN
SET 6,C
CP #24
JR Z,V_STR_VAR
SET 5,C
CALL ALPHANUM
JR NC,V_TEST_FN
V_CHAR: CALL ALPHANUM
JR NC,V_RUN_SYN
RES 6,C
RST #20
JR V_CHAR
V_STR_VAR: RST #20
RES 6,(IY+#01)
V_TEST_FN: LD A,(#5C0C)
AND A
JR Z,V_RUN_SYN
CALL SYNTAX_Z
JP NZ,STK_F_ARG
V_RUN_SYN: LD B,C
CALL SYNTAX_Z
JR NZ,V_RUN
LD A,C
AND #E0
SET 7,A
LD C,A
JR V_SYNTAX
V_RUN: LD HL,(#5C4B)
V_EACH: LD A,(HL)
AND #7F
JR Z,V_80_BYTE
CP C
JR NZ,V_NEXT
RLA
ADD A,A
JP P,V_FOUND_2
JR C,V_FOUND_2
POP DE
PUSH DE
PUSH HL
V_MATCHES: INC HL
V_SPACES: LD A,(DE)
INC DE
CP #20
JR Z,V_SPACES
OR #20
CP (HL)
JR Z,V_MATCHES
OR #80
CP (HL)
JR NZ,V_GET_PTR
LD A,(DE)
CALL ALPHANUM
JR NC,V_FOUND_1
V_GET_PTR: POP HL
V_NEXT: PUSH BC
CALL NEXT_ONE
EX DE,HL
POP BC
JR V_EACH
V_80_BYTE: SET 7,B
V_SYNTAX: POP DE
RST #18
CP #28
JR Z,V_PASS
SET 5,B
JR V_END
V_FOUND_1: POP DE
V_FOUND_2: POP DE
POP DE
PUSH HL
RST #18
V_PASS: CALL ALPHANUM
JR NC,V_END
RST #20
JR V_PASS
V_END: POP HL
RL B
BIT 6,B
RET
; Stack function argument
STK_F_ARG: LD HL,(#5C0B)
LD A,(HL)
CP #29
JP Z,V_RUN_SYN
SFA_LOOP: LD A,(HL)
OR #60
LD B,A
INC HL
LD A,(HL)
CP #0E
JR Z,SFA_CP_VR
DEC HL
CALL FN_SKPOVR
INC HL
RES 5,B
SFA_CP_VR: LD A,B
CP C
JR Z,SFA_MATCH
INC HL
INC HL
INC HL
INC HL
INC HL
CALL FN_SKPOVR
CP #29
JP Z,V_RUN_SYN
CALL FN_SKPOVR
JR SFA_LOOP
SFA_MATCH: BIT 5,C
JR NZ,SFA_END
INC HL
LD DE,(#5C65)
CALL MOVE_FP
EX DE,HL
LD (#5C65),HL
SFA_END: POP DE
POP DE
XOR A
INC A
RET
; Stack variable component
STK_VAR: XOR A
LD B,A
BIT 7,C
JR NZ,SV_COUNT
BIT 7,(HL)
JR NZ,SV_ARRAYS
INC A
SV_SIMPLE: INC HL
LD C,(HL)
INC HL
LD B,(HL)
INC HL
EX DE,HL
CALL STK_STO_D
RST #18
JP SV_SLICE_EX
SV_ARRAYS: INC HL
INC HL
INC HL
LD B,(HL)
BIT 6,C
JR Z,SV_PTR
DEC B
JR Z,SV_SIMPLE
EX DE,HL
RST #18
CP #28
JR NZ,REPORT_3
EX DE,HL
SV_PTR: EX DE,HL
JR SV_COUNT
SV_COMMA: PUSH HL
RST #18
POP HL
CP #2C
JR Z,SV_LOOP
BIT 7,C
JR Z,REPORT_3
BIT 6,C
JR NZ,SV_CLOSE
CP #29
JR NZ,SV_RPT_C
RST #20
RET
SV_CLOSE: CP #29
JR Z,SV_DIM
CP #CC
JR NZ,SV_RPT_C
SV_CH_ADD: RST #18
DEC HL
LD (#5C5D),HL
JR SV_SLICE
SV_COUNT: LD HL,#0000
SV_LOOP: PUSH HL
RST #20
POP HL
LD A,C
CP #C0
JR NZ,SV_MULT
RST #18
CP #29
JR Z,SV_DIM
CP #CC
JR Z,SV_CH_ADD
SV_MULT: PUSH BC
PUSH HL
CALL DE_DE_1
EX (SP),HL
EX DE,HL
CALL INT_EXP1
JR C,REPORT_3
DEC BC
CALL GET_HL_DE
ADD HL,BC
POP DE
POP BC
DJNZ SV_COMMA
BIT 7,C
SV_RPT_C: JR NZ,SL_RPT_C
PUSH HL
BIT 6,C
JR NZ,SV_ELEM
LD B,D
LD C,E
RST #18
CP #29
JR Z,SV_NUMBER
REPORT_3: RST #08 ; Error report
DB #02 ; Subscript wrong
SV_NUMBER: RST #20
POP HL
LD DE,#0005
CALL GET_HL_DE
ADD HL,BC
RET
SV_ELEM: CALL DE_DE_1
EX (SP),HL
CALL GET_HL_DE
POP BC
ADD HL,BC
INC HL
LD B,D
LD C,E
EX DE,HL
CALL STK_ST_0
RST #18
CP #29
JR Z,SV_DIM
CP #2C
JR NZ,REPORT_3
SV_SLICE: CALL SLICING
SV_DIM: RST #20
SV_SLICE_EX: CP #28
JR Z,SV_SLICE
RES 6,(IY+#01)
RET
; Handle slicing of strings
SLICING: CALL SYNTAX_Z
CALL NZ,STK_FETCH
RST #20
CP #29
JR Z,SL_STORE
PUSH DE
XOR A
PUSH AF
PUSH BC
LD DE,#0001
RST #18
POP HL
CP #CC
JR Z,SL_SECOND
POP AF
CALL INT_EXP2
PUSH AF
LD D,B
LD E,C
PUSH HL
RST #18
POP HL
CP #CC
JR Z,SL_SECOND
CP #29
SL_RPT_C: JP NZ,REPORT_C
LD H,D
LD L,E
JR SL_DEFINE
SL_SECOND: PUSH HL
RST #20
POP HL
CP #29
JR Z,SL_DEFINE
POP AF
CALL INT_EXP2
PUSH AF
RST #18
LD H,B
LD L,C
CP #29
JR NZ,SL_RPT_C
SL_DEFINE: POP AF
EX (SP),HL
ADD HL,DE
DEC HL
EX (SP),HL
AND A
SBC HL,DE
LD BC,#0000
JR C,SL_OVER
INC HL
AND A
JP M,REPORT_3
LD B,H
LD C,L
SL_OVER: POP DE
SL_OVER1: RES 6,(IY+#01)
SL_STORE: CALL SYNTAX_Z
RET Z
STK_ST_0: XOR A
STK_STO_D: RES 6,(IY+#01)
STK_STORE: PUSH BC ; Put five registers on the calc stack
CALL TEST_5_SP
POP BC
LD HL,(#5C65)
LD (HL),A
INC HL
LD (HL),E
INC HL
LD (HL),D
INC HL
LD (HL),C
INC HL
LD (HL),B
INC HL
LD (#5C65),HL
RET
; Check and evaluate an integer expression
INT_EXP1: XOR A
INT_EXP2: PUSH DE
PUSH HL
PUSH AF
CALL EXPT_1NUM
POP AF
CALL SYNTAX_Z
JR Z,I_RESTORE
PUSH AF
CALL FIND_INT2
POP DE
LD A,B
OR C
SCF
JR Z,I_CARRY
POP HL
PUSH HL
AND A
SBC HL,BC
I_CARRY: LD A,D
SBC A,#00
I_RESTORE: POP HL
POP DE
RET
; Load DE+1 into DE
DE_DE_1: EX DE,HL
INC HL
LD E,(HL)
INC HL
LD D,(HL)
RET
; Multiply HL by DE
GET_HL_DE: CALL SYNTAX_Z
RET Z
CALL HL_HL_DE
JP C,REPORT_4
RET
; Handle LET command
LET: LD HL,(#5C4D)
BIT 1,(IY+#37)
JR Z,L_EXISTS
LD BC,#0005
L_EACH_CH: INC BC
L_NO_SP: INC HL
LD A,(HL)
CP #20
JR Z,L_NO_SP
JR NC,L_TEST_CH
CP #10
JR C,L_SPACES
CP #16
JR NC,L_SPACES
INC HL
JR L_NO_SP
L_TEST_CH: CALL ALPHANUM
JR C,L_EACH_CH
CP #24
JP Z,L_NEW
L_SPACES: LD A,C
LD HL,(#5C59)
DEC HL
CALL MAKE_ROOM
INC HL
INC HL
EX DE,HL
PUSH DE
LD HL,(#5C4D)
DEC DE
SUB #06
LD B,A
JR Z,L_SINGLE
L_CHAR: INC HL
LD A,(HL)
CP #21
JR C,L_CHAR
OR #20
INC DE
LD (DE),A
DJNZ L_CHAR
OR #80
LD (DE),A
LD A,#C0
L_SINGLE: LD HL,(#5C4D)
XOR (HL)
OR #20
POP HL
CALL L_FIRST
L_NUMERIC: PUSH HL
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #38 ;END_CALC
POP HL
LD BC,#0005
AND A
SBC HL,BC
JR L_ENTER
L_EXISTS: BIT 6,(IY+#01)
JR Z,L_DELETE
LD DE,#0006
ADD HL,DE
JR L_NUMERIC
L_DELETE: LD HL,(#5C4D)
LD BC,(#5C72)
BIT 0,(IY+#37)
JR NZ,L_ADD
LD A,B
OR C
RET Z
PUSH HL
RST #30
PUSH DE
PUSH BC
LD D,H
LD E,L
INC HL
LD (HL),#20
LDDR
PUSH HL
CALL STK_FETCH
POP HL
EX (SP),HL
AND A
SBC HL,BC
ADD HL,BC
JR NC,L_LENGTH
LD B,H
LD C,L
L_LENGTH: EX (SP),HL
EX DE,HL
LD A,B
OR C
JR Z,L_IN_W_S
LDIR
L_IN_W_S: POP BC
POP DE
POP HL
L_ENTER: EX DE,HL
LD A,B
OR C
RET Z
PUSH DE
LDIR
POP HL
RET
L_ADD: DEC HL
DEC HL
DEC HL
LD A,(HL)
PUSH HL
PUSH BC
CALL L_STRING
POP BC
POP HL
INC BC
INC BC
INC BC
JP RECLAIM_2
L_NEW: LD A,#DF
LD HL,(#5C4D)
AND (HL)
L_STRING: PUSH AF
CALL STK_FETCH
EX DE,HL
ADD HL,BC
PUSH BC
DEC HL
LD (#5C4D),HL
INC BC
INC BC
INC BC
LD HL,(#5C59)
DEC HL
CALL MAKE_ROOM
LD HL,(#5C4D)
POP BC
PUSH BC
INC BC
LDDR
EX DE,HL
INC HL
POP BC
LD (HL),B
DEC HL
LD (HL),C
POP AF
L_FIRST: DEC HL
LD (HL),A
LD HL,(#5C59)
DEC HL
RET
; Get last value from the calc stack
STK_FETCH: LD HL,(#5C65)
DEC HL
LD B,(HL)
DEC HL
LD C,(HL)
DEC HL
LD D,(HL)
DEC HL
LD E,(HL)
DEC HL
LD A,(HL)
LD (#5C65),HL
RET
; Handle DIM command
DIM: CALL LOOK_VARS
D_RPORT_C: JP NZ,REPORT_C
CALL SYNTAX_Z
JR NZ,D_RUN
RES 6,C
CALL STK_VAR
CALL CHECK_END
D_RUN: JR C,D_LETTER
PUSH BC
CALL NEXT_ONE
CALL RECLAIM_2
POP BC
D_LETTER: SET 7,C
LD B,#00
PUSH BC
LD HL,#0001
BIT 6,C
JR NZ,D_SIZE
LD L,#05
D_SIZE: EX DE,HL
D_NO_LOOP: RST #20
LD H,#FF
CALL INT_EXP1
JP C,REPORT_3
POP HL
PUSH BC
INC H
PUSH HL
LD H,B
LD L,C
CALL GET_HL_DE
EX DE,HL
RST #18
CP #2C
JR Z,D_NO_LOOP
CP #29
JR NZ,D_RPORT_C
RST #20
POP BC
LD A,C
LD L,B
LD H,#00
INC HL
INC HL
ADD HL,HL
ADD HL,DE
JP C,REPORT_4
PUSH DE
PUSH BC
PUSH HL
LD B,H
LD C,L
LD HL,(#5C59)
DEC HL
CALL MAKE_ROOM
INC HL
LD (HL),A
POP BC
DEC BC
DEC BC
DEC BC
INC HL
LD (HL),C
INC HL
LD (HL),B
POP BC
LD A,B
INC HL
LD (HL),A
LD H,D
LD L,E
DEC DE
LD (HL),#00
BIT 6,C
JR Z,DIM_CLEAR
LD (HL),#20
DIM_CLEAR: POP BC
LDDR
DIM_SIZES: POP BC
LD (HL),B
DEC HL
LD (HL),C
DEC HL
DEC A
JR NZ,DIM_SIZES
RET
; Check that the character in A is alphanumeric
ALPHANUM: CALL NUMERIC
CCF
RET C
ALPHA: CP #41
CCF
RET NC
CP #5B
RET C
CP #61
CCF
RET NC
CP #7B
RET
; Decimal to floating point
DEC_TO_FP: CP #C4
JR NZ,NOT_BIN
LD DE,#0000
BIN_DIGIT: RST #20
SUB #31
ADC A,#00
JR NZ,BIN_END
EX DE,HL
CCF
ADC HL,HL
JP C,REPORT_6
EX DE,HL
JR BIN_DIGIT
BIN_END: LD B,D
LD C,E
JP STACK_BC
NOT_BIN: CP #2E
JR Z,DECIMAL
CALL INT_TO_FP
CP #2E
JR NZ,E_FORMAT
RST #20
CALL NUMERIC
JR C,E_FORMAT
JR DEC_STO_1
DECIMAL: RST #20
CALL NUMERIC
DEC_RPT_C: JP C,REPORT_C
RST #28 ;FP_CALC
DB #A0 ;STK_ZERO
DB #38 ;END_CALC
DEC_STO_1: RST #28 ;FP_CALC
DB #A1 ;STK_ONE
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #38 ;END_CALC
NXT_DGT_1: RST #18
CALL STK_DIGIT
JR C,E_FORMAT
RST #28 ;FP_CALC
DB #E0 ;GET_MEM_0
DB #A4 ;STK_TEN
DB #05 ;DIVISION
DB #C0 ;ST_MEM_0
DB #04 ;MULTIPLY
DB #0F ;ADDITION
DB #38 ;END_CALC
RST #20
JR NXT_DGT_1
E_FORMAT: CP #45
JR Z,SIGN_FLAG
CP #65
RET NZ
SIGN_FLAG: LD B,#FF
RST #20
CP #2B
JR Z,SIGN_DONE
CP #2D
JR NZ,ST_E_PART
INC B
SIGN_DONE: RST #20
ST_E_PART: CALL NUMERIC
JR C,DEC_RPT_C
PUSH BC
CALL INT_TO_FP
CALL FP_TO_A
POP BC
JP C,REPORT_6
AND A
JP M,REPORT_6
INC B
JR Z,E_FP_JUMP
NEG
E_FP_JUMP: JP E_TO_FP
; Check for valid digit
NUMERIC: CP #30
RET C
CP #3A
CCF
RET
; Stack digit
STK_DIGIT: CALL NUMERIC
RET C
SUB #30
STACK_A: LD C,A ;Stack accumulator
LD B,#00
STACK_BC: LD IY,#5C3A ;Stack BC register pair
XOR A
LD E,A
LD D,C
LD C,B
LD B,A
CALL STK_STORE
RST #28 ;FP_CALC
DB #38 ;END_CALC
AND A
RET
; Integer to floating point
INT_TO_FP: PUSH AF
RST #28 ;FP_CALC
DB #A0 ;STK_ZERO
DB #38 ;END_CALC
POP AF
NXT_DGT_2: CALL STK_DIGIT
RET C
RST #28 ;FP_CALC
DB #01 ;EXCHANGE
DB #A4 ;STK_TEN
DB #04 ;MULTIPLY
DB #0F ;ADDITION
DB #38 ;END_CALC
CALL CH_ADD_1
JR NXT_DGT_2
; E-format to floating point
E_TO_FP: RLCA
RRCA
JR NC,E_SAVE
CPL
INC A
E_SAVE: PUSH AF
LD HL,#5C92
CALL FP_0_1
RST #28 ;FP_CALC
DB #A4 ;STK_TEN
DB #38 ;END_CALC
POP AF
E_LOOP: SRL A
JR NC,E_TST_END
PUSH AF
RST #28 ;FP_CALC
DB #C1 ;ST_MEM_1
DB #E0 ;GET_MEM_0
DB #00 ;JUMP_TRUE
DB #04 ;to E_DIVSN
DB #04 ;MULTIPLY
DB #33 ;JUMP
DB #02 ;to E_FETCH
E_DIVSN: DB #05 ;DIVISION
E_FETCH: DB #E1 ;GET_MEM_1
DB #38 ;END_CALC
POP AF
E_TST_END: JR Z,E_END
PUSH AF
RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #04 ;MULTIPLY
DB #38 ;END_CALC
POP AF
JR E_LOOP
E_END: RST #28 ;FP_CALC
DB #02 ;DELETE
DB #38 ;END_CALC
RET
; Fetch integer
INT_FETCH: INC HL
LD C,(HL)
INC HL
LD A,(HL)
XOR C
SUB C
LD E,A
INC HL
LD A,(HL)
ADC A,C
XOR C
LD D,A
RET
; Store a positive integer. Not used in ROM.
P_INT_STO: LD C,#00
; Store an integer
INT_STORE: PUSH HL
LD (HL),#00
INC HL
LD (HL),C
INC HL
LD A,E
XOR C
SUB C
LD (HL),A
INC HL
LD A,D
ADC A,C
XOR C
LD (HL),A
INC HL
LD (HL),#00
POP HL
RET
; Get floating point number from the calc stack to the BC
FP_TO_BC: RST #28 ;FP_CALC
DB #38 ;END_CALCS
LD A,(HL)
AND A
JR Z,FP_DELETE
RST #28 ;FP_CALC
DB #A2 ;STK_HALF
DB #0F ;ADDITION
DB #27 ;INT
DB #38 ;END_CALC
FP_DELETE: RST #28 ;FP_CALC
DB #02 ;DELETE
DB #38 ;END_CALC
PUSH HL
PUSH DE
EX DE,HL
LD B,(HL)
CALL INT_FETCH
XOR A
SUB B
BIT 7,C
LD B,D
LD C,E
LD A,E
POP DE
POP HL
RET
LOG_2_A: LD D,A
RLA
SBC A,A
LD E,A
LD C,A
XOR A
LD B,A
CALL STK_STORE
RST #28 ;FP_CALC
DB #34 ;STK_DATA
DB #EF ;Exponent
DB #1A ;
DB #20 ;
DB #9A ;
DB #85 ;
DB #04 ;MULTIPLY
DB #27 ;INT
DB #38 ;END_CALC
; Floating point to A
FP_TO_A: CALL FP_TO_BC
RET C
PUSH AF
DEC B
INC B
JR Z,FP_A_END
POP AF
SCF
RET
FP_A_END: POP AF
RET
; Print a floating point number
PRINT_FP: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #36 ;LESS_0
DB #00 ;JUMP_TRUE
DB #0B ;to PF_NEGTVE
DB #31 ;DUPLICATE
DB #37 ;GREATER_0
DB #00 ;JUMP_TRUE
DB #0D ;to PS_POSTVE
DB #02 ;DELETE
DB #38 ;END_CALC
LD A,#30
RST #10
RET
PF_NEGTVE: DB #2A ;ABS
DB #38 ;END_CALC
LD A,#2D
RST #10
RST #28 ;FP_CALC
PF_POSTVE: DB #A0 ;STK_ZERO
DB #C3 ;ST_MEM_3
DB #C4 ;ST_MEM_4
DB #C5 ;ST_MEM_5
DB #02 ;DELETE
DB #38 ;END_CALC
EXX
PUSH HL
EXX
PF_LOOP: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #27 ;INT
DB #C2 ;ST_MEM_2
DB #03 ;SUBTRACT
DB #E2 ;GET_MEM_2
DB #01 ;EXCHANGE
DB #C2 ;ST_MEM_2
DB #02 ;DELETE
DB #38 ;END_CALC
LD A,(HL)
AND A
JR NZ,PF_LARGE
CALL INT_FETCH
LD B,#10
LD A,D
AND A
JR NZ,PF_SAVE
OR E
JR Z,PF_SMALL
LD D,E
LD B,#08
PF_SAVE: PUSH DE
EXX
POP DE
EXX
JR PF_BITS
PF_SMALL: RST #28 ;FP_CALC
DB #E2 ;GET_MEM_2
DB #38 ;END_CALC
LD A,(HL)
SUB #7E
CALL LOG_2_A
LD D,A
LD A,(#5CAC)
SUB D
LD (#5CAC),A
LD A,D
CALL E_TO_FP
RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #27 ;21
DB #C1 ;ST_MEM_1
DB #03 ;SUBTRACT
DB #E1 ;GET_MEM_1
DB #38 ;END_CALC
CALL FP_TO_A
PUSH HL
LD (#5CA1),A
DEC A
RLA
SBC A,A
INC A
LD HL,#5CAB
LD (HL),A
INC HL
ADD A,(HL)
LD (HL),A
POP HL
JP PF_FRACTN
PF_LARGE: SUB #80
CP #1C
JR C,PF_MEDIUM
CALL LOG_2_A
SUB #07
LD B,A
LD HL,#5CAC
ADD A,(HL)
LD (HL),A
LD A,B
NEG
CALL E_TO_FP
JR PF_LOOP
PF_MEDIUM: EX DE,HL
CALL FETCH_TWO
EXX
SET 7,D
LD A,L
EXX
SUB #80
LD B,A
PF_BITS: SLA E
RL D
EXX
RL E
RL D
EXX
LD HL,#5CAA
LD C,#05
PF_BYTES: LD A,(HL)
ADC A,A
DAA
LD (HL),A
DEC HL
DEC C
JR NZ,PF_BYTES
DJNZ PF_BITS
XOR A
LD HL,#5CA6
LD DE,#5CA1
LD B,#09
RLD
LD C,#FF
PF_DIGITS: RLD
JR NZ,PF_INSERT
DEC C
INC C
JR NZ,PF_TEST_2
PF_INSERT: LD (DE),A
INC DE
INC (IY+#71)
INC (IY+#72)
LD C,#00
PF_TEST_2: BIT 0,B
JR Z,PF_ALL_9
INC HL
PF_ALL_9: DJNZ PF_DIGITS
LD A,(#5CAB)
SUB #09
JR C,PF_MORE
DEC (IY+#71)
LD A,#04
CP (IY+#6F)
JR PF_ROUND
PF_MORE: RST #28 ;FP_CALC
DB #02 ;DELETE
DB #E2 ;GET_MEM_2
DB #38 ;END_CALC
PF_FRACTN: EX DE,HL
CALL FETCH_TWO
EXX
LD A,#80
SUB L
LD L,#00
SET 7,D
EXX
CALL SHIFT_FP
PF_FRN_LP: LD A,(IY+#71)
CP #08
JR C,PF_FR_DGT
EXX
RL D
EXX
JR PF_ROUND
PF_FR_DGT: LD BC,#0200
PF_FR_EXX: LD A,E
CALL CA_10_A_C
LD E,A
LD A,D
CALL CA_10_A_C
LD D,A
PUSH BC
EXX
POP BC
DJNZ PF_FR_EXX
LD HL,#5CA1
LD A,C
LD C,(IY+#71)
ADD HL,BC
LD (HL),A
INC (IY+#71)
JR PF_FRN_LP
PF_ROUND: PUSH AF
LD HL,#5CA1
LD C,(IY+#71)
LD B,#00
ADD HL,BC
LD B,C
POP AF
PF_RND_LP: DEC HL
LD A,(HL)
ADC A,#00
LD (HL),A
AND A
JR Z,PF_R_BACK
CP #0A
CCF
JR NC,PF_COUNT
PF_R_BACK: DJNZ PF_RND_LP
LD (HL),#01
INC B
INC (IY+#72)
PF_COUNT: LD (IY+#71),B
RST #28 ;FP_CALC
DB #02 ;DELETE
DB #38 ;END_CALC
EXX
POP HL
EXX
LD BC,(#5CAB)
LD HL,#5CA1
LD A,B
CP #09
JR C,PF_NOT_E
CP #FC
JR C,PF_E_FRMT
PF_NOT_E: AND A
CALL Z,OUT_CODE
PF_E_SBRN: XOR A
SUB B
JP M,PF_OUT_LP
LD B,A
JR PF_DC_OUT
PF_OUT_LP: LD A,C
AND A
JR Z,PF_OUT_DT
LD A,(HL)
INC HL
DEC C
PF_OUT_DT: CALL OUT_CODE
DJNZ PF_OUT_LP
PF_DC_OUT: LD A,C
AND A
RET Z
INC B
LD A,#2E
PF_DEC_0: RST #10
LD A,#30
DJNZ PF_DEC_0
LD B,C
JR PF_OUT_LP
PF_E_FRMT: LD D,B
DEC D
LD B,#01
CALL PF_E_SBRN
LD A,#45
RST #10
LD C,D
LD A,C
AND A
JP P,PF_E_POS
NEG
LD C,A
LD A,#2D
JR PF_E_SIGN
PF_E_POS: LD A,#2B
PF_E_SIGN: RST #10
LD B,#00
JP OUT_NUM_1
; Handle printing of floating point
CA_10_A_C: PUSH DE
LD L,A
LD H,#00
LD E,L
LD D,H
ADD HL,HL
ADD HL,HL
ADD HL,DE
ADD HL,HL
LD E,C
ADD HL,DE
LD C,H
LD A,L
POP DE
RET
; Prepare the two numbers for addition
PREP_ADD: LD A,(HL)
LD (HL),#00
AND A
RET Z
INC HL
BIT 7,(HL)
SET 7,(HL)
DEC HL
RET Z
PUSH BC
LD BC,#0005
ADD HL,BC
LD B,C
LD C,A
SCF
NEG_BYTE: DEC HL
LD A,(HL)
CPL
ADC A,#00
LD (HL),A
DJNZ NEG_BYTE
LD A,C
POP BC
RET
; Fetch two numbers
FETCH_TWO: PUSH HL
PUSH AF
LD C,(HL)
INC HL
LD B,(HL)
LD (HL),A
INC HL
LD A,C
LD C,(HL)
PUSH BC
INC HL
LD C,(HL)
INC HL
LD B,(HL)
EX DE,HL
LD D,A
LD E,(HL)
PUSH DE
INC HL
LD D,(HL)
INC HL
LD E,(HL)
PUSH DE
EXX
POP DE
POP HL
POP BC
EXX
INC HL
LD D,(HL)
INC HL
LD E,(HL)
POP AF
POP HL
RET
; Shift floating point numer to right
SHIFT_FP: AND A
RET Z
CP #21
JR NC,ADDEND_0
PUSH BC
LD B,A
ONE_SHIFT: EXX
SRA L
RR D
RR E
EXX
RR D
RR E
DJNZ ONE_SHIFT
POP BC
RET NC
CALL ADD_BACK
RET NZ
ADDEND_0: EXX
XOR A
ZEROS_4_5: LD L,#00
LD D,A
LD E,L
EXX
LD DE,#0000
RET
; Add back any carry
ADD_BACK: INC E
RET NZ
INC D
RET NZ
EXX
INC E
JR NZ,ALL_ADDED
INC D
ALL_ADDED: EXX
RET
; Handle subtraction
SUBTRACT: EX DE,HL
CALL NEGATE
EX DE,HL
; Handle Addition
ADDITION: LD A,(DE)
OR (HL)
JR NZ,FULL_ADDN
PUSH DE
INC HL
PUSH HL
INC HL
LD E,(HL)
INC HL
LD D,(HL)
INC HL
INC HL
INC HL
LD A,(HL)
INC HL
LD C,(HL)
INC HL
LD B,(HL)
POP HL
EX DE,HL
ADD HL,BC
EX DE,HL
ADC A,(HL)
RRCA
ADC A,#00
CALL E65536
LD (HL),A
INC HL
LD (HL),E
INC HL
LD (HL),D
DEC HL
DEC HL
DEC HL
POP DE
RET
ADDN_OFLW: DEC HL
POP DE
FULL_ADDN: CALL RE_ST_TWO
EXX
PUSH HL
EXX
PUSH DE
PUSH HL
CALL PREP_ADD
LD B,A
EX DE,HL
CALL PREP_ADD
LD C,A
CP B
JR NC,SHIFT_LEN
LD A,B
LD B,C
EX DE,HL
SHIFT_LEN: PUSH AF
SUB B
CALL FETCH_TWO
CALL SHIFT_FP
POP AF
POP HL
LD (HL),A
PUSH HL
LD L,B
LD H,C
ADD HL,DE
EXX
EX DE,HL
ADC HL,BC
EX DE,HL
LD A,H
ADC A,L
LD L,A
RRA
XOR L
EXX
EX DE,HL
POP HL
RRA
JR NC,TEST_NEG
LD A,#01
CALL SHIFT_FP
INC (HL)
JR Z,ADD_REP_6
TEST_NEG: EXX
LD A,L
AND #80
EXX
INC HL
LD (HL),A
DEC HL
JR Z,GO_NC_MLT
LD A,E
NEG
CCF
LD E,A
LD A,D
CPL
ADC A,#00
LD D,A
EXX
LD A,E
CPL
ADC A,#00
LD E,A
LD A,D
CPL
ADC A,#00
JR NC,END_COMPL
RRA
EXX
INC (HL)
ADD_REP_6: JP Z,REPORT_6
EXX
END_COMPL: LD D,A
EXX
GO_NC_MLT: XOR A
JP TEST_NORM
; HL - HL * DE
HL_HL_DE: PUSH BC
LD B,#10
LD A,H
LD C,L
LD HL,#0000
HL_LOOP: ADD HL,HL
JR C,HL_END
RL C
RLA
JR NC,HL_AGAIN
ADD HL,DE
JR C,HL_END
HL_AGAIN: DJNZ HL_LOOP
HL_END: POP BC
RET
; Prepare to multiply or divide
PREP_M_D: CALL TEST_ZERO
RET C
INC HL
XOR (HL)
SET 7,(HL)
DEC HL
RET
; Handle multiplication
MULTIPLY: LD A,(DE)
OR (HL)
JR NZ,MULT_LONG
PUSH DE
PUSH HL
PUSH DE
CALL INT_FETCH
EX DE,HL
EX (SP),HL
LD B,C
CALL INT_FETCH
LD A,B
XOR C
LD C,A
POP HL
CALL HL_HL_DE
EX DE,HL
POP HL
JR C,MULT_OFLW
LD A,D
OR E
JR NZ,MULT_RSLT
LD C,A
MULT_RSLT: CALL INT_STORE
POP DE
RET
MULT_OFLW: POP DE
MULT_LONG: CALL RE_ST_TWO
XOR A
CALL PREP_M_D
RET C
EXX
PUSH HL
EXX
PUSH DE
EX DE,HL
CALL PREP_M_D
EX DE,HL
JR C,ZERO_RSLT
PUSH HL
CALL FETCH_TWO
LD A,B
AND A
SBC HL,HL
EXX
PUSH HL
SBC HL,HL
EXX
LD B,#21
JR STRT_MLT
MLT_LOOP: JR NC,NO_ADD
ADD HL,DE
EXX
ADC HL,DE
EXX
NO_ADD: EXX
RR H
RR L
EXX
RR H
RR L
STRT_MLT: EXX
RR B
RR C
EXX
RR C
RRA
DJNZ MLT_LOOP
EX DE,HL
EXX
EX DE,HL
EXX
POP BC
POP HL
LD A,B
ADD A,C
JR NZ,MAKE_EXPT
AND A
MAKE_EXPT: DEC A
CCF
DIVN_EXPT: RLA
CCF
RRA
JP P,OFLW1_CLR
JR NC,REPORT_6
AND A
OFLW1_CLR: INC A
JR NZ,OFLW2_CLR
JR C,OFLW2_CLR
EXX
BIT 7,D
EXX
JR NZ,REPORT_6
OFLW2_CLR LD (HL),A
EXX
LD A,B
EXX
TEST_NORM: JR NC,NORMALISE
LD A,(HL)
AND A
NEAR_ZERO: LD A,#80
JR Z,SKIP_ZERO
ZERO_RSLT: XOR A
SKIP_ZERO: EXX
AND D
CALL ZEROS_4_5
RLCA
LD (HL),A
JR C,OFLOW_CLR
INC HL
LD (HL),A
DEC HL
JR OFLOW_CLR
NORMALISE: LD B,#20
SHIFT_ONE: EXX
BIT 7,D
EXX
JR NZ,NORML_NOW
RLCA
RL E
RL D
EXX
RL E
RL D
EXX
DEC (HL)
JR Z,NEAR_ZERO
DJNZ SHIFT_ONE
JR ZERO_RSLT
NORML_NOW: RLA
JR NC,OFLOW_CLR
CALL ADD_BACK
JR NZ,OFLOW_CLR
EXX
LD D,#80
EXX
INC (HL)
JR Z,REPORT_6
OFLOW_CLR: PUSH HL
INC HL
EXX
PUSH DE
EXX
POP BC
LD A,B
RLA
RL (HL)
RRA
LD (HL),A
INC HL
LD (HL),C
INC HL
LD (HL),D
INC HL
LD (HL),E
POP HL
POP DE
EXX
POP HL
EXX
RET
REPORT_6: RST #08 ; Error report
DB #05 ; Number too big
; Handle division
DIVISION: CALL RE_ST_TWO
EX DE,HL
XOR A
CALL PREP_M_D
JR C,REPORT_6
EX DE,HL
CALL PREP_M_D
RET C
EXX
PUSH HL
EXX
PUSH DE
PUSH HL
CALL FETCH_TWO
EXX
PUSH HL
LD H,B
LD L,C
EXX
LD H,C
LD L,B
XOR A
LD B,#DF
JR DIV_START
DIV_LOOP: RLA
RL C
EXX
RL C
RL B
EXX
DIV_34TH: ADD HL,HL
EXX
ADC HL,HL
EXX
JR C,SUBN_ONLY
DIV_START: SBC HL,DE
EXX
SBC HL,DE
EXX
JR NC,NO_RSTORE
ADD HL,DE
EXX
ADC HL,DE
EXX
AND A
JR COUNT_ONE
SUBN_ONLY: AND A
SBC HL,DE
EXX
SBC HL,DE
EXX
NO_RSTORE: SCF
COUNT_ONE: INC B
JP M,DIV_LOOP
PUSH AF
JR Z,DIV_34TH ; BSROM - bugfix - was DIV_START
LD E,A
LD D,C
EXX
LD E,C
LD D,B
POP AF
RR B
POP AF
RR B
EXX
POP BC
POP HL
LD A,B
SUB C
JP DIVN_EXPT
; Integer truncation towards zero
TRUNCATE: LD A,(HL)
AND A
RET Z
CP #81
JR NC,T_GR_ZERO ; BSROM - bugfixed INT
LD (HL),#00
LD A,#20
JR NIL_BYTES
E65536: JR NZ,S65536
SBC A,A
LD C,A
INC A
OR D
OR E
LD A,C
RET NZ
S65536: POP AF
JP ADDN_OFLW
NEW_CHR: CALL FP_TO_A ; BSROM - bugfixed CHR$
RET C
RET Z
POP AF
LD DE,#0001
LD BC,#FFFF
JP CHR_DLR1
T_GR_ZERO: CP #91 ; BSROM - modified INT
T_SMALL: JR NC,X_LARGE
PUSH DE
CPL
ADD A,#91
INC HL
LD D,(HL)
INC HL
LD E,(HL)
DEC HL
DEC HL
LD C,#00
BIT 7,D
JR Z,T_NUMERIC
DEC C
T_NUMERIC: SET 7,D
LD B,#08
SUB B
ADD A,B
JR C,T_TEST
LD E,D
LD D,#00
SUB B
T_TEST: JR Z,T_STORE
LD B,A
T_SHIFT: SRL D
RR E
DJNZ T_SHIFT
T_STORE: CALL INT_STORE
POP DE
RET
T_EXPNENT: LD A,(HL)
X_LARGE: SUB #A0
RET P
NEG
NIL_BYTES: PUSH DE
EX DE,HL
DEC HL
LD B,A
SRL B
SRL B
SRL B
JR Z,BITS_ZERO
BYTE_ZERO: LD (HL),#00
DEC HL
DJNZ BYTE_ZERO
BITS_ZERO: AND #07
JR Z,IX_END
LD B,A
LD A,#FF
LESS_MASK: SLA A
DJNZ LESS_MASK
AND (HL)
LD (HL),A
IX_END: EX DE,HL
POP DE
RET
; Re-stack two numbers in full floating point
RE_ST_TWO: CALL RESTK_SUB
RESTK_SUB: EX DE,HL
; Re-stack number in full form
RE_STACK: LD A,(HL)
AND A
RET NZ
PUSH DE
CALL INT_FETCH
XOR A
INC HL
LD (HL),A
DEC HL
LD (HL),A
LD B,#91
LD A,D
AND A
JR NZ,RS_NRMLSE
OR E
LD B,D
JR Z,RS_STORE
LD D,E
LD E,B
LD B,#89
RS_NRMLSE: EX DE,HL
RSTK_LOOP: DEC B
ADD HL,HL
JR NC,RSTK_LOOP
RRC C
RR H
RR L
EX DE,HL
RS_STORE: DEC HL
LD (HL),E
DEC HL
LD (HL),D
DEC HL
LD (HL),B
POP DE
RET
; Floating point calculator
; Table of constants
STK_ZERO: DB #00
DB #B0
DB #00
STK_ONE: DB #40
DB #B0
DB #00
DB #01
STK_HALF: DB #30
DB #00
STK_PI_2: DB #F1
DB #49
DB #0F
DB #DA
DB #A2
STK_TEN: DB #40
DB #B0
DB #00
DB #0A
; Floating point calculator
; Table of addresses
TBL_ADDRS: DW JUMP_TRUE
DW EXCHANGE
DW DELETE
DW SUBTRACT
DW MULTIPLY
DW DIVISION
DW TO_POWER
DW OR_FUNC
DW NO_AND_NO
DW NO_L_EQL
DW NO_GR_EQL
DW NOS_NEQL
DW NO_GRTR
DW NO_LESS
DW NOS_EQL
DW ADDITION
DW STR_AND_NO
DW STR_L_EQL
DW STR_GR_EQL
DW STRS_NEQL
DW STR_GRTR
DW STR_LESS
DW STRS_EQL
DW STRS_ADD
DW VAL_DLR
DW USR_STR
DW READ_IN
DW NEGATE
DW CODE
DW VAL
DW LEN
DW SIN_FUNC
DW COS_FUNC
DW TAN_FUNC
DW ASN_FUNC
DW ACS_FUNC
DW ATN_FUNC
DW LN
DW EXP
DW INT
DW SQR_FUNC
DW SGN
DW ABS
DW PEEK
DW IN_FUNC
DW USR_NO
DW STR_DLR
DW CHR_DLR
DW NOT_FUNC
DW DUPLICATE
DW N_MOD_M
DW JUMP
DW STK_DATA
DW DEC_JR_NZ
DW LESS_0
DW GREATER_0
DW END_CALC
DW GET_ARGT
DW TRUNCATE
DW FP_CALC_2
DW E_TO_FP
DW RE_STACK
DW SERIES_XX
DW STK_CONST_XX
DW ST_MEM_XX
DW GET_MEM_XX
; The Calculator
CALCULATE: CALL STK_PNTRS
GEN_ENT_1: LD A,B
LD (#5C67),A
GEN_ENT_2: EXX
EX (SP),HL
EXX
RE_ENTRY: LD (#5C65),DE
EXX
LD A,(HL)
INC HL
SCAN_ENT: PUSH HL
AND A
JP P,FIRST_3D
LD D,A
AND #60
RRCA
RRCA
RRCA
RRCA
ADD A,#7C
LD L,A
LD A,D
AND #1F
JR ENT_TABLE
FIRST_3D: CP #18
JR NC,DOUBLE_A
EXX
LD BC,#FFFB
LD D,H
LD E,L
ADD HL,BC
EXX
DOUBLE_A: RLCA
LD L,A
ENT_TABLE: LD DE,TBL_ADDRS
LD H,#00
ADD HL,DE
LD E,(HL)
INC HL
LD D,(HL)
LD HL,RE_ENTRY
EX (SP),HL
PUSH DE
EXX
LD BC,(#5C66)
; Handle DELETE
DELETE: RET
; Single operation
FP_CALC_2: POP AF
LD A,(#5C67)
EXX
JR SCAN_ENT
; Test that there is enough space between the calc stack and the machine stack
TEST_5_SP: PUSH DE
PUSH HL
LD BC,#0005
CALL TEST_ROOM
POP HL
POP DE
RET
; Stack floating point number, numeric variable value or an entry in the BEEP's semi-tone table
STACK_NUM: LD DE,(#5C65)
CALL MOVE_FP
LD (#5C65),DE
RET
; Move a floating point number
DUPLICATE:
MOVE_FP: CALL TEST_5_SP
LDIR
RET
; Stack literals
STK_DATA: LD H,D
LD L,E
STK_CONST: CALL TEST_5_SP
EXX
PUSH HL
EXX
EX (SP),HL
PUSH BC
LD A,(HL)
AND #C0
RLCA
RLCA
LD C,A
INC C
LD A,(HL)
AND #3F
JR NZ,FORM_EXP
INC HL
LD A,(HL)
FORM_EXP: ADD A,#50
LD (DE),A
LD A,#05
SUB C
INC HL
INC DE
LD B,#00
LDIR
POP BC
EX (SP),HL
EXX
POP HL
EXX
LD B,A
XOR A
STK_ZEROS: DEC B
RET Z
LD (DE),A
INC DE
JR STK_ZEROS
; Skip constants
SKIP_CONS: AND A
SKIP_NEXT: RET Z
PUSH AF
PUSH DE
CALL NO_RW_AT0 ; BSROM - fix for rewriting first bytes of ROM
CALL STK_CONST
POP DE
POP AF
DEC A
JR SKIP_NEXT
; Calculate memory location
LOC_MEM: LD C,A
RLCA
RLCA
ADD A,C
LD C,A
LD B,#00
ADD HL,BC
RET
; Get from memory area
GET_MEM_XX: PUSH DE
LD HL,(#5C68)
CALL LOC_MEM
CALL MOVE_FP
POP HL
RET
; Stack a constant
STK_CONST_XX: LD H,D
LD L,E
EXX
PUSH HL
LD HL,STK_ZERO
EXX
CALL SKIP_CONS
CALL STK_CONST
EXX
POP HL
EXX
RET
; Store in a memory area
ST_MEM_XX: PUSH HL
EX DE,HL
LD HL,(#5C68)
CALL LOC_MEM
EX DE,HL
CALL MOVE_FP
EX DE,HL
POP HL
RET
; Swap first number with second number
EXCHANGE: LD B,#05
SWAP_BYTE: LD A,(DE)
LD C,(HL)
EX DE,HL
LD (DE),A
LD (HL),C
INC HL
INC DE
DJNZ SWAP_BYTE
EX DE,HL
RET
; Series generator
SERIES_XX: LD B,A
CALL GEN_ENT_1
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #A0 ;STK_ZERO
DB #C2 ;ST_MEM_2
G_LOOP: DB #31 ;DUPLICATE
DB #E0 ;GET_MEM_0
DB #04 ;MULTIPLY
DB #E2 ;GET_MEM_2
DB #C1 ;ST_MEM_1
DB #03 ;SUBTRACT
DB #38 ;END_CALC
CALL STK_DATA
CALL GEN_ENT_2
DB #0F ;ADDITION
DB #01 ;EXCHANGE
DB #C2 ;ST_MEM_2
DB #02 ;DELETE
DB #35 ;DEC_JR_NZ
DB #EE ;back to G_LOOP
DB #E1 ;GET_MEM_1
DB #03 ;SUBTRACT
DB #38 ;END_CALC
RET
; Find the absolute value of the last value, integer or floating point on the calc stack
ABS: LD B,#FF
JR NEG_TEST
; Handle unary minus
NEGATE: CALL TEST_ZERO
RET C
LD B,#00
NEG_TEST: LD A,(HL)
AND A
JR Z,INT_CASE
INC HL
LD A,B
AND #80
OR (HL)
RLA
CCF
RRA
LD (HL),A
DEC HL
RET
INT_CASE: PUSH DE
PUSH HL
CALL INT_FETCH
POP HL
LD A,B
OR C
CPL
LD C,A
CALL INT_STORE
POP DE
RET
; Signum
SGN: CALL TEST_ZERO
RET C
PUSH DE
LD DE,#0001
INC HL
RL (HL)
DEC HL
SBC A,A
LD C,A
CALL INT_STORE
POP DE
RET
; Handle IN function
IN_FUNC: CALL FIND_INT2
IN A,(C)
JR IN_PK_STK
; Handle PEEK function
PEEK: CALL FIND_INT2
LD A,(BC)
IN_PK_STK: JP STACK_A
; Handle USR number
USR_NO: CALL FIND_INT2
LD HL,STACK_BC
PUSH HL
PUSH BC
RET
; Handle USR string
USR_STR: CALL STK_FETCH
DEC BC
LD A,B
OR C
JR NZ,REPORT_A
LD A,(DE)
CALL ALPHA
JR C,USR_RANGE
SUB #90
JR C,REPORT_A
CP #15
JR NC,REPORT_A
INC A
USR_RANGE: DEC A
ADD A,A
ADD A,A
ADD A,A
CP #A8
JR NC,REPORT_A
LD BC,(#5C7B)
ADD A,C
LD C,A
JR NC,USR_STACK
INC B
USR_STACK: JP STACK_BC
REPORT_A: RST #08 ; Error report
DB #09 ; Invalid argument
; Test if top value on calc stack is zero
TEST_ZERO: PUSH HL
PUSH BC
LD B,A
LD A,(HL)
INC HL
OR (HL)
INC HL
OR (HL)
INC HL
OR (HL)
LD A,B
POP BC
POP HL
RET NZ
SCF
RET
; Test if the last value on calc stack is greater than zero
GREATER_0: CALL TEST_ZERO
RET C
LD A,#FF
JR SIGN_TO_C
; Handle NOT operator
NOT_FUNC: CALL TEST_ZERO
JR FP_0_1
; Test if the last value on calc stack is less than zero
LESS_0: XOR A
SIGN_TO_C: INC HL
XOR (HL)
DEC HL
RLCA
; Place an iteger value zero or one at the calc stack or memory area
FP_0_1: PUSH HL
LD A,#00
LD (HL),A
INC HL
LD (HL),A
INC HL
RLA
LD (HL),A
RRA
INC HL
LD (HL),A
INC HL
LD (HL),A
POP HL
RET
; Handle OR operator
OR_FUNC: EX DE,HL
CALL TEST_ZERO
EX DE,HL
RET C
SCF
JR FP_0_1
; Handle number AND number
NO_AND_NO: EX DE,HL
CALL TEST_ZERO
EX DE,HL
RET NC
AND A
JR FP_0_1
; Handle string AND number
STR_AND_NO: EX DE,HL
CALL TEST_ZERO
EX DE,HL
RET NC
PUSH DE
DEC DE
XOR A
LD (DE),A
DEC DE
LD (DE),A
POP DE
RET
; Perform numeric or string comparison
NO_L_EQL:
NO_GR_EQL:
NOS_NEQL:
NO_GRTR:
NO_LESS:
NOS_EQL:
STR_L_EQL:
STR_GR_EQL:
STRS_NEQL:
STR_GRTR:
STR_LESS:
STRS_EQL: LD A,B
SUB #08
BIT 2,A
JR NZ,EX_OR_NOT
DEC A
EX_OR_NOT: RRCA
JR NC,NU_OR_STR
PUSH AF
PUSH HL
CALL EXCHANGE
POP DE
EX DE,HL
POP AF
NU_OR_STR: BIT 2,A
JR NZ,STRINGS
RRCA
PUSH AF
CALL SUBTRACT
JR END_TESTS
STRINGS: RRCA
PUSH AF
CALL STK_FETCH
PUSH DE
PUSH BC
CALL STK_FETCH
POP HL
BYTE_COMP: LD A,H
OR L
EX (SP),HL
LD A,B
JR NZ,SEC_PLUS
OR C
SECND_LOW: POP BC
JR Z,BOTH_NULL
POP AF
CCF
JR STR_TEST
BOTH_NULL: POP AF
JR STR_TEST
SEC_PLUS: OR C
JR Z,FRST_LESS
LD A,(DE)
SUB (HL)
JR C,FRST_LESS
JR NZ,SECND_LOW
DEC BC
INC DE
INC HL
EX (SP),HL
DEC HL
JR BYTE_COMP
FRST_LESS: POP BC
POP AF
AND A
STR_TEST: PUSH AF
RST #28 ;FP_CALC
DB #A0 ;STK_ZERO
DB #38 ;END_CALC
END_TESTS: POP AF
PUSH AF
CALL C,NOT_FUNC
POP AF
PUSH AF
CALL NC,GREATER_0
POP AF
RRCA
CALL NC,NOT_FUNC
RET
; Combine two strings into one
STRS_ADD: CALL STK_FETCH
PUSH DE
PUSH BC
CALL STK_FETCH
POP HL
PUSH HL
PUSH DE
PUSH BC
ADD HL,BC
LD B,H
LD C,L
RST #30
CALL STK_STO_D
POP BC
POP HL
LD A,B
OR C
JR Z,OTHER_STR
LDIR
OTHER_STR: POP BC
POP HL
LD A,B
OR C
JR Z,STK_PNTRS
LDIR
; Check stack pointers
STK_PNTRS: LD HL,(#5C65)
LD DE,#FFFB
PUSH HL
ADD HL,DE
POP DE
RET
; Handle CHR$
CHR_DLR: CALL NEW_CHR ;BSROM - bugfixed CHR$
JR C,REPORT_BD
JR NZ,REPORT_BD
PUSH AF
LD BC,#0001
RST #30
POP AF
LD (DE),A
CHR_DLR1: CALL STK_STO_D
EX DE,HL
RET
REPORT_BD: RST #08 ; Error report
DB #0A ; Integer out of range
; Handle VAL and VAL$
VAL:
VAL_DLR: CALL VAL2 ; BSROM - enhanced VAL & VAL$
PUSH HL
LD A,B
ADD A,#E3
SBC A,A
PUSH AF
CALL STK_FETCH
PUSH DE
INC BC
RST #30
POP HL
LD (#5C5D),DE
PUSH DE
LDIR
EX DE,HL
DEC HL
LD (HL),#0D
RES 7,(IY+#01)
CALL SCANNING
RST #18
CP #0D
JR NZ,V_RPORT_C
POP HL
POP AF
XOR (IY+#01)
AND #40
V_RPORT_C: JP NZ,REPORT_C
LD (#5C5D),HL
SET 7,(IY+#01)
CALL SCANNING
POP HL
LD (#5C5D),HL
JR STK_PNTRS
; Handle STR$
STR_DLR: LD BC,#0001
RST #30
LD (#5C5B),HL
PUSH HL
LD HL,(#5C51)
PUSH HL
LD A,#FF
CALL CHAN_OPEN
CALL PRINT_FP
POP HL
CALL CHAN_FLAG
POP DE
LD HL,(#5C5B)
AND A
SBC HL,DE
LD B,H
LD C,L
CALL STK_STO_D
EX DE,HL
RET
; Read in for INKEY$
READ_IN: CALL FIND_INT1
CP #10
JP NC,REPORT_BB
LD HL,(#5C51)
PUSH HL
CALL CHAN_OPEN
CALL INPUT_AD
LD BC,#0000
JR NC,R_I_STORE
INC C
RST #30
LD (DE),A
R_I_STORE: CALL STK_STO_D
POP HL
CALL CHAN_FLAG
JP STK_PNTRS
; Handle CODE
CODE: CALL STK_FETCH
LD A,B
OR C
JR Z,STK_CODE
LD A,(DE)
STK_CODE JP STACK_A
; Handle LEN
LEN: CALL STK_FETCH
JP STACK_BC
; Decrease the counter
DEC_JR_NZ: EXX
PUSH HL
LD HL,#5C67
DEC (HL)
POP HL
JR NZ,JUMP_2
INC HL
EXX
RET
; Relative jump
JUMP: EXX
JUMP_2: LD E,(HL)
LD A,E
RLA
SBC A,A
LD D,A
ADD HL,DE
EXX
RET
; Jump on true
JUMP_TRUE: INC DE
INC DE
LD A,(DE)
DEC DE
DEC DE
AND A
JR NZ,JUMP
EXX
INC HL
EXX
RET
; End of calculation
END_CALC: POP AF
EXX
EX (SP),HL
EXX
RET
; Modulus
N_MOD_M: RST #28 ;FP_CALC
DB #C0 ;ST_MEM_0
DB #02 ;DELETE
DB #31 ;DUPLICATE
DB #E0 ;GET_MEM_0
DB #05 ;DIVISION
DB #27 ;INT
DB #E0 ;GET_MEM_0
DB #01 ;EXCHANGE
DB #C0 ;ST_MEM_0
DB #04 ;MULTIPLY
DB #03 ;SUBTRACT
DB #E0 ;GET_MEM_0
DB #38 ;END_CALC
RET
; Handle INT
INT: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #36 ;LESS_0
DB #00 ;JUMP_TRUE
DB #04 ;to X_NEG
DB #3A ;TRUNCATE
DB #38 ;END_CALC
RET
X_NEG: DB #31 ;DUPLICATE
DB #3A ;TRUNCATE
DB #C0 ;ST_MEM_0
DB #03 ;SUBTRACT
DB #E0 ;GET_MEM_0
DB #01 ;EXCHANGE
DB #30 ;NOT
DB #00 ;JUMP_TRUE
DB #03 ;to EXIT
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
EXIT: DB #38 ;END_CALC
RET
; Exponential
EXP: RST #28 ;FP_CALC
DB #3D ;RE_STACK
DB #34 ;STK_DATA
DB #F1 ;Exponent
DB #38 ;
DB #AA ;
DB #3B ;
DB #29 ;
DB #04 ;MULTIPLY
DB #31 ;DUPLICATE
DB #27 ;INT
DB #C3 ;ST_MEM_3
DB #03 ;SUBTRACT
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #88 ;SERIES_08
DB #13 ;Exponent
DB #36 ;
DB #58 ;Exponent
DB #65 ;
DB #66 ;
DB #9D ;Exponent
DB #78 ;
DB #65 ;
DB #40 ;
DB #A2 ;Exponent
DB #60 ;
DB #32 ;
DB #C9 ;
DB #E7 ;Exponent
DB #21 ;
DB #F7 ;
DB #AF ;
DB #24 ;
DB #EB ;Exponent
DB #2F ;
DB #B0 ;
DB #B0 ;
DB #14 ;
DB #EE ;Exponent
DB #7E ;
DB #BB ;
DB #94 ;
DB #58 ;
DB #F1 ;Exponent
DB #3A ;
DB #7E ;
DB #F8 ;
DB #CF ;
DB #E3 ;GET_MEM_3
DB #38 ;END-CALC
CALL FP_TO_A
JR NZ,N_NEGTV
JR C,REPORT_6B
ADD A,(HL)
JR NC,RESULT_OK
REPORT_6B: RST #08 ; Error report
DB #05 ; Number too big
N_NEGTV: JR C,RSLT_ZERO
SUB (HL)
JR NC,RSLT_ZERO
NEG
RESULT_OK: LD (HL),A
RET
RSLT_ZERO: RST #28 ;FP_CALC
DB #02 ;DELETE
DB #A0 ;STK_ZERO
DB #38 ;END_CALC
RET
; Natural logarithm
LN: RST #28 ;FP_CALC
DB #3D ;RE_STACK
DB #31 ;DUPLICATE
DB #37 ;GREATER_0
DB #00 ;JUMP_TRUE
DB #04 ;to VALID
DB #38 ;END_CALC
REPORT_AB: RST #08 ; Error report
DB #09 ; Invalid argument
VALID: DB #A0 ;STK_ZERO
DB #02 ;DELETE
DB #38 ;END_CALC
LD A,(HL)
LD (HL),#80
CALL STACK_A
RST #28 ;FP_CALC
DB #34 ;STK_DATA
DB #38 ;Exponent
DB #00 ;
DB #03 ;SUBTRACT
DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #34 ;STK_DATA
DB #F0 ;Exponent
DB #4C ;
DB #CC ;
DB #CC ;
DB #CD ;
DB #03 ;SUBTRACT
DB #37 ;GREATER_0
DB #00 ;JUMP_TURE
DB #08 ;to GRE_8
DB #01 ;EXCHANGE
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #01 ;EXCHANGE
DB #38 ;END_CALC
INC (HL)
RST #28 ;FP_CALC
GRE_8: DB #01 ;EXCHANGE
DB #34 ;STK_DATA
DB #F0 ;Exponent
DB #31 ;
DB #72 ;
DB #17 ;
DB #F8 ;
DB #04 ;MULTIPLY
DB #01 ;EXCHANGE
DB #A2 ;STK_HALF
DB #03 ;SUBTRACT
DB #A2 ;STK_HALF
DB #03 ;SUBTRACT
DB #31 ;DUPLICATE
DB #34 ;STK_DATA
DB #32 ;Exponent
DB #20 ;
DB #04 ;MULTIPLY
DB #A2 ;STK_HALF
DB #03 ;SUBTRACT
DB #8C ;SERIES_0C
DB #11 ;Exponent
DB #AC ;
DB #14 ;Exponent
DB #09 ;
DB #56 ;Exponent
DB #DA ;
DB #A5 ;
DB #59 ;Exponent
DB #30 ;
DB #C5 ;
DB #5C ;Exponent
DB #90 ;
DB #AA ;
DB #9E ;Exponent
DB #70 ;
DB #6F ;
DB #61 ;
DB #A1 ;Exponent
DB #CB ;
DB #DA ;
DB #96 ;
DB #A4 ;Exponent
DB #31 ;
DB #9F ;
DB #B4 ;
DB #E7 ;Exponent
DB #A0 ;
DB #FE ;
DB #5C ;
DB #FC ;
DB #EA ;Exponent
DB #1B ;
DB #43 ;
DB #CA ;
DB #36 ;
DB #ED ;Exponent
DB #A7 ;
DB #9C ;
DB #7E ;
DB #5E ;
DB #F0 ;Exponent
DB #6E ;
DB #23 ;
DB #80 ;
DB #93 ;
DB #04 ;MULTIPLY
DB #0F ;ADDITION
DB #38 ;END_CALC
RET
; Reduce argument
GET_ARGT: RST #28 ;FP_CALC
DB #3D ;RE_STACK
DB #34 ;STK_DATA
DB #EE ;Exponent
DB #22 ;
DB #F9 ;
DB #83 ;
DB #6E ;
DB #04 ;MULTIPLY
DB #31 ;DUPLICATE
DB #A2 ;STK_HALF
DB #0F ;ADDITION
DB #27 ;INT
DB #03 ;SUBTRACT
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #31 ;DUPLICATE
DB #2A ;ABS
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #31 ;DUPLICATE
DB #37 ;GREATER_0
DB #C0 ;ST-MEM-0
DB #00 ;JUMP_TRUE
DB #04 ;to ZPLUS
DB #02 ;DELETE
DB #38 ;END_CALC
RET
ZPLUS: DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #01 ;EXCHANGE
DB #36 ;LESS_0
DB #00 ;JUMP_TRUE
DB #02 ;to YNEG
DB #1B ;NEGATE
YNEG: DB #38 ;END_CALC
RET
; Handle cosine
COS_FUNC: RST #28 ;FP_CALC
DB #39 ;GET_ARGT
DB #2A ;ABS
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #E0 ;GET-MEM-0
DB #00 ;JUMP_TRUE
DB #06 ;fwd to C_ENT
DB #1B ;NEGATE
DB #33 ;jump
DB #03 ;fwd to C_ENT
; Handle sine
SIN_FUNC: RST #28 ;FP_CALC
DB #39 ;GET_ARGT
C_ENT: DB #31 ;DUPLICATE
DB #31 ;DUPLICATE
DB #04 ;MULTIPLY
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #86 ;SERIES-06
DB #14 ;Exponent
DB #E6 ;
DB #5C ;Exponent
DB #1F ;
DB #0B ;
DB #A3 ;Exponent
DB #8F ;
DB #38 ;
DB #EE ;
DB #E9 ;Exponent
DB #15 ;
DB #63 ;
DB #BB ;
DB #23 ;
DB #EE ;Exponent
DB #92 ;
DB #0D ;
DB #CD ;
DB #ED ;
DB #F1 ;Exponent
DB #23 ;
DB #5D ;
DB #1B ;
DB #EA ;
DB #04 ;MULTIPLY
DB #38 ;END_CALC
RET
; Handle tangent
TAN_FUNC: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #1F ;SIN
DB #01 ;EXCHANGE
DB #20 ;COS
DB #05 ;DIVISION
DB #38 ;END_CALC
RET
; Handle arctan
ATN_FUNC: CALL RE_STACK
LD A,(HL)
CP #81
JR C,SMALL
RST #28 ;FP_CALC
DB #A1 ;STK_ONE
DB #1B ;NEGATE
DB #01 ;EXCHANGE
DB #05 ;DIVISION
DB #31 ;DUPLICATE
DB #36 ;LESS_0
DB #A3 ;STK_PI_2
DB #01 ;EXCHANGE
DB #00 ;JUMP_TRUE
DB #06 ;to CASES
DB #1B ;NEGATE
DB #33 ;jump
DB #03 ;to CASES
SMALL: RST #28 ;FP_CALC
DB #A0 ;STK_ZERO
CASES: DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #31 ;DUPLICATE
DB #04 ;MULTIPLY
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #8C ;SERIES_0C
DB #10 ;Exponent
DB #B2 ;
DB #13 ;Exponent
DB #0E ;
DB #55 ;Exponent
DB #E4 ;
DB #8D ;
DB #58 ;Exponent
DB #39 ;
DB #BC ;
DB #5B ;Exponent
DB #98 ;
DB #FD ;
DB #9E ;Exponent
DB #00 ;
DB #36 ;
DB #75 ;
DB #A0 ;Exponent
DB #DB ;
DB #E8 ;
DB #B4 ;
DB #63 ;Exponent
DB #42 ;
DB #C4 ;
DB #E6 ;Exponent
DB #B5 ;
DB #09 ;
DB #36 ;
DB #BE ;
DB #E9 ;Exponent
DB #36 ;
DB #73 ;
DB #1B ;
DB #5D ;
DB #EC ;Exponent
DB #D8 ;
DB #DE ;
DB #63 ;
DB #BE ;
DB #F0 ;Exponent
DB #61 ;
DB #A1 ;
DB #B3 ;
DB #0C ;
DB #04 ;MULTIPLY
DB #0F ;ADDITION
DB #38 ;END_CALC
RET
; Handle arcsin
ASN_FUNC: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #31 ;DUPLICATE
DB #04 ;MULTIPLY
DB #A1 ;STK_ONE
DB #03 ;SUBTRACT
DB #1B ;NEGATE
DB #28 ;SQR
DB #A1 ;STK_ONE
DB #0F ;ADDITION
DB #05 ;DIVISION
DB #24 ;ATN
DB #31 ;DUPLICATE
DB #0F ;ADDITION
DB #38 ;END_CALC
RET
; Handle arccos
ACS_FUNC: RST #28 ;FP_CALC
DB #22 ;ASN
DB #A3 ;STK_PI_2
DB #03 ;SUBTRACT
DB #1B ;NEGATE
DB #38 ;END_CALC
RET
; Handle square root
SQR_FUNC: RST #28 ;FP_CALC
DB #31 ;DUPLICATE
DB #30 ;NOT
DB #00 ;JUMP_TRUE
DB #1E ;to LAST
DB #A2 ;STK_HALF
DB #38 ;END_CALC
; Handle exponential
TO_POWER: RST #28 ;FP_CALC
DB #01 ;EXCHANGE
DB #31 ;DUPLICATE
DB #30 ;NOT
DB #00 ;JUMP_TRUE
DB #07 ;to XISO
DB #25 ;LN
DB #04 ;MULTIPLY
DB #38 ;END_CALC
JP EXP
XISO: DB #02 ;DELETE
DB #31 ;DUPLICATE
DB #30 ;NOT
DB #00 ;JUMP_TRUE
DB #09 ;to ONE
DB #A0 ;STK_ZERO
DB #01 ;EXCHANGE
DB #37 ;GREATER_0
DB #00 ;JUMP_TRUE
DB #06 ;to LAST
DB #A1 ;STK_ONE
DB #01 ;EXCHANGE
DB #05 ;DIVISION
ONE: DB #02 ;DELETE
DB #A1 ;STK_ONE
LAST: DB #38 ;END_CALC
RET
; BSROM additional routines
; Input of HEX numbers
HEXA: LD HL,SCAN_FUNC
CP #25
RET NZ
POP AF
CALL SYNTAX_Z
JP NZ,S_STK_DEC
LD DE,#0000
HEX1: RST #20
CALL ALPHANUM
JR NC,HEXEND
CP #41
JR C,CIS
OR #20
CP #67
JR NC,HEXEND
SUB #27
CIS: AND #0F
LD C,A
LD A,D
AND #F0
JP NZ,REPORT_6
LD A,C
EX DE,HL
ADD HL,HL
ADD HL,HL
ADD HL,HL
ADD HL,HL
OR L
LD L,A
EX DE,HL
JR HEX1
HEXEND: CALL BIN_END
JP S_BIN_1
; Allow number in VAL$ and VAL
VAL1: CP #18
RET Z
CP #9D
RET Z
XOR (IY+#01)
RET
; Evaluation of VAL and VAL$
VAL2: LD HL,(#5C5D)
BIT 6,(IY+#01)
RET Z
POP AF
PUSH BC
CALL FIND_INT2
POP AF
RRCA
JR NC,DOLAR
LD H,B
LD L,C
LD C,(HL)
INC HL
LD B,(HL)
JP STACK_BC
DOLAR: PUSH BC
LD BC,#0004
RST #30
POP HL
PUSH DE
LD A,H
CALL HEX99
LD A,L
CALL HEX99
POP DE
JP CHR_DLR1
; Hex numbers
HEX99: PUSH AF
RRCA
RRCA
RRCA
RRCA
CALL HEX98
POP AF
HEX98: AND #0F
OR #30
CP #3A
JR C,HEX98_1
ADD A,#27
HEX98_1: LD (DE),A
INC DE
RET
INFSUB: LD DE,COPYRIGHT+5
CALL PO_TOKENS1
JP HLO
MM: DW #FFFF
USERJP: JP #0052
DISKTOOLS: DW #0052
; 128k reset
RES128: DI
XOR A
LD I,A
OUT (#FE),A
LD E,#17
CC0: LD BC,#7FFD
OUT (C),E
LD BC,#0008
LD H,A
LD L,A
LD SP,HL
CC1: PUSH HL
PUSH HL
PUSH HL
PUSH HL
DJNZ CC1
DEC C
JR NZ,CC1
DEC E
BIT 4,E
JR NZ,CC0
LD B,#5C
CC2: LD (BC),A
INC C
JR NZ,CC2
DEC HL
JP RAM_DONE2
; NMI Menu
NMI_MENU: PUSH AF
PUSH HL
LD HL,#BFE0
ADD HL,SP
JR C,MM1
LD SP,#5800
LD HL,NMI_MENU
PUSH HL
PUSH HL
PUSH HL
MM1: PUSH BC
PUSH DE
PUSH IX
LD A,I
PUSH AF
MMRET: DI
LD C,#FE
LD A,R
OUT (C),A
OUT (C),0
CALL KEY_SCAN
INC E
JR Z,MMRET
DEC E
CALL K_TEST
LD XH,A
LD A,#22
OUT (#FE),A
PUST: CALL KEY_SCAN
INC E
JR NZ,PUST
LD A,#08
OUT (#FE),A
LD A,XH
LD HL,MMRET
PUSH HL
CP 'U' ; U - user function.
JR Z,USERJP
CP 'E' ; E - extended 128k reset.
JR Z,RES128
CP 'I' ; I - quiet AY. Reset FDC, DMA and stop disk drive if MB-02 is present.
JP Z,HARD
CP 'T' ; T - set tape as actual device (only on MB-02).
JP Z,JP15522
CP 'D' ; D - set disk as actual device (only on MB-02)
JP Z,JP15524
CP 'B' ; B - warm start. BASIC program with variables is not deleted.
JP Z,BASIC
CP 'Z' ; Z - user function like 'U' but this key is reserved for MB-02 applications.
LD HL,(DISKTOOLS)
JR NZ,DSKIP
JP (HL)
DSKIP: CP 'N' ; N - CLEAR #5FFF: NEW - memory above #6000 is not changed.
LD DE,#5FFF
JR Z,RESNEW
CP 'R' ; R - CLEAR #FFFF: NEW - classic 48k reset.
LD D,E
RESNEW: JP Z,NEW_1
NERES: CP 'S' ; S - save SCREEN$ on tape, or disk if MB-02 is present.
JR NZ,NESAV
LD IX,#4000
LD DE,#1B00
LD A,#FF
JP SA_BYTES1
NESAV: CP 'Q' ; Q - quit / return from NMI menu.
JR Z,QUIT
CP 'M' ; M - jump to MRS debugger (MRS must be loaded in memory).
JR Z,MRS
CALL NUMERIC
RET C
LD HL,#4000
ADD HL,SP
JR NC,DD0
LD SP,#57F0
DD0: POP BC
CALL OUT128
JP MMRET
; Quit from NMI Menu
QUIT: POP AF
POP AF
LD I,A
JP PO,RET_I
EI
RET_I: POP IX
POP DE
POP BC
POP HL
POP AF
RET
; Jump to MRS debugger
MRS: POP AF
POP AF
LD I,A
POP IX
POP DE
POP BC
POP HL
POP AF
LD (#F4FF),HL
POP HL
LD (#F544),HL
JP #F514
; Print general number
HLODVA: LD A,':'
RST #10
HLO: LD B,H
LD C,L
CALL STACK_BC
JP PRINT_FP
TT: DW #0000 ;DS #39FF-TT
UU: DW #FFFF
DISPL: LD C,A
LD A,(IY+#02)
CP #10
LD A,C
JR NZ,DIS
LD BC,#FBFE
IN C,(C)
RRC C
JR C,DII
PUSTI: XOR A
IN A,(#FE)
RRCA
JR NC,PUSTI
LD SP,(#5C3F) ;LISTSP
RES 5,(IY+#01)
RET
DII: LD C,(IY+#76)
BIT 1,C ;bit1=1 don't show colors during autolist
JR Z,DIS
CP #0D
JR Z,DIS
CP #20
JR C,DIP
DIS: JP PO_FETCH
DIP: BIT 2,C ;bit2=1 show comma instead of codes
JR NZ,DID
POP AF
DID: LD A,#1E
JR DIS
; General number printing with spaces
NUM_NEW: PUSH DE
PUSH HL
LD E,' '
DB #06
NUMCOM: LD L,C
LD BC,#D8F0
CALL OUT_SP_NO
JP OUT_NUM_3
; Check of BASIC program presence
LIN2: CALL LINE_NO
PUSH HL
LD HL,(#5C53)
LD A,(HL)
POP HL
RET
; Test of numbers at the begin of line
LIN3: RST #18
CALL NUMERIC
PUSH AF
CALL E_LINE_NO
POP AF
RET
; Show empty cursor instead of '*'
LIN4: LD A,(IY+#02)
CP #10
JR Z,LL40
LD D,#20
LL40: PUSH HL
XOR A
LD HL,(#5C51) ;channel R?
LD BC,#5CC0
SBC HL,BC
POP HL
JR Z,LL41
BIT 0,(IY+#76)
JP Z,OUT_NUM_2
DB #01
LL41: LD D,#00 ; no cursor at 'R'
PUSH DE
LD D,(HL)
INC HL
LD E,(HL)
EX DE,HL
CALL NUM_NEW
EX DE,HL
POP DE
RET
; Moving around edit zone
DOLE: CALL ED_RIGHT
LD IX,ED_RIGHT
JR NZ,HORDOL
LD HL,#5C49
RET
HORE: CALL ED_LEFT
LD IX,ED_LEFT
JR NC,HORDOL
LD HL,(#5C49)
RET
HORDOL: POP BC
LD B,#00
HD1: INC B
BIT 5,B
RET NZ
PUSH BC
CALL L_03F0
POP BC
LD A,(HL)
CP #0D
RET Z
CP ' '
JR C,HD1+1
SUB #A5
JR C,HD1
EXX
LD HL,INCB-2
LD (#5C51),HL
CALL PO_TOKENS
CALL ED_LIST_1
EXX
JR HD1+1
DW INCB
INCB: EXX
INC B
EXX
RET
; Switch 128k bank
BANKA: RST #20
CALL FETCH_NUM
CALL CHECK_END
CALL FIND_INT1
OUT128: AND #0F
OR #10
LD BC,#7FFD
OUT (C),A
RET
; Comma instead of semicolon
EDIT: RST #20
CALL FETCH_NUM
CALL CHECK_END
CALL FIND_INT2
LD (#5C49),BC
CALL SET_MIN
CALL CLS_LOWER
RES 5,(IY+#37)
VV: DW #FFFF
RES 3,(IY+#01)
CALL ED_EDIT
LD SP,(#5C3D)
POP AF
JP MAIN_2
; Modified CLS command
NEW_CLS: CALL FIND_INT1
OR A
JR Z,NECOL
LD (#5C48),A
LD (#5C8D),A
CALL SA_LD_RET
NECOL: JP CLS
; New commands
COMM: CP #27 ;"'"
JR Z,BANKA
CP #2C ;","
JR Z,EDIT
LD HL,NEWTAB
COM1: BIT 7,(HL)
JP NZ,PRINT
CP (HL)
INC HL
LD E,(HL)
INC HL
LD D,(HL)
INC HL
JR NZ,COM1
RST #20
CALL CHECK_END
EX DE,HL
JP (HL)
NEWTAB: DB '#'
DW 54885
DB '_'
DW #66
DB '*'
DW HEA
DB '?'
DW INFO
DB #7F ;(c)
DW BASIC
DB '^'
DW RES128
DB '!'
DW HARD
DB '='
DW USERJP
; Quiet AY. Reset FDC, DMA, stop drives if MB-02 is present
HARD: XOR A
LD BC,#FFFD
OUT (#13),A ; FDD motor
LD A,#D0
OUT (#0F),A ; FDC
LD A,#C3
OUT (#0B),A ; DMA
LD A,#07
OUT (C),A ; AY
LD A,#BF
OUT (#FD),A
LD A,#0D
OUT (C),A
LD A,#80
OUT (#FD),A
RET
; Warm start
BASIC: LD HL,INIT_CHAN
LD DE,#5CB6
LD BC,#0015
LD (#5C4F),DE
LDIR
LD HL,#3C00
LD (#5C36),HL
LD HL,#0040
LD (#5C38),HL
LD IY,#5C3A
LD HL,(#5CB2)
LD (HL),#3E
DEC HL
LD SP,HL
DEC HL
DEC HL
LD (#5C3D),HL
IM 1
EI
LD HL,(#5C59)
JP WARM_ST
; Enhanced POKE
NEW_POKE: CALL SYNTAX_Z
CALL NZ,FIND_INT2
LD D,B
LD E,C
POKLOP: RST #18
CP #2C
JR Z,POKOK
CP #3B
RET NZ
POKOK: PUSH DE
PUSH AF
RST #20
CALL SCANNING
POP AF
POP DE
CALL SYNTAX_Z
JR Z,POKLOP
BIT 6,(IY+#01)
JR NZ,POKNUM
POKRET: PUSH AF
PUSH DE
CALL STK_FETCH
EX DE,HL
POP DE
LD A,B
OR C
JR Z,POKNIC
LDIR
POP AF
RRCA
JR NC,POKLOP
LD H,D
LD L,E
DEC HL
SET 7,(HL)
PUSH AF
POKNIC: POP AF
JR POKLOP
POKNUM: PUSH DE
RRCA
JR C,POKDW
POKDB: CALL FIND_INT1
POP DE
JR POKLD
POKDW: CALL FIND_INT2
POP DE
LD A,C
LD (DE),A
INC DE
LD A,B
POKLD: LD (DE),A
INC DE
JR POKLOP
SS: DB #FF
WW: DW #FFFF
; New line number test
LIN1: CALL CP_LINES
RET NC
LD A,(HL)
AND #C0
RET NZ
SCF
RET
; New boot screen
INFO: CALL CLS
LD A,#FE
CALL CHAN_OPEN
LD HL,(#5C4B)
LD BC,(#5C53)
XOR A
PUSH HL
SBC HL,BC
CALL INFSUB
POP BC
SCF
LD HL,(#5C59)
SBC HL,BC
LD A,#01
CALL INFSUB
LD BC,(#5C65)
LD HL,#0000
ADD HL,SP
SBC HL,BC
LD A,#02
CALL INFSUB
JP PRINT_5
; Header command
HEA: LD A,#FE
CALL CHAN_OPEN
ZNOVU: DI
LD IX,#5C9E
LD DE,#0010
XOR A
INC E
SCF
EX AF,AF'
LD A,#0E
OUT (#FE),A
IN A,(#FE)
RRA
CALL LD_BYTES1
CALL SA_LD_RET
JR NC,ZNOVU
LD (#5C8C),A
LD A,#17
RST #10
XOR A
RST #10
RST #10
LD HL,#5C9E
LD A,(HL)
OR #30
RST #10
LD A,#3A
RST #10
LD B,#0A
MENO: INC HL
LD A,(HL)
CP #20
JR NC,MENO1
LD A,#1E
MENO1: RST #10
DJNZ MENO
LD A,#17
RST #10
LD A,#15
RST #10
RST #10
LD HL,(#5CAB)
CALL NUM_NEW
LD HL,(#5CA9)
CALL HLODVA
LD A,#0D
RST #10
JR ZNOVU
; Unused bytes
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DB #FF
JP15522: RET
DB #FF
JP15524: RET
DB #FF
DB " Busy soft rom "
DB VER1, VER2, VER3
DB " "
; Unused bytes
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DW #FFFF
DB #FF
; BSROM - new characters
CHAR_SET_N: DB #00,#00,#00,#00,#00,#00,#7E,#00 ;line
DB #00,#7E,#7E,#7E,#7E,#7E,#7E,#00 ;square
; Character set
CHAR_SET: DB #00,#00,#00,#00,#00,#00,#00,#00 ;space
DB #00,#10,#10,#10,#10,#00,#10,#00 ;!
DB #00,#24,#24,#00,#00,#00,#00,#00 ;"
DB #00,#24,#7E,#24,#24,#7E,#24,#00 ;#
DB #00,#08,#3E,#28,#3E,#0A,#3E,#08 ;$
DB #00,#62,#64,#08,#10,#26,#46,#00 ;%
DB #00,#10,#28,#10,#2A,#44,#3A,#00 ;&
DB #00,#08,#10,#00,#00,#00,#00,#00 ;'
DB #00,#04,#08,#08,#08,#08,#04,#00 ;(
DB #00,#20,#10,#10,#10,#10,#20,#00 ;)
DB #00,#00,#14,#08,#3E,#08,#14,#00 ;*
DB #00,#00,#08,#08,#3E,#08,#08,#00 ;+
DB #00,#00,#00,#00,#00,#08,#08,#10 ;,
DB #00,#00,#00,#00,#3E,#00,#00,#00 ;-
DB #00,#00,#00,#00,#00,#18,#18,#00 ;.
DB #00,#00,#02,#04,#08,#10,#20,#00 ;/
DB #00,#3C,#46,#4A,#52,#62,#3C,#00 ;0
DB #00,#18,#28,#08,#08,#08,#3E,#00 ;1
DB #00,#3C,#42,#02,#3C,#40,#7E,#00 ;2
DB #00,#3C,#42,#0C,#02,#42,#3C,#00 ;3
DB #00,#08,#18,#28,#48,#7E,#08,#00 ;4
DB #00,#7E,#40,#7C,#02,#42,#3C,#00 ;5
DB #00,#3C,#40,#7C,#42,#42,#3C,#00 ;6
DB #00,#7E,#02,#04,#08,#10,#10,#00 ;7
DB #00,#3C,#42,#3C,#42,#42,#3C,#00 ;8
DB #00,#3C,#42,#42,#3E,#02,#3C,#00 ;9
DB #00,#00,#00,#10,#00,#00,#10,#00 ;:
DB #00,#00,#10,#00,#00,#10,#10,#20 ;;
DB #00,#00,#04,#08,#10,#08,#04,#00 ;<
DB #00,#00,#00,#3E,#00,#3E,#00,#00 ;=
DB #00,#00,#10,#08,#04,#08,#10,#00 ;>
DB #00,#3C,#42,#04,#08,#00,#08,#00 ;?
DB #00,#3C,#02,#3A,#4A,#4A,#3C,#00 ;@ BSROM - more beautiful @ character
DB #00,#3C,#42,#42,#7E,#42,#42,#00 ;A
DB #00,#7C,#42,#7C,#42,#42,#7C,#00 ;B
DB #00,#3C,#42,#40,#40,#42,#3C,#00 ;C
DB #00,#78,#44,#42,#42,#44,#78,#00 ;D
DB #00,#7E,#40,#7C,#40,#40,#7E,#00 ;E
DB #00,#7E,#40,#7C,#40,#40,#40,#00 ;F
DB #00,#3C,#42,#40,#4E,#42,#3C,#00 ;G
DB #00,#42,#42,#7E,#42,#42,#42,#00 ;H
DB #00,#3E,#08,#08,#08,#08,#3E,#00 ;I
DB #00,#02,#02,#02,#42,#42,#3C,#00 ;J
DB #00,#44,#48,#70,#48,#44,#42,#00 ;K
DB #00,#40,#40,#40,#40,#40,#7E,#00 ;L
DB #00,#42,#66,#5A,#42,#42,#42,#00 ;M
DB #00,#42,#62,#52,#4A,#46,#42,#00 ;N
DB #00,#3C,#42,#42,#42,#42,#3C,#00 ;O
DB #00,#7C,#42,#42,#7C,#40,#40,#00 ;P
DB #00,#3C,#42,#42,#52,#4A,#3C,#00 ;Q
DB #00,#7C,#42,#42,#7C,#44,#42,#00 ;R
DB #00,#3C,#40,#3C,#02,#42,#3C,#00 ;S
DB #00,#FE,#10,#10,#10,#10,#10,#00 ;T
DB #00,#42,#42,#42,#42,#42,#3C,#00 ;U
DB #00,#42,#42,#42,#42,#24,#18,#00 ;V
DB #00,#42,#42,#42,#42,#5A,#24,#00 ;W
DB #00,#42,#24,#18,#18,#24,#42,#00 ;X
DB #00,#82,#44,#28,#10,#10,#10,#00 ;Y
DB #00,#7E,#04,#08,#10,#20,#7E,#00 ;Z
DB #00,#0E,#08,#08,#08,#08,#0E,#00 ;[
DB #00,#00,#40,#20,#10,#08,#04,#00 ;\
DB #00,#70,#10,#10,#10,#10,#70,#00 ;]
DB #00,#10,#38,#54,#10,#10,#10,#00 ;^
DB #00,#00,#00,#00,#00,#00,#00,#FF ;_
DB #00,#1C,#22,#78,#20,#20,#7E,#00 ;£
DB #00,#00,#38,#04,#3C,#44,#3C,#00 ;a
DB #00,#20,#20,#3C,#22,#22,#3C,#00 ;b
DB #00,#00,#1C,#20,#20,#20,#1C,#00 ;c
DB #00,#04,#04,#3C,#44,#44,#3C,#00 ;d
DB #00,#00,#38,#44,#78,#40,#3C,#00 ;e
DB #00,#0C,#10,#18,#10,#10,#10,#00 ;f
DB #00,#00,#3C,#44,#44,#3C,#04,#38 ;g
DB #00,#40,#40,#78,#44,#44,#44,#00 ;h
DB #00,#10,#00,#30,#10,#10,#38,#00 ;i
DB #00,#04,#00,#04,#04,#04,#24,#18 ;j
DB #00,#20,#28,#30,#30,#28,#24,#00 ;k
DB #00,#10,#10,#10,#10,#10,#0C,#00 ;l
DB #00,#00,#68,#54,#54,#54,#54,#00 ;m
DB #00,#00,#78,#44,#44,#44,#44,#00 ;n
DB #00,#00,#38,#44,#44,#44,#38,#00 ;o
DB #00,#00,#78,#44,#44,#78,#40,#40 ;p
DB #00,#00,#3C,#44,#44,#3C,#04,#06 ;q
DB #00,#00,#1C,#20,#20,#20,#20,#00 ;r
DB #00,#00,#38,#40,#38,#04,#78,#00 ;s
DB #00,#10,#38,#10,#10,#10,#0C,#00 ;t
DB #00,#00,#44,#44,#44,#44,#38,#00 ;u
DB #00,#00,#44,#44,#28,#28,#10,#00 ;v
DB #00,#00,#44,#54,#54,#54,#28,#00 ;w
DB #00,#00,#44,#28,#10,#28,#44,#00 ;x
DB #00,#00,#44,#44,#44,#3C,#04,#38 ;y
DB #00,#00,#7C,#08,#10,#20,#7C,#00 ;z
DB #00,#0E,#08,#30,#08,#08,#0E,#00 ;{
DB #00,#08,#08,#08,#08,#08,#08,#00 ;|
DB #00,#70,#10,#0C,#10,#10,#70,#00 ;}
DB #00,#14,#28,#00,#00,#00,#00,#00 ;~
DB #3C,#42,#99,#A1,#A1,#99,#42,#3C ;(c)
| z00m128/sjasmplus | tests/integration/bsrom/bsrom140.asm | Assembly | bsd-3-clause | 145,344 |
;
; Copyleft (C) 1995, 1996 Exobit Productions International Corp.
;
; main code by Mentat
;
; (what a cooperation work, man!) ;)))
;
.386p ;-)
locals
jumps
public exptab1
public exptab2
public crtab1
public crtab2
public colortb
public colort2
code32 segment para public use32
assume cs:code32, ds:code32
align 4
exptab1 dd 06000h, 02000h, 02000h, 06000h, 06000h, 06000h
dd 00000h, 00000h, 00000h, 00000h, 00000h, 01000h
dd 01000h, 01000h, 01000h, 01000h, 01000h, 01000h
dd 01000h, 01000h, 01000h, 01000h, 01000h, 01000h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 08000h, 0A000h, 10000h
align 4
exptab2 dd 03000h, 04400h, 04000h, 06000h, 06000h, 06000h
dd 00000h, 00000h, 00000h, 00000h, 00000h, 01000h
dd 01000h, 01000h, 01000h, 01000h, 01000h, 01000h
dd 01000h, 01000h, 01000h, 01000h, 01000h, 01000h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 00800h, 00800h, 00800h, 00800h, 00800h, 00800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 01800h, 01800h, 01800h, 01800h, 01800h, 01800h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 04000h, 04000h, 04000h, 04000h, 04000h, 04000h
dd 08000h, 0A000h, 10000h
align 4
crtab1: dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0002h, 0002h, 0001h, 0002h, 0002h, 0002h, 0002h, 0002h
dw 0002h, 0002h, 0001h, 0002h, 0002h, 0002h, 0002h, 0002h
dw 0002h, 0002h, 0001h, 0002h, 0002h, 0002h, 0002h, 0002h
dw 0002h, 0002h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0002h, 0002h, 0001h, 0002h, 0002h, 0002h, 0002h, 0002h
dw 0002h, 0002h, 0001h, 0002h, 0002h, 0002h, 0002h, 0002h
dw 0002h, 0002h, 0001h, 0002h, 0002h, 0002h, 0002h, 0002h
dw 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h
dw 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h
dw 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h
dw 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h, 0004h
dw 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h
dw 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h
dw 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h
dw 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h
dw 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h, 0008h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
align 4
crtab2: dw 0008h, 0008h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h, 0001h
dw 0001h, 0001h, 0008h, 0008h, 0008h, 0011h, 0011h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0012h, 0010h, 0011h, 0012h, 0012h, 0012h, 0012h, 0011h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
dw 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h, 0020h
align 4
colortb dw 000h, 000h, 001h, 001h, 002h, 002h, 003h, 003h
dw 004h, 004h, 005h, 005h, 006h, 006h, 007h, 007h
dw 000h, 000h, 011h, 014h, 012h, 016h, 013h, 018h
dw 015h, 01Ah, 017h, 01Ch, 019h, 01Eh, 01Bh, 01Dh
dw 000h, 000h, 021h, 021h, 022h, 022h, 023h, 023h
dw 024h, 024h, 025h, 025h, 026h, 026h, 027h, 027h
dw 000h, 000h, 031h, 031h, 032h, 032h, 033h, 033h
dw 034h, 034h, 035h, 035h, 036h, 036h, 037h, 037h
dw 000h, 000h, 041h, 042h, 043h, 046h, 04Ch, 04Ah
dw 04Dh, 044h, 059h, 047h, 04Bh, 045h, 048h, 049h
dw 000h, 000h, 051h, 051h, 052h, 052h, 053h, 053h
dw 054h, 054h, 055h, 055h, 056h, 056h, 057h, 057h
dw 000h, 000h, 061h, 061h, 062h, 062h, 063h, 063h
dw 064h, 064h, 065h, 065h, 066h, 066h, 067h, 067h
dw 000h, 000h, 071h, 071h, 072h, 072h, 073h, 073h
dw 074h, 074h, 075h, 075h, 076h, 076h, 077h, 077h
dw 000h, 000h, 081h, 081h, 082h, 082h, 083h, 083h
dw 084h, 084h, 085h, 085h, 086h, 086h, 087h, 087h
dw 000h, 000h, 091h, 092h, 093h, 094h, 095h, 096h
dw 097h, 098h, 099h, 09Ah, 09Bh, 09Ch, 09Dh, 09Eh
dw 000h, 000h, 0A1h, 0A1h, 0A2h, 0A2h, 0A3h, 0A3h
dw 0A4h, 0A4h, 0A5h, 0A5h, 0A6h, 0A6h, 0A7h, 0A7h
dw 000h, 000h, 0B1h, 0B1h, 0B2h, 0B2h, 0B3h, 0B3h
dw 0B4h, 0B4h, 0B5h, 0B5h, 0B6h, 0B6h, 0B7h, 0B7h
dw 000h, 000h, 0C1h, 0C1h, 0C2h, 0C2h, 0C3h, 0C3h
dw 0C4h, 0C4h, 0C5h, 0C5h, 0C6h, 0C6h, 0C7h, 0C7h
dw 000h, 000h, 0D1h, 0D1h, 0D2h, 0D2h, 0D3h, 0D3h
dw 0D4h, 0D4h, 0D5h, 0D5h, 0D6h, 0D6h, 0D7h, 0D7h
dw 000h, 000h, 0E1h, 0E1h, 0E2h, 0E2h, 0E3h, 0E3h
dw 0E4h, 0E4h, 0E5h, 0E5h, 0E6h, 0E6h, 0E7h, 0E7h
dw 000h, 000h, 0F1h, 0F1h, 0F2h, 0F2h, 0F3h, 0F3h
dw 0F4h, 0F4h, 0F5h, 0F5h, 0F6h, 0F6h, 0F7h, 0F7h
align 4
colort2 dw 000h, 001h, 002h, 003h, 004h, 005h, 006h, 007h
dw 008h, 009h, 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh
dw 000h, 000h, 011h, 014h, 012h, 016h, 013h, 018h
dw 015h, 01Ah, 017h, 01Ch, 019h, 01Eh, 01Bh, 01Dh
dw 000h, 000h, 021h, 021h, 022h, 022h, 023h, 023h
dw 024h, 024h, 025h, 025h, 026h, 026h, 027h, 027h
dw 000h, 000h, 031h, 031h, 032h, 032h, 033h, 033h
dw 034h, 034h, 035h, 035h, 036h, 036h, 037h, 037h
dw 000h, 000h, 041h, 042h, 043h, 046h, 04Ch, 04Ah
dw 04Dh, 044h, 059h, 047h, 04Bh, 045h, 048h, 049h
dw 000h, 000h, 051h, 051h, 052h, 052h, 053h, 053h
dw 054h, 054h, 055h, 055h, 056h, 056h, 057h, 057h
dw 000h, 000h, 061h, 061h, 062h, 062h, 063h, 063h
dw 064h, 064h, 065h, 065h, 066h, 066h, 067h, 067h
dw 000h, 000h, 071h, 071h, 072h, 072h, 073h, 073h
dw 074h, 074h, 075h, 075h, 076h, 076h, 077h, 077h
dw 000h, 000h, 081h, 081h, 082h, 082h, 083h, 083h
dw 084h, 084h, 085h, 085h, 086h, 086h, 087h, 087h
dw 000h, 000h, 091h, 092h, 093h, 094h, 095h, 096h
dw 097h, 098h, 099h, 09Ah, 09Bh, 09Ch, 09Dh, 09Eh
dw 000h, 000h, 0A1h, 0A1h, 0A2h, 0A2h, 0A3h, 0A3h
dw 0A4h, 0A4h, 0A5h, 0A5h, 0A6h, 0A6h, 0A7h, 0A7h
dw 000h, 000h, 0B1h, 0B1h, 0B2h, 0B2h, 0B3h, 0B3h
dw 0B4h, 0B4h, 0B5h, 0B5h, 0B6h, 0B6h, 0B7h, 0B7h
dw 000h, 000h, 0C1h, 0C1h, 0C2h, 0C2h, 0C3h, 0C3h
dw 0C4h, 0C4h, 0C5h, 0C5h, 0C6h, 0C6h, 0C7h, 0C7h
dw 000h, 000h, 0D1h, 0D1h, 0D2h, 0D4h, 0D5h, 0D6h
dw 0D6h, 0D8h, 0D8h, 0DAh, 0DBh, 0DCh, 0DDh, 0DEh
dw 000h, 000h, 0E1h, 0E1h, 0E2h, 0E4h, 0E5h, 0E6h
dw 0E6h, 0E8h, 0E8h, 0EAh, 0EBh, 0ECh, 0EDh, 0EEh
dw 000h, 000h, 0F1h, 0F1h, 0F2h, 0F4h, 0F5h, 0F6h
dw 0F6h, 0F8h, 0F8h, 0FAh, 0FBh, 0FCh, 0FDh, 0FEh
;ÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ
code32 ends
end
| khromalabs/Hypnotic | fwdata.asm | Assembly | bsd-3-clause | 12,347 |
kernel.elf: file format elf32-littlearm
Disassembly of section .text:
00008000 <init_entry_point>:
8000: e59ff018 ldr pc, [pc, #24] ; 8020 <reset_handler>
8004: e59ff018 ldr pc, [pc, #24] ; 8024 <basic_handler>
8008: e59ff014 ldr pc, [pc, #20] ; 8024 <basic_handler>
800c: e59ff010 ldr pc, [pc, #16] ; 8024 <basic_handler>
8010: e59ff00c ldr pc, [pc, #12] ; 8024 <basic_handler>
8014: e59ff008 ldr pc, [pc, #8] ; 8024 <basic_handler>
8018: e59ff004 ldr pc, [pc, #4] ; 8024 <basic_handler>
801c: e51ff000 ldr pc, [pc, #-0] ; 8024 <basic_handler>
00008020 <reset_handler>:
8020: 00008028 andeq r8, r0, r8, lsr #32
00008024 <basic_handler>:
8024: 0000804c andeq r8, r0, ip, asr #32
00008028 <reset>:
8028: e3a00902 mov r0, #32768 ; 0x8000
802c: e3a01000 mov r1, #0
8030: e8b003fc ldm r0!, {r2, r3, r4, r5, r6, r7, r8, r9}
8034: e8a103fc stmia r1!, {r2, r3, r4, r5, r6, r7, r8, r9}
8038: e8b003fc ldm r0!, {r2, r3, r4, r5, r6, r7, r8, r9}
803c: e8a103fc stmia r1!, {r2, r3, r4, r5, r6, r7, r8, r9}
8040: ea00000c b 8078 <init>
8044: e12fff1e bx lr
00008048 <hang>:
8048: eafffffe b 8048 <hang>
0000804c <arm_interrupt_handler>:
804c: e24ee004 sub lr, lr, #4
8050: e92d401f push {r0, r1, r2, r3, r4, lr}
8054: eb00041a bl 90c4 <irq_handler>
8058: e8fd801f ldm sp!, {r0, r1, r2, r3, r4, pc}^
805c: e12fff1e bx lr
8060: 00001741 andeq r1, r0, r1, asr #14
8064: 61656100 cmnvs r5, r0, lsl #2
8068: 01006962 tsteq r0, r2, ror #18
806c: 0000000d andeq r0, r0, sp
8070: 01080206 tsteq r8, r6, lsl #4
8074: 012c0109 teqeq ip, r9, lsl #2
00008078 <init>:
8078: e3a0d702 mov sp, #524288 ; 0x80000
807c: eb000442 bl 918c <kmain>
8080: eaffffff b 8084 <hang$>
00008084 <hang$>:
8084: eafffffe b 8084 <hang$>
8088: 00001541 andeq r1, r0, r1, asr #10
808c: 61656100 cmnvs r5, r0, lsl #2
8090: 01006962 tsteq r0, r2, ror #18
8094: 0000000b andeq r0, r0, fp
8098: 01080106 tsteq r8, r6, lsl #2
809c: 0000012c andeq r0, r0, ip, lsr #2
000080a0 <_Z3absi>:
80a0: e3500000 cmp r0, #0
80a4: b2600000 rsblt r0, r0, #0
80a8: e12fff1e bx lr
000080ac <_Z15getNumberLengthiiPi>:
80ac: e1a03000 mov r3, r0
80b0: e3a00000 mov r0, #0
80b4: e5820000 str r0, [r2]
80b8: e3a00001 mov r0, #1
80bc: ea000000 b 80c4 <_Z15getNumberLengthiiPi+0x18>
80c0: e1a00002 mov r0, r2
80c4: e0020091 mul r2, r1, r0
80c8: e1520003 cmp r2, r3
80cc: bafffffb blt 80c0 <_Z15getNumberLengthiiPi+0x14>
80d0: e12fff1e bx lr
000080d4 <_Z15getNumberLengthii>:
80d4: e1a03000 mov r3, r0
80d8: e3a00001 mov r0, #1
80dc: ea000000 b 80e4 <_Z15getNumberLengthii+0x10>
80e0: e1a00002 mov r0, r2
80e4: e0020091 mul r2, r1, r0
80e8: e1530002 cmp r3, r2
80ec: cafffffb bgt 80e0 <_Z15getNumberLengthii+0xc>
80f0: e12fff1e bx lr
000080f4 <_Z15getNumberLengthi>:
80f4: e3a03001 mov r3, #1
80f8: ea000000 b 8100 <_Z15getNumberLengthi+0xc>
80fc: e1a03002 mov r3, r2
8100: e0832103 add r2, r3, r3, lsl #2
8104: e1a02082 lsl r2, r2, #1
8108: e1500002 cmp r0, r2
810c: cafffffa bgt 80fc <_Z15getNumberLengthi+0x8>
8110: e1a00003 mov r0, r3
8114: e12fff1e bx lr
00008118 <_Z6divideiiPiS_>:
8118: e3510000 cmp r1, #0
811c: e92d00f0 push {r4, r5, r6, r7}
8120: 0a00001d beq 819c <_Z6divideiiPiS_+0x84>
8124: e3510001 cmp r1, #1
8128: 05820000 streq r0, [r2]
812c: 03a02000 moveq r2, #0
8130: 05832000 streq r2, [r3]
8134: 0a000018 beq 819c <_Z6divideiiPiS_+0x84>
8138: e3a04000 mov r4, #0
813c: e3500000 cmp r0, #0
8140: b2600000 rsblt r0, r0, #0
8144: e1500004 cmp r0, r4
8148: e5824000 str r4, [r2]
814c: e5834000 str r4, [r3]
8150: 0a000011 beq 819c <_Z6divideiiPiS_+0x84>
8154: e3510000 cmp r1, #0
8158: b2611000 rsblt r1, r1, #0
815c: e050c001 subs ip, r0, r1
8160: 4a000010 bmi 81a8 <_Z6divideiiPiS_+0x90>
8164: e061c00c rsb ip, r1, ip
8168: e5925000 ldr r5, [r2]
816c: e2617000 rsb r7, r1, #0
8170: e08c6001 add r6, ip, r1
8174: ea000001 b 8180 <_Z6divideiiPiS_+0x68>
8178: e09c6001 adds r6, ip, r1
817c: 4a000008 bmi 81a4 <_Z6divideiiPiS_+0x8c>
8180: e2844001 add r4, r4, #1
8184: e1540006 cmp r4, r6
8188: e1a00006 mov r0, r6
818c: e08cc007 add ip, ip, r7
8190: e2855001 add r5, r5, #1
8194: bafffff7 blt 8178 <_Z6divideiiPiS_+0x60>
8198: e5825000 str r5, [r2]
819c: e8bd00f0 pop {r4, r5, r6, r7}
81a0: e12fff1e bx lr
81a4: e5825000 str r5, [r2]
81a8: e5830000 str r0, [r3]
81ac: eafffffa b 819c <_Z6divideiiPiS_+0x84>
000081b0 <_Z6divideii>:
81b0: e52de004 push {lr} ; (str lr, [sp, #-4]!)
81b4: e24dd00c sub sp, sp, #12
81b8: e3a0c000 mov ip, #0
81bc: e28d2004 add r2, sp, #4
81c0: e1a0300d mov r3, sp
81c4: e58dc004 str ip, [sp, #4]
81c8: e58dc000 str ip, [sp]
81cc: ebffffd1 bl 8118 <_Z6divideiiPiS_>
81d0: e59d0004 ldr r0, [sp, #4]
81d4: e28dd00c add sp, sp, #12
81d8: e49de004 pop {lr} ; (ldr lr, [sp], #4)
81dc: e12fff1e bx lr
000081e0 <_Z6moduloii>:
81e0: e52de004 push {lr} ; (str lr, [sp, #-4]!)
81e4: e24dd00c sub sp, sp, #12
81e8: e3a0c000 mov ip, #0
81ec: e28d2004 add r2, sp, #4
81f0: e1a0300d mov r3, sp
81f4: e58dc004 str ip, [sp, #4]
81f8: e58dc000 str ip, [sp]
81fc: ebffffc5 bl 8118 <_Z6divideiiPiS_>
8200: e59d0000 ldr r0, [sp]
8204: e28dd00c add sp, sp, #12
8208: e49de004 pop {lr} ; (ldr lr, [sp], #4)
820c: e12fff1e bx lr
00008210 <_Z5allocj>:
8210: e59f30b0 ldr r3, [pc, #176] ; 82c8 <_Z5allocj+0xb8>
8214: e5933000 ldr r3, [r3]
8218: e5d32004 ldrb r2, [r3, #4]
821c: e3520000 cmp r2, #0
8220: e92d0070 push {r4, r5, r6}
8224: e1a05000 mov r5, r0
8228: 0a000003 beq 823c <_Z5allocj+0x2c>
822c: e5933000 ldr r3, [r3]
8230: e5d30004 ldrb r0, [r3, #4]
8234: e3500000 cmp r0, #0
8238: 1afffffb bne 822c <_Z5allocj+0x1c>
823c: e5936008 ldr r6, [r3, #8]
8240: e593100c ldr r1, [r3, #12]
8244: e3a04000 mov r4, #0
8248: e0860101 add r0, r6, r1, lsl #2
824c: e1550004 cmp r5, r4
8250: e2836b01 add r6, r3, #1024 ; 0x400
8254: e5c34404 strb r4, [r3, #1028] ; 0x404
8258: e5830408 str r0, [r3, #1032] ; 0x408
825c: e583540c str r5, [r3, #1036] ; 0x40c
8260: 0a000013 beq 82b4 <_Z5allocj+0xa4>
8264: e245c001 sub ip, r5, #1
8268: e1a02000 mov r2, r0
826c: e3550001 cmp r5, #1
8270: e20c1001 and r1, ip, #1
8274: e4824004 str r4, [r2], #4
8278: e3a0c001 mov ip, #1
827c: 9a00000c bls 82b4 <_Z5allocj+0xa4>
8280: e3510000 cmp r1, #0
8284: 0a000003 beq 8298 <_Z5allocj+0x88>
8288: e3a0c002 mov ip, #2
828c: e155000c cmp r5, ip
8290: e4824004 str r4, [r2], #4
8294: 9a000006 bls 82b4 <_Z5allocj+0xa4>
8298: e1a01002 mov r1, r2
829c: e4814004 str r4, [r1], #4
82a0: e28cc002 add ip, ip, #2
82a4: e155000c cmp r5, ip
82a8: e5824004 str r4, [r2, #4]
82ac: e2812004 add r2, r1, #4
82b0: 8afffff8 bhi 8298 <_Z5allocj+0x88>
82b4: e3a02001 mov r2, #1
82b8: e5836000 str r6, [r3]
82bc: e5c32004 strb r2, [r3, #4]
82c0: e8bd0070 pop {r4, r5, r6}
82c4: e12fff1e bx lr
82c8: 00009d24 andeq r9, r0, r4, lsr #26
000082cc <_Z15init_page_tablev>:
82cc: e59f1018 ldr r1, [pc, #24] ; 82ec <_Z15init_page_tablev+0x20>
82d0: e3a0380f mov r3, #983040 ; 0xf0000
82d4: e3a00000 mov r0, #0
82d8: e3a02aff mov r2, #1044480 ; 0xff000
82dc: e5813000 str r3, [r1]
82e0: e5c30004 strb r0, [r3, #4]
82e4: e5832008 str r2, [r3, #8]
82e8: e12fff1e bx lr
82ec: 00009d24 andeq r9, r0, r4, lsr #26
000082f0 <_Z10irq_enablev>:
82f0: e59f3018 ldr r3, [pc, #24] ; 8310 <_Z10irq_enablev+0x20>
82f4: e3e01000 mvn r1, #0
82f8: e3a020ff mov r2, #255 ; 0xff
82fc: e5831840 str r1, [r3, #2112] ; 0x840
8300: e3a00001 mov r0, #1
8304: e5831850 str r1, [r3, #2128] ; 0x850
8308: e5832860 str r2, [r3, #2144] ; 0x860
830c: e12fff1e bx lr
8310: 2000b000 andcs fp, r0, r0
00008314 <_Z8irq_testv>:
8314: ef0000ff svc 0x000000ff
8318: e12fff1e bx lr
0000831c <_ZN12RaspberryLib5GET32Ej>:
831c: e5900000 ldr r0, [r0]
8320: e12fff1e bx lr
00008324 <_ZN12RaspberryLib5PUT32Ejj>:
8324: e5801000 str r1, [r0]
8328: e12fff1e bx lr
0000832c <_ZN12RaspberryLib4GET4Ej>:
832c: e5d00000 ldrb r0, [r0]
8330: e12fff1e bx lr
00008334 <_ZN12RaspberryLib4PUT4Ejc>:
8334: e5c01000 strb r1, [r0]
8338: e12fff1e bx lr
0000833c <_ZN12RaspberryLib7SetGPIOEjj>:
833c: e59f2094 ldr r2, [pc, #148] ; 83d8 <_ZN12RaspberryLib7SetGPIOEjj+0x9c>
8340: e3510001 cmp r1, #1
8344: e59f3090 ldr r3, [pc, #144] ; 83dc <_ZN12RaspberryLib7SetGPIOEjj+0xa0>
8348: 11a03002 movne r3, r2
834c: e350000a cmp r0, #10
8350: 959f1088 ldrls r1, [pc, #136] ; 83e0 <_ZN12RaspberryLib7SetGPIOEjj+0xa4>
8354: 93a0c001 movls ip, #1
8358: 9a000018 bls 83c0 <_ZN12RaspberryLib7SetGPIOEjj+0x84>
835c: e59f2080 ldr r2, [pc, #128] ; 83e4 <_ZN12RaspberryLib7SetGPIOEjj+0xa8>
8360: e240100b sub r1, r0, #11
8364: e082c291 umull ip, r2, r1, r2
8368: e240000a sub r0, r0, #10
836c: e1a011a2 lsr r1, r2, #3
8370: e350000a cmp r0, #10
8374: e2012001 and r2, r1, #1
8378: e3a0c001 mov ip, #1
837c: 9a000009 bls 83a8 <_ZN12RaspberryLib7SetGPIOEjj+0x6c>
8380: e3520000 cmp r2, #0
8384: 0a000003 beq 8398 <_ZN12RaspberryLib7SetGPIOEjj+0x5c>
8388: e240000a sub r0, r0, #10
838c: e350000a cmp r0, #10
8390: e3a0c002 mov ip, #2
8394: 9a000003 bls 83a8 <_ZN12RaspberryLib7SetGPIOEjj+0x6c>
8398: e2400014 sub r0, r0, #20
839c: e350000a cmp r0, #10
83a0: e28cc002 add ip, ip, #2
83a4: 8afffffb bhi 8398 <_ZN12RaspberryLib7SetGPIOEjj+0x5c>
83a8: e1a0110c lsl r1, ip, #2
83ac: e3a02001 mov r2, #1
83b0: e1a0c20c lsl ip, ip, #4
83b4: e1a0cc12 lsl ip, r2, ip
83b8: e2811202 add r1, r1, #536870912 ; 0x20000000
83bc: e2811602 add r1, r1, #2097152 ; 0x200000
83c0: e0800080 add r0, r0, r0, lsl #1
83c4: e3a02001 mov r2, #1
83c8: e1a00012 lsl r0, r2, r0
83cc: e5810000 str r0, [r1]
83d0: e583c000 str ip, [r3]
83d4: e12fff1e bx lr
83d8: 2020001c eorcs r0, r0, ip, lsl r0
83dc: 20200028 eorcs r0, r0, r8, lsr #32
83e0: 20200000 eorcs r0, r0, r0
83e4: cccccccd stclgt 12, cr12, [ip], {205} ; 0xcd
000083e8 <_ZN12RaspberryLib12CheckCounterEv>:
83e8: e59f3004 ldr r3, [pc, #4] ; 83f4 <_ZN12RaspberryLib12CheckCounterEv+0xc>
83ec: e5930004 ldr r0, [r3, #4]
83f0: e12fff1e bx lr
83f4: 20003000 andcs r3, r0, r0
000083f8 <_ZN12RaspberryLib9WaitQuickEj>:
83f8: e59f3014 ldr r3, [pc, #20] ; 8414 <_ZN12RaspberryLib9WaitQuickEj+0x1c>
83fc: e5932004 ldr r2, [r3, #4]
8400: e0802002 add r2, r0, r2
8404: e5931004 ldr r1, [r3, #4]
8408: e1520001 cmp r2, r1
840c: 8afffffc bhi 8404 <_ZN12RaspberryLib9WaitQuickEj+0xc>
8410: e12fff1e bx lr
8414: 20003000 andcs r3, r0, r0
00008418 <_ZN12RaspberryLib4WaitEj>:
8418: e59f301c ldr r3, [pc, #28] ; 843c <_ZN12RaspberryLib4WaitEj+0x24>
841c: e0801100 add r1, r0, r0, lsl #2
8420: e5932004 ldr r2, [r3, #4]
8424: e0810101 add r0, r1, r1, lsl #2
8428: e0821280 add r1, r2, r0, lsl #5
842c: e593c004 ldr ip, [r3, #4]
8430: e151000c cmp r1, ip
8434: 8afffffc bhi 842c <_ZN12RaspberryLib4WaitEj+0x14>
8438: e12fff1e bx lr
843c: 20003000 andcs r3, r0, r0
00008440 <_ZN12RaspberryLib5BlinkEjj>:
8440: e92d40f8 push {r3, r4, r5, r6, r7, lr}
8444: e2505000 subs r5, r0, #0
8448: 0a000016 beq 84a8 <_ZN12RaspberryLib5BlinkEjj+0x68>
844c: e0810101 add r0, r1, r1, lsl #2
8450: e59f4058 ldr r4, [pc, #88] ; 84b0 <_ZN12RaspberryLib5BlinkEjj+0x70>
8454: e0801100 add r1, r0, r0, lsl #2
8458: e1a06281 lsl r6, r1, #5
845c: e1a07004 mov r7, r4
8460: e3a00010 mov r0, #16
8464: e3a01001 mov r1, #1
8468: ebffffb3 bl 833c <_ZN12RaspberryLib7SetGPIOEjj>
846c: e5942004 ldr r2, [r4, #4]
8470: e0862002 add r2, r6, r2
8474: e5943004 ldr r3, [r4, #4]
8478: e1520003 cmp r2, r3
847c: 8afffffc bhi 8474 <_ZN12RaspberryLib5BlinkEjj+0x34>
8480: e3a00010 mov r0, #16
8484: e3a01000 mov r1, #0
8488: ebffffab bl 833c <_ZN12RaspberryLib7SetGPIOEjj>
848c: e597c004 ldr ip, [r7, #4]
8490: e086200c add r2, r6, ip
8494: e594e004 ldr lr, [r4, #4]
8498: e152000e cmp r2, lr
849c: 8afffffc bhi 8494 <_ZN12RaspberryLib5BlinkEjj+0x54>
84a0: e2555001 subs r5, r5, #1
84a4: 1affffed bne 8460 <_ZN12RaspberryLib5BlinkEjj+0x20>
84a8: e8bd40f8 pop {r3, r4, r5, r6, r7, lr}
84ac: e12fff1e bx lr
84b0: 20003000 andcs r3, r0, r0
000084b4 <_ZN12RaspberryLib7PiFaultEPKc>:
84b4: e3a00004 mov r0, #4
84b8: e3a010c8 mov r1, #200 ; 0xc8
84bc: eaffffdf b 8440 <_ZN12RaspberryLib5BlinkEjj>
000084c0 <_ZN12RaspberryLib12MailboxWriteEcj>:
84c0: e59f303c ldr r3, [pc, #60] ; 8504 <_ZN12RaspberryLib12MailboxWriteEcj+0x44>
84c4: e5932898 ldr r2, [r3, #2200] ; 0x898
84c8: e3520000 cmp r2, #0
84cc: bafffffc blt 84c4 <_ZN12RaspberryLib12MailboxWriteEcj+0x4>
84d0: ee07cf15 mcr 15, 0, ip, cr7, cr5, {0}
84d4: ee07cfd5 mcr 15, 0, ip, cr7, cr5, {6}
84d8: ee07cf9a mcr 15, 0, ip, cr7, cr10, {4}
84dc: ee07cf95 mcr 15, 0, ip, cr7, cr5, {4}
84e0: e59f301c ldr r3, [pc, #28] ; 8504 <_ZN12RaspberryLib12MailboxWriteEcj+0x44>
84e4: e3c1100f bic r1, r1, #15
84e8: e1810000 orr r0, r1, r0
84ec: e58308a0 str r0, [r3, #2208] ; 0x8a0
84f0: ee07cf15 mcr 15, 0, ip, cr7, cr5, {0}
84f4: ee07cfd5 mcr 15, 0, ip, cr7, cr5, {6}
84f8: ee07cf9a mcr 15, 0, ip, cr7, cr10, {4}
84fc: ee07cf95 mcr 15, 0, ip, cr7, cr5, {4}
8500: e12fff1e bx lr
8504: 2000b000 andcs fp, r0, r0
00008508 <_ZN12RaspberryLib12MailboxCheckEc>:
8508: e92d4010 push {r4, lr}
850c: e59f2068 ldr r2, [pc, #104] ; 857c <_ZN12RaspberryLib12MailboxCheckEc+0x74>
8510: e59f4068 ldr r4, [pc, #104] ; 8580 <_ZN12RaspberryLib12MailboxCheckEc+0x78>
8514: e3a01000 mov r1, #0
8518: e5923898 ldr r3, [r2, #2200] ; 0x898
851c: e3130101 tst r3, #1073741824 ; 0x40000000
8520: 1a00000e bne 8560 <_ZN12RaspberryLib12MailboxCheckEc+0x58>
8524: ee07cf15 mcr 15, 0, ip, cr7, cr5, {0}
8528: ee07cfd5 mcr 15, 0, ip, cr7, cr5, {6}
852c: ee07cf9a mcr 15, 0, ip, cr7, cr10, {4}
8530: ee07cf95 mcr 15, 0, ip, cr7, cr5, {4}
8534: e5923880 ldr r3, [r2, #2176] ; 0x880
8538: ee07cf15 mcr 15, 0, ip, cr7, cr5, {0}
853c: ee07cfd5 mcr 15, 0, ip, cr7, cr5, {6}
8540: ee07cf9a mcr 15, 0, ip, cr7, cr10, {4}
8544: ee07cf95 mcr 15, 0, ip, cr7, cr5, {4}
8548: e203c00f and ip, r3, #15
854c: e15c0000 cmp ip, r0
8550: 1afffff0 bne 8518 <_ZN12RaspberryLib12MailboxCheckEc+0x10>
8554: e3c3000f bic r0, r3, #15
8558: e8bd4010 pop {r4, lr}
855c: e12fff1e bx lr
8560: e1510004 cmp r1, r4
8564: 92811001 addls r1, r1, #1
8568: 9affffea bls 8518 <_ZN12RaspberryLib12MailboxCheckEc+0x10>
856c: e59f0010 ldr r0, [pc, #16] ; 8584 <_ZN12RaspberryLib12MailboxCheckEc+0x7c>
8570: ebffffcf bl 84b4 <_ZN12RaspberryLib7PiFaultEPKc>
8574: e3e00000 mvn r0, #0
8578: eafffff6 b 8558 <_ZN12RaspberryLib12MailboxCheckEc+0x50>
857c: 2000b000 andcs fp, r0, r0
8580: 000fffff strdeq pc, [pc], -pc ; <UNPREDICTABLE>
8584: 00009e4c andeq r9, r0, ip, asr #28
00008588 <_ZN12RaspberryLib18AcquireFrameBufferEjj>:
8588: e3a03a02 mov r3, #8192 ; 0x2000
858c: e1a0c001 mov ip, r1
8590: e92d4010 push {r4, lr}
8594: e3a02000 mov r2, #0
8598: e1a0e000 mov lr, r0
859c: e583c004 str ip, [r3, #4]
85a0: e583c00c str ip, [r3, #12]
85a4: e3a0c018 mov ip, #24
85a8: e3a00001 mov r0, #1
85ac: e59f10e4 ldr r1, [pc, #228] ; 8698 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x110>
85b0: e583e000 str lr, [r3]
85b4: e583e008 str lr, [r3, #8]
85b8: e5832010 str r2, [r3, #16]
85bc: e583c014 str ip, [r3, #20]
85c0: e5832018 str r2, [r3, #24]
85c4: e583201c str r2, [r3, #28]
85c8: e5832020 str r2, [r3, #32]
85cc: e5832024 str r2, [r3, #36] ; 0x24
85d0: e5c32028 strb r2, [r3, #40] ; 0x28
85d4: ebffffb9 bl 84c0 <_ZN12RaspberryLib12MailboxWriteEcj>
85d8: e3a00001 mov r0, #1
85dc: ebffffc9 bl 8508 <_ZN12RaspberryLib12MailboxCheckEc>
85e0: e3500000 cmp r0, #0
85e4: 1a00000d bne 8620 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x98>
85e8: e3a02a02 mov r2, #8192 ; 0x2000
85ec: e5923020 ldr r3, [r2, #32]
85f0: e3530000 cmp r3, #0
85f4: 0a000024 beq 868c <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x104>
85f8: e5921010 ldr r1, [r2, #16]
85fc: e3510000 cmp r1, #0
8600: 0a00001e beq 8680 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xf8>
8604: e3530101 cmp r3, #1073741824 ; 0x40000000
8608: e3a0c001 mov ip, #1
860c: 82833103 addhi r3, r3, #-1073741824 ; 0xc0000000
8610: e3a00a02 mov r0, #8192 ; 0x2000
8614: e5c2c028 strb ip, [r2, #40] ; 0x28
8618: e5803020 str r3, [r0, #32]
861c: ea000014 b 8674 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xec>
8620: e3a00001 mov r0, #1
8624: ebffffb7 bl 8508 <_ZN12RaspberryLib12MailboxCheckEc>
8628: e3500000 cmp r0, #0
862c: e59f4068 ldr r4, [pc, #104] ; 869c <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x114>
8630: e3a00001 mov r0, #1
8634: 0a00000a beq 8664 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xdc>
8638: ebffffb2 bl 8508 <_ZN12RaspberryLib12MailboxCheckEc>
863c: e3500000 cmp r0, #0
8640: e2444001 sub r4, r4, #1
8644: 0a000006 beq 8664 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xdc>
8648: e2544001 subs r4, r4, #1
864c: 3affffe5 bcc 85e8 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x60>
8650: e3a00001 mov r0, #1
8654: ebffffab bl 8508 <_ZN12RaspberryLib12MailboxCheckEc>
8658: e3500000 cmp r0, #0
865c: e3a00001 mov r0, #1
8660: 1afffff4 bne 8638 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xb0>
8664: e3540000 cmp r4, #0
8668: 1affffde bne 85e8 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x60>
866c: e59f002c ldr r0, [pc, #44] ; 86a0 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x118>
8670: ebffff8f bl 84b4 <_ZN12RaspberryLib7PiFaultEPKc>
8674: e3a00a02 mov r0, #8192 ; 0x2000
8678: e8bd4010 pop {r4, lr}
867c: e12fff1e bx lr
8680: e59f001c ldr r0, [pc, #28] ; 86a4 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x11c>
8684: ebffff8a bl 84b4 <_ZN12RaspberryLib7PiFaultEPKc>
8688: eafffff9 b 8674 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xec>
868c: e59f0014 ldr r0, [pc, #20] ; 86a8 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0x120>
8690: ebffff87 bl 84b4 <_ZN12RaspberryLib7PiFaultEPKc>
8694: eafffff6 b 8674 <_ZN12RaspberryLib18AcquireFrameBufferEjj+0xec>
8698: 40002000 andmi r2, r0, r0
869c: 0000270f andeq r2, r0, pc, lsl #14
86a0: 00009e78 andeq r9, r0, r8, ror lr
86a4: 00009f10 andeq r9, r0, r0, lsl pc
86a8: 00009ec0 andeq r9, r0, r0, asr #29
000086ac <_ZN11gpu2dCanvas15initFrameBufferEv>:
86ac: e5901004 ldr r1, [r0, #4]
86b0: e92d4010 push {r4, lr}
86b4: e2811101 add r1, r1, #1073741824 ; 0x40000000
86b8: e1a04000 mov r4, r0
86bc: e3a00001 mov r0, #1
86c0: ebffff7e bl 84c0 <_ZN12RaspberryLib12MailboxWriteEcj>
86c4: e3a00001 mov r0, #1
86c8: ebffff8e bl 8508 <_ZN12RaspberryLib12MailboxCheckEc>
86cc: e3500000 cmp r0, #0
86d0: 1afffffb bne 86c4 <_ZN11gpu2dCanvas15initFrameBufferEv+0x18>
86d4: e5943004 ldr r3, [r4, #4]
86d8: e5930020 ldr r0, [r3, #32]
86dc: e3500000 cmp r0, #0
86e0: 0a000009 beq 870c <_ZN11gpu2dCanvas15initFrameBufferEv+0x60>
86e4: e5932010 ldr r2, [r3, #16]
86e8: e3520000 cmp r2, #0
86ec: 01a00002 moveq r0, r2
86f0: 0a000005 beq 870c <_ZN11gpu2dCanvas15initFrameBufferEv+0x60>
86f4: e3500101 cmp r0, #1073741824 ; 0x40000000
86f8: 82800103 addhi r0, r0, #-1073741824 ; 0xc0000000
86fc: e3a0c001 mov ip, #1
8700: e5830020 str r0, [r3, #32]
8704: e5c4c000 strb ip, [r4]
8708: e1a0000c mov r0, ip
870c: e8bd4010 pop {r4, lr}
8710: e12fff1e bx lr
00008714 <_ZN11gpu2dCanvasC1Eb>:
8714: e92d4038 push {r3, r4, r5, lr}
8718: e1a04000 mov r4, r0
871c: e5c41002 strb r1, [r4, #2]
8720: e3a05a02 mov r5, #8192 ; 0x2000
8724: e3a0cb01 mov ip, #1024 ; 0x400
8728: e3510000 cmp r1, #0
872c: e3a01000 mov r1, #0
8730: e5845004 str r5, [r4, #4]
8734: e5c41000 strb r1, [r4]
8738: e3a00c03 mov r0, #768 ; 0x300
873c: e585c000 str ip, [r5]
8740: e585c008 str ip, [r5, #8]
8744: 13a0cc06 movne ip, #1536 ; 0x600
8748: e3a03a02 mov r3, #8192 ; 0x2000
874c: 0585000c streq r0, [r5, #12]
8750: 1585c00c strne ip, [r5, #12]
8754: e5850004 str r0, [r5, #4]
8758: e3a02018 mov r2, #24
875c: e3a05000 mov r5, #0
8760: e1a00004 mov r0, r4
8764: e5832014 str r2, [r3, #20]
8768: e5835018 str r5, [r3, #24]
876c: e583501c str r5, [r3, #28]
8770: e5835010 str r5, [r3, #16]
8774: e5835020 str r5, [r3, #32]
8778: e5835024 str r5, [r3, #36] ; 0x24
877c: ebffffca bl 86ac <_ZN11gpu2dCanvas15initFrameBufferEv>
8780: e1500005 cmp r0, r5
8784: 15c45001 strbne r5, [r4, #1]
8788: e1a00004 mov r0, r4
878c: e8bd4038 pop {r3, r4, r5, lr}
8790: e12fff1e bx lr
00008794 <_ZN11gpu2dCanvasC1Ev>:
8794: e92d4010 push {r4, lr}
8798: e24dd008 sub sp, sp, #8
879c: e1a04000 mov r4, r0
87a0: e3a01001 mov r1, #1
87a4: e1a0000d mov r0, sp
87a8: ebffffd9 bl 8714 <_ZN11gpu2dCanvasC1Eb>
87ac: e1a00004 mov r0, r4
87b0: e28dd008 add sp, sp, #8
87b4: e8bd4010 pop {r4, lr}
87b8: e12fff1e bx lr
000087bc <_ZN11gpu2dCanvas4DrawEv>:
87bc: e5d03000 ldrb r3, [r0]
87c0: e3530000 cmp r3, #0
87c4: e92d4010 push {r4, lr}
87c8: e1a04000 mov r4, r0
87cc: 0a00000d beq 8808 <_ZN11gpu2dCanvas4DrawEv+0x4c>
87d0: e5d00002 ldrb r0, [r0, #2]
87d4: e3500000 cmp r0, #0
87d8: 0a00000a beq 8808 <_ZN11gpu2dCanvas4DrawEv+0x4c>
87dc: e5d4e001 ldrb lr, [r4, #1]
87e0: e594c004 ldr ip, [r4, #4]
87e4: e35e0000 cmp lr, #0
87e8: 059c2004 ldreq r2, [ip, #4]
87ec: 13a02000 movne r2, #0
87f0: e58c201c str r2, [ip, #28]
87f4: e1a00004 mov r0, r4
87f8: ebffffab bl 86ac <_ZN11gpu2dCanvas15initFrameBufferEv>
87fc: e5d42001 ldrb r2, [r4, #1]
8800: e2221001 eor r1, r2, #1
8804: e5c41001 strb r1, [r4, #1]
8808: e8bd4010 pop {r4, lr}
880c: e12fff1e bx lr
00008810 <_ZN11gpu2dCanvas5ClearEj>:
8810: e5d03000 ldrb r3, [r0]
8814: e3530000 cmp r3, #0
8818: e92d05f0 push {r4, r5, r6, r7, r8, sl}
881c: 0a000029 beq 88c8 <_ZN11gpu2dCanvas5ClearEj+0xb8>
8820: e5d05001 ldrb r5, [r0, #1]
8824: e3550000 cmp r5, #0
8828: 0a000028 beq 88d0 <_ZN11gpu2dCanvas5ClearEj+0xc0>
882c: e5903004 ldr r3, [r0, #4]
8830: e5932004 ldr r2, [r3, #4]
8834: e3a0a000 mov sl, #0
8838: e20178ff and r7, r1, #16711680 ; 0xff0000
883c: e2016cff and r6, r1, #65280 ; 0xff00
8840: e3520000 cmp r2, #0
8844: e1a05827 lsr r5, r7, #16
8848: e1a06426 lsr r6, r6, #8
884c: e20170ff and r7, r1, #255 ; 0xff
8850: 13a08000 movne r8, #0
8854: 0a00001b beq 88c8 <_ZN11gpu2dCanvas5ClearEj+0xb8>
8858: e5932000 ldr r2, [r3]
885c: e3520000 cmp r2, #0
8860: 13a01000 movne r1, #0
8864: 1088400a addne r4, r8, sl
8868: 11a0c001 movne ip, r1
886c: 0a000011 beq 88b8 <_ZN11gpu2dCanvas5ClearEj+0xa8>
8870: e5932010 ldr r2, [r3, #16]
8874: e0221294 mla r2, r4, r2, r1
8878: e5933020 ldr r3, [r3, #32]
887c: e7c25003 strb r5, [r2, r3]
8880: e5903004 ldr r3, [r0, #4]
8884: e5933020 ldr r3, [r3, #32]
8888: e0823003 add r3, r2, r3
888c: e5c36001 strb r6, [r3, #1]
8890: e5903004 ldr r3, [r0, #4]
8894: e5933020 ldr r3, [r3, #32]
8898: e0823003 add r3, r2, r3
889c: e5c37002 strb r7, [r3, #2]
88a0: e5903004 ldr r3, [r0, #4]
88a4: e5932000 ldr r2, [r3]
88a8: e28cc001 add ip, ip, #1
88ac: e152000c cmp r2, ip
88b0: e2811003 add r1, r1, #3
88b4: 8affffed bhi 8870 <_ZN11gpu2dCanvas5ClearEj+0x60>
88b8: e5932004 ldr r2, [r3, #4]
88bc: e2888001 add r8, r8, #1
88c0: e1520008 cmp r2, r8
88c4: 8affffe3 bhi 8858 <_ZN11gpu2dCanvas5ClearEj+0x48>
88c8: e8bd05f0 pop {r4, r5, r6, r7, r8, sl}
88cc: e12fff1e bx lr
88d0: e5d0a002 ldrb sl, [r0, #2]
88d4: e5903004 ldr r3, [r0, #4]
88d8: e35a0000 cmp sl, #0
88dc: 1593a004 ldrne sl, [r3, #4]
88e0: 05932004 ldreq r2, [r3, #4]
88e4: 11a0200a movne r2, sl
88e8: eaffffd2 b 8838 <_ZN11gpu2dCanvas5ClearEj+0x28>
000088ec <_ZN11gpu2dCanvas4syncEv>:
88ec: e5d03002 ldrb r3, [r0, #2]
88f0: e3530000 cmp r3, #0
88f4: e92d00f0 push {r4, r5, r6, r7}
88f8: 0a000021 beq 8984 <_ZN11gpu2dCanvas4syncEv+0x98>
88fc: e5903004 ldr r3, [r0, #4]
8900: e5935004 ldr r5, [r3, #4]
8904: e3550000 cmp r5, #0
8908: e5d06001 ldrb r6, [r0, #1]
890c: 13a04000 movne r4, #0
8910: 0a00001b beq 8984 <_ZN11gpu2dCanvas4syncEv+0x98>
8914: e5932000 ldr r2, [r3]
8918: e3520000 cmp r2, #0
891c: 13a02000 movne r2, #0
8920: 11a01002 movne r1, r2
8924: 1a000001 bne 8930 <_ZN11gpu2dCanvas4syncEv+0x44>
8928: ea000012 b 8978 <_ZN11gpu2dCanvas4syncEv+0x8c>
892c: e5935004 ldr r5, [r3, #4]
8930: e593c020 ldr ip, [r3, #32]
8934: e5933010 ldr r3, [r3, #16]
8938: e0855004 add r5, r5, r4
893c: e082700c add r7, r2, ip
8940: e02cc493 mla ip, r3, r4, ip
8944: e0030395 mul r3, r5, r3
8948: e3560000 cmp r6, #0
894c: 17d2c00c ldrbne ip, [r2, ip]
8950: 07d73003 ldrbeq r3, [r7, r3]
8954: 17c7c003 strbne ip, [r7, r3]
8958: 07c2300c strbeq r3, [r2, ip]
895c: e5903004 ldr r3, [r0, #4]
8960: e593c000 ldr ip, [r3]
8964: e2811001 add r1, r1, #1
8968: e15c0001 cmp ip, r1
896c: e2822003 add r2, r2, #3
8970: 8affffed bhi 892c <_ZN11gpu2dCanvas4syncEv+0x40>
8974: e5935004 ldr r5, [r3, #4]
8978: e2844001 add r4, r4, #1
897c: e1540005 cmp r4, r5
8980: 3affffe3 bcc 8914 <_ZN11gpu2dCanvas4syncEv+0x28>
8984: e8bd00f0 pop {r4, r5, r6, r7}
8988: e12fff1e bx lr
0000898c <_ZN11gpu2dCanvas8setPixelEjjj>:
898c: e5d0c001 ldrb ip, [r0, #1]
8990: e35c0000 cmp ip, #0
8994: e92d0030 push {r4, r5}
8998: 1a000015 bne 89f4 <_ZN11gpu2dCanvas8setPixelEjjj+0x68>
899c: e5d05002 ldrb r5, [r0, #2]
89a0: e590c004 ldr ip, [r0, #4]
89a4: e3550000 cmp r5, #0
89a8: 159c5004 ldrne r5, [ip, #4]
89ac: e59c4010 ldr r4, [ip, #16]
89b0: e0852002 add r2, r5, r2
89b4: e0811081 add r1, r1, r1, lsl #1
89b8: e0211294 mla r1, r4, r2, r1
89bc: e59c2020 ldr r2, [ip, #32]
89c0: e1a0c823 lsr ip, r3, #16
89c4: e7c1c002 strb ip, [r1, r2]
89c8: e590c004 ldr ip, [r0, #4]
89cc: e59c2020 ldr r2, [ip, #32]
89d0: e1a0c423 lsr ip, r3, #8
89d4: e0812002 add r2, r1, r2
89d8: e5c2c001 strb ip, [r2, #1]
89dc: e5900004 ldr r0, [r0, #4]
89e0: e5902020 ldr r2, [r0, #32]
89e4: e0811002 add r1, r1, r2
89e8: e5c13002 strb r3, [r1, #2]
89ec: e8bd0030 pop {r4, r5}
89f0: e12fff1e bx lr
89f4: e590c004 ldr ip, [r0, #4]
89f8: e3a05000 mov r5, #0
89fc: eaffffea b 89ac <_ZN11gpu2dCanvas8setPixelEjjj+0x20>
00008a00 <_ZN11gpu2dCanvas8DrawLineEiiiij>:
8a00: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8a04: e1530001 cmp r3, r1
8a08: e24dd00c sub sp, sp, #12
8a0c: e1a05001 mov r5, r1
8a10: e1a0a003 mov sl, r3
8a14: e1a07000 mov r7, r0
8a18: e1a04002 mov r4, r2
8a1c: e59d8034 ldr r8, [sp, #52] ; 0x34
8a20: da000039 ble 8b0c <_ZN11gpu2dCanvas8DrawLineEiiiij+0x10c>
8a24: e59d6030 ldr r6, [sp, #48] ; 0x30
8a28: e062c006 rsb ip, r2, r6
8a2c: e0613003 rsb r3, r1, r3
8a30: e1a0b08c lsl fp, ip, #1
8a34: e1e0e001 mvn lr, r1
8a38: e063900c rsb r9, r3, ip
8a3c: e063600b rsb r6, r3, fp
8a40: e08e300a add r3, lr, sl
8a44: e203c001 and ip, r3, #1
8a48: e3560000 cmp r6, #0
8a4c: e1a09089 lsl r9, r9, #1
8a50: e58dc004 str ip, [sp, #4]
8a54: da00003d ble 8b50 <_ZN11gpu2dCanvas8DrawLineEiiiij+0x150>
8a58: e2824001 add r4, r2, #1
8a5c: e1a02004 mov r2, r4
8a60: e1a03008 mov r3, r8
8a64: ebffffc8 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8a68: e0866009 add r6, r6, r9
8a6c: e2855001 add r5, r5, #1
8a70: e15a0005 cmp sl, r5
8a74: da000024 ble 8b0c <_ZN11gpu2dCanvas8DrawLineEiiiij+0x10c>
8a78: e59d0004 ldr r0, [sp, #4]
8a7c: e3500000 cmp r0, #0
8a80: 0a00000b beq 8ab4 <_ZN11gpu2dCanvas8DrawLineEiiiij+0xb4>
8a84: e3560000 cmp r6, #0
8a88: da000022 ble 8b18 <_ZN11gpu2dCanvas8DrawLineEiiiij+0x118>
8a8c: e2844001 add r4, r4, #1
8a90: e1a00007 mov r0, r7
8a94: e1a01005 mov r1, r5
8a98: e1a02004 mov r2, r4
8a9c: e1a03008 mov r3, r8
8aa0: ebffffb9 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8aa4: e0866009 add r6, r6, r9
8aa8: e2855001 add r5, r5, #1
8aac: e15a0005 cmp sl, r5
8ab0: da000015 ble 8b0c <_ZN11gpu2dCanvas8DrawLineEiiiij+0x10c>
8ab4: e3560000 cmp r6, #0
8ab8: da00001d ble 8b34 <_ZN11gpu2dCanvas8DrawLineEiiiij+0x134>
8abc: e2844001 add r4, r4, #1
8ac0: e1a00007 mov r0, r7
8ac4: e1a01005 mov r1, r5
8ac8: e1a02004 mov r2, r4
8acc: e1a03008 mov r3, r8
8ad0: ebffffad bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8ad4: e0866009 add r6, r6, r9
8ad8: e2855001 add r5, r5, #1
8adc: e3560000 cmp r6, #0
8ae0: e1a00007 mov r0, r7
8ae4: e1a03008 mov r3, r8
8ae8: e1a01005 mov r1, r5
8aec: da000009 ble 8b18 <_ZN11gpu2dCanvas8DrawLineEiiiij+0x118>
8af0: e2844001 add r4, r4, #1
8af4: e1a02004 mov r2, r4
8af8: e2855001 add r5, r5, #1
8afc: ebffffa2 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8b00: e15a0005 cmp sl, r5
8b04: e0866009 add r6, r6, r9
8b08: caffffe9 bgt 8ab4 <_ZN11gpu2dCanvas8DrawLineEiiiij+0xb4>
8b0c: e28dd00c add sp, sp, #12
8b10: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8b14: e12fff1e bx lr
8b18: e1a00007 mov r0, r7
8b1c: e1a01005 mov r1, r5
8b20: e1a02004 mov r2, r4
8b24: e1a03008 mov r3, r8
8b28: ebffff97 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8b2c: e086600b add r6, r6, fp
8b30: eaffffdc b 8aa8 <_ZN11gpu2dCanvas8DrawLineEiiiij+0xa8>
8b34: e1a01005 mov r1, r5
8b38: e1a02004 mov r2, r4
8b3c: e1a00007 mov r0, r7
8b40: e1a03008 mov r3, r8
8b44: ebffff90 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8b48: e086600b add r6, r6, fp
8b4c: eaffffe1 b 8ad8 <_ZN11gpu2dCanvas8DrawLineEiiiij+0xd8>
8b50: e1a03008 mov r3, r8
8b54: ebffff8c bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8b58: e086600b add r6, r6, fp
8b5c: eaffffc2 b 8a6c <_ZN11gpu2dCanvas8DrawLineEiiiij+0x6c>
00008b60 <_ZN11gpu2dCanvas13DrawCharacterEiicj>:
8b60: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8b64: e1a04203 lsl r4, r3, #4
8b68: e24dd054 sub sp, sp, #84 ; 0x54
8b6c: e284b007 add fp, r4, #7
8b70: e58db03c str fp, [sp, #60] ; 0x3c
8b74: e284b008 add fp, r4, #8
8b78: e58db004 str fp, [sp, #4]
8b7c: e284b009 add fp, r4, #9
8b80: e58db008 str fp, [sp, #8]
8b84: e284b00a add fp, r4, #10
8b88: e58db00c str fp, [sp, #12]
8b8c: e284b00b add fp, r4, #11
8b90: e58db010 str fp, [sp, #16]
8b94: e284b00c add fp, r4, #12
8b98: e58db014 str fp, [sp, #20]
8b9c: e284b00d add fp, r4, #13
8ba0: e58db018 str fp, [sp, #24]
8ba4: e2847001 add r7, r4, #1
8ba8: e2846002 add r6, r4, #2
8bac: e2845003 add r5, r4, #3
8bb0: e2848004 add r8, r4, #4
8bb4: e284a005 add sl, r4, #5
8bb8: e2849006 add r9, r4, #6
8bbc: e284b00e add fp, r4, #14
8bc0: e284400f add r4, r4, #15
8bc4: e58db01c str fp, [sp, #28]
8bc8: e58d4000 str r4, [sp]
8bcc: e59fc248 ldr ip, [pc, #584] ; 8e1c <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x2bc>
8bd0: e7dc3203 ldrb r3, [ip, r3, lsl #4]
8bd4: e58d3020 str r3, [sp, #32]
8bd8: e7dcb007 ldrb fp, [ip, r7]
8bdc: e58db024 str fp, [sp, #36] ; 0x24
8be0: e7dc4006 ldrb r4, [ip, r6]
8be4: e58d4028 str r4, [sp, #40] ; 0x28
8be8: e7dc3005 ldrb r3, [ip, r5]
8bec: e58d302c str r3, [sp, #44] ; 0x2c
8bf0: e7dc6008 ldrb r6, [ip, r8]
8bf4: e58d6030 str r6, [sp, #48] ; 0x30
8bf8: e7dc700a ldrb r7, [ip, sl]
8bfc: e58d7034 str r7, [sp, #52] ; 0x34
8c00: e7dca009 ldrb sl, [ip, r9]
8c04: e59d803c ldr r8, [sp, #60] ; 0x3c
8c08: e58da038 str sl, [sp, #56] ; 0x38
8c0c: e7dcb008 ldrb fp, [ip, r8]
8c10: e59d5004 ldr r5, [sp, #4]
8c14: e58db03c str fp, [sp, #60] ; 0x3c
8c18: e59d4008 ldr r4, [sp, #8]
8c1c: e28d300c add r3, sp, #12
8c20: e89302c8 ldm r3, {r3, r6, r7, r9}
8c24: e59da01c ldr sl, [sp, #28]
8c28: e7dcb005 ldrb fp, [ip, r5]
8c2c: e59d8000 ldr r8, [sp]
8c30: e7dc5004 ldrb r5, [ip, r4]
8c34: e7dc4003 ldrb r4, [ip, r3]
8c38: e7dc3006 ldrb r3, [ip, r6]
8c3c: e7dc6007 ldrb r6, [ip, r7]
8c40: e7dc7009 ldrb r7, [ip, r9]
8c44: e7dc900a ldrb r9, [ip, sl]
8c48: e1a0a001 mov sl, r1
8c4c: e59d1020 ldr r1, [sp, #32]
8c50: e7dcc008 ldrb ip, [ip, r8]
8c54: e59d8078 ldr r8, [sp, #120] ; 0x78
8c58: e5cd1040 strb r1, [sp, #64] ; 0x40
8c5c: e59d1024 ldr r1, [sp, #36] ; 0x24
8c60: e5cd1041 strb r1, [sp, #65] ; 0x41
8c64: e59d1028 ldr r1, [sp, #40] ; 0x28
8c68: e5cd1042 strb r1, [sp, #66] ; 0x42
8c6c: e59d102c ldr r1, [sp, #44] ; 0x2c
8c70: e5cd1043 strb r1, [sp, #67] ; 0x43
8c74: e59d1030 ldr r1, [sp, #48] ; 0x30
8c78: e5cd1044 strb r1, [sp, #68] ; 0x44
8c7c: e59d1034 ldr r1, [sp, #52] ; 0x34
8c80: e5cd1045 strb r1, [sp, #69] ; 0x45
8c84: e59d1038 ldr r1, [sp, #56] ; 0x38
8c88: e5cd1046 strb r1, [sp, #70] ; 0x46
8c8c: e59d103c ldr r1, [sp, #60] ; 0x3c
8c90: e5cd304b strb r3, [sp, #75] ; 0x4b
8c94: e5cd1047 strb r1, [sp, #71] ; 0x47
8c98: e5cd704d strb r7, [sp, #77] ; 0x4d
8c9c: e28a1002 add r1, sl, #2
8ca0: e1a07000 mov r7, r0
8ca4: e28a3003 add r3, sl, #3
8ca8: e28d0040 add r0, sp, #64 ; 0x40
8cac: e5cdb048 strb fp, [sp, #72] ; 0x48
8cb0: e5cd5049 strb r5, [sp, #73] ; 0x49
8cb4: e5cd604c strb r6, [sp, #76] ; 0x4c
8cb8: e5cd904e strb r9, [sp, #78] ; 0x4e
8cbc: e5cd404a strb r4, [sp, #74] ; 0x4a
8cc0: e5cdc04f strb ip, [sp, #79] ; 0x4f
8cc4: e2406001 sub r6, r0, #1
8cc8: e1a05002 mov r5, r2
8ccc: e280900f add r9, r0, #15
8cd0: e28ab001 add fp, sl, #1
8cd4: e88d000a stm sp, {r1, r3}
8cd8: ea000010 b 8d20 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x1c0>
8cdc: e3140002 tst r4, #2
8ce0: 1a000018 bne 8d48 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x1e8>
8ce4: e3140004 tst r4, #4
8ce8: 1a00001d bne 8d64 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x204>
8cec: e3140008 tst r4, #8
8cf0: 1a000022 bne 8d80 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x220>
8cf4: e3140010 tst r4, #16
8cf8: 1a000027 bne 8d9c <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x23c>
8cfc: e3140020 tst r4, #32
8d00: 1a00002c bne 8db8 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x258>
8d04: e3140040 tst r4, #64 ; 0x40
8d08: 1a000031 bne 8dd4 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x274>
8d0c: e1b043a4 lsrs r4, r4, #7
8d10: 1a000036 bne 8df0 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x290>
8d14: e1560009 cmp r6, r9
8d18: e2855001 add r5, r5, #1
8d1c: 0a00003b beq 8e10 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x2b0>
8d20: e5f64001 ldrb r4, [r6, #1]!
8d24: e3140001 tst r4, #1
8d28: 0affffeb beq 8cdc <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x17c>
8d2c: e1a00007 mov r0, r7
8d30: e1a0100a mov r1, sl
8d34: e1a02005 mov r2, r5
8d38: e1a03008 mov r3, r8
8d3c: ebffff12 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8d40: e3140002 tst r4, #2
8d44: 0affffe6 beq 8ce4 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x184>
8d48: e1a00007 mov r0, r7
8d4c: e1a0100b mov r1, fp
8d50: e1a02005 mov r2, r5
8d54: e1a03008 mov r3, r8
8d58: ebffff0b bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8d5c: e3140004 tst r4, #4
8d60: 0affffe1 beq 8cec <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x18c>
8d64: e1a00007 mov r0, r7
8d68: e59d1000 ldr r1, [sp]
8d6c: e1a02005 mov r2, r5
8d70: e1a03008 mov r3, r8
8d74: ebffff04 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8d78: e3140008 tst r4, #8
8d7c: 0affffdc beq 8cf4 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x194>
8d80: e1a00007 mov r0, r7
8d84: e59d1004 ldr r1, [sp, #4]
8d88: e1a02005 mov r2, r5
8d8c: e1a03008 mov r3, r8
8d90: ebfffefd bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8d94: e3140010 tst r4, #16
8d98: 0affffd7 beq 8cfc <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x19c>
8d9c: e1a00007 mov r0, r7
8da0: e28a1004 add r1, sl, #4
8da4: e1a02005 mov r2, r5
8da8: e1a03008 mov r3, r8
8dac: ebfffef6 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8db0: e3140020 tst r4, #32
8db4: 0affffd2 beq 8d04 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x1a4>
8db8: e1a00007 mov r0, r7
8dbc: e28a1005 add r1, sl, #5
8dc0: e1a02005 mov r2, r5
8dc4: e1a03008 mov r3, r8
8dc8: ebfffeef bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8dcc: e3140040 tst r4, #64 ; 0x40
8dd0: 0affffcd beq 8d0c <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x1ac>
8dd4: e1a00007 mov r0, r7
8dd8: e28a1006 add r1, sl, #6
8ddc: e1a02005 mov r2, r5
8de0: e1a03008 mov r3, r8
8de4: ebfffee8 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8de8: e1b043a4 lsrs r4, r4, #7
8dec: 0affffc8 beq 8d14 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x1b4>
8df0: e1a02005 mov r2, r5
8df4: e1a00007 mov r0, r7
8df8: e28a1007 add r1, sl, #7
8dfc: e1a03008 mov r3, r8
8e00: ebfffee1 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8e04: e1560009 cmp r6, r9
8e08: e2855001 add r5, r5, #1
8e0c: 1affffc3 bne 8d20 <_ZN11gpu2dCanvas13DrawCharacterEiicj+0x1c0>
8e10: e28dd054 add sp, sp, #84 ; 0x54
8e14: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8e18: e12fff1e bx lr
8e1c: 0000951c andeq r9, r0, ip, lsl r5
00008e20 <_ZN11gpu2dCanvas14ClearCharacterEii>:
8e20: e92d4ff8 push {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
8e24: e3a08000 mov r8, #0
8e28: e1a06000 mov r6, r0
8e2c: e1a09001 mov r9, r1
8e30: e1a0b002 mov fp, r2
8e34: e1a07008 mov r7, r8
8e38: e1a04807 lsl r4, r7, #16
8e3c: e1a04844 asr r4, r4, #16
8e40: e3540007 cmp r4, #7
8e44: ca000027 bgt 8ee8 <_ZN11gpu2dCanvas14ClearCharacterEii+0xc8>
8e48: e0844009 add r4, r4, r9
8e4c: e088500b add r5, r8, fp
8e50: e1a01004 mov r1, r4
8e54: e1a02005 mov r2, r5
8e58: e1a00006 mov r0, r6
8e5c: e3a03000 mov r3, #0
8e60: ebfffec9 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8e64: e2872001 add r2, r7, #1
8e68: e1a01802 lsl r1, r2, #16
8e6c: e267a007 rsb sl, r7, #7
8e70: e3510807 cmp r1, #458752 ; 0x70000
8e74: e20aa001 and sl, sl, #1
8e78: e2844001 add r4, r4, #1
8e7c: e1a07821 lsr r7, r1, #16
8e80: ca000017 bgt 8ee4 <_ZN11gpu2dCanvas14ClearCharacterEii+0xc4>
8e84: e35a0000 cmp sl, #0
8e88: 11a01004 movne r1, r4
8e8c: 11a00006 movne r0, r6
8e90: 1a00000a bne 8ec0 <_ZN11gpu2dCanvas14ClearCharacterEii+0xa0>
8e94: e1a01004 mov r1, r4
8e98: e1a00006 mov r0, r6
8e9c: e1a02005 mov r2, r5
8ea0: e3a03000 mov r3, #0
8ea4: ebfffeb8 bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8ea8: e2870001 add r0, r7, #1
8eac: e1a07800 lsl r7, r0, #16
8eb0: e2844001 add r4, r4, #1
8eb4: e1a07827 lsr r7, r7, #16
8eb8: e1a00006 mov r0, r6
8ebc: e1a01004 mov r1, r4
8ec0: e3a03000 mov r3, #0
8ec4: e1a02005 mov r2, r5
8ec8: ebfffeaf bl 898c <_ZN11gpu2dCanvas8setPixelEjjj>
8ecc: e287c001 add ip, r7, #1
8ed0: e1a0380c lsl r3, ip, #16
8ed4: e3530807 cmp r3, #458752 ; 0x70000
8ed8: e2844001 add r4, r4, #1
8edc: e1a07823 lsr r7, r3, #16
8ee0: daffffeb ble 8e94 <_ZN11gpu2dCanvas14ClearCharacterEii+0x74>
8ee4: e3a07008 mov r7, #8
8ee8: e2888001 add r8, r8, #1
8eec: e3580010 cmp r8, #16
8ef0: 1affffd0 bne 8e38 <_ZN11gpu2dCanvas14ClearCharacterEii+0x18>
8ef4: e8bd4ff8 pop {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
8ef8: e12fff1e bx lr
00008efc <_ZN7Console5clearEv>:
8efc: e92d4010 push {r4, lr}
8f00: e3a01000 mov r1, #0
8f04: e1a04000 mov r4, r0
8f08: e3a03001 mov r3, #1
8f0c: e590000c ldr r0, [r0, #12]
8f10: e884000a stm r4, {r1, r3}
8f14: ebfffe3d bl 8810 <_ZN11gpu2dCanvas5ClearEj>
8f18: e594000c ldr r0, [r4, #12]
8f1c: e8bd4010 pop {r4, lr}
8f20: eafffe25 b 87bc <_ZN11gpu2dCanvas4DrawEv>
00008f24 <_ZN7Console7newLineEv>:
8f24: e590c004 ldr ip, [r0, #4]
8f28: e28c1001 add r1, ip, #1
8f2c: e3a02000 mov r2, #0
8f30: e351002d cmp r1, #45 ; 0x2d
8f34: e5801004 str r1, [r0, #4]
8f38: e5802000 str r2, [r0]
8f3c: 912fff1e bxls lr
8f40: eaffffed b 8efc <_ZN7Console5clearEv>
00008f44 <_ZN7Console9printCharEcj>:
8f44: e92d4070 push {r4, r5, r6, lr}
8f48: e3510009 cmp r1, #9
8f4c: e24dd008 sub sp, sp, #8
8f50: e1a06001 mov r6, r1
8f54: e1a04000 mov r4, r0
8f58: e1a05002 mov r5, r2
8f5c: 0a00002a beq 900c <_ZN7Console9printCharEcj+0xc8>
8f60: e351000a cmp r1, #10
8f64: 0a000025 beq 9000 <_ZN7Console9printCharEcj+0xbc>
8f68: e3510008 cmp r1, #8
8f6c: 0a000015 beq 8fc8 <_ZN7Console9printCharEcj+0x84>
8f70: e590c000 ldr ip, [r0]
8f74: e35c0078 cmp ip, #120 ; 0x78
8f78: 8a00002c bhi 9030 <_ZN7Console9printCharEcj+0xec>
8f7c: e5943004 ldr r3, [r4, #4]
8f80: e353002d cmp r3, #45 ; 0x2d
8f84: 8a000025 bhi 9020 <_ZN7Console9printCharEcj+0xdc>
8f88: e594e008 ldr lr, [r4, #8]
8f8c: e5941000 ldr r1, [r4]
8f90: e08e2203 add r2, lr, r3, lsl #4
8f94: e594000c ldr r0, [r4, #12]
8f98: e1a03006 mov r3, r6
8f9c: e08e1181 add r1, lr, r1, lsl #3
8fa0: e58d5000 str r5, [sp]
8fa4: ebfffeed bl 8b60 <_ZN11gpu2dCanvas13DrawCharacterEiicj>
8fa8: e594000c ldr r0, [r4, #12]
8fac: ebfffe02 bl 87bc <_ZN11gpu2dCanvas4DrawEv>
8fb0: e5942000 ldr r2, [r4]
8fb4: e2823001 add r3, r2, #1
8fb8: e5843000 str r3, [r4]
8fbc: e28dd008 add sp, sp, #8
8fc0: e8bd4070 pop {r4, r5, r6, lr}
8fc4: e12fff1e bx lr
8fc8: e5901000 ldr r1, [r0]
8fcc: e3510000 cmp r1, #0
8fd0: 0afffff9 beq 8fbc <_ZN7Console9printCharEcj+0x78>
8fd4: e990000c ldmib r0, {r2, r3}
8fd8: e2411001 sub r1, r1, #1
8fdc: e5841000 str r1, [r4]
8fe0: e590000c ldr r0, [r0, #12]
8fe4: e0831181 add r1, r3, r1, lsl #3
8fe8: e0832202 add r2, r3, r2, lsl #4
8fec: ebffff8b bl 8e20 <_ZN11gpu2dCanvas14ClearCharacterEii>
8ff0: e594000c ldr r0, [r4, #12]
8ff4: e28dd008 add sp, sp, #8
8ff8: e8bd4070 pop {r4, r5, r6, lr}
8ffc: eafffdee b 87bc <_ZN11gpu2dCanvas4DrawEv>
9000: e28dd008 add sp, sp, #8
9004: e8bd4070 pop {r4, r5, r6, lr}
9008: eaffffc5 b 8f24 <_ZN7Console7newLineEv>
900c: e5900000 ldr r0, [r0]
9010: e2803004 add r3, r0, #4
9014: e3530077 cmp r3, #119 ; 0x77
9018: 95843000 strls r3, [r4]
901c: eaffffe6 b 8fbc <_ZN7Console9printCharEcj+0x78>
9020: e1a00004 mov r0, r4
9024: e28dd008 add sp, sp, #8
9028: e8bd4070 pop {r4, r5, r6, lr}
902c: eaffffb2 b 8efc <_ZN7Console5clearEv>
9030: ebffffbb bl 8f24 <_ZN7Console7newLineEv>
9034: eaffffd0 b 8f7c <_ZN7Console9printCharEcj+0x38>
00009038 <_ZN7Console6kprintEPc>:
9038: e92d4038 push {r3, r4, r5, lr}
903c: e1a04001 mov r4, r1
9040: e5d11000 ldrb r1, [r1]
9044: e3510000 cmp r1, #0
9048: e1a05000 mov r5, r0
904c: 0a000005 beq 9068 <_ZN7Console6kprintEPc+0x30>
9050: e1a00005 mov r0, r5
9054: e3e024ff mvn r2, #-16777216 ; 0xff000000
9058: ebffffb9 bl 8f44 <_ZN7Console9printCharEcj>
905c: e5f41001 ldrb r1, [r4, #1]!
9060: e3510000 cmp r1, #0
9064: 1afffff9 bne 9050 <_ZN7Console6kprintEPc+0x18>
9068: e8bd4038 pop {r3, r4, r5, lr}
906c: e12fff1e bx lr
00009070 <_ZN7Console6kprintEPKc>:
9070: eafffff0 b 9038 <_ZN7Console6kprintEPc>
00009074 <_ZN7Console4koutEPKc>:
9074: e92d4070 push {r4, r5, r6, lr}
9078: e59f4040 ldr r4, [pc, #64] ; 90c0 <_ZN7Console4koutEPKc+0x4c>
907c: e1a06001 mov r6, r1
9080: e1a05000 mov r5, r0
9084: e3a0105b mov r1, #91 ; 0x5b
9088: e1a00005 mov r0, r5
908c: e3a028ff mov r2, #16711680 ; 0xff0000
9090: ebffffab bl 8f44 <_ZN7Console9printCharEcj>
9094: e5f41001 ldrb r1, [r4, #1]!
9098: e3510000 cmp r1, #0
909c: 1afffff9 bne 9088 <_ZN7Console4koutEPKc+0x14>
90a0: e1a01006 mov r1, r6
90a4: e1a00005 mov r0, r5
90a8: ebffffe2 bl 9038 <_ZN7Console6kprintEPc>
90ac: e1a00005 mov r0, r5
90b0: e3a0100a mov r1, #10
90b4: e3a028ff mov r2, #16711680 ; 0xff0000
90b8: e8bd4070 pop {r4, r5, r6, lr}
90bc: eaffffa0 b 8f44 <_ZN7Console9printCharEcj>
90c0: 00009f58 andeq r9, r0, r8, asr pc
000090c4 <irq_handler>:
90c4: e92d4008 push {r3, lr}
90c8: e59f303c ldr r3, [pc, #60] ; 910c <irq_handler+0x48>
90cc: e5d32004 ldrb r2, [r3, #4]
90d0: e3520000 cmp r2, #0
90d4: 1a000008 bne 90fc <irq_handler+0x38>
90d8: e59f2030 ldr r2, [pc, #48] ; 9110 <irq_handler+0x4c>
90dc: e5920004 ldr r0, [r2, #4]
90e0: e2801b4e add r1, r0, #79872 ; 0x13800
90e4: e2811080 add r1, r1, #128 ; 0x80
90e8: e5923004 ldr r3, [r2, #4]
90ec: e1510003 cmp r1, r3
90f0: 8afffffc bhi 90e8 <irq_handler+0x24>
90f4: e8bd4008 pop {r3, lr}
90f8: e12fff1e bx lr
90fc: e5930008 ldr r0, [r3, #8]
9100: e59f100c ldr r1, [pc, #12] ; 9114 <irq_handler+0x50>
9104: ebffffda bl 9074 <_ZN7Console4koutEPKc>
9108: eafffff2 b 90d8 <irq_handler+0x14>
910c: 00009d24 andeq r9, r0, r4, lsr #26
9110: 20003000 andcs r3, r0, r0
9114: 00009f60 andeq r9, r0, r0, ror #30
00009118 <_ZN7ConsoleC1EP11gpu2dCanvas>:
9118: e3a02000 mov r2, #0
911c: e3a0300a mov r3, #10
9120: e92d4010 push {r4, lr}
9124: e1a04000 mov r4, r0
9128: e5802000 str r2, [r0]
912c: e980000c stmib r0, {r2, r3}
9130: e580100c str r1, [r0, #12]
9134: ebffff70 bl 8efc <_ZN7Console5clearEv>
9138: e1a00004 mov r0, r4
913c: e8bd4010 pop {r4, lr}
9140: e12fff1e bx lr
00009144 <_Z12print_headerP7Console>:
9144: e92d4010 push {r4, lr}
9148: e59f102c ldr r1, [pc, #44] ; 917c <_Z12print_headerP7Console+0x38>
914c: e1a04000 mov r4, r0
9150: ebffffb8 bl 9038 <_ZN7Console6kprintEPc>
9154: e1a00004 mov r0, r4
9158: e59f1020 ldr r1, [pc, #32] ; 9180 <_Z12print_headerP7Console+0x3c>
915c: ebffffb5 bl 9038 <_ZN7Console6kprintEPc>
9160: e1a00004 mov r0, r4
9164: e59f1018 ldr r1, [pc, #24] ; 9184 <_Z12print_headerP7Console+0x40>
9168: ebffffb2 bl 9038 <_ZN7Console6kprintEPc>
916c: e59f1014 ldr r1, [pc, #20] ; 9188 <_Z12print_headerP7Console+0x44>
9170: e1a00004 mov r0, r4
9174: e8bd4010 pop {r4, lr}
9178: eaffffae b 9038 <_ZN7Console6kprintEPc>
917c: 00009f6c andeq r9, r0, ip, ror #30
9180: 00009fb0 ; <UNDEFINED> instruction: 0x00009fb0
9184: 00009fb8 ; <UNDEFINED> instruction: 0x00009fb8
9188: 00009fc0 andeq r9, r0, r0, asr #31
0000918c <kmain>:
918c: e92d40f0 push {r4, r5, r6, r7, lr}
9190: e24dd01c sub sp, sp, #28
9194: e28d4010 add r4, sp, #16
9198: e3a01000 mov r1, #0
919c: e1a00004 mov r0, r4
91a0: ebfffd5b bl 8714 <_ZN11gpu2dCanvasC1Eb>
91a4: e59f715c ldr r7, [pc, #348] ; 9308 <kmain+0x17c>
91a8: e3a0200a mov r2, #10
91ac: e3a05000 mov r5, #0
91b0: e1a0000d mov r0, sp
91b4: e58d2008 str r2, [sp, #8]
91b8: e58d400c str r4, [sp, #12]
91bc: e58d5000 str r5, [sp]
91c0: e58d5004 str r5, [sp, #4]
91c4: ebffff4c bl 8efc <_ZN7Console5clearEv>
91c8: e28d1000 add r1, sp, #0
91cc: e3a03001 mov r3, #1
91d0: e1a0000d mov r0, sp
91d4: e5871008 str r1, [r7, #8]
91d8: e5c73004 strb r3, [r7, #4]
91dc: ebffffd8 bl 9144 <_Z12print_headerP7Console>
91e0: e1a0000d mov r0, sp
91e4: e59f1120 ldr r1, [pc, #288] ; 930c <kmain+0x180>
91e8: ebffff92 bl 9038 <_ZN7Console6kprintEPc>
91ec: e59f411c ldr r4, [pc, #284] ; 9310 <kmain+0x184>
91f0: e3a06012 mov r6, #18
91f4: e1a0000d mov r0, sp
91f8: e59f1114 ldr r1, [pc, #276] ; 9314 <kmain+0x188>
91fc: ebffff8d bl 9038 <_ZN7Console6kprintEPc>
9200: e594c004 ldr ip, [r4, #4]
9204: e28c0bea add r0, ip, #239616 ; 0x3a800
9208: e2802d06 add r2, r0, #384 ; 0x180
920c: e594e004 ldr lr, [r4, #4]
9210: e152000e cmp r2, lr
9214: e59f50f4 ldr r5, [pc, #244] ; 9310 <kmain+0x184>
9218: 8afffffb bhi 920c <kmain+0x80>
921c: e2566001 subs r6, r6, #1
9220: 1afffff3 bne 91f4 <kmain+0x68>
9224: e1a0000d mov r0, sp
9228: e59f10e8 ldr r1, [pc, #232] ; 9318 <kmain+0x18c>
922c: ebffff81 bl 9038 <_ZN7Console6kprintEPc>
9230: e3a0380f mov r3, #983040 ; 0xf0000
9234: e3a0caff mov ip, #1044480 ; 0xff000
9238: e5873000 str r3, [r7]
923c: e1a0000d mov r0, sp
9240: e59f10d4 ldr r1, [pc, #212] ; 931c <kmain+0x190>
9244: e5c36004 strb r6, [r3, #4]
9248: e583c008 str ip, [r3, #8]
924c: ebffff88 bl 9074 <_ZN7Console4koutEPKc>
9250: e59f00c8 ldr r0, [pc, #200] ; 9320 <kmain+0x194>
9254: e3e02000 mvn r2, #0
9258: e3a040ff mov r4, #255 ; 0xff
925c: e5802840 str r2, [r0, #2112] ; 0x840
9260: e5802850 str r2, [r0, #2128] ; 0x850
9264: e5804860 str r4, [r0, #2144] ; 0x860
9268: e5951004 ldr r1, [r5, #4]
926c: e2813a61 add r3, r1, #397312 ; 0x61000
9270: e2832d2a add r2, r3, #2688 ; 0xa80
9274: e595e004 ldr lr, [r5, #4]
9278: e152000e cmp r2, lr
927c: e59f408c ldr r4, [pc, #140] ; 9310 <kmain+0x184>
9280: 8afffffb bhi 9274 <kmain+0xe8>
9284: e59f1098 ldr r1, [pc, #152] ; 9324 <kmain+0x198>
9288: e1a0000d mov r0, sp
928c: ebffff78 bl 9074 <_ZN7Console4koutEPKc>
9290: e1a0000d mov r0, sp
9294: e59f108c ldr r1, [pc, #140] ; 9328 <kmain+0x19c>
9298: ebffff66 bl 9038 <_ZN7Console6kprintEPc>
929c: e5940004 ldr r0, [r4, #4]
92a0: e280183d add r1, r0, #3997696 ; 0x3d0000
92a4: e2812c09 add r2, r1, #2304 ; 0x900
92a8: e594c004 ldr ip, [r4, #4]
92ac: e152000c cmp r2, ip
92b0: e59f3058 ldr r3, [pc, #88] ; 9310 <kmain+0x184>
92b4: 8afffffb bhi 92a8 <kmain+0x11c>
92b8: ef0000ff svc 0x000000ff
92bc: e593e004 ldr lr, [r3, #4]
92c0: e28e2a61 add r2, lr, #397312 ; 0x61000
92c4: e2821d2a add r1, r2, #2688 ; 0xa80
92c8: e1a02003 mov r2, r3
92cc: e5923004 ldr r3, [r2, #4]
92d0: e1510003 cmp r1, r3
92d4: 8afffffc bhi 92cc <kmain+0x140>
92d8: e1a0000d mov r0, sp
92dc: e59f1048 ldr r1, [pc, #72] ; 932c <kmain+0x1a0>
92e0: ebffff63 bl 9074 <_ZN7Console4koutEPKc>
92e4: e3a01001 mov r1, #1
92e8: e3a00010 mov r0, #16
92ec: ebfffc12 bl 833c <_ZN12RaspberryLib7SetGPIOEjj>
92f0: e1a0000d mov r0, sp
92f4: e59f1034 ldr r1, [pc, #52] ; 9330 <kmain+0x1a4>
92f8: ebffff4e bl 9038 <_ZN7Console6kprintEPc>
92fc: e28dd01c add sp, sp, #28
9300: e8bd40f0 pop {r4, r5, r6, r7, lr}
9304: e12fff1e bx lr
9308: 00009d24 andeq r9, r0, r4, lsr #26
930c: 00009fc4 andeq r9, r0, r4, asr #31
9310: 20003000 andcs r3, r0, r0
9314: 0000a068 andeq sl, r0, r8, rrx
9318: 00009fd0 ldrdeq r9, [r0], -r0
931c: 00009fe0 andeq r9, r0, r0, ror #31
9320: 2000b000 andcs fp, r0, r0
9324: 00009ff8 strdeq r9, [r0], -r8
9328: 0000a014 andeq sl, r0, r4, lsl r0
932c: 0000a038 andeq sl, r0, r8, lsr r0
9330: 0000a050 andeq sl, r0, r0, asr r0
00009334 <_ZN7Console5kbaseElll>:
9334: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr}
9338: e2524000 subs r4, r2, #0
933c: e24dd02c sub sp, sp, #44 ; 0x2c
9340: e1a0a000 mov sl, r0
9344: e1a07001 mov r7, r1
9348: e1a06003 mov r6, r3
934c: da000053 ble 94a0 <_ZN7Console5kbaseElll+0x16c>
9350: e59f51b4 ldr r5, [pc, #436] ; 950c <_ZN7Console5kbaseElll+0x1d8>
9354: e3510401 cmp r1, #16777216 ; 0x1000000
9358: 21a0b801 lslcs fp, r1, #16
935c: 21a09821 lsrcs r9, r1, #16
9360: 31a09001 movcc r9, r1
9364: e8b5000f ldm r5!, {r0, r1, r2, r3}
9368: e28dc004 add ip, sp, #4
936c: e8ac000f stmia ip!, {r0, r1, r2, r3}
9370: e8950007 ldm r5, {r0, r1, r2}
9374: e1a0300c mov r3, ip
9378: e8a30003 stmia r3!, {r0, r1}
937c: 23a08001 movcs r8, #1
9380: 33a08000 movcc r8, #0
9384: 21a0b82b lsrcs fp, fp, #16
9388: e3580000 cmp r8, #0
938c: e1c320b0 strh r2, [r3]
9390: 1a00004c bne 94c8 <_ZN7Console5kbaseElll+0x194>
9394: e3560000 cmp r6, #0
9398: 0a000045 beq 94b4 <_ZN7Console5kbaseElll+0x180>
939c: e3560000 cmp r6, #0
93a0: ba000040 blt 94a8 <_ZN7Console5kbaseElll+0x174>
93a4: e2466001 sub r6, r6, #1
93a8: e3a09000 mov r9, #0
93ac: e3560000 cmp r6, #0
93b0: d1a05004 movle r5, r4
93b4: da000010 ble 93fc <_ZN7Console5kbaseElll+0xc8>
93b8: e3a03001 mov r3, #1
93bc: e2462001 sub r2, r6, #1
93c0: e1530006 cmp r3, r6
93c4: e0022003 and r2, r2, r3
93c8: e0050494 mul r5, r4, r4
93cc: aa00000a bge 93fc <_ZN7Console5kbaseElll+0xc8>
93d0: e3520000 cmp r2, #0
93d4: 0a000003 beq 93e8 <_ZN7Console5kbaseElll+0xb4>
93d8: e3a03002 mov r3, #2
93dc: e1530006 cmp r3, r6
93e0: e0050594 mul r5, r4, r5
93e4: aa000004 bge 93fc <_ZN7Console5kbaseElll+0xc8>
93e8: e0050594 mul r5, r4, r5
93ec: e2833002 add r3, r3, #2
93f0: e1530006 cmp r3, r6
93f4: e0050594 mul r5, r4, r5
93f8: bafffffa blt 93e8 <_ZN7Console5kbaseElll+0xb4>
93fc: e1540007 cmp r4, r7
9400: a0000794 mulge r0, r4, r7
9404: b1a00007 movlt r0, r7
9408: e1a01005 mov r1, r5
940c: e28d2024 add r2, sp, #36 ; 0x24
9410: e28d3020 add r3, sp, #32
9414: e58d9024 str r9, [sp, #36] ; 0x24
9418: e58d9020 str r9, [sp, #32]
941c: eb000243 bl 9d30 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_>
9420: e59dc020 ldr ip, [sp, #32]
9424: e08c810c add r8, ip, ip, lsl #2
9428: e1a01005 mov r1, r5
942c: e28d2024 add r2, sp, #36 ; 0x24
9430: e28d3020 add r3, sp, #32
9434: e1a00088 lsl r0, r8, #1
9438: e59d8024 ldr r8, [sp, #36] ; 0x24
943c: eb00023b bl 9d30 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_>
9440: e59d1020 ldr r1, [sp, #32]
9444: e0810101 add r0, r1, r1, lsl #2
9448: e28d2024 add r2, sp, #36 ; 0x24
944c: e28d3020 add r3, sp, #32
9450: e1a01005 mov r1, r5
9454: e1a00080 lsl r0, r0, #1
9458: eb000234 bl 9d30 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_>
945c: e1540008 cmp r4, r8
9460: a20830ff andge r3, r8, #255 ; 0xff
9464: a28d2028 addge r2, sp, #40 ; 0x28
9468: a0823003 addge r3, r2, r3
946c: b1a0000a movlt r0, sl
9470: b3a01065 movlt r1, #101 ; 0x65
9474: b3a02cff movlt r2, #65280 ; 0xff00
9478: a1a0000a movge r0, sl
947c: a5531024 ldrbge r1, [r3, #-36] ; 0xffffffdc
9480: a3a028ff movge r2, #16711680 ; 0xff0000
9484: ebfffeae bl 8f44 <_ZN7Console9printCharEcj>
9488: e3560000 cmp r6, #0
948c: ba000005 blt 94a8 <_ZN7Console5kbaseElll+0x174>
9490: e0050598 mul r5, r8, r5
9494: e2466001 sub r6, r6, #1
9498: e0657007 rsb r7, r5, r7
949c: eaffffc2 b 93ac <_ZN7Console5kbaseElll+0x78>
94a0: e59f1068 ldr r1, [pc, #104] ; 9510 <_ZN7Console5kbaseElll+0x1dc>
94a4: ebfffee3 bl 9038 <_ZN7Console6kprintEPc>
94a8: e28dd02c add sp, sp, #44 ; 0x2c
94ac: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr}
94b0: e12fff1e bx lr
94b4: e1a00007 mov r0, r7
94b8: e1a01004 mov r1, r4
94bc: eb000247 bl 9de0 <_ZN4Math13getDigitCountIlEET_S1_S1_>
94c0: e2406001 sub r6, r0, #1
94c4: eaffffb4 b 939c <_ZN7Console5kbaseElll+0x68>
94c8: e1a01004 mov r1, r4
94cc: e1a00009 mov r0, r9
94d0: eb000242 bl 9de0 <_ZN4Math13getDigitCountIlEET_S1_S1_>
94d4: e1a02004 mov r2, r4
94d8: e2403001 sub r3, r0, #1
94dc: e1a01009 mov r1, r9
94e0: e1a0000a mov r0, sl
94e4: ebffff92 bl 9334 <_ZN7Console5kbaseElll>
94e8: e1a01004 mov r1, r4
94ec: e1a0000b mov r0, fp
94f0: eb00023a bl 9de0 <_ZN4Math13getDigitCountIlEET_S1_S1_>
94f4: e1a0100b mov r1, fp
94f8: e2403001 sub r3, r0, #1
94fc: e1a02004 mov r2, r4
9500: e1a0000a mov r0, sl
9504: ebffff8a bl 9334 <_ZN7Console5kbaseElll>
9508: eaffffe6 b 94a8 <_ZN7Console5kbaseElll+0x174>
950c: 00009e30 andeq r9, r0, r0, lsr lr
9510: 0000a06c andeq sl, r0, ip, rrx
00009514 <_ZN7Console5kbaseEll>:
9514: e3a03000 mov r3, #0
9518: eaffff85 b 9334 <_ZN7Console5kbaseElll>
0000951c <_ZL19kernel_default_font>:
...
972c: 08000000 stmdaeq r0, {} ; <UNPREDICTABLE>
9730: 08080808 stmdaeq r8, {r3, fp}
9734: 08080008 stmdaeq r8, {r3}
9738: 00000000 andeq r0, r0, r0
973c: 14000000 strne r0, [r0], #-0
9740: 00141414 andseq r1, r4, r4, lsl r4
...
974c: 48480000 stmdami r8, {}^ ; <UNPREDICTABLE>
9750: 2424fe68 strtcs pc, [r4], #-3688 ; 0xfffff198
9754: 1212147f andsne r1, r2, #2130706432 ; 0x7f000000
9758: 00000000 andeq r0, r0, r0
975c: 10000000 andne r0, r0, r0
9760: 1c12927c lfmne f1, 1, [r2], {124} ; 0x7c
9764: 7c929070 ldcvc 0, cr9, [r2], {112} ; 0x70
9768: 00001010 andeq r1, r0, r0, lsl r0
976c: 06000000 streq r0, [r0], -r0
9770: 38460909 stmdacc r6, {r0, r3, r8, fp}^
9774: 60909066 addsvs r9, r0, r6, rrx
9778: 00000000 andeq r0, r0, r0
977c: 38000000 stmdacc r0, {} ; <UNPREDICTABLE>
9780: 920c0404 andls r0, ip, #4, 8 ; 0x4000000
9784: bc46a2b2 sfmlt f2, 3, [r6], {178} ; 0xb2
9788: 00000000 andeq r0, r0, r0
978c: 08000000 stmdaeq r0, {} ; <UNPREDICTABLE>
9790: 00080808 andeq r0, r8, r8, lsl #16
...
979c: 10103000 andsne r3, r0, r0
97a0: 08080808 stmdaeq r8, {r3, fp}
97a4: 10100808 andsne r0, r0, r8, lsl #16
97a8: 00000020 andeq r0, r0, r0, lsr #32
97ac: 08080c00 stmdaeq r8, {sl, fp}
97b0: 10101010 andsne r1, r0, r0, lsl r0
97b4: 08081010 stmdaeq r8, {r4, ip}
97b8: 0000000c andeq r0, r0, ip
97bc: 10000000 andne r0, r0, r0
97c0: d6387c92 ; <UNDEFINED> instruction: 0xd6387c92
97c4: 00000010 andeq r0, r0, r0, lsl r0
...
97d0: 7f080808 svcvc 0x00080808
97d4: 00080808 andeq r0, r8, r8, lsl #16
...
97e4: 18180000 ldmdane r8, {} ; <UNPREDICTABLE>
97e8: 00000408 andeq r0, r0, r8, lsl #8
...
97f4: 0000001c andeq r0, r0, ip, lsl r0
...
9804: 18180000 ldmdane r8, {} ; <UNPREDICTABLE>
9808: 00000000 andeq r0, r0, r0
980c: 40000000 andmi r0, r0, r0
9810: 10102020 andsne r2, r0, r0, lsr #32
9814: 04080818 streq r0, [r8], #-2072 ; 0xfffff7e8
9818: 00000204 andeq r0, r0, r4, lsl #4
981c: 38000000 stmdacc r0, {} ; <UNPREDICTABLE>
9820: 92828244 addls r8, r2, #68, 4 ; 0x40000004
9824: 38448282 stmdacc r4, {r1, r7, r9, pc}^
9828: 00000000 andeq r0, r0, r0
982c: 1c000000 stcne 0, cr0, [r0], {-0}
9830: 10101010 andsne r1, r0, r0, lsl r0
9834: 7c101010 ldcvc 0, cr1, [r0], {16}
9838: 00000000 andeq r0, r0, r0
983c: 7c000000 stcvc 0, cr0, [r0], {-0}
9840: 408080c2 addmi r8, r0, r2, asr #1
9844: fe041830 mcr2 8, 0, r1, cr4, cr0, {1}
9848: 00000000 andeq r0, r0, r0
984c: 7c000000 stcvc 0, cr0, [r0], {-0}
9850: 38c08082 stmiacc r0, {r1, r7, pc}^
9854: 7cc280c0 stclvc 0, cr8, [r2], {192} ; 0xc0
9858: 00000000 andeq r0, r0, r0
985c: 60000000 andvs r0, r0, r0
9860: 44485850 strbmi r5, [r8], #-2128 ; 0xfffff7b0
9864: 4040fe42 submi pc, r0, r2, asr #28
9868: 00000000 andeq r0, r0, r0
986c: 7e000000 cdpvc 0, 0, cr0, cr0, cr0, {0}
9870: c03e0202 eorsgt r0, lr, r2, lsl #4
9874: 3cc28080 stclcc 0, cr8, [r2], {128} ; 0x80
9878: 00000000 andeq r0, r0, r0
987c: 78000000 stmdavc r0, {} ; <UNPREDICTABLE>
9880: c67a0284 ldrbtgt r0, [sl], -r4, lsl #5
9884: 78c48282 stmiavc r4, {r1, r7, r9, pc}^
9888: 00000000 andeq r0, r0, r0
988c: fe000000 cdp2 0, 0, cr0, cr0, cr0, {0}
9890: 20204040 eorcs r4, r0, r0, asr #32
9894: 04081810 streq r1, [r8], #-2064 ; 0xfffff7f0
9898: 00000000 andeq r0, r0, r0
989c: 7c000000 stcvc 0, cr0, [r0], {-0}
98a0: 7c828282 sfmvc f0, 1, [r2], {130} ; 0x82
98a4: 7c868282 sfmvc f0, 1, [r6], {130} ; 0x82
98a8: 00000000 andeq r0, r0, r0
98ac: 3c000000 stccc 0, cr0, [r0], {-0}
98b0: c6828246 strgt r8, [r2], r6, asr #4
98b4: 3c4280bc mcrrcc 0, 11, r8, r2, cr12
...
98c0: 00181800 andseq r1, r8, r0, lsl #16
98c4: 18180000 ldmdane r8, {} ; <UNPREDICTABLE>
...
98d0: 00181800 andseq r1, r8, r0, lsl #16
98d4: 18180000 ldmdane r8, {} ; <UNPREDICTABLE>
98d8: 00000408 andeq r0, r0, r8, lsl #8
98dc: 00000000 andeq r0, r0, r0
98e0: 0e708000 cdpeq 0, 7, cr8, cr0, cr0, {0}
98e4: 0080700e addeq r7, r0, lr
...
98f0: 00fe0000 rscseq r0, lr, r0
98f4: 0000fe00 andeq pc, r0, r0, lsl #28
...
9900: e01c0200 ands r0, ip, r0, lsl #4
9904: 00021ce0 andeq r1, r2, r0, ror #25
9908: 00000000 andeq r0, r0, r0
990c: 1c000000 stcne 0, cr0, [r0], {-0}
9910: 08102022 ldmdaeq r0, {r1, r5, sp}
9914: 08080008 stmdaeq r8, {r3}
9918: 00000000 andeq r0, r0, r0
991c: 78000000 stmdavc r0, {} ; <UNPREDICTABLE>
9920: 92e284cc rscls r8, r2, #204, 8 ; 0xcc000000
9924: 04e29292 strbteq r9, [r2], #658 ; 0x292
9928: 0000780c andeq r7, r0, ip, lsl #16
992c: 10000000 andne r0, r0, r0
9930: 44282828 strtmi r2, [r8], #-2088 ; 0xfffff7d8
9934: 82c67c44 sbchi r7, r6, #68, 24 ; 0x4400
9938: 00000000 andeq r0, r0, r0
993c: 7e000000 cdpvc 0, 0, cr0, cr0, cr0, {0}
9940: 7e828282 cdpvc 2, 8, cr8, cr2, cr2, {4}
9944: 7e828282 cdpvc 2, 8, cr8, cr2, cr2, {4}
9948: 00000000 andeq r0, r0, r0
994c: 78000000 stmdavc r0, {} ; <UNPREDICTABLE>
9950: 02020284 andeq r0, r2, #132, 4 ; 0x40000008
9954: 78840202 stmvc r4, {r1, r9}
9958: 00000000 andeq r0, r0, r0
995c: 3e000000 cdpcc 0, 0, cr0, cr0, cr0, {0}
9960: 82828242 addhi r8, r2, #536870916 ; 0x20000004
9964: 3e428282 cdpcc 2, 4, cr8, cr2, cr2, {4}
9968: 00000000 andeq r0, r0, r0
996c: fe000000 cdp2 0, 0, cr0, cr0, cr0, {0}
9970: fe020202 cdp2 2, 0, cr0, cr2, cr2, {0}
9974: fe020202 cdp2 2, 0, cr0, cr2, cr2, {0}
9978: 00000000 andeq r0, r0, r0
997c: fe000000 cdp2 0, 0, cr0, cr0, cr0, {0}
9980: fe020202 cdp2 2, 0, cr0, cr2, cr2, {0}
9984: 02020202 andeq r0, r2, #536870912 ; 0x20000000
9988: 00000000 andeq r0, r0, r0
998c: 78000000 stmdavc r0, {} ; <UNPREDICTABLE>
9990: c2020284 andgt r0, r2, #132, 4 ; 0x40000008
9994: 78848282 stmvc r4, {r1, r7, r9, pc}
9998: 00000000 andeq r0, r0, r0
999c: 82000000 andhi r0, r0, #0
99a0: fe828282 cdp2 2, 8, cr8, cr2, cr2, {4}
99a4: 82828282 addhi r8, r2, #536870920 ; 0x20000008
99a8: 00000000 andeq r0, r0, r0
99ac: 3e000000 cdpcc 0, 0, cr0, cr0, cr0, {0}
99b0: 08080808 stmdaeq r8, {r3, fp}
99b4: 3e080808 cdpcc 8, 0, cr0, cr8, cr8, {0}
99b8: 00000000 andeq r0, r0, r0
99bc: 38000000 stmdacc r0, {} ; <UNPREDICTABLE>
99c0: 20202020 eorcs r2, r0, r0, lsr #32
99c4: 1c222020 stcne 0, cr2, [r2], #-128 ; 0xffffff80
99c8: 00000000 andeq r0, r0, r0
99cc: 42000000 andmi r0, r0, #0
99d0: 0e0a1222 cdpeq 2, 0, cr1, cr10, cr2, {1}
99d4: 42222212 eormi r2, r2, #536870913 ; 0x20000001
99d8: 00000000 andeq r0, r0, r0
99dc: 02000000 andeq r0, r0, #0
99e0: 02020202 andeq r0, r2, #536870912 ; 0x20000000
99e4: fe020202 cdp2 2, 0, cr0, cr2, cr2, {0}
99e8: 00000000 andeq r0, r0, r0
99ec: c6000000 strgt r0, [r0], -r0
99f0: aaaaaac6 bge feab4510 <_ZZN7Console5kbaseElllE3C.0+0xfeaaa6e0>
99f4: 82828292 addhi r8, r2, #536870921 ; 0x20000009
99f8: 00000000 andeq r0, r0, r0
99fc: 86000000 strhi r0, [r0], -r0
9a00: 928a8a86 addls r8, sl, #548864 ; 0x86000
9a04: c2c2a2a2 sbcgt sl, r2, #536870922 ; 0x2000000a
9a08: 00000000 andeq r0, r0, r0
9a0c: 38000000 stmdacc r0, {} ; <UNPREDICTABLE>
9a10: 82828244 addhi r8, r2, #68, 4 ; 0x40000004
9a14: 38448282 stmdacc r4, {r1, r7, r9, pc}^
9a18: 00000000 andeq r0, r0, r0
9a1c: 7e000000 cdpvc 0, 0, cr0, cr0, cr0, {0}
9a20: c28282c2 addgt r8, r2, #536870924 ; 0x2000000c
9a24: 0202027e andeq r0, r2, #-536870905 ; 0xe0000007
9a28: 00000000 andeq r0, r0, r0
9a2c: 38000000 stmdacc r0, {} ; <UNPREDICTABLE>
9a30: 82828244 addhi r8, r2, #68, 4 ; 0x40000004
9a34: 78448282 stmdavc r4, {r1, r7, r9, pc}^
9a38: 00004060 andeq r4, r0, r0, rrx
9a3c: 7e000000 cdpvc 0, 0, cr0, cr0, cr0, {0}
9a40: 7e8282c2 cdpvc 2, 8, cr8, cr2, cr2, {6}
9a44: 02828242 addeq r8, r2, #536870916 ; 0x20000004
9a48: 00000000 andeq r0, r0, r0
9a4c: 7c000000 stcvc 0, cr0, [r0], {-0}
9a50: 7c060286 sfmvc f0, 4, [r6], {134} ; 0x86
9a54: 7dc280c0 stclvc 0, cr8, [r2, #768] ; 0x300
9a58: 00000000 andeq r0, r0, r0
9a5c: 7f000000 svcvc 0x00000000
9a60: 08080808 stmdaeq r8, {r3, fp}
9a64: 08080808 stmdaeq r8, {r3, fp}
9a68: 00000000 andeq r0, r0, r0
9a6c: 82000000 andhi r0, r0, #0
9a70: 82828282 addhi r8, r2, #536870920 ; 0x20000008
9a74: 7c828282 sfmvc f0, 1, [r2], {130} ; 0x82
9a78: 00000000 andeq r0, r0, r0
9a7c: 82000000 andhi r0, r0, #0
9a80: 444444c6 strbmi r4, [r4], #-1222 ; 0xfffffb3a
9a84: 10282828 eorne r2, r8, r8, lsr #16
9a88: 00000000 andeq r0, r0, r0
9a8c: 81000000 tsthi r0, r0
9a90: 5a5a8181 bpl 16aa09c <_ZZN7Console5kbaseElllE3C.0+0x16a026c>
9a94: 6666665a ; <UNDEFINED> instruction: 0x6666665a
9a98: 00000000 andeq r0, r0, r0
9a9c: c6000000 strgt r0, [r0], -r0
9aa0: 10382844 eorsne r2, r8, r4, asr #16
9aa4: 82446c28 subhi r6, r4, #40, 24 ; 0x2800
9aa8: 00000000 andeq r0, r0, r0
9aac: 41000000 tstmi r0, r0
9ab0: 08141422 ldmdaeq r4, {r1, r5, sl, ip}
9ab4: 08080808 stmdaeq r8, {r3, fp}
9ab8: 00000000 andeq r0, r0, r0
9abc: fe000000 cdp2 0, 0, cr0, cr0, cr0, {0}
9ac0: 102060c0 eorne r6, r0, r0, asr #1
9ac4: fe060c08 cdp2 12, 0, cr0, cr6, cr8, {0}
9ac8: 00000000 andeq r0, r0, r0
9acc: 08083800 stmdaeq r8, {fp, ip, sp}
9ad0: 08080808 stmdaeq r8, {r3, fp}
9ad4: 08080808 stmdaeq r8, {r3, fp}
9ad8: 00000038 andeq r0, r0, r8, lsr r0
9adc: 02000000 andeq r0, r0, #0
9ae0: 08080404 stmdaeq r8, {r2, sl}
9ae4: 20101018 andscs r1, r0, r8, lsl r0
9ae8: 00004020 andeq r4, r0, r0, lsr #32
9aec: 10101c00 andsne r1, r0, r0, lsl #24
9af0: 10101010 andsne r1, r0, r0, lsl r0
9af4: 10101010 andsne r1, r0, r0, lsl r0
9af8: 0000001c andeq r0, r0, ip, lsl r0
9afc: 08000000 stmdaeq r0, {} ; <UNPREDICTABLE>
9b00: 00632214 rsbeq r2, r3, r4, lsl r2
...
9b18: 007f0000 rsbseq r0, pc, r0
9b1c: 10080000 andne r0, r8, r0
...
9b30: 40443800 submi r3, r4, r0, lsl #16
9b34: 5c62427c sfmpl f4, 2, [r2], #-496 ; 0xfffffe10
9b38: 00000000 andeq r0, r0, r0
9b3c: 02020200 andeq r0, r2, #0, 4
9b40: 42663e02 rsbmi r3, r6, #2, 28
9b44: 3e664242 cdpcc 2, 6, cr4, cr6, cr2, {2}
...
9b50: 02443800 subeq r3, r4, #0, 16
9b54: 38440202 stmdacc r4, {r1, r9}^
9b58: 00000000 andeq r0, r0, r0
9b5c: 40404000 submi r4, r0, r0
9b60: 42667c40 rsbmi r7, r6, #64, 24 ; 0x4000
9b64: 7c664242 sfmvc f4, 2, [r6], #-264 ; 0xfffffef8
...
9b70: 42663c00 rsbmi r3, r6, #0, 24
9b74: 3c46027e sfmcc f0, 2, [r6], {126} ; 0x7e
9b78: 00000000 andeq r0, r0, r0
9b7c: 08083000 stmdaeq r8, {ip, sp}
9b80: 08083e08 stmdaeq r8, {r3, r9, sl, fp, ip, sp}
9b84: 08080808 stmdaeq r8, {r3, fp}
...
9b90: 42667c00 rsbmi r7, r6, #0, 24
9b94: 5c664242 sfmpl f4, 2, [r6], #-264 ; 0xfffffef8
9b98: 00384440 eorseq r4, r8, r0, asr #8
9b9c: 02020200 andeq r0, r2, #0, 4
9ba0: 42463a02 submi r3, r6, #8192 ; 0x2000
9ba4: 42424242 submi r4, r2, #536870916 ; 0x20000004
9ba8: 00000000 andeq r0, r0, r0
9bac: 00000800 andeq r0, r0, r0, lsl #16
9bb0: 08080e00 stmdaeq r8, {r9, sl, fp}
9bb4: 3e080808 cdpcc 8, 0, cr0, cr8, cr8, {0}
9bb8: 00000000 andeq r0, r0, r0
9bbc: 00001000 andeq r1, r0, r0
9bc0: 10101c00 andsne r1, r0, r0, lsl #24
9bc4: 10101010 andsne r1, r0, r0, lsl r0
9bc8: 000e1010 andeq r1, lr, r0, lsl r0
9bcc: 02020200 andeq r0, r2, #0, 4
9bd0: 0a122202 beq 4923e0 <_ZZN7Console5kbaseElllE3C.0+0x4885b0>
9bd4: 4222120e eormi r1, r2, #-536870912 ; 0xe0000000
9bd8: 00000000 andeq r0, r0, r0
9bdc: 08080e00 stmdaeq r8, {r9, sl, fp}
9be0: 08080808 stmdaeq r8, {r3, fp}
9be4: 70080808 andvc r0, r8, r8, lsl #16
...
9bf0: 9292fe00 addsls pc, r2, #0, 28
9bf4: 92929292 addsls r9, r2, #536870921 ; 0x20000009
...
9c00: 42463a00 submi r3, r6, #0, 20
9c04: 42424242 submi r4, r2, #536870916 ; 0x20000004
...
9c10: 42663c00 rsbmi r3, r6, #0, 24
9c14: 3c664242 sfmcc f4, 2, [r6], #-264 ; 0xfffffef8
...
9c20: 42663e00 rsbmi r3, r6, #0, 28
9c24: 3e664242 cdpcc 2, 6, cr4, cr6, cr2, {2}
9c28: 00020202 andeq r0, r2, r2, lsl #4
9c2c: 00000000 andeq r0, r0, r0
9c30: 42667c00 rsbmi r7, r6, #0, 24
9c34: 5c664242 sfmpl f4, 2, [r6], #-264 ; 0xfffffef8
9c38: 00404040 subeq r4, r0, r0, asr #32
9c3c: 00000000 andeq r0, r0, r0
9c40: 044c3c00 strbeq r3, [ip], #-3072 ; 0xfffff400
9c44: 04040404 streq r0, [r4], #-1028 ; 0xfffffbfc
...
9c50: 02423c00 subeq r3, r2, #0, 24
9c54: 3c42403c mcrrcc 0, 3, r4, r2, cr12
9c58: 00000000 andeq r0, r0, r0
9c5c: 08000000 stmdaeq r0, {} ; <UNPREDICTABLE>
9c60: 08087e08 stmdaeq r8, {r3, r9, sl, fp, ip, sp, lr}
9c64: 70080808 andvc r0, r8, r8, lsl #16
...
9c70: 42424200 submi r4, r2, #0, 4
9c74: 5c624242 sfmpl f4, 2, [r2], #-264 ; 0xfffffef8
...
9c80: 24664200 strbtcs r4, [r6], #-512 ; 0xfffffe00
9c84: 18183c24 ldmdane r8, {r2, r5, sl, fp, ip, sp}
...
9c90: 5a818100 bpl fe06a098 <_ZZN7Console5kbaseElllE3C.0+0xfe060268>
9c94: 24245a5a strtcs r5, [r4], #-2650 ; 0xfffff5a6
...
9ca0: 18246600 stmdane r4!, {r9, sl, sp, lr}
9ca4: 66241818 ; <UNDEFINED> instruction: 0x66241818
...
9cb0: 24444200 strbcs r4, [r4], #-512 ; 0xfffffe00
9cb4: 10182824 andsne r2, r8, r4, lsr #16
9cb8: 000c0810 andeq r0, ip, r0, lsl r8
9cbc: 00000000 andeq r0, r0, r0
9cc0: 20407e00 subcs r7, r0, r0, lsl #28
9cc4: 7e020418 cfmvdlrvc mvd2, r0
9cc8: 00000000 andeq r0, r0, r0
9ccc: 08083800 stmdaeq r8, {fp, ip, sp}
9cd0: 08060808 stmdaeq r6, {r3, fp}
9cd4: 08080808 stmdaeq r8, {r3, fp}
9cd8: 00000030 andeq r0, r0, r0, lsr r0
9cdc: 08080800 stmdaeq r8, {fp}
9ce0: 08080808 stmdaeq r8, {r3, fp}
9ce4: 08080808 stmdaeq r8, {r3, fp}
9ce8: 00000808 andeq r0, r0, r8, lsl #16
9cec: 08080e00 stmdaeq r8, {r9, sl, fp}
9cf0: 08300808 ldmdaeq r0!, {r3, fp}
9cf4: 08080808 stmdaeq r8, {r3, fp}
9cf8: 00000006 andeq r0, r0, r6
9cfc: 00000000 andeq r0, r0, r0
9d00: 9c000000 stcls 0, cr0, [r0], {-0}
9d04: 00000062 andeq r0, r0, r2, rrx
9d08: 00000000 andeq r0, r0, r0
9d0c: ffffffff ; <UNDEFINED> instruction: 0xffffffff
9d10: ffffffff ; <UNDEFINED> instruction: 0xffffffff
9d14: ffffffff ; <UNDEFINED> instruction: 0xffffffff
9d18: ffffffff ; <UNDEFINED> instruction: 0xffffffff
9d1c: ffffffff ; <UNDEFINED> instruction: 0xffffffff
9d20: ffffffff ; <UNDEFINED> instruction: 0xffffffff
00009d24 <rootPageTable>:
9d24: 00000000 andeq r0, r0, r0
00009d28 <use_irq_console>:
9d28: 00000000 andeq r0, r0, r0
00009d2c <irq_console>:
9d2c: 00000000 andeq r0, r0, r0
00009d30 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_>:
9d30: e1b0cfa0 lsrs ip, r0, #31
9d34: e92d01f0 push {r4, r5, r6, r7, r8}
9d38: e1a08fa1 lsr r8, r1, #31
9d3c: 12600000 rsbne r0, r0, #0
9d40: e3580000 cmp r8, #0
9d44: 12611000 rsbne r1, r1, #0
9d48: e3510000 cmp r1, #0
9d4c: 0a00001e beq 9dcc <_ZN4Math6divideIlEET_S1_S1_PS1_S2_+0x9c>
9d50: e1500001 cmp r0, r1
9d54: ba000017 blt 9db8 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_+0x88>
9d58: e3a04000 mov r4, #0
9d5c: e5824000 str r4, [r2]
9d60: e5834000 str r4, [r3]
9d64: e5925000 ldr r5, [r2]
9d68: e2617000 rsb r7, r1, #0
9d6c: e0614000 rsb r4, r1, r0
9d70: e0844007 add r4, r4, r7
9d74: e0846001 add r6, r4, r1
9d78: e1510006 cmp r1, r6
9d7c: e2855001 add r5, r5, #1
9d80: dafffffa ble 9d70 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_+0x40>
9d84: e0010195 mul r1, r5, r1
9d88: e0610000 rsb r0, r1, r0
9d8c: e5825000 str r5, [r2]
9d90: e5830000 str r0, [r3]
9d94: e5920000 ldr r0, [r2]
9d98: e35c0000 cmp ip, #0
9d9c: 12600000 rsbne r0, r0, #0
9da0: 15820000 strne r0, [r2]
9da4: e3580000 cmp r8, #0
9da8: 12600000 rsbne r0, r0, #0
9dac: 15820000 strne r0, [r2]
9db0: e8bd01f0 pop {r4, r5, r6, r7, r8}
9db4: e12fff1e bx lr
9db8: e3a0c000 mov ip, #0
9dbc: e582c000 str ip, [r2]
9dc0: e5830000 str r0, [r3]
9dc4: e5920000 ldr r0, [r2]
9dc8: eafffff8 b 9db0 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_+0x80>
9dcc: e3e01000 mvn r1, #0
9dd0: e5821000 str r1, [r2]
9dd4: e5831000 str r1, [r3]
9dd8: e5920000 ldr r0, [r2]
9ddc: eafffff3 b 9db0 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_+0x80>
00009de0 <_ZN4Math13getDigitCountIlEET_S1_S1_>:
9de0: e92d4030 push {r4, r5, lr}
9de4: e3500000 cmp r0, #0
9de8: e24dd00c sub sp, sp, #12
9dec: e3a04000 mov r4, #0
9df0: e1a05001 mov r5, r1
9df4: e58d4004 str r4, [sp, #4]
9df8: e58d4000 str r4, [sp]
9dfc: da000007 ble 9e20 <_ZN4Math13getDigitCountIlEET_S1_S1_+0x40>
9e00: e1a01005 mov r1, r5
9e04: e28d2004 add r2, sp, #4
9e08: e1a0300d mov r3, sp
9e0c: ebffffc7 bl 9d30 <_ZN4Math6divideIlEET_S1_S1_PS1_S2_>
9e10: e59d0004 ldr r0, [sp, #4]
9e14: e3500000 cmp r0, #0
9e18: e2844001 add r4, r4, #1
9e1c: cafffff7 bgt 9e00 <_ZN4Math13getDigitCountIlEET_S1_S1_+0x20>
9e20: e1a00004 mov r0, r4
9e24: e28dd00c add sp, sp, #12
9e28: e8bd4030 pop {r4, r5, lr}
9e2c: e12fff1e bx lr
00009e30 <_ZZN7Console5kbaseElllE3C.0>:
9e30: 33323130 teqcc r2, #48, 2
9e34: 37363534 ; <UNDEFINED> instruction: 0x37363534
9e38: 42413938 submi r3, r1, #56, 18 ; 0xe0000
9e3c: 46454443 strbmi r4, [r5], -r3, asr #8
9e40: 4a494847 bmi 125bf64 <_ZZN7Console5kbaseElllE3C.0+0x1252134>
9e44: 4e4d4c4b cdpmi 12, 4, cr4, cr13, cr11, {2}
9e48: 0000504f andeq r5, r0, pc, asr #32
9e4c: 6f727245 svcvs 0x00727245
9e50: 43202e72 teqmi r0, #1824 ; 0x720
9e54: 75637269 strbvc r7, [r3, #-617]! ; 0xfffffd97
9e58: 2072616c rsbscs r6, r2, ip, ror #2
9e5c: 706f6f6c rsbvc r6, pc, ip, ror #30
9e60: 65686320 strbvs r6, [r8, #-800]! ; 0xfffffce0
9e64: 6e696b63 vnmulvs.f64 d22, d9, d19
9e68: 6f662067 svcvs 0x00662067
9e6c: 74732072 ldrbtvc r2, [r3], #-114 ; 0xffffff8e
9e70: 73757461 cmnvc r5, #1627389952 ; 0x61000000
9e74: 0000002e andeq r0, r0, lr, lsr #32
9e78: 6f727245 svcvs 0x00727245
9e7c: 54202172 strtpl r2, [r0], #-370 ; 0xfffffe8e
9e80: 6d206568 cfstr32vs mvfx6, [r0, #-416]! ; 0xfffffe60
9e84: 626c6961 rsbvs r6, ip, #1589248 ; 0x184000
9e88: 6420786f strtvs r7, [r0], #-2159 ; 0xfffff791
9e8c: 276e6469 strbcs r6, [lr, -r9, ror #8]!
9e90: 65722074 ldrbvs r2, [r2, #-116]! ; 0xffffff8c
9e94: 6e727574 mrcvs 5, 3, r7, cr2, cr4, {3}
9e98: 73206120 teqvc r0, #32, 2
9e9c: 61746975 cmnvs r4, r5, ror r9
9ea0: 20656c62 rsbcs r6, r5, r2, ror #24
9ea4: 756c6176 strbvc r6, [ip, #-374]! ; 0xfffffe8a
9ea8: 6e692065 cdpvs 0, 6, cr2, cr9, cr5, {3}
9eac: 74206120 strtvc r6, [r0], #-288 ; 0xfffffee0
9eb0: 6c656d69 stclvs 13, cr6, [r5], #-420 ; 0xfffffe5c
9eb4: 616d2079 smcvs 53769 ; 0xd209
9eb8: 72656e6e rsbvc r6, r5, #1760 ; 0x6e0
9ebc: 0000002e andeq r0, r0, lr, lsr #32
9ec0: 6f727245 svcvs 0x00727245
9ec4: 54202172 strtpl r2, [r0], #-370 ; 0xfffffe8e
9ec8: 66206568 strtvs r6, [r0], -r8, ror #10
9ecc: 656d6172 strbvs r6, [sp, #-370]! ; 0xfffffe8e
9ed0: 66667562 strbtvs r7, [r6], -r2, ror #10
9ed4: 72207265 eorvc r7, r0, #1342177286 ; 0x50000006
9ed8: 72757465 rsbsvc r7, r5, #1694498816 ; 0x65000000
9edc: 2064656e rsbcs r6, r4, lr, ror #10
9ee0: 69207369 stmdbvs r0!, {r0, r3, r5, r6, r8, r9, ip, sp, lr}
9ee4: 6c61766e stclvs 6, cr7, [r1], #-440 ; 0xfffffe48
9ee8: 202e6469 eorcs r6, lr, r9, ror #8
9eec: 726f6241 rsbvc r6, pc, #268435460 ; 0x10000004
9ef0: 676e6974 ; <UNDEFINED> instruction: 0x676e6974
9ef4: 61726620 cmnvs r2, r0, lsr #12
9ef8: 7562656d strbvc r6, [r2, #-1389]! ; 0xfffffa93
9efc: 72656666 rsbvc r6, r5, #106954752 ; 0x6600000
9f00: 71636120 cmnvc r3, r0, lsr #2
9f04: 69736975 ldmdbvs r3!, {r0, r2, r4, r5, r6, r8, fp, sp, lr}^
9f08: 6e6f6974 mcrvs 9, 3, r6, cr15, cr4, {3}
9f0c: 00000000 andeq r0, r0, r0
9f10: 6f727245 svcvs 0x00727245
9f14: 54202172 strtpl r2, [r0], #-370 ; 0xfffffe8e
9f18: 70206568 eorvc r6, r0, r8, ror #10
9f1c: 68637469 stmdavs r3!, {r0, r3, r5, r6, sl, ip, sp, lr}^
9f20: 74657220 strbtvc r7, [r5], #-544 ; 0xfffffde0
9f24: 656e7275 strbvs r7, [lr, #-629]! ; 0xfffffd8b
9f28: 73692064 cmnvc r9, #100 ; 0x64
9f2c: 766e6920 strbtvc r6, [lr], -r0, lsr #18
9f30: 64696c61 strbtvs r6, [r9], #-3169 ; 0xfffff39f
9f34: 6241202e subvs r2, r1, #46 ; 0x2e
9f38: 6974726f ldmdbvs r4!, {r0, r1, r2, r3, r5, r6, r9, ip, sp, lr}^
9f3c: 6620676e strtvs r6, [r0], -lr, ror #14
9f40: 656d6172 strbvs r6, [sp, #-370]! ; 0xfffffe8e
9f44: 66667562 strbtvs r7, [r6], -r2, ror #10
9f48: 61207265 teqvs r0, r5, ror #4
9f4c: 69757163 ldmdbvs r5!, {r0, r1, r5, r6, r8, ip, sp, lr}^
9f50: 69746973 ldmdbvs r4!, {r0, r1, r4, r5, r6, r8, fp, sp, lr}^
9f54: 002e6e6f eoreq r6, lr, pc, ror #28
9f58: 4e4f445b mcrmi 4, 2, r4, cr15, cr11, {2}
9f5c: 00095d45 andeq r5, r9, r5, asr #26
9f60: 45544e49 ldrbmi r4, [r4, #-3657] ; 0xfffff1b7
9f64: 50555252 subspl r5, r5, r2, asr r2
9f68: 00000054 andeq r0, r0, r4, asr r0
9f6c: 636c6557 cmnvs ip, #364904448 ; 0x15c00000
9f70: 20656d6f rsbcs r6, r5, pc, ror #26
9f74: 4d206f74 stcmi 15, cr6, [r0, #-464]! ; 0xfffffe30
9f78: 66646e69 strbtvs r6, [r4], -r9, ror #28
9f7c: 6579616c ldrbvs r6, [r9, #-364]! ; 0xfffffe94
9f80: 61202c72 teqvs r0, r2, ror ip
9f84: 73756320 cmnvc r5, #32, 6 ; 0x80000000
9f88: 206d6f74 rsbcs r6, sp, r4, ror pc
9f8c: 70736172 rsbsvc r6, r3, r2, ror r1
9f90: 72726562 rsbsvc r6, r2, #411041792 ; 0x18800000
9f94: 69702079 ldmdbvs r0!, {r0, r3, r4, r5, r6, sp}^
9f98: 72656b20 rsbvc r6, r5, #32, 22 ; 0x8000
9f9c: 206c656e rsbcs r6, ip, lr, ror #10
9fa0: 74697277 strbtvc r7, [r9], #-631 ; 0xfffffd89
9fa4: 206e6574 rsbcs r6, lr, r4, ror r5
9fa8: 43206e69 teqmi r0, #1680 ; 0x690
9fac: 000a2b2b andeq r2, sl, fp, lsr #22
9fb0: 6c697542 cfstr64vs mvdx7, [r9], #-264 ; 0xfffffef8
9fb4: 00203a64 eoreq r3, r0, r4, ror #20
9fb8: 2e302e30 mrccs 14, 1, r2, cr0, cr0, {1}
9fbc: 00323236 eorseq r3, r2, r6, lsr r2
9fc0: 000a0a0a andeq r0, sl, sl, lsl #20
9fc4: 74696157 strbtvc r6, [r9], #-343 ; 0xfffffea9
9fc8: 3a676e69 bcc 19e5974 <_ZZN7Console5kbaseElllE3C.0+0x19dbb44>
9fcc: 00000020 andeq r0, r0, r0, lsr #32
9fd0: 54535b0a ldrbpl r5, [r3], #-2826 ; 0xfffff4f6
9fd4: 49545241 ldmdbmi r4, {r0, r6, r9, ip, lr}^
9fd8: 0a5d474e beq 175bd18 <_ZZN7Console5kbaseElllE3C.0+0x1751ee8>
9fdc: 0000000a andeq r0, r0, sl
9fe0: 74696e49 strbtvc r6, [r9], #-3657 ; 0xfffff1b7
9fe4: 696c6169 stmdbvs ip!, {r0, r3, r5, r6, r8, sp, lr}^
9fe8: 2064657a rsbcs r6, r4, sl, ror r5
9fec: 65676170 strbvs r6, [r7, #-368]! ; 0xfffffe90
9ff0: 62617420 rsbvs r7, r1, #32, 8 ; 0x20000000
9ff4: 0000656c andeq r6, r0, ip, ror #10
9ff8: 65746e49 ldrbvs r6, [r4, #-3657]! ; 0xfffff1b7
9ffc: 70757272 rsbsvc r7, r5, r2, ror r2
a000: 65762074 ldrbvs r2, [r6, #-116]! ; 0xffffff8c
a004: 726f7463 rsbvc r7, pc, #1660944384 ; 0x63000000
a008: 4e452073 mcrmi 0, 2, r2, cr5, cr3, {3}
a00c: 454c4241 strbmi r4, [ip, #-577] ; 0xfffffdbf
a010: 00000044 andeq r0, r0, r4, asr #32
a014: 756f6241 strbvc r6, [pc, #-577]! ; 9ddb <_ZN4Math6divideIlEET_S1_S1_PS1_S2_+0xab>
a018: 6f742074 svcvs 0x00742074
a01c: 72687420 rsbvc r7, r8, #32, 8 ; 0x20000000
a020: 6120776f teqvs r0, pc, ror #14
a024: 5753206e ldrbpl r2, [r3, -lr, rrx]
a028: 78652049 stmdavc r5!, {r0, r3, r6, sp}^
a02c: 74706563 ldrbtvc r6, [r0], #-1379 ; 0xfffffa9d
a030: 2e6e6f69 cdpcs 15, 6, cr6, cr14, cr9, {3}
a034: 000a2e2e andeq r2, sl, lr, lsr #28
a038: 20495753 subcs r5, r9, r3, asr r7
a03c: 65637845 strbvs r7, [r3, #-2117]! ; 0xfffff7bb
a040: 6f697470 svcvs 0x00697470
a044: 6854206e ldmdavs r4, {r1, r2, r3, r5, r6, sp}^
a048: 6e776f72 mrcvs 15, 3, r6, cr7, cr2, {3}
a04c: 00000000 andeq r0, r0, r0
a050: 654b0a0a strbvs r0, [fp, #-2570] ; 0xfffff5f6
a054: 6c656e72 stclvs 14, cr6, [r5], #-456 ; 0xfffffe38
a058: 75687320 strbvc r7, [r8, #-800]! ; 0xfffffce0
a05c: 6e697474 mcrvs 4, 3, r7, cr9, cr4, {3}
a060: 6f642067 svcvs 0x00642067
a064: 2e2e6e77 mcrcs 14, 1, r6, cr14, cr7, {3}
a068: 0000002e andeq r0, r0, lr, lsr #32
a06c: 6f727265 svcvs 0x00727265
a070: 55203a72 strpl r3, [r0, #-2674]! ; 0xfffff58e
a074: 7075736e rsbsvc r7, r5, lr, ror #6
a078: 74726f70 ldrbtvc r6, [r2], #-3952 ; 0xfffff090
a07c: 62206465 eorvs r6, r0, #1694498816 ; 0x65000000
a080: 20657361 rsbcs r7, r5, r1, ror #6
a084: 6d206e69 stcvs 14, cr6, [r0, #-420]! ; 0xfffffe5c
a088: 65687461 strbvs r7, [r8, #-1121]! ; 0xfffffb9f
a08c: 6974616d ldmdbvs r4!, {r0, r2, r3, r5, r6, r8, sp, lr}^
a090: 206c6163 rsbcs r6, ip, r3, ror #2
a094: 7265706f rsbvc r7, r5, #111 ; 0x6f
a098: 6f697461 svcvs 0x00697461
a09c: 000a2e6e andeq r2, sl, lr, ror #28
a0a0: 3a434347 bcc 10dadc4 <_ZZN7Console5kbaseElllE3C.0+0x10d0f94>
a0a4: 6f532820 svcvs 0x00532820
a0a8: 65637275 strbvs r7, [r3, #-629]! ; 0xfffffd8b
a0ac: 47207972 ; <UNDEFINED> instruction: 0x47207972
a0b0: 4c202b2b stcmi 11, cr2, [r0], #-172 ; 0xffffff54
a0b4: 20657469 rsbcs r7, r5, r9, ror #8
a0b8: 30313032 eorscc r3, r1, r2, lsr r0
a0bc: 2d39302e ldccs 0, cr3, [r9, #-184]! ; 0xffffff48
a0c0: 20293135 eorcs r3, r9, r5, lsr r1
a0c4: 2e352e34 mrccs 14, 1, r2, cr5, cr4, {1}
a0c8: 33410031 movtcc r0, #4145 ; 0x1031
a0cc: 61000000 tstvs r0, r0
a0d0: 69626165 stmdbvs r2!, {r0, r2, r5, r6, r8, sp, lr}^
a0d4: 00290100 eoreq r0, r9, r0, lsl #2
a0d8: 41050000 tstmi r5, r0
a0dc: 54374d52 ldrtpl r4, [r7], #-3410 ; 0xfffff2ae
a0e0: 2d494d44 stclcs 13, cr4, [r9, #-272] ; 0xfffffef0
a0e4: 02060053 andeq r0, r6, #83 ; 0x53
a0e8: 01090108 tsteq r9, r8, lsl #2
a0ec: 01140412 tsteq r4, r2, lsl r4
a0f0: 03170115 tsteq r7, #1073741829 ; 0x40000005
a0f4: 01190118 tsteq r9, r8, lsl r1
a0f8: 021e011a andseq r0, lr, #-2147483642 ; 0x80000006
a0fc: Address 0x0000a0fc is out of bounds.
| SharpCoder/rpi-kernel | debug/kern.elf.asm | Assembly | mit | 85,725 |
USE32
extern current_intr_handler
global parasite_interrupt_handler:function
extern profiler_stack_sampler
parasite_interrupt_handler:
cli
pusha
push DWORD [esp + 32]
call profiler_stack_sampler
pop eax
call DWORD [current_intr_handler]
popa
sti
iret
| hioa-cs/IncludeOS | src/arch/i686/profile_intr.asm | Assembly | apache-2.0 | 271 |
;
; Copyright (c) 2015 The WebM project authors. All Rights Reserved.
;
; Use of this source code is governed by a BSD-style license
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
; in the file PATENTS. All contributing project authors may
; be found in the AUTHORS file in the root of the source tree.
;
; This file is a duplicate of mfqe_sse2.asm in VP8.
; TODO(jackychen): Find a way to fix the duplicate.
%include "vpx_ports/x86_abi_support.asm"
;void vp9_filter_by_weight16x16_sse2
;(
; unsigned char *src,
; int src_stride,
; unsigned char *dst,
; int dst_stride,
; int src_weight
;)
global sym(vp9_filter_by_weight16x16_sse2) PRIVATE
sym(vp9_filter_by_weight16x16_sse2):
push rbp
mov rbp, rsp
SHADOW_ARGS_TO_STACK 5
SAVE_XMM 6
GET_GOT rbx
push rsi
push rdi
; end prolog
movd xmm0, arg(4) ; src_weight
pshuflw xmm0, xmm0, 0x0 ; replicate to all low words
punpcklqdq xmm0, xmm0 ; replicate to all hi words
movdqa xmm1, [GLOBAL(tMFQE)]
psubw xmm1, xmm0 ; dst_weight
mov rax, arg(0) ; src
mov rsi, arg(1) ; src_stride
mov rdx, arg(2) ; dst
mov rdi, arg(3) ; dst_stride
mov rcx, 16 ; loop count
pxor xmm6, xmm6
.combine
movdqa xmm2, [rax]
movdqa xmm4, [rdx]
add rax, rsi
; src * src_weight
movdqa xmm3, xmm2
punpcklbw xmm2, xmm6
punpckhbw xmm3, xmm6
pmullw xmm2, xmm0
pmullw xmm3, xmm0
; dst * dst_weight
movdqa xmm5, xmm4
punpcklbw xmm4, xmm6
punpckhbw xmm5, xmm6
pmullw xmm4, xmm1
pmullw xmm5, xmm1
; sum, round and shift
paddw xmm2, xmm4
paddw xmm3, xmm5
paddw xmm2, [GLOBAL(tMFQE_round)]
paddw xmm3, [GLOBAL(tMFQE_round)]
psrlw xmm2, 4
psrlw xmm3, 4
packuswb xmm2, xmm3
movdqa [rdx], xmm2
add rdx, rdi
dec rcx
jnz .combine
; begin epilog
pop rdi
pop rsi
RESTORE_GOT
RESTORE_XMM
UNSHADOW_ARGS
pop rbp
ret
;void vp9_filter_by_weight8x8_sse2
;(
; unsigned char *src,
; int src_stride,
; unsigned char *dst,
; int dst_stride,
; int src_weight
;)
global sym(vp9_filter_by_weight8x8_sse2) PRIVATE
sym(vp9_filter_by_weight8x8_sse2):
push rbp
mov rbp, rsp
SHADOW_ARGS_TO_STACK 5
GET_GOT rbx
push rsi
push rdi
; end prolog
movd xmm0, arg(4) ; src_weight
pshuflw xmm0, xmm0, 0x0 ; replicate to all low words
punpcklqdq xmm0, xmm0 ; replicate to all hi words
movdqa xmm1, [GLOBAL(tMFQE)]
psubw xmm1, xmm0 ; dst_weight
mov rax, arg(0) ; src
mov rsi, arg(1) ; src_stride
mov rdx, arg(2) ; dst
mov rdi, arg(3) ; dst_stride
mov rcx, 8 ; loop count
pxor xmm4, xmm4
.combine
movq xmm2, [rax]
movq xmm3, [rdx]
add rax, rsi
; src * src_weight
punpcklbw xmm2, xmm4
pmullw xmm2, xmm0
; dst * dst_weight
punpcklbw xmm3, xmm4
pmullw xmm3, xmm1
; sum, round and shift
paddw xmm2, xmm3
paddw xmm2, [GLOBAL(tMFQE_round)]
psrlw xmm2, 4
packuswb xmm2, xmm4
movq [rdx], xmm2
add rdx, rdi
dec rcx
jnz .combine
; begin epilog
pop rdi
pop rsi
RESTORE_GOT
UNSHADOW_ARGS
pop rbp
ret
;void vp9_variance_and_sad_16x16_sse2 | arg
;(
; unsigned char *src1, 0
; int stride1, 1
; unsigned char *src2, 2
; int stride2, 3
; unsigned int *variance, 4
; unsigned int *sad, 5
;)
global sym(vp9_variance_and_sad_16x16_sse2) PRIVATE
sym(vp9_variance_and_sad_16x16_sse2):
push rbp
mov rbp, rsp
SHADOW_ARGS_TO_STACK 6
GET_GOT rbx
push rsi
push rdi
; end prolog
mov rax, arg(0) ; src1
mov rcx, arg(1) ; stride1
mov rdx, arg(2) ; src2
mov rdi, arg(3) ; stride2
mov rsi, 16 ; block height
; Prep accumulator registers
pxor xmm3, xmm3 ; SAD
pxor xmm4, xmm4 ; sum of src2
pxor xmm5, xmm5 ; sum of src2^2
; Because we're working with the actual output frames
; we can't depend on any kind of data alignment.
.accumulate
movdqa xmm0, [rax] ; src1
movdqa xmm1, [rdx] ; src2
add rax, rcx ; src1 + stride1
add rdx, rdi ; src2 + stride2
; SAD(src1, src2)
psadbw xmm0, xmm1
paddusw xmm3, xmm0
; SUM(src2)
pxor xmm2, xmm2
psadbw xmm2, xmm1 ; sum src2 by misusing SAD against 0
paddusw xmm4, xmm2
; pmaddubsw would be ideal if it took two unsigned values. instead,
; it expects a signed and an unsigned value. so instead we zero extend
; and operate on words.
pxor xmm2, xmm2
movdqa xmm0, xmm1
punpcklbw xmm0, xmm2
punpckhbw xmm1, xmm2
pmaddwd xmm0, xmm0
pmaddwd xmm1, xmm1
paddd xmm5, xmm0
paddd xmm5, xmm1
sub rsi, 1
jnz .accumulate
; phaddd only operates on adjacent double words.
; Finalize SAD and store
movdqa xmm0, xmm3
psrldq xmm0, 8
paddusw xmm0, xmm3
paddd xmm0, [GLOBAL(t128)]
psrld xmm0, 8
mov rax, arg(5)
movd [rax], xmm0
; Accumulate sum of src2
movdqa xmm0, xmm4
psrldq xmm0, 8
paddusw xmm0, xmm4
; Square src2. Ignore high value
pmuludq xmm0, xmm0
psrld xmm0, 8
; phaddw could be used to sum adjacent values but we want
; all the values summed. promote to doubles, accumulate,
; shift and sum
pxor xmm2, xmm2
movdqa xmm1, xmm5
punpckldq xmm1, xmm2
punpckhdq xmm5, xmm2
paddd xmm1, xmm5
movdqa xmm2, xmm1
psrldq xmm1, 8
paddd xmm1, xmm2
psubd xmm1, xmm0
; (variance + 128) >> 8
paddd xmm1, [GLOBAL(t128)]
psrld xmm1, 8
mov rax, arg(4)
movd [rax], xmm1
; begin epilog
pop rdi
pop rsi
RESTORE_GOT
UNSHADOW_ARGS
pop rbp
ret
SECTION_RODATA
align 16
t128:
%ifndef __NASM_VER__
ddq 128
%elif CONFIG_BIG_ENDIAN
dq 0, 128
%else
dq 128, 0
%endif
align 16
tMFQE: ; 1 << MFQE_PRECISION
times 8 dw 0x10
align 16
tMFQE_round: ; 1 << (MFQE_PRECISION - 1)
times 8 dw 0x08
| blloyd75/theoraplayer | vpx/vp9/common/x86/vp9_mfqe_sse2.asm | Assembly | bsd-3-clause | 7,525 |
processor 6502
ORG $1001
DC.W $100B,0
DC.B $9E,"4109",0,0,0 ; SYS4107
JMP main
org $1800,$00
include "fw_interface.asm"
include "fw_bootstrap.asm"
main SUBROUTINE
lda #$00
jsr fw_init
sei
sta $ff3f
lda #$00
sta $ff0a
ldy #$10
lda #$00
.0 sta $0000,y
iny
bne .0
jsr fw_run
cli
ldy #$00
.loop
iny
sty $ff19
bne .loop
jmp launch
demopart_begin = .
incbin "demopart.exo"
demopart_end = .
demopart_len = [demopart_end - demopart_begin]
org $fcb6
launch SUBROUTINE
lda #<demopart_begin
sta .src
lda #>demopart_begin
sta .src+1
lda #$f0
sta .dst
lda #$17
sta .dst+1
.loop
.src = .+1
lda $1234
.dst = .+1
sta $5678
inc .src
bne .srcok
inc .src+1
.srcok
inc .dst
bne .dstok
inc .dst+1
.dstok
lda .src
cmp #<demopart_end
bne .loop
lda .src+1
cmp #>demopart_end
bne .loop
sei
ldx .dst
ldy .dst+1
jsr fw_decrunch
cli
jmp $17fd
ECHO demopart_begin, " " , demopart_end, " ", demopart_len
| kosmonautdnb/TheLandsOfZador | Framework/trackmo/framework/driver_packed.asm | Assembly | mit | 983 |
; 1 2 3 4 5 6 7
;234567890123456789012345678901234567890123456789012345678901234567890
;=====================================================================
;
; *** TEST ***
;
;---------------------------------------------------------------------
;
; AUTHOR: Nik Mohamad Aizuddin bin Nik Azmi
; DATE CREATED: 20-MARCH-2015
;
; TEST PURPOSE: Make sure XConnect have no errors.
;
; LANGUAGE: x86 Assembly Language
; SYNTAX: Intel
; ASSEMBLER: NASM
; ARCHITECTURE: i386
; KERNEL: Linux 32-bit
; FORMAT: elf32
;
; EXTERNAL FILES: create_socket.asm
; XConnect.asm
;
;=====================================================================
extern create_socket
extern XConnect
global _start
section .bss
socket_descriptor: resd 1
section .text
_start:
;EAX = create_socket( PF_LOCAL, SOCK_STREAM, IPPROTO_IP )
mov eax, 1 ;protocol_family = PF_LOCAL
mov ebx, 1 ;socket_type = SOCK_STREAM
mov ecx, 0 ;protocol_used = IPPROTO_IP
call create_socket
mov [socket_descriptor], eax
;XConnect( socket_descriptor )
mov eax, [socket_descriptor]
call XConnect
exit:
;EXIT(0)
mov eax, 0x01 ;systemcall exit
xor ebx, ebx ;return 0
int 0x80
| nikAizuddin/lib80386 | src/xorg/X11/XConnect/test/_start.asm | Assembly | mit | 1,404 |
;; graciously taken from http://en.wikibooks.org/wiki/X86_Assembly/Bootloaders
org 7C00h
jmp short Start ;Jump over the data (the 'short' keyword makes the jmp instruction smaller)
Msg: db "What is real life? "
EndMsg:
Start: mov bx, 000Fh ;Page 0, colour attribute 15 (white) for the int 10 calls below
mov cx, 1 ;We will want to write 1 character
xor dx, dx ;Start at top left corner
mov ds, dx ;Ensure ds = 0 (to let us load the message)
cld ;Ensure direction flag is cleared (for LODSB)
Print: mov si, Msg ;Loads the address of the first byte of the message, 7C02h in this case
;; PC BIOS Interrupt 10 Subfunction 2 - Set cursor position
;; AH = 2
Char: mov ah, 2 ;BH = page, DH = row, DL = column
int 10h
lodsb ;Load a byte of the message into AL.
;; Remember that DS is 0 and SI holds the
;; offset of one of the bytes of the message.
;; PC BIOS Interrupt 10 Subfunction 9 - Write character and colour
;; AH = 9
mov ah, 9 ;BH = page, AL = character, BL = attribute, CX = character count
int 10h
inc dl ;Advance cursor
cmp dl, 80 ;Wrap around edge of screen if necessary
jne Skip
xor dl, dl
inc dh
cmp dh, 25 ;Wrap around bottom of screen if necessary
jne Skip
xor dh, dh
Skip: cmp si, EndMsg ;If we're not at end of message,
jne Char ;continue loading characters
jmp Print ;otherwise restart from the beginning of the message
times 0200h - 2 - ($ - $$) db 0 ;Zerofill up to 510 bytes
dw 0AA55h ;Boot Sector signature
;; OPTIONAL:
;; To zerofill up to the size of a standard 1.44MB, 3.5" floppy disk
;; times 1474560 - ($ - $$) db 0
| supershabam/ros | bootloaders/helloworld/floppy.asm | Assembly | mit | 1,750 |
_stressfs: file format elf32-i386
Disassembly of section .text:
00000000 <main>:
#include "fs.h"
#include "fcntl.h"
int
main(int argc, char *argv[])
{
0: 8d 4c 24 04 lea 0x4(%esp),%ecx
4: 83 e4 f0 and $0xfffffff0,%esp
7: ff 71 fc pushl -0x4(%ecx)
a: 55 push %ebp
b: 89 e5 mov %esp,%ebp
d: 51 push %ecx
e: 81 ec 24 02 00 00 sub $0x224,%esp
int fd, i;
char path[] = "stressfs0";
14: c7 45 e6 73 74 72 65 movl $0x65727473,-0x1a(%ebp)
1b: c7 45 ea 73 73 66 73 movl $0x73667373,-0x16(%ebp)
22: 66 c7 45 ee 30 00 movw $0x30,-0x12(%ebp)
char data[512];
printf(1, "stressfs starting\n");
28: 83 ec 08 sub $0x8,%esp
2b: 68 d6 08 00 00 push $0x8d6
30: 6a 01 push $0x1
32: e8 e9 04 00 00 call 520 <printf>
37: 83 c4 10 add $0x10,%esp
memset(data, 'a', sizeof(data));
3a: 83 ec 04 sub $0x4,%esp
3d: 68 00 02 00 00 push $0x200
42: 6a 61 push $0x61
44: 8d 85 e6 fd ff ff lea -0x21a(%ebp),%eax
4a: 50 push %eax
4b: e8 be 01 00 00 call 20e <memset>
50: 83 c4 10 add $0x10,%esp
for(i = 0; i < 4; i++)
53: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
5a: eb 0d jmp 69 <main+0x69>
if(fork() > 0)
5c: e8 40 03 00 00 call 3a1 <fork>
61: 85 c0 test %eax,%eax
63: 7f 0c jg 71 <main+0x71>
for(i = 0; i < 4; i++)
65: 83 45 f4 01 addl $0x1,-0xc(%ebp)
69: 83 7d f4 03 cmpl $0x3,-0xc(%ebp)
6d: 7e ed jle 5c <main+0x5c>
6f: eb 01 jmp 72 <main+0x72>
break;
71: 90 nop
printf(1, "write %d\n", i);
72: 83 ec 04 sub $0x4,%esp
75: ff 75 f4 pushl -0xc(%ebp)
78: 68 e9 08 00 00 push $0x8e9
7d: 6a 01 push $0x1
7f: e8 9c 04 00 00 call 520 <printf>
84: 83 c4 10 add $0x10,%esp
path[8] += i;
87: 0f b6 45 ee movzbl -0x12(%ebp),%eax
8b: 89 c2 mov %eax,%edx
8d: 8b 45 f4 mov -0xc(%ebp),%eax
90: 01 d0 add %edx,%eax
92: 88 45 ee mov %al,-0x12(%ebp)
fd = open(path, O_CREATE | O_RDWR);
95: 83 ec 08 sub $0x8,%esp
98: 68 02 02 00 00 push $0x202
9d: 8d 45 e6 lea -0x1a(%ebp),%eax
a0: 50 push %eax
a1: e8 43 03 00 00 call 3e9 <open>
a6: 83 c4 10 add $0x10,%esp
a9: 89 45 f0 mov %eax,-0x10(%ebp)
for(i = 0; i < 20; i++)
ac: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
b3: eb 1e jmp d3 <main+0xd3>
// printf(fd, "%d\n", i);
write(fd, data, sizeof(data));
b5: 83 ec 04 sub $0x4,%esp
b8: 68 00 02 00 00 push $0x200
bd: 8d 85 e6 fd ff ff lea -0x21a(%ebp),%eax
c3: 50 push %eax
c4: ff 75 f0 pushl -0x10(%ebp)
c7: e8 fd 02 00 00 call 3c9 <write>
cc: 83 c4 10 add $0x10,%esp
for(i = 0; i < 20; i++)
cf: 83 45 f4 01 addl $0x1,-0xc(%ebp)
d3: 83 7d f4 13 cmpl $0x13,-0xc(%ebp)
d7: 7e dc jle b5 <main+0xb5>
close(fd);
d9: 83 ec 0c sub $0xc,%esp
dc: ff 75 f0 pushl -0x10(%ebp)
df: e8 ed 02 00 00 call 3d1 <close>
e4: 83 c4 10 add $0x10,%esp
printf(1, "read\n");
e7: 83 ec 08 sub $0x8,%esp
ea: 68 f3 08 00 00 push $0x8f3
ef: 6a 01 push $0x1
f1: e8 2a 04 00 00 call 520 <printf>
f6: 83 c4 10 add $0x10,%esp
fd = open(path, O_RDONLY);
f9: 83 ec 08 sub $0x8,%esp
fc: 6a 00 push $0x0
fe: 8d 45 e6 lea -0x1a(%ebp),%eax
101: 50 push %eax
102: e8 e2 02 00 00 call 3e9 <open>
107: 83 c4 10 add $0x10,%esp
10a: 89 45 f0 mov %eax,-0x10(%ebp)
for (i = 0; i < 20; i++)
10d: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
114: eb 1e jmp 134 <main+0x134>
read(fd, data, sizeof(data));
116: 83 ec 04 sub $0x4,%esp
119: 68 00 02 00 00 push $0x200
11e: 8d 85 e6 fd ff ff lea -0x21a(%ebp),%eax
124: 50 push %eax
125: ff 75 f0 pushl -0x10(%ebp)
128: e8 94 02 00 00 call 3c1 <read>
12d: 83 c4 10 add $0x10,%esp
for (i = 0; i < 20; i++)
130: 83 45 f4 01 addl $0x1,-0xc(%ebp)
134: 83 7d f4 13 cmpl $0x13,-0xc(%ebp)
138: 7e dc jle 116 <main+0x116>
close(fd);
13a: 83 ec 0c sub $0xc,%esp
13d: ff 75 f0 pushl -0x10(%ebp)
140: e8 8c 02 00 00 call 3d1 <close>
145: 83 c4 10 add $0x10,%esp
wait();
148: e8 64 02 00 00 call 3b1 <wait>
exit();
14d: e8 57 02 00 00 call 3a9 <exit>
00000152 <stosb>:
"cc");
}
static inline void
stosb(void *addr, int data, int cnt)
{
152: 55 push %ebp
153: 89 e5 mov %esp,%ebp
155: 57 push %edi
156: 53 push %ebx
asm volatile("cld; rep stosb" :
157: 8b 4d 08 mov 0x8(%ebp),%ecx
15a: 8b 55 10 mov 0x10(%ebp),%edx
15d: 8b 45 0c mov 0xc(%ebp),%eax
160: 89 cb mov %ecx,%ebx
162: 89 df mov %ebx,%edi
164: 89 d1 mov %edx,%ecx
166: fc cld
167: f3 aa rep stos %al,%es:(%edi)
169: 89 ca mov %ecx,%edx
16b: 89 fb mov %edi,%ebx
16d: 89 5d 08 mov %ebx,0x8(%ebp)
170: 89 55 10 mov %edx,0x10(%ebp)
"=D" (addr), "=c" (cnt) :
"0" (addr), "1" (cnt), "a" (data) :
"memory", "cc");
}
173: 90 nop
174: 5b pop %ebx
175: 5f pop %edi
176: 5d pop %ebp
177: c3 ret
00000178 <strcpy>:
#include "user.h"
#include "x86.h"
char*
strcpy(char *s, char *t)
{
178: 55 push %ebp
179: 89 e5 mov %esp,%ebp
17b: 83 ec 10 sub $0x10,%esp
char *os;
os = s;
17e: 8b 45 08 mov 0x8(%ebp),%eax
181: 89 45 fc mov %eax,-0x4(%ebp)
while((*s++ = *t++) != 0)
184: 90 nop
185: 8b 45 08 mov 0x8(%ebp),%eax
188: 8d 50 01 lea 0x1(%eax),%edx
18b: 89 55 08 mov %edx,0x8(%ebp)
18e: 8b 55 0c mov 0xc(%ebp),%edx
191: 8d 4a 01 lea 0x1(%edx),%ecx
194: 89 4d 0c mov %ecx,0xc(%ebp)
197: 0f b6 12 movzbl (%edx),%edx
19a: 88 10 mov %dl,(%eax)
19c: 0f b6 00 movzbl (%eax),%eax
19f: 84 c0 test %al,%al
1a1: 75 e2 jne 185 <strcpy+0xd>
;
return os;
1a3: 8b 45 fc mov -0x4(%ebp),%eax
}
1a6: c9 leave
1a7: c3 ret
000001a8 <strcmp>:
int
strcmp(const char *p, const char *q)
{
1a8: 55 push %ebp
1a9: 89 e5 mov %esp,%ebp
while(*p && *p == *q)
1ab: eb 08 jmp 1b5 <strcmp+0xd>
p++, q++;
1ad: 83 45 08 01 addl $0x1,0x8(%ebp)
1b1: 83 45 0c 01 addl $0x1,0xc(%ebp)
while(*p && *p == *q)
1b5: 8b 45 08 mov 0x8(%ebp),%eax
1b8: 0f b6 00 movzbl (%eax),%eax
1bb: 84 c0 test %al,%al
1bd: 74 10 je 1cf <strcmp+0x27>
1bf: 8b 45 08 mov 0x8(%ebp),%eax
1c2: 0f b6 10 movzbl (%eax),%edx
1c5: 8b 45 0c mov 0xc(%ebp),%eax
1c8: 0f b6 00 movzbl (%eax),%eax
1cb: 38 c2 cmp %al,%dl
1cd: 74 de je 1ad <strcmp+0x5>
return (uchar)*p - (uchar)*q;
1cf: 8b 45 08 mov 0x8(%ebp),%eax
1d2: 0f b6 00 movzbl (%eax),%eax
1d5: 0f b6 d0 movzbl %al,%edx
1d8: 8b 45 0c mov 0xc(%ebp),%eax
1db: 0f b6 00 movzbl (%eax),%eax
1de: 0f b6 c0 movzbl %al,%eax
1e1: 29 c2 sub %eax,%edx
1e3: 89 d0 mov %edx,%eax
}
1e5: 5d pop %ebp
1e6: c3 ret
000001e7 <strlen>:
uint
strlen(char *s)
{
1e7: 55 push %ebp
1e8: 89 e5 mov %esp,%ebp
1ea: 83 ec 10 sub $0x10,%esp
int n;
for(n = 0; s[n]; n++)
1ed: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
1f4: eb 04 jmp 1fa <strlen+0x13>
1f6: 83 45 fc 01 addl $0x1,-0x4(%ebp)
1fa: 8b 55 fc mov -0x4(%ebp),%edx
1fd: 8b 45 08 mov 0x8(%ebp),%eax
200: 01 d0 add %edx,%eax
202: 0f b6 00 movzbl (%eax),%eax
205: 84 c0 test %al,%al
207: 75 ed jne 1f6 <strlen+0xf>
;
return n;
209: 8b 45 fc mov -0x4(%ebp),%eax
}
20c: c9 leave
20d: c3 ret
0000020e <memset>:
void*
memset(void *dst, int c, uint n)
{
20e: 55 push %ebp
20f: 89 e5 mov %esp,%ebp
stosb(dst, c, n);
211: 8b 45 10 mov 0x10(%ebp),%eax
214: 50 push %eax
215: ff 75 0c pushl 0xc(%ebp)
218: ff 75 08 pushl 0x8(%ebp)
21b: e8 32 ff ff ff call 152 <stosb>
220: 83 c4 0c add $0xc,%esp
return dst;
223: 8b 45 08 mov 0x8(%ebp),%eax
}
226: c9 leave
227: c3 ret
00000228 <strchr>:
char*
strchr(const char *s, char c)
{
228: 55 push %ebp
229: 89 e5 mov %esp,%ebp
22b: 83 ec 04 sub $0x4,%esp
22e: 8b 45 0c mov 0xc(%ebp),%eax
231: 88 45 fc mov %al,-0x4(%ebp)
for(; *s; s++)
234: eb 14 jmp 24a <strchr+0x22>
if(*s == c)
236: 8b 45 08 mov 0x8(%ebp),%eax
239: 0f b6 00 movzbl (%eax),%eax
23c: 3a 45 fc cmp -0x4(%ebp),%al
23f: 75 05 jne 246 <strchr+0x1e>
return (char*)s;
241: 8b 45 08 mov 0x8(%ebp),%eax
244: eb 13 jmp 259 <strchr+0x31>
for(; *s; s++)
246: 83 45 08 01 addl $0x1,0x8(%ebp)
24a: 8b 45 08 mov 0x8(%ebp),%eax
24d: 0f b6 00 movzbl (%eax),%eax
250: 84 c0 test %al,%al
252: 75 e2 jne 236 <strchr+0xe>
return 0;
254: b8 00 00 00 00 mov $0x0,%eax
}
259: c9 leave
25a: c3 ret
0000025b <gets>:
char*
gets(char *buf, int max)
{
25b: 55 push %ebp
25c: 89 e5 mov %esp,%ebp
25e: 83 ec 18 sub $0x18,%esp
int i, cc;
char c;
for(i=0; i+1 < max; ){
261: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
268: eb 42 jmp 2ac <gets+0x51>
cc = read(0, &c, 1);
26a: 83 ec 04 sub $0x4,%esp
26d: 6a 01 push $0x1
26f: 8d 45 ef lea -0x11(%ebp),%eax
272: 50 push %eax
273: 6a 00 push $0x0
275: e8 47 01 00 00 call 3c1 <read>
27a: 83 c4 10 add $0x10,%esp
27d: 89 45 f0 mov %eax,-0x10(%ebp)
if(cc < 1)
280: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
284: 7e 33 jle 2b9 <gets+0x5e>
break;
buf[i++] = c;
286: 8b 45 f4 mov -0xc(%ebp),%eax
289: 8d 50 01 lea 0x1(%eax),%edx
28c: 89 55 f4 mov %edx,-0xc(%ebp)
28f: 89 c2 mov %eax,%edx
291: 8b 45 08 mov 0x8(%ebp),%eax
294: 01 c2 add %eax,%edx
296: 0f b6 45 ef movzbl -0x11(%ebp),%eax
29a: 88 02 mov %al,(%edx)
if(c == '\n' || c == '\r')
29c: 0f b6 45 ef movzbl -0x11(%ebp),%eax
2a0: 3c 0a cmp $0xa,%al
2a2: 74 16 je 2ba <gets+0x5f>
2a4: 0f b6 45 ef movzbl -0x11(%ebp),%eax
2a8: 3c 0d cmp $0xd,%al
2aa: 74 0e je 2ba <gets+0x5f>
for(i=0; i+1 < max; ){
2ac: 8b 45 f4 mov -0xc(%ebp),%eax
2af: 83 c0 01 add $0x1,%eax
2b2: 3b 45 0c cmp 0xc(%ebp),%eax
2b5: 7c b3 jl 26a <gets+0xf>
2b7: eb 01 jmp 2ba <gets+0x5f>
break;
2b9: 90 nop
break;
}
buf[i] = '\0';
2ba: 8b 55 f4 mov -0xc(%ebp),%edx
2bd: 8b 45 08 mov 0x8(%ebp),%eax
2c0: 01 d0 add %edx,%eax
2c2: c6 00 00 movb $0x0,(%eax)
return buf;
2c5: 8b 45 08 mov 0x8(%ebp),%eax
}
2c8: c9 leave
2c9: c3 ret
000002ca <stat>:
int
stat(char *n, struct stat *st)
{
2ca: 55 push %ebp
2cb: 89 e5 mov %esp,%ebp
2cd: 83 ec 18 sub $0x18,%esp
int fd;
int r;
fd = open(n, O_RDONLY);
2d0: 83 ec 08 sub $0x8,%esp
2d3: 6a 00 push $0x0
2d5: ff 75 08 pushl 0x8(%ebp)
2d8: e8 0c 01 00 00 call 3e9 <open>
2dd: 83 c4 10 add $0x10,%esp
2e0: 89 45 f4 mov %eax,-0xc(%ebp)
if(fd < 0)
2e3: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
2e7: 79 07 jns 2f0 <stat+0x26>
return -1;
2e9: b8 ff ff ff ff mov $0xffffffff,%eax
2ee: eb 25 jmp 315 <stat+0x4b>
r = fstat(fd, st);
2f0: 83 ec 08 sub $0x8,%esp
2f3: ff 75 0c pushl 0xc(%ebp)
2f6: ff 75 f4 pushl -0xc(%ebp)
2f9: e8 03 01 00 00 call 401 <fstat>
2fe: 83 c4 10 add $0x10,%esp
301: 89 45 f0 mov %eax,-0x10(%ebp)
close(fd);
304: 83 ec 0c sub $0xc,%esp
307: ff 75 f4 pushl -0xc(%ebp)
30a: e8 c2 00 00 00 call 3d1 <close>
30f: 83 c4 10 add $0x10,%esp
return r;
312: 8b 45 f0 mov -0x10(%ebp),%eax
}
315: c9 leave
316: c3 ret
00000317 <atoi>:
int
atoi(const char *s)
{
317: 55 push %ebp
318: 89 e5 mov %esp,%ebp
31a: 83 ec 10 sub $0x10,%esp
int n;
n = 0;
31d: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%ebp)
while('0' <= *s && *s <= '9')
324: eb 25 jmp 34b <atoi+0x34>
n = n*10 + *s++ - '0';
326: 8b 55 fc mov -0x4(%ebp),%edx
329: 89 d0 mov %edx,%eax
32b: c1 e0 02 shl $0x2,%eax
32e: 01 d0 add %edx,%eax
330: 01 c0 add %eax,%eax
332: 89 c1 mov %eax,%ecx
334: 8b 45 08 mov 0x8(%ebp),%eax
337: 8d 50 01 lea 0x1(%eax),%edx
33a: 89 55 08 mov %edx,0x8(%ebp)
33d: 0f b6 00 movzbl (%eax),%eax
340: 0f be c0 movsbl %al,%eax
343: 01 c8 add %ecx,%eax
345: 83 e8 30 sub $0x30,%eax
348: 89 45 fc mov %eax,-0x4(%ebp)
while('0' <= *s && *s <= '9')
34b: 8b 45 08 mov 0x8(%ebp),%eax
34e: 0f b6 00 movzbl (%eax),%eax
351: 3c 2f cmp $0x2f,%al
353: 7e 0a jle 35f <atoi+0x48>
355: 8b 45 08 mov 0x8(%ebp),%eax
358: 0f b6 00 movzbl (%eax),%eax
35b: 3c 39 cmp $0x39,%al
35d: 7e c7 jle 326 <atoi+0xf>
return n;
35f: 8b 45 fc mov -0x4(%ebp),%eax
}
362: c9 leave
363: c3 ret
00000364 <memmove>:
void*
memmove(void *vdst, void *vsrc, int n)
{
364: 55 push %ebp
365: 89 e5 mov %esp,%ebp
367: 83 ec 10 sub $0x10,%esp
char *dst, *src;
dst = vdst;
36a: 8b 45 08 mov 0x8(%ebp),%eax
36d: 89 45 fc mov %eax,-0x4(%ebp)
src = vsrc;
370: 8b 45 0c mov 0xc(%ebp),%eax
373: 89 45 f8 mov %eax,-0x8(%ebp)
while(n-- > 0)
376: eb 17 jmp 38f <memmove+0x2b>
*dst++ = *src++;
378: 8b 45 fc mov -0x4(%ebp),%eax
37b: 8d 50 01 lea 0x1(%eax),%edx
37e: 89 55 fc mov %edx,-0x4(%ebp)
381: 8b 55 f8 mov -0x8(%ebp),%edx
384: 8d 4a 01 lea 0x1(%edx),%ecx
387: 89 4d f8 mov %ecx,-0x8(%ebp)
38a: 0f b6 12 movzbl (%edx),%edx
38d: 88 10 mov %dl,(%eax)
while(n-- > 0)
38f: 8b 45 10 mov 0x10(%ebp),%eax
392: 8d 50 ff lea -0x1(%eax),%edx
395: 89 55 10 mov %edx,0x10(%ebp)
398: 85 c0 test %eax,%eax
39a: 7f dc jg 378 <memmove+0x14>
return vdst;
39c: 8b 45 08 mov 0x8(%ebp),%eax
}
39f: c9 leave
3a0: c3 ret
000003a1 <fork>:
name: \
movl $SYS_ ## name, %eax; \
int $T_SYSCALL; \
ret
SYSCALL(fork)
3a1: b8 01 00 00 00 mov $0x1,%eax
3a6: cd 40 int $0x40
3a8: c3 ret
000003a9 <exit>:
SYSCALL(exit)
3a9: b8 02 00 00 00 mov $0x2,%eax
3ae: cd 40 int $0x40
3b0: c3 ret
000003b1 <wait>:
SYSCALL(wait)
3b1: b8 03 00 00 00 mov $0x3,%eax
3b6: cd 40 int $0x40
3b8: c3 ret
000003b9 <pipe>:
SYSCALL(pipe)
3b9: b8 04 00 00 00 mov $0x4,%eax
3be: cd 40 int $0x40
3c0: c3 ret
000003c1 <read>:
SYSCALL(read)
3c1: b8 05 00 00 00 mov $0x5,%eax
3c6: cd 40 int $0x40
3c8: c3 ret
000003c9 <write>:
SYSCALL(write)
3c9: b8 10 00 00 00 mov $0x10,%eax
3ce: cd 40 int $0x40
3d0: c3 ret
000003d1 <close>:
SYSCALL(close)
3d1: b8 15 00 00 00 mov $0x15,%eax
3d6: cd 40 int $0x40
3d8: c3 ret
000003d9 <kill>:
SYSCALL(kill)
3d9: b8 06 00 00 00 mov $0x6,%eax
3de: cd 40 int $0x40
3e0: c3 ret
000003e1 <exec>:
SYSCALL(exec)
3e1: b8 07 00 00 00 mov $0x7,%eax
3e6: cd 40 int $0x40
3e8: c3 ret
000003e9 <open>:
SYSCALL(open)
3e9: b8 0f 00 00 00 mov $0xf,%eax
3ee: cd 40 int $0x40
3f0: c3 ret
000003f1 <mknod>:
SYSCALL(mknod)
3f1: b8 11 00 00 00 mov $0x11,%eax
3f6: cd 40 int $0x40
3f8: c3 ret
000003f9 <unlink>:
SYSCALL(unlink)
3f9: b8 12 00 00 00 mov $0x12,%eax
3fe: cd 40 int $0x40
400: c3 ret
00000401 <fstat>:
SYSCALL(fstat)
401: b8 08 00 00 00 mov $0x8,%eax
406: cd 40 int $0x40
408: c3 ret
00000409 <link>:
SYSCALL(link)
409: b8 13 00 00 00 mov $0x13,%eax
40e: cd 40 int $0x40
410: c3 ret
00000411 <mkdir>:
SYSCALL(mkdir)
411: b8 14 00 00 00 mov $0x14,%eax
416: cd 40 int $0x40
418: c3 ret
00000419 <chdir>:
SYSCALL(chdir)
419: b8 09 00 00 00 mov $0x9,%eax
41e: cd 40 int $0x40
420: c3 ret
00000421 <dup>:
SYSCALL(dup)
421: b8 0a 00 00 00 mov $0xa,%eax
426: cd 40 int $0x40
428: c3 ret
00000429 <getpid>:
SYSCALL(getpid)
429: b8 0b 00 00 00 mov $0xb,%eax
42e: cd 40 int $0x40
430: c3 ret
00000431 <sbrk>:
SYSCALL(sbrk)
431: b8 0c 00 00 00 mov $0xc,%eax
436: cd 40 int $0x40
438: c3 ret
00000439 <sleep>:
SYSCALL(sleep)
439: b8 0d 00 00 00 mov $0xd,%eax
43e: cd 40 int $0x40
440: c3 ret
00000441 <uptime>:
SYSCALL(uptime)
441: b8 0e 00 00 00 mov $0xe,%eax
446: cd 40 int $0x40
448: c3 ret
00000449 <putc>:
#include "stat.h"
#include "user.h"
static void
putc(int fd, char c)
{
449: 55 push %ebp
44a: 89 e5 mov %esp,%ebp
44c: 83 ec 18 sub $0x18,%esp
44f: 8b 45 0c mov 0xc(%ebp),%eax
452: 88 45 f4 mov %al,-0xc(%ebp)
write(fd, &c, 1);
455: 83 ec 04 sub $0x4,%esp
458: 6a 01 push $0x1
45a: 8d 45 f4 lea -0xc(%ebp),%eax
45d: 50 push %eax
45e: ff 75 08 pushl 0x8(%ebp)
461: e8 63 ff ff ff call 3c9 <write>
466: 83 c4 10 add $0x10,%esp
}
469: 90 nop
46a: c9 leave
46b: c3 ret
0000046c <printint>:
static void
printint(int fd, int xx, int base, int sgn)
{
46c: 55 push %ebp
46d: 89 e5 mov %esp,%ebp
46f: 53 push %ebx
470: 83 ec 24 sub $0x24,%esp
static char digits[] = "0123456789ABCDEF";
char buf[16];
int i, neg;
uint x;
neg = 0;
473: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
if(sgn && xx < 0){
47a: 83 7d 14 00 cmpl $0x0,0x14(%ebp)
47e: 74 17 je 497 <printint+0x2b>
480: 83 7d 0c 00 cmpl $0x0,0xc(%ebp)
484: 79 11 jns 497 <printint+0x2b>
neg = 1;
486: c7 45 f0 01 00 00 00 movl $0x1,-0x10(%ebp)
x = -xx;
48d: 8b 45 0c mov 0xc(%ebp),%eax
490: f7 d8 neg %eax
492: 89 45 ec mov %eax,-0x14(%ebp)
495: eb 06 jmp 49d <printint+0x31>
} else {
x = xx;
497: 8b 45 0c mov 0xc(%ebp),%eax
49a: 89 45 ec mov %eax,-0x14(%ebp)
}
i = 0;
49d: c7 45 f4 00 00 00 00 movl $0x0,-0xc(%ebp)
do{
buf[i++] = digits[x % base];
4a4: 8b 4d f4 mov -0xc(%ebp),%ecx
4a7: 8d 41 01 lea 0x1(%ecx),%eax
4aa: 89 45 f4 mov %eax,-0xc(%ebp)
4ad: 8b 5d 10 mov 0x10(%ebp),%ebx
4b0: 8b 45 ec mov -0x14(%ebp),%eax
4b3: ba 00 00 00 00 mov $0x0,%edx
4b8: f7 f3 div %ebx
4ba: 89 d0 mov %edx,%eax
4bc: 0f b6 80 48 0b 00 00 movzbl 0xb48(%eax),%eax
4c3: 88 44 0d dc mov %al,-0x24(%ebp,%ecx,1)
}while((x /= base) != 0);
4c7: 8b 5d 10 mov 0x10(%ebp),%ebx
4ca: 8b 45 ec mov -0x14(%ebp),%eax
4cd: ba 00 00 00 00 mov $0x0,%edx
4d2: f7 f3 div %ebx
4d4: 89 45 ec mov %eax,-0x14(%ebp)
4d7: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
4db: 75 c7 jne 4a4 <printint+0x38>
if(neg)
4dd: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
4e1: 74 2d je 510 <printint+0xa4>
buf[i++] = '-';
4e3: 8b 45 f4 mov -0xc(%ebp),%eax
4e6: 8d 50 01 lea 0x1(%eax),%edx
4e9: 89 55 f4 mov %edx,-0xc(%ebp)
4ec: c6 44 05 dc 2d movb $0x2d,-0x24(%ebp,%eax,1)
while(--i >= 0)
4f1: eb 1d jmp 510 <printint+0xa4>
putc(fd, buf[i]);
4f3: 8d 55 dc lea -0x24(%ebp),%edx
4f6: 8b 45 f4 mov -0xc(%ebp),%eax
4f9: 01 d0 add %edx,%eax
4fb: 0f b6 00 movzbl (%eax),%eax
4fe: 0f be c0 movsbl %al,%eax
501: 83 ec 08 sub $0x8,%esp
504: 50 push %eax
505: ff 75 08 pushl 0x8(%ebp)
508: e8 3c ff ff ff call 449 <putc>
50d: 83 c4 10 add $0x10,%esp
while(--i >= 0)
510: 83 6d f4 01 subl $0x1,-0xc(%ebp)
514: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
518: 79 d9 jns 4f3 <printint+0x87>
}
51a: 90 nop
51b: 8b 5d fc mov -0x4(%ebp),%ebx
51e: c9 leave
51f: c3 ret
00000520 <printf>:
// Print to the given fd. Only understands %d, %x, %p, %s.
void
printf(int fd, char *fmt, ...)
{
520: 55 push %ebp
521: 89 e5 mov %esp,%ebp
523: 83 ec 28 sub $0x28,%esp
char *s;
int c, i, state;
uint *ap;
state = 0;
526: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
ap = (uint*)(void*)&fmt + 1;
52d: 8d 45 0c lea 0xc(%ebp),%eax
530: 83 c0 04 add $0x4,%eax
533: 89 45 e8 mov %eax,-0x18(%ebp)
for(i = 0; fmt[i]; i++){
536: c7 45 f0 00 00 00 00 movl $0x0,-0x10(%ebp)
53d: e9 59 01 00 00 jmp 69b <printf+0x17b>
c = fmt[i] & 0xff;
542: 8b 55 0c mov 0xc(%ebp),%edx
545: 8b 45 f0 mov -0x10(%ebp),%eax
548: 01 d0 add %edx,%eax
54a: 0f b6 00 movzbl (%eax),%eax
54d: 0f be c0 movsbl %al,%eax
550: 25 ff 00 00 00 and $0xff,%eax
555: 89 45 e4 mov %eax,-0x1c(%ebp)
if(state == 0){
558: 83 7d ec 00 cmpl $0x0,-0x14(%ebp)
55c: 75 2c jne 58a <printf+0x6a>
if(c == '%'){
55e: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
562: 75 0c jne 570 <printf+0x50>
state = '%';
564: c7 45 ec 25 00 00 00 movl $0x25,-0x14(%ebp)
56b: e9 27 01 00 00 jmp 697 <printf+0x177>
} else {
putc(fd, c);
570: 8b 45 e4 mov -0x1c(%ebp),%eax
573: 0f be c0 movsbl %al,%eax
576: 83 ec 08 sub $0x8,%esp
579: 50 push %eax
57a: ff 75 08 pushl 0x8(%ebp)
57d: e8 c7 fe ff ff call 449 <putc>
582: 83 c4 10 add $0x10,%esp
585: e9 0d 01 00 00 jmp 697 <printf+0x177>
}
} else if(state == '%'){
58a: 83 7d ec 25 cmpl $0x25,-0x14(%ebp)
58e: 0f 85 03 01 00 00 jne 697 <printf+0x177>
if(c == 'd'){
594: 83 7d e4 64 cmpl $0x64,-0x1c(%ebp)
598: 75 1e jne 5b8 <printf+0x98>
printint(fd, *ap, 10, 1);
59a: 8b 45 e8 mov -0x18(%ebp),%eax
59d: 8b 00 mov (%eax),%eax
59f: 6a 01 push $0x1
5a1: 6a 0a push $0xa
5a3: 50 push %eax
5a4: ff 75 08 pushl 0x8(%ebp)
5a7: e8 c0 fe ff ff call 46c <printint>
5ac: 83 c4 10 add $0x10,%esp
ap++;
5af: 83 45 e8 04 addl $0x4,-0x18(%ebp)
5b3: e9 d8 00 00 00 jmp 690 <printf+0x170>
} else if(c == 'x' || c == 'p'){
5b8: 83 7d e4 78 cmpl $0x78,-0x1c(%ebp)
5bc: 74 06 je 5c4 <printf+0xa4>
5be: 83 7d e4 70 cmpl $0x70,-0x1c(%ebp)
5c2: 75 1e jne 5e2 <printf+0xc2>
printint(fd, *ap, 16, 0);
5c4: 8b 45 e8 mov -0x18(%ebp),%eax
5c7: 8b 00 mov (%eax),%eax
5c9: 6a 00 push $0x0
5cb: 6a 10 push $0x10
5cd: 50 push %eax
5ce: ff 75 08 pushl 0x8(%ebp)
5d1: e8 96 fe ff ff call 46c <printint>
5d6: 83 c4 10 add $0x10,%esp
ap++;
5d9: 83 45 e8 04 addl $0x4,-0x18(%ebp)
5dd: e9 ae 00 00 00 jmp 690 <printf+0x170>
} else if(c == 's'){
5e2: 83 7d e4 73 cmpl $0x73,-0x1c(%ebp)
5e6: 75 43 jne 62b <printf+0x10b>
s = (char*)*ap;
5e8: 8b 45 e8 mov -0x18(%ebp),%eax
5eb: 8b 00 mov (%eax),%eax
5ed: 89 45 f4 mov %eax,-0xc(%ebp)
ap++;
5f0: 83 45 e8 04 addl $0x4,-0x18(%ebp)
if(s == 0)
5f4: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
5f8: 75 25 jne 61f <printf+0xff>
s = "(null)";
5fa: c7 45 f4 f9 08 00 00 movl $0x8f9,-0xc(%ebp)
while(*s != 0){
601: eb 1c jmp 61f <printf+0xff>
putc(fd, *s);
603: 8b 45 f4 mov -0xc(%ebp),%eax
606: 0f b6 00 movzbl (%eax),%eax
609: 0f be c0 movsbl %al,%eax
60c: 83 ec 08 sub $0x8,%esp
60f: 50 push %eax
610: ff 75 08 pushl 0x8(%ebp)
613: e8 31 fe ff ff call 449 <putc>
618: 83 c4 10 add $0x10,%esp
s++;
61b: 83 45 f4 01 addl $0x1,-0xc(%ebp)
while(*s != 0){
61f: 8b 45 f4 mov -0xc(%ebp),%eax
622: 0f b6 00 movzbl (%eax),%eax
625: 84 c0 test %al,%al
627: 75 da jne 603 <printf+0xe3>
629: eb 65 jmp 690 <printf+0x170>
}
} else if(c == 'c'){
62b: 83 7d e4 63 cmpl $0x63,-0x1c(%ebp)
62f: 75 1d jne 64e <printf+0x12e>
putc(fd, *ap);
631: 8b 45 e8 mov -0x18(%ebp),%eax
634: 8b 00 mov (%eax),%eax
636: 0f be c0 movsbl %al,%eax
639: 83 ec 08 sub $0x8,%esp
63c: 50 push %eax
63d: ff 75 08 pushl 0x8(%ebp)
640: e8 04 fe ff ff call 449 <putc>
645: 83 c4 10 add $0x10,%esp
ap++;
648: 83 45 e8 04 addl $0x4,-0x18(%ebp)
64c: eb 42 jmp 690 <printf+0x170>
} else if(c == '%'){
64e: 83 7d e4 25 cmpl $0x25,-0x1c(%ebp)
652: 75 17 jne 66b <printf+0x14b>
putc(fd, c);
654: 8b 45 e4 mov -0x1c(%ebp),%eax
657: 0f be c0 movsbl %al,%eax
65a: 83 ec 08 sub $0x8,%esp
65d: 50 push %eax
65e: ff 75 08 pushl 0x8(%ebp)
661: e8 e3 fd ff ff call 449 <putc>
666: 83 c4 10 add $0x10,%esp
669: eb 25 jmp 690 <printf+0x170>
} else {
// Unknown % sequence. Print it to draw attention.
putc(fd, '%');
66b: 83 ec 08 sub $0x8,%esp
66e: 6a 25 push $0x25
670: ff 75 08 pushl 0x8(%ebp)
673: e8 d1 fd ff ff call 449 <putc>
678: 83 c4 10 add $0x10,%esp
putc(fd, c);
67b: 8b 45 e4 mov -0x1c(%ebp),%eax
67e: 0f be c0 movsbl %al,%eax
681: 83 ec 08 sub $0x8,%esp
684: 50 push %eax
685: ff 75 08 pushl 0x8(%ebp)
688: e8 bc fd ff ff call 449 <putc>
68d: 83 c4 10 add $0x10,%esp
}
state = 0;
690: c7 45 ec 00 00 00 00 movl $0x0,-0x14(%ebp)
for(i = 0; fmt[i]; i++){
697: 83 45 f0 01 addl $0x1,-0x10(%ebp)
69b: 8b 55 0c mov 0xc(%ebp),%edx
69e: 8b 45 f0 mov -0x10(%ebp),%eax
6a1: 01 d0 add %edx,%eax
6a3: 0f b6 00 movzbl (%eax),%eax
6a6: 84 c0 test %al,%al
6a8: 0f 85 94 fe ff ff jne 542 <printf+0x22>
}
}
}
6ae: 90 nop
6af: c9 leave
6b0: c3 ret
000006b1 <free>:
static Header base;
static Header *freep;
void
free(void *ap)
{
6b1: 55 push %ebp
6b2: 89 e5 mov %esp,%ebp
6b4: 83 ec 10 sub $0x10,%esp
Header *bp, *p;
bp = (Header*)ap - 1;
6b7: 8b 45 08 mov 0x8(%ebp),%eax
6ba: 83 e8 08 sub $0x8,%eax
6bd: 89 45 f8 mov %eax,-0x8(%ebp)
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
6c0: a1 64 0b 00 00 mov 0xb64,%eax
6c5: 89 45 fc mov %eax,-0x4(%ebp)
6c8: eb 24 jmp 6ee <free+0x3d>
if(p >= p->s.ptr && (bp > p || bp < p->s.ptr))
6ca: 8b 45 fc mov -0x4(%ebp),%eax
6cd: 8b 00 mov (%eax),%eax
6cf: 3b 45 fc cmp -0x4(%ebp),%eax
6d2: 77 12 ja 6e6 <free+0x35>
6d4: 8b 45 f8 mov -0x8(%ebp),%eax
6d7: 3b 45 fc cmp -0x4(%ebp),%eax
6da: 77 24 ja 700 <free+0x4f>
6dc: 8b 45 fc mov -0x4(%ebp),%eax
6df: 8b 00 mov (%eax),%eax
6e1: 3b 45 f8 cmp -0x8(%ebp),%eax
6e4: 77 1a ja 700 <free+0x4f>
for(p = freep; !(bp > p && bp < p->s.ptr); p = p->s.ptr)
6e6: 8b 45 fc mov -0x4(%ebp),%eax
6e9: 8b 00 mov (%eax),%eax
6eb: 89 45 fc mov %eax,-0x4(%ebp)
6ee: 8b 45 f8 mov -0x8(%ebp),%eax
6f1: 3b 45 fc cmp -0x4(%ebp),%eax
6f4: 76 d4 jbe 6ca <free+0x19>
6f6: 8b 45 fc mov -0x4(%ebp),%eax
6f9: 8b 00 mov (%eax),%eax
6fb: 3b 45 f8 cmp -0x8(%ebp),%eax
6fe: 76 ca jbe 6ca <free+0x19>
break;
if(bp + bp->s.size == p->s.ptr){
700: 8b 45 f8 mov -0x8(%ebp),%eax
703: 8b 40 04 mov 0x4(%eax),%eax
706: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
70d: 8b 45 f8 mov -0x8(%ebp),%eax
710: 01 c2 add %eax,%edx
712: 8b 45 fc mov -0x4(%ebp),%eax
715: 8b 00 mov (%eax),%eax
717: 39 c2 cmp %eax,%edx
719: 75 24 jne 73f <free+0x8e>
bp->s.size += p->s.ptr->s.size;
71b: 8b 45 f8 mov -0x8(%ebp),%eax
71e: 8b 50 04 mov 0x4(%eax),%edx
721: 8b 45 fc mov -0x4(%ebp),%eax
724: 8b 00 mov (%eax),%eax
726: 8b 40 04 mov 0x4(%eax),%eax
729: 01 c2 add %eax,%edx
72b: 8b 45 f8 mov -0x8(%ebp),%eax
72e: 89 50 04 mov %edx,0x4(%eax)
bp->s.ptr = p->s.ptr->s.ptr;
731: 8b 45 fc mov -0x4(%ebp),%eax
734: 8b 00 mov (%eax),%eax
736: 8b 10 mov (%eax),%edx
738: 8b 45 f8 mov -0x8(%ebp),%eax
73b: 89 10 mov %edx,(%eax)
73d: eb 0a jmp 749 <free+0x98>
} else
bp->s.ptr = p->s.ptr;
73f: 8b 45 fc mov -0x4(%ebp),%eax
742: 8b 10 mov (%eax),%edx
744: 8b 45 f8 mov -0x8(%ebp),%eax
747: 89 10 mov %edx,(%eax)
if(p + p->s.size == bp){
749: 8b 45 fc mov -0x4(%ebp),%eax
74c: 8b 40 04 mov 0x4(%eax),%eax
74f: 8d 14 c5 00 00 00 00 lea 0x0(,%eax,8),%edx
756: 8b 45 fc mov -0x4(%ebp),%eax
759: 01 d0 add %edx,%eax
75b: 3b 45 f8 cmp -0x8(%ebp),%eax
75e: 75 20 jne 780 <free+0xcf>
p->s.size += bp->s.size;
760: 8b 45 fc mov -0x4(%ebp),%eax
763: 8b 50 04 mov 0x4(%eax),%edx
766: 8b 45 f8 mov -0x8(%ebp),%eax
769: 8b 40 04 mov 0x4(%eax),%eax
76c: 01 c2 add %eax,%edx
76e: 8b 45 fc mov -0x4(%ebp),%eax
771: 89 50 04 mov %edx,0x4(%eax)
p->s.ptr = bp->s.ptr;
774: 8b 45 f8 mov -0x8(%ebp),%eax
777: 8b 10 mov (%eax),%edx
779: 8b 45 fc mov -0x4(%ebp),%eax
77c: 89 10 mov %edx,(%eax)
77e: eb 08 jmp 788 <free+0xd7>
} else
p->s.ptr = bp;
780: 8b 45 fc mov -0x4(%ebp),%eax
783: 8b 55 f8 mov -0x8(%ebp),%edx
786: 89 10 mov %edx,(%eax)
freep = p;
788: 8b 45 fc mov -0x4(%ebp),%eax
78b: a3 64 0b 00 00 mov %eax,0xb64
}
790: 90 nop
791: c9 leave
792: c3 ret
00000793 <morecore>:
static Header*
morecore(uint nu)
{
793: 55 push %ebp
794: 89 e5 mov %esp,%ebp
796: 83 ec 18 sub $0x18,%esp
char *p;
Header *hp;
if(nu < 4096)
799: 81 7d 08 ff 0f 00 00 cmpl $0xfff,0x8(%ebp)
7a0: 77 07 ja 7a9 <morecore+0x16>
nu = 4096;
7a2: c7 45 08 00 10 00 00 movl $0x1000,0x8(%ebp)
p = sbrk(nu * sizeof(Header));
7a9: 8b 45 08 mov 0x8(%ebp),%eax
7ac: c1 e0 03 shl $0x3,%eax
7af: 83 ec 0c sub $0xc,%esp
7b2: 50 push %eax
7b3: e8 79 fc ff ff call 431 <sbrk>
7b8: 83 c4 10 add $0x10,%esp
7bb: 89 45 f4 mov %eax,-0xc(%ebp)
if(p == (char*)-1)
7be: 83 7d f4 ff cmpl $0xffffffff,-0xc(%ebp)
7c2: 75 07 jne 7cb <morecore+0x38>
return 0;
7c4: b8 00 00 00 00 mov $0x0,%eax
7c9: eb 26 jmp 7f1 <morecore+0x5e>
hp = (Header*)p;
7cb: 8b 45 f4 mov -0xc(%ebp),%eax
7ce: 89 45 f0 mov %eax,-0x10(%ebp)
hp->s.size = nu;
7d1: 8b 45 f0 mov -0x10(%ebp),%eax
7d4: 8b 55 08 mov 0x8(%ebp),%edx
7d7: 89 50 04 mov %edx,0x4(%eax)
free((void*)(hp + 1));
7da: 8b 45 f0 mov -0x10(%ebp),%eax
7dd: 83 c0 08 add $0x8,%eax
7e0: 83 ec 0c sub $0xc,%esp
7e3: 50 push %eax
7e4: e8 c8 fe ff ff call 6b1 <free>
7e9: 83 c4 10 add $0x10,%esp
return freep;
7ec: a1 64 0b 00 00 mov 0xb64,%eax
}
7f1: c9 leave
7f2: c3 ret
000007f3 <malloc>:
void*
malloc(uint nbytes)
{
7f3: 55 push %ebp
7f4: 89 e5 mov %esp,%ebp
7f6: 83 ec 18 sub $0x18,%esp
Header *p, *prevp;
uint nunits;
nunits = (nbytes + sizeof(Header) - 1)/sizeof(Header) + 1;
7f9: 8b 45 08 mov 0x8(%ebp),%eax
7fc: 83 c0 07 add $0x7,%eax
7ff: c1 e8 03 shr $0x3,%eax
802: 83 c0 01 add $0x1,%eax
805: 89 45 ec mov %eax,-0x14(%ebp)
if((prevp = freep) == 0){
808: a1 64 0b 00 00 mov 0xb64,%eax
80d: 89 45 f0 mov %eax,-0x10(%ebp)
810: 83 7d f0 00 cmpl $0x0,-0x10(%ebp)
814: 75 23 jne 839 <malloc+0x46>
base.s.ptr = freep = prevp = &base;
816: c7 45 f0 5c 0b 00 00 movl $0xb5c,-0x10(%ebp)
81d: 8b 45 f0 mov -0x10(%ebp),%eax
820: a3 64 0b 00 00 mov %eax,0xb64
825: a1 64 0b 00 00 mov 0xb64,%eax
82a: a3 5c 0b 00 00 mov %eax,0xb5c
base.s.size = 0;
82f: c7 05 60 0b 00 00 00 movl $0x0,0xb60
836: 00 00 00
}
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
839: 8b 45 f0 mov -0x10(%ebp),%eax
83c: 8b 00 mov (%eax),%eax
83e: 89 45 f4 mov %eax,-0xc(%ebp)
if(p->s.size >= nunits){
841: 8b 45 f4 mov -0xc(%ebp),%eax
844: 8b 40 04 mov 0x4(%eax),%eax
847: 3b 45 ec cmp -0x14(%ebp),%eax
84a: 72 4d jb 899 <malloc+0xa6>
if(p->s.size == nunits)
84c: 8b 45 f4 mov -0xc(%ebp),%eax
84f: 8b 40 04 mov 0x4(%eax),%eax
852: 3b 45 ec cmp -0x14(%ebp),%eax
855: 75 0c jne 863 <malloc+0x70>
prevp->s.ptr = p->s.ptr;
857: 8b 45 f4 mov -0xc(%ebp),%eax
85a: 8b 10 mov (%eax),%edx
85c: 8b 45 f0 mov -0x10(%ebp),%eax
85f: 89 10 mov %edx,(%eax)
861: eb 26 jmp 889 <malloc+0x96>
else {
p->s.size -= nunits;
863: 8b 45 f4 mov -0xc(%ebp),%eax
866: 8b 40 04 mov 0x4(%eax),%eax
869: 2b 45 ec sub -0x14(%ebp),%eax
86c: 89 c2 mov %eax,%edx
86e: 8b 45 f4 mov -0xc(%ebp),%eax
871: 89 50 04 mov %edx,0x4(%eax)
p += p->s.size;
874: 8b 45 f4 mov -0xc(%ebp),%eax
877: 8b 40 04 mov 0x4(%eax),%eax
87a: c1 e0 03 shl $0x3,%eax
87d: 01 45 f4 add %eax,-0xc(%ebp)
p->s.size = nunits;
880: 8b 45 f4 mov -0xc(%ebp),%eax
883: 8b 55 ec mov -0x14(%ebp),%edx
886: 89 50 04 mov %edx,0x4(%eax)
}
freep = prevp;
889: 8b 45 f0 mov -0x10(%ebp),%eax
88c: a3 64 0b 00 00 mov %eax,0xb64
return (void*)(p + 1);
891: 8b 45 f4 mov -0xc(%ebp),%eax
894: 83 c0 08 add $0x8,%eax
897: eb 3b jmp 8d4 <malloc+0xe1>
}
if(p == freep)
899: a1 64 0b 00 00 mov 0xb64,%eax
89e: 39 45 f4 cmp %eax,-0xc(%ebp)
8a1: 75 1e jne 8c1 <malloc+0xce>
if((p = morecore(nunits)) == 0)
8a3: 83 ec 0c sub $0xc,%esp
8a6: ff 75 ec pushl -0x14(%ebp)
8a9: e8 e5 fe ff ff call 793 <morecore>
8ae: 83 c4 10 add $0x10,%esp
8b1: 89 45 f4 mov %eax,-0xc(%ebp)
8b4: 83 7d f4 00 cmpl $0x0,-0xc(%ebp)
8b8: 75 07 jne 8c1 <malloc+0xce>
return 0;
8ba: b8 00 00 00 00 mov $0x0,%eax
8bf: eb 13 jmp 8d4 <malloc+0xe1>
for(p = prevp->s.ptr; ; prevp = p, p = p->s.ptr){
8c1: 8b 45 f4 mov -0xc(%ebp),%eax
8c4: 89 45 f0 mov %eax,-0x10(%ebp)
8c7: 8b 45 f4 mov -0xc(%ebp),%eax
8ca: 8b 00 mov (%eax),%eax
8cc: 89 45 f4 mov %eax,-0xc(%ebp)
if(p->s.size >= nunits){
8cf: e9 6d ff ff ff jmp 841 <malloc+0x4e>
}
}
8d4: c9 leave
8d5: c3 ret
| bouzou4/xv6-OS-Work | stressfs.asm | Assembly | mit | 43,033 |
//===========================================================================//
// GLOSS - Generic Loader for Operating System Software //
// An extensible and configurable bootloader. //
//---------------------------------------------------------------------------//
// Copyright (C) 2013-2016 ~ Adrian J. Collado <acollado@polaritech.com> //
// All Rights Reserved //
//===========================================================================//
// Seeing as how AT&T syntax is much more obscure and difficult to read (IMO)
// than Intel syntax, the assembly language code in this project for x86 based
// architectures will be using Intel syntax.
.intel_syntax noprefix
// This code will be executed in a 16 bit real mode environment.
.code16
// This code is located in the .TEXT (executable) section of the executable.
.section .text
// This function toggles the A20 line using the "Fast" A20 method (System
// Control Port 0x92).
.global I8086.A20.Toggle.Fast
I8086.A20.Toggle.Fast:
// This function, while called the Fast A20 method, is actually quite slow,
// and on some systems is dangerous. This function is the least recommended
// of all of the functions we use to toggle the A20 line. What this
// function does is outputs a value through system control port 0x92. The
// problem with this method is that on some computers it is unsupported,
// while on other computers it may do something entirely different (such as
// clearing the screen or eating your laundry). Therefore, we should only
// use this method if we have no other choice.
push ax
in al, 0x92
xor al, 0x02
and al, 0xfe
out 0x92, al
pop ax
ret
| AdrianCollado/SlickOS | Modules/Gloss/Arch/x86_64/Source/A20/Toggle.Fast.asm | Assembly | mit | 1,798 |
TITLE des-586.asm
IF @Version LT 800
ECHO MASM version 8.00 or later is strongly recommended.
ENDIF
.686
.MODEL FLAT
OPTION DOTNAME
IF @Version LT 800
.text$ SEGMENT PAGE 'CODE'
ELSE
.text$ SEGMENT ALIGN(64) 'CODE'
ENDIF
PUBLIC _DES_SPtrans
ALIGN 16
__x86_DES_encrypt PROC PRIVATE
push ecx
; Round 0
mov eax,DWORD PTR [ecx]
xor ebx,ebx
mov edx,DWORD PTR 4[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 1
mov eax,DWORD PTR 8[ecx]
xor ebx,ebx
mov edx,DWORD PTR 12[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 2
mov eax,DWORD PTR 16[ecx]
xor ebx,ebx
mov edx,DWORD PTR 20[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 3
mov eax,DWORD PTR 24[ecx]
xor ebx,ebx
mov edx,DWORD PTR 28[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 4
mov eax,DWORD PTR 32[ecx]
xor ebx,ebx
mov edx,DWORD PTR 36[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 5
mov eax,DWORD PTR 40[ecx]
xor ebx,ebx
mov edx,DWORD PTR 44[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 6
mov eax,DWORD PTR 48[ecx]
xor ebx,ebx
mov edx,DWORD PTR 52[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 7
mov eax,DWORD PTR 56[ecx]
xor ebx,ebx
mov edx,DWORD PTR 60[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 8
mov eax,DWORD PTR 64[ecx]
xor ebx,ebx
mov edx,DWORD PTR 68[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 9
mov eax,DWORD PTR 72[ecx]
xor ebx,ebx
mov edx,DWORD PTR 76[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 10
mov eax,DWORD PTR 80[ecx]
xor ebx,ebx
mov edx,DWORD PTR 84[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 11
mov eax,DWORD PTR 88[ecx]
xor ebx,ebx
mov edx,DWORD PTR 92[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 12
mov eax,DWORD PTR 96[ecx]
xor ebx,ebx
mov edx,DWORD PTR 100[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 13
mov eax,DWORD PTR 104[ecx]
xor ebx,ebx
mov edx,DWORD PTR 108[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 14
mov eax,DWORD PTR 112[ecx]
xor ebx,ebx
mov edx,DWORD PTR 116[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 15
mov eax,DWORD PTR 120[ecx]
xor ebx,ebx
mov edx,DWORD PTR 124[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
add esp,4
ret
__x86_DES_encrypt ENDP
ALIGN 16
__x86_DES_decrypt PROC PRIVATE
push ecx
; Round 15
mov eax,DWORD PTR 120[ecx]
xor ebx,ebx
mov edx,DWORD PTR 124[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 14
mov eax,DWORD PTR 112[ecx]
xor ebx,ebx
mov edx,DWORD PTR 116[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 13
mov eax,DWORD PTR 104[ecx]
xor ebx,ebx
mov edx,DWORD PTR 108[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 12
mov eax,DWORD PTR 96[ecx]
xor ebx,ebx
mov edx,DWORD PTR 100[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 11
mov eax,DWORD PTR 88[ecx]
xor ebx,ebx
mov edx,DWORD PTR 92[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 10
mov eax,DWORD PTR 80[ecx]
xor ebx,ebx
mov edx,DWORD PTR 84[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 9
mov eax,DWORD PTR 72[ecx]
xor ebx,ebx
mov edx,DWORD PTR 76[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 8
mov eax,DWORD PTR 64[ecx]
xor ebx,ebx
mov edx,DWORD PTR 68[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 7
mov eax,DWORD PTR 56[ecx]
xor ebx,ebx
mov edx,DWORD PTR 60[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 6
mov eax,DWORD PTR 48[ecx]
xor ebx,ebx
mov edx,DWORD PTR 52[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 5
mov eax,DWORD PTR 40[ecx]
xor ebx,ebx
mov edx,DWORD PTR 44[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 4
mov eax,DWORD PTR 32[ecx]
xor ebx,ebx
mov edx,DWORD PTR 36[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 3
mov eax,DWORD PTR 24[ecx]
xor ebx,ebx
mov edx,DWORD PTR 28[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 2
mov eax,DWORD PTR 16[ecx]
xor ebx,ebx
mov edx,DWORD PTR 20[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
; Round 1
mov eax,DWORD PTR 8[ecx]
xor ebx,ebx
mov edx,DWORD PTR 12[ecx]
xor eax,esi
xor ecx,ecx
xor edx,esi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor edi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor edi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor edi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor edi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor edi,DWORD PTR 0600h[ebx*1+ebp]
xor edi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor edi,DWORD PTR 0400h[eax*1+ebp]
xor edi,DWORD PTR 0500h[edx*1+ebp]
; Round 0
mov eax,DWORD PTR [ecx]
xor ebx,ebx
mov edx,DWORD PTR 4[ecx]
xor eax,edi
xor ecx,ecx
xor edx,edi
and eax,0fcfcfcfch
and edx,0cfcfcfcfh
mov bl,al
mov cl,ah
ror edx,4
xor esi,DWORD PTR [ebx*1+ebp]
mov bl,dl
xor esi,DWORD PTR 0200h[ecx*1+ebp]
mov cl,dh
shr eax,16
xor esi,DWORD PTR 0100h[ebx*1+ebp]
mov bl,ah
shr edx,16
xor esi,DWORD PTR 0300h[ecx*1+ebp]
mov cl,dh
and eax,0ffh
and edx,0ffh
xor esi,DWORD PTR 0600h[ebx*1+ebp]
xor esi,DWORD PTR 0700h[ecx*1+ebp]
mov ecx,DWORD PTR [esp]
xor esi,DWORD PTR 0400h[eax*1+ebp]
xor esi,DWORD PTR 0500h[edx*1+ebp]
add esp,4
ret
__x86_DES_decrypt ENDP
ALIGN 16
_DES_encrypt1 PROC PUBLIC
$L_DES_encrypt1_begin::
push esi
push edi
;
; Load the 2 words
mov esi,DWORD PTR 12[esp]
xor ecx,ecx
push ebx
push ebp
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 28[esp]
mov edi,DWORD PTR 4[esi]
;
; IP
rol eax,4
mov esi,eax
xor eax,edi
and eax,0f0f0f0f0h
xor esi,eax
xor edi,eax
;
rol edi,20
mov eax,edi
xor edi,esi
and edi,0fff0000fh
xor eax,edi
xor esi,edi
;
rol eax,14
mov edi,eax
xor eax,esi
and eax,033333333h
xor edi,eax
xor esi,eax
;
rol esi,22
mov eax,esi
xor esi,edi
and esi,003fc03fch
xor eax,esi
xor edi,esi
;
rol eax,9
mov esi,eax
xor eax,edi
and eax,0aaaaaaaah
xor esi,eax
xor edi,eax
;
rol edi,1
call $L000pic_point
$L000pic_point:
pop ebp
lea ebp,DWORD PTR ($Ldes_sptrans-$L000pic_point)[ebp]
mov ecx,DWORD PTR 24[esp]
cmp ebx,0
je $L001decrypt
call __x86_DES_encrypt
jmp $L002done
$L001decrypt:
call __x86_DES_decrypt
$L002done:
;
; FP
mov edx,DWORD PTR 20[esp]
ror esi,1
mov eax,edi
xor edi,esi
and edi,0aaaaaaaah
xor eax,edi
xor esi,edi
;
rol eax,23
mov edi,eax
xor eax,esi
and eax,003fc03fch
xor edi,eax
xor esi,eax
;
rol edi,10
mov eax,edi
xor edi,esi
and edi,033333333h
xor eax,edi
xor esi,edi
;
rol esi,18
mov edi,esi
xor esi,eax
and esi,0fff0000fh
xor edi,esi
xor eax,esi
;
rol edi,12
mov esi,edi
xor edi,eax
and edi,0f0f0f0f0h
xor esi,edi
xor eax,edi
;
ror eax,4
mov DWORD PTR [edx],eax
mov DWORD PTR 4[edx],esi
pop ebp
pop ebx
pop edi
pop esi
ret
_DES_encrypt1 ENDP
ALIGN 16
_DES_encrypt2 PROC PUBLIC
$L_DES_encrypt2_begin::
push esi
push edi
;
; Load the 2 words
mov eax,DWORD PTR 12[esp]
xor ecx,ecx
push ebx
push ebp
mov esi,DWORD PTR [eax]
mov ebx,DWORD PTR 28[esp]
rol esi,3
mov edi,DWORD PTR 4[eax]
rol edi,3
call $L003pic_point
$L003pic_point:
pop ebp
lea ebp,DWORD PTR ($Ldes_sptrans-$L003pic_point)[ebp]
mov ecx,DWORD PTR 24[esp]
cmp ebx,0
je $L004decrypt
call __x86_DES_encrypt
jmp $L005done
$L004decrypt:
call __x86_DES_decrypt
$L005done:
;
; Fixup
ror edi,3
mov eax,DWORD PTR 20[esp]
ror esi,3
mov DWORD PTR [eax],edi
mov DWORD PTR 4[eax],esi
pop ebp
pop ebx
pop edi
pop esi
ret
_DES_encrypt2 ENDP
ALIGN 16
_DES_encrypt3 PROC PUBLIC
$L_DES_encrypt3_begin::
push ebx
mov ebx,DWORD PTR 8[esp]
push ebp
push esi
push edi
;
; Load the data words
mov edi,DWORD PTR [ebx]
mov esi,DWORD PTR 4[ebx]
sub esp,12
;
; IP
rol edi,4
mov edx,edi
xor edi,esi
and edi,0f0f0f0f0h
xor edx,edi
xor esi,edi
;
rol esi,20
mov edi,esi
xor esi,edx
and esi,0fff0000fh
xor edi,esi
xor edx,esi
;
rol edi,14
mov esi,edi
xor edi,edx
and edi,033333333h
xor esi,edi
xor edx,edi
;
rol edx,22
mov edi,edx
xor edx,esi
and edx,003fc03fch
xor edi,edx
xor esi,edx
;
rol edi,9
mov edx,edi
xor edi,esi
and edi,0aaaaaaaah
xor edx,edi
xor esi,edi
;
ror edx,3
ror esi,2
mov DWORD PTR 4[ebx],esi
mov eax,DWORD PTR 36[esp]
mov DWORD PTR [ebx],edx
mov edi,DWORD PTR 40[esp]
mov esi,DWORD PTR 44[esp]
mov DWORD PTR 8[esp],1
mov DWORD PTR 4[esp],eax
mov DWORD PTR [esp],ebx
call $L_DES_encrypt2_begin
mov DWORD PTR 8[esp],0
mov DWORD PTR 4[esp],edi
mov DWORD PTR [esp],ebx
call $L_DES_encrypt2_begin
mov DWORD PTR 8[esp],1
mov DWORD PTR 4[esp],esi
mov DWORD PTR [esp],ebx
call $L_DES_encrypt2_begin
add esp,12
mov edi,DWORD PTR [ebx]
mov esi,DWORD PTR 4[ebx]
;
; FP
rol esi,2
rol edi,3
mov eax,edi
xor edi,esi
and edi,0aaaaaaaah
xor eax,edi
xor esi,edi
;
rol eax,23
mov edi,eax
xor eax,esi
and eax,003fc03fch
xor edi,eax
xor esi,eax
;
rol edi,10
mov eax,edi
xor edi,esi
and edi,033333333h
xor eax,edi
xor esi,edi
;
rol esi,18
mov edi,esi
xor esi,eax
and esi,0fff0000fh
xor edi,esi
xor eax,esi
;
rol edi,12
mov esi,edi
xor edi,eax
and edi,0f0f0f0f0h
xor esi,edi
xor eax,edi
;
ror eax,4
mov DWORD PTR [ebx],eax
mov DWORD PTR 4[ebx],esi
pop edi
pop esi
pop ebp
pop ebx
ret
_DES_encrypt3 ENDP
ALIGN 16
_DES_decrypt3 PROC PUBLIC
$L_DES_decrypt3_begin::
push ebx
mov ebx,DWORD PTR 8[esp]
push ebp
push esi
push edi
;
; Load the data words
mov edi,DWORD PTR [ebx]
mov esi,DWORD PTR 4[ebx]
sub esp,12
;
; IP
rol edi,4
mov edx,edi
xor edi,esi
and edi,0f0f0f0f0h
xor edx,edi
xor esi,edi
;
rol esi,20
mov edi,esi
xor esi,edx
and esi,0fff0000fh
xor edi,esi
xor edx,esi
;
rol edi,14
mov esi,edi
xor edi,edx
and edi,033333333h
xor esi,edi
xor edx,edi
;
rol edx,22
mov edi,edx
xor edx,esi
and edx,003fc03fch
xor edi,edx
xor esi,edx
;
rol edi,9
mov edx,edi
xor edi,esi
and edi,0aaaaaaaah
xor edx,edi
xor esi,edi
;
ror edx,3
ror esi,2
mov DWORD PTR 4[ebx],esi
mov esi,DWORD PTR 36[esp]
mov DWORD PTR [ebx],edx
mov edi,DWORD PTR 40[esp]
mov eax,DWORD PTR 44[esp]
mov DWORD PTR 8[esp],0
mov DWORD PTR 4[esp],eax
mov DWORD PTR [esp],ebx
call $L_DES_encrypt2_begin
mov DWORD PTR 8[esp],1
mov DWORD PTR 4[esp],edi
mov DWORD PTR [esp],ebx
call $L_DES_encrypt2_begin
mov DWORD PTR 8[esp],0
mov DWORD PTR 4[esp],esi
mov DWORD PTR [esp],ebx
call $L_DES_encrypt2_begin
add esp,12
mov edi,DWORD PTR [ebx]
mov esi,DWORD PTR 4[ebx]
;
; FP
rol esi,2
rol edi,3
mov eax,edi
xor edi,esi
and edi,0aaaaaaaah
xor eax,edi
xor esi,edi
;
rol eax,23
mov edi,eax
xor eax,esi
and eax,003fc03fch
xor edi,eax
xor esi,eax
;
rol edi,10
mov eax,edi
xor edi,esi
and edi,033333333h
xor eax,edi
xor esi,edi
;
rol esi,18
mov edi,esi
xor esi,eax
and esi,0fff0000fh
xor edi,esi
xor eax,esi
;
rol edi,12
mov esi,edi
xor edi,eax
and edi,0f0f0f0f0h
xor esi,edi
xor eax,edi
;
ror eax,4
mov DWORD PTR [ebx],eax
mov DWORD PTR 4[ebx],esi
pop edi
pop esi
pop ebp
pop ebx
ret
_DES_decrypt3 ENDP
ALIGN 16
_DES_ncbc_encrypt PROC PUBLIC
$L_DES_ncbc_encrypt_begin::
;
push ebp
push ebx
push esi
push edi
mov ebp,DWORD PTR 28[esp]
; getting iv ptr from parameter 4
mov ebx,DWORD PTR 36[esp]
mov esi,DWORD PTR [ebx]
mov edi,DWORD PTR 4[ebx]
push edi
push esi
push edi
push esi
mov ebx,esp
mov esi,DWORD PTR 36[esp]
mov edi,DWORD PTR 40[esp]
; getting encrypt flag from parameter 5
mov ecx,DWORD PTR 56[esp]
; get and push parameter 5
push ecx
; get and push parameter 3
mov eax,DWORD PTR 52[esp]
push eax
push ebx
cmp ecx,0
jz $L006decrypt
and ebp,4294967288
mov eax,DWORD PTR 12[esp]
mov ebx,DWORD PTR 16[esp]
jz $L007encrypt_finish
$L008encrypt_loop:
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR 4[esi]
xor eax,ecx
xor ebx,edx
mov DWORD PTR 12[esp],eax
mov DWORD PTR 16[esp],ebx
call $L_DES_encrypt1_begin
mov eax,DWORD PTR 12[esp]
mov ebx,DWORD PTR 16[esp]
mov DWORD PTR [edi],eax
mov DWORD PTR 4[edi],ebx
add esi,8
add edi,8
sub ebp,8
jnz $L008encrypt_loop
$L007encrypt_finish:
mov ebp,DWORD PTR 56[esp]
and ebp,7
jz $L009finish
call $L010PIC_point
$L010PIC_point:
pop edx
lea ecx,DWORD PTR ($L011cbc_enc_jmp_table-$L010PIC_point)[edx]
mov ebp,DWORD PTR [ebp*4+ecx]
add ebp,edx
xor ecx,ecx
xor edx,edx
jmp ebp
$L012ej7:
mov dh,BYTE PTR 6[esi]
shl edx,8
$L013ej6:
mov dh,BYTE PTR 5[esi]
$L014ej5:
mov dl,BYTE PTR 4[esi]
$L015ej4:
mov ecx,DWORD PTR [esi]
jmp $L016ejend
$L017ej3:
mov ch,BYTE PTR 2[esi]
shl ecx,8
$L018ej2:
mov ch,BYTE PTR 1[esi]
$L019ej1:
mov cl,BYTE PTR [esi]
$L016ejend:
xor eax,ecx
xor ebx,edx
mov DWORD PTR 12[esp],eax
mov DWORD PTR 16[esp],ebx
call $L_DES_encrypt1_begin
mov eax,DWORD PTR 12[esp]
mov ebx,DWORD PTR 16[esp]
mov DWORD PTR [edi],eax
mov DWORD PTR 4[edi],ebx
jmp $L009finish
$L006decrypt:
and ebp,4294967288
mov eax,DWORD PTR 20[esp]
mov ebx,DWORD PTR 24[esp]
jz $L020decrypt_finish
$L021decrypt_loop:
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov DWORD PTR 12[esp],eax
mov DWORD PTR 16[esp],ebx
call $L_DES_encrypt1_begin
mov eax,DWORD PTR 12[esp]
mov ebx,DWORD PTR 16[esp]
mov ecx,DWORD PTR 20[esp]
mov edx,DWORD PTR 24[esp]
xor ecx,eax
xor edx,ebx
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov DWORD PTR [edi],ecx
mov DWORD PTR 4[edi],edx
mov DWORD PTR 20[esp],eax
mov DWORD PTR 24[esp],ebx
add esi,8
add edi,8
sub ebp,8
jnz $L021decrypt_loop
$L020decrypt_finish:
mov ebp,DWORD PTR 56[esp]
and ebp,7
jz $L009finish
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov DWORD PTR 12[esp],eax
mov DWORD PTR 16[esp],ebx
call $L_DES_encrypt1_begin
mov eax,DWORD PTR 12[esp]
mov ebx,DWORD PTR 16[esp]
mov ecx,DWORD PTR 20[esp]
mov edx,DWORD PTR 24[esp]
xor ecx,eax
xor edx,ebx
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
$L022dj7:
ror edx,16
mov BYTE PTR 6[edi],dl
shr edx,16
$L023dj6:
mov BYTE PTR 5[edi],dh
$L024dj5:
mov BYTE PTR 4[edi],dl
$L025dj4:
mov DWORD PTR [edi],ecx
jmp $L026djend
$L027dj3:
ror ecx,16
mov BYTE PTR 2[edi],cl
shl ecx,16
$L028dj2:
mov BYTE PTR 1[esi],ch
$L029dj1:
mov BYTE PTR [esi],cl
$L026djend:
jmp $L009finish
$L009finish:
mov ecx,DWORD PTR 64[esp]
add esp,28
mov DWORD PTR [ecx],eax
mov DWORD PTR 4[ecx],ebx
pop edi
pop esi
pop ebx
pop ebp
ret
ALIGN 64
$L011cbc_enc_jmp_table:
DD 0
DD $L019ej1-$L010PIC_point
DD $L018ej2-$L010PIC_point
DD $L017ej3-$L010PIC_point
DD $L015ej4-$L010PIC_point
DD $L014ej5-$L010PIC_point
DD $L013ej6-$L010PIC_point
DD $L012ej7-$L010PIC_point
ALIGN 64
_DES_ncbc_encrypt ENDP
ALIGN 16
_DES_ede3_cbc_encrypt PROC PUBLIC
$L_DES_ede3_cbc_encrypt_begin::
;
push ebp
push ebx
push esi
push edi
mov ebp,DWORD PTR 28[esp]
; getting iv ptr from parameter 6
mov ebx,DWORD PTR 44[esp]
mov esi,DWORD PTR [ebx]
mov edi,DWORD PTR 4[ebx]
push edi
push esi
push edi
push esi
mov ebx,esp
mov esi,DWORD PTR 36[esp]
mov edi,DWORD PTR 40[esp]
; getting encrypt flag from parameter 7
mov ecx,DWORD PTR 64[esp]
; get and push parameter 5
mov eax,DWORD PTR 56[esp]
push eax
; get and push parameter 4
mov eax,DWORD PTR 56[esp]
push eax
; get and push parameter 3
mov eax,DWORD PTR 56[esp]
push eax
push ebx
cmp ecx,0
jz $L030decrypt
and ebp,4294967288
mov eax,DWORD PTR 16[esp]
mov ebx,DWORD PTR 20[esp]
jz $L031encrypt_finish
$L032encrypt_loop:
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR 4[esi]
xor eax,ecx
xor ebx,edx
mov DWORD PTR 16[esp],eax
mov DWORD PTR 20[esp],ebx
call $L_DES_encrypt3_begin
mov eax,DWORD PTR 16[esp]
mov ebx,DWORD PTR 20[esp]
mov DWORD PTR [edi],eax
mov DWORD PTR 4[edi],ebx
add esi,8
add edi,8
sub ebp,8
jnz $L032encrypt_loop
$L031encrypt_finish:
mov ebp,DWORD PTR 60[esp]
and ebp,7
jz $L033finish
call $L034PIC_point
$L034PIC_point:
pop edx
lea ecx,DWORD PTR ($L035cbc_enc_jmp_table-$L034PIC_point)[edx]
mov ebp,DWORD PTR [ebp*4+ecx]
add ebp,edx
xor ecx,ecx
xor edx,edx
jmp ebp
$L036ej7:
mov dh,BYTE PTR 6[esi]
shl edx,8
$L037ej6:
mov dh,BYTE PTR 5[esi]
$L038ej5:
mov dl,BYTE PTR 4[esi]
$L039ej4:
mov ecx,DWORD PTR [esi]
jmp $L040ejend
$L041ej3:
mov ch,BYTE PTR 2[esi]
shl ecx,8
$L042ej2:
mov ch,BYTE PTR 1[esi]
$L043ej1:
mov cl,BYTE PTR [esi]
$L040ejend:
xor eax,ecx
xor ebx,edx
mov DWORD PTR 16[esp],eax
mov DWORD PTR 20[esp],ebx
call $L_DES_encrypt3_begin
mov eax,DWORD PTR 16[esp]
mov ebx,DWORD PTR 20[esp]
mov DWORD PTR [edi],eax
mov DWORD PTR 4[edi],ebx
jmp $L033finish
$L030decrypt:
and ebp,4294967288
mov eax,DWORD PTR 24[esp]
mov ebx,DWORD PTR 28[esp]
jz $L044decrypt_finish
$L045decrypt_loop:
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov DWORD PTR 16[esp],eax
mov DWORD PTR 20[esp],ebx
call $L_DES_decrypt3_begin
mov eax,DWORD PTR 16[esp]
mov ebx,DWORD PTR 20[esp]
mov ecx,DWORD PTR 24[esp]
mov edx,DWORD PTR 28[esp]
xor ecx,eax
xor edx,ebx
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov DWORD PTR [edi],ecx
mov DWORD PTR 4[edi],edx
mov DWORD PTR 24[esp],eax
mov DWORD PTR 28[esp],ebx
add esi,8
add edi,8
sub ebp,8
jnz $L045decrypt_loop
$L044decrypt_finish:
mov ebp,DWORD PTR 60[esp]
and ebp,7
jz $L033finish
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
mov DWORD PTR 16[esp],eax
mov DWORD PTR 20[esp],ebx
call $L_DES_decrypt3_begin
mov eax,DWORD PTR 16[esp]
mov ebx,DWORD PTR 20[esp]
mov ecx,DWORD PTR 24[esp]
mov edx,DWORD PTR 28[esp]
xor ecx,eax
xor edx,ebx
mov eax,DWORD PTR [esi]
mov ebx,DWORD PTR 4[esi]
$L046dj7:
ror edx,16
mov BYTE PTR 6[edi],dl
shr edx,16
$L047dj6:
mov BYTE PTR 5[edi],dh
$L048dj5:
mov BYTE PTR 4[edi],dl
$L049dj4:
mov DWORD PTR [edi],ecx
jmp $L050djend
$L051dj3:
ror ecx,16
mov BYTE PTR 2[edi],cl
shl ecx,16
$L052dj2:
mov BYTE PTR 1[esi],ch
$L053dj1:
mov BYTE PTR [esi],cl
$L050djend:
jmp $L033finish
$L033finish:
mov ecx,DWORD PTR 76[esp]
add esp,32
mov DWORD PTR [ecx],eax
mov DWORD PTR 4[ecx],ebx
pop edi
pop esi
pop ebx
pop ebp
ret
ALIGN 64
$L035cbc_enc_jmp_table:
DD 0
DD $L043ej1-$L034PIC_point
DD $L042ej2-$L034PIC_point
DD $L041ej3-$L034PIC_point
DD $L039ej4-$L034PIC_point
DD $L038ej5-$L034PIC_point
DD $L037ej6-$L034PIC_point
DD $L036ej7-$L034PIC_point
ALIGN 64
_DES_ede3_cbc_encrypt ENDP
ALIGN 64
_DES_SPtrans::
$Ldes_sptrans::
DD 34080768,524288,33554434,34080770
DD 33554432,526338,524290,33554434
DD 526338,34080768,34078720,2050
DD 33556482,33554432,0,524290
DD 524288,2,33556480,526336
DD 34080770,34078720,2050,33556480
DD 2,2048,526336,34078722
DD 2048,33556482,34078722,0
DD 0,34080770,33556480,524290
DD 34080768,524288,2050,33556480
DD 34078722,2048,526336,33554434
DD 526338,2,33554434,34078720
DD 34080770,526336,34078720,33556482
DD 33554432,2050,524290,0
DD 524288,33554432,33556482,34080768
DD 2,34078722,2048,526338
DD 1074823184,0,1081344,1074790400
DD 1073741840,32784,1073774592,1081344
DD 32768,1074790416,16,1073774592
DD 1048592,1074823168,1074790400,16
DD 1048576,1073774608,1074790416,32768
DD 1081360,1073741824,0,1048592
DD 1073774608,1081360,1074823168,1073741840
DD 1073741824,1048576,32784,1074823184
DD 1048592,1074823168,1073774592,1081360
DD 1074823184,1048592,1073741840,0
DD 1073741824,32784,1048576,1074790416
DD 32768,1073741824,1081360,1073774608
DD 1074823168,32768,0,1073741840
DD 16,1074823184,1081344,1074790400
DD 1074790416,1048576,32784,1073774592
DD 1073774608,16,1074790400,1081344
DD 67108865,67371264,256,67109121
DD 262145,67108864,67109121,262400
DD 67109120,262144,67371008,1
DD 67371265,257,1,67371009
DD 0,262145,67371264,256
DD 257,67371265,262144,67108865
DD 67371009,67109120,262401,67371008
DD 262400,0,67108864,262401
DD 67371264,256,1,262144
DD 257,262145,67371008,67109121
DD 0,67371264,262400,67371009
DD 262145,67108864,67371265,1
DD 262401,67108865,67108864,67371265
DD 262144,67109120,67109121,262400
DD 67109120,0,67371009,257
DD 67108865,262401,256,67371008
DD 4198408,268439552,8,272633864
DD 0,272629760,268439560,4194312
DD 272633856,268435464,268435456,4104
DD 268435464,4198408,4194304,268435456
DD 272629768,4198400,4096,8
DD 4198400,268439560,272629760,4096
DD 4104,0,4194312,272633856
DD 268439552,272629768,272633864,4194304
DD 272629768,4104,4194304,268435464
DD 4198400,268439552,8,272629760
DD 268439560,0,4096,4194312
DD 0,272629768,272633856,4096
DD 268435456,272633864,4198408,4194304
DD 272633864,8,268439552,4198408
DD 4194312,4198400,272629760,268439560
DD 4104,268435456,268435464,272633856
DD 134217728,65536,1024,134284320
DD 134283296,134218752,66592,134283264
DD 65536,32,134217760,66560
DD 134218784,134283296,134284288,0
DD 66560,134217728,65568,1056
DD 134218752,66592,0,134217760
DD 32,134218784,134284320,65568
DD 134283264,1024,1056,134284288
DD 134284288,134218784,65568,134283264
DD 65536,32,134217760,134218752
DD 134217728,66560,134284320,0
DD 66592,134217728,1024,65568
DD 134218784,1024,0,134284320
DD 134283296,134284288,1056,65536
DD 66560,134283296,134218752,1056
DD 32,66592,134283264,134217760
DD 2147483712,2097216,0,2149588992
DD 2097216,8192,2147491904,2097152
DD 8256,2149589056,2105344,2147483648
DD 2147491840,2147483712,2149580800,2105408
DD 2097152,2147491904,2149580864,0
DD 8192,64,2149588992,2149580864
DD 2149589056,2149580800,2147483648,8256
DD 64,2105344,2105408,2147491840
DD 8256,2147483648,2147491840,2105408
DD 2149588992,2097216,0,2147491840
DD 2147483648,8192,2149580864,2097152
DD 2097216,2149589056,2105344,64
DD 2149589056,2105344,2097152,2147491904
DD 2147483712,2149580800,2105408,0
DD 8192,2147483712,2147491904,2149588992
DD 2149580800,8256,64,2149580864
DD 16384,512,16777728,16777220
DD 16794116,16388,16896,0
DD 16777216,16777732,516,16793600
DD 4,16794112,16793600,516
DD 16777732,16384,16388,16794116
DD 0,16777728,16777220,16896
DD 16793604,16900,16794112,4
DD 16900,16793604,512,16777216
DD 16900,16793600,16793604,516
DD 16384,512,16777216,16793604
DD 16777732,16900,16896,0
DD 512,16777220,4,16777728
DD 0,16777732,16777728,16896
DD 516,16384,16794116,16777216
DD 16794112,4,16388,16794116
DD 16777220,16794112,16793600,16388
DD 545259648,545390592,131200,0
DD 537001984,8388736,545259520,545390720
DD 128,536870912,8519680,131200
DD 8519808,537002112,536871040,545259520
DD 131072,8519808,8388736,537001984
DD 545390720,536871040,0,8519680
DD 536870912,8388608,537002112,545259648
DD 8388608,131072,545390592,128
DD 8388608,131072,536871040,545390720
DD 131200,536870912,0,8519680
DD 545259648,537002112,537001984,8388736
DD 545390592,128,8388736,537001984
DD 545390720,8388608,545259520,536871040
DD 8519680,131200,537002112,545259520
DD 128,545390592,8519808,0
DD 536870912,545259648,131072,8519808
.text$ ENDS
END
| jdgarcia/nodegit | vendor/openssl/asm_obsolete/x86-win32-masm/des/des-586.asm | Assembly | mit | 36,688 |
[bits 64]
mov ah, 5 ; out: b4 05
mov ax, 5 ; out: 66 b8 05 00
mov eax, 5 ; out: b8 05 00 00 00
mov rax, 5 ; out: 48 c7 c0 05 00 00 00 - optimized to signed 32-bit form
mov rax, dword 5 ; out: 48 c7 c0 05 00 00 00 - explicitly 32-bit
mov rax, qword 5 ; out: 48 b8 05 00 00 00 00 00 00 00 - explicitly 64-bit
; test sign optimization cases
mov rax, 0x7fffffff ; out: 48 c7 c0 ff ff ff 7f
mov rax, dword 0x7fffffff ; out: 48 c7 c0 ff ff ff 7f
mov rax, qword 0x7fffffff ; out: 48 b8 ff ff ff 7f 00 00 00 00
mov rax, 0x80000000 ; out: 48 b8 00 00 00 80 00 00 00 00
mov rax, dword 0x80000000 ; out: 48 c7 c0 00 00 00 80 [warning]
mov rax, qword 0x80000000 ; out: 48 b8 00 00 00 80 00 00 00 00
mov rax, -0x80000000 ; out: 48 c7 c0 00 00 00 80
mov rax, dword -0x80000000 ; out: 48 c7 c0 00 00 00 80
mov rax, qword -0x80000000 ; out: 48 b8 00 00 00 80 ff ff ff ff
mov rax, 0x100000000 ; out: 48 b8 00 00 00 00 01 00 00 00
mov rax, dword 0x100000000 ; out: 48 c7 c0 00 00 00 00 [warning]
mov rax, qword 0x100000000 ; out: 48 b8 00 00 00 00 01 00 00 00
mov ah, bl ; out: 88 dc
mov bl, r8b ; out: 44 88 c3
mov sil, r9b ; out: 44 88 ce
mov r10w, r11w ; out: 66 45 89 da
mov r15d, r12d ; out: 45 89 e7
mov r13, r14 ; out: 4d 89 f5
inc ebx ; out: ff c3
dec ecx ; out: ff c9
| 13xforever/x86-assembly-textmate-bundle | Tests/yasm-regression/nomem64.asm | Assembly | mit | 1,288 |
; reported by Busy
DEVICE ZXSPECTRUM48
org #4000
disp #10000-this1+zac1
zac1
nop
this1
ENT
org #4000+this1-zac1
disp #0000
nop
ENT
; test the warnings about cropping invalid ORG and DISP arguments
ORG -1
DISP -2
ENT
; no device mode
DEVICE NONE
org #4000
disp #10000-this2+zac2
zac2
nop
this2
ENT
org #4000+this2-zac2
disp #0000
nop
ENT
; test the warnings about cropping invalid ORG and DISP arguments
ORG -1
DISP -2
ENT
| z00m128/sjasmplus | tests/devices/Issue144_disp_crash.asm | Assembly | bsd-3-clause | 453 |
%define ARCH_ALPHA 0
%define ARCH_ARM 0
%define ARCH_AVR32 0
%define ARCH_AVR32_AP 0
%define ARCH_AVR32_UC 0
%define ARCH_BFIN 0
%define ARCH_IA64 0
%define ARCH_M68K 0
%define ARCH_MIPS 0
%define ARCH_MIPS64 0
%define ARCH_PARISC 0
%define ARCH_PPC 0
%define ARCH_PPC64 0
%define ARCH_S390 0
%define ARCH_SH4 0
%define ARCH_SPARC 0
%define ARCH_SPARC64 0
%define ARCH_TOMI 0
%define ARCH_X86 1
%define ARCH_X86_32 1
%define ARCH_X86_64 0
%define HAVE_AMD3DNOW 1
%define HAVE_AMD3DNOWEXT 1
%define HAVE_AVX 1
%define HAVE_FMA4 1
%define HAVE_MMX 1
%define HAVE_MMXEXT 1
%define HAVE_SSE 1
%define HAVE_SSE2 1
%define HAVE_SSE3 1
%define HAVE_SSE4 1
%define HAVE_SSE42 1
%define HAVE_SSSE3 1
%define HAVE_ALTIVEC 0
%define HAVE_ARMV5TE 0
%define HAVE_ARMV6 0
%define HAVE_ARMV6T2 0
%define HAVE_ARMVFP 0
%define HAVE_MMI 0
%define HAVE_NEON 0
%define HAVE_PPC4XX 0
%define HAVE_VFPV3 0
%define HAVE_VIS 0
%define HAVE_MIPSFPU 0
%define HAVE_MIPS32R2 0
%define HAVE_MIPSDSPR1 0
%define HAVE_MIPSDSPR2 0
%define HAVE_AMD3DNOW_EXTERNAL 1
%define HAVE_AMD3DNOWEXT_EXTERNAL 1
%define HAVE_AVX_EXTERNAL 1
%define HAVE_FMA4_EXTERNAL 1
%define HAVE_MMX_EXTERNAL 1
%define HAVE_MMXEXT_EXTERNAL 1
%define HAVE_SSE_EXTERNAL 1
%define HAVE_SSE2_EXTERNAL 1
%define HAVE_SSE3_EXTERNAL 1
%define HAVE_SSE4_EXTERNAL 1
%define HAVE_SSE42_EXTERNAL 1
%define HAVE_SSSE3_EXTERNAL 1
%define HAVE_ALTIVEC_EXTERNAL 0
%define HAVE_ARMV5TE_EXTERNAL 0
%define HAVE_ARMV6_EXTERNAL 0
%define HAVE_ARMV6T2_EXTERNAL 0
%define HAVE_ARMVFP_EXTERNAL 0
%define HAVE_MMI_EXTERNAL 0
%define HAVE_NEON_EXTERNAL 0
%define HAVE_PPC4XX_EXTERNAL 0
%define HAVE_VFPV3_EXTERNAL 0
%define HAVE_VIS_EXTERNAL 0
%define HAVE_MIPSFPU_EXTERNAL 0
%define HAVE_MIPS32R2_EXTERNAL 0
%define HAVE_MIPSDSPR1_EXTERNAL 0
%define HAVE_MIPSDSPR2_EXTERNAL 0
%define HAVE_AMD3DNOW_INLINE 1
%define HAVE_AMD3DNOWEXT_INLINE 1
%define HAVE_AVX_INLINE 1
%define HAVE_FMA4_INLINE 1
%define HAVE_MMX_INLINE 1
%define HAVE_MMXEXT_INLINE 1
%define HAVE_SSE_INLINE 1
%define HAVE_SSE2_INLINE 1
%define HAVE_SSE3_INLINE 1
%define HAVE_SSE4_INLINE 1
%define HAVE_SSE42_INLINE 1
%define HAVE_SSSE3_INLINE 1
%define HAVE_ALTIVEC_INLINE 0
%define HAVE_ARMV5TE_INLINE 0
%define HAVE_ARMV6_INLINE 0
%define HAVE_ARMV6T2_INLINE 0
%define HAVE_ARMVFP_INLINE 0
%define HAVE_MMI_INLINE 0
%define HAVE_NEON_INLINE 0
%define HAVE_PPC4XX_INLINE 0
%define HAVE_VFPV3_INLINE 0
%define HAVE_VIS_INLINE 0
%define HAVE_MIPSFPU_INLINE 0
%define HAVE_MIPS32R2_INLINE 0
%define HAVE_MIPSDSPR1_INLINE 0
%define HAVE_MIPSDSPR2_INLINE 0
%define HAVE_BIGENDIAN 0
%define HAVE_FAST_UNALIGNED 1
%define HAVE_INCOMPATIBLE_FORK_ABI 0
%define HAVE_PTHREADS 1
%define HAVE_W32THREADS 0
%define HAVE_OS2THREADS 0
%define HAVE_ALIGNED_MALLOC 0
%define HAVE_ALIGNED_STACK 1
%define HAVE_ALSA_ASOUNDLIB_H 0
%define HAVE_ALTIVEC_H 0
%define HAVE_ARPA_INET_H 0
%define HAVE_ASM_MOD_Q 0
%define HAVE_ASM_MOD_Y 0
%define HAVE_ASM_TYPES_H 0
%define HAVE_ATTRIBUTE_MAY_ALIAS 1
%define HAVE_ATTRIBUTE_PACKED 1
%define HAVE_BROKEN_SNPRINTF 0
%define HAVE_CBRTF 1
%define HAVE_CLOCK_GETTIME 0
%define HAVE_CLOSESOCKET 0
%define HAVE_CMOV 0
%define HAVE_CPUID 0
%define HAVE_CPUNOP 1
%define HAVE_DCBZL 0
%define HAVE_DEV_BKTR_IOCTL_BT848_H 0
%define HAVE_DEV_BKTR_IOCTL_METEOR_H 0
%define HAVE_DEV_IC_BT8XX_H 0
%define HAVE_DEV_VIDEO_BKTR_IOCTL_BT848_H 0
%define HAVE_DEV_VIDEO_METEOR_IOCTL_METEOR_H 0
%define HAVE_DIRECT_H 0
%define HAVE_DLFCN_H 1
%define HAVE_DLOPEN 1
%define HAVE_DOS_PATHS 0
%define HAVE_DXVA_H 0
%define HAVE_EBP_AVAILABLE 0
%define HAVE_EBX_AVAILABLE 1
%define HAVE_EXP2 1
%define HAVE_EXP2F 1
%define HAVE_FAST_64BIT 0
%define HAVE_FAST_CLZ 1
%define HAVE_FAST_CMOV 0
%define HAVE_FCNTL 1
%define HAVE_FORK 1
%define HAVE_GETADDRINFO 0
%define HAVE_GETHRTIME 0
%define HAVE_GETOPT 1
%define HAVE_GETPROCESSAFFINITYMASK 0
%define HAVE_GETPROCESSMEMORYINFO 0
%define HAVE_GETPROCESSTIMES 0
%define HAVE_GETSYSTEMTIMEASFILETIME 0
%define HAVE_GETRUSAGE 1
%define HAVE_GETTIMEOFDAY 1
%define HAVE_GLOB 1
%define HAVE_GNU_AS 0
%define HAVE_IBM_ASM 0
%define HAVE_INET_ATON 1
%define HAVE_INLINE_ASM 1
%define HAVE_IO_H 0
%define HAVE_ISATTY 1
%define HAVE_ISINF 1
%define HAVE_ISNAN 1
%define HAVE_JACK_PORT_GET_LATENCY_RANGE 0
%define HAVE_KBHIT 0
%define HAVE_LDBRX 0
%define HAVE_LIBDC1394_1 0
%define HAVE_LIBDC1394_2 0
%define HAVE_LLRINT 1
%define HAVE_LLRINTF 1
%define HAVE_LOCAL_ALIGNED_16 1
%define HAVE_LOCAL_ALIGNED_8 1
%define HAVE_LOCALTIME_R 1
%define HAVE_LOG2 1
%define HAVE_LOG2F 1
%define HAVE_LOONGSON 0
%define HAVE_LRINT 1
%define HAVE_LRINTF 1
%define HAVE_LZO1X_999_COMPRESS 0
%define HAVE_MACHINE_IOCTL_BT848_H 0
%define HAVE_MACHINE_IOCTL_METEOR_H 0
%define HAVE_MAKEINFO 1
%define HAVE_MALLOC_H 0
%define HAVE_MAPVIEWOFFILE 0
%define HAVE_MEMALIGN 0
%define HAVE_MKSTEMP 1
%define HAVE_MM_EMPTY 1
%define HAVE_MMAP 1
%define HAVE_MSVCRT 0
%define HAVE_NANOSLEEP 1
%define HAVE_PEEKNAMEDPIPE 0
%define HAVE_PERL 1
%define HAVE_POD2MAN 1
%define HAVE_POLL_H 1
%define HAVE_POSIX_MEMALIGN 1
%define HAVE_PTHREAD_CANCEL 1
%define HAVE_RDTSC 0
%define HAVE_RINT 1
%define HAVE_ROUND 1
%define HAVE_ROUNDF 1
%define HAVE_RWEFLAGS 0
%define HAVE_SCHED_GETAFFINITY 0
%define HAVE_SDL 0
%define HAVE_SDL_VIDEO_SIZE 0
%define HAVE_SETMODE 0
%define HAVE_SETRLIMIT 1
%define HAVE_SLEEP 0
%define HAVE_SNDIO_H 0
%define HAVE_SOCKLEN_T 0
%define HAVE_SOUNDCARD_H 0
%define HAVE_STRERROR_R 1
%define HAVE_STRUCT_ADDRINFO 0
%define HAVE_STRUCT_GROUP_SOURCE_REQ 0
%define HAVE_STRUCT_IP_MREQ_SOURCE 0
%define HAVE_STRUCT_IPV6_MREQ 0
%define HAVE_STRUCT_POLLFD 0
%define HAVE_STRUCT_RUSAGE_RU_MAXRSS 1
%define HAVE_STRUCT_SCTP_EVENT_SUBSCRIBE 0
%define HAVE_STRUCT_SOCKADDR_IN6 0
%define HAVE_STRUCT_SOCKADDR_SA_LEN 0
%define HAVE_STRUCT_SOCKADDR_STORAGE 0
%define HAVE_STRUCT_V4L2_FRMIVALENUM_DISCRETE 0
%define HAVE_SYMVER 0
%define HAVE_SYMVER_ASM_LABEL 0
%define HAVE_SYMVER_GNU_ASM 0
%define HAVE_SYSCONF 1
%define HAVE_SYSCTL 1
%define HAVE_SYS_MMAN_H 1
%define HAVE_SYS_PARAM_H 1
%define HAVE_SYS_RESOURCE_H 1
%define HAVE_SYS_SELECT_H 1
%define HAVE_SYS_SOUNDCARD_H 0
%define HAVE_SYS_TIME_H 1
%define HAVE_SYS_VIDEOIO_H 0
%define HAVE_TERMIOS_H 1
%define HAVE_TEXI2HTML 0
%define HAVE_THREADS 1
%define HAVE_TRUNC 1
%define HAVE_TRUNCF 1
%define HAVE_UNISTD_H 1
%define HAVE_USLEEP 1
%define HAVE_VFP_ARGS 0
%define HAVE_VIRTUALALLOC 0
%define HAVE_WINDOWS_H 0
%define HAVE_WINSOCK2_H 0
%define HAVE_XFORM_ASM 0
%define HAVE_XGETBV 0
%define HAVE_XMM_CLOBBERS 1
%define HAVE_YASM 1
%define CONFIG_BSFS 0
%define CONFIG_DECODERS 1
%define CONFIG_DEMUXERS 1
%define CONFIG_ENCODERS 0
%define CONFIG_FILTERS 0
%define CONFIG_HWACCELS 0
%define CONFIG_INDEVS 0
%define CONFIG_MUXERS 0
%define CONFIG_OUTDEVS 0
%define CONFIG_PARSERS 1
%define CONFIG_PROTOCOLS 0
%define CONFIG_DOC 0
%define CONFIG_HTMLPAGES 0
%define CONFIG_MANPAGES 1
%define CONFIG_PODPAGES 1
%define CONFIG_TXTPAGES 1
%define CONFIG_FFPLAY 0
%define CONFIG_FFPROBE 1
%define CONFIG_FFSERVER 0
%define CONFIG_FFMPEG 0
%define CONFIG_AVCODEC 1
%define CONFIG_AVDEVICE 0
%define CONFIG_AVFILTER 0
%define CONFIG_AVFORMAT 1
%define CONFIG_AVRESAMPLE 0
%define CONFIG_AVISYNTH 0
%define CONFIG_BZLIB 0
%define CONFIG_CRYSTALHD 0
%define CONFIG_DCT 0
%define CONFIG_DWT 0
%define CONFIG_DXVA2 0
%define CONFIG_FAST_UNALIGNED 1
%define CONFIG_FFT 1
%define CONFIG_FONTCONFIG 0
%define CONFIG_FREI0R 0
%define CONFIG_GNUTLS 0
%define CONFIG_GPL 0
%define CONFIG_GRAY 0
%define CONFIG_HARDCODED_TABLES 0
%define CONFIG_INCOMPATIBLE_FORK_ABI 0
%define CONFIG_LIBAACPLUS 0
%define CONFIG_LIBASS 0
%define CONFIG_LIBBLURAY 0
%define CONFIG_LIBCACA 0
%define CONFIG_LIBCDIO 0
%define CONFIG_LIBCELT 0
%define CONFIG_LIBDC1394 0
%define CONFIG_LIBFAAC 0
%define CONFIG_LIBFDK_AAC 0
%define CONFIG_LIBFLITE 0
%define CONFIG_LIBFREETYPE 0
%define CONFIG_LIBGSM 0
%define CONFIG_LIBIEC61883 0
%define CONFIG_LIBILBC 0
%define CONFIG_LIBMODPLUG 0
%define CONFIG_LIBMP3LAME 0
%define CONFIG_LIBNUT 0
%define CONFIG_LIBOPENCORE_AMRNB 0
%define CONFIG_LIBOPENCORE_AMRWB 0
%define CONFIG_LIBOPENCV 0
%define CONFIG_LIBOPENJPEG 0
%define CONFIG_LIBOPUS 0
%define CONFIG_LIBPULSE 0
%define CONFIG_LIBRTMP 0
%define CONFIG_LIBSCHROEDINGER 0
%define CONFIG_LIBSPEEX 0
%define CONFIG_LIBSTAGEFRIGHT_H264 0
%define CONFIG_LIBTHEORA 0
%define CONFIG_LIBTWOLAME 0
%define CONFIG_LIBUTVIDEO 0
%define CONFIG_LIBV4L2 0
%define CONFIG_LIBVO_AACENC 0
%define CONFIG_LIBVO_AMRWBENC 0
%define CONFIG_LIBVORBIS 0
%define CONFIG_LIBVPX 0
%define CONFIG_LIBX264 0
%define CONFIG_LIBXAVS 0
%define CONFIG_LIBXVID 0
%define CONFIG_LSP 0
%define CONFIG_MDCT 1
%define CONFIG_MEMALIGN_HACK 0
%define CONFIG_MEMORY_POISONING 0
%define CONFIG_NETWORK 0
%define CONFIG_NONFREE 0
%define CONFIG_OPENAL 0
%define CONFIG_OPENSSL 0
%define CONFIG_PIC 1
%define CONFIG_POSTPROC 0
%define CONFIG_RDFT 1
%define CONFIG_RUNTIME_CPUDETECT 1
%define CONFIG_SAFE_BITSTREAM_READER 1
%define CONFIG_SHARED 1
%define CONFIG_SMALL 0
%define CONFIG_SRAM 0
%define CONFIG_STATIC 1
%define CONFIG_SWRESAMPLE 0
%define CONFIG_SWSCALE 0
%define CONFIG_SWSCALE_ALPHA 1
%define CONFIG_THUMB 0
%define CONFIG_VAAPI 0
%define CONFIG_VDA 0
%define CONFIG_VDPAU 0
%define CONFIG_VERSION3 0
%define CONFIG_XMM_CLOBBER_TEST 0
%define CONFIG_X11GRAB 0
%define CONFIG_ZLIB 0
%define CONFIG_AANDCTTABLES 0
%define CONFIG_AC3DSP 0
%define CONFIG_AVUTIL 1
%define CONFIG_ERROR_RESILIENCE 0
%define CONFIG_GCRYPT 0
%define CONFIG_GOLOMB 1
%define CONFIG_GPLV3 0
%define CONFIG_H264CHROMA 0
%define CONFIG_H264DSP 0
%define CONFIG_H264PRED 1
%define CONFIG_H264QPEL 1
%define CONFIG_HUFFMAN 0
%define CONFIG_LGPLV3 0
%define CONFIG_LPC 0
%define CONFIG_MPEGAUDIODSP 0
%define CONFIG_MPEGVIDEO 0
%define CONFIG_MPEGVIDEOENC 0
%define CONFIG_NETTLE 0
%define CONFIG_RANGECODER 0
%define CONFIG_RTPDEC 0
%define CONFIG_SINEWIN 0
%define CONFIG_VP3DSP 1
%define CONFIG_AAC_ADTSTOASC_BSF 0
%define CONFIG_CHOMP_BSF 0
%define CONFIG_DUMP_EXTRADATA_BSF 0
%define CONFIG_H264_MP4TOANNEXB_BSF 0
%define CONFIG_IMX_DUMP_HEADER_BSF 0
%define CONFIG_MJPEG2JPEG_BSF 0
%define CONFIG_MJPEGA_DUMP_HEADER_BSF 0
%define CONFIG_MP3_HEADER_COMPRESS_BSF 0
%define CONFIG_MP3_HEADER_DECOMPRESS_BSF 0
%define CONFIG_MOV2TEXTSUB_BSF 0
%define CONFIG_NOISE_BSF 0
%define CONFIG_REMOVE_EXTRADATA_BSF 0
%define CONFIG_TEXT2MOVSUB_BSF 0
%define CONFIG_AASC_DECODER 0
%define CONFIG_AMV_DECODER 0
%define CONFIG_ANM_DECODER 0
%define CONFIG_ANSI_DECODER 0
%define CONFIG_ASV1_DECODER 0
%define CONFIG_ASV2_DECODER 0
%define CONFIG_AURA_DECODER 0
%define CONFIG_AURA2_DECODER 0
%define CONFIG_AVRP_DECODER 0
%define CONFIG_AVRN_DECODER 0
%define CONFIG_AVS_DECODER 0
%define CONFIG_AVUI_DECODER 0
%define CONFIG_AYUV_DECODER 0
%define CONFIG_BETHSOFTVID_DECODER 0
%define CONFIG_BFI_DECODER 0
%define CONFIG_BINK_DECODER 0
%define CONFIG_BMP_DECODER 0
%define CONFIG_BMV_VIDEO_DECODER 0
%define CONFIG_C93_DECODER 0
%define CONFIG_CAVS_DECODER 0
%define CONFIG_CDGRAPHICS_DECODER 0
%define CONFIG_CDXL_DECODER 0
%define CONFIG_CINEPAK_DECODER 0
%define CONFIG_CLJR_DECODER 0
%define CONFIG_CLLC_DECODER 0
%define CONFIG_CPIA_DECODER 0
%define CONFIG_CSCD_DECODER 0
%define CONFIG_CYUV_DECODER 0
%define CONFIG_DFA_DECODER 0
%define CONFIG_DIRAC_DECODER 0
%define CONFIG_DNXHD_DECODER 0
%define CONFIG_DPX_DECODER 0
%define CONFIG_DSICINVIDEO_DECODER 0
%define CONFIG_DVVIDEO_DECODER 0
%define CONFIG_DXA_DECODER 0
%define CONFIG_DXTORY_DECODER 0
%define CONFIG_EACMV_DECODER 0
%define CONFIG_EAMAD_DECODER 0
%define CONFIG_EATGQ_DECODER 0
%define CONFIG_EATGV_DECODER 0
%define CONFIG_EATQI_DECODER 0
%define CONFIG_EIGHTBPS_DECODER 0
%define CONFIG_EIGHTSVX_EXP_DECODER 0
%define CONFIG_EIGHTSVX_FIB_DECODER 0
%define CONFIG_ESCAPE124_DECODER 0
%define CONFIG_ESCAPE130_DECODER 0
%define CONFIG_EXR_DECODER 0
%define CONFIG_FFV1_DECODER 0
%define CONFIG_FFVHUFF_DECODER 0
%define CONFIG_FLASHSV_DECODER 0
%define CONFIG_FLASHSV2_DECODER 0
%define CONFIG_FLIC_DECODER 0
%define CONFIG_FLV_DECODER 0
%define CONFIG_FOURXM_DECODER 0
%define CONFIG_FRAPS_DECODER 0
%define CONFIG_FRWU_DECODER 0
%define CONFIG_GIF_DECODER 0
%define CONFIG_H261_DECODER 0
%define CONFIG_H263_DECODER 0
%define CONFIG_H263I_DECODER 0
%define CONFIG_H263P_DECODER 0
%define CONFIG_H264_DECODER 0
%define CONFIG_H264_CRYSTALHD_DECODER 0
%define CONFIG_H264_VDA_DECODER 0
%define CONFIG_H264_VDPAU_DECODER 0
%define CONFIG_HUFFYUV_DECODER 0
%define CONFIG_IDCIN_DECODER 0
%define CONFIG_IFF_BYTERUN1_DECODER 0
%define CONFIG_IFF_ILBM_DECODER 0
%define CONFIG_INDEO2_DECODER 0
%define CONFIG_INDEO3_DECODER 0
%define CONFIG_INDEO4_DECODER 0
%define CONFIG_INDEO5_DECODER 0
%define CONFIG_INTERPLAY_VIDEO_DECODER 0
%define CONFIG_JPEG2000_DECODER 0
%define CONFIG_JPEGLS_DECODER 0
%define CONFIG_JV_DECODER 0
%define CONFIG_KGV1_DECODER 0
%define CONFIG_KMVC_DECODER 0
%define CONFIG_LAGARITH_DECODER 0
%define CONFIG_LOCO_DECODER 0
%define CONFIG_MDEC_DECODER 0
%define CONFIG_MIMIC_DECODER 0
%define CONFIG_MJPEG_DECODER 0
%define CONFIG_MJPEGB_DECODER 0
%define CONFIG_MMVIDEO_DECODER 0
%define CONFIG_MOTIONPIXELS_DECODER 0
%define CONFIG_MPEG_XVMC_DECODER 0
%define CONFIG_MPEG1VIDEO_DECODER 0
%define CONFIG_MPEG2VIDEO_DECODER 0
%define CONFIG_MPEG4_DECODER 0
%define CONFIG_MPEG4_CRYSTALHD_DECODER 0
%define CONFIG_MPEG4_VDPAU_DECODER 0
%define CONFIG_MPEGVIDEO_DECODER 0
%define CONFIG_MPEG_VDPAU_DECODER 0
%define CONFIG_MPEG1_VDPAU_DECODER 0
%define CONFIG_MPEG2_CRYSTALHD_DECODER 0
%define CONFIG_MSA1_DECODER 0
%define CONFIG_MSMPEG4_CRYSTALHD_DECODER 0
%define CONFIG_MSMPEG4V1_DECODER 0
%define CONFIG_MSMPEG4V2_DECODER 0
%define CONFIG_MSMPEG4V3_DECODER 0
%define CONFIG_MSRLE_DECODER 0
%define CONFIG_MSS1_DECODER 0
%define CONFIG_MSS2_DECODER 0
%define CONFIG_MSVIDEO1_DECODER 0
%define CONFIG_MSZH_DECODER 0
%define CONFIG_MTS2_DECODER 0
%define CONFIG_MXPEG_DECODER 0
%define CONFIG_NUV_DECODER 0
%define CONFIG_PAF_VIDEO_DECODER 0
%define CONFIG_PAM_DECODER 0
%define CONFIG_PBM_DECODER 0
%define CONFIG_PCX_DECODER 0
%define CONFIG_PGM_DECODER 0
%define CONFIG_PGMYUV_DECODER 0
%define CONFIG_PICTOR_DECODER 0
%define CONFIG_PNG_DECODER 0
%define CONFIG_PPM_DECODER 0
%define CONFIG_PRORES_DECODER 0
%define CONFIG_PRORES_LGPL_DECODER 0
%define CONFIG_PTX_DECODER 0
%define CONFIG_QDRAW_DECODER 0
%define CONFIG_QPEG_DECODER 0
%define CONFIG_QTRLE_DECODER 0
%define CONFIG_R10K_DECODER 0
%define CONFIG_R210_DECODER 0
%define CONFIG_RAWVIDEO_DECODER 0
%define CONFIG_RL2_DECODER 0
%define CONFIG_ROQ_DECODER 0
%define CONFIG_RPZA_DECODER 0
%define CONFIG_RV10_DECODER 0
%define CONFIG_RV20_DECODER 0
%define CONFIG_RV30_DECODER 0
%define CONFIG_RV40_DECODER 0
%define CONFIG_S302M_DECODER 0
%define CONFIG_SANM_DECODER 0
%define CONFIG_SGI_DECODER 0
%define CONFIG_SMACKER_DECODER 0
%define CONFIG_SMC_DECODER 0
%define CONFIG_SNOW_DECODER 0
%define CONFIG_SP5X_DECODER 0
%define CONFIG_SUNRAST_DECODER 0
%define CONFIG_SVQ1_DECODER 0
%define CONFIG_SVQ3_DECODER 0
%define CONFIG_TARGA_DECODER 0
%define CONFIG_THEORA_DECODER 1
%define CONFIG_THP_DECODER 0
%define CONFIG_TIERTEXSEQVIDEO_DECODER 0
%define CONFIG_TIFF_DECODER 0
%define CONFIG_TMV_DECODER 0
%define CONFIG_TRUEMOTION1_DECODER 0
%define CONFIG_TRUEMOTION2_DECODER 0
%define CONFIG_TSCC_DECODER 0
%define CONFIG_TSCC2_DECODER 0
%define CONFIG_TXD_DECODER 0
%define CONFIG_ULTI_DECODER 0
%define CONFIG_UTVIDEO_DECODER 0
%define CONFIG_V210_DECODER 0
%define CONFIG_V210X_DECODER 0
%define CONFIG_V308_DECODER 0
%define CONFIG_V408_DECODER 0
%define CONFIG_V410_DECODER 0
%define CONFIG_VB_DECODER 0
%define CONFIG_VBLE_DECODER 0
%define CONFIG_VC1_DECODER 0
%define CONFIG_VC1_CRYSTALHD_DECODER 0
%define CONFIG_VC1_VDPAU_DECODER 0
%define CONFIG_VC1IMAGE_DECODER 0
%define CONFIG_VCR1_DECODER 0
%define CONFIG_VMDVIDEO_DECODER 0
%define CONFIG_VMNC_DECODER 0
%define CONFIG_VP3_DECODER 1
%define CONFIG_VP5_DECODER 0
%define CONFIG_VP6_DECODER 0
%define CONFIG_VP6A_DECODER 0
%define CONFIG_VP6F_DECODER 0
%define CONFIG_VP8_DECODER 1
%define CONFIG_VQA_DECODER 0
%define CONFIG_WMV1_DECODER 0
%define CONFIG_WMV2_DECODER 0
%define CONFIG_WMV3_DECODER 0
%define CONFIG_WMV3_CRYSTALHD_DECODER 0
%define CONFIG_WMV3_VDPAU_DECODER 0
%define CONFIG_WMV3IMAGE_DECODER 0
%define CONFIG_WNV1_DECODER 0
%define CONFIG_XAN_WC3_DECODER 0
%define CONFIG_XAN_WC4_DECODER 0
%define CONFIG_XBM_DECODER 0
%define CONFIG_XL_DECODER 0
%define CONFIG_XWD_DECODER 0
%define CONFIG_Y41P_DECODER 0
%define CONFIG_YOP_DECODER 0
%define CONFIG_YUV4_DECODER 0
%define CONFIG_ZEROCODEC_DECODER 0
%define CONFIG_ZLIB_DECODER 0
%define CONFIG_ZMBV_DECODER 0
%define CONFIG_AAC_DECODER 0
%define CONFIG_AAC_LATM_DECODER 0
%define CONFIG_AC3_DECODER 0
%define CONFIG_ALAC_DECODER 0
%define CONFIG_ALS_DECODER 0
%define CONFIG_AMRNB_DECODER 0
%define CONFIG_AMRWB_DECODER 0
%define CONFIG_APE_DECODER 0
%define CONFIG_ATRAC1_DECODER 0
%define CONFIG_ATRAC3_DECODER 0
%define CONFIG_BINKAUDIO_DCT_DECODER 0
%define CONFIG_BINKAUDIO_RDFT_DECODER 0
%define CONFIG_BMV_AUDIO_DECODER 0
%define CONFIG_COOK_DECODER 0
%define CONFIG_DCA_DECODER 0
%define CONFIG_DSICINAUDIO_DECODER 0
%define CONFIG_EAC3_DECODER 0
%define CONFIG_FFWAVESYNTH_DECODER 0
%define CONFIG_FLAC_DECODER 0
%define CONFIG_G723_1_DECODER 0
%define CONFIG_G729_DECODER 0
%define CONFIG_GSM_DECODER 0
%define CONFIG_GSM_MS_DECODER 0
%define CONFIG_IAC_DECODER 0
%define CONFIG_IMC_DECODER 0
%define CONFIG_MACE3_DECODER 0
%define CONFIG_MACE6_DECODER 0
%define CONFIG_MLP_DECODER 0
%define CONFIG_MP1_DECODER 0
%define CONFIG_MP1FLOAT_DECODER 0
%define CONFIG_MP2_DECODER 0
%define CONFIG_MP2FLOAT_DECODER 0
%define CONFIG_MP3_DECODER 0
%define CONFIG_MP3FLOAT_DECODER 0
%define CONFIG_MP3ADU_DECODER 0
%define CONFIG_MP3ADUFLOAT_DECODER 0
%define CONFIG_MP3ON4_DECODER 0
%define CONFIG_MP3ON4FLOAT_DECODER 0
%define CONFIG_MPC7_DECODER 0
%define CONFIG_MPC8_DECODER 0
%define CONFIG_NELLYMOSER_DECODER 0
%define CONFIG_PAF_AUDIO_DECODER 0
%define CONFIG_QCELP_DECODER 0
%define CONFIG_QDM2_DECODER 0
%define CONFIG_RA_144_DECODER 0
%define CONFIG_RA_288_DECODER 0
%define CONFIG_RALF_DECODER 0
%define CONFIG_SHORTEN_DECODER 0
%define CONFIG_SIPR_DECODER 0
%define CONFIG_SMACKAUD_DECODER 0
%define CONFIG_SONIC_DECODER 0
%define CONFIG_TRUEHD_DECODER 0
%define CONFIG_TRUESPEECH_DECODER 0
%define CONFIG_TTA_DECODER 0
%define CONFIG_TWINVQ_DECODER 0
%define CONFIG_VMDAUDIO_DECODER 0
%define CONFIG_VORBIS_DECODER 1
%define CONFIG_WAVPACK_DECODER 0
%define CONFIG_WMALOSSLESS_DECODER 0
%define CONFIG_WMAPRO_DECODER 0
%define CONFIG_WMAV1_DECODER 0
%define CONFIG_WMAV2_DECODER 0
%define CONFIG_WMAVOICE_DECODER 0
%define CONFIG_WS_SND1_DECODER 0
%define CONFIG_PCM_ALAW_DECODER 0
%define CONFIG_PCM_BLURAY_DECODER 0
%define CONFIG_PCM_DVD_DECODER 0
%define CONFIG_PCM_F32BE_DECODER 0
%define CONFIG_PCM_F32LE_DECODER 1
%define CONFIG_PCM_F64BE_DECODER 0
%define CONFIG_PCM_F64LE_DECODER 0
%define CONFIG_PCM_LXF_DECODER 0
%define CONFIG_PCM_MULAW_DECODER 0
%define CONFIG_PCM_S8_DECODER 0
%define CONFIG_PCM_S8_PLANAR_DECODER 0
%define CONFIG_PCM_S16BE_DECODER 1
%define CONFIG_PCM_S16LE_DECODER 1
%define CONFIG_PCM_S16LE_PLANAR_DECODER 0
%define CONFIG_PCM_S24BE_DECODER 1
%define CONFIG_PCM_S24DAUD_DECODER 0
%define CONFIG_PCM_S24LE_DECODER 1
%define CONFIG_PCM_S32BE_DECODER 0
%define CONFIG_PCM_S32LE_DECODER 0
%define CONFIG_PCM_U8_DECODER 1
%define CONFIG_PCM_U16BE_DECODER 0
%define CONFIG_PCM_U16LE_DECODER 0
%define CONFIG_PCM_U24BE_DECODER 0
%define CONFIG_PCM_U24LE_DECODER 0
%define CONFIG_PCM_U32BE_DECODER 0
%define CONFIG_PCM_U32LE_DECODER 0
%define CONFIG_PCM_ZORK_DECODER 0
%define CONFIG_INTERPLAY_DPCM_DECODER 0
%define CONFIG_ROQ_DPCM_DECODER 0
%define CONFIG_SOL_DPCM_DECODER 0
%define CONFIG_XAN_DPCM_DECODER 0
%define CONFIG_ADPCM_4XM_DECODER 0
%define CONFIG_ADPCM_ADX_DECODER 0
%define CONFIG_ADPCM_CT_DECODER 0
%define CONFIG_ADPCM_EA_DECODER 0
%define CONFIG_ADPCM_EA_MAXIS_XA_DECODER 0
%define CONFIG_ADPCM_EA_R1_DECODER 0
%define CONFIG_ADPCM_EA_R2_DECODER 0
%define CONFIG_ADPCM_EA_R3_DECODER 0
%define CONFIG_ADPCM_EA_XAS_DECODER 0
%define CONFIG_ADPCM_G722_DECODER 0
%define CONFIG_ADPCM_G726_DECODER 0
%define CONFIG_ADPCM_IMA_AMV_DECODER 0
%define CONFIG_ADPCM_IMA_APC_DECODER 0
%define CONFIG_ADPCM_IMA_DK3_DECODER 0
%define CONFIG_ADPCM_IMA_DK4_DECODER 0
%define CONFIG_ADPCM_IMA_EA_EACS_DECODER 0
%define CONFIG_ADPCM_IMA_EA_SEAD_DECODER 0
%define CONFIG_ADPCM_IMA_ISS_DECODER 0
%define CONFIG_ADPCM_IMA_QT_DECODER 0
%define CONFIG_ADPCM_IMA_SMJPEG_DECODER 0
%define CONFIG_ADPCM_IMA_WAV_DECODER 0
%define CONFIG_ADPCM_IMA_WS_DECODER 0
%define CONFIG_ADPCM_MS_DECODER 0
%define CONFIG_ADPCM_SBPRO_2_DECODER 0
%define CONFIG_ADPCM_SBPRO_3_DECODER 0
%define CONFIG_ADPCM_SBPRO_4_DECODER 0
%define CONFIG_ADPCM_SWF_DECODER 0
%define CONFIG_ADPCM_THP_DECODER 0
%define CONFIG_ADPCM_XA_DECODER 0
%define CONFIG_ADPCM_YAMAHA_DECODER 0
%define CONFIG_VIMA_DECODER 0
%define CONFIG_ASS_DECODER 0
%define CONFIG_DVBSUB_DECODER 0
%define CONFIG_DVDSUB_DECODER 0
%define CONFIG_JACOSUB_DECODER 0
%define CONFIG_MICRODVD_DECODER 0
%define CONFIG_MOVTEXT_DECODER 0
%define CONFIG_PGSSUB_DECODER 0
%define CONFIG_REALTEXT_DECODER 0
%define CONFIG_SAMI_DECODER 0
%define CONFIG_SRT_DECODER 0
%define CONFIG_SUBRIP_DECODER 0
%define CONFIG_SUBVIEWER_DECODER 0
%define CONFIG_WEBVTT_DECODER 0
%define CONFIG_XSUB_DECODER 0
%define CONFIG_LIBCELT_DECODER 0
%define CONFIG_LIBGSM_DECODER 0
%define CONFIG_LIBGSM_MS_DECODER 0
%define CONFIG_LIBILBC_DECODER 0
%define CONFIG_LIBOPENCORE_AMRNB_DECODER 0
%define CONFIG_LIBOPENCORE_AMRWB_DECODER 0
%define CONFIG_LIBOPENJPEG_DECODER 0
%define CONFIG_LIBOPUS_DECODER 0
%define CONFIG_LIBSCHROEDINGER_DECODER 0
%define CONFIG_LIBSPEEX_DECODER 0
%define CONFIG_LIBSTAGEFRIGHT_H264_DECODER 0
%define CONFIG_LIBUTVIDEO_DECODER 0
%define CONFIG_LIBVORBIS_DECODER 0
%define CONFIG_LIBVPX_DECODER 0
%define CONFIG_BINTEXT_DECODER 0
%define CONFIG_XBIN_DECODER 0
%define CONFIG_IDF_DECODER 0
%define CONFIG_AAC_DEMUXER 0
%define CONFIG_AC3_DEMUXER 0
%define CONFIG_ACT_DEMUXER 0
%define CONFIG_ADF_DEMUXER 0
%define CONFIG_ADX_DEMUXER 0
%define CONFIG_AEA_DEMUXER 0
%define CONFIG_AIFF_DEMUXER 0
%define CONFIG_AMR_DEMUXER 0
%define CONFIG_ANM_DEMUXER 0
%define CONFIG_APC_DEMUXER 0
%define CONFIG_APE_DEMUXER 0
%define CONFIG_ASF_DEMUXER 0
%define CONFIG_ASS_DEMUXER 0
%define CONFIG_AU_DEMUXER 0
%define CONFIG_AVI_DEMUXER 0
%define CONFIG_AVISYNTH_DEMUXER 0
%define CONFIG_AVS_DEMUXER 0
%define CONFIG_BETHSOFTVID_DEMUXER 0
%define CONFIG_BFI_DEMUXER 0
%define CONFIG_BINTEXT_DEMUXER 0
%define CONFIG_BINK_DEMUXER 0
%define CONFIG_BIT_DEMUXER 0
%define CONFIG_BMV_DEMUXER 0
%define CONFIG_C93_DEMUXER 0
%define CONFIG_CAF_DEMUXER 0
%define CONFIG_CAVSVIDEO_DEMUXER 0
%define CONFIG_CDG_DEMUXER 0
%define CONFIG_CDXL_DEMUXER 0
%define CONFIG_DAUD_DEMUXER 0
%define CONFIG_DFA_DEMUXER 0
%define CONFIG_DIRAC_DEMUXER 0
%define CONFIG_DNXHD_DEMUXER 0
%define CONFIG_DSICIN_DEMUXER 0
%define CONFIG_DTS_DEMUXER 0
%define CONFIG_DV_DEMUXER 0
%define CONFIG_DXA_DEMUXER 0
%define CONFIG_EA_DEMUXER 0
%define CONFIG_EA_CDATA_DEMUXER 0
%define CONFIG_EAC3_DEMUXER 0
%define CONFIG_FFM_DEMUXER 0
%define CONFIG_FFMETADATA_DEMUXER 0
%define CONFIG_FILMSTRIP_DEMUXER 0
%define CONFIG_FLAC_DEMUXER 0
%define CONFIG_FLIC_DEMUXER 0
%define CONFIG_FLV_DEMUXER 0
%define CONFIG_FOURXM_DEMUXER 0
%define CONFIG_G722_DEMUXER 0
%define CONFIG_G723_1_DEMUXER 0
%define CONFIG_G729_DEMUXER 0
%define CONFIG_GSM_DEMUXER 0
%define CONFIG_GXF_DEMUXER 0
%define CONFIG_H261_DEMUXER 0
%define CONFIG_H263_DEMUXER 0
%define CONFIG_H264_DEMUXER 0
%define CONFIG_HLS_DEMUXER 0
%define CONFIG_ICO_DEMUXER 0
%define CONFIG_IDCIN_DEMUXER 0
%define CONFIG_IDF_DEMUXER 0
%define CONFIG_IFF_DEMUXER 0
%define CONFIG_ILBC_DEMUXER 0
%define CONFIG_IMAGE2_DEMUXER 0
%define CONFIG_IMAGE2PIPE_DEMUXER 0
%define CONFIG_INGENIENT_DEMUXER 0
%define CONFIG_IPMOVIE_DEMUXER 0
%define CONFIG_ISS_DEMUXER 0
%define CONFIG_IV8_DEMUXER 0
%define CONFIG_IVF_DEMUXER 0
%define CONFIG_JACOSUB_DEMUXER 0
%define CONFIG_JV_DEMUXER 0
%define CONFIG_LATM_DEMUXER 0
%define CONFIG_LMLM4_DEMUXER 0
%define CONFIG_LOAS_DEMUXER 0
%define CONFIG_LXF_DEMUXER 0
%define CONFIG_M4V_DEMUXER 0
%define CONFIG_MATROSKA_DEMUXER 1
%define CONFIG_MGSTS_DEMUXER 0
%define CONFIG_MICRODVD_DEMUXER 0
%define CONFIG_MJPEG_DEMUXER 0
%define CONFIG_MLP_DEMUXER 0
%define CONFIG_MM_DEMUXER 0
%define CONFIG_MMF_DEMUXER 0
%define CONFIG_MOV_DEMUXER 0
%define CONFIG_MP3_DEMUXER 0
%define CONFIG_MPC_DEMUXER 0
%define CONFIG_MPC8_DEMUXER 0
%define CONFIG_MPEGPS_DEMUXER 0
%define CONFIG_MPEGTS_DEMUXER 0
%define CONFIG_MPEGTSRAW_DEMUXER 0
%define CONFIG_MPEGVIDEO_DEMUXER 0
%define CONFIG_MSNWC_TCP_DEMUXER 0
%define CONFIG_MTV_DEMUXER 0
%define CONFIG_MVI_DEMUXER 0
%define CONFIG_MXF_DEMUXER 0
%define CONFIG_MXG_DEMUXER 0
%define CONFIG_NC_DEMUXER 0
%define CONFIG_NSV_DEMUXER 0
%define CONFIG_NUT_DEMUXER 0
%define CONFIG_NUV_DEMUXER 0
%define CONFIG_OGG_DEMUXER 1
%define CONFIG_OMA_DEMUXER 0
%define CONFIG_PAF_DEMUXER 0
%define CONFIG_PCM_ALAW_DEMUXER 0
%define CONFIG_PCM_MULAW_DEMUXER 0
%define CONFIG_PCM_F64BE_DEMUXER 0
%define CONFIG_PCM_F64LE_DEMUXER 0
%define CONFIG_PCM_F32BE_DEMUXER 0
%define CONFIG_PCM_F32LE_DEMUXER 0
%define CONFIG_PCM_S32BE_DEMUXER 0
%define CONFIG_PCM_S32LE_DEMUXER 0
%define CONFIG_PCM_S24BE_DEMUXER 0
%define CONFIG_PCM_S24LE_DEMUXER 0
%define CONFIG_PCM_S16BE_DEMUXER 0
%define CONFIG_PCM_S16LE_DEMUXER 0
%define CONFIG_PCM_S8_DEMUXER 0
%define CONFIG_PCM_U32BE_DEMUXER 0
%define CONFIG_PCM_U32LE_DEMUXER 0
%define CONFIG_PCM_U24BE_DEMUXER 0
%define CONFIG_PCM_U24LE_DEMUXER 0
%define CONFIG_PCM_U16BE_DEMUXER 0
%define CONFIG_PCM_U16LE_DEMUXER 0
%define CONFIG_PCM_U8_DEMUXER 0
%define CONFIG_PMP_DEMUXER 0
%define CONFIG_PVA_DEMUXER 0
%define CONFIG_QCP_DEMUXER 0
%define CONFIG_R3D_DEMUXER 0
%define CONFIG_RAWVIDEO_DEMUXER 0
%define CONFIG_REALTEXT_DEMUXER 0
%define CONFIG_RL2_DEMUXER 0
%define CONFIG_RM_DEMUXER 0
%define CONFIG_ROQ_DEMUXER 0
%define CONFIG_RPL_DEMUXER 0
%define CONFIG_RSO_DEMUXER 0
%define CONFIG_RTP_DEMUXER 0
%define CONFIG_RTSP_DEMUXER 0
%define CONFIG_SAMI_DEMUXER 0
%define CONFIG_SAP_DEMUXER 0
%define CONFIG_SBG_DEMUXER 0
%define CONFIG_SDP_DEMUXER 0
%define CONFIG_SEGAFILM_DEMUXER 0
%define CONFIG_SHORTEN_DEMUXER 0
%define CONFIG_SIFF_DEMUXER 0
%define CONFIG_SMACKER_DEMUXER 0
%define CONFIG_SMJPEG_DEMUXER 0
%define CONFIG_SMUSH_DEMUXER 0
%define CONFIG_SOL_DEMUXER 0
%define CONFIG_SOX_DEMUXER 0
%define CONFIG_SPDIF_DEMUXER 0
%define CONFIG_SRT_DEMUXER 0
%define CONFIG_STR_DEMUXER 0
%define CONFIG_SUBVIEWER_DEMUXER 0
%define CONFIG_SWF_DEMUXER 0
%define CONFIG_THP_DEMUXER 0
%define CONFIG_TIERTEXSEQ_DEMUXER 0
%define CONFIG_TMV_DEMUXER 0
%define CONFIG_TRUEHD_DEMUXER 0
%define CONFIG_TTA_DEMUXER 0
%define CONFIG_TXD_DEMUXER 0
%define CONFIG_TTY_DEMUXER 0
%define CONFIG_VC1_DEMUXER 0
%define CONFIG_VC1T_DEMUXER 0
%define CONFIG_VMD_DEMUXER 0
%define CONFIG_VOC_DEMUXER 0
%define CONFIG_VQF_DEMUXER 0
%define CONFIG_W64_DEMUXER 0
%define CONFIG_WAV_DEMUXER 1
%define CONFIG_WC3_DEMUXER 0
%define CONFIG_WEBVTT_DEMUXER 0
%define CONFIG_WSAUD_DEMUXER 0
%define CONFIG_WSVQA_DEMUXER 0
%define CONFIG_WTV_DEMUXER 0
%define CONFIG_WV_DEMUXER 0
%define CONFIG_XA_DEMUXER 0
%define CONFIG_XBIN_DEMUXER 0
%define CONFIG_XMV_DEMUXER 0
%define CONFIG_XWMA_DEMUXER 0
%define CONFIG_YOP_DEMUXER 0
%define CONFIG_YUV4MPEGPIPE_DEMUXER 0
%define CONFIG_LIBMODPLUG_DEMUXER 0
%define CONFIG_LIBNUT_DEMUXER 0
%define CONFIG_A64MULTI_ENCODER 0
%define CONFIG_A64MULTI5_ENCODER 0
%define CONFIG_AMV_ENCODER 0
%define CONFIG_ASV1_ENCODER 0
%define CONFIG_ASV2_ENCODER 0
%define CONFIG_AVRP_ENCODER 0
%define CONFIG_AVUI_ENCODER 0
%define CONFIG_AYUV_ENCODER 0
%define CONFIG_BMP_ENCODER 0
%define CONFIG_CLJR_ENCODER 0
%define CONFIG_DNXHD_ENCODER 0
%define CONFIG_DPX_ENCODER 0
%define CONFIG_DVVIDEO_ENCODER 0
%define CONFIG_FFV1_ENCODER 0
%define CONFIG_FFVHUFF_ENCODER 0
%define CONFIG_FLASHSV_ENCODER 0
%define CONFIG_FLASHSV2_ENCODER 0
%define CONFIG_FLV_ENCODER 0
%define CONFIG_GIF_ENCODER 0
%define CONFIG_H261_ENCODER 0
%define CONFIG_H263_ENCODER 0
%define CONFIG_H263P_ENCODER 0
%define CONFIG_HUFFYUV_ENCODER 0
%define CONFIG_JPEG2000_ENCODER 0
%define CONFIG_JPEGLS_ENCODER 0
%define CONFIG_LJPEG_ENCODER 0
%define CONFIG_MJPEG_ENCODER 0
%define CONFIG_MPEG1VIDEO_ENCODER 0
%define CONFIG_MPEG2VIDEO_ENCODER 0
%define CONFIG_MPEG4_ENCODER 0
%define CONFIG_MSMPEG4V2_ENCODER 0
%define CONFIG_MSMPEG4V3_ENCODER 0
%define CONFIG_MSVIDEO1_ENCODER 0
%define CONFIG_PAM_ENCODER 0
%define CONFIG_PBM_ENCODER 0
%define CONFIG_PCX_ENCODER 0
%define CONFIG_PGM_ENCODER 0
%define CONFIG_PGMYUV_ENCODER 0
%define CONFIG_PNG_ENCODER 0
%define CONFIG_PPM_ENCODER 0
%define CONFIG_PRORES_ENCODER 0
%define CONFIG_PRORES_ANATOLIY_ENCODER 0
%define CONFIG_PRORES_KOSTYA_ENCODER 0
%define CONFIG_QTRLE_ENCODER 0
%define CONFIG_R10K_ENCODER 0
%define CONFIG_R210_ENCODER 0
%define CONFIG_RAWVIDEO_ENCODER 0
%define CONFIG_ROQ_ENCODER 0
%define CONFIG_RV10_ENCODER 0
%define CONFIG_RV20_ENCODER 0
%define CONFIG_SGI_ENCODER 0
%define CONFIG_SNOW_ENCODER 0
%define CONFIG_SUNRAST_ENCODER 0
%define CONFIG_SVQ1_ENCODER 0
%define CONFIG_TARGA_ENCODER 0
%define CONFIG_TIFF_ENCODER 0
%define CONFIG_UTVIDEO_ENCODER 0
%define CONFIG_V210_ENCODER 0
%define CONFIG_V308_ENCODER 0
%define CONFIG_V408_ENCODER 0
%define CONFIG_V410_ENCODER 0
%define CONFIG_WMV1_ENCODER 0
%define CONFIG_WMV2_ENCODER 0
%define CONFIG_XBM_ENCODER 0
%define CONFIG_XWD_ENCODER 0
%define CONFIG_Y41P_ENCODER 0
%define CONFIG_YUV4_ENCODER 0
%define CONFIG_ZLIB_ENCODER 0
%define CONFIG_ZMBV_ENCODER 0
%define CONFIG_AAC_ENCODER 0
%define CONFIG_AC3_ENCODER 0
%define CONFIG_AC3_FIXED_ENCODER 0
%define CONFIG_ALAC_ENCODER 0
%define CONFIG_DCA_ENCODER 0
%define CONFIG_EAC3_ENCODER 0
%define CONFIG_FLAC_ENCODER 0
%define CONFIG_G723_1_ENCODER 0
%define CONFIG_MP2_ENCODER 0
%define CONFIG_NELLYMOSER_ENCODER 0
%define CONFIG_RA_144_ENCODER 0
%define CONFIG_SONIC_ENCODER 0
%define CONFIG_SONIC_LS_ENCODER 0
%define CONFIG_VORBIS_ENCODER 0
%define CONFIG_WMAV1_ENCODER 0
%define CONFIG_WMAV2_ENCODER 0
%define CONFIG_PCM_ALAW_ENCODER 0
%define CONFIG_PCM_F32BE_ENCODER 0
%define CONFIG_PCM_F32LE_ENCODER 0
%define CONFIG_PCM_F64BE_ENCODER 0
%define CONFIG_PCM_F64LE_ENCODER 0
%define CONFIG_PCM_MULAW_ENCODER 0
%define CONFIG_PCM_S8_ENCODER 0
%define CONFIG_PCM_S16BE_ENCODER 0
%define CONFIG_PCM_S16LE_ENCODER 0
%define CONFIG_PCM_S24BE_ENCODER 0
%define CONFIG_PCM_S24DAUD_ENCODER 0
%define CONFIG_PCM_S24LE_ENCODER 0
%define CONFIG_PCM_S32BE_ENCODER 0
%define CONFIG_PCM_S32LE_ENCODER 0
%define CONFIG_PCM_U8_ENCODER 0
%define CONFIG_PCM_U16BE_ENCODER 0
%define CONFIG_PCM_U16LE_ENCODER 0
%define CONFIG_PCM_U24BE_ENCODER 0
%define CONFIG_PCM_U24LE_ENCODER 0
%define CONFIG_PCM_U32BE_ENCODER 0
%define CONFIG_PCM_U32LE_ENCODER 0
%define CONFIG_ROQ_DPCM_ENCODER 0
%define CONFIG_ADPCM_ADX_ENCODER 0
%define CONFIG_ADPCM_G722_ENCODER 0
%define CONFIG_ADPCM_G726_ENCODER 0
%define CONFIG_ADPCM_IMA_QT_ENCODER 0
%define CONFIG_ADPCM_IMA_WAV_ENCODER 0
%define CONFIG_ADPCM_MS_ENCODER 0
%define CONFIG_ADPCM_SWF_ENCODER 0
%define CONFIG_ADPCM_YAMAHA_ENCODER 0
%define CONFIG_ASS_ENCODER 0
%define CONFIG_DVBSUB_ENCODER 0
%define CONFIG_DVDSUB_ENCODER 0
%define CONFIG_MOVTEXT_ENCODER 0
%define CONFIG_SRT_ENCODER 0
%define CONFIG_SUBRIP_ENCODER 0
%define CONFIG_XSUB_ENCODER 0
%define CONFIG_LIBFAAC_ENCODER 0
%define CONFIG_LIBFDK_AAC_ENCODER 0
%define CONFIG_LIBGSM_ENCODER 0
%define CONFIG_LIBGSM_MS_ENCODER 0
%define CONFIG_LIBILBC_ENCODER 0
%define CONFIG_LIBMP3LAME_ENCODER 0
%define CONFIG_LIBOPENCORE_AMRNB_ENCODER 0
%define CONFIG_LIBOPENJPEG_ENCODER 0
%define CONFIG_LIBSCHROEDINGER_ENCODER 0
%define CONFIG_LIBSPEEX_ENCODER 0
%define CONFIG_LIBTHEORA_ENCODER 0
%define CONFIG_LIBTWOLAME_ENCODER 0
%define CONFIG_LIBUTVIDEO_ENCODER 0
%define CONFIG_LIBVO_AACENC_ENCODER 0
%define CONFIG_LIBVO_AMRWBENC_ENCODER 0
%define CONFIG_LIBVORBIS_ENCODER 0
%define CONFIG_LIBVPX_ENCODER 0
%define CONFIG_LIBX264_ENCODER 0
%define CONFIG_LIBX264RGB_ENCODER 0
%define CONFIG_LIBXAVS_ENCODER 0
%define CONFIG_LIBXVID_ENCODER 0
%define CONFIG_LIBAACPLUS_ENCODER 0
%define CONFIG_ACONVERT_FILTER 0
%define CONFIG_AFIFO_FILTER 0
%define CONFIG_AFORMAT_FILTER 0
%define CONFIG_AMERGE_FILTER 0
%define CONFIG_AMIX_FILTER 0
%define CONFIG_ANULL_FILTER 0
%define CONFIG_ARESAMPLE_FILTER 0
%define CONFIG_ASENDCMD_FILTER 0
%define CONFIG_ASETNSAMPLES_FILTER 0
%define CONFIG_ASETPTS_FILTER 0
%define CONFIG_ASETTB_FILTER 0
%define CONFIG_ASHOWINFO_FILTER 0
%define CONFIG_ASPLIT_FILTER 0
%define CONFIG_ASTREAMSYNC_FILTER 0
%define CONFIG_ASYNCTS_FILTER 0
%define CONFIG_ATEMPO_FILTER 0
%define CONFIG_CHANNELMAP_FILTER 0
%define CONFIG_CHANNELSPLIT_FILTER 0
%define CONFIG_EARWAX_FILTER 0
%define CONFIG_JOIN_FILTER 0
%define CONFIG_PAN_FILTER 0
%define CONFIG_SILENCEDETECT_FILTER 0
%define CONFIG_VOLUME_FILTER 0
%define CONFIG_VOLUMEDETECT_FILTER 0
%define CONFIG_RESAMPLE_FILTER 0
%define CONFIG_AEVALSRC_FILTER 0
%define CONFIG_ANULLSRC_FILTER 0
%define CONFIG_FLITE_FILTER 0
%define CONFIG_ANULLSINK_FILTER 0
%define CONFIG_ALPHAEXTRACT_FILTER 0
%define CONFIG_ALPHAMERGE_FILTER 0
%define CONFIG_ASS_FILTER 0
%define CONFIG_BBOX_FILTER 0
%define CONFIG_BLACKDETECT_FILTER 0
%define CONFIG_BLACKFRAME_FILTER 0
%define CONFIG_BOXBLUR_FILTER 0
%define CONFIG_COLORMATRIX_FILTER 0
%define CONFIG_COPY_FILTER 0
%define CONFIG_CROP_FILTER 0
%define CONFIG_CROPDETECT_FILTER 0
%define CONFIG_DECIMATE_FILTER 0
%define CONFIG_DELOGO_FILTER 0
%define CONFIG_DESHAKE_FILTER 0
%define CONFIG_DRAWBOX_FILTER 0
%define CONFIG_DRAWTEXT_FILTER 0
%define CONFIG_EDGEDETECT_FILTER 0
%define CONFIG_FADE_FILTER 0
%define CONFIG_FIELDORDER_FILTER 0
%define CONFIG_FIFO_FILTER 0
%define CONFIG_FORMAT_FILTER 0
%define CONFIG_FPS_FILTER 0
%define CONFIG_FRAMESTEP_FILTER 0
%define CONFIG_FREI0R_FILTER 0
%define CONFIG_GRADFUN_FILTER 0
%define CONFIG_HFLIP_FILTER 0
%define CONFIG_HQDN3D_FILTER 0
%define CONFIG_HUE_FILTER 0
%define CONFIG_IDET_FILTER 0
%define CONFIG_LUT_FILTER 0
%define CONFIG_LUTRGB_FILTER 0
%define CONFIG_LUTYUV_FILTER 0
%define CONFIG_MP_FILTER 0
%define CONFIG_NEGATE_FILTER 0
%define CONFIG_NOFORMAT_FILTER 0
%define CONFIG_NULL_FILTER 0
%define CONFIG_OCV_FILTER 0
%define CONFIG_OVERLAY_FILTER 0
%define CONFIG_PAD_FILTER 0
%define CONFIG_PIXDESCTEST_FILTER 0
%define CONFIG_REMOVELOGO_FILTER 0
%define CONFIG_SCALE_FILTER 0
%define CONFIG_SELECT_FILTER 0
%define CONFIG_SENDCMD_FILTER 0
%define CONFIG_SETDAR_FILTER 0
%define CONFIG_SETFIELD_FILTER 0
%define CONFIG_SETPTS_FILTER 0
%define CONFIG_SETSAR_FILTER 0
%define CONFIG_SETTB_FILTER 0
%define CONFIG_SHOWINFO_FILTER 0
%define CONFIG_SLICIFY_FILTER 0
%define CONFIG_SMARTBLUR_FILTER 0
%define CONFIG_SPLIT_FILTER 0
%define CONFIG_SUPER2XSAI_FILTER 0
%define CONFIG_SWAPUV_FILTER 0
%define CONFIG_THUMBNAIL_FILTER 0
%define CONFIG_TILE_FILTER 0
%define CONFIG_TINTERLACE_FILTER 0
%define CONFIG_TRANSPOSE_FILTER 0
%define CONFIG_UNSHARP_FILTER 0
%define CONFIG_VFLIP_FILTER 0
%define CONFIG_YADIF_FILTER 0
%define CONFIG_CELLAUTO_FILTER 0
%define CONFIG_COLOR_FILTER 0
%define CONFIG_FREI0R_SRC_FILTER 0
%define CONFIG_LIFE_FILTER 0
%define CONFIG_MANDELBROT_FILTER 0
%define CONFIG_MPTESTSRC_FILTER 0
%define CONFIG_NULLSRC_FILTER 0
%define CONFIG_RGBTESTSRC_FILTER 0
%define CONFIG_SMPTEBARS_FILTER 0
%define CONFIG_TESTSRC_FILTER 0
%define CONFIG_NULLSINK_FILTER 0
%define CONFIG_CONCAT_FILTER 0
%define CONFIG_SHOWSPECTRUM_FILTER 0
%define CONFIG_SHOWWAVES_FILTER 0
%define CONFIG_AMOVIE_FILTER 0
%define CONFIG_MOVIE_FILTER 0
%define CONFIG_VSINK_FILTER 0
%define CONFIG_ASINK_FILTER 0
%define CONFIG_VSINK_FILTER 0
%define CONFIG_ASINK_FILTER 0
%define CONFIG_H263_VAAPI_HWACCEL 0
%define CONFIG_H264_DXVA2_HWACCEL 0
%define CONFIG_H264_VAAPI_HWACCEL 0
%define CONFIG_H264_VDA_HWACCEL 0
%define CONFIG_MPEG1_VDPAU_HWACCEL 0
%define CONFIG_MPEG2_DXVA2_HWACCEL 0
%define CONFIG_MPEG2_VAAPI_HWACCEL 0
%define CONFIG_MPEG2_VDPAU_HWACCEL 0
%define CONFIG_MPEG4_VAAPI_HWACCEL 0
%define CONFIG_VC1_DXVA2_HWACCEL 0
%define CONFIG_VC1_VAAPI_HWACCEL 0
%define CONFIG_WMV3_DXVA2_HWACCEL 0
%define CONFIG_WMV3_VAAPI_HWACCEL 0
%define CONFIG_ALSA_INDEV 0
%define CONFIG_BKTR_INDEV 0
%define CONFIG_DSHOW_INDEV 0
%define CONFIG_DV1394_INDEV 0
%define CONFIG_FBDEV_INDEV 0
%define CONFIG_IEC61883_INDEV 0
%define CONFIG_JACK_INDEV 0
%define CONFIG_LAVFI_INDEV 0
%define CONFIG_OPENAL_INDEV 0
%define CONFIG_OSS_INDEV 0
%define CONFIG_PULSE_INDEV 0
%define CONFIG_SNDIO_INDEV 0
%define CONFIG_V4L2_INDEV 0
%define CONFIG_VFWCAP_INDEV 0
%define CONFIG_X11GRAB_INDEV 0
%define CONFIG_LIBCDIO_INDEV 0
%define CONFIG_LIBDC1394_INDEV 0
%define CONFIG_A64_MUXER 0
%define CONFIG_AC3_MUXER 0
%define CONFIG_ADTS_MUXER 0
%define CONFIG_ADX_MUXER 0
%define CONFIG_AIFF_MUXER 0
%define CONFIG_AMR_MUXER 0
%define CONFIG_ASF_MUXER 0
%define CONFIG_ASS_MUXER 0
%define CONFIG_ASF_STREAM_MUXER 0
%define CONFIG_AU_MUXER 0
%define CONFIG_AVI_MUXER 0
%define CONFIG_AVM2_MUXER 0
%define CONFIG_BIT_MUXER 0
%define CONFIG_CAF_MUXER 0
%define CONFIG_CAVSVIDEO_MUXER 0
%define CONFIG_CRC_MUXER 0
%define CONFIG_DAUD_MUXER 0
%define CONFIG_DIRAC_MUXER 0
%define CONFIG_DNXHD_MUXER 0
%define CONFIG_DTS_MUXER 0
%define CONFIG_DV_MUXER 0
%define CONFIG_EAC3_MUXER 0
%define CONFIG_F4V_MUXER 0
%define CONFIG_FFM_MUXER 0
%define CONFIG_FFMETADATA_MUXER 0
%define CONFIG_FILMSTRIP_MUXER 0
%define CONFIG_FLAC_MUXER 0
%define CONFIG_FLV_MUXER 0
%define CONFIG_FRAMECRC_MUXER 0
%define CONFIG_FRAMEMD5_MUXER 0
%define CONFIG_G722_MUXER 0
%define CONFIG_G723_1_MUXER 0
%define CONFIG_GIF_MUXER 0
%define CONFIG_GXF_MUXER 0
%define CONFIG_H261_MUXER 0
%define CONFIG_H263_MUXER 0
%define CONFIG_H264_MUXER 0
%define CONFIG_ICO_MUXER 0
%define CONFIG_ILBC_MUXER 0
%define CONFIG_IMAGE2_MUXER 0
%define CONFIG_IMAGE2PIPE_MUXER 0
%define CONFIG_IPOD_MUXER 0
%define CONFIG_ISMV_MUXER 0
%define CONFIG_IVF_MUXER 0
%define CONFIG_JACOSUB_MUXER 0
%define CONFIG_LATM_MUXER 0
%define CONFIG_M4V_MUXER 0
%define CONFIG_MD5_MUXER 0
%define CONFIG_MATROSKA_MUXER 0
%define CONFIG_MATROSKA_AUDIO_MUXER 0
%define CONFIG_MICRODVD_MUXER 0
%define CONFIG_MJPEG_MUXER 0
%define CONFIG_MLP_MUXER 0
%define CONFIG_MMF_MUXER 0
%define CONFIG_MOV_MUXER 0
%define CONFIG_MP2_MUXER 0
%define CONFIG_MP3_MUXER 0
%define CONFIG_MP4_MUXER 0
%define CONFIG_MPEG1SYSTEM_MUXER 0
%define CONFIG_MPEG1VCD_MUXER 0
%define CONFIG_MPEG1VIDEO_MUXER 0
%define CONFIG_MPEG2DVD_MUXER 0
%define CONFIG_MPEG2SVCD_MUXER 0
%define CONFIG_MPEG2VIDEO_MUXER 0
%define CONFIG_MPEG2VOB_MUXER 0
%define CONFIG_MPEGTS_MUXER 0
%define CONFIG_MPJPEG_MUXER 0
%define CONFIG_MXF_MUXER 0
%define CONFIG_MXF_D10_MUXER 0
%define CONFIG_NULL_MUXER 0
%define CONFIG_NUT_MUXER 0
%define CONFIG_OGG_MUXER 0
%define CONFIG_OMA_MUXER 0
%define CONFIG_PCM_ALAW_MUXER 0
%define CONFIG_PCM_MULAW_MUXER 0
%define CONFIG_PCM_F64BE_MUXER 0
%define CONFIG_PCM_F64LE_MUXER 0
%define CONFIG_PCM_F32BE_MUXER 0
%define CONFIG_PCM_F32LE_MUXER 0
%define CONFIG_PCM_S32BE_MUXER 0
%define CONFIG_PCM_S32LE_MUXER 0
%define CONFIG_PCM_S24BE_MUXER 0
%define CONFIG_PCM_S24LE_MUXER 0
%define CONFIG_PCM_S16BE_MUXER 0
%define CONFIG_PCM_S16LE_MUXER 0
%define CONFIG_PCM_S8_MUXER 0
%define CONFIG_PCM_U32BE_MUXER 0
%define CONFIG_PCM_U32LE_MUXER 0
%define CONFIG_PCM_U24BE_MUXER 0
%define CONFIG_PCM_U24LE_MUXER 0
%define CONFIG_PCM_U16BE_MUXER 0
%define CONFIG_PCM_U16LE_MUXER 0
%define CONFIG_PCM_U8_MUXER 0
%define CONFIG_PSP_MUXER 0
%define CONFIG_RAWVIDEO_MUXER 0
%define CONFIG_RM_MUXER 0
%define CONFIG_ROQ_MUXER 0
%define CONFIG_RSO_MUXER 0
%define CONFIG_RTP_MUXER 0
%define CONFIG_RTSP_MUXER 0
%define CONFIG_SAP_MUXER 0
%define CONFIG_SEGMENT_MUXER 0
%define CONFIG_STREAM_SEGMENT_MUXER 0
%define CONFIG_SMJPEG_MUXER 0
%define CONFIG_SMOOTHSTREAMING_MUXER 0
%define CONFIG_SOX_MUXER 0
%define CONFIG_SPDIF_MUXER 0
%define CONFIG_SRT_MUXER 0
%define CONFIG_SWF_MUXER 0
%define CONFIG_TG2_MUXER 0
%define CONFIG_TGP_MUXER 0
%define CONFIG_MKVTIMESTAMP_V2_MUXER 0
%define CONFIG_TRUEHD_MUXER 0
%define CONFIG_VC1T_MUXER 0
%define CONFIG_VOC_MUXER 0
%define CONFIG_WAV_MUXER 0
%define CONFIG_WEBM_MUXER 0
%define CONFIG_WTV_MUXER 0
%define CONFIG_WV_MUXER 0
%define CONFIG_YUV4MPEGPIPE_MUXER 0
%define CONFIG_LIBNUT_MUXER 0
%define CONFIG_ALSA_OUTDEV 0
%define CONFIG_CACA_OUTDEV 0
%define CONFIG_OSS_OUTDEV 0
%define CONFIG_SDL_OUTDEV 0
%define CONFIG_SNDIO_OUTDEV 0
%define CONFIG_AAC_PARSER 0
%define CONFIG_AAC_LATM_PARSER 0
%define CONFIG_AC3_PARSER 0
%define CONFIG_ADX_PARSER 0
%define CONFIG_BMP_PARSER 0
%define CONFIG_CAVSVIDEO_PARSER 0
%define CONFIG_COOK_PARSER 0
%define CONFIG_DCA_PARSER 0
%define CONFIG_DIRAC_PARSER 0
%define CONFIG_DNXHD_PARSER 0
%define CONFIG_DVBSUB_PARSER 0
%define CONFIG_DVDSUB_PARSER 0
%define CONFIG_FLAC_PARSER 0
%define CONFIG_GSM_PARSER 0
%define CONFIG_H261_PARSER 0
%define CONFIG_H263_PARSER 0
%define CONFIG_H264_PARSER 0
%define CONFIG_MJPEG_PARSER 0
%define CONFIG_MLP_PARSER 0
%define CONFIG_MPEG4VIDEO_PARSER 0
%define CONFIG_MPEGAUDIO_PARSER 0
%define CONFIG_MPEGVIDEO_PARSER 0
%define CONFIG_PNG_PARSER 0
%define CONFIG_PNM_PARSER 0
%define CONFIG_RV30_PARSER 0
%define CONFIG_RV40_PARSER 0
%define CONFIG_VC1_PARSER 0
%define CONFIG_VORBIS_PARSER 1
%define CONFIG_VP3_PARSER 1
%define CONFIG_VP8_PARSER 1
%define CONFIG_APPLEHTTP_PROTOCOL 0
%define CONFIG_BLURAY_PROTOCOL 0
%define CONFIG_CACHE_PROTOCOL 0
%define CONFIG_CONCAT_PROTOCOL 0
%define CONFIG_CRYPTO_PROTOCOL 0
%define CONFIG_FFRTMPCRYPT_PROTOCOL 0
%define CONFIG_FFRTMPHTTP_PROTOCOL 0
%define CONFIG_FILE_PROTOCOL 0
%define CONFIG_GOPHER_PROTOCOL 0
%define CONFIG_HLS_PROTOCOL 0
%define CONFIG_HTTP_PROTOCOL 0
%define CONFIG_HTTPPROXY_PROTOCOL 0
%define CONFIG_HTTPS_PROTOCOL 0
%define CONFIG_MMSH_PROTOCOL 0
%define CONFIG_MMST_PROTOCOL 0
%define CONFIG_MD5_PROTOCOL 0
%define CONFIG_PIPE_PROTOCOL 0
%define CONFIG_RTMP_PROTOCOL 0
%define CONFIG_RTMPE_PROTOCOL 0
%define CONFIG_RTMPS_PROTOCOL 0
%define CONFIG_RTMPT_PROTOCOL 0
%define CONFIG_RTMPTE_PROTOCOL 0
%define CONFIG_RTMPTS_PROTOCOL 0
%define CONFIG_RTP_PROTOCOL 0
%define CONFIG_SCTP_PROTOCOL 0
%define CONFIG_TCP_PROTOCOL 0
%define CONFIG_TLS_PROTOCOL 0
%define CONFIG_UDP_PROTOCOL 0
%define CONFIG_LIBRTMP_PROTOCOL 0
%define CONFIG_LIBRTMPE_PROTOCOL 0
%define CONFIG_LIBRTMPS_PROTOCOL 0
%define CONFIG_LIBRTMPT_PROTOCOL 0
%define CONFIG_LIBRTMPTE_PROTOCOL 0
| leighpauls/k2cro4 | third_party/ffmpeg/chromium/config/Chromium/mac/ia32/config.asm | Assembly | bsd-3-clause | 42,365 |
;- The mouse is read 4 successive times, in order to assemble the mouse data
;(horiz most-significant-nybble/horiz LSN/vert MSN/vert LSN).
;- values are deltas, and reading the mouse every VSYNC is normal
;- For vertical movement, up is positive, down is negative
;- For horizontal movement, left is positive, right is negative
;- I was not able to yield a delta value greater than 0x25 (hexadecimal)
;during a 1-VSYNC interval (I didn't try all *that* hard though). This
;should give you an idea of the sensitivity.
;
; PCE mouse driver source
;
.bss
msflag: .ds 1
msvert: .ds 1
mshorz: .ds 1
.code
;
; These stub interfaces are available from LIB1_BANK
; But the real guts are in LIB2_BANK
;
mousinit:
maplibfunc lib2_mousinit
rts
mousread:
maplibfunc lib2_mousread
rts
;
; These functions are available in bank 2 of the
; library:
;
.bank LIB2_BANK
;
; detect and initialize the mouse
;
lib2_mousinit:
lda #$20 ; reset resource-usage flag
tsb <irq_m ; to skip joystick read portion of vsync
stz joy ; clear joypad memory area
tii joy, joy+1, $4
stz joytrg ; clear joypad memory area
tii joytrg, joytrg+1, $4
stz joyold ; clear joypad memory area
tii joyold, joyold+1, $4
stz joybuf ; clear joypad memory area
tii joybuf, joybuf+1, $4
stz joy6 ; clear joypad memory area
tii joy6, joy6+1, $4
stz joytrg6 ; clear joypad memory area
tii joytrg6, joytrg6+1, $4
stz joyold6 ; clear joypad memory area
tii joyold6, joyold6+1, $4
stz joybuf6 ; clear joypad memory area
tii joybuf6, joybuf6+1, $4
stz msvert
stz mshorz
stz msflag
cla ; counter of 'good' reads (where vertical == 0)
ldx #$0A ; try 10 iterations
.loop1: pha
phx
lda #1
; jsr wait_vsync ; wait for 1 vsync frame
jsr lib2_mousread ; read mouse
plx
pla
ldy msvert ; read mouse vertical axis movement
bne .l1 ; if (val == 0), inc counter
inc a
.l1: dex
bne .loop1 ; next iteration
cmp #$00 ; if #$00 value found even once (out of 10 times)
bne .mous ; then return(1)
lda #$20 ; reset #$20 bit of $F5
trb <irq_m
cla ; bad return code
sta msflag
stz msvert
stz mshorz
rts
.mous:
lda #$20 ; reset #$20 bit of $F5
trb <irq_m
lda #$01 ; good return code
sta msflag
rts
;
; actual mechanics of reading mouse
;
lib2_mousread:
ldx #$04 ; # iterations (actually 5)
.loop1: lda joy,X ; copy 'current' value to 'previous' value
sta joyold,X
dex
bpl .loop1
stz joy ; initialize joypad #1's value
lda #$01 ; reset joypad port# to joystick #1
sta joyport
lda #$03
sta joyport
lda #$01
sta joyport
jsr delay240 ; delay 240 CPU cycles
lda joyport ; read joystick port
asl a ; upper nybble of 8-bit value - shift it
asl a
asl a
asl a
sta mshorz ; store it
jsr msbutt ; read buttons (toggle port/read other nybble)
lda #$01 ; reset joystick port again (to stick #1)
sta joyport
lda #$03
sta joyport
lda #$01
sta joyport
jsr delay14 ; wait 14 cycles to settle (reference code says 9)
lda joyport ; read port
and #$0F ; lower nybble of 8-bit value
tsb mshorz ; 'or' it into memory
bsr msbutt ; read buttons (toggle port/read other nybble)
lda #$01 ; reset joystick port again
sta joyport
lda #$03
sta joyport
lda #$01
sta joyport
jsr delay14 ; wait 14 cycles to settle (reference code says 9)
lda joyport ; read port
asl a ; upper nybble of 8-bit value - shift it
asl a
asl a
asl a
sta msvert
bsr msbutt ; read buttons (toggle port/read other nybble)
lda #$01 ; reset joystick port again
sta joyport
lda #$03
sta joyport
lda #$01
sta joyport
jsr delay14 ; wait 14 cycles to settle (reference code says 9)
lda joyport ; read port
and #$0F ; lower nybble of 8-bit value
tsb msvert ; 'or' it into value
bsr msbutt ; read buttons (toggle port/read other nybble)
lda joytrg ; check joystick buttons
cmp #$04 ; is 'select' newly-pressed ?
bne .exit
lda joy ; if so, are both run & select pressed ?
cmp #$0C
bne .exit
jmp [soft_reset] ; if yes, reboot
.exit: rts ; else return
delay240:
pha ; delay loop for 240 processor cycles
phx ; (including call/return overhead)
cla
nop
.lp: nop
inc a
cmp #21
bcc .lp
plx
pla
delay14:
rts
msbutt:
stz joyport ; toggle joystick port to read buttons
jsr delay14 ; wait 14 cycles to settle (reference code says 9)
lda joyport ; read value
eor #$FF ; change low-active to high-active
and #$0F ; only 4 bits
tsb joy ; 'or' it into value
ora joyold ; determine 'newly-pressed' buttons
eor joyold
sta joytrg ; put them into 'delta'
rts
.bank LIB1_BANK ; restore bank-context
| trapexit/chipce8 | asm/mouse.asm | Assembly | mit | 4,965 |
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