code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module OAI33D2HVT (
A1,
A2,
A3,
B1,
B2,
B3,
ZN
);
input A1, A2, A3, B1, B2, B3;
output ZN;
or (A, A1, A2, A3);
or (B, B1, B2, B3);
nand (ZN, A, B);
specify
(A1 => ZN) = (0, 0);
(A2 => ZN) = (0, 0);
(A3 => ZN) = (0, 0);
(B1 => ZN) = (0, 0);
(B2 => ZN) = (0, 0);
(B3 => ZN) = (0, 0);
endspecify
endmodule
| 6.579591 |
module OAI33D4HVT (
A1,
A2,
A3,
B1,
B2,
B3,
ZN
);
input A1, A2, A3, B1, B2, B3;
output ZN;
or (A, A1, A2, A3);
or (B, B1, B2, B3);
nand (ZN, A, B);
specify
(A1 => ZN) = (0, 0);
(A2 => ZN) = (0, 0);
(A3 => ZN) = (0, 0);
(B1 => ZN) = (0, 0);
(B2 => ZN) = (0, 0);
(B3 => ZN) = (0, 0);
endspecify
endmodule
| 6.723295 |
module OR2D0HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 6.818015 |
module OR2D1HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.093008 |
module OR2D2HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.375407 |
module OR2D4HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.088539 |
module OR2D8HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.019447 |
module OR2XD1HVT (
A1,
A2,
Z
);
input A1, A2;
output Z;
or (Z, A1, A2);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
endspecify
endmodule
| 7.419713 |
module OR3D1HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 6.774595 |
module OR3D2HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 7.168888 |
module OR3D4HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 7.225882 |
module OR3XD1HVT (
A1,
A2,
A3,
Z
);
input A1, A2, A3;
output Z;
or (Z, A1, A2, A3);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
endspecify
endmodule
| 6.725959 |
module OR4D0HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.791091 |
module OR4D1HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.98472 |
module OR4D2HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 7.161565 |
module OR4D4HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 7.116772 |
module OR4D8HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.686429 |
module OR4XD1HVT (
A1,
A2,
A3,
A4,
Z
);
input A1, A2, A3, A4;
output Z;
or (Z, A1, A2, A3, A4);
specify
(A1 => Z) = (0, 0);
(A2 => Z) = (0, 0);
(A3 => Z) = (0, 0);
(A4 => Z) = (0, 0);
endspecify
endmodule
| 6.88515 |
module cr_tcipif_dummy_bus (
bmu_tcipif_ibus_acc_deny,
bmu_tcipif_ibus_addr,
bmu_tcipif_ibus_req,
bmu_tcipif_ibus_write,
cpurst_b,
forever_cpuclk,
pad_yy_gate_clk_en_b,
tcipif_bmu_ibus_acc_err,
tcipif_bmu_ibus_data,
tcipif_bmu_ibus_data_vld,
tcipif_bmu_ibus_grnt,
tcipif_bmu_ibus_trans_cmplt
);
// &Ports; @23
input bmu_tcipif_ibus_acc_deny;
input [31:0] bmu_tcipif_ibus_addr;
input bmu_tcipif_ibus_req;
input bmu_tcipif_ibus_write;
input cpurst_b;
input forever_cpuclk;
input pad_yy_gate_clk_en_b;
output tcipif_bmu_ibus_acc_err;
output [31:0] tcipif_bmu_ibus_data;
output tcipif_bmu_ibus_data_vld;
output tcipif_bmu_ibus_grnt;
output tcipif_bmu_ibus_trans_cmplt;
// &Regs; @24
reg bus_next_state;
reg bus_state;
// &Wires; @25
wire bmu_tcipif_ibus_acc_deny;
wire bmu_tcipif_ibus_req;
wire cpurst_b;
wire forever_cpuclk;
wire ibus_acc_err;
wire ibus_busy;
wire ibus_req;
wire pad_yy_gate_clk_en_b;
wire sel_cpuclk;
wire tcipif_bmu_ibus_acc_err;
wire [31:0] tcipif_bmu_ibus_data;
wire tcipif_bmu_ibus_data_vld;
wire tcipif_bmu_ibus_grnt;
wire tcipif_bmu_ibus_trans_cmplt;
//==========================================================
// ACK to IBUS
//==========================================================
// &Force("input","bmu_tcipif_ibus_addr"); @30
// &Force("input","bmu_tcipif_ibus_write"); @31
// &Force("bus","bmu_tcipif_ibus_addr",31,0); @33
assign tcipif_bmu_ibus_grnt = bmu_tcipif_ibus_req;
assign ibus_req = bmu_tcipif_ibus_req && !bmu_tcipif_ibus_acc_deny;
parameter IDLE = 1'b0, ERROR = 1'b1;
// &Instance("gated_clk_cell", "x_tcipif_ibus_sel_clk"); @41
gated_clk_cell x_tcipif_ibus_sel_clk (
.clk_in (forever_cpuclk),
.clk_out (sel_cpuclk),
.external_en (1'b0),
.global_en (1'b1),
.local_en (bmu_tcipif_ibus_req),
.module_en (ibus_busy),
.pad_yy_gate_clk_en_b(pad_yy_gate_clk_en_b)
);
// &Connect(.clk_in (forever_cpuclk ), @42
// .external_en (1'b0 ), @43
// .global_en (1'b1 ), @44
// .module_en (ibus_busy ), @45
// .local_en (bmu_tcipif_ibus_req), @46
// .clk_out (sel_cpuclk ) @47
// ); @48
assign ibus_busy = (bus_state != IDLE);
always @(posedge sel_cpuclk or negedge cpurst_b) begin
if (!cpurst_b) bus_state <= IDLE;
else bus_state <= bus_next_state;
end
// &CombBeg; @59
always @(bus_state or ibus_req) begin
case (bus_state)
IDLE:
if (ibus_req) bus_next_state = ERROR;
else bus_next_state = IDLE;
ERROR:
if (ibus_req) bus_next_state = ERROR;
else bus_next_state = IDLE;
default: bus_next_state = IDLE;
endcase
// &CombEnd; @74
end
assign ibus_acc_err = (bus_state == ERROR);
assign tcipif_bmu_ibus_trans_cmplt = ibus_acc_err;
assign tcipif_bmu_ibus_acc_err = ibus_acc_err;
assign tcipif_bmu_ibus_data_vld = 1'b0;
assign tcipif_bmu_ibus_data[31:0] = 32'b0;
// &ModuleEnd; @85
endmodule
| 7.807747 |
module tcm_controller (
input wire clk,
input wire rstn,
input wire [$clog2(`TCM_SIZE)-1:0] addr,
input wire w_rb,
input wire [ `BUS_ACC_WIDTH-1:0] acc,
output reg [ `BUS_WIDTH-1:0] rdata,
input wire [ `BUS_WIDTH-1:0] wdata,
input wire req,
output reg resp,
output wire fault
);
// fault generation
wire invld_addr = 0;
wire invld_acc = (addr[0]==1'd1 && acc!=`BUS_ACC_1B) || (addr[1:0]==2'd2 && acc==`BUS_ACC_4B);
wire invld_wr = 0;
wire invld = |{invld_addr, invld_acc, invld_wr};
assign fault = req & invld;
// resp generation
always @(posedge clk) begin
if (~rstn) begin
resp <= 0;
end else begin
resp <= req & ~invld;
end
end
// array operations
reg [31:0] array[0:(1<<($clog2(`TCM_SIZE)-2))-1];
wire [$clog2(`TCM_SIZE)-3:0] cell_addr = addr[$clog2(`TCM_SIZE)-1:2];
wire [1:0] byte_sel[0:`BUS_ACC_CNT-1];
assign byte_sel[`BUS_ACC_1B] = addr[1:0];
assign byte_sel[`BUS_ACC_2B] = {addr[1], 1'b0};
assign byte_sel[`BUS_ACC_4B] = 2'd0;
always @(posedge clk) begin
if (req) begin
if (~w_rb) begin // read
rdata[7:0] <= array[cell_addr][{byte_sel[acc]|0, 3'd0}+:8];
rdata[15:8] <= array[cell_addr][{byte_sel[acc]|1, 3'd0}+:8];
rdata[23:16] <= array[cell_addr][{byte_sel[acc]|2, 3'd0}+:8];
rdata[31:24] <= array[cell_addr][{byte_sel[acc]|3, 3'd0}+:8];
end else begin
if (acc == `BUS_ACC_1B) begin // write 1B
array[cell_addr][{byte_sel[`BUS_ACC_1B], 3'd0}+:8] <= wdata[7:0];
end else if (acc == `BUS_ACC_2B) begin // write 2B
array[cell_addr][{byte_sel[`BUS_ACC_2B], 3'd0}+:16] <= wdata[15:0];
end else if (acc == `BUS_ACC_4B) begin // write 4B
array[cell_addr] <= wdata;
end
end
end
end
endmodule
| 6.865106 |
module tcm_mem_pmem_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [ WIDTH-1:0] ram [DEPTH-1:0];
reg [ ADDR_W-1:0] rd_ptr;
reg [ ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end else begin
// Push
if (push_i & accept_o) begin
ram[wr_ptr] <= data_in_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr <= rd_ptr + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count <= count + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count <= count - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign accept_o = (count != DEPTH);
assign valid_o = (count != 0);
/* verilator lint_on WIDTH */
assign data_out_o = ram[rd_ptr];
endmodule
| 6.878785 |
module tcm_mem_ram (
// Inputs
input clk_i
, input rst_i
, input [13:0] addr0_i
, input [31:0] data0_i
, input [ 3:0] wr0_i
, input [13:0] addr1_i
// Outputs
, output [31:0] data0_o
, output [31:0] data1_o
);
//-----------------------------------------------------------------
// Dual Port RAM 64KB
// Mode: Read First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram[8191:0] /*verilator public*/;
// reg [63:0] ram [8191:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
initial begin
$readmemh(
"D:/DOING/00-GRAD/02-proj/07-FPGA_contest/UniRISCV_221108/ubriscvOnPango/source/uart_tx_test_bin.txt",
ram);
end
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// wire [12:0] ram_addr_0;
// assign ram_addr_0 = addr0_i[12:0];
// // wire ram_sel;
// // assign ram_sel = addr0_i[0];
// wire [12:0] ram_addr_1;
// assign ram_addr_1 = addr1_i[12:0];
// Synchronous write
always @(posedge clk_i) begin
if (wr0_i[0]) ram[addr0_i][7:0] <= data0_i[7:0];
if (wr0_i[1]) ram[addr0_i][15:8] <= data0_i[15:8];
if (wr0_i[2]) ram[addr0_i][23:16] <= data0_i[23:16];
if (wr0_i[3]) ram[addr0_i][31:24] <= data0_i[31:24];
ram_read0_q <= ram[addr0_i];
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
| 7.439146 |
module tcm_mem_ram (
// Inputs
input clk0_i
, input rst0_i
, input [13:0] addr0_i
, input [31:0] data0_i
, input [ 3:0] wr0_i
, input clk1_i
, input rst1_i
, input [13:0] addr1_i
, input [31:0] data1_i
, input [ 3:0] wr1_i
// Outputs
, output [31:0] data0_o
, output [31:0] data1_o
);
//-----------------------------------------------------------------
// Dual Port RAM 64KB
// Mode: Read First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram[16383:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @(posedge clk0_i) begin
if (wr0_i[0]) ram[addr0_i][7:0] <= data0_i[7:0];
if (wr0_i[1]) ram[addr0_i][15:8] <= data0_i[15:8];
if (wr0_i[2]) ram[addr0_i][23:16] <= data0_i[23:16];
if (wr0_i[3]) ram[addr0_i][31:24] <= data0_i[31:24];
ram_read0_q <= ram[addr0_i];
end
always @(posedge clk1_i) begin
if (wr1_i[0]) ram[addr1_i][7:0] <= data1_i[7:0];
if (wr1_i[1]) ram[addr1_i][15:8] <= data1_i[15:8];
if (wr1_i[2]) ram[addr1_i][23:16] <= data1_i[23:16];
if (wr1_i[3]) ram[addr1_i][31:24] <= data1_i[31:24];
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
| 7.439146 |
module tcm_wrapper (
input wire clk,
input wire rstn,
// data bus interface
input wire [ `XLEN-1:0] d_addr, // byte addr
input wire d_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] d_acc,
output wire [ `BUS_WIDTH-1:0] d_rdata,
input wire [ `BUS_WIDTH-1:0] d_wdata,
input wire d_req,
output wire d_resp,
output wire tcm_d_fault,
// instruction bus interface
input wire [ `XLEN-1:0] i_addr, // byte addr
input wire i_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] i_acc,
output wire [ `BUS_WIDTH-1:0] i_rdata,
input wire [ `BUS_WIDTH-1:0] i_wdata,
input wire i_req,
output wire i_resp,
output wire tcm_i_fault
);
wire [ `XLEN-1:0] addr;
wire w_rb;
wire [$clog2(`BUS_ACC_CNT)-1:0] acc;
wire [ `BUS_WIDTH-1:0] rdata;
wire [ `BUS_WIDTH-1:0] wdata;
wire req;
wire resp;
wire fault;
bus_duplexer bus_duplexer (
.clk (clk),
.rstn(rstn),
.d_addr (d_addr),
.d_w_rb (d_w_rb),
.d_acc (d_acc),
.d_wdata(d_wdata),
.d_rdata(d_rdata),
.d_req (d_req),
.d_resp (d_resp),
.periph_d_fault(tcm_d_fault),
.i_addr (i_addr),
.i_w_rb (i_w_rb),
.i_acc (i_acc),
.i_wdata(i_wdata),
.i_rdata(i_rdata),
.i_req (i_req),
.i_resp (i_resp),
.periph_i_fault(tcm_i_fault),
.addr (addr),
.w_rb (w_rb),
.acc (acc),
.rdata(rdata),
.wdata(wdata),
.req (req),
.resp (resp),
.fault(fault)
);
tcm_controller tcm_controller (
.clk (clk),
.rstn(rstn),
.addr (addr[$clog2(`TCM_SIZE)-1:0]),
.w_rb (w_rb),
.acc (acc),
.rdata(rdata),
.wdata(wdata),
.req (req),
.resp (resp),
.fault(fault)
);
endmodule
| 6.955985 |
module tcon (
input wire CLK120, // 120 MHz clock
output reg CKV_, // Clock
output reg STV_, // STV[D|U]
output reg OEV_, // OE Vertical
output reg STH_, // STH[L|R]
output reg OEH_, // OE Horizontal
output wire CPH1_, // CPH
output wire CLK10_, // 10MHz clock
output reg [8:0] hdata, // HOR counter
output reg [8:0] vdata // VERT counter
// other settings : mod = 1, LR = 1, UD = 0, CPH3 = 0, CHP2 = 0
);
// Counter 0..9 for get 10 MHz
reg [3:0] cnt;
reg CLK10;
//----------------------------------
always @(posedge CLK120) begin
if (cnt == 4) CLK10 <= 1;
if (cnt == 9) begin
CLK10 <= 0;
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
end
assign CLK10_ = CLK10;
//----------------------------------
// CPH1 (10 MHz)
assign CPH1_ = CLK10;
// data counter
reg [8:0] _hdata; // HOR counter
reg [8:0] _vdata; // VERT counter
always @(posedge CLK10) begin
if (_hdata == 481) begin //481
_hdata <= 0;
if (_vdata == 240) begin //240
_vdata <= 0;
end else begin
_vdata <= _vdata + 1;
end
end else begin
_hdata <= _hdata + 1;
end
end
//----------------------------------------
// STH - first hor sync
//Start pulse for horizontal scan (Gate) line
wire _STH_ = _hdata == 0; //0
//
//Output enable input for data (Source) driver
wire _OEH_ = _hdata != 481; //481
//
// STV - end of frame - 3
wire _STV_ = _vdata == 240; //240
//
//Output enable input for scan(Gate) driver
wire _OEV_ = _hdata == 1; //1
//
//Shift clock input for scan (Gate) driver
// synchro
always @(posedge CLK10) begin
hdata <= _hdata - 1;
vdata <= _vdata - 1;
STH_ <= _STH_;
OEH_ <= _OEH_;
OEV_ <= _OEV_;
CKV_ <= _OEV_;
STV_ <= _STV_;
end
// initial values
initial begin
//cnt <= 0;
//CLK10 <= 0;
_hdata <= 0;
_vdata <= 0;
end
endmodule
| 7.756165 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/tcon_comb/tcon_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
s_pad,
t_pad,
u_pad,
v_pad,
w_pad,
x_pad,
y_pad,
z_pad,
a0_pad,
b0_pad,
c0_pad,
d0_pad,
e0_pad,
f0_pad,
g0_pad,
h0_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad, f_pad, g_pad, h_pad, i_pad,
s_pad, t_pad, u_pad, v_pad, w_pad, x_pad, y_pad, z_pad;
output a0_pad, b0_pad, c0_pad, d0_pad, e0_pad, f0_pad, g0_pad, h0_pad;
assign a0_pad = i_pad ? a_pad : s_pad;
assign b0_pad = i_pad ? b_pad : t_pad;
assign c0_pad = i_pad ? c_pad : u_pad;
assign d0_pad = i_pad ? d_pad : v_pad;
assign e0_pad = i_pad ? e_pad : w_pad;
assign f0_pad = i_pad ? f_pad : x_pad;
assign g0_pad = i_pad ? g_pad : y_pad;
assign h0_pad = i_pad ? h_pad : z_pad;
endmodule
| 6.939825 |
module Tcounter_tb ();
reg clk;
reg restn;
reg enable;
wire [3:0] Q;
Tcounter #(5) counter (
enable,
restn,
clk,
Q
);
always begin
clk = 0;
#10 clk = 1;
forever #50 clk = ~clk;
end
initial begin
restn = 0;
enable = 0;
#10 restn = 1;
enable = 1;
#400 enable = 0;
#300 enable = 1;
#800 enable = 0;
#200 enable = 1;
end
endmodule
| 7.163737 |
module tcPreset (
tcPresetEn,
presetIn,
tcAddr,
presetOut
);
input tcPresetEn;
input [`tcPresetLen-1:0] presetIn;
input [`tcAddrLen-1:0] tcAddr;
output [(`tcPresetLen*`tcNumbers)-1:0] presetOut;
reg [`tcPresetLen-1:0] presets[`tcNumbers-1:0];
always @(posedge tcPresetEn) begin
if (tcPresetEn) begin
presets[tcAddr] = presetIn;
end
end
assign presetOut[`tcPresetLen-1:0] = presets[0];
assign presetOut[(`tcPresetLen*2)-1:`tcPresetLen] = presets[1];
assign presetOut[(`tcPresetLen*3)-1:(`tcPresetLen*2)] = presets[2];
assign presetOut[(`tcPresetLen*4)-1:(`tcPresetLen*3)] = presets[3];
assign presetOut[(`tcPresetLen*5)-1:(`tcPresetLen*4)] = presets[4];
assign presetOut[(`tcPresetLen*6)-1:(`tcPresetLen*5)] = presets[5];
assign presetOut[(`tcPresetLen*7)-1:(`tcPresetLen*6)] = presets[6];
// assign presetOut[(`tcPresetLen*8)-1:(`tcPresetLen*7)] = presets[7];
// assign presetOut[(`tcPresetLen*9)-1:(`tcPresetLen*8)] = presets[8];
// assign presetOut[(`tcPresetLen*10)-1:(`tcPresetLen*9)] = presets[9];
// assign presetOut[(`tcPresetLen*11)-1:(`tcPresetLen*10)] = presets[10];
// assign presetOut[(`tcPresetLen*12)-1:(`tcPresetLen*11)] = presets[11];
// assign presetOut[(`tcPresetLen*13)-1:(`tcPresetLen*12)] = presets[12];
// assign presetOut[(`tcPresetLen*14)-1:(`tcPresetLen*13)] = presets[13];
// assign presetOut[(`tcPresetLen*15)-1:(`tcPresetLen*14)] = presets[14];
// assign presetOut[(`tcPresetLen*16)-1:(`tcPresetLen*15)] = presets[15];
endmodule
| 7.423486 |
module tcp_check #(
parameter SRC_PORT = 16'h0400,
parameter DES_PORT = 16'h00aa
) (
input clk,
input reset,
input [31:0] tcp_data_in,
input tcp_data_valid,
output reg tcp_error_out
);
localparam IDLE_s = 2'b00;
localparam HEADER_s = 2'b01;
localparam DATA_s = 2'b11;
localparam END_s = 2'b10;
reg [31:0] counter;
reg [31:0] tcp_data_buf1, tcp_data_buf2;
reg tcp_data_valid_r;
reg [15:0] length;
reg [15:0] checksum;
reg [15:0] urg_ptr;
reg [1:0] state;
reg [2:0] cnt;
always @(posedge clk) begin
if (reset) begin
state <= IDLE_s;
tcp_data_buf1 <= 'h0;
tcp_data_buf2 <= 'h0;
tcp_error_out <= 1'b0;
counter <= 'h0;
length <= 'h0;
checksum <= 'h0;
urg_ptr <= 'h0;
cnt <= 'h0;
end else begin
tcp_data_buf1 <= tcp_data_in;
tcp_data_buf2 <= tcp_data_buf1;
tcp_data_valid_r <= tcp_data_valid;
case (state)
IDLE_s: begin
if (tcp_data_valid) begin
state <= HEADER_s;
end else begin
state <= IDLE_s;
end
end
HEADER_s: begin
case (cnt)
3'h0: begin
if (tcp_data_buf1 == {SRC_PORT, DES_PORT} && tcp_data_valid_r) begin
tcp_error_out <= 1'b0;
cnt <= cnt + 'h1;
end else begin
tcp_error_out <= 1'b1;
$display("Source Port Error");
$stop;
end
end // case: 0
3'h1: begin
if (tcp_data_buf1 == `SEQ && tcp_data_valid_r) begin
tcp_error_out <= 1'b0;
cnt <= cnt + 'h1;
end else begin
tcp_error_out <= 1'b1;
$display("SEQ Error");
$stop;
end
end // case: 3'h1
3'h2: begin
if (tcp_data_buf1 == `ACK && tcp_data_valid_r) begin
tcp_error_out <= 1'b0;
cnt <= cnt + 'h1;
end else begin
tcp_error_out <= 1'b1;
cnt <= cnt + 1'h1;
$display("ACK Error");
$stop;
end
end // case: 3'h2
3'h3: begin
cnt <= cnt + 'h1;
if (tcp_data_buf1[23:16] != 'h0) begin
$display("This is a ctrl package and the flag is %x", tcp_data_buf1[23:16]);
end else begin
length <= (tcp_data_buf1 - 20) >> 2;
end
end
3'h4: begin
checksum <= tcp_data_buf1[31:16];
urg_ptr <= tcp_data_buf1[15:0];
state <= DATA_s;
end
default: begin
tcp_error_out <= 1'b0;
end
endcase // case (cnt)
end
DATA_s: begin
if (tcp_data_valid_r) begin
counter <= counter + 'h1;
if (counter != tcp_data_buf1) begin
$display("TCP Data Error");
tcp_error_out <= 1'b1;
end else if (counter == (length - 1)) begin
$display("TCP Data Passes Checking");
tcp_error_out <= 1'b0;
end
end else begin
counter <= 'h0;
state <= END_s;
end
end // case: Data_s
END_s: begin
state <= IDLE_s;
end
default: state <= IDLE_s;
endcase // case (state)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
| 6.637453 |
module Tcp_test;
// Inputs
reg CLOCK = 0;
reg paused = 1;
wire available;
wire [7:0] pktcount;
wire streamvalid;
wire [7:0] stream;
wire pcapfinished;
wire newpkt;
wire [7:0] tcpdata1, tcpdata2;
wire tcpdataValidA;
wire tcpdataValidB;
// Instantiate the Unit Under Test (UUT)
PcapParser #(
.pcap_filename("pcap/tcp-4846-connect-disconnect.pcap")
) pcap (
.CLOCK(CLOCK),
.pause(paused),
.available(available),
.datavalid(streamvalid),
.data(stream),
.pcapfinished(pcapfinished),
.newpkt(newpkt)
);
Tcp #(
.port(80),
.mac (48'hC471FEC856BF)
) tcp1 (
.CLOCK(CLOCK),
.tcpA_src_port(16'd57284),
.tcpA_src_ip({8'd10, 8'd210, 8'd50, 8'd28}),
.tcpA_dst_port(16'd4846),
.tcpA_dst_ip({8'd10, 8'd210, 8'd144, 8'd11}),
.tcpB_src_port(16'd0),
.tcpB_src_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpB_dst_port(16'd0),
.tcpB_dst_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpC_src_port(16'd0),
.tcpC_src_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpC_dst_port(16'd0),
.tcpC_dst_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpD_src_port(16'd0),
.tcpD_src_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpD_dst_port(16'd0),
.tcpD_dst_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.dataValid(streamvalid),
.data(stream),
.newpkt(newpkt),
.outDataMatchA(tcpdataValidA),
.outData(tcpdata1)
);
Tcp #(
.port(80),
.mac (48'hC471FEC856BF)
) tcp2 (
.CLOCK(CLOCK),
.tcpA_src_port(16'd57284),
.tcpA_src_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpA_dst_port(16'd0),
.tcpA_dst_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpB_src_port(16'd57284),
.tcpB_src_ip({8'd10, 8'd210, 8'd50, 8'd28}),
.tcpB_dst_port(16'd4846),
.tcpB_dst_ip({8'd10, 8'd210, 8'd144, 8'd11}),
.tcpC_src_port(16'd0),
.tcpC_src_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpC_dst_port(16'd0),
.tcpC_dst_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpD_src_port(16'd0),
.tcpD_src_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.tcpD_dst_port(16'd0),
.tcpD_dst_ip({8'd0, 8'd0, 8'd0, 8'd0}),
.dataValid(streamvalid),
.data(stream),
.newpkt(newpkt),
.outDataMatchB(tcpdataValidB),
.outData(tcpdata2)
);
always #10 CLOCK = ~CLOCK;
integer i;
integer acount, bcount;
initial begin
$dumpfile("bin/olittletoe.lxt");
$dumpvars(0, tcp1, tcp2);
acount = 0;
bcount = 0;
#100 paused = 0;
// Add stimulus here
while (~pcapfinished) begin
// $display("stream: %8d %x %d %x %x %c", i, paused, pktcount, streamvalid, stream, stream);
#20 i = i + 1;
end
if (acount != 1) begin
$display(" tcp A - expected one output byte, got %d values last %x", acount, tcpdata1);
$finish_and_return(-1);
end
if (bcount != 1) begin
$display(" tcp B - expected one output byte, got %d values last %x", bcount, tcpdata2);
$finish_and_return(-1);
end
$finish;
end
always @(posedge CLOCK) begin
if (tcpdataValidA) begin
$display("tcpA: %x ", tcpdata1);
acount = acount + 1;
if (acount > 1 || tcpdata1 != 8'h20) begin
$display(" tcp - expected one output byte, value 0x20, got %d values last %x", acount,
tcpdata1);
$finish_and_return(-1);
end
end
if (tcpdataValidB) begin
$display("tcpB: %x ", tcpdata2);
bcount = bcount + 1;
if (bcount > 1 || tcpdata2 != 8'h20) begin
$display(" tcp - expected one output byte, value 0x20, got %d values last %x", bcount,
tcpdata2);
$finish_and_return(-1);
end
end
end
endmodule
| 6.796265 |
module tcrc_cell2 (
input wire enable,
input wire preload,
input wire clock,
input wire reset,
input wire load,
input wire Input,
output wire q
);
//tmrg default triplicate
//tmrg tmr_error false
reg q_i;
//triplication signals
wire q_iVoted = q_i;
assign q = q_iVoted;
always@(posedge clock) // rising clock edge
begin
if (reset == 1'b0) // synchronous reset (active low)
q_i <= 1'b0;
else if (enable == 1'b1) begin
q_i <= (preload & load) | (Input & (~load)); // load ist der enable, entwd. Input oder preload
end else q_i <= q_iVoted;
end
endmodule
| 7.498852 |
module tcrc2 (
input wire clock,
input wire bitin,
input wire activ,
input wire reset,
input wire [14:0] crc_pre_load_ext,
input wire [14:0] crc_pre_load_rem,
input wire extended,
input wire load,
input wire load_activ,
input wire crc_shft_out,
input wire zerointcrc,
output wire crc_tosend
);
//tmrg default triplicate
//tmrg tmr_error false
reg edged;
reg enable_i; // Flankenmerker
wire activ_i;
wire reset_i;
wire load_i;
wire bitin_i;
wire feedback;
wire [14:0] q_out; // Ausg�nge Register
wire [14:0] inp; // Eing�nge Register
reg [14:0] crc_pre_load_i; // Ausgang MUX bas/ext
assign reset_i = reset;
//triplication signals
wire enable_iVoted = enable_i;
wire edgedVoted = edged;
// crc_shft_out=1 : Register ist jetzt Sendeschieberegister, deshalb feedback auf 0 stellen.
// Sonst normale XOR-R�ckkopplung
assign activ_i = (activ & (~crc_shft_out)) | (load_activ & crc_shft_out);
assign feedback = (~crc_shft_out) & q_out[14]; // R�ckf�hrung
assign load_i = load & load_activ;
assign bitin_i = (bitin | crc_shft_out) & zerointcrc;
// Nullen reinschieben (die fehlenden 15 Takte vor versendung), R�ckkopplung wie CRC-Generatorpolynom:
assign inp[0] = bitin_i ^ feedback;
assign inp[1] = q_out[0];
assign inp[2] = q_out[1];
assign inp[3] = q_out[2] ^ feedback;
assign inp[4] = q_out[3] ^ feedback;
assign inp[5] = q_out[4];
assign inp[6] = q_out[5];
assign inp[7] = q_out[6] ^ feedback;
assign inp[8] = q_out[7] ^ feedback;
assign inp[9] = q_out[8];
assign inp[10] = q_out[9] ^ feedback;
assign inp[11] = q_out[10];
assign inp[12] = q_out[11];
assign inp[13] = q_out[12];
assign inp[14] = q_out[13] ^ feedback;
assign crc_tosend = q_out[14];
//// Register instanziieren
genvar i;
generate
for (i = 0; i < 15; i = i + 1) begin
tcrc_cell2 reg_i (
.enable (enable_iVoted),
.preload(crc_pre_load_i[i]),
.clock (clock),
.reset (reset_i),
.load (load_i),
.Input (inp[i]),
.q (q_out[i])
);
end
endgenerate
// Multiplexer: abh�ngig von IDE crcreg mit unten oder oben vorladen
always @(extended, crc_pre_load_ext, crc_pre_load_rem) begin
if (extended == 1'b1) crc_pre_load_i = crc_pre_load_ext; // extended
else crc_pre_load_i = crc_pre_load_rem; // basic
end
always@(negedge clock) // DW 2005_06_30 clock Flanke von negativ auf positiv geaendert.
begin
if (reset == 1'b0) // synchroner reset
begin
enable_i <= 1'b1;
edged = 1'b0;
end else begin
edged = edgedVoted;
enable_i <= enable_iVoted;
if (activ_i == 1'b1)
if (edgedVoted == 1'b0) // war schon flanke?
begin
edged = 1'b1; // dann aber jetzt
enable_i <= 1'b1; // Schiebesignal
end else begin
edged = 1'b1; // war schon!
enable_i <= 1'b0; // Signal kurz
end
else begin
edged = 1'b0; // kein activ, flanke neg.
if (load == 1'b1 && load_activ == 1'b1) enable_i <= 1'b1; // Vorladen
else enable_i <= 1'b0;
end
end
end
endmodule
| 7.645063 |
module tcReset (
tcResetEn,
resetIn,
tcAddr,
resetOut
);
input tcResetEn, resetIn;
input [`tcAddrLen-1:0] tcAddr;
output [`tcNumbers-1:0] resetOut;
reg [`tcNumbers-1:0] resets;
always @(posedge tcResetEn) begin
if (tcResetEn) begin
resets[tcAddr] = resetIn;
end
end
assign resetOut = resets;
endmodule
| 7.414333 |
module tcsm_smtc (
in,
out
);
parameter nob = 4;
input [nob:0] in;
output [nob:0] out;
wire [nob:0] in_c, tc;
assign in_c = ~in;
assign tc = in_c + 1;
assign out = in[4] ? tc : in;
endmodule
| 7.205662 |
module tcu (
input clk,
n_Rst,
input byte_send, //data is sent
input start_trans, //signal from the debugger to start transmitting
input start_send,
output reg enable_count, //counts the number of bits that is sent out
output reg enable_start,
output reg tx_enable,
output reg start_bit, //send start bit
output reg tx_state //indicating whether it is IDLE(0) or BUSY(1)
);
//TOP LEVEL STATES
parameter [2:0] IDLE = 3'd0, START_SEND = 3'd1, START_BIT = 3'd2, SEND_BIT = 3'd3, STOP = 3'd4;
reg [2:0] state;
reg [2:0] nextState;
//next state logic
always @(posedge clk, negedge n_Rst) begin
if (n_Rst == 1'd0) begin
state <= IDLE;
end else begin
state <= nextState;
end
end
//state machines transition
always @(state, start_trans, byte_send, start_send) begin
case (state)
IDLE: begin
if (start_trans == 1'b1) begin
nextState <= START_SEND;
end else begin
nextState <= IDLE;
end
end
START_SEND: begin
if (start_send == 1'b1) begin
nextState <= SEND_BIT;
end else begin
nextState <= START_SEND;
end
end
SEND_BIT: begin
if (byte_send == 1'b1) begin
nextState <= STOP;
end else begin
nextState <= SEND_BIT;
end
end
STOP: begin
nextState <= IDLE;
end
default: begin
nextState <= IDLE;
end
endcase
end
//state machine output
always @(state, start_trans, byte_send) begin
case (state)
IDLE: begin
enable_start = 1'b0;
enable_count = 1'b0;
tx_state = 1'b0;
tx_enable = 1'b0;
end
START_SEND: begin
enable_start = 1'b1;
enable_count = 1'b0;
tx_state = 1'b1;
tx_enable = 1'b1;
end
SEND_BIT: begin
enable_start = 1'b0;
enable_count = 1'b1;
tx_state = 1'b1;
tx_enable = 1'b1;
end
STOP: begin
enable_start = 1'b0;
enable_count = 1'b0;
tx_state = 1'b0;
tx_enable = 1'b1;
end
default: begin
enable_start = 1'b0;
enable_count = 1'b0;
tx_state = 1'b0;
tx_enable = 1'b0;
end
endcase
end
endmodule
| 7.620568 |
module Tcustom1Rcustom_look_ahead_routing #(
parameter RAw = 3,
parameter EAw = 3,
parameter DSTPw = 4
) (
reset,
clk,
current_r_addr,
dest_e_addr,
src_e_addr,
destport
);
input [RAw-1 : 0] current_r_addr;
input [EAw-1 : 0] dest_e_addr;
input [EAw-1 : 0] src_e_addr;
output [DSTPw-1 : 0] destport;
input reset, clk;
reg [EAw-1 : 0] dest_e_addr_delay;
reg [EAw-1 : 0] src_e_addr_delay;
always @(`pronoc_clk_reset_edge) begin
if (`pronoc_reset) begin
dest_e_addr_delay <= {EAw{1'b0}};
src_e_addr_delay <= {EAw{1'b0}};
end else begin
dest_e_addr_delay <= dest_e_addr;
src_e_addr_delay <= src_e_addr;
end
end
Tcustom1Rcustom_look_ahead_routing_comb #(
.RAw (RAw),
.EAw (EAw),
.DSTPw(DSTPw)
) lkp_cmb (
.current_r_addr(current_r_addr),
.dest_e_addr(dest_e_addr_delay),
.src_e_addr(src_e_addr_delay),
.destport(destport)
);
endmodule
| 7.316693 |
module Tcustom1Rcustom_look_ahead_routing_genvar #(
parameter RAw = 3,
parameter EAw = 3,
parameter DSTPw = 4,
parameter CURRENT_R_ADDR = 0
) (
dest_e_addr,
src_e_addr,
destport,
reset,
clk
);
input [EAw-1 : 0] dest_e_addr;
input [EAw-1 : 0] src_e_addr;
output [DSTPw-1 : 0] destport;
input reset, clk;
reg [EAw-1 : 0] dest_e_addr_delay;
reg [EAw-1 : 0] src_e_addr_delay;
always @(`pronoc_clk_reset_edge) begin
if (`pronoc_reset) begin
dest_e_addr_delay <= {EAw{1'b0}};
src_e_addr_delay <= {EAw{1'b0}};
end else begin
dest_e_addr_delay <= dest_e_addr;
src_e_addr_delay <= src_e_addr;
end
end
custom1_look_ahead_routing_genvar_comb #(
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw),
.CURRENT_R_ADDR(CURRENT_R_ADDR)
) lkp_cmb (
.dest_e_addr(dest_e_addr_delay),
.src_e_addr(src_e_addr_delay),
.destport(destport)
);
endmodule
| 7.316693 |
module tcu_ctrl_reset (
input wire clk_i,
input wire reset_n_i,
output wire reset_sync_n_o,
input wire tcu_reset_i
);
reg r_tcu_reset, rin_tcu_reset;
reg [3:0] r_tcu_reset_count, rin_tcu_reset_count;
always @(posedge clk_i or negedge reset_n_i) begin
if (reset_n_i == 1'b0) begin
r_tcu_reset <= 1'b0;
r_tcu_reset_count <= 4'd0;
end else begin
r_tcu_reset <= rin_tcu_reset;
r_tcu_reset_count <= rin_tcu_reset_count;
end
end
always @* begin
rin_tcu_reset = 1'b0;
rin_tcu_reset_count = r_tcu_reset_count;
//tcu_reset_i is valid for only 1 cycle
//when counter overflows to 0, tcu_reset_all turns off
if (tcu_reset_i || (r_tcu_reset_count > 4'd0)) begin
rin_tcu_reset_count = r_tcu_reset_count + 4'd1;
rin_tcu_reset = 1'b1;
end
end
util_reset_sync i_reset_sync_tcu_ctrl (
.clk_i (clk_i),
.reset_q_i (reset_n_i & (~r_tcu_reset)),
.scan_mode_i (1'b0),
.sync_reset_q_o(reset_sync_n_o)
);
endmodule
| 6.59883 |
module tcu_priv_timer #(
parameter TIMER_SIZE = 32,
parameter CLKFREQ_MHZ = 100
) (
input wire clk_i,
input wire reset_n_i,
input wire timer_value_valid_i,
input wire [TIMER_SIZE-1:0] timer_value_i,
input wire timer_int_stall_i,
output reg timer_int_valid_o //trigger interrupt when not stalled
);
localparam TIMER_FACTOR = 1000 / CLKFREQ_MHZ;
localparam TIMER_STATES_SIZE = 2;
localparam S_TIMER_CTRL_IDLE = 2'h0;
localparam S_TIMER_CTRL_RUN = 2'h1;
localparam S_TIMER_CTRL_STOP = 2'h2;
reg [TIMER_STATES_SIZE-1:0] timer_ctrl_state, next_timer_ctrl_state;
//timer in ns
reg [TIMER_SIZE-1:0] r_timer, rin_timer;
//time [ns] = cycles * 1000 / freq [MHz]
wire [TIMER_SIZE-1:0] timer_incr = {{(TIMER_SIZE - 1) {1'b0}}, 1'b1} * TIMER_FACTOR;
//synopsys sync_set_reset "reset_n_i"
always @(posedge clk_i) begin
if (reset_n_i == 1'b0) begin
timer_ctrl_state <= S_TIMER_CTRL_IDLE;
r_timer <= {TIMER_SIZE{1'b0}};
end else begin
timer_ctrl_state <= next_timer_ctrl_state;
r_timer <= rin_timer;
end
end
//---------------
//state machine to trigger timer
always @* begin
next_timer_ctrl_state = timer_ctrl_state;
rin_timer = r_timer;
timer_int_valid_o = 1'b0;
case (timer_ctrl_state)
S_TIMER_CTRL_IDLE: begin
if (timer_value_valid_i && (timer_value_i != {TIMER_SIZE{1'b0}})) begin
//set timer
rin_timer = timer_value_i;
next_timer_ctrl_state = S_TIMER_CTRL_RUN;
end
end
S_TIMER_CTRL_RUN: begin
//stop when timer is unset, or reset it with new value
if (timer_value_valid_i) begin
if (timer_value_i == {TIMER_SIZE{1'b0}}) begin
next_timer_ctrl_state = S_TIMER_CTRL_IDLE;
end else begin
rin_timer = timer_value_i;
end
end //otherwise count down
else if (r_timer > timer_incr) begin
rin_timer = r_timer - timer_incr;
end else begin
next_timer_ctrl_state = S_TIMER_CTRL_STOP;
end
end
S_TIMER_CTRL_STOP: begin
//time is over
timer_int_valid_o = 1'b1;
if (!timer_int_stall_i) begin
next_timer_ctrl_state = S_TIMER_CTRL_IDLE;
end
end
default: begin
next_timer_ctrl_state = S_TIMER_CTRL_IDLE;
end
endcase
end
endmodule
| 8.038579 |
module tc_clock_generator_fmax (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h00;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_fmin (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h7f;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h01 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h01;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h02 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h02;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h04 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h04;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h08 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h08;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h10 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h10;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h20 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h20;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h30 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h30;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h38 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h38;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h3b (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h3b;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h3c (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h3c;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_clock_generator_h40 (
// tests do not have ports
);
localparam UNITDELAY = 1;
// values to test
localparam [7:1] c_clkdiv = 7'h40;
// calculate number of inverting gates with
// regular inverters + enabling NAND2 + inverting multiplexors + feedback driver
localparam [63:0] c_number_of_inverters = {c_clkdiv, 1'b1} + 7 + 1;
// expected result, two half-waves
localparam [63:0] c_clkperiod = (2 * c_number_of_inverters * UNITDELAY);
// ------------ test bench -------------------------------
tb_clock_generator tbench (
.i_clkdiv (c_clkdiv),
.i_clkperiod(c_clkperiod)
);
endmodule
| 7.250333 |
module tc_counter (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begin
#1;
// activate reset
rst_tb <= ~0;
rst_tb <= #(`RST_PERIOD) 0;
end
// ------------ testbench top level signals -----------------------
localparam c_width = 5;
reg r_enable = 0;
wire [c_width-1:0] w_result;
// ------------ device-under-test (DUT) ---------------------------
VfD_counter dut (
.i_enable(r_enable),
.o_result(w_result),
.clk(clk_tb),
.rst(rst_tb)
);
// ------------ functional model -------------------------------
reg [c_width-1:0] r_expectation = 0;
always @(posedge clk_tb) begin
if (r_enable) r_expectation = r_expectation + 1;
end
// ------------ test functionality -------------------------------
integer failed = 0; // failed test item counter
task t_initialize;
begin
#1;
@(negedge rst_tb);
@(posedge clk_tb);
#(`STROBE);
end
endtask
task t_run;
input integer reps;
begin
repeat (reps) begin
@(posedge clk_tb);
#(`STROBE);
failed = (r_expectation == w_result) ? failed : failed + 1;
end
end
endtask
task t_enable;
begin
r_enable <= ~0;
@(posedge clk_tb);
#(`STROBE);
end
endtask
task t_disable;
begin
r_enable <= 0;
@(posedge clk_tb);
#(`STROBE);
end
endtask
initial begin
t_initialize;
// 1st, enable and run
t_enable;
t_run(15);
// 2nd, stop
t_disable;
#1;
if (failed) $display("\t%m: *failed* %0d times", failed);
else $display("\t%m: *well done*");
$finish;
end
// ------------ testbench flow control ---------------------------
initial begin
$dumpfile(`DUMPFILE);
$dumpvars;
#(`TIMELIMIT);
$display("\t%m: *time limit (%t) reached*", $time);
$finish;
end
endmodule
| 7.607854 |
module tc_ds1wm (
ADDR,
ADS_N,
CLK,
EN_N,
RD_N,
WR_N,
MR,
INTR,
DATA,
IO,
STPZ
);
output [2:0] ADDR;
output ADS_N;
output CLK;
output EN_N;
output RD_N;
output WR_N;
output MR;
input INTR;
inout [7:0] DATA;
inout IO;
input STPZ;
reg MR;
`ifdef OW_SWITCH
reg [63:0] ROMID;
reg [63:0] ROMID1;
reg [63:0] ROMID2;
reg [63:0] ROMID3;
reg [63:0] ROMID4;
wire [63:0] xow_slave_romid;
wire [63:0] xxow_slave_romid;
wire [63:0] xxxow_slave_romid;
wire [63:0] xxxxow_slave_romid;
`else
reg [63:0] ROMID;
wire [63:0] xow_slave_romid;
`endif
wire CLK;
wire [7:0] clksel;
initial begin
ROMID = 64'hFFFF_FFFF_FFFF_FFFF;
end
cpu_bfm xcpu_bfm (
// Interface to DS1WM/
.ADDR(ADDR),
.ADS_N (ADS_N),
.CLKSEL(clksel),
.RD_N (RD_N),
.WR_N (WR_N),
.EN_N (EN_N),
.INTR(INTR),
.DATA(DATA)
);
`ifdef OW_SWITCH
ow_slave xow_slave (
.IO(IO),
.ROMID(xow_slave_romid)
);
ow_slave xxow_slave (
.IO(IO),
.ROMID(xxow_slave_romid)
);
ow_slave xxxow_slave (
.IO(IO),
.ROMID(xxxow_slave_romid)
);
ow_slave xxxxow_slave (
.IO(IO),
.ROMID(xxxxow_slave_romid)
);
scoreboard xscoreboard (
.OWS_ROMID1(xow_slave_romid),
.OWS_ROMID2(xxow_slave_romid),
.OWS_ROMID3(xxxow_slave_romid),
.OWS_ROMID4(xxxxow_slave_romid),
.STPZ(STPZ)
);
`else
ow_slave xow_slave (
.IO(IO),
.ROMID(xow_slave_romid)
);
scoreboard xscoreboard (
.OWS_ROMID(xow_slave_romid),
.STPZ(STPZ)
);
`endif
clkgen xclkgen (
.CLK(CLK),
.SEL(clksel)
);
// Generate System CLOCK
/*
parameter tclk = 125; // clk half-period 4Mhz -> 125ns
initial begin
CLK = 0;
forever #tclk CLK = !CLK;
.ROMID(xxxxow_slave_romid)
end
*/
task reset();
begin
MR = 1'b0;
@(posedge CLK);
MR = 1'b1;
@(posedge CLK);
MR = 1'b0;
end
endtask
`include "stimulus.inc"
endmodule
| 6.591918 |
module tc_heartbeat (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begin
#1;
// activate reset
rst_tb <= ~0;
rst_tb <= #(`RST_PERIOD) 0;
end
// ------------ testbench top level signals -----------------------
localparam f_clkin = 12_000;
wire w_ledout;
// ------------ device-under-test (DUT) ---------------------------
defparam dut.f_clkin = f_clkin;
VfD_heartbeat dut (
.o_led(w_ledout),
.clk(clk_tb),
.rst(rst_tb)
);
// ------------ test functionality -------------------------------
integer failed = 0; // failed test item counter
task t_initialize;
begin
#1;
@(negedge rst_tb);
@(posedge clk_tb);
#(`STROBE);
end
endtask
task t_run;
input integer reps;
begin
repeat (reps) begin
@(posedge clk_tb);
end
end
endtask
initial begin
t_initialize;
t_run(25_000);
#1;
if (failed) $display("\t%m: *failed* %0d times", failed);
else $display("\t%m: *well done*");
$finish;
end
// ------------ testbench flow control ---------------------------
initial begin
$dumpfile(`DUMPFILE);
$dumpvars;
#(`TIMELIMIT);
$display("\t%m: *time limit (%t) reached*", $time);
$finish;
end
endmodule
| 7.636051 |
module tc_prescaler (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begin
#1;
// activate reset
rst_tb <= ~0;
rst_tb <= #(`RST_PERIOD) 0;
end
// ------------ testbench top level signals -----------------------
localparam f_clkin = 12_000;
localparam f_clkout = 2;
wire w_clkout;
// ------------ device-under-test (DUT) ---------------------------
defparam dut.f_clkin = f_clkin; defparam dut.f_clkout = f_clkout;
VfD_prescaler dut (
.o_clk(w_clkout),
.clk(clk_tb)
);
// ------------ functional model -------------------------------
time last_edge = 0;
always @(posedge w_clkout) begin
if (w_clkout) $display("\tclock period is %t", $time - last_edge);
last_edge <= $time;
end
// ------------ test functionality -------------------------------
integer failed = 0; // failed test item counter
task t_initialize;
begin
#1;
@(negedge rst_tb);
@(posedge clk_tb);
#(`STROBE);
end
endtask
task t_run;
input integer reps;
begin
repeat (reps) begin
@(posedge clk_tb);
end
end
endtask
initial begin
t_initialize;
t_run(500_000);
#1;
if (failed) $display("\t%m: *failed* %0d times", failed);
else $display("\t%m: *well done*");
$finish;
end
// ------------ testbench flow control ---------------------------
initial begin
$dumpfile(`DUMPFILE);
$dumpvars;
#(`TIMELIMIT);
$display("\t%m: *time limit (%t) reached*", $time);
$finish;
end
endmodule
| 7.768142 |
module tc_shiftreg (
// Sorry, testbenches do not have ports
);
// ------------ global signals -------------------------------
reg clk_tb = ~0; // start with falling edge
always @(clk_tb) begin
clk_tb <= #(`CLK_PERIOD / 2) ~clk_tb;
end
reg rst_tb = 0; // start inactive
initial begin
#1;
// activate reset
rst_tb <= ~0;
rst_tb <= #(`RST_PERIOD) 0;
end
// ------------ testbench top level signals -----------------------
localparam c_width = 5;
reg r_enable = 0;
wire [c_width-1:0] w_result;
// ------------ device-under-test (DUT) ---------------------------
VfD_shiftreg dut (
.i_enable(r_enable),
.o_result(w_result),
.clk(clk_tb),
.rst(rst_tb)
);
// ------------ functional model -------------------------------
reg [c_width-1:0] r_expectation = 0;
always @(posedge clk_tb) begin
if (r_enable) r_expectation = {r_enable, r_expectation[c_width-1:1]};
end
// ------------ test functionality -------------------------------
integer failed = 0; // failed test item counter
task t_initialize;
begin
#1;
@(negedge rst_tb);
@(posedge clk_tb);
#(`STROBE);
end
endtask
task t_run;
input integer reps;
begin
repeat (reps) begin
@(posedge clk_tb);
#(`STROBE);
failed = (r_expectation == w_result) ? failed : failed + 1;
// this ist ugly - same code snippet as in device-under-test
end
end
endtask
task t_enable;
begin
r_enable <= ~0;
@(posedge clk_tb);
#(`STROBE);
end
endtask
task t_disable;
begin
r_enable <= 0;
@(posedge clk_tb);
#(`STROBE);
end
endtask
initial begin
t_initialize;
// 1st, enable and run
t_enable;
t_run(15);
// 2nd, stop
t_disable;
#1;
if (failed) $display("\t%m: *failed* %0d times", failed);
else $display("\t%m: *well done*");
$finish;
end
// ------------ testbench flow control ---------------------------
initial begin
$dumpfile(`DUMPFILE);
$dumpvars;
#(`TIMELIMIT);
$display("\t%m: *time limit (%t) reached*", $time);
$finish;
end
endmodule
| 7.859092 |
module part_TD25 (
INPUT,
O_5ns,
O_10ns,
O_15ns,
O_20ns,
O_25ns
);
input INPUT;
output O_5ns, O_10ns, O_15ns, O_20ns, O_25ns;
reg O_5ns, O_10ns, O_15ns, O_20ns, O_25ns;
initial begin
O_5ns <= 0;
O_10ns <= 0;
O_15ns <= 0;
O_20ns <= 0;
O_25ns <= 0;
end
always @(posedge INPUT) begin
O_5ns <= #(5) 1;
O_10ns <= #(10) 1;
O_15ns <= #(15) 1;
O_20ns <= #(20) 1;
O_25ns <= #(25) 1;
end
always @(negedge INPUT) begin
O_5ns <= #(5) 0;
O_10ns <= #(10) 0;
O_15ns <= #(15) 0;
O_20ns <= #(20) 0;
O_25ns <= #(25) 0;
end
endmodule
| 6.781923 |
module: TD4_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`default_nettype none
module TD4_test;
// Inputs
reg clock;
reg reset;
reg [3:0] sw;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
TD4_top uut (
.clock(clock),
.reset(reset),
.sw(sw),
.LED(LED)
);
initial begin
// Initialize Inputs
clock <= 0;
reset <= 1'bX;
sw <= 4'b1010;
// Wait 100 ns for global reset to finish
#50;
reset <= 1'b0;
#175;
reset <= 1'b1;
// Add stimulus here
end
//clock
always #100 begin
clock <= ~clock;
end
endmodule
| 7.147029 |
module TD4_top (
clock,
reset,
sw,
LED
);
input clock, reset;
input [3:0] sw;
output [3:0] LED;
wire [3:0] ip; //instruction pointer
wire [7:0] ramdata; //ramo
TD4_core TD4_core0 (
.clock(clock),
.reset(reset),
.sw(sw),
.LED(LED),
.ip(ip),
.ramdata(ramdata)
);
ram16 ram16_0 (
.data(ramdata),
.addr(ip)
);
endmodule
| 6.998169 |
module ram16 (
addr,
data
);
input [3:0] addr;
output [7:0] data;
//ram
wire [7:0] ram[15:0];
assign data = ram[addr];
assign ram[0] = 8'b10110111;
assign ram[1] = 8'b00000001;
assign ram[2] = 8'b11100001;
assign ram[3] = 8'b00000001;
assign ram[4] = 8'b11100011;
assign ram[5] = 8'b10110110;
assign ram[6] = 8'b00000001;
assign ram[7] = 8'b11100110;
assign ram[8] = 8'b00000001;
assign ram[9] = 8'b11101000;
assign ram[10] = 8'b10110000;
assign ram[11] = 8'b10110100;
assign ram[12] = 8'b00000001;
assign ram[13] = 8'b11101010;
assign ram[14] = 8'b10111000;
assign ram[15] = 8'b11111111;
/*
initial begin
ram[0] <= 8'b10110111;
ram[1] <= 8'b00000001;
ram[2] <= 8'b11100001;
ram[3] <= 8'b00000001;
ram[4] <= 8'b11100011;
ram[5] <= 8'b10110110;
ram[6] <= 8'b00000001;
ram[7] <= 8'b11100110;
ram[8] <= 8'b00000001;
ram[9] <= 8'b11101000;
ram[10] <= 8'b10110000;
ram[11] <= 8'b10110100;
ram[12] <= 8'b00000001;
ram[13] <= 8'b11101010;
ram[14] <= 8'b10111000;
ram[15] <= 8'b11111111;
*/
/*
ram[0] <= 8'b00111100; // mov A 1100
ram[1] <= 8'b00110110; // mov A 0110
ram[2] <= 8'b01110011; // mov B 0011
ram[3] <= 8'b01111001; // mov B 1001
ram[4] <= 8'b00010000; // mov A,B
ram[5] <= 8'b00111100; // mov A 1100
ram[6] <= 8'b01000000; // mov B,A
ram[7] <= 8'b00001100; // add A,1100
ram[8] <= 8'b01010011; // add B,0011
ram[9] <= 8'b00100000; // in A
ram[10] <= 8'b01100000; // in B
ram[11] <= 8'b10110101; // out 0101
ram[12] <= 8'b10010000; // out B
// ram[13] <= 8'b11110000; // jmp 0000
// ram[13] <= 8'b11100001; // jnc 0001
ram[13] <= 8'b00001111; // add A 1111
ram[14] <= 8'b11100010; // jnc 0010
ram[15] <= 8'b10111010; // out 1010 */
// end
endmodule
| 7.26066 |
module tdata_m3_for_arty_a7_axis_broadcaster_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 8,
parameter C_M_AXIS_TDATA_WIDTH = 8
) (
input wire [C_S_AXIS_TDATA_WIDTH-1:0] tdata,
output wire [C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[7:0], tdata[7:0]};
endmodule
| 8.718377 |
module tdata_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[23:16], tdata[7:0], tdata[15:8]};
endmodule
| 8.718377 |
module tdata_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[7:0], tdata[7:0], tdata[7:0]};
endmodule
| 8.718377 |
module tdata_mov_obj_det_axis_subset_converter_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[4:0], 3'b000, tdata[10:5], 2'b00, tdata[15:11], 3'b000};
endmodule
| 6.972496 |
module tdata_mov_obj_det_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[4:0], 3'b000, tdata[10:5], 2'b00, tdata[15:11], 3'b000};
endmodule
| 6.972496 |
module tdata_system_axis_subset_converter_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[23:0]};
endmodule
| 7.827217 |
module TDC (
input clk,
input start,
input stop,
input reset,
output reg [39:0] data,
output reg valid
);
wire [9:0] fine1_out;
wire [9:0] fine2_out;
wire [15:0] course_out;
wire coarse_done;
reg set;
wire or_reset;
wire fine1_stop;
wire fine2_stop;
or (or_reset, set, reset);
edgeDetector Start (
.clk (clk),
.reset(or_reset),
.level(start),
.out (fine1_stop)
);
edgeDetector Stop (
.clk (clk),
.reset(or_reset),
.level(stop),
.out (fine2_stop)
);
fine_counter #(
.x(46),
.y(4)
) fine1 (
.start(start),
.stop (fine1_stop),
.reset(or_reset),
.clk (clk),
.data (fine1_out)
);
fine_counter #(
.x(47),
.y(3)
) fine2 (
.start(stop),
.stop (fine2_stop),
.reset(or_reset),
.clk (clk),
.data (fine2_out)
);
Coarse_Counter_22 coarse (
.start(start),
.stop (stop),
.clk (clk),
.data (course_out),
.reset(or_reset)
);
//STATE MACHINE
localparam [2:0]
WAIT_FS = 3'b000,
WAIT_FP = 3'b001,
VALID = 3'b010,
WAIT_FR = 3'b011,
WAIT_FSub = 3'b100,
WAIT_FSub2 = 3'b101
;
reg [2:0] state, next;
initial begin
state <= WAIT_FS;
end
always @(posedge clk, posedge reset) begin
if (reset) begin
state <= WAIT_FS;
end else begin
state <= next;
end
end
always @(posedge clk) begin
case (state)
WAIT_FS: begin
set = 1'b0;
if (start == 1'b1) begin
next <= WAIT_FP;
end else begin
next <= WAIT_FS;
valid <= 1'b0;
end
end
WAIT_FP: begin
if (stop == 1'b1) begin
next <= WAIT_FSub;
end else begin
next <= WAIT_FP;
valid <= 1'b0;
end
end
WAIT_FSub: begin
next <= WAIT_FSub2;
end
WAIT_FSub2: begin
next <= VALID;
end
VALID: begin
data[23:14] <= fine1_out[9:0];
data[13:4] <= fine2_out[9:0];
data[39:24] <= course_out[15:0];
data[3:0] <= 4'b0101;
valid <= 1'b1;
next <= WAIT_FR;
end
WAIT_FR: begin
valid <= 1'b0;
set = 1'b1;
if (start == 0 && stop == 0) begin
next <= WAIT_FS;
end else begin
next <= WAIT_FR;
end
end
endcase
end
endmodule
| 7.096077 |
module TdcFifo_1024x8 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull
);
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output rdfull;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
dcfifo dcfifo_component (
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.rdfull(sub_wire2),
.aclr(),
.rdusedw(),
.wrempty(),
.wrfull(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Arria GX",
dcfifo_component.lpm_numwords = 1024, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 10, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.58075 |
module TdcFifo_1024x8 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull
);
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output rdfull;
endmodule
| 6.58075 |
module TdcTestBench;
parameter master_ck_period = 25;
parameter master_ck_half_period = master_ck_period / 2;
parameter master_ck_hold = 1; // data hold time
parameter fast_ck_period = 4;
parameter fast_ck_half_period = fast_ck_period / 2;
parameter fast_ck_hold = 0.5; // data hold time
reg Master_clock, Fast_clock, Master_resetB;
reg trig_pulse;
reg fast_clock;
wire [7:0] trig_time;
wire time_valid;
// LoResTdc Dut(.CLK(Fast_clock), .RSTb(Master_resetB), .START(Master_clock), .STOP(trig_pulse), .TIME(trig_time), .VALID(time_valid));
HiResTdc Dut (
.CLK (Fast_clock),
.RSTb (Master_resetB),
.START(Master_clock),
.STOP (trig_pulse),
.TIME (trig_time),
.VALID(time_valid)
);
// Time 0 values
initial begin
Master_clock = 0;
Fast_clock = 0;
Master_resetB = 1;
trig_pulse = 0;
fast_clock = 0;
end
// Main test vectors
initial begin
Sleep(2);
issue_RESET;
Sleep(20);
trig_pulse = 1;
Sleep(1);
trig_pulse = 0;
#(master_ck_period + 5);
trig_pulse = 1;
Sleep(1);
trig_pulse = 0;
#(master_ck_period - 5);
#(master_ck_period + 9);
trig_pulse = 1;
Sleep(1);
trig_pulse = 0;
#(master_ck_period - 9);
#(master_ck_period + 13);
trig_pulse = 1;
Sleep(1);
trig_pulse = 0;
#(master_ck_period - 13);
end
// Clock generator: free running
initial begin
#(master_ck_period - master_ck_hold) Master_clock <= ~Master_clock;
forever #master_ck_half_period Master_clock <= ~Master_clock;
end
initial begin
#(fast_ck_period - fast_ck_hold) Fast_clock <= ~Fast_clock;
forever #fast_ck_half_period Fast_clock <= ~Fast_clock;
end
// User tasks
task Sleep;
input [31:0] waittime;
begin
repeat (waittime) #master_ck_period;
end
endtask // Sleep
task issue_RESET;
begin
#master_ck_period Master_resetB = 0;
#master_ck_period;
#master_ck_period;
#master_ck_period;
#master_ck_period Master_resetB = 1;
#master_ck_period;
end
endtask // issue_RESET
endmodule
| 6.673967 |
module TDC_DeltaT_1Chan #(
parameter WORDSIZE = 16,
parameter CNTSIZE = 38
) (
input CH1,
input [CNTSIZE-1:0] cnt,
input clk,
input rst,
output [WORDSIZE-1:0] outData,
output wrEn
);
reg [CNTSIZE-1:0] last1_d, last1_q; //last time point registers
reg wrEn_d, wrEn_q; //write enable registers
reg [WORDSIZE-1:0] outData_d, outData_q; //output data registers
//assign outputs
assign outData = outData_q;
assign wrEn = wrEn_q;
always @(posedge clk) begin
if (rst) begin
wrEn_d <= 0;
last1_d <= 0;
outData_d <= 0;
end else begin
wrEn_d <= CH1;
if (CH1) begin
last1_d <= cnt;
outData_d <= cnt - last1_q;
end
end
outData_q <= outData_d;
last1_q <= last1_d;
wrEn_q <= wrEn_d;
end
endmodule
| 7.313546 |
module: Two_Digit_Counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TDC_test;
// Inputs
reg clk;
reg rst;
// Outputs
wire [6:0] seg_1;
wire [6:0] seg_10;
// Instantiate the Unit Under Test (UUT)
Two_Digit_Counter uut (
.clk(clk),
.rst(rst),
.seg_1(seg_1),
.seg_10(seg_10)
);
initial begin
rst = 1; clk =0;
#100
rst=0;
end
always
#10 clk = ~clk;
// Add stimulus here
endmodule
| 6.826338 |
module TDC_TOP (
input iCLK,
input iRST,
input iHIT,
//DEBUG OUTPUTS
//output [`NUM_STAGES-1:0] oTHERMOMETERSTART,
//output [`NUM_STAGES-1:0] oTHERMOMETERSTOP,
//END OF DEBUG OUTPUTS
output oVALUEREADY,
//output [`COARSE_BITS-1:0] oCOARSEARBITERVALUE,
output [`NUM_OUTPUT_BITS-1:0] oTDCVALUE
);
//PLL TO SHIFT SYSTEM CLOCK FOR TDC SAMPLING AND COARSE COUNTING
//wire wCLK0;
wire wCLK1;
wire wCLK2;
PHASEPLL pll_inst (
.iCLK (iCLK),
.reset(iRST),
.oCLK (wCLK1),
.oCLK2(wCLK2)
);
//TDC BLOCK
TDCMODULE tdc_module_inst (
.iCLK0(iCLK),
.iCLK1(wCLK1),
.iCLK2(wCLK2),
.iRST(iRST),
.iHIT(iHIT),
//DEBUG OUTPUTS
//.oTHERMOMETERSTART(oTHERMOMETERSTART),
//.oTHERMOMETERSTOP(oTHERMOMETERSTOP),
//END OF DEBUG OUTPUTS
//.oCOARSEARBITERVALUE(oCOARSEARBITERVALUE),
.oVALUEREADY(oVALUEREADY),
.oTDCVALUE(oTDCVALUE)
);
endmodule
| 7.854513 |
module tDecoder;
reg [15:0] instruction;
reg clk, reset, IR;
//start signals
wire ALUstr, MOVstr, LDSRstr;
wire [3:0] opCode;
//decoder control signals
wire IRiEn, IRjEn;
reg BRjEn, IF;
// Register signals
wire [ 3:0] index;
wire [15:0] bus;
decoder D (
IR,
instruction,
ALUstr,
MOVstr,
LDSRstr,
opCode,
index,
reset,
IRiEn,
IRjEn,
IF,
BRjEn,
bus
);
initial begin
clk = 0;
BRjEn = 0;
// ADDI R_0, #7
#5 reset = 1;
#5 reset = 0;
instruction = {4'd7, 6'd0, 6'd10};
#5 BRjEn = 1;
#10 $finish;
end
endmodule
| 6.910868 |
module tdest_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDEST_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDEST_WIDTH-1:0] tdest_out
);
assign tdest_out = {tdest[0:0]};
endmodule
| 6.91769 |
module tdest_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDEST_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TDEST_WIDTH-1:0] tdest_out
);
assign tdest_out = {tdest[0:0]};
endmodule
| 6.91769 |
module RX (
input wire HCLK,
input wire HRESETn,
input wire SCK,
input wire SDI,
output wire [31:0] DATA,
output wire BRCK,
output wire BWCK
);
localparam ST_S0 = 4'b0001,
ST_S1 = 4'b0010,
ST_S2 = 4'b0100,
ST_S3 = 4'b1000;
reg [3:0] state, nstate;
// Synchronizers
reg [1:0] sdi_sync;
`SYNC_BEGIN(sdi_sync, 2'h0)
sdi_sync <= {sdi_sync[0], SDI};
`SYNC_END
reg [1:0] sck_sync;
`SYNC_BEGIN(sck_sync, 2'h3)
sck_sync <= {sck_sync[0], SCK};
`SYNC_END
wire SDI_SYNC = sdi_sync[1];
wire SCK_SYNC = sck_sync[1];
// Edge detector
`SYNC_BEGIN(state, ST_S0)
state <= nstate;
`SYNC_END
always @*
case(state)
ST_S0: if(SCK_SYNC) nstate = ST_S0; else nstate = ST_S1;
ST_S1: nstate = ST_S2;
ST_S2: if(SCK_SYNC) nstate = ST_S3; else nstate = ST_S2;
ST_S3: nstate = ST_S0;
endcase
// Shift Register
reg [31:0] shifter;
`SYNC_BEGIN(shifter, 'h0)
if((state == ST_S1) /*&& (SCK_SYNC == 1'b1)*/) shifter <= {SDI_SYNC, shifter[31:1]};
`SYNC_END
assign DATA = shifter;
assign BRCK = (state == ST_S3);
assign BWCK = (state == ST_S1);
endmodule
| 7.66798 |
module tdl (
input en,
input clk,
input trigI,
output [3:0] counter_value
);
tdl_on_slice seg0 (
.en(en),
.clk(clk),
.and_gate0_I0(trigI),
.counter_value(counter_value[3:0])
);
endmodule
| 7.859092 |
module tdl_on_slice (
input en,
input clk,
input and_gate0_I0,
output cascade_out,
output [3:0] counter_value
);
wire [3:0] and_to_fd;
(* s = "true" *) AND2 and_gate0 (
.O (and_to_fd[0]),
.I0(and_gate0_I0),
.I1(en)
);
(* s = "true" *) AND2 and_gate1 (
.O (and_to_fd[1]),
.I0(and_to_fd[0]),
.I1(en)
);
(* s = "true" *) AND2 and_gate2 (
.O (and_to_fd[2]),
.I0(and_to_fd[1]),
.I1(en)
);
(* s = "true" *) AND2 and_gate3 (
.O (and_to_fd[3]),
.I0(and_to_fd[2]),
.I1(en)
);
(* s = "true" *) FD d_ff0 (
.C(clk),
.D(and_to_fd[0]),
.Q(counter_value[0])
);
(* s = "true" *) FD d_ff1 (
.C(clk),
.D(and_to_fd[1]),
.Q(counter_value[1])
);
(* s = "true" *) FD d_ff2 (
.C(clk),
.D(and_to_fd[2]),
.Q(counter_value[2])
);
(* s = "true" *) FD d_ff3 (
.C(clk),
.D(and_to_fd[3]),
.Q(counter_value[3])
);
assign cascade_out = and_to_fd[3];
endmodule
| 6.621552 |
module tdm (
num,
an,
num1,
num2,
num3,
num4,
clk
);
output reg [3:0] num;
output reg [3:0] an;
// hex inputs
input [3:0] num1;
input [3:0] num2;
input [3:0] num3;
input [3:0] num4;
input clk;
reg [1:0] counter;
reg cout;
initial begin
counter = 3'b000;
end
always @(posedge clk) begin
counter = counter + 1;
end
always @(counter) begin
case (counter)
2'b00: an = 4'b0001;
2'b01: an = 4'b0010;
2'b10: an = 4'b0100;
2'b11: an = 4'b1000;
endcase
end
always @(counter or num4 or num3 or num2 or num1) begin
case (counter)
2'b00: num = num1;
2'b01: num = num2;
2'b10: num = num3;
2'b11: num = num4;
endcase
end
endmodule
| 6.815959 |
module tdm_gen (
input bclk,
input wclk,
output tdm_out
);
reg [1:0] wc_ff;
reg [5:0] bclk_cnt;
parameter FIX_DATA = 32'hABCD0000;
assign tdm_out = FIX_DATA[bclk_cnt[4:0]];
always @(posedge bclk) begin
wc_ff <= {wc_ff[0], wclk};
end
always @(negedge bclk) begin
if (wc_ff == 2'b01) bclk_cnt <= 6'd62;
else begin
bclk_cnt <= bclk_cnt - 6'd1;
end
end
endmodule
| 7.082334 |
module tdm_input (
input mclk,
input [7:0] cnt256_n,
input tdm_in,
output reg [15:0] ch1_out,
output reg [15:0] ch2_out
);
reg [63:0] data_reg;
always @(posedge mclk) begin
if (cnt256_n == 8'd0) begin
//VtgWX^̃f[^Oɏo
ch1_out <= data_reg[63:48];
ch2_out <= data_reg[31:16];
end else if (cnt256_n[1:0] == 2'd2) begin
//VAf[^荞
data_reg <= {data_reg[62:0], tdm_in};
end else begin
//Latch
end
end
endmodule
| 6.532695 |
module Tdot (
input wire clk,
input wire reset,
input wire [7:0] a0,
input wire [7:0] a1,
input wire [7:0] a2,
input wire [7:0] b0,
input wire [7:0] b1,
input wire [7:0] b2,
input wire [7:0] c,
output wire [7:0] y
);
top t (
.clk(clk),
.reset(reset),
.a0(a0),
.a1(a1),
.a2(a2),
.b0(b0),
.b1(b1),
.b2(b2),
.c(c),
.en(1'd1),
.y(y)
);
endmodule
| 8.210756 |
module tdo_mux (
input TDO_0C,
input TDO_17,
input [32:0] FSEL,
output reg TDO
);
always @(TDO_0C or TDO_17 or FSEL)
case (FSEL)
33'h000001000: TDO <= TDO_0C;
33'h000800000: TDO <= TDO_17;
default: TDO <= 1'b0;
endcase
endmodule
| 7.233606 |
module true_dual_port_ram_readfirst_reg1 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2
)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0]
memory[(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
always @(posedge clock1) begin
if (enable1) begin
odata1 <= memory[addr1];
if (write1) memory[addr1] <= idata1;
end
end
always @(posedge clock2) begin
if (enable2) begin
odata2 <= memory[addr2];
if (write2) memory[addr2] <= idata2;
end
end
endmodule
| 9.063194 |
module true_dual_port_ram_readfirst_reg2 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2
)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0]
memory[(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1) begin
if (enable1) begin
odata1_reg <= memory[addr1];
if (write1) memory[addr1] <= idata1;
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2) begin
if (enable2) begin
odata2_reg <= memory[addr2];
if (write2) memory[addr2] <= idata2;
end
odata2 <= odata2_reg;
end
endmodule
| 9.063194 |
module true_dual_port_ram_writefirst_reg1 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2
)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0]
memory[(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
always @(posedge clock1) begin
if (enable1) begin
odata1 <= memory[addr1];
if (write1) begin
memory[addr1] <= idata1;
odata1 <= idata1;
end
end
end
always @(posedge clock2) begin
if (enable2) begin
odata2 <= memory[addr2];
if (write2) begin
memory[addr2] <= idata2;
odata2 <= idata2;
end
end
end
endmodule
| 9.063194 |
module true_dual_port_ram_writefirst_reg2 #(
parameter integer DATA_WIDTH = 8,
ADDR_WIDTH = 10
) (
input wire clock1,
input wire enable1,
input wire write1,
input wire [ADDR_WIDTH-1:0] addr1,
input wire [DATA_WIDTH-1:0] idata1,
output reg [DATA_WIDTH-1:0] odata1,
input wire clock2,
input wire enable2,
input wire write2,
input wire [ADDR_WIDTH-1:0] addr2,
input wire [DATA_WIDTH-1:0] idata2,
output reg [DATA_WIDTH-1:0] odata2
)
/* synthesis syn_hier = "hard" */;
reg [DATA_WIDTH-1:0]
memory[(1<<ADDR_WIDTH)-1:0]
/* synthesis syn_ramstyle="no_rw_check" */;
reg [DATA_WIDTH-1:0] odata1_reg;
always @(posedge clock1) begin
if (enable1) begin
odata1_reg <= memory[addr1];
if (write1) begin
memory[addr1] <= idata1;
odata1_reg <= idata1;
end
end
odata1 <= odata1_reg;
end
reg [DATA_WIDTH-1:0] odata2_reg;
always @(posedge clock2) begin
if (enable2) begin
odata2_reg <= memory[addr2];
if (write2) begin
memory[addr2] <= idata2;
odata2_reg <= idata2;
end
end
odata2 <= odata2_reg;
end
endmodule
| 9.063194 |
module tdt_dmi_pulse_sync #(
parameter SYNC_NUM = 2
) (
input src_clk,
input dst_clk,
input src_rst_b,
input dst_rst_b,
input src_pulse,
output dst_pulse
);
reg src_pulse_2_lvl;
wire dst_lvl;
reg dst_lvl_d;
wire dst_lvl_src;
reg dst_lvl_src_d;
wire dst_pulse_2_src;
always @(posedge src_clk or negedge src_rst_b) begin
if (!src_rst_b) dst_lvl_src_d <= 1'b0;
else dst_lvl_src_d <= dst_lvl_src;
end
assign dst_pulse_2_src = dst_lvl_src & ~dst_lvl_src_d;
always @(posedge src_clk or negedge src_rst_b) begin
if (!src_rst_b) src_pulse_2_lvl <= 1'b0;
else if (dst_pulse_2_src) src_pulse_2_lvl <= 1'b0;
else if (src_pulse) src_pulse_2_lvl <= 1'b1;
//src_pulse_2_lvl <= ~src_pulse_2_lvl;
end
tdt_dmi_sync_dff #(
.SYNC_NUM(SYNC_NUM)
) x_tdt_dmi_sync_dff (
.dst_clk (dst_clk),
.dst_rst_b(dst_rst_b),
.src_in (src_pulse_2_lvl),
.dst_out (dst_lvl)
);
tdt_dmi_sync_dff #(
.SYNC_NUM(SYNC_NUM)
) x_tdt_dmi_sync_dff_back (
.dst_clk (src_clk),
.dst_rst_b(src_rst_b),
.src_in (dst_lvl),
.dst_out (dst_lvl_src)
);
always @(posedge dst_clk or negedge dst_rst_b) begin
if (!dst_rst_b) dst_lvl_d <= 1'b0;
else dst_lvl_d <= dst_lvl;
end
assign dst_pulse = dst_lvl & ~dst_lvl_d;
endmodule
| 6.996321 |
module tdt_dmi_rst_top (
sys_apb_clk,
sys_apb_rst_b,
pad_yy_scan_mode,
pad_yy_scan_rst_b,
sync_sys_apb_rst_b
);
input sys_apb_clk;
input sys_apb_rst_b;
input pad_yy_scan_mode;
input pad_yy_scan_rst_b;
output sync_sys_apb_rst_b;
wire sync_sys_apb_rst_b;
wire async_apb_rst_b;
reg sys_apb_rst_ff_1st;
assign async_apb_rst_b = sys_apb_rst_b;
always @(posedge sys_apb_clk or negedge async_apb_rst_b) begin
if (!async_apb_rst_b) sys_apb_rst_ff_1st <= 1'b0;
else sys_apb_rst_ff_1st <= 1'b1;
end
assign sync_sys_apb_rst_b = pad_yy_scan_mode ? pad_yy_scan_rst_b : sys_apb_rst_ff_1st;
endmodule
| 6.717745 |
module tdt_dmi_sync_dff #(
parameter SYNC_NUM = 2
) (
input dst_clk,
input dst_rst_b,
input src_in,
output dst_out
);
reg [SYNC_NUM-1:0] sync_ff;
always @(posedge dst_clk or negedge dst_rst_b) begin
if (!dst_rst_b) sync_ff[SYNC_NUM-1:0] <= {SYNC_NUM{1'b0}};
else sync_ff[SYNC_NUM-1:0] <= {sync_ff[SYNC_NUM-2:0], src_in};
end
assign dst_out = sync_ff[SYNC_NUM-1];
endmodule
| 6.782225 |
module tdt_dm_pulse_sync #(
parameter SYNC_NUM = 2
) (
input src_clk,
input dst_clk,
input src_rst_b,
input dst_rst_b,
input src_pulse,
output dst_pulse
);
reg src_pulse_2_lvl;
wire dst_lvl;
reg dst_lvl_d;
wire dst_lvl_src;
reg dst_lvl_src_d;
wire dst_pulse_2_src;
always @(posedge src_clk or negedge src_rst_b) begin
if (!src_rst_b) dst_lvl_src_d <= 1'b0;
else dst_lvl_src_d <= dst_lvl_src;
end
assign dst_pulse_2_src = dst_lvl_src & ~dst_lvl_src_d;
always @(posedge src_clk or negedge src_rst_b) begin
if (!src_rst_b) src_pulse_2_lvl <= 1'b0;
else if (dst_pulse_2_src) src_pulse_2_lvl <= 1'b0;
else if (src_pulse) src_pulse_2_lvl <= 1'b1;
//src_pulse_2_lvl <= ~src_pulse_2_lvl;
end
tdt_dm_sync_dff #(
.SYNC_NUM(SYNC_NUM)
) x_tdt_dm_sync_dff (
.dst_clk (dst_clk),
.dst_rst_b(dst_rst_b),
.src_in (src_pulse_2_lvl),
.dst_out (dst_lvl)
);
tdt_dm_sync_dff #(
.SYNC_NUM(SYNC_NUM)
) x_tdt_dm_sync_dff_back (
.dst_clk (src_clk),
.dst_rst_b(src_rst_b),
.src_in (dst_lvl),
.dst_out (dst_lvl_src)
);
always @(posedge dst_clk or negedge dst_rst_b) begin
if (!dst_rst_b) dst_lvl_d <= 1'b0;
else dst_lvl_d <= dst_lvl;
end
assign dst_pulse = dst_lvl & ~dst_lvl_d;
endmodule
| 7.389619 |
module tdt_dm_sync_dff #(
parameter SYNC_NUM = 2
) (
input dst_clk,
input dst_rst_b,
input src_in,
output dst_out
);
reg [SYNC_NUM-1:0] sync_ff;
always @(posedge dst_clk or negedge dst_rst_b) begin
if (!dst_rst_b) sync_ff[SYNC_NUM-1:0] <= {SYNC_NUM{1'b0}};
else sync_ff[SYNC_NUM-1:0] <= {sync_ff[SYNC_NUM-2:0], src_in};
end
assign dst_out = sync_ff[SYNC_NUM-1];
endmodule
| 7.288187 |
module tdt_dtm_io (
input pad_dtm_jtag2_sel,
input pad_dtm_tap_en,
input pad_dtm_tdi,
input pad_dtm_tms_i,
output dtm_pad_tdo,
output dtm_pad_tdo_en,
output dtm_pad_tms_o,
output dtm_pad_tms_oe,
input chain_io_tdo,
input ctrl_io_tdo_en,
input ctrl_io_tms_oe,
output io_chain_tdi,
output io_ctrl_tap_en
);
assign io_ctrl_tap_en = pad_dtm_tap_en;
assign io_chain_tdi = pad_dtm_jtag2_sel ? pad_dtm_tms_i : pad_dtm_tdi;
assign dtm_pad_tdo = chain_io_tdo;
assign dtm_pad_tms_o = chain_io_tdo;
assign dtm_pad_tdo_en = ctrl_io_tdo_en;
assign dtm_pad_tms_oe = ctrl_io_tms_oe;
endmodule
| 6.511749 |
module TD_Detect (
oTD_Stable,
oNTSC,
oPAL,
iTD_VS,
iTD_HS,
iRST_N
);
input iTD_VS;
input iTD_HS;
input iRST_N;
output oTD_Stable;
output oNTSC;
output oPAL;
reg NTSC;
reg PAL;
reg Pre_VS;
reg [7:0] Stable_Cont;
assign oTD_Stable = NTSC || PAL;
assign oNTSC = NTSC;
assign oPAL = PAL;
always @(posedge iTD_HS or negedge iRST_N)
if (!iRST_N) begin
Pre_VS <= 1'b0;
Stable_Cont <= 4'h0;
NTSC <= 1'b0;
PAL <= 1'b0;
end else begin
Pre_VS <= iTD_VS;
if (!iTD_VS) Stable_Cont <= Stable_Cont + 1'b1;
else Stable_Cont <= 0;
if ({Pre_VS, iTD_VS} == 2'b01) begin
if ((Stable_Cont >= 4 && Stable_Cont <= 14)) NTSC <= 1'b1;
else NTSC <= 1'b0;
if ((Stable_Cont >= 8'h14 && Stable_Cont <= 8'h1f)) PAL <= 1'b1;
else PAL <= 1'b0;
end
end
endmodule
| 6.977162 |
module td_fused_top_ap_hadd_0_full_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
`ifdef complex_dsp
adder_fp u_add_fp (
.a (s_axis_a_tdata),
.b (s_axis_b_tdata),
.out(m_axis_result_tdata)
);
`else
FPAddSub u_FPAddSub (
.clk(),
.rst(1'b0),
.a(s_axis_a_tdata),
.b(s_axis_b_tdata),
.operation(1'b0),
.result(m_axis_result_tdata),
.flags()
);
`endif
endmodule
| 6.827284 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
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