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H: What does this mean in the datasheet for PWM motor control? My aim is to control a DC servo motor through PWM. It has a motor controller attached to it that takes in some DC source and PWM for controlling the motors. I programmed/used a myRio (MCU) to produce PWM from one of its pins and connected it to the motor controller but it is not producing the expected results i.e only going in one direction. The MCU is programmed to produced a PWM at 10 kHz for duty cycles 0 to 50 % and then 50 % back down to 0 %. However, the motor does not change direction. The MCU produces an output of 3.3 Vpeak for the PWM (checked on oscilloscope). The MCU digital pin output voltage can be programmed or changed. In the datasheet of the motor controller (sabertooth 2X12) it states: "In all cases, an analog voltage of 2.5 V corresponds to no movement. Signals above 2.5 V will command a forward motion and signals below 2.5 V will command a backwards motion." So my college believes that a PWM voltage of 5 V is required based on those three lines of datasheet snippet I provided. My main question is what does the datasheet snippet above mean? (Is it correct to assume a 5 Vpeak PWM signal is required)? Datasheet full (see page 9): https://www.dimensionengineering.com/datasheets/Sabertooth2x12.pdf AI: I've used Sabertooth and their sister SyRen controllers extensively. They are great quality devices, but they are NOT servo controllers. They are motor controllers, so they can change motor speed and direction, but they don't have feedback input and therefore cannot receive position commands. The PWM signal is typically used in two ways: As low-current position control command for hobby servo controllers. In this case the width of a pulse defines target position and a servo moves motor to reach that position. This has nothing to do with Sabertooth/SyRen controllers. They accept either analog or serial or R/C commands. You can convert your PWM signal into analog voltage (e.g. by using RC low-pass filter), which is cumbersome and imprecise, not to mention pointless. Or you can use mode 2 and send PWM signal at approximately 50-100 Hz frequency (not 10 kHz!). In either case, your command will not control the position. It will only control motor speed and direction, even if you use R/C servo signal format. If you change the frequency of PWM in your MCU and configure the switches on Sabertooth accordingly you should be able to control the motor immediately. As high-current power to the motor. In this case the width of a pulse defines average current going through the motor and therefore direction and speed/torque. It is, indeed, typical for this signal to have 10-20 kHz frequency. This kind of PWM is exactly what Sabertooth generates on its output. It does not require any PWM coming from MCU. To answer you main question, the analog input is designed to receive stable (as in "not pulsed") DC voltage in a certain range. The simplest example would be a potentiometer between 5V and ground with wiper connected to analog input. Or, specifically in case of 2-channel Sabertooth controller, an analog joystick with its two axes connected to two analog inputs. This is exactly what Sabertooth is designed for, because it supports automatic mixing of these two channels into differential control of two wheels, also known as "tank" control. Finally, analog signal is not the best way to control Sabertooth if you want to use it with MCU. Its main selling feature is support for a simple 1-byte serial protocol, as well as more advanced addressable protocol that allows connection of multiple controllers to a single UART port. Having said that, you can build a servo driver using analog input. For this you need a sensor connected to the comparator circuit that generates analog command for controller. The comparator would compare sensor voltage (actual servo position) with analog signal from MCU (target position) and move motor to reduce the difference. This is not a trivial task to design and tune up. And it would probably cost more than buying hobby servo of suitable size.
H: UART printing gibberish to the terminal when the STLink Debugger is not connected Custom board, not an ST development board. MCU: STM32G031J6M6 SO8 package. UART RX/TX are Pins 1 and 8 respectively. Pin 8 is also SWDCLK Pin 7 is SWDIO and not used except for SWD NRST is Pin 4 and has an internal pull-up. From reading the option bytes via the STM32 CubeProgrammer. All the options are checked by default, including nBOOT_SEL, nBOOT1, nBOOT0 and NRST_Mode is 3. The BOOT_LOCK is unchecked (0) With this configuration it appears the MCU is booting straight into flash memory as intended. I am able to flash the firmware and also run the program successfully. But the successful running is only with the STLink utility connected to the board. If it's not connected, there's some random gibberish characters being displayed on the terminal along with my own input as i type into the keyboard. e.g. if i type 'ACTION', i will see 'AACTION??$d', etc. The input is clean when the STLink is connected. If I disconnect the STLink and reconnect it, the program no longer seems to work (at least I am unable to track where it is in its execution state), I have to then do a power reset with the STLink connected and it's functional again. The firmware is a 'Release' build. In the main loop, I just added a block of code to continually print 'hi\n' so it seems the UART init is OK even without the STLink connected, and it prints hi continuously except for those random gibberish characters turning up sometimes along with the hi. The gibberish seems more persistent when I'm typing, almost like an echo. I have an FTDI (original not fake) TTL-232R serial convertor connected to the board and back to the PC via USB on the same USB bus as the STLink debugger. I am only using the GND, TX, and RX pins. FTDI TTL-232R Serial Convertor AI: I would verify that you have a good ground from the DUT to the FTDI converter cable. You could have a situation where the ST-Link is ground referencing your system to the host PC.
H: Is it bad practice to use the positive/rising edge of a "non-clock" signal? Situation: Before a data ready signal can go high it must wait for a data valid signal to go high. Once data ready goes high, data ready must remain high until a separate process is complete which should reset data ready to low and again data ready should wait for data valid to go high and so forth. FPGA: xc7s25csga324-1, Spartan-7 S25, speed grade -1, Switching Characteristics Timing diagram of hypothetical situation for a 3-bit sample: Problem: data valid only goes high for one clock cycle and so it would be convenient for the data ready to wait for the positive/rising edge of data valid. Question: Will programming the data ready signal to trigger on the positive/rising edge of data valid cause issues in implementation since data valid is not a clock? AI: If whatever you're interfacing to acts per the drawing, then AND data_ready and data_valid together, and sample at the falling edge of the clock. Then hold that state and do whatever you do with the incoming data bits until data_valid goes low, and stop.
H: Which Kicad footprint represents a 2.2 µF MKP audio coupling capacitor? I'd like to add six rectangular-shaped 2.2 µF MKP capacitors used as coupling caps for an audio circuit to my PCB in Kicad, but I'm not quite sure about the right footprint. What makes the choice even harder, is the fact that these caps are very big, yet are equipped with fairly long terminals, so that I could make them stand in the air somehow. Any idea? UPDATE: I've now made Pcbnew generate a PCB layout, but now all these caps occupy the complete PCB surface underneath them, so that the somehow remain on the ground floor. Also, the regulator in the top left corner appears to lie on the board instead of standing on it. This may make the board grow too large. See the screenshot attached: UPDATE #2: There is in fact a vertical footprint for the regulator, and when it comes to the big coupling caps, distributing them over the board in a smart way is the clue. I did some manual replacement work and then used Freeroute to draw the conductors: AI: You are looking for a footprint with 27.5mm pitch (Rastermaß) between pins and 32mm length. The closest two footprints in KiCad are: C_Rect_L31.5mm_W13.0mm_P27.50mm_MKS4 C_Rect_L33.0mm_W13.0mm_P27.50mm_MKS4 You can use either of these and modify it to the exact dimensions
H: Can I automatically create a net class from this Blanket + Parameter? [ALTIUM] I added this blanket + parameter to my schematic, and now I want to create a net class from all of the nets that lay within the boundaries of the blanket. Do I have to manually add all of the nets, or is there an easier way to do it? AI: Double-click on the parameter set object (labeled "HV" in your image) to open its properties dialog. In the right-hand panel click the "Add..." button and choose "Net Class". Then you can give the net class a name. This creates a net class for all nets inside the blanket.
H: Line termination for single-ended to fully-differential conversion I am trying to convert a single-ended signal from a sensor to a differential one by using THS4500 from TI. The output of the sensor goes through a buffer before being connected to the fully differential amplifier. There are two configurations that I have simulated and tested. or My question is, when is R5 (the termination resistor) necessary? From what I can tell, there is no difference in the output. AI: R3 is the input impedance to the virtual ground while R5 is in parallel, so logically from a unity gain voltage source with low impedance, R5 is redundant. I can't think of a good reason to use R5 on U4, as I assume you are choosing differential to send the signal over longer distance to improve CMRR. This assumes you have good signal integrity between signal and all grounds.
H: Switching a load using a 2N2222 transistor with a Wemos d1 So I have this... device... that draws about 0.1~0.2 A and requires 3.6 V. In the below schematic it's represented as a speaker. I want to be able to toggle the power to this device with a Wemos D1 mini (sadly, represented below as an Arduino since I can't find a Wemos in circuit-diagram.org). All is powered by an 18650 shield that outputs both 5 V and 3.3 V. Since a Wemos D1 pin can only handle about ~12 mA I need to use a transistor to switch the required 0.1~0.2 A. Here's what I've come up with: My 'reasoning' is: I need a 4k7 resistor to limit the current from the datapin (D4). I see 4k7 everywhere so... I guess that'll do? I was planning on using a 2N2222 (but I have others) as my 'switch'. This should drop around 0.6 V, leaving 5 V - 0.6 V = 4.4 V? This is a bit on the high side I'm afraid. Using the 3.3 V is going to leave 2.7 V for the switched load, which is too low. My main question is: What can I do to get close(r) to the desired 3.6 V without using a ton of components? Add a dropper diode or two? Second: will this work at all? Does my reasoning make any sense at all? (The device/load is a gag-birthday card which plays music at a rather annoying volume; it comes with 3 LR1130 batteries, 3 x 1.2 V = 3.6 V and using my bench supply I measured it using about 100 ~ 200 mA - I just want to control when it plays. It still plays when I lower the voltage, all the way down to 1.8 V but then it's barely audible - below 3 V is not gonna cut it, I'm afraid). AI: You can on have your load on the emitter side when your base voltage is a max 3.3v from the wells. Try this...
H: Changing opamp reference in linear power supply not giving expected results I am currently working to make a 30V 5A linear power supply and came up with this circuit so far. The circuit is supposed to give twice the reference voltage Vref. This is the output voltage that I am getting which is the expected output. But to be able to achieve 0V(or very close to 0V) at the output, I decided to take the output voltage as reference for the opamp supply voltage and the reference voltage(Vref). This is the circuit that I came up with to achieve this. This is the output voltage that I am getting. Changing the reference voltage(Vref) has a negligible effect on the output in the second case. In first circuit everything works as expected. What mistake am I making here? AI: How can you drive the ballast transistor with a voltage that can not be higher than 12 V (output of op-amp -> base of Q2) (first picture)? EDIT : As @VictorTito pointed out, it is (arguably) better if the op amp power supply is "fixed" and not floating ... Ok, I haven't done a full stability study in this case. This may have "advantages"? Seems that the emitter of Q2 would return to the ground, with some resistor between the Q3 base and Q2 collector. More effective. example of behavior, but not very linear. Another example... more interesting and "linear".
H: Slayer exciter doesn't work I know that similar questions have been asked here, but none of the answers seem to work for me. Also, I am new to this site, and I am not much of an expert when it comes to electronics, so feel free to tell me if I forgot any important information, or if you need more information and want me to probe at a specific point in the circuit. I built a Slayer exciter circuit, using the schematic Electroboom used a few years back. Even though I checked my connections a hundred times, I still can't get it to work. I used a transistor of the type BC637, a diode rated for 1 A, and a self-made inductor. I used an iron nail as the core and wound around 500 windings around it. Its inductance is 26.8 mH. My primary is a piece of thick wire with 6 turns. I made the following observations: Nothing oscillates. Wherever I probe, I see no oscillation. At the base of the transistor, I measure around 0.7 V, more or less, depending on the resistor. If I disconnect the secondary, probe around it, and quickly close the connection between the base and the resistor, I do see a spike down to around -1.2 V, but if I connect the secondary and do the same thing again, the voltage just goes up to the value of 0.7 V because of the resistor being connected to +. Any help of what I could do to make this thing work and light up my fluorescent lamp would be greatly appreciated. ADD: It works! I made a new coil with a ferrite core, made around 400-500 windings. The primary is now 4 windings. The resistor is 10kO, and everything works perfectly fine, a CFL close to the end of the secondary lights up. AI: Iron nail shorts your transformer by having substantial eddy currents. Iron nail can be a good core for DC electric magnet but transformer cores cannot be made of solid conductive material. Try it with no core. Entertainment sites are not anything that should be believed. I guess you have believed one. ADD due a comment: A ferrite core which is intended to be used in inductors or transformers in the operating frequency works. Ferrites are insulators, so there's no eddy currents. They work as coil inductance boosters due high magnetic permeability. A transformer with a core made of right ferrite material can have superior performance when compared to a coreless transformer. There exists hundreds of different ferrite materials. Many of the are useless in transformers and inductors. Some of them are designed to attenuate unwanted radio frequency noise emissions by causing losses via complex molecular resonances. You may see them as blocks around power supply- and computer device interconnection cables, for example. Others (as useless for inductors and transformers) are designed to distort the propagation of microwaves in a well controlled way in GHz range components.
H: Positive edge reset and negative edge reset I am new to Verilog and I am trying to implement an asynchronous reset. I have difficulties understanding the difference between using always @ (posedge clk or posedge reset) and always @ (posedge clk or negedge reset). What are the differences between them and which one should I use to implement the asynchronous reset? AI: Posedge reset reacts on positive edge of reset signal, that is transition from 0 to 1. Negedge is transition from 1 to 0. Which to use depends on whether the reset signal is active high or low. If it is active high (reset=1 means it should reset), you need to react on change from 0 to 1.
H: Is there less noise in an E-MOSFET than in a D-MOSFET and if so, why? Since there is a threshold voltage needed to switch on a E-MOSFET, as compared to no threshold voltage needed to switch on a D-MOSFET, I would deduce that a E-MOSFET has lower noise than a D-MOSFET. Is my reasoning correct? Is there less noise in an E-MOSFET than in a D-MOSFET, and if so, why ? AI: Since there is a threshold voltage needed to switch on a E-MOSFET, as compared to no threshold voltage needed to switch on a D-MOSFET..... That isn't correct... For any MOSFET, there is always a gate source threshold voltage. That threshold voltage is the voltage required between gate and source that typically causes a small amount of drain current to be conducted. Some MOSFETs might use a drain current of 100 μA and others might use a drain current of 250 μA as their reference point. Others may use some other lowish value. Either way, this small (but not zero) drain current is the value at which the gate-source voltage is defined as \$V_{GS(THRESHOLD)}\$. Take the BSP29 from Infineon as an example. It is a depletion-mode, N-channel MOSFET and, in its data sheet, you'll see this: - And, if the gate-source voltage falls more negative it turns off even more: - And you can also see this in the table above. Look at drain-source cut-off current. With \$V_{GS}\$ at -3 volts, drain current is typically 0.1 μA with 240 volts DC between drain and source i.e. it properly turns off with the correct control voltage on the gate. And, you can take the gate-source voltage to even more negative values. This device has a limit of -20 volts. I would deduce that a E-MOSFET has lower noise than a D-MOSFET. Is my reasoning correct? Is there less noise in an E-MOSFET than in a D-MOSFET, and if so, why ? If there is "less noise" in an E-MOSFET than a D-MOSFET, it has nothing really to do with threshold voltages. Both have threshold voltages.
H: Valid Use of Voltage Divider Supply? I know it's not a good practice to use a voltage divider as a power supply, but I'm considering it for an unusual circuit. Is this a good use of a voltage divider or is there a better way to do this I'm not considering? This is a latching power shutdown circuit. The purpose is to power down the device after it is idle for some time to avoid battery drain. It is triggered via the IDLE_SHDN signal, 3.3 logic level coming from an MCU. The MCU itself and all voltage rails power down when this is triggered. The mosfet pulls down on the SHDN pin of a LT4356CMS-1, which is upstream of all power supplies, resulting in a total powerdown of the entire board. If I read the datasheets correctly, both the latch and mosfet gate current needs are very low, so I can get away with just a voltage divider to power them. The other main consideration is the supply line is really unstable: The input line VIN is coming from a battery that is connected to an automotive alternator. When the engine is not running the power is 12V (though I allow as low as 9 for my circuits) - this is the scenario when the idle shutdown is needed, when it is running it's very noisy around 15.5 volts. I'm using a TVS diode (SMBJ15CA-C78410) with 16.7V breakdown and 24.4 clamping to protect VIN from transients. My main concern is whether the voltage divider will have enough power to drive the mosfet while staying in the range needed so the latch doesn't get killed by transients when the engine is running. One question is do I correctly read the NOR gate datasheet that the output voltage may be lower than the input? Update Based on feedback, here is the design using an automotive LDO with latching enable. I added in the reverse battery/transient circuit it works with for reference since there were some questions in that area. I ultimately decided to have the TVS kick in at a much higher level based on brhans' concern. I feel much better that this design will be safe in a much wider range of conditions. AI: No matter what you're doing, you want a capacitor on your VCC. This would already go far as to stabiliing the supply. Otherwise, you'd need to source the full gate charge current through your 90 kΩ resistor, and that current can be very high, even if just for very shortly. The rest of your arguments are all actually against a simple voltage divider, not quite sure why you think saying "my input voltage fluctuates so that a linear divider fluctuates, too" suggests that said divider is a good idea. So, honestly, use sufficiently much capacity on VCC to begin with. Then, calculate how much energy charging Q5's gate might take - and compare that to the energy in your capacitor. Rule of thumb: if that is two orders of magnitude larger, you're fine; you can ignore the current through R72 for the duration of charging Q5's gate, it will be negligible in comparison. Calculate how long it will take to charge your capacitor through your R72. I bet it's longer than you actually want to wait. Most likely, you'll end up realizing that a 10 or 100 nF capacitor and a cheap linear regulator is simpler, and more space / work / partcount efficient. Most linear regulators come with very low standby current consumption (hint: try to not use regulators that start with LM31x or LM8xxx, these are from the sixties). Many even come with an (inverted) enable pin that you can use to even further reduce power consumption. This might even completely obsolete your whole U31/Q5!
H: Sony HiFi STK 403-130 Question I am going to separately use sony HiFi stk 403-130 amp circuit. In the below image, I marked numbers in RED 1 - What voltage 5/9/12 DC/AC should I input to run number 3 Relay. 2 - What voltage 5/9/12 DC/AC should I input to mute sound. AI: 1 - What voltage 5/9/12 DC/AC should I input to run number 3 Relay. If reusing the same relay then either measure what voltage activates the coil or figure out the part number and find the data sheet. If a brand new relay.... Firstly, choose an appropriate relay that has a coil operating voltage to suit your needs and has a limit of much less than 50 volts (that's the rating of Q488, the 2SC2785 transistor used in the design). You do need to check on contact wetting current and, if in doubt, choose a sealed relay that guarantees operation down to a few tens of microamps of current. But you also need to choose a relay that can operate with several amps of current passing through the contacts and, choose one that has low degradation on those contacts over time. It's not easy to figure out and certainly, without a definitive specification of the amplifier's output drive capabilities, it's something you'll have to research. 2 - What voltage 5/9/12 DC/AC should I input to mute sound. The answer above is the same.
H: SOIC-8 package size error I designed a PCB using both NE5532 and OP177 opamps. In principle both opamps are in SOIC-8 packages. However when I received the opamps, I found the NE5532 are much larger than the footprint they were designed to have on the PCB (using the KiCad SOIC-8 3.9x4.9mm footprint). If I measure the width of the NE5532 it appears to be wider than 5mm, while the datasheet says it shouldn't be wider than 4mm. What has gone wrong here? Have I made a bad assumption somewhere? Or is this a faulty package? The NE5532 I ordered is this, and the OP177 is this, both from Mouser. Here's the OP177 (top) and NE5532 (bottom), both in "SOIC-8" packages: AI: This is the NE5532APSR dimensional drawing from its data sheet: - This is the OP177GSZ dimensional drawing from its data sheet: - Can you see the difference now?
H: Why are we able to ignore the henries, Hz, farads, siemens and ohms when calculating the characteristic impedance of a transmission line? I have seen calculations, and every time we just take the coefficents of these values and end up calculating a simple complex number. The units all equate to various exponents of area, second, metre and kg, but they do NOT cancel out. Also as we have a root, which complex number is the actual answer, is it dependent on context? $$=\sqrt{\frac{R + 2\pi f L j}{G + 2\pi f C j}}$$ AI: At DC, the characteristic impedance equation becomes: - $$\sqrt{\dfrac{R}{G}}$$ Because G is the inverse of resistance we can say it is the inverse of ohms so, when you analyse the above formula it becomes: - $$\sqrt{\text{ ohms}^2} = \text{ ohms}$$ At high frequencies, the characteristic impedance equation becomes: - $$\sqrt{\dfrac{L}{C}}$$ And, if you did dimensional analysis it would be in ohms. Inductance is dimensionally \$M^{+1}\cdot L^{+2}\cdot T^{-2}\cdot A^{-2}\$ Capacitance is dimensionally \$M^{-1}\cdot L^{-2}\cdot T^{+4}\cdot A^{+2}\$ Divide inductance by capacitance: \$M^{+2}\cdot L^{+4}\cdot T^{-6}\cdot A^{-4}\$ Take the square root: \$M^{+1}\cdot L^{+2}\cdot T^{-3}\cdot A^{-2}\$ Dimensionally that is resistance in ohms. Image from IsaacPhysics.org. But what about middling frequencies where all four transmission line parameters are involved. If you take into account that Inductance is multiplied by \$j\omega\$, the dimensions for \$j\omega L\$ are these: - $$M^{+1}\cdot L^{+2}\cdot T^{-3}\cdot A^{-2}$$ Note that \$T^{-2}\$ has become \$T^{-3}\$ because of the dimensions of frequency. Now, if that is multiplied by 1/G (for example) we get ohms multiplied by \$M^{+1}\cdot L^{+2}\cdot T^{-3}\cdot A^{-2}\$. This equals: - $$M^{+2}\cdot L^{+4}\cdot T^{-6}\cdot A^{-4}$$ And of course, by inspection this is dimensionally ohms squared. You can try the same with \$R\$ and \$j\omega C\$ but, you'll find the same. Any of the more complex "middle frequency" terms resolve dimensionally to ohms when square rooted.
H: Where is my capacitors energy missing? To avoid "mistakes", may I recall that, mathematically, \$\infty \times 0 \$ can be ... finite! Otherwise, why use a Dirac impulse? After reading this and this, I have yet a "question" about the energy stored in a capacitor and transferred to another capacitor of the same value to simplify "calculus". Mathematical answer given by user150526 "May 22 '19 at 8:12". But why is (s)he right ? Without any doubt. (When the wire is "resistive") I have one capacitor C1, which value is 1uF, charged at voltage 100 V. I have another capacitor C2 also of value 1uF which is discharged (V=0). After wiring in parallel these capacitors, the common voltage is 50 V, no doubt. While calculating the energy before wiring (C1), and after wiring (C1+C2), I find that the total energy is not the same. I have lost half of my energy which is "disappeared". Where is this energy? Because energy can't be lost! But how can I prove this, simply? I "forget" the case if the wire can be considered as an inductor. So I made a simulation with a "theoretical" switch. And the transfer of energy can be done, almost with total efficiency. Thanks also for a suggested proposal (from @bobflux) of superconducting wire between capacitors (wire as inductor). Very interesting as "superconducting wheel"? AI: The circuit has ideal wires (in fact, everything is ideal) so there is no resistance, and no inductance. Therefore, when the switch is closed... If voltage on both caps is different, infinite current will flow from one capacitor to the other, that takes zero time, and after that, charge is equalized and half the energy has disappeared. This is simply due to the model being too simple and unrealistic. It is like the collision of two rigid bodies. If they are infinitely rigid, then when they bump into each other, an infinite force will be involved during zero time. If you want to solve it, I'd recommend adding a resistor of known value R in series with one of the wires, then solve the differential equations and calculate the energy state at t=0 and t=infinity. Notice it does not depend on the resistance, no matter how small it is, it will always burn half the energy. So asymptotically, even if the resistance is zero, it will still burn half the energy. OK, let's use superconducting wires, then. No resistance, but there is inductance. This one is realistic enough: it is an undamped LC tank, and when the switch is closed, it will resonate forever. Total energy in the circuit is constant, it just moves around between inductor and capacitor. This circuit never reaches steady state, so you can't calculate the limit on this one with L going to zero to get back to the first circuit. In a real circuit, energy would still decay due to the electromagnetic waves emitted by the circuit as AC current flows through it, and it would eventually reach steady state, with half the energy lost. Energy loss due to emitted waves is quite like adding a lossy element, for example a resistor, to the circuit.
H: BJT Amplifier Simulation I am trying to build a simple CE amplifier for an AM signal as part of a home-brewed transistor radio. I would like to have a working simulation before I get a breadboard. My simulation works in small time-steps but not large time-steps and I have no idea why. Falstad Simulation Before you make fun of my mistakes, I am a hobbyist and BJT biasing is very confusing to me. I chose fixed bias topology because it seemed the simplest. What am I doing wrong with this simulation? Any advice/rules of thumb I can incorporate? EDIT: I have built the first BJT stage on a breadboard following the exact schematic as shown. My expectation is that the first BJT stage should giving me a larger amplitude RF signal whose frequency is equal to what my antenna would pick up (AM radio stations in the range of 500khz-1.6Mhz). I am probing ground to the output capacitor with a multimeter and get no voltage, AC or DC. All I have on the breadboard is: VCC/GND wires from 5V power supply The first bjt stage (same as schematic) A 3' length of wire->10nf input cap->base of BJT (2n2222) Another 3' length of wire that is plugged directly into ground to make a dipole antenna I probed between emitter pin of BJT and ground, 5V DC. Base pin of BJT to ground: 2.5V DC. Collector pin of BJT to ground: 2V dc. Collector output cap to ground: 0V AC or DC. Antenna side of input cap to ground: 0V AC or DC. However, I am using an analog multimeter and do not think it would pick up a few mV of antenna signal. Is my transistor biased wrong? Should base to ground voltage be closer to 1V? Are my input/output cap values the wrong magnitude for 500khz to 1.6Mhz? Did I take the simulation out of context? AI: My simulation works in small time-steps but not large time-steps and I have no idea why. The transient simulation must run with small time-steps so that the AM carrier frequency has many time samples. If the AM signal source has a 1 MHz carrier frequency, then time samples should be separated by no more than 0.5 microseconds, otherwise you violate sampling criteria. I would use finer time steps, something like 50 nanoseconds for an AM carrier frequency of 1 MHz. The AM diode detector after the amplifier re-generates the AM modulation on the carrier. To see this waveform, the simulation must run for a long time.... For example, if the AM modulation is 1 kHz, the simulation must run for at least 1 millisecond to see only one cycle. If your modulation is 100 Hz, you need to run for at least 10 ms. On the one hand, you need fine time steps to properly sample a high-frequency carrier - on the other hand, you need many of those consecutive samples to see the result of the AM detector. The simulation run takes a long time to complete when the carrier frequency -to- modulation frequency ratio is large - there's no way around it. For complex waveforms having many frequency components, a simulator's guess at appropriate time-steps may err on the too-long side. I don't know how Falstad sets time-step default. Oscilloscopes are similarly poor at guessing time-step size. The general rule is to choose a time-step shorter than half the period of the shortest wavelength that you expect to encounter in your circuit. An accurate simulation of an oscillator would want a much shorter time-step.
H: Input resistance of a non-ideal op amp OP1 has a finite input resistance, but an infinite open loop gain (other parameters are also ideal). The other two op amps are ideal as well. Can I still assume that there is a virtual ground between the positive and negative terminals of OP1 and the input resistance (Rin in the schematic) is actually R1? It's a pretty basic question but I want to know if my assumption is correct. AI: Can I still assume that there is a virtual ground between the positive and negative terminals of OP1 ... With negative feedback as shown the output will adjust until OP1's inverting input is very close to that of the non-inverting input. Since the non-inverting input is physically grounded you can assume that the inverting input is virtually grounded. ... and the input resistance (Rin in the schematic) is actually R1? Correct.
H: How to derive the below equation First, I would like to verify is the circuit I drawn correct? Rin is consider large enough to be negligible in the equation. I tried using KVL to obtain 3 equation as below, considering to get vth and Isc so Ro=vth/Isc $$-v_i+i(R_1+R_2+R_{out})+A_{vo}V_d=0$$ $$-v_i+iR_1-V_d=0$$ $$v_{th}=v_o=iR_0+A_{vo}V_d$$ and $$I_{sc}=\frac{v_i}{R_1+R_2}+\frac{AV_d}{R_{out}}$$ $$v_i=\frac{v_o}{A_{cl}}$$ where $$A_{cl}$$ mean close loop gain I been substituting Vd in terms of i,R1 and Vi but the equation only become very complicated and I don't see anyway of getting the above equation. Is the equation I formed correctly? Also is there a much simpler method to get the output resistance? AI: It's probably better to use the dependent voltage source, as you did. But I'd infer it mentally and keep the schematic more like this: simulate this circuit – Schematic created using CircuitLab This allows me to quickly set up four equations and four unknowns. The purpose of \$I_{_\text{O}}\$ is to allow me to inject a current. I'd set it to \$0\:\text{A}\$ and then \$1\:\text{A}\$ and measure the difference of \$V_{_\text{O}}\$ (and divide by 1, the obvious change in current.) Keeping all this in symbolic form can be handled easily with SymPy. So that's my recommendation. Please note that in your paper-written diagram, you've not labeled the node between \$R_1\$ and \$R_2\$. I don't know if that's an oversight or if you are fully aware, but just didn't say anything about it. And I don't see how you can move towards the solution you show without it clearly named. var( 'vi vo va ia r1 r2 rout vm avo io' ) # list needed variables eq1 = Eq( vm/r1 + vm/r2, vi/r1 + vo/r2 ) # KCL for VM eq2 = Eq( va, -avovm ) # opamp open loop voltage gain eq3 = Eq( vo/rout + vo/r2, va/rout + v/r2 + io ) # KCL for VO, with injection IO current eq4 = Eq( va/rout, vo/rout + ia ) # KCL for VA, with opamp output current ans = solve( [ eq1, eq2, eq3, eq4 ], [ v, ia, vo, va ] ) vo0 = ans[vo].subs( { io:0 } ) # VO without injected current vo1 = ans[vo].subs( { io:1 } ) # VO with injected 1A current pprint( simplify( vo1 - vo0 ) ) # Print output resistance rout⋅(r₁ + r₂) ─────────────────────── avo⋅r₁ + r₁ + r₂ + rout The above is exactly equivalent to your given correct answer. This can be tested in the following way: n = rout(r1+r2)/(r1+r2+rout) # ROUT \|\| (R1 + R2) d = 1 + r1avo/(rout+r1+r2) # 1 + R1Avo/(ROUT + R1 + R2) pprint( simplify( n / d ) ) rout⋅(r₁ + r₂) ─────────────────────── avo⋅r₁ + r₁ + r₂ + rout Their answer is correct and the approach shown above is soundly reasoned in getting to the same place.
H: Power rating for a 2 ohm resistor on the input power rail of a 5V DC circuit I'm working with a surface mount IC in an SOP-8 package. The IC handles LIPO battery charging at up to 2.1A. It also provides an integrated boost converter with 5V, 2.4A output. Below is an image of a prototype I built that works fine using through-hole components. Now, I want to rebuild this circuit with all surface mount components which are as small as possible on a PCB. In the example circuit shown in the IC datasheet includes a 2 ohm resistor in series with a capacitor on the USB charger input power rail, the resistor is shown as R1 in the schematic. The "VIN" in the schematic represents the IC power input at the #1 pin. The question is around the resistor R1. Firstly, I'm not sure I even need to use it? Is the purpose of this resistor just to drain the bypass capacitors? Secondly, if best practice would be to use the 2 ohm resistor here, what is the appropriate power rating which I must choose? The voltage source will be a standard consumer-grade 5V ac/dc converter with 1A to 3A output, going to a micro-USB input. In the prototype shown in the picture, I used the large through hole resistor rated at 3W, and it seemed to work fine, at least in the runtime testing as long as 8hrs, it never got hot to touch. In moving to surface mount components, 2ohm resistors with such high wattage ratings are both large and expensive. I'd prefer to eliminate it due to PCB size constraints and cost. simulate this circuit – Schematic created using CircuitLab AI: There will be no DC current through that resistor, so unless there is something terribly wrong with the circuit or the supply powering this circuit, it will never heat up. The purpose of the resistor is not to drain the bypass caps, as there is no DC path to drain them. The purpose of the resistor and capacitor is to dampen transient voltage spikes that might happen when devices are hot-plugged together, for example there is an USB cable connected to a powered 5V source and then this charger is plugged in. The cable has inductance so the inrush current taken by the caps can cause large voltage spikes that are maybe enough to destroy or degrade the chrager IC, so it is better leave the RC damper in the circuit than remove it. Since the resistor is just a part of an RC filter, it means there will ever be max 5V over the resistor, and thus max 2.5A current spike running through the resistor, which means max power dissipation is 12.5 Watts. However, the capacitor will be approximately fully charged in 0.1 milliseconds, so the surge is very short. So technically, a resistor that can handle the large surge is needed. In practice, any standard SMD resistor could be used, as long as it can handle the momentary high current for extremely small amount time without acting as a fuse. The pulse load ability depends on resistor model, for example it might require a 1206 resistor that can normally handle 0.25W to handle a short pulse load of 12.5W.
H: What is this symbol that looks like Ø on a schematic? I'd like to ask about this "empty set" like symbol with a diagonal line through a circle, as shown in the picture below. I have found it in an old electrical schematic. What is it exactly? AI: Those are terminals. Usually they indicate where external devices are connected to a board or panel and also for inter-connections between boards or panels. In this case I would expect that devices 17 and 2 are wired to terminals (screw or solder-post) on the main assembly.
H: TTL voltage drop I recently bought a lot of TTL components like 8-bit registers, bus transceivers, etc. to build an ALU and 2 registers. My issue is that when I build a register, the voltage drops to 4.2, sometimes even below 4V even though I put resistors in every output in series with the LEDs. I built 2 8-bit registers with bus transceivers using 74LS377N for registers and 74LS245N for bus transceivers. These two registers are built on different breadboards. And I connected the power to the bottom breadboard and wired the bottom breadboard to the other breadboard to provide power to it. The problem is that voltage drops significantly across these 2 breadboards. Then I tore it all apart and individually tested the TTL components to see what's gonna happen. I powered up the breadboard and connected the two power lines on the sides. I put an 8-bit register and then only connected the power and the ground pins, leaving the rest disconnected. Then I saw the voltage drop below 4.5V from 5.1V. And I had like 6 of these registers so I tested them all. Some of them dropped to 4.9V and one of them didn't drop at all. But mostly they dropped below 4.5V. What am I missing? Or is there something I don't know about or I'm doing wrong? I'm kinda new to this so every bit of knowledge is appreciated :) EDIT: Later, I went on to try this on other logic gates like 7400, 7408, etc., and saw that they behave like this too. Most of them drop the voltage, and a couple of them keeps it the same. I feel like it's about the logic gates I bought. But I have like tens of them. EDIT: The alu I'm building is the one that Ben Eater built in his video, here is a screenshot. I built the exact same circuit but the LEDs that are at the bottom, which are the ones that are farthest away from the power supply, barely get any current. And I have checked everything like 10 times over the past 2 weeks. AND YES I have connected everything as Ben Eater did, except he was using some LEDs with built-in resistors so therefore I added 220 ohm resistors in series with the LEDs. But besides that, everything is the same. AI: TTL requires a +5V DC supply having less than 5% variation (from Texas Instruments 74LS00 data sheet): Measure your 5V supply voltage with no connection to breadboards, nor to anything else other than your voltmeter. Then measure your 5V supply voltage when connected to TTL chips on breadboards. Both measurements should lie within the range of 4.75 to 5.25V. You might make a further check by measuring at each TTL chip: measure from its Vcc pin to its GND pin...this DC voltage should also be within the range of 4.75V to 5.25V. If your measurements are outside this range, then you need a stiffer, better regulated +5V supply. It is also possible that voltage drop along wires connecting chips to the supply have too much resistance or are too long. Andrew Morton mentions that OP's photo is Ben Eater's version of the ALU. I'm amazed that there are no Vcc-to-GND bypass capacitors! Wow, I'm surprised that such construction works reliably. Not only should a multimeter show Vcc voltage to be near +5V, but an oscilloscope should show no short-term variations of that +5V. Bypass capacitors are meant to smooth any variations. You'll often see a 0.1uf capacitor connected from Vcc-to-GND at each TTL chip:
H: How to add a flyback diode to protect a relay on another PCB that does not have a flyback diode I have a PCB (SEPARATE PCB) that I want to test by building up a "Test PCB". The test will involve switching the relays. This PCB (SEPARATE PCB) has a few relays on it, however, they do not have any flyback diodes on it. I am using an Atmega32 to turn on an IRL540 logic MOSFET. I thought by applying a flyback diode across a resistor and an LED on my Test PCB then the voltage spike can be suppressed through my Test PCB instead of the SEPARATE PCB that does not have a flyback diode. D3 is a 20V Zener diode I am not PWMing the MOSFET, just using it has a switch. Is this method okay? If not how do I prevent the spike from the SEPARATE PCB using my Test PCB? I cannot tamper with the SEPARATE PCB, by adding components to it Before: simulate this circuit – Schematic created using CircuitLab After: simulate this circuit AI: Is this method okay? If not how do I prevent the spike from the SEPARATE PCB using my Test PCB? If you can't modify the relay board then you have fewer options: - A flyback diode as you have shown providing both 12 volt supplies are linked else... A Zener diode (rated at least 3 volts higher than your relay supply voltage) with cathode to M1's drain and anode to 0 volts. A snubber (a resistor in series with a capacitor) across M1 drain and 0 volts Note that R2 likely is too small in value for a standard LED. Circuit showing zener and snubber options: - Put the snubber (or zener) across the MOSFET as close to the MOSFET as you can. The snubber protects the MOSFET so, it should be closest to the MOSFET but, don't worry if it's an inch either way. A regular parallel diode with the relay (close up) keeps back-emf current local to the relay and, when placed further away, extends the back-emf current loop and can cause EM interference so, it's a compromise in not having that diode directly across the relay coil. Make sure that if you do opt for the diode to your local positive supply, that power supply should not be too much lower than the relay 12 volts else it'll keep the relay activated when the MOSFET is deactivated. Given all of this, I favour a zener or the snubber. Watch out for wiring non-idealities that can cause relay or relay load currents to flow into the ATMEGA control and potentially reset it. That is why I suggest a star-point grounding arrangement.
H: Why does increasing torque on DC motor in circuit affect the speed and functioning of another DC motor in the circuit? I am working on a project in which there are system components listed below as module: 8 ultrasonic sensors 12-30 V (Sensor module) 3 DC motors (Drive module) 35 V to 5 V buck converter and a 35 V - 5 V isolated DC-DC converter (Power module) 1 Microcontroller (Controller module) 2 Encoder (Encoder module) Let me explain the required functioning of the module. I am using a LiFePo4 battery (26.5 V, 18 Ah) for powering the PCB and I have isolated the sensor module and drive module using optocouplers for the safety of my microcontroller. The motor module optocoupler uses 5 V logic and the sensor module optocoupler uses 3.3 V, so the sensors gives signals to the controller through an optocoupler and then the controller gives a signal to the motor driver through an optocoupler and the motor runs accordingly. I am using a buck converter circuit to convert incoming power from the battery to 5 V that it can deliver to the motor side optocouplers and I am using another isolated DC/DC converter circuit to convert the battery voltage to isolated 5 V to power up the microcontroller. My microcontroller can source 3.3 V to the sensor optocoupler circuit and direct power from the battery is going to the power sensors and the motor driver; there is no regulation or any other circuitry. Let me attach details of components: Buck converter IC 35 V - 5 V MC34063 Isolated DC-DC converter Hi-link 18~36 V to 5 V Microcontroller CC1350 Launchpad 2 low power Motor driver DRV8872 1 High power motor driver Cytron MD10C I don't have datasheets of the sensors, motors, and encoder right now but I remember some current ratings: Each sensor's current output is 100-200 mA; operating volatge is 12-30 V High power motor continuous current which I have noticed is 2-3 A but at some places when it require more torque it reaches 4-4.5 A and the operating voltage is 20-30 V Low power motor of which are are two each normally take 500 mA; at some places when they require more torque current reaches to 900 mA and the operating voltage is 20-30 V My question: when I test the whole system on the bench, and there is almost no torque compared to normal operation, when I then try to put torque on the high power motor, why do both low power motors start behaving abnormally? They start running with a jerky motion. I have placed a LED on the input from the controller to the driver, that LED also flickers so it seems the motor driver gets a similar signal from the controller I put torque on the high power motor. I want to know why it is happening even though the circuit is isolated (24 V <> 5 V). Let me share the circuit diagram: AI: Why does increasing torque on DC motor in circuit affect the speed and functioning of another DC motor in the circuit? It looks like all three motors share the same power rail (VM) so, if one motor is drawing a lot of current the VM voltage may sag and reduce the speed on the other motors. If you want to avoid this then, make VM more powerful or, regulate VM with a sufficiently rated regulator to avoid droop. You can of course use individual regulators for each motors to help avoiding "crosstalk". Maybe you have some form of feedback that you can use for adjusting the control signals to the motors that are labouring on the diminishing VM supply?
H: 80% amperage rule for continuous loads? I'm trying to understand how an electrical load affects a circuit. Let's say, for example, I have a setup that is on a 120 V, 15 A circuit: 120 V x 15 A = 1,800 W max if we have a continuous load (3+ hours), then we should aim for 80% amperage; so 15 A becomes 12 A and 120 V x 12 A = 1,440 W max if we maintain a continuous load of less than 1,440 W, there is nothing to worry about if we ever reach 1,801 W, the circuit breaker turns off immediately to prevent any damage to the circuit My question is: If we have a system running continuously at somewhere in between (let's say 1,600 W), what happens? Does it do long-term damage to either the circuit or the electrical device(s)? Does it do short-term damage to either the circuit or the electrical device(s)? Does it make no difference at all until a new load is introduced that pushes it over 1,800 W? And does it make a difference whether the voltage or amperage changes? If we have 240 V x 20 A = 4,800 W max and 240 V x 16 A = 3,840 W (continuous), and we run the system somewhere in between (like 4,200 W continuous), would the same concept apply (ie, same level of damage/non-damage) or would it be less or more damaging due to more power being involved? Edit: Thank you for all your answers. I regret being able to only vote 1 answer as being correct. :[ AI: Assuming that this is someplace where the US or Canadian electrical codes apply, a 15 amp circuit is designed to be loaded at 15 amps 24/7 with no damage and only long-term (many years) deterioration. The 80% rule says that no individual load shall exceed 80% of the branch circuit current rating. That reduces the probability of nuisance circuit breaker tripping. Nuisance tripping may tempt users to use extension cords on a continuous basis or otherwise engage in less safe usage practices. Here is a trip curve for typical residential circuit breakers in the US.
H: Asynchronous generator - Is the calculated stator current here phase current or line current? Please see the below circuit schematic for an induction (asynchronous) generator. I have a delta connection, with a voltage = 380V, so phase voltage = line voltage = 380V Then I calculate the stator current: I_stator = Voltage/Z_overall = 380V/Z_overall Ohms Is this calculated stator current, phase current or line current? AI: Three phase machines are analyzed using one phase of the equivalent circuit for a wye-connected machine. The calculated stator current is the line current for the wye equivalent of the actual delta-connected machine. The stator voltage is the line-to-neutral voltage of the equivalent wye-connected machine. To get from the equivalent circuit shown to the actual machine, you need to multiply the VA at the terminal by three and then determine the parameters you need for an equivalent delta-connected machine. Re comments: If the circuit given is the equivalent circuit to be analyzed for a 3-phase induction motor rated 380 volts, Vs1 would be 380/sqrt3 or 219 V. Thestator, rotor and magnetizing branch impedances should be the per phase values for the wye equivalent of the given machine. The stator current would be the line current for the wye equivalent of the given machine. If the motor is operating as a generator, the slip is negative and that would result in a negative value for the portion of the rotor resistance (R2[1-s]/s) that represents mechanical to electrical power conversion. I assume that would result in a negative value for the rotor impedance, the overall impedance at the terminals and the stator current. If the equivalent circuit is adequate to completely analyze the machine acting as a generator, the machine rotor should appear to be a source for real power. The magnetizing branch should appear to be an inductive load for the electric grid source to which the machine is connected. Here is a related problem worked out:
H: BJT astable multivibrator frequency increasing with voltage I'm trying to get a 27V 120Hz square-wave, so I tried this circuit : I get a decent 128Hz signal with 9V, which is close enough. However, if I increase the input voltage past a certain point, the frequency increases too. For 27V, it is about double, 250Hz. I get no such increase in LTspice simulation so I guess it is due to some real-world physical limitation of the components. What is happening and why? Can I/should I use such a circuit with 27V or is it too high? AI: The reason is that during switching cycles, the base of each NPN is pumped below ground. Most NPN base-emitter junctions will break down and degrade with 6-9 V reverse bias. LTSpice and other simulators don't simulate this breakdown. This is why simulation results are different from measurement. For 27 V output, it's best to run this from 6 V, and then amplify to get 27 V. You can do that with another NPN driven from one of the collectors with about 10 k. This will also isolate the oscillator from variable loading effects of the 27 V signal. Your NPNs may have been slightly damaged by running at 27 V. You could instead replace the 47 nF with 10 nF and connect 47 nF from each NPN base to ground. This will attenuate the 27 V signal by about 5x and 'save' the NPNs. The frequency will now depend on (47nF + 10 nF).
H: How does a power plant's increased output translate to the Volts, Amps and Watts on the power lines? In the context of a power plant, that wants to output more electricity. If the formula for Watts is VA=W, does Voltage or Current get increased to supply more Watts? AI: How does a power plant increase load? Power plants do not increase load, the customer's served control the load by turning things on and off or adjusting loads to use more power. A power plant connected to a grid can supply a larger share of the load. Viewed simply, the plant does that by increasing its internal voltage to be slightly above the voltage at the grid connection. The grid voltage remains constant, but the current and power supplied by the power plant under consideration increase. I know the formula for wattage is VA=W. For an AC power plant, that is not true. The phase relationship between the voltage in current must be considered. That means that W = V * A * pf, where pf (power factor) is a number between 0 and 1 that accounts for the phase relationship. A power plant could increase power delivered without increasing current by increasing pf.
H: Will this power supply be able to power raspberry pis I don’t know if this is the correct place to ask but I was wondering if this power supply will be able to power 4 raspberry pis. Here is the link: https://m.aliexpress.com/item/32946637768.html?spm=a2g0n.shopcart-amp.item.32946637768& I’m planning on making a pi cluster and I want to power the pis with some sort of power supply. I don’t know if this will work but if anyone knows of any other good power supplies, let me know. Thanks!!! AI: No .
H: NPN transistor resistor from base to GND. Is this useful? I have a circuit where many NPN BJTs are interfacing 3.3 V GPIOs with higher voltage circuitry. Each application has a similar setup to the image below (resistor R422 is what's in question). I did this myself, but I am not sure where I got the idea to add resistors from the base to GND, and someone recently inquired about this and I couldn't give a good answer. Do these resistors serve a purpose? As a side note, these transistors are being used for simple on/off purposes and are not on fast data transmission lines. AI: Depending on the MCU, its IO pin may be tri-state at power up (or reset) until it is programmed to either a '0' or a '1'. If it is tri-state, small amounts of leakage (on the transistor, pin, or PC board) may be amplified by the transistor and cause detrimental leakage on the collector. When initialised, the IO pin will generate a good '0' or '1' and the resistor has negligible effect.
H: Circuit to convert a pulse signal to square wave How can I convert a pulse signal into a square wave. I have a pulse signal created using a Function Signal Generator, ZK-PP2K Pulse Frequency Generator 8A Driver Module LCD Pulse Frequency Cycle Module 1Hz-150KHz Motor Controller LCD Display https://www.amazon.com/Function-Generator-Frequency-1Hz-150KHz-Controller/dp/B08HV2FPJR Specifications: 1>.Product name: ZK-PP2K PWM Signal Generator 3>.Work voltage:DC 3.3V-30V 4>.Frequency range:1Hz~150KHz 5>.Frequency accuracy:2% 6>.Duty cycle range:0.00%-100% 7>.Output Current:8A(Max) 8>.Number of pulses:1~9999 or Infinite 9>.Delay time:0.000s~9999s 10>.Pulse width:0.000s~9999s I watched a video that uses simulink to create a model that does this. https://youtu.be/m6aw6HcIbPc How can I convert this simulink example into a "workable" circuit. My thoughts were to use a combination of an op-amp and bridge wave rectifiers but I think I'm over thinking it since I already have the pulse generated. Any thoughts? AI: Detail of the waveforms you require: - So, what you want is an output that flips each time the input pulse rises. This can be achieved with a D type flip flop like this: - Image from here. How can I convert this simulink example into a "workable" circuit. Of course you need to do other things to make a working circuit: - Power supply for the D type flip flop Power rail decoupling capacitor to ensure no glitches Careful layout to prevent EMI Unused pins on the D type flip flop tied to the appropriate power rail Connectors for input signal and output signal Maybe a 1 kΩ resistor in series with the output from the circuit to prevent careless shorts when connecting it to an oscilloscope. An input resistor to prevent significant stress on the circuit in case your powerful PWM driver is set up incorrectly. Maybe even an attenuator formed from two resistors. You can also use JK flip-flops. Here's two cascaded showing how you can take an input signal of frequency \$f\$ and reduce \$f\$ by 4: - Image from here.
H: AVSS pins in PIC18f46k80 I'm trying to use ADC module in PIC18f46k80 and I want to connect VREF- to AVSS. But the problem is that I can't find AVSS pin in this microcontroller: Is AVSS the same as VSS here? meaning I simply have to connect VSS to gnd? AI: That is correct. On the package types which does not have the AVSS and AVDD pins, they are internally connected to VSS/VDD.
H: Current versus voltage not exponential above forward voltage of diode? I have done a simple current over forward voltage simulation for a PN diode with LTSpice. I wonder why the curve is only exponential around the "knee-point" but it seems to be linear when going above that point. I assume that this is some effect that is modelled in the SPICE model because If I use a simple model that only models the diode with the two parameters Is and n, it seems there is no such effect. When I look into the 1N4148 datasheet, I see the curves are "saturating" on the logarithmic y scale -> is this the effect I observe in my simulation? If yes, what is the physical reason behind that effect and which SPICE parameter takes care of it? AI: I wonder why the curve is only exponential around the "knee-point" but it seems to be linear when going above that point. If I adjust RS (a model parameter for diodes), I get these curves using micro-cap and the 1N4148 diode model: - The shallowest curve is with RS at 0.65 Ω. The next steeper curve is with RS halved, then halved again, then halved again. Of some interest might be the log plot of current vs voltage over the full range from 0 volts to 1 volt applied: - The blue curve is with RS at 0.65 Ω the orange curve is a straight line reference. Blue is not too far away from the standard graph (shown in the question for the 1N4148). With about 0.5 volts applied, the standard graph suggests a current of about 100 μA and, this pretty much tallies with the micro-cap prediction. With 0.8 volts applied, the standard graph suggests a current of between 10 mA and 20 mA. Micro-cap comes up with about 30 mA. Not too shabby but, pretty dependent on the model parameters of course. It looks fairly linear (log displayed current) between an applied voltage of 0.2 volts and 0.8 volts (see orange marker line).
H: Controlling Relay using ESP8266 Module I have 5 such relays attached to an ESP-12E module with a 600ma Power Supply. The LED (LED4) glows but the relay doesn't switch. Is there anything wrong with my schematic? Using MMBT3904 instead of a BC848B and using a 5V sugar cube relay. AI: For comparison, as you have a drive of 3.3V max, see the difference of the relay current. Circuit 1 (left) is not really "the good choice". Here for a drive of 5V.
H: Why don't oscilloscope probes use twisted pairs? I was reading online about how Ethernet cables use twisted pairs instead of coaxial cables because it's better in some way. Some websites say that twisted pairs cost less, can carry higher frequencies, and filter out noise, cross talk, interference, etc. This website here says that "The wires are twisted together to reduce noise" and this website here says that twisted pairs provide "high data transmission rates" If that's the case, why are most oscilloscope probe cables made using coaxial cables? Maybe some advantage I'm missing out on? I thought oscilloscopes are supposed to capture a higher and wider range of frequencies than ethernet cables, so a better ethernet cable would be made up of coaxial cable. But after looking at the benefits of ethernet cables, I thought that the better oscilloscope probe cable would be made up of twisted pairs. Hence why I am confused right now. AI: If that's the case, why are most oscilloscope probe cables made using coaxial cables? Unless you have a specialist differential probe fitted on your o-scope input terminal, the input to the bare terminal is what is known as "unbalanced". This means that the input has a locally grounded reference terminal connected to the o-scope chassis. Coaxial cable is ideal for an unbalanced input but, it can be far from ideal when dealing with a balanced signal. Twisted pair is ideal for a truly balanced input. The scope input is not balanced (unless using a specialist probe) therefore it is far from ideal. An oscilloscope input is high impedance (a feature) and, twisted pair requires termination resistors (circa 50 to 100 Ω) for best performance at high frequencies hence, you also have a clash of requirements.
H: Identify PCB components from picture The whole pcb represent a filtering and amplification stage for an incoming analog signal, before leading to and A/D stage. reference: page 20 doi:10.1088/0967-3334/33/6/943 (I didn't want to post a reference that somebody might not have access to, but yes, it might be helpful) Since I am trying to reproduce the project from a picture, I am interested in understanding what components where used. My knowledge of the amplification and filtering stages is solid, but I am unsure on a few components, which I think to be safety/power management/interconnection related. In the original source, the succesive A/D stage is left unspecified. Here is the picture I am trying to identify 1 and 2. I think that 3 is the plug to the power line and 4 is the trimmer for a variable gain amplifier in the circuit. I am fairly sure that 5 belong to a circuit splitting the incoming 12V power supply in two differential 5V (to power the amplifiers of 7 +/- with respect to a reference); and 6 is an on/off button while 7 is the circuit implementing the actual function If you could point me in the right direction, especially with 1 and 2, it would be an amazing aid. Thank you in advance for you help, Kind regards AI: BNC connector (signal out) Isolation transformer DIN connector (power in) rotary selector switch (dipswitch) - probably gain select or something like that SMT electrolytic aluminum capacitors power ON/OFF rocker switch (most likely double pole) The only one that is not obvious from the appearance is the isolation transformer (other modules are sold in similar packages) and the ID is from the line in the paper: The other parts are the integrated circuits and other components that form the amplifier, as described in the paper. In addition (to the external medical power supply) "a transformer was used when the final output signal was sent to a data acquisition board."
H: Designing a pi filter (C-L-C) for the output of a TPS62740 buck converter We are using a TPS62740 IC as DC-DC converter. We are getting ripple at the output in the range of 10 mV to 12 mV, so we are thinking to add a pi (C-L-L) filter at the output of the DC-DC converter. As you can see, the peak-to-peak voltage is around 12 mV, but the frequency is not stable, varying by up to 100 kHz. The DC-DC converter switches at up to 2 MHz, V(in) = 3.6 V, we are operating with a small load (50 mA) and V(out) = 2.5 V. We want to design a pi filter for it. Please help me out with this problem. AI: These diagrams look like a regular PFM operation for me, especially after you've mentioned variable frequency. In my practice, there are two nice approaches besides passive filtering: If power consumption isn't critical - you may add a constant load at your output (fixed resistor) to shift the converter to the PWM mode. It will allow you to get a fixed frequency, plus often it will decrease ripple amplitude. Other part numbers often do have a dedicated "Forced PWM" pin, but with this one, I'm afraid it's the only option You may push your load point a bit higher (e.g., 2.6 V) and supply it to the 2.5V LDO with high PSRR, or even a voltage reference if the absolute value of the voltage matters (pay attention to the fact that for your output 25 mV is already 1% accuracy!). I've used such an approach for systems with capacitive touch, which are unpleasantly sensitive to such ripple, and with good LDO, it has higher efficiency compared to the first option In case these options aren't enough and you still need a passive filter - I believe any online calculator (e.g. this one) will do the job, the number of stages will depend on your specs (how much attenuation you'll need)
H: High-side current sensing questions: Gain formula and circuit type What is the formula for the gain in this circuit? I can not find a good description of the operation of this high-side current measurement. Why is there a PNP transistor at the output? What is the name of this configuration? This is the circuit from the datasheet of the bq500211: AI: I don't know if the circuit has a specific name but it sure is a type of current-to-current converter/amplifier: Generates a current proportional to the current-to-be-measured. This allows the designer to use a burden resistor to convert this current into a voltage for measurement purposes such as feeding to an ADC or using a ref voltage in a comparator. Basically, the circuit utilizes the properties of a closed-loop operational amplifier: The inputs of the op amp are at equal voltage. In other words, the differential input voltage is zero. The inputs don't draw current. Normally, R17 can be omitted but it's there to decrease the imbalance caused by the offset current of the op amp. Can be ignored for calculations. $$ \mathrm{ V_{IN}-V_A=I_x\cdot R21 \\ V_{IN}-I_L \cdot R7 = V_A \ \ \ \ (R17 \ is \ ignored) \\ \Rightarrow \frac{I_x}{I_L}= \frac{R7}{R21} } $$ So, the circuit generates a current proportional to the load current. The ratio is determined by R7 and R21. To convert this current into a voltage, R30 is placed as a burden resistor (assuming the ADC or the other circuit draws negligible current). So, the gain for this current-to-voltage converter will be $$ \mathrm{ V_x=I_x\cdot R30 = (I_L\cdot \frac{R7}{R21})\cdot R30 \\ \Rightarrow \frac{V_x}{I_L}=\frac{R7\cdot R30}{R21} = \frac{1\ V}{1 \ A} } $$ The converter generates one Volt at VX node per one Amp of output current. This circuit is not a good choice for high-accuracy measurements, because it assumes that the emitter and the collector currents of the output transistor to be equal. Still a good choice for some practical applications. A better option is to use a differential amplifier but the common-mode voltage requirement is a limiting parameter for the op amp (The common-mode voltage of the op amp should be higher than the maximum rail voltage).
H: Diodes made using separate p and n-type semiconductors Can a diode be made by connecting, in series, separate n and p-type semiconductors? Assume that all ends are attached to Ohmic contacts. I am hoping that this will prevent any discontinuities in the potential. I have seen a similar question on the Physics Stack Exchange, but the question is too old to make comments (https://physics.stackexchange.com/questions/72432/would-connecting-p-type-and-n-type-semiconductors-work-as-a-diode). But in that question, they didn't talk about Ohmic contacts. AI: Can a diode be made by connecting, in series, separate n and p-type semiconductors? No. What you show would behave as 2 resistors in series. Note that PN junctions in a semiconductor rely on dopings within the same crystal structure, i.e. monocrystalline silicon. Your picture shows two independent crystals.
H: P-channel high side mosfet getting hot when not in use My high side mosfet shown as Q2 in the diagram gets very hot when not supposed to let any current through it. When DIR1 is high and DIR2 is low current is supposed to run through transistor Q1 through the motor and through Q4 and Q5. These three transistors seems to behave as intended but I must have overseen something. The weird thing is when the H-bridge is configured this way some current still runs through Q2 since it's getting hot. It is more prominent at a lower duty cycle of the PWM-signal. Wouldn't most of the current go through diode D2 during the low part of the PWM-signal at Q5's gate as it has a lower forward voltage drop than the body diode of the transistor Q2? The waveform I'm seeing at the motor with a PWM-signal at Q5 with a frequency of 1 kHz and a duty cycle of 50%. Here's a waveform of the voltage over the motor: Here's a picture of the diagram for the circuit: EDIT The new circuit has been tested and the waveform looks much better but I've measured the voltage over the motor and some oscillation occurs. What can cause this oscillation? The other question is why is there a delay before the motor voltage drops? Is this caused by the diode being too slow? The PWM frequency is 4.5 kHz and the duty cycle is 50%. Here is the new waveform: Updated circuit: AI: You disconnect the source terminals of Q3/Q4 from ground with Q5 so they go out of control. Without a connection between Q3/Q4's source terminal and ground, they are essentially out of control because your opto's direction output is ground referenced but no current loop exists between your optos and Q3/4 Vgs. The only reason they stay conducting is that Q3/Q4 have stored charge in their gate-source capacitance so can stay turned on when Q5 stops conducting. You are coasting through it (you cannot change the conduction state of Q3 or Q4 while Q5 is not conducting) but you don't notice due to how the circuit is used. What you do notice is the effect on Q1/Q2. Q1/Q2 have a pull-up resistor which drains their gate-source capacitance when Q5 stops conducting. When Q5 stops conducting, the current path which keeps Q1/Q2's Vgs charged against the pull-up resistor discharging Vgs dissappears. Q1/Q2 are basically trying to turning off every time you open Q5 and then need to turn back on again and it looks like they have trouble doing so. UPDATE: Correct. The updated circuit I described looks your updated schematic. If you choose a NMOS for the new Q5 then you need a floating high-side gate drive. If you choose PMOS then things can be simpler. Remember, the voltage between gate-source is all the MOSFET cares about. The PMOS source is fixed to +V so to achieve the appropriate Vgs to control the PMOS, the gate needs to be driven between +V and +V-Vgate, where Vgate is the voltage to achieve the rated RDson in the datasheet, not Vgth. Vgth just barely gets the PMOS to conduct which is useless when using it as a switch; You want to fully conduct. The simplest way to do this is to simply pull the PMOS gate all the way to GND, but if your +V is high enough, then your max Vgs on the PMOS will be exceeded. If this is the case, then you need to include things like zener diodes to limit how far below +V the PMOS Vg can be pulled towards ground. Since this is a gate drive you will be PWMing, it will be switching on and off and high frequency so you need to be mindful about how quickly the gate-source capacitance can be charged and discharged. So things like 2.5K pull-up gate resistors you used elsewhere won't be optimal; They'll have an RC time constant with the gate capacitance which could be too slow for your PWM frequency. You might consider things replacing pull-up resistors with pull transistors instead. So instead of a pull-up resistor and pull-down NMOS, you have a pull-up PMOS and a pull-down NMOS which are driven together for a totem pole. Shoot-through can still be a problem here but since currents are lower you can use resistors to limit the shoot-through and tolerate the losses. You don't want a ton of complexity into the gate-drive because then you start getting circuits that are fractals of each other. Another approach that sometimes work is to flip the PMOS and NMOS in the gate-drive circuit so the PMOS is on the bottom and an NMOS on top which acts more like an push-pull amplifier so can't shoot-through but also isn't as efficient as a switch. But that tends to be tolerable if gate drive currents are low. SECOND UPDATE: Whoops. My bad. With a high-side Q5, the PMOS Vgs still discharges when Q5 is not conducting because Q5 has an anti-parallel parasitic body diode. That provides a path for Cgs around the loop that includes Q5 and the pull-up resistor to discharge. If you really want to stick with the use of Q5, put a diode in series with Q5 so current cannot flow backwards through Q5's body diode (you can see it in the schematic symbol. Almost all discrete MOSFETs have a parasitic body diode as a result of the way they are manufactured. They don't need to, but they often do 99% of the time. When they don't they have a fourth body terminal. I've never seen a power discrete MOSFET like that. Only a few special-purpose signal MOSFETs).
H: Should battery be disconnected on both terminals? I am building an EV and I was wondering, should I disconnect only positive or both main HV battery terminals? Which option do car manufacturers use? I don't see any disadvantages with disconnecting only one, unless there is some damage to battery pack and possible short circuit to car's body. Here's approximate schematic: Should I use only A1, A2 relays or also B's? AI: For safety reasons, it's a must to disconnect both ends of the battery. Because it's a high-voltage source and should be treated as such - just like making the phase and neutral conductors dead before working with live voltages. And that's what manufacturers do. There are different options like using contactors on both sides, or using semiconductor switches at positive-side and contactors at negative side.
H: Include a txt file in an .ac Ltspice simulation I have a .txt file containing measurement of an impedance I have performed. I know that in .TRAN simulation I can easily include a measured voltage or current (saved in a .txt file) in my LTSpice simulation. However, how can I do the same in an .ac simulation? I do not want do go down the road of fitting and deducing the equivalent electrical circuit that will reproduce the same frequency behavior of the impedance of the component I have measured, I'd rather just include the file in my simulation and get the bode diagram. AI: You can convert the data and use the old FREQ syntax. For example: freq real imag 1 0.3 0.7 2 0.5 0.2 These need to be converted in a (freq mag phase) triplet: E1 out 0 FREQ {V(in)} + (1, {hypot(0.3,0.7)}, {atan2(0.3,0.7)180/pi}), ; needs degrees + (2, {hypot(0.5,0.2)}, {atan2(0.5,0.2)180/pi}), ... Where V(in) is assumed to be the input (and needs the curly braces). Since atan2() will wrap your phase, you may need to do this externally and unwrap it, then simply include the raw numbers as triplets: (1 0.762 23.2) (2 0.539 68.2) .... Then simply add .inc <filename>.txt in your schematic and probe V(out) (which can be changed in the E1 <output_node> 0 ... line.
H: Why do Zener diodes have a lower breakdown voltage than normal? Here I do not understand some physics. So for normal diode we have a depletion zone width say Wn, and for Zener diode we have Wz. Then, we know that Wn > Wz. By reverse-biasing we make the depletion zone wider, until Epn is too high, and eventually everything breaks, so the current starts flow. But if Wz < Wn, than it should have greater Vbd? I assume that the answer is in potential difference between PN. Even though Wz < Wn, we have Ez >> En at PN junction due to higher doping, so it takes much less Vbd to start the flow in Zener. Is it correct? AI: The zener breakdown in zener diodes is due to quantum tunneling.The doping of a zener diode is very big-> the electric field is very big -> the width of the depletion region is very small and doesnt change with applied reverse voltages. Now back to quantum tunneling: As shown in the picture a classical particle cannot go from the first bottom of the hill to the second bottom of the hill without giving the particle some energy to overcome the potential energy needed to reach the top of the hill then roll back down. However quantum particles(electrons or holes) can tunnel through the the hill as long as the hill is very small in width and has a finite potential at the top of the hill. In our case at the zener breakdown voltage the energy of the conduction electrons in n type region becomes equal to the energy of the valence holes in the p type region and because the barrier is very small in width and the electric field of the depletion region is of finite value electrons from the conduction band of n type region can tunnel to the valence band of the p type region. Note however we have a second breakdown voltage called the avalanche breakdown voltage under which the kinetic energy of the minority charge carriers inside the depletion region can break the bond of a atom with its valence electron creating a electron-hole pair increasing current tremendously and destorying the diode.The avalance breakdown voltage is much higher than the zener breakdown voltage. Normal diodes exhibit only avalanche breakdown while zener diodes exhibit both zener and avalanche breakdown.
H: A circuit cannot contain two different currents in series; otherwise KCL will be violated I'm currently studying the textbook Fundamentals of Electric Circuits, 7th edition, by Charles Alexander and Matthew Sadiku. Chapter 2.4 Kirchhoff's Laws gives the following example: Kirchhoff’s current law (KCL) states that the algebraic sum of currents entering a node (or a closed boundary) is zero. ... A simple application of KCL is combining current sources in parallel. The combined current is the algebraic sum of the current supplied by the individual sources. For example, the current sources shown in Fig. 2.18(a) can be combined as in Fig. 2.18(b). The combined or equivalent current source can be found by applying KCL to node \$a\$. $$I_T = I_1 - I_2 + I_3$$ A circuit cannot contain two different currents, \$I_1\$ and \$I_2\$, in series, unless \$I_1 = I_2\$; otherwise KCL will be violated. I don't understand why a circuit cannot contain two different currents in series, and why this would violate Kirchhoff's current law. If two currents, such as \$I_1\$ and \$I_2\$, are in series, then wouldn't the current just be the net of the two, as shown in 2.18(b)? I get the impression that I am misunderstanding/misinterpreting what this is saying. EDIT For some reason, despite the fact that we've had four answers, no one has yet explained this concept. The closest we've come is Neil_UK, who just commented that my reasoning is incorrect since I am assuming that the currents also add in series, just as they do in parallel. So why exactly is it incorrect to assume that the currents add in series, just as they do in parallel? This seems like it would be the natural assumption. What is the correct way to think about this? EDIT2 From the same textbook, “a branch represents a single element such as a voltage source or a resistor.” And, again, from the same textbook, “a node is the point of connection between two or more branches.” AI: Here is the circuit we understand you to mean when you say "two currents in series": simulate this circuit – Schematic created using CircuitLab For I2 to be a 2 A current source, 2A must be flowing in to its left terminal and 2 A flowing out of its right terminal. But for I1 to be a 1 A current source, 1 A must be flowing in to its left terminal and 1 A flowing out of its right terminal. That means 1 A is flowing in to node A from the left but 2 A is flowing out of node A to the right. And no other branches connect to node A. What your book means by saying "KCL will be violated" is if you form a KCL equation at node "A", you get $$1\ {\rm A} = 2\ {\rm A}$$ which is a logical contradiction. To address the edits in your question post, From the same textbook, “a branch represents a single element such as a voltage source or a resistor.” And, again, from the same textbook, “a node is the point of connection between two or more branches.” Yes, but two branches are in series only if there is no other branch that also connects at their common node. For example I1 and I2 are two branches in my diagram above that connect at node A. No other branch connects to node A and therefore I1 and I2 are in series. So why exactly is it incorrect to assume that the currents add in series, just as they do in parallel? It's a matter of the sign convention for the branches. A generic way to write KCL is $$\sum_n I_n = \sum_m I_m,$$ where each \$I_n\$ is the current of a branch with its reference direction pointing in to the node, and each \$I_m\$ is the current of a branch with its reference direction pointing out of the node. When we talk about branches in parallel we typically have one source branch on the left side of this equation and two or more load branches (the parallel branches) on the right side of the equation. Since all the load branches are on the right side, their currents add. When we talk about branches in series we have exactly two branches connecting at a node, and we put one branch on the left side (we take its reference direction as pointing in to the node) and one on the right side (we take its reference direction as pointing out of the node). In this case we get that the two currents must be equal.
H: How to control voltage using PID when driving SCR? I am designing a scr based digital battery charger for the first time and have successfully driven scr to provide 110V-DC from a 140V singe-phase transformer. 2 SCR-diode combination forms full bridge rectifier and each scr driven via gate driver controlled from software. Now my design needs to constantly maintain a 110VDC up-to 10Amps of current. To do this I have used a voltage divider feedback from output (470k+10K) and a PID controller combination which varies trigger angle of SCR (from 90degree to 180degree, every half cycle) to maintain the voltage (i.e. between 0A to 10A) Software samples adc at every 10us and my PID controller runs every 1ms. When I tested with 40ohm rheostat as load, it is working but not to my expectation. The problem is if I draw more current voltage first dips down and then after few seconds(2-3sec) pulls back-up OR if I suddenly increase the resistance, voltage shoots up (which is very scary) then eventually comes down to desired 110V. I have seen analog SCR based PCB that maintain the voltage as if voltmeter is stuck at 110V display no matter the load. I want to show similar output from a digital controlled design. So if any one has tried this and achieved immediate control using PID please provide hints. Please note that I have ensured common things like, SCR target trigger pulse decided by PID is generated from software exactly at the right time from zero crossing (0.1us resolution). Have tried to maintain minimum delay in voltage feedback using lesser capacitance values (although the feedback is isolted using opto, but its propagation delay is lesser than PID loop) Tried for 10-15 day and nights for fine tuning PID Kp, Ki, Kd terms and read all theory related to it. I just feel the problem with software is that even though PID loop runs every 1 ms, SCR can be triggerred only at every 10ms (due to 50Hz AC). So eventually PID input will have a delay of 10ms before it realize the result of last set value. So when I try running PID every 5,10,15,20 ms. But still 2-3 seconds dip or shoot is inevitable. But if this was the case, how analog SCR charger PCB achieving it? AI: Of course executing PID loop faster than actuator can follow leads to wrong computation of integral part, and D-part as well. It has to be determined if PID is actually the correct way. A system with L and R is suitable to be controlled with PI controller, this way all the motor controllers do work. To have a very simple and reliable control, you should start with P-control. This is the closer approximation you are asking for : I have seen analog SCR based PCB that maintain the voltage as if voltmeter is stuck at 110V display no matter the load. The output RMS voltage is not linear to the phase angle, so you could use a specific inverse function to linearize the system. With this purely analytical approach you could know the phase angle "a priori" with known input supply volatge and the desired (setpoint) output voltage. Then you measure the output voltage and apply only a slight correction, computed via P-controller. From here you can start doing PI, PID,...
H: What do the stars in a power meter symbol mean? Sometimes I see stars in a power meter in three-phase circuit are drawn as below. What do the stars in a power meter symbol mean? There is another example here (page 14/20): Now it seems to me that they are dots to indicate the polarity of the windings. AI: Power is the average of this instantaneous calculation: - $$\text{voltage} \times \text{current}$$ So, if you get the voltage winding or the current winding backwards you get this: - $$-\text{voltage} \times \text{current} $$ Or you get this: - $$\text{voltage} \times -\text{current} $$ Given that some analogue power meters have their needle centred like this it's not a big deal: - Image from here. But, unfortunately most don't so, you should respect the polarity indicators on the terminals to ensure power is read meaningfully. Wattmeter internals (magnetic coupled type): - Image from How does a Wattmeter work? (back to basics).
H: Expected behaviour of a non-inverting buffer IC I am using an NL17SZ07 buffer w/ open drain. Is it to be expected that I need to pull the output high with a pull-up resistor to have the output behave as expected? I would have anticipated that the output would step with the input at the supply voltage, without the need for a pull-up. Perhaps it is the open drain that is causing this? It is causing a lag on the rising edge of the output, that can only be helped by lowering the value of the pull-up. Is this to be anticipated? Perhaps this is the wrong component for the job. AI: That's exactly what an "open drain" output does, so this is to be anticipated.
H: Voltage drops when current reaches limit on supply Why is it, when I'm powering a circuit via a lab bench power supply set to limit 2 mA and the current drawn from the circuit reaches the limit, the supply voltage drops? AI: That is called Constant Current Constant Voltage (CC/CV). The power supply has to lower the voltage to keep the current at the limit, when the current limit is reached. If the voltage were to keep rising then the current limit you set would be violated. Imagine if you had a simple resistive load. If the voltage goes up so does the current. So in order for the power supply to maintain the max allowed current, it must keep the voltage fixed at a lower setting.
H: Which IC with top mark 15ZL is shown in this image? Can anyone determine the part number of this IC with top mark 15ZL and find the datasheet? AI: Looks like a Torex XC6201P302MR 3.0V LDO regulator.
H: Is there a way to determine polarity of a DC device that has missing power adapter? Let's say someone has bench power supply and a multimeter, then is it possible in safe manner without damaging device to use these tools to determine devices polarity? Update#1: In this specific case it is braun shaver. I was able to find aftermarket charger but as can be seen plug has both terminals as equals (opposed to ones where usually plus is in middle and minus around it). AI: From this website is a photo of a Braun charger cord that purports to show the polarity. Might be correct. Note that it's for a Braun toothbrush, not a shaver. Maybe start the power supply off slowly from zero with current limit set to something reasonable. Edit: Here (from Amazon.ca) is an adapter that claims to be for some Braun models of shaver: Polarity markings are similar even though the plug is a bit different. And another shaver adapter from Amazon.ca: All three of these are consistent, but you're still taking a bit of a risk connecting it.
H: DC coupled amplifier circuits How can the transistors in an op amp's differential input turn on if the input voltages are smaller than \$V_{BE}\$, like 0.2V? How can the transistors in the differential amplifier start conducting with such small voltages? I understand how with AC coupling one can bias the inputs of an amplifier but I don't understand how it works with DC coupled circuits. AI: Sorry if the answer is "long" ... When components have already "good" values, it is "easy" to simulate this "simple" op-amp and determine the "steady" states values of voltage for all nodes and currents in any branch. DC Dynamic Analysis It is the first step (1 of 3). Changing one input voltage (ina or inb), you can see the "behavior" of the output in "DC Dynamic" mode. Ok, you can calculate all parameters of interest to see if all is correct, but it takes time. The second step (2/3) answer at your question. It is DC analysis. What you see is the behavior when changing one input voltage (here V3). And allow to view some parameters ... And specially, what is the change of V3 needed (~ 1,279 mV) to make a full span of output voltage , well below 0.2 V. One can see the gain which is ~ -6873, slope of output Vo. One can see that there is also an input offset voltage (~ 100 uV). One can see that output voltage can be - 5V (to -rail), but only ~ 4.2V max(not to +rail 5V). DC Analysis Step 3/3 ... AC analysis, parameter C1 (open loop, with feedback), TRAN Analysis (open loop, with feedback, only parameter offset). AC Open loop AC closed loop, 1 case TRANsient Analysis open loop TRANsient Analysis closed loop, 1 case
H: Are "switched" TRS connector pins (sense pins) suitable for audio multiplexing? TRS jacks are commonly available with "switched" or "sense" contacts, like this: This form is commonly used to ground the input pins when nothing is plugged in. But can these contacts also be used to multiplex an audio signal, like this? The idea is to use an external signal when a plug is in, but a separate fallback signal when unplugged. For this to work, it seems like the following characteristics would be important: Low and well-defined sense contact resistance (from pin 2 to 3 and from pin 4 to 5). I.e., minimize distortion of the fallback signal. Extremely high resistance and low parasitic capacitance between sense and "real" contacts when plugged in. I.e., minimize crosstalk between the signal from the plug and the "fallback" signal. I've looked at a number of datasheets (CUI SJ1-352XN, Amphenol ACJM-NV35-2, Kobiconn 16PJ108-EX, Kycon STX-3120-5B) and haven't found any clear statements about these properties. Some of them list "contact resistance," but it's not clearly stated whether this value also applies to the sense contacts. Others don't mention contact resistance at all, and none of them mention any crosstalk properties. I do have two kinds of these jacks (the Kycon STX-3120-5B and an unidentifiable generic, i.e. cheap garbage) and have tried to measure these properties myself. Sense contact resistance for both measures in the tens of milli-ohms unplugged and "off-scale high" for my meter when plugged in. So it seems promising, but I don't know if I can rely on these characteristics after a healthy number of mating cycles and in all connectors in a batch. Is this a normal, sane thing to do or are these pins really not meant for this purpose? The input signal in my application is rated up to +4 dBu (about 3.5 Vpp) and the connector feeds an audio preamplifier with a ~20k input impedance (current through the connector is thus a fraction of a mA). AI: This is a standard technique in audio consoles, called "jack normalling". There are many ways it can be configured: as in your case to insert an external input in place of the normal internal one, in a left/mono, right/stereo scheme where unplugging from right jack cause right signal to route to left's ring, or as an effects return where your signal is output on the ring and returns, effected, on the tip. As to your other concerns, contact resistance and parasitic capacitance - these are completely insignificant at these levels and frequencies. Any decent quality jack should work fine - professional companies ship zillions of units with this scheme.
H: Modelling I2C capacitance for cables under water My setup works fine with following combination of hardware: Raspberry Pi4 connected to a TCA9548A I2C Multiplexer from Texas Instruments, whereas each channel is connected over 4wires (GND, VCC, SDA, SCL) with 140cm 30awg silicone wires to two more I2C sensors. In the office, the setup works perfectly. When the cables are immersed in water, which they need to be for the application, I get errors. Wrong addresses are displayed for the I2C sensors and it happens very very rarely that the sensors are recognized under their correct address and can also be read out. My question is basically: How can I model the wire capacitance with regard to the surrounding water and maybe other relevant water parameters such as the electrical conductivity? AI: Polymers' water uptake can vary a lot (e.g. https://omnexus.specialchem.com/polymer-properties/properties/water-absorption-24-hours#A-C ). This water ingress changes the relative permittivity as already mentioned. This is even used to build sensors (e.g. https://www.mdpi.com/1424-8220/18/5/1516/htm ). The final value strongly depends on the exact conditions and material composition but to give an idea, one can take a look at research papers like DOI:10.1109/TDEI.2015.005291 i.e. figure 3 (For a sneak peek look here: https://www.semanticscholar.org/paper/A-capacitance-study-of-anomalous-diffusion-of-water-Gao-Liang/89f65da7fe71ba55a923a3876e801587781f1799/figure/4 ). In the mentioned publication an increase of the relative permittivity from 3.5 to 6.0 is reported for some of the investigated materials. So how to deal with that? Select the cable (isolation) carefully - ideally something with a very low water uptake and enough thickness Keep the cable short as possible Lower the switching frequency EDIT: thinking about it, a coax cable might do the trick if it is hermetic. EDIT2: if none of the approaches works one can try to use differential I2C bus extender. The trick is that differential transmission is less susceptible to signal perturbances. Downside is the additional HW requried.
H: Low voltage at N-Channel source pin I made a pcb which uses an N-Channel Mosfet for enabling/disabling the NTC thermistor as in the schematic below. The problem is I get 2V at the Drain pin instead of 3.3V. I measure 3.3V at NTC_TRIG and power pins with a voltmeter so there isn't any issure there. Currently using this N-Channel mosfet whose gate threshold voltage(1.6V typical) seems suitable for my application. MCU is STM32F030C8 powered with 3.3V Schematic: AI: You can either swap drain and source and use a P-channel MOSFET, or drive the gate with several volts higher than the 3.3V supply and stay with the 2N7002 (likely not convenient for you). You have made a source follower so for output current 250uA it will drop Vgs(th) from the gate voltage (source voltage effectively reduces Vgs). In the case of using the P-channel MOSFET, input low will turn the MOSFET “on” and high will turn it “off”. Suitable P-channel MOSFETs might include the BSS84 and the AO3401A for lower Rds(on).
H: Is low humidity bad for HIPOT testing electrical harnesses? From what I understand for HIPOT testing high humidity could be a potential issue because if cable insulators absorb moisture that could affect their resistance. What about low humidity? Is there any reason why low humidity would be bad for HIPOT testing? Most cables aren't ESD sensitive which is why you usually would want to have a minimum humidity requirement. AI: The disadvantage in testing your electrical harnesses in a low-humidity ambient is that you will not evaluate the potential for the insulating materials contained in your harnesses to leak current when exposed to moisture. Ideally, the components are tested under the worst-case operating conditions. In HIPOT testing, the worst-case is at the high-end of the humidity range. There is no parasitic conduction path that is revealed at the low-humidity limit. So in conclusion, there is no reason to test your electrical harnesses at the low-humidity limit.
H: Can anyone please identify this chip? Is from an LED board from a modern Pinball machine. Seems like the output is connected to a 74HC594D legs RCLR and SRCLR. AI: Possibly ST Microelectronics STWD100NYWY3F watchdog timer. However other SOT23-5 ICs could bear this marking, so this is by no means definitive.
H: DC DC converter I am newbie trying to build a circuit, please help me out. I am trying to build a DC-DC converter whose input will be 24V and output would be 5V 3A. I have picked AP63301WU-7 DC DC converter from Diodes Inc. As per the application circuit, I have to use two resistors 158Kohm and 30.1Kohm that act as a voltage divider at the Feedback pin. The problem is I am unable to find a resistor that is rated to the required wattage (which will be 3A * 24V = 72W). The closest I could find has a power rating of 660mW. Is it fine to use this resistor? AI: Those are feedback resistors that carry minuscule current. Any 0.1W resistor would do. 5V / (158K + 30K) = 0.00003A or 30uA 30uA * 5V = 0.15mW
H: Stand alone CAN bus module or STM32 embedded CAN? I have spent days studying and trying to achieve simple communications with CAN bus from scratch using stm32f1, but I still have not achieved the desired results and it is difficult to understand and program. On the other hand, there are CAN bus modules that communicate with a microcontroller by SPI like this: https://www.ebay.com/itm/283953770322?hash=item421cf6af52:g:JHAAAOSwIeVfQ7HI and there are many libraries to handle these modules, but the official microchip page does not recommend continuing to use the MCP2515. My Doubt is: What difference is there in using CAN bus from scratch (STM32) than using a separate module? using a stand alone module affects the security of the CAN bus? Should a stand alone module be used in industry? AI: What difference is there in using CAN bus from scratch (STM32) than using a separate module? External CAN controllers is mainly a thing of the past. In the 1990s, it was about the only way to use CAN, before microcontrollers started supporting on-chip CAN controllers. Since then, the only reason to use an external CAN controller is that you have specialized project requirements leading to a very specialized MCU - one that doesn't come with a CAN version. using a stand alone module affects the security of the CAN bus? Not security as in protection from malicious use. But it makes the whole design slightly more sensitive to EMI since SPI isn't nearly as rugged as CAN. The external controller also introduces a lot of latency, BoM costs and overall extra pointless complexity. but the official microchip page does not recommend continuing to use the MCP2515 That would mostly be because Microchip has made a new generation of all their transceivers and controllers with support for CAN FD. The new modern parts are backwards-compatible and also have better immunity and ESD protection etc.
H: Touching the antenna of a crystal set I built the crystal set shown in the diagram below and I find that the signal it receives is clearer when I touch an uninsulated part of the aerial (i.e. the node labelled "green" on the diagram). Would anyone be able to explain why this happens? Thanks. (Source: S. Voron, R. Tester and M. Middleton, Funway into Electronics Volume 1. Chullora, NSW: Dick Smith Electronics, 2008) AI: Your body is a not too bad antenna .If your antenna system is not very good like say a whip antenna and/or a ferrite rod then the signal addition is going to give a volume increase .These passive receivers do not have automatic gain control so this effect is more pronounced when compared to say a car radio .Your body is also capacitive at AMBC frequencies which will tune the system lower.
H: Equation (mathematical function) of ramp signal vs saw tooth signal I have a sawtooth current source whose peak value is 1A. 0A to 1A. with a frequency of 1kHz. This current source is going to charge a 1F capacitor, so I was trying to find the equation for the current source so that I can calculate the voltage across the capacitor after 1s from time t=0s. I understand that the equation of a ramp signal would be that of a straight line equation. In that case, is the ramp waveform similar to the saw tooth waveform? Would there be any difference in the current equation of the capacitor between the two waveforms? Why do we not include the frequency term while calculating the integral? AI: I was trying to find the equation for the current source so that I can calculate the voltage across the capacitor after 1s from time t=0s. If there's doubt, just use your good old trusted simulator to get your brain aligned to the right ballpark. Here's my attempt using micro-cap: - A slightly closer look at the changing voltage waveform around 0.6 seconds: - As you can see, the voltage rate of change is proportional to the current changing (as per the equation further down). So, I was trying to find out the equation for the current source so that I can calculate the voltage across the capacitor after 1s from time t=0s It's not that easy to find an equation for the sawtooth waveform because it has sudden edges and discontinuities. Better to use a sim IMHO. I understand that the equation of a ramp signal would be that of a straight line equation. In that case, the ramp waveform is similar to the saw tooth waveform right? No, a ramp is part of a sawtooth waveform but, they are not the same. A sawtooth has a ramp-up equation followed by an infinite slope ramp-down equation (aka a discontinuity). So, would there be any difference in the current equation of the capacitor between the two waveforms? As always (and forever) the equation for a capacitor is this: - $$I_C = C\dfrac{dV_C}{dt}$$ It's that same equation for all waveform types and amplitudes. And the other question is, why do we not include the frequency term while calculating the integral ? Because we don't need to. Links to mathematical waveform definition for a sawtooth From wikipedia From Wolfram From digital signals Harris. They concentrate on the Fourier version but, wiki does contain the formulas for a time-based waveform I believe. The capacitor voltage if just a 0.5 amps current source were applied: - I've changed the current source from a 0 to 1 amp sawtooth waveform at 1 kHz to just a constant current source of 0.5 amps. Can you see that there is very little difference in the capacitor voltage ramp. OK, if you are looking for minutia then it might be important.
H: Slider operating force range I'm reading the datasheet of PTB0153-2010BPB103. It states: Mechanical Characteristics Operating Force ................10 to 100 gf Stop Strength ................. 5 kgf min. Sliding Life .................. 15,000 cycles Soldering Condition ........... 300 °C max. within 3 seconds Travel ........................ 45, 60, 100 mm The Travel allows different values, but in the "How to order" section I can see how it's defined. What about the Operating Force? It says "10 to 100 gf" but I don't understand which is the actual value. I don't think it's a tolerance because it's an order of magnitude. I'm also thinking about some different operating conditions but I don't see any meaning in that. What does this specification mean? AI: The Travel allows different values, but in the "How to order" section I can see how it's defined. For a 45 mm travel the part number begins PTB 45.... For a 60 mm travel the part number begins PTB 60.... For a 100 mm travel the part number begins PTB 01.... What about the Operating Force? It says "10 to 100 gf" but I don't understand which is the actual value. That's the force needed to start moving the slider. It's somewhere between 10 g and 100 g (a stiction value plus sliding force value). Data sheet. This value isn't an "order option" number. It's a variable value that applies to all the sliders in this product range.
H: Attenuation in current booster circuit with op-amp I was testing a current booster circuit in Multisim with a TL081IP when I noticed that I'm getting high attenuation at surprisingly low frequencies (above 1 kHz). The circuit and the frequency response is shown below: From my understanding, I can't see why this is happening since this op-amp has a unity gain frequency of 3 MHz and its lowest slew rate specified is 8 V/μs. The current the op-amp is outputting is also always below its short circuit current (+-26 mA). Can someone give me an insight on this? Much appreciated. AI: Can someone give me an insight on this? Much appreciated. At lower frequencies the op-amp has a great open loop gain: - An open loop gain of 120 dB means a DC gain of 1,000,000 and, with low frequency signals, the op-amp can rapidly drive its output through the unbiased point (dead-band) of your output transistors and things will look pretty good. Yes, the problem here is that you are not biasing the output transistors into partial conduction and that means the op-amp output has to move at least 2 x 0.6 volts on it's output before one transistor turns off and the other one starts to turn on. You are using class B biasing: - At high frequencies that's a problem because, the open loop gain falls linearly with frequency for this type of op-amp: - In other words, the op-amp cannot change it's output to overcome the 1.2 volts dead-band (imposed by lack of BJT bias) at the higher frequencies with the slew rate limitations it has. If it can't move the output at least 1.2 volts to overcome the bias problem, the signal reaching the transistor bases will become more ineffective as frequency rises and, you lose output amplitude. If you want to see this for yourself, just do a transient analysis and look at the op-amp output. If you want to fix it then use class AB biasing on your transistors
H: practical connection of LED to a MCU While aiming to blink an led with this 8051 MCU, I used configuration 1 to connect my LED. It doesn't work. But 2 and 3 worked. logically, there should not be any reason behind why configuration 1 do not works. Because it will alternatively give 5V (assuming no tolerance) and 0 V. But I'm guessing it didn't work because although the pin is switching between 5 V and 0, the MCU is not able to supply sufficient current to the LED, because the MCU is current limited. Is this correct guess? or any other reason behind it? AI: Yes, your guess is correct. The 8051 has a peculiar I/O structure, sometimes referred to as "quasi-tristate" or "quasi-bidirectional". The output drivers can pull down strongly, but there is only a very weak internal pullup resistance that is permanently connected. In order to improve the risetime when switching high, a pullup transistor in parallel with that resistance is switched on for a very brief time — 1 µs or less — too short for you to see it on your LED.
H: Feasibility of obtaining a 210µF 4.5kV DC capacitor? I'm looking for a high-capacitance, high-voltage capacitor for a experiment I'm interested in trying out (i.e. order of 100µF rated for at least 4.5kV DC). I realise these specifications may be unrealistic, and am yet to find any capacitors like this available online. My question is: is this sort of capacitor even remotely possible to obtain? And if not, are there any substitutes that have similar properties (e.g. capacitor banks)? AI: My question is: is this sort of capacitor even remotely possible to obtain? And if not, are there any substitutes that have similar properties (e.g. capacitor banks)? There are capacitor banks but not for DC. Those are designed to operate across very high line voltages, and capacitances are not high. I don't know if there are commercial products for your purpose but what you can do is to connect 10 of 1000μ / 450V (or, with a 10% margin, 1000μ / 500V) capacitors in series to get 100μF / 4.5kV capacitor. This is practically achievable, but quite expensive and large. I'm not sure but can be a bit heavy as well. But it may be even fun to build such a bank. Remember to put equal resistances (a bit higher like 470k or 1M) across each capacitor so that each capacitor share equal voltage.
H: What is the purpose of capacitor C4 (47 pF) in the feedback network of this buck converter circuit? What is the purpose of capacitor C4 (47 pF) in this circuit? Datasheet AI: The trouble with converters like this is that they can go unstable quite easily and need a hand to prevent this from happening. Unlike linear voltage regulators, the feedback isn't directly from the chip output but, passes via an LC low-pass filter. Of course, that LC filter is needed (for switching regulators) to give a fairly decent DC voltage at the output but, consider what happens both below and above the cut-off frequency of the LC low-pass filter: - Image from my crappy website. Don't feel pressurized or inclined to go there at all because all you need to know is pictured above. The green trace is phase angle shift. A bit below the cut-off frequency, \$F_n\$ (~9.2 kHz with the component values from the question), the phase angle of the filter's output signal will be close to 0°. That's not a problem and also, it's pretty much what a linear regulator will receive at its FB terminal. But, above 9.2 kHz there will be a near 180° phase shift before 40 kHz is reached. That represents a big problem if not handled correctly. Any extra degree or two of phase shift will turn a simple buck regulator into an oscillator (due to the phase of the FB signal becoming inverted). So, if you add a small value capacitor across the top feedback resistor you can retard the lagging phase of the fed-back signal from nearly 180° to something more like 150° and, at much higher frequencies, it will retard the phase back to about 90°. $$\color{red}{\text{This stops the circuit becoming an unwanted chip-busting oscillator}}$$ Sometimes things won't go unstable but, one little transient load condition change on the output can make these devices sing out loud. Think about a linear voltage regulator; if instead of taking the feedback directly from the output, you inserted an inductor between output and smoothing capacitor, would you really expect decent performance and no load-induced crazy overshoots on the output voltage and, no oscillations?
H: What does Hot Swappable mean? new to electronics. I am not quite sure I understand hot-swapping fully. It appears that hot-swapping is when you could replace a device while the system is operating without interruptions; however, how would you replace a device that needs to always constantly be turned ON if it turns off it would interrupt the system? Seems impossible. AI: It doesn't mean that there won't be any interruptions, it just means that the device will not be damaged and can resume normal operation after a hot plug/unplug event. SATA hard disks are a good example of this: If you unplug the disk while the computer is running, you of course won't be able to access the disk anymore. Similarly, you will only be able to access a disk once you've actually plugged it in. "Hot swappable" only means that you don't have to shut down the entire computer in order to swap a disk. (Of course, you'll have to tell the operating system that you're about to unplug the disk, otherwise you might lose some data that was not yet written by the OS. You'd typically do this by unmounting the drive. This is what "safe remove" does in Windows.) Imagine having to reboot your computer every time you want to plug in or remove an USB device - that'd be super annoying. That's why USB devices must be hot pluggable.
H: Replacing a 18650 battery that was being charged at 5 V I'm trying to change my wireless speaker's battery that uses one 18650 battery, but when I checked the voltage that goes to the battery while it is being charged, I saw that it was 5 V. I know that the charge voltage should be around 4.2 V - 4.3 V only, so my question is: is it safe to just replace the 18650 battery? Or should I make adjustments to the circuit to prevent overcharging? My wireless speaker is a knock-off brand so I'm not so sure about it's charging protections. AI: Going by your latest comment about charging at 4.3V, the situation is pretty clear: This charger doesn't properly implement the CC-CV charging that's required for Li-Ion batteries. It instead just provides a limited current to the battery irrespective of its voltage (I could imagine that it's just a diode and a resistor connected straight to 5V). Throw it away, it's a bomb. (Or charge the battery outside of the speaker.)
H: Do laptops use different batteries than powerbanks So I was researching about laptop batteries and I got confused on whether laptop batteries and other batteries like power banks are the same. To clarify I was looking at the new MacBook Pro battery specs and it has a 100wh battery capacity which is around 8,800 mAh, when looking around the web there are other batteries like power banks with 10,000 mAh, 20,000mAh, etc but with a much less price tag. So to come to my question. Are the batteries inside laptops the same as the power banks? And if so, question 1, why are big-name laptop batteries priced (800% +) above the power bank prices with the same capacity (ignoring the fact that they are manufactured by big-names). And question 2, why don't they use bigger say 20,000mAh for more device uptime because power banks come with that capacity? Any help on clarifying this would help. Thanks in advance. JUST FOR REFERENCE OF PRICE DIFFERENCE: https://www.alibaba.com/product-detail/Battery-Banks-Wholesale-USB-Portable-Battery_62451720213.html?spm=a2700.galleryofferlist.normal_offer.d_title.19377cacADgTTO&s=p https://www.bestbuy.com/site/denaq-lithium-ion-battery-for-apple-macbook-pro-with-retina-display-laptops/6382319.p?skuId=6382319&ref=212&loc=1&gclid=Cj0KCQiAqbyNBhC2ARIsALDwAsB4ZUaWkaVxfURrbrYrvA7RC1IBEM50EfFNOY4E1qA1pPG-ftbmolsaAoMVEALw_wcB&gclsrc=aw.ds AI: 20,000 mAh capacity as figured in a power bank is about 72 Wh (they calculate it based on a single cell voltage of 3.6 V average). That's a genuine wh rating on (say) a Huawei or Xiaomi power bank as opposed to some outrageous lie by a nefarious Aliexpress seller. It's quite heavy too, uses good quality 18650 batteries. Given the usual premium for Apple products, I don't see an inexplicable price difference per Wh.
H: What does it mean to have a large time constant of a RC network than the time period of an input AC signal What does it mean to have a large time constant of a RC network than the time period of an input AC signal? Can someone tell me how to understand this and what sense does it make? AI: What does it mean to have a large time constant of a RC network than the time period of an input AC signal? If you apply a 1 kHz (0 volts to 5 volts) square waveform to three low pass filters having time constants of 1RC, 10RC and 100RC you get this (a meaning): - 1RC at the top and 100RC at the bottom (R = 100 Ω, C = 100 nF). Schematic: -
H: LTSpice: How to change x-axis (ac sweep) I want to plot a Bode diagram. LTSpice automatically plots the results as a function of frequency. I would like to multiply the frequency by 2*π, in order to obtain the angular frequency. How can I modify the x-axis quantities? AI: Maybe this is ugly, but it seems to provide the results you want: The default ac sweep, which gives the result in Hz is commented at the bottom. Also note that the number of steps (100) appears in different places for the two commands.
H: What is this bridge like component? As I was looking at some Texas Instruments evaluation module, FDC2214EVM to be precise, I found a component unknown to me: AI: It's just a test point for easily attaching a scope probe ground. The silk screen indicates it is connected to ground, there may be some for other signals although they are usually just small round pads for manual probing. The ground clip of the scope is always the tricky one to find a good connection for when probing a board. Here's another similar type: Test point
H: Working of a clamper circuit I was reading about the clamper circuit on wikipedia and found this below image for a positive clamper circuit. My question is During the positive (Rising/increasing portion) half of the input AC waveform, the capacitor gets charged right? Meaning the positive charges are accumulated on the left side of the capacitor plate and negative charges are on the right side of the capacitor plate. So, in that case, during this instant, the output voltage is taken across the resistor. So, the resistor at that time, is connected to the right side of the capacitor which is having negative charges. So, my doubt is - "When the input AC signal increases, the output voltage cannot also increase in the same fashion because the output voltage is taken across the resistor and it is connected to the right side of the capacitor plate which at time has negative charges, right?" Can someone clarify what I am misunderstanding over here? AI: The first thing to remember that this circuit, at its heart, contains a high-pass filter. In your previous question, I answered it from the perspective of a low-pass filter. For this particular circuit (using a high-pass) you actually want the time constant to be very long for a clamper. So, here's a reminder of what happens to a square wave when it passes through different RC filtering values before moving on to the clamping element: - So, here are the three waveforms from top to bottom: - RC 10 x RC 100 x RC And, you should be able to see that with a square wave used as the source, the best fit for that waveform at the output is when we have 100 x RC. Of course this is the opposite to a low-pass but, hopefully you can begin to see that. To the clamper (using 100 x RC) with a sinewave feed... As per without the diode clamps, the best performer is the 100 x RC circuit at the bottom but, it's got some distortion and maybe, upping it to 1000 x RC is better so, here's input and output waveforms shown together: - Green is output and orange is input. Clearly, the output signal remains above the instantaneous value of the input signal apart from the first half cycle (where they are close to the same value). the positive charges are accumulated on the left side of the capacitor plate and negative charges are on the right side of the capacitor plate. No, it's the other way round. Schematic used: -
H: Can I amp a radio transmitter to increase its range? I want to buy a sub-gigahertz radio module which has a TX power of 16 dBm. With the inverse square law, I can see that it has a power of -90 dBm at 50 km. I don't know if this is the correct way to determine power at a certain range or not, but either way, this is not enough. Can I use something like an op-amp to just increase the output power and get higher range? AI: The Friis transmission path-loss equation in decibels is this: - Path loss (dB) = 32.45 + 20\$log_{10}\$(f) + 20\$log_{10}\$(d) Where f is in MHz and d is in kilometres. So, If I assume 100 MHz (sub 1 GHz) and a distance of 50 km, I get an attenuation of 32.45 dB + 40 dB + 33.98 dB = 106.4 dB. And, this agrees with you expecting a receiver level of -90 dBm from a carrier transmit power of +16 dBm. I don't know if this is the correct way to determine power at a certain range or not Well, it's a good start. You can make directional antennas to increase the receiver level by many decibels. You can also be prudent with the bandwidth of the information you wish to send to get a few more decibels too. but either way, this is not enough (receive power). Well, that depends on the bandwidth of the information you wish to send (and you haven't told us that). The formula for a decent receive level (ignoring fading) is this: - Power (dBm) needed by a receiver is -154 dBm + \$10log_{10}\$(data rate) So, if your data rate is (say) 1 kHz, the receiver power needed is -154 dBm + 30 dBm = -124 dBm, then with an extra 20 dB added in to account for fading, you'd be looking at -124 dBm. But, of course, your bandwidth might be much bigger than what I've assumed. Can I use something like an op-amp to just increase the output power and get higher range? No, you'd never do this for two reasons: - You might exceed the regulatory specifications on power emitted (ideal op-amp) Ideal op-amps might do the job but, real op-amps wont, ever. Extra information here and here.
H: Do Output Voltage rails get an identifying symbol in schematics? For example, I have a 3.3V regulator using 5V input from a USB port. I use that output 3.3V rail all over my schematic. Sure, I can read the entire schematic and see - yep, that's the output. But is there a graphic or unique symbol that indicates that this output is the "source" of the 3.3V rail, and this USB connector pin is the "source" of the 5V and everything else receives it - something like input/output symbols on pins? Just looking for best practices. Thanks! AI: I couldn't say if there is a single "best practice" - in fact there are many standards and different companies may adopt or enforce whatever suits them best. But I can provide at least one example: Inputs, such as VCC, have traditionally been drawn as arrows in many schematics, but a number of symbols can be used. In my schematic, I use an arrow to indicate inputs to a device, such as a regulator or IC. (The arrow points in the opposite direction from what one might initially expect.) I use a circle to indicate outputs. A circle can also represent a terminal or post, but in this case it merely serves a visual purpose. (For me at least, the circle visually looks like an "O" and I associate it with "output.") Depending on your CAD software, the symbol used may or may not alter how it connects to other nodes of the same name. In Altium, with the settings I am using for most projects, the symbol is unimportant, while the net name determines connectivity. Thus, I can use VCC_OUT elsewhere with an arrow as an input, and the output of this example connects. Of course, I wouldn't name the nets in this way. They are usually something like VCC_5V0 or VCC_IO, etc.
H: Is there any use of a 65 mV reference voltage? I am a senior studying electronics, and have happened to make a bandgap reference circuit that gives out an output reference voltage of ~65 mV. I've constructed this after quite a few months of research and simulations alongside my mentor. I wasn't really paying attention to the output reference voltage I was getting, I was more focused on the circuit's performance, like its Temperature Coefficient or its Line Sensitivity. While all that seems to be decent according to my literature survey, I feel the value of the reference voltage itself isn't useful. It seems a silly question to ask my mentor, but what exactly could I use a 65 mV reference voltage for? P.S. I'm not willing to share any details of my circuit because I'm still working on it, and would like to keep the work confidential. AI: That's a sensible reference voltage for direct measurement of thermocouple voltages (65mV will cover most applications). Usually the signal is amplified before the ADC so there is no need of such a reference, of course so I'm not sure there is much there for you. Of course you can always amplify the reference to make it whatever you want, you might want to compare the output noise resulting from that compared to commercial offerings. Even a 3:1 amplification brings you up to the 200mV range. Also, as supply voltages slowly creep downward, a reference that operates from a single alkaline button cell (1.5V, maybe 0.8V at end of life) might benefit from a reference in the 50-500mV range. The (ancient) LM10 (a voltage reference plus op-amp) was not wildly successful in the market, but is still around. It has a 200mV nominal reference voltage but cannot operate from less than about 1.2V. You didn't indicate what the minimum supply voltage is for your circuit, but if it's well in the sub-1V range, that is a good feature.
H: Will internal signals impedance be affected by adjacent planes? I am routing an 8-layer PCB, and need to have strict impedance control on one of my nets. The signal layer that the sensitive net is on is in between a ground plane and a power plane. Such as: ------- GND ------- Signal ------- Vcc My question here is, will the capacitive nature of the two planes have an effect on the impedance of my sensitive net? Is it better to route high speed signals on internal layers or should I keep on outside layers under a solid ground plane? AI: Yes, both planes will affect the impedance. Although it it nothing wrong with using a power plane as a reference plane. When having impedance controlled lines between two planes, it is usually referred to as stripline. Can be symmetric (same distance to both reference planes) or asymmetric (not same distance to both planes). Although, when using ground and power planes as references for a stripline, one should make sure the power plane is well decoupled to the ground plane (using decoupling capacitors).
H: Are AC coupling capacitors required for the Clock lanes in the PCIe spec I'm working on implementing a PCIe 2.0 x2 system on a with a Xilinx Ultrascale. Reading through the PCIe 2.0 specification it requires 75-200nF AC coupling capacitors on the TX lines coming from the baseboard device. What about the clock lanes? Do those need to have coupling caps inline with them as well? I would guess it would be necessary but I can't find anything saying whether they are or aren't required for the clock lanes. AI: There are PCIe devices out there, requiring AC coupling on the clock lanes as well. This is determined by the receiver, and the most common case is that AC coupling is not needed for the clock lanes. If you are to use the FPGA as a PCIe slave device and the FPGA datasheet does not specify the clock lanes to be AC coupled, they should not be. If you are using the FPGA as a master device, it is up to the slave to determine whether it needs AC coupling on the clock or not. When designing a base board with a PCIe connector, the base board should never have any AC coupling on the clock lanes. It should then be on the daughter board if the daughter board (receiver) needs AC coupling.
H: Is there a fuse holder equivalent for a diode? When using a protection diode if it blows it does its job and saves a much more expensive component from getting damaged or destroyed. That's all fine and well but I was wondering about how we then can design this diode to be more easily replaced. Perhaps even by less technically skilled personnel (if possible). My first idea for this would be to use some equivalent to a fuse holder. I was unable to find anything and I've only seen other similar posts suggest the use of a header which seemed like a bad idea to me. So my question of course does anyone know of some sort of equivalent fuse holder for use with other components such as diodes? AI: You could put it on a PCB or mold it into a package, but it might be better to have a more robust design (or less sloppy customers). One potential issue is that a blown fuse is typically “safe” if removed whereas a shorted TVS that is removed also removes the protection. Maybe you combine a fuse and TVS into one 3-pin module. Especially since the blown TVS will take out the fuse too.
H: STM32G030 BOOT0 pin - SWCLK I designed a board with an STM32G030C8T6 MCU and some peripherals. The board is working just fine, regarding the functionalities, but I have some issues with flashing. So, the first "strange" thing to me was that the BOOT0 pin is the same as the SWCLK pin. Generally, I always pull the BOOT0 pin low through a 10k resistor and connect the SWCLK through a 22ohm resistor in series. Here, I was a bit confused. The reference manual states that the BOOT0 pin should be low in order to boot from the main flash memory, which is what I want. So, in the end what seemed to make sense to me was that I connected the SWCLK through a 22ohm resistor to the BOOT0 pin, and I also pulled it low through a 10k resistor. And then, the strangest thing happened... Yesterday, I could program the board from STM32CubeIDE with an ST-Link V3 mini. I had some issues, but in the majority of the cases, it worked, so I did not really pay attention to the programming fails. But today, I had many-many error messages, like "ST-Link device not responding" and "waiting for response", "check the power connection", "GDB server error" and such. Then I thought, since this BOOT0 vs SWCLK was the only strange thing about the design, I turned on the oscilloscope and measured that pin. I took the GND of the ST-Link as reference and measured the pin right at the MCU... And the programming was successful. Then I played around with it for a while, and the conclusion is the following: the programming was only successful if I measured the pin with the oscilloscope, it was always OK when I measured it and it was never OK when I did not measure it... (yesterday was also sometimes OK when I wasn't measuring, but not today... magic) So there it is... I don't really know where to put this information... Does anyone have any explanation? Also, is the 22ohm - 10k solution wrong? What would be the good solution in this case when the two pins are the same? A jumper maybe, so that it is only pulled down through the 10k when I am done programming? Also, this was what I measured, not the best image, 1.00V / 100ns. This seems a bit noisy to me, but this was the first time I measured the SWCLK or any SW programming pins, so I don't really have a reference. For the NRST, I usually have a 100nF capacitor to avoid parasitic resets. Should I maybe also have a 100nF capacitor for the SWCLK and one for the SWDIO pins as well to reduce noise? My only guess is that in fact the problem was that the signal on the SWCLK pin was too noisy, and that is why the programming failed. And when I measured the signal on the pin referenced to the GDN, the input capacitance of the oscilloscope probe acted as a bypass capacitor and reduced the noise so that the programming worked. But as far as I know, an oscilloscope probe should have around 10-25pF, so then a 100nF capacitance would be too much. AI: Some ideas for you to try. Check signal on ST-LINK SWCLK pin with no MCU attached. If there is something on it try powering up MCU before you power up ST-LINK. From 6.3.1 in datasheet: "PA14 is shared with BOOT0 functionality. Caution is required as the debugging device can manipulate BOOT0 pin value." Replace R19 with a jumper. See Typical SWD circuit at ARM developer site. It is not clear if you have NRST pin available on SWD connector. It is not technically required, but very helpful in situations like this. If you do have it try configuring ST-LINK for hardware reset. See this post at ST forums for details. Program BOOT_SEL bit to ignore BOOT0 pin altogether. See "2.5 Boot configuration" in datasheet.
H: How to spread a current spike? I have a 12V circuit powered by a 'smart' power supply feeding two USB sockets (similar to this one). The two sockets are parallel to each other and in series with a simple switch. Whenever I flick the switch on, the supply's short circuit protection is triggered.[a] The supply stops providing current for 10 seconds and then turns back on. This doesn't happen when I connect only either of the sockets or when I connect them one after other. My theory is that the sockets contain some largish capacitors[b] that, when connected simultaneously, simply pull too much current for a brief moment triggering the protection. If the switch is left on throughout the 10s period the protection doesn't trigger again - the supply just returns to normal operation. I assume that this is because when the supply restarts it has some kind of ramp-up period that is just enough for the capacitors to charge while slow enough not to trigger the protection. Anyway, due to physical constraints I can't add another switch to power up each socket individually. Is there some component I could insert somewhere into the circuit that would prevent the protection from triggering? Unfortunately I don't know what is the current threshold for the protection to trigger. What I do know is that each socket is rated 40 W meaning that together they must be able to pull ~7 A continuously. [a] The supply signals this on its display. [b] I deduce this from the several seconds its display stays on after disconnecting it from power. AI: Answer: Use an NTC metal oxide Inrush Current Limiter, ICL It appears the output is switched on without a soft start, so your surge current depends on the capacitance of each load and the associated loop ESR. Thus Ipk= 5V/ESRc= C * dV/dt is my best guess that with two loads the Ipkt duration is integrated to trip OCP. Thus dV/dt = 5V/ESRC is too fast for your supply with two loads. Since you can't easily modify the loads or source, one alternative is to insert ICL's for the desired current limit. You may have to get a few values to see what works with every combination of two devices connected that you have. But something in the 1 ohm R25 range will protect it. For other characteristics like operating temperature , you want to choose one with the highest R25'C resistance but also the highest current rating > 7A. https://www.digikey.ca/en/products/filter/inrush-current-limiters-icl/151?s=N4IgjCBcoGwOwE4qgMZQGYEMA2BnApgDQgD2UA2iHAHQCsABAIIjE0AcTLIHzxb1AZk59qAFmHc6E-ggmzmAXWIAHAC5QQAVQB2AS1UB5dAFl8mXAFcATvhABfYmARsk0EGkhY8RUhRAAGECUQNQ0AZVUrXW0Ac3sHEAAmP10UbCDiGGQQXQATDQBaMH8IFXVIEC5VAE9lWwrzNDs7IA
H: PSpice and calculations don't add up for an active band pass filter I designed a basic active band pass filter and used these equations to come up with a center frequency of 29.9 kHz: $$f_0 = \frac{1}{2\pi\sqrt{(R_1\|\|R_2)R_2R_3C_1C_2}}$$ In PSpice, it looks like the center frequency is almost 36 kHz. Did I use the wrong equations to calculate the center frequency? Per @Sphero's recommendation, this is what the waveform looks like: AI: Here is the result if you follow my comment above: I'm not going to check your calculations (at least right now) but maybe try simulating it with a better op-amp model and higher supply voltages. 30kHz is pretty high for a 741 (look at all that required gain!) and +/-5V is right at the minimum. Something like an AD8034 off +/-10V. And look at the output in a transient analysis at the center of the passband before trusting the AC analysis. Pretty much bang-on.
H: Parallel electret microphones I want to make an electret microphone setup for my accordion. 4 mics on the treble side and 2 on the bass side. Would I need a preamp for each mic and then mix the outputs using an opamp? Or would it be possible to make it not using preamps or an active mixer? Would the signal be loud enough for a sound card to then amplify for example? It would be nice if the mics could be powered by 48v phantom power. Could this circuit work? Using preamplifiers and an opamp mixer AI: I did a microphone bar for our accordion orchestra and it was way simpler than what you envision. I used a mini-XLR plug like those used on wireless transmitters: AKG apparently uses 4V through 4kOhm. Found that out later: my amp now has gotten 3.7V through 1.2kOhm instead. The 4V through 4kOhm variant does work as well, though. As does a +48V to mini-XLR adapter that comes with a number of affordable instrument microphones. The circuit for the microphone capsules just put 4 capsules in parallel. For volume control I ended up with a 5kOhm linear pot (you really want to use this for fine adjustments and not as a general volume control so a log pot gets too fiddly) with the wiper connected to the combined "hot" from the mics (doing it the other way round gives you wiper noise of constant volume rather than wiper noise proportional to the loudness, quite irritating at lower levels), the low side of the mics connected to signal ground, the low side of the pot connected to signal ground through a 47uF Tantal capacitor (this makes sure that the mics receive full voltage even at low volume settings) and the high side of the volume pot going to hot+power (pins 2+3) in the mini-XLR. Somewhat paranoically I wired the microphone bar exterior (electrically separated) to shield in the connecting cable and mini-XLR and put signal ground and combined hot+power through the two inner lines of a thin microphone cable. I used a 3.5mm 4-way socket in the bar itself, putting hot+power on the tip and first ring, signal ground on the second ring, and shield on shield. That way I can connect the microphone bar in a pinch to video microphone inputs with a simple 3.5mm TRS cable instead of the mini-XLR ended cable. I didn't give the 4 mics quite the same distance in order to avoid stacking comb filtering effects. If you do the shielding carefully and have a noise-free power-supply (the voltage reference of a voltage regulator is too noisy without additional capacitors), you don't need active components apart from the mics themselves to get reasonably noise-free signal, assuming capsules of good size. At least for live play (we use this for a bass accordion and after I was through with the amp as well, there is no background noise or hum between playing). Bar itself is an aluminum U profile with rubber lining on the edges to block outside sound well enough to avoid feedback. Buttonhole elastics are used for attaching to the grille screws. Padded textile tape (for bicycle bars) reduces microphoning from the bar itself. Have fun finding your own solutions!
H: Decoupling capacitors in power card This is a power card. I have highlighted the part between the EMI filter and the Transient protection module. Are those capacitors needed? As per the data sheet, there has to be an R*C cell. Please correct me if I am wrong. AI: Are those capacitors needed? The Gaia FGDS-10A-50V data sheet (page 3) recommends this: - So, if you want "better EMI performance" then you need to fit capacitors that together in parallel are equivalent to the values implied in the data sheet (extract directly above). Having said that, your circuit appears to have 3 x 220 μF capacitors in parallel and this is greater than what the table covers so, maybe you might be able to remove one capacitor but, I'd generally just leave it as it is unless there is a pressing reason to change it that you have not disclosed. Additionally, the Gaia LGDS-300 data sheet (page 10) states this: - So, if you want to meet the MIL standards for EMI compliance, you fit them.
H: Extract the nodal admittance matrix of a given circuit in LTspice I am wondering if there is a way to extract the Nodal admittance matrix of a very complicated circuit using LTspice. Like draw the circuit or automatically generate a netlist (in the case of a very complicated circuit -using python for instance-) and then ask LTspice to compute the Nodal admittance matrix. After all it is what is does to solve the circuit, right? Thanks in advance :) AI: After it is what is does to solve the circuit, right? That is incorrect. No simulator that I'm aware of solves circuit model problems by understanding anything about admittance matrices (or S parameters etc. for example). Simulators use entirely different algorithms altogether. I am wondering if there is a way to extract the Nodal admittance matrix of a very complicated circuit using LTspice. No, that isn't likely to be possible. Of course, you can take the AC analysis results and fit them to a formula involving s and that might be of some use (trial and error needed). Then you are a little closer to finding the matrices. Here's a Q and A that might help you understand how simulators work. Simple extract: - The general equations produced are nonlinear differential algebraic equations which are solved using implicit integration methods, Newton's method and sparse matrix techniques.
H: I can't figure out how to design my transistor practice circuit in way that it would work I wanted to test out making a circuit with a transistor. The way I understood transistors from online videos: The transistor (using BC327, see below) needs a closed circuit from the positive terminal through a resistor (first I used a 200 ohm resistor, but I then feared it would burn the transistor, so I used a 4.7 kohm resistor) through the base → emitter of the transistor all the way to the negative terminal. That should allow the current to pass from +Terminal+ → 200 ohm resistor → LED → transistor collector → transistor emitter → -Terminal- I enclose the schematics I made beforehand and a few angles of the actual breadboard project. Do I understand the working of transistors wrong, or did I just connect something in a wrong way? What are some additional tips to make my breadboarding look "better" or closer to any standards that there might be? AI: BC327 is a PNP transistor. The circuit in your schematic requires a NPN transistor (BC337 for example).
H: What is the function of emitter biasing of a transistor? I have been reading about transistor biasing to counteract inaccuracies in transistor manufacture, add stability etc. One circuit I can't see the benefit in, which is diagrammed in the datasheet for the PEMD17, has a resistor between the emitter and base. Of all of the standard biasing configurations I've read about, I've not read about this one. It looks just like a voltage divider on the input signal. From the datasheet, I would expect to ground pin 1, apply a signal at 2 to control a load at pin 6. The R2 seems to have no benefit other than to alter the base input. The following diagram shows how I would expect to use the circuit. Is that application incorrect? simulate this circuit – Schematic created using CircuitLab AI: R2 is there so that the circuit is in a defined state when there's no signal on R1. If you have a high or a low on the input at R1, then the circuit works like you expect - it switches the load on when the input is high and off when it is low. If R1 is left open (remove the signal generator from your diagram,) then stray voltages and currents may appear on the base of Q1. That can randomly turn your load on or off - or somewhere inbetween. R2 pulls the base of Q1 down to zero volts so that the load is off when there's no input on R1. Consider a microcontroller driving a small motor through a transistor. At power on, the output pins of many modern microcontrollers can be undefined - they are high impedance (open) until your code says to set them to output mode at a particular level. Until your code executes, the output is floating. If there's any electrical noise in the vicinity, enough current may flow through the base of the transistor to cause the motor to run. If you have a pull down on the base of the transistor, then the stray voltages will have to be very substantial to make the motor run. That pull down makes the system stable during start up.
H: What crystal oscillator for a CH340G? I think this should be a relatively simple question. I need to know what would be the best kind of 12Mhz crystal to run with a CH340G driver. I know barely anything about oscillators, and everything I found made me all the more confused. If anyone knows a simple answer to what crystal is normally used for something like that, I would be very thankful. AI: If you use just about any HC49/U or similar 12MHz crystal with a datasheet load capacitance of 12-18pF and the datasheet-recommended 22pF NP0 ceramic capacitors you will be fine. Ones with 6 or 8pF will also likely be fine. Using extremely small crystals (with low maximum drive levels) may require more analysis. The effective load capacitance is 22pF/2 + Cstray.
H: Driving a Peltier Module via N-channel MOSFET H-Bridge I'm working on a circuit to control a heating/cooling element (Peltier module) using an H-bridge. I'm using FDP8447L for that purpose. My Peltier is rated for 6 amps current and 15.4 Volts. The gate of the N-channel MOSFETS will be turned on through an output from a microcontroller that will be amplified using an optical relay hooked up to 18 volts to turn the gate on as shown in the picture below. The switching PS output is the 15V that should be passing through the MOSFETS to the Peltier module depending on which side of the H-bridge is active. My question is: When I tried to prototype this, the top left MOSFET labeled (U$9) gets really hot and starts smoking after some time. One thing I realized, was that I kept the signal that's supposed to activate the other side of the bridge floating (kept the gates of the other side of the H-bridge floating) which I think is a bad idea for MOSFETS. As silly as it might sound, but I'm really confused, to avoid this, do I need to place a pull down resistor between the gate and the source of each MOSFET? On the two upper MOSFETS U$9 & U$12, is there any difference between connecting the gate resistor between the gate and GND vs. connecting it between the gate and the source? Finally, what's a good pull-down resistor value? AI: do I need to place a pull down resistor between the gate and the source of each MOSFET? Here's what the datasheet for the AQV212S tells you: - And that certainly means using a pull down resistor of 100 kΩ or less on each floating line. You only need one per node i.e. not 1 per MOSFET. My question is: When I tried to prototype this, the top left MOSFET labeled (U$9) gets really hot and starts smoking after some time. Yes, that is a definite problem that will happen without a pull-down resistor to 0 volts. Here's the next potential problem: - It looks like you are trying to use one of the N channel devices upside down. Bad things may happen due to the internal bulk diode becoming forward biased. Try swapping for a P channel MOSFET. Maybe if there was a clearer schematic this might not be a problem. There's also some possible confusion with the lower MOSFETs connected incorrectly too (if I guess what you PELTIER- node name implies). I can't be sure about this without a clearer statement of what voltages are meant to appear on what nodes.
H: How do you convert dBm to Vrms? I'm trying to convert dBm to Vrms. The formula for dBm is \$ dBm = 10 * log(P1 / P0) \$ where P0 = 1mW so \$ +13dBm = 20mW \$ If I convert this to a voltage using the formula \$ P = Vrms^2/R \$ where R = 50 ohm, I find that \$ Vrms^2 = 20mW * 50ohm = 1000mV \$ \$ Vrms = 31.62mV \$ Now if I solve the equation a different way I get a different result. \$ dBm = 10log(P1/P0) \$ where \$P0\$ = 1mW substituting \$P1\$ for \$ Vrms^2/R \$ and \$P0\$ for 1mW we get \$ dBm = 10log(Vrms^2/(R * 1mW)) \$ simplifying \$dBm = 10log(Vrms^2/SQRT(R 1mW)^2)\$ \$dBm = 10log(Vrms/SQRT(R 1mW))^2\$ \$ dBm = 20 * log (Vrms/SQRT(R1mW)) \$ plugging in \$ dBm = +13\$ and \$ R = 50 \$ I get \$ Vrms = 0.999V\$ This is the correct answer according to some online calculators I've used. But where is the inconsistency in the first solution? AI: Your error stems from a misunderstanding of units. The square root of 1000 mV is not 31 mV. It's either 1 √V or 31 √(mV), which are both strange, non-physical units. The correct units are actually a bit different: mW ohms is (mV * A) * (V/A), so you really have a value of 1000 VmV, or 1 V^2. Taking the square root yields 1 V. 1 V^2 is likewise the same as 1000000 mVmV, and taking the square root of that yields 1000 mV, which is consistent. Working in a dimensionally consistent way we can re-do the calculation with embedded dimensions: \$P = V_\text{RMS}^2/R\ \implies PR = V_\text{RMS}^2\$, hence \$V_\text{RMS} = \sqrt{20\,[\text{mW}] \cdot 50\,[\Omega]} = \sqrt{1\,[\text V^2]} = 1\,[\text{V}]\$. \$P = V_\text{RMS}^2/R\ \implies PR = V_\text{RMS}^2\$, hence \$V_\text{RMS} = \sqrt{20\,[\text{mW}] \cdot 50\,[\Omega]} = \sqrt{1000000\,[\text{(mV)}^2]} = 1000\,[\text{mV}]\$.
H: LPDDR3 length matching I am designing a pcb using LDDR3 for the first time. There are some questions that confuse me. Should I match all DQ,DQS,DM signals with equal length? Should I match the common address CA signals with each other and with other DQ, DQS, DM signals at the same length? Is there a document you can recommend me about DDR3 pcb design? Thank you very much. AI: The ground rules: in every DQS group, the DQS, DQ and DM signals need to be matched. DQS groups are independent from each other. CA signals need to be matched. DQS must be shorter than CA for any chip. You can route CA either as a tree, or as a bus, the typical pinout on DDR3 ICs makes the bus routing a bit easier. The DDR3 controller will pretty much always support read leveling, i.e. it will delay the sampling point for the signals in each DQ group to match the length of the CA signals for that IC. If the controller does not also support write leveling (i.e. delaying the outgoing data transfer in each group to match the CA timing), then you should also length-match the DQS groups to be a tiny bit shorter than CA for each IC, so the distance between the command and the data is the same for all ICs. If the controller does support write leveling, these delays are added inside the controller and don't need to be implemented as traces. If you have multiple ranks, I'd route ODT along with CA. The controller will nonetheless run a calibration sequence to determine actual timings and where the optimal sampling points are.
H: Advice to calculate the transfer function of circuits I'm a bit confused, to get the transfer function, what's the approach to work out in the cascade arranges like these? I know it should be done using superposition, but passing R2 and cR3 I got lost and can't land a KCL equation that makes sense. I'm only asking for the technique. AI: Hint: - Just use your eyes and simplify. Here's a big start: - Now it's your turn - take this diagram and simplify each stage to just its gain values. No need to use KCL if you understand how op-amps work.
H: Grounding GPIO with separate PS to relay (not relay board)? I am trying to control a 12 VDC Bosch Automotive relay with an RPi. I am using a separate 12 VDC power supply to trigger the relay. The RPi is using GPIO18 which is connected to a 1k resistor, which is connected to the base of a 2N2222 transistor whose collector is connected to the relay output and emitter connected to the 12 VDC power supply negative lead. I am not sure if the correct grounding of the RPI would be past the transistor to the 12 VDC PS? See line with "?" in below diagram. I have read in multiple posts that RPi GPIO does not need grounding, and then have been told it could not work without grounding (but mine actually does). I would love clarification and correction of my schematic if I have it wrong. AI: Recall that collector current (from collector to emitter) is allowed to flow by a BJT transistor in response to a current from the base to the emitter. In order for the base current to flow, there must be a common ground between the Pi and the emitter. So, yes, you must make that connection if there isn't already a common ground in place.
H: Interfacing RJ45 to 3 pin RMII and bidirectionality I am trying to add an Ethernet interface to a dev board (This board specifically). From looking at the schematics, I see that it has a 3 pin PHY input (GND, TRX+, and TRX-). From my understanding, a CAT5 cable has 4 wires essentially (RX+- and TX+- and both can be bidirectional). So to interface this with say a RJ45 cable, do I just connect the TRX+ to the TX+ and TRX- to TX-, or the RX+ to TRX+ and RX- to TRX-? I'm sure I'm oversimplifying this and any guidance would be appreciated. I am planning on having the three wire board connect to another PCB that would have the RJ45 port and just wire the pins to the corresponding locations. AI: That PHY is for 100BASE-T1 (commonly known as "Automotive Ethernet" or BroadR-Reach), which is different from "standard" 100BASE-TX (FastEthernet) in that it uses a single pair for communication. Converting it to 100BASE-TX involves using some sort of active media converter. It can of course be done, but if you do not want the 100BASE-T1 you are much better of just using a standard 100BASE-TX PHY to begin with.
H: Is Ohm's law valid in AC circuits? I am confused over this and I’m hoping for clarification. By Ohm's law we can compute the resistance of a circuit as V/I. In the case of two sinusoids we have sin(x) / cos(x) or something like that. Doesn’t this give a sinusoidal resistance? I don’t understand this because resistance is a set value. A 100 ohm resistor is a 100 ohm resistor. Does the division of the sinusoids always result in a constant term? AI: Ohm's Law, in its standard formulation, applies to specifically those circuit elements which we consider resistors (or ohmic) - the voltage and current are instantaneously proportional at all times with the relation \$V(t) = I(t)R\$. This excludes an element with out-of-phase voltage and current from the standard Ohm's Law formulation. Because its voltage and current are out of phase, it is simply not a resistor and not handled by the equation. However, when discussing linear circuitry (i.e. circuits composed of resistors, capacitors, and inductors) operating at one frequency, it is possible to represent sines and cosines as complex numbers instead. This is called phasor analysis. In your example of voltage as sin(x) and current as cos(x), we can suppose that \$x = \omega t\$ (i.e. the frequency is \$\omega/2\pi\$ Hz). Then, the voltage is -1j volts (where j is the square root of -1) and the current is 1 ampere. We can then apply an extended form of Ohm's Law and say that the impedance of the circuit is \$Z = V/I = -1j \,[\Omega]\$. This formulation can be extended to other phases (not just 90 degrees); for example a resistor and inductor in parallel may have an impedance of 0.4j + 0.6 (at some fixed frequency). Of course, this extended phasor formulation agrees with the standard Ohm's Law formulation whenever the circuit is purely resistive.
H: Is there a fluid that visually displays electrical voltage/current? I have a device that subjects fluid in a cuvette to a DC voltage waveform for a few seconds. The device is pretty powerful (lots of capacitors), able to continuously deliver up to 1,000 Vdc @ 40 A through the cuvette. I am looking for a fluid to use in testing that: Visually indicates when subjected to voltage or current Note: electrolysis bubbling or temperature change isn't good enough Ideal: fluid shimmers, sparkles, or changes color Impedance somewhat resembles that of water Nice-to-have: multi-use Can be zapped multiple times with the same visual response Are there fluids out there which possess these properties? AI: water containing universal indicator will change colour at each electrode.
H: Help identify an SMD (diode?) component I suspect this is a diode: the board has PD13 marking next to it. I found a schematic for a similar product that identifies the PD13 as TVS_SMAJ20A. Would that make it a TVS diode? AI: PD13 is a designator it doesn't really tell you the part number or the part characteristics. It probably stands for "protection diode" or something like that, and it's the 13th in some kind of ordering. You need the second character in the code to be sure. It's plausible that's what it is, because the SMAJ20A (which is a part number) has the code BV. Since it has the lines on one end it's unipolar type. From the datasheet Caution though- there are maybe 10 part numbers that have a code starting with 'B' so the ID hinges on how 'similar' your similar product is. Since it has the same designator I'd guess it's very close...
H: Impedance matching conditions for matching network I'm trying to understand general concepts involved in impedance matching and I have a question about the conditions which should be satisfied by the matching network. Assume we have in the most general case the classical problem of matching impedance between a source S with impedance \$Z_S\$ and a load L with impedance \$Z_L\$: The most general strategy is to put an impedance matching network between source and load (which is a circuit that can be relatively simple, like an L- or T-network, or a transformer, but also can be much more complicated, depending of the actual problem), and the task of the practical impedance matching is then to adapt the parameters of the components in the matching network such that the impedances of source, load and matching network satisfy certain conditions. Now I read that the conditions for the matching network that should be satisfied by involved impedances depend on two auxilary impedances: the input impedance \$Z_{in}\$ and the output impedance \$Z_{out}\$. These two arise as follows: we can replace the network Firstly (I) by an equivalent circuit where \$Z_{in}\$ "summarizes" the impedance of the matching network & load replaced in one common impedance \$Z_{in}\$. In case of an L-matching network here Andy aka provided an explicit calculation of \$Z_{in}\$. And secondly (II) we can also replace it by The generator and the impedance \$Z_{out}\$ replace the source (generator & \$Z_{S}\$) and the matching network. Note that here the calculation of \$Z_{out}\$ is a bit more subtle because we have to take into account the generator \$V_S\$. But the derivation of \$Z_{out}\$ from given \$Z_{S}\$ and the matching network is not the subject of this question. If one has fixed a matching box there is an arsenal of techniques available to do it, e.g. by transforming the source and matching network by a sequence of Norton and Theverin transformations until they have the desired shape in the picture above. My concrete question is: Assume we can calculate \$Z_{in}\$ and \$Z_{out}\$ as functions of the parameters of the components sitting in the matching network and our goal is to find the optimal parameters for these components in order to archieve an impedance match via maximum power transfer. Which are in most general setting the conditions on \$Z_{S}\$, \$Z_{L}\$, \$Z_{in}\$, and \$Z_{out}\$ which should be satisfied in order to obtain the impedance match? Proposal: Should always simultaneously be satisfied both - (I) \$Z_{S}^= Z_{in}\$ and (II) \$Z_{out}= Z_{L}^\$ - or does it suffice only to archieve (I) \$Z_{S}^= Z_{in}\$? Why I'm asking this: several times I found in the net tutorials about impedance-matching methods that the authors only focus on \$Z_{in}\$ and ignore the discussion about \$Z_{out}\$ completely. AI: If you do matching at one port the other port will also get matched. Consider a simple L impedance transformer: simulate this circuit – Schematic created using CircuitLab It is easy to show that around resonance frequency: $$R_{in} \approx \frac{R_P}{\omega^2C^2R_P^2} = \frac{R_P}{Q^2}$$ Now, suppose you have a matched source at input, as shown below: simulate this circuit The output impedance becomes \$R_{out} = Q^2R_{in} = R_P\$, which is matched to load impedance. So you need to match just once either at output or input. This can be proved in general for any matching network. There could be other ways to prove it but this is what I can think of. Consider the matching network as shown below which is transforming source impedance \$Z_s\$ to load impedance \$Z_l\$. Let's say that the input is matched for maximum power so \$Z_{in}= Z_s^\$ simulate this circuit Now, let's switch and apply the voltage at the other port of the matching network as shown below: simulate this circuit Since impedance looking into the input port is still \$Z_s^\$. This means that maximum power is transferred from the matching network into the source impedance. Since the matching network itself is lossless, this implies that this power is same as that transferred to the output impedance of the matching network, \$Z_{out}\$. Thus, the only way that the power transferred to the source can be maximum is if power transferred to the load \$Z_{out}\$ is maximum. That is if, \$Z_{out} = Z_l^\$.
H: What is this component, is this a microphone? I was researching projects and I saw a PCB. I am wondering what is this component. I don't know what it is so I want to ask you, what is this component? Is this a microphone? I am asking about this big white thing. Top side: Bottom side: Another PCB design, again they say they use microphone. AI: It's a light guide, a piece of plastic that is intended to be illuminated by a LED.
H: Change range of a DC signal without changing the offset with op amps I have a voltage signal with the following range: low - 2.5VDC middle point - 2.725VDC high - 2.95VDC I would like to condition this signal to: low - 0.4VDC middle point - 1.65VDC high - 2.9VDC I have only a +/-12VDC power supply available, op-amps, capacitors and resistors. Anybody has any suggestions on how can I do it? Thanks! EDIT: Added by DKNguyen for clarification. AI: Try this code imported into Falstad Circuit Simulator $ 1 0.000005 10.20027730826997 57 5 50 5e-11 v -176 224 -176 176 0 0 40 2.5 0 0 0.5 w 304 304 304 352 0 a 304 288 448 288 9 15 -15 1000000 1.4249675011270142 1.4249715005717007 100000 w 448 288 448 352 0 r 304 352 448 352 0 45550 r 208 352 304 352 0 10000 w 208 208 304 208 0 w 304 208 304 272 0 O 448 288 512 288 0 0 a 64 208 208 208 9 15 -15 1000000 0.7124857502849943 0.7125 100000 v -80 320 -80 272 0 0 40 -1.075 0 0 0.5 r 0 160 -80 160 0 50000 r 0 224 -80 224 0 50000 w -80 160 -128 160 0 g -80 320 -80 336 0 0 r 64 272 208 272 0 10000 w 208 272 208 208 0 w 64 224 64 272 0 w 0 224 64 192 0 w 64 192 0 160 0 g -176 224 -176 240 0 0 r 64 272 64 336 0 10000 g 64 336 64 352 0 0 v 208 400 208 352 0 0 40 1.65 0 0 0.5 g 208 400 208 416 0 0 x -241 102 -210 105 4 15 Input x -163 304 -113 307 4 15 -1.075V x 149 379 186 382 4 15 1.65V x -67 109 -4 112 4 24 Offset x 42 107 367 110 4 24 Offset\sCompensation\sAmplifier x 329 222 599 225 4 24 Dynamic\sRange\sAmplifier w -80 224 -80 272 0 S -128 160 -176 160 0 0 false 0 2 S -176 144 -224 144 0 0 false 0 2 v -224 208 -224 160 0 0 40 2.725 0 0 0.5 v -272 176 -272 128 0 0 40 2.95 0 0 0.5 g -272 176 -272 192 0 0 g -224 208 -224 224 0 0 w -272 128 -224 128 0 Not very elegant, but I'm not sure if op-amp offsetting circuits ever are. The structure is a summer to offset the voltage center by -1.075V so 2.725V becomes 1.65V. The resistor divider nature of the summer halves the output voltage from what it should be so I re-amplified it by two relative to GND to compensate. Then the re-centered signal is fed and amplified by a gain of 5.555 to change the dynamic range from \$2.95V-2.5V=0.4V\$ to \$2.9V - 0.4V = 2.5V\$. The amplification here takes place about 1.65V (rather than GND) so that the signal center is preserved.
H: Why doesn't my LTSpice simulation get the same results as this one? Here's what i want to have as a result: Here is what i have: I have an ideal op amp and the green curve only hits 5 Volts when input is 2.7V, in the video it's 2.55. The green curve only hits 0 volts when input is 2.3V, in the video it's 2.45 V. Why is this happening? AI: You are running in to speed issues with the opamp where the output is delayed from the input which gives the impression that your hysteresis band is wider. Slow down your ramp so your rise and fall times are 500ms like the TI demonstration and you'll get results closer to the TI demo.. Also, opamps have issues being used as a comparator since coming out of saturation will cause excess delays. Better to use a comparator which is made to quickly come out of saturation. You can use the LT1017 which is slow enough to see issues if your ramp time is too fast.

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