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H: Buffer op amp amplifier saturation
I have designed a buffer amplifier using an LM358 op-amp, with an input of a 1kHz sine wave and a power supply of +/-6V. whenever I increase the input sine amplitude above a certain threshold, I get a weird output (unlike the normal saturation that we all expect such as the one in Figure 1).
Figure 1 (Above). Normal saturation.
Figure 2 (Above). Weird unexpected saturation.
Why is the saturation in Figure 2 like that? I am used to Figure 1's output but not Figure 2. I guess it's linked to the -+ 6 Volt supply, but I'm really lost.
I've tried looking online for similar waveforms, but I found nothing.
AI: The "weird" output looks like "phase reversal", which can occur in some op amps when the input common mode range is exceeded:
Source: https://www.analog.com/media/en/training-seminars/tutorials/MT-036.pdf
The TI datasheet for the LM358 indicates that the input common mode range has a maximum of 1.5V below the positive power supply voltage, i.e. 4.5V in your case. As pointed out in this thread on TI's E2E forum, the LM358 is susceptible to phase reversal.
The LM358 model in your simulation is evidently accurate enough to model this phase reversal behavior, but in general you need to keep your op amp within its specified limits (input common mode range here) in order for the simulation to reliably model reality (and you need to keep a real op amp within its specified limits anyway).
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H: Do datasheet specs for a dual diode refer to both diodes in series or to the individual diodes themself?
The question: With a dual diode such as the MMBD3004S (datasheet here), are the ratings such as reverse breakdown voltage specified for each diode individually, or for both the diodes combined? There don't appear to be any notes in the datasheet specifying either way although, at a guess, I'd lean towards the former. Hopefully, someone can clarify one way or the other for me.
The context: I'm designing a high-voltage flyback power supply using the LT3420, VOUT of 190V, VBAT of 5V and N of 16. As a result, the peak reverse voltage for the rectifying diode is approximately 450V by my calculation (using the equation on page 12 of the datasheet here).
AI: The reverse breakdown is for each diode. Two in series will yield double the breakdown voltage.
The LTC datasheet specifies the Vishay GSD2004S SOT-23 type with the diodes in series. That diode has a breakdown of 240V (480V combined), so the Diodes Inc device should be even better, yielding a combined breakdown of 600V.
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H: How much current for a 5V 60 LED/m WS2812B 5m LED strip?
I'm planning on controlling a 5m 60 LED/m WS2812B chip 5V strip with a Raspberry Pi Zero W. According to the website it draws 18 watts per meter (90 watts total). What current would this strip draw, and what would you recommend on powering both the Pi and the strip from one PSU? Any link to some decent, budget ones would be appreciated.
AI: 90W at 5V comes out to 18A. You can find several 5V 20A power supplies around.
P(power)=V(volts)*I(amps) therefore I=P/V 90W/5V=18A
I have built several similar projects using WS2812b with Arduino and LPD8806 with Raspberry Pi. I used this 5V 60A power supply and it has been running in my attic for years with no issues. Its a bit large for what you need but at $20, you're not going to find much cheaper.
Unrelated to the power supply, its a lot easier to use the LPD8806 or some similar 4 pin cable with RPi because you can control the clock. The three pin addressable strips need to have their data output at a very specific frequency and it can be troublesome to run long strips. It can be done, especially with the short run you have, and the 3 pin version are usually cheaper.
P.S. Hardware Recommendations is a good site for these kinds of questions.
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H: Questions about the voltages of a lithium jump starter I purchased
I purchased an Audew jump starter based on several favorable reviews on youtube.
According to the specs, the jump start output is 14.8V, but when I check the voltage with my multimeter it measures 16.3V.
The jump starter also has a 15V/10A output for a cigarette lighter adapter. The actual voltage for this also measured 16.3 which I guess is no surprise. I tried to power a 150W inverter but the inverter wouldn't even power a 15W device - I'm assuming the inverter can't handle the 16V?
My bigger concern is if it is still safe to use this battery to Jump Start a car? I understand that a car needs greater than 12V to start, but is 16V too much to risk damage?
AI: Summary: The jump start pack voltage of 16V + will drop to around the current battery voltage as soon as it is connected. There is good reason to expect it to be safe to use. *
The following is based on the characteristics of LiIon battery chemistry.
It is extremely likely that the equipment is 'fit for purpose'. As in all such cases, caveat emptor*
The charging device appears to be using 4 x LiIon cells.
A typical Lithium Ion cell has a maximum fully charged voltage of 4.2V.
Anything in the range 4.0 - 4.2V can be considered charged. Lower Vmax leads to longer cycle lifetime in exchange for a moderate reduction in per cycle energy capacity.
A typical cell is quoted as having a nominal voltage of 3.6 ot 3.7 volts. This is the nominal average voltage across a discharge cycle.
So 14.8/4 = 3.7V / cell = expected nominal voltage.
16.3 / 4 = 4.075 V which is inside the 4.0-4.2V range.
This has the advantage of allowing a simpler and safer charge termination system if they choose to use it. It will not noticeably affect charged capacity.
Automotive electronics must be engineered to withstand "things that happen" in a typical automotive electrical system. Voltages over or well over the nominal 13.8V max of the system can happen under certain normal operating conditions.
The jump start pack voltage of 16V + will drop to around the current battery voltage as soon as it is connected. There is good reason to expect it to be safe to use*.
150 W Inverter
The pack should be able to power a 150 Watt load (about 10 amps)- although it is possible that it will work well as a jump start pack while failing to power such a load. If the inverter starts on the original 16+V the voltage will usually almost immediately drop to well under 16V under a substantial load. If it operates but does not provide much power, measuring voltages at the source and at the inverter terminals may help assesss why.
This is because most jump starting devices do not do function in the manner that they claim or that they are commionly believed to work. In almost all cases the devices do NOT power the vehicle starter motor directly. Instead, they transfer charge to the "dead" battery, providing it with the ability to return most of this energy in a short period when the next starting attempt is made. This is a fortunate but little appreciated 'feature' of typical lead acid automotive batteries.
I once jump-started a vehicle using 2 x 6V 3 Ah batteries in series, connected by a length of bell wire. This was being used as a camping light supply - which job it did well. Maximum current available at cranking voltages at the end of the bell-wire would have been a few amps. 10 minutes or so trickle charging of the 'dead' battery allowed the vehicle to start. Over decades I have regularly jump-started vehicles using jumper leads and clip connections that would have been wholly incapable of providing cranking level currents directly.
*Caveat emptor -> let the buyer beware -> It's your responsibility.
These diodes are potentially suitable. This is a Digikey selector guide of diodes of 10A plus, through hole or stud or plate mount. Unusually in this case you want high forward voltage drop. eg These cost $US0.64/1 in stock at Digikey and drop 1V at 10A. 1 or 2 in series would drop the voltage initially. A relay or switch across them will allow lower battery voltage operation without loss. These have the advantage that they do not need heat sinking - but will get very hot at 10A - about 100C rise above ambient! (which they are rated for !).
These are 64 cents and drop 2V at 10A and need a heatsink.
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H: 8X1 MUX using Verilog
I am trying to write a design and a testbench Verilog code for a 8X1 MUX with input width of 8 bits each.
Here is my design code :
module MUX8_1(
input [7:0] a[8],
input [2:0] sel,
output reg [7:0] y
);
always @ (sel) begin
case (sel [2:0])
3'b000 : begin y [7:0]<= a [0];end
3'b001 : begin y [7:0]<= a [1];end
3'b010 : begin y [7:0]<= a [2];end
3'b011 : begin y [7:0]<= a [3];end
3'b100 : begin y [7:0]<= a [4];end
3'b101 : begin y [7:0]<= a [5];end
3'b110 : begin y [7:0]<= a [6];end
3'b111 : begin y [7:0]<= a [7];end
default : begin $display ("error " ) ; end
endcase
end
endmodule: MUX8_1
Here is my testbench
module testbench_MUX();
reg clk;
reg [7:0] d[8];
reg [2:0] select;
wire z ;
MUX8_1 mux(.a(d) , .sel(select),.y(z));
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
initial begin
clk =1;
forever begin
/* toggle the clk every 50 time units which is configured in
the simulation to be 1ns*/
clk = #50 ~clk;
end
end
initial begin // {
d[0]= 'h00;
d[1]= 'hA1;
d[2]= 'hA2;
d[3]= 'hA3;
d[4]= 'hB4;
d[5]= 'hB5;
d[6]= 'hB6;
d[7]= 'hB7;
for ( int i=0 ; i<=7 ; i++ ) begin
@ ( posedge clk);
select = i;
end
@ ( posedge clk);
$finish;
end // }
always @(z) begin
$display ("at t=%0t : select='b%3b, output= 'h%0h",$time,select,z) ;
end
endmodule
However the output is wrong :
# KERNEL: at t=100 : select='b000, output= 'h0
# KERNEL: at t=200 : select='b001, output= 'h1
# KERNEL: at t=300 : select='b010, output= 'h0
# KERNEL: at t=400 : select='b011, output= 'h1
# KERNEL: at t=500 : select='b100, output= 'h0
# KERNEL: at t=600 : select='b101, output= 'h1
# KERNEL: at t=700 : select='b110, output= 'h0
# KERNEL: at t=800 : select='b111, output= 'h1
So where is the problem ?
AI: The code is not VHDL. It is not legal Verilog either because input a is two dimensional (ports can only be single bits and one dimensional vectors in Verilog). It is legal SystemVerilog; the successor of Verilog.
The reason z only has the value of 0 or 1 is because it was defined as a single bit (wire z;). There should be a compile warning. Change it to 8-bits (wire [7:0] z;) and that should fix the output.
Other note:
always @(sel) should be always @* (or always_comb for SystemVerilog). The former is not sensitive to changes on a for simulation. The latter figures out the sensitivity list automatically.
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H: LCD backlight connection, K pin connected only
I have been trying to build the attached schematic, and my issue lies with LCD backlight.
The designer has attached the cathode (K) pin, but not the anode (A) pin. This did not work for me. It is an old schematic, and is designed for an LCD with only 14 pins + A and K, without the newer 15 and 16 pins.
I was wondering how only using the K pin could be possible, and if there was anything I could do to get my newer module to work?
AI: Sometimes there is a place to mount a series backlight resistor right on the LCD display- maybe to the +5V pin 2. Probably something like 100 to 220 ohms is appropriate, sometimes as low as 50 but take care not to damage the backlight.
There is a lot of variation between different common LCD displays for the backlight connections.
For your newer module, you would connect A to +5 through an appropriate resistor and K to the MOSFET drain. The LCD datasheet should supply guidance as to which of 15/16 is A/K (usually 15 is A, 16 is K) and what resistor is required. Sometimes there's already a suitable resistor mounted on the display, but don't count on it or you could fry the display.
The original circuit appears to have had a resistor on the display, as none is shown on the schematic.
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H: What are these four pin components labeled LB-4 on a motor control circuit from 1979?
This board performs the speed control logic for a 3 HP shunt-wound DC motor driver in a CNC mill built in 1979. The spindle turned on intermittently last week and then stopped working, so I'm reverse engineering the circuit to debug it.
I've ID'd everything except these three black components with the blue dots near the card edge connector. They each have four leads, and the only markings are "LB-4", a little chat bubble like logo, and +, - markings for two of the leads.
There's no continuity between any of the leads. Can anyone help me identify these?
I'm also not certain about the three big green bricks. They seem to just be power resistors but the markings on them say
E M L
2.2K 100
(logo) 0.60
for the large two and
1K 100
(logo) E.776
for the small one, where (logo) is a little downward arrow in a circle. What has me skeptical about the 'power resistor' guess is that they measure more than 2.2 kohms.
Edit: Back image:
AI: Those black components look like bridge rectifiers to me.
The resistor in the bottom left looks burned out. Try replacing that first.
Excellent job overlaying the mask you added to the latter image.
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H: AC-DC High voltage converter
I don't have much experience with power electronics but I'm trying to design a power supply with AC 220Vrms (311peak) to DC 1500V converter to charge a capacitor in 50 miliseconds (and keep charging it, since it'll discharge as soon as it reaches 1500V).
Conventional transformer + bridge rectifier dissipates a lot of power through the resistor needed to limit the current that charges the capacitor.
So, I'm thinking about using a bridge rectifier + a boost converter (with IGBT) to do that, like the following schematic:
Note that, with duty cycle of 60%, the voltage reaches 1500V in 50ms:
The problem here is the inductor, that using 5mH the current is too high:
I've found some 5mH inductors that can handle high currents like this but its purpose is for filtering and not store energy for switching.
Should I use another topology for the ac/dc converter? Any thoughts?
AI: For safety, you should use a flyback transformer as the output, to provide isolation between input and output. However, driving a the flyback primary inductance and driving a boost inductor have essentially the same issues, so I'll concentrate on the boost converter you've illustrated. Note that a boost converter delivers an uncontrolled output current into loads below your input rail voltage, a flyback stays controlled all the way down to zero load volts.
For safety, you must use a mains isolation transformer on the input should you come to work on this. Working on directly connected mains components is a recipe for accidents. At best you toast your oscilloscope, at worst you toast your house, or you and your nearest and dearest.
You can design away the 'current is too high' problem. Put a current sensor resistor into the emitter of the IGBT, and switch it off when the current reaches your target current, rather than using a fixed duty cycle. This will have two profound effects. You control the peak current down, to just below the max of your inductor. You control the trough voltage currents up, to keep charging at all times.
Use a reservoir capacitor on your input bridge, you're wasting significant amounts of time not really charging your load due to low input voltage. A more even charging current means the peaks do not have to be as large.
I recently tore-down a switch-mode LED driver, and it had a (to me) novel capacitor/diode arrangement after the bridge rectifier. This is a win/win/win arrangement that reduces capacitor values and improves power factor, but only for switch mode loads that can use low voltages efficiently. The two capacitors charge in series, at a total of half their capacitance, reducing their peak charging current. However they discharge in parallel, which allows the bridge voltage to fall so that most of the work is done by the mains input, and then hold over at half the input voltage, with twice the capacitance. No 'balancing' is needed, their voltage is equalised every discharge cycle.
The main problem with your choice of inductor is not that it's a 'filter type', but that it's iron cored, so really intended for mains frequencies. You're running it at 1kHz. That's a very unusual frequency to run a boost converter at. Too high for efficient iron magnetics, too low to make use of the speed potential of your IGBT and ferrite magnetics.
Your IGBT, with a high current base drive (use a gate driver IC) could manage switching frequencies an order of magnitude higher, or more, allowing the use of a far smaller inductor, which would need to be ferrite cored. Think in the 20 kHz to 100 kHz region, still a managable speed for low switching and magnetic losses, and high enough for reasonable size magnetics.
simulate this circuit – Schematic created using CircuitLab
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H: Linear Circuit and System Interpetation
My question is about interpreting a given circuit as being itself a linear system. We know that a linear system needs to satisfy the superposition principle: if \$f(ax_1+bx_2)=af(x_1)+bf(x_2)\$. This means that a zero input should result in a zero output. Circuit components like ideal resistors, capacitors, inductors, etc. are linear since their element laws obey superposition (\$ V_r = IR, \hspace{6pt} V_i = L\frac{dI}{dt}, \hspace{6 pt} V_c = \frac{1}{c}\int I\hspace{2pt} \mathrm{d}x\$, etc).
But given a circuit that contains current or voltage sources, for example, isn't this now a nonlinear system?
Take for example some Thevenin circuit equivalent like the one below with its i-v curve at its port. The i-v curve doesn't pass through the origin since the Thevenin equivalent has a voltage source inside of it and so it has a nonzero open circuit voltage, so this system has a technically nonlinear i-v relationship.
So some bottom line questions:
Sources have nonlinear i-v curves; are they included as part of "linear" circuit theory since they should actually be considered inputs as opposed to components of the circuit itself?
A circuit containing resistors with i-v characteristics of the form \$V = IR+V_0\$ where \$V_0\$ is some constant could not be considered a linear circuit and you could no longer employ superposition analysis or Thevenin/Norton analysis, correct?
Does it even make sense to try to define an input/output of a two terminal device? I was originally going to say that the Thevenin equivalent circuit below had nonzero "output" current for zero "input" voltage but I'm not sure if that's even meaningful to say.
AI: But given a circuit that contains current or voltage sources, for example, isn't this now a nonlinear system?
It is not strictly a linear system.
But if you consider only its response to an AC stimulus, it may still behave as a linear system.
Therefore we often call something a "linear circuit" even if it is not a linear system.
In any case, we almost always apply linear circuit theory to circuits that are not in fact linear, but that behave linearly in response to perturbations of the input around an operating or bias point. (Physicists talk about perturbation theory as a general method of finding linear approximations to the behavior of nonlinear systems, and linear circuit theory is one example of this)
A circuit containing resistors with i-v characteristics of the form \$V = IR+V_0\$ where \$V_0\$ is some constant could not be considered a linear circuit and you could no longer employ superposition analysis or Thevenin/Norton analysis, correct?
You can still do Thevenin and Norton analysis because Thevenin and Norton equivalents apply to networks containing a combination of linear resistors (or impedances if we get into AC analysis) and ideal sources.
Your "resistor" is basically a series combination of what the rest of us call a resistor and a voltage source. It's actually already its own Thevenin equivalent. And so long as the \$R\$ coefficient isnt' 0, we can also find a Norton equivalent for it.
Does it even make sense to try to define an input/output of a two terminal device?
We can choose either voltage or current as an input, and the other as output.
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H: bridged emitter follower - how does it work?
I built a rough test version of the above circuit, it is intended as a bridged (i.e 'balanced') unity gain buffer for headphones.
The test circuit seems to work, as in there is sound and it is not blatantly distorted .
The op amp outputs in the circuits are from the balanced XLR output from my DAC, therefore the op amp circuit is internal to the DAC and can not be modified, it's just there for clarity.
If possible my aim is to have distortion no worse than a typical emitter follower (e.g single supply, ac coupled, dc biased) with this circuit, but with a reduced number of parts.
Would this behave like a typical emitter follower or is there any obvious issue?
There are 2 things I'm most interested to know and will be do my best to describe them:
1. The load 'floats' between the 2 outputs it seems, how does the NPN handle negative voltage swings from the op amp?
For example, If the negative side of the load (300 ohm headphone) were connected to -12V supply instead of the output of the negative half as it's shown in circuit then the NPN would be able to source current even during negative voltage swings on the op amp output.
So what happens during negative swing when it is connected 'floating' between the negative and postive halves? can the NPN still source current during negative voltage swings from the op amp?
2. The -12V supply is treated as ground for the NPNs, this means Re is connected to the output of the negative voltage regulator, does this matter?
Would it be better/worse to instead connect Re before the regulator, to the negative output of bridge rectifier?
This would resemble a more 'normal' single ended supply for the NPN... you would never see a negative regulator on ground for a single supply.
To be clear I am not looking for a 'better' alternative to this circuit, I want to know the problems with this circuit and, if they exist, solutions.
If problems exist without solutions then my alternative will simply be to build the standard single supply, AC coupled emitter follower
AI: For (1), the NPN can't sink current though its emitter, it can only source. R(e) is sinking both the load and transistor current during the low-swing. The way to make a transistor sink current on the low side is to use a push-pull (class B) type driver, which doubles the number of transistors, but is much more efficient.
Anyway, so R(e) needs to be reasonably low enough to sink your load. For 300 ohms it should be about... 300 ohms.
For (2), your input is bipolar, and so is the op-amp output Vout. The amp output will swing above and below ground, with its gain set by R1 and R2. For the NPN emitter-follower to track that, it needs to be able to follow the op-amp down to Vout - V(be).
For example, if op-amp Vout is -1V, then V(be) will need to be able to follow down to -1V - 0.7V = -1.7V. So you need the negative Ve supply.
(n.b, typical NPN V(be) is 0.7V)
If you want to be able to use ground for V(e), that is, for the amp to be uni-polar, you need to add an offset the input signal to bring it such that Vout swings between V(be) and +12V. You can do this by AC coupling it and using a voltage divider to set the bias at the op-amp input to at least 6V+Vbe, or +6.7V. That's what's shown in this link.
Anyway, I did a quick Falstad sim of your setup, with a small change. Try it here: link
Two more things. First, if you take the op-amp feedback from the NPN's emitter instead of the op-amp Vo, you will get better accuracy: V(e) will be a copy of the input owing to the negative feedback to the op-amp. This is in the sim; the op-amp gain is set to 1.
Second, it's not strictly necessary to have the DC blocking caps to the load, since in theory the two emitters should be at the same voltage when the input is at zero and so no current will flow through the speaker. At the very least you could get away with just one DC blocker. You can edit the sim and try it yourself.
MORE: If you poke around in Falstad, you'll find in the 'Transistors' pull-down there's a sample push-pull driver. You can enhance that one using the op-amp feedback, like I showed you for the emitter-follower version. The op-amp will help mask the crossover distortion inherent in the push-pull.
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H: Why is my set up short circuiting?
Disclaimer: I'm a noob.
I have the following schematic (updated as per @Transistor):
I had first tried this out on my breadboard. It worked fine. From what I read online, this was two capacitors set up in parallel.
When I do the setup on a PCB prototype board, it short circuits (I'm assuming it is a short circuit because the lights of my Arduino Uno go off.)
Is this enough information for someone to be able to tell me what I'm doing wrong? I can post a picture of what the setup actually looks like if needed.
AI: There isn't enough information in the question to answer fully but your schematic is not correct.
simulate this circuit – Schematic created using CircuitLab
Figure 1. 5 V supply, decoupling capacitors and servo connection.
If you can clarify in your question what is going on we will help further.
Figure 2. The short-circuit.
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H: ngspice simulation : random signal source
I'm new at the ngspice simulator and I don't understand this line of a Netlist that I found
Vn 1 n1 dc 0V ac 1mV trrandom(1 5us 0s 125m 0m)
if the random signal is only used in the transient simulation why did they keep the ac signal with an amplitude of 1mV ?
AI: It's just in the manual
:
4.1.8 Randomvoltagesource
The TRRANDOM option yields statistically distributed voltage values, derived from the ngspice random number generator. These values may be used in the transient simulation directly within a circuit, e.g. for generating a specific noise voltage, but especially they may be used in the control of behavioral sources […] to simulate the circuit dependence on statistically varying device parameters. A Monte-Carlo simulation may thus be handled in a single simulation run.
You should read the line as follows:
Vn 1 n1 dc 0V ac 1mV trrandom(1 5us 0s 125m 0m)
--
name of voltage source
Vn 1 n1 dc 0V ac 1mV trrandom(1 5us 0s 125m 0m)
----
nodes the voltage source is connected to
Vn 1 n1 dc 0V ac 1mV trrandom(1 5us 0s 125m 0m)
-----
type and value of voltage source for transient analysis
Vn 1 n1 dc 0V ac 1mV trrandom(1 5us 0s 125m 0m)
------
AC amplitude for ac analysis
Vn 1 n1 dc 0V ac 1mV trrandom(1 5us 0s 125m 0m)
+++++ --------------------------
adds statistically distributed voltage values to the DC of 0V (the +++ part)
According the specification of TRRANDOM(TYPE TS <TD <PARAM1 <PARAM2>>>) in your example
the noise is uniformly distributed
the duration of an individual voltage value is 5 us
time delay parameter is not used
the noise has an amplitude of 125mV
the noise has an offset of 0mV
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H: Switching 12V 2A witch raspberry pi 3.3V
I've bought an LED strip with 3 Colours. Each colour schould be switched individually. Sadly I couldn't find any Mosfet suiting my applecation and I'm not really good at finding Mosfet's or drawing Scematics. The Mosfet should be able to:
Switch fully on with the 3.3V from my raspberry pi
switch up to 2A
simulate this circuit – Schematic created using CircuitLab
It would be great if you could either give me an example for a suited Mosfet or Point out to me how to find the Right one!
Thanks in Advance!
P.S.: I'm sorry for the rude tone, but I'm not a native english speaker and not the best at it.
AI: Here are three suggestions to choose from:
Look at this answer: https://electronics.stackexchange.com/a/81138/250420
Look up logic-level MOSFETs
If you really want to use the MOSFET you have, there are easy circuit solutions. Here is one. Note that if you are using an LED array with built-in resistors, designed for 12V, you won't need the series resistor R3. Also, be attentive to the power deposited in that resistor, maybe divide it into several if necessary:
simulate this circuit – Schematic created using CircuitLab
R1 is there so that if the RPi is not connected, the LEDs are off. Otherwise, it is not necessary. R4's value is chosen high enough to limit the base current of Q1, but low enough so that when the RPi GPIO voltage is low, the base voltage is low enough to turn off Q1.
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H: Terminology of AC -DC converters
I would like to ask about the difference between the terms "AC-DC Converter", "DC-AC Converter" and "Inverter".
If I am getting it right, the "AC-DC converter" converters AC voltage to DC.
The "DC-AC converter" turns DC into AC.
The inverter can do both?
To be more specific I am working on this configuration:
This topology is characterized by four-quadrant operation. Some authors call it "Three - phase voltage source Inverter" while other "Bidirectional AC-DC Converter". Which is the proper terminology ?
AI: The schematic shows a basic 3 phase inverter with back-EMF clamp diodes which may also be used with a generator to convert AC to DC and appropriate changes in phase-control of gates. With that additional application in mind, it can support bi-direction conversion.
The DC to AC conversion feature alone is most commonly referred to as an AC Inverter.
The article entitled HIL co-simulation of finite set-model predictive control using FPGA for a three-phase VSI system is a post-graduate level article that does not focus on these basic controls. These are perhaps better described in your beginner electronics textbook or in Wiki.
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H: Thermocouple amplifier and cold junction compensation
I am trying to design a thermocouple amplifier with cold junction compensation. I already designed a simple amplifier for the thermocouple using LM358. Note that I can built this entire circuit using only cheap and easy to find components, such as low power transistors, LM358, LM324, resistors, diodes, pots, trimmers. I know that I could buy from the internet modules, but I can't at this moment .
I also need a cold junction compensation, which should be connected to Arduino, to an analog input.
Schematic: https://ibb.co/Sfs9dPX
AI: I already designed a simple amplifier for the thermocouple using
LM358.
Unfortunately, the LM358 makes a very poor amplifier for thermocouples given that it has an input offset voltage that may be as high as +/- 3mV. Given that a thermocouple (K-type for example) produces 41 μV per degree celcius, it means that your temperature accuracy is only to within +/- 3000/41 = +/-73 degrees celcius.
Here is your proposed design and some figures from the LM358 data sheet and, at the bottom the graphs for various thermocouples: -
This is not the intelligent way to design thermocouple amplifiers - use a precision InAmp (like the AD8221) if you want anything like decent accuracy. Use a negative rail so that if someone connects the thermocouple backwards you can still retrieve measurements (albeit them being negative). The cold junction compensation is trivial so, get your basic amplifier design right first.
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H: What is the purpose of this polygon arrays on PCB?
I'm interested what is the purpose these polygon array on below picture.
Thermal management?
Thanks for the help!
AI: It's called "copper thieving". The copper is added to areas with low density of copper to create a more even distribution across the board. Even distribution helps ensure that the plating thickness is fairly even, and you don't get areas with little copper and very thick plating, and areas with heavy copper density and very thin or even missing plating. This can also affect hole plating for critical areas such as press-fit connectors.
The added copper is typically added by the PCB manufacturer, in collaboration with the customer, obviously, since adding copper in otherwise blank areas may violate some other intent of the designer. Altium comments on it. Here is a useful blog entry with design tips for avoiding problems when the fabricator adds thieving to outer layers.
Edit: Typical note to fabricator:
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H: Buck Converter with RLE Load
I am trying to calculate the duty cycle of the buck converter as in the figure for discontinuous conduction mode of operation. I have worked to the math and have got the following graph as in the picture-
The Duty cycle depends on the load current. How we find out the on time if we do not have the load current?
AI: You can't figure out how long your switch is going to have to be on without knowing what current the load draws!
Remember, the physical idea of your converter is "charge the field in an inductor, exactly as much as necessary to supply the right output voltage".
A load takes energy from that field, so you'll have to replenish that, and that's exactly what you do during your on time. So, if less energy is taken, then there's less on-time.
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H: 4 Layer PCB Altium - 2nd Layer Ground, others Thermal
I read since a long time but never had an account, now its my turn to ask a question on here:
I have an idea but currently unsure if that works technically or if it is good design:
1st (Top Layer) : SMD Devices + Routing
2nd Layer : Ground Plane (only Ground)
3rd Layer : Thermal Plane
4rd Layer : Thermal Plane + THD Connections.
So all of my devices are SMD, apart of a few connectors which are THD.
The 3rd and 4rd Layer are only copper planes which are connected to a heat/cold source to regulate temperature of whole PCB. Obviously I will need vias which go only from 1st Layer to 2nd (to ground). Is that maybe too expensive to manufacture?
I am only concerning about my connectors: the pins are soldered on the bottom. Normally THD are like vias, so it also has a connection on the top layer. Which I can connect then to a local ground plane which goes with vias down to the 2nd Layer.
Is that alright?
Maximum Frequency will be about 90 MHz.
AI: Obvisouly I will need vias which go only from 1st Layer to 2nd (to ground). Is that maybe too expensive to manufacture ?
This is called a "blind via" and they are more expensive than regular via's, typically you don't need them though.
(This is a 6 layer board it seems, but imagine it's 4)
In the image above you have a "4" layer board. The blind via connects layer 1 to layer 2, but doesn't go to layer 3 or 4. But take a look at the "through via", it connects Layer 1 and Layer 4, but not 2 or 3. This ends up looking like a small hole on the inner layers that don't connect. Your board design software accounts for this when you add a via, removing some copper around the layers that it doesn't connect to.
I am only concerning about my connectors: the pins are soldered on the bottom. Normally THD are like vias, so it also has a connection on the top layer. Which I can connect then to a local ground plane which goes with vias down to the 2nd Layer. Is that alright ?
THD are kind of like via's, with no internal plane connections (usually, sometimes they do). You can safely solder these without shorting out your internal planes. You don't need to worry about "local ground planes", if the through-hole connects to a net with the same name as the internal layer, like GND, it will connect internally.
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H: What is the theory behind these current equations? (for Z paramaters)
In the photo below is shown the method for deriving z-parameters of the circuit. Apologies for my badly drawn values for resistors as they weren't shown in the original image. Basically I'm struggling to see where the parts in red circles are coming from. I understand each of the Z equations but I don't know the actual theory behind those identities for Io and Io'.
The Io identity applies when I2 is 0. I can't tell if the 1/2 in the identity is actually a half, or if its the resistor values(there is a 1 and a 2 ohm resistor in the circuit). The reason this confuses me is because I'm doing this with a similar circuit which doesn't have that 1ohm resistor, but does have the other 3, so I need to know if the identity would be different for my circuit.
The Io' identity applies when I1 is 0. It seems like it is 2/(2+4+6) but again I'm not sure why.
So can anyone tell me whats the name of the rule that would provide an explanation for the circled identities, and help me understand why they apply when I1 and I2 equal 0.
Sorry if I haven't explained this well I'm having difficulty putting it into words, so if you're confused I'll happily clear up anything you need!
AI: The Io identity applies when I2 is 0.
Just think about how the \$I_1\$ current shares itself out. The 1 ohm resistor is irrelevant and so \$I_1\$ flows into two parallel resistors of which one is 6 ohm and the other is a series connected 4 ohm and 2 ohm. That series resistance is also 6 ohm hence the current shares equally: -
$$I_0 = \dfrac{1}{2} I_1$$
The reason this confuses me is because I'm doing this with a similar
circuit which doesn't have that 1ohm resistor, but does have the other
3, so I need to know if the identity would be different for my
circuit.
The 1 ohm is irrelevant when connected in series with a current source.
In the second circuit \$I_2\$ (from the voltage source on the right) flows into a 2 ohm load in parallel with a 10 ohm (4 plus 6 in series) load. The far left 1 ohm resistor is now regarded as open circuit because it was in series with a current source.
Can you see now how \$I_0'\$ is formed from your second equation inside the red box?
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H: how the comparator amp works as integrated amplifier
I need some explain how does comparator work as zero cross detection and integrated amp
AI: 1) There is no comparator, instead the LM324 is a very slow quad opamp.
2) The 1m resistors are a dead short, they are probably 1M which is 1 million ohms.
3) The total gain is 12195 so a very small signal produces a saturated output.
4) The LM324 is so noisy that with the gain that is so high, I think its output will be its own noise at a saturated output level.
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H: Induction motor starting torque and pull out torque
Recently I was doing some work on the induction motor where I found some general theory on starting speed torque curve of the induction motor. Where the theory is the starting torque will be 1.5x of rated torque & pull out torque will be 2x. Is this the always a condition or is there a any chance for the pull out torque can be 4x or 5x of the rated torque.
Speed torque curve of induction motor
AI: Induction motor designs have considerable variation in the pull-out torque actually provided. Across the power range of available induction motors manufactured to international standards, there is some variation in the minimum pull-out torque required. However 4x or 5x would be quite difficult to find in a normal motor. High-slip motors have the highest pull-out torque - above 3x. There are special low-slip designs that have about 2.7x.
In custom designed motors, pretty much anything you want to pay for is available.
The curve referenced and the information in the question and in the above response pertain to three-phase induction motors. A single-phase motor with a permanently-connected capacitor (PSC motor) would typically have pull-out torque above 4x starting torque and be capable of continuous operation at nearly 2x starting torque. If you re-define rated torque as 60% of starting torque, that becomes a motor with pull-out torque equal to 5x rated.
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H: Risk of long-term shorting XLR cable
I'm adding a 'mute switch' into my XLR cable.
To mute an XLR cable/Phantom powered microphone you temporarily connect pin 2 and 3 in the cable to short the connection. I have seen plenty of youtube videos and tutorials online of people doing this to add quick mute buttons and stuff into their podcast setups.
The difference with what i'm planning is instead of a momentary switch like a lot of people make, i'm going to add an SPST switch, so that I can flick a switch and mute my microphone for long periods of time, and only enable it when I want to.
Will there be any risk to my equipment when I mute the microphone and short pins 2 and 3 for long periods of time?
If it helps, the microphone and usb interface in my setup are
https://eu.audio-technica.com/AT2020
https://focusrite.com/en/usb-audio-interface/scarlett/scarlett-solo
AI: For long-term muting, you could just turn the 48V phantom power off from the Focusrite. Or, make the switch disconnect pins 2&3 from the mic, to turn it off and save power.
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H: Charge indicator with comparator - very sensitive to noise
I need an indicator when the current from my charger is larger than 100mA. I tried the below circuit but this seems very sensitivity to noise. Probably I am getting some ripple in the mV range from the charger.
Is there a more robust, less sensitive way to set this up?
AI: You can try something along these lines:
simulate this circuit – Schematic created using CircuitLab
R7 and C1 form a low-pass filter with a cutoff frequency of 1.6Hz to filter out load spikes and SMPS noise.
R6 and R9 provide some positive feedback amounting to about 5mA hysteresis. Increase R9 if you want to increase the hysteresis.
R10/C2 balance out any bias current, and can be eliminated if the bias current is small enough.
The op-amp needs to be a low Vos type (your whole signal is ~3mV), high voltage power supply capable and with an input common mode range that includes the positive supply rail. There are some such op-amps available, but only a few.
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H: What is the orientation of the pins in this drawing of an L4940V5 TO-220?
I am a novice trying to build a circuit using a L4904v5 voltage regulator. The datasheet has the following images:
This 2D pinout drawing gives me few clues about which side I am viewing it from. I assume it was viewed from the side is "flat" and does not have the "side dimples" or the round hole since they are not shown in the pinout image. There is also a lightly printed symbol on one of the pins that you can see in the actual picture. I do not recognize the symbol though.
1) Is my interpretation correct?
2) If I am wrong, will connecting this regulator backwards, to a 7.5 volt source, damage it?
3) What does the symbol mean?
AI: It would be obvious if you had the physical component in hand. If the drawing was viewed from the side of the heatsink tab (i.e. the rear) it would look completely different. Assume connecting anything that is polarized in reverse will damage it.
Wholly appropriate images taken from Interface Bus
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H: Which one is the correct symbol of enhancement type MOSFET?
I studied MOSFET from ' Electric Devices and Circuit Theories by Robert L. Boylestad ' The symbols of depletion type and enhancement type MOSFET are given below from the book.
But recently, in the book of Sedra/Smith named Microelectronic Circuits, I have found that the symbol of enhancement type is similar to the symbol of depletion type of Boylestad's book.
I've seen in the datasheet of many MOSFET that the enhancement type symbol is like the Boylestad's book.
Which one is correct?
AI: To really check on what really is the correct symbol for what, you should refer to particular standards.
Below is what the IEEE 315-1975 standard (which can easily be accessible online if you look on Google) tells us, for an example...
(the IEC label nearby also indicates that it's ubiquitous to IEC standards as well)
You can claim that this is old information, and it is (frankly, I'm surprised how they don't update this standard). However, it's the most recent document that we have on this.
So which one is right? Well... Technically they're all correct and it depends what standard you're following. The Sedra/Smith textbook is not wrong because it's showing a different type of transistor symbol that doesn't show too much bulk (or substrate) activity, except for Figure 5.19a, which shows the arrow pointing outward on the P-channel FET.
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H: Multiplying oscillator signal with a pulse
I am trying to multiply my oscillator sine signal with my pulse. But, the voltage of the oscillator is too big so it saturates.
This is the output I am getting from my oscillator. I am getting the required 100kHz frequency for my oscillator by would like to reduce the voltage in order to feed it into my diff amp.
If I just add an 10mV sine input instead of the 300mV that I am getting from the oscillator, the circuit works properly. Can I reduce the voltage in the oscillator so that the output doesn't saturate or is there any way to change my diff amp in order for the output signal to not saturate.
My output when the signal from the oscillator is 300mV
My output when I feed a very small input sine wave into the input of the diff amp and my required output
AI: Put 1k resistors in series with each of the emitters of Q1 and Q2 to reduce the gain of the differential amp. This is called emitter degeneration.
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H: LTSpice simulation issue
I am studying a circuit which will charge a capacitor till using a voltage doubler till it reaches a specified voltage value. Then it will discharge through a resistor. An SPDT switch is realised for this function using 2 SPST switches. A behavioral source is used to control these switches. But the simulation is getting stuck when this switching is about to happen. Any idea why this is happening
Version 4
SHEET 1 2296 680
WIRE 400 -112 80 -112
WIRE 656 -96 640 -96
WIRE 400 -48 400 -112
WIRE 656 16 656 -96
WIRE 400 64 400 16
WIRE 400 64 320 64
WIRE 496 64 400 64
WIRE 512 64 496 64
WIRE 640 64 576 64
WIRE 768 64 720 64
WIRE 848 64 768 64
WIRE 1024 64 928 64
WIRE 320 80 320 64
WIRE 400 80 400 64
WIRE 1024 80 1024 64
WIRE 80 96 80 -112
WIRE 496 96 496 64
WIRE 768 128 768 64
WIRE 320 208 320 144
WIRE 400 208 400 144
WIRE 80 224 80 176
WIRE 1472 224 1472 192
WIRE 496 288 496 160
WIRE 768 288 768 192
WIRE 768 288 496 288
WIRE 1024 288 1024 160
FLAG 80 224 0
FLAG 400 208 0
FLAG 320 208 0
FLAG 1472 224 0
FLAG 1472 112 Vc1
FLAG 864 16 Vc1
FLAG 912 16 0
FLAG 768 64 Vout
FLAG 1360 192 0
FLAG 1360 112 Vdc
FLAG 1024 288 0
FLAG 768 288 0
FLAG 576 -96 Vc1
FLAG 704 16 0
SYMBOL voltage 80 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=100
SYMATTR InstName V1
SYMATTR Value SINE(0 220 60)
SYMBOL cap 384 -48 R0
SYMATTR InstName C1
SYMATTR Value 30pF
SYMATTR SpiceLine Rser=0.1
SYMBOL diode 512 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL diode 512 160 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL cap 752 128 R0
SYMATTR InstName C3
SYMATTR Value 100n
SYMATTR SpiceLine Rser=2
SYMBOL cap 304 80 R0
SYMATTR InstName C4
SYMATTR Value 30pF
SYMATTR SpiceLine Rser=0.1
SYMBOL cap 384 80 R0
SYMATTR InstName C2
SYMATTR Value 30pF
SYMATTR SpiceLine Rser=0.1
SYMBOL res 1008 64 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL bv 1472 96 R0
SYMATTR InstName B1
SYMATTR Value V=if(V(Vout)>V(Vdc),5,0)
SYMBOL voltage 1360 96 R0
SYMATTR InstName V2
SYMATTR Value 145V
SYMBOL sw 944 64 R90
SYMATTR InstName SW3
SYMATTR Value S3
SYMBOL sw 736 64 R90
SYMATTR InstName SW1
SYMATTR Value S3
SYMBOL Digital\\inv 576 -160 R0
SYMATTR InstName A1
SYMATTR Value2 Vhigh=5 Vlow=0
TEXT 48 248 Left 2 !.tran 300 startup uic
TEXT 592 392 Left 2 ;.step param C LIST 100n 1u 10u
TEXT 592 432 Left 2 ;.meas TRAN t9 FIND time WHEN V(Vout)=145 TD=0 FALL=1
TEXT 592 464 Left 2 !.model S3 SW(Ron=125 Roff=1000000G Vt=2.5 Vh=-1.5)
AI: Besides what Spehro Pefhany said, there are a few other things:
the Roff/Ron ratio for the VCSW is too large, and it can (and will) introduce possible numeric inaccuracies. Roff=1G is more than enough, even air has a finite resistance. Still, you used negative hysteresis, which is the recommended way (well done!).
instead of using a conditional if() (corrected in the other answer), which is guaranteed to introduce discontinuities, why not use the readily available A-devices, which can also reduce the component count and provide guaranteed convergence and superior behaviour during simulation. The if() can be replaced by a Schmitt trigger, the 145V voltage source can be eliminated by setting vt=145, and the inverter can also be eliminated by using the complementary output of the Schmitt trigger. In addition, tau can control the rising/falling times to have a smoother behaviour and, thus, continuous derivatives, while td (and, possibly, vh) avoids self-oscillations at very high frequencies. In fact, you may even discard the Schmitt trigger, too, by using the vt and vh of the switches, but that tends to be a bit finicky and it can make the schematic a bit less readable.
the diodes you are using are the default ones which, even if they have a tiny smooth region around the knee (a few points, no more), it can be improved with additional settings. In particular, the forward voltage and the on resistance should be set, while epsilon/revepsilon will make your like easier by introducing quadratic smooth knee regions, especially when switching is involved.
you used series resistance for the capacitors probably to avoid high switching currents and noise (well done!, part II), but the values are a bit too high than what you'd expect from such small capacitors and, besides, this is meant to be a study-case, borderline ideal, so Rser=1m is more than enough in this case. This causes you to adapt the input capacitive divider.
you have used uic in the simulation card, which ensures that everything starts from zero, so startup is no longer needed, particularly since this flag is used for DC supplies, it adds a small ramp from zero to DC at the beginning. You only have a sine, so it's not needed.
one more (possible) thing, the sine source has 220 as the value but, unless you already know, that is not the RMS value, but the peak value. So if you need 220V RMS then you will need to set it to ~311.
With these, this is how it looks, and it runs without hiccups, and fast (I stopped it at ~120s since the switching frequency gets too high compared to the sine source):
If the switching frequency is too high, inscrease td, and if you can live with larger ripple, you can set vh>0, too.
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H: Syntax error near "else" in Verilog, in an initial block, next to assert
I'm trying to make a self-checking testbench for an ALU I'm designing for an extra credit assignment. Here's what I have:
module testbench();
wire [31:0] a, b, y;
wire [2:0] f;
wire zero;
alu test(a, b, f, y, zero);
initial begin
a = 0; b = 0; f = 3'd2; #100;
assert (y === 0) else $warning("0 + 0 failed");
a = 0; b = 8'hFFFFFFFF; f = 3'd2; #100;
assert (y === 8'hFFFFFFFF) else $warning("0 + FFFFFFFF failed");
a = 1; b = 8'hFFFFFFFF; f = 3'd2; #100;
assert (y === 0) else $warning("1 + FFFFFFFF failed");
a = 8'h000000FF; b = 1; f = 3'd2; #100;
assert (y === 8'h00000100) else $warning("FF + 1 failed");
end
endmodule
I'm getting four critical warnings, all of them saying 'Syntax error near "else".', for each of the lines with the assert statements. I don't know why that's happening, I have the statements in the initial block. Does anyone know if I'm missing something here?
AI: You must use logic instead of wire. You cannot make procedural assignment s to wire signals.
You need to use 32'h instead of 8'h
Your file should have a .sv file extension; otherwise might be compiled with Verilog syntax rules.
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H: Is it possible to drive a power piezoelectric in lower frequency than its own frequency?
I am driving a piezo transducer simply by an inductor series with piezo.
the resonant frequency of the piezo is about 40KHz and I designed a 20KHz transducer.
I'm giving a pulse voltage (using a class E driver) to drive this series circuit
and by turning the value of L(inductor), I force the piezo and L to resonate at 20KHz frequency and get a high voltage on piezo electrodes.
My questions are:
Why does nobody mention this method to drive a power piezo?
Is this method damages the piezo?
Without considering the efficiency, is it alright to drive a piezo in other frequencies?
AI: If you don't care about maximizing the output amplitude when lightly damped then you can operate away from mechanical resonance.
Operating a resonant transducer at it's mechanical resonant frequency allows relatively small drive voltage and current to result in a lot of motion (strain).
Efficiency aside, since there are limits to drive voltage, whether it's supplied by a coil or an amplifier, operating away from resonance limits the maximum output amplitude. From this website.
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H: 4940v5 drop-in replacement for LM7805?
I am a novice who purchased several TO-220 L4940v5 chips thinking they were drop-in replacements for the inefficient TO-220 7805s that I've been using. But not a single one seems to work. No heat, no voltage output, nothing. Thinking I had the pins backward I tried a fresh one with the in & out swapped, but still no result.
Is the L4940v5 not pin-compatible with the 7805?
EDIT: Here is what I built. It is the same as the reference diagram on the L4904v5 datasheet, except my output capacitor is larger (it's what I had).
AI: Getting no output sounds like something is wrong, like maybe the parts are defective. Hopefully you purchased them from a reliable source.
They're not exact replacements because they can withstand less input voltage (30V rather than 35V) and they draw rather nasty amounts of Iq (as much as 100mA typical) when the output current is high and the regulator is dropping out (this hideous behavior is typical of such antediluvian regulators made with low-hFE lateral PNP pass transistors).
I suppose it's possible this is causing your source to current limit and restart, resulting in an endless loop.
They don't say so in the datasheet but the regulator is probably not guaranteed stable with ceramic output caps, and needs a fat-ish 22uF or more aluminum electrolytic or tantalum cap with relatively high ESR on the output. The LM7805 is much more forgiving.
There's no power dissipation advantage in dropping one of these in place of a 7805, not at all, under some conditions just the opposite. There are switching regulators that you can use such as the Murata OKI-78SR-5/1.5-W36-C which actually are very efficient and are (more-or-less) drop-in replacements allowing you to leave off the heatsink.
Be sure to read the datasheet.
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H: Why can an AC circuit breaker not be used in DC circuits?
Let's assume that I want to use a 20-amp GE AC circuit breaker in a DC circuit. So, after testing it in a DC circuit with some loads and ammeter + clamp DC amp meter I find the current at which the breaker trips. Let's assume as an example this is 45 amps. So, is it possible to use the AC circuit breaker in the DC circuit on a permanent basis? I've seen a YouTube clip where a person is using an AC 6-amp 230V breaker with a DC circuit and it tripped at 13 amps when loaded.
Are there any significant safety hazards with this technique? I mean I was thinking since it's the current that matters maybe these breakers can be used with 6V/12V/24V circuits where the currents are generally going to be drawing only under 20 amps in the above mentioned case while using, but in a short circuit scenario, the current will be in 35A to 55A range thus causing the breaker to trip.
Update: I had these two breakers from the old panel in my storeroom. What you guys said is very true. It seems to be quite dangerous to use them in DC too. I have a high-current 12/24V supply capable of 35-amp output. But I’ll only be using it under 20 amps mostly. I build these supplies from UPS transformers. So, I tried to connect the three supplies and I had built to the GE breaker, in short, to see its response only 2 seconds power ON. The first one was with the biggest transformer from a 2000VA UPS. It had very thick low voltage windings (10AWG likely) and shoutings the AC low voltage caused the breaker to trip in 39-41ms. With another transformer from a 700VA UPS from low voltage AC side, it tripped at around 1.17s and finally from a 300VA UPS transformer low voltage AC the breaker did not trip. Now trying the first two transformers I’m dead short on the breaker via a 50 Amp rectifier (Imax peak 400A briefly) I was surprised the breaker didn’t trip even after 2 seconds and I immediately gave up the DC breaker idea. I’ll put the breaker on the AC low-voltage high-current side for safety and add a 400-amp rectifier to protect in case of a dead short.
AI: You certainly can use Square D "QO" panels/breakers on DC
And the reason you can do that is Underwriter's Laboratories (UL) listed the breakers for DC service, and the labeling and instructions (which are approved by UL) state that explicitly. This was backed by testing in UL's lab. This is a condition of using them in mains power (NEC 110.2).
Naturally, you must read the instructions and data sheets, and use them conforming with those instructions (required in NEC 110.3(B) and 110.12).
So as long as you use breakers listed for DC, and follow the instructions, Bob's your uncle!
Trip curves
So, let's say after testing it in a DC circuit with some loads and ammeter + clamp DC amp meter I find the current at which the breaker trips. Let's say this is 45Amps.
Current singular? You think the breaker is that simple, trips at 45A does not trip at 44A? It's not like that at all.
Competent breakers (not those DC hobby toy breakers) have two trip mechanisms:
Magnetic trip is a loop of wire around a solenoid core. When current exceeds a certain amount, the plunger pulls and causes an instant trip.
Thermal trip is a bimetal strip through which current flows. It is sized to heat at about the same rate as wires in the walls, and trip somewhat before those wires start a building fire.
Together, these two mechanisms create a fairly complex trip curve with manufacturing tolerances:
Now you can see that a 4.5x to 8x overload causes a trip in 1 second. A 2x overload causes a trip in 9 to 35 seconds.
Now look at that video again. Mind you, the youtuber had already been "warming up the breaker" with a slight 115% overload. And upon overloading at 2x, it tripped in 13 seconds - which considering the previous "warming up", is pretty much center of range.
In other words, that Euro-DINrail breaker tripped very consistently with the spec of a Square D QO type which actually is rated for DC.
Why's the guy upset about 200% trip, then?
Because the youtuber has never met a breaker trip curve, has no idea this is normal, and is just "making stuff up" for the camera.
Nonetheless, the youtuber is correct: Since the breaker is not listed for DC, it must not be used with DC.
Here's another video of someone punching 340V DC (that's 240V rectified and smoothed) through another 6A mains breaker definitely not listed for such high voltage DC. Higher voltage DC is very nasty stuff.
The most important part, though, is that this youtuber tests the breaker on AC first, and it trips almost instantly. But on DC it trips much slower. This is a huge red flag that something is horribly wrong and that breaker is not fit for that purpose.
The arcing and smoking after the trip is because 340 volts DC is a Very Nasty Customer. This is 600 VDC.
Obviously, if you do stupid experiments, you get stupid results.
Use components according to their labeling and instructions. Do not attempt off-label uses.
Look for SWD and HID ratings
One more thing. Since you're dealing in North American stock, watch for SWD (SWitching Duty) endorsement; these are listed for use as switches on a daily basis. Virtually all new stock is this; it's for the common commercial application of using a subpanel specifically to power banks of lights, and using the panel as the light switches.
Also look for HID (High Intensity Discharge) endorsement, which means the breaker is specifically rated for daily switching duty, while dealing with the large inductive kick you get when interrupting highly inductive loads (such as HID or fluorescent lighting that uses old-school magnetic current-transformer ballasts). Nobody's installing magnetic ballasts today (except indoor horticulture), but DC loads present similar arcs. So if you are dealing in a DC-rated family of breakers, all things being equal, an HID breaker will be better.
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H: What is the Purpose of the Clock?
There are many examples of logic circuits that have the clock signal, such as the JK flip flop and the clocked SR NOR Latch, but I still wonder what is the purpose of the clock. Why do people think of adding the clock signal into the circuit? Isn’t it simpler and easier to learn without the clock?
AI: Using a clock allows us to build synchronous logic, ultimately letting us accurately control the timing and sequence of the operations that our circuits perform. On each clock transition, all of our storage elements update on that edge, meaning that our circuit makes one state transition to the next state. This is a very important simplifying factor for our design, since the transitions are all synchronized and predictable. We need to verify that our circuit meets a set of timing constraints (i.e. setup/hold times for our storage elements), and once those conditions are met, we are assured that the circuit will operate as expected. Many of our design tools (simulators, FPGA fitters, etc) are based around synchronous methodology for these exact reasons.
On the other hand, clock-less, or asynchronous circuits, make sense for simple logic problems but become extremely unwieldy and hard to design for larger problems; the assertion that clockless designs are simpler is not really true. Without a single synchronizing clock signal, different parts of the logic might operate at different speeds due to their propagation delays, which causes design challenges such as glitches, timing skews, and so on. As an illustration, an asynchronous design may requires multiple special transitions to sychronize two components, while a synchronous design with a shared clock can simply use the clock edge (and possibly a single signal, asserted synchronously with the clock).
In practice, there are asynchronous CPUs out there as an example of async design, but they are far from the mainstream; not only do they fail to fit with the more common synchronous design methodology, but many of the optimizations designed for higher CPU performance (such as the Tomasulo algorithm and other superscalar designs) assume that there is a clock that governs the time available for execution units to perform their computation and yield a value.
They achieve modestly higher performance, but the design time (and thus cost) as well as complexity of integration make them unattractive for most commercial applications.
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H: Limiting the current with the LM2679
I'm building a power supply, and I'm trying to see if the LM2679 will fit my needs. I like how it's similar to the LM2596 as well as the fact that it has a pin to limit the switch current. However, I have a question regarding the relationship switch current limit and the max output current.
For reference, my test schematic is below. It outputs 5 volts ideally, and it is set to give out 1 A. I adjust the current to the load with switches and resistors, incrementing the current to the load in 0.25 increments until it hits 1A or goes over it. Looking at the waveforms, as it hit 1A, the output voltage lowers in order to adjust for the increasing load, which is what I expect. However, what I'm confused about is the relationship between the switch current and the output current going to the load.
The datasheet states that the peak switch current is equal to a factor of 37,125 divided by the adjustment resistor, Radj. It recommends that for the full temperature range, this limit must be greater than 50% of the max load current. So, assuming my max load is 1 amp, that means the max switch current is 1.5A. Using that value, Radj = 24.75kOhms. I would think that ideally, the load current would be able to tolerate that limit, but as you can see, the voltage is dropping as the load is reaching 1 amp, perhaps even before that. As the load goes past 1 amp, it peaks but the current goes down and kind of settles. I understand that the peak switch current is not the max current limit that can go to the load, but is there a general rule-of-thumb of sorts with regards to the relationship between max load current and the switch mode current?
AI: In the datasheet the following is also stated
The peak switch current is equal to a factor of 37,125 divided by RADJ. A resistance of 5.6 kΩ sets the current limit to typically 6.3 A and an RADJ of 8.25 kΩ reduces the maximum current to approximately 4.4 A. For predictable control of the current limit, TI recommends keeping the peak switch current greater than 3 A. For lower current applications a 3-A switching regulator with adjustable current limit, the LM2673, is available.
meaning that for a peak current lower than 3 A, a lower precision should be expected regarding the current peak detection.
As for the relationship between the switch and load current, there is some dependence on a couple of parameters and the mode of operation as follows:
Discontinuous Mode
Continuous Mode
Source
Since the the LM2679 can operate in both modes, DCM and CCM, I would say it is not straight forward to come up with a rule-of thumb for the peak current value. As long as the peak current was kep above 3A, your best option would be to follow the ratio set by RADJ.
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H: Multimeter diode mode: do different multimeters show the same results approximately?
I think that in many cases the voltage that a multimeter shows in diode mode is dependent on the current it uses for that mode. So the values measured by different multimeters in diode mode should be different in many cases. Am I right? If that's the case, why don't they make a universally accepted standard, so that all multimeters use the same amount of current in diode made and the measured values can be compared (which could be helpful in diagnostics)?
AI: Typical multimeter currents are about 1 mA, with a fair amount of variation, and this is not standardized that well, but it's not a massive issue given the exponential I-V characteristic of properly-functioning diodes under forward bias.
Furthermore, if I'm using a multimeter for a diode test, I'm not looking for a precise value anyway. Instead, I'm looking to see whether I am hitting a diode drop at all. In practice, if I really cared about my diode's saturation current, I'd grab something more precise than a multimeter.
The current in a forward-biased diode is given by:
$$I_D = I_S\cdot e^{\frac{V_F}{nV_T}} - 1$$
where \$V_T\$ is the thermal voltage (about 26 mV at room temperature) and \$n\$ is either one or two depending on semiconductor type. \$I_S\$ is a constant current associated with that diode and environmental conditions (e.g. temperature).
It follows from this math that the forward voltage of the diode will vary very little even for moderate differences in current; in the worst case (ideality factor of 2 corresponding to indirect bandgap semiconductors), a 10x difference in current between two meters will only yield a ~0.1 V discrepancy.
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H: Why is the LTspice cut-off frequency for my multiple feedback low-pass filter not matching?
I am designing a 6th-order multiple feedback low-pass filter with the cut-off frequency at 1000 Hz. I wrote a Matlab script that calculated the capacitor and resistor values.
I combined all transfer functions together and got a Bode plot with exactly 1000 Hz as the cut-off frequency, with 6th-order roll-off. FYI: the gain K = 1.
I even checked it with an online Butterworth multiple feedback low-pass calculator and got the exact same values. Now, when I build the schematic in LTSpice, the cut-off frequency is skewered and I cannot figure out why.
Either something about the multiple feedback topology is the issue, or I am missing something in LTspice. Any solutions or explanations to why LTspice is not giving me the correct Bode response? Down below is my MATLAB plot, the online filter calculator, and my LTspice schematic and Bode plot.
AI: I just now realized that my LTSpice power supply was not correct. Guess I answered my question ¯_(ツ)_/¯
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H: plotting dirac delta function using inverse Fourier transform
I was trying to plot shifted dirac delta function in Matlab.
$$\begin{align}\mathscr{F}\left(\delta(t-t_0)\right)&=\mathcal{F}(\omega)=e^{-j\omega t_0} \\
e^{-j\omega t_0}&=\cos\omega t_0-j\sin\omega t_0\end{align}$$
Using Trigonometric form of Fourier transform:
$$\begin{align}\mathrm{A}(\omega)-j\mathrm{B}(\omega)&=\cos\omega t_0-j\sin\omega t_0 \\
\delta(t-t_0)&=\frac 1{\pi}\int_0^{\infty}{\cos\omega t_0 \cos\omega t+\sin\omega t_0 \sin\omega t \space \mathrm{d}\omega}\end{align}$$
Let's assume \$t_0=\pi\$.
For more information on trigonometric form of FT: https://imagizer.imageshack.com/img922/8960/Z9xkMw.jpg
Given below is Matlab code and the plot generated using it. Where am I going wrong? Thank you for the help.
clear all; close all; clc;
t=linspace(-5,5,800);
for it=1:800
f=@(w)(1/pi).*(cos(w.*pi).*cos(w.*t(it))+ sin(w.*pi).*sin(w.*t(it)));
F(it)=integral(f,0,3000);
end
figure('Name','inverse Fourier transform');
plot(t,F,'red');
hold on;
AI: I don't think you did anything wrong. The problem is probably that a delta function is quite pathological, and the Matlab integral function can't handle things to sufficient numerical precision. Instead of a delta function, do a very narrow Gaussian pulse, which you can also Fourier transform analytically. Below is a shifted Gaussian pulse of width \$\Delta t=0.01\$
clear all; close all; clc;
t=linspace(-5,5,800);
for it=1:800
f=@(w)(1/pi).*(cos(w.*pi).*exp(-(w.*w*.0001/2)).*cos(w.*t(it))+ sin(w.*pi).*exp(-(w.*w*.0001/2)).*sin(w.*t(it)));
F(it)=integral(f,0,3000);
end
figure('Name','inverse Fourier transform');
plot(t,F,'red');
hold on;
Gives
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H: Maximum error of nominal resistor combinations
Suppose you have resistors which have nominal values of \$R_0\$ or \$2R_0\$ but can vary to be anywhere between \$(1 ± .03)R_0\$ or \$(2 ± .06)R_0\$, respectively, so each can have about 3% error.
Is it correct to calculate the maximum error of two possible combinations of these resistors as follows? (These are the only two combinations I care about.)
Parallel connection of two \$2R_0\$ resistors: \$2.06R_0||2.06R_0 = 1.03R_0,\$ correct value is \$1R_0\$, so overall 3% error. Alternatively, \$1.94R_0||1.94R_0 = .97R_0,\$ so still 3% error.
Series connection of two \$R_0\$ resistors: \$1.03R_0 + 1.03R_0 = 2.06R_0,\$ correct value is \$2R_0\$, so overall 3% error. Alternatively, \$0.97R_0 + 0.97R_0 = 1.94R_0,\$ so still 3% error.
A text I'm reading suggests that the second case of two \$R_0\$ resistors in series should have a maximum error of 6% and not 3% but I don't understand how.
AI: Resistor networks consisting of the same tolerance resistors have an overall tolerance equivalent to that of the individual resistors.
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H: why is \$P^{max}_{Z_L}=|\hat I_L|^2\times 4\$,not \$|\hat I_L|^2\times 5\$,when \$\hat Z_L=\hat Z^*_{th}=4-3jΩ\$
What is the max power of \$\hat Z_L ,P^{max}_{Z_L},\$ when the \$\hat Z_{th}=4+3j Ω\$??
First i know the Imaginary part of impedance will cause Reactive Power,so the real power can't be the same as the apparent Power,so we can know if we want to have a \$P^{max}_{Z_L}\$,we have to cancel the Imaginary part of impedance,so obviously we can know the \$\hat Z_L=\hat Z^*_{th}=4-3jΩ\$,and \$\hat I_L=\frac{V_{th}}{\hat Z_L+\hat Z_{th}}=25∠0\$
The answer show me \$P^{max}_{Z_L}=|\hat I_L|^2\times 4\$,however, i think the \$P^{max}_{Z_L}=|\hat I_L|^2\times \sqrt{4^2+(-3)^2}=|\hat I_L|^2\times 5\$
So i want to ask why is \$P^{max}_{Z_L}=|\hat I_L|^2\times 4\$? or the answer is wrong?
AI: 25 A flows through a 4 ohm resistance in series with a 3 ohm reactance. Only the resistance dissipates power, hence the power is \$25^2\times 4\$ W.
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H: Motor specifications - how to compute allowable running time for power levels between the continuous and peak specs?
Say a motor is rated for 20 N·m continuous torque, and 35 N·m peak (peak = for no more than 30 seconds). Alternatively it may be specified at with continuous/peak currents, but if the motor efficiency is good overall, then this is almost an equivalent definition.
Say that I want to run the motor producing 25 N·m for some time. Is there a general mathematical model that approximates the safe run-time at that level? It's certainly more than 30 seconds, but I'm unsure how to derive an approximate value.
More specifics: it's a 3-phase brushless motor, and it does have a temperature sensor. However using the temperature alone (and disregarding the specs) does not seem to be a good approach. E.g. 30 seconds at 35 N·m does not heat it very much, and it doesn't get even close to the max temperature per specifications. I'm also constraining myself to the typical application RPM ranges, e.g. 50 to 100% of the rated speed.
AI: The power dissipated in the motor goes as I2, which is the same as torque squared. (35/25)2 is more or less 2, so if the motor heating was purely adiabatic, you would expect to get a minimum of 60 seconds from it at 25 Nm. However, during that time, there will be some cooling, so you would expect more. How much more? That's not possible to say without more measurements on the motor.
The temperature sensor is likely to lag the winding temperature. The sensor is probably there to guard against long term overheat. If you measure the winding temperature directly, you might get a better idea of what the peak temperature is.
How to measure the winding temperature? Measure the DC resistance of a winding when cold. They might be quite low, so you may have to use a 4-terminal (Kelvin) measurement to get reasonable resolution and stability, which you will need.
Run the motor at 35 Nm for 30 seconds. Detach from the ESC and quickly measure the resistance again. The tempco of copper is about 0.4% per degree C, about 10% in 25 °C, which is why your measurement needs reasonable resolution.
Repeat with 25 Nm. Increase the run time without exceeding the previous winding temperature rise you measured. Note that you don't need an exact conversion from resistance change to temperature, you're just targeting the same resistance change.
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H: why is \$|V_C|=90\$, not \$70\$? series RLC circuit
If \$|V_S|=100V\$,\$|V_R|=60V\$,and \$|V_L|=10V\$,then what is \$|V_C|\$ ?
simulate this circuit – Schematic created using CircuitLab
My solution
\$100=\sqrt{60^2+(10-V_C)^2}\$,so \$(10-V_C)^2=80^2\$,so \$(10-V_C)=80\$,now we can know\$V_C=10-80=-70V\$,so \$|V_C|=70\$
However ,the book tells me the answer is \$|V_C|=90\$ ,indeed if i replace
\$|V_C|\$ with \$90\$ into \$(10-V_C)^2=80^2\$,the formula does hold,so i want to ask why is \$|V_C|=90\$,not \$70\$,what is the mistake about my calculation?
AI: $$V_s = \sqrt{V_R^2 + (V_L - V_c)^2}$$
$$(10-V_C)^2 = 80^2$$
This is a quadratic equation, and has the roots -70 and 90. We can ignore the negative value, which gives us the value of \$V_c\$ as \$90 \space V\$.
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H: Problem with custom USB microphone
I developed a MEMS microphone based audio capturing device and transfer that audio via USB to the PC. I used Audacity opensource software to test my working and found the audio plays well when recorded and I play back the recorded sound but has static/crackling noise during the live stream.
I tried this with various apps but I find this issue only while listening to live streaming audio and not with the recorded audio.
Is there a problem with my hardware designed or the Audacity app. Since the recorded sound is similar to what I expect I think there could be a problem with live stream mode. I tried a few settings on Audacity but still, get the same static/crackling noise.
What could be the issue? How can I fix this problem?
Configuration
Sample rate: 8kHz
Channels: Mono
Format: PCM 16
AI: That can be a lot of things, most including software problems, but in all likelihood:
This is a rate mismatch problem. Either, your software can't resample the 8 kHz to its internal sampling rate e.g. for codecs, or you think you're doing 8 kHz, where in reality you're doing 7.992 kHz or 8.008 kHz (or some other variation).
So, encoder expect 8000 samples a second an average, gets less (or more), and things run out of sync.
Solution:
Make sure the oscillator you used for generating the 8 kHz is not your source for clock mismatch
Try using a higher sampling rate; not all clock generators are equal, and 8 kHz sampling rate is really unusually low for PC audio systems (because the highest signal frequency you can represent with that is just under 4 kHz; that's lower than what you'd typically want, anyways, because the signal power spectrum useful for making speech intellegible extends to beyond 5 kHz. 4 kHz just gives you slightly better sound than the POTS-typical 3.4 kHz cutoff, so you'll sound like people on the phone in old movies.
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H: How to model voltage controlled switch in LTSpice?
Having trouble making a Buck converter using two complimentary switches in LTSpice. I've got everything laid out exactly as perscribed, but when I run I get the following error:
"Can't find definition of model "SW""
I've put the model for each one right there, so I've got no clue why it wouldn't know what to do with the switches. If anyone has any ideas on how to correct that please let me know, thanks.
AI: You are not assigning a model to your switch, but just renaming it.
In order to assign a model, you have to right click on the switch and change its value to the model name you want to use.
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H: High bulk capacitance (100.000 uF) discharge time on Wifi router supply
I want a WiFi router, those supplied with 12V x 1~1.5A AC-DC wall adapter, to remain ON for a short time (maybe one second or a little more) after the AC mains gets its energy interrupted, when AC goes down.
One idea is to place 10x electrolytic caps of 10.000uF x 16V on the 12V output out the adapter (supply input of WiFi router), a nominal 100.000uF capacitance.
Is there a way to "have an idea" of the number of seconds the routers can remain ON after the AC goes down? And also for Wifi routers with integrated modem.
AI: Is there a way to "have an idea" of the number of seconds the routers
can remain ON after the AC goes down?
You want to hold the 12 volt DC on for a period of time using a capacitor so, the first limitation of this idea is that the voltage will instantly start to droop once the power is removed. But that isn't necessarily a show-stopper if the router can survive all the way down to 10 volts. It will be taking a roughly constant current as the capacitor is supplying the rapidly drooping voltage and this might be (say) 1 amp (just for numerical convenience).
The formula: -
$$I = C\dfrac{dv}{dt}$$
So, dv will be the change in voltage (say 2 volts) and dt will be the time allowed for it to droop (say 2 seconds). Hence: -
$$1\text{ amp} = C\dfrac{2\text{ volts}}{2\text{ seconds}}$$
Or, rearranging, C = 1 farad.
That's quite large (supercap sort of size) so pick carefully. If your current is only 100 mA then a 0.1 farad capacitor would hold up a drooping supply of 12 volts for 2 seconds. If only 1 second is required then 50,000 uF would do the job.
But, it all comes down to how low a voltage can you tolerate on your router before it gives up the ghost?
One idea is to place 10x electrolytic caps of 10.000uF x 16V on the
12V output out the adapter (supply input of WiFi router), a nominal
100.000uF capacitance.
Very unlikely to be anywhere near enough. You are probably about a thousand times too small.
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H: Simple DIAC circuit which I do not understand - LTspice
Here is the circuit :
Here is the model and the parameters of the DIAC :
.SUBCKT DIAC DIAC_IN DIAC_OUT PARAMS:
+Tr=0.342
+Vbo=13.6V
+Delta_V=19V
+Ibo=15uA
*
*Tr: Rise time (in µs)
*Vbo: Break over voltage
*Delta_V: Dynamic breakover voltage
*Ibo: Breakover current
C_C1 N02098 DIAC_OUT 1u IC=0
V_IDIAC1 DIAC_IN N01041 DC 0Vdc AC 0Vac
R_R1 N02098 TRG {1.462*Tr}
D_D1 N06161 N01041 DZ19V
E_ABM1 TRG DIAC_OUT VALUE { IF(ABS(I(V_IDIAC1))>{Ibo},1,0)}
D_D2 N06161 N01060 DZ19V
D_D3 N10655 N01060 DZ14V
D_D4 N10655 DIAC_OUT DZ14V
S_S1 N01041 N01060 N02098 DIAC_OUT _S1
RS_S1 N02098 DIAC_OUT 1G
C_C2 DIAC_IN DIAC_OUT 10p
****************
* Switch Model *
****************
.MODEL _S1 VSWITCH Roff=1e7 Ron=2.2 Voff=0.1V Von=0.99V
****************
* Diodes Model *
****************
.model DZ14V D(Is=3.142f Rs=0.1 Ikf=0 N=1 Xti=3 Eg=1.11 M=.3282
+ Vj=.75 Fc=.5 Isr=1.973n Nr=2 Bv={Vbo} Ibv=.14467 Nbv=1.093
+ Ibvl=.1m Nbvl=1.2722 Tbv1=001433.3u)
*
.model DZ19V D(Is=6.994f Rs=5.612 Ikf=0 N=1 Eg=1.11 M=.2906
+ Vj=.75 Fc=.5 Isr=2.088n Nr=2 Bv={Delta_V} Ibv=.17098 Nbv=1.2072
+ Ibvl=2.002m Nbvl=1.1457 Tbv1=888.89u)
* Vz = 18 @ 14mA, Zz = 37 @ 1mA, Zz = 11 @ 5mA, Zz = 7.9 @ 20mA
.ends
*
*********************************************************************
* Standard DIACs *
*********************************************************************
*$
.subckt myDIAC DIAC_IN DIAC_OUT
X1 DIAC_IN DIAC_OUT DIAC params:
+Tr=0.342
+Vbo=13.6V
+Delta_V=19V
+Ibo=16uA
* 2008 / ST / Rev 1
.ends
where :
* This DIAC model simulates:
*Tr: Rise time (in µs)
*Vbo: Break over voltage
*Delta_V: Dynamic breakover voltage
*Ibo: Breakover current
*
*All these parameters are constant, and don't vary neither
*with temperature nor other parameters.
What I think :
When Vc reaches the breakover voltage (32V), the DIAC begins to conducts, until the current is lower than the breakover current, ie 16uA. The current of the source voltage is able to provide 15uA due to the limiting resistor 60 Meg (this is a simulation). So it should conduct until the capacitor is able to provide 1 uA. And then wait again that the voltage across the capacitor rise to 32V. The voltage capacitor should "oscillate" over the time. Nevertheless, here what the simulation shows :
What is weird is that the capacitor voltage stays @ 32V whereas if the DIAC was not conducting, it should continue to grow until the voltage source. Nevertheless when conducting the DIAC have a "forward" voltage lower than 32V. In the model the forward voltage is equal to 32V - 19V = 13V.
Thank you very much and have a nice day ! :D
AI: The DIAC will never reach a current that causes it to properly "flip". As voltage rises across the capacitor, the DIAC progressively steals more current away from the capacitor and you end up with a stalemate - the capacitor can no longer increase its charge (due to the DIAC leeching off a small current): -
You can prove this by removing the capacitor and plotting applied voltage across the DIAC against the current it takes - I bet you that it doesn't reach the break-over point until the current is greater than what the 900 volt supply and 60 Mohm can deliver.
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H: Designing a triac based regulatable DC supply
I need about (30V-160V)32A DC for my project. I am trying to build an electronic circuit to regulate AC mains (220V, 50Hz) to produce voltage from 30V to 160V and rectify it to produce DC voltage. With some inspiration from circuit diagrams posted online, I have designed my circuit (Enclosed)
Kindly comment on my method and if possible help me improve my design.
Stay safe!
Edit 1 Note.
1. The required output DC 50-160V 32A, 8 Hour duty, 2. The available input 3 Phase AC 415V, 24A per phase 3. I have got a few BTA 41, some heat sinks, some 470Kohm potentiometers, KBPC3510 diode blocks, and 10 DB3 and 10K ohm resistor each.
AI: There are a few things to be aware of with this approach.
It is not isolated. The output must be considered live.
*Figure 1. Phase-angle and output current into a linear load. Source: Dimmers for LEDs.
Voltage will increase as the dimmer trigger delay decreases from 180° to 90°.
Once you reach the 90° the rectifier and smoothing capacitor will give peak voltage output of \$ 220 \sqrt 2 \$. Unless you have a large load to quickly discharge the capacitor you won't see much variation in voltage between 90° and 0° because the bridge rectifier will be reverse biased.
To limit the voltage to 160 V you will have to limit the minimum resistance on the pot.
Your most likely failure is of triac short-circuit. This will apply full mains voltage to the rectifier and will blow the capacitor if not adequately rated. Loss of the dimmer capacitor would also tend to switch the triac on early.
I'd be very careful.
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H: How to model and understand the asymmetry of a parallel RLC circuit spectrum
I'm working with some parallel RCL circuits and I have noted that when I record a power spectrum (so \$\rm{dB}\$ vs \$\rm{Hz}\$) that the spectrum is asymmetric:
As I'm sure you all know if we calculate the impedance of a parallel RCL circuit
simulate this circuit – Schematic created using CircuitLab
we get
$$ z_{\rm{RCL}} = \frac{i L R \omega}{R + i L \omega - C L R \omega^{2}} $$
and if we take the real-part of this then we get
$$ {\rm{Re}}\left(z_{\rm{RCL}} \right) = \frac{1}{R \left(\frac{1}{R^{2}} + \left( \frac{1}{L \omega} - C\omega \right)^{2} \right)}$$
which just by looking at we can tell is symmetric. But if we plot it:
So my first question is: Where does this asymmetry come from?
My first guess is that this is parasitic inductances and capacitances.
So my first question is: how can I adjust my equation to consider these asymmetries so I can do better fits?
My end goal is to extract the \$Q\$-factor and resonance frequency.
Further research and comments
Some additional comments since having an answer. The circuit proposed in the answer below is indeed a better fit,
$${\rm{Re}}(Z) = \frac{R}{1 + C \omega^{2} (C R^{2} + L (C L \omega^{2} - 2))}$$
and is asymmetrical in the direction that is shown by my data. However there seems to be other components at work as the tilt in my data seems to be more extreme than is represented by the lineshape as described above.
In the graph above we can see the data, which I have linearised, add the lineshape as shown above. While the asymmetry is present (if I plot to large frequency spans) it seems to have a quite small sensitivity to frequency scaling, which makes me wonder if parasitic inductances and capacitances would adjust this.
Just for clarity here is the new lineshape showing the asymmetry better in logarithmic units:
AI: The RCL circuit is actually a shielded inductor, so a solenoid inside
of a copper can essentially. The capacitance is parasitic coming from
coil-to-coil and coil-to-shield interactions.
This means that the noise comes from the inductor's series resistance and therefore is not parallel to the inductor but in series: -
simulate this circuit – Schematic created using CircuitLab
For the above (and below) I've made an estimate of the R, L and C values to roughly match the peak in the response at 29.6 MHz.
If so, then the 2nd order filter characteristic is low pass and not band pass such as shown with this on-line simulator: -
The red trace above is the response of a low pass 2nd-order filter and not a band-pass filter - might it look familiar?
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H: Why is GPU memory fixed?
In pretty much all modern computers and mobile devices, the CPU can have varying amounts of memory (either to be configured by the user or fixed at point of assembly). Apart from historical form-factor reasons (where GPUs just came as 'a card' that was actually composed of the GPU itself, power management, I/O and memory), is there any fundamental reason (ie, electronic engineering reason, not marketing) why GPUs don't come in different amounts of memories for a specific GPU model?
Of course, different models of GPU might have different amounts of memory, but to my knowledge, a specific GPU model will always come with a specific amount memory (for example, the AMD R9 280x in my workstation always has 3 GB of memory).
For general consumer applications, I can understand that there might be a cost/complexity argument - it is simply easier and cheaper to have one configuration. But for applications that are more GPGPU oriented, it seems like linking memory configuration to processor configuration could be limiting? (for example, my place of work recently acquired a number of GPGPU servers. Each of the GPU's comes with I think 24 GB or RAM, but the FDTD simulations they run don't need anywhere near that amount of RAM).
AI: Is there any fundamental reason (ie, electronic engineering reason, not marketing) why GPUs don't come in different amounts of memories for a specific GPU model?
Don't know whether you mean that with "marketing reason" but: memory slots, the boards and auxillary electronics of exchangeable RAM "modules" cost money. That's the main reason why you don't do that.
Technically, RAM chips can behave quite differently, and that's why you have the SPD information on the EEPROM of your PC RAM module: the memory controller needs to know how to even use the specific RAM you just plugged in.
That flexibility of course makes the whole thing both more prone to errors, and complex – not something you want, again, on cost level.
Don't forget that restricting the number of possible RAM configurations (as in amount, and sizes of individual RAM ICs) also simplifies not only the memory interface, but the system architecture and probably even reduces die size of the actual processing units: if you know how much memory you have at which physical addresses, you don't have to even think about designing in e.g. address remapping units that are flexible.
Then: When you add a connector to the mix, the whole host-RAM connection, which, especially in graphic cards, is a very high-rate bus, gets significantly less deterministic than when you solder the memory to the same high-quality multi-layer board. That means that your memory controller now needs to do way complex things, like effectively equalizing the received signal from the RAM, and that drives up complexity, too. In fact, it will shift the development effort of "make damn sure your RAM traces are within specs, dear graphic cards designer" towards "make damn sure the integrated memory controller can deal with all sorts of absurd channel effects, dear GPU manufacturer"; and you can see how that is non-desirable to companies that form an duopol on high-end GPUs.
or example, my place of work recently acquired a number of GPGPU servers. Each of the GPU's comes with I think 24 GB or RAM, but the FDTD simulations they run don't need anywhere near that amount of RAM
Yep, but exactly in the market of datacenter / HPC things, where hardware cost is less of an issue than reliability and extensibility, Nvidia GPUs with interfaces to "standard" DDR RAM modules exist. Nvidia themselves has the DGX-1 rack server.
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H: ADN8810 control frequency from Arduino Due
Resurrecting a 3 year old project. I'm skilled software engineer but new to electronics so it's a bit of a walk in the wood at night without a flashlight. The pcb has a ADN8810 - 12-bit current source with an adjustable fullscale output current of up to 300 mA. My understanding is that the output current is controlled by SPI.
So the question is: what is the maximum frequency I can change the current if ADN8810 is controlled by Arduino Due via SPI protocol?
AI: The maximum SCLK frequency, according to the datasheet, is 12.5 MHz, and a transfer takes 16 bits, so that limits your update rate to (12.5 / 16) MHz = 100 MHz / 128 = 781 kHz to begin with.
You have a settling time of the output of 3 µs, so, if you need accurate output after every time you write, that's take 16 / 12.5 µs + 3µs, but that's just latency; your effective possible rate of accurate change is 1/(3µs) = 333.33 kHz.
When you look at fig. 13, you'll find that the output impedance, however, starts drastically changing after ca. 1 kHz, so whether or not that works for you: depends on what you attach to it.
Regarding the Arduino Due: I'm not an Arduino expert, but an 84 MHz ARM Cortex-M3 like used on that board should do a couple MHz of SPI rate, easily. I don't know efficient the Arduino SPI library is – it might or might not be simple and close to the metal – but software is easy to replace; FreeRTOS runs on the Arduino Due, so you won't be maneuvering yourself into a development dead-end if the Arduino software platform doesn't work.
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H: Spherical waves in far field region
in my antennas book (I do not put its reference because it is not in english) it is written that, at high distance from the source, the electromagnetic field radiated by it is a spherical wave.
This can be shown by analyzing the expression of the EM field at high distance generated by some specific antennas. For instance, for a half-wave dipole (which is not the short herzian dipole) we get (Reference here, page 17):
It is a spherical wave because its dependence on r is given by the term:
\$\frac{e^{-jkr}}{r}\$
I do not understand how can be this physically possible. A spherical wave is ideally generated only from a point source. I easily understand how even the wave generated by a small source (for example a short Herzian dipole) can be, at high distance, approximated as spherical. But in this case, in which the linear current source is not short, I don't understand why the wave cannot be, more plausibly (from a physical point of view), cylindrical. Furthermore, if it is true that at a great distance any wave is spherical, in which situations do cylindrical waves exist? I can't imagine how a cylinder becomes a sphere at a great distance.
AI: There's a couple of parts to this. Within the near field, roughly less than couple of wavelengths away from the radiating element, there is no E&M wave as such. In the near field region, the electric and magnetic fields can exist independently of each other.
Once you get more than a handful of wavelengths away from the element, the traditional E&M field takes over (not being precise in my language here), and takes on the classical spherical wavefront.
As you get further and further away from the element, the spherical wavefront starts to flatten as a function of D (distance from the element). Think of the wavefront as being the circumference of a circle.
In the extreme far field, many many wavelengths away, the wavefront is to all intents and purposes flat (planar), as analogsystemsrf said.
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H: Verilog output is hiZ in testbench
I'm new to verilog and modelsim. I'm having trouble with my AND and OR modules in this particular testbench. The output is always Z(hi impedance)
module mux2to1_tb();
reg[1:0] r0,r1;
reg r2;
wire[1:0] out;
initial
begin
r0=1;
r1=3;
r2=0;
#10;
r2=1;
#10;
end
mux tm(r0,r1,r2,out);
endmodule
here is the mux module
module mux(d0,d1,s0,out);
input[1:0]d0,d1;
input s0;
output[1:0] out;
wire [1:0]w1,w2,w3,w4;
assign w4[0]=s0;
assign w4[1]=s0;
inv2bit M0(w4,w3);
and2bit M1(d0,w3,w1);
and2bit M2(d1,w4,w2);
or2bit M3(w1,w2,out);
endmodule
/*assign w3= ~w4;
assign w1= d0&w3;
assign w2= d1&w4;
assign out= w1|w2;*/
this is the or module
module or2bit(iA,iB,out);
input iA,iB;
output out;
assign out= iA|iB;
endmodule
this is the inverter module
module inv2bit(i1,out);
input i1;
output out;
assign out= ~i1;
endmodule
AI: You declared the out signal as a wire in your testbench, and you connected it to the out output port of your mux module. However, the out signal in mux is undriven (it is not connected to anything else). In Verilog, wire signals default to the z value.
In mux you have an undeclared signal named outX. Is this X a typo? In other words, out and outX are two different signals. If you rename outX as out everywhere, the out will be connected.
UPDATE: You have confirmed the X was a typo, and updated the Question accordingly. That problem is solved.
Since you added the inv/and/or module code to the Question, we can see that you try to connect 2-bit signals to 1-bit ports in your submodules. For example: w4[1:0] to i1 in inv2bit. You need to change the port declarations to be 2-bit wide, such as:
input [1:0] i1;
output [1:0] out;
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H: Is there a full list of the names & abbreviation of electronic components
I came by a few electronic components that I don't recognize them from their shape nor their letters printed on the PCB. Is there a full list of the names and abbreviation of electronic components?
Some of the letters that I don't know their components' names.
Q (SMD with 2 terminals from one side and 1 terminal from the opposite side)
Q (Not SMD with 3 terminals & has a tower shape, 3/4 circle)
IC (3 terminals from one side and 1 wide terminal from the opposite side)
OJ (It's like SMD resistance with a 0 written on top of it)
X (It might belong to the below component with SC8.000 writing on top of it)
SC8.000 written on the curved metal rectangular in the picture below.
AI: Is there a full list of the names and abbreviation of electronic components?
That would require a) full knowledge of all possible components and b) full cooperation of all engineers ever. So, no, such a list does not exist.
There's a few standards, but your board markings agree with none that I would be aware of. So, we can only help you "acutely" map the letters for this very board, not for other boards to types of devices:
Q is typically associated with transistors. There's multiple legend about where that hails from. It's probably a thing from vacuum tube times.
IC is just "integrated circuit". That can refer to anything from a single transistor with a biasing resistor in the same package, to a billion-gates CPU. In your 4-pin case, probably either such a self-biased transistor, a diode pair, or a linear voltage regulator, but it might also be a switch-mode supply, a or some other power electronics.
OJ is "orange juice". The "O" is probably a zero, and it's probably supposed to mean "0 Ω resistor or jumper", which "explains" the J
X is for Crystal
And that's exactly what the silver component is, a crystal oscillator. "SC" stands for "stress cut", and describes in which direction the piezoelectric crystal inside the metal dome has been sliced. 8 probably means "8 MHz", that's a common resonant frequency.
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H: Problem with LTC3872 Voltage Converter. Simulated results not matching with information provided in the datasheet
I'm trying to make a boost converter that takes an input of 3.7V and outputs 5V. I found a chip that I think will work well, the LTC3872 by Linear Technology.
In the datasheet they give an example circuit which takes an input of 3.3V and has an output of 5V. However when I tried copying that exact circuit in LTSpice, it actually decreases the voltage. The resulting output voltage is 2.72 volts.
I've gone over the circuit several times and I can't seem to figure out any difference between the two so I'm thinking that there either is a problem with LTSpice or with the datasheet.
Is there something that I missed or am I doing something wrong?
For reference the datasheet can be found here: https://www.analog.com/media/en/technical-documentation/data-sheets/3872fc.pdf
AI: I followed G36's suggestion and found a setting when I right clicked the module in LTSpice, and it appears that there was a different topology that they used that seems to work.
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H: External vs arduino power supply for servo motors?
I recently built a project that involves the control of three SG90 servo motors. I started off by controlling this through the 5V output pin of the Arduino Uno, with the Arduino powered through the barrel plug with a 9V mains power supply.
However, the servos couldn't perform the full 180° sweep, it would appear to be due to the high torque at the end of the motion for my application.
I then switched to powering the servos separately to the Arduino using four AA batteries in series. I now had no issues with the servos stalling and could perform the full sweep.
I am not sure why this is though.
Four AAs in series will result in 6V, which is not that different to the 5V Arduino output pin, and it seems the current is the issue with servo stalling. Surely the number of batteries makes no difference to this as connected in series it stays the same. Is the current of the AA battery just higher than the 5V Arduino output pin?
Any help would be greatly appreciated, I'd really like to have a better understanding of this.
AI: SG90 servo motors pull 360mA at stall, so 3 of them will pull up to 1,080mA. The MC332690-5.0 in the Arduino can only supply 800mA. So you will need an external power source if you want to fully power 3 of these servo motors.
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H: Without the use of any software, what would be the cheapest way to connect my broken laptop's keyboard to my desktop?
I am trying to use an old keyboard from a laptop as a new set of keybindable keys for my desktop. I will worry about software side later what I need here is this: How can I use the keyboard from my laptop as a USB or bluetooth, etc. input to my desktop?
I have searched around and I see often that when people don't use software from a laptop to desktop (Which I cant do due to the laptop being broken and unreasonable to fix) and they actually have the same question as me, it doesn't get answered because people just say "it isn't worth it"
I know it isn't worth it, but I still want to do it. Is there any electrical wiring solution to my problem? Again, I want to connect the ribbon cable from my laptop's keyboard to my PC somehow as an input device.
AI: This is like asking how you would change the electrically wiring on an HDMI cable so it plugs into an PAL/NTSC television. In other words, it assumes everything is the same except the wires are swapped around. Obviously this is not the case. If you are really lucky the USB in your laptop keyboard is self-contained then you just run those signals out to a plug, but then it is just a keyboard like any other that you can buy for $20. Not some special rebindable one.
Besides, I think laptops almost always, if not always, have the keyboard USB controller on the motherboard such that the keyboard itself is just a dumb matrix keypad.
What you are asking for is a custom "laptop keyboard USB controller" which is not something that can be built without a firm knowledge of hardware and software. Buy one or build one from an open source project. Just make sure you find one that allows rebinding in the controller itself.
Frank Adam's Project:
https://www.youtube.com/watch?v=Z1PheqSNNP8
https://www.hackster.io/frank-adams/laptop-touchpad-conversion-to-usb-d70519
https://www.instructables.com/id/How-to-Make-a-USB-Laptop-Keyboard-Controller/
https://github.com/thedalles77/USB_Laptop_Keyboard_Controller
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H: ESP8266 / ESP32 - Health issues
I am doing a pretty specific project, where I plan to connect up to 150 devices, mostly depending on ESP32 and a few ESP8266 devices.
All of them will be located in a tiny space of around 5-8 square meters.
Are there any research or norms (like ISO in Europe) that touches that topic?
Is it healthy to have so many active devices in such a small space?
How many wifi devices (ESP32 or ESP8266) can be “mounted” in one square meter (Ideally some researches or legal norms, not “just experience” or “commons sense” because this project aims to be a commercial one)
Is this a really health concern?
are there any research on that?
AI: Ok, that system makes no sense at all. IEEE802.11a/g/n as used by these devices is collision avoidance-based. That many devices in this little space would inherently lead to congestion.
Is it healthy to have so many active devices in such a small space?
No, because doing this means you've probably been drinking heavily!
How many wifi devices (ESP32 or ESP8266) can be “mounted” in one square meter (Ideally some researches or legal norms, not “just experience” or “commons sense” because this project aims to be a commercial one)
That's not touched specifically by legal limits, because the single-device legal limit suffices: these devices will avoid interrupting each other, so there will be constant congestion, and very few devices (as in: 1, or 2 per channel pair) will be active at a time.
So, already covered. Also, this commercial project will be a total failure.
There's nothing unhealthy about this. These devices are specified to not be active at the same time, so a) your network won't work, and b) even if it did, it would be totally harmless.
Also note that wifi devices do power control, i.e. when they talk to another device they know is close, they reduce their output power.
Just a quick calculation: 150 devices on 8 m² is one device every 12.3 cm, if you used the densest possible packing (that's hexagonal packing in the 2D plane). At that distance, you're not even in the far field of the antennas with your neighbor's antenna, and thus, the thing will totally break down, I'd presume.
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H: What are press-fit pins used for?
I found a this DIP socket that has "press-fit" pins. What are these actually used for? Are they literally used as a replacement for soldering? If so, why would anyone do this since that would seem to decrease permanence and increase cost?
https://www.mill-max.com/catalog/download/2017-11:096M.pdf
AI: Yes, they eliminate soldering. The corners of the pins bite into the walls of the plated-through holes with enough pressure to create a reliable gas-tight connection.
There are some PCBs on which the only through-hole devices are connectors and sockets (the rest are SMD, which are reflow soldered), so using press-fit versions of both eliminates an entire soldering step, which saves money in the overall process. Plus, they allow connectors to be on both sides of the board.
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H: Meaning of "no exposed metal in this area" on connector drawing
I am looking at the mechanical drawing for the JAE WP7B-P050VA1 connector, and it has the following drawing suggesting a PCB footprint:
My question pertains to the "no exposed metal in this area" note: does this mean that I am not allowed to run any traces through this area, or is doing so fine as long as it is covered by solder mask?
AI: Solder masks are not meant to be used as insulators, their purpose is to keep the solder contained within the pads. Solder masks are thin and are easily pierced. So, no traces in the indicated area.
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H: The proof of \$PF_{p}=cos\theta_p=sin\theta_s\$
There is a Series RC circuit ,which power factor is \$\frac{\sqrt{3}}{2}\$,now if i modify this "Series" RC circuit to "parallel" RC circuit,then what is the value of power factor of this circuit?
The answer shows me that
\$PF_{p}=cos\theta_p=sin\theta_s=\frac{1}{2}=0.5\$.does anyone know its proof?Why can this ,\$cos\theta_p=sin\theta_s\$,theorem hold?
\$PF_{p}\$:power factor of parallel RC circuit
\$\theta_p\$ : \$\theta\$ of parallel RC circuit, \$\theta=\theta_v-\theta_i\$
\$\theta_s\$ : \$\theta\$ of Series RC circuit, \$\theta=\theta_v-\theta_i\$
AI: In series RC, current passes through both R and C.
$$
P=i^2\cdot R \\ Q=i^2\cdot X_C \\ S = \sqrt{P^2+Q^2}=i^2\sqrt{R^2+X_C^2} \\ \therefore PF_s=\frac{P}{S}=\frac {R}{\sqrt{R^2+X_C^2}}
$$
In parallel RC (with the same R and C), the supply voltage is applied to both R and C.
$$
P = \frac{V^2}{R} \\ Q=\frac{V^2}{X_C} \\ S = \sqrt{P^2+Q^2}=V^2\sqrt{\frac{1}{R^2}+\frac{1}{X_C^2}}=V^2\cdot \frac{\sqrt{R^2+X_C^2}}{R \cdot X_C} \\ \therefore PF_p=\frac{P}{S}=\frac {X_C}{\sqrt{R^2+X_C^2}}
$$
So, finally we obtain
$$
PF_s^2 + PF_p^2 = 1
$$
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H: Extracting 25W from a pair of 18650 li-ion in series
If I have 2 bats of li-ion in series. 8.4V full charged and 6V full discharged. What should be their minimum mAh capacity, if they are 18650 size, and considering a constant load of 25W.
25W/6V = 4.16A?
Would they heat much at that power?
AI: What should be their minimum mAh capacity, if they are 18650 size, and considering a constant load of 25W.
Rather than look for a minimum mAh capacity, look for a cell rated for at least 5A continuous discharge, or ideally higher. For example, a quick search shows that the LG Chem sells the HG2 series, which are rated for 200 cycles at 20A discharge. I have no personal experience with that product, so it is worth looking at other high current batteries to see which makes the most sense for your application.
Would they heat much at that power?
It is going to depend on the battery. A 20A rated part probably doesn't get too hot at 4A, but cooling might be a good idea if you're going to sustain that load for long.
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H: What is the purpose of ferrite or inductor on the voltage input of FTDI chip?
I bumped into a couple of strange symbols that look like inductors or ferrite beads, I'm not sure what this is. Does anyone know what it is and what is the purpose of it? My guess is it has something to do with a general use of USB as a power supply. There are no parameters or anything to go by:
Here is a link to the document that has this schematic on page 28: https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT4232H.pdf
My plan is to ignore it, but I am afraid it might be important for the stability of this chip
EDIT: it seems to be an LC filter, as mentioned on page 9 of the datasheet. I'm still not sure if that is what it is or how to make it.
AI: My plan is to ignore it, but I am afraid it might be important for the
stability of this chip
Ignore at your peril: -
If you google around for USB interface circuits that use this chip, you'll find the appropriate device to use for the inductor. I've build one myself (and did the same) but, for the life of me I just cannot remember what I fitted other than that I went on the hunt for what other people had used and got an answer.
It's a bit crap that the data sheet isn't more forthcoming on this part of course. OK, here's a start: -
Located in this document. They are 600 ohm ferrite beads. I expect if you dig a bit more you'll find the part number. Use them.
You can find the part number in this document. It's an 0603 size ferrite bead so not hard to fit and, there is never a good reason to ignore them.
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H: Is my thinking right for the simple harmonic circuit
If this is a simple harmonic circuit, then what is the \$X_C\$?
I know harmonic circuit means that there is no value in the imaginary part of the impendence or admittance, that is, \$Z_{th}=R+0j\$ or \$Y_{th}=G+0j\$.
In this question, if the circuit wants to be a harmonic circuit, I think \$\frac{1}{R_1+12j}=Y_1\$, and \$\frac{1}{-jX_C}=Y_2=\$, and \$Y_1+Y_2=\$real value, not complex value.
So \$Y_1+Y_2=\frac{1}{1+12j}+\frac{1}{-jX_C}=\frac{1-12j}{145}+\frac{j}{X_C}=\frac{(1-12j)X_C+145j}{145X_C},\$ so now our purpose is let \$-12X_Cj+145j=0\$,
that is \$12X_C=145\$,so \$X_C \approx 12Ω\$
The solution from the book
\$X_C=X_Lp=\frac{1^2+12^2}{12}=12Ω\$
Although our answer are the same, I still want to ask that is my thinking, right? Why can the book just calculate like that, it seems the author just use some unknown formula. Does anyone know about that formula?
AI: If you drill down through the equation for the impedance of the circuit and equate the imaginary terms to zero you find that the frequency where the phase angle is purely resistive is: -
$$\omega = \sqrt{\dfrac{1}{LC} -\dfrac{R^2}{L^2}}$$
Then, if you square both sides and merge \$\omega\$ with the L and C terms to produce impedance terms you get: -
$$1 = \dfrac{X_C}{X_L} - \dfrac{R^2}{X_L^2}$$
$$\dfrac{X_C}{X_L} = 1 + \dfrac{R^2}{X_L^2}$$
$$X_C = X_L + \dfrac{R^2}{X_L}$$
So,
$$X_C = 12 + \dfrac{1^2}{12^2} = 12.0833\text{ ohms}$$
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H: Why output voltage becomes less when beyond resonating frequency?
In a class C amplifier (Figure A), every time the transistor turns on in every "pulse", the collector current becomes saturated. This charges the capacitor to its maximum (Vcc). This capacitor will always get charged to its maximum, independent of the input signal frequency.
So why does the output voltage reduce when the frequency is below or above its own specific resonating frequency? (Figure B)
I mean, whether the input frequency is in resonance or not, the capacitor will always get charged to the fullest when the transistor turns on, thus swinging the tank circuit to peak Vcc. So why is the output voltage damped when it is beyond the resonance?
AI: In a common emitter amplifier, the gain will be given by the the collector impedance and load impedance:
\$A_v = \frac{Z_{collector}//R_L}{r_e}\$, where \$r_e = \frac{26mV}{I_E}\$
Given that, a tank circuit reaches its maximum impedance at its resonant frequency. In other words, \$Z_{collector}\$ is maximum at \$f_r\$.
For frequencies below or above \$f_r\$, its impedance is lower and decreases as long as the frequency moves further from \$f_r\$. So the parallel \$Z_{collector}//R_L\$, and thus Gain \$A_v\$, is low for any frequency different of \$f_r\$.
Therefore, you have a tuned amplifier which only amplifies signals of a certain frequency and "ignores" other frequencies.
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H: Why do we use 2 transistors for each path of a MUX in CMOS?
Below is the schematic of a CMOS level 2to1 multiplexer. As you can see that if we want to choose A0, we set S input as Logic-0.
My question is that what happens if we remove one transistor from each path. PMOS from C0 path, and NMOS from C1 path. Doesn't the circuit work without them as well?
The schematic is taken from Yamin Li's Computer Principles and Design in Verilog HDL book.
AI: Doesn't the circuit work without them as well?
No it does not, the PMOS + NMOS circuit is called a passgate or transmission gate. So this circuit has two passgates, C0 and C1.
In order to be able to conduct a high signal, the PMOS is needed (then the NMOS does nothing).
In order to conduct a low signal, the NMOS is needed (and the PMOS does nothing).
Only when a signal is "in the middle" both NMOS and PMOS conduct the signal. Note that in digital (logic) circuits the signal should never be "in the middle".
As we do not know if the input signal is either low or high, we have to support both low and high so an NMOS and a PMOS are needed.
For a more detailed explanation of the pass gate, look here.
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H: ISO 7637 Supply Transient pulses - Explanation
I am trying to design an input power supply filter circuit inorder to protect from ISO 7637 pulses.
I am referring this Little fuse app note
There seem to be different pulses. Pulse 1, 2a, 2b and so on.
In page two of the app note, they have given the description of the pulses.
My questions:
Why are some pulses negative and some pulses positive? I just want to understand how some pulses can be positive and can be negative
Can someone explain in simple terms regarding the pulse 1 and pulse 2 description in page 2?
Like please explain "disconnection of the power supply from an
inductive load " and "Interruption of series inductive load"? Any block diagram or explanation with the concept and direction of current and voltage would be very helpful to me.
Quotes phrases are verbatim.
(P.S. I understand when an Inductive load is disconnected, we need to protect DUT with the help of a flyback diode to prevent from heavy voltage build-up. Is this the reason why some voltage pulses are positive and some are negative.)
AI: Here are some answers but, because you are not making quotes verbatim there are some answers that I cannot give. May I suggest you copy and paste the exact section you refer to.
Positive and negative pulses can come from the alternator when the battery is disconnected or connected (worse when disconnected)
Negative pulses can arise if there is an inductive load and the battery is disconnected - the inductance will try and take its former positive lead to a large negative value in order to keep current circulating (as per the normal inductor formula)
"disconnecting the inductive load from a power supply"
\$\color{red}{\text{That sentence doesn't appear in the document}}\$
"series interruption of inductive load"
\$\color{red}{\text{That sentence doesn't appear in the document}}\$
I tried partial sentence searches but I'm wasting my time realistically.
EDIT section with verbatim quotes
disconnection of the power supply from an inductive load
I believe I explained that under the 2nd bullet point above - a negative pulse appears on the previous connection to battery positive.
Interruption of series inductive load
This is the more regular flyback situation we see when we use a flyback diode to protect a transistor that might be controlling said inductive load.
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H: Find the average power dissipation of the load
I have given the following voltage and current waveforms.
I am required to find the average power dissipation of the load.
I know \$ P_{avg} = \frac {\int_0^T \mathrm{v}\mathrm{i}\,\mathrm{d}t}{T} \$
I have trouble finding the equations for the waveforms.
Please anyone help.
(Is there any other that is easier to find the average power ?)
AI: Well, because the function is periodic with period \$\text{T}\$, so \$\text{P}\left(t+\text{T}\right)=\text{P}\left(t\right)\$, we know that the average is given by:
$$\overline{\text{P}}=\frac{1}{\text{T}}\int_0^\text{T}\text{P}\left(t\right)\space\text{d}t\tag1$$
Where:
$$\text{P}\left(t\right)=\text{V}\left(t\right)\cdot\text{I}\left(t\right)\tag2$$
Using your pictures we get:
$$\overline{\text{P}}=\frac{1}{\text{T}}\cdot\left\{\int_0^\frac{\text{T}}{2}\text{P}\left(t\right)\space\text{d}t+\int_\frac{\text{T}}{2}^\text{T}\text{P}\left(t\right)\space\text{d}t\right\}=$$
$$\frac{1}{\text{T}}\cdot\left\{\int_0^\frac{\text{T}}{4}\text{P}\left(t\right)\space\text{d}t+\int_\frac{\text{T}}{4}^\frac{\text{T}}{2}\text{P}\left(t\right)\space\text{d}t+\int_\frac{\text{T}}{2}^\frac{3\text{T}}{4}\text{P}\left(t\right)\space\text{d}t+\int_\frac{3\text{T}}{4}^\text{T}\text{P}\left(t\right)\space\text{d}t\right\}=$$
$$\frac{1}{\text{T}}\cdot\left\{0+\int_\frac{\text{T}}{4}^\frac{\text{T}}{2}\text{P}\left(t\right)\space\text{d}t+\int_\frac{\text{T}}{2}^\frac{3\text{T}}{4}\text{P}\left(t\right)\space\text{d}t+0\right\}=$$
$$\frac{1}{\text{T}}\cdot\left\{\int_\frac{\text{T}}{4}^\frac{\text{T}}{2}\text{P}\left(t\right)\space\text{d}t+\int_\frac{\text{T}}{2}^\frac{3\text{T}}{4}\text{P}\left(t\right)\space\text{d}t\right\}\tag3$$
Now, try to prove that:
$$\int_\frac{\text{T}}{4}^\frac{\text{T}}{2}\text{P}\left(t\right)\space\text{d}t=\int_\frac{\text{T}}{2}^\frac{3\text{T}}{4}\text{P}\left(t\right)\space\text{d}t=\frac{\text{V}_\text{m}\text{I}_\text{m}\text{T}}{8}\tag4$$
Which gives:
$$\overline{\text{P}}=\frac{1}{\text{T}}\cdot\left\{\frac{\text{V}_\text{m}\text{I}_\text{m}\text{T}}{8}+\frac{\text{V}_\text{m}\text{I}_\text{m}\text{T}}{8}\right\}=\frac{\text{V}_\text{m}\text{I}_\text{m}}{4}\tag5$$
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H: Reverse voltage in LED buck converter circuit
The circuit
simulate this circuit – Schematic created using CircuitLab
Everything is fine except when the switch is open, I measure ~-3.5V on the points marked.
Why is that and is it dangerous for other components that get powered by the 5V after the switch?
The module is of those which are all over ebay
AI: The PC power supply is not earthed (it should be, for noise and for safety), that means that there is voltage relative to earth on both outputs. Since the LM2596 module is connected to the PSU those outputs are waving around at tens of volts wrt earth.
Stray capacitance from the output and multimeter leads couples to the LED ground connection and it is rectified by the diode (LED), so you see a DC voltage there (at very little available current)
If you properly earth the PSU that effect will disappear.
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H: RLC circuit and equivalent load resistance of a transformer
I would like to know when there is no more energy into the RLC circuit with the transformer. (R in RLC circuit symbolized the resistance at the secondary). I tried to simplify this model by doing an equivalent circuit without a transformer. Then It will be easier for me to do others calculs...
Here are the circuits :
For the circuit without transformer, the quality factor according to my calculs (which may be wrong) is the following :
$$Q = \frac{Rload2*\sqrt{C}}{\sqrt{L}}$$
According to my calculs which may be wrong, the equivalent load resistance at the primary is equal to :
$$Rload2 = \frac{Rload3*Np}{Ns}$$ where Np is the primary turn number and Ns is the secondary turn number.
So the equivalent quality factor Q of the circuit with the transformer is equal to :
$$Q = \frac{Rload3*Np*\sqrt{C}}{Ns*\sqrt{L}}$$
Nevertheless when I adjust Rload2 in the circuit without transformer to have the same quality factor Q, it rings differently. I could understand that the voltage/current waveform is different but I have some trouble to understand why the same energy at t=0 will take more/less time to be dissipated if Rload2 is really the equivalent resistance of the circuit Rload3 with the transformer
Here are the results :
So what is my mistake ?
Thank you very much !
AI: Impedance transformation
A transformer converts an impedance by using the turns ratio squared. Your formula just used the turns ratio (un-squared).
The reason is quite simple when you analyse 1 ohm on a secondary with 1 volt across it. This bit is easy; the current is 1 amp. Now, if the transformer primary had ten times the turns, the primary voltage would be of course 10 volts and the load current taken as seen on the primary side is 0.1 amps. Hence, 10 volts divided by 0.1 amps = 100 ohms. That's called the primary referred secondary load impedance.
A 1 ohm resistor is transformed to 100 ohms using a 10:1 transformer.
Apart from the above, it is unclear if L7 took account of the primary magnetization inductance as would be seen when you connected the transformer in parallel with L8. In other words I couldn't check this because your values are unclear.
Q factor
If you want to check your Q formula, this wiki page on RLC circuits can help. If I read your circuit correctly (i.e. the charging resistor can be ignored when the switch operates), then your formula is correct.
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H: How can I replace a SN74LS04?
I came across Ben Eater's Youtube channel and website and thought I'd give the clock circuit a shot (possibly doing the entire 8-bit computer thing in the future). He conveniently put list of items online what's in the kit. I wanted to order it from him, but shipping is quite expensive as I am not based in the US.
I can find basically all items, I do have some trouble finding the ICs though. One is a Hex Inverter 74LS04, but I cannot find that one (and also not the 74LS08 and 74LS32).
When searching for an inverter I do find the 7416, could that be a decent replacement (I checked the datasheets, and I don't really see a big differences). Same for the AND and OR gates, can I safely use ones that look the same on the first look?
AI: Generally, without having looked at any of these chips in particular, yes:
What you need here is the same functionality – if it's from the same logic family (LS), then it will react to compatible voltage levels.
You'll need to make sure these are actually the same functionalities – e.g. some things have push-pull outputs, other open drain, some things have tristate logic, others not...
Timing would not necessarily be the same – but considering this is breadboard, it's very unlikely that timing restrictions arise from the logic gates; the thing will be limited by the wiring parasitic effects.
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H: Steady-state Error Definition
In the textbooks and reference material which I have been using during my course on control systems, a common definition of steady-state error is as follows:
$$E(s)=R(s)-C(s)$$
where E(s) is the error (and also the signal carried forward directly from the summing node), R(s) input and C(s) output.
This definition has the slightly unsettling effect of yielding a negative error in the case that the output is above the reference signal, and vice versa. Wouldn't it be more logical to flip the RHS expression?
Is there any particular reasoning behind selecting this convention?
AI: where E(s) is the error (and also the signal carried forward directly
from the summing node), R(s) input and C(s) output.
The error is "demand" minus "output" and the output and the demand are desired to be equal hence, the "thing that does the math" is a subtractor: -
Picture from here.
This definition has the slightly unsettling effect of yielding a
negative error in the case that the output is above the reference
signal, and vice versa.
If the controller, feedback network and plant (as shown above) are non-inverting, then "demand" minus "output" is absolutely correct in that the error produced drives the system towards closer accuracy.
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H: Is it possible to have a register with multiple drivers?
This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are synchronous to the same clock. Normally in these cases I guess that you need a multiplexer to decide which signal actually go to the input of the register. But, it is possible to connect both signals to the input without any multiplexer? I am assuming that at all times only one source wants to write to the register. I have this question because I'm wondering if it is possible to avoid using the multiplexer and thus reducing resource usage in the final circuit.
Thank you in advance
AI: It's possible to do this in certain technologies, like bipolar open collector and custom cmos. But you won't see this available for most synthesis tools to implement directly in and FPGA or ASIC.
With open collector, you declare a net as tri1 or a wire with an attached pullup. Or you can use the wand net directly. Each open collector driver can pull the net to 0, but all have to be off to have the net be 1. I2C protocol uses this technology for intra-board communication. There are other technologies that give you a wire-ed NOR.
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H: Subwoofer high level connection and Class T amplifier
This question has a connection to a previous one of mine:
I have a BK Electronics Gemini I subwoofer that will soon be spare. It has two inputs called: low level and high level. The low level input is a pair of RCA connectors that may be connected to a suitable output of an A/V receiver. Up to now, this is the only one that I have used. The high level connector is a cable with a fancy connector at one end that goes to the sub and three bared wires at the other end: black, red, and yellow. The instructions say to connect the black to the black of the left or right speaker terminal. The red and yellow go to the red terminals of the left and right speakers. It assumes that the black terminals are common and this avoids an earth loop. Considering the responses to my previous question, I was cautious. There is a small warning to check before using it with a Class D amplifier.
I had considered using it in a different room with a small SMSL SA-36A amplifier. This describes itself as Class T. This appears to be a variant of a Class D. So, I presume that I should not use this form of connection to this amplifier.
Here's the subwoofer end of the cable: Neutrik Speakon.
AI: The amplifier chips were made by Tripath who went bankrupt years ago. The output per channel is about 8W, not 20W.
Yes, the outputs of the amplifier are "bridged" with no common ground, so they cannot be connected with only 3 wires.
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H: How to detect if the logic PCB can successfully communicate with the power PCB
In most devices (As washers, refrigerators etc.) you find a logical board (The one the user interacts with and mostly has the buttons and a digital or an LCD screens etc.) and you find the power board that that has the transformer, triac, relay etc.
The power board powers the logic board with a DC current, and the logic board sends different commands, I believe via electrical pulses, either via multiple pins or like in Morse code, which being received by a Microprocessor in the electrical board, which takes the appropriate action, like starting the motor etc.
My question is
In the pictures below, you find both boards connected via 10 pins, I believe 2 of them to provide DC power to the logic board from the power board, and I believe the other 8 pins is to deliver the command messages to the power board from the logic board.
DMM has 2 terminals, positive and negative, How should I connect them to these wires (Pins) to detect if the logic board indeed sending command messages to the power board?
AI: Not at all. A DMM is meant to measure constant signals (either DC or AC), not changing information signals.
What you'd need is a logic analyzer, and a bit of knowledge on the basics of serial interfaces like UART, SPI and I²C. Your question betrays that you're still missing too many basics – but that can be changed.
Because when I say sending a command or an electric pulse, in my mind the logic board will send electrons to the power board.
No, that's not how electricity works. A current flows, but the net amount of electrons always stays the same (and is irrelevant). What the transmitting end does is impose a voltage or a current on a wire.
Which means in my mind that these 8 Pins are paths for electrons from the logic to the power board. So to detect the electrical pulse on my DMM, I should connect the negative terminal to one of these pins, but where do I connect the positive terminal.
This betrays that you really need to think about what voltage is. The fact that there's electrons involved doesn't mean any voltage has to be negative.
Honestly, feels like you've skipped the part where you learn the basics of electricity (current, voltage, resistance, linear networks, Kirchhoff's law…), and try to skip to digital circuits.
That won't work. Take a step back, get a book or any other good introduction to the very basics of electronics.
(to answer the question: can't be said, probably you should connect your negative probe to device ground, and your positive to the data line, but these lines might be differential, and most definitely clocked themselves, so again, no chance measuring anything useful with a DMM.)
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H: Basic code using millis() function to calculate time elapsed
I do not know why the simple code below does not work. It may have to do with how unsigned long behaves?
Code simply determines if elapsed time has exceeded Snooze_Time which is 10000 by comparing the current millis() to the start value of millis().
unsigned long Start_Time;
unsigned long Time_Elapsed;
unsigned long Snooze_Time;
void setup()
{
Snooze_Time = 10000; //Time to start beep
Start_Time = millis();
Serial.begin(250000);
}
void loop() {
Time_Elapsed = millis() - Start_Time;
if (Time_Elapsed >> Snooze_Time)
{
Serial.println("ELAPSED >> SNOOZE");
Serial.print("Time_Elapsed: ");
Serial.println(Time_Elapsed);
Serial.print("Snooze_Time: ");
Serial.println(Snooze_Time);
Serial.println();
}
if(Time_Elapsed << Snooze_Time)
{
Serial.println("ELAPSED << SNOOZE");
Serial.print("Time_Elapsed: ");
Serial.println(Time_Elapsed);
Serial.print("Snooze_Time: ");
Serial.println(Snooze_Time);
Serial.println();
}
}
The early output from the Serial.prints is this, which appears correct.
Then once Time_Elapsed becomes greater than 65533, far greater than 10000, for no apparent reason both if statements pass for Time_Elapsed << 10000 AND Time_Elapsed >> 10000.
If fact, 65539 passes both if conditions
Any help is appreciated.
AI: if (Time_Elapsed >> Snooze_Time)
In C-style languages, >> and << are bit-shift operators (C++ which Arduino technically is adds some excessively clever overloading for additional uses, but that's not relevant here)
The comparison operators are <, >, etc.
On traditional platform's Arduino's millis() overflows after around 50 days, though there are some 3rd party platforms where it happens much, much faster. The tie-in to 65536 would be related to the size of an int on typical ATmega compilers, to the extant that your program changes there it only a curious result of the fact that you accidentally used an entirely inappropriate operator for your test.
There are existing questions on Arduino SE which discuss how to perform overflow safe timing.
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H: Max7219 and Common Anode Displays, choosing the correct transistors
I've got some common anode 7 Segment displays that I want to use a Maxim 7219 IC to drive with. The Max7219 is designed for direct driving common cathode displays but Maxim do have an app note that describes using the chip to drive higher current and/or voltage 7 segment displays as long as they are in a common anode configuration. In my case I want common anode, but at regular voltage/current levels.
The led's are fairly typical, 25mA max current, 3.3Vf, and I intend to drive everything from a 5V supply voltage.
I am not really sure what I should be looking for in the transistors though? I went for these two
2n3904 NPN Datasheet
AO3401A Fet Datasheet
as they seem to be able to handle the relatively small currents and voltages involved, and seemed to be quite cheap. My proposed circuit is below. Does this seem like a good choice?
AI: You did select a proper MOSFET and NPN transistor for your application. You selected a MOSFET that could handle maximum current through each seven segment display ( with good headroom) and voltage rating. You selected a proper NPN transistor which can handle current of each LED and with proper voltage ratings. These transistors can work at 5V. The circuit also looks good.
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H: cascading shift registers 595 vs 594
Simple question, i need to use 3 shift register to control 6 analog switches and 12 leds with only 6 digital outputs, nothing difficult BUT my IC provider doesnt have the clasic 595 in DIP package, so i was wondering to use a 594. Because i'm using analog switches for analog signals, it is very important that they all change at the same time, 595 has latch outputs with OE, wich is perfect, 594 just has a Rclk to pass with a pulse the data from Shift Registers to Out Registers, so my question exactly is :
Can i use ONLY this Rclk to control each IC (1 for analog switches and 2 for the leds) that way i put all the Shift Reg clk together so data goes thru all 3 IC and the Reg clr also together cause i need to have a LOW output everywhere at the power on of the system.
SO : 6 outs pins from microcontroller = 3xRclk, Serial data, Sr clk, Reg clr (Sr clr are put to high)
Thanks
AI: If you don't need the /OE (tri-state) functionality of the HC595, the HC594 is almost equivalent, except for the /RCLR input (which the HC594 has and the HC595 does not have). Pinouts, except for the /OE and /RCLR pins mentioned, are nearly the same.
The setup you descibe would work for 3 cascaded 594s with individual RCLKs. As you have to shift in 24 new bits whenever 1 output changes anyway, you could ask yourself if you need 3 separate RCLKs (one might do).
The same goes for /RCLR on the HC594. A parallel reset is very handy if you can spare an I/O pin on the Arduino, but you accomplish the same by shifting in 24 zeroes on startup (which you would have to do if you had a HC595 anyway).
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H: Creating ladder PLC logic using force inputs and outputs
I am currently using Allen Bradley PLC and RSLogix Micro to program it. The problem is:
Create a ladder logic diagram for the following problem in which pump #1 and pump #2, alternately or
simultaneously, pump liquid.
• When the level switch closes, first pump #1 turns on. If pump #1 runs more than 30 seconds, then
pump #2 turns on. Both pumps continue operating until the level switch opens, indicating a lower
liquid level.
• When the level switch closes again, pump #2 turns on. Note that either pump #1 or pump #2 will
turn on first to discharge the liquid. Similarly, if pump #2 runs more than 30 seconds, then pump #1
turns on. Both pumps continue operating until the level switch opens, indicating a lower liquid level.
Therefore, either pump #1 or pump #2 discharges the liquid, or both pumps discharge the liquid.
Use the force function to close and open the level switch and turn the pumps on accordingly to
discharge the liquid level.
Use the force function to turn off (i.e., disable) one of the pumps. Now, run the program and
examine if it is working properly.
The updated solution:
The question is that I am not sure if I understand the alternating process between the two pumps.
3rd attempt: The first part of the problem.
4th attempt: So I tried to insert the "flip-flop". And I understand that XOR command is used to alternatively change the value of the B3:0/1. However, when I tried to put in RS Logix the program that you provided, I could not write the address B:3.0/1. Because, it said that address should be specified to the word level. And also the BSR command is represented different in RS Logix. Is represented as in the picture below:
Assuming that the flip flop is working and the values are changing alternately I wrote the program.
Thank you so much!
5th attempt: This time the program worked. And the pumps where energized alternatively.
AI: You appear to be lacking understanding of how a PLC program is executed. The PLC code is scanned or executed every few milliseconds and the inputs read at the start of the scan and the outputs written at the end of each scan.
Attempt 1:
Figure 1. The problems.
When I:0/0 turns on O:0/0 turns on in the PLC memory (but the output won't turn on until the end of the program scan).
Since T:4/1 has not turned on yet the program turns off O:0/0. Since this is the last occurrence of O:0/0 before END this is what get's written to the output. Remember that the last rung to affect the output "wins".
Same as (1) above.
Same as (2) above.
How to fix:
Document your program. Assign names to your inputs and outputs, internal bits and timers.
Add comments to rungs to explain what each rung is doing.
Draw a timing or sequence diagram. This will clarify your thinking.
Outputs should only appear once in the program.
(If you need to) use bit memory, B:0/0, etc.. to keep track of status internally and then use those to control the outputs at the end of the scan.
The assignment has a bit of a twist in it because the outputs have to alternate. I suggest that you ignore this bit for now. Just get it working for the first sequence. Do that first and then update your post with the new code.
Delete rungs 0000 and 0002.
Write the logic for pump 1 on rung 0004.
Write the logic for pump 2 on rung 0005.
Tip: Reduce the window width before taking a screengrab so that the picture is legible in SE's 640 pixel wide image size. That way we'll be able to read it in the post.
Attempt 2:
Figure 2. This won't work because #1 Pump can never turn on.
Attempt 3:
OK, you've got that working. Now you need to make a bit "flip-flop" or alternate every time the float switch turns on. We won't use it yet - we'll just get it working. I'll give you the code for this as it's a bit tricky.
I:0 B3:0 +XOR------------------+
---] [-----|OSR|---------------+ Source A: I:0/0 +--
0 0 | Source B: B3:0/1 |
| Dest: B3:0/1 |
+---------------------+
Figure 3. A flip-flop created using the XOR instruction.
Have a look at the SLC 500 Instruction Set page 118 to understand the operation of the XOR instruction.
If you get that working you can now use B:3.0/1 in your output logic with simple modification to the two pump output rungs. Report back again and try to explain how you think the XOR is working.
Attempt 4:
We have a few problems:
Figure 4. A few more problems.
You forgot to say which PLC you're using so the instruction set may be different. You'll need to add the OSR in here. If it requires two bits then be careful not to use any that we're writing to elsewhere. I had written the address format incorrectly in Figure 3 and have corrected it.
For the XOR to work we need to Source B to be the same as Dest.
See 2.
Think when B3:0/0 is going to turn on and off. (Try it in your program.) Then think about what will happen the outputs when it does turn on. Will that satisfy your requirements?
Same as 4.
Once again, document as you go. You have omitted naming the bits. If you don't get into good habits with this you will suffer much pain in your career.
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H: Simplest way to limit current from MCU pin
I'm trying to build a very simple flyback power supply capable of only about 1mA. The basis is to supply a PWM wave to a 1-1 sepic inductor (shielded coupled inductor).
The problem is that it would be easy for the inductor to saturate and essentially short to ground.
It feels like there should be a simple and inexpensive way to limit current going to the coil (magical cccs1 below). For example, a FET + a gate resistor that will limit current through the inductor?
simulate this circuit – Schematic created using CircuitLab
Note. the circuit above is obviously incomplete for simplicity sake
AI: I'll assume that you don't want to just use a resistor, which would be the easiest and most straightforward solution.
A constant-current diode is probably the easiest solution for limiting current, at least when a resistor alone won't do. You can just buy one, but you can also make your own as the actual circuit is quite simple:
simulate this circuit – Schematic created using CircuitLab
Of course, what resistor you need to use depends on the threshold voltage and gain of the JFET, so it's not the most temperature-stable nor is it particularly stable with respect to device variations, but it's hard to get simpler if all you need is to limit current.
You can do a little better for stability by using a TLV431, and perhaps a lower voltage drop as well:
simulate this circuit
Here, the current will be limited to whatever current is necessary to generate a 1.24 V voltage drop across R1, plus whatever current R2 allows through the TLV431. The value of R2 isn't critical, but should be low enough to allow at least 0.1 mA (or whatever \$I_{K,MIN}\$ is for your specific TL(V)431) into the TLV431 cathode and enough left over to drive Q1. Note that if you use a TL431 instead of a TLV431, the voltage across R1 will need to be 2.5 V, not 1.24 V.
Any of these solutions will produce a voltage drop even when the current is below the limiting value, so be aware of that. There is an easy solution that won't produce much of a voltage drop: the current mirror, shown below.
simulate this circuit
Here, the current through Q1 is equal to the current through Q2. This has a few downsides, however: it relies on the transistors being exactly matched, and the current through Q2, set by resistor R1, is just wasting power in that resistor. There are ways to mitigate the matching requirement, though not eliminate it entirely, but there will always be wasted power in the resistor. This is why I tend to prefer the other options when possible; they have less of a constant power draw.
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H: Impedance matching for broad bandwidth voltage amplifier
I need some basic advice for impedance matching: I have a photodetector (Det01CFC from Thorlabs) that generates a current. For my experiment, I would like to amplify this signal with an amplifier. The amplifier that I can use is the LNA-1440 with an input impedance of 50 Ohm.
What kind of circuit would you use to get the best performance in terms of bandwidth and gain? For example, would it work to connect the photodetector directly to the amplifier since they seem to have a matching impedance, or do I need something in between?
Thank you very much for your help :)
AI: You should read the manual for your detector:
This detector is designed to drive a 50-ohm load. Since your amplifier has a 50-ohm input, there is no matching network required. You can just connect the detector to the amplifier through a 50-ohm cable.
In comments you added,
I plan to measure from about 5 MHz to 100 MHz
You should probably include a 100-150 MHz low pass filter in your system to eliminate noise that your 1.2 GHz detector and 1.4 GHz amplifier will be producing outside your signal band.
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H: Using an LSM6DS3 IMU with a LiPo battery power supply and LDO with Enable
I am trying to build a circuit containing the LSM6DS3 IMU (Datasheet) to be powered by the Sparkfun 110mAh Lithium battery PRT-13853 (Datasheet).
According to the datasheet of the IMU, it is able to operate in a voltage range from 1.71 to 3.6V (page 23):
The battery provides a voltage between 4.2 and 2.8V (page 4):
Edit: according to another question, LiPo batteries should not really be discharged below 3.7V. That should not change anything for my question though.
This means the batteries voltage stays high enough IMU during the entire discharge cycle, but must be regulated down.
Given the low current consumption of the IMU, I thought about using an LDO linear regulator. Would the TLV755P be a suitable regulator? If not, what alternatives would be better and why?
AI: LDO's are suitable for the use of batteries, but you are correct that the battery needs to be protected from overdrawing the voltage (low voltage condition).
The TLV755P has an enable pin that can be used to shut down the LDO at 1.28V (falling voltage).
simulate this circuit – Schematic created using CircuitLab
So if you do use an LDO make sure that it has an enable
Also, make sure you calculate the power dissipated
Power = Voltage drop x current through LDO
(The voltage drop is the battery voltage - LDO output voltage)
If its more than ~250mW then it would be a good idea to look into how hot the part will get.
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H: Using DDR4 RAM instead of SRAM
Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual resolution of around 500ps.
The BlockRAM has a size of a few MB. I want to safe around 2GB of ADC samples.
I am considering using a DDR3/DDR4 RAM module that is typically used in PCs.
I never saw someone using a PC RAM module to store data coming from an ADC.
Is it even possible to store the samples in a DDR3/DDR4 RAM module?
AI: DRAM (including DDR) requires the use of a memory controller, which takes care of the low-level details of timing, protocol and refresh management. The FPGA platform you're using likely includes configurable IP for this.
Your life will be easier if you use AXI or AXI-S internally to move your data, as these will be supported by blocks such as DMA and routing, as well as the memory controller you ultimately settle on. (Does not apply if you use Lattice, who, last I checked, only supported Wishbone.)
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H: Can I use a ferrite bead instead of a resistor on the data wire of my LED strip?
I have a WS2812B[PDF] LED strip which I want to control with the PWM0 pin (GPIO18) of my Raspberry Pi.
Multiple sources highly recommend to insert a 330-470 resistor in between the data pin of the controller and the DIN of the first LED.
It looks something like this:
simulate this circuit – Schematic created using CircuitLab
Apparently the resistor is there “for impedance matching between the [Raspberry Pi's] low-impedance output and the WS2812B's high-impedance input. When using long wires, they act like transmission lines, causing reflections, resulting in unwanted oscillations, ringing and noise.” quote This could damage the IC, cause flickering in the LED or something like that.
image source
But I'm currently missing such a resistor, so my first thought was that maybe a ferrite bead could as well do the job. (Therefore the question.)
The LED strip without any resistor or ferrite bead looks fine to me and I also don't own an oscilloscope, so I cannot verify if a ferrite bead would work equally well.
I also lack the skills in electronics and electrical engineering to be confident enough that I'm not talking complete nonsense here. If somebody could help me out with that, I would appreciate it. Thank you very much in advance!
AI: It's hard to say since we don't know what the input to the WS2812B is, but the datasheet does say that the digital input should be between -0.5V and 5.5V (which typically means there is diodes on the output and the input current is 1uA, which typically means that it is a FET not a BJT transistor input.
If the signal were to exceed 5.5V it would turn the protection diode on (but you wouldn't want to burn out the diode so keep it below 5.5V).
Either way its best to avoid ringing and wouldn't really matter how the ringing is stopped, just as long as it is attenuated and the rise time is not attenuated too much.
If people are touching the wire it might be good to put a TVS diode on the input so the first LED's input's aren't blown out.
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H: Why is my pullup resistor more noise immune than a pull down?
I have a circuit that appears to have some noise problems related to stepper motors I'm driving. When I changed some switches to use pull up instead of pull down resistors, I get better results. Why?
I'm using a PCF8574 digital IO expander for some limit switches. It has an interrupt pin that goes LOW on any transition from the limit switches. The limit switches are mounted on an aluminum frame with no more than 3' of wire. Several of the limit switches are within 1 inch next to a stepper motor, being driven at no more than 2.2A. Digital inputs are pulled low via 10Kohm, and the limit switches connect digital signals to 3.3V. Logic voltage does not seem to be a problem. The stepper motor and limit switch lines are sometimes ran next to each other (no cable shielding).
When I power my stepper motors, the interrupt pin goes nuts (my uC resets interrupt via a read request). As in, the IO expander detects high->low and/or low->high transitions when none of the limit switches are being pressed.
Limit switch state is correctly transmitted if I'm not powering the motors. Problem is only when motors are on.
Stepper motor drivers have adequate capacitors (470uF), and all digital logic have small caps nearby.
When I change from a pull down to a pull up resistor on the digital inputs, the interrupt does not go crazy.
Why do pullup resistors work better for my limit switches?
AI: PCF8574 I/O already has pull-ups in it, in the form of a 'weak 100 µA current source'.
If you try to pull the input down with 10 kΩ then the 100 μA internal pullup current flowing through your pull-down resistor will raise the open-circuit input voltage by 1 volt, reducing your noise margin.
With a 10k pull-up you are improving the noise margin because your resistor and the internal pull-up are working together instead of fighting each other.
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H: How should I size the transistors in the class AB linear amplifier
If I want to design a class AB linear amplifier as the following one, how should I determine the width of the pmos and nmos?
Class AB amplifier specifications:
Vdd: 6V
Input: 0.5V to 5.5V
Output voltage 0.5V to 5.5V
Output current: -450mA to 450mA
Length: 180nm
As both pmos and nmos are either turned on or off, so they are in the triode region instead of in the saturation region, so I suppose the square-law formula as stated below is not applicable in this case. Am I correct?
So if the square-law formula cannot be used, what formula can be used for sizing the transistors in the linear amplifier? Thanks.
AI: The parameters for FETs depend on your design specs for RdsOn (<1% of load), Vds, load, Pmax, thermal margin, etc.
Cross-conduction failure MUST BE avoided. (both Nch & Pch on at the same time)
With common-emitter, (CE) complementary drivers only one driver is active at a time. With voltage feedback, this eliminates the Vgs exponential factors and
eliminates the crossover-distortion with the Op Amp gain as error correction.
Each component in Class AB ought to be rated for power and temperature equal to the load so that at half power, you are derating your device dissipation and heat rise 50% which is prudent for any thermal design.
update
On second thought, it is possible to use PAIRED DRAINS with current feedback. But phase shift with high gain and stray reactive loads will need phase margin compensation. (not shown)
Here is my design
I chose very low RdsOn (mOhm) power FETs with an ideal Op Amp to drive an inverting BJT to the FET with negative feedback to correct for all non-linearity. I arbitrarily chose a voltage gain of 100 max.
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H: resistor combination circuit
simulate this circuit – Schematic created using CircuitLab
This is probably a very stupid question. I am new to electrical engineering in general, I was working with NOT transistor gates in order to make a simple SR Latch and came across this case. D2 and D1 in my circuit are both pulled to ground even though when simulated D2 should still be fine the only reason I decided to ask about this is because I couldn't find anything on the internet about it (maybe I was using the wrong terms?). If someone could take a moment of their time to tell me why this doesn't work that would be amazing. The desired result is to have D2 be ON while D1 is pulled to ground and OFF.
It seems I lack understanding in the topic and I'm trying to get a better grasp on it.
AI: R1 and R3 form a voltage divider.
This limits the voltage available to R2 to only 2.5 V.
The forward voltage of your LED is 2 V.
The remaining 0.5 V is dropped over R2, but this yields us a current of only:
$$\frac{0.5\ V}{4.7\ kΩ} =1\ mA$$
Which might not be enough to see it light.
Note that this is an over simplified way of calculating the voltages and currents (it's actually worse than I've shown). I am ignoring certain effects, but the overall point is, you are drawing current over those resistances which is limiting the voltage and therefore current available to the upper LED.
If you could do away with R1, and increase R2 and R3 to compensate, this could work.
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H: Is there a way to permanently assign 0 to one of an array of registers in verilog?
Is there a synthesizable way to permanently assign the value to a particular memory location? I need a reg that is fixed at 0 and cannot be written to. All writes should be ignored and the register must remain 0.
AI: The following will work for both synthesis and simulation, and should work for both ASIC and FPGA designs as it doesnt need an initial block.
wire imNothing = 0;
always @ * begin
theReg <= imNothing;
end
This is basically equivalent to connecting theReg to the wire imNothing which is permanetly attached to 0.
Having said that, this doesn't stop you overwriting the value.
In the case of your comment, using an array for which some indexes you wish to always be zero, then the above would only work if you avoid writing to the register.
You basically have to manually add the checks as part of your code. For example if you are writing to a memory, you could do:
memory[addr] <= (addr == ingoreAddr) ? 0 : writeData;
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H: Chip antenna too good to be true?
I have the following setup:
Very small PCB - 25mm in diameter that hosts chip antenna;
I feed directly into antenna matching network with about 7.5cm coax via ufl connector;
There are no other components on the board as I'm testing antenna only.
I use miniVNA Tiny to get some meaningful vision into the quality of RF that was proposed by the vendor. I calibrated it at the end of coax, so that I basically measure the antenna only.
Scanning the entire supported range from 1MHz through 3GHz produces the following results:
Which looks too good to be true. The frequencies I'm interested in are around 900MHz, 1.5GHz, 2.5Ghz, ie LoRaWAN, GPS and WiFi, and it looks like all good.
I really would like to play the devil's advocate to make ensure this is nothing wrong with my setup and I'm reading the right values.
What concerns me is that no matter how I try to confuse the antenna either with a metal object nearby or anything similar, fundamentally the outcome is similar in terms of values/diagram.
Update
A nice link that has lots of goodies at the bottom https://www.nonstopsystems.com/radio/frank_radio_coax-sw.htm
AI: You literally say "I don't trust the swr I measured to represent my system" (and I agree. The worst possible antenna is a perfectly matched termination resistor. Which has perfect swr. I often wonder why vswr is so commonly oversold as metric, especially within the ham radio scene!).
You have a device that calls itself vna - so do some network analysis with it instead of just measuring reflections!
Use your chip antenna as an antenna: use a known to be OK on at least on band antenna as counterpart.
Test s12 with your chip antenna connected to port 1, and more than 1 wavelength away your known antenna, connected to port 2.
If performance isn't worse outside of the bands your other antenna supports, something is fishy.
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H: Can I change the voltage (12V) input into my optocoupler to 24 V?
simulate this circuit – Schematic created using CircuitLab
I have an inductive sensor (LJ18A3-8-Z/BX,) normally open 6V to 36V 300mA. It is connected to a 12V 80kHz single channel opto-coupler. At the moment it is connected to a 12V DC power supply.
The positive wires (brown) from the power supply and sensor are screwed into one terminal on the opto-coupler board, the negative (blue) wires between the power supply and sensor are directly connected and the final wire from the sensor (signal?) connects to the second terminal on the opto-coupler board. According to the specification sheet for the sensor, it operates at 12V 8mA or 24V 15mA.
Can I change the supply voltage to 24V and if so, would I need to change or add a resistor to the opto-coupler board?
Between the terminals on the board and the opto-coupler chip is a 1Kohm resistor and a red LED on the other side. My thinking is I've essentially increased the power in the circuit by a factor of 4, assuming I should also increase the resistor by a factor of 4 as well?
optocoupler link data on the optocoupler link to supplier
AI: Inductive sensor parameter looks like quiscient current of sensor itself, nothing to do with output current. Output of sensor probably open collector. Optocoulpler has a LED inside, usually infrared. LEE! feed with curent, not voltage. With 12V supply you may have approximately 10 mA. For sure it could be measured with multimeter. 24V gives 12V in addition. So keep the same current resistor 1.2kOhm in series should be added. Or datasheet mention 50 mA max, the additional resistor not needed. But that info is not trustable.
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H: Is the voltage accurate?
The question is Find the Q-points for the diodes in the circuit using the ideal diode model:
The book solution is:
However, per my analysis both diodes are conducting because if as assumed that D1 is cut off the voltage at D1 cathode side would be -3.92 V which is less than the voltage for the same diode anode side! Thus, since
VD1 (anode side) = 0 - VD1 (cathode side) = -3.92
0-(-3.92) = 3.92
D1 will conduct.
Am I right?
The Book is:
Microelectronic circuit design / Richard C. Jaeger, Travis N. Blalock. — 4th ed.
ISBN 978-0-07-338045-2
AI: You are correct, both diodes will conduct.
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H: Transistor current limit
Suppose the DC motor has a peak current of 500ma and after that it drops to 100ma, the transistor can switch continuously 200ma.
If I limit the current of the transistor from the base current to 100ma, for some reason could the transistor consume a higher peak than that when starting the motor or would it be limited to 100ma?How effective is limiting hfe gain against inrush currents?
AI: The Hfe value is one of the least stable or predictable metrics or a BJT, datasheets often gives ranges of 50 to 200. Current gain varies widely from one device to another and also with current, temperature etc. That said, a BJT will do an effective job of limiting the inrush current but it’s not possible to predict with any degree of accuracy what the current limit will be.
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H: Inductor not working
I tried building a toroidal inductor with the following parameters:
OD= 1.400 in / 35.55 mm +/- 0.75 mm
ID = 0.900 in / 23.0 mm +/- 0.55 mm
Ht = 0.500 in / 12.7 mm +/- 0.50 mm
Wire: solid insulated copper 14G
Data sheet for the material: https://www.fair-rite.com/43-material-data-sheet/
For some reason inductor the is not working when a connect it to a battery (doesn't work as a magnet). I was expecting to get more than 100 micro Henry out of it.
Is it possible that is not working because the wire is insulated with thick plastic? What are other possible reasons for it not working?
Thank you!
AI: The magnetism you see from that coil will be very low. The main reason is that the wire is wound on to a ring. That means that the magnetic field has no need to leave the ring. Electromagnets are normally rods, or U-shaped.
The other reason is that you don't have many turns of wire. Electromagnets have a large number of turns. The insulation on the wire isn't a problem.
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H: 12VDC Fan rated at 0.08A only drawing 0.04A, can I increase current draw in order to bring the rpm up?
I've built a small desktop fume extractor for soldering.
It uses a 120mm 1000RPM, 12V, 0.08A case fan. Not huge, but it does the job.
The fan is only drawing roughly 0.04A and I have been fault finding and theory checking all afternoon and I can't figure it out and I feel like such a fool now, I should know this.
The fan is powered by a 12V DC 1.5A supply.
AI: The .08A is most likely just a guide to power consumption, not a spec. The fan is designed to work on 12VDC, and that's what you should give it. The current draw will depend on the load on the fan which usually won't change much. You could try upping the voltage a bit but it's really pot luck how far and at some point you will damage it if you go too far.
(Of course if you have a comprehensive data sheet for the fan you might be able to learn the max voltage, but mostly this info doesn't exist on cheaper models.)
If you don't have enough air movement, the solution is a bigger and stronger fan, or multiple fans.
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H: What is the difference between Continuous-Time and Continuous Value in signals?
I do not understand the difference between Continuous Value and Continuous-time. Discrete-time and discrete value. Can anybody offer a clearer explanation?
AI: I do not understand the difference between time & value
Time is along the x horizontal axis and, value is on the y vertical axis. The signal in the top diagram (left) and the bottom diagram (left) is both continuous in time and continuous in value in that there are no sudden changes in either axis.
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H: Is my Inverse z-transform solution method accurate?
The question is as follows:
The book answer is as follows:
However, my approach is as shown below I even cross checked my partial fraction and it was correct.
Please tell me where is my mistake?
Ok. Below is my revised trial after Mr. Any pointed where was my mistake. Kindly review my answer and advise me where is my mistake.
I used the z transform property of shifting:
AI: I stopped at what appears to be your first mistake: -
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H: Determining node voltages and ladder currents in R-2R DAC Ladder with Op-Amp
I'm really curious about the voltages at the nodes between the R resistors in the R-2R DAC ladder with an Op-Amp. I've tried using KCL and Ohm's law to find them, but I haven't been able to. Simulation shows different results.
The voltage source at the bottom is 3 V, in the ladder configuration, 2R resistors are vertical, and R resistors are horizontal.
R = 3 Ohm, 2R = 6 Ohm. Rf = 5 Ohm. The rightmost resistor is 1 Ohm.
One more thing to note, the switches seem to be on the ground, but when the simulation runs, I give it value of 1, and they are switched to the 2R resistors.
I've used the fact that the Op-amp has a "virtual ground" concept - when one terminal is grounded, so is the other. Therefore, the current through Rf resistor should be 4.98/Rf. The current through the rightmost 2R resistor should be just 3/2R, since one end is basically grounded. Then according to KCL, we have one current entering that node, and two currents leaving that node (one leaving to the 2R, the other leaving to the R). But this approach doesn't seem to be helping much. After a few nodes, the currents inthe ladder (and also the node voltages) stray really far away from my expected values. What am I missing here?
AI: The switches are connected incorrectly. There should never be a possibility that the ladder resistors are not connected to anything, which is what I see in your schematic. The switch needs to be connected so that the ladder resistor is either connected to ground or to the reference voltage at all times.
For me, the easiest way to analyze an R2R ladder is with superposition.
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H: Is the there a KiCAD plugin for making automatic board outlines?
Is there a plugin for kicad that can make simple shaped board outlines automatically? For example rectangles, rectangles with rounded edges etc.
I think that could be super usefull. Beacuse at the moment I edit the cooardinates of the lines manually to do precise cutouts.
AI: Well, rather than a plug in, you can use an external graphics package and create the PCB outline there. I use Inkscape, export the image via a .dxf file and then import as a graphic. Others might use Adobe Illustrator, and there are even more others than can export .dxf. Obviously AutoCad/SolidWorks and their derivatives/competitors.
So do this:-
To produce this:-
A point to note is that no matter how good a plug-in would be, it would still be a functional compromise when compared to a dedicated CAD/graphics package. I've had boards manufactured via this process and it's perfectly accurate. Just don't get too creative because you have to bear in mind the manufacturing capability of the board houses. They usually have a capabilities page somewhere.
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H: Offset problems with charge amplifier
I have a question about designing a charge amplifier.
I am currently using this simple setup for my application. As input, I can use several commercial piezo-based accelerometers. I need a pretty wide bandwidth (up to 0.1Hz). Instead of a high valued resistor (which would be about 1000 GOhm) I use a T-network instead.
The amplification of the accelerometer signal works fine. However, the offset of the signal is rather undefined. It drifts all the time between the two rails of the OPA.
I understand that with a defined offset, I can perform a correction at the IN+ Input of the OPA. But as the offset is drifting there is no chance with this method.
I know, that with 20pF, the amplification is pretty high (I need it for the detection of seismic activity). But also if I replace the capacitor with 2.2nF, the problem remains.
At last, when I apply a high signal to the circuitry (for example harsh shaking of the accelerometer), the signal goes into the rails of the opa. It stays there for a certain time until it recovers.
After the recovery, the offset of the output has changed considerably. Not like a drift but a stepwise change.
I suppose the whole effect is due to a charging effect somewhere. But as I am not really a specialist in analog circuitry, I cannot see where.
Probably it is connected to the pretty high resistance in the feedback. But I really need this bandwidth. And I have seen in published papers that these high resistors are not unusual for detecting seismic activity.
I hope you guys can help me. Thanks in advance.
P.S. The JFET OPA I am using: https://www.ti.com/lit/ds/symlink/opa4140.pdf?ts=1609760897207&ref_url=https%253A%252F%252Fwww.ti.com%252Fstore%252Fti%252Fen%252Fp%252Fproduct%252F%253Fp%253DOPA4140AIPWR
Proposal from Bimpelrekkie:
Add a capacitor in series to R17 in order to lower the DC gain. Like this:
However, as Bimpelrekkie also mentioned, the capacity must be very high in order not to alter the cut-off frequency at low frequencies. LTSpice shows that with a 1mF capacitor this is guaranteed.
Unfortunately, I don't have this high valued capacitors in stock. So I cannot test it immediately.
Proposal from Andy aka:
Andy aka proposed to short out R17 and decrease C28 to roughly 3uF. Like this:
However, this not only drastically changes the transfer function of the charge amplifier, but also creates an unwanted resonance at low frequencies.
Proposal from Andy aka #2:
Andy aka proposed, in order to simulate my setup correctly, I have to put the capacitor, defining my accelerometer, parallel to a current source.
So up to now all simulations in LTSpice are performed like this (capacitor in series with voltage source):
AI: In Spice, I just put a capacitor in series with the voltage source to
simulate the stuff.
This is probably the wrong way to simulate the circuit. The normal way is to use a current source in parallel with the capacitance of the accelerometer. What value source capacitor did you choose for the simulation?
The accelerometer has roughly a capacity of 5nF. Therefore I have
chosen this. Is this wrong thinking? Oh, that would be embarrassing
Well either you have the red face or I do but firstly, we should look at the reasoning behind your dc feedback network. I think you have gone for the 5000:1 attenuator so that you can choose a 10 MΩ feedback resistor so that input bias current effects are minimized. Looking at the op-amp data sheet, the bias current is worst case 10 pA at normal temperatures and through a 10 M&ohm, resistor, this will produce an input voltage offset of 0.1 mV. The feedback resistors provide a gain of 5000 so that immediately puts the offset output voltage at 0.5 volts and it's becoming problematic.
Changes in temperature of the device could make the offset input current 2 to 10 times worse and this is probably what you see.
So, back to basics (with me being prepared to be red-faced), use only unity gain feedback; maybe 15 MΩ: -
The AC response is now this: -
And that looks OK to me.
The transient response for frequencies of 0.01 Hz, 0.1 Hz and 1 Hz (all superimposed) with an excitation current of 0.1 μA is this: -
This is how I would set-up a simulation to design a charge amplifier and it's how I'd analyse the op-amp's input current in order to decide on an adequate DC feedback system.
Of course, I'm sticking my neck out but I thought you appreciate some tangible help even if I missed something important.
Following further conversations, it looks like the feedback capacitor needs to be significantly higher. Here's an AC response using a single 100 MΩ feedback resistor and variable capacitor: -
The problem is the limitation on open loop gain. In the picture above, I simulated using an OP4177 device and it's model has an open-loop gain of 100 million (160 dB) but this is not what you will find with most op-amps.
So with red constraints at 0.1 Hz and 10 kHz and a purple constraint at 160 dB, all you can play with is the feedback capacitor and it looks to me like 20 nF (as opposed to 20 pF) is viable but only if you can get an op-amp with this extremely large open-loop gain (160 dB). Typically, you'd be lucky to find a suitable op-amp that is much more than 10 million and then you are constrained to using a bigger feedback capacitor like 200 nF or even higher.
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H: Recreate "Voltage gain vs Frequency" graph of Op-Amp in LT Spice
I am trying to recreate the "Voltage gain vs Frequency" graph of the LT1037 Op-Amp in LT Spice. According to the datasheet page 6 the graph looks like this: -
Trying to recreate this in LT Spice gives me a graph, that doesn't match the graph above: -
As you can see, the gain is not as high, and graph starts to roll off at a higher frequency. I would like to know why the two graphs doesn't match at all. I believe it has something to do with the resistor values, but I have a feeling that I'm missing some key understanding - such as a wrong circuit design.
AI: The determination of the open-loop gain of an op-amp in a SPICE simulator can be done in various ways. However, in any case, to reveal the ac response, you need to maintain adequate bias on the output to prevent the op-amp from railing up or down. For instance, if you have a 12-V supply, you may want to maintain the output at 6 V so that enough dynamics exists on the output (no risks of saturation) when ac-modulating the circuit. Assume a large open-loop gain, e.g. 120 dB, then it translates to \$10^6\$ which implies a dc bias precisely tweaked at the µV level.
Another approach is to include the op-amp whose frequency response is needed within an external self-biasing circuit which automatically adjusts the dc bias to match the 6-V (or any other value) you want. The circuit is rather simple here with a LM358:
When you launch a SPICE simulation, whether it is an AC or TRAN analysis, the engine always starts by a bias point calculation to determine where to run the linearization of all nonlinear elements. Dc analysis is done by opening all capacitors and shorting all inductors. In the proposed circuit, the inductor LoL is replaced by a short while CoL is open-circuited. The voltage-controlled voltage-source then adjusts its output and biases the op-amp to have it deliver the voltage set by \$V_4\$ which is 6 V in this example: the circuit operates in closed-loop. Then, when the ac analysis starts, LoL and CoL form a low-pass filter and block any modulation, making the circuit run in open-loop in ac. If you plot the op-amp output in this mode, you obtain its open-loop gain as wanted:
This LoL-CoL trick is extensively used for opening the loop with averaged models for switching converters. What is cool with this circuit is that if you change the supply, the loading conditions or the op-amp sub-circuit, the auto-bias circuit automatically tweaks the bias to maintain the output within the selected output voltage range.
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H: Isolating and instrumentation Amplifiers, does the order matter?
I've been reading up on the concepts of properly isolating sensitive signals in applications like analog front ends.
For small signals, it is appropriate to use an in-amp. I understand that. But what about isolation?
It seems (see figure below) most flow-charts and lectures show the in-amp being the first stage of input, cascading into an isolation amplifier or barrier of some type.
Practically speaking, looking at isolation amplifiers it seems their topology outputs a differential signal to mitigate noise. However, what if you are only interested in observing the positive wave cycle? In this instance is it appropriate to leave the naught output floating? Pull down resistor? Or cascade into a differential amp?
TI Isolation Amp
From this line of thought, why is it important to first feed the signal to an inamp before isolation? If an isolation amp outputs a fully differential signal wouldn't it make sense to first isolate the signal, feeding the differential output to the difference amp and reduce the component count?
AI: In general, when amplifying small signals, you but the main gain stage first to get the signal up to a usable level. This makes the system more noise immune, and also (if the source is high impedance) performs impedance conversion.
In this case, reversing the order would mean connecting the source (looks like the human body in this case) directly to the isolation amp, which probably wouldn't work at all. If the preamp here is amplifying electrodes on the human body, the preamp needs to be first.
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H: voltage direction confusion
This may look notoriously trivial to ask.
we can see the direction of electron flow as indicated in the picture.
the down side of the arrow must be the positive side of the voltage drop in each resistor, so two positive voltages + v_be=0 it implies v_be is a negative (-0.7 approx.). but in every book it's written that v_be=0.7 volts, is not it incorrect? or they are just talking about the absolute value of v_be?
as indicated in answer section, it is just a matter of convention. now let us see a second picture :
a simple voltage divider JFET. Assuming these authors are following the same conventional current rules in all other circuits, here, the Gate-source voltage should be positive, as just like v_be, but this time it is negative. why?
AI: Not notoriously trivial because the reason is notoriously silly.
Benjamin Franklin did not know what actually moved to carry electricity so had to guess a polarity for each charged component.
He guessed wrong but by the time we figured out it was the negative-assigned particle (electrons) that actually moved, it was too ingrained and difficult to change so most things continue to use so-called "conventional" current flow, not actual electron flow.
That is an N-channel JFET which looks like this:
https://www.tutorialspoint.com/basic_electronics/basic_electronics_jfet.htm
Note the P and N-doped silicon. That forms a diode. If your gate voltage is more positive than the source terminal, that forward biases the diode and produces a short which blows the JFET.
So an N-channel JFET must have a gate voltage that is more negative than the source so that the PN-junction is reverse biased. In your circuit, the way the voltage dividers and resistors are set up, the gate voltage is lower than the source pin voltage, even though both voltages are still positive when measured relative to GND. Also, unlike the JFET circuit, the PN junction in the BJT is forward biased and heavily influences what voltage will appear between R1 and R2 since it effectively puts a diode and Re in parallel with R2.
It is not obvious in your diagram because it is using a single supply and dividers. It is much more obvious in a diagram like this:
https://www.tutorialspoint.com/basic_electronics/basic_electronics_jfet.htm
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H: Difference between a DC SSR (solid state relay) and AC SSR
I am trying to understand the difference between a DC and AC solid state relay. For electromechanical relays, I notice that they are often rated for some VAC load and a smaller DC load. Solid state relays, however, seem to be rated only for VAC or DC.
What would happen if one accidentally applied a DC load to a VAC solid state relay and vice versa?
Can one convert between each type with the addition of simple components (e.g. diodes, optocouplers, etc.)?
If I have a completely unmarked relay, how can I determine if it is for VAC or DC loads, preferably using a multimeter or similar device?.
AI: What would happen if one accidentally applied a DC load to a VAC solid
state relay and vice versa?
An SSR (solid state relay) that uses a triac as the switching element, when fed from a DC supply to a load that takes DC current, will never turn-off once activated. On an AC supply, by virtue of the supply alternating, it passes through zero every few milliseconds and, commutates the triac into an off state when it is no longer being activated by the control signal.
A DC SSR might not be capable of dealing with the reverse voltage situation of AC because it might only use a single MOSFET as the switch. What would happen then is that when the supply reverses, the MOSFET will act like a conducting diode hence, it would be inappropriate to use it in many situations.
Can one convert between each type with the addition of simple
components (e.g. diodes, optocouplers, etc.)?
No.
If I have a completely unmarked relay, how can I determine if it is
for VAC or DC loads, preferably using a multimeter or similar device?.
The same with any device that has no provenance; it's pretty useless and unreliable in all but the most desperate of situations. Don't get into that desperate situation is my advice. If you need an SSR, buy one that has provenance and a data sheet and one that is sourced via a reliable distributor from a recognized original manufacturing facility having decent quality standards.
What to check for when buying an electronic component or module.
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