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H: Simplest ATmega328P / Arduino PCB schematic for PC serial communication
I'm a little bit new to electronics. For a project, I needed the simplest possible form of Arduino board. The board will recieve data from the PC via serial connection, run some basic computations (using an Arduino library) on this data, and return the output to PC with serial connection. There are two basic things that I need from this board.
Should be Arduino bootloader burnable (If yes, how will I do it?)
Should be able to do serial communication via USB.
I have used ATmega 328P-MU (the SMD version) as the microcontroller and FT232RL for USB to UART conversion.
And this is my design (I'm using easyeda.com):
Since I'm new to electronics, I wanted to check if the design is correct and the board will run as I want, before I send the design to online PCB assembly.
Should I change anything in my design, or will it work as I wanted?
Thanks in advance :)
AI: Should be Arduino bootloader burnable (If yes, how will I do it?)
You need a SPI connection (pins 15, 16, 17 and reset) to your mictrocontroller in order to burn the bootloader, which is still missing from your schematic.
Should be able to do serial communication via USB.
It should be possible, after you have burnt your microcontroller.
However, if you don't really have a very good reason for replicating an arduino board, you should just buy one arduino platform.
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H: When does the transformer equation hold?
The "transformer equation" is as follows, $$\frac{N_s}{N_p}=\frac{V_s}{V_p}$$
What is assumed when this equation is used?
(Primary coil on the left, secondary on the right, in both cases)
Is transformer 1 an ideal transformer, or transformer 2 (I have seen both in books and I'm not sure whether in the first picture, the other field lines are just not shown because they are irrelevant). It would make sense that transformer 1 is ideal and is 100% efficient because no work is done by the magnetic field in the air, but wouldn't a magnetic field through "ideal air" do no work regardless? How does this relate to flux linkage? Surely the flux linkage in both coils must be the same for the equation to hold, so in transformer 2, conceptually, less magnetic field lines go through the secondary coil than the primary coil, therefore the equation would not hold.
AI: The most basic and important assumption required for the equation to hold is that all of the flux generated in one coil (primary or secondary) passes through the other coil. For this assumption to be true, generally a magnetic core is needed to trap and guide the flux from one coil to the other. Without the core, much of the magnetic flux generated by one coil does not pass through the other coil.
After that, there are many issues that lead to deviation from the ideal behavior, such as various forms of losses.
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H: Problem with wide voltage range CC sinking
I want to sink ~10 mA of constant current at wide range of voltages even lower voltages like 10 mV, below circuit suggested to me in one of my older questions:
simulate this circuit – Schematic created using CircuitLab
The problem is when input voltage is zero, output will became negative (link to simulator):
Making another path for the current to flow solves the problem to some degree but the output is still negative (link to simulator):
How can I prevent the output from getting negative?
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. A quick test.
I suspect that your problem is that Q1's emitter is one diode-drop below ground - maybe at -0.6 or -0.7 V. Meanwhile the transistor is in saturation so the collector is probably 0.2 V higher than the emitter at -0.5 V.
A quick test would be to raise the base voltage by one diode drop - done here by R2 and Q2. This should hold the emitter closer to 0 V and may be adequate for your problem. I've chosen to use the base emitter junction as a diode so that the voltage drops will match.
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H: What might be inside my speaker switch?
I have a speaker switch which has been in continuous use since some time in the 1980s. It a QED SSU4. To my surprise, there are plenty of pictures on the net and even some for sale. Even more surprising, is that the prices are similar to what I paid new decades ago.
It connects up to 4 pairs of stereo speakers to one amp output. There are 4 nice rocker switches to turn each set off with no limitation e.g. all 4 off, all 4 on, and any other combination. (*)
I am interested in how it achieves this claim: "At no time will the load presented to the amplifier fall to less than 1/2 of the speakers in use. i.e. with 8 ohm speakers the minimum load will be 4 ohms which almost all amplifier are capable of driving." So, it is not simply connecting all in parallel. It is a passive unit (no power supply).
This seems to be true. It spent most of its life connected to a NAD 3020B which claims to cope with 4 Ohm but not 2 Ohm. At times, e.g. student parties, it was driven hard but never showed signs of failing. Now it is connected to a SMSL SA-50 which also seems happy but it is not run so loud any more as I am no longer a student.
I don't want to open it up and look as I may damage it. It is still doing an important job well.
I don't necessarily need to know how this specific switch is made but how could that function be achieved with 1980s technology?
(*) My maths says that is 16 combinations though the instructions claim only 15 and they are not omitting all off as all on and all off are explicitly listed.
Edit: further detail in response to comments.
Here is a link to a unit that looks just like mine. The packaging seems slightly different: https://www.canuckaudiomart.com/details/649374943-qed-4way-speaker-switching-unit-model-ssu4/images/1624887/.
As mentioned in comments, some combination of parallel and serial connections is a possibility but you might expect this to cause a considerable change in volume as the switches were flicked. There is a change but it is quite small. Nothing is currently connected to output 2 but 1, 3, and 4 are in use. No other set goes off at the wrong time as switch 2 is thrown. This suggests that output 2 is never in series with another.
AI: It has 1 and 2 in parallel with 3 and 4. Within each pair, it switches the speakers in one at a time or in series. There is a load resistor to keep the impedance at or below 220\$\Omega\$
I was curious enough to work this though, so I'm going to write an answer describing how I worked it out.
There are probably a number of ways you could wire something like this. The first clue is the specification that the impedance presented to the amplifier would be no lower than half the speaker impedance. This is a big clue that some of the time the speakers are in parallel. The second is that amplifiers put out quite a lot of power and this is a small box, so there is unlikely to be any resistors standing in for unused speakers or it would get very hot.
Google turns up some photos where someone has taken one apart. That is a big help. Cropped, and with labels added based on the other photos, we have:
Two things are immediately obvious:
The left and right channel are laid out exactly the same, and don't connect to each other anywhere. This is what you'd expect.
The wiring of speakers 1 & 2 is identical to the wiring of speakers 3 & 4 (except the resistors - I'll come back to them later), and connected in parallel. That tells us the first part of how this works.
These together mean we only have to bother tracing 1/4 of the wiring, which saves some time. Tracing out the wiring gives:
simulate this circuit – Schematic created using CircuitLab
Where I've drawn it out in all four combinations of switch positions, and highlighted the wires which are carrying current to the speakers. So that is the second half of how it works.
So What are the resistors for? Well when both switches are off, there is not path from amp+ to amp-, and not all amplifiers are happy driving an open circuit. They provide a 220\$\Omega\$ path through both switches to prevent that.
Why don't you hear a large change in volume from speaker 2 when you switch out speaker 1? Well, that's another question altogether. It will depends a bit how the amplifier reacts to changes to the load impedance, but also the human ear/brain combo has a very non-linear perception of loudness.
Finally, I though I would note down the impedance the amplifier sees with different switch positions (assuming all speakers are 8\$\Omega\$):
Any one speaker: 8\$\Omega\$
Speakers 1 & 2 or 3 & 4: 16\$\Omega\$
Any other pair of speakers: 4\$\Omega\$
Any three speakers: 5.3\$\Omega\$
All four speakers: 8 \$\Omega\$
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H: Ideal inductor in DC circuit
If a ideal inductor of inductance L is connected to dc voltage say,V. How does the current change across it?
I tried writing kirchoff's law
\$ V = L \cdot \dfrac{di}{dt} \$
I got
\$ i (t) = i(at \text{ } t=0) + \dfrac{V \cdot t}{L} \$
is my try correct?
AI: The current-voltage relationship for an inductor is: -
$$V = L\dfrac{di}{dt}$$
The above relationship tells you that current rises linearly when you apply a fixed voltage to the inductor. More generally, the formula can be solved for current by integrating both sides: -
$$i = \dfrac{1}{L}\int{v\: dt}$$
And, for a linearly rising voltage (for instance) with \$v = V_{S}\cdot t\$,
$$i = \dfrac{V_{S}}{L}\int{t\: dt} = \dfrac{V_{S}}{2L}t^2$$
So, if your DC voltage source is fixed at some value, you would use the top formula to calculate how current changes linearly with time. If your DC voltage source is (for example) rising in amplitude, use the last formula. There are of course many other examples where the DC voltage source is changing differently to those above so, this answer is just an example of some possibilities.
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H: Why is an inductive load presented as a resistor on schematic diagrams?
The presentation of a resistor load, such as a light bulb, as a resistor on a schematic diagram makes sense to me. However, why do we present inductive loads as such, seeing it isn't a resistor as such?
AI: The resistor symbol is commonly used to indicate "There is a load here of some type", even if that load is not a resistor. It's just a convenient way to simplify schematic concepts. It does not mean inductors=resistors.
Technically, light bulbs are not resistors either. Their resistance is highly non-linear, and they do not behave like resistors.
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H: Best way to have circuit powered by USB when plugged in and battery when not?
I am building a circuit that uses a rechargeable battery and also has a USB port so it can be plugged in to charge the battery and power the system.
I am using a buck/boost converter to supply 3.3V for the circuit. I want the input for the converter to be the battery voltage when not connected to USB, but when plugged in, I want the input to be the USB.
One way I thought to do this was with a low forward voltage drop diode in series with each supply. Think it would work, but still some voltage drop, not the most efficient.
Another way I thought would be with a P channel FET that switches the battery voltage off when USB 5V is at the gate. Seems like the better method.
Would either of these solutions work?
Thanks
EDIT
Following the advice given, this solution seems like it should work:
*Note the symbol for P channel Fet was re drawn from original image so that source is on top and drain on bottom
AI: I just asked a similar question here. One answer was what you proposed in your first circuit, but the diodes need to be ideal and the voltages need to be the same. See user 比尔盖子's answer.
The solution I chose was a premade power supply mux from Pololu:
https://www.pololu.com/product/2596
US$5 and does everything I need it to, and can handle different voltages.
EDIT: Also, you will need a buck/boost on the output of circuit to maintain consistent voltage (LiPo won't be 5V exactly so your Vout will jump around without it). I also discovered you need a lot of cap on Vout because the IR droop from the switching will cause circuits to brownout and/or reset.
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H: Electrical pole wires dividing
I would like to ask you very lay question. I know that there are 3 phases wires on this electrical pole on this picture. But where is neutral wire? I want to have more clear in this question.
Thank you
EDIT:
I thought until now that neutral wire is needed as output always. And so wires which are going from electric power generator for example from water power plant can be just phases, no need neutral wire?
AI: A neutral wire is not required to transmit 3-phase power. It is not required for distribution and usage either in many situations. It is only used in situations where it is desirable to use line-to-neutral connection for single-phase loads at a lower voltage than the line-to-line connection.
Neutrals are generally formed where required using a transformer. They are the exception rather than the rule. A neutral is not made available at the generator except where a portable generator is designed for loads to be connected directly.
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H: Breadboard and Circuit Confusion
I'm still a noob to this stuff, and I've run into a problem I can not explain, or understand. I will need help translating / editing this into a real question for you all, so please bear with me.
ASSUME all else is connected properly (pin 1,2,8,9,15...)
See pictures below, this is a simplified version of the whole - the difference is the resistor.
This is a shift-in register (SN74HC165N) that I am using for a joystick controller via an Arduino Leonardo.
With the resistor (top picture) everything works fine, but I can not see how the bottom picture does not work.
How would this look in a circuit diagram? Is there a free automatic breadboard to diagram app out there? Perhaps that would help me understand what is happening.
AI: Figure 1. What you've got. (1) V+, (2) switch and (3) GND.
simulate this circuit – Schematic created using CircuitLab
Figure 2. (a) What you did in photo 1. (b) What you did in photo 2.
In Figure 2b if you press the button you short circuit the power supply.
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H: LTspice model of the UC3845 oscillator
I have a circuit whose the purpose is to reduce the EMI by "moving" the switching frequency around a value. I would like to understand how this circuit affects the switching frequency, i.e. how it affects the oscillator frequency of the UC3845. For this, I need to understand how the UC3845 is working. Finally I would like to do an FFT for seing how it change the frequency spectrum.
Here is the datasheet: https://www.mouser.fr/datasheet/2/308/UC3844B-D-1814882.pdf
According to the datasheet the frequency is set according to a capacitor Ct and a resistor Rt. It is mentionned that the "capacitor Ct is charged from the 5.0 V reference through resistor Rt to approximately 2.8 V and discharged to 1.2 V by an internal current sink." I can predict the charging time of the capacitor but with the informations given I can't predict what would be the discharging time... as I do not know the sink current. Apparently the sink current or the capacitor depends on the deadtime that we want to have." During the discharge of Ct, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the output to be in a low state, thus producing a controlled amount of output deadtime" The output is the pin linked to N MOSFET. So it is opened. Well, I though "deadtime" was the time when the energy in the inductor is null, it is only possible in DCM. Nevertheless in the datasheet it seems to mean that the MOSFET is just OFF. Did I do a mistake?
What is interesting, or (what I learnt) is that the resistor Rt and the capacitor Ct do not only set the switching frequency but also the deadtime.
Nevertheless, I do not know how to model the oscillator without knowing the current drawn from the capacitor by the current sink. That's why i am looking for an LTspice model of this IC.
Thank you very much and have a nice day!
AI: Since you're aiming to make a model for an IC, I'd recommend you go the behavioural way. You could implement a real current source, discharge, proper elements, but the simulation will just go much slower for virtually the same results.
This is a behavioural version for an oscillator I made once for the venerable TL494. It can be configured based on external R and C, with a frequency f=1.2/(R*C) (which can be changed), with variable blanking time set by the a parameter, and with adjustable peak voltage set by Vpk.
The nodes R and C are the external pins, and rst is the blanking pulse. Rt and Ct don't need to be defined with a .param, but like this they are there for automatic frequency calculation (shown on V1, not needed) and measuring purposes, which show that the method is pretty accurate. This can be simplified to work without I1 and R1, different configurations (charge from Vref, discharge to ground), etc. This is one option out of many, it gives you an idea (or more).
As a final note, unless your aim is to "get dirty" with modeling, I'd recommend to search the net for already existent models, which may be made by people who are likely to know more than you about these things. If it were me, I'd recommend to search the LTspice group, in the Files section (you'll have to register, no money needed though). I seem to recall models for these PWM ICs in there.
Looking over the datasheet you linked, it looks like there's no mention of the internals of the oscillator, but if you search for the datasheet from TI (for example), it says that there is an internal threshold of ~2.7V, and the pk-pk oscillator waveform is ~1.7V. It also says that the discharge current is ~6mA.
However, in your datasheet (which is taken from OnSemi), it depicts the waveforms of the oscillator, where it clearly shows that the charge/discharge is not made with constant current. That the charging is not constant, it's obvious since Rt goes from Vref to RT/CT pin, but the comment on the 6mA discharge in the TI datasheet seems to be misleading.
With these in mind, here's an adapted version which is not accurate, but works:
V1 shows (in green) the frequency that should have been, according to TI's datasheet (f=1.72/(RC)), and the error log shows the measured frequency. It's ~10% difference, and you could set some lower/upper thresholds, maybe a larger discharge resistance for the switch, and you could get closer. If you really want this path, by all means, have fun.
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H: Difference between junction points in old schematic
What's the difference between the black circle and the white one in this old schematic? Of course the black ones are junctions, but are the white circles a pin, or an input of some kind? I'm trying to redraw the circuit in KiCad but I can't find a way to express the "white" junction.
The attached picture is a Tone assembly of a vintage amplifier from the 70s.
AI: Notice that the hollow circles are only on the potentiometer connections. If the potentiometers are mounted off-board separate wires will be attached to those points.
Figure 1. Off-board potentiometer wiring example. Image source: blog.mklec.com
Guitar Effects Pedal Offboard Wiring demystified. (This seems to be offline now.)
On your PCB design I would use a pin connector symbol - maybe a pin header.
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H: External power to WEMOS mini using 3.3V 1W Zener diode
I'm using a 12V DC 2A power source to power a 12V LED strip, and controlling it using a WEMOS mini and a relay.
Yes, I know there is a power shield for WEMOS, but I tried to regulate the 12v input to power the WEMOS as well, which did not succeed.
First I tried with a 3.3V Zener diode via 3.3V pin on WEMOS- with no success.
Later I tried with a 5.1V Zener diode, and 5V pin on WEMOS - and again no succees.
See schematic (please ignore diode's catalog number.) Circuit yields voltages as expected.
Measuring current, using a multi-meter, shows a draw of only 10mA, when I guess a 200mA is needed at start.
Since it is a 1W diode, at least P=VI should yield a nominal of 200mA when using a 5V diode.
simulate this circuit – Schematic created using CircuitLab
AI: If you need 200 mA at 3.3 volts, R1 must be no more than 43.5 Ohms. 1K would drop 200 volts when passing 200 mA.
Much better to use a switch mode voltage regulator (DC-DC converter). A linear regulator would dissipate 1.75 Watts, and require a heatsink.
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H: Meaning of "A voltage source “likes” an open-circuit load"
I read a book "The Art of Electronics" by Paul Horowitz, Winfield Hill.
In the book, I saw some phases.
A voltage source “likes” an open-circuit load and “hates” a short-circuit load
A current source “likes” a short-circuit load and “hates” an open-circuit load
It said "obviously" at the end of the first sentence, but I think I need more understanding of what it's meaning by.
AI: A voltage source shorted causes current to rise until something overheats or burns out. Therefore shorts are bad for a voltage source and could damage it.
An open circuit for a current source causes the voltage to rise until current flows. Usually the source will reach it's limit and stop regulating current.
Both of those conditions cause the respective sources to stop functioning correctly. Hence they "hate" it. The opposite condition represents no load, hence they "like" not having to work.
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H: How does this audio power amplifier circuit work?
How do I simulate an audio amplifier in Multisim?
I'm required to search for audio power amplifier circuit and explain how it works in details so I need to know the detailed process of this circuit and understand how does it work?
also I found this circuit from here SE
AI: Unfortunately you have NOT chosen a "normal" circuit.
The chosen circuit relates to a TDA2002 IC - datasheet here which has unusual connections.
With this IC Pin 2 is allowed to have "AC coupling" via a capacitor due to the IC being "unusually constructed" internally.
This is NOT the case for every amplifier IC or for standard opamps - the diagram you are using would not work wity standard opamps or many other amplifier ICs.
I suggest that you look at the TDA2040 circuit here which is very very similar BUT which connects the IC in a more standard manner.
TDA2040 datasheet here
The diagram below is taken from fig 13 of the datasheet.
This diagram, from the above page, operates in a standard manner and is a MUCH better example for your purposes.
DO NOT just copy the following. Use it as a starting point for understanding. Ask questions if you need to.
R2 & R3 set the DC level of the amplifier's pin 1 input at about half supply voltage.
R5 ensures that Vout properly tracks the pin 1 DC level.
R5 and R4 set the AC gain.
R6 C6 is a Zobel network - Google knows.
C3 blocks DC from the speaker.
______________________________________________
SIMPLE ALTERNATIVE:
OR the LM358 circuit from this SE EE question is very simple and may suit your need.
Note - this is a "preamplifier" in that it amplifies the microphone signal to a level suited to the main amplifier. It does however demonstrate the principles that you are required to explain, except for the power level.
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H: Transfer Verilog Code to For Loops Syntax
I have built an block that does simple moving average on a "factor" numbers in the vector.. and its works good for my needs.
My problem with it that I think my syntax is bit dumb.
I have an array and I push my data into the array and using the factor trigger (can be 2,4,8,16,32) I accumulate the data signals and than make right shift to divide by the factor value.
I read that using for loops is not recomendded but maybe its just nonsense and for loops in synthesis is perfectly fine.
someone can confirm that using for loop for my need is fine and how it can be done here so it be can be synthesized?
my code:
module average #
(
--parameters--
)
(
input clk,
input rst_n,
input [FACTOR_WIDTH-1 : 0] factor, // Average (2, 4, 8, 16, 32)
input [INPUT_WIDTH-1 : 0] din,
--more inputs outputs--
);
reg [INPUT_WIDTH-1 :0] din_dly [0:32-1];
reg [OUTPUT_WIDTH-1:0] dout_sum;
reg [OUTPUT_WIDTH-1:0] dout_shift;
initial begin
dout_sum = {OUTPUT_WIDTH{1'b0}};
dout_shift = {OUTPUT_WIDTH{1'b0}};
for (index = 0; index < 32; index = index + 1) begin
din_dly[index] = {INPUT_WIDTH{1'b0}};
end
end
always @(posedge clk or negedge rst_n) begin : average_logic
if (~rst_n) begin
dout_sum <= {OUTPUT_WIDTH{1'b0}};
dout_shift <= {OUTPUT_WIDTH{1'b0}};
--flags=0--
end else begin
if (--flags--) begin
if (factor == 2) begin
dout_sum <= din_dly[0] + din_dly[1];
dout_shift <= dout_sum>>1; //dout_sum / 2;
end
if (factor == 4) begin
dout_sum <= din_dly[0] + din_dly[1] + din_dly[2] + din_dly[3];
dout_shift <= dout_sum>>2; //dout_sum / 4;
end
if (factor == 8) begin
dout_sum <= din_dly[0] + din_dly[1] + din_dly[2] + din_dly[3]
+ din_dly[4] + din_dly[5] + din_dly[6] + din_dly[7];
dout_shift <= dout_sum>>3; //dout_sum / 8;
end
if (factor == 16) begin
dout_sum <= din_dly[0] + din_dly[1] + din_dly[2] + din_dly[3]
+ din_dly[4] + din_dly[5] + din_dly[6] + din_dly[7]
+ din_dly[8] + din_dly[9] + din_dly[10] + din_dly[11]
+ din_dly[12] + din_dly[13] + din_dly[14] + din_dly[15];
dout_shift <= dout_sum>>4; //dout_sum / 16;
end
if (factor == 32) begin
dout_sum <= din_dly[0] + din_dly[1] + din_dly[2] + din_dly[3]
+ din_dly[4] + din_dly[5] + din_dly[6] + din_dly[7]
+ din_dly[8] + din_dly[9] + din_dly[10] + din_dly[11]
+ din_dly[12] + din_dly[13] + din_dly[14] + din_dly[15]
+ din_dly[16] + din_dly[17] + din_dly[18] + din_dly[19]
+ din_dly[20] + din_dly[21] + din_dly[22] + din_dly[23]
+ din_dly[24] + din_dly[25] + din_dly[26] + din_dly[27]
+ din_dly[28] + din_dly[29] + din_dly[30] + din_dly[31];
dout_shift <= dout_sum>>5; //dout_sum / 32;
end
--logic--
end else begin
--logic--
end
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
din_dly[0] <= {INPUT_WIDTH{1'b0}};
din_dly[1] <= {INPUT_WIDTH{1'b0}};
din_dly[2] <= {INPUT_WIDTH{1'b0}};
din_dly[3] <= {INPUT_WIDTH{1'b0}};
din_dly[4] <= {INPUT_WIDTH{1'b0}};
din_dly[5] <= {INPUT_WIDTH{1'b0}};
din_dly[6] <= {INPUT_WIDTH{1'b0}};
din_dly[7] <= {INPUT_WIDTH{1'b0}};
din_dly[8] <= {INPUT_WIDTH{1'b0}};
din_dly[9] <= {INPUT_WIDTH{1'b0}};
din_dly[10] <= {INPUT_WIDTH{1'b0}};
din_dly[11] <= {INPUT_WIDTH{1'b0}};
din_dly[12] <= {INPUT_WIDTH{1'b0}};
din_dly[13] <= {INPUT_WIDTH{1'b0}};
din_dly[14] <= {INPUT_WIDTH{1'b0}};
din_dly[15] <= {INPUT_WIDTH{1'b0}};
din_dly[16] <= {INPUT_WIDTH{1'b0}};
din_dly[17] <= {INPUT_WIDTH{1'b0}};
din_dly[18] <= {INPUT_WIDTH{1'b0}};
din_dly[19] <= {INPUT_WIDTH{1'b0}};
din_dly[20] <= {INPUT_WIDTH{1'b0}};
din_dly[21] <= {INPUT_WIDTH{1'b0}};
din_dly[22] <= {INPUT_WIDTH{1'b0}};
din_dly[23] <= {INPUT_WIDTH{1'b0}};
din_dly[24] <= {INPUT_WIDTH{1'b0}};
din_dly[25] <= {INPUT_WIDTH{1'b0}};
din_dly[26] <= {INPUT_WIDTH{1'b0}};
din_dly[27] <= {INPUT_WIDTH{1'b0}};
din_dly[28] <= {INPUT_WIDTH{1'b0}};
din_dly[29] <= {INPUT_WIDTH{1'b0}};
din_dly[30] <= {INPUT_WIDTH{1'b0}};
din_dly[31] <= {INPUT_WIDTH{1'b0}};
end else begin
if (--flag--) begin
if (factor == 2) begin
din_dly[0] <= din;
din_dly[1] <= din_dly[0];
end
if (factor == 4) begin
din_dly[0] <= din;
din_dly[1] <= din_dly[0];
din_dly[2] <= din_dly[1];
din_dly[3] <= din_dly[2];
end
if (factor == 8) begin
din_dly[0] <= din;
din_dly[1] <= din_dly[0];
din_dly[2] <= din_dly[1];
din_dly[3] <= din_dly[2];
din_dly[4] <= din_dly[3];
din_dly[5] <= din_dly[4];
din_dly[6] <= din_dly[5];
din_dly[7] <= din_dly[6];
end
if (factor == 16) begin
din_dly[0] <= din;
din_dly[1] <= din_dly[0];
din_dly[2] <= din_dly[1];
din_dly[3] <= din_dly[2];
din_dly[4] <= din_dly[3];
din_dly[5] <= din_dly[4];
din_dly[6] <= din_dly[5];
din_dly[7] <= din_dly[6];
din_dly[8] <= din_dly[7];
din_dly[9] <= din_dly[8];
din_dly[10] <= din_dly[9];
din_dly[11] <= din_dly[10];
din_dly[12] <= din_dly[11];
din_dly[13] <= din_dly[12];
din_dly[14] <= din_dly[13];
din_dly[15] <= din_dly[14];
end
if (factor == 32) begin
din_dly[0] <= din;
din_dly[1] <= din_dly[0];
din_dly[2] <= din_dly[1];
din_dly[3] <= din_dly[2];
din_dly[4] <= din_dly[3];
din_dly[5] <= din_dly[4];
din_dly[6] <= din_dly[5];
din_dly[7] <= din_dly[6];
din_dly[8] <= din_dly[7];
din_dly[9] <= din_dly[8];
din_dly[10] <= din_dly[9];
din_dly[11] <= din_dly[10];
din_dly[12] <= din_dly[11];
din_dly[13] <= din_dly[12];
din_dly[14] <= din_dly[13];
din_dly[15] <= din_dly[14];
din_dly[16] <= din_dly[15];
din_dly[17] <= din_dly[16];
din_dly[18] <= din_dly[17];
din_dly[19] <= din_dly[18];
din_dly[20] <= din_dly[19];
din_dly[21] <= din_dly[20];
din_dly[22] <= din_dly[21];
din_dly[23] <= din_dly[22];
din_dly[24] <= din_dly[23];
din_dly[25] <= din_dly[24];
din_dly[26] <= din_dly[25];
din_dly[27] <= din_dly[26];
din_dly[28] <= din_dly[27];
din_dly[29] <= din_dly[28];
din_dly[30] <= din_dly[29];
din_dly[31] <= din_dly[30];
end
end
if (--some flags--) begin
din_dly[0] <= {INPUT_WIDTH{1'b0}};
din_dly[1] <= {INPUT_WIDTH{1'b0}};
din_dly[2] <= {INPUT_WIDTH{1'b0}};
din_dly[3] <= {INPUT_WIDTH{1'b0}};
din_dly[4] <= {INPUT_WIDTH{1'b0}};
din_dly[5] <= {INPUT_WIDTH{1'b0}};
din_dly[6] <= {INPUT_WIDTH{1'b0}};
din_dly[7] <= {INPUT_WIDTH{1'b0}};
din_dly[8] <= {INPUT_WIDTH{1'b0}};
din_dly[9] <= {INPUT_WIDTH{1'b0}};
din_dly[10] <= {INPUT_WIDTH{1'b0}};
din_dly[11] <= {INPUT_WIDTH{1'b0}};
din_dly[12] <= {INPUT_WIDTH{1'b0}};
din_dly[13] <= {INPUT_WIDTH{1'b0}};
din_dly[14] <= {INPUT_WIDTH{1'b0}};
din_dly[15] <= {INPUT_WIDTH{1'b0}};
din_dly[16] <= {INPUT_WIDTH{1'b0}};
din_dly[17] <= {INPUT_WIDTH{1'b0}};
din_dly[18] <= {INPUT_WIDTH{1'b0}};
din_dly[19] <= {INPUT_WIDTH{1'b0}};
din_dly[20] <= {INPUT_WIDTH{1'b0}};
din_dly[21] <= {INPUT_WIDTH{1'b0}};
din_dly[22] <= {INPUT_WIDTH{1'b0}};
din_dly[23] <= {INPUT_WIDTH{1'b0}};
din_dly[24] <= {INPUT_WIDTH{1'b0}};
din_dly[25] <= {INPUT_WIDTH{1'b0}};
din_dly[26] <= {INPUT_WIDTH{1'b0}};
din_dly[27] <= {INPUT_WIDTH{1'b0}};
din_dly[28] <= {INPUT_WIDTH{1'b0}};
din_dly[29] <= {INPUT_WIDTH{1'b0}};
din_dly[30] <= {INPUT_WIDTH{1'b0}};
din_dly[31] <= {INPUT_WIDTH{1'b0}};
end
end
end
endmodule
thanks!
AI: For loops in Verilog can be used for synthesis purposes. However the caveat is that the number of loops must be known at synthesis because the tools will unroll the loop into hardware. This means your loop limit must be a constant, a parameter/localparam, or a genvar.
As such if you want to use for loops in your code, you'll need to find a way to factor it such that you have a constant number of loops. One such example might be:
reg [FACTOR_WIDTH-0:0] i;
always @ (posedge clk ... ) begin
...
dout_sum = {OUTPUT_WIDTH{1'b0}};
for (i = 0; i < 32; i = i + 1) begin
dout_sum = dout_sum + ( (i < factor) ? din_dly[i] : {OUTPUT_WIDTH{1'b0}} );
end
...
end
That way you still have the same number of loops always, but you simply add on (32-factor) zeros on in some of the loops. This will result in a chain of adders and multiplexers which may not give a high f-max.
You would have to reconcile how to do dout_shift. This could be done with a simple lookup table to convert factor into how many bits to shift.
An alternate solution would be a generate for block which makes one set of logic for each different factor.
//logic to convert factor to a value 0-5 representing log2(factor). Can be a simple case statement.
reg [5:0] factorLog2;
...
reg [OUTPUT_WIDTH-1:0] dout_shift_all [5:0];
genvar i;
generate for (i = 0; i < 6; i = i + 1) begin : factor_loop
// Create the sum - this is the async part of the calculation
reg [OUTPUT_WIDTH-1:0] dout_sum_factor;
integer j;
always @ * begin
dout_sum_factor = {OUTPUT_WIDTH{1'b0}};
for (j = 0; j < (1 << i); j = j + 1) begin
dout_sum_factor = dout_sum_factor + din_dly[j];
end
end
// Pipeline dout_sum_factor
reg [OUTPUT_WIDTH-1:0] dout_sum_buf;
always @ (posedge clk) begin
dout_sum_buf <= dout_sum_factor;
end
// Could make pipeline this but would take an extra clock cycle compared to original code
always @ * begin
dout_shift_all[i] = dout_sum_buf >> i;
end
end endgenerate
//Existing logic tweaked to use dout_shift_all
always @ (posedge clk ... ) begin
...
dout_sum_shift = dout_shift_all[factorLog2];
...
end
This would produce more logic but would be faster as it's more parallel and pipelineable.
|
H: Is there any device or way to measure how many watts a computer's processor is using?
I know there's a device to measure how many watts a computer is using, you get an energy meter you plug the computer into it and it tells you
But I'm interested in finding out how many watts a processor uses.
Is there any device that can plug into a CPU socket as an intermediary and report it, and then that figure could be displayed on an LED or fed out on a wire and read by an arduino or raspberry pi.
Is it feasible and reasonably simple for such a device to be built?
e.g. just as one can measure how many volts a power supply rail is using, e.g. one can check that the red wire is 5V.. So too would it be simple to have a socket that is female one end and male another end and exposes its pins and then would a multimeter or some device connected to it be able to read off the power without interfering with what the processor is doing?
Processors do report TDP but that's a maximum. I'm interested in how many watts it runs at e.g. idling.
added It has been pointed out to me that watts don't necessarily correlate with heat across processors e.g. an Intel Core i5 3230M is is based on 22nm, the cores are big.. Compared to a newer processor like a 7000u/8000u would be based on 14nm, and AMD's 4000 series is based on 7nm. It's apparently perhaps a combination of small core and low watts that lead to low heat.
AI: Some motherboards, especially laptops, have this as part of their sensor suite: https://unix.stackexchange.com/questions/68531/return-value-of-current-watt-consumption-on-command-line.
Also, try OpenHardwareMonitor for Windows.
The power supply for a large CPU will usually be put through a switchmode converter right next to it on the motherboard, and that itself may be a microprocessor or dedicated IC. Given that these measure their output voltage and through current as part of their operation, that is the ideal point to take a measurement. Note that it may vary a lot from one microsecond to another depending on CPU load.
The power management systems will want to know the power consumption so they can adjust the fans, the CPU speed scaling and ACPI power state in order to achieve best performance without overheating.
Edit: a device that fits in the socket is called an "interposer", and looks like this.
Intel also sell them, although with a price listed as "build to order" that's going to be very expensive. The problem in building one is not disrupting any of the data signals.
|
H: Multiple inputs for 5.1 audio system
this is my first post here and I hope I chose the right SE site.
I have a Logitech X-530 5.1 audio system, which is very old and supports input using 3 3.5mm jacks for Front, Rear and Sub (I suppose, green, orange and black jacks).
I'm currently using the system with the provided 3-female-jacks-to-2-female-RCA adapter and a RCA-to-3.5mm-jack cable connected to the computer. I know the system is used as a 2.1 one and it wasn't a big deal, until I decided to update my working station and include additional computers.
Right now, I would like to connect the speakers with 3 computers which will output audio but not at the same time. One computer has an integrated 5.1 sound card, another has a USB 5.1 sound card with an additional Line In jack and the last one just the headphones jack.
Is it possible to achieve this setting by making a switch like this one?
How would the circuit be changed in order to have 3 output jacks (for the speakers) and 3x3 input jacks for the computers the switch has to act on?
Are there any electonic-related info I need to worry about? In case I don't have a soldering unit, do you know any already made switches or alternatives?
Thank you so much!
AI: The best choice regarding user interface would be to select the input with the least amount of fumbling with switches. A rotary switch could be an option. Here's an example showing a 6-positions 2-pole switch:
Turning the knob turns all switches simultaneously so this switch would allow to select one stereo source (2 channels) from 6 sources.
Here you'd need at least 3-position switch since you have 3 audio sources, and 6 poles since you have 6 channels. This will require some searching, but you'll probably find one. Here's a 4 pole 3 positions switch as an example.
Another solution would be with pushbuttons, same as your usual home theatre amplifier. I'd recommend a trip to the nearest electronics junkyard to gut a broken 5.1 amplifier. Failing that, you can pick 6PST or 6PDT pushbutton switches, latching (not momentary). But if you use independent switches, then when you push one to switch on a source you'll have to switch off the previous one, so that's 2 button presses.
Edit: schematic with pushbuttons
All grounds (sleeves) are connected together.
Each channel has a bus (light green) connected to the corresponding output.
Each input can be connected to its corresponding bus via the pushbuttons (red lines).
If two buttons are pushed at the same time, two inputs will be connected to the same output. This is usually not a problem as most audio devices will tolerate a short. If you are paranoid you can replace the red wires in the drawing with resistors, say 330R.
|
H: PCB Crystal Layout
I'm designing PCB with 16MHz crystal for ATMega328p.
Right now that is my layout. VIAs ring around edge of board is to stop EMI radiation from edges.
There is no Ground plane under capacitors and crystal. Top layer under ATMega is Ground, bottom VCC.
Red is top, blue is bottom.
Crystal and MCU ground plane is connected to Global bottom ground plane only in one place.
As You can see there is not much space on PCB.
Can anyone suggest me how to improve my layout?
@EDIT
Updated with suggestions. Should crystal grounds be connected together or only stiched to bottom ground plane?
@EDIT2
I haven't moved labels inside PCB, because i don't care about them. I'll be ordering PCB without top silkscreen, so that's not a big deal.
That about VIAs under crystal ground pins? Should it be there?
I've reduced number or VIAs. It looks like that now:
AI: Initial Design Review
The first thing I notice is your MCU ground is only connected to the main ground plane via a tiny thin trace that runs around the crystal:
This means all the current return paths from the various signals will run through this elongated loop which will effectively act like an antenna - the complete opposite of what you want.
You should try to give the MCU as solid of a ground connection as possible. I'd remove the power plane from underneath the MCU and make it a solid ground plane with several stitching vias connecting top and bottom layers underneath the MCU. Route the route power traces to the various via as a simple trace - perhaps a little star connection if you wish.
There is a decoupling capacitor on the left of the chip, however that doesn't connect to the ground plane below - a via could be added which would help the situation.
Secondly I wouldn't remove the ground plane underneath the crystal. Leaving the large gap will cause the current return paths for the crystal traces to have to flow through an elongated path back to the MCU instead of being able to run directly underneath the traces in a short loop.
Remove the ground plane gap, and add stitching vias from the crystal caps back to ground.
You probably don't need to isolate the stitching ring from the ground plane on the top layer either. I'm not sure it will have any affect doing so.
Update: (Based on Revision 2 of question)
The layout of the ground plane is much improved. I would suggest however you've gone a bit over the top on the number of extra stitching vias.
For underneath the MCU, I'd go with either 5 vias in an X shape, or 9 vias in a 3x3 grid.
For the MCU and decoupling caps one or two each will be fine.
My other suggestion would be to tidy up the reference designators on the board. Make sure all ref-des labes are within the confines of the board, and don't overlap the copper pads.
Update: (Based on Revision 3 of question)
Much better. My only final point would be to remove the four vias directly under the crystal. The ground pads of the crystal typically just connect to the shell and have little function. You can simply connect the pad in the top right to the ground plane, and a small trace to the bottom left pad as in your first drawing.
|
H: Computer Instruction Format - Calculating the number of Opcodes
I found the following question on a different site:
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______ .
Note – This question was Numerical Type.
(A) 14
(B) 15
(C) 16
(D) 12
The author claims the correct answer is 14. I do not understand why. Here is my reasoning. For an I-type instruction, we have 6 bits for the register and 4 bits for the immediate value. That leaves 6 bits left over for the opcode. That means that we should have 2^6 = 64 opcodes which means we have 64 - 8 = 56
R-type opcodes.
Another way to look at this problem is to say that an R-type instruction needs 12 bits for two register specifications. This leaves 4 bits for the opcode. Hence, there are 16 R-type opcodes. I am not sure
about what happens because some of the I-opcodes overlap.
Hence, I am not sure what the right answer is, or how to get it?
Updated Answer:
Now for an R-type Opcode, I see
1-bit for a flag to specify if it is I or R format
12-bits to specify two registers
3-bits for the opcode
Now, I am seeing 8 different R opcodes because 2^3 = 8.
AI: Yes, 14 is right.
You have 8 I type codes, so you can have all I opcodes fit into 13 bits only.
That leaves 3 bits to determine if the opcode is I code or not. You can select one of the 8 bit patterns to indicate that the opcode is I code, which leaves 7 bit patterns for the R codes.
Since R code only needs 12 bits, you have one more bit to determine the R code, which doubles the 7 codes above to 14.
In other words, if 4 top bits define 16 codes, two of those must be reserved for I codes and 14 left for R codes.
|
H: Differential amplifier IC vs op amp with resistors to make it amplify a differential signal
What is the advantage of using a differential smplifier IC instead of using a normal op-amp and designing the resistor network around it?
The ICs seem to be more expensive and require more power.
The application I am looking at is to amplify the signal from a Wheatstone bridge, and I would like to minimise cost and power if possible.
Would it be advisable to use an instrumentation amplifier?
AI: Instrumentation amplifiers have better accuracy. Suppose you have taken four 10K resistors to make a differential amplifier (i.e. 1x gain). The last band of the color code represents tolerance. This means that the resistance may not be exactly 10k. It may be 10.001k or 10.015K. So, there might be a little difference between the values of the resistors. So, the output will not be 'Non Inverting input - Inverting Input'.
Secondly, the PCB trace has a significant amount of resistance. The trace resistance will also be added with the 10K resistors.
And during soldering, the connection will also have some unknown resistance.
So, it is quite impossible to make a precise differential amplifier by hand. I had to make an ADC converter for a thesis that contained 8 differential amplifiers (for some complicated gain equations). I used rail-to-rail op-amps. The PCB is good. But it doesn't work properly when the signal input is below 0.625 volts.
Instrumentation amplifier IC is made on a silicon wafer with highly precise resistance and less temperature sensitivity. So the output is more accurate.
|
H: YM3012 Analog Ground
I am trying to build a circuit using Yamaha Sound chip YM2151 with Yamaha DAC YM3012. This is my first attempt in doing anything with analog signals, so there is much to learn!
While reading a datasheet, I stumbled across the below schematic which shows Analog Ground.
Can someone please explain how it works? Why is there 10/15 V if my circuit required 5 V? How do I build this part of the circuit?
AI: I only found the 1992 data sheet so maybe yours is later but it did contain a schematic that helps.
I've superimposed your circuit (lower down) with an extract from the data sheet (higher up) and, on your circuit, I've corrected what appears to be a mistake (shown by the red dot): -
Why there is 10/15V if my circuit required 5V?
It's actually +/- 12 volts to put a number on it. You need to use an external dual supply for the op-amp circuits.
How do I build this part of the circuit?
Get hold of a DC-to-DC converter from the likes of TRACO (for instance) - they produce dual output types and 12 volts (as well as 10 volts and 15 volts) are standard parts. The input supply for the TRACO would nominally be 5 volts and attached to your 5 volt and digital ground.
While reading a datasheet I stumbled across below schematic which
shows Analog Ground. Can someone please explain how it works?
Analogue ground is connected to digital ground at just one point (the red circled point that seems to be omitted in your diagram). Any digital circuits in excess of the Yamaha chip will tee-off from that point - this prevents noisy digital currents influencing nice clean analogue currents on the analogue ground.
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H: Effective time constant of an RC circuit
I have read in some books that to determine the equivalent time constant of charging of a capacitor in any RC circuit containing either only one capacitor and any number of resistors arranged in any way or any number of capacitors arranged in any way and one resistor, we follow the follow the following steps:
1)Short circuit all the batteries.
2)In case of many resistors, the product of equivalent resistance across the capacitor and the capacitance of the capacitor will give the time constant of the circuit.
3)In case of many capacitors, the product of equivalent capacitance across the resistance and the resistance of the resistor will give the equivanent time constant.
I have given a lot of thought on this but I am not able to figure out why that method works. Can someone please help? Can't this method be somehow extended to the general case containing any number of capacitors and resistors?
AI: I have given a lot of thought on this but I am not able to figure out why that method works.
This is an application of the Thevenin theorem.
Step 2 is very straightforward. You're treating everything except the capacitor as a one-port network, and the capacitor as the load. Then you're following the usual method of finding the Thevenin resistance of the source network.
Step 3 is a bit less obvious, but you're actually doing the same thing. You treat everything except the resistor as a one-port source, zero the load, and find the equivalent impedance of the source.
If you're familiar with Laplace analysis, you know that capacitors can be treated as a kind of complex-valued resistor, aka an impedance or reactance (in this case, where the impedance will be purely imaginary). Understanding the Laplace analysis makes it much more clear why the two scenarios (several resistors and one capacitor or several capacitors and one resistor) can be treated in very similar ways.
Can't this method be somehow extended to the general case containing any number of capacitors and resistors?
In this case, you can pick out one capacitor and find a Thevenin equivalent source for the network driving it.
But the behavior won't necessarily be equivalent to a single resistor in series with this capacitor, allowing you to characterize the circuit with a single time constant.
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H: Limit current through Force Sensing Resistor
I am using an ICL7660 chip to provide a negative reference supply to an inverting op-amp set up for a Force Sensing Resistor (FSR).
The minimum resistance of the FSR is about 1kohm, this means that for an output voltage of 5V from the ICL7660, the maximum current through the FSR will be 5mA. However, according to the specs the maximum current permitted is 1mA/cm^2. For the FSR I am using, this means the maximum current permitted should be 246microA. How should I go about limiting the current? Thanks.
AI: For FSR resistors it’s best to limit current through it to below 1mA/cm^2 of applied force. Usually this is done with a pull-up or pull down resistor of sufficient resistance. For example if 5V source used with a 10kohm resistor in pull up configuration , current is limited to maximum of 500uA.
In your circuit which is a FSR current to voltage converter, you would set RG to minimum resistance value of FSR. Perhaps a little more if that FSR resistance goes quite low.
For example if your FSR ranges from 1M ohm to 4.7kohm (no pressure to full pressure) , and you apply force across 1cm^2 then you should set RG to 4.7k ohm. That way if -5V is used as reference and max output of op amp is 5V then max current would only be 5/4.7k ohm or 1.06mA.
Source: https://www.sparkfun.com/datasheets/Sensors/Pressure/fsrguide.pdf
EDIT: I’m going to add some additional information from my own experience with FSR.
If you have an FSR that goes to values of less than 1k when fully pressed then the above advice needs to be tweaked. Here you should add a series resistance to the FSR. Let’s call the sum of the minimum resistance of FSR and Radded= Rmin. You would then set RG=Rmin. But ensure that Vout or VREF (of op amp or reference voltage, assuming they are the same) will cause V/RG=V/Rmin is less than or equal to max current of FSR.
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H: What happens when a program needs to use more than the allotted 16 registers?
I'm just learning about how programs work under the hood of a computer. We discussed how registers are a limited resource to the CPU. So what happens when a program is massive and needs more than 16 registers? I've tried looking this up and couldn't find any answers regarding it.
AI: Programs aren’t giant, monolithic things. They’re broken up into smaller routines and tasks. As a result, there isn't a need to have a large number of variables in registers at the CPU's beck and call. It's just not efficient.
Instead, some tricks are used to make better use of the registers. One of the most important ones is the use of a special region set aside in system memory, called stack.
How does stack work?
When a program branches off to perform a sub task, some of the CPU registers will be saved to memory to free them up for the subtask, then restored once more when the subtask is done. This is most often done using stack memory, using special CPU stack opcodes that are designed to be fast and efficient.
How do stack opcodes work?
Stack accessed in a last-in, first-out fashion, by the special stack opcodes that ‘push’ or ‘pop’ groups of registers, called stack frames, onto or off of the stack RAM.
A register, called a stack pointer, is used to keep track of the top of the stack. On some CPUs it’s a special register; on others, any register can be used as a stack pointer.
The stack frame also includes other calling context, such as the program counter, status flags, and other vital information needed to restore the context when the subtask is done.
What implements the stack?
The details of managing registers and manipulating the stack via stack push/pop opcodes are dealt with by the compiler. In broad terms, the compiler looks at the subtask code, determines how many local variables the task needs, then inserts code to save (push) registers to stack memory, freeing them for the task to use. Likewise, when the task is done, another block of inserted code restores (pops) the registers from the stack.
Even within a task, the compiler will examine how variables are used, and determine when a variable is no longer needed and thus free up its register to be reused.
If, on the other hand, if the compiler can’t find any registers free, it will make a decision to punt some variables to memory (push them onto the stack, usually), only pulling them back into registers as they’re needed.
Here's a discussion that explains stacks pretty well. https://stackoverflow.com/questions/10057443/explain-the-concept-of-a-stack-frame-in-a-nutshell
As a programmer, having awareness of how the compiler uses the register, stack and main memory resources can help you to create better, faster code, even if you never look at a line of assembly.
What's in a name, anyway?
One such register-saving operation is called the stack exchange, where a register is swapped with the top of the stack. And, yes, that's where this website got its name.
What happens when you run out of stack RAM? Why, you get a stack overflow, which is, not at all coincidentally, the name of SE's programming-oriented sister site.
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H: Overloading buck regulator
I'm having a hard time explaining to myself why the output voltage of a buck regulator drops at the load when the load pulls more current than the max limit of the buck regulator.
Can someone help me understand this by assuming let's say I have a 3.3V buck regulator circuit that is rated for up to 2A. What happens to the buck topology components' voltages/currents when the load tries to pull 3A instead that causes the voltage output of regulator to drop?
Does same thing happen if I use a linear regulator instead, meaning output voltage drop during overloading?
Thanks,
Dan
AI: Does same thing happen if I use a linear regulator instead, meaning output voltage drop during overloading?
Everything drops in output voltage when the current gets too high. If it did not you would have a perpetual motion machine that produces energy from nothing.
Can someone help me understand this by assuming let's say I have a 3.3V buck regulator circuit that is rated for up to 2A. What happens to the buck topology components' voltages/currents when the load tries to pull 3A instead that causes the voltage output of regulator to drop?
Inductors saturate when the current gets too high and they stop doing their inductive thing
Transistor switches saturate and can't pass more current to the output.
Any and all resistances in the current path will produce increasing voltage drops as current increases to the point where they output voltage as dropped intolerably low.
The capacitor is too small to supply enough charge to "tide things over" for the frequency at which the converter is operating at; The frequency being how often that capacitor is topped up.
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H: How to reverse-engineer/find datasheet for an IC
I have an integrated circuit in the form as a DIN chip, and I have no clue what it is. I have tried searching for the markings on the chip, which are as follows:
Top:
HDJ2100-393
937GA1925463B2WW
Bottom:
TAIWAN
937GA1925463B2WW
It is a 40-pin chip.
I found two of these inside of an old CD mixer.
It is a Numark CD-MIX 1, and it was on what appeared to be the display system, as there were two near where the LCDs were. All I could find for a manual is the quickstart guide here, but I don't have the manual because it was basically in a giant bin of audio equipment.
Could someone tell me what this is or direct me on how to figure it out?
AI: More often than not, such ICs are custom made for a specific purpose. Their datasheets and other such information is usually private, and not publicly available.
I found a device which fits your description (called Inter-m CDC-2050), and which includes this IC. I couldn't find any datasheet for it, though.
https://www.manualslib.com/manual/972704/Inter-M-Cdc-2050.html#manual
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H: VHDL: Kan sequence of if/else be optimized?
I am new to VHDL and I try to find all places where I can replace if/else statements with cases of inlined OR/AND operations to get more things executed in parallel instead of sequence.
Now I have the following statement:
if (val = 0) then
returnVal := 0;
end if;
if (val > 0)
then
returnVal := 1;
end if;
returnVal := 2;
return returnVal;
As I can see, this will be executed sequentially with a depth of 3.
Is this exact statement possible to do in a more efficient manner?
NOTE: The values 0, 1 and 2 are not important - they must just be different, e.g. could be -123, 234 and 432 if that makes it easier for optimizing
Thanks
UPDATE: As pointed out, this logic was broken. The intended logic is:
if (val = 0) then
return 0;
end if;
if (val > 0)
then
return 1:
end if;
return 2;
UPDATE 2: I am programming VHDL and deploying to an FPGA which is important as it differs from microcontrollers in the terms of parallelism.
UPDATE 3: I realise, that I may not have been explicit about my exact question, so my apoligies. What I mean is: The three statements are mutually exclusive: Than value is either < 0, = 0 or > 0. And even though a case switch cant be used here, I was wondering if anyone had another input to how to improve performance of this.
AI: No need.
Write sequential code - and synth will unroll it all to execute in parallel anyway (but preserving the same semantics as your sequential version).
Some more detail here: https://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant/13956532#13956532
What you are defining with your sequential code is the semantics not the implementation.
That is : focus on the semantics of the problem - the highest level abstraction that accurately encapsulates your meaning. That's difficult enough to get right as the question demonstrates!
In that context, functions and procedures are good practice, raising the level of abstraction.
Now consider what happens to something even more sequential like a FOR loop in a process. Synthesis will unroll it so that each loop iteration runs in parallel anyway. Same happens here.
For completeness, in VHDL-2008, conditional and case expressions (when/else and with/select) are available within processes, so a shorter expression of your example is possible:
return (2 when val < 0 else 1 when val > 0 else 0); -- vhdl-2008 syntax
but the implementation will likely be identical.
As would a CASE statement based implementation of the identical algorithm (at least, where the expressions are mutually exclusive as here. An IF statement prioritises when expressions overlap : that would be a compile error in a CASE).
Both the implementation and the speed are likely to be identical. It's a different expression of exactly the same algorithm, and synth tools are brutal at reorganising and optimising; brutally honest in preserving semantics accurately, and brutally ruthless in exploiting mistakes to optimise away redundant hardware ( cough return 2;)
Which boils down to : TEST it first in simulation; THEN synthesise.
Given big enough, complex enough examples, unrolling a whole sequential algorithm and attempting to execute it in a single clock cycle is undesirable and consumes too much FPGA. But that's a story for another day; learn about pipelining and state machines before tackling that.
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H: How does this voltage adjustment circuit work?
This is a real-world application. My circuit 101 knowledge is not up to the task.
I cannot understand the purpose of the portion of the circuit highlighted in yellow. With the presence of diode D3 and D4, I can't see that R_10K ever gets utilized. The only scenario R_10K will have some current passing through it is when V@pointA < 0.7Vdc and V@pointB > -0.7Vdc, but that's an impossibility, you can't reconcile the currents flowing in R14 and R15. The circuit just seems impossible to operate. I must be missing something here.
In retrospect, judging from all the answers to this question, the place I was stuck upon was the notion that: Once D3 and D4 are conducting, they will short circuit R_10K.
In a real-world situation, a forward-biased diode is not a short circuit.
AI: R15 and R15 provide enough current to bias D3 and D4 "on" so that each has roughly 0.7V across it. So the 10K pot has about 1.4V across it and 140uA of current through it.
DR14 will have about (15V - 0.7V)/1.5K or about 9.5mA through it. That current, minus the 140uA in the pot flows through the diode D3. Similar reasoning for the negative branch of the circuit.
So the pot can set a voltage of anywhere from ~ +0.7V to -0.7V depending on the wiper position.
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H: What's the difference among these static protection bags?
I have some old modems & other cards stored in plastic static bags and noticed that a few of them were distinct... these are all from the 1990s or maybe early 2Ks.
Here's a sampling:
From left to right, there are:
Opaque and mirror-like
Translucent (this is what I thought of as "normal" and most the ones I have are like this)
Hexagonal pattern on less-shiny clear plastic
Grid pattern
Do the patterned ones have some special function? Do these all do the same job and equally well?
More detail on two:
PS: I can't really find any relevant tags... please suggest if you know.
AI: There are two types of anti-static bag: static-dissipative (pink, red, or occasionally black) and static-discharge (silver or grey).
Static-dissipative bags are designed to remove any static build-up that gradually builds up during shipping by transferring the charge to ground (i.e. what-ever the bag is touching). However, they are not designed to handle electrostatic discharge (e.g. sparks) since they are not good conductors of electricity. Measured with a multimeter one should be able to measure a resistance through this material; I measured about 10M Ω across 1 mm. I don't have one at hand to examine but I suspect that the cross-hatched bags1 fall into this category. The red/pink bags use tallow amine as the dissipative additive while the black ones use carbon.
Conductive static-discharge bags, on the other hand, are designed to deal with sudden static discharges. They work by having a conductive metal layer (typically aluminum) usually beneath a thin, protective, often static-dissipative plastic layer. They protect the parts inside from sudden sparks by passing the current to ground (whatever the bag is touching) through the bag (and thus not the components within) with very little resistance; I measured <0.1 Ω/mm.
A third anti-static device that you may encounter is anti-static foam. This is a black, spongy, rough, and fairly firm material. This material contains a large amount of carbon and has a moderately high resistance; I measured ~100k Ω/mm. It prevents static build-up during shipment/storage at the component level. Static-sensitive devices are placed with their metal pins touching or piercing the foam (they are typically overwrapped with a bag as well). The foam ensures that all pins on a component are at the same electrical potential 2.
Dave Jones at EEVblog did a nice series of tests (YouTube) on various types of bags; well worth a watch. For preservation purposes the silver conductive bags would be the best choice. Since we're on the topic, static-sensitive devices should not be stored loose in polyethylene containers since they are very prone to building up a static charge.
1 Conjecture: I suspect that the carbon material can be printed on the bags while tallow amine needs to be mixed in to the plastic. Using a cross-hatch pattern would be a cost-saving measure.
2 One manufacturer I know ships their boards in bubble wrap envelopes that are silver on the outside and pink on the inside. In this case the outer layer protects against sudden discharges (i.e. sparks) while the mildly-conductive inner layer keeps all pins/traces on the enclosed board at the same electrical potential.
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H: Cannot Find the Syntax Error Near Process
I'm very new to VHDL and this one must be a really easy question. The code gives me the error that there is a syntax error near the last process, please take a look:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fsm is
Port ( D : in STD_LOGIC_vector(1 downto 0);
CLK : in STD_LOGIC;
outLed : out STD_LOGIC);
end fsm;
architecture Behavioral of fsm is
type state_type is (s1,s2,s3,s4);
signal next_state, state: state_type;
begin
process(CLK)
begin
if rising_edge(CLK) then
state <= next_state;
end if;
end process;
outLed <= '1' when state = S1 and D = "01" else
'1' when state = S2 and (D = "01" or D = "10") else
'1' when state = S3 and (D="01" or D= "10") else
'1' when state = S4 and D="10" else
'0';
process(state, clk) begin
case state is
when S1 =>
if D= "01" then next_state <= S2;
else next_state <= S1; end if;
when S2 =>
if D="10" then next_state <= S1;
elsif D = "01" then next_state <= S3;
else next_state <= S2; end if;
when S3 =>
if D = "10" then next_state <= S2;
elsif D = "01" then next_state <= S4;
else next_state <= S3; end if;
when S4 =>
if D = "10" then next_state <= S3;
else next_State <= S4; end if;
when others =>
next_state <= S1;
end process;
end Behavioral;
Thank you.
AI: There needs to be an "end case" statement, before the "end process" statement. This is basic vhdl syntax. Despite writing a lot of VHDL over the years, I didn't know by looking at it. I just googled it.
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H: Extension cord to Power strip in old house
I live in a old house that has very old wiring. We got a small upgrade so we now have grounded outlets. I need to plug in a lot of devices into this outlet such as speakers, monitor and a gaming computer. So I bought the longest power strip I could find since I need to stretch it to my desk. But it is not long enough. My question is, is it dangerous to plug a power strip into a extension cord? In a old house that has old wiring and does not have many amps? Would I need a high rated extension cord?
AI: The extension cord and power strip must be rated for the total power you expect to use.
If you intend to plug in phone or notebook chargers (and even desktop computers) you'll probably run out of outlets long before you overload things (unless you use a very light-duty extension). Laser printers are fairly heavy loads (mine draws about 7 Amps when printing).
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H: How to apply if-else condition of inputs and display the output on 7 segment display on Proteus
I am fairly new at using Proteus. This is my second time using it. This is not a homework question. I am trying to figure out, if i have 7 doors leading to a vault and 2 are main doors, 5 are internal doors. if any of the doors is opened i will turn the LED to green. and display on the 7 segment display which door was opened. i know for a logic diagram i can simply OR all the inputs and attach an LED, but how would i display it on a 7segment display.
I just want an algorithm or any basic hint not details. just where to start. Thanks.
AI: Here are some comments
First of all, note your circuit is fully digital. From the open-close switches to the 7 segment (or any other) display.
Lights (c.XIX) The simplest solution is to feed every door into a single LED. Easy. Good for most users. Probably the best solution, before the world ends. And clear to show which door is the one opened. And how many doors are opened.
Gates (60') Lets assume you have just 4 doors. As you have realized, you can solve this purely with digital gates, such as the one you show. In this fashion this is a Standard Problem useful to exercise your skills (in this case, your proper domain of the Proteus simulator interface). All these are available in Proteus:
74HCT4002 Dual 4-input NOR Gate and
74HCT02 Quad 2-Input NOR Gate for the NOR gates,
74HCT20 Dual 4-input NAND Gate and
74HCT00 Quad 2-Input NAND Gate for the NOR gates, and
74HTC04 Hex Inverters, for converting the NOR and NAND in OR and NAND, if required, or 74HCT14 Hex Schmitt-Thriggered Inverters if in addition you need to compare small analog voltage levels.
74HCT126 Quadruple Bus Buffer Gate with Tristate Outputs, for some output control switching, and also for equalling the delay of an inverting gate, if required.
ICs (70') Now you have 7 doors, which means roughly 8 bits (obviously). This means nor 4 bit BCD, nor a 7 segment is enough for a 74HCT4511 BCD to 7 Segment Decoder. The easy way is to split the solution in 4 bit each, with two independent circuits. Now things are getting innecesarily cumbersome in the 70'. And also how to "encode" several doors opening at the same time. In here you are seriously thinking in going back in using simple LEDs (and you are right).
MCUs. You now figure it out. Finally, this is not the real way. If everything is digital, you should directly aim into a microprocessor (or something at the level), with 8 or more input and a way to integrate everything. There are really cheaper MCUs you can use which will discourage you to use any gate in the real life. But the gate way will give you an good skill on how to deal with digital concepts in a more analog fashion, how to work with delays, understand how the digital input output works, etc. Arduino or any similar platforms are the XXI century way to go.
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H: Generation of a shorter pulse based on trigger (similar to 555 as monostable)
I need to create a shorter pulse based on a trigger signal. Trigger signal has a duration between 1 to 10 ms and the desired output should be 0.5 ms.
To do the opposite (longer output pulse than input trigger) one can use a 555 as monostable (shown on the left) but what I need is the situation shown on the right. Is it possible to this with a 555 or with other monolitic IC?
Many thanks in advance!
AI: If I understand your application correctly you can use an edge-triggered monostable multivibrator, for example 74LVC1G123.
As shown in the TI datasheet, figure 2, it is possible to have an output pulse shorter than the input pulse:
If the timing jitter (delay from the input to output) isn't too critical, you could also consider using a tiny microcontroller.
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H: Cost reduction by eliminating vias from PCB design
I am designing a small (30mmX20mm) and not complicated two layer PCB. It is possible to do the design without using vias.
Is it possible to determine how much can I save approximately by eliminating vias from design?
Is it worth it?
AI: Basically, the cost breakdown for doing the drilling of vias and other through-holes is:
(1) setup time (putting the board on the machine)
(2) time on the machine
(3) removing the board from the machine
(4) (later) plate-through holes
Costs #1, 3, and 4 are the same regardless of the number of vias. Cost #2 does vary, not just with the number of vias, but how long it takes to drill them, and how often the bit needs changing.
So there is some benefit to reducing vias if you have to have them, and also keeping the hole sizes large enough that the bits don't wear out as quickly. But in the big picture, for a very simple board this won't matter much.
Also consider that if your board has a special shape or uses 'mouse bites' or other breakaways for panelization, that takes routing time on the same machine that does the drilling. This in fact will dominate time spent on the drilling table. Using v-scribe singulation avoids this.
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H: Why a PMOS active load is used for a NMOS common source amplifier?
let's consider this NMOS common source voltage amplifier with active load:
For small signals the PMOS transistor M2 acts as a resistor of value \$\frac1{g_{mP}}\$ (P stands for PMOS) and so the voltage gain of this amplifier will be:
G = \$-\frac{g_{mN}}{g_{mP}}\$
I have been told that in some IC it is not a good amplifier because it has a big sensitivity to temperature variations, since \$g_{mN}\$ and \$g_{mP}\$ change differently with temperature and so their variations are not balanced. It would be a better option to get a gain which are expressed as ratios of similar physical quantities.
So my question is: why not use always a NMOS transistor as active load? Something like this:
I'd say it will work exactly in the same manner. But I have always (or almost always) seen the amplifier with a pmos active load. Also in differential pairs, I have always seen only pmos active load for nmos amplifiers:
AI: diode-connected FETS unless very long channel will be high-GM, low-incremental resistance, causing low gain and high distortion.
Using the Pchannel as active-load may result in very high gain (depends on the channel length, so lambda-coefficient is not a bother) and low distortion.
In any case, long-channel FETs have higher channel-bulk capacity that has to be charged and discharged.
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H: SR Latch output pin biases state of the logic gate under special circumstance
I am having a really hard time putting my question in the right words, but I will try my best. So I am working with an MCU (EFM32TG11) that features a bootloader with pin activation. To make the process of booting into the bootloader as autonomous as possible, I thought of a circuit which can set a pin high that determines the boot procedure and remain it high when I perform a software reset. The circuit contains a section that triggers a one shot at power up to initialize the SR latch and the SR latch itself (constructed with two NOR gates) with pull downs on the input pins. Here is my circuit for reference:
Latching the BTL_SIGNAL, which is connected to the activation pin, works actually well by pulsing BTL_ENTER or BTL_EXIT with two other GPIO pins. Now the problem:
When the BTL_SINGAL is latched high and I perform the software reset on my MCU the BTL_SIGNAL falls to a LOW state and I have now idea why. I measured all the nets in the circuit but nothing unexpected occurred as far as I can judge. Disconnecting the transistor from the BTL_EXIT signal did not help. What actually helped was using one of the OPAMPs from an LM358 I had laying around in buffer configuration. I can live with that solution, but I was just curios why this happens... another piece of information: When booted into the application the BTL_SIGNAL pin is actively disabled, when booted into the bootloader it is set to input without pull resistors.
AI: Ok, so after the answer from @Bill I went back and tried and it did not work and then I tried all sorts kind of things ... and I finally found the problem.
So for everyone who plans to work with a similar setup and the Gecko xmodem bootloader on a 32bit SiLabs MCU (EFR32 or EFM32) watch out: In the GPIO activation part of the bootlaoder the input pin quickly gets reconfigured as output and is actively driven hogh/low for a very short amount of time to charge or discharge decoupling caps depending on the configuration whether a low or high pin state activates the bootloader! This did not appear to me before because I was not using some kind of logic gate to latch the state... but rather a simple slide switch.
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H: Additional Voltage on I2C Bus
I have redesigned one of my boards to the ICM-20689 (datasheet) instead of the ICM-20789 because of a voltage issue that I previously had. Link to previous issue.
A little background on my setup. The ICM-20689 is running on 3.3V with 3.3V on the VDDIO pin and 10k pullup resistors on the I2C bus. The master device is running at 5V, but only needs 60% (3V) to read a voltage high. The frequency is set to 400kHz.
I have been able to communicate with the device just fine and get good data. I wanted to look at the bus voltages with an oscilloscope to make sure that everything looked fine, and I noticed something a little odd. Before the master starts talking with the ICM-20689, the bus line is at a voltage of 3.3V. When the master wakes up the device and starts receiving data, the voltage jumps to 3.7V.
My oscilloscope is not the greatest, but the probe is in 10x mode, and I am using the trigger to capture the data on the first packet of data sent. On all subsequent data packages, the voltage stays at 3.7V. Is this is an issue with the device, or is this maybe an issue with my measurement setup?
Edit: Here is the schematic for the ICM-20689. This "voltage bump" happens on both the SCL and SDA lines. To my knowledge, there are no internal pull-ups active on any devices on the bus.
Is this normal for I2C? What is causing this bump? Is this something I should be worried about, or is this within allowable tolerances?
AI: In the comments you say that you are using an ATmega32U4 with the standard Arduino Wire library. Pullup resistor value for that MCU is specified as 20 - 50k Ω. A value of ~32k would cause the voltage you are seeing.
In twi.c we see:-
void twi_init(void)
{
...
// activate internal pullups for twi.
digitalWrite(SDA, 1);
digitalWrite(SCL, 1);
To disable the internal pullups you could comment out those lines in the library code. However then you may have problems with the voltage being too low for reliable operation (ATmega32U4 specifies minimum high level of 0.7 * Vcc, which is 3.5 V at Vcc = 5 V). The proper solution is to use an I2C level shifter circuit like this:-
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H: Why is vivado so wasteful with its D-flipflop placement?
I have an implemented project in vivado, and I'm looking at the resultant layout between 8 slices:
As you can see, all 8 slices except one only have a single D-flipflop. This seems awfully wasteful. Why not put all of these flip-flops on two slices?
AI: Has the placer violated space constraints? No.
Has the router violated timings constraints? Probably not, if it finished successfully.
In which case you have a good design.
If you reduced the size of chip available to it, you'd find it would put more latches per slice.
If you tightened the timing constraints, you might find that if local routing resources were faster than inter-slice, that it would place latches on the same slice.
Lots of things have to be optimised by a placer/router. Amongst them is fast access to I/O pins, and heat generation, both of which would favour a spread such as you've shown.
Unless you've had several iterations around the constraints, you're not going to get the fastest possible, or the tightest area layout. When it's met constraints, the placer/router usually stops.
It's not obvious when we first write constraints for an automatic tool just how it's going to satisfy those. I frequently find myself thinking 'Oh, I didn't mean that, but I suppose that's exactly what I asked for' when doing this sort of thing.
There's a quite fun AI example where the system is given a bipedal walker, and asked to optimise its speed from start point to finish point across some difficult terrain. One solution it came up with was to give the walker very long legs, and have it fall over at the start. It was so tall it reached the finish.
Consider another optimisation problem. Manufacturer A wants to optimise his tools, so that me, the user, chooses them over manufacturer B. What makes a good placer/router, once meeting constraints has been achieved? A FAST placer router wins. If I use 90% of the resources, then I expect the tool to struggle, but if use 10%, I expect it to fly through. Why would the tool designers have it put all the latches in one slice, and then struggle to optimise the constrained local routing, when this initial placement is guarranteed to route easily?
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H: What will gain be when both the zener diodes are conducting?
I have seen in solution that they have considered both 10k and 20k to be parallel when both the diodes are conducting. How will 10k and 20k be in parallel when zener diodes are conducting? Why are we not considering the drop across zener diode when both diodes are conducting?
AI: We do consider the effect of the diodes.
The red line shows what the transfer function should look like.
The blue line shows what the transfer function would look like if the Zener diodes were considered conducting, but you ignored the diode drops.
The green line shows the transfer function if the Zener diodes are assumed conducting (even in regions where they aren't) and you include the diode drops.
Since the slope of the green and blue lines are the same, you can use the parallel combination of the two resistors to find the slope of the transfer function in the case where the diodes are active.
You then have to make a separate calculation to find the offset, and this takes account of the diode drops.
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H: Why will i calculate the wrong power ,but right loading resistance in this circuit?
The question wants me to calculate that what is the \$R_L\$ value when we have the maximum \$P_{R_L}\$ from this circuit
simulate this circuit – Schematic created using CircuitLab
My thinking
When we are calculating the equivalent resistance,we can see the original circuit as the circuit in the left hand below ,and the left hand circuit is equal to the right hand circuit,by the way,\$R_{10}=R_1//R_3,\$ and \$R_{12}=R_2//R_4,\$
simulate this circuit
So according to \$P_{R_L}=I^2 R_L=(\frac{60}{2.1+R_L+0.9})^2R_L=\frac{60^2}{(3+R_L)^2}R_L\$,and use the Maximum Power Transfer Theorem,we can know \$R_L=3Ω\$, we can have the maximum \$P_{R_L}\$ from this circuit.
So now we can know the voltage of \$a\$ point,\$V_a\$, and the voltage of \$b\$ point,\$V_b\$ is as below
\$V_a=60\frac{3+0.9}{2.1+3+0.9}=39V\$
\$V_b=60\frac{0.9}{2.1+3+0.9}=9V\$
So the voltage of the loading resistor is \$39-9=30\$,so the \$P_{R_L}=\frac{V^2}{R_L}=\frac{30^2}{3}=300W \$
However,the answer shows me
Answer:
simulate this circuit
The \$V_{th}=60\frac{3}{7+3}-60\frac{1}{9+1}=12\$,and \$R_{th}=(7//3)+(9//1)=3 \$ ,so \$P_{R_L}=\frac{V^2}{4R_{th}}=12\$
I found that the main difference between solution and my thinking is that our \$V_{th}\$ are not the same ,my \$V_{th}\$ is the voltage of the loading resistor=30V,but solution's is \$12V\$ ,Why can't the voltage of loading resistor be calculated as i think??where am i wrong?
AI: You correctly found the Thevenin resistance of 3 ohm but then it went wrong when you assumed all the resistors were in series with 60 volts. The 3 ohms calculated is also the load you need to apply between A and B to get maximum power transfer too.
Why can't the voltage of loading resistor be calculated as i
think??where am i wrong?
Consider that this can be solved by "splitting the voltage source" covered in E5 is this short document: -
And that circuit becomes the one below when you convert the potential dividers on each supply and, calculate the new voltage source value for each side: -
So, the difference voltage between the two sources is 12 volts and it is this 12 volts that drives current through the 3 ohm resistor connected across A and B. So, that's: -
$$I = \dfrac{12\text{ volts}}{2.1 + 3 + 0.9} = 2 \text{ amps}$$
So the maximum power into the Thevenin resistance of 3 ohms is 12 watts.
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H: What happens when DC is applied to a piezo crystal?
I've heard that when an alternating current is passed through a piezo crystal it vibrates. But what happens if a direct current is passed through the crystal? I'm assuming depending on the direction of the DC applied the crystal either compresses or expands. Am I right? I'm interested in compressing a cuboidal shaped piezo crystal. How do I do it with DC. I haven't bought a crystal yet so I would like to know theoretically what direction of DC will cause the crystal to compress or expand?
AI: How do I do it with DC
For a very short period of time is the short answer.
Longer answer - a piezo is basically a capacitor in terms of equivalent circuit and, to push a constant current through that capacitor requires a ramp voltage applied to the terminals. This follows from the basic capacitance equation: -
$$ I = C\dfrac{dv}{dt}$$
In other words, to keep current at a constant value dv/dt needs to be constant and that means a voltage waveform that is a ramp. Pretty soon you will have raised the ramping voltage so high that you have thousands of volts across the piezo and it's going to breakdown due to over-stress voltage.
so I would like to know theoretically what direction of DC will cause
the crystal to compress or expand?
Assuming you can overcome the above difficulty by only applying the ramp for a short period of time, the data sheet for the piezo will tell you the answer.
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H: How can I protect a MOSFET bi-directional switch
I need to protect a MOSFET bi-directional switch made with 2 of IRF540 (VDS 100V) against potentially over-voltages on inductive loads.
Because isolator is slow (say ~1mS), I am concerning about the moment when SW just opens or closes into inductive load (a motor).
The plan is to put some uni-directional TVS across mosfets with VBR < VDSS.
Should be bi-directional (because load can generate negative spikes)?
Should I connect the common? My guess is yes because in case of a event, I don't want to let the 2'nd mosfet to handle that too.
Any comments really appreciated!
AI: Should I connect the common? My guess is yes because in case of a
event
You don't need to connect to common because one of the MOSFETs will be reversed biased and its body diode will be therefore forward biased.
Because isolator is slow (say ~1mS), I am concerning about the moment
when SW just opens or closes into inductive load (a motor)
Well, when activating, one of the MOSFETs is going to be vulnerable and the other will conduct through its body diode and be less of a problem but you do need to check that the body diode can handle the same current as the load when passing through the off-to-on situation.
By the looks of it the IRF540 is going to be OK in that respect.
But generally, and putting numbers on it, if the load is 20 amps and this activates in 1 ms linearly, the voltage will fall from (say) 50 volts to 0 volts and the peak power will be about halfway i.e. 10 amps and 25 volts = 250 watts. You could use a simulator to get a more precise figure (and I recommend that you do) but, a short estimate is 250 watts for 1 ms.
Looking at figure 8 in the data sheet suggests that it will be OK at these levels but you have to put real numbers onto this graph that represent the true operating conditions (and not just my guesstimates): -
The plan is to put some uni-directional TVS across mosfets with VBR <
VDSS
The TVS would need to be quite beafy in order to handle the back emf at the current being taken by the inductive load when it is disconnected. This might be 10 amps (for instance) and the energy stored in the inductive load might keep pushing that current into the TVS for a few tens of milliseconds. If the TVS voltage was 70 volts, that's a power of 700 watts sustained for several tens of milli seconds.
I'd probably consider one of these: -
It has a stand-off voltage of 60 volts at 2 uA (only you can decide if this is sufficient) and it clamps at 96.8 volts with a peak current of 52.7 amps. If you draw a line between 60 volts and 96.8 volts and moved along that line a linear proportion of the current you will need (possibly 10 amps) compared to 52.7 amps, you can estimate that at 10 amps, the TVS will clamp around 67 volts.
Again, these are my numbers and you need to use your own. Anyway, that's a peak power of 670 watts and well within the 5 kW rating but the next graph will help you understand how long it will survive: -
As you should be able to see, a 10 ms pulse of nearly 2 kW is on the limit so, providing your pulse isn't much in excess of 10 ms you should be OK. But you can parallel devices providing you used worst case limits but I would recommend using a simulator for this. I designed a triple-parallel TVS surge suppressor like this.
Do not use MOV devices as an alternative - the MOV will be called into action for each on-off cycle of the load and MOVs/varistors only have a limited number of surge cycles before they fail short-circuit. A TVS (of the appropriate voltage rating) is, more than likely, the most reliable solution but choose with care and choose a beafy one.
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H: What is ADC Supply Current in Microcontroller and how much current will a GPIO take
I am having this Microcontroller
In this Microcontroller, I am using the ADC peripheral and normal GPIO port.
My questions:
On Page 58, table 42, There is a parameter called as Supply Current per ADC which is mentioned as 1mA. What does it mean? It also mentions that it depends on the conversion rate.
Does it mean, if I connect a voltage (within the mentioned limits of the pin) with a series resistor to that ADC pin, that pin will consume 1mA?
So, if I connect two ADC inputs to the ADC peripheral, it will consume 2mA?
Suppose, I configure a port as Input port. How much maximum current will the Microcontroller pin draw?
Injection current will come only when I impress a voltage above that the supply voltage of the GPIO. And Leakage current, will come into picture only when the device is operating in low power state or shutdown.
So, If I donot use the microcontroller in the above two conditions, (applying voltage to the pin within limits and in normal working mode), how much will the microcontroller pin take for a normal GPI input?
This Microcontroll has two supplies. ADC Reference supply high and ADC Reference supply low? Usually, I have seen only ADC reference supply as a single reference supply pin. But here, there is reference high and reference low? Any idea on why is this implemented and any use case of it?
AI: 1) It means the current consumption of the ADC circuit within the IC, not from the input pin. Each ADC that you enable consumes 1 mA from the IC power supply.
2) That is the leakage current. 0.5 µA max., in or out. But if you use the ADC to sample a voltage, it gulps current in to charge its sample-hold capacitor.
3) It is implemented to enable the user to select both Vref- and Vref+ for the ADC. Users might want full-scale readings between 0.5 V and 2.8 V instead of between 0 V and 3.3 V.
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H: Is microcontroller power consumption directly related to its operation time?
I have to decide on a way to measure the efficiency of an algorithm running on a microcontroller/microprocessor.
My thought is that I can use the runtime of the algorithm to complete a certain task as an indirect measure of how the power consumption of that algorithm compares to another algorithm's power consumption. This would only make sense though, if the time spent in operation of the microcontroller was directly related to its power consumption. Is this assumption true?
The microcontroller runs under the exact same conditions with each algorithm, same peripherals etc.
AI: There are many things that alter the power consumption of the device, but assuming your just computing an algorithm with all unused peripherals switching off, e.g. ADC (pulsing current each sample), GPIO (changing state consumes a small amount of current), watchdog circuit disabled (runs a clock and triggers an interrupt),
Then yes, the longer something takes to compute, the more power it has consumed, there is a trade off between clock speed and total power consumption (for most devices running at the highest clock speed for the shortest time uses less energy than a slower clock for a longer time) however again assuming that all stays the same, longer time = more power
If you want to start including other peripherals, towards the bottom of the datasheet for your device you will find chart after chart after chart outlining what the power consumption is for your particular use case, and various other relations, e.g. if you have the pin pullup left on, how long your switching that pin low increases consumption, if your driving something else in the signal, it will consume something in both high and low states, if your using ADC's, then the input buffers will have a non linear current draw depending on the input voltage. (usually you would disable them)
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H: Finding delay in a cosine signal
Is there a delay (or phase shift ) in the following cosine signal?
If yes, how to find delay in a signal? Will appreciate your help! Thanks!
AI: Cosine is sine but shifted in time 1/4 cycle. Your signal is a sum of at least 2 sinusoidal signals with different frequencies. Fourier transform can help to decide the frequencies, amplitudes and phase angles but if you have only this short sample the result is very inaccurate.
ADD due the edit in the question
The questioner has added that he knows there's 2 frequency components. He knows the frequencies and amplitudes, only phases (or delays as he says) are unknown. This starts to sound homework, so no ready to use answer is given.
You can find the phase angles with QI-mixing. That's the general technique to present a sine as sum of orthogonal vector components; essential in data communication. That mixing is actually equal with calculating one frequency component of the Fourier transform.
Or you can force Excel solver to fit the phase angles to the time series.
I guessed by watching your image and formula (fixed to form X(n)=0.5*cos(2n*pi*3/200 + q) + 1.5*cos(2n*pi*7/200 + q) that the number q is zero. But there's only the image accuracy available.
Plotting that guess in Excel gave this:
When scaled your plot to the same size and placed together in Photoshop for comparison I can say that q=0 is as good guess as the screen resolution makes possible.
Numeric data would give more accuracy.
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H: Designing a Buck Boost Regulator 12V Circuit
I have been trying to source a Buck/Boost IC to design a circuit for my needs but I'm having a little trouble understanding how I would do this.
I am currently designing a circuit that will provide a regulated 12V output (around 3A max) from either a 12V battery or 12V DC input.
My go-to would be an adjustable linear voltage regulator, but these can only step down to voltage levels that are less than the voltage input (dependant on the dropout voltage of the regulator). As battery voltages will decrease over time (approx 12.65V to 11.9V) the linear regulator would not suffice (Not to mention that 12.65V is within the voltage dropout range of the linear voltage regulator when it is set to output 12V).
I could decrease/increase the input voltage and combine that with a boost or buck/linear regulator to achieve a 12V output but I would prefer to keep the input as 12V.
I found this post (Stabilize 12V to 12V) which recommends a Buck-Boost Converter. This seems like it would work for my application.
I've had a look on RS components through some datasheets but the typical circuit applications either show the IC in Buck or Boost configuration and not as a Buck-Boost. (Example TI MC33063AP)
Therefore, I was just wondering if there were some pointers on how to construct a suitable circuit for this application. For example, some ICs seem to mention PWM control, I assume this would mean I need to include something like a 555 IC to control the buck/boost functionality?
There also seems to be a lot of terminology for Buck-boost (Buck boost switching regulators, Buck boost controllers, Synchronous buck boost etc..) is there a particular type that would be best suited to this application?
AI: I could decrease/increase the input voltage and combine that with a
boost or buck/linear regulator to achieve a 12V output but I would
prefer to keep the input as 12V.
Well, that's what a buck-boost regulator does so, when you say this in the next paragraph...
I found this post (Stabilize 12V to 12V) which recommends a Buck-Boost
Converter. This seems like it would work for my application.
You are inadvertently forming a contradiction (no problem, just saying).
I've had a look on RS components through some datasheets but the
typical circuit applications either show the IC in Buck or Boost
configuration and not as a Buck-Boost.
Well, they do have a section called buck boost: -
Try this link to the above page and note that top of the list is the MC34063 (similar part number to what you referred to) and might be very similar but make by ON semiconductor rather than TI but, do read the data sheets carefully.
For example, some ICs seem to mention PWM control, I assume this would
mean I need to include something like a 555 IC to control the
buck/boost functionality?
No, that won't be needed - buck-boost chips will have this built inside for controlling the transistors associated with the circuitry.
is there a particular type that would be best suited to this
application?
Generally I don't use RS or FEC to search for what I want, I got direct to TI or AD and use there search engines. For example this one by AD (Analog Devices): -
Press "search" and it comes up with 13 options: -
I browsed down that list and half-heartedly chose the device that appeared to use the fewest components: -
But I could have gone to choose a device that used internal transistors (if there were one that would do 3 amps) and find just one suitable device: -
If you need any more help choosing just say.
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H: How to turn on an LED when voltage drops to low?
I have an old vehicle from the 70's and it has a gauge for oil pressure. I want to add a 12v LED to the dash that will light up when the oil pressure is too low.
The installed sensor on the engine is restive to ground. The resistance changes as the oil pressure changes (more pressure = less resistance), thus changing the reading on the dash gauge. I want my warning light to be connected to this same sensor.
Note, although vehicle is 12 V, it has a factory "constant voltage unit" that provides the gauges with 5 V. I will be replacing this with a simple 5 V regulator (eg LM7805). So gauge circuit will be... +12v----LM7805----Gauge----Sensor----Ground. The circuit for the LED indicator would connect between the gauge and sensor.
In the past, I've been able to accomplish this with an Arduino and some code, but don't want to use an MCU in this application. However, I can't seem to figure out how to do this with a simple discreet component design.
Thanks!
AI: An Arduino, at a cost of under $5, is an excellent solution.
This circuit should work, but values will depend somewhat on the oil pressure sensor resistance.
Reducing sensor voltage below a certain level will turn on Q1 and so LED1.
R2 can be adjusted to vary the turn on level.
The circuit can be improved if of interest.
simulate this circuit – Schematic created using CircuitLab
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H: Calculate op-amp input voltage with potential divider and series resistor
I have managed to confuse myself when it comes to calculating the voltage drop over a series resistor connected to a potential divider (See below):
The op amp non-inverting input is connected to a 20K resistor which is then connected to the output of a voltage divider (Top resistor is 56K, bottom is 7K). The input voltage to the potential divider is 12V.
I would like to calculate the voltage "seen" by the op amp (set as a voltage buffer) on its non-inverting input (in this case pin 3).
The input resistance for an ideal op amp should be infinite, however in practise there is a very minute input leakage current. This gives me the following questions:
1) Is the resistance "seen" on the potential divider output branch, equal to the sum of the op amp input resistance and 20k resistor? Or would it be equal to the equivalent parallel resistance of 7k||20k+op amp input resistance?
2) As the input resistance of the comparator is very high, (and I don't have specific values for it) could I somehow calculate the potential divider output voltage drops over the 20k resistor and op amp without calculating current draw?
3) Related to the previous questions, can I "split" the problem into two parts? i.e Calculate the potential divider output voltage and then calculate the voltage drop over the 20k resistor and op amp?
4) Would an equivalent circuit without the op amp (i.e 20k resistor is left floating on one side) help me calculate the voltage drop over the 20k resistor?
Thank you for your help- I've been driving myself mad for days with this problem...
AI: The resistance is "seen", but its effect is so small that unless you're working in precision circuitry you will not be able to measure it. (the op amp input is really high impedance)
You can refer to the bias input current if you want to know the voltage drop as this will dominate that input resistance in most op amps, e.g. 5pA * 20K = 100nV,
As the effect is about 7 significant figures away from the the divider voltage, in this case your safe to ignore it, if you had say 1 Giga-ohm resistors for your divider then it would be a different story (noise dominates there, but the DC value would be affected)
refer to the input bias currents if you want the 20K drop, it will dominate the input impedance.
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H: What is the voltage on CD4017 outputs?
What is the voltage of "high" signal on "out" pins? Do I understand it correctly, that it is dependent only on provided Vdd and it is a little (approx. 0.5 V) lower than Vdd?
AI: CD4017 is a CMOS device, and as such, the output high voltage will be essentially the rail voltage when the output is sourcing no current.
The output impedance is essentially resistive for small output currents, and the voltage drop with respect to the rail will be more or less linear with current. The datasheet specifies the minimum output current when you have a drop of 500 mV, at least for rail voltages of 5 V and 10 V.
Although it has graphs of output current versus output voltage drop all the way down to the other rail, these should be regarded as transient figures, useful for seeing how fast a capacitance will be charged by the output, rather than as recommendations for what continuous current can be drawn.
The datasheet will have a graph of voltage drop versus output current.
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H: When is a wire considered high-Z?
I need to make sure I understand perfectly the high-Z state and its relation to voltage.I intend to explain what I have understood based on three example, is there something wrong ?
Let's consider the three following examples :
If the LED is red, the point 1 will approximatively be at 1.3 V because the voltage drop across a RED LED is approximatively 2 V.
Point 4 is at high-Z so we do not know its voltage. Can we assume it is near 1.3 V, or can it really be anything ? If I measure it with a voltmeter I would get around 1.3 V, but it is because the voltmeter is injecting a small current resulting in measuring the LED's resistor value ?
Point 3 is at high-Z as well. But is point 2 considered at high-Z ? It is not really an unconnected wire as it is connected to a resistor. More generally, if we replace the resistor with any other passive component, would 2 be at high-Z or no ?
AI: Think at an Hi-Z wire in this way: can I connect its lead to any (reasonable) point in the circuit without having current flowing in the wire?
If yes, then the other lead of the wire is connected to a Hi-Z point of the circuit. A Hi-Z point is one connected to a very high resistance so no current can flow.
In your schematic NO wire (neither of 1,2,3,4) is Hi-Z because if you connect one of them to GND, current starts flowing and the LED lights up.
UPDATE: Wire number 3 can actually be Hi-Z, provided that the resistor attached to it has a very high ohmic value.
Hi-Z is used for example in microcontrollers when they start-up. Given that any I/O pin can be connected to anything, and at the start time the microcontroller does not even know whether a certain own I/O pin is (will be configured as) an input or an output, those I/O are Hi-Z: you can pull them low or high, you can attach them to an input of some other IC, but nothing happens, they seem to be connected nowhere and no current can flow.
Another example where Hi-Z is desirable is in scope probes: a scope probe should be Hi-Z (as much as possible) in order to not pollute (or worse) the signal you are trying to measure.
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H: Using too many Modules in Verilog affect timing?
I have a straightforward quest about HDL and FPGA design.
If I seperate my code to a lot of modules, by modules I mean verilog files which do specifig things instead of writing close to the top module, does it affect clk timing?
Ill try to illustrate my question:
the first option the I write most of my code in 1 file (not a top file, I know I shouldnt write logic on the top):
the second option that I going deep with my modules, instead of write lot of code in 1 file, I will have seperate hdl files that does some functionality and bring back upstair the answers, something like this:
does it affect timings of the clock/reset etc?
does it good design to write lot of modules and going deep with the modules or I should stay close the the top?
In my opinion, I using Lattice FPGA and I "Share Resources" option in the syntesis, and than, its doesnt matter.
AI: No, it doesn't affect the timing or final netlist. If you take a signal from the top level and assign it to successive modules, the compiler will recognise this is the same signal. Modules are there to allow you to:
Group functionality into logical blocks.
Reuse common designs.
Keep design elements at a size you, as a human, can keep track of.
I try to have only assignments and very simple logic (e.g. ORing the output of two modules) at the top level. This keeps the namespace clean, and allows easy traversal of the hierarchy in the simulator.
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H: Help deriving the transfer function of an LC circuit?
I have the LC circuit below. I believe (but I'm not certain) that this is a 3rd order filter. Since there are two capacitors and 1 inductor.
The circuit is a passive low pass pi filter. The component values have been chosen so that the cutoff frequency is 15kHz. The input is from a signal generator with a source impedance of 50ohms (the resistor shown).
I need to derive a transfer function for the circuit but I'm not sure how, since I don't know the order of the system. The Bode plots of the system are below:
Can anyone help me derive the transfer function of the system using these Bode plots?
AI: If you do the algebra (it's amazing what folk will do in lock-down of course) you get the following transfer function: -
$$H(s) = \dfrac{1}{s^3LC_1C_2R + s^2LC_2 + sR(C_1+C_2) + 1}$$
And just to demonstrate that is correct I used micro-cap 12 and the following circuit: -
Inside the red box is the input AC voltage that can be swept from low to high frequencies. To the left of that is the conventional circuit formed by R, L, C1 and C2.
To the right we have micro-caps 12's Laplace function solver. Both circuits are fed from V1 (red box).
Comparing both bode plots we get identical overlapping results: -
If this helps then that's good. If you require the derivation of the above TF then ask. I don't suppose it hurts to post my reasonably legible hand calcs: -
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H: Why will i calculate the wrong current when i transform part of circuit to Thevenin circuit?
Here is the circuit in this question
The original circuit is in the left hand side,as we can see,there are two norton circuits in it,so i transform them to the thevenin equivalent circuit,just like the circuit in the right hand side.
Now i can use the KVL to calculate the \$i\$ value
KVL:\$-12=4i+4i+24+4i+12,\$ so \$-48=12i\$,i can know \$i=-4\$
However,the answer for the \$i\$ is \$2\$, i want to ask why?can anyone tell me the reason that why will calculate the wrong answer?
The solution:
\$i_1=\frac{-12-(-24)-(-12)}{4+4+4}=2\$
AI: i can know i=−4
That is totally correct and this means that current passing through R3 (aka R6) is 4 amps. Note that R3 didn't transform into R6; it is R6.
The problem arises when you then assume that that current also flows through R1 in the original circuit. R1 has been transformed into R4 and moved position (but R3 or R6 hasn't) hence, the 4 amps is valid for R3 or R6 but not valid for R1 in the original position it took.
But you are one step away from realizing the proper answer is 2 amps: -
If 6 amps flows from I1 and 4 amps flow into R3 then 2 amps MUST flow into R1.
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H: LED Driver Output - Current Adjustment Range
I bought this Led Driver(HLG-480H-48A) for my Strips that use around 43V 9A. I've never used a LED driver before and have got a few questions about them:
The output current adjustment range (according to datasheet) is from 5-10A. Does that mean that the driver "pushes" 5A minimum through the circuit?
If I connect a LED strip that uses same voltage but only 3A what will happen?
I want to connect 3 strips(total I=9A), all in parallel to the same driver. What will happen if one of them has a short-circuit/fault? Will the other ones get damaged as well or should I independently fuse them with a fast acting 3A fuse?
Thank you for your time.
AI: 1) The driver "pushes" as much current through the load (the LEDs) as what you have set, if you set it to 5 A that current will be 5 A.
However the driver only supports a voltage of around 48 V (actually that's adjustable between 40.8 V and 50.4 V). So with the LEDs connected and the current set to 5 A, the voltage across the LEDs must be less than 48 V.
Suppose you connected LEDs that need 60 V when 5 A is flowing through them. This driver cannot support that, you would get the maximum voltage of 48 V and the current would have a very low value (how much depends on the LEDs).
2) The LEDs are rated for 3 A then you must use a driver that outputs 3 A or less. This driver outputs 5 A, which is much more than 3 A. The LEDs will be overdriven, get too hot and will die very soon. Just don't do this. Underdriving (using a lower current than the LEDs need) is always OK, overdriving is not.
3) Connecting 3 x 3 A LED strips for 9 A and using a 9 A driver will work but is risky.
When one LED fails open: the other strips get 9 A / 2 = 4.5 A and are overdriven. They will soon fail as well.
When one LED fails short: then the other LEDs in that string will take most of the current and will be overdriven. This will make that strip fail sooner. When one of those LEDs then fails open, see above what happens.
It is really a much better idea to use 3 separate 3 A drivers.
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H: How to detect an unconnected LED with an ADC?
Let's consider the following simple example :
An MCU controls the lighting of an LED with the wire "CMD_LED" by switching the state of an NMOS transistor.
When CMD_LED = 1, the transistor is closed and the LED is lighted.
When CMD_LED = 0, the transistor is opened an the LED is off.
The red rectangle can be connected or unconnected from the circuit.
I want to detect an unconnected LED. To do so I have to use an ADC input of the MCU to measure a specific voltage. I cannot measure the voltage inside the red rectangle.
Is it possible to detect that the LED is unconnected, based on this method ? If so where should I measure the voltage ?
I don't know how the MCU can distinguish between the unconnected LED and the open transistor...
Thanks for you help. :)
AI: A long time ago for a product, I worked out this issue by using a current mirror. Basically, I used a matched NPN pair wired up as a mirror and sent a very small (tens of microamps) current to the LED, not enough to light it. The mirror output swung enough voltage that it could read it with a GPIO. Once my diags were done I turned off the current mirror so even the phantom sense wasn’t present. Why did I go to so much trouble? I was very short on GPIOs and needed to resort to some tricks to reuse them.
The ADC can measure the FET drain voltage with the FET ‘off’, with a bit of work. First, toggle the FET 'on' then 'off' to discharge the drain and trace capacitance, then quickly sense the drain voltage afterward. The voltage will stay at 0 if the LED is unconnected, or drift up towards Vcc with the LED present as the LED leakage bleeds off charge.
That said, the ADC sensing method poses a couple of difficulties: ADC input range (which needs to include Vcc), and ADC input impedance loading the circuit when the driver FET is 'off'. Either one will prevent proper sensing of the FET drain charge.
What to do then? Forget the ADC. There's an easier way.
Use an nFET to watch the driver drain voltage. Just like with the ADC method: pulse the driver 'on' then check the FET state shortly afterward. If the sense FET stays off, no LED; if it turns on, LED is connected. Try it, here:
simulate this circuit – Schematic created using CircuitLab
This circuit takes advantage of the fact that there's a bit of capacitance present on the driver FET drain and the board trace. The sensing nFET doesn't load this, and so can detect the driver drain off-state charge with the LED present or absent.
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H: AC behavior of a capacitor
While under DC current capacitors cause open circuit as time goes to infinity but under AC current they flow through capacitor. As I know Maxwell described this behavior as "Aether current". Is this current under AC source actually caused by microwaves or how is it possible for current to pass through it and how AC current can pass while DC can't?
AI: The current does not actually "pass through." Charge flowing into one terminal of a capacitor accumulates and forces charge to flow out the other terminal of a capacitor causing that side to have a deficit of charge. In effect, that is current, but the current stops when the capacitor is charged to a voltage that equals the source voltage. When the source voltage reverses, the accumulated charge reverses direction of flow. With AC current, the process in continuous.
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H: Avoiding ground loops with common-ground DAQ
I am looking to acquire data from several sensors on a machine, each of which are part of a control system featuring several grounds linked at a single central point. I need each sensor's signal at the point of measurement compared to its own ground at that point, while avoiding ground loop issues caused by the common ground in the DAQ.
The sensors operate on a 5 V supply and generate an analog output between 0-5 V, with an output from DC to 20 kHz. I would like the DAQ to log the sensor signals, while isolating grounds, with an accuracy of 0.2 %.
What component or circuit exists that performs this function?
AI: What component or circuit exists that performs this function?
Given that the OP has revealed that the DAQ is the DT9816-S, in order to get the most from converting its very good single ended input to a differential input, I would suggest using the AD8221 instrumentation amplifier as a decent choice. I've used them myself when designing DAQs for test beds and found them to be pretty good: -
Because of the need to protect sensitive inputs I would use series resistors with each input. They will also allow for a little RFI filtering: -
The gain set resistor can be left open circuit for G = 1 operation.
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H: Reading a rotary encoder using a microcontroller and converting to Serial TTL?
I have an incremental rotary encoder (Bournes-EMS22Q) that I would like to have available on a wired network via RJ45 or via serial TTL (we have a serial-to-ethernet converter we can use Netburner SBL2E). This seems like a fairly simple problem however the more I look into it the more complex it gets, there doesn't seem to be an off-the-shelf solution and it looks like I'll have to make something myself.
Has anyone come across this problem before? How can I get from the encoder output (5 pin) to serial/ethernet?
I'm now looking at a chip-level solution using this 32-bit Quaderature Counter which gives me an SPI output but how do I go from SPI in this case to serial TTL/Ethernet? Will I need to use a microcontroller?
Is there a magical hardware component that I'm missing? Any recommendations on how to solve this problem greatly appreciated.
AI: You need a microcontroller and custom firmware to read and interpret the encoder then transmit the message over serial. In essence, you have to do it manually. No magic pre-packaged solution.
If unfamiliar with microcontrollers, you can try a PICAXE or Arduino.
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H: Do electronics companies publish the diagram of their electric boards
I'm new to the electronics world, and I came to know that electronics companies (As Fairchild) provide datasheet for the components they produce (As IGBT, Triac, etc.).
Do electronics companies (As Samsung, LG, Sony, etc.) provide a datasheets & a diagrams for the electric boards in their devices?
If the answer is NO! Then how can you tell what component is connected to other components in an electric board that you are fixing for a better diagnosis of the problem, especially with the existence of the "Surface" components as (Capacitors, Resistance, Optocoupler, etc.)?
If the answer is YES! Where can I find these diagrams?
Thank you in advance
AI: If the manufacturer provides a service manual, it would be there. In the very old days it was common to have the schematics inside the manual or sometimes even glued to the inside of the case on old television sets, but those days are long gone. For test and lab equipment sometimes the schematics are provided with the detailed user manual.
Most consumer products are very reliable and not easy to fix so it makes little sense to make schematics available to to the public.
Sometimes 3rd parties like Sam's will provide service manuals.
Even without service manuals, looking for power supply problems and obvious connections between subsystems, backlight inverters and so on can allow a substantial subset of common issues to be repaired.
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H: GPIO Open Drain LED driving
I was trying to understand GPIO open drain configuration. As far as I understood, to avoid floating output, one should use internal or external pull-up resistors. This is OK. However, I saw multiple times this driving LEDs example. I am kind of stuck here, because;
In this video and other sources, I generally see that internall pull-up resistors are 30-50k ohms. I also confirmed this from the datasheet of one of the MCUs of STM. I know that classic 5mm LEDs require approximately 20mA to give decent light output. Now, I am confused because considering 5V for Vcc, 5V - 2V(LED on) / 30k ohms = 0.1 mA of current, which looks to me that it won't be enough to drive an LED.
So, what do I miss / don't know / know but wrong here?
Thanks.
AI: 'As far as I understood, to avoid floating output, one should use
internal or external pull-up resistors'
There is no problem with leaving an open-drain output floating.
I generally see that internal pull-up resistors are 30-50k
The LED will not be very bright but it will generally be visible. 10mA or 20mA is often way too much these days with LEDs being so efficient.
Normally you would use the output transistor to sink current and add a series resistor to the LED, if you happened to have an open-drain output (and also for a more usual push-pull output). Otherwise you're wasting power when the LED is off.
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H: How can I dim 50 high-power LEDs in series with an Arduino?
What I'm trying to do is to use an Arduino to control the brightness of two series of 50 high-power LEDs independently.
Each series has an independent LED driver, and each LED has a foward voltage and current of 2V and 700mA respectively.
What I want to do is to be able to vary the brightness of each series from 0% (OFF) to 100% (full brightness) with 0.5% or 1% steps using my PC or my smartphone (with a BT module) and an Arduino.
I've searched on the internet about how to do this, and I found that maybe I could use an n-MOSFET to control the current provided by the LED Driver using an analog output of the Arduino (as far as I know controlling the current I can control the brightness which is the main point), but I saw that those MOSFET can get very hot (and I don't want this) and the current doesn't change linearly, so I'm afraid of not being able to precisely control the brightness. So now I'm completely lost on this problem, if someone could help me I would be extremely grateful.
OBS: I'm a complete noob in electronics and with Arduino, so if it's not asking too much, please explain exactly how I should build this circuit to get it to work.
AI: An n-channel MOSFET is a great way to dim LEDs. Something like the IRFZ24N is likely what you'd want - it can handle way more amperage than you'll ever need, and pretty cheap.
The way you drive an LED with a MOSFET is to view the MOSFET as a switch - because it is! Current will flow between the Drain and Source, but only when the voltage between Gate and Source is high enough (Vgs). Because the switch is voltage-controlled, you'll want a pull-down resistor to make the switch OFF when the Arduino isn't driving it.
simulate this circuit – Schematic created using CircuitLab
The code you'll want to look up is the Arduino function analogWrite. This will let you pulse an output on and off for different amounts of time (pulse-width modulation is the key term here, or PWM). For your application, PWM will let you control brightness.
R2 is to limit the current to 500mA - just for example. If you post exactly what "LED Drivers" you're using, we could help you utilize them, but this is a valid solution for driving the LEDs without those drivers.
Your MOSFET isn't likely to get hot passing 300mA, or even the full 700mA. This is because a MOSFET has a really low "switch resistance" (RDS_ON), around 70mΩ in the IRFZ24N. 700mA through 70mΩ is only 0.03W, maybe 2 or 3 degrees hotter than ambient! If anything will get hot, it'll be the LEDs themselves and the resistor (300mA through 10Ω is 0.9W, hence the need for a beefy resistor!)
A switching LED driver prevents this resistor heat issue by converting the voltage to the right place instead of shedding it as additional heat. Yours might do that, so if you can let us know what those are we could avoid a lot of heat problems!
EDIT REVOKED: Didn't realize you wanted independent control.
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H: In a linear time invariant system, is it possible for a SS response to exist, when we have a bounded input?
The answers provided showed that it is possible. I don't understand why. I think since it said that the input signal is bounded, it means that the modes of the signal are within the unit circle, so the forced response will decay to 0. Since we dont have the forced response, there won't be a steady state. Where am I wrong here?
I read it on page 3.29 of this file . It said: "If all of the input signal poles are within the unit circle, then the forced response will decay towards zero as n → ∞."
AI: I don't do z-transforms in my sleep, but if I read the next two bullet points in the text you referred to, they say
If the input signal has a pole on the unit circle then there is a persistent sinusoidal component of the input signal. The forced response to such a sinusoid is also a persistent sinusoid
In this case, the forced response is also called the steady-state response.
From this I can deduce that
An input with a pole on the unit circle is also a bounded input in the time domain (because the sinusoids are bounded functions). So it's not correct that all poles must be within the unit circle for the input to be bounded.
The text defines the steady state response as the response to an input with a pole on the unit circle, not the response to an input with all poles within the unit circle. That is, it defines the steady state response as the response to an input with a sinusoidal component, not the response to an input that decays as \$t\to\infty\$.
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H: Signal Conversion 36V to Logic Level with Zener Diode
I have 8 cells in series and I want to check them, whether all are connected. I came up with the following schematic:
simulate this circuit – Schematic created using CircuitLab
My question is about R and how viable this solution is.
My reasons for calculating R is the following: I saw that a CMOS gate leaks 1uA. While I don't want to waste energy, I want to be as closely as possible. Not too close, due to noise. So I came up with 470k. Is this too high? Does this work? (Sorry, I don't have 2V Zeners at hand, so I can't check it myself)
Let's say I have a RC element (R=100, C=0.1uF) between the cell and R. Does this help and make those 470k a safer solution?
Do you see any other problems?
AI: Zeners, particularly low voltage ones, leak far more than the CMOS input (1uA is a very loose specification at high temperature). For example, 100uA at 1V for a 2.2V zener.
So I suggest you lose the Zeners and use a different kind of clamp. For example, a diode clamp to a 2.5V shunt reference for each input. You only need one 2.5V shunt reference, but each input needs the series resistor and diode.
The other problem is that if the input is left open (not grounded), there is no reason for it to go to logic low, so you really need a resistor to ground on each input. You could use 470K resistors to ground and varying values for different series resistors, but the first one would call for a relatively low value of resistance, perhaps 100K.
Edit:
Clamping scheme:
simulate this circuit – Schematic created using CircuitLab
(not shown the Vref to cathode connection on the TL431 to set the voltage to 2.495V nominal).
The TL431 can clamp significant current (up to 100mA total). Input voltage will
be one diode drop plus 2.5V.
Using the supply voltage runs the risk of causing it to rise out of regulation as most regulators cannot sink current and also you would have to use Schottky diodes, which are relatively leaky compared to signal diodes such as the 1N4148/LL4148.
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H: Is there a method to know the temperature value of a microcontroller?
I want to know if there is a method to know the temperature of the microcontroller to avoid its over heat.
AI: The vast majority of microcontrollers on the market today have some kind of built-in die temperature sensor. Often this is implemented as an extra channel on the ADC multiplexer. It may not be especially accurate, but should be fine for detecting an overheat condition.
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H: Why is a square wave used for audio power calculations?
I am trying to read this datasheet (NXP TDF8546 Class AB Power Amplifier). On page 12, the power calculations are mentioned as
Po(max): RL = 4 Ohm, Vp = 14.4V, Vi = 2 V RMS Square wave
As far as I know, while calculating power calculations for any power amplifiers, engineers typically consider the sine wave. The reason I know is, its fundamental signal, and harsh input for power amplifier.
Why NXP considered square wave instead of sine wave in this datasheet?
AI: Because a square wave is the waveform with a given amplitude that produces the maximum amount of power.
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H: Input impedance of grounded emitter amplifier with DC feedback
In AoE3 2.3.5.C (page98) it states the following (referring to the circuit in the image):
For instance, feedback acts to reduce the input and output impedances. The input signal sees \$R_1\$ resistance effectively reduced by the voltage gain of the stage. In this case it is equivalent to a resistor of about 200\$\Omega\$ to ground (not pleasant at all!)...
The intrinsic emitter resistance \$r_e\$ is \$\frac{V_T}{I_E} = 25.3\Omega\$ (with \$V_T \approx 25.3mV\$). Only \$R_2\$ and \$r_e\$ are "to ground" so \$R_1\$ does not play in the part. So \$R_{R2||(\beta*re)} = 1844\Omega\$ (with \$\beta \approx 100\$), and hence the signal input impedance. I can't understand how input impedance is reduced to 200\$\Omega\$ in this grounded emitter amplifier circuit with DC feedback.
AI: It's mostly about how the collector voltage changes with respect to a base voltage change.
To start, it's assumed that the input capacitance's impedance is negligible at the frequency under discussion and can be neglected. Next, you know that the voltage gain is near \$A_v=\frac{R_{_\text{C}}}{r_e}\approx 320\$ (given your own figures here.)
Since the collector voltage moves in the opposite direction to the base voltage, and does so by that gain figure, then the change in voltage across the resistor will be \$v_{_{\text{R}_1}}=-A_v\cdot v_i - v_i=-\left(A_v+1\right)v_i\$. Therefore, \$i_{_{\text{R}_1}}=\frac{v_{_{\text{R}_1}}}{R_1}=-\left(A_v+1\right)\frac{v_i}{R_1}\$.
Normally, you'd expect \$\mid\: i_{_{\text{R}_1}}\mid=\frac{\mid v_i\mid }{R_1}\$. But as you can see, it is \$\mid-\left(A_v+1\right)\mid=A_v+1\$ times larger. So the resistance of \$R_1\$, as seen by the input, appears to be about 321 times smaller because of the direction and magnitude of the collector voltage change with respect to the base voltage change.
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H: How to check with a simple multimeter whether an old lead-acid battery and its charger are still working?
I have an old (ca. 10 years old) 6V lead-acid battery and a mains charger for it and I know the combination worked years ago.
Now I tried to recharge the battery and the charger's LED turns on during charging, but when I use the battery with a LED bicycle light (for dynamo use) the bicycle light doesn't illuminate. Of course the light might be defective, so my question is:
How can I check whether the lead-acid battery and its charger are still working?
I do have a simple digital multimeter and after charging the battery over night it gives me a voltage of 4.5V at the battery (no other load attached,) but at the plugged-in charger I see strangely only 0.15V (no other load attached.)
I have no idea what's going on. Is all of this normal and the bicycle light is the problem?
Update:
The battery is a DiaMec SLA battery. Here a picture of it:
And the brand of the charger is PowerTech:
Update II / Resolution:
Finally, after reading all the great tips and comments, I did get a new battery (exactly same make and model) and the old charger works perfectly with it and the lamp works as well. So indeed, as people told me, it was the battery which was defective.
AI: With the battery connected to the charger, and charging up, I would expect to see something like 7V (give or take a fraction of a volt). Once the charger is disconnected, the battery would drop to about 6.5V when freshly charged.
If the battery is only giving 4.5V, then it is totally flat. If it has been left like that for years, it is unlikely to ever work again.
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H: Coded OFDM, interleaving, sensitivity, and narrow band interference
Coding (which is a controlled redundancy) and interleaving across sub-carriers protects OFDM signals from a narrow band interferer (CW) that could destroy one subcarrrier. It provides a kind of frequency diversity
Suppose we have an AWGN channel , a coded OFDM signal with a certain modulation and coding scheme at a low coding rate and a certain corresponding sensitivity.
Suppose now that this signal is hit with a strong inband CW destroying one subcarrier, would the protection provided by coding and interleaving allow reception of this signal at the same sensitivity level when it was exposed to AWGN only?
AI: A strong inband carrier may be strong enough to overload the frontend Low Noise Amplifier transistor, and prevent ANY of the OFDM passing thru.
On the other hand, dropping the desired signal and the inband carrier/jammer by 20/30//50/80 dB should just impair that one channel of the large number used by the OFDM.
If there is enough interleaving, despite the low-coding gain (such as Viterbi 7/8, not 1/2), then you may succeed. If you expect big problems, you might employ handshaking at various times, and upon TX/RX agreement switch from 7/8 to 1/2 when interference requires that for a viable signal.
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H: Why do i get three different methods to calculate the same current ,but get three different current values?
I want to find the current \$I_R\$,and i used three methods,and i got three different
\$I_R\$ values,i hope someone can tell me where am i wrong!
simulate this circuit – Schematic created using CircuitLab
method 1 & 2 : There are two circuits as below,the main difference between them is the direction of \$I_2\$,which are opposite!
Left hand circuit :
\$I_R=I_1=3\frac{(2+3)}{(2+3)+(1+R_L)}=3\frac{5}{6+R_L}=\frac{15}{6+R_L}\$
Right hand circuit :
\$I_R=I_1=3+I_2=3+1\frac{3}{3+(2+1+R_L)}=3+\frac{3}{6+R_L}=\frac{21+3R_L}{6+R_L}\$
simulate this circuit
method 3:superposition
\$I_R=I_{R1}+I_{R2}+I_{R3}=0+[3\frac{(2+3)}{(2+3)+(1+R_L)}]+[1\frac{3}{3+(2+1+R_L)}]=\frac{18}{6+R_L}\$
simulate this circuit
If we use the maximum power Maximum Power Transfer Theorem,we can know \$R_L=6Ω\$.However,now i have a big problem,that is,we can see that when i replace \$R_L\$ with \$6Ω\$ in the current from method 1 to method 2,we can find that we have three different \$I_R\$ values!!
I believe that \$I_R\$ value by using method 3 is correct,but i don't know where am i wrong in my method 1 and method 2,can anyone tell me the mistake i made?
AI: Method 3 is correct.
\$I_R=I_{R1}+I_{R2}+I_{R3}=\color{orange}{0\text{ A }}+\color{magenta}{[3\text{ A }\frac{(2\Omega+3\Omega)}{(2\Omega+3\Omega)+(1\Omega+R_L)}]} +\color{blue}{[1\text{ A }\frac{3\Omega}{3\Omega+(2\Omega+1\Omega+R_L)}] } =\frac{18\Omega}{6\Omega+R_L}\text{ A}\$
That method also shows what goes wrong in method 1 and 2:
In the Left hand circuit:
\$I_R=I_1=3 \text{ A } \frac{(2\Omega+3\Omega)}{(2\Omega+3\Omega)+(1\Omega+R_L)}\$
The current of 3A isn't divided across \$R_3\$, \$R_2\$, \$R_4\$ and \$R_L\$ like that, because it does not take into account the contribution of the 1A current.
You can see it comparing it to the solution of method 3: Only the contribution of the 3A current source (magenta part) is taken into account by this method 1, not the contribution of the 1A current source (blue part).
Right hand circuit:
\$I_R=I_1=3\text{ A }+I_2=3\text{ A }+1\text{ A }\frac{3\Omega}{3\Omega+(2\Omega+1\Omega+R_L)}\$
The problem here is that the 3A current is not only running through \$R_9\$ and \$R_L\$, but also through \$R_8\$ and \$R_7\$.
Comparing to method 3 you can see that only \$ \frac{(2\Omega+3\Omega)}{(2\Omega+3\Omega)+(1\Omega+R_L)}\$ part of the 3A current flow through \$R_L\$.
Regarding method 1 correct approach would be:
Using the left hand circuit:
The voltage across \$R_2\$ is given by \$V_{R_2}= (i_2+1\text{ A }) \cdot R_2 \$
The voltage across \$R_3\$ is given by \$V_{R_3}=i_2 \cdot R_3 \$
The sum of these voltages is across \$R_1\$ and \$R_L\$, so the current through \$R_L\$ is given by
$$ i_{R_L} = \frac{ V_{R_2}+V_{R_3} }{R_1+R_L} = \frac{ (i_2+1\text{ A }) \cdot R_2 + i_2 \cdot R_3 }{R_1+R_L}$$
According KCL, \$i_2+i_{R_L}=3\text{ A }\$. Substituting for \$i_2\$ this yields
$$ i_{R_L} = \frac{ (3\text{ A }-i_{R_L} +1\text{ A }) \cdot R_2 + (3\text{ A }-i_{R_L}) \cdot R_3 }{R_1+R_L}$$
$$ i_{R_L} (R_1+R_L) = 4\text{ A } \cdot R_2 - i_{R_L} \cdot R_2 + 3\text{ A } \cdot R_3 - i_{R_L}\cdot R_3 $$
$$ i_{R_L} (R_1+R_2+R_3+R_L) = 4\text{ A } \cdot R_2 + 3\text{ A } \cdot R_3 $$
$$ i_{R_L} = \frac{ 4\text{ A } \cdot R_2 + 3\text{ A } \cdot R_3 }{R_1+R_2+R_3+R_L} $$
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H: Understanding LED datasheet terms
I was looking through an LED datasheet for an LED I am using and came across some terms that I am not familiar with. I a new to electronics, and have looked on the internet for explanations, but they provide relatively (to me) in-depth and complicated answers.
(Continuous) Forward Current
(Zener) Reverse current
Peak Forward Current(Duty /10 @ 1KHZ)
Reverse Voltage
Forward Voltage
Electrostatic Discharge
Any help in understanding these would be great
AI: (Continuous) Forward Current - how much maximum current can be put through the LED (30 mA for the LED in question) continuously (as opposed to peak forward current)
(Zener) Reverse current - it has zener diodes internally protecting the LED and these are limited to a certain amount of current before they might fail. The reverse current is that limit.
Peak Forward Current(Duty /10 @ 1KHZ) - tells you that you can exceed the continuous current (30 mA) by using 100 mA ONLY if the duty cycle of the applied current waveform is 10% i.e. you can apply 100 mA for 100 microseconds every 1 milli-second.
Reverse Voltage - this is the nominal reverse voltage of the in-built zener diodes (5 volts) before it starts to heavily conduct (\$I_R\$ >> 50 uA) - see also Zener Reverse Voltage = 5.2 volts at Iz = 5 mA. See also Zener Reverse Current of 100 mA (maximum rating)
Forward Voltage - this is the typical voltage across the LED when feeding it at 20 mA (between 3.0 and 3.6 volts)
Electrostatic Discharge - this tells you that the device is capable of withstanding an ESD event of 4000 volts based on the typical mode of a human (body model) touching the device when in circuit.
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H: How do I make a battery voltage indicator using the battery being tested?
I am trying to make a circuit that will test if a 5V battery is under 5V, with the testing circuit running off the battery being tested.
I have seen other answers to this question, however they rely on separate power sources to power the circuit. I am looking for a system similar to those found in flashlights or smoke alarms, telling you to replace the battery.
Any help would be great :)
AI: I would consider using a MAX931 low-power comparator with an in-built voltage reference that is accurate to within 1% of 1.182 volts : -
V+ and Vin can connect to the battery and the two resistors (use high values to avoid excessive battery current) set the point at which the output goes low when the battery voltage drops below the required set-point.
The chip works from 2.5 volts to 11 volts so 5 volts is fine.
Choose the resistor divider so that the low threshold for the battery (say 4 volts) produces 1.18 volts at IN+.
What you drive with the output is up for grabs but, a simple scheme might be to illuminate a low power LED when the output switches low thus indicating that the battery has dropped below 4 volts (or whatever value you think is right).
The output stage can easily drive 10 mA into an LED and series resistor tied up to the battery supply. Or maybe you use the logic low output to trigger a low frequency oscillator that pulses the LED on for 0.5 seconds every (say) 20 seconds.
Or maybe you just drive a low power LED when the battery voltage is good. No LED illumination means battery bad.
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H: Matched biasing transistor vs. emitter resistor in current mirror
If adding emitter resistors can reduce the temperature variation in \$V_{BE}\$, why do we still need to find a matched pair of transistors to construct a current mirror?
AI: You are right about the emitter resistor reducing the temperature variation of the current mirror. However, not the collector current is mirrored but the base current / voltage is mirrored, meaning that you still have some dependency on the gain of the second pair of your current mirror.
In the following circuit, the current through \$Q_1\$ will be approximately given by:
$$I_{C,Q_1} \propto I_B\cdot \beta_{Q_1}$$
$$I_{C,Q_1} \propto I_{C, Q_2}\dfrac{\beta_{Q_2}+1}{\beta_{Q_1}+1} \dfrac{\beta_{Q_1}}{\beta_{Q_2}}$$
simulate this circuit – Schematic created using CircuitLab
EDIT #1
Consider the following circuit:
The base voltage which is common for both transistor is given approximately by (for the sake of simplicity the internal emitter resistance is neglected ):
$$V_B = V_{BE,1}+ R_{E,1} (I_{C,1}(1+\dfrac{1}{\beta_1})) = V_{BE,2}+ R_{E,2} (I_{C,2}(1+\dfrac{1}{\beta_2}))$$
For a matched transistor and resistor, the above formula yields:
$$I_{C,1}=I_{C,2}$$
Assumming now that, \$\beta\$ is not matched, the collector current of \$Q_2\$ is given by:
$$I_{C,2}=I_{C,1}\dfrac{\beta_1 +1}{\beta_2 +1}\dfrac{\beta_2}{\beta_1}$$
As already explained in this question, \$\beta\$, which is defined by collector to base current ratio, has some temperature dependence given by:
$$\beta = \dfrac{I_C}{I_B}=\dfrac{I_C}{I_E - I_C}$$ where \$I_E\$ can be written in terms of thermal voltage \$V_T\$, which is dependent on the temperature according to:
$$V_T=\dfrac{k_BT}{q}$$
The following simulation, can show that although not very significant, the beta of the transistor still play a role on the mirrored current despite the introduction of matched emitter degeneration resistors.
This simulation, modifies the beta of the second transistor, by adding a \$\pm 50%\$ tolerance to its nominal beta value. All other parameters are left untouched. Furthermore, the simulation is run for 3 different temperatures in order to accout their variations on the final collector curent.
As you can see in the above plot, the output current (\$I_{Q,2}\$) has a dependence on the temperature, and consequently on beta.
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H: What is the flowing current through an inductor when the switching gets delayed?
Consider the following circuit in which the switching takes place instantaneously at \$t=0\$.
The current flowing through the inductor right before switching is \$ \tfrac{E}{R_1} \$. As the current must be continuous then it must be the same right after switching. It is not hard to derive that $$ i_L(t)= \frac{E}{R_1} \exp \left( -\frac{R_2}{L}t \right) $$ .
Question
I wonder if there is an amount of time delay in switching, what is the current through the inductor? Does it become zero? Where does the stored energy in the inductor go?
AI: I wonder if there is an amount of time delay in switching, what is the
current through the inductor? Does it become zero? Where does the
stored energy in the inductor go?
It will instantly produce a spark across the open contact and fizzle the energy to zero pretty much in micro or nano seconds. The inductor does only what it knows as per this formula: -
$$V = L\dfrac{di}{dt}$$
Meaning that the rapid change in current causes a massive voltage and the energy burns off in the resulting spark.
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H: Different readings of voltmeter on simple circuit
Hi I am trying to learn the basics of electronics and puzzled by the following qucs simulation.
Why the readings of voltmeters are different? I would expect, by the way zero readings on both voltmeters as they are basically breaking the circuit one for another.
At least the readings should be symmetric but they are not.
AI: I suspect the impedance of the virtual meters is infinite - breaking the circuit. You may get better results by putting a 10 megaohm resistor in parallel with the meter.
Edit: this modification of your circuit clears up what's going on.
Falstad makes three simplifying assumptions:
(1) It defines an absolute voltage for purposes of simulation, rather than real voltages which are defined between two points.
(2) A voltmeter with nothing on the other end therefore produces a voltage as if the other end was connected to zero volts. Real voltmeters do not do this.
(3) Voltmeters have infinite impedance.
(4) In the original circuit at the top of the page, it looks like it arbitrarily decided that the positive terminal of the battery was to be used for "absolute zero voltage". That explains all the rest of the readings - the resistor and the right-hand terminals get assigned "absolute zero".
Not entirely broken, but all you're doing is showing how the simulation is a simplification of reality.
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H: Transfer characteristics of circuits involving op amp with diodes
How should I approach such questions?
AI: Ask yourself for each case (\$V_i\$ positive and \$V_i\$ negative), what the output has to do to satisfy the fundamental (idealized) property of such an op-amp circuit, which is that the input terminals are held at the same voltage.
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H: MCP3008/ADuM3154/ESP32 - Corrupted MISO Data Line
I have 3 MCP3008's being read by an ESP32 on the same bus isolated by an ADUM3154ARSZ. I was reading each pin on the MCP3008's about every 10ms. I seemed to have a lot of jitter and after averaging the values I found them to be way too low. I then tried just reading one of the inputs every second to see what was going on and it appeared to be missing almost every second result. (0 or very low value)
02:28:21.170 > 426
02:28:22.178 > 0
02:28:23.204 > 1
02:28:24.210 > 422
02:28:25.218 > 0
02:28:26.230 > 424
02:28:27.234 > 1
02:28:28.242 > 425
02:28:29.250 > 0
02:28:30.258 > 0
02:28:31.282 > 423
02:28:32.290 > 0
02:28:33.298 > 424
02:28:34.306 > 1
02:28:35.314 > 0
02:28:36.322 > 425
I hooked up my scope to the serial pins at the MCP3008 and I seem to be getting corruption/low voltage on the MISO data line between the MCP3008's and ADUM3154ARSZ. (See pictures below) I have stripped everything down to just reading one MCP3008 through the isolator. I added a 10k pullup on the MISO line thinking that the isolator wasn't pulling the line up hard enough, but did not seem to change anything. I added some different delays between pulling the ADUM3154ARSZ address lines low and starting the SPI transaction but it did not seem to help either. (Shouldn't matter as address 0 is both address lines low anyways) Changing up the time between reads does not seem to change the ratio of how many good readings vs bad readings there are.
Also, when zooming right out on my scope I see the MISO line getting pulled down up to 15ms after the initial read and then about 12ms and then 9ms and keeps going down till 0ms and goes back 15ms or so. (Not sure what this is but seems to be a repeatable pattern)
I am not sure why it's doing this and was hoping someone here could spot what I am doing wrong.
Thanks!
Schematic for reference: (L3V3 and LGND are supply for ESP32 and P3V3 are supply for MCP3008's)
Good Reading:
Bad Reading:
Another Bad Reading:
AI: Complete facepalm here, I totally missed the pullups on the CS lines...
I had read on page 17:
To allow compatibility with nonstandard SPI interfaces, the MI pin is
always active, and does not tristate when the slave select is not
asserted.
I had assumed that this also applied to all the pins including the CS.
I also thought the MCP3008's had CS pullups too. Not sure how I missed this in the scope, the CS looked good but I didn't realize the other 2 MCP's that I was not probing were driving the MISO line low.
From page 18:
Figure 12 illustrates the behavior of the SSA0 and SSA1
channels. This diagram assumes that MSS is low and that SS0,
SS1, SS2, and SS3 are pulled up.
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H: Do all USB cables have power lines?
I have a USB type A to type B cable, I took it from a printer. Now, I want to utilize this USB cable to make a 5V breadboard power supply. I will cut the cable and connect power lines to breadboard's power rails. But, I can't be sure if it is guaranteed to have cables for power transmission or not. I mean, I don't want to ruin the cable if it cannot be used to transmit power.
So, I am sure (well, almost) that there are data lines in the cable, because it was used to transfer data between computer and printer. However, printer had its own power plug. Thus, I am not sure whether this cable has a power line or just data lines.
AI: If the USB connector on the cable is stamped/embossed with the USB logotype, then it has all four wires connected.
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H: Optocoupler - Emitter follower for driving an optocoupler
I have some troubles to understand the above circuit :
simulate this circuit – Schematic created using CircuitLab
The goal is to discharge the capacitor which was previously charged to 20V the most rapidly. (At least I think). The collector emitter voltage drop of the phototransitor and the forward diode voltage have to share the voltage of the discharging capacitor. At the beginning of the discharge, ie when the voltage of the capacitor is equal to 20V, the diode forward voltage is equal to Vf (lower than 1V), so VCE has to be equal to at least 19V ! So if VCE is high, the collector current Ic of the phototransitor is limited by the gain of the phototransitor and the forward current of the emitter diode $$If*CTR = Ic$$ where CTR is the current transfer ratio. So for discharging the most rapidly the capacitor, we have to have a high collector current, ie a high forward current flowing through the emmitter diode. What do you think ? Wouldn't be better if a resistor would be added in series with the phototransitor ? It will allow to saturate the photransitor without necessary diminishing the collector current if the forward current is high.
By the way I did not get why there is a shunt resistor R2. It will reduce If. Nevertheless it could help to reduce noise problem. (leakage current will not be a problem, isn't it ?) Wouldn't be better if the shunt resistor would be placed as a pull down resistor. Same thing for the capacitor next to the shunt resistor? This capacitor will slow down the discharge of the capacitor charged to 20V. What do you think ?
Thank you very much and have a nice day :)
AI: This depends largely on what size capacitor you're discharging and how long you have to discharge it, as well as the residual voltage you can tolerate. If it's a 100pF cap you're discharging, I'd say you can do it with the schematic above; there will be a high peak current, but not long enough to significantly heat the driver. If it's a 100uF cap, you'll probably want to include additional drive or add a series resistor (which will slow the discharge rate). "The most rapidly" isn't a workable spec unless you're doing high energy EMP research, which is far more expensive than this; you need a number to work to.
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H: Common mode feedback for current mirrors
I was reading the chapter about Op - Amp design in Microelectronic Circuits by Sedra Smith, and I have some questions about the so called "common mode feedback" (CMFB) which is used to control some current mirrors.
Let's consider this scheme:
The book says:
Relying solely on matching will not be sufficient to ensure that the
currents supplied by Q9 and Q10 are exactly equal to the currents supplied by Q7 and Q8. Any
small mismatch \$\Delta\$I between the two sets of currents will be multiplied by the large output
resistance between each of the collector nodes and ground, and thus there will be large changes
in the voltages vO1 and vO2. These changes in turn can cause one set of the current sources
(i.e., Q7
−Q8 or Q9
−Q10) to saturate. We therefore need a circuit that detects the change in the
dc or common-mode component VCM of vO1 and vO2,
VCM
= 1
2
(vO1
+vO2)
and adjusts the bias voltage on the bases of Q7 and Q8, VB, to restore current equality. This
negative-feedback loop should be insensitive to the differential signal components of vO1 and
vO2; otherwise it would reduce the differential gain. Thus the feedback loop should provide
common-mode feedback (CMF).
I have the following questions:
1) How is it possible that for instance current of Q9 is different from that of Q7? Their channels are in series (since the load is supposed to be of infinite impedance) and so, by kirchoff current law, all the current through Q9 should go on Q7, I think...
2) Does the book refer to DC or signal currents?
3) Why do we decide that the CMFB has to read the common mode voltage? Suppose there is a mismatch between current of Q9 and current of Q7: there would be a spurious value inside vO1. Which is the link between this spurious voltage, and the common mode voltage between the outputs in 1 and 2?
AI: 1) The currents of Q7/Q8 and Q9/Q10 are set by the bias voltages. It is very difficult to get this bias voltage exactly right without a feedback network, so the theoretical collector currents would differ. This discrepancy in current results in wild shifts in output voltage as a result of the Early effect (i.e. R_out in the small-signal model of each BJT).
2) The DC bias itself is susceptible.
3) This portion of the question isn't that clear. We want to regulate the common-mode voltage because it is part of the desired specification of a differential amplifier: as the outputs swing up and down with a differential input, they swing around a well-regulated constant common-mode voltage. If we regulated Q7 and Q8 using only the voltage at vO1, we wouldn't get a fully differential amplifier; instead we would get something along the lines of a differential-to-single-ended amplifier.
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H: Why would a large resistor in series cause a different voltage reading?
I'm watching Electroboom and don't understand why the voltage drops when he touches the spoon. He states there must be a large resistance in series. Why would the voltage not already have dropped before touching the spoon if there was a resistor? He states he's putting his body in parallel with it but I don't really understand what the circuit diagram would look like.
AI: First he is measuring the voltage with nothing but his multimeter. Multimeters tend to have very high internal resistances. Mine has 10 MOhm. Therefor the source doesn't have to provide a significant current. He measured ~5 volt. That would be 5 V/10 000 000 Ohm = 0,0000005 ampere.
If he touches the wire a parallel path for the electricity through his body is created. His body has a much lower resistance. I assume its about 1 kOhm. That means that there should be a higher current than before but the source isn't powerful enough to provide that current. Therefor the voltage has to drop. Otherwise the circuit would violate Ohms Law which is V=R*I.
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H: Can de-ionized water be used instead of distilled water to prepare lead acid battery electrolyte?
I have a couple of Yuasa and Power Sonic conventional lead-acid bike batteries that I recently purchased for a very good bargain price from a seller. They are new and never used. But unfortunately, the seller did not have the battery acid packs in his possession. So, I have to end up preparing that myself.
I know that I'll need to prepare a 36-38% concentrated sulfuric acid solution (this is what manufacturers usually use) using my concentrated acid which is a 95-98% ACS reagent sulfuric acid.
Now I know that they usually use distilled water to prepare them. But I was thinking if it's possible to use ultrapure de-ionized water instead.
AI: Either type will work (deionized [DI] or distilled.) Both have had most mineral contaminants removed; DI more so than distilled. DI however is overkill, as distilled easily meets acceptable contaminant limits for lead-acid batteries.
More here: https://www.trojanbattery.com/pdf/WP_EffectOfImpurities_0612.pdf
So, ask the battery maker who employs the chemist ;-)
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H: Making a phantom powered power switch (not mute switch) with LED indicator
I want to create an XLR inline power switch (with indicator) so that I can turn my phantom powered microphone on and off as I please!
I have found a few guides online that explain how to create a mute switch, but I'm not sure that will work for what I require.
I've read that an XLR cable has 3 pins, and that you run all of the pins to themselves, 1 - 1, 2 - 2 and 3 - 3 and then you mute the microphone by making a connection between pin 2 and 3, and this shorts the microphone and disables the audio. So this means that when the switch is on, the microphone would be muted.
I want to add one of these these inline to the XLR cable and how I want it to work is that when the switch is on, the microphone and LED on the switch are both on, then when you switch it off, they both turn off.
How would I go about wiring the switch so that when it's in the on position, pin 2 and 3 are disconnected, and then when I switch it off, pins 2 and 3 connect and it shorts the microphone and turns it off?
I'm an absolute novice at electronics, I've learned everything above from researching so absolutely any help would be appreciated!
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. (a) What you want. (b) What you're considering using.
You need a switch with two normally open (NO) contacts and one normally closed (NC).
The switch you've chosen has only one contact and two terminals so I suspect that the LED common connection is through the body of the switch and requires mounting in a panel connected to negative. (That's usually easy on a car dashboard.)
It is not suitable for your application.
simulate this circuit
Figure 2. The requirements can be met with a double-pole, double-throw, 2P2T, switch.
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H: What do these numbers represent in this schematic diagram?
What are those 1 4 and 2 3 on both sides of the button? They look like having connected to same places at both ends, it looks like redundant cable to me.
So, what are they representing?
AI: Tactile switches usually have four pins, with pin pairs already connected to each other. Very often you'll see that the switch closes contact between the pins on a particular side.
Since pin numbering is typically done on alternating sides, but the contact is done between adjacent pins, you can have pairs [1,4] and [2,3] electrically connected.
Here is an excerpt from a common tactile switch datasheet (C&K PTS645):
The schematic (top right corner) shows a slightly different arrangement where the pairs are [1,2] and [3,4].
You can use a switch with either arrangement, just be sure you know which pins are electrically "normally closed" and which are "normally open" by examining the datasheet before you solder.
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H: What degree of magnetic shielding does a Kozyrev Mirror require?
After learning about kozyrev mirrors, I’m curious what types of fields they’re designed to shield. “The earth’s electromagnetic field” was all I could find. But does that mean just earths magnetic field, the field shown by a compass? Or also the the ELF of the Schumann resonance? Or both? How is a kozyrev mirror related to a zero gauss chamber, one and the same or no?
Also, what materials does it require to match the required degree of shielding?
AI: If you want magnetic shielding, then use sheets of metal.
The standard PCB thickness foil, 35 microns or 1.4 mils, have a few dB effect at 4MHz (1 neper of attenuation), 3 nepers of attenuation at 40MHz and 10 nepers (87dB) at 400MHz.
For low frequency magnetic protection, you either need much thicker copper, or switch to steel.
Read up on "skin depth" for some guidance.
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H: Can the HAL_ADC_Start(&hadc1) function be executed only once?
I am using STM32F103C8T6 ADC1 single channel continuous conversion mode to collect the ambient temperature, but I am not very clear about using the function HAL_ADC_Start (& hadc1) because the function is called once before the "while" loop of the main () program and the Call this function multiple times in the loop, will this affect the value collected by ADC1?
Thanks for the answer
AI: If you use continuous conversion mode you don't need to call this function multiple times. Just call it once and the conversions will start and go on and on.
To get the results in your loop you can use HAL_ADC_PollForConversion(&hadc) or start the ADC with interrupts and get the result in the callback function.
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H: Does a turbine experience a countering electromagnetic force while it induces a voltage?
I am assuming yes, because of the law of conservation of energy. A certain amount of energy is required to turn a turbine. So if we want a turbine to spin as well as induce a voltage, then more energy will be required to do so. I suspect the turning of the turbine is impeded by an emf, which requires more energy to push through, compared to a situation where we were just looking to spin a turbine without wanting to induce a voltage.
AI: The turbine needs to develop sufficient torque to overcome the electromagnetic forces within the generator.
With a turbine alone, the hydraulic energy requirement would be to just rotate it at the desired RPM. To that would be added the energy required to keep the electrically unloaded generator rotating at the same RPM. The final addition would be the energy required to feed the electrical load, with the generator maintaining the same RPM.
The ultimate power (torque at the desired RPM), required to be generated by the turbine, would be decided by the electrical load.
The rate of flow of the fluid in the hydraulic system would determine the power that could be generated by the turbine.
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H: Using Python to simulate an LTspice netlist
I am new to Python, and I want to simulate LTspice circuits automatically using Python.
I added the library ltspice and scripted a fair amount in order for Python to automatically generate an LTspice netlist I want.
The problem I am facing is that I don't know what command I should use to simulate the netlist in LTspice using Python so I can plot the output voltages and currents.
Looking forward to your suggestions.
AI: Errrm.
What's unclear about the examples on the Python ltspice library page?
Example circuit:
Example code:
import ltspice
import matplotlib.pyplot as plt
import numpy as np
import os
l = ltspice.Ltspice(os.path.dirname(__file__)+'\\rc.raw')
# Make sure that the .raw file is located in the correct path
l.parse()
time = l.getTime()
V_source = l.getData('V(source)')
V_cap = l.getData('V(cap)')
plt.plot(time, V_source)
plt.plot(time, V_cap)
plt.show()
Example output:
You have named nodes (cap and source) and ask for the data using the following line:
l.getData('V(source)')
"getData" is the function. "V()" tells LTspice you want the voltage, and "source" says which node.
From the comments, it seems that the ltspice library only does part of what you need.
This project seems to cover the other half - namely, making LTspice execute a simulation from within a Python program.
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H: effects of hFE in emitter follower?
There are multiple hFE options for BD139s, with the higher hFE being slightly more expensive. What advantages or disadvantages, if any, would the higher hFE parts have in emitter follower circuit?
AI: Advantages of higher hFE:
Higher input impedance to the circuit
Lower output impedance
This way the emitter follower load effects to previous and next stages are reduced.
Disadvantages:
Depending on the polarization of the transistor, high hFE can affect negatively the stability due to variations on temperature.
References:
Emitter Follower, Ruye Wang, Electronic Circuits - I. pp. 1-21, A.P.Godse, U.A.Bakshi
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H: Efficient way of writing to flash memory without losing data
For my project, I am writing some code that gets some results and I want to store these results on external flash memory. The external flash memory in question is a MX25R8035F. I found that writing without erasing only works the first time I wrote something to an address.
But because of this I'm running into some memory issues. The smallest erase is a sector erase (4096 bytes.) If I want to write to a specific address I would first need to read the sector that contains that address, change the bytes that I want to be changed and then write the whole sector (writing is only per page.)
Is there a more efficient way of using this external flash memory? Specifically using less memory to change one or two bytes.
The function I use now this can be found below:
uint8_t EXT_FLASH_write(size_t address, uint8_t *buf, size_t length) {
/*
* The entire sector will be erased when writing to an offset inside that sector
* Therefore this function will first retrieve all data inside the sector and update the retrieved
* data with the values inside buff which and will then write the entire content back to the sector
*/
uint8_t wbuf[4];
SPI_Transaction transaction;
uint32_t sectorBaseAddr;
uint8_t temp[EXT_FLASH_ERASE_SECTOR_SIZE];
uint8_t tries;
size_t ilen; /* interim length per instruction */
uint32_t bufIndex = 0;
uint8_t pageIterations;
while (length > 0) {
// first retrieve entire sector so it can be erased on the chip
sectorBaseAddr = EXT_FLASH_SECTOR_BASE_ADDR(address);
EXT_FLASH_read(sectorBaseAddr, temp, EXT_FLASH_ERASE_SECTOR_SIZE);
// Erase the sector on the chip
EXT_FLASH_erase(address, EXT_FLASH_ERASE_SECTOR_SIZE);
ilen = EXT_FLASH_PROGRAM_PAGE_SIZE
- (address % EXT_FLASH_PROGRAM_PAGE_SIZE);
if (length < ilen)
ilen = length;
memcpy(temp + (address - sectorBaseAddr), buf + bufIndex, length);
bufIndex += ilen;
address += ilen;
length -= ilen;
tries = 0;
if (EXT_FLASH_writeEnable() != 0) {
if (tries == EXT_FLASH_MAX_TRIES) {
return 1;
}
tries++;
}
tries = 0;
while (EXT_FLASH_waitReady() != 2) {
if (tries == EXT_FLASH_MAX_TRIES) {
return 1;
}
EXT_FLASH_writeEnable();
tries++;
}
// programming the external flash can only be done in pages
// so divide current sector into pages and write each page separately
for (pageIterations = 0;
pageIterations * EXT_FLASH_PROGRAM_PAGE_SIZE
< EXT_FLASH_ERASE_SECTOR_SIZE; pageIterations++) {
EXT_FLASH_select();
wbuf[0] = EXT_FLASH_CODE_PROGRAM;
wbuf[1] = ((sectorBaseAddr
+ (pageIterations * EXT_FLASH_PROGRAM_PAGE_SIZE)) >> 16)
& 0xff;
wbuf[2] = ((sectorBaseAddr
+ (pageIterations * EXT_FLASH_PROGRAM_PAGE_SIZE)) >> 8)
& 0xff;
wbuf[3] = (sectorBaseAddr
+ (pageIterations * EXT_FLASH_PROGRAM_PAGE_SIZE)) & 0xff;
// Configure the transaction
transaction.count = sizeof(wbuf);
transaction.txBuf = wbuf;
transaction.rxBuf = NULL;
if (!SPI_transfer(masterSpi, &transaction)) {
/* failure */
EXT_FLASH_deselect();
return 1;
}
// Configure the transaction
transaction.count = EXT_FLASH_PROGRAM_PAGE_SIZE;
transaction.txBuf = temp
+ (pageIterations * EXT_FLASH_PROGRAM_PAGE_SIZE);
transaction.rxBuf = NULL;
if (!SPI_transfer(masterSpi, &transaction)) {
/* failure */
EXT_FLASH_deselect();
return 1;
}
EXT_FLASH_deselect();
}
}
return 0;
}
AI: FLASH is cheap and provides lot of memory, but comes with the cost of sector erase. So you might want to use EEPROM instead.
Of course it is possible to overcome this flash limitation with some clever software, which tracks the bits and bytes with a journal (i.e. you don't overwrite a byte value but write a new copy of it and note in the journal that the new byte is the recent one). But this is a really big software overhead and you might not want to do that.
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H: Ideal voltage source connected with ideal Inductor
We have an ideal inductor with the dc source in figure A.
When switch is closed we get equal and opposite voltage across the inductor against the source voltage and a constant rate of rise of current given by di/dt = V/L. This constant rate of rise/change in current will also produce the rising magnetic field (shown in green colour).
Suppose some how we reverse the battery instantly, shown in figure B. That reversed battery will cause the reversed rise of current (shown in figure B in brown colour). But at the same time the magnetic field (which was caused by the current when battery was not reversed) is collapsing and is inducing the voltage and current opposite to the reversed current.
My question is will there be no reversed current flowing as long as the magnetic field is collapsing as that collapsing magnetic field is causing the current in the opposite direction of the reversed current.
Plus there will also be electric and magnetic field produced by the reversed voltage.
How will these two collapsing and rising magnetic field are going to interact with each other ?
AI: Simple mechanical analogy
You have an object that can travel only forwards or backwards.
If the object's velocity was +1 m/s (i.e. forwards) then, after 10 seconds the distance traveled will be +10 metres.
If the forward speed slowed, the object's distance from the starting point would still increase even though the object's velocity slowed down.
If the speed fell to 0 m/s then the object would still be at a positive distance from the starting point and, that distance will remain fixed until the object started moving again.
If the object then moved (backwards) at -1 m/s, then the positive distance would start to fall towards zero.
If the object continued to move backwards, the distance from the starting point would eventually become negative.
In this analogy: -
Velocity behaves like inductor voltage
Distance behaves like inductor current
Back to the question
Suppose some how we reverse the battery instantly, shown in figure B.
That reversed battery will cause the reversed rise of current
No, current will start to fall from its previous positive value just like the analogy above where distance traveled falls from a positive value when velocity reverses to a negative value.
Here is your homework: -
Study it, then study it again.......
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H: HC-05 Bluetooth RF transmit power
The datasheet of the HC-05 Bluetooth module says the RF transmit power is up to +4 dBm RF, but I think that is for boundary value conditions.
I am planning to use the it at a data rate of 100 kbps and distance will be up to 2-3 metres only, so will the transmit power decrease and if it decreases what will the value of RF transmit power be?
We are using micro hard radio PMDDL2450 and we don't want the HC-05 Bluetooth module to interfere with the radio because both operate at the same frequencies.
AI: You cannot avoid two devices, which are using the same frequency band, to interfere with each other. You also cannot (and should not) try to solve that by increasing the transmitted power.
You are probably unaware of the fact that Bluetooth is designed to be robust against interference from other devices using the same frequency band. Bluetooth does this by changing frequency all the time and simply re-transmitting packets that got lost. So you should not worry about this and first see what you get.
It is unclear to me how that "micro hard" radio will deal with any interference.
Do realize that multiple devices can work in the same frequency band provided that they "take turns" when using it. Some high data-rate connections (Like WiFi and probably that "micro hard" device as well) take up a large part of the bandwidth, leaving little room for other devices. When that happens datarates will drop as packets have to be re-send. That hinders efficient use of the bandwidth.
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H: How to check SMD capacitor for being shorted, without disconnecting it from the electric board
This YouTube video shows that you can check SMD capacitors for being shorted using buzzer mode, by touching the ground of the electric board with the negative terminal while touching each side of the SMD capacitors with the positive terminal, the one that has both of its sides making a buzz is identified as shorted.
"SMD bad capacitor test / laptop - desktop computer & electronics troubleshooting"
My problem is that I couldn't identify the "ground" on my electric board.
It's a 2 circuits (AC & DC) board.
P.S: The 2 golden squares near the microprocessor don't exist on my board, the rest is identical to mine.
Also when I checked some of my SMD capacitors using resistance mode, I got the following values:
11K Ohms
12.4K Ohms
11.6M Ohms
11.3M Ohms
0.L Ohms (after moving upwards to reach 40MOhms, the maximum of my DMM)
What ohm value should be used to consider an SMD capacitor good or bad?
AI: Without a schematic, you will need to engage in some sleuthing to find the ground plane. A good place to start checking would be the negative (-) pins of the large electrolytic capacitors, which are clearly indicated on the plastic sleevings of the capacitors (the lighter-coloured section).
Using the plated-through-hole mounting pad may or may not work, because they are not always connected to ground. You can check this by measuring between the electrolytic capacitor negative pin and the mounting pad.
You can still take direct continuity measurements across the capacitors. A short is a short.
One final point to remember - these capacitors are almost always connected in parallel with other components in the circuit. A short indicates that one or more of the devices on the circuit have failed short - not necessarily the capacitor.
The most common failure mechanism for ceramic capacitors to fail short is mechanical stress causing the ceramic layers to crack and internally short out. Unless you dropped the assembly, I doubt the caps are bad. If they were exposed to excessive electrical or thermal stress, you would see burning, discoloration, etc.
The measurements you took already - all with some resistance or beyond the DMM measurement capability - imply that none of the circuits connected to the capacitors you checked are shorted. Your problem is likely elsewhere, or different in nature (i.e. not a short).
Where I would start is putting your DMM in DC voltage mode, plug the AC power in and check for DC on the logic board by carefully measuring voltages across the ceramic caps and e-caps on the logic board. DO NOT PROBE THE POWER SUPPLY. If you touch the wrong area you could get electrocuted. Also be very careful to not short your probes together when measuring, or you may get a really big spark.
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H: Using voltage regulators for a computer harddrive
I've got an Intel NUC (NUC8I3BEH3) that's using its own 19V, 90w power supply (pictures).
After a few issues with 4TB 2.5" hard drives, and external USB disks, I'd like to use a 3.5" drive, but the NUC's internal SATA power connector does not support this (doesn't provide 12V).
I'm considering an aluminium case (Hammond diecast enclosure, 1590DBK, 187x119x56mm), that's screwed on to the Intel NUC's 2 mounting holes, with a larger hole in the base to route the power, data cables, and maybe allow some air flow.
For power, could I run a wire off the 19V power supply (internal), in a safe way to power a 4TB Western Digital Red hard drive (WD40EFRX), which needs a 5V and 12V supply, 1.75 amperes (peak), at 4.5 watts.
Maybe using two linear voltage regulators to provide 5V and 12V (e.g. L78S05CV and L78S12CV)?
These can accept an input up to 35V, current up to 2 amperes, and have a thermal resistance of 5 °C/W junction-case or 50 °C/W junction-ambient.
Or, as per @bimpelrekkie's suggestion, a fixed switching regulator (e.g. LM2596T-12 and
LM2596T-5.0.
But I'm not sure:
Would this be appropriate for a hard drive? Can it provide a clean enough power supply, and keep running for a long period of time (4+ years).
Would it produce too much heat? I'm considering getting some 20x15x10mm heatsinks, with 3M screws, for the 3.75mm hole.
Is there a good way to connect them to the aluminium case, assuming a heatsink? I don't think solder works, or thermal tape would hold well enough, so maybe an epoxy that can also handle high temperatures (just to be sure.)
Will the 90W power supply be happy with the extra load? The computer currently uses 25W while running both of the CPU cores at 100%.
Where I'd connect the 19V supply to the 12V regulator first, should the 5V regulator connect to the 12V (so there is less of a drop from 12V to 5V, maybe helping with heat/life,) or should I connect it directly to 19V (so there is less current being pulled though the 12v regulator?) i.e. series or parallel?
Is there another way of doing this? Maybe two DC-DC step down buck converters? I've never used these before, they do look interesting, but I don't know how reliable they are.
And is there anything else I should consider with this setup?
Previously I've used a separate power supply, with an external USB hard drive, but this has introduced 2 extra wires, and where this computer will be in an office 4+ hours away, I don't want to do that journey because one of the cables have "fallen out" (at least if the computer only has 1 cable, I can get someone non-technical to check it).
AI: Let's check the current draw from the HDD documentation:
So it consumes 1.75A peak on the 12V line, and apparently doesn't even use 5V since there is no specification. That's high for a linear regulator. The linear regulator will dissipate (19-12)*1.75 = 12W peak. Since we don't know how long the peaks last and what "average" means, it is safer to design the heat sink for peak power. Then the 5°C/W spec on the regulator RthJC is a problem because the chip will be 5*12=60°C hotter than the heat sink, so it's a no-go. You need a buck converter.
19V 90W supply means 4.7 Amps. It'll probably be adequate, although you should measure the power drawn by the Nuc with GPU maxed too.
Unfortunately if you shop online with the usual suspects you will most likely find modules using low quality cheap fake components like "LM2596" ; quotes are a must since many of these modules do not have an actual LM2596, but instead an unknown chip with "LM2596" written on top. Also the last one I tested had the correct inductor value for a LM2596, which was too low for the counterfeit chip, so it saturated on every cycle. Also you will get garbage-tier general-purpose capacitors which can't handle the ripple current and run burning hot. Do not expect any kind of reliability from these abominations. A likely ending for that story is capacitor failure, followed by overvoltage on the output and death of whatever is connected to it.
So I can think about several options :
1) If the HDD does not require 5V.
Check if the Nuc can run reliably from 12V. If this is the case, replace 19V supply with a 12V supply. Done.
2) Use a buck to step down from 19V to 12V (and 5V). Here's one that should be reliable.
this computer will be in an office 4+ hours away, I don't want to do that journey because one of the cables have "fallen out"
3)
In this case a much better option is to buy only commercial off the shelf parts that can be easily delivered if they break and replaced by the end user. Since a 12V power supply for an external hard drive enclosure costs less than a 4 hour trip, I recommend giving a backup one to the customer. If you're afraid of connectors getting unplugged, apply adhesive tape.
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H: What happens to step down converter effiency when current consumption is very low
I'm planning to use a MAX640 (Maxim 9 V -> 3.3 V Step-Down DC-DC Converter) to supply a couple of ICs with 3.3 V.
In active mode the current consumption of the ICs are around 20 mA and according to the datasheet the efficiency of MAX640 is around 90 %. Hence the total current consumption will be around (20 mA/ 90 %) = 22-23 mA, right?
But most of the time I want to shutdown ICs (and MCU) to get a consumption of maybe 10 uA.. looking at the datasheet (EFFICIENCY vs OUTPUT CURRENT) it is not even plotted... what will happen? Can I not use the MAX640 if I drop the current consumption that low?
A final question, anyone have a tip of a Step-Down DC-DC converter (or with equal functionality) that also can measure current consumption (analog, spi, i2c)
AI: In active mode the current consumption of the ICs are around 20 mA and
according to the datasheet the efficiency of MAX640 is around 90 %.
Hence the total current consumption will be around (20 mA/ 90 %) =
22-23 mA, right?
No, that doesn't make any sense.
Look at the graphs in the data sheet typically this one: -
With a load current of 20 mA (not the chip current consumption) the efficiency is around 90% for the MAX640 so, if the output voltage is 3.3 volts, then the output power at 20 mA is 66 mW and the input power to the device and load is 66 mW/0.9 = 73 mW. So, if the input voltage is 9 volts and a power power of 73 mW is taken, the current is 8.11 mA.
But most of the time I want to shutdown ICs (and MCU) to get a
consumption of maybe 10 uA.. looking at the datasheet (EFFICIENCY vs
OUTPUT CURRENT) it is not even plotted... what will happen? Can I not
use the MAX640 if I drop the current consumption that low?
No, it won't be plotted because there is no need - the device is in standby mode and the load is not powered. In standby, the device takes 10 uA typically and the load is not powered.
However, if your load took only 50 μA, there would still be a significant power consumption just to keep the MAX640 operating in non-standby mode. At 50 μA load current (see the graph above) the efficiency is 50% hence input power will be 2 x 3.3 volts x 50 μA = 330 μW or, from 9 volts, the overall load and device current would be 37 μA.
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H: What does the black point mean when we are calculate the inductance of several inductors which connected together?
What does this black point mean?i mean because what reason ,so we will say the inductance of the circuit below can be written as this,by the way , \$M\$ means Mutual inductance.
Also,i want to ask that Why can the inductance of the circuit below be calculated like this?
\$L_{AB}=L_1+L_2+L_3+2M_{12}-2M_{13}-2M_{23}=3+7+10+(2\times2)-(2\times1)-(2\times 3)=16H\$
AI: The dots indicate the direction of the magnetic coupling. In your final circuit, L1 and L2 are coupled so their magnetic fields add, increasing the total inductance; L3, coupled oppositely so the magnetic fields of L1 and L2 are in opposition to L3 (thereby canceling the magnetic field to some extent), decreases the total inductance. A similar notation indicates the polarity of a transformer coupling.
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H: What gets wrong when I average AC voltage and current to get power?
Power is half the product of peak AC voltage and current (or product of its RMS voltage and current). But why is it wrong when I average first the voltage and current before getting the power?
I get that the average of AC voltage and current is zero. But what is then the use of the formula:
V(ave) = 2V/pi
AND
I(ave) = 2I/pi
This is the formula for averaging sinusoidal 360 degree voltage and current, right? Why can't I average the voltage and current to find power?
AI: You have made a false math assumption. You have caught from the wind "taking average and multiplication are distributive". That's not true as you have already found. You can check it with two voltage samples U1, U2 and two current samples I1, I2
The average power is (U1*I1 + U2*I2)/2. There's no way to reduce this to ((U1+U2)/2)*((I1+I2)/2)
You must calculate P(t)=U(t)*I(t). That's the momentary power. The average power is the average of U(t)*I(t) calculated over the period of interest. With sinusoidal current and voltage we calculate the average over one cycle.
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H: How to protect an input from ESD?
I would like to protect the input of a sensor (reference : MAX30001) from ESD.
In the datasheet, they say that the absolute maximum rating of this input is -0.3 V < Vinput < 2 V.
Do I have to strictly respect the given interval ? If yes, I do not know how to do it.
If I put a simple Zener like this :
The voltage of the input would be between - Vforward and +Vbreakdown. Problem : forward voltages of Zener diodes are 0.7 V, and I cannot find a breakdown voltage below 3 V.
If I put two clamping diodes like this :
The voltage of the input would be between - Vforward and Vdd + Vforward. Problem : Vdd is 1.8 V and I cannot find diodes with a forward voltage of 0.2 V.
What clamping diode do we typically use ? Schottky diodes ?
What other solutions do I have ?
Thanks. :)
AI: What other solutions do I have ?
Given that the data sheet says this: -
Maximum Current into Any Pin.........................................±50mA
It gives you some leeway to add a resistor in series with the input pin.
But you also need to know how big a resistor can be used and there's a clue on page 14: -
So, I estimate that the inputs are at least 50 MΩ and so a 1 kΩ in series with each input isn't going to have much of a performance implication.
How to protect an input from ESD?
So, at a maximum current of 50 mA, the voltage drop across 1 kΩ is 50 volts i.e. plenty of headroom to add a TVS of 10 volts or 20 volts on the non-chip side of the input resistor. I wouldn't use a zener - use a TVS or TVS array suitably specified for protecting against ESD.
And, as @Justme points out, the device has the following level of ESD protection built in: -
Note 10 says: ESD test performed with 1kΩ series resistor designed to withstand 8kV surge voltage.
So, I guess 1 kΩ (as I derived above) is perfectly sensible. However, given that I have suggested using an external TVS in front of the 1 kΩ that resistor need not be rated at 8 kV: -
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H: Finding the wattage given on the bulb
Sorry for what might seem like a really simple question. I came across a LED bulb that has the following specs:
It is rated for:
120VAC (which I assume is just because the wall voltage in the US is 120VAC @ 60Hz)
14W power
14mA current
However, I don't know how they calculated 14W if according to the power law equation:
P = I * V
I should get something like
16.8W = .14A * 120V
So my question is, where does the 14W come from if the power equation is 16.8W?
Thanks in advance!
AI: The power factor is not 1.00 in most electronics, particularly inexpensive low-power electronics, so the product of current and voltage (VA) will, in general, be higher than the real power (W) drawn.
As well, those numbers may be maximums and not nominal so you can't necessarily depend on them to be consistent.
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H: Help with ID of this chip from a Bluetooth speaker - top marking AWF ANG (AWFANG)
I am trying to find out what this chip is or what it does.
It is from a Bluetooth speaker which is not charging the battery. I have no idea if this is at fault, but would like to rule it out.
It only has pins on 3 sides, top and bottom has 5 each and left hand side has 6.
AI: It's a Silergy SY6982EQDC High Efficiency, 2A, Two-Cell Boost Li-Ion Battery Charger.
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H: What limits the maximum number of nodes of a RS422 bus? How to check if N>10 nodes is possible without repeater?
I have 13 identical devices which communicate with a host via RS422. None of them are addressable (they assume point-to-point connection).
I would like to string them in a RS422 bus. I thought of using relays and Chip Select signals to switch the TX+/- lines of the devices, however I am still facing the "maximum 10 nodes" limitation of the RS422 standard.
I read the limitation to 10 nodes may be extended on a case-by-case basis, but what does this limit depend on and how can I check my 13 devices may comply to the RS422 standard?
I need the full reliability of the standard, so I cannot "just test and see if it works".
P.S: For your information, the devices used are Maxon ENX EASY quadrature encoders with RS422 tranceivers implementing the SSI2 protocol.
AI: Basically the standard defines it, by specifying how much a single receiving unit can load the bus (with resistance and capacitance), and how much load on a singly-terminated bus a single driving unit must be able to drive. The numbers are just selected so that a standard driver can drive a singly-terminated bus with ten standard receivers. Sometimes modern receivers do not load down the bus so much so if it presents half a load then you can have 20 half-loading receivers.
Also the wiring capacitance and resistance loads the bus, so long wires limit the number of receivers too. To calculate this you need to know the capacitance of the wire.
But that only applies to the RS-422 drivers drivers and buses.
Not to SSI encoder devices, that utilize RS-422 standard, and further define how they use the RS-422 signaling. As devices, they are meant to be connected so that there is one bus master, and one encoder, and you can't change that.
Your encoder already incorporates a RS-422 receiver for the clock bus, and since the encoder is meant to be the single receiver at the end of a bus, it provides a termination resistor. So you cannot have multiple encoders connected to the clock bus, and no matter how you multiplex the bus to many encoders, the encoder has to be at the end of the bus wire.
Also the encoders have RS-422 transmitters for the data. They are always active, driving the bus - at least no SSI bus application note says otherwise. With RS-422, only one transmitter can be active at one time, and the transmitter must also be at the start of the bus to avoid signal reflections from stubs.
So clearly, the SSI encoders are point-to-point devices meant to be on the end of the bus, not in the middle.
If you do use for example relays to mux between encoders, either you have to have the relays at the master end, and from each relay you run a cable to each encoder. If you want to have one chain of encoders, you have to have a relay at each encoder to select if the bus goes to this encoder or if the bus continues to the next relay.
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