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H: Battery-Full indicator LED I am in need of your advice on a BMS design. I am designing a circuit which gets powers from battery or USB input (with Power Path management). After searching I found BQ24232 IC (http://www.ti.com/lit/ds/symlink/bq24232.pdf) will work for me. Here, I need to have an LED to indicate charging complete (Battery Full). The IC has a ~CHG pin which goes to VSS while charging and get high impedance when getting full, according to the datasheet. As the datasheet is only giving words on using it to indicate charging status,by connecting LED between output and this pin, I would like to know if this will work if I connect LED between this pin and VSS to indicate battery-full status. I will appreciate every single possible advice from you all. Edit: In summary, I need to understand what does this mean by "~CHG is high impedance when charging is complete". And how can I make use of this pin for Battery-full indicator LED? Thank you AI: You can connect it like this: simulate this circuit – Schematic created using CircuitLab The /CHG pin will sink up to 5mA with less than 400mV drop so it will definitely turn any LED off. Here Vusb is "IN" on the bq2423x (5V power from the USB bus). The /CHG pin is the drain of an N-channel MOSFET (source is grounded) so it either pulls the output low, or it is turned off and the output can assume any value of output voltage (from 0V up to the supply voltage of the chip). When the battery is charging the MOSFET is "on" and it shunts the LED, so the current flows through R1 to ground through the chip so the LED remains dark. When charging is complete the MOSFET turns "off", allowing the /CHG output voltage to rise to 2-3V depending on the LED, and the LED illuminates.
H: Are 1uF NP0/C0G capacitors different than regular 1uF capacitors? I am reviewing a schematic that contains several reference to 1uF 0402 SMD capacitors. Some of them are marked simply "1uF" and others as "1uF, NP0/C0G." I think both are the same. Is there any difference? AI: 1uF, 0402 size in NP0/C0G is not available: Per here http://www.avx.com/products/ceramic-capacitors/surface-mount/c0g-np0-dielectric/ C0G (NP0) is the most popular formulation of the “temperature-compensating,” EIA Class I ceramic materials. Modern C0G (NP0) formulations contain neodymium, samarium and other rare earth oxides. C0G (NP0) ceramics offer one of the most stable capacitor dielectrics available. Capacitance change with temperature is 0 ±30ppm/°C which is less than ±0.3% C from -55°C to +125°C. Capacitance drift or hysteresis for C0G (NP0) ceramics is negligible at less than ±0.05% versus up to ±2% for films. Typical capacitance change with life is less than ±0.1% for C0G (NP0), one-fifth that shown by most other dielectrics. yet: Features & Benefits C0G (NP0) formulations show no aging characteristics and have an operating temperature range from -55°C to +125°C Voltage Range: 6.3V to 500V Capacitance Range: 0.5pF to 0.1µF Sizes: 01005 to 2225 More: https://www.allaboutcircuits.com/technical-articles/x7r-x5r-c0g...-a-concise-guide-to-ceramic-capacitor-types/ Class 1 Caps As you may have noticed in the chart, C0G is extremely stable (note that C0G and NP0 both have a zero, not an uppercase “O”). C0G is a Class 1 dielectric and an all-around capacitor superstar: the capacitance is not significantly affected by temperature, applied voltage, or aging. It does, however, have one disadvantage that has become particularly relevant in this age of relentless miniaturization: it is not efficient with respect to volume. For example, if you go onto Digi-Key and search for a 0.1 µF C0G cap, the smallest in-stock part is a 1206. In contrast, you can find a 0.1 µF X7R cap in the 0306 package, and with a voltage rating (10 V) high enough for 3.3 V or even 5 V circuitry.
H: Finding Impedances on a Network Hey there the first part of the question (finding the new C value) is pretty easy. However I am stuck at the second part, it asks me to find the empadance values and etc. Can you help me with that? AI: simulate this circuit – Schematic created using CircuitLab If 10:1 probe sees Vab=0.2 then Vab=2V If V1=12Vp and Vab=2Vp then C1=71.4nF If C1=50nF then Vab=4Vp
H: What is the purpose of this AND gate in an audio amplifier I am analyzing the below audio amplifier circuit (from 4D Systems) and I am trying to figure out, what is the purpose of the positive AND gate (SN74LVC1G08) which connects to the audio input signal? Audio input is PWM format. AI: We can only guess, but it is most likely a buffer, both to speed it up and to reference it to the 3.3V supply going into L1. If I were implementing something like that, I'd make sure that the 3.3V supply was exceptionally clean, possibly even regulated from some higher voltage for no other purpose than to provide power for that AND gate. The reason for this is that the AND gate is essentially multiplying its supply voltage by the PWM -- that's why I'd make it clean, and that's why the circuit designer has put L1 and C27 in there.
H: How to run a 0.05A fan with a 10A source? I am constructing a circuit to drive a powerful LED that requires about 10 amps at 12V. I also have a battery that happily supplies that. For obvious reasons, that LED requires a cooling fan, and I've chosen one that takes 0.05 amps at 12V. How can I run this fan with the existing circuit? EDIT: I will probably be using a boost converter to control the current. It will be boosting from ~10V to the 12V required for the LED. I will also be using it to dim the LED. Specifications for the boost converter: Input: 8.5-50V, 15A max Output: 10-60V, 12A max AI: You just connect the fan in parallel with the LED, and it will draw 0.05A. You don't have to do anything to limit the current - the fan does that for itself. Edit: If your supply is 10V, it would be easiest to just connect the fan to the 10V supply. It's close enough that the fan should run fine.
H: Switch Individual Lights In LED Series I am working on a hobby layout that will have LED lighting for some of the elements. I would like to individually switch LEDs in series on/off. I used ledcalc.com to generate the circuit diagram below. I am stuck on if it is possible to switch one or more of the LEDs in a given series without affecting the LEDs that follow. For example, Lamp 1 below has on/off switch while Lamp 2 and Lamp 3 are always on. Lights would be common 5 mm LEDs if that matters. simulate this circuit – Schematic created using CircuitLab AI: Placing a switch ACROSS lamp1 will extinguish it when the switch is closed. The current in the "leg" will increase. You can design the cct so current is "somewhat low when switch is open and somewhat high when switch is closed so brightness is "much the same" overall. eg with 3V LEDs. If series R is 100 Ohms. 2 LEDS I = V/R = (12-9)/100 = 30 mA. 2 LEDS I = V/R = (12-6)/100 = 60 mA. You'll notice a 2:1 difference but it will not APPEAR to be that much. _______________________________________ Alternative - Use a SPDT switch and operate EITHER the LED or a zener of equal voltage. LEDS shown are example only. With eg 3V white LEDs I ~~= V/R = (12 - 9) /100 = 30 mA. Choose zener to suit LED. Zener voltage will depend on current. eg for a 2V7 rated zener, Vz is usually about 2V7 at 10 mA and somewhat more at higher currents. As jsotola notes - a resistor could be used in place of the zener. R = V/I = V_LED_replaced / Istring For white LEDs at Vf = 3V and 30 mA LED string current, R = V/I = 3V / 30 mA = 100 ohms So 3 LEDs have 100 ohms in series and 2 LEDS have 100 ohms in series. (Following that line of though 4 LEDS need NO Ohms in series at 12V BUT this is "not really so". The equation relies on Vsupply being exactly 12V and each LED having a Vf (forward voltage) of 3V at 30 mA. If that was exactly and always so then it would work. In practice the spread in LED Vfs and small supply variations would usually lead to "very poor" results. simulate this circuit – Schematic created using CircuitLab
H: How to design a snap/breakable PCB module? I am designing a board which can be snapped (a part of the PCB could be broken off if not required): Are there some design guidelines I should follow? What are the common rules (holes sizes and spacing) so the board can be snapped without too much strength but also not too easily? Also, I saw some examples that uses two lines of stamp holes (e.g. the board below). Are there some advantages of doing that (e.g. reduced mechanical stress) other than having custom spacing between the boards? AI: The method you show is known as "breakaway tabs" or "break-away tabs" or, more colloquially as "mouse bites". If you search for guidelines you can find some useful documents, and references to an international standard- IPC-7351. That's not a free document but you may be able to find copies floating about on the net. You want Figure 3.21 (break-away tabs) and 3.20 (V-groove scoring). They suggest, for a low-stress break-away, 5 holes per tab, 0.8mm diameter unplated, spaced 1.25mm apart, every 75mm along an edge with 1.2mm radius routed outlines. You can allow the routed radius to break into the holes.
H: JK flip flop not toggling when both inputs are 1? Instead of toggling, this circuit throws this error. What does this mean and how do I fix it? AI: Try this instead Notice there are 2 stages of latches to make the clock edge sensitive.
H: Art of electronics condensed Is there a book similar to the Art of Electronics but in a much more condensed form ? The Art of electronics seems more like a reference book with more than 1000 pages. Or anyone who has created their own summarised version which can be read online covering all the topics in the above book mentioned ? AI: Absolutely! Here’s the condensed version:
H: Why is this Verilog RAM modification better in terms of resource usage? I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm using as Video RAM for a VGA module): module text_ram #( parameter A = 10, parameter D = 8 ) ( input clk, input we, input [A-1:0] addr, input [D-1:0] din, output reg [D-1:0] dout ); reg [D-1:0] vram [0:(1<<A)-1]; // 2^A memory spaces of D bits initial $readmemh("lib/video.hex", vram, 0, 1024); always @(posedge clk) begin if (we) vram[addr] <= din; dout <= vram[addr]; end endmodule Analysing the resources with icebox_stat (alongside with all the other logic I have; sorry, but I don't know how to isolate the stats for a single component), it reports: DFFs: 21 LUTs: 204 CARRYs: 26 BRAMs: 3 IOBs: 4 PLLs: 0 GLBs: 3 Now, with this simple modification (which, granted, makes dout different, but ok for my intended purpose): always @(posedge clk) if (we) vram[addr] <= din; always @(*) dout <= vram[addr]; It reports: DFFs: 21 LUTs: 151 CARRYs: 26 BRAMs: 0 IOBs: 4 PLLs: 0 GLBs: 1 Not only it's 53 less LUTs, but what really surprises me is that the BRAM usage seems gone! Can someone please explain me why? Also, how can I inspect such cases to make sure I understand the underlying decisions of Yosys and NextPnr? AI: As Joshua says, something is clearly wrong here. The synthesis tool has clearly optimized away your memory. Having had a quick readup on the ice40 blockram it seems to have registered output, so making the output combinatorial would force the tool to use a big bunch of registers instead of a blockram. Speculating a bit here, but I wonder if readmemh only works on things that the synthesis tool was able to infer as blockram, and not on "big hunks of registers". Another possibility is you have forgotten to hook up some of the inputs and/or outputs properly. With the aggressive optimization that synthesis tools do, you can't really test resource usage without having a functional design.
H: Why doesn't KVL work for the bottom loop? I was doing a practice problem. I calculated the correct value for i_a = -2.4 A. But I used KVL on the bottom loop to get R, and got the inverse of the answer that I actually needed. My equation was -5ia - 6V + 18-6R = 0. There is no current flow from the current source above to the loop below. According to the solutions, I needed to use voltage division to get the correct answer, but I was wondering why is this the case? I could get the correct solution with current division but I don't get why KVL doesn't work for this loop. AI: My equation was -5ia - 6V + 18-6R = 0 The current through the unknown resistor is not \$6R\$, it's \$6/R\$. So you should have $$-5i_a - 6\ {\rm V} -\left(18\ \Omega\right)\left(\frac{6\ {\rm V}}{R}\right)=0$$ (I've assumed the blue probe of the voltmeter is the positive probe, because otherwise you're going to end up with a negative resistor value) (Also, notice that if you had included the units in your equation, you would have seen right away that you were adding a voltage to a term with units of \$[\Omega^2V]\$, so the equation can't be correct) You will get the same result by using the resistor divider formula $$ 6\ {\rm V} = -5i_a\frac{R}{R+18\ \Omega}$$ because the resistor divider formula can be derived from KVL and Ohm's Law.
H: Extension cord's power socket grounding pin soaked in cleaning agent sud, what is a proper way of cleaning? I didn't really know what tags to use. Anyways, this might sound stupid, however I was cleaning up something above the extension cord which was laying on the ground, and while I pressed the wipe suds and agent dripped into the grounding socket, nothing as far as I am aware. Now I don't know what can corrode and what can go bad, however this was a cleaning agent with the common Benzalkonium chloride 0.75g/100 g and among others: <5% amphoteric surfacatans, buthylphenyl methylpropional, Linaool, perfume. It is a pretty good surge protecting extension cord though, so I don't really wanna throw it. I am not sure how to "cure" it and what damaged I might've done. Few hours has passed and I haven't turned it on - although it is plugged at the wall right now. I cleaned it with a q-tip and a bit of water few times, the color is now gone when wiping, but of course a bit of the moisture went inside. It wasn't a terrible amount, more like few milliliters though. AI: It's probably fine as is, but to be sure: rinse with denatured alcohol, shake dry, and allow to sit in a warm place until the alcohol smell is gone (or mostly gone).
H: Lead-Acid Battery charger using LM350 and LM301 Given the circuit below, I want to discuss some issues concerning the way the circuit works. Here is the circuit: Let me report what is wirten in the handout: The circuit furnishes an initial voltage of 2.5 voltes per cell at 25C° to rapidly charge the battery. The charging current decreases as the battery charges. and when the current drops to 180mA, the charging circuit reduces the voltage to 2.35v, leaving the battery in a fully charged state. The LM301 compares the voltage across R1 to 18mv set by R2. The comparators output controls the voltage regulator, forcing it to produce the lower float voltage when the battery charging current drops below 180mA. The 150mV difference between charging and float voltages is set by the ratio of R3 and R4. The LED shows the state of the circuit. Let's take the case of a 6V battery. To charge that battery, usullay it is suggested to charge it with a Voltage around 7.5V (2.5v per cell as it is mentionned). LM350 or LM317 have a 1.25 voltage reference. So how do we acheive a starting charging voltage of 7.5V from this circuit (When I did my calculation I did not end up with 7.5v but more with Vref=1.25v and Iadj=50uA). The handout says that "LM301 Compares the voltage across R1 and R2", so the OPAMP here plays a role of a comparator (The output is either High or Low), am I right? In case I am right, how can this OPAMP be Low (sink current to allow the upper LED to be ON ) since its output (PIN 6) is taken form an emitter of a npn transistor (From the datasheet of the LM301). How does the PNP transistor contribute to the selection of charging voltage (2.5V per cell of 2.35v per cell) ? AI: the LM301 datasheet shows and Sziklai pair Q12,Q11 pulling down on the output via R10 and R11, it is these components that pass the bulk of the LED current when the output is low. the PNP transistor is controlled via the pair of 4.7K resistors by the op-amp that is cating at a comparitor, the trasistor is either off or fully conducting the 1.5K will pass about 10mA when 12V is selected or 5mA when 6V is selected , that will add about 1V or 0.5V to the voltage on the 100 ohm resistor, which itself lifts the whole LM315 regulator. (these figures are all estimations they are inaccurate but should be in the right ballpark.)
H: how can I calculate the smallest measurable voltage for a given adc? I have a project where I use 4 strain gauges in full bridge configuration with a hx711 module and an Arduino mini pro. How can I estimate the smallest voltage I can measure with a given adc from its datasheet, in this case the hx711 module? AI: $$ \frac {V_{in-max} - V_{in-min}}{ 2^{bits}} $$ or your noise voltage, whichever is higher. If multiple readings that should read the same are close together you have higher confidence. You will likely need filtering of some sort. Actually getting a 24-bit ADC to work to its full potential and output with a resolution of 24-bits is as an art.
H: Do I have match impedance while routing PAL video tracks? I am designing a PCB with PAL video output. PCB contains 50ohm and 100 ohm traces. The connection between RF coax connector is very close. So 75 ohm traces are 80 micron for my stack-up. I am confused whether to route them so thin track or not. Signal bandwith is 15MHz. Any suggestions? AI: A golden rule for deciding on whether matching impedances are required is that if the highest signal frequency (including relevant harmonics) has a wavelength of X then, the longest un-terminated signal track is X/10. 15 MHz has a wavelength of 20 metres so, you should consider using matching impedances and correct balanced routing (where applicable) if the connection length is longer than 2 metres. However, taking into account that the velocity of propagation along PCB tracks is about two-thirds of the speed of light means that the original 20 metre wavelength for 15 MHz (the maximum frequency) is reduced to 13.3 metres. Hence the golden rule suggests un-terminated tracks no longer than 1.33 metres.
H: What is the output in Figure 3-19(a) if the input voltage is increased to a peak value of 20 v? Will it be the same as if the input voltage is still 10 V? Or the zener diodes will breakdown (get damaged)? AI: The peaks will increase because real zeners are not "ideal" and have an internal resistance that causes a greater volt drop when conducting more current (due to the increased input voltage). The slopes will approximately double because the input waveform has doubled in magnitude. Or the zener diodes will breakdown (get damaged)? An unfortunate choice of words - a zener is said to breakdown when the reverse voltage exceeds the "breakdown" voltage. It doesn't mean it will break-down (like a car) and there isn't enough information in the question to ascertain if either zener will fail when the input voltage doubles.
H: Feedback resistors not connected to boost regulator I was using a TPS65131 boost regulator and accidentally forgot to add feedback resistor R3. I noticed that my output negative voltage was -30 volts. I realised that there was no feedback and added the resistor R3. Now, I am not getting any negative output voltage at all. Is there any chance that if feedback resistor is not added, the IC can get damaged? The components are added as per the datasheet for +-15 volts. AI: Is there any chance that if feedback resistor is not added, the IC can get damaged? Yes, it's quite possibly damaged: - The absolute limit of voltage difference between the incoming supply and OUTN is 24 volts so, if your incoming supply was 5 volts and you saw -30 volts at the neg output (possibly -30.5 volts at OUTN), that's a total difference of 35 volts and significantly greater than the allowed 24 volts.
H: Emulation in advance CPU Vs Native CPU My question is very specific but I might face difficulty framing it well so hope I dont get penalized. Background: Playstation 1, houses 32-bit RISC MIPS R3051 processor, running at 33.8688 MHz with 2 MB RAM, 1MB video RAM. The games targetted for this platform runs smoothly. On the other hand an Ingenic 32-bit XBurst MIPS processor runs at 600MHz, with 128MB RAM, and can support the games for Playstation 1 in emulation. Concern: Now both are MIPS processors, one running at 34MHz and other at 600Mhz, The Ingenic cpu with its specs is an overkill for PS1, however the performance of games running under Ingenic cpu, running embedded linux, is quite poor in various cases. Question: My question is, in such cases, does the performance depends on the fact that one is running an operating system with operating system overhead and the other running proprietary firmware? Or the fact that the emulation software has to perform dynamic runtime compiling which utilizes too much CPU time and hence result in poor performance? AI: Several problems here: 1) Speed of light and Causality A significant part of modern CPU performance comes from stuff like pipelining and branch prediction. For example it may take 4 cycles to execute one addition, but if the pipeline has 4 stages, it can still execute one addition per cycle, which multiplies throughput by 4. Great! ...Unless the next operation reuses the result of the previous one. Then causality dictates the next operation must wait for the result of the previous one to be available, which introduces pipeline stalls. The most problematic case of this is conditional branches. The CPU does not know if it has to branch or not until the condition has been calculated, so it has to wait. More pipeline stalls. An interpreter for any interpreted language needs to ... interpret ... the bytecode which will usually lead to lots of conditionals, switch-case statements, jump tables, etc. This is the worst possible code for any modern CPU which uses branch prediction because the same interpreter inner loop will interpret a different operation every time it is run, so the branch prediction will be wrong most of the time! Additionally, if the interpreter does not fit into the cpu instruction cache, then it is reeeeally going to suck, because a lot of these mispredicted branches will turn into cache misses and non-prefetched random SDRAM accesses which are slow as hell. Take-home point: modern pipelined superscalar CPUs are very good at data flow code (apply the same operation many times to lots of data), and terrible at control flow code (lots of tests, jumps, conditions, etc). The latter is a very hard problem, because the performance bottleneck is basically causality and the speed of light (propagation speed of signals), and that's not negotiable. This is why most CPU emulators recompile the original asm code into the destination cpu asm code... Even if the recompilation is done in a suboptimal way it will still be much better. Nowadays we'd use LLVM for that. But this is a problem for emulators designed before LLVM... 2) Custom hardware PS1 has a GPU which does polygon texturing, sprites and geometry, and a sound chip. These are programmable custom hardware. Emulating custom hardware is usually slow, in part because concurrent hardware processes do not map well to sequential software processes. For example hardware can quickly evaluate lots of flags, bits, compute bitwise operations with a bunch of logic gates, etc. Whereas software will have to run lots of tests and conditions, which brings us back to the point 1) above. Worst case, software has to emulate every logic gate one at a time and this will really suck. Also the geometry processor uses a non-standard fixed point format that is what you'd expect for optimized custom hardware of the era, and that a modern CPU cannot process without lots of bit-twiddling and contorsions... So you'll get code for "if the sign bit is 1 then..." making your math 10x slower (at least) and this cannot be translated into asm code for your CPU since it manipulates data formats that your CPU does not understand. And all this stuff runs in parallel, synchronized by electrical signals that will have to be emulated too! 3) Memory PS1 has RAM for the CPU, another RAM bank for the GPU, another for the sound chip, and each have various internal caches. Even if clock frequency is low, all that stuff can be accessed in parallel at the same time... with potentially lots of random accesses... and while modern DDR SDRAM is pretty good at sequential throughput, it still sucks, and will always suck at random accesses because of... you guessed it, speed of light. Commands have to go from the cpu, through a controller, to the SDRAM chips, be processed, come back... therefore, latency. So I wouldn't be surprised if the main performance bottleneck in your emulator was memory, in other words, cache size.
H: Why do I have to put my transistor after of my component, instead of before? I'm working on a very simple project, where I want to control a 24V LED with my arduino. Since the arduino can't output that voltage, I have a separate power source, and use a transistor. This allows me to use the 5V signal from the arduino to toggle the 24V. However, after wiring this all up, nothing worked, and after trying a few too many permutations, I also must've burnt my poor arduino. I later found an online circuit simulator, and eventually figured out how to get it working. But I have no clue why one of these ways works, and one doesn't. Here's the one that doesn't work. I placed the transistor before the the component (replaced here with a multimeter) and it only gets 5V. But this seems to be logical to me - 25V goes into the collector - 5V goes into the base. Base toggles emitter - and should be emitting 25V into the multimeter. Here's one that does work: Now, the transistor is placed after our component. We feed 25V directly into our multimeter, and it reads it as such. Then we use the 5V from our arduino to determine whether the circuits get completed or not. This works - and it makes sense that it does. But I can't understand why this works, and the last one doesn't. All it should be doing is opening or closing the circuit - yet that one gets 5V, this gets 25V. Can anyone explain what I'm missing? AI: I suppose you used an NPN transistor. To make an NPN transistor conduct from its collector to its emitter, you must apply a voltage to the base about 0.7V higher than the emitter. Look at this: simulate this circuit – Schematic created using CircuitLab The base must be 0.7V higher than the voltage applied to the LED. If the LED were to light up, it would have about 24V across it. You must therefore apply about 24.7V to the base of the transistor. But, the Arduino can only put out 5V, so the base never gets enough voltage to let the transistor conduct. Compare with this: simulate this circuit Now the base only has to reach 0.7V as the emitter is at 0V. That's easy to do with the 5V output from the Arduino. I left out a series resistor for the LED because if it is intended to operate on 24V it will already have some kind of current limiting built it. I don't know what happened to your Arduino. It is easy to destroy an IO pin with too high a voltage.
H: My cellphone is acting as an RFID tag? I bought a cheap keyboard emulating RFID (miFare) reader for my PC. I just noticed that the reader can 'read' my cell phone (Pixel 1 XL). Every read seems to return a different serial number. I can find much stuff online about using a cell phone as an RFID reader, but not much if anything about using it as an RFID tag. Where can I find more information on this number? Is this a TOTP? AI: This is the standard NFC implementation on cell phones. The number is effectively a nonce; randomly generated on each scan and made available to apps on the phone via software API. This is sufficient for most use cases: the connection to a user account is made over the internet based on the random nonce. This makes it difficult to track a specific phone, makes replay attacks difficult/impossible, and it makes it impossible to 'spoof' a specific NFC card.
H: Why pick 262144 Hz oscillator frequency? Some Bulova watches (for example the Precisionist collection) use 262144 Hz crystal oscillators instead of the usual 32768 Hz. What are the true advantages of this higher frequency, if they even exist? The usual quartz clock frequency is 32768 Hz because that's the lowest power of two above 20 kHz. This means the usual frequency is above human hearing range, but still allows ticking at one second intervals by simply dividing with 2^15. Bulova claims their ~262 kHz watches are an order of magnitude more precise (~10 seconds per year vs the ~15 seconds per month of standard quartz watches). Do higher frequencies really help with precision or is it just marketing? Their ~262 kHz watches also tick eight times per second. Many people enjoy this smoother motion, and it feels a bit more like a mechanical watch. But couldn't they achieve exactly the same effect by just dividing the usual ~32 kHz by 2^12? It seems like they chose to maintain the 2^15 divisor, for some reason. AI: As already commented, the accuracy doesn't depend on frequency. It does significantly depend on temperature. What Is ‘High Accuracy Quartz’? Most watches rocking a quartz movement are guaranteed accurate to around 15 seconds a month or so. This is still much better than even the best mechanical watches, but there’s a breed of quartz watches out there that can do even better: the High Accuracy Quartz (HAQ). HAQ’s still operate under the same principals as standard quartz movements, but they take into account the one major threat to quartz accuracy: changes in temperature. HAQ’s are, thus, thermo-compensated and can detect these changes and adjust themselves accordingly, which typically results in a guaranteed accuracy rate of around 10 seconds per year. Source: https://gearpatrol.com/2018/08/20/your-complete-guide-to-quartz-watches/ It's quite likely they used thermo-compensation, which has nothing to do with frequency. A drawback of a higher frequency is a higher power consumption. Their manual suggests the battery should be replaced each year which sounds frequent to me (I havent replaced the battery of my cheap watch the last 3 years).
H: Torque of motor vs operation as generator While trying to work out which motor to use for a wind turbine project, I'm coming across torque numbers for DC motors. I'm mainly looking at a BLDC motor right now. Clearly, for a smallish turbine that I'm aiming for, I'm looking for low startup torque. So, is there any relation between motor torque and/or wattage with its generator torque? Or more in general, how does one decide which motor is best for a given set of blades? AI: So, is there any relation between motor torque and/or wattage with its generator torque? Generally yes. To a pretty good first approximation, the torque that a DC motor gives for a given current is equal to the torque that same machine will need to absorb to deliver the same current as a generator. The biggest difference will be the machine's friction torque, which is always a loss either way. Clearly, for a smallish turbine that I'm aiming for, I'm looking for low startup torque. For an ideal DC machine, as long as there is no current, there is no torque. So in that sense "startup torque" is entirely under your control, or at least under the control of the electronics you use. Typically what's not ideal about a DC machine is the friction torque and cogging torque. These are often not well specified in datasheets (and aren't specified at all if you're buying a motor for hobbyist or consumer use, such as an RC plane motor). Or more in general, how does one decide which motor is best for a given set of blades? You find the speed and torque at which the blades are most efficient, and you find a machine that will absorb that torque at that speed -- or you choose to drive the motor through a set of gears (probably step-up) to spin the motor at a different speed, while absorbing the same power. Then you figure out the speeds and whatnot for when the wind conditions aren't ideal (most especially you check what happens if the turbine goes overspeed), and you deal with those.
H: How to use/create a real time clock to use with specialized? I want an accurate clock that will output a square wave that operates at 1 Hz. I need it to connect to a chain of binary counters. When the right binary number has been achieved the outputs will trigger AND logic gates to advances the count on the display. This would happen once every 86400 seconds (1 Day). I don't know if this means using an RTC but the ones I have researched are only connected to microcontrollers. I have tried using a 555 in astable mode but did not receive accurate results (I did not use a crystal). If anyone knows any way to achieve this, please let me know. Thank you. AI: CD4060 IC binary counter + Osc follow Xtal Osc design Use Q15 = divide by 2^15= 32,768 = 1 Hz Xtal 32,768 kHz + discrete RC parts or MEMS OSC XO 32.7680KHZ CMOS SMD more CD4060/4040's and gates to reset after output = 86,400 s 1 0101 0001 1000 0000 = 86,400 3V or 3.6V Li Ion
H: If you have multiple small pcbs in a single chassis, what is the naming convention for components? ie, on board 1 do you name resistors R1-R10, then on board 2 name them R1-R10 also? Or do you name resistors R1-R10 on board 1, R11-R20 on board 2, etc? What is the convention or best practice? AI: I've seen it done R100-R199 on board 1, R200-R299 on board 2 etc...
H: Getting several voltages from a single transformer I have a multi-tap transformer and I need to get two different voltage from the transformer, variable and steady. Is the below diagram correct, will it work this way? simulate this circuit – Schematic created using CircuitLab edit: simulate this circuit edit 2 (rewritten): I designed a digital linear CV/CC mini PSU 20V/1A based on LM317 series regulator. I'm well aware that linear regulators specially LM317 are not efficient, but since I'm not going to draw more than few hundred milliampere the heat and efficiency isn't really an issue. According to LM317 datasheet at 1 A voltage drop is going to be ~2.5 V. I am planning to use Schottky diodes for the bridge rectifier so I get half of normal diodes' voltage drop on bridge rectifier. I need a transformer at least 4 V higher than the maximum output (20 V) with four taps so I can use two relays and switch between taps to reduce the overall voltage drop on the regulator. Also LM317 needs negative voltage to be able to output 0 V therefore a -5 V would be enough. For powering MCU and fan and op amps supply I need another 24V which should be steady. The voltages that I need are: 8, 16, 24 V -5 V 24 V AI: simulate this circuit – Schematic created using CircuitLab Figure 1. This is OP's edited schematic simplified to show only two taps and the bridge rectifiers exploded into their individual diodes. An earth has been added to the bottom of the transformer as a voltage reference point. With the earth shown in the second circuit and the AC voltage frozen at V = -5 V and -10 V we can see a problem. D11 will be trying to pull the DC common line to -4.3 V (0.7 V diode drop) but D16 will pull it to -9.3 V. To repeat: You can't have a common on both sides of the bridge rectifiers. simulate this circuit Figure 2. A simple solution. SW1 represents the multi-tap selector. This solution uses half-wave rectifiers so the capacitors need to be a bit larger. Use one of the online calculators to check values. The permanent 24 V is taken from the topmost tap on the transformer. The negative rail is generated from the lowest tap on the transformer or from an independent secondary.
H: Which is better - components on both sides or components on one side of the PCB? I am working on a PCB design. 50k PCBs will be produced. SMD components: 100 Through-hole components: 25 I need to minimize PCB size. There are no high-speed signals or sensitive signals in the design. I have two options: Components on single-side PCB with multilayer (4 or higher) layout Components on both (double side) sides of PCB with 2 layer layout I need to clarify which costs less in production. AI: PCB size is not the only cost consideration and you need to consider recurring costs vs. one time (non-recurring) costs (some of the non-recurring may actually occur more than once for a 50k run). Note that using double sided techniques rarely (if ever) yield a PCB half the size of a single sided part - in my experience you may get one that is perhaps 40% smaller if it is given lots of attention. The non-recurring costs associated with PCBs includes the cost of tooling and the cost of solder stencils (which really are not that expensive although with a run of 50k you may need to use new ones after a certain number of runs which is very specific to the actual PCB). Also in this category is test tooling which does have a certain amount of volume costs (50k boards will require the test tooling to have a certain amount of maintenance). Another non-recurring cost is the fabrication and assembly documentation; poor documentation will incur recurring costs as you will be constantly fielding calls from the assembler and the specifics of the PCB may not be as controlled as you need. I suggest using the guidelines from IPC-D-326 (which incorporates IPC-D-325). Recurring costs are: Fabrication Number of layers Size (panelizing can reduce this depending on the specifics of the PCB) Number of drill holes (often forgotten but can be a major cost driver) Size of drill holes (to minimise costs keep the aspect ratio - the thickness of the PCB to the diameter of the drill - no higher than 8:1 and no smaller than 0.3mm) The quality of the material (in particular Tg) as identified from IPC-4101. If you have high via densities you will need a relatively high Tg or you risk breaking the via barrels; this is a very common 'gotcha' that can destroy yields at assembly (the bare PCB test will not pick this up as it will only show up post reflow - the time above Tg is critical). The PCB class (as identified from IPC-A-600) Assembly The assembly class as identified from IPC-A-610. The number of passes through reflow and perhaps in your case selective soldering; basically there is a recurring cost for each process step required. You should also keep in mind that if a cleaning process is applied, it will normally be done for each pass through soldering. The number of boards in a single panel; the more the better, in general (so you get more PCBs through for each process step although pick and place will have a higher cost but that is usually small compared to the gains from fitting more PCBs per panel). Component density has an impact here as well; there will inevitably be some waste of components (usually the smaller parts) and the higher the density the higher that waste is typically. Testing. An automated test will have a non-recurring cost for the implementation and the lowest possible recurring cost (apart from no test at all). In terms of cost, it increases as you go from automated -> unskilled test labour -> skilled test labour on a per unit time basis. There are other issues but these are the main ones in my experience and there is no single (or simple) answer; it depends on the specifics of your PCB. In the past where I have had the space for a single sided unit I have had the design done for both single sided and double sided design (incurring another non-recurring cost at the design stage) for high volume applications and sent both for quotations and the result can often be quite surprising. In one case (where the design was always going to be double sided due to space constraints), the overall cost of fabrication and assembly was lower (by about 20%) when I increased the layer count from 14 to 18. This significantly reduced the via count and eliminated high aspect ratio drills (the lower layer count had aspect ratios of up to 12 - the higher layer count maxed out at 10) and had the serendipitous effect of enhanced signal integrity (as I was able to use single layer routing for the majority of high speed signals). [The methods required to run high speed signals across multiple layers while minimising losses is beyond the scope of this answer - suffice to say they are quite involved and use up more space than would otherwise be necessary]
H: Does the CircuitLab simulation ignore OpAmp power rail current? After I saw lots of simulations with CircuitLab here I subscribed today. And then I tried to simulate a simple circuit with an OpAmp which did not work as expected because I could not "measure" the current on the voltage rails of the OpAmp. I simplified the schematic and here it is. When I simulate it the current on RL is between 0 to 15mA and the voltage between 0 and 3.5V. So far ok. But if I measure the current on the OpAmp + and - rails the current it 0. I would have expected that the current on the positive rail is the same as the outgoing current. What is wrong here? Does the CircuitLab simulation not work with this OpAmp (from their list) or does the current simulation on the OpAmp rails not work with any OpAmp or do I do something wrong here? simulate this circuit – Schematic created using CircuitLab AI: I think CircuitLab doesn't simulate the power draw by the opamp (neither for the output, nor for the quiescent current needed by the IC innards). The reason for this, I guess, is that LM324 is a jellybean part, made by a handful of manufacturers, so if you truly want to simulate, you would need to specify exact part number and manufacturer, not just "LM324". If you go that direction, then it's probably best to use the manufacturer's SPICE models for that opamp, even though I'm not sure if they simulate the quiescent current as well, but it's more likely that they do. E.g. I just tried similar to your schematic in LTspice and it seems they simulate the power rails, I was able to measure the current going in the opamp.
H: Output drop/change in linear circuits Lets say I have a linear circuit with some input and output voltages. Assume this is a block with inputs/outputs. When I connect input of another block to the output of my first block, I observe that my first output will change but I don't want it to change or I want to be able to foresee this change and interfere beforehand to sustain my second block with that original output signal. What can I do about it? AI: Do you mean "change level slightly" or "change state"/ change excessively compared to expectation. The first is a natural consequence of applying ANY load to ANY source - how much the change is depends on source and load impedances. Simplistically Vout = Voc x Zload / (Zsource + Zload). If this is unacceptable then feedback will allow "zero" change or (as Andy says) a buffer with lower Zsource can be used. In logic systems these are designed to allow a certain number of loads to be connected without taking performance outside specification. The number of standard loads that can be accommodated is termed "fanout". In analog systems it's up to you to design to suit your need. If a load causes a source to change state or to change "too much" then "you are doing something wrong" - the circuit needs to be properly designed.
H: How does negative feedback reduce noise? It is a well established fact that negative feedback improves a lot of parameters related to amplification. Effect of negative feedback on some of the factors such as gain, input and output impedances etc. can be found by mathematically solving some practical circuits, but I could not find a suitable explanation for the noise reduction caused by the negative feedback. Can anyone give me an intuitive (or mathematical) idea as to how the negative feedback helps in reducing noise? Edit: Excerpt from Boylested's book on Electronic Devices AI: Feedback reduces all types of errors introduced by block "G" in the schematic above, including noise. However, all feedback does is minimize \$ \theta_e \$ which does not reduce noise or other kinds of errors (offset...) from the input stage (represented as a substractor on the schematic). This has practical applications in opamps for example, if you want to pay more for low-noise transistors, they have to go in the input stage. 1/f noise in the rest of the circuit will be reduced by feedback. So when saying "feedback improves characteristic X" it is important to keep in mind what is "characteristic X" and to what part of the circuit it applies.
H: High frequency filter circuit design I am a trying to design a design an Electrosurgical interference suppression (ESIS) protection layer to filter out high frequency noise caused by Electrosurgical equipment during surgery. I am using ADAS1000, an electrocardiogram AFE. I understand inductors can be used to block certain frequencies in a circuit. My question is how do I go about designing a circuit to block 100kHz-5MHz noise on a electrode?( Single conduct line) AI: Assuming you want to measure cardio signals with a flat gain/phase response to 300 Hz and > 100 dB attenuation on signals from arc noise from Electrosurgery > 100kHz. I would chose RLD, STP cables ,active CM shield with CM chokes this attenuates by balancing the input signal to cancel mutual coupling of high stray E-B fields [V/m, A/m] If your noise is less , pls specify. I chose a 6th order RLC 10kHz filter, This would be differential "Pi filter" for differential signals with SMD Chokes with SRF assisting with attenuation. Show below as single ended. Simulation More practical L Values
H: What is the purpose of coating around heating element in soldering airgun? I have disassembled my SMD reworking airgun (to determine the cause of a 5-E error) and in aigun I have found a paper-like coating wrapped around the heating element that totally crumbled to dust and little pieces when I touched it. What is the purpose of this coating? Could I use the aigun without it or I will get some problem? AI: Mica sheets are used as electrical insulators for heatsinks , heater guns and microwave ovens , maybe (salvage) from old toasters It prevents the body plastic from melting and is rated by thickness. The heater coil also has high AC voltage on it. Looks like you cooked it maybe by blocking the intake air or cheap quality inadequate thickness. Good luck.
H: Frequency Domain Analysis with Transistors I have some doubts about how some circuits with transistors are described in electronics textbooks. Let's see an example (taken from Thomas H.Lee, The Design of CMOS Radio-Frequency Circuits). This books (and all other books I have read about circuits with transistors) uses a convention in which signals in time domain are indicated with small letters. So for instance iout = iout(t). Let's consider this example with a Small Signal Mosfet model with parasitic capacitances: The book considers the situation in which a current source iin is put at the input of the Mosfet, and tries to evaluate the current gain. The result of the analysis is this one: You may see there is the variable ω, which is due to the presence of the capacitances. My question is: how can be this analysis correct? It is a time domain analysis, so it is not correct to say that the voltage drop on a capacitance is 1/jωC * current: we should use integrals. I think the previous relationship is true only if we indicate with \$i_d\$ and \$i_{in}\$ the fourier transforms of the drain current and input current. But they have been defined as time domain signals. The book goes on and uses also equations like that of the drain current of a MOSFET in saturation (\$i_d = k(v {gs} - v_t)^2)\$ and always in time domain. How can this analysis be correct? I'll replace all these signals with their Fourier transform: is it true? AI: Yes, the book is playing a bit fast and loose with conventions -- but because they're conventions and not hard-and-fast rules, you need to just roll with it and try to understand the author's intent. That expression is calculated in the Laplace or Fourier domain, to find the response of the circuit to sinusoidal signals in steady-state. So by that measure, and by "normal" convention, the author should have used \$I_d\$, \$I_{in}\$, etc. However, the notation above is practically a convention in itself for this sort of circuit analysis so -- roll with it.
H: What is the charger voltage graph while charging Lithium battery with CC/CV approach? What is the voltage graph from the point of view of the charger while performing a CC/CV charging? Isn't a "Dedicated Lithium Ion CC/CV charger" simply "a Constant Voltage DC Source with Current Limit" (like we use in labs)? Looking closely to the CC/CV transition of the graph, there is a sharp turn in the battery current¹. If the internal resistance of the battery is not changing that sharp - which I think it's not the case -, this is a good indication of a sharp voltage change on the output of charger. It might be quite possible that the charger exceeds the CV value right before the CC/CV transition point to keep the current constant, and then, lower the output to preserve the required CV level. Is there any point in the charging process that the output of the power source exceeds the CV limit in CC stage? Edit (Conclusion) Regarding the answers, IMHO, the "CC/CV" declaration for the battery charging process is quite misleading by definition. "Constant Current" term leaves the terminal voltages undefined by definition. However, according to the answers, it is defined and can not be greater than CV limit at any point during the charging process. IMO, it would be clearer if it was defined as "CV+CL (current limit)" for the charging stage. ¹: It was because of the two capacitors in the equivalent circuit model. AI: Looking closely to the CC/CV transition of the graph, there is a sharp turn in the battery current. If the internal resistance of the battery is not changing that sharp - which I think it's not the case -, this is a good indication of a sharp voltage change on the output of charger. The charger is connected directly to the battery, so their voltages are always equal. In the CC phase the battery controls the voltage as it charges up. The charger merely responds by raising its voltage to keep the current going. If you compare the battery voltage curves during CC charging and discharging, you will see that they are almost a mirror image of each other. That is because in both cases the battery's voltage is determined by its state of charge (with a slight difference due to voltage drop across the battery's internal resistance, which is positive during charging and negative during discharge). At the CC/CV transition there is no change in charger output voltage, which then remains constant in the CV phase. At this point the charger is controlling the voltage, by decreasing charging current to prevent the battery voltage from increasing. It might be quite possible that the charger exceeds the CV value right before the CC/CV transition point to keep the current constant It shouldn't. The charger may need to produce a higher voltage internally to overcome resistance in its components and wiring, but it should not exceed the CV value at the battery terminals. Is there any point in the charging process that the output of the power source exceeds the CV limit in CC stage? No. Power output is maximum at the point where both current and voltage are maximum, which is at the CC/CV transition.
H: 1V voltage reference and temperature coefficient There are precision 1V voltage references like ADR510 which I don't have access to, though I do have LM385 1.2V, LM336Z5 5V and the famous TL431 at hand. The easiest solution is to use a voltage divider: simulate this circuit – Schematic created using CircuitLab But using voltage dividers is not temperature coefficient, in page 6 of LM336 datasheet there's a schematic which claims: If minimum temperature coefficient is desired, four diodes can be added in series with the adjustment potentiometer as shown in Figure 2. When the device is adjusted to 5.00V the temperature coefficient is minimized. Almost any silicon signal diode can be used for this purpose such as a 1N914,1N4148 or a 1N457. How diodes makes above circuit temperature coefficient? How do I achieve a temperature coefficient 1V voltage reference? AI: There are two questions: 1) About diodes and temperature coefficient: the p-n junction in conduction state has voltage drop about 0.5V...0.8V, and - what is interesting, temperature coefficient of this drop is near constant and equal -2.2mV/K (without valuable dependency on current and voltage drop). This -2.2mV/K coefficient is the result of some physical properties of junctions based on silicon. So, this coefficient is very frequently used for compensation of temperature drift, because it is well defined. 2) About drift of 1V reference voltage: it depends on type of IC, used as reference: each IC type has own temperature coefficient - you can find this in reference data of this IC. For example, LM385 is very well compensated in temperatures about room temperature (25 Celsjus degrees), and - in typical applications - don't need additional compensation. If you need better compensation, there is no universal rule for all cases. You need always start with checking manufacturer's recomendations, very often placed in application notes. For example, TI in his datasheet shows precision 10V source built on LM385 (Fig. 17 in http://www.ti.com/lit/ds/symlink/lm285-adj.pdf).
H: Detecting switch closure Any techniques/circuits/sensors that can determine the open/closed state of a set of contacts, independently of whatever power or signals are being switched by the contacts? Obviously easy if there's no or a known load; but (for example): three NO switches in series switching 120 VAC to a bulb.. what black box circuit could be connected across each set of contacts and measure the state of each switch? Ultimately a logic-level output for a uC, and don't need a fast response time (under a second is fine). Edit: let's assume a few mAs of leakage ok, and a power load: DC-60Hz, < 250v. AI: The AL5890 from Diodes Incorporated offers some interesting possibilities. Figure 1. A simple 2-pin constant current LED driver from Diodes Inc. can handle a DC input up to 400 V. The AL5890 is available in pre-fixed regulated current ratings of 10, 15, 20, 30 and 40 mA. It supports either high-side or low-side driving and is intended for use with LED lighting chains. simulate this circuit – Schematic created using CircuitLab Figure 2. An AL5890 in series with an opto-isolator across each switch should allow monitoring of each contact on a DC circuit. simulate this circuit Figure 3. The AC version requires a bridge rectifier on each switch. I haven't checked the details on this. The AL5890 have a maximum power dissipation and so the current goes down as the voltage goes up. In your application you have to assume worst case which is all switches closed except one, so full mains voltage would be across that. Check to see if this can be accommodated with a single LED as the load. If this circuit works your monitoring circuit would need to check for pulses from the opto-transistors as the AC voltage rises away from the zero-cross.
H: Basic understanding of Voltage drop What is the second/lower 15 k-ohm resistor for? I understand why there is a 12 k-Ohm resistor in the top, that's for the V-out. But why is there a 15 k-Ohm resistor in the lower right? Why would you need to make a voltage drop on the path back to the battery, isn't that just waste of energy? AI: What is the second/lower 15 k-ohm resistor for? I understand why there is a 12 k-Ohm resistor in the top, that's for the V-out. The arrangement shown gives \$ V_{OUT} = \frac {15}{12+15}9 = 5 \ \text V\$. But why is there a 15 k-Ohm resistor in the lower right? You wouldn't need it if the load required 5 V and was exactly 15 kΩ. This could be the case in some situations. In many cases you might not know the load impedance or it could change somewhat from device to device so it makes sense to make a divider using known resistor values to drive the following circuit. Why would you need to make a voltage drop on the path back to the battery, isn't that just waste of energy? If the 15 kΩ resistor was not there then VOUT would be 9 V as there is no current flowing so there is no voltage drop across the 12k resistor. When current is drawn from VOUT the voltage drop will vary with the current. This may not be desirable. All current must return to the battery in any case. Yes, energy is consumed and no, the circuit is (hopefully) performing a useful function so there is a benefit to the energy cost. From the comments: But why is Vout 9V without the 15 k-ohm resistor? simulate this circuit – Schematic created using CircuitLab Figure 1. With a very high input impedance voltmeter (10 MΩ, say) so little current will be drawn that there will be no voltage drop across R1 so the meter will read 9 V. I thought that the Vout is only dependent on the 12 k-ohm resistor, as Vout lies above the 15 k-ohm resistor, and current flows from left to right and then down and back to battery? What you are writing is that, the Vout is also dependent on the lower resistor, even though Vout lies just above it. How can that be? Perhaps the easiest way to imagine this is to consider a potentiometer. simulate this circuit Figure 2. Various configurations of voltage divider. In Figure 2a we have added a GND point from which all voltage measurements will be taken. We have combined your potential divider into one resistor, R1: 12k + 15k = 27k. It should be clear that the voltage reading at the bottom of R1 will be 0 V and at the top will be 9 V. In Figure 2b we have replaced R1 with a potentiometer R2. I hope that it is clear that the voltages at the bottom and top are still 0 V and 9 V respectively. The wiper on the potentiometer is shown in mid-position. Q: What do you think the VM2 reading will be? A: 9 V / 2 = 4.5 V. As the wiper runs from bottom to top the VM2 reading will increase linearly from 0 to 9 V and will be 9 V times the ratio of the lower resistance divided by the total resistance. \$ V_{OUT} = \frac {R_L}{R_{Tot}} 9 \ \text V \$. In Figure 2c we have replaced R2 with R3 and R4 which are in the ratio 12k:15k which is 4:5. This is equivalent to having the wiper of R2 at 5/9 of the way towards the top. From the previous paragraph we can see that this should give the result \$ V_{OUT} = \frac {R_L}{R_{Tot}} 9 = \frac {5}{9} 9 = 5 \ \text V \$.
H: How to choose the series pass transistor? I plan on using the LT3080 to regulate a variable 1-36V 7A DC power supply. This regulator by itself will not provide more than an amp or so, so I will have to use an external series pass transistor per the recommendation in their datasheet: Now, I am sure this will work fine, however the recommended BJT is expensive, something like $7 a piece. Given I am planning to make a few of these regulator boards, I would like to keep the cost down by choosing a comparable part. This is where I need help. On Mouser I see plenty of PNP BJTs that support 100v emitter-collector, and 10s of amps for 60 cents, but I don’t know if that will work. So what parameters should I be looking for in the datasheet that would be suitable in this application? It would be great if you can also explain why this part was chosen in the first place and why it is more expensive than other seemingly similar BJTs. AI: Power dissipation ,Current ,Voltage and Safe operating Area .On the Ap note circuit life is good because the input /output differential voltage is only 2V7 so power wasted is manageable with the Husky MJE4502 on a heatsink .You want to increase max current by 40% Which is not a show stopper .However your expected input /output differential will be more than 36V .This will call for many Power devices in parallel .Your Calculated Heatsink will have to be much less than 1 Kelvin per watt which as a rule of thumb it wont be easy .Consider reducing your input volts .Prebuck works well for me .Some large off the shelf linear lab power supplies have automatic relays that step the tapped transformer secondary windings to save heat by keeping input /output differential volts not too high .
H: Solving CMOS logic structures Can somebody please help me with understanding how to derive the equation from the red box from included picture (the other equations are trivial, it's just the right usage of De'Morgan's law)? I am able to derive the equation for the NMOS device thanks to this video: https://www.youtube.com/watch?v=CoTR3bwtW_c , but not for the PMOS one. Can You, please, explain how to do it step-by-step? On the upcoming test we will probably have something more complicated, so the more I understand the better. Also, I don't know what should I do with more complex circuits, especially with PMOS. Unfortunately, my lecturer didn't explain this good enough... What about something like this? (I came up with this by myself, so I don't know if it is even doable, so please excuse me my lack of knowledge, I am still learning; L is the output) AI: The PMOS turn on when the voltage is low. So you have a pull up network with two parallel legs. The first leg has two transistors in series, which means that both need to turn on for the output to be pulled high. This is your \$\bar{A}\bar{B}\$ term. The second leg has a single transistor. This is your \$\bar{C}\$ term. Because they are in parallel the pull up network will pull the output high, if at least one of the legs is active. Hence \$F = \bar{A}\bar{B} + \bar{C}\$.
H: Effect of lower voltage supply in flash circuits Let's consider this circuit which represents the internal structure of a flash for a generic camera. enter link description here Here my reference guide. Usually in an external flash there are 4 aa batteries with 1.5V, so a total voltage source of 6V. Now let's suppose to use 4 aa rechargeable batteries, which are of 1.2V. The flash works also in this situation (with 4.8V of total voltage source), but which may be the effect of this variation? Does it mean less maximum light emitted by the flash? I'd say that lower voltage mean lower maximum light emitted by the flash, but same recycle time (since the time constant depends only on the capacitance and the resistance). AI: There is no standard stating how a manufacturer must or should implement a flash charging system. However, my experience from many years of using many camera flashes of a wide range of energy outputs, and with a wide range of AA cells, rechargeable and primary, is that in all cases The flash will not fire until the internal "reservoir capacitor" is at a certain level (shown by a "ready" indicator lighting). Lower capability batteries increase the time taken to reach this level (as you'd expect), and that Flash brightness is independent of the battery state EXCEPT in full manual mode - see below. Use of lower voltage cells with high discharge current capability will often result in faster recycle times than higher voltage cells with lower discharge capacity. For example, a good NiMH 3000 mA cell will provide up to about 10A when fully charged, falling to a few amps towards the end of its capacity. Primary cells vary with type and brand. A good AA Alkaline cell may approach a good NimH cell initially but fade more quickly. A modern camera will utilise the battery available discharge rate over a range of battery voltages. eg typically from about 4V to 7V+ for AA cells. When carrying out extremely flash-intensive high shooting rate photography (eg on stage dancers or similar) I usually choose Alkaline cells and discard them when the recycle time becomes excessive. This is usually in <= 100 flashes - depending on ambient light and distance to subject which affects energy use. I use Alkalines cells NOT due to their energy capacity but because NimH or Alkalines come out of the flash at well over 60 degrees c in those circumstances. Alkalines can be discarded in a safe place 'on the spot' rather than having to juggle 4 'red hot' NimH cells. All properly engineered flashes use the energy required to implement the desired exposure and, if there is charge remaining, terminate the flash cycle and retain surplus energy for subsequent use. This allows either a single flash that consumes all available energy (eg manual 100%) or multiple lower energy flashes if the system so dictates. A flash will often continue to top up the internal capacitor above a certain minimum level once the "ready" indicator illuminates. This allows multiple flashes of less than 100% energy. Specifically: Does it mean less maximum light emitted by the flash? No. It results in longer time to recycle. I'd say that lower voltage mean lower maximum light emitted by the flash, but same recycle time (since the time constant depends only on the capacitance and the resistance). Not in any example that I have ever seen over many years EXCEPT when the flash is set to Manual mode and all available energy is expended by the user as soon as the flash allows. In those cases only, a higher recycle rate at lower intensities is possible. Most modern flashes, apart from very low cost ones, have one or more automatic modes as well as manual mode, and most users use the flash in automatic mode almost always.
H: Synthesizing this simple analog notch filter? I want to synthesize this simple analog audio filter which is a notch: The inductor with resistor creates a simple one-pole low pass filter with the cutoff frequency at: fc = 1/(2pi L R) The capacitor with the resistor creates a one-pole high pass filter with the cutoff freq at: fc = 1/(2pi C R) So is synthesizing this circuit as simple as just running the input through both filters and summing it together? ie. onePoleHPF.setFreq(1/(2piCR)); onePoleLPF.setFreq(1/(2piLR)); output = onePoleHPF.process(input) + onePoleLPF.process(input); Or is it not really that simple? Do I need to "weight" their contributions or gain scale them somehow to ensure I'm not adding gain at any overlapping frequency? If so, in what proportion? Like output = onePoleHPF.process(input * 0.5) + onePoleLPF.process(input * 0.5); I think one of these two approaches is correct because parallel elements share the same voltage across them so I think the input voltage is just split 50/50 between the two pathways. Or will this not work and I need to create a completely new filter to get the right output? If so, how would I get a transfer function to make this work? EDIT this is inserted after I got an answer from user287001: The answer was what I needed. The principles I used come from: https://www.dsprelated.com/freebooks/pasp/String_Excitation.html. If I have two resistors in series of identical impedance at that point instead of one resistor (more accurate for my simulation) like this: (Sim from https://www.falstad.com/afilter/) Then the equation becomes: \$V_o(s) = V_i(s) * \frac{2R}{2R+\frac{1}{\frac{1}{sL} + sC}}\$ Substituting \$s = \frac{1-z^{-1}}{T}\$ where T is the sampling period and having Wolfram Alpha simplify: \$V_o(z) = \frac{2 R V_i(z) (C L z^{-2} - 2 C L z^{-1} + C L + T^{2})}{2 C L R z^{-2} - 4 C L R z^{-1} + 2 C L R - L T z^{-1} + L T + 2 R T^{2}}\$ Multiplying both sides out I get: \$2CLRV_o[n-2] - 4CLRV_o[n-1]-TLV_o[n-1] + 2CLRV_o[n] + TLV_o[n] + 2RT^{2}V_o[n] = 2R (V_i[n-2]CL-2CLV_i[n-1] + V_i[n]CL + V_i[n]T^{2})\$ Then to isolate for \$V_o[n]\$: \$V_o[n] = \frac{2R (V_i[n-2]CL - 2CLV_i[n-1] + V_i[n]CL + V_i[n]T^{2}) - 2CLRV_o[n-2] + 4CLRV_o[n-1] + TLV_o[n-1]}{2CLR + TL + 2RT^{2}}\$ Does that look correct? Thanks a bunch. AI: Sorry, but it's wrong. The current through L depends on what's gone through C, it cannot be divided to 2 independent circuits like you have done. It must be calculated all parts together. You should use a software function which lets you input the right transfer function. Start by learning to do the analysis manually to find the right transfer function. Understanding phasor calculus with complex numbers and s-domain impedances are the basics. I guess you need the notch filter functionality to process signals, not a simulation of the drawn LC filter. I'm sure the filtering is possible more effectively by using filter synthesis methods for DSP without dragging along L nor C. ADD: A comment shows that the guess was wrong. The circuit can be worked as a voltage divider, but the upper resistor is replaced by L and C in parallel. Here's the transfer function, simplify it algebraically to the form that you can input. If it happens that you cannot cope with impedances sL and 1/sC, you have several months of studies in front of you or you must get an electrician to assist. ADD2 after the question was augmented: For me z=exp(sT). Your version z=1/(1-sT) can probably be used in some cases. I'm not so good with z-transforms that I can say what errors you introduce. It's a kind of first order approximation and it can work if T<<1/(2Pi*signal frequency).
H: Please identify diode This is a diode for a 9500-HBE Dock. I can not seem to be able to identify it. It's connected to the DC jack. Thanks for your help. AI: It is the SMBJ10CA from Diodes Inc, a transient voltage suppressor.
H: Which IPC standard we should follow? Our PCB designing team is of 5 members and we want to incorporate IPC standards in our designs from now on. We deal with a single-sided layer to 18 layers of PCB. We are into digital, analog, RF and mixed designs. We mainly want to use standards for Schematic designing, Footprint creation, and Naming conventions. What standards do we need to study and follow? AI: Although a lot of standards exist, not all of them are suitable for everyone; that said, some of them are extremely useful. IPC-7351B is used for footprint creation (and many implementations permit adding height dimensions allowing tools to export to files suitable for mechanical analysis to ensure everything fits within a particular housing - this ability has saved me a lot of trouble a number of times in the past). This standard also has a footprint naming convention that reflects the physical characteristics of the device. Implementing this standard is very useful when using external fabricators and assemblers (the usual state of affairs for smaller companies) as all can agree on pad sizes and so forth for various devices. There are standards for schematics although the only one I have used (and it was contractually required because those projects were for a US govt agency) is the IEEE STD 91 for logic symbols. Most places I have been at developed schematic and signal naming conventions internally to meet their own needs and as such there are many ways to do this, but some things are pretty much agreed as you can see from this canonical answer. For PCB and assembly documentation, I personally suggest (and myself use) the guidance from IPC-D-326. Whatever you use for signal and component naming needs to be consistent so don't have both TR and Q for transistors (both of which are widely used); use one or the other or people will become confused (a situation I have seen on occasion). The same rule goes for IC and U (both widely used for integrated circuits). There are many ways to implement net naming conventions, but the key is that they should a) be descriptive and b) be short enough to be readable. As an example, some packages accommodate bars over \$ \overline {signal names}\$ although the same can be achieved with text (such as a trailing # symbol) for negated signals. There is no single correct method. Your outputs are perhaps the documents where standards matter most (because that information will go elsewhere if you sub out the assembly and fabrication). Most of the better contract manufacturers and fabricators will accept ODB++ format. It has advantages over the multiple file approach of gerbers, pick and place files and drill drawings as all the information is in one place. That is not to say that using the gerber approach is wrong; it is simply a different method of getting the information necessary to your suppliers. For any drawing (schematic included) I would suggest you will always need blocks for the project name, sheet name, company name and (should you have or need one) a CAGE code. There should also be a revision block with entries for the revision ID, implemented by, checked by and authorised by names. Be liberal with free text to explain things that may not be obvious (without making the sheet unreadable). Anything beyond that is going to be based on experience and opinions so I am not going to go there. The overall message is that the documentation needs to be easily readable and complete for all the design documents. Most IPC standards cost money (some are free) but there are many online resources that cover what is in them. IPC-7351 compliant footprint generators in particular are often bundled with CAD tools. You can find an explanation of what it is here.
H: Autobias Vbe with output current sensing this is a question about analog audio amplifiers and automatic regulation of the output stage bias circuitry. I basically need to implement an autobias circuit on this output stage topology: As you can see, it's a very simple and classic output stage, the entire amplifier is a classical three-stage: input, VAS and output. The target, is to use one o more transistor to sense the current flowing in the output transistor and regulating the bias accordingly. Obviously, without using thermal compensation and putting the Vbe transistor on the heatsink. I found on Douglas Self's book "Audio Amplifier Design Handbook (6th ed)" a circuit capable of doing it: He use a differential to regulate the current of Tr13, but I can't understand what is V_Ref. Can you help me to understand how this circuit works? And how to implement this on a common amplifier output stage? AI: The important thing to understand is that "dynamic bias" gimmicks are mostly useless. Let's do a simulation: "V4" is a voltage source which drives this output stage. I've replaced the CFP lower transistor with a darlington, besides that it should work like the original. The diff pair Q15,Q16 compares the voltage on emitter resistors R16,R17 with reference V3. I labeled both emitters e1,e2 on the schematic so the voltage between them is v(e1,e2). I set reference V3 to 66mV, R16+R17 in series make 0.66 ohms, so we have idle current of 100mA. The output of this diff pair drives Q13. When v(e1,e2) is too high relative to desired bias voltage V3, Q13 conducts more and shunts some current, discharging C4, which reduces v(e1,e2). When v(e1,e2) is too low, Q13 conducts less, thus voltage on C4 increases, also increasing v(e1,e2). This works nicely until a load is connected to the amplifier and it draws enough output current to pull the amp out of class A. As long as output current is low enough to stay in class A, that is as long as both both output transistors conduct, then this scheme will keep v(e1,e2) constant as desired. This would make it pretty good for a pure class A amplifier. However, when output current exceeds what class A can provide then one of the transistors will turn off, and voltage on the other emitter resistor will increase as current increases. Say Q9 turns off, then v(e2)=v(out) since there is no current in R17, and all the output current flows through R16. If output voltage increases, and output current increases, then v(e1,e2) will be greater than the reference voltage... and Q13 will turn on hard, discharging C4. Since C4 can only charge through current source I2, until it is charged again to the desired bias voltage, the amp will be underbiased and run in class B, producing huge crossover distortion as shown on the simulation below: Curves from top to bottom: Input and output voltage (showing crossover distortion) Emitter current of both output transistors. At the beginning, they are biased at 100mA each without signal. v(e1,e2) is the voltage on both emitter resistors v(c4) is the bias voltage ie(Q15) and ie(Q16) are currents through the diff pair... it does clip... ie(Q13) is the current through the shunt transistor Q13, which becomes quite chaotic as soon as output current exceeds Class-A current... In other words, this would work for class A, but definitely not for class AB, so unless you want a space heater this is only for headphone amps... I'm sure Self mentions this, right?
H: Quantization results in harmonics in ADC FFT plot This is taken from Analog-to-Digital Conversion by Marcel Pelgrom. Okay, I understand that with 1-bit quantization, the output is block-wave (Square) and that of course when you do the Fourier Series, has harmonics. That makes sense. What I don't understand is, how come when we go to higher quantization bit levels (2, 3, 4, 5), the harmonic power decreases? I mean there is still square/block waves asssociated with those, just with smaller jumps. TLDR: Why does increasing number of quantization bits, decrease the harmonic power? AI: The total quantization noise is proportional to the difference between the fundamental or original waveform and the quantized one. The more steps, the likelier one can get a closer fit or approximation to the waveform. So the jumps are still there and will still produce harmonics, but there is less energy available for the jumps to put into the spectrum which those jumps produce, as more of the energy is in the better approximated fundamental. Conservation of energy, or Parseval’s theorem limits the total power.
H: Making a 64 pin breakout board, looking for help with best practices and any glaring design errors. First design in a few years Long time lurker first time poster. I am making a breakout for a MCU we want to prototype with and I was curious if there are design rules I should follow for these. The datasheet for the MCU says "0.1 µF ceramic at each pin plus bulk capacitor 1 to 10 µF" for each power pin. But since I am tying all the power pins together can I get by with one or two bypass caps and a bulk cap? I have attached images of my board layout and the datasheet section in particular. Please ignore the silkscreen I am working on that last once placement of parts is done. https://i.stack.imgur.com/bN5sI.jpg AI: Generally looks ok, and welcome :) Few things: Make sure all your pin headers are on 0.1" spacing. Even if you're not putting it on a breadboard, this will make sure any header cables will fit nicely. See, for example, the 3 little connectors toward the bottom left. The component to the top right seems to have a trace going from a via through the ground plane to the bottom pad. This doesn't seem to be on the same net as the plane, so could be a short. Each power pin on the MCU package must have a capacitor on it, usually 10-100 nF will do. Use as small a component size as you feel comfortable soldering. Put a 10 uF for each supply voltage where it comes into the board. This is very much rule of thumb, but should get you started! Some of your trace bundles could be tidied up. For example, the bottom right one has the right most trace going out to the right then down. If you went down first to meet the other traces in the bundle, the ground plane can fill in to the space. The bottom left one is nice.
H: Nor gate using photodiodes and transistors doesn't work correctly I'm creating a circuit for a robot to avoid obstacles. It is created without using any ICs. When the robot meets an obstacle the LED (at the right side of the transistors) should be off because of V_CE is 0.7V and voltage barrier across the led is 1.5V. My problem is when the robot meets an obstacle it just reduces the light intensity of LED. It means that my logic gate doesn't work correctly. What is wrong with my circuit? I need to give the output into the opamp. AI: I've drawn your original receiver stage on the left, and an improved one on the right. A photodiode generates current proportional to the light impinging on it, plus a bit of leakage current (called "dark current" in the datasheet). A transistor will pretty much amplify any base current -- so the circuit on the left will always have some collector current, and in the case of a photodiode that always has some light on it, it will be difficult to control the on/off switch point. In the circuit on the right, R5 will consume some of the current from D2. This will hold the base voltage of Q2 down. Then you can select R5 such that the base voltage of the transistor hits 0.6V at roughly the light level you want to sense. With carefully controlled lighting, this may be enough to make things work for you. Note that I suggest that if you use this circuit, you make R5 adjustable -- I'd suggest an audio taper pot, because those are roughly logarithmic (see my comment to this answer for my reason). simulate this circuit – Schematic created using CircuitLab
H: Using a depletion mode mosfet as a current limiting device I have recently discovered the exciting world of depletion mode mosfets. Curiously, even in this document, I found nowhere that a depletion mode mosfet could be used as a current limiting/inrush current limiting device. But this is strange, because what prevent us to use them like this: or like this (with a suitable heat sink of course) ? To put flesh on bones, I have built a 800V, 10-20 mA PSU. I have a IXTY01N100D depletion mosfet, with 1000V breakdown voltage and 400mA current. It is not so easy to build a conventional inrush current limiter at this voltage. I wonder if I can use this transistor to limit the inrush current in the filtering output cap. AI: It should work. It's a common use for depletion FEts and several examples in the document you linked to use them as current sources. Respect the Safe Operating Area though: You can also make an AC current limiter with two depletion FETs:
H: Can LM339 comparator inputs go way above Vcc? The datasheet for the LM339 quad open-drain comparator shows the absolute max values: \$V_{cc} \le 36V\$ (Supply voltage) \$V_{I} \le 36V\$ (Input voltage range (either input)) I want to compare a (fairly weak, 100k impedance) \$0V\$ to \$+15V\$ input signal against a \$+3V\$ reference, while powering the device from a \$+5V\$ supply. According to the spec, that should be fine. However, I'm surprised and wary, because it's common that device inputs can't go much above the supply rail. Then again, I can imagine comparators being unusual in this respect, and if that were the case here, I'd expect to see the input defined as \$V_{I} \le V_{cc}+0.6V\$, or similar. Have you used an LM339 like this, and was it fine? I've been looking for a circuit diagram of the internals of the device, but I'm struggling to find anything that makes it crystal clear. I don't want to find out in a year's time that we're gently destroying them! AI: "Absolute maximum ratings" are about not destroying the device. "Electrical characteristics" or "Recommended operating conditions" are about proper functionality. For example, a supply voltage of zero volts is perfectly safe (well within maximum ratings!) but of course the device won't operate... So, your voltage seems allowed by max. ratings, but will the comparator compare? "Electrical Characteristics" in the datasheet: There is fine print: What's important is "will provide a proper output". Some comparators/opamps will misbehave or reverse the output if input voltage is outside correct operating conditions (but still inside maximum ratings), for example. In this case it will work. Datasheet page 13 confirms: Most likely the internal transistors (highlighted in yellow) have been designed to have quite high Vebo rating, so the b-e junction doesn't break down under such high inverse voltage. Usually discrete BJTs have Vebo around 6V so the b-e junction would break down and avalanche around 6V when reverse biased. Also there are probably ESD protection diodes from inputs to GND, but not from inputs to positive supply.
H: SNR vs SINAD/SNDR This is from Analog-to-Digital Converison by Marcel Pelgrom He defines an approximate relationship between Signal to Quantization Noise Ratio (SNQR or just SNR) and number of bits as: The author then uses this later on, How does he replace SNR with SINAD in 5.13 to get the ENOB equation? Aren't they different? AI: SNR and SINAD perform a similar function. SNR is Signal to Noise ratio. When considering a perfect quantiser, it's a good measure of how much noise is introduced by the quantisation steps. SINAD is Signal to Noise and Distortion. Distortion is caused by a non-linear converter. Its effect on the signal is to introduce other tones that should not be there, in other words, energy that is not part of the wanted signal. Noise and distortion are lumped together as being energy that should not be there. ENOB, or Effective Number of Bits, is generally used to get a measure of how imperfect a signal converter is, so generally uses SINAD rather than plain SNR. However, these are approximate figures, and there's little point getting picky about them if the actual performance of a converter matters to you. If it matters, you'll specify it and measure it for exactly the performance you need. The only two classes of people who would want to get picky about exactly how ENOB is calculated are (1) Picky people who like a fight and (2) Marketting people from converter brand A who want their ENOB to be 0.1 bits better than the converter from brand B.
H: LTSPICE P-Channel MOSFET I'm learning LTSPICE and am very confused by the results coming from playing around with P-channel MOSFETs. I created a very complete test of P-channel and N-channel MOSFETs, and all the N-channel results make sense to me, but can someone please explain what's going on with the P-channel? M1 behaves as a forward biased diode with a voltage drop of about 0.105 V (seems small but believable). M2, which according to my understanding of P-FETs should behave like a closed circuit, behaves virtually identically to M1. M3 and M4 are also identical, and the results are: M4, which is likely the most useful configuration, has a waveform that makes sense, but the numbers don't make any sense. Shouldn't this work as a switch, meaning that the voltage should go between roughly 0 and roughly 20, not 19.898 and 19.895? (R_ds,on = 0.035 ohms) And M3 is the same - is that okay? Lool I was fighting with a more complicated simulation all day and finally decided to go back to the basics, and now I'm just more confused... AI: Shouldn't this work as a switch, meaning that the voltage should go between roughly 0 and roughly 20, not 19.898 and 19.895? If you want to switch the PMOS off, you need to drive the gate very close to the source. So you need the pulse amplitude to be ~20 V, rather than 5 V. As it is, you are only testing the difference between the transistor being very strongly "on" (\$V_{gs}=-20\ V\$) and being just slightly less strongly on (\$V_{gs}=-15\ V\$). To put the MOSFET into cut-off mode, you want \$V_{gs} > -0.3\ V\$ (based on the datasheet minimum \$V_{gs}({\rm th})\$).
H: Stability of SMPS designed for a motherboard Many books have covered the stability of many configurations of switch mode power supplies and they have given details on how to set the poles and the zeros of the compensator to make the the power supply more stable and robust, but all the books I have undergone, they took the example of the load to be a resistance load. My question is, if we want to design a more practical SMPS to feed a more complecated and realistic circuit (example of a motherboard of an airconditionar, mobile phone etc.) these circuits are a combination of resistors, inductors, capacitors, actives devices and so on. How do we study the poles and zeros of the power supply in that case? And how to make it stable? AI: Are you asking about a SMPS that will power a variety of loads (motherboard of an air conditioner, mobile phone) without changing any of the design? If so, I don't think such a design exists. The closed loop performance of a power supply (PS) is closely tied to the load it has to drive and the resultant feedback that has to be implemented to ensure the power supply meets all it's performance requirements such as regulation, over current/over voltage protection, good behavior at startup, etc. Therefore most power supplies have to be tailored to their loads. Our power supply group designs SMPS's for many different applications (loads). The design for a digital system with a relatively constant load is a lot different than the design for the transmit portion of a radar with hundreds of amps of load current being required at the radar's PRF (Pulse Repetition Frequency), 100 Hz to 50 kHz, for instance.
H: FFT of a square wave I'm generating a square wave as PWM whose frequency is set to 25 Hz. On the oscilloscope, I've got: The data referred to the image above was stored and maniputed, then I plot it using jupyter notebook, as shown below: Applying the FFT to that signal,I've got: The main question is: wasn't the main peak (the 2.7 V) supposed to be near 25 Hz? UPDATE: I just did the corrections that you tell and the visualization is better! I'm still obtaining the main peak in 0 Hz, but the second harmonic is in 25 Hz ( but the amplitude is low). I also didn't get the 13 V dc offset that Chris pointed out. UPDATE 2: I subtracted the average dc level (1.35 V) from the signal as most of you told me and I got the result I believe it's correct now: AI: Your signal is a square wave with its base at 0V and its peak at 2.7V or so. So it has an average voltage of 1.35V. In the frequency domain, the overall average of a signal is its content at DC or 0Hz -- so that's why there's a peak at 0Hz. The FFT of a square wave that is centered on 0V has energy at every odd harmonic, starting at 1. So there's energy at 1f, 3f, 5f, etc.
H: Is this how a R-2R DAC for VGA should work? I'm trying to wrap my head around if this is how a R-2R DAC should work. I say should for two reasons: (1) because I think I understand the theory behind the resistor ladder of subsequent voltage-dividing, and (2) because I analysed the schematic of a common VGA Pmod from Xilinx, which I would expect to be, well... correct... So, let's start with the circuit: With all bits on, this achieves a ~0.7V max, considering the 75 internal impedance of a VGA monitor. Now, I've broken down all the possible combinations and the resulting voltage: ... which, suffice to say, is not what I expected how this should behave. A perfect DAC would be linear. A gamma-corrected VGA DAC would possibly be a curve. But these deltas are all over the place. So here are the questions: (1) am I interpreting something wrong? (2) Is this how this type of DAC supposed to work? (3) How can we improve over this design? AI: The bits you control are either On or Disconnected, while in general a R2R DAC input would be connected to 3V3 or 0V. Disconnecting changes the impedance. Try with SPDT switches.
H: Is a pull up/down resistor really necessary? Logical reading (1 or 0) of a micro-controller input GPIO pin may float if it is neither connected to VCC nor GND; someone said it is because of surrounding RF interference. When a floating GPIO input pin voltage is affected by RF interference that makes it fall in the undefined logical range (i.e. 0.8V - 2.2V for Raspberry Pi), it can cause the logical value of a floating pin to change. I wonder if this problem could be solved by how a microcontroller is designed. i.e. Enlarge the logical voltage range, say <6V for low >6V for high. Since interference may seldom reach such high level voltage. AI: tl;dr increasing IO rail swing has drawbacks, and also doesn't help because static charge can still swing to either rail. To start, there are tons of practical reasons why we don't just increase I/O voltage. It's not as simple as some guy crossing out 3.3v on a piece of paper and writing 12v instead. Modern CMOS processes for processors are designed to create thin gate oxides for fast, low-voltage devices. The processing steps needed to grow a thick gate oxide would be both costly and adversely affect performance and yield. The nice thing about a lot of cheap ICs is that they have a simple process--a 3v3 chip might have all gate oxides grown to withstand 3.3v+safety factor. You've now introduced multiple new masks (plus photoresist and etching steps), perhaps doubling or tripling the price of the chip. Likewise, power dissipation for high-speed circuitry would be an issue. Especially for fast signals, high voltage swings imply high power dissipation (on the order of voltage squared) due to capacitances and series impedances. Additionally, if you must maintain your core at 3.3v to remain within a power/thermal budget, you'll need to add level shifting, which itself generates additional heat, consumes additional power, and causes users to incur additional costs. Your thresholds are also fairly arbitrary--a sharp 6V threshold requires a voltage comparator, which leads to its own instability problems in case of certain feedback structures that could very well arise on a floating pin. For a reasonable I/O buffer, the threshold is going to be a reflection of the gate threshold voltages of the transistors in the buffer, which ties back to our manufacturing limitations. You run into the same shoot-through problems, but they're worse now since the region where both FETs are on is wider thanks to the higher rails, and the supply voltage is higher leading to yet more power dissipation. You've made the issue worse rather than better. Now, with all of that said, simply making I/O thresholds higher isn't going to fix the issue of floating signals. Given the amazingly high resistance of the gate oxide, a floating pin can easily reach 6V--especially given that there's a >6V rail nearby! When all of this is said and done, we've delayed chip production by a year while we develop fabrication processes and establish contracts to do mixed-voltage systems with both high-performance cores at 1v2 and 12V I/Os. We've pushed our power budget up, meaning that we must buy more expensive heatsinks and fans, as well as larger batteries and power supplies, and we also haven't reliably fixed the issue. Or, you could buy a tape/reel of 10000 pullup/pulldown resistors for $10 on DigiKey, or for less in Shenzhen. More likely than not, your PCB manufacturing partner already has some standard pullup/pulldown resistor on hand, loaded in their pick-and-place machines, and ready to be placed. Or, your chip might already include pullups/pulldowns, since those can be fabricated fairly easily on some processes using weak MOSFETs.
H: Counter Circuit starts from wrong number in Logisim I'm trying to design a synchronous counter using J-K, T and D flip flop. It should count as "1, 3, 0, 2, 7" and 1 respectively. Everything works fine, i designed flip-flop tables and input-outputs etc. but it starts from 0 and goes like 2, 7, 1, 3 and 0 respectively. I'm trying to find out my error but i just couldn't realize the error. AI: I understand you want to power-up with 1 (0b001) as the initial output. There is more than one way to do this, but probably the easiest for me to explain here is to configure your J-K flip-flop as a toggle type (TFF), just as you appear to do in your schematic. (I'll also include the DFF table, because it appears you are supposed to use one.) Here's the table: $$\begin{array}{c\|c\|c\|c\|c} \text{State} & \text{Next} & \text{TFF}& \text{DFF}\\\\ {\begin{smallmatrix}\begin{array}{cccc} Q_C & Q_B & \overline{Q_A}\\\\ 0&0&1\\ 0&1&1\\ 0&0&0\\ 0&1&0\\ 1&1&1\\\\ 1&0&0\\ 1&0&1\\ 1&1&0 \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{cccc} Q_C & Q_B & \overline{Q_A}\\\\ 0&1&1\\ 0&0&0\\ 0&1&0\\ 1&1&1\\ 0&0&1\\\\ x&x&x\\ x&x&x\\ x&x&x \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{cccc} T_C & T_B & T_A\\\\ 0&1&0\\ 0&1&1\\ 0&1&0\\ 1&0&1\\ 1&1&0\\\\ x&x&x\\ x&x&x\\ x&x&x\\ \end{array}\end{smallmatrix}} & {\begin{smallmatrix}\begin{array}{cccc} D_C & D_B & D_A\\\\ 0&1&0\\ 0&0&1\\ 0&1&1\\ 1&1&0\\ 0&0&0\\\\ x&x&x\\ x&x&x\\ x&x&x\\ \end{array}\end{smallmatrix}} \end{array}$$ The above table should be pretty easy to follow. The left column just shows the current state of your TFF outputs. The next column show you the next state that you want. The third column shows you which of the FF will need to be toggled (0 in the positions where there is no change in the bit value and 1 in the positions where there is a change.) The fourth column is really just a copy of the second column, except that the \$Q_\text{A}\$ isn't inverted. There are then three TFF K-map tables drawn from the third column above: $$\begin{array}{rl} \begin{smallmatrix}\begin{array}{r\|cccc} T_C&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\ \hline \overline{Q_C}&0&0&1&0\\ Q_C&x&x&x&1 \end{array}\end{smallmatrix} & \begin{smallmatrix}\begin{array}{r\|cccc} T_B&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\ \hline \overline{Q_C}&1&1&0&1\\ Q_C&x&x&x&1 \end{array}\end{smallmatrix}\\\\ \begin{smallmatrix}\begin{array}{r\|cccc} T_A&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\ \hline \overline{Q_C}&0&0&1&1\\ Q_C&x&x&x&0 \end{array}\end{smallmatrix} \end{array}$$ There are also three DFF K-map tables drawn from the last column above: $$\begin{array}{rl} \begin{smallmatrix}\begin{array}{r\|cccc} D_C&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\ \hline \overline{Q_C}&0&0&1&0\\ Q_C&x&x&x&0 \end{array}\end{smallmatrix} & \begin{smallmatrix}\begin{array}{r\|cccc} D_B&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\ \hline \overline{Q_C}&1&1&1&0\\ Q_C&x&x&x&0 \end{array}\end{smallmatrix}\\\\ \begin{smallmatrix}\begin{array}{r\|cccc} D_A&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\ \hline \overline{Q_C}&0&1&0&1\\ Q_C&x&x&x&0 \end{array}\end{smallmatrix} \end{array}$$ Just skimming over the above tables, I'd use the DFF for the high order bit and use the JK and the TFF for the lower two order bits (doesn't matter which is which, since the JK is operated as a TFF, anyway.) You'll need two AND gates and one NOT gate to get it done if you follow the above advice. As it appears you have succeeded, here's the schematic I might try:
H: Energy dissipation of a resistor in an AC circuit I am given a resistor of known resistance with a sinusoidal voltage across it, and am asked to calculate the energy dissipation between t=0 and t=1. Not sure how to do it. Would I Use P=V^2/R and integrate between the limits to calculate energy dissipation or Calculate voltage at t=0 and t=1, then use P=V^2/R? Thank you for your response. AI: Calculate voltage at t=0 and t=1, then use P=V^2/R? Nope, power (or voltage) at t=0 and t=1 gives no information about what happens between t=0 and t=1. Use P=V^2/R and integrate between the limits to calculate energy dissipation Yes, you have to calculate \$ Energy = \int_{t=t_0}^{t=t_1} power dt = \frac{1}{R} \int_{t=t_0}^{t=t_1} v^2 dt\$ Also \$ P_{avg} = \frac{Energy}{t_1-t_0} = \frac{1}{t_1-t_0} \int_{t=t_0}^{t=t_1} \frac{v^2}{R} dt = \frac{1}{t_1-t_0} \frac{1}{R} \int_{t=t_0}^{t=t_1} v^2 dt\$ \$ P_{avg} = V_{rms}^2/R\$ with Vrms being the RMS (root mean square) value of voltage. \$ V_{rms} = \sqrt{ \frac{1}{t_1-t_0} \int_{t=t_0}^{t=t_1} v^2 dt }\$ If you combine these two equations you will end up with the one on top using average power. When an AC voltage (or any periodic voltage) is considered, its "RMS voltage" is the DC voltage that would result in the same dissipation in a resistor.
H: Application of Frequency Response Theorem in Linear Circuits One of the most important results of control theory for linear systems is the so called "Frequency Response Theorem" (here the references): Briefly, it says that under the hypotesis of stability and linearity, if the input signal is sinusoidal, the output signal will be the original sine with phase and amplitude variations respectively equal to phase and amplitude of the transfer function of that system. Now, let's consider for instance a RC low pass filter: The output signal will be like this: So, it is not sinusoidal, although both R and C are linear components. Where is the mistake? AI: The problem is that you statement: "The output signal will be like this:" is rather wrong. What you have shown there is the output of a rectifier circuit. I don't know where that came from but it is NOT the output of the given circuit. You get that output waveform if you replace the R with a diode, but in that case you no longer have a Linear Circuit.
H: ESP32 Dev Board DTR/RTS I recently got an ESP32 development board. I also found the schematic to this board online but I got an question. Can someone explain to me, what this part of the circuit is doing? Schematic: https://dl.espressif.com/dl/schematics/ESP32-Core-Board-V2_sch.pdf AI: EN is enable... Or nrst pin. IO0 is a boot mode pin. When the esp32 chip exits reset, it samples io0 and if it's low it will enter programming mode. This enables the dev board to reset the board and automatically select the correct values for those pins when programming. See: https://github.com/espressif/esptool/wiki/ESP32-Boot-Mode-Selection
H: Fine, coarse adjustment digitally I want to add fine and coarse adjustment to a power supply for both voltage and current control, for fine tuning I'll need four potentiometers either 10 turn or regular ones. I was thinking to trim two of this pots to reduce the cost and space and I came up with this idea: simulate this circuit – Schematic created using CircuitLab Basically converting an 8 bit PWM to voltage and using it as voltage reference, above circuit is the same as this one: simulate this circuit And the problem with above circuit is; if we set the coarse pot to output it's maximum voltage, it's like the coarse pot isn't in the circuit anymore and therefore we can't get any fine tuning. In this question @Spehro Pefhany suggested a voltage divider "network" for coarse and fine tuning. How can I combine digital(DAC) and analog(POT) to achieve coarse/fine tuning? AI: Fine, coarse adjustment digitally? Do both in one simple digital to analog interface The simplest method to control Voltage and current limit is to use an analog Vref derived from a DAC output with say 8 bit resolution for 256 levels. Define the digital interface for convenience, too many ways to mention; Serial Async - Tx only or with feedback UART with 1 byte for voltage and 1 byte for current limit followed by using Serial Data & Clock on 2 ports, a serial DAC Serial Sync - Clk+data depends on distance, speed and resolution use a SIPO register to discrete R-2R DAC Here an 8 bit DAC simulated with a clock and counter , add a unity gain Op Amp buffer and choose the terminator R to scale down the Vmax range. You may easily Slider change the value in this browser based Simulator. Analog The concept of two pots for coarse and fine must be done in series , not parallel unless they are bufference to prevent short circuiting each other in parallel. Often a fixed R is put in series to limit the tuning range. For coarse, fine the total resistance defines the load and the chpice for fine tuning % determines it's value. e.g. 1k:100R or 1M:50K for 5% fine tune range. simulate this circuit – Schematic created using CircuitLab
H: Can an instruction set do everything? Given a certain instruction set, and that any high-level code is just converted to machine code anyway, then except simulating human intelligence, is it sufficient enough to do anything you want a computer to do? For example, can the instruction set of the Arduino be used to generate high definition graphics on a modern computer monitor and play games? Why or why not? *Note: I mean the Arduino instruction set only, not the board itself. AI: Once a programming language is 'Turing Complete', it can be used to emulate any other language. The only difference is then speed. The instruction set of all MCUs is Turing Complete. It couldn't really be otherwise, they would not work as MCUs if they were not. The provision of more instructions above the minimum needed for Turing Completeness makes the compiler easier, and the program faster. For instance you could do everything with a load/store to a single accumulator. However, being able to do arithmetic between several registers allows faster code. According to this wikipedia page, a properly chosen single instruction can give you a Turing Complete machine. However, trying to program such a machine is really an exercise in what's theoretically possible, rather than having a useful MCU.
H: Does the Shockley Ideal diode equation involve drift current? I've encountered a contradiction in semiconductors. The ideal diode equation considers saturation current (the current when applied voltage is reverse biased to the diode). I thought that saturation current was due to drift. However, on the other hand, the derivation of the Schockly ideal diode equation assumes no drift current in the transport equation. See here: https://www.pveducation.org/pvcdrom/solving-for-quasi-neutral-regions Where is my misunderstanding? AI: Saturation current is diffusion current, not drift. It is minority carrier diffusion current.
H: N-MOSFET switching behavior when turning off I am switching a 1 Ohm load with an N-channel MOSFET, which is driven by a TC4420 driver. The load is three Arcol HS50 330 mOhm resistors in series, the power supply is a 3S LiPo battery. The switching frequency is 1kHz with 10% duty. I am trying to understand what is happening in the circuit when the FET is switching off. I started with this: This is the waveform in this case. Channel 2 (blue) is just the signal generator output, Channel 1 (yellow) is Vds, channel 4 (green) is the battery voltage, measured on the main battery wires (if I measure it through the balancer connector, the shape of the waveform is still the same, with smaller amplitude): First I thought the huge peak around 55V is the avalanche breakdown of the FET, due to the load and the wiring having some inductance, followed by some ringing for the same reason plus the FET output capacitance. But then why is there that big rise on the battery voltage? This implies to me that current is flowing into the battery, which I really do not understand. Then I tried adding a flyback diode: Which resulted in a bigger battery voltage rise, but not much otherwise: To eliminate the ringing, I added a snubber circuit (without the previous flywheel diode): This was quite effective regarding the ringing: So I tried with both the snubber and the diode: With the same additional results as before (bigger battery voltage rise, and nothing else): So my question is basically what is happening here? More specifically: What causes the voltage rise on the battery, when I do not expect the current flowing back into the battery? Why does the avalance happen regardless the presence of the flywheel diode? (Maybe this is some other phenomenon, not avalanche?) AI: You have a massive loop inductance in your measurement set-up: - I've tried to indicate that with a green dotted line showing the loop. I estimate that loop inductance to be about 1 uH. If I simulate a 1 ohm load in series with 1 uH I get this: - Vin (red) is the gate drive voltage (fed via a 10 ohm resistor but could be made much worse by having long leads as indicative of the set-up picture). Vout (blue) is the drain voltage i(R1) is the current through the 1 ohm load I'm using an IRFZ44N MOSFET by the way - the same as shown in the OP's circuit diagrams. But then why is there that big rise on the battery voltage? Because of bad probing techniques and an ill-defined 0 volts node (also with series inductances). Just look at the grey left-most probe tip connected to the red lead from the battery - that probe earth point is back close to the source of the MOSFET but, there's a hundred mm (or more) ground wiring back to the battery negative terminal so, it's impossible to conclude that there is any movement on the battery voltage at all. Everything need to be ten times closer to make any sense of o-scope readings and even then, there'll be ringing and inductive artefacts present (but smaller). And, I haven't modeled the inductance of those power resistors - you can get low inductance versions of those resistors but you appear to be using the standard parts and the data sheet doesn't give any indication of the inductance for those parts unfortunately.
H: Cause of systematic offset in operational amplifiers I have some doubts about the systematic offset problem of an op amp. Here (slide 15) it is quite well explained: Briefly, it is due to the fact that Q6 and Q7 may not be crossed by the same current. But there are two things that I do not understand: 1) I have also been told that the offset is due to the mismatch of the main transistors of the differential pair. Is this mismatch linked to the current mismatch of Q6 and Q7 shown by the previous slide? 2) How is it possible that Q6 and Q7 are crossed by different DC currents? The load is assumed to be an infinite impedance and the only path between Q6 and Q7 goes across a capacitor Cc, which is an open circuit at DC. In my university course I have also used this schematic for an op - amp: This schematic is similar to that shown in the initial slide, with the difference that now there is a third stage which is a voltage amplifier. Let's zoom on the second stage (which is the cause of the systematic offset): The current that flows in M7 and M12 is the same: and it is obvious because there are not other paths for DC current! But there is a small DC offset in output (116uV) when DC input values are 0. This seems to be in contrast with the definition of systematic voltage given in the previous slide. AI: I think you should make a distinction between what I would call "balance" and "offset". In my view your circuit actually doesn't have any Offset! All transistors are all perfectly matched and identical, or exactly 10 times wider if W is 10 times larger for example. Offset is a statistical effect that is the result of small variations between transistors (and other components). You usually simulate this using a Monte Carlo simulation and for that also statistical models are required. Balance is the result of the circuit, for example making sure that the input differential pair transistors (M1 and M2) are identical in size and have a identical operating points meaning the same \$I_D\$ but also the voltage must be the same. If that is the case (and it looks like it is in your circuit, at least in the input stage), your circuit is balanced. The 2nd and 3rd stages in your opamp both add a very large amount of gain (I would never do that, chances are this opamp will be unstable when feedback is added) because these stages are all "current into a high impedance point" amplifiers. So even the smallest imbalance is amplified a lot. Even small numerical rounding off of the simulator could show up this way. My guess is that the 116 uV you see is caused by this. I would just ignore that 116 uV and consider it to be zero. Also I would suggest to limit the number of "current into a high impedance point" amplifier stages you have now as these WILL get you into trouble. That's my 25 years of design experience tip :-)
H: RC circuit with current and voltage source I am once again stuck on a task. The circuit initially looks like this: And the question is: So my attempt: The first thing that came up in my mind was that the switch had been closed for a long time. That made me think that initially the capacitor behaves like an open circuit. So I redrawed the circuit like this: Where Vc = Vab So I thought that I could find Req and find Vab through the voltage divider. However there are two things that makes it difficult form the to continue: The question states that when t = 1 μs then the switch opens, but the plot of Vc(t) should be from 0 I don't know how I should consider the current source. Most problems that I solved have either had a current source or a voltage source. How should I look on the circuit when I have a current and voltage source? Thanks in advance! Edit: Here is my new circuit after some help, however on the final state I am uncertain if the switch should be open and the capacitor not acting like an open circuit? : AI: I'm assuming that the current direction of the current source is as shown below: - I don't know how I should consider the current source. Most problems that I solved have either had a current source or a voltage source. How should I look on the circuit when I have a current and voltage source? My preference is to make the voltage source \$V_A\$ into a current source but first... Your redraw is correct but there's one more thing you can do. R1 (in series with the current source) has no effect on the circuit because it is purely in series with a current source. It's the same for resistors in parallel with a voltage source - they do not affect the voltage source and can be turned into open circuits. In R1's case it becomes a short circuit. Then, turn \$V_A\$ into a current source of 6 mA in parallel with R3. Do you see what I did here? The effective series combo of 6 volts and 1000 ohms become a current source of 6 mA in parallel with 1000 ohms. So now you have R2 \|\| R3 being fed by a current source of 2 mA (from the left) and a current source of 6 mA from the right. Total current is 8 mA into R2 \|\| R3 (500 ohm) or, put another way, 4 mA flows into R2. That sets the initial charged capacitor voltage. Can you take it from here?
H: Trouble deriving/understanding time constant I have the following problem: Consider the circuit below: The component values are: \$R_1 =5000 \Omega\$, \$R_2 =1000 \Omega\$, \$V_z = 5 \text{V} \$. When \$i_1\$ jumps from \$12 \text{mA} \$ to \$0 \text{mA}\$, what is the time constant for discharging the inductor immediately after? \$ \tau = L/R_1\$ \$ \tau = L/R_2\$ \$ \tau = L/(R_1+R_2)\$ \$ \tau = L/(R_1\|\|R_2)\$ Here are my thoughts. Since current through an inductor can't change momentarily, \$i_L=12 \text{mA}\$. The current will run through the zener-diode, when \$V_z=5 \text{V}\$. The zener-diode allows a current of \$i = \frac{5 \text{V}}{5000 \Omega}=1 \text{mA}\$ to run through \$R_1\$, while there flows \$11 \text{mA}\$ through the zener-diode. These two currents meet at the middle node, and causes \$ 12 \text{mA}\$ to flow through \$R_2\$. So as far as I see it, the current flows through bots \$R_1\$ and \$R_2\$ back into the inductor. \$R_1\$ and \$R_2\$ are in parallel, so my guess it that the time constant is expressed as: \$ \tau = L/(R_1\|\|R_2)\$. HOWEVER, it turns out the correct answer is \$ \tau = L/R_2\$ which I don't quite understand. Can someone explain to me why this is the case? AI: Analysing the voltage loop during the discharge time you have: $$-L\dfrac{di_Lt}{dt}=5V+i_L(t) R_2$$ Taking the laplace transform gives: $$L(sI_L(s) - I_L(0))=-5V-I_L(s) R_2$$ Rearranging: $$I(s)=\dfrac{I(0)L-5V}{Ls+R_2} = \dfrac{I(0)-\dfrac{5V}{L}}{s+\dfrac{R_2}{L}}$$ Taking the inverse laplace: $$I(t)=(I(0)-\dfrac{5V}{L})\cdot e^{-t\dfrac{R_2}{L}}$$ $$t\dfrac{R_2}{L}= - \ln(\dfrac{LI(t)}{LI(0)-5V})$$ $$t= - \dfrac{L}{R_2} \ln(\dfrac{LI(t)}{LI(0)-5V})$$ Meaning, that the discharge time is proportional to \$\dfrac{L}{R_2}\$ NOTE The negative sine of the voltage across the inductor in the first equation is due to the fact that it is discharging at the point of interest. Calculation must be double checked!
H: Gain-Phase measurement without dedicated equipment I was wondering if it is possible to make Gain-Phase measurements without dedicated equipment like the venerable HP4194A or a more modern Bode 100. As far as I understand, a Gain-Phase analyser is a device used to measure the transfer function of a DUT (Device Under Test) like this: LF-OUT generates a sinusoidal signal, R measures the input and T measures the transmitted signal. Computing T/R (taking care of magnitude and phase, of course) one can computed the transfer function. If I don’t have such a dedicated equipment, I thought I can make the same measurement simply with a function generator and an oscilloscope like in the following picture: Then I can compute the transfer function as Ch2/Ch1 (taking care of magnitude and phase, of course) Would this setup replace a Gain-Phase analyser? Or am I missing something? Many thanks in advance! AI: Just use a dual-trace scope and a function/sine generator; and trigger the scope sweep from the function generator's "sync" output. At each frequency of interest, adjust the scope's "variable time" knob (you do have one, right?), to use exactly NINE horizontal divisions per input sin cycle; thus you have exactly 40 degrees per division; most scopes have either 4 or 5 small time-tics per major division, thus you can easily interpolate to 1 or 2 or 4 degrees. ADVANTAGES? you get to WATCH how the circuit performs over the tested frequency range; (1) if the time delay is not absolutely stable at each frequency, you probably have spurious oscillation, to be debugged. Maybe ensure the bypass caps are installed, so the 2 meters of wire from powersupply to circuit is not causing problems (2) you get to look for clipping at all frequencies (3) at some frequencies, because of poles and zeros, you'll see very small output; is the RANDOM NOISE AND POWER SUPPLY NOISE about what you predicted? (4) you get to discover SLEWRATE limiting (5) you get to see blatant cases of distortion; 2nd order causes lopsided output sine shapes; crossover distortion in a class_A? cannot happen, right? but if you do? SUMMARY: you are responsible for all modes of behavior of your system. Be responsible. Examine the waveforms. Otherwise your boss will have to hire a consultant later, to clean up the mess you made.
H: Only spikes in H-Bridge I'm implementing a 300V MOSFET H Bridge with IR2110 driver. I decided to first try it in low (and safe) voltages, thus replacing the 300V with 12V as shown in the diagram. The MOSFETs I'm using are P20NM60FP, with a VGS of 5V. Ideally, I should have this waveform at output load I've checked every connection and the control signal from my microcontroller is correct (5V high, 1 Hz frequency). However, when I tried it, I get this spiky waveform as a result. Any ideas as to why is this happening? AI: Your o-scope time base is set to 1.00 seconds and, by the looks of it your control signals will be switching at 0.5 Hz. This is waaaaaaaaaaay too low in frequency. You have (in your driver circuit) bootstrap components that help give good drive signals to your upper N channel MOSFETs but, these bootstrap circuits can only work when you have sufficient drive frequency in your control signals. Try upping the frequency to 10 kHz. I don't know what your expected operating frequency is but if it's higher than 10 kHz then run at that higher frequency. If you expect to run at 0.5 Hz or thereabouts, this circuit won't work. The circuit above needs tens of kHz to work properly.
H: Purpose of inverted channel for UART bus communication I'd like to understand the purpose of an inverted logic channel on device-to-device communication that is being done via UART. For some background - I'm trying to reverse engineer this device-to-device communication with a logic analyzer that I have determined uses UART with the following configuration: Parity: None Data Bits: 9 Baud Rate: 38400bps Stop Bits: 1 On the device, i determined three pins that seemed to be transmitting within an expected logic level. After recording for 20 seconds, I noticed the first and second pin seemed to be linked - a perfect inverse logic level of each other at all times, an example is shown below: My first instinct, is that one channel is TX and the other is RX, and when data is being transmitted on TX the RX line is being used to confirm the data is being received as a method of validation. Is this something that is commonly done for UART communication? The transmission medium is through a flat-untwisted RJ-12 cable, with lengths around 1M-3M. Context is for an audio device connecting to its remote. AI: More than likely it's a balanced-differential data transmission. This offers much superior noise immunity on long lines compared to a single-ended data transmission system. It also doesn't generate the interference that a single-ended data transmission generates because E and H fields cancel. But it requires (for optimum performance), a differential signal that is transmitted simultaneously on two balanced wires such as twisted pair for example: - Picture from this wiki page.
H: When is a non-polarized electrolytic capacitor inappropriate? I am recapping a vintage power supply and I've done similar before but I'm a hobbyist non-expert. My understanding has always been that using a non-polarized cap is acceptable where an polarized capacitor is specified but that, essentially, that's uncommon because the NP/BP cap will be substantially larger and more expensive anyway. I'm hoping someone can help me understand why it would be that the 250uF/100V part I'm trying to replace is available very inexpensively (and in a reasonable package size) as a non polar electrolytic apparently intended for speaker crossovers ($3.50 currently) but Mouser has nothing at all in that spec for less than like $12 a piece. This suggests to me that something else is going on here and I'm wary of using the cheaper "spec-compliant" non polar part because I assume I'm missing something. Are caps in speaker crossovers different or special (or worse or unreliable thus cheaper)? Thanks for any insight. I have framed this as this specific question but if you think this bears as a jumping off point to link to or gently explain other characteristics of capacitors that I'm apparently unaware of, I'm all ears! AI: It's actually the polarity that you have to worry about more, non polarized caps can be used wherever polarized caps are used. But, there are other properties (such as max voltage, and ESR) of capacitors that need to be considered and what the application of the capacitor is. In general if it's a power bypass capacitor, you need a higher voltage rating than the application (or existing capacitor) and a lower ESR (equivalent series resistance). If the capacitor is for a filter, then if you don't want to calculate how it will alter the filter frequencies, then you will need to match the specs of the cap as close as possible. I didn't look at the links, but as far as I know all electrolytic caps are polarized. (you can put them back to back, positive to positive, to make them unpolarized)
H: What is Bus capacitance in I2C? How it limits number of devices can be connected to the bus? Bus capacitance limits number of devices that can be connected by I2C. What problem is encountered if one tries to exceed this limit can anyone explain this in detail please. Thank you AI: What is bus capacitance in I2C? It's the same as any capacitance - consider the copper traces running over a ground plane. There is some capacitance between the metal, determined by the total area of the traces and dialectic constant between them. Devices on the bus will also have some known capacitance between their IO pins and ground. I2C bus signals can be in the range of 100kbit/s, 400kbit/s or even 1Mbit/s. Adding a capacitor to ground on these signal lines will increase the rise and fall times of the I2C signal lines. How does it limit the number of devices on the bus? Each additional devices adds input capacitance to the signal lines in addition to increasing the bus trace area on the pcb. There's also additional noise added due to the longer traces. As the capacitance on the outputs increases, the signal lines become more sloped. If it's too high, they won't ever reach the threshold for any slave devices on the bus to recognize the signal at all. Or, in the case of the data line, the value might not reach the threshold in time to be registered. Electrical Theory Consider what an I2C connection looks like in a device. The SDA and SCL lines are said to be "Open Drain" which means they are connected to ground through an N channel FET and can sink current. Therefore, they can pull the lines low, but not set them high. That's why you need to connect external pullup resistors to the control lines. The lines are monitored through a diode which has some input threshold which must be overcome. simulate this circuit – Schematic created using CircuitLab So pulling the signal low is very quick, but to go high, current must flow through the external resistor and the internal circuitry to ground. This is not instantaneous, and any additional capacitance on the lines will further increase the rise time. Here are some example waveforms of a 50kHz clock line. The actual capacitor values are just to prove the point. Practical Considerations The device input capacitance is typically around 10pF, but exact values can be found in the datasheet. Another value to consider is the maximum sink current of any of the open drain connections, as this will put a lower limit on the pullup resistor values. This technical article from All About Circuits does an excellent job at visualizing these concepts and digging deeper into the calculations for signal rise time and acceptable pullup values.
H: Voltage Reference Resistor Calculation (Shunt) I am trying to design a circuit using this LM4040-5 Voltage Precision Reference for my DAC8554, but I can't for the life of me figure out how to properly calculate the resistor value to be applied. Right now the LM4040-5V (5V reference) is giving me voltages ranging between 4.77v to 5.11v. Obviously not very precise! This is the basic schematic for the LM4040 via its datasheet, as well as the formula they suggest for calculating the Resistor value: So for my particular design, VS == +12v, VR == +5v, but where/how can I obtain the values for IL (load) and IQ (operating current)? AI: These are values that come from the datasheets for the respective parts. The DAC shows the following: So you need to supply 250uA to the DAC. Then for the LM4040 to operate correctly it needs a reverse current of: So at least 74uA for the -5 version. So the minimum current through the resistor has to be 324uA. Unless you're counting every uA I'd go up to 500uA at least to be sure you have enough current over input supply tolerance, etc. With 12V on one side of the resistor and 5V on the other then, the maximum resistor value you can have is (12-5)V/500uA or 14K. Anything higher may not regulate properly. This is of course assuming you don't have any other load connected to the reference.
H: Why are integrated circuits powered by low voltage and high current? I've heard that a typical graphics card uses around 100 A of current and only 1 V of voltage. Is there a specific reason why not to use the other way around, so high voltage and low amp? Usually high current leads to high losses, that's why power transmission lines usually prefer high voltage instead of high current. So what am I fundamentally not understanding why that is a bad idea for integrated circuits? AI: I am not sure why this wasn't the first thing pointed out by any of the earlier answers, but it is because as transistors are made smaller to increase speed, increase density, and reduce power consumption, the gate oxide layer is made thinner (which also increases leakage currents). A thin gate oxide layer can't withstand very high voltages so you end up with a device that only operates at very low voltages. Thin oxide layers also have more leakage so you don't want a high voltage anyways since that would just increase leakage current and increases static power consumption. Your mistake is this: Data processing, unlike power systems, isn't about power delivery; It's about data processing. So it is not that designers choose to operate at low voltages and high currents thus going against \$I^2R\$. Yes, they are concerned about power consumption and heat due to losses, but they aren't concerned with the efficient delivery of power. A power designer has to deliver X amount of power and would increase voltage so they could decrease current while delivering that same power. A digital designer would outright decrease the "power output" if they could. Their optimizations necessitate low operating voltages which results in high leakage currents. The goal of these optimizations is to allow smaller transistors so you can pack more of them in as well as switch them faster, and when you have millions upon millions of transistors switching very frequently that results a lot of charging/discharging the gate capacitances. This dynamic current results in the high peak currents which can be tens of amps in high-speed, high density digital logic. You can see that all this current and power is undesired and unintentional. Ideally, we would like really no current at all because our concern is information, not energy/power. High voltages would also be nice for noise immunity but this runs directly counter to making transistors smaller.
H: Selecting residual current for RCBO I'm creating a portable test socket for electrical appliances that comes equip with a RCBO, power meter and possibly emergency stop button. My test socket will operate at max 240V AC and 10A. The purpose of the RCBO is to protect myself when I'm working on or fixing electrical appliances. When searching for RCBO breakers, they seem to have different rated residual current varying from 10mA to 300mA with the most common being 30mA. I understand that in a household application where multiple devices are connected there can be some leakage current where the higher rated residual current RCBOs are used. However, in my case where the RCBO is connected close to a single appliance, which value is most suitable for me? And also to take note the 10mA RCBOs are almost triple the price of the 30mA version from my local supplier. AI: For personal protection when working on equipment a 10 mA RCD/RCBO is best. If that is unaffordable then a 30 mA one should be adequate. A 300 mA model will not provide protection against electrocution. In the UK a 300 mA trip is used to provide protection against fire, not electrocution. Typically it would also be a time delayed design. Circuits fed from a 300 mA time-delayed RCD that need to provide protection against electrocution will also have a 30 or 10 mA normal speed RCD. Wiring outside the UK will follow the relevant local standards but a 300 mA trip won't protect you anywhere in the world.
H: Is dram constantly refreshing during windows sleeps? I know that sram and dram are volatile so even when windows is in sleep mode(not hibernation, in which memory is backed up to secondary storage), but I'm curious whether dram is constantly refreshing. I'm pretty sure about this because otherwise dram wouldn't be able to store information, but I can't find any source regarding this. Also, if so, is dram refeshing mechanism the only part where computer consumes power during sleep mode? AI: Modern DRAM such as SDRAM, DDR ... DDR4 have an "automatic self refresh mode" where the memory just need to be powered to internally manage periodic refresh cycles. The rest of the computer can be powered down to save energy. In that mode, DRAM draws about half the normal idle current and 1/5 to 1/10 of the current drawn during reads. (DRAM refresh period is in the order of 20ms, so it's impractical to periodically awake the computer just to refresh DRAM.)
H: What is the purpose of an "anti-pumping relay"? A project I'm working on has another firm replacing the anti-pumping relay on a motor starter (4160 V, 500 hp). I've never heard of an anti-pumping relay and after googling it, I still don't understand the purpose. My summary is that it prevents a circuit breaker from 'hunting' and repetitive closures. How does a circuit breaker 'hunt'? How do repetitive circuit-breaker closures occur? What does an anti-pumping relay do? AI: I had to just read up on this at this link: https://www.electrical4u.net/relay/anti-pumping-relay-diagram-and-working-function-explanation/ https://electricalfundaz.com/circuit-breaker-antipumping-device/ https://peguru.com/2012/03/power-circuit-breaker-operation-and-control-scheme/ But this is my interpretation of it things. Circuit breaker hunting is as follows: If there is a fault and the breaker trips, it will be expected to trip against instantly if you try to close it right? So suppose you have a button that you press to close the breaker. If you push this button to try and reset the breaker when there is still a fault on the line, it will instantly trip again, as it should. But the breaker opens and closes very fast, and you are a slow human slowly pushing the button. This means the entire time you have the button depressed the breaker is furiously opening and closing. This is bad for the breaker. There also seems to be another reason: The circuit breaker has two coils in it: one to open/trip the breaker, and another to close it. These coils are not designed for continuous duty and so will burn out if current is applied to them for too long (such as a slow human pressing a button to close the breaker). It seems that the trip coil is automatically disconnected by the breaker itself whenever a trip occurs. However, the close coil is a problem since a slow human is slowly pushing a button to energize the close coil longer than necessary. All this sounds like an electromechanical, power system equivalent of a level-triggered, non-retriggerable, astable (one-shot) timer.
H: How do I test the voltage of a battery without a multimeter? (Analogue components) I am trying to make a subsystem for my project that gives a low battery warning when the batteries are close to dying. How do I implement this? Many thanks AI: If you want something simple and your battery voltage is maybe too small for using a zener diode, you can use some bipolar transistors for turning off the an LED in case the battery voltage is insuficient. Consider the following circuit. If the battery voltage is high enough the LED will turn on with a current set by \$R_{LED}\$. The point at which the led is turned off can be regulated through the pot \$R_3\$. EDIT #1 Here is an updated version whose threshold can be more linearly controlled via a pot too: The value of \$R_3\$ can be roughly calculated to turn off the LED for a given battery voltage threshold \$V_{BAT,TH}\$: $$R_3=(V_{BAT,TH}-V_Z-V_{BE})\dfrac{R_2}{V_{BE}}$$ For example: $$R_3=(3V-2.1V-650mV)\dfrac{100k\Omega}{650mV}\approx 38k\Omega$$
H: What's the purpose of this resistor into a NOT gate? I'm trying to understand part of an envelope generator circuit. Here's the part of the schematic for the GATE IN, marked by the K, which can accepts a signal of between 0V and +5V. I understand that the 470k resistor is a pullup resistor which will keep the NOT gate (a CD4069 hex inverter with a +5V supply voltage) input pin high if there is no signal from the gate. What's the purpose of the 330k resistor though? Why shouldn't I just connect K directly to the input pin? Update: More details on the GATE IN signal. This circuit is intended to be used in a modular synthesizer. The GATE IN control voltage is expected to trigger the attack stage of the envelope generator at +5V and the release stage at 0V. There shouldn't be any other values presented to GATE IN. However, other voltages present in modular sythesizers typically range from -15V to +15V, and with some effort (to break things) could be presented to GATE IN. AI: It's probably to protect the gate input from voltages outside the range of 0~5V, including ESD. The relatively modern 4069UB on your linked datasheet is rated to withstand +/-10mA at the input, which would theoretically represent more than +/-6kV at the input. In practice the resistor would probably flash over and the supply voltage might get lifted to a destructively high voltage for a high positive input voltage via the two resistors shown.
H: Express reverse diode voltage drop as a function of temperature I've made a simple temperature meter, with means of series of Ge diodes, followed by 10k resistor. I am applying +5V to topmost diode cathode, and measuring voltage drop between resistor and ground simulate this circuit – Schematic created using CircuitLab Now I am trying to find formula for V(T). It's totally non linear, Probably I could make conversion in software. But, I need to know, what does it looks like? PS. If interested, for a calibration I know that Rdiode is ~20k for +5C and ~1k for 20C. And I only need narrow range -20C to +30C for rude street temperature measurement. AI: Germanium diodes are not obsolete, they are better than silicon ones and have better temperature stability and parameters. The function that you are looking for is a datasheet parameter. You can easily measure it, its a function of current or voltage change based on temperature. Its called a diode temperature characteristic. The characteristic will change in quadrants 1 and 3 based on the temperature, meaning the voltage and current through the diode will change with the temperature in a border. The characteristic and the original image. Formulas and explanations.
H: Can you use an FPGA / verilog to accelerate SAT / SMT solving? I am aware that SAT and SMT are widely used in hardware verification. This would tell me intuitively that trying every input on a circuit is slower than porting the circuit to a solver. However, we have ASICs for computing SHA256 faster in mining Bitcoin, so my thought is why not for SAT? I would like to build something that takes CNF SAT expressions (later on SMTLIB) and generates Verilog for them. I am not sure if it would be faster to pipe test inputs back and forth over USB or write a little harness to run within the Verilog. Either way, I'd like to offload the expression testing onto an FPGA. I figure generation + device programming time will be fixed (say, 20 seconds) so it will only make sense for longer running solves. Is this feasible or is there something about SAT solving / FPGAs I don't understand? AI: Yes, you can certainly use FPGAs to do this kind of work, there’s lots of literature pointing to it. Examples - [1] [2] [3] [4] SMT = Satisfiable Modulo Theory SAT is Boolean Satisfiable Problem, nicknamed a ‘SAT’ for short. More about this stuff here: https://people.eecs.berkeley.edu/~sseshia/pubdir/SMT-BookChapter.pdf My suggestion is to address the bitstream loading time. Some FPGAs support what Xilinx calls ‘tandem’ configuration, where a large FPGA first has a smaller bitstream loaded locally that’s enough to light up PCI Express, then the rest of the bitstream is loaded at high speed over the PCIe link. More here: https://www.xilinx.com/Attachment/Xilinx_Answer_51950.pdf
H: What should I look out for when driving high power relays with MOSFETs? Initially I was designing a relay controller for lower powered relay, but since I could not find the optocoupler that is rated for my application, I turned to MOSFETs. and it so happens that the logic level MOSFETs I find are way overkill for my application. Since the FETs I am using can do more than my original target, I decided to upgrade my circuit so that I may use it again in the future more versatility. So here is what I have so far, I decided to use 2 out 4 channels of my controller using NMOS and the other 2 using PMOS. I did this because I thought in the future if I ever need it to power something else that needs to be referenced to the same ground. Although this might not happen but why not when you can. The FETs I am planning to use are the: NMOS - CSD88539ND PMOS - FDS8935 Here is basically how each channel would look like in the schematic: I have decided that the absolute limit that my controller should carry is 50V 1A DC. I don't know if relays like that even exist, but nonetheless that is my target. What other things I should look out for when powering this big of a load relay? Is there a chance that that power might surge back to GPIO pins? AI: You have not mentioned the relay solenoid current. Your 1M resistors are too large to be useful here, you should reduce them to 100k at the most. I would actually suggest a slightly better arrangement: simulate this circuit – Schematic created using CircuitLab Both resistor values can be increased, but they should follow each other's values; if you increase R1 to 1k you should also increase the R2 to at least 22k, so that the driving voltage is not significantly reduced due to voltage divider formed by R1 and R2. This brings up another issue: is your GPIO output voltage sufficient to turn the MOSFET completely on? I would be wary of using a resistor in series with a freewheeling diode across a relay solenoid because the current spike is high and could produce a high voltage spike across the resistor which would defeat the purpose of the diode. A zener diode in series with a regular diode would be better because it would only conduct the highest voltage spikes and the relay would function better (a plain diode across relay coils is bad for the relay switch contacts, according to this short article: Coil Suppression Can Reduce Relay Life). The zener diode needs to have a voltage rating between the supply voltage and the MOSFET's maximum Vds rating so that the spike never goes above it. For example, if the supply voltage is 24V and the Vds(max) is 60V, the zener voltage should be between 30V and 40V. The power supply voltage should not be reaching the zener voltage (if you have an unregulated power source). The zener diode should have the highest power rating you can get. 0.5W and 1W will not be enough. You could also use more than one zener and share the voltage drop (as well as the power) across them equally, and then you could use lower power zeners.
H: How much time computer can last without power? I got curious what if my power power was cut off by some amount of time, say 1/10 second, will computer be still working? I think so instinctly but not sure. Is there a way of telling how long will it last? I use P650B power supply. EDIT And what are the edge cases? Between working and not working. will the programs running on it be partially damaged? AI: What you are looking for is called hold-up time. This is the amount of time the power supply can sustain regulation after loss of input power. Manufacturers provide this data in the power supply specification. Here is an example from Corsair. source This is the minimum guaranteed hold-up time from a loss of all input power. In reality you can sustain regulation for longer depending on the specific AC power conditions.
H: Would either of these BJTs require a heat sink? I am brand new to heat calculations and trying to determine if I need a heat sink for the BJTs or not. Below is the circuit with voltages and current with the data sheet of the used BJTs. The maximum ambient temperature will be 25C. AI: Heatsinks are generally for power transistors or other power devices. But adding a heat sink Will help to keep the device cool. In your case, Q1 is dissipating only about 67mW which is safely below the max power rating of 625mW and no heatsinl required. The second transistor is dissipating about 200mW. This too is more than half lower than max power rating which is good an wont require heatsink. Note though that these are DC power though and the overall power (DC +AC) must be lower than max power. Take a look at peak power of Q2 when ac signal is applied at input of your circuit. It should be well below Pmax. To determine if heatsink is require you need to check if Junction temperature of transistor is below a max of 150C . At this temperature the decide will be destroyed. Though a better temperature is 100C. If at your power dissipation the junction temperature reaches 100C then you require a heatsink. The formula for junction temperature is shown below.
H: Do usb and vga controllers consume power if there are not devices connected to them? Let's consider the following situation. There is a server, for example supermicro, that has 4 USB2 ports, 4 USB3 ports, and 2 VGA ports. At the same time we don't use these ports, I mean there are no devices connected to them. Do these ports consume any power in such a situation? I am asking as I need to understand if these ports draw any power from power supply. AI: The answer depends on the level of implementation of ACPI system states in your particular system. Each device on a computing platform also has special device power states within ACPI: From NCR website: ACPI defines power states for peripherals which are separate from the system power state. The device power states range from D0 (fully-on) to D3 (off) It is the responsibility of the driver developer for each peripheral to define and support the available power states. There is also some extension to Sleep States called "Modern Standby", some improvement over "connected standby". If your system supports Intel-defined so-called "S0ix" mode, and all peripheral controllers (and their drivers!) are compliant, the USB host controller will be forced into D3 state if nothing is connected to it. Even if HID devices are connected, the system will selectively suspend them after some period of inactivity, and put host controller[s] into D3. All these complications are invented mostly to prolong battery life of laptops, tablets, and phones. Implementation of low power saving modes is pretty complicated and requires additional embedded management processors into main computing cores, and it takes some toll. It is quite unlikely that your server system supports them.
H: Laser and galvo project I'm working on passion project that would allow me to control laser and mirror galvanometer (galvo in further text) using Arduino board. Laser and galvo that I've bought are encased in plastic housing unit and galvo can direct laser beam only horizontally, it was spare part from laser printer and came without any wires. Photo album of galvo in question: https://photos.app.goo.gl/yYuCsytvfRXX8Vnv8 Since I don’t have experience with electronics I need help figuring some things out. What kind of wires (input jacks) do I need to buy for laser and galvo circuit boards (designated in the images above)? What kind of power supply do I need? What kind of Arduino board do I need? Any additional equipment? It should be taken into consideration that I plan to add camera so I can manipulate laser through optics instead sight, after I finish this first part of the project. Thank you. AI: What kind of wires (input jacks) do I need to buy for laser and galvo circuit boards (designated in the images above)? A quick Google search turns up a few guides to wiring up that board, or at least one that looks just like it. I suggest taking a look at one of those. But in general, assuming that is actually a polygonal scanner and not a galvo, it is going to take a DC voltage (probably 12, 15 or 24v), and a clock signal, which the driver will use to synchronize the motor rotation rate to. The clock signal is used to let you synchronize the beam scanning to another axis (for 2D scanning) or to a power modulator (if you are drawing something with the beam). There is probably a feedback signal as well that indicates the true phase of the mirror so you can figure out if it is locked to the clock and/or detect error conditions. Since you don't know how many clock edges corresponds to one revolution, I would start by trying to get the motor spinning at a relatively low speed and then use a laser and a photodiode to measure how many times per second the beam scans. Since the mirror scans 720 degrees per revolution and looks to have 4 faces, from that you can calculate how many clock cycles there are per revolution.
H: Compute electric field in complex 3D geometry I have a CAD file with a pretty complex geometry. I would like to compute the electric field generated by this geometry when a specific charge density is defined. I guess I will have to go through some finite elements algorithms (which I have no experience at all, so any suggestions for tutorials and literature is more than welcome) Could you suggest some toolboxes to simulate the electric field, or more in general to solve partial differential equations, in a complex geometry. It is not a requirement, but I prefer to use Python or MATLAB as programming languages. AI: Maybe Quickfield is useful to you. It is a finite element analysis software package running on Windows platforms which does computer simulations of electromagnetic fields. You can import CAD drawings.
H: Techniques for determining the peak of sine wave via ADC From the book "Digital Protection for Power Systems" the author presents some algorithms to process a sinusoidal waveform. For example, below there's a fragment taken from the index. He also mentions the Walsh Transforms in another chapter. Although the author proposes the mathematical formulations, there's no sample code. In my case, I'm reading a 60 Hz signal from a CT, and added a DC shift for the ADC. I don't need to calculate RMS, rather the peak value is just OK. Has anyone used any of these methods? The simplest method I think is to sample let's say at 1 kHz, and then find the min and max. AI: Once oversampling at 1kHz, 'just finding' the min and max sounds good to me, to well within 5%. Let's do the error analysis. 1kHz is 16x oversampling, which means you'll always have a sample within 2pi/32 = 0.2 radians of the peak. cos(0.2) = 0.98. With random phasing, your 'peak' will be within (+0%, -2%) of the true peak. That meets your 5% specification. Do you need to do any more work on this? What's the noise on your signal? If you need to start averaging samples due to high noise, or rejecting sporadic noise peaks, then life gets a lot more interesting. The simplest mitigation to noise is an analogue filter before your ADC. You will already have an anti-alias filter there, but it might be worth tightening it down to just over 60Hz. If you need to do (or want to do) digital processing, then the fact that your input frequency is tightly controlled should mean you don't need to actively synchronise to the incoming waveform. As you are (reasonably accurately) oversampling 16 times, or better still change to exactly 16x, you could compute the total power of 8 successive samples, one complete half-cycle. That gives you a measure of the RMS signal, with noise events suppressed somewhat. More half-cycles summed, more noise suppression, but then you're waiting longer for a detection. If you want to do non-linear noise suppression, then you need to start tracking the signal you're sampling, with a software PLL. The possibilities for making this little area of the project a big area are endless. Don't over-design it.
H: Is superposition theorem the only method to calculate the \$I_0\$ in this circuit? When I learned the superposition theorem, the book provided this circuit to me, and taught me how to use the superposition theorem to find the value of \$I_0\$: simulate this circuit – Schematic created using CircuitLab However, I want to ask that why should use the superposition theorem to find the \$I_0\$ in this circuit? Must we use the superposition theorem to find the \$I_0\$? I mean, is the superposition theorem the only method to calculate the \$I_0\$? If I have no idea about superposition theorem, that is, f I don't know what the superposition theorem is, I don't know there is a method called superposition theorem which can be used to calculate the \$I_0\$ value. Can we still use other methods to calculate the \$I_0\$? If yes, can anyone show me how to calculate the \$I_0\$? AI: i want to ask that why should use the superposition theorem to find the I0 in this circuit?must we use the superposition theorem to find the I0? No, unless you are instructed to do so. i mean is superposition theorem the only method to calculate the I0? And... can we still use some methods to calculate the I0? if yes!can anyone show me how to calculate the I0? My natural instinct is to simplify.... So, I'd rearrange - the current source is attached to a grounded voltage source - that immediately allows it (the current source) to be moved directly across R3 - this simplifies any analysis because you can turn it into a voltage source of 48 volts in series with 12 kohm (R3). I'd then rearrange V1, R1 and R2 into a 3 volt source in series with R1\|\|R2 (= 6 kohm). It's simple math to see that the current through R4 flows right to left with a magnitude of 1.5 mA. Drill down a bit more and the current though R2 is easily found (0.5 mA). Simulation confirms: - And, just in case anyone is perturbed by my suggested modification to split the current source from the voltage source and place it across R3: - Then, convert I1 to a voltage source (I've called it V_I1 below) and rearrange the proper voltage source (V1), R1 and R2 into a source with a single resistor of 6 kohm (named R5) and it's really simple to find the current through R4. As I said earlier, drilling down a little more finds I_0.
H: How to do convolution related problems? I do not understand the concept of convolution. If possible could you please explain in layman terms so that I can solve this question. What is the h(t)? AI: HINT The transfer function in the s-domain (using Laplace transform) is given by: $$\mathcal{H}\left(\text{s}\right):=\frac{\text{v}_\text{o}\left(\text{s}\right)}{\text{v}_\text{i}\left(\text{s}\right)}=\frac{\text{R}}{\text{R}+\text{sL}}\tag1$$ Using the definition of the Laplace transform we know: $$\text{v}_\text{i}\left(\text{s}\right)=\mathcal{L}_t\left[\text{V}_\text{i}\left(t\right)\right]_{\left(\text{s}\right)}=\int_0^\infty\text{V}_\text{i}\left(t\right)\exp\left(-\text{s}t\right)\space\text{d}t=$$ $$\int_0^1\left(\theta\left(t\right)-\theta\left(t-1\right)\right)\exp\left(-\text{s}t\right)\space\text{d}t\tag2$$ Where \$\theta\left(t\right)\$ is the Heaviside Theta function. Besides that, an impulse response of a system is given by the output of a system when a Dirac delta function is applied to the input.
H: How to increase data through put of RS485 RTU? I am using 20 sensor nodes, each has mpu9250 i2c, Arduino atmega328 MCU 8MHz and max485 chip in it, each server has a unique id program. I have Arduino due as Modbus client with max485 chip, I hope to use Arduino Modbus library RS485 RTU, assume server is continually reading data and updating local variable with imu data 12bytes, and ready to send over the bus. and client is polling data from each server node. all sensor are connected the same bus, 1.5ft from the sensor node to sensor node away each (cat 5 cables), the reason to choose Modbus is having higher data rates compared to CAN bus or I2C, I have a doubtable point, how long it will take to respond to client with data? how to calculate request/response time or the time to gather data from all sensors by the client? in other words how many samples per second achievable? AI: It is generally accepted that RS-485 can be used with data rates up to 10 Mbit/s or, at lower speeds, distances up to 1,200 m (4,000 ft). As a rule of thumb, the speed in bit/s multiplied by the length in metres should not exceed 10 on the power of 8. Thus a 50-meter cable should not signal faster than 2 Mbit/s. The modbus documentation from TycoElectronics.
H: Isolated DC/DC converter help I would really appreciate if someone would share his insights on whether an isolated DC/DC converter of a fixed output (12V) can sustain that output even when input is lower than 12V, the datasheet says the input range 9-36 VDC which may be the answer but i would really like to get a confirmation if possible. Also a side question, this datasheet does not indicate any input or output filters or recommended capacitors for optimal operation except a 10F MLCC at the output , any recommendations on this ? my thought was to throw a few bulk capacitors at the input/output and call it a day. DC/DC Converter Datasheet AI: this datasheet does not indicate any input or output filters or recommended capacitors for optimal operation except a 10F MLCC at the output , any recommendations on this ? First of all read this section in the data sheet on how to make it compliant with EN55032: - I would really appreciate if someone would share his insights on whether an isolated DC/DC converter of a fixed output (12V) can sustain that output even when input is lower than 12V, the datasheet says the input range 9-36 VDC which may be the answer but i would really like to get a confirmation if possible. Secondy, yes it will work from 9 volts input to 36 volts input because, internally, is a flyback converter.
H: Preset D flip flop as 0 for total sum I'm trying to implement a total sum that follows this code SUM = SUM + INPUT SUM and INPUT are 5 bit signals in binary. I know how to implement the adder and i have 5 D flip flops to store SUM but at the start of the system, SUM is not defined because the input to SUM uses the output from the adder which uses SUM and so on and so forth. I'm not sure how to initialize my SUM to be all 0's. Any advice for building this circuit in general would be appreciated outside of my question. Thanks in advance! AI: You need a reset signal. If your flip flops have a reset input, you can just use that. Otherwise, you need to create your own reset signal by using logic gates to force the input to the flops to be 0.
H: Can I connect the primary of two coupled inductors (transformer) directly to mains voltage in parallel or do I need intermediary circuitary? Examining a voltage regulator schematic, I believe I can connect the primary side of a step down transformer to mains voltage directly to step it down on the secondary, but PSpice doesn't let me simulate that same exact circuit(transformer with bridge rectifier) claiming I can't have a voltage source and inductor loop without a series resistor to break it. I don't know if this is just a PSpice limitation or if connecting the primary of a transformer directly to mains without resistors is a bad idea? In PSpice, the two inductors are coupled using Place->PSpice Component->Passive->Coupling. Background: The goal is to rebuild a voltage regulator using discrete components. I am trying to go from a 120 V 60 Hz to 12 Volts. Once I can step down and clip the negative wave correctly, I'll add the capacitive filter to smoothify or make the waveform more DC like. AI: I don't know if this is just a PSpice limitation or if connecting the primary of a transformer directly to mains without resistors is a bad idea? Put a 1 milli ohm resistor in series to break apart the inductor and the pure voltage source. It's a common enough trick to have to do on nearly all simulators. The thing is this: a pure voltage source doesn't exist so it's no big deal adding the resistor like everyone else. Make it 1 micro-ohm if you want or a pico ohm. Even try 0 ohms - sometimes that works. But, as per the comment by @user4574, the real circuit needs a fuse to protect the wiring infra-structure in the building.
H: How do I apply KVL in this circuit? simulate this circuit – Schematic created using CircuitLab β = 100 I am applying KVL Clock Wise on both Loop.So I came up with 5 - 100IB - 0.7 = 0 On the second loop:- VCE + 50Ic - 8 = 0 or VCE + 50Ic + 8 = 0 which one is correct please explain. AI: You must decide in advance whether you are going to say that a voltage is positive in the KVL equation when you move from its negative terminal to its positive terminal, or that it is positive in the KVL equation when you move from its positive terminal to its negative terminal. Having made that decision you must be consistent with all voltages as you go around the loop. First, let's recognize that the voltage across the resistor is positive at the right end of the resistor, and VCE is positive at the collector. If I go counterclockwise starting at the transistor's emitter, and I say that a voltage increase is positive (moving from negative terminal to positive terminal) then I get this equation: \$V_{CE} + R2\times I_C - 8 = 0\$ If I go CCW but say that a voltage decrease is a positive term then I get: \$ -V_{CE} - R2\times I_C + 8 = 0\$ These terms are algebraically equivalent, so it doesn't matter which way you choose to write the voltage terms as long as you are consistent.
H: Why harmonic distortion and not at other frequencies? Despite searching I can't seem to find the answer to this. In understanding harmonic distortion, one piece of the puzzle that is missing for me is: - why does the distortion manifest at harmonic frequencies and not other frequencies. Feel free to simply point me at a textbook / reading that explains it, if that's easier! I understand that non-linear loads can create distortion. Intuitively, this is because the load can change it's characteristics (resistance, capacitance, etc etc.) in complex (difficult to predict...) fashion. I understand enough of Fourier analysis to understand harmonics, 1st (fundamental), 2nd, etc etc. I don't see why the distortion would tend to be at harmonic frequencies. E.g., if I put a 1KHz sine wave through a non-linear load, why would the distortion show up at harmonics and not something a little less friendly, say, at 1.8KHz, depending on the circuit design? I come across this in studying audio systems. They rely on THD as a measure of fidelity (for non-clipping signals), but it baffles me why the distortion falls into nicely behaved harmonics... Thanks!! Update: thanks to all the great quick answers below, I think I figured it out. non-linear loads are still predicable: "A nonlinear impedance effects every cycle of the waveform in the same way" (Charles Cowie) other impacts that do not effect every cycle the same way are transient, or interharmonic. These can be highly unpredictable, due to external forces, etc. They can change the fundamental frequency (e.g., a sharp cutoff) any periodic (distorted?) waveform "can be represented by their fundamental component and a Fourier series of harmonics of various magnitudes, frequencies and angles.(this cites another source)" (from relayman357) there are some great math workthroughs below that illustrate this. So the piece that I was missing was that the distorted waveform still sits on the fundamental frequency in a periodic fashion, so by definition the distortions are harmonics (different phases/amplitudes,etc.). Non harmonic distortion (interharmonic) isn't periodic. Loads like amplifiers don't typically change the fundamental frequency but "give it hair", so it's still periodic. AI: A sinewave of 1 kHz only contains one frequency: 1 kHz. Let's describe that mathematically: \$x = sin(2 \pi f t) \$ Where \$f\$ is the 1 kHz, \$t\$ equals time and \$X\$ is the sinusoidal signal. If an amplifier is ideal then it would only amplify the signal, i.e. increase the amplitude: \$y = A x = A sin(2 \pi f t)\$ Note how that still has is just a sinewave, only the amplitude (value of the minimums and maximums) have changed. But that's a linear amplifier, it will not introduce harmonics. Now what if the amplifier distorts. Do you remember the Taylor series? It is a way to express any function in the form of a polynomial like this: \$y = A x + B x^2 + C x^3 ...\$ What I wrote there is the Taylor expansion that describes the behavior of an amplifier with distortion. If you fill in \$x = sin(2 \pi f t) \$ you will get \$sin(2 \pi f t) \$, \$x = sin^2(2 \pi f t) \$ and \$x = sin^3(2 \pi f t) \$ terms and these are the harmonic frequencies. Note that there is no way to get terms other than \$x = sin^n(2 \pi f t) \$ making it impossible to get frequencies that are not a multiple of the base frequency of \$x\$. Bonus question: What would be needed to get other (non-harmonic) frequencies? With a sinewave as input, there is no way. But if we combine two or more sinewaves of different frequencies, then we can get intermodulation products. For example, make \$x\$ a signal consisting of a 1 kHz (\$f_1\$) and a 200 Hz (\$f_2\$) tone: \$x = sin(2 \pi f_1 t) + sin(2 \pi f_2 t)\$ Then at the output of a distorting amplifier we will find sum and difference frequencies so we would get: 200 Hz 400 Hz ( 2 x 200 Hz, the 2nd harmonic of \$f_2\$) 600 Hz ( 3 x 200 Hz, the 3rd harmonic of \$f_2\$) 800 Hz (1 kHz - 200 Hz) 1 kHz 1.2 kHz ( 1 kHz + 200 Hz) 1.4 kHz ( 1 kHz + 2 x 200 Hz) etc etc note how they're all 200 Hz (\$f_2\$) apart! How many frequency components are present depends on how much the amplifier distorts and the amplitudes of the signals.
H: SN74LS26 2-input NAND gate. No output I purchased SN74LS26N quadruple 2-input NAND Gates chips for my circuit. Before I insert any chip into circuit I test it on separate breadboard. So I did with this chip and I get NO output when my inputs are LOW... Does it make any sense to you? I am doing something wrong? simulate this circuit – Schematic created using CircuitLab I am not the best with schematics so I hope this is clean for you.. I tried adding bypass electrolytic caps 0.1uF but that didn't help Thanks! AI: The LS26 contains open-collector NAND gates. You must add pullup resistors to the outputs in order to see a high logic output. These gates are designed to interface to circuits operating at higher voltages, so there is no internal circuitry that pulls the output to 5V.
H: Pour copper area inside cutout Altium 19 I have a board design in Altium 19 which has a differential pair on layer 2 and a power plane on layer 3 (the rest of L2 is GND). I need to cut out the power plane on L3 and have an area of GND to give a reference for my diff pair - how can I acheive this in Altium? I have tried making a cutout then drawing a copper pour within that, but the copper pour doesn't work, though the cutout does. Also tried moving the polygons around in polygon manager, without success. AI: I see you've found an alternative solution, but I'll still answer the question you asked in case it's useful for future readers. I have tried making a cutout then drawing a copper pour within that, but the copper pour doesn't work, though the cutout does. You don't need to make a cut-out. Just put the GND polygon inside the power polygon. Then, in the polygon manager, adjust the pour order so that the GND polygon is poured first. Then when the power polygon is poured, it will flow around the GND polygon, respecting your clearance rules as it pours. It's also possible to just use the power plane as a reference for your transmission line. The main consideration is just to make sure there is good AC coupling (bypassing) between the power plane and ground planes, particularly near the two ends of your transmission lines.
H: Choice of buck-boost converter I have a Li-Po battery which has a discharge voltage range of (2.5-4.2)V and I want a regulator which is able to convert this voltage to 3.3V. I was told to use a buck boost converter. I have found one which is a buck boost converter and the other a buck converter. Reading the descriptions of both, I think both will work but I would like to ask for your opinions or if you have any other recommendations of components that'll work. Here below are the datasheets of each component: Buck Buckboost AI: The maximum output voltage of a buck converter is slightly lower than the input voltage. Therefore if you use the buck design, you won't get 3.3 V output when your battery voltage drops below 3.4 V or so. This behavior isn't really explicitly mentioned in the datasheet (except where they call the chip a "step-down" converter), because it's such a fundamental limitation of buck converters that people using them are expected to know about it. There is one section that does at least allude to the limitation:
H: Inconsistent performance of circularly polarized antenna I have a circularly polarized patch antenna for an RFID reader, with a gain of 8dBi and bandwidth from 914MHz to 919MHz and an axial of 0.34dB. I have read that using a CP RFID patch antenna means that the RFID tag will still be detected no matter the orientation of the RFID relative to the CP RFID patch antenna. But when testing this I see that there is a difference in terms of the detection of the RFID tag when I change the orientation of the RFID from horizontal orientated to vertically orientated. I connected the antenna to the reader and then to my computer where the software shows the retrieved data from the RFID tag. For example, I placed two tags at a distance of 1.5m away from the reader's antenna at the same height in free space (outdoors). One RFID tag was horizontally orientated while the second RFID tag was vertically orientated. When testing these tags the horizontally orientated RFID tag showed to more stable because the reader's antenna picked it up continuously and I could see the data from the RFID tag using the software. However, when testing the vertically orientated RFID tag I noticed that the vertically orientated was barely detected by the reader's antenna, in that one second, the data appeared on the computer and next minute the data was not there. This does not make sense because the CP polarized suppose to detect the RFID tag regardless of its orientation. However, I did notice that when I brought the vertically orientated RFID closer to the reader's antenna the antenna started to pick the RFID tag in a more stable manner. Why does this change in performance exist? AI: The antenna as an axial ratio of 0.34dB which means this antenna is not truly circularly polarized. A true circularly polarized antenna will have an axial that is unity (0dB). Therefore the antenna in the question is very close to unity but it is not truly circularly polarized. This axial ratio shows the antenna has an elliptical polarization (the minor and major axis are not equal). "A circularly polarized field is made up of two orthogonal E-field components of equal amplitude (and 90 degrees out of phase)". Since the two E-field components are not equal because of the elliptical polarization the E-field strength that reaches the RFID will be different. Therefore, in this case, the vertically orientated RFID tag might only be receiving the minor axis E-field, while the horizontally orientated receives the major axis E-field. Hence the variance in the detection with respect to the orientation of the RFID tag. With regards to the RFID tag been detected when it is closer. Keep in mind that the intensity of the radiation is inverse to the distance. So the further you move away from the source the weaker the intensity gets and the closer you move towards to the source the stronger the intensity becomes. Also, it could be that as you move closer the minor axis E-field is now above the threshold to detect the RFID tag but as you move further away remember the minor E-field will drop and will always be less than the major axis E-field.
H: Calculating the voltage drop in a split-phase system We are working with an electrician to install permanent wiring to a large trailer unit - it will be a 120/240 V split-phase system (the trailer itself uses a NEMA 14-50 dryer plug) delivering 50 amps at a distance of 300 ft. I (think I) understand that this wiring set up effectively gives us three circuits - two 120 V/50 A circuits and a single 240 V/50 A circuit. What I am struggling to understand is how I determine the proper wiring size for the system, given the parameters of the circuit and our voltage drop needs ( <3% ). Following Ohm's Law, I have been using the formula to calculate the expected voltage drop for particular wire gauges (4 AWG or 1 AWG): Vd = 2 * L * R * A Where: Vd: voltage drop L: one way distance (in thousands of ft) R: resistance of wire (in Ohms per 1000 ft) A: load current (in amperes) Ex. 1 1 AWG wire, 300ft, 50A Resistance of 1 AWG wire / 1000ft = .124 Ohms Vd = 2 * 50 * (.3) * (.124) Vd = 3.72 V Ex. 2 4 AWG wire, 300ft, 50A Resistance of 4 AWG wire / 1000 ft = .249 Ohms Vd = 2 * 50 * (.3) * (.249) Vd = 7.47 V Based on this information, my numbers suggest that we would need to use 1 AWG wire, but the electrician has said that 4 AWG is more than sufficient. I have complete confidence in this electrician, so I am sure there is something that I am missing. How does the presence of the split-phase 240 V system affect voltage drop considerations (if at all?). Any comments or help is greatly appreciated! AI: The 50A breaker pair feeding the NEMA 14-50 plug limits the current on any phase to ... 50A, period, no matter how you load your phases. The breakers are linked, so if you have a single-phase fault on L1, it will trip itself and L2. Your electrician will use that breaker panel limit not only to calculate the IR drop, but also the allowable cable temperature rise given the ambient temperature, conduit type, wire material and insulation type, as these all affect the 'ampacity' of the wire. As for the voltage drop, the NEC specifies a maximum drop of 5%, not 3%. See https://www.mikeholt.com/technnical-voltage-drop-calculations-part-one.php At 300ft and 50A, #4 ga. copper will be less than that, about 3.5%. So, plenty. Your electrician knows what they're doing. BONUS: An IR drop calc, with a wire resistance chart: https://www.calculator.net/voltage-drop-calculator.html tl; dr: resistance of #4 ga. is 0.2485 ohm/1000ft One-way IR drop for 300' at 50A = 50 * 300/1000 = 3.73V Two-way IR drop is 7.46V, or 3.1%
H: Why are these two electrolytic capacitors so hugely different in size? I'm recapping a vintage amp, and that amp has two larger caps at 2200uF @ 50V. I have sourced some possible replacements, and I'd like some insight into why these are SO different in size, and how I should think about that. (These are both new parts. Original cap not pictured. I know they are slightly different in capacitance--the schematic asked for one thing but the original part was another-- but I think the question here still stands since the specs are so close). The big one is a Sprague Atom rated to 85°C. (data sheet here). The small one is a JWCO part rated to 105°C. (Data sheet here)-- it's over an inch long, which makes the Sprague huge at like 2.5"+ and way more diameter. Now, I get that the JWCO is a sort of no-name commodity part that I don't want to use in an audio amplifier-- I get that. But even a Nichicon audio cap at 2200/50 is only going to be a bit over an inch long. But what I don't get here is WHY these are so enormously different in size, and what's up with the Sprague? Small variances wouldn't surprise me at all based on materials and construction but this is not a small variance. Even the 50-year-old cap I'm replacing is much smaller than the Sprague (though not as small as the JWCO or a Nichicon). Thanks for any insight. Piecing together my knowledge of components by example! AI: Alotta empty air... Those are very old designs (60's), one might use them to restore vintage equipment w/o affecting their appearance. https://www.lespaulforum.com/forum/showthread.php?177151-Sprague-TVA-Atom-vs-Nichicon-VX-Series Guitarists and audiophiles spend stupid money chasing "tone", thinking there's some sort of magic in the parts themselves.

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