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H: Ambiguity in the Definition of Resonance Frequency
we know that in a series LC circuit the resonance frequency is defined as that frequency in which the total impedance offered by the circuit is zero.
We also know that in a parallel LC circuit the resonance frequency is defined as that frequency in which the total admittance offered by the circuit is zero.
I have seen several times analyzes of much more complex circuits (composed of several series and more parallel elements of L and C) in which the resonance frequency was defined as that frequency in which the total admittance was infinite, for example.
My question is: what is the general definition of "resonance condition"? With what criterion do we define the resonance condition for a given circuit?
AI: Write differential equations that describe a circuit. Set all sources equal to zero. Find the non-zero functions of time that satisfy the differential equations. For lumped, linear, time invariant circuits, these functions will be complex exponentials. A “resonant frequency” in radians per second is the imaginary part of the argument of the complex exponential. This definition works for all circuits, as well as lumped mechanical systems.
The resonant frequencies are a property of the circuit, and have nothing to do with inputs or outputs. |
H: Is this Non-Inverting integrator correct?
I've seen time again the formula for an inverting integrator. I was wondering if I could swap the configurations on the inverting and non inverting inputs of the op amp to make the circuit a non-inverting integrator. I did the math, but when I searched online to make sure my math was correct, I found nothing supporting my derivation. So I'm wondering if my math is incorrect or if I have a conceptual gap with the functionality of an op amp. Here's my work:
I called the non-inverting input to the op amp \$v_{+}\$ the inverting input \$v_{-}\$, the amplification \$A\$, the output voltage \$v_{out}\$, and the input voltage \$v_{in}\$.
$$ v_{out} = A\times(v_+ - v_-) $$
Because I grounded \$v_-\$, $$v_{out} = Av_+$$ $$v_+ = \frac{v_{out}}{A}$$
The current going through resistor \$I_R\$ is the same current going through the capacitor, \$I_C\$. Where \$I_R=\frac{v_{in}-v_+}{R}\$, and \$I_C = \frac{dv}{dt}C\$. Therefore, by equating these equations we can solve: $$I_R = I_C$$ $$\frac{v_{in}-v_+}{R}=\frac{dv}{dt}C$$
$$\frac{1}{RC}(v_{in}-v_+)=\frac{dv}{dt}$$ $$\frac{1}{RC}(v_{in}-\frac{v_{out}}{A})=\frac{dv}{dt}$$ $$\lim_{A\rightarrow\infty}\frac{1}{RC}(v_{in}-\frac{v_{out}}{A}) = \frac{1}{RC}v_{in}=\frac{dv}{dt}$$ $$\frac{1}{RC}v_{in}dt=dv$$ $$\frac{1}{RC}\int v_{in}dt=v(t)-v(0)$$ $$\therefore v(t)=\frac{1}{RC}\int v_{in}dt + v(0)$$ The inverting integrator follows the same formula, except it has a negative tacked on infront of the integral: $$v(t)=-\frac{1}{RC}\int v_{in}dt + v(0)$$
AI: I think your math is correct. However, real op amps will not work with this configuration, because real op amps have finite frequency response, or a time delay, or they shift the phase of a sine wave: all of which are about the same thing.
So, when you try this with a real op amp, the circuit will be unstable.
You can see this mathematically by adding a pole to the gain of the op amp... perhaps writing it is A/(s+a), or A/s. (s being the Laplace variable, "a" a small number), then doing the math in the Laplace domain.
This just shows that using an ideal model can lead to the wrong conclusions sometimes. |
H: SA636 Local Oscillator -- Which Pin?
This is about a very specific RF system on a chip -- NXP's SA636, "Low voltage, high-performance mixer FM/IF system...". Datasheet is here: https://www.nxp.com/docs/en/data-sheet/SA636.pdf. The datasheets and application notes differ in what looks like a critical way to me, and I'm wondering what route to take before I spend cash on PCBs.
I'm trying to build a radio for 162MHz, a frequency that should be well within limits for this IC. I'm injecting my local oscillator (LO) signal, but where, exactly, I do that isn't clear. The chip has four relevant pins, two for the RF input and two for the LO; the RF and LO signals are internally mixed via a Gilbert cell. On the LO side, the two pins look like this, with one pin connected to the base of an internal transistor and the other to its emitter:
The datasheet itself has the LO injected on the OSC_IN (base) pin:
But in the application notes, the LO is injected on the emitter side of that transistor: (note that the application notes are using the SSOP package, with different pin numbers compared to the HVQFN package. Pin 3 & 4 in SSOP == pin 1 & 2 in HVQFN, respectively)
So, I'm wondering where to connect my 151.3MHz LO -- should I connect to the base or to the emitter? My guess is the emitter, but that's going by feel and I'd like to think things through rather than just go with my gut.
Datasheet: https://www.nxp.com/docs/en/data-sheet/SA636.pdf
AN1996: https://www.nxp.com/docs/en/application-note/AN1996.pdf
AI: The last image LO source to filter to Pin 4 looks correct in the App Note but the label in Box , OSC_Out is wrong and is reversed with Pin 3.
Pin 4 = OSC IN |
H: Need help in designing a BJT Amplifier with Avnl = 100
For our final project, we need to design a "single-stage BJT-based highpass amplifier using voltage divider configuration".
The amplifier has the following requirements:
\$V_{CC} = 12V, f_L = 300 Hz, Vs = 300 m V_{pk-pk}, and A_{VNL} = 100 to 300 \$.
I decided to use a 2N3904. And the following is what I have so far
I set the voltage at R2 to 6.35 to have the maximum swing for the output. I set R2 to 10k ohms and R1 needs to be 8.87k ohms to set the voltage divider.
\$ 6.35 = 12 \times \frac{10k}{10k+R1} \$
Next, I set \$I_C = 10 mA\$. Then \$R_E = \frac{6.35-0.7}{10mA}=565\Omega\$.
For the gain to be 100, \$R_C = 100\times re = 100\times\frac{26mV}{10mA} =260\Omega\$
For the capacitors, I use the formula \$1/(2\pi\times R\times300) \$ and then
increase it a bit more.
The problem is then I can only get a maximum of \$2.39V\$ and a minimum of \$ -3.439V\$. I don't what else I can do.
Thank you for the help.
EDIT:
Here is the result of the DC point analysis:
Based on my understanding, the DC point analysis looks good to me. That being said, I still do not know what I am missing to make it work.
AI: There are a bunch of problems with your circuit. Your collector is at 9.5 V and your emitter is at 5.3 V. I would expect the output to swing between -3.2 V and 2.5 V having 1 V across the collector emitter to keep the transistor biased. You need to bring the emitter voltage down to about 1 V. Put your Q point at half the supply voltage.
Your decoupling capacitor is too low for 300 Hz. The 50 uF capacitor has an impedance \$X \approx 10\ \Omega\$. This will decrease your gain significantly. Even worse, the impedance is frequency dependent. So the gain will change with frequency. If you decrease the biasing current, it will have less of an effect, as the resistors will all increase in value.
The standard method for controlling the gain is to put a resistor in series with the emitter capacitor. Then the AC signal will see a resistor as well as a capacitor at the emitter. |
H: Overlay plots from PSpice - SIMetrix or SIMetrix to PSpice
I wanted to verify the accuracy of a identical model which I modelled, between PSpice and SIMetrix simulator
I ran model in Pspice and SIMetrix separately and probed required nets (net names are identical in both the simulators)
Saved the file of SIMetrix in .dat format and appended in PSpice as shown
So I tried another approach to overlay in MS-EXCEL or Libre office and exported the simulation plot in .CSV but I couldn't find option to export SIMetrix plot in .CSV or any other format.
Is there any different approach to do this exercise?
AI: This might be one of the alternatives,
OVERLAY from SIMetrix to PSpice
Goto > SIMetrix simulation window >edit> copy ASCII data
Paste the data cntrl+v in Notepad and save it in .txt
Import the saved .txt in PSpice
Generate .dat using .txt file |
H: Using 2 postive regulators with 2 prong power supplies for bipolor power supply
My nephew and I have been working on a circuit that uses +/- 4.5V. Up until now we have been using 2 3-AAA battery holders to supply each leg and now wish to move to mains power.
My question is, discounting the more unusual topographies(auto transformers, cap dividers), is it safe to assume that 2 2-prong 5V(12V) power supplies are isolated from each, and therefore I can use 2 positive regulators to regulate the output. As noted in some of the comments, I have metered inside/outside of the barrel to each prong, with all of them showing open.
I know I can use 2 separate taps from a transformer for this.
In the past I've used 2 supplies like this in a audio application(sans regulators), and it worked fine.
If it comes down to it, I can dig out a multi-tap transformer(not a center-tap) and use that, but that's a lot of work, and the result is much heavier, hotter and less efficient compared to using 2 wall-warts.
And as far as I know, using an inverted buck DC/DC still requires a negative regulator.
AI: If you view the output of a black box that has two wires coming out from a power source inside, one ++ and the other -- you would never know if it was a negative or positive regulator. In addition any current flowing out the ++ has to flow back in the -- wire when a load is connected between the two. All just depends on what you bring out as GND.
So as long as the wall warts that you use have:
100% isolation between the input AC terminals and the DC outputs
No connections to the AC side safety GND
You can use the two wall warts along side each other, one as the +V supply and the other as the -V supply. Just tie the opposite sides of each together to become the DC circuit GND. |
H: What is IDC connector pitch on a USBAsp?
I am planning to use a USBASP programmer to program one of my boards, and I want to use a fitting receptacle on my board. I fail to find the exact pitch that the USBAsp's IDC connector has (as I understand there are 2mm and 2.54mm pitches). Does anyone have any info?
AI: I found this repository containing some design files and although the board is different from the one I'm gonna use, I'm assuming they do follow the same standard. The pitch on this one is 2.54mm. Feel free to correct me, but until then, I'll leave this as an answer. |
H: Calculating resistance for integrated circuit with logical gates, so that the circuit works properly
I have found this task with its solution:
For the circuit shown below calculate \$R\$ so that the circuit works
properly. All gates belong to the \$TTL\$ series.
Solution:
$$\begin{align*}R_{max} &= \frac{V_{CC} -
U_{OH_{MIN}}}{\color{red}{N_O} \cdot I_{OH_{MAX}} +
\color{blue}{N_{I}} \cdot I_{IH_{MAX}}} = \frac{5 -
2.4[V]}{\color{red}{4} \cdot 250 + \color{blue}{3} \cdot 40 [\mu A]} = 2321 \Omega \\ R_{min}&= \frac{V_{CC} - U_{OL_{MAX}}}{I_{OL_{MAX}} -
\color{blue}{N_{I}} \cdot I_{IL_{MAX}}} = \frac{5 - 0.4 [V]}{16 -
\color{blue}{3} \cdot 1.6 [mA]} = 410 \Omega \end{align*}$$
Please ignore the actual current/voltage values, they come from the \$TTL\$ specification.
My questions are:
how can I determine what's input and what's output?
To my 'sense', \$ABCD\$ are inputs while \$XYZ\$ are outputs.
Why \$\color{red}{N_{O} = 4}\;\$ (number of outputs) and \$\color{blue}{N_{I} = 3}\;\$ (number of inputs)?
This is the part I am struggling with.
How can I determine what's input, what's output and how many of them are in the circuit diagram?
AI: It would probably have been clearer to put the letters right on the gates themselves. "A" refers to the output of the gate just to its left, and the same thing applies to "B", "C" and "D". Similarly, "X" refers to the input of the gate to its right, and so on for "Y" and "Z". |
H: VHDL: Port mapping to physical pins when you have "subcomponents" inside a component
Let's say you have a project in VHDL that looks something like this:
Generally it's pretty easy to map the ports together between Component 1 and Component 2. However, what if Component 1 is code from another VHDL project that you created earlier, such as a binary to seven segment decoder, which also contains components inside it that has been port mapped together as well. Then how do you Integrate Component 1 into the final project (the Top Module) and map it together with Component 2, when Component 1 already contains components that has been mapped together?
Could someone provide an example?
AI: I've never seen components "encapsulate" any external pin mappings – they are, instead, logical modules with a clear interface.
The external pin mapping is done on a project, not on the component level. |
H: What is the range of feedback resistors of LM2577 adjustable version?
I am making custom boost converter with LM2577 adjustable version.
I have a question about selecting feedback resistors R1 and R2
For R1 and R2 formulas available in the datasheet, but they do not specify the range kilo or mega or just ohms.
Which range I should use? Ohm range or kiloohm range?
AI: The typical application from the datasheet shows feedback of a few k\$ \Omega\$.
Digging a little deeper for an underlying reason, look at the input bias current on the feedback pin (which is attached to the error amplifier)
At the maximum possible current, a resistance in the 100s of K\$ \Omega\$ or M\$ \Omega\$ would give a significant error from the feedback network; keeping the values below a few 10s of kohms minimises that error.
I would use resistors in the range of a few k\$ \Omega\$ for this. |
H: Does an ISP clock interfere with the on-board clock when programming via ISP?
I am planning to use ISP programmer to program my new AVR board. I use an 8 MHz crystal on my PCB to clock the micro (atmega328p-au). Now, as I understand the ISP programmer will provide its own clock to my board when programming. It occurs to me that this might pose an issue. I've read that using an SPI clock much slower than the system clock is the way to go, but haven't found any specific documentation. Any suggestions? Thanks!
AI: ISP clock can't "interfere" with on-board clock. ISP clock is the clock for the ISP data. The MCU still needs a clock to run itself, and this clock needs to be high enough for the given ISP clock. Slower MCU clock needs slower ISP clock for sure, exact parameters are given in AVR datasheet. |
H: Question about a circuit problem with opamp
I would like to solve the following circuit, but I can't understand why i1=0, whereas i2=v2/R1.
If i2 is not equal to 0, where does the current go after the first resistor?
AI: Call the node connected to the negative terminal of the voltage source ground.
The left side of R1 is at 0 V because it's connected to ground.
The right side of R1 is at 0 V because it's connected to the virtual ground at the summing node of the op-amp.
Therefore there's no voltage across the resistor, so no current through it.
If i2 is not equal to 0, where does the current go after the first resistor?
Into the output pin of the op-amp.
The output pin of the op-amp behaves (somewhat) like an ideal voltage source. An ideal voltage source can have whatever current is necessary through it, positive or negative, to produce the voltage it is sourcing. |
H: What is the proper configuration for an adjustable voltage divider circuit
I am making a circuit that need a voltage reference that is adjustable. The the answer that many of us would think of is a voltage divider.
There are 2 configurations that I thought this can be done, and it is only now that I have wondered which is the proper or probably the best.
The configuration on the right seems to be the most optimal since it requires less parts.
Are the two configuration essentially the same? If not what are the pros and cons of the each configuration?
AI: The right one is the best for a number of reasons, the left version is very rarely used:
1: The right one can be adjusted linearly from 0-100% (assuming a linear law potentiometer). Or it use a logarithmic law potentiometer that is preferred for audio applications.
2: The left one depends upon the actual resistance of the variable resistor that is usually not very well controlled (maybe 10-20%). The right one does not depend upon the absolute value.
3: The left one cannot be adjusted to give zero output. The minimum is when RV2 is at its maximum value, but the output will not be zero.
4: The left one puts a significant current through the wiper of the variable resistor. Because of contact resistance variations as it is adjusted this can cause noise in the output. It is not at all suitable for audio value control. |
H: Operation of this circuit
I have this circuit. I did the truth table but I wasn't able to understand what operations this circuit do on pair of 2-bit binary inputs (A1, A0) and (B1, B0).
I thought it was mod or div but it's not
AI: Is n't that a simple 2-bit multiplier ?:
No idea how can I format like this. So doing on my notebook. |
H: How does this strobe light circuit work?
I took apart the top of my strobe light and couldn’t exactly understand parts of the circuit. Could someone explain how it works?
When the strobe is plugged in, it immediately starts flashing and doesn’t stop until unplugged. The three wires are attached to a knob on the outside, that increases the flash speed as it’s turned clockwise.
AI: This circuit is probably similar to what you have. It is from my high school electronics class, 45 years ago. The first project that I ever built. Too dangerous to be built in schools today. THIS CIRCUIT CAN KILL YOU!
C1/D1/D2/C2 are a voltage doubler. C2 quickly charges to about 300VDC. C4 also quickly charges to about 160V.
C3 slowly charges until the threshold of the diac is reached. It then discharges through the SCR gate. This causes the SCR to conduct, which causes C4 to discharge through the trigger coil, causing a high voltage pulse on the trigger coil secondary, which ionizes the Xenon gas.
When the Xenon gas is ionized, it creates a path for C2 to discharge. The C2 energy is what causes the flash. A higher value C2 will cause a brighter flash, but you won't be able to fire it as often. After C2 is discharged, the cycle repeats.
The trigger coil used to be sold by Radio Shack. It has a very high turns ratio, 1:100, probably more.
Why are all 3 leads connected to the potentiometer? It is an old habit of EEs. With only the wiper and one end connected, a intermittent wiper would cause infinite resistance. With the 3rd lead connected, an open wiper will default to be the same as fully CCW, or fully CW.
Edit: added simulation.
Note that since Circuit Lab doesn't have models for the SCR or Diac, equivalent circuits were used. I didn't model the Xenon tube, so the plots are not valid after the SCR fires. C2 would normally discharge through the Xenon tube and the cycle would start over again.
To keep the plot readable, the trigger transformer only has a ratio of 1:5, in reality it is much, much higher.
Since I was not allowed to have 2 editable schematics in an answer, the first was changed to a picture.
simulate this circuit – Schematic created using CircuitLab |
H: Vector Analyzer: what is IF bandwidth?
I noticed that if I set IF bandwidth low, the measures done with a vector analyzer are better (with higher SNR) but it is slower.
Precisely, what does it happen when I change it? Can you explain me simply what it represents?
AI: Many receivers, such as your vector analyzer, use a superheterodyne receiver (https://en.wikipedia.org/wiki/Superheterodyne_receiver) architecture. These are distinct from other receivers in that they use an Intermediate Frequency (IF), or multiple IFs, as opposed to either just directly using the RF coming in, or down converting the signal to baseband (i.e. from DC, or near DC, and up rather than bandpass around some carrier frequency).
Some of the key advantages of doing this are: filters can be made more selective at lower frequencies, it's easier to make tuneable oscillators than it is amplifiers and filters, and lower frequency components tend to be cheaper and perform better. These advantages also apply to direct conversion down to baseband, but there are other challenges there.
So in your VNA:
What it does is measure the response of your network over a bit of the spectrum at a time.
It sends out RF signals at some frequency and analyzes the reflections. A tuneable oscillator is fed into a mixer with the incoming reflections. This down-converts the reflections from their RF frequency to a fixed IF.
This allows filters and amplifiers designed to operate at a fixed IF to be used across the whole range. Making the bandwidth of this IF section smaller lets you look at a smaller piece of the spectrum at a time. This has two impacts:
Generally less spectrum will have less noise in it
To look through the whole range you want to it, it will take more time to do the sweep
Edit: I suppose also the rise time of the IF signal's envelope would be slower with a narrower bandwidth. |
H: Selecting transformer voltage for lamp drawing 32W and 6.6A
I have a lamp with the following known specs:
32W
6.6A
AC
Applying p = V x I, I expect the required input voltage to be 4.8V AC.
However, this seems to be an unusual input voltage for a lamp. For context: this is a MR-16 style quartz (possibly halogen) bulb, listed as part number 21127 here.
The only specs given for this lamp are watts and amps, above, so I cannot confirm voltage via their documentation. The typical application of this bulb is part of a significantly more complex circuit involving a constant current regulator.
I have tried looking for a 120V AC --> 4.8V AC 6.6A transformer without success.
My questions:
Is finding a transformer outputting 4.8V AC at 6.6A actually the simplest way to power this bulb? What alternatives exist?
Could the transformer output DC instead of AC without harming the bulb?
What are the consequences to the bulb of using a transformer which outputs a more standard 6V or 12V?
What are the consequences to the bulb of using a transformer which outputs less than 4.8V?
My guess is exceeding 4.8 volts would cause the bulb to burn out faster, whereas less than 4.8 volts would cause the bulb to emit less light (but would this be harmful to the transformer?). I also expect transformers outputting either DC or AC could be used.
Thank you for your guidance.
AI: The 2009 Cooper Crouse-Hinds catalog for airport runway lights indicates some of the lamps require a constant current power supply, i.e. a special transformer designed to prevent the inrush current spike that shortens lamp life. Look to the fixture manufacturer for a replacement.
On the other hand, if you're just experimenting with a lamp, likely surplused because of replacement by efficient, long-life LED's, try gradually increasing voltage on the lamp until 6.6 amps are drawn, and check the voltage at that point. You could then use an ordinary transformer of that voltage rating, but with shortened lamp life.
You also might try an old desktop PC power supply that has 5 V DC output, putting a one ohm variable resistor (rheostat) in series, gradually reducing the resistance. To make your own rheostat, use nichrome wire from a heating element, with a bolt and nut slider. About 30 cm of 0.65 mm (22 AWG), 50 cm of 0.80 mm (20 AWG) or 1 m of 1.0 or 1.2 mm (16 or 18 AWG) should be ample. Use thicker wire if possible to spread out the heat... don't burn the fingers.
BTW, don't touch the quartz lamp, or wipe with alcohol if touched, to avoid damage from sodium in sweat. |
H: Voltage divider reverse formula
I have this schematic, with an power supply of 24V and I want to read this voltage with my arduino so i need a voltage divider, the formula for voltage divider is Vout = (Vin * R2)/R1+R2, so with my data, Vout is 2.824V (24 * 10000)/75000+10000.
So what is the reverse formula to convert 2.824V to 24V, for printing on my serial monitor?
AI: It will look something like this:
$$V_{OUT} = ADC\cdot \frac{V_{REF}}{1024} \cdot (1 + \frac{R_1}{R_2}) $$
Where \$ADC\$ is a value (between 0...1023) read by Arduino ADC. and \$V_{ref}\$ is an Arduino ADC reference voltage.
Or to answer your question directly
$$V_{CC} = V_{ADC} \cdot (1+\frac{R_1}{R_2}) = 2.824V \cdot8.5 = 24V $$ |
H: How to calculate the value of the thermistor based on the output voltage of this circuit
I recently bought a board that consists of this circuitry. It came without an instruction whatsoever, so I have to figure out how to measure the temperature based on the output voltage at the To.
The circuit consists of a Wheatstone Bridge of R13-R15 and an NTC thermistor TH1. the voltage between point A and B Vd then go through a differential amplifier U3A and then further amplified by U3B. I don't have a volt meter or oscilloscope with me, what I did is read the To using an Arduino ADC and convert it to Voltage output. In order to calculate the temperature, I need to know the thermistor value based on To output voltage, I sort of know the basic theory on how this circuit works, but not quite able to figure out the relationship between To and the resistance of the thermistor yet.
Here are my questions:
1) What is the gain of this overall circuit?
If I read it correct, it has a gain of 12, so Vd = To/12, is this correct?
2) Once I derive the Vd, I assumed that:
Vd = Vref * R14/(R14+R15) - Vref * R15/(R15+TH1)
and further derive from this formula to get the TH1 value. Again, what is the correct formula for getting the resistance value of TH1?
But so far what I get seems to be way off from the correct temperature.
AI: This circuit can be split into four sections
Reference generation
Wheatstone bridge
Differential amplifier
1st order filter
non-inverting amplifier
Reference Generation
A simple voltage divider from Vcc and buffered to provide a low-impedance source to the bridge:
U2B V+ pin sits at 0.5Vcc and thus Vref ~ 2.5V (accuracy of the rail and resistors dependant)
Wheatstone Bridge
The resistors around the Thermistor (R13,14,15) are 10k so it is safe to assume that the Thermistor is a 10k at some reference temperature.
The thevenin equivalent at this operating point for nodes A & B is therefore 5k with the voltages at these nodes being 1.25V
simulate this circuit – Schematic created using CircuitLab
Differential Amplifier
Assuming you forgot the 20k from V+ to GND, the differential amplifier stage has a gain of \$ \frac{ 20k}{10k + 5k} \$ = 1.33
simulate this circuit
1st order filter
This will provide some attenuation at non-DC temperature changes, but assuming the rate of change of thermistor resistors in << the 3dB point of the 1st order filter, this will not change the gain of the circuit (except for a leakage component)
non-inverting amplifier
The final stage is a classic non-inverting amplifier with a gain of 11 ( \$\frac{100k}{10k} + 1\$ )
Overall gain is therefore 14.63 when the temperature is such that the thermistor presents 10k resistance.
As the temperature changes then the bridge impedance will change. This will produce a non-constant impedance and thus the gain of the differential amplifier will also vary with temperature. If this is acceptable this is a cheap implementation. Creating an instrumentation amplifier would produce a more constant impedance and thus gain response. You have an unused OPAMP so this is a possibility |
H: USB 2.0 High-Power Circuit
Is there are special circuit that says to USB socket how much current the device needs?
Our device needs at up to 200mA or little bit more.
I have been searching but I do not find a clear answer anywhere. Should there be resistors on data lines or something else?
Unit load for USB 2.0 is 100mA and for USB 3.0 it's 150mA according to Wikipedia.
How does a the host know how much current to supply?
How does the slave ask for load units?
AI: For USB 2, a device cannot take more than 100mA until it has enumerated with host and it has host permission to draw more. Host keeps track how much devices have already requested and how much is still available for more devices, and based on this it either allows the device to use requested power amount or not. Basically, a device can't draw 200mA without asking.
For USB 2 chargers, the charger is just a power supply and has resistances to indicate to device that how much the device can draw. |
H: Are there multiple bits on a data cable at the same time?
Let's say there is a copper under sea cable from New York to Lisbon with a length of 5350km.
Then a signal needs approx. t = 5350km/c ≈ 19ms to arrive.
Now let's imagine sending a file from New York to Lisbon.
I assume that you don't have to wait until one bit arrived before sending the next bit.
Because if you would have to wait you would have a speed of only 1000ms/19ms ≈ 53bit/s.
So let's instead assume a speed of 1 MBit/s (still slow).
That would mean there are 19ms*1MBit/s = 19000 bits on the wire at the same time.
I did the same calculations with a standard LAN cable of 20m. With a speed of 10 MBit/s you can wait. But to get a speed of 100 MBit/s there must be multiple bits on the wire at one time.
Is that correct?
AI: It's just like radio — when you're listening to an FM station at 100 MHz, the individual carrier waves are only about 3 meters long, so there are many hundreds or thousands of them "in flight" between the transmitter and you at any given moment.
Adding a copper wire transmission line does not really change this in any significant way. |
H: How to make gain margin 6dB
So I have a non-inverting opamp configuration R1=20k and the system starts to oscillate if R2 is less than 20k. I need to make the gain margin equal to 6dB by choosing the right value for R2.
AI: Here is a circuit with gain of +0.1 ( -20dB gain, but INPHASE) and the opamp has rolloff well below Unity Gain Bandwidth. What to do?
try this compensation approach: make the noise gain 6dB higher (or even more, if you need) at very high frequencies, using a series RC from virtual-ground to Ground.
simulate this circuit – Schematic created using CircuitLab |
H: stm32f429 hardware development
I have built a custom stm32f429 board. It uses SPI, I2C, UART and CAN for communication with various sensors. This is my first stm32f429 board, i've designed boards around stm32f3 and f1 series before. I'm using SWD interface via the stlink-v2 debugger/programmer. The STLink utility recognizes the board without any issues and i can even program the chip with STLink.
However with openocd the board is detected without any issues, but i run into the following error when doing a "reset halt" from the telnet session.
"target stm32f4x.cpu not halted"
Following are the openocd commands i use:
openocd -f ~/openocd-0.9.0/tcl/interface/stlink-v2.cfg -f ~/openocd-0.9.0/tcl/target/stm32f4x.cfg
In a separate window
telnet localhost 4444
My initial diagnosis was that this is definitely related to the NRST circuitry. So i checked if PDR_ON is connected to Vdd since according to AN4488, if PRD_ON is pulled to GND the internal power on reset and power down reset circuitry is disabled. PDR_ON voltage is 3.275V, which is the same for all VDD pins. VCAP1 and VCAP2 are at 1.132V and i'm using 2.2uF caps on VCAP pins.
External reset circuit is pretty simple. I have attached the relevant snapshots of the schematic here for reference. Please do let me know how to proceed with further diagnosis or if i've missed something in the design of the board.
P.S PDR_ON is connected to Vdd. In the schematic it is left unconnected.
AI: NRST pin is hardwired directly to VDD so not all ways to reset the MCU core are available. |
H: Basic Dependent Source Circuit Problem
https://ibb.co/JmBt71D
Here, i added a image of the circuit problem.
I wonder how to solve it.
Firstly, i found a equation with respect to KVL for the left side of the circuit: -36+24*I+12*I=0 and I=1A so, VΔ=12V
Secondly, the current of VCCS is causing trouble because it depends on VΔ but this is current source so, should i think it like behaving as DC 0.5VΔA=0.5*12A= 6A ?
After the comment of "The Photon" (thank you!) i have learned that we should think like there is no current flows on the wire that i0 is shown on. So, i0=0.
Lastly, for the right part of the question.
There is no independent source and there is only a VCCS= 6A(?). The resistors are parallel connected so, their voltages must be equal and the current 6A dissipated as 2A through 20ohm Resistor, 4A through 10ohm Resistor. Then, by the KCL, 6A+i1+i2=0; The values must be like this i1=-2A, i2=-4A.
VΔ= 12V , i1=-2A, i2=-4A, however, I am not sure about my results. Are my assumptions and thinking correct ? and, Can you please help me about checking calculations ?
AI: Physics 101
To get one thing immediately straight, imagine what would happen if there was a current along that wire connecting the blue circle of "matter in the universe" and the green circle of "matter in the universe?" (The assumption here is that \$i_0\$ is continuous and not a momentary "charge balancing" event.)
Not good stuff. A charge differential would build up between the two until -- no matter how far apart these two bits of matter were in the universe, even millions of light years apart -- there would be an arcing of charge to neutralize these two bits. And that assumes you had some way of nailing them down so they didn't move. More likely, they would vastly overwhelm any separating velocity or otherwise gravitational forces pulling them apart and would instead slam back towards each other with an impact that would shake the universe. (Maybe another "big bang?")
So you know without any thought at all, simply from basic physics and forget the electronics part, that these two separated "blobs" do not have anything other than \$i_0=0\:\text{A}\$. There's no other option, if you start with \$i_0\$ as continuous through all time and not a momentary event.
Electronics Analysis
That's one of your questions out of the way. So this means you can analyze these two circuits, separately, except that there is some "magic" in that something is measuring \$V_\Delta\$ in the blue-circled circuit and using that information to impel a current source magnitude in the other one. That doesn't violate common sense physics, so you can proceed.
The blue circled circuit on the left is a trivial voltage divider. So just compute, holding the bottom wire for now as the default "ground reference":
$$V_\Delta=+36\:\text{V}\cdot\frac{12\:\Omega}{12\:\Omega+24\:\Omega}= +12\:\text{V}$$
That confirms your own results I see near the bottom of your question.
The voltage-dependent current source in the green circled circuit on the right is then \$I=0.5\cdot V_\Delta=6\:\text{A}\$. As this value is positive and not negative, the computed current must point in the direction of the arrow given in the diagram, too.
I just want to make sure that you recognize that the the "0.5" you see
there has units of amps divided by volts, or Siemens. So the
equation is really either \$i=0.5\:\text{S}\cdot V_\Delta =6\:\text{A}\$ or else
\$i=\frac{V_\Delta}{2\:\Omega}=6\:\text{A}\$. Lesson here is never
forget dimensional analysis. This isn't mathematics 101. It's
physics/electronics 101. Mathematicians can treat all numbers as
unitless. A physicist or engineer doesn't have that freedom. Reality
IS and you always need to make sure that the units work out. It's a basic sanity test and, used properly and with wisdom, can be used to
guide you correctly in the right direction towards solutions you've
never dealt with before.
Now, in keeping with the idea that the bottom wire within the green circle is in fact tied to the bottom wire within the blue circle, where we treated that node as "ground", there is only one unknown voltage node in the green circle and we can use KCL for that node (call it \$v_x\$) and also add a few details regarding the resistors:
$$\begin{align*}\left(i_1=\frac{v_x}{20\:\Omega}\right)+\left(i_2=\frac{v_x}{10\:\Omega}\right)+\left(i=6\:\text{A}\right)&=0\:\text{A}\\\\\therefore\\\\v_x&=-40\:\text{V}\end{align*}$$
And from there I know the rest is trivial to work out. You already have your results, in fact. |
H: CAN Bus multidirectional
I am currently looking for a uC for a project of mine which needs a CAN interface. This would be my first project using CAN. Since I want to send and receive messages between the master and at least 8 slaves I was wondering about the amount of CAN ports I need.
According to this post I can send and receive messages on the same uC using only one port.
Looking at the Part selector of Microchip one of the fields says 'CAN Receivers buffer' and 'CAN transmitters buffer', which suggests otherwise.
Can I use them on the same bus or do I need a busline for sending and a separate one for transmitting?
AI: The point of CAN is that you have (usually) a single controller and a single transceiver in a CAN node (some safety critical systems may have more than one bus for redundancy).
All CAN nodes talk bidirectionally over the same single wire pair.
The number of transmit and recieve buffers (and filters / masks) reduces the load on the firmware. For example if have 8 transmit buffers and you want to send 5 messages that have lower priority than the current bus traffic you can simply load all of them at once and the controller will send them whenever the bus is available. If you have only one buffer, then you can queue just one frame in the controller and the firmware needs to queue the rest. |
H: How to solve a two BJT circuit?
Please could someone help me understand how to solve this circuit?
AI: IF that is your hand-writing, may I complement you on artistic expression and sense of scale.
Unfortunately , I can barely print my own name after recent surgery from a random event called hand Ischemia with TOS bypass and nerve damage. So I resort to a quick mouse drawn simulation.
Since this is just a two stage emitter follower, the best you can hope for is unity gain and DC bias not to screw up the signal. Unfortunately Q2 hFE has a significant effect on the input impedance and resulting 16k voltage divider effects.
Can you read the resulting DC out and AC Vpp attenuation?
Then figure it out.
Left is input, right trace is output. hFE1=20, hFE2=50 |
H: What is the difference between transresistance and differential resistance?
Transresistance is defined as the change in output voltage over change in input current. While differential resistance is defined in the same manner. So what is the difference ?
AI: Transresistance, as given by the definition, refers to an input current and an output voltage. Thus the current and voltage are not meassured at the same points. For example, the transresistance of an amplifier is the ratio of the change in output voltage of the amplifier to the input current of the amplifier. Differential resistance, on other other hand, refers to a current and a voltage measured at the same points. It is usually used to describe the behavior of a non-linear resistor. A linear resistor exhibits the same resistance (ratio of voltage across it to current through it) independent of the actual magnitudes of the voltage and current (at least up to its power limits). A non-linear resistor will have a varying resistance depending on the magnitude of the current through it. The differential resistance of such a device is the ratio of a small change in voltage to the resulting change in current measured at some fixed voltage level. It will change as the fixed voltage level is varied, which is why the resistor is designated as non-linear. At any rate, the difference in the two terms is the points where the voltage and current are measured: different points for transresistance (which is what the "trans" refers to) and at the same points for differential resistance. |
H: GPS relative positioning
I have a set of 4 rovers crawling on the ground, each of them equipped with a standard GPS positioning system. The rovers start together from a known position. Each rover is locating itself via GPS.
I command the rovers to move 1 meter straight, with a control loop on the GPS positioning. GPS absolute accuracy is larger than 1 meter but how do they behave relative to each other?
Atmospheric conditions can influence the absolute accuracy but the 4 rovers are very close to each other (let's say in a range of 10 or 20 meters). Shouldn't all the GPSs on board be influenced in the same way?
If that is true, the relative positioning should be kept and after crawling for 1 meter forward, the relative position of each rover should be the same. Is that correct?
AI: Atmospheric conditions can influence the absolute accuracy but the 4 rovers are very close to each other (let's say in a range of 10 or 20 meters). Shouldn't all the GPSs on board be influenced in the same way?
Yes and no.
Yes, each signal from each individual satellite will induce the same satellite/receiver distance estimation error (due to propagation delay uncertainties and satellite position uncertainties) for all 4 rovers. If all rovers are using the same satellites to determine their positions, expect the position calculation errors to be similar, and the accuracy of their relative position to be pretty good. I'm assuming there are no significant reflections involved.
No, on stand-alone GPS receivers you have no control over which satellites are being used for the location calculation. You need at least 4 satellites, but 8 or more can be used if you have a good receiver and unobstructed sky view. In practice, the list of satellites being used in the calculation changes over time: satellites with borderline signal strength can be dropped or added to the list dynamically. If the lists of satellites used in two different rovers are different, you can no longer assume that the same errors will affect the position calculation on both receivers equally and the relative position accuracy will suffer as a consequence. Also keep in mind that the satellites are not stationary and over minutes new satellites will rise over the horizon while old satellites will disappear, what can make the performance of your system time-of-day dependent.
Technically, the best solution possible is to use RTK, as @AndersPetersson recommended. This technique was conceived to provide incredible relative position accuracy. Typically, you'll need a static reference station and a RTK-capable receiver on each rover.
A middle ground solution would be to use GPS assistance (A-GPS) if your receiver has that capability. The idea is to obtain correction parameters from the internet that will improve the absolute position accuracy of each individual receiver, what will indirectly improve the relative position accuracy among the rovers. |
H: (Micro) USB Timed Relay
I am currently trying to build a low power server with a Raspberry Pi I don't use any more (3B) but I am struggling to find a way to cut down it's power usage in it's off hours. Since the Pi uses ~100mA even when completely shut down, I am looking for a way to terminate the power going to it until such time as it needs to be booted back up for use. The server itself is intended to be outside my control for long (a month or more preferably) periods of time so anything that requires I be there isn't applicable.
Basically, I am looking for some kind of device or module that uses a very low amount of power, 5mA or less (preferably MUCH less), with micro-usb slots that either has a timer or can be programmed with a timer that will power off one of the slots after a certain time period and then turn it back on at another.
Below is a crude representation of what I am looking for.
The only thing I have found that even comes close is the Sleepy Pi (One example of where it's sold). However I really don't want to shell out $50+ for something that should be much easier to accomplish if I can avoid it.
AI: You want some form of "Real Time Clock"
Web searching RTC and/or "Real Time Clock" will show you much.
I'm advised that the RPM has no low power sleep mode.
While you cannot enable an internal micropower Pi RTC mode you WILL be able to have it woken (or turned on) periodically, allowing it to check if it wants to be awake and, if not, again turning itself off completely. A simple hardware counter and power up circuit could draw under 1 microamp and wake the system hourly or daily or ... . A more intelligent system (as simple as eg an Arduino or an RTC IC) would allow you to set the "delay time to next wakeup".
You could (with certainty) use an eg Arduino with wake up / alarm capability to restart the Pi. With due care (app notes available) current drain can be half an oily rag (ie under 10 uA with eae and under 1 uA with a little more effort.)
[A 100 mAh LiIon single cell will provide 10 uA for over a year].
There are numerous RTC ICs available.
Some will have "alarms" (interrupt drives or switched turn on, or ... for Pi).
Asian suppliers on AliExpress sell many RTC modules with a range of capabilities. Prices start from about $0.00 ish.
You COULD use a classic low power counter and power up and have the Pi check time etc and resleep if desired. The effort and cost would be higher than alternatives.
Ultra low power Arduino:
Here is how to operate an Arduino Pro-Mini (the Pro being an inexplicable but irrelevant label) at about 5 uA in sleep mode but WITH the watchdog timer running.
ARDUINO LOW POWER - HOW TO RUN ATMEGA328P FOR A YEAR ON COIN CELL BATTERY
He makes use of this excellent low-power Arduino library to achieve various low power modes.
Pro-Minis are available for $2 (or less) from China.
Aliexpress Arduino Real Time Clock - cveat emptor, as ever, but most probably OK.
Various RTC modules from Digikey here
and here
RTC 1307 'Hats' / modules ... intended for various systems
here
Olde Technology - CD4060 self oscillating divider:
It's been quote some decades since I've used these - but I think a wakeup oscillator with a current in the 1 - 5 uA region should be possible.
CD4060 - Digikey $US0.53/1.
Needs 2 resistors and a acapacitor to operate.
IC quiescent is 5 uA max, 40 nanoamp typical (! :-) ) at 5V.
Add oscillator current of Vcc/Rtiming - say maybe 1 uA or less, and the oscillatior gate may draw more in the transition region depending on how good a job they did.
See fig 12 for circuit. |
H: Trouble understanding thevenin's model from AoE Lab
I am using the AoE lab book to teach myself electronics. I am on the voltage divider section, and I am confused at their simplified explanation. I'd like to explain it a different way, but I am not sure how to understand the open circuit voltage.
For the following circuit:
simulate this circuit – Schematic created using CircuitLab
Calculating Vout is simple:
$$V_{out} = V_{in}\frac{R2}{R1 + R2}$$
$$V_{out} = 30\frac{10000}{20000} = 15V$$
Now we introduce a load into the circuit:
simulate this circuit
My approach to solving this myself was to turn the original circuit into a black box and imagine we are looking at it from the perspective of the output.
From reading, the short circuit current here will be
$$I_{sc} = \frac{V}{R} = \frac{15}{10000} = .0015A$$
The first of my questions is - why does only the first resistor matter for calculating the short circuit voltage? Shouldn't both resistors be...resisting in the circuit? Intuitively, is this because we are bypassing R2 via a short circuit and the voltage will just (for lack of a better term) ignore the resistor and follow the path of least resistance (ground)?
After this I need to derive the open circuit voltage. I am having trouble figuring out how to view the circuit in a way that makes this make sense. If I disconnect the load, the open circuit voltage would be the original Vout, would it not?
Basically, I am trying to derive the math that makes treating R1 and R2 in parallel make sense. I understand the thevenin resistance will be this value, and the thevenin voltage is equal to vout (15V) in this case. The explanations in the lab book, while helpful, sort of handwaved through this part (they began to talk about switching voltages and grounds to show which resistor matters) and I'd appreciate any help in understanding this section. I feel like it is critical to understanding circuit impedance (the next section) and I would like to fully understand it before moving on.
Thank you!
AI: You're close. I'm not sure how the AoE book approaches things, but I'd say you're introducing the load resistor too early. The point of using a Thévenin equivalent circuit is to obtain a model for the (sub)circuit in question, and then put a load on there and see how the circuit behaves.
In your case we have the following simple circuit (note that, for the time being, I will ignore the exact numerical values of the resistances and just focus on the general solution).
simulate this circuit – Schematic created using CircuitLab
I'm calling the output node "out" instead of "Vout" because we will be worrying about both its voltage and its current.
As you correctly point out, to determine the open-circuit voltage \$V_{oc}\$, we leave the output node open-circuit (infinite impedance to ground) and calculate the voltage at the node "out", which in this case is a simple voltage divider:
$$
V_{oc} = V_s \cdot {R2 \over R1 + R2}
$$
In calculating the short-circuit current \$I_{sc}\$, we short this output node to ground (zero impedance to ground). Since the output node is at ground potential, there is zero volts across R2 and therefore no current flows through it.
$$
I_{sc} = {V_s \over R1}
$$
Note that your approach above had an error, since you were using \$V_{oc}\$ instead of \$V_s\$ in this calculation.
As a side note, we can alternatively view the above two circuit setups in terms of parallel resistors. (Remember that, if you have two resistors in parallel, then the resultant resistance is always less than or equal to the smaller of the two resistances.)
In the \$V_{oc}\$ calculation, the low-side resistance is R2 in parallel with an infinitely high resistor, which is equal to R2.
In the \$I_{sc}\$ calculation, the low-side resistance is R2 in parallel with zero ohms, which is equal to zero.
Finally, to get the Thévenin resistance \$R_{th}\$, we can just divide the open-circuit voltage by the short-circuit current:
$$
R_{th} = {V_{oc} \over I_{sc}} = {V_s \cdot {R2 \over R1 + R2} \over {V_s \over R1}} = {R1 \cdot R2 \over R1 + R2} = {R1 \parallel R2}
$$ |
H: USB to UART Bridge IC question
I have a few basic questions regarding this USB to UART bridge IC
My questions are just from the hardware perspective. I have little to no software knowledge. So please bear with me and help me understand your answer in simple terms.
This IC converts USB protocol to UART protocol at the available 4 output channels, right? Is there any software within the IC that will do this conversion of protocol or do we have to write separately? Like, what should a hardware person keep in mind while using the IC? Like, just connect differential lines on Input and take 4 Tx,Rx lines on the output connected appropriately to the Micro or SOC or whatever IC?
If I have one USB 2.0 running at 480Mb/s connected as the input, how is speed and addressing done for each channel? Will all output UART channels operate at the same speed? What happens if two output channels require value from USB at the same time?
AI: Usually when you have a multichannel USB to UART bridge it simply appears in the system as multiple serial ports, so you don't need anything special to communicate over one of the UARTs. In Windows for example you will simply have 4 COM ports.
The datasheet says that an individual UART can go up to 12 Mbps. Each channel speed can be set separately (just like in every other serial port). USB does not have very predictable timings, but you can count on the chip (and you operating system) to reliably deliver all the data. That is what the FIFOs in the chip are for - to hold the data until it can be transmitted. |
H: I2C data sampling is done at clock edge or level
I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication.
One thing that I could not understand is related to the sampling of the data at the SDA line. Is it done at the falling or rising edge of the SCL line or is it done at the SCL HIGH or LOW level?
AI: Data transfer-
The state of SDA(high or low) can change only when SCL is low. This means SDA must be stable when SCL high.
Sampling is done while the SCL going 0 to 1 state. Changing SDA when SCL is low provides some timing margin for accurate sampling.
As for I2C itself is a mutual interface standard. Both sides(TX and RX) can control the SDA line in different times. So SDA pins on both sides must be birectional.
Start and Stop Conditions-
Start: when SCL:HIGH , Falling edge of SDA occurs
Stop: when SCL: HIGH , Rising edge of SDA occurs |
H: Relating input torque on BLDC motor shaft with output current
I am trying to build a drone generator with a gasoline engine and a 14-pole,170KV, 2KW BLDC skateboard motor (this one). Before designing the system and running it, I wanted to clear out a fundamental doubt that has been troubling me. Details are as follows:
At a given voltage, how is the maximum output current that my generator can deliver related to the input torque at the generator shaft? Would increasing the input torque on the generator increase the current delivering capacity of my generator?
I am aware about the fact that at constant supply voltage (hence speed), a BLDC will draw different currents for different propellers due to difference in aerodynamic loading.
Also,in brushed permanent magnet dc motors, at a constant voltage, the motor will draw whatever current it needs from the source (with a little voltage drop) OR if I use a brushed dc generator, I will be able to generate larger currents (at the risk of burning my coils) at constant voltage (const. shaft speed).
Will the same hold true in case of a BLDC?
Please share your views.
Cheers.
AI: A useful expression.
With about 2% error -
Mechanical power into an alternator (or any shaft).
Watts = kg.m torque x RPM.
That's a rehash of Power = work per second
= Force x distance per second.
For a rotating shaft distance = radius x 2 x Pi x RPM/60.
Force = torque/radius.
Cancel and you get Watts = 2 x Pi x RPM/60 x torque_Nm.
= Torque kgm x g x RPM x 2Pi/60 ~~= RPM x kg.m torque :-)
Your BLDCM used as an alternator will make somewhat LESS volts per PPM ("KV") when used as an alternator than its motor spec.
Motors and alternators BOTH produce a voltage - in a motor we call it back emf and the motor speed stabilises when back emf + resistive drop = applied voltage. At the same speed with the same emf produced the alternator output is the generated emf LESS the IR drop. Murphy winds both ways :-).
Ignoring mechanical losses:
Motor: - Vapplied = Vbackemf + IR
Alternator:- Vout = Valternator - IR
ie with motor the terminal voltage is higher than the generated AC backemf and for an alternator the Vout is lower than the generated AC. |
H: Removing delay in UART communication layer
I'm writing to a UART Device. So I'm doing the following:
I'm transmitting the message as follows:
HAL_UART_Transmit_IT(&huart5, data, size);
uint8_t d;
HAL_UART_Receive_IT(&huart5, &d, 1);
push_single(&_readBuffer, d); // push to ring buffer
Then I'm reeving the data and pushing it to ringbuffer
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
if (huart == &huart5)
{
if (!isFull(&_readBuffer))
{
uint8_t data;
HAL_UART_Receive_IT(&huart5, &data, 1);
if(data !='\000')
{
push_single(&_readBuffer, data);
}
}
}
}
in main i have to wait for data to be arrived and check if it's ok or not. I want to remove that delay:
char sendATcommand(const char *ATcommand, const char *expected_answer, unsigned int timeout)
{
char x = 0, answer = 0;
char response[200];
unsigned long previous;
memset(response, '\0', 200); // Initialize the string
safe_flushReceiveBuffers();
safe_write(ATcommand, strlen(ATcommand));
HAL_Delay(timeout); // delay until message arrive
previous = HAL_GetTick();
;
// this loop waits for the answer
do
{
uint8_t byte_avil = safe_bytesAvailable();
if (byte_avil != 0)
{
// if there are data in the UART input buffer, reads it and checks for the asnwer
response[x] = safe_read_single();
x++;
// check if the desired answer is in the response of the module
if (strstr(response, expected_answer) != NULL)
{
printf("\n");
answer = 1;
}
}
}
// Waits for the asnwer with time out
while ((answer == 0) && ((HAL_GetTick() - previous) < timeout));
return answer;
}
2nd problem:
I'm also receiving some garbage characters from the UART + correct message. I don't know from where those characters come from.
AI: HAL_UART_Receive_IT() only initiates UART receive. It doesn't wait until any data is received. Thus, when you check the variable 'd' straight afterwards, the byte might have been received... but maybe not. Only in HAL_UART_RxCpltCallback() can you be sure the data has been set to a valid value.
To complicate matters, if you have fast UART speed your code might not yet have setup the UART driver to receiving the next byte when the byte arrives.
What you should do is a single call to HAL_UART_Receive_IT() to start saving the maximum number of bytes to a large enough buffer, then check from you non-interrupt code if new data has been written by checking huart->RxXferCount or huart->pRxBuffPtr.
When you have received the last byte, stop the UART or simply ignore further data.
Pseudocode:
uint8_t buffer[200];
HAL_UART_Receive_IT(huart, buffer, 200);
uint8_t* nextToProcess = &buffer[0];
while (!timeout) {
if (huart->pRxBuffPtr > nextToProcess) {
uint8_t received = *nextToProcess;
nextToProcess++;
// Handle the 'received' byte here, checking for end-of-transmission
}
} |
H: Is there a limit for the max charger supply current for this power bank?
To charge this power bank 5V supply is needed through micro USB. It says FOR the power bank the charge current: ≤ 2200 mA.
What does that indicate for the power supply max current which charges this power bank? Does that mean one should use a 5V supply/adapter with Imax>2.2A or Imax<2.2A?
(Normally when we use a supply for a device we apply exact voltage with minimum current the device needs or more. For example a device with input sepcs 5V 2A would work fine with a supply rated for 5V 4A. But it wouldnt work for 5V 0.5A)
But in this case it is not that clear to me.
AI: The power bank should internally limit the charging current to a safe level, and automatically ramp the current down when approaching a fully charged state.
Therefore you can safely use a 5V 3A power supply. |
H: Input and Output Impedances of Single to Differential mode converter
I have this circuit that converts a single ended input signal to differential output signal. I want to understand how to calculate or find out its input and output impedances?
The two op-amps are in inverting and non-inverting configuration. Will this circuit work correctly as single to differential mode converter or should both of the op-amps be in the same configuration?
AI: It depends on what you're driving the circuit with. Your noninverting arm has infinite input impedance, and your inverting arm has relatively small input impedance. This could be problematic, but not in every situation. For example, if your input is some sort of piezo-device, you will be very unhappy.
The input impedance of the inverting input is \$330R \parallel 660R\$. The output impedances are small, approximately \$33R\$ on each branch. |
H: 3-way solenoid valve gets hot
I have this Bosch 3-way valve that I use in a hydronic system.
If I run 12V to energize the valve, it gets very HOT!
Is that normal with such valves?
AI: If this is definitely an on/off valve, which is designed to be either fully operated or fully released - see note below - then you can reduce the power it dissipates by reducing the drive power after you initially operate it. Solenoid-operated devices like valves and relays can normally maintain their 'on' state with a considerably lower coil current (holding current) than is necessary to switch them from 'off' to 'on' (operating current) though. After an initial 'hit' of the rated supply voltage to operate the valve, you should find you can reduce the voltage/current to a lower level and it will stay open quite happily with a lot less power.
You could devise a clever circuit to do this but unless you're short of space the easiest way is to use one resistor and one capacitor:
simulate this circuit – Schematic created using CircuitLab
L1 is the valve coil. Start by measuring its DC resistance, by connecting a multimeter on resistance range to the two coil terminals. You'll need to experiment with the values of R1 and C1 but I would start with R1 about the same as the resistance of the coil and C1 chosen for a time constant of about a second with that resistance, i.e. if L1 measures 100 ohms then try 10 000 µF for C1, if 50 ohms try about 20 000 µF, and so on. D1 is there to protect C1 from a voltage spike when you switch the power off; a 1N4000 type rectifier diode should be fine.
Obviously C1 must be rated for at least your drive voltage, and R1 must be rated for the power that it will dissipate. For example if the coil has a DC resistance of 60 ohms and R1 is also 60 ohms then once C1 has charged the current through R1 and the coil will be 0.1 A, and R1 and the coil will dissipate 0.6 W each.
One catch with this circuit is that if you try to switch the valve off then on again less than a few seconds afterwards, C1 will not have time to fully discharge through R1 and so the valve may not operate properly. Another is that if the coil resistance is really low, the size and cost of C1 may become impractical. If either of those is a possibility you may have to use something more complex e.g. a monostable timer to generate the 'hit' pulse - if so, ask and someone can help you further.
Note: if you had a proportioning valve i.e. one that partially opens one port and closes the other in proportion to the drive current, then this technique would not work well. In that case you could experiment with putting a resistor in series to reduce the current, as perhaps you wouldn't need the full 12 volts to fully close the 'normally open' port. |
H: I want to put a radio transceiver in the seatpost of my bike. Will it work?
I am a noob regarding electronics. I want to create a device for my bicycle using a GPS with an eByte E32 (a 1W LoRa SX1268 433MHz radio transceiver) and some batteries. The device will be in the seat post.
Will the RF transmitter work or it will create something like a "Faraday cage"?
AI: This is a surface-mount RF module, so you need to make a PCB to solder it on, unless you do some freestyle wire soldering. You also need an antenna, a GPS module, a microcontroller, voltage regulator and battery.
For the device to run from a reasonable battery for a month, will take a strategy on when to power on the RF module and the GPS, and even to take the MCU into power-save mode. Careless design of the electronics easily adds unwanted currents that can reduce your battery time a lot.
As an example, assume you want a 1000 mAh 3.7V battery (about 20 grams). A month of battery time is 720 hours, giving you a power budget of 1.4 mA on average. As comparison, a GPS often draws 15 mA. When your RF module listens it draws an additional 14 mA and when sending, it will briefly draw 650 mA. Plus the MCU. Maybe you can fit a battery 10 times this size, at 200 grams. That eases the engineering but you still have to consider the power draw.
As you categorize yourself as a 'noob' with electronics, I'd humbly suggest this is an advanced project that you need to develop in multiple stages as you learn more of the topics involved.
A Particle or Pycom development board could help you accelerate the process by providing built-in RF, microcontroller and easy addition of a breakout GPS module. Still, this doesn't solve the power problem.
As for your question on RF shielding, if the antenna (not the module itself) is enclosed in or even close to metal, the RF properties will be affected. Unfortunately even carbon fiber is conductive so it suffers the same disadvantage. You might be able to place the antenna in some clever location, connected via a thin coaxial cable as antennas often are.
The boring answer is I'd look for some ready-made solution if you want to go cycling anytime soon. |
H: TinyFPGA A Series Board programmer compatibility
Since the TinyFPGA programmer writes configurations to the Flash memory of the FPGA chip, can I use that programmer for A series boards on any LCMXO2 chip? Or can I at least use it for the same chip with a different package?
AI: From what I read, theoretically, yes. I see nothing in the wiring hardware specific to the chip. It's just a JTAG bridge direct wired to the FPGA where everything specific is handled on the PC side, so whatever FPGA the PC software supports. |
H: How to enter bootloader on a Embedded Linux System with no keyboard?
I am trying to reflash a microcontroller.
An instruction in the manual states that:
Power up the owa4x and press the space bar to enter the bootloader prompt
Insert the uSD card with the images to flash
Confirm a FAT32 formatted SD card is accessible
I only SSH into this microcontroller and as such it does not have a keyboard to press the space bar or a screen to see anything. If I am able to SSH I assume it's already booted up and too late to go to the bootloader, but prior to it I can't do anything because it's not booted yet.
How can I do an equivalent of that operation through SSH route?
Manual doesn't provide anymore insight.
Thank you for your help.
AI: What you have is not a "microcontroller" but rather an Embedded Linux System built around an Arm Cortex A8 "System on a Chip" (SOC)
Pressing space at startup is typically the behavior of a human-interactive bootloader, for example the very common Das U-Boot or proprietary alternatives of similar functionality. These are much like the startup / configuration menu of a desktop PC, in that they are small programs that run first on startup and allow selecting the source and configuration flags of the primary operating system to be run, in your case typically a Debian Linux. In addition to booting an operating system from removable media, in the case of more compact systems they may be configured with the capability to copy a new image to internal storage - though Debian systems are often large and complex enough that a (perhaps smaller) instance of the OS is booted and used to do the full copy.
Generally speaking the communication channel used is a serial port to be connected to a serial terminal. On the SoC itself this would be logic level (3v3 or quite possibly even lower) but on a finished product it may or may not be inverted and translated to RS232 levels.
You will probably need a serial terminal program and a suitable electrical interface - typically an adapter from your PC's USB port to either RS232 serial or logic level serial. You will also need to set an appropriate baud rate, though 115200 is quite common except for a few SOCs with serial timing issues that cause 57600 to be chosen instead (Additional settings of N81 with no flow control are nearly universal)
Ultimately the documentation for the product you are trying to use is hidden behind a registration portal. You'll probably need to jump through the necessary hoops to register, then study the documentation. This will help clarify if you will be interacting with U-Boot or some other bootloader, and if you will be doing the copy at that level, or if you will be allowing some instance of Linux to boot and then have that perform the copy to internal storage. |
H: LTspice not getting exactly -3dB point
Looking to answer another question on this site, to did some math and fired up LTspice to check some values and I am not able to the -3dB point.
I found the transfer function to be
$$ H(s) = \cfrac{1 + \cfrac{s}{\cfrac{1}{R_2C_1}}}{1+ \cfrac{s}{\frac{1}{(R_1+ R_2)C_1}}} $$
This equation was corrected based off the answer that @ThePhoton had pointed out.
Where the \$w_z = \frac{1}{R_2 C_1} = 10,000 \$ and \$ f_z = \frac{w_z}{2 \pi} = 1.592\$ kHz
The same is done for the pole
\$ w_p = 2000\$ and \$ f_p = 318.3 \$ Hz
On the plot above, I am measuring the output at R2, I have placed cursors as closely as I can get it to the \$f_p \$ and \$ f_z \$ and if we look at the magnitude I am getting -2.83 dB and -11.14 dB respectively.
It's like I am off by ~ 0.2 dB for both, because I am expected -3dB and -13.97dB.
I must be missing something. What is it ?
edit Adding my .asc file if anyone wants to try
Version 4
SHEET 1 880 680
WIRE 128 64 48 64
WIRE 336 64 208 64
WIRE 336 80 336 64
WIRE 48 128 48 64
WIRE 336 208 336 160
FLAG 336 272 0
FLAG 48 208 0
SYMBOL voltage 48 112 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMATTR Value2 AC 1
SYMBOL res 224 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 400
SYMBOL res 352 176 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL cap 320 208 R0
SYMATTR InstName C1
SYMATTR Value 1µ
TEXT 14 296 Left 2 !.ac oct 10000 1 10000
AI: First, your transfer function is not correct. You can see this must be true because your \$H(s)\$ has a pole at 0, while the actual response has the pole at ~300 Hz. I calculate
$$H(s) = \frac{1 + s(R_2C_1)}{1+s(R_1+R_2)C_1}$$
You could also write this as
$$H(s) = \frac{1+s/z}{1 + s/p}$$
where \$z = 1/R_2C_1\$ and \$p=1/\left[(R_1+R_2)C_1\right]\$.
Next, when you assume that the response is exactly -3 dB at the zero frequency, you assume that the pole is having no effect at that frequency. That is, you assume
$$1 + s(R_2C_1)\approx 1$$
But this isn't exactly true, so you don't get exactly -3 dB at the pole frequency. |
H: Optocouplers driving MOSFETs in an inverter
For many hours I was trying to simulate in LTspice XVII an optocoupler driver for MOSFETs in an inverter. My project is to build a SMPS with linear voltage stabilizer (I didnt put it on the schematic yet) that is conotrolled by AVR microcontroller. I've managed earlier to succesfully drive a MOSFET through an optocoupler but I couldn't succesfully apply it to my main schematic.
Here is the picture of my schematic of LTspice:
I don't know what seems to be the problem. My guesses are that I've made mistake somewhere in the schematic (most likely) or the optocoupler isn't capable of switching at 20 kHz.
Here is what I tried to solve:
I've tried changing the PULSE voltage source (microcontroller output) frequency to 200 Hz and the voltage on the 10k resistor at least dropped to 0 V (at 20 kHz it varied from ~10V to 15V).
Here is the picture of the voltage on the resistor (I suppose that is the Vgs) (10k - blue, 1k2 - green):
Changing resistance of the 10k resistor to 1k2 (with the pulse voltage freq = 20 kHz) and the voltage also managed to drop to 0 V.
I've connected te ground of the resistor to the source of the MOSFET - but that short circuited the primary winding of the transformer.
Question:
How can I make this optocouplers to drive the MOSFET transistors, so that the transforer works (right now there is no voltage on the primary winding).
(In case the simulation works properly) What would you suggest to reduce Vgs rise time? Are Totem Pole optocouplers faster and also can be applied to driving MOSFETs?
Thanks in advance for any help.
AI: The voltage that controls a MOSFET is NOT the voltage at the gate. It is the voltage difference between the gate and source pins of the MOSFET.
The voltage you are applying to the MOSFET gates are all relative to ground, but the MOSFET does not care what the voltage relative to ground is, and in fact cannot know what the potential at ground is if none of its pins are connected to ground.
R6 and R10 pulling the gate to ground instead of to the source pin are indicative of this lack of understanding and are a good way to exceed the gate-source voltage limits of your MOSFETs.
When you drive a MOSFET that has a load connected between source pin and ground, and apply a gate voltage relative to ground, you get a source follower where the MOSFET's attempts to turn on inherently reduce the gate-source voltage difference due to the voltage rise across the load causing the source pin voltage to rise above ground while the gate voltage stays the same (since it is relative to ground). An equilibrium is found where the source pin "follows" the gate voltage with some offset. It has its uses, but not when you're trying to use the MOSFET as a switch.
This is the reason so-called "high-side gate drivers" exist. These are circuits that take a ground referenced control signal and output a voltage difference between two pins which are connected the MOSFET gate and source pins respectively. That way, the voltage applied to the gate is always a predictable amount relative to the source pin which is the only thing the MOSFET cares about.
Also, this gate driver won't be able to switch fast enough for 20kHz anyways. Pull-downs are just too slow. Consider using the opto to drive a totem-pole consisting of a pair of complimentary, smaller transistors (either BJTs or MOSFETs, possibly both in parallel) which in turn drive the gate. You can use a PNP/PMOS on top with NPN/NMOS on bottom or vice versa. They both have their advantages and disadvantages in this case (lack of shoot through in the small transistors despite being driven off a common gate/base signal being the benefit of the NPN/NMOS on top and PNP/PMOS on the bottom, at the expense of not being able to output the full gate drive supply voltage since they are source/emitter followers).
Of course, power this little totem pole off a supply referenced off the MOSFET source, however you decide to go about it (isolated DC-DC converter, charge pump that floats capacitor charged relative to ground up to the source pin, or bootstrap). |
H: Diode ROM with decoder and multiplexers
I have this question on my exam I couldn't answer:
A diode ROM has been built using a decoder and multiplexers. If A4A3A2A1A0 = 01001, what is D3D2D1D0?
Here is the first schematic:
The answer is supposed to be:
Can anyone explain the solution?
AI: I've seen people do this before, it's really strange and was far more common back in the 80s (or earlier) when memory was really, really expensive and programs were short.
The general concept is you run your address lines to a demultiplexer (or inverting demultiplexer, as in this case) and have a pull-up resistor from every data line to 5V. You then place a diode in every spot you want to be a 0 (depending on address, like a memory) when you want that bit in your program to be a '0' at a certain address from the non-fixed side of the pull-up resistor to that output of the demultiplexer.
When the demultiplexer output is low, current will run through the pull-up resistor and diode and since the diode forward voltage drop is 0.7V it will be under the 0.8V required for a logic '0' but when the demulitplexer output is high no current runs through that leg of the circuit and it is high.
It's an incredibly difficult concept to describe in a text box, see this article: http://www.wintergroundfairlands.com/2013/10/visualizing-roms-1-diode-matrix-rom.html |
H: Is the TC ("terminal count") output of a 4-bit sync counter (74163) reasonably assumed to be glitch-free?
My gut tells me so, but the proof eludes me. Effectively this output is the AND of all four bits. These four bits go from 0 to 1 at very distinct times, assuming the counter is running at a reasonable clock rate. From this, I assume that the TC output's transition from 0 to 1 is safe. But what about the other way? When the counter rolls over and all bits go from 1 to 0, may I assume that TC makes a glitch-free transition from 1 to 0 as well? I sense that I'm missing some elementary rule of thumb here.
AI: No, I don't think you can assume it will be glitch free.
The problem is not that the expected low to high and high to low transitions will be glitchy, in fact those transitions are likely to be glitch-free.
The problem rather is that the output may briefly glitch high during counting. For example during the transition from 1101 to 1110 if the units flip-flop is slightly slower than the twos flip-flop then the data outputs may briefly be 1111 and thus the TC/RCO output may briefly go high. |
H: Can I replace a dual section capacitor in a tube amplifier design with two single capacitors?
I was planning on building this schematic, but found it hard to source their 20/20 dual section cap (C3/C4). Could I replace this with two single 20uF caps, or is it a dual-section for a reason?
AI: I added the C3/4 designator, since I assume you are asking about that?
Historically since large caps came in sockets it was more convenient. Nowadays that design would be 2 discrete capacitors. I see no issue with what you are considering. |
H: How to get an analog signal 0 to 12 V DC based on reference 0 to 5 V DC?
I have an Arduino which is creating an analog voltage from 0 to 5 V (I used external DAC for it) and I need to use it for the regulation of "big" circuit with 12 V DC. So I am trying to get on the "big" circuit analog values from 0 to 12 V DC (the maximum current by 12 V is 55 mA).
Right now I am using MOSFET IRF520 for it, but it doesn't work as well as I expected. The MOSFET starts to open by voltage approximately 3 V and is fully opened by 4 V. So for the regulation of the big circuit, I am using just 1 V difference.
Right now I am considering maybe some JFET (e.g. J112?) could be a better choice for this type of job but I am not sure.
Can you please tell me, how would you solve this issue and what for a device would you use? Maybe can you propose some concrete FETs/transistors good for it?
AI: You need feedback if you want an exact ratio of 12/5, an open loop transistor will not do this. I would use an opamp with a transistor amplifier. You could also look for an opamp that will output 55 mA (most won't) and leave out the transistor.
You need a rail-to-rail opamp so the output will go to ground. The supply voltage needs to be a few volts higher than 12V if you use a transistor.
Also see the "adding gain" section of this article:
https://www.allaboutcircuits.com/technical-articles/how-to-buffer-an-op-amp-output-for-higher-current-part-1/
simulate this circuit – Schematic created using CircuitLab |
H: CD4006 Behavioral model in LTSpice
I want to simulate the behavioral model of CD4006 chip in LTspice. It is a CMOS 18-Stage Static Register. Looking at the Datasheet I see the one stage logic diagram that consist of inverting buffers and flops. But this stage has D, Q, !Q, CL and !CL i/os. CL - is for clock. D - is for DATA, Q and !Q - outputs, but what is the !CL input ? Is it CLR, that is usual attribute for FLOPs in LTspice?
AI: At the top of page 6 in the datasheet is a small diagram showing how each flip-flop is constructed from transmission gates and inverters. The transmission gates need both the true and complement of the clock, and it is often easier to generate these globally for all of the flip-flops rather than internal to each flip-flop. So, !CL (or \$\overline{CL}\$) is just the complement of the clock signal. |
H: How to interface HCSR04 ultrasonic sensor with ATxmega256A3?
I have to interface HCSR04 with ATXMega256. I am using the TCC0 Timer in Capture mode with setting it to capture pulse width, using Event System Channel 0 source: Port A Pin0.
Anyway, my code is shown below in one file using USARTE1 to send the measurement to another terminal:
#define F_CPU 16000000UL
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <avr/io.h>
#define USART_Format_Set(_usart, _charSize, _parityMode, _twoStopBits) \
(_usart)->CTRLC = (uint8_t) _charSize | _parityMode | \
(_twoStopBits ? USART_SBMODE_bm : 0)
#define USART_RxdInterruptLevel_Set(_usart, _rxdIntLevel) \
((_usart)->CTRLA = ((_usart)->CTRLA & ~USART_RXCINTLVL_gm) | _rxdIntLevel)
#define USART_Baudrate_Set(_usart, _bselValue, _bScaleFactor) \
(_usart)->BAUDCTRLA = (uint8_t)_bselValue; \
(_usart)->BAUDCTRLB = (_bScaleFactor << USART_BSCALE0_bp) | (_bselValue >> 8)
#define USART_Rx_Enable(_usart) ((_usart)->CTRLB |= USART_RXEN_bm)
#define USART_Tx_Enable(_usart) ((_usart)->CTRLB |= USART_TXEN_bm)
#define USART_IsTXDataRegisterEmpty(_usart) (((_usart)->STATUS & USART_DREIF_bm) != 0)
#define USART_PutChar(_usart, _data) ((_usart)->DATA = _data)
void usart_putchar (uint8_t data)
{
while (!USART_IsTXDataRegisterEmpty(&USARTE1));
USART_PutChar(&USARTE1, data);
}
volatile uint16_t pulseWidth = 0;
int main(void)
{
cli();
int16_t count_a = 0;
// System clock External oscillator 16 MHz
OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_16KCLK_gc;
OSC.CTRL |= OSC_XOSCEN_bm;
CCP = CCP_IOREG_gc;
while ((OSC.STATUS & OSC_XOSCRDY_bm) == 0);
OSC.CTRL &= ~(OSC_RC2MEN_bm | OSC_RC32MEN_bm | OSC_RC32KEN_bm | OSC_PLLEN_bm);
PORTCFG.CLKEVOUT = (PORTCFG.CLKEVOUT & (~PORTCFG_CLKOUT_gm)) | PORTCFG_CLKOUT_OFF_gc;
// Port initialize
PORTB.DIR =0x01; // Trig Port at PB0
PORTA.DIR = 0x00; // Echo Port at PA0
PORTA.PIN0CTRL = PORT_ISC_BOTHEDGES_gc;
PORTE.DIR = 0x80; // USART at USARTE1
// Timer TCCO in capture pulse width mode
EVSYS.CH0MUX = EVSYS_CHMUX_PORTA_PIN0_gc;
TCC0.CTRLB = TC0_CCAEN_bm | TC_WGMODE_NORMAL_gc;
TCC0.CTRLA = TC_CLKSEL_DIV1_gc;
TCC0.CTRLD = TC_EVACT_PW_gc | TC_EVSEL_CH0_gc;
TCC0.INTCTRLB = TC_CCAINTLVL_LO_gc;
TCC0.INTFLAGS = TCC0.INTFLAGS;
// USARTE1
USART_Format_Set(&USARTE1, USART_CHSIZE_8BIT_gc, USART_PMODE_DISABLED_gc, false);
USART_RxdInterruptLevel_Set(&USARTE1, USART_RXCINTLVL_LO_gc);
USART_Baudrate_Set(&USARTE1, 0xCE5 , -5); // 9600
USART_Rx_Enable(&USARTE1);
USART_Tx_Enable(&USARTE1);
// PMIL
PMIC.INTPRI = 0x00;
PMIC.CTRL |= PMIC_LOLVLEX_bm;
sei();
while (1)
{
PORTB.OUT = 0x01; // trig the sensor
_delay_us((20));
PORTB.OUT = 0x00;
count_a = pulseWidth / 58;
// pulseWidth = 0;
uint8_t hByte = count_a >> 8;
uint8_t lByte = count_a & 0xff ;
count_a = 0;
usart_putchar(hByte);
usart_putchar(lByte);
_delay_ms(250);
}
}
ISR(TCC0_CCA_vect)
{
pulseWidth = TCC0.CCA;
}
In Atmel Studio 7 I have written a .stim file to generate pulses with 10 ms, and in simulation I was able to capture this pulse which is equal to \$10000/58 = 172 cm\$, but with the real xmega, the terminal received random bytes. Also I checked the USARTE1 sending process and it works fine.
Have you any suggestion please to determine where the problem is?
AI: It appears to me that you don't wait for the echo to return.
Reading from https://randomnerdtutorials.com/complete-guide-for-ultrasonic-sensor-hc-sr04/ :
"The HC-SR04 barely works to 10 feet giving a total path length of 20
feet and a path time of about 20ms so set the timeout to something
above that, say 25 or 30ms."
So the measurement could take up to 20 ms to arrive. I think you should reset pulseWidth to 0 before starting a sample, then wait until you got a value:
pulseWidth = 0;
PORTB.OUT = 0x01; // trig the sensor
_delay_us((20));
PORTB.OUT = 0x00;
while (pulseWidth == 0) ; //Waiting here.
count_a = pulseWidth / 58;
Or better yet, delay until a timeout, to catch if the echo goes missing.
By the way, the link I quoted only pings for 10 us, not 20 us.
Still, your code should catch the pulseWidth value registered on the previous loop, so something else could be wrong here. You might need to reset the input capture timer, as is done in https://www.avrfreaks.net/forum/xmega-input-capture
If those ideas don't help, if you can check the pins with an oscilloscope, that would help you narrow down if the signal arrives as it should. |
H: Is there any reason as to why the schematic symbol of comparators is almost equivalent to that of op amps?
They do similar tasks, but they are almost completely different because comparators output digital signals. In that case, I am confused as to why their schematic symbol is almost entirely the same. Is it implying something else that I am not realizing?
AI: They are not completely different. They are much more similar than you think.
Technically, a comparator is just an op-amp optimized to operate in the saturation region (have the output saturate since it is always either LO or HI, but be able to leave saturation quickly for fast switching). Being linear in the linear region is not a design priority.
An op-amp is a comparator optimized to operate in the linear region (to be very linear in the linear region where it will spend all its time due to negative feedback). An op-amp used as a comparator will be slower since it is slow to get out of saturation.
Most opamps also have frequency compensation so that they can be easily used with negative feedback. Comparators have no need for such a thing.
Those are the big ones but op-amps also tend to place higher priority on things like noise, offset, and input bias currents than comparators. All that good analog stuff. |
H: Single-package DC/DC converters for PoE -- good idea?
I'm planning a design where we'll use PoE to power a data acquisition board (essentially, an ADC + microcontroller + ethernet PHY and interface).
I look at DC/DC isolated converters to get the 5V or 3.3V from the, say 48V from the PoE wires, and I get a headache! I look at two reference designs (from TI and from Analog Devices / LT), and they have a components count of about 50 parts !!!! The Art of Electronics (3rd Edition), on Figure 9.83 show a "real world" example of a switching converter (in that case, it is AC/DC, but same principle), with approx. 40 parts, and they say that that is a "relatively uncomplicated" circuit .....
On the other hand, I see single-package DC/DC converters such as the CUI PDQ10-Q48-S_X_ — 1-inch by 1-inch by 10mm height, 10W, input DC between 18V and 75V. I don't see why something like this would not work. Any comments?
As a secondary question: I guess I will at least want to put the recommended EMI input filter (C-L-C, as per datasheet suggested circuit), and some TVS (say, a 60V or 70V Zener TVS?) just after the output of the rectifier bridge from the ethernet isolation transformers? Any other aspects I need to pay attention to?
AI: The Art of Electronics example is for line voltage so it has some extra filtering, and regulated, not constant.
PoE is not just "here is 48V" too, you deal with long unshielded lines (ethernet is up to 100m) so you have to take care of some transient protection too.
There is also a matter of negotiating required power mode if you need to do bit more than standard ~15W
On the other hand, I see single-package DC/DC converters such as the CUI PDQ10-Q48-S_X_ — 1-inch by 1-inch by 10mm height, 10W, input DC between 18V and 75V. I don't see why something like this would not work. Any comments?
Those tiny converters have quite a few parts:
So not like they are significantly smaller on part count.
Biggest thing to watch aside from input filtering you've mentioned is that they can be quite noisy in high frequency region and your typical LDO is not fast enough to filter it |
H: How to end sending data over I2C by Slave or Master?
Let us say a Slave or Master is sending multiple bytes to the receiver on I2C bus and the number of bytes is not defined before hand. So then how will the sender tell the receiver that it has no more data to send?
So far what I understand is that for the case when the sender is Master then it sends a NACK to tell the Slave (Receiver) that there is no more data to send. And after sending NACK then it sends the STOP condition to finish the session.
But I wonder how does this handshaking takes place between a Master and Slave when the Slave is sender and the Master is receiver and only the Slave (sender) knows when there is no more data to send to the receiver?
AI: But I wonder how does this handshaking takes place between a Master and Slave when the Slave is sender and the Master is receiver and only the Slave (sender) knows when there is no more data to send to the receiver?
This isn't supposed to happen. i2c is a very defined protocol and each slave device should be known to each master. Typically, the master requests the slave to transmit, and either the message size is fixed, the message is sequential, or the message includes how many bytes will be sent.
Master writes a register address, then master switches to read and the slave sends a byte. That's all the master wants, sends a stop.
Master writes a register address, then master switches to read and the slave sends a byte, then the master reads again, so the slave sends the next byte (or same byte). The master reads how ever many it wants, arbitrarily, then sends a stop.
Master writes a register address, then master switches to read and the slave sends a byte. That byte tells the master how many bytes that register should have. Master reads and slave sends that many, then master stops.
All communication is controlled by the master. The slave does nothing the master doesn't want it to do. The master controls the speed of the clock (clock stretching not withstanding) and how many bytes are read. At no time should the slave try forcing the data line when the master did not tell it to. The data structure should be known before hand. |
H: Chip selection: Serial interfaces
I am narrowing the selection of an uC for my project and currently reading the datasheets. One contender is Microchips 'ATSAMC21*' series. Using the parametric selection tool I get following information
In the datasheet it says on p. 2
Up to eight Serial Communication Interfaces (SERCOM), each configurable to operate as either
Does this mean I have eight interfaces as combination of SPI,I2C and UART?
Or like in the table above 6-8 separate interfaces (18 in total)?
AI: As I read the datasheet, you get a total of 8 serial ports that you can configure any way you like. |
H: Need help finding pin layout diagram for GSM module (SIM800c RPi development board)
I'm having a bit of a conundrum. I bought a SIM800c development board off of ebay but the pins are not labeled at all and I have no idea which pins Rx and Tx are. I really want to hook it up to my COM port and test it out with putty. In case you weren't aware, these GSM modules communicate via the UART in AT commands.
Anyways I do have some helpful hints to solve this mystery. Here is a link to the item that I purchased.
https://www.ebay.com/itm/202041471362
You can see a picture of it on there. I also found what looks like my module along with a pinout->
https://www.itead.cc/wiki/RPI_SIM800_GSM/GPRS_ADD-ON_V2.0#Pinmap
Its not exactly the same as the one that I bought, but its the best thing I was able to dig up. I'm not sure if this is the correct pinout?
I tried hooking it up to some pins labeled "Test pins". There were pins for power and ground, along with two pins, one labeled R and the other labeled T. I thought those must be it, but when I test the AT commands in putty, there is no response from the GSM module. I'm pretty sure these can't be the right pins.
Please someone with knowledge, can you tell me which pins are Rx and Tx? If you have a schematic, please share.
One more thing I'd like to add is that I tried contacting the seller on ebay, but they told me "They are only a customer service and they don't know anything technical. Please research the internet."
AI: This is probably not the answer you are looking for, but those 2 boards are not the same. There are many different versions of the SIM800c breakout boards, and that means you cannot say for sure whether pinouts are the same with these 2.
This bit of the answer you may enjoy less, although it is good news in that you can figure it out for yourself! You can look up the DATASHEET for the actual module and get a pinout of the module. Using a multimeter set to continuity mode, you can test each pin until you get a beep. You can then draw your own diagram of a pinout for that board. If you wanted, you could then upload it here as your own answer in case anybody else has a similar issue with this board.
If you are only after the Tx/Rx pins for now, then those are just pins 1 & 2 so shouldn't take too long! |
H: Are all USB controllers kept at host side?
I see a lot of USB controllers in battery charging circuits. They have USB host controllers, embedded controller and USB port controller at host side. (Refer tps2547 )
Can somebody tell me what are the minimum control and protection circuits needed for charging using USB?
Is it the sole responsibility of the host to ensure reliable power to whichever device it is powering ? Is there any protection or control circuitry at device side, say load switches or similar kind?
Iam lost in the vast pool of resources with so many standards and specifications. Please note that Iam primarily looking for power transfer through USB.
AI: In practice, the absolute bare minimum is a stable 5V/500ma rail with the data lines shorted together. That will cause most devices to charge at "normal" speed.
That doesn't work for everything, and there is a proliferation of hacks for progressively more complicated schemes.
Is it the sole responsibility of the host to ensure reliable power to whichever device it is powering ?
Yes. You can't guarantee anything in particular at the client side, and you certainly shouldn't rely on it having any particular protection. There are all sorts of "USB" gimmick devices like fans and lights that just use it as a power rail.
You also need some kind of overcurrent protection in case a cable is damaged, resulting in a short circuit between the rails. |
H: I2C Communication Open drain benefits vs Push pull
I am reading this TI I2C App Note for understanding the I2C operation and need to understand how Multi master I2C will operate.
I was not able to understand this para in the app note, "Since no device may force a high on a line, this means that the bus will never
run into a communication issue where one device may try to transmit a high, and another transmits a low,
causing a short (power rail to ground). I
2C requires that if a master in a multi-master environment transmits
a high, but see's that the line is low (another device is pulling it down), to halt communications because
another device is using the bus. Push-pull interfaces do not allow for this type of freedom, which is a
benefit of I
2C.
"
This is the first para of Section 1.1 Open-Drain for Bidirectional Communication
I have some doubts :
I don't understand how they are saying Open drain is better than push pull config? Can someone give an example? And when they say two devices start communicate at the same time, how is this possible? Two devices can't communicate at the same time, right? And are the two devices slaves? or masters?
Please provide an example how push pull is dangerous when compared to Open drain in I2C?
AI: "Two devices can't communicate at the same time, right? And are the
two devices slaves? or masters?"
Two devices can communicate at the same time on the same bus (with eachother), but not more, no matter their role.
On I2C, only the master(s) can start communcations. If a masters wants to do so, he can check wether the SDA pin is pulled low (for the duration of 2x I2C cycle time), which means another master is currently active, so it can wait for the other master/slave to finish before transmitting itself.
I don't understand how they are saying Open drain is better than push
pull config? Please provide an example how push pull is dangerous when
compared to Open drain in I2C?
Consider the scenario with push/pull:
Imagine two masters and one slave on the bus. How could a master check whats happenning on the bus - i.e. is another IC currently talking?
If you configure the master(s) to pull SDA to HIGH while they are idle, and then tell one master to start sending data, he will pull SDA low - and you have a short circuit.
So the solution is not to pull SDA to HIGH by any of the ICs, but have it pulled high by a pull-up resistor. Now your ICs only need to pull SDA to LOW to do their work (and the other ICs can sense that), and leave SDA floating otherwise (which will be pulled up by the resistor). This way, no short circuits are possible, as none of the ICs are supplying current to SDA, they only sink the (very small) current supplied through the pull-up to do their signalling. |
H: RLC circuit (simulation in Scilab)
I tried to solve a RLC circuit and I obtained the matrix. I tried to do a circuit in Scilab, but I didn't obtain a sinusoidal response. The output is in the capacitor and the input is the step function. Why didn't I get the sinusoidal response?
AI: The circuit is overdamped. The output will rise to v(t)/5 with no overshoot. If you rerun the simulation with smaller values of resistors, you'll see the damped sinusoids you were expecting. |
H: C - wrapping globals in a struct?
A firmware style question concerning C.
I have some legacy code I am tidying up. One of the nasty features is global variables being scattered through the source files. I can make a few of them locals, which is fine. However, how to deal with the rest. I favour creating a struct and putting them inside it.
I know that there is theoretically another level of indirection when accessing them, but from a style POV is this better or worse than putting them in files globals.c and/or globals.h?
AI: If you can't get rid of the globals, I'd say you should only pack them together in a struct if they are actually related. If not, then I'd keep them separate or in smaller structs.
Also, I wouldn't like a globals.h file either. Keep them at the top of the source file where they most belong. This way when navigating through the code, you likely stay in the place where you were or go to the place you likely wanted to go. |
H: are flex PCB's really used?
Are there any application where flex pcb's (rigid/flex) are really being used and required? or is this a more luxury product which is not entirely mature yet to the level where it can be implemented in every day products.
AI: As the comments suggest, the main use of flexible PCB techniques is interconnect: linking one (rigid) PCB to another. They can be produced in arbitrary shapes more easily and cheaply than thin cable looms.
Lots of laptops and tablets will have flexible PCB connectors for things like the screen.
Placing components on flexible PCBs has the problem that the components themselves are not flexible, so they tend to strain the joints. Unless a "stiffener" is attached behind the PCB. |
H: Burning graphite with 9V battery vs. Arduino's 5V
First off, I'd like to say that I am completely new to electronics and the way circuits work, so this may be a really dumb question.
I've tried searching Google but I can't really find what I'm looking for since I'm new to all this.
Basically, I'm trying to get a pencil graphite to produce some smoke.
When I connect one part of graphite to the +5V Arduino pin and other to ground, it smokes for a bit before Arduino's short-circuit protection kicks in.
The above works as expected, but when I connect it the same to the 9V battery as the source, the graphite barely warms up.
So my question is - why does Arduino's 5V make graphite smoke while the 9V battery doesn't?
AI: A 9V battery can't provide much current due to it's internal resistance. Depending on what is powering the Arduino 5V, it can put out much more current than a 9V battery. |
H: Can an induction motor be used to generate power?
Induction motors do not have magnets in them, instead the magnetic field the outer coils generate creates electricity, and subsequently magnetic field, in the inner coil. This means those motors need no brushes as the inner coil is not connected to anything.
I was wondering, purely academically, if you could prime the motor with field first, by putting current through the outer coil and then spin it to generate electricity. Assuming you'd spin it correctly, I imagine the magnetic fields would maintain themselves using power absorbed from the motion until the system came to a halt.
Is this possible or nonsense?
AI: Induction motors make very good generators. They are the typical generator used in wind turbines for instance.
Let's look at the speed torque curve. Here's one from electrical4u.com
Speeds in the 0 to ns, standstill to synchronous, are normally the only speeds people consider.
Normally, an induction motor operates at full load with a few percent slip. Consider what happens as the torque delivered by the motor drops, the slip reduces, and less energy is drawn from the supply. As the torque drops to zero, the speed rises to synchronous speed, and no power is drawn from the supply.
If we now increase the speed above synchronous, driving the motor externally, torque is required to turn the motor, and energy is delivered to the supply. |
H: Water and electricity?
I just put my Ipad Air 3 in my bag, it was raining and forgot to close it such that when I got home, my Ipad and the inside of my bag was extremely wet. I know a bit of physics but not figure whether or not something could happen to the inner workings of my Ipad (so I am reaching out to the wizards):
Does water affect electricity in any way (e.g. slower flow of electrons, less stable) if the water has not destroyed the whole circuit? More specifically for my case, in case some water slipped inside towards the inner workings, and the Ipad seems to be workings just as great as before, could any of the electronic circuits have been affected?
AI: Unfortunately water can be bad for electronics in several ways:
It can create shorts between signal wires, causing logical errors or destroying chips that suddenly have unexpected voltage levels.
It can short out power lines, causing heat that can burn up parts of the device or disable the battery.
It can corrode metals, possibly causing the above two problems now or later, or changing the electrical characteristics such as resistance or capacitance with hard-to-predict results.
Water drops on the loose inside the device could also move around as the device is handled.
To be certain the device won't develop problems later on, it should be opened up, inspected and left to dry out. Then again, it might be fine as is. It's just really hard to tell from the outside. |
H: Understanding datasheet for SMPS transformer
Looking at different datasheets of SMPS transformer, I found that the manufacturer always specifies voltage in a certain frequency range. Why is this parameter important?
For example this transformer:
https://www.weonline.de/katalog/datasheet/750311564.pdf
voltage is only specified for 40 V @100kHz.
Is this voltage-frequency parameter somehow related to volt \$\times\$ second or saturation?
EDIT:
Removed the insulation part.
I went to fast through the datasheet. So, the part of the insulation voltage is quite clear, I am interested in the relation between voltage-frequency and the magnetic properties.
Does it mean that if If I would apply 80v at a higher frequency (>200 khz)that the core would not saturate since the increased voltage is compensated with lower “seconds”
AI: The manufacturer always specifies voltage in a certain frequency range. Why is this parameter important?
Because these are the parameters the transformer has been specifically designed for.
As depicted, this transformer's primary input of 10-40v @100kHz will produce X to 5v/3A at the output. (Since the input ranges from 10-40vAC, then 10 is 1/4 of 40, so the output at (input=10V) would be about a quarter of 5V/3A, or 1.25V/0.75A.)
The 500v rating is an insulation-test between the windings, to ensure that it will not break down during service (and accidentally inject 40v pulses into your 5v device.)
What would happen if I apply 200V at a certain frequency ?
If you applied 200V at any frequency between windings (such as one lead to the primary winding and one lead to the secondary winding), then nothing will happen as this transformer has already passed it's 500V isolation test.
If you applied a slightly higher voltage than 40v (@100kHz) to the primary winding, the output would rise linearly from 5V to match. However, the transformer would run hotter than designed and may fail prematurely. Attempting the primary at 200vAC@100kHz (5x the voltage it is rated for) would far exceed the saturation limits (explained below) and likely burst into flames.
Is this voltage-frequency parameter somehow related to volt.second or saturation?
This transformer uses a ferrite core material which enables the magnetic flux to change orientation at a very rapid rate (in this model, 100,000 times per second or 100kHz.) This fast rate is desirable because, for a given power rating, the faster the rate-of-change, the smaller the core needs to be. This means a smaller and lighter transformer.
Saturation is the inability of the core material to "hold" any more magnetism. Ferrite is very good at "collecting" or "holding" this magnetism, but has limits. Attempting to put more power into (or take out of) the transformer than it is designed for will result in exceeding the saturation limit. When this happens, the core cannot perform it's function any longer, reducing efficiency and generating heat. Slightly exceeding the limit infrequently, for a short time, may be ok; just realize that exceeding it is bad and should be avoided.
As for frequency, this is limited by the composition of the core material. If the transformer is rated for 100kHz, then faster alternations than this will incur losses, as the core material is only "so fast." Drastically exceeding this (such as 200kHz) will be very lossy, resulting in reduced output and excess heat generation because the core material is too slow. It is possible to make the core material glow red hot by doing this, just like an induction heater.
Going lower in frequency is interesting. Faraday's law of induction states that the voltage across a coil is equal to negative the time rate-of-change of flux, times the number of turns of wire. For a sinusoid wave, the time-rate-of-change is 2*pi*frequency. So for a fixed flux capacity (the core material) and fixed number of turns (the winding), reducing the frequency means the voltage must reduce by the same factor. i.e. for a 40v primary at 100kHz, but using 10kHz, you can apply at most 10kHz/100kHz*40v = 4V. This means that using 4V@10kHz will produce the same saturation as if it were powered from 40v@100kHz! Not very efficient...
In short, high-frequency transformers are carefully designed for a set power, input range, and frequency. There is a little wiggle-room in these specs but for the most efficiency and longest life, stick to the datasheet specifications and be careful of exceeding them. |
H: SMPS voltage feedback using op-amps
I'm designing an adjustable high-voltage low-current power supply using UC3843 control chip.
Basic parameters: Uin = 24 V DC, Uout = 30-1000 V DC, Iout = 10 mA, Uripple < 1 V, fsw = 40 kHz
I have a few questions about one aspect of my desing - the voltage feedback. I most simple cases, the voltage feedback can be realized using a simple resistive divider, possibly with a variable resitor to achieve adjustable output voltage. However, in my case I can't use a potentiometer directly in the divider because of high voltage at the output. Instead of that, I came up with following circuit, which uses 2 op-amps, the first as voltage follower and the second, with variable gain, to achieve desired range of output voltage:
simulate this circuit – Schematic created using CircuitLab
(In blue are voltages with potentiometer set to low resistance, red is the opposite)
The IC operates in closed loop in order to achieve zero difference at the output of the error amplifier. That means, voltage between R1 and R2 will be in steady state equal to 2.5 V internal reference.
My questions are:
Is there in general something wrong using an op-amp in voltage feedback like this? Are op-amps fast enough to transfer fast changes at the input to the output?
Is op-amp MC33072 suitable for this application?
Should I place some small capacitors for better noise imunity, e.g. across R6?
AI: Yes and no -- you've identified the biggest potential problem. Typical "general purpose" op-amps are generally fast enough for today's "general purpose" switchers; I'm assuming that your loop will be particularly slow based on the voltage and the UC3843. Basically the bandwidth should be at least ten times the anticipated loop bandwidth of the supply.
I'm too lazy to check for you, but in addition to vetting the bandwidth of the as-built amplifier stages, make sure that it doesn't hit the rails, or suffer from phase inversion or slow recovery when it's common mode range is exceeded. You'll also want to check voltage and current offsets (and the effect of current bias on your unbalanced op-amp inputs)
Probably not. In general a capacitor across R6 would be a Bad Thing -- it would slow down the loop, and potentially destabilize it. If you get close to production and you have really high-frequency noise getting into the system, then a cap across R6 that's small enough not to compromise loop stability may be necessary, but I'd consider that a desperate measure, to fix a problem that's usually better dealt with by careful board layout. |
H: Is it possible to provide DAC voltage to VOUT_ADJ to control Vout?
I am using a TPS61391 booster.
I need to adjust Vout via a DAC connected to FB pin voltage divider (VOUT_ADJ).
is this possible?
DAC voltage varies from 0 to 3.3V.
AI: Yes, this is certainly possible.
FB stands for "feedback", and the feedback voltage is 1.2V according to datasheet. So, in normal operation Rup and Rdown resistor divider is used to bring desired output voltage to 1.2V level, no Radj necessary.
However you can apply external control voltage via Radj to shift the equilibrium point up or down. The proportion between three resistors plus the output range of your DAC will define the effective adjustment range.
I did not read datasheet in detail, but I suspect the efficiency of the conversion will suffer if you move output voltage too far from the design point. This feature is not implemented to build something like adjustable bench supply, but rather to fine tune the output (add temperature compensation, for example). |
H: Copper oxide on cables after tinning w/ no clean flux
We just found a problem with some (translucent) speaker wire.
We have been tinning wires for a year by dipping the stripped end in no clean flux and then dipping again in lead free solder. We have a new customer that gave us translucent wires to tin and solder, one day after tinning the first batch we noticed that there was a greenish color for about 1/2" where we have tinned and soldered the wires.
We follow the dipping procedure as directed in the flux PDF.
Has anyone seen this issue?
If it has happened before we did not notice because we were using colored wires.
AI: According to Kester's "Green Corrosion with Rosin Flux?"
https://www.kester.com/Portals/0/Documents/FAQs/GreenCorrosion_Global.pdf
The green is not an oxide. It is copper abietate. It is harmless but also green in colour like other harmful forms of copper corrosion.
It is formed when the abietic acid in the flux reacts with copper (particularly when heat-activated).
It is just the flux doing its job and reacting with the pre-existing oxides on the copper to remove them from the bulk copper surface to expose the clean copper below...except in this case it has nowhere to go and nothing to displace it (i.e solder). Copper that has no oxidation to begin with would not produce this green residue.
You can tell your customer this. It's nothing to be concerned about since it is not an actual corrosion product of copper.
Of course...unless it's due to chlorine released when PVC insulation is heated which might produce Coppper II Chloride (I'm not sure) which is also green but actually is an undesirable corrosive contaminant.
Either way, it doesn't seem like there is anything you can do about it other than not to dip the entire stripped end into flux. Even if you don't, it might wick up. |
H: Degrees of freedom concept in sensors
I was examining the specs of a breakout board.
It says in there that,
Integrate 10 dof sensors
Adxl345 accelerometer
ITG3200 gyro
HMC5883L Compass
BMP280 pressure sensor
Why is it called as a 10 DOF sensor? In past I was dealing with some IMUs consisting of an accelerometer + a gyroscope and they were called as 6 DOF sensors. Which was a little bit more understandable, I was thinking that 3 measurements from accel and 3 from gyro = 6 degrees of freedom. However in the above case, I am not sure.
AI: In this context, DOF (degrees of freedom) just mean the number of independent parameters.
Here it is 10:
accelerometer = 3 (acceleration in three dimensions)
gyro = 3 (rate of rotation around three axes)
compass = 3 (magnetic field in three dimensions)
pressure = 1 (well... pressure) |
H: Can a memory chip have a certain starting address
In my book there is a question stated:
Can a memory chip of capacity 512 KB have the starting address
2B0000h?
To me this seems like an incomplete question with a wrong answer in the book. The answer states:
No, because the first 16 bits of the starting address are zero, which
means the capacity of a chip that can have this starting address is 64
kB.
Is it possible to deduce such an answer based on the given information and why does he say that the capacity of a chip that can have this starting address is 64kB, if the one writing the answer wrote 64kb I would understand that he got it from the 16 zero bits, but even then we can't know if there are more chips and a decoder before it all enabling different chips or if there are more of these chips connected in parallel to form 16 bit words etc.? Also we don't even know how many bits we need for offset, as we don't know if the word on for this processor is 8, 16, 32 bit etc. or if it can address only words or bytes?
AI: The question makes perfect sense in context of how things are kept simple in an usual textbook. There are no MMUs or other fancy base address selectors, it's just how to match a bit pattern on bus and decode it to a chip select for large enough a block of memory.
The memory is said to be 512 kilobytes (0x80000) and can be assumed to be byte addressable in one contiguous chunk with single chip select for simple address decoding. That chip then needs 19 bits of address lines to access all its addresses from 0x00000 to 0x7FFFF. Therefore any address decoding must use the remaining higher address bits, so chip base address must be any multiple of 0x80000, including 0, so for example 0x200000, 0x280000, or 0x30000 could be start addresses, but 0x2B0000 can't.
Address 0x2B0000 as start address must use address bit 16 and higher for decoding so it leaves address bits 0 to 15 for the chip so 16 address bits means 64 kilobytes is maximum block for a memory that must start at 0x2B0000. |
H: Decoupling on Power-on-reset-IC
Is it a good idea to place the usual 100nF decoupling capacitor on a power-on-reset chip? Mightn't that influence its behavior on brown-out or power dips?
What is the best approach here?
The power-on-reset IC is a Micrel MIC803. I could not find any info on this on SE or in the datasheet. The reference circuit does not show a decoupling capacitor, but many reference circuits don't even if it is advisable to put one in.
AI: The datasheet link does say that additional glitch immunity can be achieved with a 100nF bypass cap.
So basically it does not need it in general and case by case it can be determined if it is necessary. If PCB area is not an issue, draw a place for the cap but decide later to mount it. |
H: Why is BER higher for binary modulation compared to quaternary?
I came across this image in my notes and I fail to understand why BER seems to decrease as the modulation order increases and I was hoping for an answer
AI: Put simply, for the same average energy per bit, the modulation scheme with more bits per symbol must have less distance between the points on its constellation diagram. Therefore a smaller noise excursion can produce a bit error. |
H: SMD Electronics Part that could be used for hanging
I'm working on a decorative PCB and I want the ability to hang it up on a wall conveniently. I was trying to think of something that would work similar to the saw tooth looking piece in this example
One requirement is that is has to be a surface mounted part. Something I thought of was a test point ( https://www.digikey.ca/product-detail/en/harwin-inc/S1751-46R/952-1478-1-ND/2264564 ), but they don't seem to come in a large enough size to work. The other thing I thought of was using a battery holder ( https://www.digikey.ca/product-detail/en/linx-technologies-inc/BAT-HLD-001-TR/BAT-HLD-001-TRCT-ND/5803803 ), which could work alright but is still a bit small.
I wanted to see if anyone had any ideas for common SMD electronics parts that could work with a household nail or screw.
AI: There is such thing as PCB cut-out. You can make it exactly in a shape of sawtooth hanger near the top of pcb.
Another simple option is to use right-angle rectangular header with pins facing down. If your PCB is heavy you can use either shrouded or dual row headers. |
H: I2C bus arbitration - communication layer
I want to understand about the communication layer on which I2C Bus arbitration is done.
My question is based on this question which was previously asked here.
The accepted answer states that
Bus arbitration is not part of several of the protocols you mention.
RS422, RS485 and SPI can have bus arbitration but it is not part of
the protocol, rather must be implemented on a different communications
layer.
I understand the I2C arbitration procedure but I want to understand that on which communication layer is I2C bus arbitration done ?
Can someone brief on the communication layer regarding the bus arbitration for I2C protocol and other protocols which have bus arbitration
AI: I2C arbitration works at the datalink level. I2C uses open-drain connections: SDA is low if any device pulls it low, but SDA is high only when all devices are not pulling it low. So during I2C slave address where two masters are transmitting, if one master pulls SDA low while the other master wants SDA high, then the open-drain datalink resolves the conflict in favor of the low value. Whichever master is transmitting the higher-numbered slave address, lost the I2C arbitration and must immediately release the bus. This only works if both I2C masters detect during each bit transfer that SDA is in the requested state. Not all I2C implementations are compatible with multi-master systems. A software bit-banging I2C master might not support multi-master address arbitration. |
H: Why is a LIN cluster limited to 16 nodes?
It says everywhere that a LIN network can be made up of at most 16 nodes (1 master node and up to 15 slave nodes). The id field however is 6 bits long allowing for more than 15 slaves to be addressed. Why this limitation to a total of 16 nodes? What was to happen if i were to add a 17th node?
AI: If a certain allowed resistance and capacitance is specified for each slave node, and 15 slaves is allowed for total resistance and capacitance on bus for error-free operation with good margin, then adding yet another node can exceed the total allowed resistance and capacitance on bus and then it fails to operate within specification as there is too much resistive and capacitive load.
On the other hand, if all slaves load the bus as little as possible, it might work fine with one more slave, or ten more, but that's why there are specifications. If the whole system and each device on it is made by the specification, it is safe to assume it works. Having an ambiguous specification which says you can have as many devices as long as the total bus load, rise times etc are not exceeded, it would be difficult to calculate beforehand how many devices you can have there, and it would need to be measured if the electrical parameters are within specification and good margins. |
H: On-Board Charger Battery Load
I am designing an On board charger for electric vehicles for my graduation project. And I am confused about testing the OBC. My goal is charging a 400V battery pack, but I don't have a battery pack and probably I won't.
Is it enough to use resistors instead of batteries? If not what can I use for equivalent to battery?
AI: To measure power capabilities of charger:
Yes, the resistors will be enough, because they will give you the opportunity to load the charger with the same current as in the real application.
EDIT: And as I just saw in the comments to the question: Yes, estimation of power efficiency will also be possible.
To measure behaviour during real charging process:
No, the resistors won't emulate a real charging process but be just a constant load. The charger won't be able to detect a progress in charging state and can't adjust to that.
Does your lab have a programmable electronic load? If yes, you can use that to simulate the charging process of the batteries and by that verify the behaviour of the charger. |
H: Why does VHDL not allow to alias slice of an array in this way?
This code does not compile:
type array_1_t is array (0 to 73) of std_logic_vector(31 downto 0);
type array_2_t is array (0 to 22) of std_logic_vector(31 downto 0);
signal my_array_1: array_1_t;
alias my_array_2_1: array_2_t is my_array_1(0 to 22);
alias my_array_2_2: array_2_t is my_array_1(23 to 45);
alias my_array_2_3: array_2_t is my_array_1(46 to 73);
The error is "The type of aliased object does not match the type in the alias declaration."
Both of these arrays are of std_logic_vector(31 downto 0). When then does this code not compile?
AI: The element type is the same but not the types themselves.
IEEE Std 1076-2008 6.6.2 Object aliases:
The following rules apply to object aliases:
..
c) The name shall be a static name (see 8.1) that denotes an object. The base type of the name specified in an alias declaration shall be the same as the base type of the type mark in the subtype indication (if the subtype indication is present)....
and 6.6 Alias declarations, 6.6.1 General
An alias declaration declares an alternate name for an existing named entity.
How can a named entity have two different types? The alias has a subtype indication type mark that's different from the thing being aliased.
So how should an alias of array slice be created in this case?
Declare type array_1_t as an unbounded array type so you can constrain it in the aliases:
library ieee;
use ieee.std_logic_1164.all;
package alias_slice_pkg is
type array_1_t is array (natural range <>) of std_logic_vector(31 downto 0);
signal my_array_1: array_1_t(0 to 73);
alias my_array_1_1: array_1_t (0 to 22) is my_array_1(0 to 22);
alias my_array_1_2: array_1_t (0 to 22) is my_array_1(23 to 45);
alias my_array_1_3: array_1_t (0 to 27) is my_array_1(46 to 73);
end package;
A package declaration is used here for illustration purposes providing a minimal, complete, and verifiable example. |
H: Li-Ion Protection IC Always in Overcurrent Detect Mode
I am seeing an issue with AP9211SA-AF-HAC7 Battery management system.
The battery protection circuit, designed as per the schematic attached (the same as the reference design in the data sheet(https://www.diodes.com/assets/Datasheets/AP9211.pdf)), continuously enters over current mode with any load that draws more than 1-2mA attached.
If the circuit is powered, then the load attached after, everything works as expected, it will happily allow up to 1A of current draw the the Voltage of the battery.
As this is an auto-wake-up version of the chip, it comes out of under voltage lockout fine, as long as there is no load attached, as soon as there is a load applied, this is not the case and the chip returns to overcurrent protection mode.
I am unsure of how exactly the Vm pin monitors the current and am wondering if this could be the cause? but it is the same value as stated in the datasheet so I'm really not sure what is wrong here.
Any explanation/help would be greatly appreciated.
NOTE:
I have tested multiple chips, also multiple versions of the same
chip
- AP9211SA-AF-HAC7
- AP9211SA-AJ-HAC7
- AP9211SA-AA-HAC7
- AP9211SA-AB-HAC7
I have also tested my circuitry using a bread-boarded version to rule out any issues with my PCB layout.
AI: The AP9211 is described as "specially designed for 1-cell Li+ rechargeable battery pack application". This suggests that it is designed to be permanently attached to the battery, and may not be suitable for your 'unconventional' application.
But why does it not turn on if a load is present when the battery is connected? Regarding over-current, the datasheets says:-
In discharge overcurrent or short current status, R VMS is connected
to V SS but R VMD is not connected. The voltage of VM pin is almost
equal to VDD as long as the load is connected. When the load is
disconnected, the voltage of VM pin will become almost equal to V SS
(due to R VMS being connected) and then the AP9211 will release from
discharge overcurrent or short current status.
I suspect the IC powers up like this, with the discharge MOSFET turned off so even a small load will hold it in over-current protection mode. To use it in your device you may need to provide a power switch to disconnect the load when the battery is inserted (perhaps a 'soft' switch activated by very low current would do the job).
If this is not acceptable then you might need to use a different protection IC which does not require the load to be disconnected at power on. However I looked at a few other protection ICs and all they appeared to have the same limitation. If the battery has to be removed from your device for charging then you might consider making a circuit that just protects against over-discharge (which could be set to a higher voltage for better cell longevity) and over-current protection via eg. a polyfuse. |
H: GPIO Button setup with switching power supply
I have a small board with 8 GPIO's, I previously had 4 buttons connected thus used 4 as inputs and 4 as outputs. I use a 10k pull-down resistor for each button. I don't have a resister pre input to protect against programming mishaps (nothing like living on the edge).
I want to connect 8 buttons now, so instead I plan to switch all 8 GPIO's to inputs and use a switching power supply to run 3v through the switches in place of the GPIO outputs.
I've actually already done this and it works fine, but I was reading a tutorial that suggested I needed to protect the GPIO because the power supply could supply up-to 1A in my case and the maximum sink current on the GPIO is 2mA.
Now I didn't think this is how current worked and dismissed it as misguided as I thought something had to draw that current from the PSU, but now it's got me worried as I am a complete amateur with electronics and don't particularly want to fry something.
There is nothing in my circuit other than Board/GPIO, 1A 3vdc PSU, momentary switch and a pull-down resistor. Does my GPIO need current limiting / protection?
AI: Good news, the solution is simpler than you thought. A GPIO input draws very little current, almost none at all. The voltage source will not determine the current draw -- the MCU GPIO will. You can therefore "power" the buttons from most any voltage source with a voltage level suitable for the MCU. The voltage supply for the MCU is a good choice, as it's already guaranteed to be within specs for the MCU.
Just connect the buttons as per schematics in this post: Smart ways to detect a button (less power consuming)
You can also add a capacitor between each GPIO input and ground for easy debouncing. You can use a RC time constant calculator (Google for it) to determine a suitable capacitance value. You probably want about 20 ms time constant. |
H: User controlled storage devices existence
Today's memory devices have a lot of logic embedded before data is actually written onto the NAND pages.
An example could be wear levelling algorithm , FTL functionalities etc.
The typical life of a NAND cell would be around 100000 cycles of operation.
My question is:
Can the storage devices performance be maxed out if all of the internal logic were removed?
(Assuming I dont care what happens after 100000 cycles. I just need speed for 100000 cycles and then, before the end, I would backup and use another storage.)
Are there any such devices out there that allow me to disable such logic?
How practical are such devices in terms of speed improvement (if they exist?)
AI: To answer your questions in turn
"Can storage devices performance be maxed out..." - This very much depends on what you want to do. If you're using your storage as a block device for a filesystem like FAT32 or NTFS. The lack of the FTL will make things
considerably slower: Imagine you edit a file and change a "1" to a "2". With an FTL, a spare pre-erased block will be allocated and your new data written there. Without the FTL you'll need to erase the original block, wait for the erase to finish (very slow), and then write the data. The other issue you'll have without an FTL is that you'll need to make the next layer up aware of the bad sectors on the flash. However there are use cases where not having an FTL makes sense (eg with filesystems like YAFFS)
"Are there any such devices...": Smartmedia cards are just raw nand flash chips with the pins brought out to pads. But a typical USB smartmedia reader will implement the FTL. However there are/were devices which used them directly.
"How practical...": not really practical for the reasons mentioned above. Early android phones used raw nand and YAFFS, modern ones use eMMC with an FTL and (usually) an ext3/4 filesystem. |
H: Shorting of VCC & GND for short duration of time
I have used ULN2003A for my custom board. While checking "continuity" between VCC and GND there is a continuity for a short duration of time(less than a second), it comes at a random time.
I have powered ON a fully assembled board and tested. Everything is working as expected.
In the datasheet, it is mentioned that there are freewheeling diodes for protection. Do these diodes cause that short duration continuity?
Edit:-
I have followed EVM for designing schematic:-
AI: Based on your comment : When you use the multimeter in continuity mode it applies a voltage to the circuit. Since you apply the voltage between VCC and Ground, the capacitors which are initially completely discharged provide a short circuit for a very short time. So this will give you the short "beep sound" you are witnessing. |
H: Voltage divider resistor PN balancing
Refer the representational schematics for voltage sensing by ADC (SAR). I read somewhere to balance the P and N lines add R3 = R1||R2. How come R1 and R2 parallel combination could be considered as contributing error voltage at P so that N has to be R3=R1||R2. Could somebody shed some light as to how the actual current path is balanced?
simulate this circuit – Schematic created using CircuitLab
AI: The idea is to have the equivalent of two voltage sources with equal series resistances (Thevenin sources) for each input.
The equivalent circuit of a voltages source combined with a voltage divider consisting of resistors R1 and R2 (that's what you have at the non-inverting input) is a Thevenin source with resistance \$R_{th} = R1 || R2\$.
I.e. both circuits in following diagram are equivalent:
simulate this circuit – Schematic created using CircuitLab
So the source at the inverting input should also have a series resistance \$R3 = R1 || R2\$. |
H: Addition Amplifier equation doesn't seem to work
In this addition amplifier, when I set V1=5V, V2=5V, R1=3.3kOhm R2=10kOhm, the answer (theoretically) should be -20.15V, but the actual result is -13.04V. Why is this happening? Is the equation for the addition amplifier wrong? Or is something wrong with the amplifier?
The supply voltage was +/-15V, and the equation that I am referring to is
V_0=-(R_2/R_11 v1 + R_2/R_12 v2), where R_2 =10kOhm in this case
Thank you!
AI: Now you have provided the supply voltages, it seems I was correct in my comment. You say you have a supply rail of +/- 15V. Let us look at the DATASHEET for the 741 Op-Amp:
You can see that the output will only get to a maximum of +/- 14V, which means your -13.04V that you measured is within its maximum output (depending on load).
Page 7 of the datasheet shows a diagram of the 741 internal schematic. As you can see, it is mainly resistors and transistors, these will have losses over them, which is why the op amp can never output all the way to its supply rail. |
H: How to desolder an element from a PCB?
I want to desolder an element from a PCB, I can see all the solder joints that are holding it on to the board and I can reach all of them easily.
I am not very experienced in working with a soldering iron, tbh this is the first time I am working with one but I informed myself how to do it correctly and I also got myself a desoldering pump to remove the melted solder joints.
The only thing that is giving me headaches is the fact that I read it can be difficult to desolder solder joints that are close or on a ground plane because the ground plane absorbs heat.
I took a look at my board and this may be the case for 3 or 4 of them.
My question is do I have to take special care of those solder joints, do I need a specific tool to remove those or can I remove them just like the others?
AI: Whenever you have to desolder something the first question you need to ask yourself is: do I need the component intact?
Because if you removing damaged component then often the easiest way is to separate its pins first. For most but the smallest SMD components this can be done with wire cutter. The plastic connector shroud can be broken or melted away etc. Once you've done that removing pins one-by-one becomes trivial.
If you do need the component, see if you can distribute heat to all pins simultaneously. For 2-5 pins this usually can be done by adding solder to the pads, making a blob of molten solder. For more pins you can cut a piece of heavy gauge copper wire and put it along the pads, then cover everything in solder and keep heating until all pins got loose. Here is very good video demonstrating this technique.
Pump and/or wick can be used afterwards to clean the pads.
In either case having an iron suitable for the job is most important. Big chisel or screwdriver type tips work best for this. |
H: Does changing the diameter of a wire affect the TCR of a wire?
I have a wire wound resistor that is changing too much when being heated and cooled. I know changing the chemical composition of the wire is the biggest factor in changing the temperature coefficient of resistance (TCR) of the wire, but I already have wires with a larger diameter of the same material. Although the resistivity of these wires would be lower, would the TCR improve? There would also be more wire on the resistor. I cannot find anything online that relates to this.
AI: Changing the diameter of a wire does not effect the TCR of a wire. However the TCR is not necessarily linear. The TCR at a high temperature could be higher or lower than it is at room temperature. Of course a change in diameter will change the resistivity. Using a larger wire to make a resistor of the same value will mean that the temperature will not increase as much for a given power dissipation because there is more surface area available to transfer heat our of the wire. |
H: Are there any low temperature (60 - 100 degree celsius) soldering pastes?
I'm looking for low temperature soldering paste that doesn't come in a wheel of filament. It seems tin and bismuth soldering pastes have a melting point of around 160 degrees Celsius.
Are there any formulations, or products on the market, for an even lower temperature soldering paste? I guess this company makes them, but I'm wondering if there is a formulation with a stronger market presence.
I need a conductivity strong enough to use ICs.
AI: There are chip removal alloys (lead-free) that melt around 79-91°C.
As well as being expensive, they're probably brittle and perhaps nasty in other ways.
Leaded alloys are available that melt at ~58°C, a bit less than what you are asking for.
As far as I know, those alloys are not available in paste form, however. What the industry calls "Low Temperature Soldering" is more like peak 190°C (lead-free process). |
H: What does the T stand for in AXI4-Stream's TDATA, TVALID, TREADY, etc.?
In the AXI4-Stream protocol, the names of the signal that make up a stream are prefixed with T: TDATA, TVALID, TREADY, TLAST, etc.
Does the T prefix have a meaning? "Transfer" comes to mind, but that term is also used in the (non-stream) AXI4 protocol, where the signal names are not prefixed with T.
AI: It would appear to mean 'Transfer'.
The specification does not explicitly state it but it clearly implies it on p1-2, the second page of the spec':
STREAM TERMS
The following stream terms are used in this specification:
TRANSFER A single transfer of data across an AXI4-Stream interface.
A single transfer is defined by a single TVALID, TREADY handshake.
See Handshake process on page 2-3.
The definition of a transfer is that it uses a TVALID/TREADY handshake. So a Transfer is that 'T' being made Valid and accepted by Ready. According to that definition text. |
H: Differential Pair Length Matching
I am routing a 16 bit ADC chip, the LTC2217 (datasheet) to FPGA. Each bit is an LVDS pair and I know +/- of the pair should be the same length but what about from pair to pair? I have 2 of these chips, 18 pairs, if you include OF and CLK, 36 pairs of LvDS having to be meandered to the same length becomes somewhat messy.
IE say bit 1 is 35mm and bit 0 is 37mm, how far off, if any are they allowed to be? I assume it has to do with sampling frequency, which for this chip is 105Msps.
AI: The answer is driven by the output timing diagram of your ADC, shown here:
The chip provides a clock signal synchronized to the data. The clock falling edge is in the middle of the data valid interval as they leave the chip.
At maximum data rate, the clock period is about 10 ns.
This means you need to keep all your data signals aligned to the clock, with skew no more than 3 or 4 ns.
Since propagation velocity on the board is somewhere in the neighborhood of 40 cm / ns, this should be relatively easily achieved. To be tidy, I'd shoot for no more than 1 or 2 cm of trace length difference between any data signal and the clock. |
H: Which adapter/handling to choose on (Type N) rf test devices when SMA/K cables have to be connected frequently?
I'm no expert in high frequency. But probably it is no good idea to change the adapters sitting on type N female output on and on as a torque wrench is used to fix them.
But I have to make measurements where often a amplifier or bias tee is connected betwenn a rf-probe and a signal generator or vector network analyzer. The rf-probes have 2.92mm K connectors, the devices (bias tee, amplifier) often SMA.
Now the probe vendor says that SMA cables/connectors damage the K-connector on rf-Probe.
As I want to use the expensive low loss cables maybe also in future up to 40 GHz, currently only 1-10 GHz, I'm wondering what is the right handling here? I also want to prevent to much insertion losses by many connector adapters. The money is not really the problem of if an adapter costs 100-200€
What do you suggest here? Combining SMA and K cables with adapters or changing the test device adapters (N to SMA/K) on and on (probably 100-200 times a year? Are there adapters or products I missed that could help me?
AI: Now the probe vendor says that SMA cables/connectors damage the K-connector on rf-Probe.
Probes are very fragile and could be damaged by a very small error in operating them. They should practically be treated as consumables, and if you're using them you should budget replacing them occasionally.
So what I'd do is buy a set of probes with SMA connectors, and use them with your SMA cables.
Save the expensive K-connectorized probes (and the risk of damaging them) for the times when you need the 40 GHz bandwidth and are using K-connectorized cables.
The thing is also we have to compare measurements with same frequency response between research groups and in best case very low losses. If I have to use K-probes 1-10 GHz (they are set to 40) with max. 3 GHz test devices what do you suggest?
If you're okay with the risk your K-connector probes will be damaged, just go ahead and use them with SMA cables.
An SMA plug with nominal geometry will not damage a K jack. The risk is that the SMA standard allows looser tolerance on the center pin length, so that an in-spec SMA plug with a maximum length center pin can damage the socket in the K jack.
So, to reduce the risk, you can use new SMA cables from a reputable vendor. These are unlikely to damage your K connectors (though I can't absolutely promise they won't). If your lab has an SMA connector gauge, you can probably check which of your cables have relatively long center pins and avoid using those with the probes.
If you can't take that risk, then all you're left with is buying some SMA-K adapters and using them to connect your cables to your probes. |
H: Reading ADC value with uV Reference voltage
I'm trying to improve the accuracy of the ADC by amplifying the signal by 1/256 (i.e. 1/2^8) to make 2 8-bit ADC into 16-bit ADC. My question is can the ADC give good results if the ADC values are from +25uV to -25uV by putting the reference voltage at 50uV.
I'm using ATxmega256A3U. I know that if the microcontroller says 0 to 2.5V then it should be good but I'm worried/curious if this will work. Has anyone tried it before?
AI: For the first ATxmega256 part I found a datasheet for, this will be out of spec:
Also be aware that 50 uV (never mind 50 uV / 256) is below the noise floor for this ADC: |
H: Determine angular position from two potentiometers
I am trying to generate a continuous angle based on the output of the two potentiometers that are inside my device. The pots are shifted by 180 degrees and are capable of spinning continuously. How can I use the signals from both pots to determine direction while also getting a continuous angle function? I understand how to do this with rotary encoders but am having difficulties doing the same with this device.
AI: There will be a gap in each of the two pots near where they (ideally) instantaneously switch from 95% to 5% or vice-versa depending on the direction of rotation.
I suggest using the center range of each- switching from one to the other when the current one goes out of the center of the range, in this case it would be 50% +/- 22.5%. There will tend to be a smallish glitch at the transition. If you need to eliminate that you could blend the two readings together with a function that weights the two readings in a variable fashion. You still want to ignore the output that is too close to the transition, but to blend the two inputs in the intermediate range. |
H: How to implement 32-bit adder logic using two 16-bit adders?
I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this.
verilog code
module top_module(
input [0:31] a,
input [0:31] b,
output [0:31] sum);
add16 adder2 (.sum(sum[16:31]), .a(a[16:31]), .b(b[16:31]));
add16 adder1 (.sum(sum[0:15]), .a(a[0:15]), .b(b[0:15]));
endmodule
This is the top level figure of the circuit:
This is the output waveform:
AI: To chain smaller adders to make larger ones, you need the building-block adders to have carry in and carry out connections and you need to link those connections from one ader to the next.
Your diagram does not match your code, your diagram shows a carry connection, but your code does not.
You need to expand your add16 module to support carry in and out connections if it does not already do so, then connect them up as in the diagram you have drawn.
P.S. This is the sort of thing you would normally only do as an excercise, normally you just use the + operator to add things and let the synthesis tool sort it out. |
H: What is the purpose /name of this CMOS gate configuration?
I have tried search via google images, but it's not good at recognizing line drawings
AI: Drawn as logic instead of transistors, it looks like this:
simulate this circuit – Schematic created using CircuitLab
The bottom branch is A & !B & C, the top branch is !A & B & !C, so the final expression is
$$OUT = A \overline{B} C + \overline{A} B \overline{C}$$
It isn't clear why this was implemented as multiplexers rather than a more conventional SOP circuit. |
H: Struggling to understand zero cross detecting circuit
I'm considering using this zero-cross detector circuit in a design but I'm struggling to understand exactly how Q1 is activated. The description says "Q1 turns on and feeds current from C1 to the opto via R4, whenever the mains voltage (divided by (R1+R2)/R3) is lower than the voltage across C1." I understand this, but it doesn't explain how the base of Q1 is activated. In order for the optocoupler to indicate a zero crossing, the base must be activated only when a zero-crossing occurs, so its reasonable to assume that it has something to do with the capacitor discharging, but how it actually happens is still eluding me. Can anyone venture an answer?
AI: D1-D4 form a bridge rectifier that will charge C1 up to about 1/20th of the peak voltage of the incoming AC power. (R1 + R2 are 440K, R3 is 22k 440/22 = 1/20).
During this time that C1 is charging the current will flow through C1 and through D5. This will reverse bias the base emitter junction of Q1 so it will not pass any current.
For a short period at the the end of each 1/2 cycle of the incoming AC the voltage will drop to a low value and C1 will start discharging into R3 via the base emitter junction of Q1. (The emitter will be negative with respect to the base). This in turn will cause a pulse of current to flow in the collector of Q1 through the optocoupler LED and R4 from C1 (which is still charged at this time).
The pulse of current will cause the output transistor of the opto-coupler to draw current and cause the output voltage to pulse to ground for a short time (500us-1ms).
These pulses will be centred on the zero-crossings of the input signal. |
H: How to extend detection distance of computer mouse?
I recently learned that modern computer mice take tiny pictures many times a second and compares them to understand in what direction it is heading. And that the little light at the bottom is to create shadows for uniform colored, textured surfaces to get a decent image.
I was wondering, is it possible to extend how far away the image sensor can pickup on a surface? Right now, if I hover my mouse over about 0.1" above the surface, I still get movement of my cursor, but beyond it fails to detect. If I were to put a strong magnification lens right after the sensor, would I be able to hover the mouse higher?
AI: Yes, what you suggest is possible. (Congratulations on your cogent thought process).
The mouse navigation compares "features" from one image frame to the next, and calculates how much X-movement and Y-movement has transpired. If no image features can be found, then no movement can be calculated. An out-of-focus image contains no features: a mouse's lens is extremely near-sighted.
A lens of a different focal length can focus further away. For example, a fixed focal-length camera usually extends focus to infinity. Doing this converts a mouse to a camera (See my profile photo; it was done with this modified mouse):
Having a sharp focus very far away likely allows features to be found, and XY movements to be calculated. Still, pointing it at a featureless sky would confuse the internal calculator, and yield no motion-detection.
However, the mouse is now useless as a mouse on a mouse-pad because features very close are out-of-focus.
Notice that the mouse's LED light source has been removed. Daylight is sufficient to create an image. The internal chip can accommodate a fairly wide range of light levels (but not as wide as your eye).
For a mouse on a pad, the LED is needed for illumination, since the mouse itself shields room light from the small space between mouse and pad.
The plastic lens included with this mouse could not be moved close enough to the internal chip to allow infinity-focus. It was replaced with a 4.5mm focal length plano-convex glass lens. The lens quality need not be high since pixel-count is so small.
Lens is mounted in a machined-brass housing that press-fit over the ADNS-2610 chip's cover. The tiny cover hole (to allow light inside) was drilled out to about 3mm dia. The cover has a 5.6mm diameter step over which the brass housing press-fit. The cover can be pried off the chip with care.
Interface to this 8-pin chip is serial I2C. This is an older chip that requires +5V Vdd. Avago data sheet is very well-done.
Have tested its XY scanning ability with infinity focus, but not used it as a mouse this way: you may find that much gesture movement yields small cursor motion on your screen.
More modern chips provide more pixels and pixel download rates are fast enough to allow video frame rates when used as a camera. Getting data sheets for them and getting small quantities for experimenting seems to be a problem. |
H: Stability - Driving a Capacitive Load
I know I have been asked not to provide video links and ask questions.
But I have no proper guide/mentor or anyone who can provide me better answers other than users in this site. So, please pardon me for this. I rely on this site for answers which can Solve my queries and help me with my understanding.
If you seen my previous questions, you would notice that a majority of my questions would have been related to control loop stability analysis of a dc-dc converter. I was not able to grasp the concept of zeroes with respect to electrical components. All I understood is that, If I have a pole, it means the electrical component will oscillate (at some frequency) and the system will be unstable. But what happens when a component provides a zero instead of a pole? How does one understand or find whether a component will provide a zero or a pole? What effect will that zero have in the system?
So, I am trying to learn it by watching questions and answers in this site, reading app notes, watching lectures and so on to get clarity.
In this Video, around 3:08 , he says that when the capacitance magnitude matches the resistance magnitude, we get a zero.
I don't understand that. Can you tell me :
Is he meaning that at some frequency, the capacitance impedance will be equal to the resistor's resistance? If so, at this point, what will the combination of the resistor and the capacitor connected to ground look like? And when he says zero, what effect will it have on the system?
Please do not think that I am asking multiple questions. If anyone can provide the answer which can help me clear my doubt regarding the poles and zeroes in an electrical circuit (in simple electrical terms for a beginner to understand) and how one can figure that this component will provide a pole or a zero, then that answer would solve all my questions.
Would be really grateful.
AI: Ok newbie,
i've read your questions and comments and have a gauge of your understanding level. what classes have you taken pertaining this subject?
If you're designing a DC-DC converter for stability using bode plots (poles and zeros), you received great answers already. You need to make it a goal of understanding them.
This is a pretty good read:
https://web.stanford.edu/class/archive/engr/engr40m.1178/reader/chapter7.pdf
It boils down to what another answer alluded to:
Poles/Zeros
zeros have +20db/decade gain and poles have -20db/decade attenuation.
You asked why in a comment? At the stage of PSU design you should have learned it, follow the math in my link.
Simply, in an RC circuit, as the frequency goes up, the impedance of C will become lower and lower, and the ratio of R - C will drop/increase and this rate happens to be at 20dB/decade.
Or thinking in the time-domain instead of frequency domain, the capacitor takes time to charge, so any fast changes in voltage will not be relayed with attenuation.
There is also phase. +/-90 degrees for a single zero/pole (respectively), 180 degrees for double pole/zero. The phase transitions quickly at the R+C or L+C crossover/corner frequency.
Multiple poles/zeros will have Nx20db/decade gain. so 2 pole will have 40db/decade (on average), roughly. With higher order yet poles/zeros other things come into play involving phase, and for real accuracy s-diagrams are needed. This link describes them in great detail: https://web.mit.edu/2.14/www/Handouts/PoleZero.pdf
It's not critical to understand this all for PSU design, as it's usually a combination of passive poles or at most a 2 pole LC, but it's good to understand the basics.
With this information you should know how to draw a bode plot. Good link:
https://pages.mtu.edu/~tbco/cm416/bodestab.html
Intuitively, this means a pole "slows down" the response of the system, because higher frequencies are attenuated. This often, but not always, has a stabilizing effect. A real-world example of a pole is heating up a pot of water to exactly 90C. You can crank it on "HIGH" (high input power) but the temperature (output voltage) takes like 5 minutes to warm up. The circuits have their own physical limitations that limit their speed, described w/ poles/zeros.
By inverse logic a zero "speeds up" the response of a system, by applying gain to higher frequencies which is more likely to have a destabilizing effect. Intuitively this makes sense: if an "ideal" zero will have more and more gain as frequency increase, then at some absurd 2.4GHz I will have +100dB of gain. So any teeny tiny interference from a wifi-router will cause the output voltage to change by an incredible amount. bad.
Both poles and zeros affect phase and gain, which affect stability.
There's a final point about the gain part of the bode plot: the gain level is usually set externally by an R+C and includes factors like the gain of the amplifier, any R-dividers, and so on. It's a variable that can be changed to affect the stability, where generally lower gain will mean a slower but more stable response.
Stability Critereon
Why is this gain/phase behavior of poles/zeros important?
A good read:
https://pages.mtu.edu/~tbco/cm416/bodestab.html
But basically, one things need to occur for sustained oscilaltions (instability):
+When PHASE reaches -180 degrees, there is greater than unity gain ( A > 1V/V, A > 0dB)
+Or, described inversely: when gain approaches unity (0.001dB), there is 180 degrees of phase shift
In reality, you don't want to approach anywhere near 0dB at 180 degrees phase shift, so the concepts of "gain margin" and "phase margin" as described in the link arise. As you "approach" this unstable point, you may have "DC stability" where your DC level will be correct, but a sudden shift in the DC operating point (say a step change in the load) will cause decaying oscillations at frequencies near the 0db/180degree point.
Gain margin is how much gain you have to spare when the phase reaches the trechearous 180 degrees. You want it to be well below the 0db threshold, maybe like -20dB.
Phase margin is how much phase you have to spare when gain hits 0dB. You want about -45 degrees for damped performance.
Intuitively, this stability critereon makes sense:
If you have GAIN while having 180 degree inversion, your system went from negative feedback to positive feedback. Having 180 degree inversion (and thus some positive feedback) is fine if it's gain is <0dB, because it won't accumulate. But having >0dB gain and positive feedback means a positive feedback loop that will grow as it oscillates. Even if gain is only 1.001 or like +0.1dB, it will gain until it reaches some other physical limitation.
So, you asked for intuition instead of tough math about poles/zeros, I hope this helps.
To bring it to your original question, why does a C on the output cause instability?
A big capacitor right at the output is an R+C zero in some converter topologies, and L+C in others.
It generally has a stabilizing effect on DC-DC converters, but can also cause instability. It depends on what this RC did to the bode-plot and whether it ruined the gain/phase margin of the converter.
Thinking about it in the time-domain, a super large C will cause the output voltage to change SLOWLY. This, like i said, usually stabilizes the output voltage, but you have to consider what the PSU system is doing. Basically, will the PSU patiently increase the current to charge the cap, or will it "accelerate" too quickly and dump huge current into the cap, overshooting. In the 90C pot of water example, you'd hope your control scheme would turn the power down a bit from HIGH as the pot of water approaches 90C, lest we overshoot and accidentally boil the water.
This rationale can be applied to any aspect of the PSU, they all have bandwidth/gain--i think of it as inertia as in the pot of water.
The output voltage (capacitor) can only gain voltage so fast. The inductor can only increase current supplied so fast. The amplifier only has so much gain at high frequencies. Bode plots allows us to quantify it.
There are also empirical ways to categorize a PSU (or any) control system. By applying a "Step" change to the input voltage or output load, the converter closed loop response can be characterized, and stability inferred. |
H: Two switches and two LEDs using 8051
I am trying to work around a circuit and my requirement is as follows: -
There are two inputs and two outputs. Each input controls an individual led. I am writing a code for this requirement using a Nuvoton MS51 based controller (Which itself is 8051 based controller). The software used for the same is Keil. Following is the code I have written-
#include "MS51.h"
void main (void)
{
P01_INPUT_MODE;
P03_INPUT_MODE;
P10_PUSHPULL_MODE;
P00_PUSHPULL_MODE;
while (1)
{
if (!(P0 & SET_BIT3))
{
while( !(P0 & SET_BIT3));
P0 ^= 0x01;
}
if (!(P0 & SET_BIT1))
{
while (!(P0 & SET_BIT1));
P1 ^= 0x01;
}
}
}
The problem I am facing is that both the switches are not working simultaneously but only in a sequence. The first switch will work, then the second (I am not able to use the first switch again).
Is there anything wrong that I am doing in the code?
Solution: I have found the mistake I was doing. The mistake was of pull-up/pull-down of the switch. My switch is pulled down and the code that I had written corresponded to the case of a pull-up. Hence my code was being stuck in the while loop again and again, hence stopping the flow of code to the next line.
AI: The code may incorrectly assume buttons being active low if they actually are active high. The code can't know that, it just looks at the bit value and it may be incorrect.
But that is how the code you wrote works - if either of the button bits are low, it sits in the corresponding button loop while it is low, or in other words, until it is high again without checking for the other button. If you want it to work differently, take paper and pen and design how it should work and then write it. Rarely any software is written first without thinking how it should work. |
H: Switching frequency and controller's crossover frequency in DC-DC converters
In the context of control loop stability of DC-DC Converters,
A switch mode power supply is essentially a sampled-data system, therefore the theoretical maximum bandwidth is one half the switching frequency. Practically the phase and transport lag there make it impossible to close the loop there, so 1/5 to 1/10th the switching frequency is a good rule of thumb.
Could some one tell me what does the words in blockquote mean when it says, "there make it impossible to close the loop there"? What does "close the loop" mean in electrical terms?
AI: What does "close the loop" mean in electrical terms ?
This is a control theory concept and simply means that you measure some physical quantity you want to keep at a certain value and then use this measurement to tweak some sort of control to cause this quantity to get closer to the desired value.
Let's be a little less abstract... think about a thermostat in a house air conditioner. This is a closed loop because the thermostat will measure the room temperature and if the room is hotter than desired it will turn on the air conditioner so that the temperature drops and get closer to the desired value. Once the temperature is low enough the air conditioner turns off to prevent the room from becoming too cold. If you simply turn on the air conditioner with the fan at a certain speed and leave it on all the time regardless of the actual room temperature, then you have an open loop.
Now back to your DC-DC converter... closed loop means that you'll measure the output voltage and will increase or decrease the duty cycle of the switcher if the output voltage is too low or too high in an attempt to keep the output voltage at the desired value.
"there make it impossible to close the loop there"
My understanding is that "there" means "at frequencies close to the switching frequency".
The idea is that in a switched circuit you only have the opportunity to "fix things" once per cycle. If you want the output voltage to go up, you increase the duty cycle (I'm thinking about a Buck converter) for that particular period; if you want the output voltage to go down, you decrease the duty cycle for that particular period. This means that the switching frequency imposes a limitation on how fast you can change the output voltage - you can never react faster than the switching period. That's why the text suggests using 1/5 or 1/10 of the switching frequency as an upper limit in terms of how fast you should design your control circuit to react in order to keep the output voltage constant. |
H: Noise on probe while measuring Switching Frequency of Buck Converter
I have a buck converter and I am measuring the voltage ripple at the output capacitor along with that I am measuring the switching frequency at the cathode of the diode. Please refer the below image. I am using 500MHz keysight scope.
Probe 1: Output Voltage across output capacitor (AC coupling mode is used with short ground tip)
Probe 2: Switching frequency measured at cathode of diode (DC coupling with ground of the probe connected to scope ground)
While measuring these two simultaneously, my output ripple voltage is picking up high noise. If I don't measure the switching frequency along with the output voltage ripple, I have no problem. While measuring together, my output ripple voltage probe, picks up noise.
What might be the problem?
AI: The output of your switching converter is a low-impedance node (at high frequency, it is basically a capacitor) so you don't have to worry about the probe loading the probed signal.
It is a hostile environment though:
Coil and traces emit AC magnetic fields...
This means the Magnetic EMI Loop Antenna Sensor in your scope probe (also known as a ground wire with alligator clip) will happily pick up any stray fields and turn them into spurious signal on your scope. It also adds inductance in the ground connection which will do all sorts of bad things to high speed signals (spurious ringing, lowered bandwidth, etc). You need to get rid of that loop antenna, and/or make its loop area as small as possible. Most likely, if you got a 500MHz Keysight scope, the probes came with these ground springs, so use them. It will look a lot cleaner.
There is HF AC current going through "GND"
Thus "GND" will not be at the same potential everywhere, and you should put the probe's GND spring tip on the correct spot, which probably won't be too close to where the switching happens. It is also a bad idea to probe on a capacitor. Since it shorts AC, ripple will be lower... but since it has AC current running through it which creates voltage in the pin inductance, HF ripple might also be higher... or just wrong.
If you're interested in ripple at the load, then... probe there. Or on vias on your ground/power plane. Or any place downstream of the DC-DC output caps. But not directly on the caps.
While measuring these two simultaneously, my output ripple voltage is picking up high noise. If I don't measure the switching frequency along with the output voltage ripple, I have no problem.
I'm going to guess your two probes' Grounds are at different places on your PCB, and there is a voltage difference between these two "GNDs" on your PCB, which creates a current inside the probes, cable shields, and scope internal ground. This can be a problem. Try putting the probe grounds in the same place, and a bit away from the switching.
You can clip a ferrite sleeve on one of the probe cables to increase its common mode impedance, too.
If you want a high-quality measurement of output ripple, but you're just interested in the switching signal on the diode to measure frequency or trigger the scope, but you don't care about signal integrity or accurate measurements, then simply not connecting the ground of this probe at all may be a solution. Use the ground clip on the probe which measures ripple, and just use the tip on the other probe.
You can also solder a 51R resistor and a 50R coax, then connect that to your scope. Make sure to use 50R termination on the scope, and double check if the termination resistor inside the scope is specified to take the voltage you're using. You can AC-couple it at the source by adding a cap in series with the 50R resistor too. |
H: Help identifying connector on vinyl shellhead
I'm working on a DIY project where I'm basically creating/connecting my own vinyl record player arm.
I have one of these shellheads in the picture below. Ideally I wan't to be able to use this, and also use the connector show, without soldering cables directly onto it. Is this a regular type of connector, which I can buy the female part of? If so, what is it called? It looks like a short DIN connector, but the pins are perfectly squared, which DIN isn't.
Thank you!
AI: Often called an SME tonearm headshell connector 4-pin.
The mating part is either a replacement SME 3009 or 3012 tonearm or a female SME tonearm 4-pin socket. Here are a few examples of available parts:
http://www.audiosilente.com/spare-parts-for-sme-new-sme-3009-connector-with-gold-plated-pins.html
https://www.ebay.com/itm/New-5pcs-lot-Technics-tonearm-headshell-SME-socket-connector-pure-silver-wire-/123834227569 |
H: Replacing a 1.5V with a 5V power source
I've got a motor that's driven by a 1.5V battery. The shaft turns slowly and that's the way I'd like after replacing with a USB cable (5V) source.
In the current circuit there's no resisters (just a diode) - so using ohms law - not sure what the current draw is. It's V/0 right? Infinity?
If I can find the current draw - I plan to use 5/I to add an appropriate resistor and I should be good to go - right?
Please help the nube boob.
AI: Just adding a resistor is not the right way to go. The current draw of a simple DC motor changes depending on the load. In an unloaded condition the current will be at a minimum. In a stalled condition it will reach a maximun. To run a 1.5V motor from a 5V source you should step down the voltage with a regulator IC or a string of 4 or 5 silicon diodes, (the diodes will need to be rated for at least the maximum motor current, or best guess in this case). Using a USB from a PC might be risky if you do not know the motor's current draw, best to test out the idea using a USB wall adapter first. |
H: Minimum voltage drop to run a circuit
Disclaimer : this question may be more 'physics' than electric engineering
So suppose you have a circuit with a battery and some other elements, the elements, the battery continuously provides energy to the circuit lets say 'E' by the kirchoff voltage law all this energy should be used up as you loop the circuit. Now my question is how would you find the minimum amount of energy which you would need to run a circuit , or how do you find the current/voltage rating given on the back of electirc products?
AI: Typically you design a circuit with parts where you have datasheets. These datasheets will explicitly tell you in which voltage range they will work and the designer of the circuit will make sure, that the parts are supplied by the correct voltage by specifing that as input voltage. If other stuff (e.g. a voltage divider or voltage regulator) is placed in front of that device, the voltage rating for the input voltage will change in a way you can easily calculate.
The manufacturer supplying the sub-part with datasheet (like transistor, IC, whatever) will as well use math and simulations to find the proper voltage range. In addition he will probably do extensive testing to check which voltages lead to failure or degradation. |
H: ADC / data acquisition board - general layout question
For one of my current projects, I am designing a small data acquisition board.
However, I am currently not sure about the overall layout of the board.
Here are 2 possible variants I came up with. First of all, the position of the connectors is necessary for these positions, due to mechanical constraints.
My question is actually regarding the position of the I2C expander and its position. The LED's it drives have to be in this position for visibility.
The I2C expander has to be powered by the digital supply.
The state of the LED's will not change during data acquisition and also the I2C bus will not have to transmit any data during the acquisition.
So here are my questions:
which of the 2 layouts is better in terms of EMI / radiated emissions?
For the case, that the LED state does not change during acquisition, do I have to expect any other negative effects on the ADC due to the constant LED currents / I2C expander quiescent currents?
If 1 and 2 are both not optimal, what have I missed and how could I arrange it better?
For case 2, would it be better to have the GND left unconnected on 1 side of creating a loop with the analog plane in the middle?
The ADC I'm planning to use is an ADS8881 - Product page - Datasheet
The MCU I'm planning to use is an STM32F103 - Product page
AI: 1) Initially routing diagram 2 is the better of the two.
2) It is always best to avoid running digital lines (or their ground returns) close to or over ADC lines, even if they are considered constant or slow. There can often be moderate levels of digital noise even on stable digital lines.
3) Consider moving the IO-expander right up against the MCU to reduce high speed trace lengths.
Widening the cutout lines between the two ground planes would better isolate the digital and analog signals and reduce potential noise transfer.
If the digital supply is a switcher type consider moving it further away from the analog supply components.
You might even try to keep the analog ground separated all the way back to the main power entry point or the filter components of the analog supply. Connect the two grounds at only one point.
To minimize radiated emissions reduce the length and loop size of all high speed signals, minimize the number of sharp angles in traces with high speed signals.
Keeping the analog input lines short and direct can help reduce noise. However this might be a compromise if the ADC uses a serial interface (with longer high speed lines).
4) No. |
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