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H: Problem with 74HC76, silly mistake or possible fake?
I am a hobbyist and have been buying a few cheap ICs on AliExpress to play around with at home. I know that there is some risk involved in buying these but I seem to have had mostly good luck so far. A couple months back I received a batch of ICs that were definitely fake because they didn't have any coherent output. When I contacted the seller they didn't reply and it was too late for me to initiate a dispute. So now I try and sanity check what I receive right away.
Right now I am having a problem when testing some SN74HC76s (JK flip-flops). I have a bench power supply with current limiting and when set at 5V, 20mA it just dumps all the current out of ground. I've verified this with a DMM. I don't think this is normal for this chip, is it? The datasheet doesn't seem to indicate this. Neither Q nor ~Q are going high. I am hoping that you guys can sanity check my hookup to make sure I'm setting it up properly. No matter what the reason for it failing to work I just want to understand why. If it is a fake, I'd like to get better at realizing it sooner. Thanks for any help.
Here's the datasheet
AI: That chip in the picture is L293D, not 74HC76, so it does not work. |
H: High Current voltage regulator. using 7805
I a have a battery that supplies a a voltage range of 11.1 - 12.4V depending on how charged it is.
I would like to regulate this down to 5v. The issue is I would need to draw up to 6 amps through it.
The voltage regulator i have access to is the 7805.
Looking at the datasheet I found the circuit using a transistor to carry most of the current.
I have a BD180 transistor which can carry up to 3 amps, but i would need 2 of these in parallel somehow, as 3 amps isn't enough.
I am not that well versed in electronics and dont really know how u would go about doing this, any help is appreciated
AI: A linear regulator like the 7805 + transistors will simply "burn off" the voltage difference of 12 V - 5 V = 7 V. At the current of 6 A that means about 42 Watts will be converted into heat. That will require a massive heatsink which can be expensive.
You will be much better off using a switched converter which is much more efficient and will be cheaper as well as you do not need the large heatsink anymore.
I would never recommend a beginner to build their own switched converter, the chance that it will simply not work is quite large. Especially at the large current you want, the chance of success will be small as you don't yet know what it takes to make that work.
I'm experienced with electronics and even I don't build my own switched converters. Instead I just buy a module! Much easier and also cheaper.
So I also suggest that you just buy a ready made module, here's an example.
6 A is quite a lot of current, if you need it for multiple devices then I suggest that you split them in groups of about 3 A each and then use two modules to power them. Connect all (black) ground wires together but keep the (red) 5 V wires separate per group. Spreading the load like this will very likely prevent issues in the future. These cheap modules usually don't work well at or near their full load current. So it is better to spread the work across two modules which then operate at a lower current. Often they can handle that much better. |
H: Battery output power calculated from internal resistance - explanation, relation to heat generation and actual power?
On a battery manufacturer specification (https://www.scib.jp/en/product/cell.htm, "High power 10Ah cell") it says: Output power 1800W* (SOC:50%, 10s, 25°C), *This value is calculated from the internal resistance.
How is this power rating calculation from the battery's internal resistance carried out exactly?
How does the above calculated output power relate to the heat generation rate (W) of the battery that is also calculated from the internal resistance?
And how does this theoretical output power (typically) relate to the actual battery output power available to the user in practice?
AI: How is this power rating calculation from the battery's internal resistance carried out exactly?
My guess is that it is based on the maximum power transfer theorem, hence the maximum power you can deliver to a load depends on the internal resistance of the battery.
How does the above calculated output power relate to the heat generation rate (W) of the battery that is also calculated from the internal resistance?
If the above guess is correct, then the power delivered is the same as the power dissipated in the battery itself.
And how does this theoretical output power (typically) relate to the actual battery output power available to the user in practice?
At maximum power transfer, the output voltage of the battery cell would be half of the no-load voltage. In addition, the efficiency would be 50% and hence a lot of the energy is lost in internal dissipation. For a practical case, the allowable voltage drop and criteria for energy efficiency would limit the power delivery. I have no industry experience on battery systems, but to increase the energy efficiency to above 80% or 90%, the power must be decreased less than 64% or 36% of the stated maximum output power value (again using the same theorem). However, the internal resistance will vary with several operating parameters, so my numbers are for an ideal case. |
H: Rain sensor + transistor
I have a Raspberry with a rain sensor connected. In order to avoid electrolysis on the rain sensor I would put a transistor (2N3904) in the circuit to power on the rain board only few times per day, read the sensor, then power off. I would ask if the circuit I drew is right.
In the scheme I put a “Vibration Motor” just for simulating the circuit (see attachments). In my case it will be substituted with the board of the rain sensor: the GPIO pin of Pi with 5v (my sensor works with 3.3v but I used 5v for showing two different sources) will be connected to Vcc pin on rain board, the Collector of the transistor will be connected to GND on the rain board and the Emitter will be connected to GND of Pi. The Base of the transistor will be connected to a GPIO pin set as output (3.3v). A python script will put this pin = True at specific intervals.
Could the above circuit work?
Forgive me if I made any trivial mistake.
Thanks
AI: I believe this should be able to work, and I will provide the calculation for selecting the correct base resistor to ensure the transistor is turned fully on.
You state the sensor draws 15 mA when on, so let's be conservative and aim for a collector current of 20 mA. According to the data sheet of the transistor it has a current gain of at least 100, therefore the base current Ib must be:
$$I_b=\frac{I_c}{h_{FE}}=\frac{20mA}{100}=200uA$$
The resistor is then chosen to allow this amount of current to flow when 3.3V is applied by your GPIO. The base-emitter junctions typically drops 0.7V so there will be 2.6V across the base resistor. Using ohms law the appropriate restore can be calculated:
$$R_{base} = \frac{3.3V - 0.7V}{200uA}=13k\Omega$$
Round down to 10k ohm to be sure the transistor is fully on and you should be good to go! |
H: Building a keyboard matrix
I want to build a 7 Rows x 15 Columns keyboard from scratch, thus I have started from the theoretical design of the matrix. The classic way should be to assign directly the Rows and Columns to (7+15) I/O of a microcontroller and also connect 7X15 diodes to every each switch in order to prevent the "ghost" effect.
Yet, I redesigned a matrix using multiplexers - demultiplexers as follows:
Just to keep it simple, let's say that I have a 8x4 matrix, the columns connected to a demultiplexer and the rows connected to a multiplexer. That should work with the pseudocode:
for each output of the demux:
for each input of the mux:
check if a individual button has been pressed, else \\
send HIGH due to pull up resistors
Since in every each loop only one switch can be inspected and there is not any physical connection to other switches, I think I could prevent the "ghost effect" without the need for any diode component.
Also, for a 15x7 matrix, instead of using (15+7) pins, I could use a 16:4 demux and a 8:3 mux, thus only 4+3 = 7 pins.
Please, tell me your opinion, or point any flaws of the design.
AI: There is still a ghost effect.
Let's say that the user has pressed R4C9, R4C10 and R3C10. When C9 is energized by the demultiplexer, current can flow onto line R4 via R4C9, then line C10 via R4C10, then line R3 via R3C10. The R3 line will be energized. When you energize C9 and check R3, you will see the signal present that means the key is pressed, even though the key is not pressed.
There's no problem with using multiplexers instead of separate I/O pins. It might affect how quickly you can scan all the keys. |
H: Difference CPU, ASIP, DSP
During lecture CPU (Central Processing Unit), ASIP (Application-Specific Instruction set Processor) and DSP (Digital Signal Processor) were briefly mentioned.
Unfortunately the main differences (and use cases) weren't discussed.
In my understanding CPUs are the general purpose work horses. They are flexible, but not as efficient to specific tasks. DSPs are basically stripped down CPUs, which are really efficient at digital signalling applications. ASIPs have an custom instruction set for specific use cases.
Is this understanding correct? Could you elaborate further the differences and use cases of those devices? Is a DSP an ASIP?
AI: "ASIP" is not a term the industry bothers to use. The similar-sounding "ASIC" (application specific integrated circuit) basically means any piece of specialized IC design that isn't a general purpose processor.
A DSP is not "stripped down", it is optimized for digital signal processing tasks, which usually means convolution, fast fourier transform, discrete cosine transform, filtering, and so on.
This usually means having the ability to do a block of multiplications and additions in one instruction.
DSPs are generally more powerful than microcontrollers but lack some of the features required for multi-user operating systems, such as virtual memory. |
H: Does cutting the covering of subwoofer wire affect the sound quality?
I have Sony 5.1 channel sound system. There is some cut on covering of subwoofer wire. The copper wire is not affected at all. So, I am curious to know whether it will leak the passage of sound and hence, the sound quality will be affected or not?
Is there any disadvantage of it?
AI: Although I'm tempted to state there's some special effect from the insulation capacitance and characteristic impedance that only the golden-ear audiophile can hear (a stunning difference!), no there is no measurable direct effect from that bit of insulation being there or not. The insulation keeps the wire from shorting to the other wire or to ground.
You can wrap some electrical tape around the bare spot and get on with your life. Heat shrink tubing might be a bit more attractive, but the kind of insulation used for speaker wire is sometimes very low melting point so you might further damage the wire with the heat gun. |
H: Using different UART pins on STM32 Nucleo
I am trying to use the STM32F103RB Nucleo board. I am learning how to do serial comms so started with the classic 'Hello world' printed to a serial monitor.
Eventually, I want to print data to the serial monitor, while receiving data via different UART pins. The Nucleo uses pins 16 & 17 (PA22 & PA3) as the default Tx/Rx pins. I started with them, and had no problem. The code was simple:
#include "mbed.h"
Serial pc(PA_2, PA_3);
int main() {
pc.printf("Hello World \n");
}
Looking through the DATASHEET I can see that pins 42 & 43 (PA9 & PA10) can also be used for UART, with PA9 Tx, & PA10 Rx. I decided to change the pin definitions for Tx and Rx, so the code now looked like this:
#include "mbed.h"
Serial pc(PA_9, PA_10);
int main() {
pc.printf("Hello World \n");
}
And this now doesn't work. Looking through THIS PAGE I don't see why that doesn't work. I have used 'Serial', given it a name (pc), then defined the Tx and Rx pins. I am using the mBed online environment if that makes a difference to anything.
Can anyone see if there is some simple mistakle or something I have overlooked when trying to do what should be a simple task?
If there is any more information required, please ask.
AI: Along with SWD flashing, the debug interface chip on the Nucleo provides a USB<>serial functionality to allow the target chip to communicate with a PC.
But this functionality is hard wired to the default UART pins of the target.
If you wish to use different UART pins, you will need something to connect those to your PC as well or instead - either an external 3v3 USB-UART, or to somehow rewire the on board one.
The signals to the on-board one are routed via resistors which can be removed, and there are header footprints which could help with re-routing. For the 64-pin STM32 Nucleo, these can be seen in the schematic (circled in red). |
H: Is this circuit correct?
I need to know if this circuit is efficient to transfer most of the current from several identical independent 2 phase dynamos. The converters are all the same and ideal for the voltages no problem with that.
Is this the correct way? Thanks!
AI: Simplest form of load balancing is to add a series resistor to each diode. But you lose some voltage.
You were losing some voltage anyway, because of the diode.
It works as follows. The DC/DC converter with the highest output voltage and the lowest diode drop will start supplying current first and the most. But, with increasing current, the voltage over the series resistor causes the output voltage to drop. That allows lower voltage supplies to catch up and the system more or less balances out. The voltage drop over the diodes, which also varies with current, will help a bit with balancing
As I said, that is is simplest method. A much more complex but efficient scheme would be if you measure the current from each output and use that to "somehow?" control the output voltage. Whether that is possible greatly depends on what the DC/DC converters offer for a feedback mechanism.
If the DC/DC converters have a constant current mode, you could just wait for that to kick in and distribute the load. (It will not be balanced.) The disadvantage is that the converter(s) with the highest output voltage will be used most of the time and the others will follow one-by-one. Again the voltage drop over the diodes will help a bit with balancing. |
H: Does AC phase shift violate Ohms law?
Ok, so I am not new to electronics by any means, but I still can't grasp one key concept: AC voltage-current phase shift. I understand the math behind it, but I need someone to explain to me how it works at the fundamental level.
Let's take into consideration the circuit below.
The input sine voltage is 100V and we know that inductor causes voltage to lag 90 degree behind the current.
My first question is does the phase shift happen in the whole circuit, or only after/before the inductor?
My second question is if we would measure the voltage and current flowing through the resistor R1, and since they are not in phase, doesn't this violate the Ohms law (how can maximum current flow through the resistor when it doesn't experience maximum voltage)?
Thank you.
simulate this circuit – Schematic created using CircuitLab
AI: The input sine voltage is 100V and we know that inductor causes voltage to lag 90 deg behind the current.
My first question is does the phase shift happen in the whole circuit, or only after/before the inductor?
The current through the entire circuit lags the supply voltage. The voltage across the inductor leads the current.
My second qustion is if we would measure the the voltage and current flowing through the resistor R1, and since they are not in phase, doesn't this violate the ohms law ...
The voltage across the resistor is in phase with the current. The amount by which the current lags the supply voltage is determined by the combined effect of the resistor and the inductor. |
H: How I can solve this circuit with diodes?
I tried to solve this circuit but without success.. Also is there any current flowing trough D3? and how this isn't short circuit?
AI: You know the Shockley diode equation:
$$I_\text{D}=I_\text{SAT}\left(e^{^\frac{V_\text{D}}{\eta\,V_T}}-1\right)$$
Since the emission coefficient, \$\eta\$, isn't specified we can assume it is \$\eta=1\$ and simplify a bit (or you can keep it in, if you want.) Here, I'll ignore it.
The only voltage you need to compute is the common node shared by all three diodes (unlabeled in your diagram.) Let's call it \$V_\text{X}\$. Then nodal analysis says that the sum of the currents into the node must equal the currents out of the node. So it's easy to set up the following (since \$I_{\text{SAT}_1}=I_{\text{SAT}_2}\$, I'm just replacing any instance of \$I_{\text{SAT}_2}\$ with \$I_{\text{SAT}_1}\$ below):
$$\begin{align*}
I_{\text{SAT}_1}\left(e^{^\frac{V_\text{X}}{V_T}}-1\right)+I_{\text{SAT}_3}\left(e^{^\frac{-V_\text{X}}{V_T}}-1\right)&=I_{\text{SAT}_1}\left(e^{^\frac{65\:\text{mV}-V_\text{X}}{V_T}}-1\right)\\\\
e^{^\frac{V_\text{X}}{V_T}}+\frac{I_{\text{SAT}_3}}{I_{\text{SAT}_1}}\cdot e^{^\frac{-V_\text{X}}{V_T}}-\frac{I_{\text{SAT}_3}}{I_{\text{SAT}_1}}&=e^{^\frac{65\:\text{mV}}{V_T}}\cdot e^{^\frac{-V_\text{X}}{V_T}}\\\\
\left(e^{^\frac{V_\text{X}}{V_T}}\right)^2-\frac{I_{\text{SAT}_3}}{I_{\text{SAT}_1}}\cdot e^{^\frac{V_\text{X}}{V_T}}+\frac{I_{\text{SAT}_3}}{I_{\text{SAT}_1}}&=e^{^\frac{65\:\text{mV}}{V_T}}
\end{align*}$$
Set \$y=e^{^\frac{V_\text{X}}{V_T}}\$ and the above becomes this quadratic:
$$y^2+\left(-\frac{I_{\text{SAT}_3}}{I_{\text{SAT}_1}}\right)y+\left(\frac{I_{\text{SAT}_3}}{I_{\text{SAT}_1}}-e^{^\frac{65\:\text{mV}}{V_T}}\right)=0$$
Solve that for \$y\$ (pick the reasonable one of the two answers) and then find \$V_\text{X}=V_T\,\operatorname{ln}\:y\$. (I think in your situation \$V_T\approx 25\:\text{mV}\$, but feel free to use whatever you think is appropriate there.) |
H: How to wire up a street light to change lights in specific states (digital circuit)
This is the final project for the only electronics course in my career. I have never taken any other electronics course and I'm seriously at a lost here. I need to score 100 here to pass the course.
I need to create a synchronous counter that will control a streetlight with 4 sides. The South-North side has 4 lights (an extra green one to steer left) while every other has 3.
The cycle lasts 14 seconds.
I have the counter made, but I have no idea how to actually make it turn on/off the lights at the specified times.
Problem instructions are as follow:
"The first green light of S-N and the one from N-S must light up for 5 seconds,
meanwhile, the red lights from E-W and W-E must be on as well.
After these 5 seconds, the yellow lights for both S-N and N-S turn on for 2 seconds.
After this, the red lights for S-N and N-S turn on
and the 2nd green light of S-N will turn on for 2 seconds to allow traffic coming from the south to steer to the west.
This is the only instance where 2 lights of the same side are lit up simultaneously.
While the 2nd green light from S-N is on, every other Red light must be on as well.
After the 2nd green light from S-N turns down, the red light of S-N and N-S will stay on, and the green lights of W-E and E-W will turn on for 3 seconds.
After these 3 seconds, the yellow lights will turn on (while the green ones will turn off) for 2 seconds
and then the red ones will turn on, starting the cycle anew.
Total duration is 14 seconds".
This is SERIOUSLY driving me crazy because I see no way in which I could say "From 1 to 5 stay ON and then turn OFF", I cannot think of a single way of setting up logic gates so that they're only outputting 1 to the lights when
they're 0001, 0010, 0011, 0100 and 0101. Because if I make logic to output 1 when you have that, then literally every other binary code except from 0 and 15 will output one. I.e the lights will never turn off.
Note that this is entirely digital, using Digital Works. The solution cannot have any component that is not included in the program and should, in fact, only include Flip flops, LEDs, logic gates and of course the wires.
EDIT: Thank you for your help and tips. I managed to do it.
For reference, here is the completed and working circuit:
AI: There are lots of ways to take this. You could go asynchronous or synchronous, for example. But I'll suggest a start using a synchronous counter. You need a modulo 14 counter. For that, I might suggest a modulo 7 LFSR (not the only way to go) with a separate FF that toggles to make a total of 14 states:
simulate this circuit – Schematic created using CircuitLab
The codes, in sequence, are: 0000, 0111, 0100, 1101, 1000, 0011, 1110, 0001, 0110, 0101, 1100, 1001, 0010, and 1111. (The missing codes are 1010 and 1011.) This provides 14 distinct states. You can then use these, with added logic, to generate your light controls. (Note that in the above diagram, not only do you have access to each bit but also access to the inverted state of each bit. Also, if these DFFs have both Q and /Q, then the above diagram can be simplified a bit.)
By the way, you only have 7 distinct light control wires. You need three for the east-west and west-east directions (all of which use the same controls for red, yellow, and green lights), plus three more for the shared north-south and south-north directions (again, all of which use the same controls for the red, yellow, and green lights), and one more control line for the special south-north special-green light.
This is not necessarily the best way to handle it. It may require some combinatorial logic that you may wish were smaller. But it certainly can work.
(Note that the CLK input should be driven with a \$1\:\text{s}\$ clock rate.)
Do you know how to lay out the combinatorial logic needed for your control lines to the lights? Is that the problem?
I've quickly laid out what I think may work, regarding K-maps for the above states. However, be aware that I may make mistakes. So check the following work for yourself. (In what follows, 0 means off and 1 means on.)
East-West and West-East K-maps:
$$\begin{array}{rl}
\begin{smallmatrix}\begin{array}{r|cccc}
Red&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&1&1&1&0\\
\overline{Q_D}\:Q_C&1&0&1&1\\
Q_D\: Q_C&0&1&0&1\\
Q_D\:\overline{Q_C}&1&0&x&x
\end{array}\end{smallmatrix}
&
\begin{smallmatrix}\begin{array}{r|cccc}
Yellow&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&0&0&0&1\\
\overline{Q_D}\:Q_C&0&0&0&0\\
Q_D\: Q_C&0&0&1&0\\
Q_D\:\overline{Q_C}&0&0&x&x
\end{array}\end{smallmatrix}\\\\
\begin{smallmatrix}\begin{array}{r|cccc}
Green&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&0&0&0&0\\
\overline{Q_D}\:Q_C&0&1&0&0\\
Q_D\: Q_C&1&0&0&0\\
Q_D\:\overline{Q_C}&0&1&x&x
\end{array}\end{smallmatrix}
\end{array}$$
North-South and South-North K-maps:
$$\begin{array}{rl}
\begin{smallmatrix}\begin{array}{r|cccc}
Red&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&0&1&0&1\\
\overline{Q_D}\:Q_C&0&1&0&1\\
Q_D\: Q_C&1&0&1&0\\
Q_D\:\overline{Q_C}&0&1&x&x
\end{array}\end{smallmatrix}
&
\begin{smallmatrix}\begin{array}{r|cccc}
Yellow&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&0&0&1&0\\
\overline{Q_D}\:Q_C&0&0&0&0\\
Q_D\: Q_C&0&0&0&1\\
Q_D\:\overline{Q_C}&0&0&x&x
\end{array}\end{smallmatrix}\\\\
\begin{smallmatrix}\begin{array}{r|cccc}
Green&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&1&0&0&0\\
\overline{Q_D}\:Q_C&1&0&1&0\\
Q_D\: Q_C&0&1&0&0\\
Q_D\:\overline{Q_C}&1&0&x&x
\end{array}\end{smallmatrix}
\end{array}$$
Special-Green South-North K-map:
$$\begin{array}{rl}
\begin{smallmatrix}\begin{array}{r|cccc}
Green&\overline{Q_B}\:\overline{Q_A}&\overline{Q_B}\: Q_A&Q_B \:Q_A&Q_B \:\overline{Q_A}\\
\hline
\overline{Q_D}\:\overline{Q_C}&0&1&0&0\\
\overline{Q_D}\:Q_C&0&0&0&1\\
Q_D\: Q_C&0&0&0&0\\
Q_D\:\overline{Q_C}&0&0&x&x
\end{array}\end{smallmatrix}
\end{array}$$
I've included a possible solution below. It's validated, so it works. The point isn't to provide you with a direct answer, but is instead intended merely to let you know what one possible solution might look like.
You appeared to complain about the ability to hold the lights for given times (5 seconds, or 3 seconds, etc.) This shows exactly how that can be achieved.
I didn't attempt to optimize the design (I'm sure that more could be done.) But I simply took the above K-maps and developed what amounts to a CPLD or (AND-OR) matrix solution for the combinatorial logic. The clock is intended to have a one second cycle time.
Here is the lighting results from the above schematic:
Everything prefixed with NS applies to both the north-to-south direction as well as the south-to-north direction. The light prefixed with SN only applies to the south-to-north direction. The rest, prefixed with EW applies to both the east-to-west as well as the west-to-east directions. |
H: What is wrong with this complex circuit analysis?
I tried mesh analysis of this simple circuit but it is wrong, i can't figure out why though.
I simply applied KVL using the two mesh currents.
EDIT:
the phasor Ig is known so i make the obtained linear system in a system with Vx1 and I2 as unknowns.
Plugging in the data from the problem:
R1 = 2;
C1 = 0.333;
L1 = 2;
Ig1 = −2;
C2 = 1;
R2 = 0.5;
ω =1;
I solve the system. The correct solution is Vx = -3-6j though.
AI: The substitutions of \$I_1\$ and \$R_2\$ are incorrect.
\begin{cases}
-V_x+I_2(j \omega L_1)=-I_1(R_2+j \omega L_1)
\\
\\
0 + I_2(R_1+\frac{1}{j \omega C_1}+\frac{1}{j \omega C_2}+j \omega L_1)=-I_1(j \omega L_1)
\end{cases}
\begin{cases}
-V_x+2jI_2=\color{red}{-(-2)}(\color{red}{0.5}+2j)=1+4j
\\
\\
0 + (2-2j)I_2=\color{red}{-(-2)}I_1(2j)=4j
\end{cases}
The last part of your calculation is correct, but used incorrect values.
For completeness, I'll continue with the correct values.
Compared to your solution \$I_2\$ actually changes sign, so:
$$ I_2=-1+j$$
Substiting this into
$$-V_x+2jI_2=1+4j$$
yields
$$V_x=2j(-1+j)-1-4j=-3-6j$$ |
H: Programmable polarity switch for DC circuit
My question concerns a future research project in electrocoagulation (water treatment) I am planning right now.
I will have a lab power supply connected to two (or more) plates in water. The operation will run in a galvanostatic mode, meaning I want to have a constant current through the system as one of the major outcome determining factor is the charge density through the plates (e.g. \$mA/cm^2\$). The plan is to procure a lab power supply that can supply up to 30 A, since that is at the higher end of the range I want to test. My measuring probes and the power supply will be programmable, meaning I have the possibility of centrally controlling the electrical inputs and the data collection of experiments from my computer.
One thing that I want to test is reversing the polarity of my electrodes to counteract electrode passivization, i.e. switching the anode and cathode during the experiment. I would like to do this in a programmable fashion as well. For example, either at timed intervals or maybe when a certain voltage drop has occurred due to the increased resistance from the passivization.
Given that I have all required signals connected to the computer, what would be the way to solve my problem? The programmable side will not be an issue for me, I am mostly interested in the best way to solve the problem.
Requirements:
Switching circuit should be able to handle up to 30A passing through the switching side.
Programable
Thanks in advance!
AI: Use a H bridge / motor controller (where your anode and cathode replace the motor).
Image source: multiple motor h bridge? |
H: How to establish communication between microcontroller on a bread board and laptop using usb cable?
I want to learn about microcontrollers and use them in some projects. But I do not want to buy an Arduino, although that is what would be easy for doing projects. This creates a problem in programming the microcontroller. Although a programmer can be used, I noticed that many microcontrollers have an SPI. I thought I could use this along with a USB to programming it serially. I may also read the data serially (using shift registers) into the computer. This way, I think, I can establish communication of some sort between the two. But I am not sure if my computer will allow me to write to a USB port without any identifiable device being connected.
I am aware I would have to write some code to make this smooth since, both the microcontroller and the computer have different clock speeds.
AI: An Arduino does not have to be a pre-fabricated board - it can be as simple as a microcontroller IC and some support components.
An eg basic Arduino Nano clone from Asia for under $US3 incl shipping gives you a few basic ICs a voltage regulator, a USB to serial interface and some support firmware to allow bootloading from USB. You gain nothing by not starting with a few parts on a board and the bootloader and free environment. Once running you can pursue whatever purist directions that seem good.
Struggling with months to achieve what can be done in hours in setting up an Arduino will teach you much, but there are far far far better ways to use the same learning time.
I built my first microcontroller system on strip board about 45 years ago!!!
Based on a Nat Semi SC/MP.
NO O/S,
Binary toggle switch program and data input.
(No keyboard or keypad initially).
LED I/O (yes, we had LEDs :-) ).
No assembler (let alone an HLL).
Later we graduated to using Baudot code teleprinetrs - that we wrote our own code for.
So, yes, I know what you can learn the hard way.
Buy an Arduino to start :-).
You can learn far far far more quickly by starting with an Arduino and working DOWN once you have it running. Arduino use in no way misses out on ANY computer architecture aspects. You are doing yourself a massively large disservice by not starting with Arduino.
Arduino Bootloader:
What it does and why use it, & How to turn any appropriate AVR microcontroller IC into an Arduino.
An Arduino-less Arduino here
and
Adding a bootloader with ICSP here
and
here
and here
Stack Exchange discussion here
What it is and what it does here |
H: How does a number is saved in a register
I've tried looking online, but I still haven't quite figured it out - does a number, for example 0x100 saved in a register by some convention like little/big endian like thigs are saved in memory or maybe it is just casting every digit into 4 bytes from lsb to msb? e.g. if I'm writing the following line in assembly:
movq $0x100, %rax
will rax look like this: msb 00000000 00000000 00000001 00000000 lsb
or perhaps something else by little-endian convention or something like that?
thank you for your help
AI: Registers don't have endianness. Endianness is only relevant when data is stored in memory.
The reason endianness is relevant to memory is because you can access the individual bytes of memory, using an address. You generally can't access the individual bytes of a register, and when you can, they have names (like %al is "the lowest byte of %rax") which mean the same thing regardless of endianness.
If you couldn't access individual bytes from memory, or if you used a command like "get me the lowest byte of address 5" instead of "get me address 20", then endianness wouldn't matter for memory either. |
H: Controling linear PSU temperature
In many digital lab PSU designs, designers usually use a thermistor to control the cooling fan speed based on the main regulator actual temperature.
When we have both current and voltage values, is there a reason why they don't control the cooling fan speed based on how much power (in watts) is being drawn from PSU?
AI: As the goal is to not have the heatsinks too hot, it's far easier to measure the temperature of the heatsinks, than to estimate their temperature by measuring the line input voltage, the output current, the air inlet temperature, the mass air flow through the heatsink, and compute a non-linear function for heat transfer versus flow rate. |
H: Cable wires - confirmation of live and ground
I bought a generic DC power extension cable and I'm trying to wire it to a connector with a cable attached. The connectors cable clearly has two wires - a red and black/+ and -. This is what I'm used to, coming from the world of breakout boards and tiny wires. The generic wire, once stripped, however has outer bare wire strands surrounding a sheathed tiny wire:
(I've attached a photo. I've twisted up the outer wire so I could test it with my multimeter). My logical assumption is that the inner sheathed wire is + and the outer is -. Is this correct? I've hooked it up to my solar panel and tested it on my multimeter. It shows 7v when I've got the red wired touching the inner sheathed wire and the black wire touching the outer, and -7v the other way round. I just don't want to connect it up and fry my solar charger board. It's be great if someone could give me a 'yes! you're right!' confirmation please?
AI: Cables don't care which way around you use them. The only difference between a live wire and a ground wire is that one of them is connected to live, and one of them is connected to ground. The electricity doesn't care what colour of wire it's flowing through.
Feel free to use green and yellow wires for 240V. But don't actually do that because the next electrician who sees the cable might electrocute themselves by mistake! For mains electricity, colour codes are there so that people don't electrocute themselves or blow things up by mistake.
Since this is not mains electricity, and you are dealing with only a few volts (nowhere near 120 or 240V) and there is no risk of electrocution, and probably nobody will see it except you, you can use whichever wire you want for whatever purpose you want.
If you are going to have a ground wire, I would suggest using the outer wire for ground. That way, in case the black insulation gets damaged and the wire touches something metal through a hole in the insulation, it has less chance of damaging your circuit. Otherwise, it doesn't matter.
Edit: I missed that your cable already has a connector on one end. In that case, the connector is wired a certain way around. When your multimeter shows a positive voltage, the red lead is touching the positive wire, so in this case, the inner one is positive. |
H: What exactly is meant by beta dependence in this fixed bias BJT scheme?
What I understand that, in a fixed bias BJT scheme the problem is beta dependence.
Below is an example from a text:
Now I read that this is not a good design. But I will still solve this by assuming we have a constant unchanging beta:
So the aim is to obtain around 7.5V(half-rail) at output when there is no small signal input.
I will use beta and write KVL as follows:
I neglect Vbe since it is small relative to the 7.5V; I also take Ie=Ic=100*Ib.
KVL:
Ib * Rb + Ie * Re = 15V or
Ib * Rb + 100 * Ib * Re = 15V
Since we want 7.5V output it means:
Ib * Rb = Ie * Re = 7.5V this yields:
Rb = 100 * Re
Using the KVL equation with this becomes:
Ib * 100 * Re + Ib * 100 * Re = 15V
Re = (15/200) * (1/Ib)
Re = 7.5/Ie
So if we set Ie = 1mA
Re = 7.5k Ohm
Rb = 750k Ohm
Now above assumes beta is known equal to 100 and is fixed and never changes. And I read it is bad design. Now the reason is given as because it is dependent on beta.
But here what is meant by beta dependence? Does that mean two same models have different beta or does that mean beta is changing by time for the same unit?
AI: Rearranging your formulae and using your assumptions:
Rb = (Vcc-Ve) x (Re/Ve) x Beta. -> Rb is proportional to Beta.
and/or, re-rearranging
Ve = (Vcc x Re)/ ( Beta x Rb + Re) <- Ve is Beta dependant.
Beta values for a batch of transistors often differ by 2:1 and sometimes more.
Beta varies with age and temperature.
Your bias resistor and/or your operating point will be "all over the map".
E&OE - even if I made an error there (which I don't think I did) the point is that
the circuit is "undesignable" in real world situations. |
H: Identify a fried capacitor
I am trying to clearly identify a fried ceramic capacitor in order to replace it. By chance, I could take a picture on another device of the same type:
So far what I found after some search:
I suppose that "101 K" is 100 pF +/- 10%.
SL2KV (or is it SL2KY?) might be: dielectric = SL, max voltage = 2kV ?
6D from "9 6 D" might be "2016 december/january" as it is written on some Murata capacitors.
Leads have "outside kinks" and 5 mm spacing. Diameter is around 6 mm.
The problem is that, when searching for this kind of component on Digikey, Farnell or Radiospares, there is either too many choices or not enough. I cannot find, for instance, what is the constructor or if it is single or multilayer.
More detail: I am trying to repair a TV whose stopped working, probably because of a lightning surge. The power supply board is showing 2 fried components: this one and a resistor I could easily identify. I hope by replacing these 2 components that the board will work again.
AI: Its looks like CX or CY typically applied in between L and N or L and gnd or N and gnd. The gnd is the low voltage side of the power supply.
Normally these caps are purposed for electromagnetic noise suppression. They do this by provide very low impedance path for very high frequency harmonic noise so that these noise are diverted away from sensitive electronics.
What is important for you to note when replacing these capacitor are simply the capacitance value (100pF) and their voltage rating (2000V).
For the repairing you are trying to do, pls do check all semiconductor components around the area because most of the time, these will go bad too, especially the high voltage switching IC. |
H: Changing Polygon clearnce in Altium
I need to change the polygon clearance. Here are my setting rules.
But it seems that the lower rule for all clearances is superior to the second one and nothing has been changed. what is my mistake that the first rule is superior?
AI: You can set the priorities of the rules, with that eponymous button down at the bottom of the screen. 1 is the highest. |
H: Coupling capacitors in a CE amplifier
I know that those C2 and C3 are used to isolate DC from the input and output. Capacitors are always open to DC(w=0) and since the equivalent impedance of a capacitor can be expressed as 1/jwc in frequency domain, to get a low impedance(almost short circuit), I think to use a larger capacitance value like 100F. I know in reality 100F is not a so logical value for common capacitors, however, I use LTspice program and it is easy to use a 100F in a simulation. So I enter 100F for the values of C2 and C3. However, when I do that the results get creepy.
The Vout waveform for 100uF C2 and C3 is a nice sinusoidal wave with gain > 300 ( 620 mVpp nice looking sine wave ) .
But for 100F C2 and C3, the result is,
So, why is this the case? Why using a higher capacitance is not a better thing?
p.s : I hope they were called as "coupling" capacitors.
AI: As @glen_geek mentioned in his comment above,
Ah , LTSpice interprets 100F as "100 femto-farads"...a very tiny capacitance. If you substitute 100, LTSpice should interpret that as 100 farads. |
H: What makes LM386 so common at sound amplification
TL, DR at the end.
Preamble: This quesiton results from an analog electronics lab project. However, I am not someone who asks here and wants you to do the job for me. Rather, I have been extensively spending time for this and right now I feel I am stuck. So I wanted to ask for your recommendations
I have been dealing with constructing an audio amplifier for few days. I need this for a project at university. So I CANNOT USE LM386, instead I have to design my amplifier circuit using basic components of electronics(res,cap,bjt,mosfet etc.).
However, while searching on the internet, I saw that LM386 is a very commonly used IC for audio amplification projects. I assume that LM386 is an opAmp in its basics. But I don't know what makes it this much different than other opAmps (such has LM741, another widely used opAmp). So this is the deal, I want to learn which feature of it makes the difference.
My thought:
Since an 8 ohms speaker will be driven at the output, I think it might be the output impedance of LM386 is so low to be able to drive a load as low as 8 ohms speaker. And indeed, when I investigate the LM386 datasheet, in the example applications part, they used speaker symbol as load and the recommended load value is 4 - 32 ohms, which made me to think that they designed LM386 specifically to drive low resistive loads. However, I couldn't find the output impedance value at anywhere in the datasheet for LM386 ( which I also could not find for LM741 an I totaly don't know why they don't include it (?)).
So, question #1 : Is LM386 specially produced to drive speakers, or its capability of doing that is because it is designed to drive low resistance value loads like a speaker?
When I was doing some simulations where an LM741 was used and the 8 ohms load directly connected to its output, the voltage on the 8 ohms load can never exceed 160mV peak levels. And my idea is this happens because of the fact that LM741 has a maximum output current of 20-25 mA.
So, question #2: if I am right and this is the case, can I conclude that LM386 is engineered so that it also will be able to deliver high amount of currents to the load? ( I think that way because for an 8 ohms speaker, 2 W of power ( I guess a normal power rating for a small speaker) will occur at 500 mA, and 0.5 A is much higher than the rating for LM741(25mA) )
In a nutshell, I think you might be understand the situation. I am actualy trying to understand the key factors which make LM386 a better audio application opAmp than LM741(for example). My aim is to understand these and by that, to design my own topologies.
TL, DR: The origin of all these questions in my brain is -> With what kind of an approach, I might be able to drive an 8 ohms speaker effectively at 1-2 W power ratings without using LM386 or the commercial ICs like it.
By the way, I am also open to the advices or recommendations.
Thanks in advance.
AI: Yes, LM386 is designed to supply far more current than most op-amps.
However, LM386 should not be viewed as an op-amp. It is designed to drive low-resistance loads like a speaker, while op-amps have far more applications. LM386 does have differential inputs (inverting and non-inverting). And it does have a single output, like an op amp. But its internal biasing is different from an op-amp. It is designed to set quiescent output voltage mid-way between the supply voltage.
Most often, you'll see LM386 circuits with a single uni-polar supply less than +12V. With a +12V supply, output voltage is very close to +6V DC.
Those differential input pins on LM386 have internal pull-down resistors to the negative supply pin, unlike most op-amps that have open-circuit inputs. With inputs left open-circuit, +in and -in sit very close to the negative supply voltage (usually ground) on a LM386. Done like this, output voltage sits near half-DCsupply.
In summary:
LM386 has low gain between 20 to 200. Op-amp has much higher gain at DC
LM386 self-biases inputs and outputs. Op-amp must be biased by user.
LM386 has much more current available at output. Op-amps generally limit current to +-20mA
Duplicating LM386 with discrete transistors, resistors, capacitors is not a good way to proceed - it is very difficult to match current gain of discrete transistors, and it is very difficult to temperature-track each transistor in the same way that LM386 transistors track on one silicon chip. |
H: What commands in assembly cast value from hexa to decimal when they are called?
how can I know if a command is treating an immediate as a decimal or as a hexadecimal? For e.g div casts the values into decimal before it makes the arithmetic division:
.data
x: .quad 0x16
y: .quad 0x7
z: .space 8
.text
.global main
main:
xor %rax, %rax
xor %rbx, %rbx
xor %rdx, %rdx
movq x, %rax
movq y, %rbx
div %rbx
movq %rax, z
ret
I'm getting those results:
and my guess is that div looks at the decimal value of the number inside a register (cast it from hex to dec) but is it always like that in all arithmetic commands? Are there commands from different type that also act like this? I've tried reading the manual, but it doesn't specified there, I found it out by accident when debugging in sasm.
Thank you very much for your time and attention.
AI: Registers hold numbers, so there is no conversion. It is up to you to think a number in hex or decimal. |
H: Rubber insides and circuit transparent sheets of USB keyboard don't work outside of plastic case
I have very little knowledge of electronics and circuits, so I apologize in advance if the question is dumb. I couldn't find answer anywhere.
I am trying to remove plastic part of my keyboard and have it be only that white rubber part on the inside with those transparent circuit sheets. Reasons are I can't see which letter is where, so I wanted to challenge myself in a weird way and second was that it feels nicer.
I disassembled my keyboard and I saw those pins on microcontroller, and found a datasheet for it. I thought that the microcontroller (on one side green on other brownish board) sends current through that transparrent circuit sheet and checks if there is a pressed key. With that in mind I put the sheets with rubber keys over it on my wooden desk and placed microcontroller over the pins the exact same way as it was in the keyboard. Problem is, it does not work, numlock led diode is still lit on, but it won't change when I press the numlock key.
EDIT
My phone camera died few days ago, so I found few photos online that could better explain it:
I wanted to have these parts inside of keyboard without black plastic around them sitting on my desk.
Questions:
Is it possible for current to go through those circuits if I change black plastic for wooden table?
Do the little pins (on picture bottom left on keyboard) that connect to microcontroller have to be on certain surface or is wood fine for them too?
Desk:
AI: There is usually a clamp to ensure even and firm pressure between the flexible circuit boards (the keyboard matrix) and the keyboard controller PCB edge connector. Just placing them on top of each other is unlikely to work.
You can see some details on a project I did using a keyboard and some footswitches in Soldering on keyboard controller circuit board. I use it for advancing video slide presentations with my feet. |
H: Does driving a speaker with a DC offset AC signal matter?
Do these two input signals have different effects on a speaker?
An AC signal with some value of DC offset.
Same AC signal but centered at 0 V.
AI: Yes.
Figure 1. Cutaway view of a dynamic loudspeaker for the bass register.
1. Magnet,
2. Voicecoil,
3. Suspension,
4. Diaphragm. Source: Wikipedia.
A DC component in the signal will cause:
Bias of the speaker cone (4) and the suspension (3) from the neutral position. This means that the cone will reach the limit of its travel - or at least where it becomes highly non-linear - in one direction in a shorter distance compared with the other.
Maximum undistorted volume will be decreased as a result.
The coil (2) will be heating even when no audio is playing. |
H: Flash programming for a custom design with SAME70
How can I add flash programming capabilities to a custom-design board witg the SAME70 or SAMV71? For example, with the UC3-A3 (AVR32), I just expose TDI, TDO, TCK, TMS, RESET, GND/VDD, and voila: I connect a JTAG programmer and done. This option seems to be unavailable with the SAME70/V71.
What would be the equivalent for these SAM Cortex-M7 microcontrollers? The datasheet is non-explicit at best. I would seem that I need to connect the SWD interface as shown in Figure 60-1 or 60-2 of the SAME70 datasheet. However, every reference to this SWD feature (including the description of the SWD tag in electronics.SE.com !!) mention debug and test only. The evaluation board uses EDBG via USB, but that does not seem like a viable option for a custom design.
Any tips or pointers will be appreciated!
AI: Have a look at the schematic for the SAME70 Xplained PCB. The header marked "JTAG" contains the necessary signals for programming without the secondary CPU.
However, as the fine print in the MCU manual mentions, JTAG functionality is only for factory testing, and the SW-DP is what you would use with something like the JLINK. Image below is from the eval board user manual.
From the MCU datasheet:
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
The JTAG Debug Port TDI, TDO, TMS and TCK is inactive. It is provided for Boundary Scan Manufacturing Test
purpose only. |
H: How to change the led on this board to a brighter led? 12v input
Needed to change these led to brighter led. Is it possible?
If yes then how can it be done?
Noobie!!
AI: Yes, it is almost certainly possible. I'm not sure exactly which part you are asking about.
One way of looking at it is that the brightness of the LEDs will depend mostly on two things:
The efficiency of the LED (in converting electrical power to light).
The power consumed by the LED.
So, you could just replace your LEDs with more efficient ones (without changing anything else in the circuit) and you should get more brightness.
Alternatively, you could change (reduce) the value of a couple of resistors to increase the current flowing through the LEDs. Power = Current x Voltage, and the voltage across an LED is roughly constant, so more current means more power.
For best results, you may need to combine both of these ideas. (Buy some good quality bright LEDs and refer to their data sheet to choose best resistor values).
The big word of warning with both approaches is that you should not allow so much current to flow through the LED as to destroy it. You should check the datasheet of your LED to find this limit (or, if you have no datasheet and lots of LEDs, then test one to destruction to find how much current is too much, then use a bit less than that). |
H: What does that statement exactly mean? ( about dB )
When you separate the collected signals, each car’s channel must
attenuate the other cars’ signals at least by 20 dB.
A speaker will be able to generate a sound which contains 3 different frequency values of sine waves. And also the amplitudes of the sine waves will be tunable, so that at each instant;
A(f1) = 0 (meaning does not exist at that time)
A(f2) = above_threshold ( higher amplitude w.r.t f3 )
A(f3) = below_threshold
Note: The f1,f2,f3 will be change their states for different scenarios.
A means amplitude, f_i correspondes to the sine wave at that frequency.
Then a microphone(seperated by 10 cm from the speaker) should be able to collect this sound, distinguish different frequency components by also indicating their relative amplitudes, because "which of frequency components has higher amplitude which one has lower amplitude and which one is non-existing" is an important information that should be obtained.
This information will be used in a next step of decison mechanism, so I will need DC converted signal levels. To achieve that I plan to amplify signals and then full wave rectify them.
So, relating this part, there is a requirement which is quoted above. Please notice that car's signal means one of the three different frequencies.
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. Block diagram of the system. Because you have only three channels BP (band-pass 0.7 kHz could be replaced with an LP (low-pass) 0.7 kHz filter and PB 1.3 kHz could be replaced by a HP 1.3 kHz filter.
When you separate the collected signals, each car’s channel must attenuate the other cars’ signals at least by 20 dB.
This is telling you that the band-pass filters must attenuate the adjacent frequencies by at least 20 dB or 1/10. So if each band-pass filter gave an output of X Vp-p for its tuned frequency then it would give < X/10 Vp-p for either of the other two frequencies.
To achieve this with such close channel spacing you will have to calculate the attenuation rate required. For example, an attenuation rate of 20 dB/decade on a 1 kHz filter would attenuate by 20 dB at 100 Hz or 10 kHz. Because your channels are so close to each other you will need much steeper attenuation.
Since you are working with sine waves there is no need to full-wave rectify in the peak detection circuits. Half-wave rectification will give you the same accuracy. |
H: PCB Layer Stack Dielectric Constant Math
I have a question reference PCB layer stack and the adding multiple dielectric constants together.
The image and description below should help clarify the question:
The differential pair will be configured in an Edge Coupled External on the top layer, with the signal ground / screen on layer 3.
So the Prepreg (between layer 1 and 2) and the Core (between layer 2 and 3) will form a combined dielectric constant.
I have not included any differential speed as this will be a factor but not important for the question below, more interested in how best to approach the problem which can then be applied to any differential pair in future. Running the ground on layer 2 is not an option in this case, although it would simplify the problem.
Question: What is the best practice in this scenario for calculating the expected dielectric constant; (1) can we treat this like a series capacitor adding the reciprocals of each, (2) do we simple add them together, (3) do we add them and then divide to produce a mean value, (4) or?
AI: Assuming the frequency is so low that the capacitance as whole board size component is meaningful you can well calculate the capasitance per unit area between the two remaining metal layers with the following formula:
$$\frac{C}{A} = \frac{1}{\frac{s_1}{e_1} + \frac{s_2}{e_2}}$$
Where e1 and e2 are absolute permittivities of the dielectric layers, s1 and s2 are their thicknesses. This applies the idea to have 2 capacitors in series. |
H: How to calculate RMS power of an offset sine wave
I know when it is centered at 0, Vpeak/sqrt(2) gives the RMS.
When I do FFT on LTspice, it gives a peak at -17dB which is equal to 0.141254
On the FFT page, program says that it shows RMS values. But, I don't think the RMS of this wave is 0.14 W. You are also welcome to answer for this question involving LTspice.
However, main question is : I actually don't think this question is specific to power calculation, anyway, what is the method to calculate RMS of such sine waves?
AI: You want to know the rms of a waveform \$ f(t) \$.
There are two approaches here direct application of the formula:
$$RMS = \sqrt{\dfrac{1}{T} \cdot \int_0^T (f(t))^2 \text{d}t}$$
Where T is the period of the signal. However there is another useful function:
$$RMS = \sqrt{RMS_1^2 + RMS_2^2}$$
Where \$RMS_1\$ and \$RMS_2\$ are the RMS values two signals that when added together give \$f(t)\$.
This only works provided the two signals do not share any frequency content in common. In this case a sine wave only contains one frequency as does DC (0 Hz which is different) so you can use this formula.
The RMS of a sin wave is \$ \dfrac{\sqrt{2}}{2} \cdot V_{pk} = \dfrac{\sqrt{2}}{4} \cdot V_{pkpk}\$ where \$V_{pkpk}\$ is the peak to peak voltage. The RMS of a DC signal is the same as the DC value. |
H: Attach output to a state in Finite State Machine in VHDL
In my digital electronics class we are currently dealing with Finite-State-Machines and VHDL.
I have written a VHDL-code for finite state machine and I've run into trouble. I want to attach the output to my state, but I don't know how to do it.
For example, I have a state \$S_0\$ where the outputs are \$z_0 =0\$, \$z_1=0\$, \$z_3=0\$.
How do I "attach" that output to \$S_0\$ in terms of VHDL-coding?
Something like: \$S_0: z_0 <=0; z_1<=0; z_2<=0;\$
just gives me: "\$S_0\$ is already defined in this region".
Here is my VHDL-code. I have no idea if what I've written make sense, but hopefully, you can help me?
use IEEE.STD_LOGIC_1164.ALL;
entity Thunderbird is
port( B : in std_logic;
L : in std_logic;
R : in std_logic;
H : in std_logic;
Reset : in std_logic;
Clock : in std_logic;
L0,L1,L2 : out std_logic;
R0,R1,R2 : out std_logic);
end Thunderbird;
architecture Behavioral of Thunderbird is
type state_type is (s00, sH, sB, sR1, sRB1, sR2, sRB2, sR3, sL1, sLB1, sL2, sLB2, sL3, sTB, sRB0, sLB0);
signal current_state, next_state: state_type;
begin
process(all)
begin
if rising_edge(Clock) then
if Reset = '1'
then current_state <= s00;
else
current_state <= next_state;
end if;
end if;
case current_state is
when s00 =>
if H ='1' then next_state <= sH;
elsif
H = '0' and L = '0' and R = '0' and B = '1' then next_state <= sB;
elsif
H = '0' and L = '1' and R = '0' and B = '0' then next_state <= sL1;
elsif
H = '0' and L = '1' and R = '0' and B = '1' then next_state <= sLB1;
elsif
H = '0' and L = '0' and R = '1' and B = '0' then next_state <= sR1;
elsif
H = '0' and L = '0' and R = '1' and B = '1' then next_state <= sRB1;
end if;
when sH =>
next_state <= s00;
when sB =>
if H = '0' and L = '0' and R = '0' and B = '0' then next_state <= s00;
elsif
H = '1' then next_state <= sH;
elsif
H = '0' and L = '0' and R = '1' and B = '1' then next_state <=sRB1;
elsif
H = '0' and L = '1' and R = '0' and B = '1' then next_state <=sLB1;
elsif
H = '0' and L = '1' and R = '0' and B = '0' then next_state <=sL1;
elsif
H = '0' and L = '0' and R = '1' and B = '0' then next_state <= sR1;
end if;
when sR1 =>
if H = '0' and B = '0' then next_state <=sR2;
elsif
H = '0' and B = '1' then next_state <= sRB2;
elsif
H = '1' then next_state <= sH;
end if;
when sR2 =>
if H = '0' and B = '0' then next_state <= sR3;
elsif
H = '0' and B = '1' then next_state <= sTB;
elsif
H = '1' then next_state <= sH;
end if;
when sR3 =>
if H = '0' and B = '0' then next_state <= s00;
elsif
H = '0' and B = '1' then next_state <= sRB0;
elsif
H = '1' then next_state <= sH;
end if;
when sRB1 =>
if H = '0' and B = '0' then next_state <= sR2;
elsif
H = '0' and B = '1' then next_state <= sRB2;
elsif
H = '1' then next_state <= sH;
end if;
when sRB2 =>
if H = '0' and B = '0' then next_state <= sR3;
elsif
H = '0' and B = '1' then next_state <= sTB;
elsif
H = '1' then next_state <= sH;
end if;
when sL1 =>
if H = '0' and B = '0' then next_state <=sL2;
elsif
H = '0' and B = '1' then next_state <= sLB2;
elsif
H = '1' then next_state <= sH;
end if;
when sL2 =>
if H = '0' and B = '0' then next_state <= sL3;
elsif
H = '0' and L = '0' and R = '0' and B = '1' then next_state <= sTB;
elsif
H = '1' then next_state <= sH;
end if;
when sL3 =>
if H = '0' and B = '0' then next_state <= s00;
elsif
H = '0' and B = '1' then next_state <= sLB0;
elsif
H = '1' then next_state <= sH;
end if;
when sRB0 =>
if H = '1' then next_state <= sH;
elsif
H = '0' and L = '0' and R = '0' and B = '1' then next_state <= sB;
elsif
H = '0' and L = '1' and R = '0' and B = '0' then next_state <= sL1;
elsif
H = '0' and L = '1' and R = '0' and B = '1' then next_state <= sLB1;
elsif
H = '0' and L = '0' and R = '1' and B = '0' then next_state <= sR1;
elsif
H = '0' and L = '0' and R = '1' and B = '1' then next_state <= sRB1;
end if;
when sLB0 =>
if H = '1' then next_state <= sH;
elsif
H = '0' and L = '0' and R = '0' and B = '1' then next_state <= sB;
elsif
H = '0' and L = '1' and R = '0' and B = '0' then next_state <= sL1;
elsif
H = '0' and L = '1' and R = '0' and B = '1' then next_state <= sLB1;
elsif
H = '0' and L = '0' and R = '1' and B = '0' then next_state <= sR1;
elsif
H = '0' and L = '0' and R = '1'and B = '1' then next_state <= sRB1;
end if;
when sLB1 =>
if H = '0' and B = '0' then next_state <= sL2;
elsif
H = '0' and B = '1' then next_state <= sLB2;
elsif
H = '1' then next_state <= sH;
end if;
when sLB2 =>
if H = '0' and B = '0' then next_state <= sL3;
elsif
H = '0' and B = '1' then next_state <= sTB;
elsif
H = '1' then next_state <= sH;
end if;
when sTB =>
if H = '0' and B = '0' then next_state <= s00;
elsif
H = '0' and B = '1' then next_state <= sB;
elsif
H = '1' then next_state <= sH;
end if;
end case;
end process;
end Behavioral;
AI: For writing concurrent code (outside of a clocked process), try this:
z0 <= '0' when (current_state = s00) else
'1' when (current_state = sh) else
'0'; --when others
z1 <= '0' when (current_state = s00) else
'0' when (current_state = sh) else
'1'; --when others
make sure that the last selection doesn't have a "when (...)" or else you will produce inferred latches (bad). Another way to do this would be to assign z0,z1, etc directly at the same location you are assigning next_state to current state:
if (next_state = s00) then
z0 <= '0';
z1 <= '0';
elsif (next_state = sh) then
z0 <= '1';
z1 <= '0';
else
z0 <= '0';
z1 <= '1';
end if;
Either make a signal named "z0" and "z1" in your architecture declaration section (and then drive the appropriate output), or add "z0" and "z1" as an output port to your module. |
H: Which are the physical factors that determine the maximum transportable resolution of a cable (for instance: HDMI)?
Which are the physical and electrical factors that determine that an old generation HDMI can transport for instance 1080p resolution, while a new HDMI (2.0) arrives at 4k?
Is it due to a different attenuation of the cable, to a different communication protocol etc?
AI: It basically comes down to the standards that define speeds, and devices that need to use these speeds. ICs then need to be designed to work at these speeds, and the transmission lines (cables) need to be able to pass that signal adequately. As there is need for faster speeds, also the technology used to make chips work at these speeds have advanced, such as automatic receiver equalization or pre-emphasis at the transmitter.
At some point HDMI supported up to 6.7 Gbit/s rate to support 1080p with 36-bit colors, so nothing faster existed. Then that increased to 9 Gbit/s when first 4K resolutions were defined in HDMI and devices started using those resolutions so better chips were needed. Next version of standard supported up to 18 Gbit/s to allow more bit depth and refresh rates, and also defines a standard for a cable to pass this, so again new chips to support this were needed. Same thing with next version again.
Communication protocol has so far remained basically the same, it is just faster. Cables need to be good enough to work with this, so longer cables need to be better quality than shorter cables, as long as they don't attenuate signal more than what standard requires, regardless of their length. |
H: Phase Lead and phase Lag
I find the concept of phase lag and and lead quite confusing.
Suppose we have two voltages
\$V(\theta) = V_{max} \cdot \sin(\theta + 30^o)\$
and
\$V(\theta) = V_{max} \cdot \sin(\theta + 60^o)\$
If frequency and maximum voltages are same
then according to the definition
"The leading alternating quantity is one which reaches it maximum or zero value earlier than the other quantity."
\$V(\theta) = V_{max} \cdot \sin(\theta + 60^o)\$ is leading the \$V(\theta) = V_{max} \cdot \sin(\theta + 30^o)\$ by 30 degree.
But what if we compare
\$V(\theta) = V_{max} \cdot \sin(\theta + 89^o)\$ and \$V(\theta) = V_{max}\cdot \sin(\theta + 120^o)\$ ?
Then which one is leading ?
For example if \$ \theta\$ is 1 degree then \$V(\theta) = V_{max} \cdot \sin(1^o + 89^o) = V(\theta) = V_{max} \cdot \sin(90^o)\$
and \$V(\theta) = V_{max} \cdot \sin(1^o + 120^o)\$ is \$V(\theta) = V_{max} \cdot \sin(121^o)\$
so it means that \$V_{max} \cdot \sin(\theta + 89^o)\$ is leading the \$V_{max}\cdot \sin(\theta + 120^o)\$ because \$89^o\$ reaches its maximum value earlier than \$120^o\$ ?
While on the other had \$120^o\$ is greater than \$89^o\$ in phase. So what is the case ? Which one of them is leading ?
AI: The start time is arbitrary. What matters is the difference between the waveforms. \$\theta + 120\$ is 31 degrees ahead of \$\theta + 89\$ and always will be.
The second example in the question is considering a time when the +120 eave has just passed the point of interest, so the next to reach it is the +89 wave. But the +120 had already reached it in this example: it’s clearly leading.
Note that leading by more than a half cycle, I.e. 270 degrees which is more than 180 and geometrically equivalent to -90, is considered to be lagging by convention. |
H: Pads reflecting in controlled impedance strip?
Background
I'm designing a controlled impedance line for a 1900MHz signal travelling between SIM7000A cellular chip and an antenna.
Question
Tuning circuits are recommended for antennas with series and shunt passives to correct their impedance to 50 ohms by using a Smith chart. These are soldered to pads on the PCB (obviously). When the signal transitions from the controlled impedance copper trace to the pads the tuning components are mounted onto wouldn't it be reflected? How can we assume the characteristic impedance of a pad is 50 ohms?
AI: How can we assume the characteristic impedance of a pad is 50 ohms?
You can't.
There's a similar issue whenever you connect a component to an impedance controlled trace. Whether it's an antenna, a filter, a simple DC-blocking capacitor, or the actual IC pad the trace connects to.
When the signal transitions from the controlled impedance copper trace to the pads the tuning components are mounted onto wouldn't it be reflected?
If the pad is wider than the track, it will be a capacitive disocontinuity in the track. If your matching network has a capacitor to (AC) ground at this point, then no big deal, you just account for the pad capacitance when choosing your added discrete capacitor.
If the pad size isn't too much more than the track, and your matching requirements are not too strict, possibly you can just ignore the small capacitance.
If you have stricter requirements, the capacitance provided by the pad might be ameliorated by removing (some of) the ground plane beneath the pad.
Or by increasing an inductive element in the matching network.
So, short answer: yes, there's likely a discontinuity due to the pad. How you deal with it depends on your requirements, the kind of circuit you're working with, and what freedoms you have to change the layout. |
H: Considering the power dissipation of a transistor
These two waveforms are the power dissipation vs time graphs on two bjts (npn and pnp). I got these using LTspice ( alt + right click on the bjts ).
The thing is, while considering will my transistors be able to dissipate those powers without burning themselves, which value of the powers should I use? For example they peak around 3 W, however their average is (ctrl + letf click on the label) shown as around 1W. So, can I consider this 3 W peak as too short to damage the transistors?
transistors are : 2n2222 and 2n2907
AI: The thing is, while considering will my transistors be able to dissipate those powers without burning themselves, which value of the powers should I use?
Before considering Safe Operating Area and transient thermal impedance, first look at average power, here it is 1W. If average power is enough to make the smoke come out, there's no need to check the other conditions.
Check transistor datasheet, it specifies maximum disipated power of 1.2W at Tc=25°C.
"Maximum dissipated power" as specified in a datasheet is not exactly what it says, because it implies that the case is cooled by a perfect heatsink of infinite size which magically holds the case at 25°C. This ain't gonna happen in the real world. Unless maybe you dip it in liquid HCFC coolant or something.
"Maximum dissipated power" is useful for comparing transistors, but it doesn't tell you how much your transistor will be able to ... dissipate ... in real world conditions, with a real heat sink, inside an enclosure that may be hot, maybe with low airflow, dust, cat hair clogging the vents, etc.
In this case, your problem is that 2N2222 is a low-power transistor, which means its silicon chip is quite small, so it will have a small contact area to the metal case, and the case is also small and not designed to transfer heat efficiently. This explains the enormous ThetaJC, or Thermal Resistance Junction To Case, of 97°C/W. This means with one watt average the chip will be 97°C hotter than the case. And you won't be able to keep the case at 25°C, so your transistor will burn.
This huge ThetaJC comes from the way the TO18 package is constructed. Consider the long and complicated path heat has to travel to get from the chip to the case... This is a very old package...
So you need a transistor with better heat transfer between the chip and the case. For example, a SOT89.
In this package, the chip is mounted on the large copper slug in the middle, which is directly exposed, so you get a "Thermal Resistance, Junction to Leads" of about 5-10 °C/W, which is way better than 97°C/W. You still have to cool the center lead by using PCB copper area as a heat sink, but at least if you keep it cool, the chip will not be 100°C hotter than the leads as in the 2N2222 case. It will only be 5-10°C hotter than the center lead if it dissipates 1W. This is how, with proper heat sinking, a tiny SMD package can safely dissipate a lot more power than a TO18.
If you make a push-pull emitter follower with your transistors, the center pad will be the collector, that is the supply voltages, which is nice because you can add copper area for cooling.
Likewise TO220 has good thermal resistance junction to case because the chip is soldered on a copper slug, and heat travels through in the correct direction (depth-wise through a large cross-section area of copper) and not in the bad direction (lengthwise through a thin metal plate).
In your case, for your average power, I'd go with SOT89 transistors in SMD if space is tight, but that would be pushing it a bit. Most likely DPAK. If you want to prototype it, use TO220 or TO126 transistors and a small heatsink. Even a very small clip-on heatsink will do. Or a TO220 with no heatsink at all, but you will burn your fingers. When prototyping, it is always nice to not burn fingers.
The important thing to remember is that temperature difference between case (or heatsink) and air helps cooling because it moves air by convection. However, temperature difference between chip and case does not help at all, it is a part of your thermal budget that you spend but it does not help cooling. This is why manufacturers optimize packages for low RthJC.
Once you have picked a transistor and package that can safely handle the average power, then you will have to check safe operating area and transient thermal impedance. |
H: Detecting short circuit (max4080)
I'm using Max4080 to measure the current:
simulate this circuit – Schematic created using CircuitLab
The problem is it can't detect short circuit because when RS- is connected to ground, Rsense will be at low-side. Max4080 is a high-side current measurement chip...
Is there anyway at all to make this chip to detect short circuit(with extra circuitry)?
Can I use this chip to measure the current and then detect the short circuit with something like this?
I know measuring current at low-side is easy and I'll eventually going to use it if I can't find a solution(easy/cheap/accessible) to measure the current at high-side.
AI: From the linked datasheet, the output is valid when the common mode of RS+/- is 4.5-76 V. You will be able to measure current accurately until your 15 V / 1 A supply is forced below 4.5 V output by its overcurrent protection. What are you trying to use short circuit detection for? If you want to protect the power supply, you will need additional circuitry. If you want to know the power supply status and its self-protection is adequate for your application, can you get that as a feature of the supply? |
H: Balanced impedance CM and DM stages EMI Filtering
Here is the following assertion :
I would like to understand why line impedance imbalance can cause CM noise to get converted into DM noise ?
Thank you very much !
AI: Think of a DC voltage source with two equal resistors R1 and R2 connected at its + and - Terminals and a load resistor RL connecting R1 and R2.
The voltage source is the common mode signal (or CM noise).
Now if you slightly change R1 or R2, the load resistor RL will get a different voltage despite the fact that you did not change the common mode DC voltage source. |
H: STM8L151 UART software
I am new in STM programming and I want to do a simple UART communication but I don't know where to start.Can somebody send a tutorial for stm8l or a full code would be better so I can examine it.
Thx.
Schematics :
AI: I am not familiar with STM8, but with STM32 there is STM32CubeMX, where you can configure your code and find examples. It seems that there is version for STM8 too.
Once you download it, it should have some examples (they should be in STM8Cube folder in C:/Users/your user, if it is similar to STM32CubeMX) and you would be able to generate your starting code, it should be similar as for STM32CubeMX, which has a lot of tutorials in the internet. |
H: Confusing regarding sub domains of main specializations EE?
I want to apply for masters program in Hungary in EE
As shown attached snapshot, there are listed 3 secondary specializations:
Smart city
Smart systems integration
Optical Communication
I know that subject number 3 (Optical Communication) is secondary specialization of Main specialization (Multimedia Systems and Services)
But i am confused regarding the remaining two secondary specializations(smart city and smart systems integration), regarding to which main specialization (Electric power systems or embedded systems) they both belong/refer to?
AI: The last line of the first complete paragraph of the snapshot says "Any main specialization can be combined with any secondary specialization." That seems to support what Dave Tweed said in his comment. Systems integration and optical communication are important aspects of many engineering specializations. "Smart City" likely refers to EE applied to the infrastructure of the modern urban environment. All of the main specializations listed would be applicable in that context. |
H: KiCad Simulation VSOURCE Triangle waveform
I want to simulate a second order active low-pass filter in KiCad, using the internal spice-based simulation tool. The input signal must be a triangle waveform of 30kHz and 0,5 V peak to peak, and the problem is I can't find any tutorial, on how to create a triangle waveform using the VSOURCE (Can't find the right settings). I know that I can build a triangle wave generator circuit using an op-amp, but I don't want to do that yet. Any ideas?
Thanks
AI: I might try the following settings: |
H: Can I charge a lipo battery using piezoeletric energy harvesting?
I use a 9V 800mAh lipo Okcell battery to power my ESP8266 ESP-01 with a voltage regulator to change it to 3.3V. I use the ESP to detect the voltage peak from a piezoelectric when someone is running to measure the force and determine the time someone on air from the voltage graph.
The current consumption of my ESP8266 is about 75mA. From my understanding the battery can power my ESP8266 for about 8 hours because of the 20% power loss from the voltage regulator.
So for my project, can I use the piezoelectric to power my battery while im not using it. The piezoelectric I'm using is PZT type. I want to a use a force amplification frame for the piezoelectric so I use ANSYS simulation to simulate it.
Of course the data is not 100% correct but I still cannot measure the voltage and current generated from the piezoelectric as I still did not fabricate it yet.
So is there any way to use the piezoelectric to power the battery theoretically speaking. It doesn't matter if it will take 1000 hours or not, my supervisor just want to know if it still can do.
AI: In principle, any source of voltage/current can be used to provide power. In the case of piezoelectrics, the devil is in the details: PZTs simply don't produce much.
Especially in this case, you are looking at a losing cause. Consider that your esp8266 draws 75 mA at 3.3 volts, or 247 mW. Meanwhile, according to your illustration, the PZT produces 5.36 mW. I'm sure you see the problem.
If you were to make a dedicated micropower controller, you could produce a unit which transforms the high-voltage/low current PZT output to a usable level. The controller would turn off the 8266 most of the time, and direct the transformed PZT output to a battery charger. At regular intervals, the controller would turn the 8266 on and allow it to make a measurement, then turn it off again. You would, of course, need to account for the power draw of the controller, but dedicated simple logic can be built in CMOS with very low power draw.
In the best possible case, the duty cycle of the 8266 would be about 5.36/247, or about 2%. This would assume perfect efficiency both in the transformation/charging process, and in the 3.3 regulator. And you won't get that in either case. Regulators can operate in the 90% efficiency range if you know what you're doing, but battery charging is notoriously inefficient, especially as you approach full charge. I'd estimate that you might hope for something on the order of a factor of 5 - 10 worse than the ideal. |
H: Computation of the Scattering Matrix of a Transmission Line
let's consider this transmission line (with losses) in which a and b denote respectively the reflected and the incident waves at each port:
This exercise asks to find its scattering parameters normalized with respect to an arbitrary impedance Zc1, which is different from Zc.
It starts with the computation of S12 and S22: in this case, according to the Scattering Parameters' definitions, we have to analyze the network in case a1 = 0 (i.e. port 1 adapted) and with a source applied to port 2. The exercise so analyzes this situation:
What I do not understand is this: why is port 1 closed on Zc1 and not to Zc? The exercise asks to find S-matrix normalized with respect to Zc1, but if we close port 1 on Zc1, it will be non true that a1 = 0, from my point of view. In fact, there will be physically reflection, since there is an impedance mismatch between the load Zc1 and the transmission line which has characteristic impedance Zc. How can this procedure be correct?
AI: why is port 1 closed on Zc1 and not to Zc?
Because in the problem statement you specifically said you wanted, "scattering parameters normalized with respect to an arbitrary impedance Zc1, which is different from Zc".
To test (or simulate) the scattering parameters of a network normalized to an impedance \$Z_{c1}\$, you terminate it with the impedance \$Z_{c1}\$.
if we close port 1 on Zc1, it will be non true that a1 = 0, from my point of view. In fact, there will be physically reflection, since there is an impedance mismatch between the load Zc1 and the transmission line which has characteristic impedance Zc.
You are correct there will be a reflection there. But this reflection is only within the transmission line being tested (the DUT), so it is not considered as part of the wave \$a_1\$.
Imagine you replaced the termination \$Z_{c1}\$ with a length of transmission line of characteristic impedance \$Z_{c1}\$, and terminated that with the impedance \$Z_{c1}\$. As far as the behavior of your DUT is concerned, this would not change anything. But it would be clear that there is no forward travelling wave \$a_1\$ in this transmission line. The reflection is entirely within the DUT, not in the termination. |
H: LTspice a voltage source as a function of time
I saw the ability to control R by time in someone's drawing, tried it, and it worked fine. Then, I thought that I could use that "time" keyword also to control the voltage of a DC source. However it didn't work. It gives an error:
Error on line 2 : vcc n001 0 time*2
Unknown parameter "time*2"
Vcc: Missing value, assumed 0V @ DC
.OP point found by inspection.
So, is there an easy way, as easy as it is with the resistor value, to do what I want?
AI: The problem is you try to make an alterating voltage source with a DC source.
Use Arbitrary behavioral voltage source (BV) instead.
You don't need curly braces for that, just V=time*10m |
H: Correct Polarization of Common Source Amplifiers
I was reading a book about amplifiers and I have read the following sentence about the following picture:
The idea-guide is that we must access simultaneously to the Gate terminal and to the Source terminal of a transistor so that we can command it to produce a controlled current, as shown in the previous picture.
But from a practical point of view, access to those two points requires some caution in order, for example, not to alter the polarization of the transistor: in fact we could not directly connect two ideal voltage generators referred to ground to the two terminals of the transistors shown above. We should necessarily think of a coupling in AC, at least for one of the two inputs (though this is not always possible, in particular in an integrated circuit where the realization of high value capacitors is practically impossible).
First question: can you explain me the highlighted sentences? I do not understand which is the problem: I have always seen Common - Source configurations with only a voltage source with its positive terminal connected to the Gate and its negative terminal (often GND) connected to the Source. I have never seen two voltage sources connected as it says; but also if I decide to do this, I do not see any problem).
Then it continues in this way
Note that the two inputs have different DC voltage and different impedance shown on signal. Both of these situations are uncomfortable in application practice.
Second question: why?
Then it says:
To overcome these obstacles we could think of accessing one of the two terminals of the transistor via a follower stage. The following circuit has the beneficial effect, as it is easy to verify, to bring the two inputs, Va and Vb, of the new system to the same DC value.
The solution of adding a follower to the simple initial transistor is actually correct and effective. This configuration of transistors is typical of the input stage of operational amplifiers (OpAmp) and is usually called "differential stage". In fact, the input impedances of the two terminals have been matched to a high value (in the case of even infinite MOSFETs), making this stage ideal when both voltage signals are to be read. Note how in this case, thanks to symmetry, the follower is lost and who is the signal transistor.
Third question: can you explain me how does it work in simple words?
AI: The author of the book tries to reveal the "philosophy" behind the transistor differential amplifier (aka long-tailed pair) by building the circuit... and not by giving the ultimate perfect circuit solution... which deserves our respect. Here is what this "building scenario" would look like briefly:
We can drive a (FET) transistor from the side of the gate (common-source amplifier), from the side of the source (common-gate amplifier)... or from both (differential amplifier). So the bare transistor is itself a differential amplifier with two inputs - inverting (the gate) and non-inverting (the source). Then let's apply the two (grounded) input voltages VA and VB respectively to its gate and source.
The problem of this "1-transistor differential amplifier" is that the input sources do not work under the same load conditions - VA is practically unloaded (it "sees" the extremely high input impedance of the gate) while VB is significantly loaded (it "sees" the very low output impedance of the source)... ie, the trouble is in the non-inverting input (the source). Then let's help it.
If we connect a(nother) source follower (acting as a buffer) between the VB input voltage source and the source, we will "alleviate the suffering" of VB and put it under the same conditions as VA. Thus both they will "see" the same input impedance. |
H: Is this DIN connector suited for MIDI devices?
I'm having difficulties to find PCB mount "MIDI" connectors by a supplier like Farnell, no search with the keyword "MIDI" succeeds. I know a MIDI connector is a DIN5 connector, but there seems to be many variations of "DIN5".
For example, do you think that a product like this is suited for standard MIDI cables (for electronic music devices)?
The image looks ok but I wonder if the "angle" of each "line hole"/pin is not a little bit different than usual MIDI devices...
Here is the datasheet.
Here is a connector that I know working for MIDI, I wonder if the one I linked is similar.
Edit: The angle of the "linear holes" seems to be very different from one item to another. Why? By the way, why is it a "linear hole" and not just a round hole like all other connectors?
Linked to 5-pin DIN socket advertised as MIDI, not the same as on my MIDI gear but not a duplicate since here I have a more precise question about the angle of the linear holes (not present in the other question).
AI: While one might expect that the socket's contacts would be a round metal receptacle, there is another design that looks like a fork. The two extensions of the fork make contact with the plug's pins by contacting the pin on either side. This fork-contact has a flat profile, and during manufacture, it is inserted into the slot that you see as a "line". The sides of the fork also flex inside this slot in order to provide a spring-loaded contact with the pin from the plug.
So these "lines" (slots), and the angle they are made at, have nothing to do with the pin arrangement in the socket. Only the round hole where the pin actually enters is a factor in whether the "pins are in the right place". |
H: Capacitor Maximum Frequency of Operation
The correct answer is 760kHz.
My Solution is:
First find self-resonant capacitor frequency.
Self-Resonant Frequency = 1/(2pi*sqrt(LC)) = 758kHz.
From our second condition, we have that the capacitor must be operated less tahn 75.8kHz.
Capacitor Impedance 1/(2*pifC) > 10r, this leads to f < 72kHz.
Thus, I take the lower of these two conditions. Hence, my answer is 72kHz. What am I doing wrong?
AI: You followed all the instructions and got the correct answer that they requested.
But the question has false assumptions.
The cap is very good and is low Q ~1. Thus there is no significant resonance at the crossover frequency when the magnitude of impedance for L=C. This means the impedance 1 decade above is about the same as 1 decade down is still useful .
Of course if you are using this cap. with a Buck Converter then the effects of the series inductor and interference with the loop filter spectrum must be simulated to avoid stability issue .
Here SRF of 25kHz with a Q of 22 dB into a 10 Ohm load @ for a Buck SMPS perhaps operating much higher than 25kHz yet has good attenuation higher above this. |
H: Computer power supplies usually have higher efficiency on 230V than on 115V. Why?
As seen here in the example, this particular power supply (and most others too) has higher efficiency when running on 230V. Given that computer power supplies are usually required to output a combination of 12V, 5V, and 3.3V DC, why is it that stepping down from a higher AC voltage is more efficient? It seems counter-intuitive.
Also is this a result intrinsic to the process of converting AC to DC, or is it a compromise that manufactures settle with for compatibility? In other words, if someone is to build a power supply that only works on 115V, is it more difficult to achieve the same efficiency as one built only for 230V?
AI: As the law \$ P = U * I\$ , to acheive the same power at lower voltage, you need to increase the current.
In resistive components, like wires, pcb traces, transformer wire (green), losses increase to the square of the current, as \$P(loss) = R * I ^ 2\$.
In switching components and other diodes/rectifiers, (Green) the losses equal to \$ P(loss) = V(bandgap) * I \$.
V is bound to the component regardless of the voltage input, like ~1V for a rectifier.
Eddy currents losses (Red) will also increase in any core as the current (and thus electromagnetic field) increases.
Losses related to capacitor leakage are negligible. |
H: How can I estimate the minimum beta for this driver to work in hard saturation?
Imagine I build the below LED driver circuit where I know all the component parameters such as 2V LED forward drop and resistors and Vcc and Vbb as in the following diagram:
And if I only dont know the beta of the NPN transistor; how can we estimate the required minimum beta for hard saturation?
In hard saturation Vce will be zero? So Ic= 9mA.
Ib = 0.9mA.
Does that mean a beta of 10 suffice for hard saturation??
AI: Let's start with your circuit and play around with it a little bit. Beforehand, let's create a "model" for the LED. Not a complex one. Just a really simple one. But one that is complicated enough to highlight a few ideas.
Suppose that the LED voltage is: \$V_\text{LED}=1.8\:\text{V}+I_\text{LED}\cdot 20\:\Omega\$. The idea here is that \$I_\text{LED}=0\:\text{mA}\$ when \$V_\text{LED}\le 1.8\:\text{V}\$ and that \$V_\text{LED}=2.0\:\text{V}\$ when \$I_\text{LED}=10\:\text{mA}\$, etc. This is a simple, but not overly-simplistic model for an LED operating near its designated operating current. I'm creating this model for you because of what's coming ahead. So bear with me.
Now, let's take your circuit with two resistors and discuss it in several circumstances:
simulate this circuit – Schematic created using CircuitLab
The first two on the left are saturated. The reason is that the collector resistor is large enough to cause a sufficient voltage drop, together with the LED drop, to force the collector voltage to its VCE(sat) value. When that happens, the collector resistor determines the LED current.
I wanted to create a slightly more complicated LED model above, because I didn't want to make this too easy for you. Let's take the left-most case. An overly simple calculation using \$V_\text{LED}=2.0\:\text{V}\$ would suggest that \$I_\text{LED}=\frac{15\:\text{V}-2\:\text{V}-200\:\text{mV}}{1.5\:\text{k}\Omega}\approx 8.53\:\text{mA}\$. But the fact is, the LED voltage will be a little less than expected because of its model. And because \$V_\text{LED}\lt 2.0\:\text{V}\$, we can expect slightly more current. But still, \$R_2\$ does limit the current in the LED in the left-most example.
How do we know that the left-most circuit is saturated? We know because \$\beta=100\$ in active mode. But this would suggest a collector current of \$95\:\text{mA}\$ and that would cause \$R_2\$ to drop \$142.5\:\text{V}\$. We know this is impossible! So the BJT must be saturated.
Next towards the right is still a circuit that is saturated. Again, a simple calculation would suggest (if it weren't saturated) that the voltage drop across \$R_2\$ would be \$20.9\:\text{V}\$. And again, we know that's impossible. So the circuit must be saturated. A simplistic estimate of the current (without the fancy LED model mentioned above) would be \$I_\text{LED}=\frac{15\:\text{V}-2\:\text{V}-200\:\text{mV}}{220\:\Omega}\approx 58.2\:\text{mA}\$. But because the LED is dropping not quite \$3\:\text{V}\$ (using our fancier model), we find that the actual current is slightly less (as shown in the schematic.) Still, \$R_2\$ does closely limit the current in the LED.
In the 3rd case from the left (2nd from the right), we are no longer saturated. Now, we are limited by \$\beta=100\$ for the BJT's active mode. We can easily tell by noting that the voltage drop across \$R_2\$ using the maximum \$\beta=100\$ provides a voltage drop of \$9.5\:\text{V}\$. The LED itself drops \$3.7\:\text{V}\$. So the collector voltage is \$1.8\:\text{V}\$, which is definitely not a saturated collector voltage here. This means we can use \$\beta=100\$ for the calculations, since that's the maximum \$\beta\$ for this BJT. What's limiting the current in the LED now is the BJT's \$\beta\$. No longer is \$R_2\$ playing any part in it.
The 4th case (right-most) is similar. I've just further lowered \$R_2\$ to make the point still more obvious. The current in the LED is still limited by the BJT's \$\beta\$.
Note that in the last two cases (the right-most two cases), the current in the LED depends upon the BJT's active mode \$\beta\$. Since this varies from BJT to BJT, these two right-most circuits are not managed well. The LED current will depend a great deal on the specific BJT, it's temperature, etc. So these are not "good" switch circuits.
Note also that the 2nd from the left schematic is pretty close to active mode. It's still saturated. But it's getting close to the maximum allowed by the active mode \$\beta\$ of the BJT. \$\beta=\frac{54.2\:\text{mA}}{950\:\mu\text{A}}\approx 57\$. The value of \$R_2\$ is still performing its "current limiting" function, but it's getting too close to not performing that function.
This is why the left-most circuit is considered better. Here, \$\beta=9\$ (go ahead and check.) And this design is very safe because it's a long ways away from entering into active mode. Note also that the simplified calculation for the LED current is closer here than it is in the circuit that is 2nd from the left, despite the fact that it is still a saturated circuit.
Pushing \$\beta\$ lower is usually good, when operating the BJT as a switch, because it keeps you further away from active mode. The further away you are, the better. But of course, you also have to keep in mind how much extra base current is being wasted (which adds to power, as well.) So there is always a "balancing act" here. Where exactly you decide to strike that balance is your choice. |
H: Voltage across tape recorders
Here there's a question that I'd like to double check with you lot.
According to an article on impedance, the voltage across each of the tape recorders in the image is divided by two. Is that so?
Thanks for your time!
AI: The author of that article seems to be confused. The caption says:-
Figure 2. In a matched-impedance system working to the 600 ohm
standard, connecting two tape machine inputs to the same console
output would cause a level drop of 6dB, because each of the two
parallel 600 ohm loads only receives half the signal power.
6dB drop is incorrect, but so is 3dB (half power). It is actually about 3.5dB, ie. slightly less than half power.
We can prove this by examining the equivalent circuits:-
simulate this circuit – Schematic created using CircuitLab
R1 and R3 represent the output impedance of the source, and the other resistors are the loads.
In the first case the signal voltage splits equally between source and load resistors, 1/2 across each causing a 6dB drop. However the source's internal voltage has been set 6dB higher to produce a reading of 0dBVU (at 0.5V in this example) on the load's VU meter.
In the second case with two loads in parallel the total load impedance is 300Ω. Voltage still splits proportionally to the resistances, now 2/3 across the source and 1/3 across the loads (= 2/3 of 1/2). As the total resistance seen by the source is now 900Ω instead of 1200Ω, the current it has to deliver increases by 1/3. This current splits equally between the two loads, so each gets 2/3 of the current of the single termination.
Power = voltage x current, so with 2/3 the voltage and 2/3 the current the power is 4/9 times as much. Decibels are 10xlog10(power ratio), so 4/9 = ~-3.5dB. |
H: STM32F0 SPI--what am I missing?
I'm trying to send SPI data to a MAX7219 from an STM32F042 (the protocol is one-way without MISO). I must be missing something very obvious. With the code below, the only visible side effect is the GPIO nCS line wiggling. Neither clock nor MOSI show any activity.
What am I missing?
#include "stm32f0xx.h"
int main(void)
{
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
// SCK
GPIOB->MODER |= GPIO_MODER_MODER3_1; // alternate function
// GPIOB->OTYPER default push-pull
// GPIOB->AFR[] default AF 0: SPI1_SCK,
// MOSI
GPIOB->MODER |= GPIO_MODER_MODER5_1; // alternate function
// soft nCS
GPIOB->MODER |= GPIO_MODER_MODER4_0; // GPO
GPIOB->ODR = GPIO_ODR_4; // deselect
// SPI configuration
SPI1->CR1 |= SPI_CR1_MSTR; // master mode
SPI1->CR1 |= SPI_CR1_BR_1; // spi_sck = SystemCoreClock / 8 = 6 MHz
SPI1->CR1 |= SPI_CR1_SSI; // software CS
SPI1->CR2 |= SPI_CR2_DS_3 | SPI_CR2_DS_2 |
SPI_CR2_DS_1 | SPI_CR2_DS_0; // 16 bit format
SPI1->CR1 |= SPI_CR1_SPE; // SPI Enable
// transmit test packet
while(!(SPI1->SR & SPI_SR_TXE)); // make sure TX buffer is empty
while(SPI1->SR & SPI_SR_BSY); // make sure SPI isn't busy
GPIOB->ODR &= ~GPIO_ODR_4; // chip select
uint16_t data = 0xAAAA; // test packet
SPI1->DR = data;
while(!(SPI1->SR & SPI_SR_TXE)); // make sure TX buffer is empty
while(SPI1->SR & SPI_SR_BSY); // make sure SPI isn't busy
GPIOB->ODR |= GPIO_ODR_4; // deselect
while(1);
}
AI: Enable SPI_CR1_SSM.
The output now remains high-z since chip select is low.
Aside from clock setup and gpio, this is minimal init for SPI:
SPI2->CR1 |= SPI_CR1_SSM;
SPI2->CR1 |= SPI_CR1_SSI;
SPI2->CR1 |= SPI_CR1_MSTR | SPI_CR1_SPE; |
H: Improving the classic 18V mod for guitars
I am trying to figure out how to use a potentiometer or some form of fader to bring my circuit from 9 V to 18 V, and then back to 9 V without it being permanently one or the other, having to disassemble to change.
I don't want popping from an DPDT switch.
I'm wanting to be able to roll it up to 18 V when I need more headroom and then roll it back down to 9 V for a grittier sound.
What is the most efficient way to do this, what do I need?
Before its mentioned yes the guitar has a gain boost.
Edit: the power source is two 9 V batteries rated at 540 mAh. The current draw is 1.22 mA @ 9 V total. (3 active humbuckers 0.08 mA @ 9 V each with boost preamp 0.98 mA @ 9 V.)
I hope this helps.
AI: Your question gives no clue regarding the voltage available for the task and the maximum current required. Assuming that there's a few volts to spare and that the current is < 100 mA a simple solution would be to use the ancient LM317 adjustable voltage regulator.
simulate this circuit – Schematic created using CircuitLab
Figure 1. Adjustable voltage regulator circuit.
The LM317 adjusts its output so that it is 1.25 V higher than the ADJ pin. I have chosen the resistor values to make the maths easy (100 Ω/volt) so you can scale them up to use a 1k pot for R3, etc.
You'll need to calculate the power dissipation in U1 and check if you need a heatsink. \$ P = (V_{in+} - V_{OUT
min}) I \$. |
H: How does a CAN transceiver work?
CAN Transceiver Transmit Mode
I try to understand the transmit functionality of a CAN transceiver. I found this post a good starting point, but it doesn't completely answer my question.
Block Diagram
Let's say we have the following CAN transceiver block diagram (VDD = 5 V / VSS = GND = 0 V).
(CAN Physical Layer Discussion p. 5)
CAN Bus Basics
In my understanding there are a few simple basics for an ISO-11898-4 "complient" CAN-Bus.
In the recessive state: CANH and CANL should be at the same voltage level (≈ 2.5 V).
=> CANH ≈ 2.5 V & CANL ≈ 2.5 V
In the dominant state: CANH and CANL should have a high voltage difference (≈ 2 V).
=> CANH ≈ 3.5 V & CANL ≈ 1.5 V
There must be at least one termination resistor of ≈ 120 Ω.
A logical TxD LOW or 0 bit is transformed to a dominant state.
A logical TxD HIGH or 1 bit is transformed to a recessive state.
This should be enough for the first understanding!
Functional Description
Recessive state
CANH and CANL output transistors are open (high impedant).
The recessive voltage level of CANH and CANL = VDD / 2 ≈ 2.5 V is created by the following circuit part.
Dominant state
CANH and CANL output transistors are closed.
Let's say:
Transistor (collector emitter voltage): Uce = 0.1 V
Didode (diode drop voltage) UD = 0.5 V.
=> CANH = VDD - (Uce + UD) = 5 V - (0.1 V + 0.5 V) = 4.4 V.
=> CANL = Uce + UD = 0.1 V + 0.5 V = 0.6 V.
=> UT (Rtermination voltage) = VDD - (2 * (Uce + UD)) = 5 V - (2 * (0.1 V + 0.5 V)) = 3.8 V.
=> IT (Rtermination current) = UT / 120 Ω = 3.8 V / 120 Ω ≈ 32 mA
QUESTIONS
Did I miss something or is my calculation valid (just for basic understanding :) )?
Can anyone explain how the recessive voltage generator in picture 2 works in detail? How big are the resistors to CANH and CANL?
Will Itermination double if there is a second termination resistor?
AI: Did I miss something or is my calculation valid (just for basic understanding :) )?
First of all, the schematic shows BJT's. They have no drain source, but collector emitter.
Next, the idea of calculation is in the right direction, however.
The datasheet does not directly give voltage drops across its internal components, but still defines values of \$V_{O(CANH)}\$ and \$V_{O(CANL)}\$ as well as the maximum differential voltage in the dominant state \$V_{DIFF(d)(o)}\$ (or: UT (Rtermination voltage) as you call it).
You're \$V_{O(CANH)}\$ and \$V_{O(CANL)}\$ might be valid, but the datasheet claims a UT (Rtermination voltage) = 3.8V will not occur as 3.0V is the maximum value.
Can anyone explain how the recessive voltage generator in picture 2 works in detail? How big are the resistors to CANH and CANL?
The voltage source generates a voltage of (about) half the supply voltage (check parameter number D7 in the picture above). This voltage is fed to a buffer, which on its turn is enabled/disabled by the Power-On Reset block.
The values of those resistors are not given in the datasheet. The datasheet defines the resistance seen from the CAN nodes to ground in Figure 2-1.
Parameter numbers D20 and D22 show the resistance is in the order of kWatts, oops, kΩ of course!
Will Itermination double if there is a second termination resistor?
By crude approximation: yes |
H: Does a program exist to draw logic signal waveform from csv data?
Assuming that I want to collect several seconds of activity of digital signal on multiple pins of a device, one way is to create a simple FPGA design that buffers all that information and then transmits it to the PC or stores it into a file (csv format e.g) on some form of removeable media (by using a softcore with code that can read/write file access system for example).
Once I have this sequence of 1s and 0s on my PC, I would like to visualize all the activity by making waveforms that can be zoomed in, zoomed out and panned and perhaps do some processing on the results e.g collect sequence of serial bits into a single byte during post processing and then do maths with it.
Does a method to do such post processing of data collected via a custom solution (involving FPGA in this case), exist?
I do not have a logic analyzer and do not think that a logic analyzer can capture a lot of data like this as it has a very limited buffer space and sample rate anyway for such a situation.
AI: Your question is quite broad but here are a few pointers.
A convenient way to display data is Excel as the comment pointed out, although if you need to zoom / pan, or display lots of point, excel is quickly limited. (Been there...)
One of the best tool for data visualization is Matlab (and perhaps their open-source equivalent). With a few lines of code you will be able to plot your data on a chart and have powerfull zoom/pan functionalities.
Another approach would be to use the software processing which is the "arduino for display", with here some starting point to link hardware directly to your computer and display a graph. This would require more work to get the pan/zoom working but you would have your signal without the need of saving it to a file.
For a one-shot thing I would go with Matlab. If you want to make a tool that you would use regularly in the future, processing is probably the (easy) way to go. |
H: LED current source safety margin
I have a power LED that requires 600mA at around 25 Volts. Since there are mainly 24 Volts and 36 Volts power supplies available on the market for a reasonable price, I needed to choose a 36 Volts model, because otherwise (at 24 Volts) the LED would be undervolted and probably draw a lot less than the nominal 600 mA. So this decision is already made and not part of the question.
But now for the constant current control: I found two models of constant current DC-DC converters, one rated for up to 36 Volts input, and the other for up to 56 Volts (for those interested, they are the Meanwell LDD-600L and LDD-600H, but that doesn't matter for the question).
I wonder if it is safe to choose the 36V input model and drive it with my 36V power supply, or if I should rather choose the 56V model.
In other words, can I generally assume that the manufacturer has already included a safety margin into the 36V input voltage rating, so that it can operate at this voltage for an indefinite amount of time. Or would prolonged operation so close to the upper boundary of the spec result in severely reduced life span?
At least as far as I can see, the datasheets seem to give no indication about that.
By the way: buying an already current limited power supply is not an option because I would need three of them (it is actually an RGB LED) because of cost and because I want PWM control.
AI: If a device is speced to run off of a common DC voltage such as 36v and does not specify a tolerance or other requirements for that common DC voltage, then it is going to have sufficient margin built in to run from typical power supplies. If it didn't, the vendor would have to deal with large numbers of returned units that failed when customers hooked them into poorly regulated smps. |
H: NCP1117 Regulator voltage feedback not working correctly
I'm having a brain fart. Reading 3.1V ish on the output. My +5V0 net is after a schottky diode with 5V + a little bit coming from the NCP1117, and another 5V0 coming from a USB connector. Reason being I want the regulated voltage after the diode to be 5V, accounting for the diode voltage drop.
My feedback resistors look fine, I checked the parts on the board and they look fine, and my input looks solid too.
After the +5V0 net is a 3.3V regulator for 3.3V logic stuff. That's about it. The +5V0 only powers a handful of devices which seem to be functioning correctly with the 5V0 USB going through the diode and only powering to about 4.6V.
LINK TO DATASHEET
Any clues?
Thanks in advance
AI: You (and a lot of the answers so far) seem to think that the path from OUT to SET is a feedback loop, and that putting the diode in that path will somehow allow the regulator to compensate for the \$V_f\$ of the diode.
Nothing could be farther from the truth.
The fact is, there are a lot of things you give up when you simplify a regulator to just 3 pins, and one of those things is an external feedback loop. The only thing that such a regulator can do is maintain a fixed voltage between OUT and SET, and the feedback loop that accomplishes that is entirely internal to the chip.
The equation that you show as part of your schematic is based on the assumption that there is a fixed resistor between OUT and SET, and therefore this resistor has a fixed amount of current flowing through it, which allows you to use a second resistor to establish a voltage for SET relative to ground. Putting a diode in there completely violates that assumption, because the voltage drop across the diode will be based partly on the load current, and you can no longer assume that the current through the two resistors is still constant.
If you want a circuit that regulates the voltage at the cathode of the diode, then you need to pick a different kind of regulator (either linear or switching) that actually has an external feedback pin. |
H: CE amplifier non-sinusoidal signals
I am trying to learn some transistor amplification by simulating. However there is something I don't understand why.
Why all waveforms are somehow distorted or bad-looking sinusoidal-ish waves instead of nice sine waves? Only the Vbase waveform looks decent.
AI: A very short answer: The input signal at the base (Vin=VBE) is transferred into an output current Ic acording to the transfer characteristic (control function):
Ic=Io[exp(VBE/Vt)-1]
This is not a linear function and, therefore, the output current does not swing in exact proportion to the input voltage (and the same applies to the output voltage at the collector which is caused by the output current swing). And this nonlinearity causes distortions.
Only for very small input voltages we could consider the relation as "quasi-linear". |
H: Finding current in RLC circuit
I am given the following circuit:
Thanks for any help.
AI: Assuming you want the current through the horizontal R0, you can,
Combine all the other passive devices using series and parallel combinations. Since you have two source frequencies, you'd do this calculation separately for each frequency.
Use superposition
A. Find the current through R0 due to each of the sources.
B. Sum these currents to get the total current through R0. |
H: Assign existing footprint to existing component in Circuit Maker?
I found the following two components in Circuit Studio that I am using in my design:
AOD407:
And IRLR8726:
The manufacturer recommended footprint is exactly the same for both, and they use the same 3D model in Altium. The trouble is, whoever did the footprint for the 407 on Octopart departed from the recommended footprint, making their own instead. This is undesirable for me, as my design needs symmetry.
Left: 407 Footprint (non-standard, custom), Right: 8726 Standard Footprint
In the parts page, I can add new footprints to the part, and I added one, but it starts with a blank template. I do NOT want to copy and paste the standard footprint into the template. This is too much effort for a professional tool. How can I import existing footprints in the footprint editor? This will allow me to standardize my footprints for these and other parts.
I am using Circuit Maker, which is essentially the community version of Altium.
AI: You can have multiple footprints for each component.
http://documentation.circuitstudio.com/display/CSTU/Component+Management+in+CircuitStudio
Under the component, In the models tab, click add, then browse the pcb library for the footprint. You can delete the old footprint or I believe there is some way to select it. You can also do this for one component only if done through the PCB editor and not the library |
H: HX711 module VCC and no VDD
(Image source and more details: circuitio.io)
I am trying to build the above circuit powered by battery alone. Sparkfun HX711 is expensive and hence I am using HX711 bought on Amazon. Here is the documentation
HX711 module has Operating Voltage: 2.7V to 5VDC and Operating current: <10 mA
Sparkfun HX711 has VCC and VDD.
VCC is the analog voltage to power the load cell. VDD is the digital supply voltage used to set the logic level.
[...]
In many cases, you can just short VCC and VDD together. If your microcontroller uses 3.3V logic however, you'll want to connect VCC to 5V and VDD to 3.3V.
(Source: SparkFun - Load Cell Amplifier HX711 Breakout Hookup Guide)
Amazon HX711 has only VCC and no VDD. Therefore, can I connect LoadCellHX711SF VCC to NodeMCU1 3V3 instead of connecting LoadCellHX711SF VDD to NodeMCU1 3V3?
AI: I use this "no name" module in 3V3 without problem. You can safely connect VCC to 3V3. Heere is the reverse to compare to the HX711 datasheet |
H: Need help to design efficient zero crossing CURRENT detector : clamp diode solution
I try to design a replacement potter's wheel motor controller for an old potter wheel. I have solve my zero crossing voltage detector and TRIAC command.
Now I begin to understand the importance of the phase shift between current and voltage on inductive load like motor and I think I need to detect the real state of the triac.
In addition of zero crossing VOLTAGE detector, I think I need an isolated zero crossing CURRENT detector to be sure TRIAC is really off.
Inspired from this schematic, the idea is to put diode in series with the load, to use forward voltage as limiter for the optocoupler SFH6206-3 like the following schematic:
I select STTH20R04G-TR diode because they can handle more than 16 A
I use the forward voltage dropout of diodes (2 x 1.7V) minus SFH6206-3T diode forward voltage max (1.65V) to get the voltage accross R10 (1.75 V)
I want 1 mA to the optocoupler diode so I need (3.4-1.65)/0.001 = 1750 ohms max, I select R10 as 1600 ohms from E24 serie.
For the output of the optocoupler I use CTR value of 34%, so I probably get 0.34*0.001 = 340 µA through R10 when current flow to the load.
I want IZCD low level as low as possible (VIL of µC is 1V and VCESat is 0.4V) so I want 2.9V across R10, R10 must be at least (3.3-0.4)/0.000340 = 8529 ohms.
I select 10 kohms and get IZCD = 0.4 V when current flow to the load
When current not flow to the load, there is a current leakage of optocoupler (50 nA).
I got 10000*0.00000005=500µV across R10 is this case, IZCD~=3.3V when current stop to flow through the load.
I'm not confident with TRIAC leakage current through snubber and I think a forgot something...
Can you help me to take a look of my zero crossing CURRENT detector and tell me if it can theoretically work?
I'm not confident with the "as is" STTH20R04G-TR power dissipation do you think they are ok? Do I need heat-sink? (They are bit big, did you know smaller diode without the need of heat-sink?)
Is there an other (isolated and simple) way to detected current flowing and stop flowing through the load to be sure TRIAC is really OFF.
(I know TRIAC voltage is low as ~1.5V when TRIAC is ON but I don't know how to exploit this information?)
Thanks in advance for you help
EDIT 2019-11-03 (Thanks to Bruce Abbott)
I move the the current detector between the TRIAC and snubber and correct the optocoupler resistor value. (R10 can be 1/4 W).
At 1mA the typical optocoupler LED voltage is ~1.025V, so assuming
0.6V per diode the required value for R10 is ((0.6*2)-1.025)/1mA = 175Ω. At 3.4V the LED current will probably be around 10~15mA.
Using a standard diode like DSI30-08A, we can found the calculation values in the datasheets
Forward current versus voltage drop of DSI30-08A
Diode Forward Voltage (Typ.) vs. Forward Current of SFH6206-3
I think this first solution is not really optimized, it seem to loose a lot of power, I hope someone got a better architecture to detect current zero crossing.
AI: I select STTH20R04G-TR diode because they can handle more than 16 Arms
This is an 'ultrafast recovery' diode which has a 'softer' V/A curve than most rectifier diodes. This will waste more power at high current, but still drop about the same voltage as other diodes at low current. The low current behavior is important because the TRIAC holding current could be quite low (the datasheet says 50mA maximum, but does not specify a minimum).
Whether the diodes will need 'extra' heat-sinking depends on the current draw. Letting them run hot reduces heat-sinking requirements because the voltage drop decreases, but may adversely affect the current detection threshold (as well as not being good for adjacent parts on the PCB).
You have calculated the optocoupler input current based on rectifier voltage drop at high current. At low current (eg. 50mA) it may be too low to operate the optocoupler, and so may falsely detect that the TRIAC has turned off when it hasn't. At 1mA the typical optocoupler LED voltage is ~1.025V, so assuming 0.6V per diode the required value for R10 is ((0.6*2)-1.025)/1mA = 175Ω. At 3.4V the LED current will probably be around 10~15mA.
The snubber could be a problem because it bypasses the TRIAC and injects current into the diodes and optocoupler. At mains frequency it might be OK since close to Triac turn-off the voltage is low anyway, but at higher frequencies the capacitor becomes a short circuit so noise will be amplified. This may cause glitches at the optocoupler output. You could try moving the snubber to the other side of the diodes so the optocoupler only responds to actual TRIAC current. |
H: How to determine LVDT sensitivity?
I performed an experiment using an LVDT where I used a generator voltage of 4.84V. I determined the secondary voltage at the beginning position, obtaining 2.48V and at the end (displacement os 22.5 cm) 2.12V.
Now I have to compute the sensitivity in mV/V/mm.
I thought that this was given by
$$S=\frac{\Delta V_{sec}}{V_{prim} \Delta x}$$
which leads me to 0.3306 mV/V/mm.
Now apparently this is wrong and I should obtain a value around 4... My guess is that the expression I'm using, even if its dimensions are correct is not right. I read on this: http://www.gatewaycoalition.org/files/bioengg_Instrumentation/site/LinearVariableDifferentialTransformer.html
that they basically multiply the output and the input and divide by the excitation voltage times the displacement. But in that case, the units are not right. Can someone help me?
Thanks!
AI: Your math looks right, with the numbers shown. I suspect that your measurements, or experimental setup is probably wrong.
Most likely, you are being confused by the AC voltage output measurements. Try using (-2.48) and (+2.12) in your calculations. I then get an answer of 4.22 mV/V/mm.
LVDT's tend to have 2 windings, with the signal output (in VAC) going like:
Distance[mm], Output[Vac]
0 mm, 2.48 Vac
112.5 mm, 0 Vac (right at mid-stroke)
225 mm, 2.12 Vac
So:
dX = 225 mm
and dVac = dVac (1st winding) + dVac (2nd winding), or:
dVac = 2.48 + 2.12 = 4.6 Vac
So, with Vexcitation = 4.84 Vac,
S = 1000*(dVac / Vexc) / dX:
S = 1000 * (4.6 Vac /4.84 Vac ) / 225 mm = 4.22 [mV/V/mm] |
H: Does adding the input signals change the behaviour of an amplifier?
I have these 3 signals, they differ by 300 Hz each. When I use any of these signals as input to a class B amplifier, I get the desired current amplification. The thing is, I have to input all these 3 signals at the same time to the speaker(my load). My plan to do it to use an adding op-Amp configuration. However, I wonder will the amplifier work properly or will there be any problems?
Also, what are the chances that I suffer from momentary excess voltages on
the load, an 8 ohms speaker in fact, which may result in damage to the speaker?
Thanks in advance.
edit : I don't know does it affect the question but I think I have to add that, actually at any time instant only two of the three signals will be active, and one of them will be lower in amplitude relative the other one.
AI: No. The 3 signals will not change the behavior of the operational amplifier, providing the op amp continues to operate in its linear region. It if starts to compress, saturate, or limit, then it starts to act like a mixer and you may start to see new frequencies in the output. |
H: I swapped +5V and ground on a chip, how to know if the chip is dead?
Well, I accidentally connected ground to the +5V pin and vice-versa on a (W65C22), I don't know how to be sure that I didn't burn the chip.
One thing I was noticing is that when the cables were swapped, when I connected power not even an LED connected from 5V to ground through a resistor would turn on, so maybe the chip has some sort of security around power pins so current flows in only one direction, do chips have this kind of protection?
AI: I accidentally connected ground to the +5V pin and vice-versa on a (W65C22), I don't know how to be sure that I didn't burn the chip.
It's very, very likely that you damaged the IC. Whether it is totally dead, or just partially damaged, would need further checking (unless it's already obvious - you haven't mentioned the results of subsequent checks - what checks did you do so far?). However you can't trust that IC completely, even if it seems to work now.
Symptoms of obvious internal damage include "bubbles" in the top or bottom of the IC epoxy package (due to the die inside the package getting very hot) - even part of the package now being missing - or, as commented, any smell from the IC.
Another symptom of internal damage is an increased current drain (with correct polarity power applied, obviously) sometimes leading to the IC package being significantly hotter than usual.
maybe the chip has some sort of security around power pins so current flows in only one direction, do chips have this kind of protection?
No, typical ICs don't have that type of protection.
when the cables were swapped, when I connected power not even an LED connected from 5V to ground through a resistor would turn on
That behaviour is because your IC drew so much current that the power supply voltage dropped (temporarily), and that is why the LED could not light - insufficient voltage across it, due to the high current through the reversed IC. |
H: Current sharing parallel power supplies
Recently, I purchased two 48v 25A power supplies. I want to put them both in parallel. In reality, each PSU consists of 2 smaller individual units(see picture), so 4 units in total. Pin 8 of that ribbon wire connector is the pins you need to connect in order for the two smaller PSUs to output 48v at 25A.
So I know that linking both pin 8’s of the connectors in one power supply will make the 2 smaller units work together.
My question is, could I simply daisy chain the current share pins of all 4 sub-power supplies(what is done in picture) to make them all work together to output 48v at 50A? Reason asked is because these were very expensive and don’t want to cook anything.
Original: https://prnt.sc/q5aqyu
Edit: Datasheet for said PSUs
AI: No you cannot blindly connect all 4 supplies ganged together and expect rated performance with any load.
Current sharing can be active or passive. They support the 2 module active current share using the signal on pin 8 to be compared with internal current sense so that parallel current share is kept within 2% of total rated current. This is not possible with 4 modules.
Passive current sharing is when you have no active feedback for sharing current and rely only on the matching of voltage divided by wire resistance from source to dynamic load to determine the current share.
The challenge is to define load regulation error and current share imbalance which are tradeoffs.
The following shows an imbalance in average output impedance and voltage mismatching on current sharing errors.
0.4% or 20 mV max @ 25 A , 48V means ESR = 20mV/25A = 0.8 mΩ
However if the voltage error was nulled then drifted to 5mV or 0.1% with no load the parallel supplies now share an ESR`= 1.6 mΩ (=2x 0.8 mΩ)
Thus a hypothetically mismatched circulation current occurs at 1mV/1.6mΩ = 0.625A per mV of error.
e.g. a 0.4% voltage error or 20mV difference results in a 28% current sharing imbalance and a system failure.
Obviously System Specs need to be defined and then stability assumptions not mentioned to verified at worst case loads. Current sharing causes disturbances in each others active voltage regulation and current sharing, both which can cause instability or actually unstable oscillation and system fault. |
H: Is my understanding of output impedance for this transistor circuit correct?
Im having trouble to understand the meaning of output impedance of an active circuit and in this case the emitter follower. I have read several information but yet failed to get the meaning. Im looking for an easy but correct definition.
If we call the output impedance of an emitter follower Zout. This is what I understand about the meaning of Zout: If we couple a variable load R and vary it, the output impedance Zout is then the change in Vce relative to the change in I R as I have drawn below?:
Is that the correct meaning of Zout in layman’s term? Definitions containing “Looking into” makes thing more complicated at the moment. If mine wrong could you provide such explanation similar to mine? Im completely confused and this is my maybe tenth time I struggle to understand.
The definition might be the inverse slope of Vce Ic curves but I need a more concrete definition showing also how it is obtained?
AI: ... I need a more concrete definition showing also how it is obtained
Since the base of the BJT is nailed down hard (zero impedance voltage source), the dynamic output impedance is (you can find the starting equation at this Wiki page on the BJT and the Ebers-Moll model):
$$\begin{align*}
\operatorname{D}\,I_\text{E}&=\operatorname{D}\left[I_\text{ES}\left(e^{^\left[\frac{V_{_\text{BE}}}{\eta\,V_T}\right]}-1\right)\right]\\\\
&=I_\text{ES}\,\operatorname{D}\left[e^{^\left[\frac{V_{_\text{BE}}}{\eta\,V_T}\right]}-1\right]\\\\
&=I_\text{ES}\,\:e^{^\left[\frac{V_{_\text{BE}}}{\eta\,V_T}\right]}\operatorname{D}\left[\frac{V_{_\text{BE}}}{\eta\,V_T}\right]\\\\
&=\frac{I_\text{ES}\,\:e^{^\left[\frac{V_{_\text{BE}}}{\eta\,V_T}\right]}}{\eta\,V_T}\:\:\operatorname{D}\,V_{_\text{BE}}\\\\
&\approx \frac{I_\text{E}}{\eta\,V_T}\:\:\operatorname{D}\,V_{_\text{BE}}\\\\&\therefore\\\\
r_e=\frac{\text{d}\,V_{_\text{BE}}}{\text{d}\,I_\text{E}} &= \frac{\eta\,V_T}{I_\text{E}}
\end{align*}$$
(\$\eta\$ is the emission co-efficient and is often just taken as \$\eta=1\$.)
There is also some Ohmic base resistance, \$r_b^{'}\$, and Ohmic emitter resistance, \$r_e^{'}\$, to account for. (For small signal BJTs, \$5\:\Omega \le r_b^{'}\le 20\:\Omega\$ and \$50\:\text{m}\Omega \le r_e^{'}\le 400\:\text{m}\Omega\$.)
Roughly speaking, this Ohmic portion adds another \$r_e^{'}+\frac{r_b^{'}}{\beta+1}\$. So the total, including Ohmic and dynamic resistances, is:
$$r_e=\frac{\eta\,V_T}{I_\text{E}}+r_e^{'}+\frac{r_b^{'}}{\beta+1}$$
(If the voltage source at the BJT's base has some source resistance, then just treat it similarly to how \$r_b^{'}\$ was treated, above.)
The above only accounts for the simplified BJT portion which doesn't include, for example, the Early Effect. It also assumes that the temperature is dead-stable and doesn't move. (The saturation current, \$I_\text{ES}\$, is highly temperature-dependent -- on the order of the 3rd power of the absolute temperature, proportionally. So these equations become seriously bogged down if you want to start taking into account changes in temperature due to changes in the collector current, for example.)
Finally, it doesn't account for \$R_\text{E}\$, which will appear to be "in parallel" with the above formula for \$r_e\$. The value of \$R_\text{E}\$ can be selected so that it is near the expected load current (higher or lower) in order to stabilize the net apparent output impedance (if that is needed for some reason.) However, \$R_\text{E}\$ may be there to provide a very low, minimum load for the circuit, with the output impedance now guaranteed to be no higher than \$R_\text{E}\$.
Because the dynamic resistance portion often dominates, the total value may also change rapidly with variations in the emitter current.
Let's test the above idea using a Spice program to see if the above simplified, theoretical treatment is supported by the vastly more sophisticated calculations used by Spice. I'll avoid the complexities of using the .MEAS statement to automatically compute this. Instead, I'll do it manually and in plain view.
Here's the circuit in LTspice:
From the BJT information, together with an estimated emitter current of \$I_\text{E}\approx \frac{6\:\text{V}-700\:\text{mV}}{1.0\:\text{k}\Omega}\approx 5.3\:\text{mA}\$, we find that \$r_e\approx \frac{26\:\text{mV}}{5.3\:\text{mA}}+200\:\text{m}\Omega+\frac{10\:\Omega}{201}\approx 5.2\:\Omega\$, with most of that coming from the first term. Technically, we'd need to put that in parallel with the \$1\:\text{k}\Omega\$ resistor, dropping it to about \$5.17\:\Omega\$. But I already rounded the above value to the nearest tenth, so this means we'll stick with \$r_e\approx 5.2\:\Omega\$ for a theoretical estimate.
(The .temp card on the above schematic is there so that \$V_T=26\:\text{mV}\$.)
Now let's see what LTspice tells us:
Just by eye, I can read off the following two voltages from above: \$5.303677(6)\:\text{V}\$ and \$5.303682(8)\:\text{V}\$. We know that the injected current is \$1\:\mu\text{A}\$. So we compute, \$r_e=\frac{5.3036828\:\text{V}-5.3036776\:\text{V}}{1\:\mu\text{A}}=5.2\:\Omega\$!!!
Which is remarkably good, as I didn't even try this out before writing the above text.
An important note about the above process is that I didn't inject \$10\:\text{mA}\$. This would have substantially moved the point along that curve I talked about earlier and therefore the computation would be a very different secant instead of an exact tangent. I chose an injection current that was less than a thousandth of the current in \$R_1\$ to test the idea.
That doesn't mean it isn't useful to explore how \$r_e\$ varies with different loads. It's just that if you want to find out the exact tangent value with Spice, you need to keep the change tiny. Otherwise, you get conflated results and you can't use that to verify the earlier theory that I developed.
Just a note. |
H: How to design a switched mode battery discharger
I have a very basic understanding of switched mode power supplies and know that this is a simple buck converter suitable to e.g. charge a 12 V car battery from an input of, say, 24 V, with a dc current that may have some ripple:
The voltage on the battery resp. the charging current can be controlled with the duty cycle on the switch.
My problem is to find a similar schematic for discharging the battery with a controlled current. The purpose is to measure the discharge process in order to find the capacity of the battery. This is a schematic with the disadvantage that the discharge current goes on and off, instead of having just a little ripple:
All I find on the Internet are schematics that regulate the output voltage / current over the resistor, but in my project I need to regulate the current in the battery instead, and want a dc current with just a little ripple.
Any ideas?
AI: Use a boost circuit instead of buck then the battery current will be continuous
in a buck converter the curren draw is sufficient for the converter to enter continuous conduction mode, because the inductor is connected directly to the source, the source will also see continuous draw (with ripple at whatever level the inductor ripple is less any absorebed by input capacitance) |
H: Combinational loop in Verilog/SystemVerilog
What's the difference between a += 1 and a = a+1 in Verilog?
always_comb begin
a = '0;
a += 1;
end
always_comb begin
a= '0;
a = a+1;
end
Is the 2nd case a combinational loop?
AI: a+=1 is just a short-hand for a=a+1. They both are equivalent.
There is no combinational loop in both cases.
a will be simply driven 1 in both cases. Synthesiser usually flags this as warning or info. |
H: Voltage levels of Microcontroller Oscillator Pins
I am using MPC5606S Microcontroller.
I want to clear one concept and have a doubt.
The Microcontroller using 8MHz crystal on the pins 27 (XTAL) and 29 (EXTAL) And a 32.768kHz RTC crystal between pins 71 (XTAL32) and 72 (EXTAL32).
My understanding :
The Crystal is constantly bombarded with some noise composed of many frequencies. But since the Power is not provided to the microcontroller, the amplifier (OP-AMP amplifier) circuitry present inside the Controller is inactive and does not amplify the resonant frequency of the crystal which is 8MHz. Once, the Controller is powered, the amplifier is active and now only the 8MHz resonant frequency is amplified and is provided to the other sub-section blocks inside the microcontroller. Is my understanding correct?
My doubt :
What determines the voltage levels of the RTC 32.768kHz and 8MHz oscillations?
I have captured the below waveforms for both oscillations :
AI: Indeed as stated in the comments, a Pierce oscillator is most commonly used for a simple crystal oscillator circuit used in for example a MicroController.
Here's a typical example of such a circuit:
Source: this presentation.
To get an oscillator to start, it needs to have a loop gain greater than one. That means that for example a 1 mV signal across C2 will be amplified to (for example) 10 mV across C1. That then feeds back through the crystal to C1. As long as more than 1 mV "gets back" at C1 we have a loop gain of more than 1 and the oscillator can start.
Where does the 1 mV signal come from?
That can be noise but also a result of just switching on the circuit. Any imbalance or disturbance will do.
What determines the voltage levels of the RTC 32.768kHz and 8MHz oscillations?
When the oscillator gets going the signals will start to increase in level (1 mV becomes 1.1 mV, 2 mV, 3 mV ... etc). So when does that stop?
Obviously the signal cannot grow to more than the value of \$V_{DD}\$ because that's the maximum voltage that the amplifier (Qp and Qn) can output. So that supply voltage \$V_{DD}\$ is a limiting factor, the amplifier would clip.
When an amplifier starts to clip, it means that it is hitting its limit, it wants to output for example 3.3 V but it can't and only manages 3.0 V. That means that it amplifies the signal with less gain (compared to when it amplifies small signals). That then decreases the loop gain and that fixes the amplitude of the signal at a certain level. The oscillator settles at the point where the average loopgain is 1 (one) so that we get a stable oscillation, the signal does not increase nor does it decrease. |
H: Why do sidebands appear after Amplitude Modulation?
In amplitude modulation, the amplitude of the carrier wave is changed according to the variations in the message signal, and that's what we draw inside the two envelops of the message signal, that's totally fine, but what is confusing to me, that we never changed the frequency of the carrier wave, then why do those two sidebands appear in the frequency response of the AM wave, I know that the mathematics works out to be like that, but how on the earth they appear in first place, when we never tried to mess with the frequency of the carrier?
AI: AM means that the amplitude of the carrier is multiplied by the payload signal plus some offset.
The multiplication theorem for sine says
\$\sin(a) \cdot \sin(b) = \frac{1}{2} ( \cos(a-b) - \cos(a+b))\$
Let \$a=2\pi f_c t\$ be the carrier phase and \$b=2\pi f_s t\$ the phase of a sinusoidal payload signal then as a result of AM (=multiplication of sines) you get a sum of two sinusoids. The frequency of one of them is a little bit below (\$f_c-f_s\$) and one of them a little bit above (\$f_c+f_s\$) the carrier frequency.
This works not only for a payload signal that is a pure sine wave but also for a whole band (any signal can be seen as a sum of sinusoids).
So as a result you get one band above and one (mirrored) below the carrier frequency.
(Note: The offset mentioned in the beginning results in the fact that also the unchanged carrier frequency will be present after AM; but I've neglected that for simplicity).
BTW:
we never tried to mess with the frequency of the carrier
AM does mess with the frequency.
It's a missconception that multiplication of two signals wouldn't mean messing with the frequency; that's true only for multiplication by a constant; that's a linear operation; multiplcation of two time varying signals is not. Any non-linear operation introduces new frequencies.
Simple example: frequency doubling (=messing with frequency) of a sinusoid can be done by simply squaring the signal (=multiplying by itself). |
H: Strategy against Side Channel Attack
I am newbie to Hardware Security. While studying Side Channel Attack, I realized that power consumption profile of electronic control unit is a key to encrypt what algorithm runs on it. I thought implementing same algorithm with different approach may change power consumption profile.
For example:
Task is to blink a led every 1 second.
First approach is to configure GPIO and make it happen with delay.
Second approach is configuring a TIMER that gives logic 1 per second.
But I don't have tools to test this phenomenon. So I would like to take some ideas if it may work or don't.
AI: Clarification
First of, your understanding of a Side Channel Attack is wrong: Generally attackers already know what algorithms are running on hardware, it's mentioned in the datasheet of the chip or product. SCAs are meant to extract pre-encoding data by exploiting an implementation specific data-dependency feature.
Existing solutions
There's quite a lot of literature regarding SCA protection and more specifically protection against power profiling. The most effective accepted solution generally comes down to making sure that each bitflip is compensated by a closely positioned bitflip in the opposite direction.
It's not 100% foolproof, but it's as close as we get today (unless some company somewhere solved it better and didn't publish yet, although I'd be skeptical of unpublished cryptographic insurance).
Issues with your solution
Why your solution won't work: You're basically inserting predictable and even known noise. Since you should assume that the attacker knows your exact implementation, it'd be trivial to filter out your inserted power frequency and just continue on as if you'd never put in the protection.
Issues with any self-designed solution
Schneier's Law, let me repeat that, with feeling: Schneier's Law
Conclusion
If this is for an actual product, drop this idea and consult an expert.
If this is for a hobby project or school assignment, do go on, have some fun daydreaming, but keep the problems in mind. |
H: Pig tail vs SMA pcb mount connector
Is there any difference in applying a 50-ohm female SMA PCB mount connector to an antenna as opposed to a pig-tail connector to a microstrip patch antenna?
The difference is in terms of the performance of the antenna, such as the resonant frequency shifting, BW, gain, axial ratio
AI: Impedance matching is impedance matching. So, no, technically there's no difference.
That is, unless either or both of the connectors aren't perfectly 50Ω impedance. |
H: What is boot line in BSP
On the wikipedia page Board support package it mentions the term "boot line". What is the meaning of "boot line"?
AI: If you run a program from a command prompt on a desktop operating system, you can add extra command line parameters after the name of the program. This provides a mechanism to push parameters into the program being run.
The "boot line" in VxWorks provides similar functionality. It allows parameters to be passed into the VxWorks application being booted. |
H: BLDC/BLAC controller motor voltage reverse protection
I am currently designing a BLDC controller and keep running into a power safety issue:
I have added a smart diode reverse protection controller to my design with its transistor between the fuse and the bulk capacitance (4 x 220uF elcap bank).
This was done to protect all downstream components (and the polarized capacitors especially) from reverse polarity events.
Now obviously this poses a big problem during regenerative braking since the IC (LM5050) interrupts the supply line and makes the micro think an undervoltage event occured (which it momentarily did, since the power to the motor was cut).
What is a good way to mitigate/solve this issue and how does this get solved by real electronics designers?
Thanks!
simulate this circuit – Schematic created using CircuitLab
AI: If you only want to protect against reverse polarity then you are using the wrong technique. Instead of an LM5050 you can just turn the FET on with positive supply voltage. If the polarity is reversed the FET won't turn on.
simulate this circuit – Schematic created using CircuitLab
As in your circuit the FET is oriented so the body diode conducts, then the FET shorts it out when turned on. However since we don't have a Gate voltage booster the FET has to placed in the negative lead so positive supply voltage will turn it on. This means either the supply or controller's negative rail must be floating (not connected to ground). |
H: Rejection of particular frequency in a signal which contains many frequencies in its spectrum (fourier transform)
How does a filter know which frequency is to reject?
Detail:
A signal may contain a lot of frequencies. How could we surely say that the result of linear combination of the result of applying these frequencies individually will produce the same result as applying the whole signal?
At any point of time there will be a voltage level which will be applied to a circuit (linear combination of amplitude of contained frequencies.) Circuit only "sees" voltages, so how will it know that which frequency to reject? I mean the resultant signal amplitude values will be the value, after subtracting the value of rejected signal frequency amplitude from original input signal value at every time instant.
AI: I find the way you are phrasing your question a little confused but I think I know what you are looking for. I'll try to answer.
A circuit only sees (instantaneously) voltages - well yes, but there are elements on the circuit that are time-dependent. If we are talking about an analogue circuit, this is L's and C's. These elements store energy in one form or other, and release it with a rate which is variable depending on component value.
So now we have a circuit that has some "memory" characteristics. It's instantaneous state is dependent on the sum of all previous states.
There are a number of ways of analysing this mathematically, but eventually we find that with certain circuit configurations we can arrange that the circuit's response varies according to the frequency content (Fourier spectrum) of the input. (This is one form of analysis that works well for periodic signals - signals which are assumed to behave in the same way, over and over, through all of time. In practice of course, nothing does this, but, say, a 1MHz waveform running for a second or two is close enough for the assumption to hold.)
Likewise a digital filter works by computing the instantaneous output based on some conmbination of previous (sampled) inputs. Now the memory element is really memory, used to store some number of samples in a rolling buffer.
In the end the important fact is that circuit behaviour has a time (and therefor frequency) dependent element. |
H: PINOUT ON LT1789CS8-1
the following in-amp IC is 8-lead plastic SO, but there is no indication about which pin is first pin (oreintation is not printed on the IC ) any information about how to determine it is good enough.
Picture:
AI: The LT1789 datasheet (page 22) clearly shows that pin 1 is on the chamfered side: |
H: How can I turn a midi keyboard to a stand-alone piano using Arduino or any other way?
I have a midi keyboard, but I find it frustrating to start PC, DAW system every time I want to play.
Is there a way to use Arduino to create an on the go stand alone piano. (It should work like a digital piano). Just switch on and play.
AI: You have many options here, although it is not as simple as you might think, if you want both a good sound and use an MCU.
Arduino (Uno) with speaker
Buy a MIDI shield and a MIDI cable
Write a sketch that reads MIDI note on and off commands (at least)
Connect a speaker to the Arduino
Extend the sketch to play the correct frequency based on the notes
Pros:
Reasonably easy
Very less hardware needed
Cons:
Very bad sound (like beeps, comparable to a toy 'piano' at best)
Monophonic
Arduino DUE or Raspberry PI
Get an Arduino Due at least (probably you can better move to Raspberry PI or similar device)
Sample a real piano (by key range, or velocity range), or get the samples from your DAW.
Read the MIDI on/off keys and decide which sample/velocity sample to use.
Add SRAM probably for the samples, or try to read it from a Flash (doubt it will be fast enough). For very good stereo multi-velocity samples expect a few GB.
Use a DAC to output the sound and connect it to some speaker system.
Note the above is a simplification
Pros:
Very good learning experience (if that is what you seek for)
Cheaper than a MIDI module
Cons:
Much time to invest (DACs, sampling, building your own 'synthesizer')
No MCU needed: MIDI Module
Buy a separate MIDI module where you can directly connect the MIDI cable to.
Pros:
No time to invest
Quality is as good as the MIDI module (much better than what you get on an Arduino at least).
Cons:
No 'learning' of Arduino
More expensive (MIDI module) |
H: VHDL using 'if' to compare a 'variable'
Using Xilinx, I need to compare a 'variable' called 'row', defined as:
variable row : std_logic_vector(2 * n - 1 downto 0);
This line was given to me, now I need an if statement that will execute if row is = 1.
I have tried:
if (row = "1") then
but the IDE warns me that this condition will always result in false? which should not happen.
If I try if (row = '1') then or if (row = 1) then then I get the error:
found '0' definitions of operator "="
Googling this, the only suggestion is to include libraries that I have already included:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
AI: Your variable is a std_logic_vector and you compare it to an integer. You have to cast the std_logic_vector like this:
if(to_integer(signed(row)) = 1) or if(to_integer(unsigned(row)) = 1) |
H: Can we reduce power consumption of digital interfaces by using high impedance transmission lines?
Transmission lines must be terminated with the same impedance as the transmission line has itself to get an impedance matching and avoid reflections at a high impedance end point. This termination resistance closes the current loop between two differential signal lines and creates a decent amount of power loss so that low voltage amplitudes are required to reduce power consumption.
But still digital interfaces use quite low impedance transmission lines like 100 Ohm in Ethernet communication.
Can we reduce power consumption of digital interfaces by using high impedance transmission lines with high impedance terminations? Because I don't know of any examples I assume that it is not a good way to go. If that is true, why so?
AI: While, in theory, high impedances would reduce power dissipation for the same voltage swing, there are several important issues in practice.
1) It's the power, not the voltage, of a signal that determines signal to noise ratio. If you must swing the full rail, then you'd win by increasing the impedance. However if you launch a specific power, then low impedance is not so much of a problem, just reduce your swing.
2) It's not physically practical to get impedances of much more than 100 ohms on a board. The signal conductor needs to get unmanufacturably thin, the space to the ground plane space-consumingly large. The impedance goes as the log ratio of spacing to centre, so you rapidly run out of improvement.
There are other reasons we like a fairly meaty centre conductor, as well as the fab being able to make it. The copper losses vary inversely with the conductor surface area (all the RF flows in the surface), and in fact 75 ohms is the lowest loss geometry (which it why it's used for receive antenna feeds). The highest power handling geometry is around 35 ohms, dependant on heating and surface electric fields. These two figures are why 50 ohms was chosen as a compromise between the two competing criteria as the 'standard' impedance for test gear.
3) In a high speed detector, input impedance is a critical parameter. It's easier to handle with a lower impedance line, for much the same geometrical reasons that you can't make a high Z line on a board, you can't really make a high Z line receiver IC. |
H: Wiring Nest Thermostat E Heatlink in place of original Thermostat
I have a Nest Thermostat E, which requires me to replace my thermostat with the Nest Heatlink.
Google provides step by step instructions on how to do this using a series of questions and answers. However, I'm struggling with a lack of knowledge.
Does your diagram have any of these labels for the common wire?
COM
Common
HCOM
No exact match
-> No exact match
Does your diagram have any of these labels for the normally open wire?
NO
NA
CALL
H ON
Demand
Call of heat
N/O
On
No exact match
-> No exact match
The common wire is always connected to one end of your switch...
I identified the brown wire (1) as the Common wire.
When your heating is off, the "normally open" wire is the one that
isn't connected to your switch
By my admittedly very limited understanding of this description, this could either be the Grey wire (2) or the Black wire (3)?
The instructions then go on to say wire the Common, and Normally open wires into the Heatlink E, and disconnect all of the others and cap them off.
So at this point i'm left with some questions I'm hoping someone here could please answer for me:
Exactly which wire I should use as the 'normally open' wire?
I recognise the Yellow/Green as earth/ground. Should this really be
capped off and not connected?
I like to learn rather than just do, so an explanation on why it may
be laid out like it is (Wire's 2 and 3 leading to the same switch).
Here are pictures of the current wiring and the diagram.
Thanks
AI: Google seems to be truly unhelpful on this one of their products.
Your existing thermostat has a live feed in at terminal 1, which is brown (as it should be) and the neutral is connected to terminal 2 (it should be blue, and is sleeved to indicate so), that is likely there for a function light. The switched output is at terminal 3, looks like that's a black wire.
So you need the brown to the C terminal and the black to NO.
Here's the only image I could find, from here
The E version is battery operated, so doesn't use any mains power. No ground connection or neutral are needed to the Heat Link, so those wires should be insulated and not connected. |
H: Syntax and/or best practice for buffering a vector in Verilog or VHDL
I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data.
Ultimately, these data need to go into several AXI slave register, since Block A is part of a larger AXI slave peripheral. A faster AXI clock drives another block (Block B) that handles the AXI transactions with the ARM core.
The sampling clock clocks the data into the Block A output registers, so these data are sitting there waiting to be placed in the AXI registers. (I think) I want some kind of multi-dimensional shift register to get these data into the AXI clock domain, something like:
...
input wire axi_clk,
input wire [5:0] data_in,
output wire [5:0] data_out,
...
reg [5:0] data_buf[2:0];
assign data_out = data_buf[2];
...
always @ (posedge axi_clk) begin
data_buf[2:0] <= {data_buf[1:0], data_in};
end
Instead of shifting one bit at a time every clock, I want to shift all 6 bits of data_buf in parallel each clock.
How should I set this up? Forgive the pseudocode; everything I've done so far has thrown errors, and I haven't found example code of what I'm trying to do, or confirmation that it's even possible with easily readable code.
PS - My team does not want to use SystemVerilog, but any version of VHDL or Verilog is acceptable.
AI: To transport a multi bit vector. in parallel, between clock domains you should use an asynchronous FIFO. There is no other solution.
Do not try to design an asynchronous FIFO yourself, you are not ready for that. Instead instance one from the IP library. (Select one with independent read and write clock.)
The alternative is to transport the data bit-by-bit between the clock domains, using a single bit synchronizer. You said you don't want to do that, but it is a lot simpler.
(For synchronizers look up the Xilinx xpm_cdc_array_single module or related cdc IP blocks.) |
H: Is EMC shielding of a grounding wire required?
Consider the following 2 use cases:
Fully electric vehicle with 2 different insulated voltage systems: 1 high voltage @1000V DC insulated from chassis and 24VDC system with minus pole (-) at chassis. Would PE cable (connected to chassis) need to be shielded? If yes, then why?
Single phase house supply system. Would the PE cable need to be shielded? If yes, then why?
In my opinion there is no need for shielding as these cables' sole purpose is to protect the people from indirect contact should any live part came into contact with metal exposed parts (that can be touched by people).
In short, these conductors are not meant to carry any signal/current (if not for brief periods < 1s), I don't see any reason for EM shielding.
Short clarification:
In question 1, the the chassis is ground (as in "return path") only for 24V system while metal parts of chassis of high power loads are connected to the chassis with a PE cable (as in "Protective Earth").
In question 2, consider a TT system, the PE cable is grounded.
AI: I see no reason to shield the grounding (return) that is connected to chassis.
As standard design practice, we twist the supply (hot) line with its return.
If there is a need for an overall shield around that twisted pair bundle, then the shield is connected to chassis at both ends. The only reason for the shield is if you were to have some conducted emissions (CEs) flowing as common mode currents on your twisted pair supply+return cable, that would then become radiated emissions (REs) from an unshielded cable. |
H: What do you do to help you grasp a concept or understand something you're seeing for the very first time?
Often in industry you come across a lot of different devices or even concepts you're seeing/hearing for the very first time. Things like encoders, resolvers, PID, pressure transmitters etc.
I would like to know what some of you guys do in order to quickly get a clear understanding of it and become a master at the subject matter.
Are there certain steps you follow or is it just random?
It would also help if you gave an example of a time you saw something for the first time and the steps to you took, and how long it took you to master it.
I'm not sure if this is the right platform for this but I'll take my chances anyway. I'd appreciate any positive feedback.
Thanks!
AI: The theoretical concepts you hold in your head are everything. And the more widely applicable they are, the better. Concepts that can be applied across dozens of disciplines are much better than concepts which apply only in a narrow circumstance.
This is an important point to understand: You cannot see something if you don't have a theoretical concept in your mind for it. For example, you cannot even recognize or observe evidence that the world is curved like a ball, if you don't have any concept of spheres or curvature already in mind. We cannot notice that for which we have no concepts to apply.
Some people have muddled ideas, which they are able to make work for them. But they aren't terribly good for you to learn from. For example, prior to and around the time of Galileo, many felt that the propensity of something to sink or float in water was at least in part because of how sharp it was. Knives sank because they cut the water. A log floated because it didn't have an edge to cut the water nearly so well. This idea kind of worked and helped explain observation. But it was quite muddled.
During a debate on this topic, Galileo had prepared for himself some wax and metal filings. He shaped it into a cone, as he added metal filings. Eventually, testing showed him that the wax cone was finally neutrally buoyant. At this point, he made a demonstration using a deep bowl of water. He placed the cone, point-first into the water very slowly and eventually released his hold. The cone floated. Then he removed and inverted the cone's orientation and lowered it into the water until only the tip remained, when he again released it. The cone sank. He then asked the audience to explain why, if the idea of "cutting water" was important to sinking and floating, that the cone floats with the blunt end down and the cone sinks with the sharp pointed end down.
Now, Galileo didn't muddle his question with the idea of surface tension. I'm not even sure he was aware of it when considering this demonstration. But that's not the point. The point here is that he was challenging an idea that others held and was able to come up with an experimental test to make the point.
This is the kind of sharp thinking about the world that you want to watch, study, and learn from. Not the confused ideas by people who don't attempt to challenge their ideas, but instead only argue for them without struggling to find a way to disprove what they believe.
Seek out the work product of the very best you can find (and I'd definitely recommend reading what you can grab from Galileo's writing -- he was even able to anticipate atomic bonds!) and learn to see as they see the world. Don't assume they are always right. Galileo's test above didn't account for surface tension, for example. (But that wasn't its point, either. He wasn't providing a theory, he was challenging a different one.) Most of what the best of us think about the world is probably wrong, anyway. It's not the conclusions you are after. It's how they think that you want to study and learn from and acquire, where possible.
You should also look for concepts which can be applied in a variety of circumstances, using different slices of the idea when facing different slices of the world around you. So a good teacher will usually express ideas in a variety of different perspectives in order to help convey to you the fuller notions -- which cannot be gained by only one slice or perspective but require multiple viewpoints in order to acquire.
I also think a good teacher will let you struggle for a while on your own. What's the point of just handing you the theory that this oddball concept we today call density, the mathematical ratio of mass (another oddball concept, different from weight) to volume, so that you know why things sink or float? If it is just given to you on a silver platter, how will you learn to think on your own?
A bad teacher, attempting to allow students to uncover this idea of density, might use a variety of objects that all have the same volume but different masses. Students playing with these, in water, would only discover that heavier things sink. They would not discover this special ratio I mentioned above. So there are very bad ways to teach. Be aware of these.
Find people who have been around the block on a subject and are willing to talk about how they see things. Find books that are well-recommended by such people. And use your own head, too. Sit down and apply what you learn so that it deepens inside of you and becomes a part of how you see.
Textbooks written earlier in a topic's development will usually do more explaining than more modern books, which focus on increasingly more narrow perspectives as they expand into minute details of continuing interest. So, I will often look towards earlier texts. An example is that if you want to understand compilers and operating systems, it is probably better to look to earlier textbooks (say, from the late 1960's to the early 1980's.) This is because they don't assume much about the reader and will take you for a gentle, longer ride. The best books on compilation (for me) came from DEC in their books on the PDP-8 and PDP-11. The best book I know of on operating system design comes from Douglas Comer's 1983 XINU book. (His later books are not as nice to read.)
That's about it, for now. I have to leave for a bit. Just thought I'd throw that out.
Another approach is to find someone who has written a paper on the topic and then write them. I've often found them quite willing to share, when someone expresses an interest in their field. |
H: How can there be a current without a voltage?
Recently while trying to understand inductive AC circuits better, I got very confused with a question.
Let's suppose we have a purely inductive AC circuit with ideal wires and a switch. Let's also suppose that whenever we close the switch of our AC circuit, at time \$t=0\$ our voltage cycle starts from 0 i.e. \$V(0)=V_0\sin\omega (0)=0\$
But generally we are taught that that in a purely inductive AC circuit, the current lags voltage by 90 degrees. That implies even at time \$t=0\$ we have a maximum negative current. We can also have a look at the current equation \$I(t)=I_0\sin\left(\omega t-\dfrac\pi 2\right)\$ which says at \$t=0\$ the current is not 0.
So, my question is that (physically speaking) how can a current exist at t=0 in such a circuit even without a voltage?
Moreover the circuit was previously disconnected so how was the current increased in the first place?
I searched and found this EE SE post but I'm still confused. I understood the energy argument put forward by user Dave Tweed's answer and I'm okay with the fact that at \$t>0\$ it's possible for either \$V\$ or \$I\$ to be 0 at times but what I'm unable to get why is there a current even at t=0 when instantaneous voltage is also 0.
Thank you so much for your help.
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. Test circuit. L1 has 1 Ω ESR. SW1 is set to close at t = 1 ms.
Figure 2. The resultant voltage and current curves at the top of L1.
So, my question is that (physically speaking) how can a current exist at t=0 in such a circuit even without a voltage?
You can see from the simulation that \$ I_{t = 0} = 0 \$. You can also see that there is a curve at the start of the current trace and that the trace is biased positive when the voltage is switched on at 0°. You can play with the simulation to try different time delays on SW1 to see the effect. You may also play with the ESR (equivelant series resistance). I added 1 Ω to make a realistic inductor as I wasn't sure how the simulator would handle an ideal one.
Moreover the circuit was previously disconnected so how was the current increased in the first place?
It wasn't.
Remember that the 90° phase shift applies in a steady state. Switch on and switch off will be transient conditions. |
H: LTspice, plotting a node voltage problem
Edit: The question is answered in a such way that I am happy now, however for the interested ones, the mystery of the question is still on.
These two are the parts from my circuit, related to the question.
Now, I want to be able to plot V(pnp_c), however it does not allow me to choose it. You can see from the above list that there is not such quantity as V(pnp_c). If I remove -9v label, then it allows me to select it. You may say that "they are essentialy the same point, they are at equal potentials, why bother?". My answer to that is, while simulating the power of the pnp by ALT + left click, Ltspice formulates it so that it will depend the value of -9v label as follows:
Please note that npn power expression is independent from V(+9v) instead it is related to npn_c which is nice.
The problem starts here, If I want to change the power rail to another value, by directly connecting a voltage source, or by changing it with another label, then I also have to replot the power on the pnp. However, if it were be using V(pnp_c) instead of V(-9v) then this problem would have been eliminated.
I wanted to think that it just don't accept two nodes with different names and it chooses the constant voltage one, however as you can see from the above picture, for npn, the arrangement is the same but it does not create a problem and recognises npn_c as a node. Things get more confusing at that point.
So, why I am able to choose npn_c as a node but cannot choose pnp_c ?
AI: Like Michael Karas already answered and LTspice also states in its help file:
Each node in the circuit requires a unique name.
Still, playing around with labels on the same node seems to reveal that
LTspice prefers the bottom labels above the top labels in a schematic (first rule)
next, LTspice prefers right side labels above left side labels (second rule)
LTspice picks the label that fits above rules best and uses that name as node name
order of placement or alphanumerical order of naming is not relevant
(what OP also already discovered) you can still use the other (less preferred) label name to refer to its node (in the waveform viewer as well as in behavioral sources, etc)
So, in your case -9v is lower than pnp_c, so -9v 'wins' becoming the final node name.
And npn_c is lower than +9v (first rule, despite it is more to the right side (second rule)) , so npn_c 'wins' becoming the final node name.
The ugly way to solve your issue is swapping -9v and pnp_c in vertical order.
A better way is not connecting several labels to the same node, but insert a component between the labels instead.
I found that inserting a jumper will not show 2 different node names (despite the description suggests).
Inserting an e.g. 1mΩ resistor between the labels -9v and pnp_c would work (same applies to other labels on the same net). |
H: Explanation for Method of Monitoring Current from a Power Supply
I recently came across an interesting way to monitor current, but was not certain exactly how it works. Likewise, I was hoping that someone might be able to explain how the device measures current.
The object shown in green is a High Voltage Electrostatic Precipitator capable of putting out a maximum of 30 kV and 10 mA (however, the designer stated that the load will usually only draw 1-3 mA).
Going from left to right, the first voltmeter is used for measuring the current off of the positive lead (the other voltmeter uses a voltage divider to find the voltage, but that section is irrelevant to the question). What is interesting is that the device is, in fact, a voltmeter rather than an ammeter. The voltmeter is set to roughly 3000 mV DC.
What's more interesting is that the readings (in mV) provided by the left-most voltmeter provide the exact number of milliamps that the load (shown as the box below the ballast resistor) is consuming.
Likewise, I was curious why this is and what math may be behind this effect?
AI: The 10 ohm resistor is simple acting as a current to voltage converter since it is in series with the load. By Ohm's law, the voltage across the resistor in volts is simply 10 times the current through the resistor in amperes. However, the conversion factor is such that the current in milliamperes will be 1/10 the voltage in millivolts since the value of the resistor is 10 0hms. |
H: Will swapping the input terminals on my op amp give me a negative reference voltage?
I am using an AD8031 op amp which outputs a 1.6V reference voltage with the circuit in the picture. I am powering it using 3.3V. I thought the output would be negative since the feedback is negative.
How can I get a negative voltage output? Will swapping the input terminals accomplish this?
AI: Two points:
Negative feedback adjusts the output so that the inverting input voltage matches the non-inverting input voltage. Since the non-inverting input is at half-supply the output voltage will be too.
Figure 1. Internals of the ancient 741 opamp. Source: Wikipedia.
From the internal schematic of the 741 op-amp it should be clear that the output can source current from the \$ V_{S+} \$ rail via Q14 or sink current to the \$ V_{S-} \$ rail via Q20.
In general, op-amps output stages are configured similarly to the bad-old 741. If the upper output transistor turns on the output is pulled towards positive rail. If the lower transistor is turned on the output is pulled towards the negative rail which is 0 V in your schematic. It is not possible to generate an output voltage higher than the positive supply pin or more negative than the negative supply pin.
How can I get a negative voltage output?
You can't with that circuit. You need a negative voltage power supply or DC-DC converter.
Will swapping the input terminals accomplish this?
No. This should be clear by now. |
H: Allowable current in Ni-Cr 80 20 gauge wire?
I am creating a small oven for curing composites out-of-autoclave, and have some Ni-Cr 80 20gauge wire lying around. I need to put up to 8.6 amps through the wire at maximum. The current is controlled with a PID bang-bang controller, so the duty cycle is not 100% at that current.
I know that 20 gauge Cu wire is rated for ~7 amps, but since Ni-Cr has a higher melting point I figured I might be able to get away with using my left over wire. The one problem that might knock down the amount of amperage allowed even further is that the ambient environment of the furnace will be at 200 C at maximum steady state conditions, but the duty cycle on the wire will be much lower than on ramps up to steady temperature.
Any insight would be greatly appreciated.
AI: You can elevate the wire to Operating Temperature: 900°C
I believe this is a visible red temperature of heat energy levels. The closer the temperature is to melting temp, the more fragile it becomes.
Melting temp: Ni-Cr 1400'C , Cu 1100'C
For straight wire at room temp:
No. / AWG) 204 °C 316 °C 427 °C 538 °C 649 °C 760 °C 871 °C 982 °C 1093 °C
20 3.58 4.77 5.92 7.25 8.86 10.69 12.72 15.43 16.87
The ambient temp of 200'C means you subtract 175'C then with a coil wire the heat rise per amp may be another 50'C. More insulation could increase this even more.
The bottom line is the wire temperature margin below melting.
Thus 650'C +250'C looks to be very close to the 900'C ideal working temp but geometric thermal resistance will affect your results. |
H: Name of connector that connects wires to washer drain pump
I was sent here from https://diy.stackexchange.com/ as they said connector identification is quite common here.
I'm looking to replace a connector that connects to my washers' drain pump.
I first suspected the drain pump to have gone bad, but it looks like the wire itself was burnt or sheared off. I was going to splice the wire back together but figured it would be better to replace the connector all together.
I've attached some pictures to help identify it.
The washer is an Amana NTW4516FW1
AI: I know this is not the answer you're looking for, but I'd just splice the wire back together unless you have a reason to think the connector itself was part of the problem. Someone here may be able to tell you the general name of the connector, or maybe the exact style or even a part number, but you could spend a long time finding one, and possibly for more money than you think that small thing is worth.
Also, many connectors of that sort require a tool to insert the contacts into the plastic housing. You don't have one of those, so unless you get a connector with leads attached you still have a problem. And then, what connects to the other end? A different connector?
If it were me and I was forced to replace the connector I'd check out the appliance repair shops or someone junking a used machine. I'd also try to determine what happened to the wire to assure myself that it was not going to happen again after the repair. |
H: How to design a transimpedance amplifier that can adjust to large voltage swings?
I am making a photodiode sensor based on one show in the image below which I got from this research article. The problem I run into with my photodiode sensor is that variations in sunlight create amplitude swings that are too large. The circuit shown claims to be able to solve this issue.
How does this sunlight adjustment work, and what is this type of circuit called?
AI: It's can be described as a log-responding AGC linear-optical TIA PD detector.
AGC: Automatic gain control
TIA: Transimpedance Amp.
PD: Photo Diode
The negative feedback voltage controls the collector current to shunt the PD current and increase the gain when the output (pin 7) rises above 2.5V then Vbe is reduced with Ic shunt and thus higher gain.
The inputs are all biased to Vref=Vcc/2.
The PD's have a negative linear gain but the output is integrated towards the the average voltage of Vcc/2. Q1 has a log Ic vs Vbe response.
Thus the TIA has a wide dynamic range with a long time constant (R1C5=5.6ms) and a linear response at fast response (R2C1=125ns) for small signals. |
H: Microcontroller Always ON domain
I have a question about the MPC5606S Microcontroller.
I have very minimal software knowledge and only want to understand in hardware perspective.
On page 68 of the MCU datasheet, we have a block diagram which mentioned PD0 Always ON domain.
But in this Reference Manual of the MCU, on page 1235, the block diagram mentions that this Always ON domain have wakeup input pads.
What are the ports/pins of the MCU in the Always ON Domain?
(Are the Always ON domain pins the same as mentioned in Table 41-1 on page 1238?)
Can't we have any output ports in the Always ON domain?
Is it necessary that I have to connect it in one of the pins in PD0 Domains if I want to drive a PWM output during Mircocontroller sleep condition?
AI: Always on domain: Power is present.
Wake-up pads: Wake the MCU from sleep mode.
The reference on the first datasheet, always on domain, means the electronic is always powered. You cannot selectively power-off this section.
The wakeup pads are for waking up the device from sleep mode (MCU).
Sleep mode and power are two different things. Power means you physically have a voltage present, while sleep is that the CPU, Memory, and others while being powered, doesn't do anything to save power.
PWM During sleep mode will really depend on which MCU you are using. You need to find MCU which contains a hardware PWM module that can operate during sleep. Some MCU has this functionality like the PIC family from Microchip.
Another way to generate a PWM during sleep is to use a GPIO and a timer, set the timer so that the device wakes up each time the pin state has to be changed, this will likely be less efficient than the solution above. |
H: What type of pin in this (see picture)? I see them in FSRs but they don't appear to be Dupont connectors
Here are the images of the pins:
And here is the FSR that it came from:
AI: They appear to be some form of pins used in clincher connectors |
H: What is RS-485 and MODBUS?
I understand the title seems too broad but it's a bit specific and I'm totally new to the communication stuff, so please bare with me. If the question is too broad, please provide some suitable links that I can look upon.
Now I'm given a simulator pyModSlave and a USB driver, that has two output pins.
I've a MAX485 (to be honest, I'm completely lost as to what this does)
and an ESP32 .
Task given:
Interface ESP32 with RS485 annd run ModBus library of Arduino IDE with RS485.
Questions:
What is the difference between RS-485 and MODBUS?
How does data get transmitted in this type of system? For example, say I've a temperature sensor, that gives out data in RS-485. What does this mean? All I know about transmitting data is as a binary number as 1s and 0s. What does MODBUS do in all this?
AI: RS-485 is a standard defining electrical characteristics of a serial link. It dictates electrically how multiple devices can send 1's and 0's to each other over a differential bus. What voltage levels represent a 1 and a 0, Impedance of the cabling, etc.
It doesn't define the protocol - i.e. when devices should talk to each other, what they should say, what the 1's and 0's mean. For example, you could send this:
110011011100001
But it doesn't mean anything without a protocol defining how to interpret it.
MODBUS is a communications protocol. It defines what devices should send to each other and when. There are set of rules that devices must obey in order to ensure they are interoperable.
I'm not going to go into detail on the protocol in this answer as there are hundreds of resources online, for example this document from the MODBUS organisation themselves.
In the case of serial transmission over an interface such as RS-485, you will likely be using the "MODBUS RTU" protocol, which is specifically designed for serial links.
I've a MAX485 (to be honest, I'm completely lost as to what this does)
It's a TTL UART to RS-485 Converter, to allow single-ended logic level signals (such as those from a microcontroller IO pin) to be electrically interfaced with an RS-485 bus. |
H: I want maximum 5V output from an Op-Amp. Is it a good idea to use a supply voltage for the Op-Amp of more than 5V?
I have the following circuit.
An Op-Amp (currently TLC2272CP) as a buffer (voltage follower). The non-inverted input of the op-amp comes from a DAC (MCP4922). I measure with an ADC (MCP3202) the input voltage of the Op-Amp and I measure with the same ADC the output voltage.
Currently I use 5.0V supply voltage.
For testing I set the DAC to a fixed voltage for a few seconds.
My goal is to have exactly the output voltage at the Op-Amp output which I set with the DAC independent of the load (max a few mA).
The desired output voltage will change slowly (less than 1Hz)
My testing shows: If there is no load on the Op-Amp output then the output voltage is equal to the input voltage almost for the full range from 0V up to 5V. This is what I expected.
But with a load (initial test with a 2.2kOhm resistor to V+ or GND) the output of the Op-Amp goes only to a maximum of about 4.1V.
I looked at the data sheet of the Op-Amp and it shows a High-Level output of minimum 4.25V with a load of 1mA.
I want to be able to get nearer to 5V. Probably something like 4.8V is good enough.
The ADC and DAC allow max 5.5V supply voltage. That Op-Amp allows up to 8V supply voltage.
I guess I won't be able to do this with these parts and conditions. My idea is to use 6V or 7V supply voltage for the Op-Amp and continue with 5V supply voltage for the ADC and DAC. I guess with the higher supply voltage for the Op-Amp it should be no problem to reach 5V output, even if the output current is a few mA.
My question is: Is this the proper way to do this? Or what should I do to have output voltage, with load, of at least 4.8V?
And when I use a higher supply voltage for the Op-Amp I have to make sure that the output voltage is never higher than 5V. Because I don't want anything higher and a higher output might destroy the ADC which measures the output voltage.
Currently my idea is to use a Zener diode to make sure the output is never higher than 5V (also not when the circuit is just switched on). Is that a good way to do this?
AI: You have two problems. Firstly, you are quite correct, the output voltage achievable from a 5 volt rail is limited to circa 4.25 volts with a 1 mA load and, to improve this you can raise the positive supply rail a volt or so.
The 2nd problem is that the input common mode range is limited to only 4 volts (page 6 of data sheet) and, given that you are operating the op-amp as a unity gain buffer, this is likely to be the problem actually seen when powering at +5 volts DC. However, this will improve if you run at a higher supply.
And when I use a higher supply voltage for the Op-Amp I have to make
sure that the output voltage is never higher than 5V. Because I don't
want anything higher and a higher output might destroy the ADC which
measures the output voltage.
You might be able to use a series resistor in your ADC input to limit the current to an acceptable value. Read the ADC data sheet to check. Else, I would use a schottky diode from the op-amp output to the local 5 volt rail of the ADC. A zener could be used but they tend to be a little leaky below their clamping point and may not quite be good enough for what you want.
Also, the op-amp you have chosen is not that great on input offset voltage but, if you are content with a standing error of up to typically +/- 1 mV then that's OK. |
H: Resistor ratings for inductor fly-back suppression
I am building a circuit for user to interface with relays, and I am trying to build a protection to the circuit against fly-back from the inductor coil of the relay. Since there is no specific relay it is quite hard to choose the parts. All that is certain is the relay must be 5V and draws up to max of 250 mA (my recommended limit), but a protection for higher amp rating would be better.
The protection in my circuit is a diode - resistor combo. with the diode being 1n4007 which is greatly way more than what I need (which is good). the resistor is a bit tricky and what I am not sure about.
Assuming from what I know about inductors, is that it is a current source, and the voltage will depend on the resistor.
Here is my computation
V = I × R
5 = 0.25A (largest 5V coil current I found) × X ohms
X = 5/0.25
X = 20 ohms
20 ohms is for my absolute max, but for lower current loads it could go up to 50 ohms + (assuming 5V is our desired voltage). I don't know which is a better safe side value — is higher the better or the opposite? My guess is lower, but how low a resistor that generates 1 volt?
On a similar note, the power rating required for this resistor:
P = I × V
P = 0.25A × 5V
P = 1.25 watts
1.25 watt resistor are hard to find on resistor values that low. Will a 1/4 or
1/2 watt resistor work since the current is not continuous and it goes down?
Please help me if what I know is correct, thank you.
AI: You are getting muddled.
It's not the 5 volts that is used to power the relay that needs to be factored in when designing a resistive flyback suppressor, it's the maximum voltage that your driving circuit can withstand under flyback conditions that has to be considered.
For instance, consider the situation of using an NPN (or N channel) transistor to activate a relay. When the relay is deactivated, the inductive 250 mA would produce a peak voltage of 25 volts in a 100 ohm flyback resistor. This means the collector (or drain) of the transistor would see a peak voltage of 25 volts plus 5 volts (30 volts).
Therefore, if the transistor has a voltage rating greater than 40 volts (a little added margin) then you would be good to go.
Regarding the power rating you don't need to pick a resistor that has a rating equivalent to the instantaneous value of the power surge; resistors are usually very good at handling largish short power surges so, if the flyback surge is done in less than 10 ms (fairly normal) then pretty much any quarter or half watt resistor will do the job. |
H: Is shared ground necessary?
I ask this mainly for curiosity and am not trying to make shortcuts for real projects.
I have a couple of devices (mcu development boards) that connect to each other using various communication busses. One of which is UART.
For normal situations, you need a common ground as reference as said here: https://stackoverflow.com/questions/27138706/does-ardunino-serial-need-a-common-ground
However, all my devices in my test setup get power from usb from the same computer. Accidentally, I disconnected one of the ground wires between two devices and everything remained working.
Is this just 'luck' or is it because the voltage source for all devices is the same?
AI: Yes you need a shared ground. The reason it works is because everything connected to your PC and share supply grounds. But it also means that the supply ground will be the reference to all your signals, which isn't ideal.
Ideally all communication lines include a signal ground, which is tied to the main ground of each PCB through appropriate PCB layout. That way you don't have to worry about the quality of the supply ground, where there could be ground currents messing up potentials, EMI etc. |
H: USB usage restrictions
I find it quite hard to find any information on how to deal with legal issues concerning the use of USB online. I mainly have two question I cannot seem to find a definitive answer to.
Is it required by law (US or any other country) to have a VID/PID combination that is registered with the USB-IF? If no, why would you still want to register one?
Is the trident logo free for usage without a Logo License Agreement (this logo does not appear in the logo usage guidelines)?
I tried to search myself using these sources but they offer no definitive answer:
https://www.usb.org/compliance
https://www.usb.org/logo-license
https://www.usb.org/sites/default/files/usb-if_logo_usage_guidelines_final_103019.pdf
https://www.eevblog.com/forum/projects/how-to-label-a-usb-port-(legal)/
https://www.quora.com/Who-designed-the-USB-symbol-Whats-the-story-behind-the-individual-or-group-who-designed-it-and-the-design-process-they-pursued
AI: Is it required by law (US or any other country) to have a VID/PID combination that is registered with the USB-IF?
It is required by the license agreement, which is a kind of contract. It becomes a matter of law only in the sense that most countries have laws that cover contracts.
If no, why would you still want to register one?
Because you want your device to be recognized as being distinct from all of the other devices that are already out there. And all of the other device manufacturers want that, too.
Is the trident logo free for usage without a Logo License Agreement (this logo does not appear in the logo usage guidelines)?
No. If you put the logo on a non-compliant device, this will cause harm to the USB community at large. They will come after you in order to protect themselves. |
H: A really basic question about ammeters and their ranges
I was performing a basic verification of Ohm's law in a DC circuit experiment the other day, during my exams and I mistakenly used an ammeter with range 0-10A instead of the 0-1A ammeter that the practical manual expects us to use.
The invigilator/examiner noticed this error and told me that this is a really bad error on my part and this will not be forgiven. She cut half my marks just because of this small error(?). I retorted by saying that it shouldn't really matter, because all I am doing is just reading the current value in the circuit and the range of the ammeter used won't affect that value. She said that isn't the case and the range of the ammeter WILL affect the current reading. I didn't know much of the specifics about the working of an ammeter, so I just ignored her. I don't even care about the marks too.
All I want to know is whether the range of the ammeter affects the current reading shown by it? If possible, I also want to know how the current value is affected just by swapping it out with an ammeter of a different range.
I looked up the working of an ammeter and I found that an ammeter is just a galvanometer with a resistance in parallel (I don't understand what they mean by parallel). Maybe the resistance increases the overall resistance of the circuit and hence leads to decrease in current(?). Please let me know if my speculation is correct or not. Thanks in advance for tolerating my zero knowledge of the subject :)
AI: I looked up the working of an ammeter and i found that an ammeter is just a galvanometer with a resistance in parallel
We call this the shunt resistance of the ammeter.
The difference between the high current range and the low current range is that the value of this resistance is lower for the high current range.
If the circuit you're measuring has a relatively low impedance (less than maybe 20x the shunt resistance) as measured from the points you connected the ammeter, then the choice of range will affect the measured current.
But using a higher range will actually give you a more accurate result, because its lower shunt resistance will affect the measured circuit less.
(On the other hand, the result will be less precise because each step of the ADC in the ammeter will correspond to a larger increment of current)
In comments you added,
it is a digital meter
In this case, there's no actual galvonometer in your meter. But just the same, the principle is to measure the voltage across a low-valued shunt resistor. And a larger shunt resistor is needed for the lower ammeter range, leading to the same result: The higher range affects the measured circuit less than the lower range. |
H: Calculation of Relay current
I am using Relay OJE series SPST and I want to drive the relay with V=5v and the resistance through the coil is 125 ohm. From microcontroller 3.3v and 1k resistor. The NPN type is BC817-25 and the max hfe/B is 400.
What is Ib, Ic? And how much current goes through the coil? To make sure my relay type is ok and can handle the current!
AI: The BJT can't pull its collector below ground.
Instead it will go into saturation mode with \$V_{ce}\$ in the neighborhood of 0.2 V. So the voltage across the relay coil will be around 4.8 V. And the coil current will be about 40 mA.
If you buy a 5 V relay, this will be exactly what it expects and it will work accordingly. |
H: LED driver: how to choose current and voltage?
In my project I have a microcontroller which has to light 3 groups of LED. Group A has 3 LED, Group B has 2 LED, Group C has 1 LED. There are all the same LED. In each group the LED are in series.
Let's consider group A :
VCC is obtained from a positive voltage regulator. The lighting of the group is controlled by an MOSFET which acts as a switch. The microcontroller is driving this transistor open or close.
I have never done this before so I have questions :
How do I know which voltage I have to appply with the regulator for each group? Is it the sum of each forward voltage ? Let's consider each LED has a forward voltage of 3 V. I would then need to apply 9 V, 6 V and 3 V?
Do I need a series resistor in each group?
How do I know the current which will be drawn by the LED in each group? How do I set the current to 1 A in each group for example?
AI: A schematic would definitely help. In general, LEDs don't regulate the current themselves, so you'll need a way to bias them. Most simply this is done with a series resistor. For instance in your group A with 3 LEDs and 3V forward drop across them, would give 9V across the LEDs as you mention. You'll need the regulated voltage to be greater than that, let's say 10V for starters. This would give 1V drop across the series resistor. Choose the value of resistance to set the current.
The higher the voltage used, the less susceptible the circuit is to differences in component parameters, but will dissipate more power. With that in mind, you'll have ensure that all parts meet the power requirements as you mention 1A through the LEDs, which is quite a lot using this method. With that amount of current, maybe consider using an LED driver chip. |
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