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H: Jitter measurement in High speed serial link - Random jitter mean not 0
I made some jitter measurements of my high speed serial link yesterday. Now i'm analysing the jitter sources, and found out, my random jitter is often not around zero, most time about -1 .. -0.5ps.
What's the reason for a not 0 mean of the random jitter?
The pictures show a plot of the random/periodic jitter and the total jitter.
The scope cannot give a seperate plot for random jitter and periodic jitter, but the second should be similar to a dual dirac function, so symetric around 0. So why is my RJPJ not around 0?
The TJ is a convolution from RJPJ with Data dependend Jitter(DDJ). DDJ is caused from a PRBS-7.
Edit:
I am measuring differential transceiver of a fpga, connected by two skew matched cables. There is no "known" asymmetry in my measurement. If this would be static asymmetry, every measurement would have been an equal RJ, i think. I have a 16Gbit/s NRZ signal, the cables are rated up to 18Ghz, the connectors on the Board 12GHz.
AI: A non-zero mean implies your sync clock has a constant phase offset error. from some source. ( computation error? mixer error?)
Bit edge-shift can be caused by many things:
Pattern dependent bit shift, assymetry f/BW ratio
Non-linear phase shift or non-flat group delay in the passband of the channel
asymmetry in the data pattern
aliasing in the measurement system with data rate
path length echos from return loss.
logic skew in prop delay
non-sine or non-random noise in clock PS
etc.
Can you elaborate on the system parameters and tests variables?
You can report back on which were relevant or which items you can control by changing each variable and create budget of jitter for each source in order to improve BER or Bit rate. |
H: Circuit rewriting
I am trying to find the current flowing through the 2 ohm resistor in the circuit labeled (A).
To do this, I tried to rewrite the circuit entirely but I think I got it wrong at (C).
I know I have to use Kirchhoff's laws, but I simply don't know where to start.
Thank you for any help
AI: simulate this circuit – Schematic created using CircuitLab
Your transformation to B seems fine. From there it should be simple to calculate x using V = I * R and solving for x.
Since I suspect this might be homework just one last hint: Assume I1 = I2 + I3. The current flowing through R1 is the sum of the current flowing through R2 and R3 (and x < 12V).
Be careful of the direction the current is flowing in that scenario. If it later turns out x > 12V then one of I1, I2 or I3 will be negative. Which just means the current across that resistor flows the other way than assumed. The result will still be valid. |
H: Flyback converter - turn ratio
I'm building a smps using flyback topology with maximum aoutput voltage of 46V. I'm a novice, however I have read a lot about impulse power supply design. Right now I'm about to buy a transformer, and the one I want to buy has output voltage specified for 19V.
From what I understand, the transformer ratio in such a converter doesn't have to be exactly Vin/Vout, because Vout is determined by the duty cycle on primary winding.
Is that right? Is it possible to obtain 46V in this topology when Vout is only 19V?
AI: Short answer: Depends on what the transformer specs and what your requirements say. But I personally don't recommend it.
Long answer: The transfer function of the converter: Vo = N . Vi . D / (1-D), where D is the duty-cycle (D = ton. fSW).
There is always an input voltage range defined for the transformer and its design should guarantee the required output voltage at minimum input voltage. And generally, it's assumed that the D is nearly 50% (0.45 - 0.47 in practice) at minimum input voltage.
For example, if the transformer is designed for 85..265 Vac (or 120..375 VDC) then this means that the output voltage will be 19 VDC and D will be nearly 0.5 at 120 VDC input in a proper designed flyback converter. Thus, if the input goes to 310 VDC (i.e. 220 Vac) then D decreases to 20%.
Now let's think about this:
The maximum value of the D should not exceed 0.48 in practice. If you want to increase the output to 46 VDC then new value of the D will be D' = D . 46 / 19 = 2.4D .
What's the maximum value of D'? 0.48
What's the nominal value? 0.48/2.4 = 0.2
At what input voltage D will be 0.2? 310 VDC
So, if you guarantee that the input voltage will never go below 310VDC then yes, you can use the same transformer to get 46 VDC.
Please take the assumptions above into account. So please check the specs first. |
H: Operation of tuned collector feedback oscillator
I am trying to understand the following tuned collector feedback oscillator extracted from here using LTSpice. I understand that L1 and C1 creates the resonance at the oscillation frequency and L2 provides the feedback.
However, The voltage at the output (V(C3)) is not sinusoidal as expected. Please refer to the following waveform.
If I understand it correctly, transistor goes to saturation (edit: because of high gain).
When capacitors C2 and C4 are removed (as suggested in comment), output become close to sinusoidal (refer the following).
I am not sure why the circuit behave this way, and what is the need of C2 and C4?
AI: The type of oscillator you are simulating needs careful consideration to get anywhere near decent sinusoidal performance. In its simple form you will never get a great sinewave purity because the output waveform has nothing other than the power rails to control amplitude. Yes you have feedback to make it "sing" but there is no active control element that can make the amplitude stable AND keep its output sinusoidal.
So currently, the output "hits" the power rails (one or the other or both) and this controls the output amplitude by limiting/clipping.
However, your simplified circuit has too much positive feedback for "adequate" performance. Look what I've done below; L2 has reduced to 0.01 uH and I've added 10 ohm in series with the main collector inductor (for realism): -
But still, the output is "hitting" the bottom limit and clipping because.... it needs something that can stabilize the output amplitude.
This can be achieved with a JFET in series with the feedback to the base. The standard way is to rectify the output level to get a "measure" of the output amplitude then use this "measure" to control the JFET so that it starts to lower gain as amplitude rises above a certain threshold.
It can also be done with diodes and here is my attempt: -
Now you have about 10 volts peak to peak and much better sine wave purity: -
Diodes used were 1N4148 but any fast recovery signal diode should be OK. |
H: Feeding a PCB dipole with single ended RF signal
As suggested how do you feed a Dipole antenna with single ended RF IC. I found tons of examples single antenna Line feeding a differential RF port on IC but not other way round.
What I want to do is feed a PCB DIPOLE antenna with singled ended feed from the IC and match the impedance. I have considered using a 50:75ohm Balun in reverse as per the below image but not sure this will work.
If I can use a discrete component only solution that would be great as well.
Any reference or advise would be great.
Freq 868Mhz.
IC RF line 50 ohm impedance.
Dipole antenna needs to be fed with 71,3ohm impedance.
Each leg of the Dipole I have as 82mm in lenght (164mm overall)
https://www.mouser.com/ds/2/611/JTI_Balun-0900BL15C050_2005-06-263841.pdf
EDIT: Using this circuit design with either a 50:50 ohm, or a 50:75 ohm Balun and matching accordingly ?
EDIT: To be as discrete as possible my current dipole feed circuit looks as follows, the device will be used to match the 50 ohm micro strip to the 73 ohm Dipole feed. any suggestions
AI: First, make a stubline/series trans line matching circuit to match your 50Ω to 71Ω:
The lengths you need result from reading the ratio of \$\lambda\$ from a smith chart.
After that, you could implement a Rat-Race Coupler in PCB technology, matched to your 71Ω source:
In the naming above, you'd feed in your unipolar signal at P1, and attach your dipole to P2 and P4. (omit P3, or terminate it to ground with 71Ω – if your dipole is well-matched, the power leaving P3 should be 0.)
To give you a feeling of the sizes involved:
a \$\frac\lambda4\$ piece of microstrip line is 45mm long on 1.6mm thick FR4 (assuming an Er=4.7 and 35µm copper), so you your rat race ring would need to have a circumference of ca 275mm, corresponding to a diameter of 87.5 mm. That's not really small – but if you have PCB to spare (or can elegantly route this around your whole circuit!), that's a nice way of going at this.
If you need to save space, you need to be smarter about the rat race: You might want to replace the transmission line \$\frac34\lambda\$ element with an actual RC (lowpass!) that is equivalent in phase shift, for example.
Another option would be to go for a Wilkinson power divider (which is only \$\frac13\$ of the size), followed by a \$\frac\lambda2\$ phase shifting network on one side only. |
H: DALI Click Board: Not clear about the board operation, usage and circuit design
I am developing a DALI Control Device using STM32 board. I have already programmed the board to send DALI Slave commands according to DALI Protocol. But I am facing problem interfacing my board with DALI PHY Board called DALI Click.
DALI Click circuit design is given its datasheet as follows:
There are two problems for me regarding this board;
I could not understand exactly what is happening in the Red marked zones 1 & 2 design wise. I can see the green marked zone is the current limiting circuit but to what value exactly? What is the PHY_SEL pin? How to use this?
I am rather getting a perfect signal according to the protocol from stm32 transmitter pin (Tx Pin). I have tried connecting the two boards as given below left the pin PHY_SEL(CS) open!
I am not getting any signal from the DALI+ and DALI- pins
Is my pin configuration correct? Why is there no signal coming out of DALI bus pins?
PS: Default jumper positions are as per circuit diagram given above.
EDIT:
I have essentially followed this complete setup, I am not getting any signal out of DALI Click board. I have two of these boards and have tried with both of them. I have tested the DALI RGBW LED with WAGO module as well, it is working fine. The problem is no decent signal from Click!
I did not extend this setup to my STM32 board but I have connected STM32 board to DALI Click as per the described pin configuration
AI: Zone 1 of this circuit diagram is a linear voltage regulator. It is used to provide a stabilised supply to the rest of the circuit from the incoming DALI signal. The diodes are necessary so that you can use a large capacitor on the d.c. supply without affecting the DALI signal.
Zone 2 of this circuit diagram is the DALI transmit circuit. After opto isolation, it uses a FET which is rated to sink the full DALI power supply current so that the line can be pulled low, this is how DALI works. The pulses are produced by not pulling the line low so that it goes high due to the power supply. The capacitors should limit the rise/fall rates to meet the specification.
The green zone of this circuit diagram is for constant current in the opto LED of the receiver over the range of voltages that are allowed for a "high". It is not a current supply to the DALI bus.
The PHY_SEL pin is just a button with a pull up so that the micro can use this for the "physical selection" method documented in the Ed 1 version of the standards (see commands 269, 270, 267) but has been obsoleted in Ed 2.
It looks like your pin selection is correct, but I don't see in your schematic where the DALI bus power is coming from. You always need a (nominally 16V) current limited (8-250mA) DALI bus power supply which transmitters modulate to produce the signal by pulling it down. |
H: How to solder PCB?
I have maybe question because of my first PCB I soldered yesterday.
I used a 2x8 cm PCB, and this is the circuit I did:
A I J K L M N
o-- -D1-—o--SW1--o---VCC o
| D1 SW1 REL
Ad 5V X---o D1 D2-SW1--o---CH1 o
| D2 | REL
X o R1 D2—-R2 R3 GND o
R1 R2 R3 |
X o R1 o R2 R3 o o
R1 R2 R3 |
Ad GND X---o R1 o R2 R3 o o
| R1 R2 R3 |
O-- -R1--o---R2--R3--o o
A .. N are the columns of the PCB, I leave column B..H free for future additions (the VCC and GND lines are connected)
Dx are diodes, Rx are resistors, SW1 is a pin header for a switch and column - Column N is a pin header for a relay (module).
X are the connection 'terminals' of the PCB (on the left/right side, right side is unused)
However, during soldering, I noticed a few things and wonder what is best:
I had a lot of soldering to do from one hole to an adjecent hole, and sometimes more like the connection between SW1, CH1 and R3 (colums K, L, M). Since I used just soldering, it was like a big 'solder blob' ... is it best to use some small wire instead? It will be very tiny wire(s)
For the long VCC and GND lines I used a wire which I bent (see column A and the Xes) and soldered them on various places.
I noticed it was very hard to solder adjecent lines (components close together), but leaving more space needs longer lines (and have to use wires instead of just solder?)
What are guidelines to make those 'interconnections' between adjecent holes?
And a side question: this is a 'double' sided board, but I don't see what it means, since the holes are connected anyway from the top and bottom side after soldering. Or do I miss something here?
Update 1
There was a discussion about my 'ascii' notiation... I will explain it a bit below.
The problem is, that I never have soldered on a proto/pcb/stripboard whatsoever, only did breadboarding. Since I want to be sure I don't mix up lines/columns, I like to make it visible before I start (and to see it fits).
I will leave the ASCII text above, however, to make it clear, I thought it's better using Excel. I also spaced out the colums more, so it's easier to solder.
The result is below.
AI: And a side question: this is a 'double' sided board, but I don't see what it means, since the holes are connected anyway from the top and bottom side after soldering. Or do I miss something here?
Yes, the green PCBs have their holes connected on both sides, before and after soldering. Calling it "double sided" is very misleading, but "true" in some sense.
This question will gain several opinion-based answers, anyhoo... disregarding that, this is what I recommend. Might be interesting since I use the exact same boards as you.
larger image
Circuit I made and used as blueprint (ish)
(Ring inverter with LEDs on the other side)
As you can see, I don't limit myself only to the plane of either side, I also go up a couple of millimeters and use that space as well. The metal pieces are from trimmed LED legs and large round resistors - no, I haven't ruined tons of LEDs so I can have small legs that work great with soldering. I simply don't throw away the legs of LEDs, I reuse them and cut them accordingly.
larger image
Circuit I made and used as blueprint
(Half bridge)
But using regular uninsulated copper wire works great too. Notice how I use the holes as a meeting point for two or more components. You usually don't need to space things apart. SOT-23 is great for 2.54 mm spacing.
(Modified version of this one that actually worked IRL)
I assume you are going to work with ICs - use their legs as well.
larger image
Circuit I made and used as blueprint
It's ugly, but it's your ugly thing. And you can't say that something you made is ugly, therefore it's handsome.
You probably cannot see it, but legs 3 and 5 are connected underneath the IC and soldered. (IC = LM393)
On the other side there are two transistors, and again I use the holes as nodes / meeting points. I rarely connect pins to different holes and then bridge the connection. |
H: Circuit to measure Voltage and Current (will it work?)
Hello,
I have a question, If my circuit will work:
Function:
Gate is on GND
Supplying a voltage betwenn 0V and 10V
10V Input is ~3.3V output
If the voltage goes above 10V the diodes D2 and D3 clamp it to ~3,3V
(This works as I understand)
Function
Vgate = 3.3v
Supplying a current between 0mA to 20mA
the voltage drop at R3 should "Supply" the voltage divider
again max output is 3.3V
Will the 2nd function work?
AI: The Si2356 is a good choice for a 3.3 volt gate control. It will have an on-resistance of about 0.05 ohms and that is negligible compared to the 499 ohm resistor (R3) so 20 mA will produce 9.98 volts across R3. The impact of 150 k in parallel with R3 is also quite negligible (it'll drop to 497.3 ohms) so the real voltage developed for 20 mA is 9.95 volts.
When using it as a voltage potential divider there will be anything from 1 uA to 10 uA leakage into the "off" MOSFET but, in comparison with the current though the series combo of R1 and R2 isn't a big deal.
R1 and R2 convert 10 volts to 3.329 volts but beware of resistor tolerances. For instance, if using 1% resistors for R1 and R2, 10 volts in could mean the 3.329 volts is a bit higher at nearly 3.4 volts. I don't think it'll cause a problem other than the uncertainty of value. I'd use 0.1% resistors if it is critical for performance. |
H: Voltage across inductor in AC
http://physics.bu.edu/~duffy/PY106/ACcircuits.html
The voltage across inductor is V=IXL but from the graph this doesn't seem to be true so what does it show ? Same for Capacitors
AI: The voltage across an inductor is V = \$L\dfrac{di}{dt}\$ so if the steady state voltage is a sinewave then the current, when differentiated is a sine wave. This means the current is an inverted cosine wave as shown in the picture.
The voltage across inductor is V=IXL
If you are reffering to RMS voltage and current then that is correct but, of course RMS voltages and currents do not embody the notion of phase angle (as seen in the diagram above). So the ratio of the voltage and current magnitudes equals the magnitude of the impedance but, behind this simplistic notion lies a deeper truth. |
H: Ideal component to switch 84V DC?
I wanted to control a 84V LED strip using a ATtiny13a microcontroller with minimal power wasted. I just want to turn it on and off, don't need any PWM dimming. The strip uses 270mA current and is about 22W power. MCU will be getting around 5V and 10-15mA supply and MCU uses only about 3-4mA max.
I have 3 components for this but I don't know which will waste least power as heat.I have IRL540N Logic level Mosfet , TIP122 Darlington power transistor and BT169D Thryistor/SCR. I'm avoiding sugar cube relays because I only have minimal space in the case/box for this project, which is also why I need the component which wastes the least power since I couldn't fit a heat sink.
I have programmed the MCUs eeprom to turn the circuit on and off alternatively each time the setup is powered on and off so the latching feature of the thyristor/SCR is not a problem here. I also have opto-isolators to protect the MCU from high voltage.
So which one of those components is ideal for my project? Also if there are any other components which will do the job better please let me know.
Thanks in advance.
AI: Use the MOSFET. Its use case is switching a DC load. If the LED strip has a lot of inductance, put a flyback diode across it.
If you drive the gate with 5 V relative to source, then the RDS(on) is specced as 0.077 ohms from the linked data sheet. The power dissipated will thus be 0.27 * 0.27 * 0.077 = 0.006 W. No need for a heatsink. |
H: Zener dynamic resistance Rz: Is this graph or the values for Rz correct?
The textbook I'm studying from states that the typical dynamic resistance ranges from 1 Ohm to 50 Ohms. Seeing the following graph something doesn't make sense:
Since the slope in the breakdown region is 1/Rz and the graph is almost a vertical line the typical values I'm given are not justified. In the best case scenario and for Rz=1 the slope is 1. Looking at the graph the slope should be a very big number.
Is this graph a supposedly ideal zener diode? Is the slope smaller in reality? Or have I utterly failed my high school math teacher?
AI: The misleading occurrence in the diagram of the Zener diode characteristic you are looking is that the the anode current axis in the diagram itself is probably graduated in milliamperes (\$\mathrm{mA}\$) while the Anode voltage axis is graduated in volts (\$\mathrm{V}\$). When you work in the breakdown region, beyond \$V_A\simeq V_Z\$, a variation of \$0.1\mathrm{V}\$ for a Zener diode with \$R_Z\simeq 1\Omega\$ causes a variation in anode current of nearly \$100\mathrm{mA}\$, probably out of sight since out of the ranges of diagram. The same thing happens even if the scale is logarithmic. |
H: Bridge rectifier simulation problem
I use virtuoso cadence to make two bridge rectifier,one of them use NMOS to replace the diode,and the other use DION_MM directly,like the picture shown
But their simulation are wrong,like the picture below shown,and i want to ask where is my schematic wrong?the gnd position?The red line is the wave of right schematic,and the blue line is the left,and the black line is the alternating current voltage source
AI: But their simulation are wrong,like the picture below shown,and i want
to ask where is my schematic wrong?the gnd position?
You need to place your circuit simulator's ground reference point on the bottom of the load resistor if you want to display the bridge rectified output as is normally presented.
Any sim will calculate the voltage at a node relative to the ground reference point and because you have yours on the AC output, you will not see the voltage directly across the load resistor.
If you want to simultaneously show the AC voltage pattern AND the bridge output then you need to use a "voltage controlled voltage source" conncted to one of the input voltages you want to display then, on the output of the VCVS, tie it to the ground reference point. Think of it like a differential amplifier but in-built into most sims: -
Red = input voltage relative to ground
Blue = output voltage relative to ground
Green = voltage across R1 re-referenced to ground so it can be viewed correctly |
H: Dim and "unblink" a pc power LED?
I just built an HTPC. It's got a bright white power-on indicator LED that is in fact needlessly bright and, which is worse, blinks when the pc is in suspend mode. I want it to be less eye-catching.
I suppose I can wire a resistor in front of the LED to dim it, but I've no idea how to select the proper value.
(and/or)
Can I wire a capacitor in front of the LED to make it's "very binary" blinking into a somewhat smoother wave pattern, sort of pulsating? I really don't care about the specific wave form, I just want it to draw less attention (making it glow constantly, but dimmer, in suspend than in power-on would be just fine, if that's a simpler thing to do).
I've no idea about the ratings of the components involved. I'm sure the LED is being driven at 5V (I can check), and I suppose it draws somewhere between 20 and 200 mA.
Can you help a feller out with some component choices based on such poor specs?
Update: I have soldered together a 2200uF capacitor and two 100k potentionmeters -- see photos here. I have tried to recreate Spehro Pefhany's diagram (dead bug style, it's gloriously hideous) and I can report a 50% success: the dimming works nicely, but the blinking seems to be completely disabled -- it's always on (at whatever brightness I choose) and I can't detect even a hint of variance regardless of how I adjust the 2nd pot.
Have I (despite triple-checking) put it together wrongly? What should I change to restore at least some blinking?
AI: I'd use a 5k potentiometer:
simulate this circuit – Schematic created using CircuitLab
Adjust brightness as desired by turning the knob. If you want to be fancy, mount the potentiometer so that it is accessible from outside. |
H: Quick question: do I need a resistor for a keyboard key switch
I am building 3D printed keyboard. I am probably going to use some off-brand cherry MX switches (probably outemu switches). Since mechanical keys simply allow current when pressed in, I do not need a resistor to protect the key switch.
So my question is “do I need a resistor for a keyboard key switch?”
Edit.
So I am going to put it on a “keyboard matrix” that looks like the picture given (hopefully it was given. I don’t know how pictures work on the app)
And each output from the matrix will go into the input on an arduino.
I think I got my answer, dim. The switch itself doesn’t need a resistor. But the Arduino might. Thanks all who had input. Much appreciated
AI: You need resistors to protect the outputs of the keyboard controller, at least.
If you scan rows and read columns, then pressing two keys in the same column at the same time will connect two row outputs, while one is high and the other is low, leading to a short. So the bare minimum are current limiting resistors in the row lines, around 10k should be sufficient.
However, if you press two keys in the same column, the column line will then be driven to half the supply voltage, and you cannot get a clear reading then.
If you instead add one diode per key and a weak pulldown for each of the columns, you can build the matrix so that the column readback will capture the true state of each key, even if multiple keys are pressed at the same time. This is a bit more expensive, but definitely worth it if you ever want to use your keyboard for gaming. |
H: short pulse suppression
I'm looking to build a component (simulink) that cuts off short pulses in a digital signal (that has a varying pulse length). Does anyone have an idea?
I thought about using an integrator and comparing the output value to a calculated value that would be the integral of the shortest pulse I want to keep, but it didn't really work out so far (resetting the integral to 0 at every rising edge of the digital signal).
AI: If you are dealing with a digital signal I would consider using a D type flip flop that was self-clocking. The incoming "raw" data (containing pulses that need to be eradicated because they are too short) is fed into an RC low pass filter followed by a schmitt trigger. The schmitt trigger will produce a logical 1 after a pulse has been present for the required amount of time as determined by the RC low pass filter.
The schmitt trigger output can then be used to clock the data through the D type flip flop. Should subsequently the "raw" data fall to 0 it can be used to clear said D type flip-flop. It's kind-of a self clocking D type circuit. |
H: Why is Zener avalanche noise saw tooth shaped?
I have the following schematic of a Zener based noise source:-
simulate this circuit – Schematic created using CircuitLab
When built, an oscilloscope reveals a saw tooth noise signal at the "Noise" node, like:
The time base is 1us/div. Can anyone explain why the signal is saw tooth shaped? Initially I expected a triangular, or even sine shaped wave form. I think that it's something to do with the impedance of the Zener in conjunction with the much higher 100 kOhm resistor. The electrons cascade freely across the junction, but the resistor restricts current flow when the avalanche stops. We're talking 60uA. The result being slower charge build up than when current flows during avalanche.
This wave form isn't particular to my set up. There are other examples elsewhere on the Interweb when people have really zoomed in on the signal,
one being https://youtu.be/CAas_kbTW3Q?t=714. Also there's a good chart here showing the rising edge to be slightly curved. It's probably unfamiliar as it's usually shown with a much slower time base. Am I right about the resistance/impedance explanation?
AI: Consider that you effectively have this:
simulate this circuit – Schematic created using CircuitLab
where C is the junction capacitance, plus any external capacitance (leads, breadboard, etc). Some of the current from R1 leaks through D1, but the rest charges C. Once the voltage reaches a certain level, avalanche breakdown occurs and current flows from C until the avalanche stops. Then the current begins charging C again.
To calculate C you first need to know the leakage. Decrease V1 until the noise disappears. Then measure the current. Then increase V1 back to 30V. Measure the rising slope of the noise dV/dt. Measure the average value of V. The current through R1 is approximately constant at (30V - V)/100kohm. Subtract the leakage current from this, then use I=C dV/dt to calculate the capacitance. |
H: Using diode to protect controller input
I'm looking to use inductive proximity sensors on a Duet Wifi (3D Printer Control Board), the board itself runs 3.3v but the sensors require 12-24. I've asked this on the product forum and they pointed me to some documentation that says to use a diode as follows:
NPN output normally-open inductive or capacitive sensor
Connect its output wire to the cathode of a diode, and the anode of the diode to
the E0 STP pin. Connect the sensor ground wire to a ground pin on the
Duet, and the sensor's + power wire to a suitable voltage (typically
to VIN because these sensors usually need between 6 and 30V power).
The diode should preferably be a small-signal Schottky diode such as
BAT43 or BAT85, but a small signal silicon diode such as 1N4148 works
for some people.
How is the diode working in this scenario? It appears to be placed backwards and if I use 24v, that isn't enough to reach the reverse breakdown voltage of any of the recommended diodes.
AI: The sensor uses a pull-down transistor which is on (pulling down) when the sensor is tripped and not doing anything otherwise. I believe they're suggesting the following:
This implies that the Duet Wifi's input pin has a built-in pull-up resistor. The pin's value is normally at 3.3v unless pulled down by the sensor. Thus the Duet's pin actually provides current out of its 3.3v supply through the built-in pull-up resistor into the sensor's pull-down transistor. The diode ensures that current can only come out of the Duet's pin, preventing damage to the Duet board if you were to accidentally connect it to 12v.
I believe the diode could be left out if you're quite certain that the sensor doesn't have an internal pull-up resistor and you're careful to connect it correctly. If in doubt, use the diode like they said. |
H: MCU Input Protection
I am working on a simple protection circuit for an I/O pin on an MCU. The device will be 3v battery powered. The MCU's I/O pin has a voltage tolerance of (GND - .6V) to (Vdd + .6V).
Pull-to-ground Digital Input (Pulse Signals)
Digital 24Vdc Input (from a thermostat)
High-Frequency 24V Counter
Pull-to-ground Serial Input (1200 baud - 9600 baud rates)
On the MCU will be an internal setting that will be used to decide what type of signal to look for and process, so this input circuit will just need to make sure that the MCU's I/O pin is protected no matter the input type (listed above).
Here is another one of my posts explaining my first attempts. The below circuit is a modification of the one recommended by @Jeroen3.
simulate this circuit – Schematic created using CircuitLab
So far the simulations look pretty good. Here is a voltage sweep of 0V-24V:
Frequency responses also look pretty good.
Does anyone have any experience with a similar circuit, suggestions, or can spot possible issues?
AI: Your circuit is way over-designed. Try something simpler, like this plain diode limiter
The 5-ms-like bursts are NOT high-frequency by any means. If you can afford 10k series resistor (R1), the above circuit will serve all your cases.
If you don't like having +4 V on MCU input, reduce the reference 3.3V voltage to 2.5V rail. Or use Schottky diodes. The capacitor C1, if placed in close proximity to the diodes, will also protect your inputs from any ESD. |
H: Question of chargining the battery
When a battery has electricity,we can see it as a VDC source,but i just wonder that when we charge the battery,is it necessary to make another circuit to charge the battery or just connect it with a VDC source?i mean that is the picture shwon correct?
AI: No that is not a general solution and may be risky.
That has no defined current limit or voltage limit or smart charge profile.
This is important to prevent battery damage or catastrophic failure.
e.g. minimize outgassing or self heating
Read
http://batteryuniversity.com/learn/article/all_about_chargers |
H: How a current buffers works, I want to make (1-5)V to (4-20)mA V-I converter, how can I make this circuit load independent?
I want to make a 1-5V to 4-20mA Voltage to Current convereter. I choose this circuit. The circuit is working for only 250ohm load the conversion ratio is 4. But I want to make this circuit load resistance independent how can I do this.
V vs I plot as shown below graph.
please help.
Thank you.
I want to share some thing after this. I make some modification of the above circuit add got the the require current but as floating load. I want to make the grounded load with mentioned specification.
AI: Then you need to measure the current, you can either measure the current through a resistor on the low side, or on the high side.
High side means that neither of the ends of the resistor are connected to ground.
Low side means that one of the ends resistor are connected to ground.
Low side is much easier to measure, but it also means that whatever current you are trying to measure through won't have a real ground. It will have a small resistor before its ground.
If you're going to measure high side then you will most certainly need an instrumentation amplifier.
Here is a schematic that measures the high side.
Link to circuit
The input is the "+4" on the rightmost op-amp
If you're going to make an instrumentation amplifier yourself out of four individual op-amps and four resistors, then don't. The precision needed for the resistor has to be within 0.1%, they must be matched. That's why you look here and find this one.
If whatever you are trying to control is okay with low side measurement, then you can use this circuit.
Link to circuit
The input is the "+4" on the rightmost op-amp
In this setup there's no matching required, so you can easily do it with two individual op-amps. You don't need a special IC for low side measuring.
Extra notes:
You don't have to use 1 Ω shunt resistor. You can use 5 Ω, 0.3 Ω or whatever. The problem with large resistances is that they will dissipate a lot of heat, or you need to drive your system with 12 V, or maybe even 24 V so you can force the current through your large resistance.
If you however use a small resistance for measuring the current, then you need to increase the gain. In the two schematics above, the gain is \$\frac{100k}{400}=250\$. If you would use a 0.1 Ω resistor instead the gain would have to be 2500. The bandwidth of the op-amps goes down as gain goes up. So if the unity gain of an op-amp is 1 MHz and you use a 0.1 Ω resistor and a gain of 2500. Then the bandwidth of this new system will be \$\frac{1\text{ MHz}}{2500}=400\text{ Hz}\$.
Or simply change the voltage range, from 1-5 V => 4-20 mA to 0.1-0.5 V => 4-20 mA. But then the SNR will decrease. Noise will affect your op-amp more. So you will need more / better shielding than the two previous paragraph's.
In electronics it's all about compromises. You can't have it all. But you can cascade/cascode things in a clever way to reduce many problems. |
H: How do i make sure the battery is charging in the simulation?
Here is the schematic from "Parasitic Power Harvesting in Shoes,IEEE,1998" ,and i add a button cell battery(the blue one) to let the PZT charge it(battery).
So i have to simulate it to make sure the PZT can really charge the battery,and if i use PCB,which thing can i use to replace that battery? because i don't think i can buy a dead battery (need to be charge) outside.And if i use computer software,like virtuoso cadence,which component can i use?
AI: I've never heard of a rechargeable button cell battery. Most rechargeable batteries need some amount of regulation to prevent damage from overcharging or over-discharging.
In this case, you might consider using a super-capacitor. The only regulation you need to worry about with a supercapacitor is not charging it past its rated voltage. Supercapacitors have a lower capacity for a given size, but I doubt you'll be making much power, so the low capacity won't be a problem. Here's a cheap 5.5-volt supercap (Digi-Key)
I recommend putting it where C4 is because that's on the 5-volt regulated output of the Max666. I haven't looked very carefully, but I believe that would keep it safe from overcharging. |
H: Why did this "backwards" power jack pass ERC in EAGLE?
As will become obvious, I am new to Eagle and PCB layout. I set out a simple design, starting with a power jack. The power jack seems to clearly have a "+" terminal labelled, so I connected that to the positive input of my 5V step-down converter.
On the board layout, I should have noticed that what I thought was the positive terminal was labelled GND (but alas, I did not notice):
However, the board passed ERC.
Did I misinterpret the "+" symbol on the schematic view? I would appreciate any insight into my error.
AI: The power jack seems to clearly have a "+" terminal labelled
It's not a "+" terminal, it's the symbol's 'origin' crosshairs. If you look closely you should see one on most symbols, though often it is partially obscured by other elements in the drawing.
Here are some examples (taken from Sparkfun's tutorial Using EAGLE: Schematic):- |
H: How can I find the equivalent resistance, Rxy, of the two NMOS transistors in Figure 5.25 in Razavi's "Design of Analog CMOS Integrated Circuits"?
While calculating the gain (\$-G_mR_{out}\$) of the differential pair (with active current mirror), in order to find \$R_{out}\$, how is Razavi able to substitute M1 and M2 with \$R_{xy}=2r_{01,2}\$?
AI: To find \$R_{xy}\$, we redraw the portion of Figure 5.25 of interest below, substituting small signal models for M1 and M2 (with \$\gamma=0\$, \$g_{m1}=g_{m2}=g_m,r_{o1}=r_{o2}=r_{o}\$), and apply a test voltage \$v_{test}\$ across the terminals:
From the above network we can use KVL to write,
\$v_{test}=(i_{test}+g_mv_p)r_o + (i_{test}-g_mv_p)r_o\$
\$v_{test}=2i_{test}r_o + (g_mv_p-g_mv_p)r_o\$
\$R_{xy}=\frac{v_{test}}{i_{test}}=2r_o=2r_{o1,2}\$. |
H: Embedded cascaded if-else statements
I'm designing an MCU based acoustic guitar tuner. I've broken the frequency spectrum from note C2 (65.41 Hz) to note C5 (523.25 Hz) into many sub-bands to give the user an accurate depiction of what note they're plucking. The note letter, number, and an indication of whether they're slightly sharp, slightly flat, or well-tuned will appear on an LCD.
The problem is that I can't see a way to avoid a massive if-else chain to determine in which band the input frequency lies. I've got 66 cases of 'else if ()', and this seems very slow/inefficient/silly to me. I need to figure of what note they've played and get it out to the LCD before the next pulse comes in. At highest frequency, this gives me a little less than 2 ms. Just clocking out 32 bits serially to the LCD driver takes up a decent amount of those 2 ms, so I need to figure out in which band the frequency lies fairly quickly. Can I do anything to improve the software and avoid a ridiculous amount of if-else-statements?
Edit for more information:
I'm programming in C on an AVR ATmega. To associate a frequency with a note, I'm using the formula: frequency = 440 * 2^(x / 12), where x is the number of half-steps away from A4 (440 Hz). An input is well-tuned if it is within +/- 0.25 half-steps from its centre-frequency. It is considered flat if it is less than 0.25 half-steps from centre but greater than 1 half-step from centre (where the half-steps are negative with respect to centre). It is sharp if it is more than 0.25 half-steps from centre but less than 1 half-step from centre (where the half-steps are positive with respect to centre).
For example:
G2 flat = [92.5 Hz, 96.6 Hz]
G2 good = [96.6 Hz, 99.4 Hz]
G2 sharp = [99.4 Hz, 103.8 Hz]
Where G2 centre frequency is 98 Hz.
AI: Further to my comments, you have a few musical problems with your approach.
Figure 1. The gStrings chromatic tuner displays tuning accuracy in cents. Note the large marks around +/-15 cent to indicate the limits of acceptable tuning.
Most tuners break a semitone into 100 cents. The gStrings Android tuner, for example, indicates acceptably in tune at +/-12 cents and most of us would try to do much better than that. You're going to use +/-50 cent which will be terrible as it would allow errors up to half a semitone.
Most good tuners will allow the user to set a deviation from the A-440 standard to allow tuning to a non-tunable instrument (e.g., an old piano) that is slightly flat. This is also useful when playing along with recordings that are slightly above or below standard concert pitch - possibly due to incorrect speed in the recording equipment. You need to incorporate this feature into yours if it is to be useful.
Figure 2. Guitar harmonics. Source: Hyperphysics.
The guitar string vibrates simultaneously in several modes - full string, half, third, quarter, fifth, etc., giving the harmonics mixed in with the fundemental. Guitarists can "play harmonics" by plucking the string while very lightly touching the string at the half or third, etc., way point along the string. With a bit of practice you can hear that the harmonic was there all the time when the note was played normally. In effect the guitarist is suppressing the fundemental and allowing the harmonics through. Skip through this guitar harmonics video to see this in action.
The frequency ratio between adjacent semitones on the well-tempered scale is \$ \sqrt[12]{2} \$. If your system has enough computational power you could convert the fundemental frequency to a \$ log_{12} \$ which will linearise the semitone scale into a simple arithmetic sequence.
Table 1: Note that the difference between log values of adjacent notes is a constant.
Note Frequency Log base 12 Diff of logs
A 440 2.4494983453
A# 466.1637615181 2.4727435908 0.0232452455
B 493.8833012561 2.4959888363 0.0232452455
C 523.2511306012 2.5192340817 0.0232452455
C# 554.3652619537 2.5424793272 0.0232452455
D 587.3295358348 2.5657245727 0.0232452455
D# 622.2539674442 2.5889698181 0.0232452455
E 659.2551138257 2.6122150636 0.0232452455
F 698.456462866 2.6354603091 0.0232452455
F# 739.9888454233 2.6587055546 0.0232452455
G 783.9908719635 2.6819508 0.0232452455
G# 830.6093951599 2.7051960455 0.0232452455
A 880 2.728441291 0.0232452455
By subtracting the log of the reference frequency (A = 440 Hz, A = 339 Hz, etc.) the log value will be 0 at the reference frequency.
Note that if you divide the \$ log_{12} \$ value by 0.0232452455 the values will increment by 1 per semitone. Now your note lookup is
Round to the nearest integer.
Integer divide by 12 to find the octave number.
Modulo 12 division to find the note offset into an array [A, Bb, B, C, C#, etc.]. |
H: Differences between flip-flop control inputs and clock inputs
I'm studying clocked flip-flops (FFs).
However, I cannot differentiate between the two terms control inputs and clock inputs.
Can you tell me the differences between those two types of inputs, or are they the same?
Thanks in advance.
AI: A clock is a continuous free-running square wave of a fixed frequency. It governs when the registers (flip-flops and latches) in a circuit could adopt their input level as their output. It provides timing to the circuit.
(There are situations where the clock isn't continuous, free-running or fixed frequency but ignore those for now, let's stick with the typical case for synchronous digital logic.)
The control inputs govern if the registers will adopt their input level as their output. If they do, it will happen on the next clock edge for synchronous controls (e.g. Clock Enable CE, Latch Enable LE) or as fast as possible for asynchronous controls (e.g. preset PRE, clear CLR). Therefore the term synchronous and asynchronous indicate if they are gated internally with the clock or not.
In a synchronous logic circuit, the asynchronous inputs are normally used only for rare and exceptional control, such as power-on reset or a critical failure response. Using the clock and synchronous control inputs allows the timing within the circuit to be predicted accurately. |
H: Changing pin direction without glitching on LPC800
I'm looking at an LPC812 Cortex M0+ microcontroller and its GPIO functions. On a PIC microcontroller, one would always set the LATch prior to changing the direction of a given pin. This avoids the possibly nasty situation where a pin "gitches". ie: the output state of the pin is a 1 just before you change direction and set it to a 0. This results in a pin output changing from 1 to 0 over a sub-microsecond duration.
(related: Why set PORTx before TRISx?)
However, it is not obvious from the user manual (UM10601) whether writing a value to a pin which is currently an input has any logical effect (it will not have a physical effect on the pin state as it's an input). Thus if I write a zero to PIN0 (page 92/93) that should in theory clear all the output bits. If they were latched, which isn't certain.
Section 7.7.2 says that "If either or both of these conditions (ie: set to gpio and set to output) is (are) not met, writing to the pin has no effect.". Which isn't helpful as I know there's no physical effect.
Under the IOCON description (6.3, page 68) is the following Remark:
If the open-drain pins PIO0_10 and PIO0_11 are not available on the package, prevent the pins from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0 register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.
In my opinion this is an incorrect sequence (unless the GPIO port outputs defaults to low, something else that isn't documented). On a PIC16 I would set the HI/LO state first, then change the direction.
I admit that if the part had arrived I would just test this on the bench. However I'll put this on stackexchange as I'm seeing examples everywhere which set direction and then the value, all of which may be glitching output pins.
AI: You're over-analysing this. There are two registers involved in a GPIO pin, the output data register, and the direction register. Both of these are writable at any time (and I agree your Section 7.7.2 quote does not make this super-clear.)
The remark on p68 doesn't care about a transition, it cares about a power-optimised stable end state. Changing the order makes no real difference, but is cleaner as you describe.
There is no changing from 1 to 0 over a sub-microsecond duration. When you enable the output, it takes the driven value in just the same way as if you drive it from 1 to 0 using the data value.
It is only when the reset data value is 0, the tri-state is pulled up, and after enabling the output you write 1 to the data pin that you would see a pulse.
All peripherals are different, but for example
A read from GPIODATA returns the last bit value written if the
respective pins are configured as output, or it returns the value on
the corresponding input GPIN bit when these are configured as inputs.
All bits are cleared by a reset.
Specifically, the last write and not the last write whilst the pin direction was set as output. |
H: association of resistors with short circuit
hi, a somewhat basic question: if i4 = 1, and all resistors have value R, what would be the voltage drop between a and b?
AI: As @Bart said as a hint, R2, R3 and R4 are in parallel.
If you try to move the resistors and their connections to find an arrangement, you may get this :
simulate this circuit – Schematic created using CircuitLab
So, you should be able to apply Ohm's Law by yourself, I guess (I hope). |
H: Loop of a wire and right hand rule
When the loop is the figure shown below will be rotated in clockwise direction the the slip ring connected to the red segment of the loop will give us the positive voltage and the slip ring connected to the black segment of the loop will give us negative voltage according to the Flemings right hand rule.
What if the loop is rotated in counter clockwise direction ? Will the slip rings provide us the same polarities which they were giving when the loop was moving clockwise ?
Plus
The voltage from the loop is given by the equation.
V(t) = Vmaximum * sin (theta)
Where theta is the positive angle the red segment makes in the clockwise direction or in counter clockwise direction from this position ?
AI: When the loop is the figure shown below will be rotated in clockwise
direction the the slip ring connected to the red segment of the loop
will give us the positive voltage and the slip ring connected to the
black segment of the loop will give us negative voltage according to
the Flemings right hand rule.
With the loop in that position, the induced voltage is zero so NO, there is no voltage generated at this instant or position. Reason: the induced voltage relies on rate of change of flux and with the coil vertical the flux cutting the coil may be at a maximum but the rate of change of flux is zero: -
Improved picture source here.
So, using the picture above, (and considering the case from position 1 to position 3), the voltage increases to a positive peak due to the rate of change of flux (that the coil is cutting) increasing.
Conductor DC is indicating the flow of current should the generator output be loaded. Due to Fleming's right hand rule conductor BA also has current flowing the same way hence the terminal voltage on the closer slip ring is positive.
If you reverse direction it is the same as swapping the magnet poles and the waveform will be inverted. Flemings right hand (generator) rule: -
Strictly speaking this rule applies to the current direction but given that the current direction is dictated by the polarity of the induced voltage, it matter little. What ever way you try and rotate your right hand, if you reverse either the direction of travel or the magnetic field, current reverses and, by inference, induced voltage polarity reverses. |
H: Why GSM module connects with same apn for different operator?
I'm using SIM868 in one of the GPS tracker that is being developed.
HTTP protocol is used in sending data to the server.I have tried this with SIM cards of 2 network operations,Vodafone and Airtel.
AT+SAPBR=3,1,"APN","www"
is the command I use to set the apn of the network, in here the apn of Vodafone is "www" and the apn of Airtel is "airtelgprs.com". However it is found that Airtel network also works with the apn of Vodafone and vice-versa. Both networks are able to connect and send data to the server(verified in the server side as well).
How is it happening? Is apn not a mandatory parameter in connecting to internet?
Regards,
Joe
AI: That parameter is mandatory, but how (and whether at all) your provider uses it is pretty much up to them. |
H: EI Lamination core geometry for 3-phase transformer
There are several tables for EI Lamination geometries for 3-phase transformer cores available from manufacturers. Is there a general standard (something comparable to the AWG table concerning wire geometry)? Or is there something like a geometric rule for this type of core geometry? If yes, does somebody know a useful link?
AI: In the link you posted, tables 3.10 and 3.11 give figures for the size of this manufacturer's 3 phase cores.
The sizes start off 0.25, 0.375, 0.5, which is linear increments of 0.125, then it continues 0.562, 0.625 which is now 1/16ths, then back to 1/8ths with 0.875. Once it gets to 1.0, it then continues 1.2, 1.5, 1.8, which looks like it's out of the E12 resistor series, for which the next size would be 2.2, but instead it jumps to 2.4 then 3.6.
I think it's safe to say there is absolutely no coherent series here. It's likely that the company has been asked by specific customers at different times to design particular sized cores, and has then simply put them into the catalogue in size order. There might have been an attempt from time to time by different people to impose some sort of structure on one part of the size range, which never got carried through into a complete revamp of their catalogue. I would not be surprised if other manufacturers matched some of the sizes, and were different in others.
When people try to structure a range like this, they'll tend to use a logarithmic scale. Popular ones are E3, 1.0, 2.2, 4.7, E6 which infills E3 with 1.5, 3.3 and 6.8, and E12 through to E192, which I'm not going to detail here. Another one, which I am trying to commit to memory so I can approximate logs in my head, is E10 which goes 1.0, 1.25, 1.6, 2.0, 2.5, 3.2, 4.0, 5.0, 6.3, and 8.0. The E10 tends to get used for capacitor voltages, whereas the E12 series gets used for the values. No, I don't know why either. |
H: Lowest energy use, 240v or 12v
I am fitting a heating system to my boat and want to know which of these two systems will use less energy from my 12v batteries. System one is a heating unit which uses 190 watts at 240v through an inverter, and system two is a heating unit which uses 72 watts at 12v direct from the battery bank. Many thanks.
AI: The 72W DC system will use 72 watts from your batteries, and deliver 72 watts to where the heater is sited.
The 190W AC system will use somewhere north of 190W from your batteries, maybe 220W, deliver 190W to where the heater is, and 30W to where the inverter is. If you're careful with layout, you can make the inverter deliver its waste heat to the place you want heated as well.
Either way, that's not much heat for a boat. I suggest you get a gas fired heater. |
H: How to compare footprints of SMD components?
How easy is it to compare dimensions and footprints for different size SMT components?
For example, is it possible to compare the footprints of 0603 and 0402 components to determine if I can use an 0402 component on the footprint of an 0603? Or some another parts?
Which software or web services can I use to do this?
AI: It completely depends on how the footprint for the 0603 part was designed. Although there are recommended sizes for all of the solder pads for each component, some PCB designers deviate from those standards for particular reasons. In particular, the pads are often elongated towards the middle of the component precisely to allow a smaller component to be used on that footprint.
This is often done during the prototyping stage to allow maximum flexibility when working with components that are on hand.
That said: you can often make a 0402 component work on a 0603 footprint IF you are placing and soldering the component by hand. I would not expect that an automated Pick and Place machine would be able to do this. |
H: How to come up with MOSFET equivalent of a tuned collector feedback oscillator?
I am trying to come up with a MOSFET equivalent version of the following tuned collector feedback oscillator. Primary objective to try with MOSFET is to improve the efficiency of oscillator.
But I am not sure how can I change the circuit when BJT is replaced with a MOSFET.
Kindly appreciate your suggestions.
AI: Both an NPN BJT and a N-channel MOSFET have the same sense of characteristic, increase the base/gate voltage and the current drawn through the collector/drain increases. However there are several differences.
The devices will be biassed slightly differently. A BJT has a fairly well defined 0.7v (ish) from base to emitter when the collector-emitter current is being controlled. The FET has a poorly defined gate-source threshhold voltage, which can easily vary by 2:1 for FETs of the same make, and do vary between types of FET. Threshhold voltages in the 1 to 3v range are to be expected. If you need accurate control of the drain current, then make your gate bias variable.
Although we normally think of a BJT as driven by its base current, for small signals we can also consider it to be base voltage driven, and define its \$g_m\$. A FET will tend to have a lower \$g_m\$ than a BJT, so allowance for this must be made in your choice of feedback components. |
H: AXP209 : Usage without ACIN?
I'm currently bulding and Android device and I've got a question which can't get answered.
The AXP209 is an IPS and power manager. It allow the usage and charge of a standard lipo.
It has two inputs : ACIN and USB VBUS. In a case of a tablet, will the IPS use VBUS to charge the battery and make the whole thing work, or is ACIN needed ?
Datasheet
AI: Whatever; After some deeper search into the datasheet, I've found this :
The AXP209 power input can come from lithium battery (BAT),USB VBUS Input, external power
supply (ACIN). The IPS will select an appropriate power source depending on the battery and external
power conditions.
O When only the battery is available, no external power input, the battery powers the system;
O When there is a valid external power source(VBUS Or ACIN), is is the preferred power supply.
O When the external power is removed, the IPS will seamlessly switch over to battery power.
O When both VBUS and ACIN are available, ACIN will be used to power the system and recharge
the lithium battery;
O If the ACIN cannot provide sufficient current, VBUS is also connected to source more
current;
O If the drive capacity is still insufficient, then the charge current is reduced to zero, the
battery is used to power the system
So in the case of the AXP209 IPS, the order is ACIN > VBUS > BAT. When one of it fails, by delivering not enough power or by simply being absent, the IPS chooses a better supply seamlessly.
The answer to the question is yes then, the IPS can be used without ACIN,
Edit : and yes I'm sorry not looking deep enough and answering my dump question by myself |
H: If two iBeacons are too close to eachother, could their signals get confused for one another?
I have a simple question that I can't find the answer to. I am testing an app with some iBeacons, and I observe that one of my iBeacons never begins to range...the region is monitored, its just not being detected. When I look at console output the other beacons get detected, and then a few seconds later, another beacon gets detected, but it has the same UUID/major/minor/identifier values as one of the other locations already detected.
So all but one of the beacons get recognized and their states get determined. Then it appears that one of the beacons that has already been determined, gets determined again (same info). These beacons are somewhat close together (about a meter apart in x, y but on different floors (2nd floor and 3rd floor), and I'm wondering if one beacon signal could override another...which would be why I am seeing the info for one of the beacons twice. Otherwise I'm not sure why I can't detect this one beacon.
AI: iBeacon seems to be based of Bluetooth Low Energy (BLE).
As discussed here, Bluetooth devices cannot normally interfere with each others. They simply "wait" for their turn.
In your case, I guess they are "beacons", which are connecting and disconnecting frequently to devices to send data. Your issue might be that you are misunderstanding one beacon for another ? Or it might be software related. |
H: Only one attachInterrupt works at a time
I am using the MSP430f5529 launchpad and coding in Energia.
The goal is to make a program that can detect whether the onboard pushbutton is up or down (as part of an eventual Morse code decoder), which I planned to implement using two attachInterrupts.
If I use one, for example attachInterrupt(BUTTON, buttonPress, FALLING), it works fine and the button press is detected. If I use attachInterrupt(BUTTON, buttonRelease, RISING), the button release is detected.
However, if I have bothattachInterrupts in the same program, only one of them works; based on trial and error, it seems whichever interrupt was declared last takes precedence.
In the below code, for example, only buttonPress fires. If I swap the order of my attachInterrupts, only buttonRelease will fire.
#define BUTTON PUSH2
volatile int buttonDown = 987; // set to an arbitrary value so I can tell if the functions changed it at all
void setup() {
Serial.begin(9600);
Serial.println("Test code for buttons");
// Enable internal pullup
pinMode(BUTTON, INPUT_PULLUP);
// attaching release before press
attachInterrupt(BUTTON, buttonRelease, RISING);
attachInterrupt(BUTTON, buttonPress, FALLING);
}
void loop() {
Serial.print("buttonDown: ");
Serial.println(buttonDown);
}
void buttonPress() {
buttonDown = 1;
}
void buttonRelease() {
buttonDown = 0;
}
How can I make both buttonRelease and buttonPress work at the correct times? I tried to just check if the button state changed using a single interrupt (that detected CHANGE, not just RISING or FALLING), but that seemed to lead to even more problems down the road, since the hardware would sometimes register a change in the middle of running the code needed to process what to do with that change.
AI: For the pins that support pin change interrupts (P1, P2), each pin has a flag that controls which edge the interrupt is triggered on. This means that the pin cannot trigger an interrupt for a rising edge AND a falling edge like you want. See Page 308 |
H: Common transistor topologies
I'm trying to get my head around transistors and I had some difficulties to understand the various way we can connect a transistor.
For example, here are a few possible arrangment:
simulate this circuit – Schematic created using CircuitLab
In theory, both of those circuits should be equivalent except on the left, the led is on when the base is low and on the right the led is on when the base is high.
The difference I see is that on the left, when the transistor is in cutoff state R1 and D1 aren't affected by a voltage drop through the transistor unlike the schema on the right.
So technically something like this is:
simulate this circuit
Here the arrangement at the top is capable to supply 15v to the gate of the mosfet but the arrangment to the bottom can't barely supply more than 2v according to the simulation.
The question might be a bit vague, but what I'm really interested to know is if there is a list known pattern for transistor arrangement and their pros/cons?
For example, there is the darlington transistor which is pretty much like my last schematic but it seems it doesn't work if you want to amplify the voltage output for a mosfet using a transistor. In my examples, I used a clock but had in mind an output pin coming from a mcu.
For example, I saw on stackexchange someone recommending this kind of pattern:
simulate this circuit
To drive a Mosfet, yet in this particular example, doesn't seem to work in my case. Actually it looks like half of an H-bridge.
Also, in my particular examples, all of the collector have a 12v applied and driven with a 5v logic on/off.
AI: This is not an answer at this stage but merely shows a few problems with your understanding.
You are missing the power supplies on your schematics. Add them in.
simulate this circuit – Schematic created using CircuitLab
Figure 1. (a) The LED is always on. When Q1 turns on it short circuits the supply and probably burns out. (b) This will work but the emitter will be about 0.7 V below whatever voltage is on the base.
simulate this circuit
Figure 2. (a) M1's gate is permanently connected to 12 V via R3. Q1 does nothing for it. (b) With a 5 V clock signal the emitter of Q3 will reach < 5 V. This might turn on M3 a little but once current flows the voltage on R8 will rise, reduce the voltage and turn it off. If the clock signal voltage was high enough you could turn on M3 but without a discharge path M3 will probably never switch off.
simulate this circuit
Figure 3. The Q1 and Q2 parts are OKish but having M1 on the high side of the load will prevent it working properly.
Also, in my particular examples, all of the collector have a 12 V applied and driven with a 5 V logic on/off.
In all except Figure 1a you are running the NPN transistors in "emitter-follower" mode the emitter will follow the base voltage minus about 0.5 to 0.7 V because of the base-emitter diode voltage drop. You will never get the emitter above about 4.5 V so most of your circuits won't work properly, if at all.
Edit after OP's update:
The difference I see is that on the left, when the transistor is in cutoff state R1 and D1 aren't affected by a voltage drop through the transistor unlike the schema on the right.
That is correct. That arrangement is referred to as shunting the current. Your arrangement is inefficient, however as high current is high current is shunted it's rather power hungry. A better arrangement is shown below in 1a.
simulate this circuit
Figure 4. (a) All that is required is to shunt the LED current. R4 then limits the current to slightly more than when the LED is on. With the transistor turned hard on (note addition of base current limiting resistor) there will be about 0.2 V across Q1.
I'm really interested to know is if there is a list known pattern for transistor arrangement and their pros/cons?
What you are asking is for transistor circuit topologies. I had a look around for a good one but drew a blank. My old The Art of Electronics by Horowitz and Hill gives many examples. |
H: What are the mechanism and effects of non-linearity in an attenuating barrier in the presence of a high-strength EM field?
It's my understanding that in electromagnetics, if an attenuating device is functioning linearly, it means that 1) input and output signal strengths are proportional; and 2) input f = output f. How accurate and complete is this definition?
It's also my understanding that an attenuating barrier can become non-linear in the presence of a high-strength EM field (e.g., 50 kV/m, 133 A/m). Why/how does this occur? What properties of the barrier material affect this (e.g., permitivity, permeability, ferromagnetic properties, etc.)?
It's also my understanding that non-linearity causes a barrier's attenuation to be enhanced or diminished by frequency, depending on the detail of the non-linearity. What is meant by "the detail of the non-linearity"? Why/how does non-linearity cause attenuation to be enhanced or diminished at a frequency? In other words, what material properties determine whether attenuation increases or decreases?
Actually, if the definition of linearity in the first paragraph above is okay, then I think I understand, at least partially, why non-linearity might cause attenuation to increase or decrease at a frequency. If the non-linearity involves a frequency shift, then attenuation would increase at the input frequency and decrease at the output frequency. If the non-linearity involves a change in the proportionality of input and output signal strengths, then depending on how the proportion changes, attenuation would be increased or decreased. Do I have this right?
This is a rewrite of this question, which was titled and worded poorly. Selvek's answer was helpful, though. I would have asked him for clarification, but it didn't seem to make sense to contribute further to an unclear question that misses what I had intended to ask and that's inviting down votes. So, re-asking seemed a good solution. Apologies if this isn't correct procedure. I'm new here. I did reach out for help from a moderator, but I haven't received a reply yet.
AI: Non-linear material properties are wide ranging and depends on the purpose.
For magnetic fields, ferrite, cobalt etc are all linear until they start to saturate then the "mu" coefficent (permeability) can drop to a low slope value. This would look like this.
This one is steep when linear and flat equivalent to air (mu=1) when saturated.
If mu is high = 10k and drops to 1 then it is pretty significant reduction in inductance and shielding effects become transparent.. But in reality this would require a very high H field like a nuclear blast. So then you need lower mu materials that dont saturate so easily like thick wet concrete walls.
It all depends on the application.
There are lots of other non-linear properties such as rise time and aperture effect of a waveguide with 1/4 wavelength impedance inversion effects. |
H: How to transmit data with a laser beam?
I am working on a project about data transmission with lasers. The project is very young so I can modify my current planned setup if necessary.
This is the actual planned setup:
Every raspberryPi can control a laser (probably via a dedicated driver) and a phototransistor. After a "syncing" phase the devices can communicate turning on and off their own laser to send a one or a zero respectively. To help receive the laser beam I am planning to add some kind of lens.
My goal is to archive enough bandwidth to make a voice call (see below for more detaild) between the two devices, about 5 KBps.
The expected working distance is at least 4 meters, up to 20 meters if possible.
I thought about infrared laser to avoid some disturbs from artificial ligth, sun, etc.
What kind of (possibly low cost) laser and photransistor can I use in this setup? I have searched online for some lasers but I am concerned about the speed at which the laser can turn on and off.
Clarification: I have not been very clear about what i wanted to archive with the project. Sorry. My goal is to be able to transmit arbitrary data (bytes) over this channel. With this first prototype the goal is transmitting fast enougth to carry a phone call. The voice is first received by a microphone connected to a sound card, converted to binary data, compressed, sent through the laser channel, received by the other end, decompressed and played through a speaker. In future prototypes with more bandwith i'd like to transmit other kind of data such as small files or video streaming.
AI: My answer is about the use of laser diodes.
Using a laser to transmit optical information requires a little knowledge. The first bit of knowledge is the threshold current that is needed for the device to commence lasering. Below this current, the lasering is poor or zero and there is a time lag on returning to lasering when current rises again. This means your data can be interrupted. So, if you want a good system, stay above the lasering theshold. However, that threshold is temperature dependent: -
Picture Source
So where do you pitch the forward current to cover the likely (or possible) variations in temperature (bearing in mind the self heating of the device). What about this: -
If I choose a minimum current of 55 mA I can always produce laser light. See the blue line I've added to the picture above. But if the maximum output power is 10 mW, I can't modulate the light with a current greater than about 65 mA at 0 degC. This gives me a light output that varies between about 6 mW and 10 mW at 0 degC and between about 1 mW and 3 mW at 50 degC.
But you could go for more sophisticated approach. You could make the average laser current rise with temperature using a thermistor. So, at 0 degC the average current is about 52 mA and at 60 degC it's about 78 mA. This now positions the unmodulated light output at 5 mW across the range of temperatures.
This is important because now you can modulate the light output between 1 mW and 10 mW - this is called the extinction ratio (by the way) i.e. the ratio between lightest and darkest laser light output levels.
It's still a little tricky though because to get 1mW to 10 mW at 0 degC requires a change in current of about 25 mA whereas at 50 deg C you'll never quite get 10 mW even with 100 mA but you might get 1 mW to 9 mW with a change in current of 45 mA.
So the laser output gain reduces with temperature.
I'm labouring these two points (threshold and gain temperature sensitivity) because be under no illusion, to get a reliable free-space transmission system working across a gap of 20 metres requires every tweak possible to make it work successfully.
You'll need a small (but not parallel) "diversion angle" to make your system usable but, because of this, you will be receiving micro watts (at best) at 20 metres and you may be "in the noise" of your receiver.
Just think about that tiny little window in your photodiode (yes, use a photodiode for speed) - you might have an active area of 1 square mm. If your laser is illuminating a 20 m distant target with an area of of 100 mm x 100 mm you have spread your 5 mW average power thinly over 10,000 square mm and so your receiver window acquires just 500 nW and that's just on a good day!
Do not underestimate the difficulties and the head scratching. Do not under-estimate the length of time you might spend trying to understand the equivalent input noise of this or that photodiode. It can be done but it can also be very tricky. Choose a photodiode that is as big as you can but not so big that it is too slow for the data rate. If you can get 4 sq mm then you have quadrupled the receive power compared to 1 sq mm.
If you are going to use a lens (or you need a lens) mount it at the laser end and not the photodiode end. Mounting at the photodiode end is much less effective given that the lens can only receive and focus the power that hits the lens. Hence a small receiver lens is of moderate use compared to a lens at the laser used for focussing a slightly divergent beam. |
H: 02B k SMD part misbehaving
First, I would like to identify an SMD part in this image, having 02B k printed on it. Where can I find some documentation? I think it should work as some kind of AND gate.
There are three of them on this board, and two of them are probably misbehaving. For both inputs fully open (+12V, +12V), it should output +12V. This way does work only one of them, the second outputs nothing at all, and the third one outputs just a small fraction of the input voltage.
What are these parts?
What may have caused the failures?
Edit:
Whole board:
Well, it seems that the problem is not caused by these transistors after all. On the control circuit (C4-C6) aren't the same inputs, so I suspect the problem will be somewhere else.
Edit2:
This board is a three-color (RGB) LED stripe driver, controlled by an IR remote
AI: They are likely to be transistors as @Rev1.0 suggests. As to whether they are MOSFETs or BJTs, it's hard to tell beyond educated guesswork.
A quick search for SOT-23 packages bearing the marking O2B finds the LN2302BLT1G NMOS. The pin-out for the NMOS makes good sense - gate to U2, resistor from gate to source, and drain going to output.
The Guesswork
The circuit as you point out is an RGB LED driver, so there are three outputs which drive the LED cathodes using transistors, with the fourth pin being power to the anode. The transistors frying could be the result of a current surge on the power rail frying the outputs.
There is a sensor input which as you point out is an IR controller (V = power, S = sensor, G = ground at a guess) connected to U2. The three transistors also connect to U2.
The bottom right corner of your circuit is a Zener diode base shunt voltage regulator of some sort - series resistor, smoothing capacitor, then series diode (reverse polarity protection probably), and parallel zener diode.
U1 is an I2C EEPROM connected to U2, so U2 is probably some form of microcontroller which could be something like a PIC12F series MCU. The PIC12F's are 8-pin devices with VDD/VSS pins in the correct place and pins 2,3,5,6,7 are all IO pins which would match your circuit. Pin 4 of U2 has a pull-up resistor and connects to the sensor input. That corresponds to the reset pin of the MCU, so the sensor could be some form of shutdown pin.
Each transistor has a 47kOhm pull-down on what is either it's gate (NMOS) or base (BJT). There is also a 10kOhm series resistor between the gate/base and the output.
10kOhm base resistor seems quite high for a BJT - it would limit the current through the base quite heavily. The linked MOSFET has a <1V threshold voltage, so the 10k/47k divider that results wouldn't have too much affect. |
H: Input Output Relationship of Inverting amplifier
Can someone explain the input output relationship of below attached image ?
AI: simulate this circuit – Schematic created using CircuitLab |
H: Bad Measuring Equipment?
I was measuring the current through current mirror, when I experienced a problem. But first, I want to mention that I measured this with two ammeters of same manufacturer and same model (Mustool MT826 Digital Multimeter). Both were set to mA (milli ampere) setting of measurement and through both of them, the current measured was about 0.5 mA for both collector currents through Q1 and Q2. Then I thought that it would be better to set both of meters to uA (micro ampere) setting of measurement, and so I did. But only one at the beginning; AM1 was set to mA setting while AM2 was set to uA setting - there I spotted a problem. Suddenly, the current through AM1 was around 2.5 mA while current through AM2 was decreased to 300 uA.
So this got me thinking for a while and I came to conclusion that at different settings for current measurement, the ammeter is "seen" as different load to the emitter of Q1 and Q2. So, my question is:
Is it normal for ammeter to change its internal resistance, when we switch between different settings of measurement (uA, mA, A) or is this due to bad measuring equipment bought?
simulate this circuit – Schematic created using CircuitLab
AI: Yes, it's completely normal. Often a fixed voltage (for full scale input) is presented to the measuring circuitry (the "burden voltage") so the resistance of the ammeter decreases (more or less) linearly with the scale.
In other words a 20mA range might look like 10\$\Omega\$ (200mV burden), but a 20A (called a 10A) range would be more like 10m\$\Omega\$. Plus lead, some internal, and switch resistances.
It's important to remember that an ammeter (when properly working) will tell you the current that is passing through it, however that may not accurately reflect the current that would be passing through the circuit if the ammeter was replaced by a short. You can think of the ammeter as something like this:
simulate this circuit – Schematic created using CircuitLab
The resistor Rm is usually fairly stable and fixed (for each range) however Rx can be unstable because it includes copper wires, the flaky rotary switch, trace resistances, the banana jacks and plugs on your meter and so on. |
H: Long lived LED vs EL Wire Lamp
I'm on a quest to build a small cylinder (1/2" diameter) that illuminates for extended periods of time on a single charge. I've looked at numerous small sized batteries and decided on using 2 LR44s rated at ~170 mAh @ 1.5 V (each). This would be my first true engineering project so excuse my shoddy calculations.
I'm debating between using an LED OR an EL Wire design. From what I've read, an LED DC takes ~20 mA for ~7000 mCd luminosity (and ~10 mA for ~3500 using linear relation) which would give me about 34 hours (170 * 2 / 10) of continuous use.
Now from what I've read about EL Wire,
each meter of high brightness EL draws about 10-15 mA at the high voltage
So if I have a 1" length keychain It would draw ~ 0.3 mA (0.025m * 12 mA) which would give me a runtime of ~1,133 hours (170 * 2 / 0.3). Is that at all accurate?
If it is, does an inverter of that size (1/2"x1/2") exist?
AI: You have a few issues with your calculations, if you have two batteries that are rated at 170mAH at 1.5V each and you put them in series to get 3V to power the led but the capacity will still only be 170mAH (devices in series all share the same current, so any current that goes through the first battery will also go through the second). You could place the two batteries in parallel to get a capacity of 170mAH * 2 but then you would only have an output voltage of 1.5V to work with. Thus for calculating the lifetime for the LED you should be using 170mAH/10ma = 17 hours.
For the case of the EL wire you need to account for the output voltage. When you increase the voltage with the inverter the power out will be equal to the power in times the efficiency. Electrical power is voltage times current, so to have an output of .3mA at 100V (average pulled from link provided) will use .3mA*100V = 30mW of power. If you have the two batteries in series to provide 3V to the inverter it will need to supply 30mW/3V = 10mA of current. If you factor in the efficiency of the inverter it will end up needing to pull more than 10mA from the batteries so the expected life will be under that of the LED. |
H: Generate rotary encoder signal
I need to generate signals at the output of a Mega Arduino to simulate the signals of a rotary encoder. I know how to generate frequency signals through the function below. How could I generate the signals as in the image below, with a time lag between them? I have to take into account that the frequency must be the same.
void Encoder() {
tone(51,60);//Generates a 60Hz signal at output 51
tone(52,60);//Generates a 60Hz signal at output 52
}
update:
I was able to generate the desired signal by doing the following:
void Encoder() {
int i;
for (i == 0; i <= 10000; i++) {
digitalWrite(50, HIGH);
delay(10);
digitalWrite(48, HIGH);
delay(10);
digitalWrite(50, LOW);
delay(10);
digitalWrite(48, LOW);
delay(10);
digitalWrite(50, HIGH);
delay(10);
digitalWrite(48, HIGH);
delay(10);
digitalWrite(50, LOW);
delay(10);
digitalWrite(48, LOW);
delay(10);
}
}
AI: If you don't care too much about the exact frequency and timing you can use the below method- delays are 1/4 of 1/60 second or 4167us ideally, but the writes and the loop use some time so the frequency will be a bit lower than 60Hz.
If you need very accurate timing or you need the micro to be available for other tasks you can access the on-chip timers directly, but that's a bit more effort.
// play with the below number a bit to change the timing
#define DLY 4167
void setup() {
pinMode(13, OUTPUT);
pinMode(12, OUTPUT);
digitalWrite(13, LOW);
digitalWrite(12, LOW);
}
void loop() {
delayMicroseconds(DLY);
digitalWrite(12, HIGH);
delayMicroseconds(DLY);
digitalWrite(13, HIGH);
delayMicroseconds(DLY);
digitalWrite(12, LOW);
delayMicroseconds(DLY);
digitalWrite(13, LOW);
}
(ignore the voltage display, they are both 0/5V) |
H: What is the connector shown in the photo?
Is the connector marked as CN3 in this photo a standard one? If so what is it called?
AI: After counting 12 pins before the seperator, it looks like this is an M.2 Key E connector.
Such as this one from TE Connectivity. |
H: DIY 5V power supply from phone charger
I want to power 25 Adafruit NeoPixel LEDs. According to the specifications they draw a maximum of 60mA at 5V each. In total that would be 1,5A at 5V.
I would like to use a 2A USB phone charger as a power supply for the LEDs. If I cut open an old USB cable, there should be 2 power lines in there. I would like to use those to power the LEDs.
Is there any reason that a USB phone charger should not be used as a power supply?
Is there any reason that this is a bad idea?
AI: Given that you at looking to use it at 75% of it's rated capacity, you should be good to go. USB chargers are ubiquitous as basic 5V switching supplies.
It will work, given you buy a decent/reputable usb charger and not a cheap knockoff of questionable quality. A decent charger will have proper isolation between the mains side and the dc output, as well as safety features like a fuse or Over Current Protection. A cheap one may not actually put out 2 Amps.
Keep in mind that some chargers will put out slightly more than 5V, to make up for power loss over the cable. This would benefit you. You want to use a quality cable as well, with thicker wires. Cheap wires may use aluminum instead of copper (or copper coated aluminum) and of a smaller cross section, resulting in higher power loss at higher distances/current. |
H: Via in between differential traces - how bad is it?
I'm working on a board that has some LVDS 2.5 signals. All the guides I've read about board layout say not to put vias in between the differential traces, eg this guide
In a few cases it would be a lot easier to route the differential pairs out like this:
Looking at B5 and B6, they go around a power pad (with a via right next to it) and then continue together. I'd want to do that with a few ground pads also.
If I don't do that, I'll need either 3 mil trace and space instead of 5 mil, or a 6 layer board instead of 4 layer. Ouch.
So the question is, how bad is this really? Should I expect 10 mV coupled into the LVDS lines, or 100 mV?
The BGA is 1.0mm pitch, the traces are 7.7 mil spaced 5 mil apart for 100 ohm differential (but probably 5/5 while escaping the BGA). The top layer is signal, then ground 0.23 mm below that, then power. The BGA is an Artix-7 XC7A15T.
UPDATE The LVDS signals are clocked at 600MHz DDR.
UPDATE I'm more worried about current spikes on the power/ground coupling into the LVDS lines in different directions on each line, ie driving one line higher and the other lower, enough to cause the receiver to read the wrong (or indeterminate) value. Not so much about impedance discontinuity or reflections. But I really don't know... that's just intuition.
AI: The short answer is that I'd argue that a spacing change near the start or end point of a differential signal is not that bad. I'd also argue that 6 layers is not that many. But at high speeds, definitely keep all noise sources away from the clock.
For the longer answer, let's look at the reasons given. The Toradex source you cite mentioned an impedance discontinuity, and EMC compliance.
The impedance discontinuity comes from the fact that, if there is a via between traces, the traces are at first have a capacitive coupling with each other, then that coupling is removed and replaced with the via, then they couple together again. Any impedance change will cause a reflection (see Impedance Mismatch). The ratio of reflection is:
$$
\Gamma=\frac{Z_1-Z_2}{Z_1+Z_2}
$$
Where Z is the impedance change. Note that the real impedance is different for different frequencies. So, we get signals reflecting back to the driver, potentially damaging the driver by forcing an over or under voltage condition (not very likely, particularly not with an FPGA's LVDS, which was relatively rugged when I used it, but reliability is important), and then it can reflect back again from the impedance change at the driver, and hit the receiver. Worst case, it destructively interferes with an edge and makes it non-monotonic.
What needs to happen for this worst case scenario? I believe the rule of thumb is that you are in trouble if the reflection distance is over 1/6 the fundamental wavelength. So, if your edge rate (not switching frequency, but the rise time of your edges) is 1 ns, we know electricity travels about 6 inches per ns in copper, so if the reflection distance is over 1 inch, you are on thin ice, and should look at how much the impedance is changing. Similarly, if the via is near the receiving side of the signal, I would argue that the impedance mismatch is going to get lost in the impedance mismatch inherent in reaching the receiver.
The second issue Toradex points to is EMC compliance, which is a bit of a fuzzy term. They could be worried about coupling or trace length mismatch. I don't think coupling is necessarily an issue; these are differential lines so the net coupling should cancel out, unless you are really pushing your voltage margins. Trace length mismatch could be more common if there is an obstruction in your traces, but it is not a necessary outcome.
To go a bit more into coupling, in the ideal case, if you couple the same signal into a differential pair, you would prefer to couple into both. Doing that would bump them both by a few mV, and the differential signal (Vp - Vn) would be unaffected. As long as the absolute voltages of each signal are within spec, you should be fine. At very high speeds you may run into an issue where the signal couples into one line slightly before it would couple into the other. This would be an issue, but I'd argue even here having the noise couple into both lines is better than having it couple into one, because either the noise is reduced by the differential nature, or you have two problems instead of one.
If you are dealing with something very high speed, with edge rates under 1 ns, then you should be explaining the answer to me, and you should probably use a board with more than 4 layers. If you're just trying to drive an 80 MSPS ADC, this advice should be solid. Keep in mind that edge sensitive lines, like clocks, are by far the most important signals to treat correctly.
One final tip: If the going gets tough, look into microvias which may be placed in the BGA pads. |
H: A 5V @ 1A wifi surveillance camera placed 50ft away (indoor)
I need to place a Wifi surveillance camera near the entrance of my house where no power outlet is in that area.
I pulled a wire wrapping wire (awg 30) to the target location without thinking about wire resistance. And as you all expected, it didn't able to power the webcam.
The power the camera uses is 5V @ 1A.
I measured the wire resistance of my awg 30 wire to the location is 11 ohms (to and from) which is 6 ohms one way which is around 50 ft.
So my question is what is the minimum gauge I need to use to be able to power my webcam placed 50ft away from the USB power adapter?
Or how many awg30 wires I need to pull to lower the resistance to allow enough power to pass through?
I assume the common practice is that the voltage drop is less than 5% of the required voltage.
So 5% of 5V is 0.25V
R=V/I so to allow 1A to pass through the resistance should be 0.25V/1A = 0.25ohms.
From the chart:
https://www.cirris.com/learning-center/calculators/133-wire-resistance-calculator-table?
Therefore I need a minimum of one 14 Gauge wire (or a bundle of fifty awg 30 wires LOL) to power the webcam 50ft way?
AI: There are two ways to approach this
1) Use thick enough wire to run 5v
2) Accept a voltage drop and work round it, with easy-to-obtain parts
Run 5V
How much current does your webcam use? It may say '5v 1A' on the side, but have you measured it? It's probably less. But let's assume worst case of 1A.
How much voltage can you allow to drop to the camera? Let's guess at 0.5v, as 10% of your supply voltage. That may be too much, but let's do the sums for that as a baseline.
Dropping 0.5v at 1A requires a loop resistance of 0.5ohms or less. As your measured loop resistance is 11 ohms, you need 22 strands in parallel.
It would be more sensible simply to use thicker wire.
[pause] You've just updated your OP to reflect the above calculation, with slightly different starting assumptions, but the same general conclusions[/pause]
Work with the voltage drop
Your camera requires 5 watts. To deliver 5W into 11 ohms requires 7.5V. So a bit more than 15v supply at the house driving an 11 ohm loop and a voltage converter at the far end would be able to do the job.
Laptop adaptors (typical voltages around 19v) are easy to come by these days. You would need a buck converter at the far end, which are also easily and cheaply available, with an input range that covered at least 7 to 19v, and an output of 1A.
Choice
The cost and hassle of buying and drawing thicker wire, versus the cost and hassle of leaving the existing wire there, changing the driving power supply, and buying a remote voltage converter.
Notes. It's probably wise to increase the wire gauge further for option 1, as your 5v supply might be on the low side of 5v, and the camera a bit touchy about whether it gets 5.0 or 4.9v. An extra 0.25 or 0.5v drop could be the difference between it working or not. |
H: What form for Transfer Functions to use for filters and Bode plots?
I've seen some different forms for the equation of a transfer function and wonder which one is most correct and why? Does it depend on type of filter etc.?
Let's take an example and its transfer function: $$H(w)=\frac{V_o(w)}{V_i(w)}=\frac{R_2jwL}{R_1(R_2+jwL)+R_2jwL}$$
With some algebra you can get it on two different forms:
\$H_1(w)=\bigl(\frac{R_2}{R_1+R_2}\bigr)\frac{jw}{jw+\bigl(\frac{R_1R_2}{L(R_1+R_2}\bigl)}\$ where \$\frac{R_1R_2}{L(R_1+R_2)}\$ is the pole (and \$jw\$ is a zero?).
\$H_2(w)=\bigl(\frac{L}{R_1}\bigr)\frac{jw}{1+j\Biggl(\frac{w}{\bigl(\frac{R_1R_2}{L(R_1+R_2)}\bigl)}\Biggr)}\$ where \$\frac{R_1R_2}{L(R_1+R_2)}\$ is the pole (and \$jw\$ is a zero?).
\$H_1(0)=0\$, \$H_2(0)=0\$, \$H_1(\infty)=\frac{R_2}{R_1+R_2}\$ and \$H_2(\infty)=\frac{R_2}{R_1+R_2}\$.
Questions:
They are clearly the same (if I've calculated it all right), but which form is most correct and standard to use? Does it differ from type of filter, i.e low vs. high pass etc.? It seems easier to use \$H_1\$ to read of the constant \$\frac{R_2}{R_1+R_2}\$ as \$w\$ approach \$\infty\$, although I've seen the form av \$H_2\$ more often and it seems standard two try to get a "\$1+...\$" in the denominator?
Thank you!
AI: I'd be considering the gain factor as important and, for a high pass filter the gain is: -
\$\dfrac{R_2}{R_1+R_2}\$ at higher frequencies. I'd call it "K".
Clearly also for this type of filter, the effective series resistance is the parallel value of R1 and R2 hence I'd call that "R". Then I'd end up with a transfer function like this: -
\$H(s)=\dfrac{sK}{\frac{R}{L}+s}\$
This makes more sense because it uses gain (K) and the time constant (\$\tau\$) explicitly. If you are talking poles and zeros, it's probably better to use "s" rather than \$j\omega\$. |
H: GPIO input protection
I know this subject has been covered but I have a specific question regarding zener characteristics for microcontroller GPIO protection in vehicles where nominal voltage could be 12 or 24VDC. CircuitLab asks for Rs and Iz. I wanted to use as small a package as possible for space consideration but 100mW packages advertise a dynamic impedance of 100ohms or more. Running the DC sweep simulator made the voltage at Vout easily rise well above 5V. With the 220mW package, the impedance is advertised at 19ohms. Running the simulator shows me good up to 60+ volts which is my goal. I feel like the simulator can't really function properly without a more detailed model and that the smaller 100mW package would probably be just fine? Would appreciate any thoughts on this. This circuit is more or less based on this Digikey white paper. I didn't feel the input clipping diode to be worth the space it took so I omitted it.
AI: Running the DC sweep simulator made the voltage at Vout easily rise
well above 5V.
The MMBZ zener diode is rated at 4.7 volts at 20 mA. At this current there is 19 ohms of resistance hence you can model the zener as a 4.32 volt device in series with 19 ohms and get a reasonable result. The 4.32 volts is as a result of reducing 4.7 volts by the volt drop across the 19 ohm resistor at 20 mA.
However, given that you cannot drive more than about 5 mA into the zener (24 volts/4.7 kohm) you will never exceed 4.7 volts.
I feel like the simulator can't really function properly without a
more detailed model and that the smaller 100mW package would probably
be just fine? Would appreciate any thoughts on this.
Without a link to this device, darkness reigns over this question. |
H: Downed Power Line Scenarios
In the case where you hit a power line with your car, is it possible if you
a) touch the frame of the car [(i) either one or (ii) both hands] and your body has no contact with the ground, you will not be electrocuted.
Similarly, if you b) open the car door and have one foot on the ground and the other foot still remaining in the car. (keeping in mind that that the body is not in contact with the frame of the car)
I may have misunderstood something, but is the reason that you do not get electrocuted due to the negligible potential difference for scenario a) with both hands and that one hand touching the frame will result in the same reasoning for scenario b) where you are not completing the circuit that you won't get electrocuted?
Thank You!
AI: In the case where you hit a power line with your car, is it possible if you
a) touch the frame of the car [(i) either one or (ii) both hands] and your body has no contact with the ground, you will not be electrocuted.
It is current through the body that kills. The levels are quite low and we typically set RCD/GFCI devices to 30 mA as a safe limit.
To get current to flow through the body a voltage (potential) difference is required between two points of the body. Since the car's chassis is steel or aluminium all points on the car's chassis will be at the same potential so there is little risk.
Similarly, if you b) open the car door and have one foot on the ground and the other foot still remaining in the car. (keeping in mind that that the body is not in contact with the frame of the car)
You are relying on the insulation of the carpet and your shoes. This might be OK for domestic voltages but not for distribution voltages.
I may have misunderstood something, but is the reason that you do not get electrocuted due to the negligible potential difference for scenario a) with both hands and that one hand touching the frame will result in the same reasoning for scenario b) where you are not completing the circuit that you won't get electrocuted?
You are missing the capacitative current.
Figure 1. Electric shock through body to ground capacitance. Source: All About Circuits.
I can't find a good illustration but if you imagine that's a capacitor between the guys body and the ground then with AC voltage an AC current will flow through the body capacitance to ground. This effect is used safely in neon screw-driver type phase-testers by including a high value resistor in the circuit. Without that there is danger of electrocution.
For power distribution systems at higher voltages it is common to fit ground fault detection relays which, if a ground fault is detected, connect that phase to ground to reduce the risk to anyone coming in contact with the wire. |
H: What is incorrect with my 555 LED flasher circuit?
I have built a circuit to flash an LED using a 555 timer IC, but it doesn't flash... the LED just stays on steadily.
-- I carefully followed the instructions on a common tutorial, which is: http://www.instructables.com/id/Flashing-LED-using-555-Timer/
-- Here you can watch a video where I give a nice clear display of the circuit I built, and what the IC pins and leads all connect to. Video is at: https://youtu.be/qYDeqq9Bua4
-- I have tried it with 9V battery and also 4 AA's. Same result. I also tried with different color LEDs in case the draw is different somehow. Same result.
-- My capacitor: I forgot to mention in the video that I am using one that is "Electrolytic Cap 1uF / 50V" ... the instructions called for 1uF capacitor and this seemed to me to fit that specification.
-- I have checked the positive/negative on the LED and the capacitor. And I know that you see exposed leads to resistors around, but nothing is shorting out...
-- Here is a photo of the circuit. I'm sure very hard to see it. The video linked above(even just the first several seconds of it) might be easier to see. Photo is:
-- In the tutorial I followed, linked above, this is the schematic that I I was told that we were following:
-- As you can see, I am clearly novice at building electronics from scratch. I dabble in other IT stuff like Arduino but trying to get smarter on the electronics here.
Giant, huge thanks for your time and any help you can give!
Eric
AI: That doesn’t look like a 470k resistor in your photo. It looks more like a 470 ohm. Do you have a multimeter to test it?
The correct colours should be yellow, violet, black, orange in the 5 band colour code, or yellow violet yellow in the 4 band colour code.
The brown band indicated it is a 1% tolerance resistor on the 5 band colour code.
Just noticed @davetweed has made a similar comment, |
H: capacitor placement: series or parallel with IC?
I have doubts about capacitor placement near ICs,
It's a good place for it?
----EDITED: IMAGES CHANGED TO SCHEMATIC -------------------------------
Thanks in advance!
AI: Figure 1. OP's original circuit.
The capacitor symbol indicates that it is made of two parallel plates with no contact between them. The capacitor can hold charge on the plates and can absorb some current while it charges up. In your arrangement it blocks battery power reaching the IC as DC cannot flow through it.
simulate this circuit – Schematic created using CircuitLab
Figure 2. The correct installation of the decoupling capacitor.
The purpose of C1 is to act as a tiny battery right beside the chip. When the chip switches its output a very brief surge in demand can cause a momentary drop in voltage at the chip terminals due to resistance and inductance of the battery and wiring. The capacitor provides a tiny energy reservoir to supply the current during these momentary high demands. It can also absorb transients in the supply caused by other chips on the same power lines.
I didn't know that ignorance is something to be punished.
You're not being punished. Read the comments from a neutral point of view. You've got a pile of guys trying to help within an hour of the post! If you can respond to the comments well - which I think you did - it's a great site. |
H: How to know / test a supercapacitors really store the energy
If i charge a supercapacitor, how do i know or test this supercapacitors that it really store the energy (like a battery) and doesn't discharge ? Can anyone give some reference or method?
Can i use the multimeter to see whether the supercapacitor have voltage or not?if it has voltage ,then it does charge the energy?
AI: how do i know or test this supercapacitors that it really store the energy (like a battery) and doesn't discharge ?
Put a high impedance voltmeter across the super capacitor and plot the reduction of voltage with time. Energy stored is \$\frac{CV^2}{2}\$ so as the voltage dwindles, so does the energy. If V reduces to 90%, Energy has reduced to 81%. |
H: P-channel enhancement MOSFET behaviour
I'm puzzled in understanding how the P-channel enhancement MOSFET in figure is activated.
The role of the MOSFET is to disable the VBAT supply when VUSB is provided (a usb cable is plugged).
I kind of understood that when VUSB is provided, 5V are both at gate and source, turning off the MOSFET, which is fine.
From the datasheet Vgs=-0.55V, so for the MOSFET to turn on and let VBAT power the U1 voltage regulator, there should be a difference in voltage between gate and source.
Let's assume VUSB is disconnected (usb cable unplugged), the MOSFET is off and VBAT is connected to a 3.7V battery, where does the Vgs of at least -0.55V comes from?
Mosfet datasheet
Thanks!
AI: I'm puzzled in understanding how the P-channel enhancement MOSFET in
figure is activated.
When VUSB is not present, D1 is reverse biased so can be ignored. Under this situation the gate is connected to GND via R7 and the gate voltage settles at GND because the gate is insulated from the rest of the MOSFET. This is 50% of the criteria needed to turn on a P channel MOSFET. The other 50% comes from the source being a volt or so higher than the gate (MOSFET dependent).
When VBAT is considered, the obvious choice of conduction is through the MOSFET body diode thus raising the source voltage and, because the MOSFET is P channel (and the gate is now at GND), the MOSFET turns on and offers a high conduction path for current to be taken by the regulator from VBAT. This shorts out the previously conducting body diode and very little forward voltage is dropped across the MOSFET as it supplies current to the voltage regulator - the MOSFET is behaving as an "ideal diode".
If VUSB is high it will turn off the MOSFET and VUSB will source the current needed by the regulator through D1 losing about 0.7 volts in the process. The body diode should be reverse biased now so no current should be taken from the battery. This of course presumes that under normal circumstances VUSB is bigger than VBAT. |
H: How can I increase audio output volume from this board?
I have this Audio DAC board: https://www.banggood.com/PCM5102PCM5102A-DAC-Decoder-Board-I2S-32Bit-384K-For-Raspberry-Pi-Red-Core-Player-p-1259752.html?rmmds=myorder&cur_warehouse=CN
I drive it from an ESP32 via I2S which is working wonderfully thanks to this library. The problem is, the audio output is really quiet. I want to drive the speakers louder.
I have an LM380N(datasheet) which I believe is the right chip to increase the power going out to the speakers, but I am not sure where on this board to 'tap into' in order to drive the LM380N correctly. I presume I cannot feed the LM380N my I2S signal, so where in the chain will the LM380N sit, and how can feed it the correct input / outputs.
Any advice on what to do here?
AI: A little digging around will tell you that the audio outputs of the DAC board are "line level" and not intended for speakers: -
I am not sure where on this board to 'tap into' in order to drive the
LM380N correctly.
You connect your audio amplifier's input to the "gold" RCA phono jacks at the top left of the picture above.
so where in the chain will the LM380N sit, and how can feed it the
correct input / outputs.
The output connects to your speaker as shown below: -
And your input connects to the gold phono output left or right. You'll need two LM380 chips for stereo. |
H: Please explain the terms line voltage, phase voltage, line current and phase current in a 3-phase circuit
I have searched online for an explanation of these terms and was unable to find a clear enough one. Request you to explain with reference to the images below:
Thanks
AI: Phase voltage is between A and N (or B/C and N). Also a to N or b/c to N.
Line voltage is between any two of the three feed lines (ignoring N if present)
Line current flows down any line between source and load (ignoring N if present)
Phase current is the current in any load element whether star or delta |
H: Constant voltage driver max current output as a limiting mechanism?
Let's say I have a 12V LED, which can handle 2A, and a 12V 1A constant voltage driver.
Presumably, the driver will limit the current to 1A.
Is this a good method of limiting the current (assuming 1A is fine with your application) ?
What exactly about the driver limits the current, and could it be bad for the driver, that the LED would pull more if it could?
AI: Is this a good method of limiting the current
I would say No, it is not a good idea to rely on the maximum rated current of the power supply.
Usually the maximum rated current of the power supply is the maximum current it is designed to handle, this does not say anything about the actual current which will flow.
I can design a 12V, 10A power supply and sell it as "rated for 1 A" (because I'm an idiot or just because I feel like it). Then you connect your, say 10V, 1 A LED and you assume that my supply will limit the current to 1A. But that will not happen. My supply supplies 12 V and can deliver 10A if it has to (even though I rated it for only 1A). So your LED will get 12 V and perhaps draw 5 A, your LED will then be damaged.
In your case using a 1 A supply with a 2 A load is also a bad idea. It is very well possible that the LED will ask 2 A and the supply will deliver what it can deliver, which might be more than 1 A.
Problem is, the supply is rated for 1 A and when you draw more than 1 A, anything can happen. It could safely supply the higher current. More likely the supply will be overloaded and therefore overheat and in the end it will suffer damage.
You cannot and should not rely on a 1 A supply actually monitoring the current and regulating such that only 1 A will flow. Only Lab supplies with current regulation can be expected to do this.
The general rule in the case of constant voltage is that the current rating of the supply should be the same or higher that the current required by the load (your LED).
If you had a 12 V 1 A constant current LED driver then indeed you can use that with a 12 V 2 A LED. The LED would simply get 1 A from the driver and not burn at full brightness. But you mentioned that the supply is constant voltage so this does not apply in your case. |
H: Contradiction while solving circuit problem!
Translation: Find the supplied power from the 4V Source using meshes method
I proposed five equations related with the circuit but I only find contradiction cause I find Rv value fixed. I suspect there should be voltage drops in current sources but I am not sure I think I am doing something conceptually wrong.
Here my calcuations
I skipped some steps but I hope you can follow me.
I am currently getting I2=I3 = 0 which makes the first two equations to fix Rv. By my understanding it is a contradiction.
Note: .5Nk is a name for the resistor value (proportional to N), I have just called it Rv.
AI: Let's set up the mesh equations as you have the schematic drawn up:
$$\begin{align*}
0\:\text{V}-200\cdot I_3-600\cdot I_3-400\cdot\left(I_3-I_2\right)-V_{5\:\text{mA}}&= 0\:\text{V}\\\\
0\:\text{V}-R_V\cdot\left(I_2-I_1\right)-400\cdot\left(I_2-I_3\right)-V_{V_2\over 400}&=0\:\text{V}\\\\
0\:\text{V}+4\:\text{V}-500\cdot I_1+V_{5\:\text{mA}}-R_V\cdot\left(I_1-I_2\right)&=0\:\text{V}\\\\
I_1-I_3&=5\:\text{mA}\\\\
I_2=\frac{V_2=200\cdot I_3}{400}&=\frac{I_3}{2}
\end{align*}$$
This provides 5 equations and five unknowns: \$I_1\$, \$I_2\$, \$I_3\$, \$V_{5\:\text{mA}}\$, \$V_{V_2\over 400}\$.
Note that this includes the fact that there are, in fact, voltage drops across your current sources. Those are just two more variables, as shown.
Solving this yields 5 functions which depend upon \$R_V\$.
I can't tell you if \$I_2=I_3=0\:\text{A}\$ without knowing more about \$R_V\$. And I don't understand \$.5\:N\:k\$. (Does it mean \$500\cdot N\$?) So I'm stuck at this point, if you are looking for numerical results that aren't functions of \$R_V\$ (or N.)
(You can get \$I_2=I_3=0\:\text{A}\$ if and only if \$R_V=300\:\Omega\$. For obvious reasons.) |
H: How can you calculate a railgun's exit velocity?
Having a cylindrical iron container with wall thickness of 20 cm, and a total weight of 50 tons when filled with its cargo, how would you be able to calculate its required voltage and current input in a vertical railgun system, with a needed exit velocity of 12km/s? For example, the rail diameter would be 80cm. There would be 4 in total, 2 positive terminals and 2 negative terminals, connected to each other independently, through an 'insulated channel', so it doesn't make contact with the container itself.
Also, is there any formula that can be used for calculating current and voltage required for a certain exit velocity, or exit speed having a certain current and voltage input? Would it depend on many other factors, if so, which?
If any more specifications would be required for such a calculation, please make some as an example, it would be very helpful.
AI: This page should help you, it's pretty much the exact calculation you're looking for.
https://www.wired.com/2014/08/the-physics-of-the-railgun/
Note that the projectile itself MUST be conductive, as this is the way that railguns work. |
H: I have a 9V battery, but I only need to output 4.5V from it. How do I accomplish this?
This is the circuit I have so far: Falstad Voltage Divider Circuit
simulate this circuit – Schematic created using CircuitLab
As you can see, I tried using a simple voltage divider, but this interferes with the other resistors in the circuit and does not give me the desired voltage. I want to know if there is a way to turn a 9V source into a 4.5V source WITHOUT changing anything in the circuit as it is.
AI: Okay so this is what I have come up with so far. I used an inverting amplifier. I think this accomplishes my goal unless I am missing something: Updated circuit |
H: Replace copper capillary thermostat with digital temperature controller relay
Our lab has an old New Brunswick Model G25 incubator shaker. Its temperature control function is broken lately. We would like to replace the two copper capillary thermostats with modern digital temperature controllers. Such as this one on Amazon.
I found its manual. On page 32, it has the circuit diagram. I found an RCAS bridging the "control" thermostat 1TAS-2 (pic 1). In the manual of another similar model, I learned this is a resister capacitor in series circuit (1mF+100Ω, pic 2).
My questions are:
What is the purpose of this bridging RCAS design? To provide a low constitutive current to the heater circuits? To prevent spark or surge from the thermostat?
Will it affect my attempt to replace the capillary thermostats with digital controllers?
Thank you very much. I have rudimentary electrical skills. Any suggestions on this project will be appreciated.
AI: RCAS is intended to extend the life of the contacts by absorbing arc energy during shut off to the motor. It must be used on the new relay. ( plastic cap and power resistor , same values )
Although the thermostat has a 10A relay and the G25 is rated at 10A , 10A relays are only rated for heater loads and not inductive motor loads which generate a hotter arc when the motor acts as a generator shutting down.
So if you can replace it with a 25A relay , somehow, or get a thermostat to drive a 25A relay, or use the 10A relay to drive a 25A DC relay using the internal supply voltage then it will last longer. A reverse diode is needed across the DC relay coil to suppress an impulse voltage during shutoff from inductance.
Remote location of the thermostat may pose noise and attachment problems but needs to be thermally attached like the copper tubes perhaps with thin epoxy. |
H: Number of point to point link
I dont know if this is unrelevant here but i wish if someone could help me .
The number of point to point links required in a fully connected network for 50 entities is
(a) 1250
(b) 1225
(c) 2500
(d) 50
My answer is 1225 but its 2500 every where in internet .
As per i know the mathematics is n(n-1)/2 but every where its 2500 , I dont know what is the concept i am missing .
Thanks in advance
AI: The answer depends on your definition of "fully connected network". If the normal meaning is used, where each connection is bidirectional, then the answer is 1225.
It's possible that the questioner is using a weird definition where each link is unidirectional, in which case the answer would be 50*50=2500. This would (I think) be very unusual, and it's more likely that the questioner just made a mistake. If this were ever asked in a formal setting, I would say 1225, and if marked as wrong, I would complain to the examining body.
It's probable that the results you're seeing on the internet have all been copied from the same incorrect source. |
H: Eliminating or reducing the red glow from IR LEDs at night
tl;dr; my question is simply this: is there a way to hide a bunch of IR LEDs (for a night-camera) so they don't get such a red glow at night?
Preferably not at the expense of the light output, but that would be ok too, if that's the only way.
Background (not-tl;did-r): I setup a baby cam for my son when he was born with a Raspberry Pi and a Pi cam with no IR filter so I could watch him at night. It has worked flawlessly and frankly I couldn't imagine parenting without it. He's now 1.5 years old, and sometimes wakes in the middle of the night and sits there talking to his stuffed animals.
Just a few days ago he seemed to notice the IR light for the first time, and now he'll be fine until his eye catches the light and he seems to get terrified and start crying once he sees it. At least, I assume it's what's scaring him (there's also an LED on the Raspberry Pi itself).
The light is more powerful than it needs to be, I believe it's a 48-LED cluster, so if a solution involves dimming the light, it would probably be fine. I was thinking about putting it in the opposite corner of the room, but keeping the camera above him, but I think the slats from the crib would block much of the light and it would be very shadow'y. And I'm not so sure that would keep him from seeing it.
I was thinking maybe some sort of plastic (acrylic) plate or filter. I'm not sure.
Thanks
Edit, here's a pic of the setup. This is an older pic of an older IR light that I got from Ebay. Half the LEDs burnt out within about 3 or 4 months. It's since been replaced by another cheap Ebay one, but same basic setup. I'm definitely open to moving things around so it's not so... "in yo face!"
AI: If you use 940nm IR LEDs instead of the shorter wavelength ones, most people will not be able to see the red glow. Our eyes are slightly sensitive to the shorter wavelength IR resulting in the red glow. Most IR sensitive cameras don't have a problem with the 940nm LEDs although some are slightly less sensitive at that wavelength. |
H: Increasing voltage, but same current
There are a lot of questions asking what happens if you change the current, but keeping the same voltage. If more current is flowing to me it means you can damage the device. But what if it is the other way around? What happens if you increase the voltage, but have the same current?
Let's say I power on a device with an adapter that outputs 5 volts @ 2 amperes. If I would like to connect that same device to an adapter that outputs 20 volts @ 2 amperes, will I burn it? I think you burn a device by passing too much current, no? Could increasing the voltage also burn it if you are passing the same current?
AI: The load determines the ratio of current to voltage at its terminals.
If you control the voltage you supply, it determines the current.
If you control the current you supply, it determines the voltage.
It's possible to break a load by supplying, or letting it define, too much of either.
Let's compare a 5 V, 2 A adapter, and a 20 V, 2 A adapter, driving different loads.
We'll drive a 100 ohm load, which has a thermal limit of 1 watt. With 5 V, it will draw 50 mA and dissipate 250 mW, and run happily. With 20 V, it will draw 200 mA and dissipate 4 watts, and eventually overheat.
Now let's drive a 1 ohm load, which has a thermal limit of 10 watts. With a 2 A supply, it will collapse the input voltage to 2 V, and dissipate 4 watts. It doesn't matter whether it's the 5 V supply, or the 20 V supply driving it; if they both put out a constant current of 2 A, then the load will drop their voltage to 2 V. Different adapters may behave differently to the current limit however; some will deliver a constant current, some will shutdown for a moment and try to restart, and repeat that cycle continuously, and some will deliver a lower current (so-called foldback limiting) to protect themselves.
Now let's connect the gate-source junction of a FET, that has a voltage limit of 15 V. On 5 V, it will draw essentially no current and survive. On 20 V, it will draw essentially no current, punch through and be destroyed. |
H: Two switches and one bulb
I have a battery, 2 sw's and one bulb.
The question asks to design a circuit that with every change in one of the sw's the bulb will change it state - no matter what is the other switch state.
How can I dot that?
AI: Sounds like the circuit for the landing light switch, one switchback bottom of stairs and second at the top of the stairs.
http://www.lightwiring.co.uk/two-way-switching-3-wire-system-new-harmonised-cable-colours/ |
H: Difference between LVDS and "Low Power LVDS"
It sounds like a double emphasis but indeed, pin 25 of the LTC2323 (http://www.linear.com/product/LTC2323-16) I lets me choose between:
CMOS (GND)
LVDS (IOVDD)
Low-Power LVDS (leave floating)
As often, the datasheet does not bother discussing difference at all and neither does my Google search or Wikipedia ersult in enlightenment.
I want to use "LVDS": I connect the digital lines differentially (100 Ohm terminated) to a Spartan-6 FPGA. The IO voltage is 2.5V. Shall I set the pin to LVDS or Low-Power LVDS?
AI: As shown on page 4 of the datasheet, the voltage over the 100 Ω load resistor is smaller in low-power mode, i.e., the current is smaller:
LVDS is a standard (TIA-644).
You can use low-power mode if your FPGA has a more sensitive receiver that is able to cope with 75 mV (the datasheet would tell you this). |
H: Data source switch with simple logic level shift
I would like to hack a 3.3v UART controlled Self Balancing Scooter in away that it can keep old logic (control), but optionally it should be able to switch to external control data source.
The question is will the presented schema do the job if
3.3v Data IN - is the original source. I have no control on it.
Switch 5.0v - is the switch to disconnect original source.
5.0v Data IN - is come from an Arduino UNO board and need to be logic level shifted to 3.3v
3.3v Data OUT - is the UART signal connected to motor control board of the hoverboard
In practice
I cut the wires between the Motor Controller and the Gyro Board.
Unfortunately I have no information about the schematics of the current circuitry.
AI: Your circuit as is wouldn't work well for several reasons:
Your transistor base has no resistor
The output is driven only by diodes, so there is no way to pull the output low
You could add a pull-down on the output, but if the input pin to which the circuit connects has an internal pull-up resistor (which is likely for a UART RX), they will fight each other. Your 1k series resistor and pull-down resistor will also fight each other acting as a level shifter.
Even if you added a pull-down resistor on the output, when the switch pin is selecting the 3.3V input, the output will stay high if 5V data input is high, regardless of what the 3.3V input is doing.
You could always use an SN74LVC2G157DCUR.
These are dedicated 2:1 multiplexers with select line. You'll get better performance than trying to hook up a circuit with transistors and resistors. As they cost less than 40p in singles, they aren't going to break the bank.
The nice thing about them for your application is they also support down-translation. That means that if you run the IC from a 3.3V supply, the inputs remain 5V tolerant. So in your case you would make the connections:
3.3V Data In
5V Data In
N/C
GND
3.3V Data Out
Switch 5V
GND
3.3V Power
No need for any level shifting as the chip will do that itself. |
H: Is it possible to find an inverse system for this difference equation?
y[n] = x[2n + 1] + x[2n − 1]
I know that a system is invertible if none of two inputs results in the same output. In my opinion two such inputs exist so this system is not invertible since any number of x[n] can be a found which satisfy x[n]+x[n-2]=y[(n-1)/2] . But I am not sure whether I am right or not.
AI: Just think of your system in simpler terms. Assume \$x[2n + 1] = a\$ and \$x[2n − 1] = b\$. Therefore:
$$
y = a+b
$$
Can you find a unique solution for both \$a\$ and \$b\$, knowing only the value \$y\$ ? The answer is no, there are infinte possible solutions. However, if you absolutely must find an inverse, constraints could be added to the problem, so that we have new probabilistic possibilities.
Are \$x[2n + 1]\$ and \$x[2n - 1]\$ completely independent from each other, or is there some correlation? Is \$x\$ limited in amplitude or bandwidth? Perhaps a stochastic process can describe it? If enough constraints can be brought to the problem, one could then find an "expected" value for \$a\$ and \$b\$.
For example, say \$x\$ is described by a gaussian stochastic process, with mean \$\mu\$. Then the expected answer would be the one which brings both \$a\$ and \$b\$ closest to \$\mu\$.
One must realize that the system must then be solved for all \$n\$ in your considered range (do you wish to find solution \$\forall n \geq 0\$ ?). In this particular problem, this means solving:
$$
y[0] = x[1] + x[-1]\\
y[1] = x[3] + x[1]\\
y[2] = x[5] + x[3] \\
\dots
$$
If by some constraint or known value, you can find \$x[-1]\$, then you can solve for \$x[1]\$ and \$x[3]\$ and all others \$x[2n+1]\$.
In sum: is the system invertible? In strict terms, no. Is it possible to find an expected inverse signal? Given sufficient constraints, yes. |
H: How to ground wi-fi antenna outer wire on circuit board connector?
I have a quick question regarding a Wi-Fi antenna modification I am doing to my drone controller. I want to replace the antenna which is soldered to the board in the controller. I want to replace it with a SMA connector, so that I may mount an external antenna instead.
My question is: how do I ground the outer wire on the circuit board? Is it okay to run a wire carrying the outer wire current to GND? Or do I have to use the antenne ground? Where would I find that?
AI: There's no proper wiring of the return path on that board. If you connected the shield of your external antenna "somewhere" to GND, you won't get an external antenna but just a long internal+external antenna wire.
Find the WiFi PHY chip (could be that one near to the existing antenna) and check which pin is HF ground. Your cable shield goes there.
EDIT: Oh yes, and Marcus is right, wire antennas are often enough not 50Ω impedance so you may need an impedance matching transformer. |
H: Need for Temperature Compensation of Current Mirror
I am currently learning about current mirror configurations. I have made two of them so far. Both of them worked as desired but, when heated or cooled, the current through the right side (the side where the output is taken from) decreased or increased significantly with small temperature differences.
simulate this circuit – Schematic created using CircuitLab
\$R_{load}\$ for both circuits was low or shorted to +10V. Both circuits were set to mirror the current of 500 uA. All transistors were hand-matched (they are all very close to each other as far as beta is concerned).
Without emitter degeneration both circuits were significantly affected by temperature, especially Fig. A, where the current through \$R_{load1}\$ changed by 100 uA or more (1 second of heating) as I touched either of Q1 or Q2 with a finger tip; but as the transistors Q4 and Q5 were touched with a finger tip, the current through \$R_{load2}\$ changed by 50 uA (1 second of heating also), which is less then in the first example but still too much.
With emitter degeneration both circuits greatly improved their temperature stability. For example (the \$R_e\$ added were 1 kOhm) if I refer to Fig. B, the current through \$R_{load2}\$ changed only by 10 uA (when heated by approx. 1 second), while the result with Fig. A was a bit worse.
Both circuits are improved as emitter degeneration is added to Q1/Q2 or Q3/Q4. In both examples, current through Q1 or Q3 was approximately constant at all times but the current through Q2 or Q5 wasn't even close to that.
I there any way to compensate either of circuits shown here, due to varying temperature? I thought that Q5 was going to correct the temperature variation error in current but obviously didn't.
AI: The three main steps are
a) Use as much emitter degeneration as you can
b) Match the temperatures of Q1 and Q2
c) Match the dissipation of Q1 and Q2
For (b), at the very least, glue Q1 and Q2 together. Far better is to use a monolithic transistor array like the CA3046, which constains 5 transistors made on the same substrate. For a really hardcore thermally matched pair, the LM394 'SuperMatch' pair uses thousands of transistor die connected like a chess board.
Q5 not only increases the output impedance, but also controls the dissipation in Q4. Play with series drops on Q5 base or emitter to equalise the Q3/4 dissipation match.
A slightly more complicated solution with less bandwidth but much more precision is to do away with Q1, and use an op-amp to drive Q2 to equalise the voltage drops on Re1/2. Replacing Q2 with a FET eliminates any beta variation contribution to the output accuracy well. Then you only need to be concerned about amplifier Vos drift with temperature, and tempco or Re1/2 resistors. |
H: What is the power plug in the photo called?
Is the plug shown in the photo, which looks like IEC 320 but with angular tips, standard? If so what is it called?
AI: Apparently, there are HP server power supplies that have a non-standard connection.
They are found on ParallelMiner as KT-1200-200V-1 for example.
We use a custom 12inch power cord to bypass the proprietary AC plug
Behold the custom cable:
It's just a cable with quick-connects.
Apparently this is the 277VAC version of the power supply:
HP 1200W Common Slot 277VAC Hot Plug Power Supply Kit (717359-B21).
The plug and socket are called LS-25 and LS-26. (an adapter is sold by stuartconnections)
HP also sells adapter TK801A and TK802A.
(source) |
H: Op-amp voltage calculation
\$I_3=10*10^{-6}A \$ and \$ I_4=30*10^{-6}\$.
Then i want to calculate the \$v_0\$ .
By V=IR , I get \$200k*I_4\$= -6 V.
By voltage divider rule, \$\frac {40k}{50k}*-6V=-4.8\ \mathrm V\$ .
Can i understand that part like this below?
AI: I hope you can understand my point.
Not really.
simulate this circuit – Schematic created using CircuitLab
Figure 1. The output and voltage divider.
Your calculation is correct but the -6 V appears at the op-amp output. The 10k and 40k are a potential divider as you correctly point out and your calculation is correct.
Your second diagram is showing the divider and \$ V_O \$. When doing the calculations we need to assign a direction for the voltage calculation on the diagram. In your example you have chosen the bottom of the 40k as the negative for the measurement and the top as +. The sign of the calculation result indicates that, actually, the top of the 40k resistor is at a lower voltage than the bottom. Everything is mathematically consistent. If you connect your multimeter black lead (COM) to the bottom of the 40k resistor and the red (V) lead to the top the meter would display -4.8 V. |
H: Clarification on R, I, and J type Instruction formats in MIPS
I would like some clarification on some concepts of register types, to know if I understand it correctly.
If I had a 32-bit CPU.
Would that mean that the max number of operations that can be executed by the CPU be: $$3\times2^{6} = 192$$
Also, would the number of registers in the CPU be:$$2^{5} = 32$$
Which would then make the main memory be: $$32 \times 4bits = 64 bits = 8bytes$$
Finally, the maximum size of the target address of the J-type would be:$$2^{26} $$
AI: Would that mean that the max number of operations that can be executed
by the CPU be: \$3\cdot 2^6 = 192\$
Not quite. The CPU needs to be able to distinguish whether an instruction is an R, I, or J type instruction from the opcode, so the number of opcodes is just \$2^6=64\$. However, the R type instructions also contain the 6 bit funct field which acts as another opcode field for the R type instructions. R type instructions always have an opcode field of 000000, so your total number of instructions is \$2^6-1 + 2^6=127\$, because you have \$2^6\$ opcode encodings, but you use one to select the R type instruction, where you then have \$2^6\$ more instructions from the funct field.
Also, would the number of registers in the CPU be: \$2^5=32\$
Yep, MIPS has 32 registers.
Which would then make the main memory be:
\$32×4bits=64bits=8bytes\$
I'm not sure how you're getting this. The (maximum) size of main memory depends on how many bits are in an address * the smallest addressable unit. MIPS has 32 bit addresses (that's what a 32 bit cpu usually means), and the smallest addressable unit is 1 byte. That means the maximum amount of memory is $$2^{32}bytes = 4,294,967,296bytes = 4GiB$$
But how do you use a 32 bit address if there's only 5 bits per field in an instruction? MIPS is a Load-Store architecture, which means most instructions only interact with registers, and only load and store instructions can access memory. So for example, say I want to add 5 to the int stored at address 0x14859868:
lui $8, 0x1485 # load upper 16 bits into register 8
ori $8, $8, 0x9868 # load lower 16 bits into register 8
lw $9, 0($8) # load register 9 with the contents of memory at 0x14859868
addi $9, $9, 5 # add 5 to the number in register 9
sw $9, 0($8) # store the contents or register 9 to
# the memory pointed to by register 8
Instead of specifying the address directly, I load the address into a register ($8) and use it as a pointer to access the memory. |
H: Super capacitor in UPS system instand of battery
I got an idea to use super capacitors in UPS system like battery replacemant. I have UPS what give me 220V/2000W what use 3 batteries 12V/7,2A.
That UPS power whole my office (lights, computers, monitors) for 2 hours with no electricity. I want to get more efficient power source for my UPS and think that super capacitors can be good solution.
What you think and what capacitors to use?
AI: This is not a good idea. Capacitors & Supercapacitors are designed to be used for short pulses of high current. A UPS is not a great application for them, which is why they use batteries. In any case, let's do the math.
Let's assume you want to use this supercapacitor. The specs are:
Capacitance: 3000F
Max Voltage: 2.7V
Cost: $56
Dimensions: 6cm*13cm
You say your current 2000W ups powers your office for 2 hours. This means that it can store
$$2000W * 2 h * 60 m * 60 s = 14.4MJ$$
Each capacitor can store
$$ 0.5*C*V^2 = 0.5*3000*2.7^2 = 10.9kJ$$
So you need:
\$ \frac{14.4* 10^6}{10.9*10^3}=1317 \$ capacitors, which would cost you $73,745, and take up half a cubic meter of space. Not to mention Transistor's point that a UPS expects its batteries to be putting out a roughly constant voltage, which these capacitors won't do. You'd either need to redesign the UPS or throw even more capacitors at the problem. Either way, it's not a practical solution for UPS energy storage, which is why no one uses supercaps for their UPS. |
H: MC34063 inverter stops switchng at low current and burns out through inductor
I fried a few MC34063 on the breadboard this evening.... was trying to make a 10V to -15V inverter to supply 30mA. It was working fine. However, the chips and inductor suddenly became hot when toggling the input power a few times. About 0.8A was flowing through the inductor when the chip failed. I thought the inductor core saturated, but simulations are also giving the same result if I lower the switching current. A similar circuit is below (actually I used 1mH 3.5Ohm inductor and Rsc=0.63Ohm (1Ohm turned out to be actualy 0.63Ohm)). The circuit below works fine if R3=1Ohm, but becomes weird if R3=2Ohm. Current flows into Vdd and out through Isns in the simulation (have not checked this in the failed parts). (Also, my timing cap was 1nF, not 330pF, it was running at about 33KHz, but oscilloscope showed gaps between clusters of square waves).
I checked with and without load on the breadboard, as well as simulation. Same results... and a pile of black chips (It took me a while to figure out). The inductor is fine, even after heating a bit each time.
So, what's going on? I know that MC34063 is an old design and all that, but this is like walking on eggshells. Everything works... till some kid toggles the power switch a few times...
edit: Schottky diode orientation is fine. Here is the figure from datasheet, for reference
I agree with all comments about the breadboard. But, can anyone explain why the simulation fails if I decrease the current by increasing Rsc, or if I decrease the inductor value? I suspect the same thing happened on the breadboard. The inductance decreased enough so the darlington continued to conduct. Why did the current sense not work, even in simulation?
edit: I simulated while ramping up the voltage from 2 to 5 to 10V, every 10ms, and this one seems to simulate fine without the inductor current going up and locking (all other values same as the first schematic). May be the input cap is part of the design. Although, I did manage to fry one chip when switching off power to the circuit, can't figure out how that could have happened. I'll put in the input cap and try to fry another chip.
edit: I'm accepting analogsystemsfr's answer for pointing me towards capacitors. Initially I had a 330uF 25V on the output. I replaced it with 100uF 25V and added an input cap 100uF 25V as per the datasheet (100uF). All Capacitors were old but had tested OK on LCR meter before use. Both 100uF started heating up today, and I checked all three caps after that. All three caps had gone bad (but inductor and chip had not heated, and I was still getting my -15V output, althout very slowly after switch on). Replaced input and output caps with new 100uF 50V, and then input with 1000uF 50V. All are working fine with no heating, and tested OK after use. I toggled the power button maybe 40-50 times, and the chip did not fry. So I guess it was the capacitor. I still have no idea why it went bad. I have -15V across the caps, so it should have been fine, unless my input 10V got added to it somehow and became 25V across the caps during switching. Repetitive 25V across an old 25V cap may have damaged it... is my best guess now. And that shorted cap possibly led to chip failure. [My LCR meter shows two of the failed caps as a pair of opposing diodes with Vf of ~3V, the third one shows missing part (so failed open). None of the caps bulged or smoked.]
AI: Your schematic shows no input capacitors. What are you using there?
And you have a "breadboard" with what parasitic inductances? Post a photo?
Between inductances and capacitances, you have many opportunities for ringing.
! amp switched in 10 nanoSeconds into 100 nanoHenries (4" of wire) will generate
(wait for it)
V = L * dI/dT
V = 100nanHenry * 1 amp / 10 nanoSeconds = 10 volts |
H: Electric potential diagrams
Despite having a degree in electrical engineering, sometimes I still don't get the fundamentals of electricity. Can someone please explain the electric potential diagrams in the following link: http://www.physicsclassroom.com/class/circuits/Lesson-1/Electric-Potential-Difference
If one were think about electric potential as analogous to gravitational potential, there should be a gradual decline from the high potential (+) to low potential (-). Why isn't that seem to be the case?
If in circuit A, the potential has already reached zero at point C, how can the charged particles continue their journey to the lowest potential (point D)?
I have few more questions but these are the most pressing ones and it would be lovely if someone could find time to address these. Cheers.
AI: In theory, all wires are perfect conductors, and so require zero volts to push a current through them. With superconductors, that's actually true, but with copper wires, it's not quite true.
But even a tiny voltage is enough to push a current through a copper wire.
So for circuit A, there should really be a very slight slope from A to B, and from C to D. But the vast majority of the voltage drop will still be from B to C. |
H: RF Via fences/stitching spacing
I'm working on a 4-layer PCB with a U-Blox module and I'm trying to calculate the space between the fencing vias next to the Antenna trace and for the stitching vias.
According to the datasheet we have the following possible frequencies:
The case which would cause the closest vias is the last one.
According to the calculations suggested here https://electronics.stackexchange.com/a/42028 I should put them ideally with the following spacing:
$$
\frac{\lambda}{20} = \frac{C/2170Mhz}{20} = \frac{138.25mm}{20} = 6.9mm
$$
but if we look at this image from the datasheet it seems way too much compared to what they did; consider that the side of the module (the white outline) shown in the above figure is 16mm, so according to calculation there should be a dot at the beginning and at the end of the track and that's it.
My best guess is they are basing the fence spacing on the Greatest Common Divisor for the mean value of each frequency reported in the table to cover each operational mode.
Stitching wise I report what found in this page:
https://www.edn.com/electronics-blogs/the-practicing-instrumentation-engineer/4406491/Via-spacing-on-high-performance-PCBs
$$
\lambda = \frac{300}{F\times\sqrt{\varepsilon_{R}}} = \frac{300}{2170Mhz\times2.097} = 60mm
$$
now \$\lambda/8\$ is 7.5mm and that should be the necessary spacing for the ground stitching (Er = 4.4 for typical FR-4 PCB material).
To sum up:
1) How much space there should be between each fencing via in my case?
2) How much space there should be between each stitching via in my case?
3) Does the frequency actually relates to the fencing/stitching space, or placing the vias closer than the smallest \$\lambda/20\$ (for fencing) and \$\lambda/8\$ (for stitching) is all that matters?
4) Is all that stitching shown in figure really necessary from an RF point of view?
AI: Spacing your vias by 1/20 wavelength is very unlikely to cause any problems.
Does the frequency actually relates to the fencing/stitching space, or placing the vias closer than the smallest λ/20 (for fencing) and λ/8 (for stitching) is all that matters?
The frequency and the wavelength are intimately related, so the operating frequency has just as much to do with the via spacing as the wavelength does.
Is all that stitching shown in figure really necessary from an RF point of view?
Probably not. But for a low-volume board like a demo board, adding a few extra vias is cheap insurance against having to re-do the layout in the unlikely event there's a problem caused by spacing the vias too widely. |
H: Purpose of ICs in EMCA - Type-C
I can't find the purpose of IC ( which is power sourced by VConn) inside the EMCA.
Source/Sink can communicate with EMCA via this IC. But what is exactly function of this IC in Power Delivery ?
P/S: IC means : Integrated Circuit inside EMCA( Electronics Mark Cable Assembly - a type of cable which complies with Type-C connector). This IC is powered by Vconn signal.
Thank you!
AI: I found the answer for my question:
Do all USB Type C cables support full power delivery
In order for a USB-PD compliant source to advertise capabilities
greater than 3A (or up to the full 5A limit of the spec) the Type-C
cable must be an Electronically Marked Cable Assembly (EMCA) and
support SOP' packets. It must respond to the "Discover Identity" VDM
sequence (USB-PD spec section 6.4.4.3.1) with a cable VDO packet with
bits 6..5 set to indicate 5A current handling capability. |
H: How to assert multiple properties in System Verilog
What is the most efficient way to assert multiple properties in SV ?
Example:
property x;
if(expr1)
a===b;
endproperty
property y;
if(expr2)
c===d;
endproperty
Is something like this is needed: assert (x && y)?
AI: You can use the property and operator
assert (x and y);
For your example, there's not much difference from the logical && operator, but that operator can only be used on Boolean expressions. |
H: How to See the Stackup in Allegro Free Viewer?
We are copying some part of a PCB reference design. The stackup information is needed to calculate the trace signal transmission line parameters.
The reference is in _PCB.brd files. It can be opened with the Cadence Allegro Free Physical Viewer. In the viewer, how can you see the thickness of each layer, and its dielectric number?
In the same software package it also installs a SIM and MCM Free Viewer. Would that be what should be used?
AI: Look under "Setup > Cross-section...". In Allegro Free Physical Viewer 16.6 (and 17.2, IIRC), the cross-section report lists the layers with name, material, thickness, dielectric constant, loss tangent, etc.
If you have access to Allegro Physical Viewer Plus, it shows a much prettier graphical stackup representation, but it is still the same information, just displayed differently. |
H: Automated voltage measurement: Tradeoff between PLC and averages
I am setting up an automated voltage measurement of a precision device. In my case, I am using a Keithley 2000 and controlling it over RS232 from MATLAB.
The voltages I am measuring have to be quite precise (more than 16 bit precision, resolution of tens of \$\mu V\$ on a \$\pm4\ V\$ signal). As such, I need to use some method to get low noise in my measurement. At the same time I need the measurement to be fast enough, since I need to repeat this measurement for every one of the boards \$2^{16}\$ possible outputs.
There are a few ways I can try to lower the measured noise, but I am not sure which is the best. The Keithley 2000, just like most bench multimeters, allows the user to set the measurement time (in number of power-line cycles) and apply filters. I want to work in multiples of a power-line cycle, so all noise from mains hum is canceled out as much as possible. Should I then use as much power-line-cycles as possible and lower number of measurements before averaging, or just 1 power-line cycle and then do a higher number of samples for averageing? For example, 3 measurements at 10 PLC versus 30 measurements at 1 PLC.
AI: I know little about this but I expect that you need to sample at an odd number of mains half-cycles so that the noise cancels out.
Figure 1. The image shows hum superimposed on a steady signal. Each black 'x' is a sampling point and it should be reasonably obvious that sampling at any odd multiple of the half-wave time (every half-wave, every 3, every 5, etc.) will result in samples that alternate above or below or exactly on the signal. Averaging each pair of readings will eliminate the hum.
This approach is commonly used in industrial signal applications such as temperature controllers where a very low voltage signal is being measured and the sensor wires run in close proximity to mains cables.
Keithly themselves have published a book Low Level Measurements - Prcision DC Current, Voltage and Resistance Measurements. I'm looking at the 4th Edition but I haven't studied it. The Sixth Edition is available online. |
H: What does ClockDivision do, as opposed to the Prescaler for STM32 timers?
I am using an STM32 board (F7 series), and am looking through the HAL API documentation. When I initialize a timer, I see two values, Prescaler and ClockDivision. Now I understand that the Prescaler is used to divide the frequency of the clock. However, what is the ClockDivision supposed to do? I see it has three possible values, DIV1, DIV2, and DIV4.
My auto-generated code says the following.
AI: With a big assumption that everything below holds true or at least be similar to F7 series description. I could be completely wrong! Please double check!
According to the stm32 F4 family datasheet register description, the "ClockDivision" stands for
CKD:
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(ETR, TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value
I could not find any specific documentation related to F7 series and I am not quite aware of dead-time generators usage but ETR stands for "External Trigger Input".
Beware TIM1 is a special Timer, the same description do not hold true for other general pupose timers(ex. TIM2 etc.)
Also, HAL API Documentation is particularly not useful as it is just an accumulation of all the HAL Library comments without any description. If you are still interested, this might be helpful for you. |
H: SPI timing on CS5480
Good day folks :)
i just want to know if i'm understanding it right? i read the datasheet and i saw the start-up row in the switching characteristics. Does every time - let's say i execute a command on a microcontroller to do SPI communication to a slave, will it always have a this start-up time delay then continue to sck + sdo??
i have this calculation of SPI data-in to the CS5480 ic in nanosecond unit, 10-bit transmission (1 start bit, 8 data bit, 1 stop bit)
am i doing it right?
would i have to include start-up time to my computation every time i do SPI transaction?
Hope you can help me on my dumb question since i am new to this and doing self study :) thanks
AI: No, the oscillator start-up time is once when you power up the CPU. It can be repeated if you go come out of deep power down mode (I don't know: does the CS5480 have that). It is definitely not per instruction! |
H: Is there anything wrong with this particular timer circuit utilizing 555?
I created following simple timer circuit for one shot operation.
My expectation is it to give 5v as output (for D RELAY and SP RELAY) for certain number of seconds/minutes soon as it got powered-on. Time interval to be selected using the rotary switch (bottom side).
I created this circuit by taking this. Additional things I added are voltage regular part with AMS1117-5.0 and various resister series selectable using rotary switch combined with 1000uF capacitor.
I tested timer part, excluding voltage regular, on breadboard and worked good. Then created PCB with SMD components (except 1000uF and 22uF capacitors and BS170 MOSFET. Those are through hole ones).
I am using a wall adapter having 8.4v for Vcc.
The problem is the timer is not working at all. It even does not give HIGH when I tested it using multimeter put across OUT pin of 555 and GND.
I am not yet good at electronics and took around one day to build the PCB!
Please help me to identify the problem in this circuit.
Many thanks in advance!
AI: Your concept (guessing here, because you have not precisely explained what you expect to happen) appears to be wrong- opening the ground on the x1117 will not give you 0V, it will give you almost the input voltage.
When the MOSFET switches on it will drop to 5V.
But your timer not working is another thing and may involve some issue with construction or some other difference between your breadboard and the PCB (including a fried chip, but that's probably unlikely without a bit of drama such as it getting very hot).
Measure the voltages on each pin- pin 5 should measure about 2/3 Vcc and pins 2,4,8 should measure about Vcc. Make sure the rotary switch is wired correctly. And try triggering the timer by momentarily shorting C1. |
H: Current sink for microcontroller port not constant
I have designed a two-transistor current sink for my application. I need it to keep the current constant which flows through an IR-LED:
simulate this circuit – Schematic created using CircuitLab
The current should be constant at:
I = UBE1 / R1 = ~0.7 V / 120 Ohm = ~5.8 mA
Now the problem is that the current will not stay constant as desired when varying the voltage between 2.6 V and 3.3 V. It varies between 1.6 mA and 4 mA. What do I miss here?
AI: What do I miss here?
You forgot to take into account the forward volt drop of the LED. It might be betweeen 0.8 volts and 3 volts depending on technology.
Thus, if your supply voltage is 2.6 volts, the "current control circuit" might only receive (maybe) 1.5 volts across it and, given that the two transistors might need at least 1.4 to 1.6 volts across their circuit to begin reasonable conduction, you are on the edge of it just starting to conduct.
If your supply voltage did rise higher I'm sure it would begin current limiting around the 5 or 6 mA mark. Here is a slightly improved version of your circuit: -
Note that Rb connects directly to the positive rail - it will help but only a little bit because to get conduction from both transistors you still need 1.4 volts to 1.6 volts from Q2's collector to ground (your IO port).
Pictures from here. |
H: Is the NAND logic gate perfectly symmetrical?
In other words: if we swap A and B, will Q behave exactly the same in DC and transient analysis?
AI: There will be a very small difference in that circuit because of the differences in VGS in the N stack while the circuit is sinking current during switching. M1 will be marginally slower than M2 under some conditions.
There are however likely to be other factors, say in how the circuit is laid out, that will have an equally large effect.
Define perfect. Much of what we do in EE is about modelling. The model is never perfect and at most levels of abstraction the behaviour of this circuit would be considered to be symmetrical. If we let very small differences in a circuit that typically would include tens of these gates effect us we will never get anything done. |
H: Clarification on MIPS sw and lw
If I have the following code in C
A[1] = 2;
Where the starting address A[0] is $s0.
addi $t0, $s0, 1 #t0->A[0]
lw $t1, 0($t0) #t1->A[1]
addi $t1, $t1, 2
This is where I am a bit confused. Is it necessary to add:
sw $t1, 0($t1)
Or is the code fine as is? I think it is fine because, I am adding 2 to the contents of $t1, which is effectively, A[1] = 2.
AI: If &A is stored in $s0, then A[1] = 2 compiles to
ori $t0, $0, 2 # Move 2 into $t0
sw $t0, 4($s0) # Store $t0 into $s0 + 4 (because ints are 4 bytes)
As mentioned in the comments, your code doesn't make a lot of sense because you seem to be doing something resembling x = A[1] +2. You have to use a sw because the C code stores a value to the array. |
H: Time for serial data(UART) transmission
Dear all i have a very simple question on serial data transmission.
signed int NUM;//32 bit
NUM=235;
the serial configuration is:
115200 baud rate
1 start
1 stop
no parity.
How much time will it take to transmit this number(NUM) over the serial port?
furthermore, I send the data in two ways as follows. My IDE is Keil Microvision.
1> use printf("%d /n", NUM);
2> I have written a function
void Send_Info(uint32 count1)
{
int k;
static uint8 NumPos[6]={0};
NumPos[0]= count1 / 10000 + 0x30; //tenthousand1
NumPos[1]= count1 % 10000 / 1000 + 0x30; //thousand1
NumPos[2]= count1 % 1000 / 100 + 0x30; //hundred1
NumPos[3]= count1 % 100 / 10 + 0x30; //decimal1
NumPos[4]= count1 % 10 + 0x30; //unit1
NumPos[5]= 0x0D; //CR
for(k = 0; k < 6; k++)
{
(void)stdout_putchar(NumPos[k]);
}
}
All transmission happens inside an interrupt which occurs in every 0.5 sec.
AI: The number of bits to transmit is 32. In addition, there is 1 start and 1 stop bit per 8 or 9 bits (depending what is selected for #data bits), assuming 8 data bits, there are 4 start bits and 4 stop bits, so in total 32 + 4 + 4 = 40 bits.
115200 baud means 115200 bits/sec, so 40 bits will take 40 / 115200 = appr. 0.000347 s = 347 us.
However, there might be a slight overhead / delay for the processing itself, but this is high likely negligible.
UPDATE
The question seems to have been edited. The above is true for sending 4 bytes (32 bits) of real data (resulting in 40 bits). In the example above 6 bytes are sent, but the formula stays the same. |
H: What determines the frequency of the oscillator?
I want to understand what determines the frequency of this ring oscillator and how to lower the frequency.
AI: Propagation delay and charge current (Ron) * charge load capacitance Ciss * number of stages with odd number of inverters ( for self DC bias negative feedback) determines ramp time to threshold. If equal, twice the ramp time is inverse to resulting frequency. Normally RC=T is asymptotic of 1-1/e for T=64% but for CMOS it is usually 50% threshold so T is an approximation and rise time for 10~90% is Tr=0.35/f(-3db) is another approximation for a single stage.
Lowering Vdd raises Ron value and thus lowers f. Adding more C load to Ciss also lower frequency.
if Pch and Nch are same dimension then Ron is usually higher for Pch. |
H: center tap transformer full wave rectifier current rating
for a 24V output, I have the option to purchase a 0-24V 5A transformer, or a 24-0-24V 5A transformer. Can I draw 24V 7A from the 24-0-24V transformer (full wave rectification with 2 diodes)? Assuming I^2*R heating loss, since each winding is being used half the time, I should be able to increase the current sqrt(2) times, right? Any other possible problems (core saturation, core heating etc) that I should be worried about? Will the 24-0-24 transformer provide a bigger safety margin if I'm only drawing 5A continuously?
edit: sorry for the stupid question. Neil_UK is right. To answer my own question, I may be able to draw 7A, but the voltage will drop, as it is defined by the secondary winding resistance (and the primary side voltage and turns ratio). 48V 5A is not the same as two 24V 5A transformers. I'm probably better off getting a single 24V 7A (or 8 or 10A) transformer. Less headache, more stable voltage and more safety margin at not too much higher cost (considering transformers live for decades).
PS: also, this is for a bench power supply, so SMPS will not do (without DC-DC tracking pre-regulators and stuff). In hindsight, I think I will need 12V and maybe 6V taps.
AI: You can safely draw about 5A from a 48V CT 5A(RMS) transformer (rated at 240VA) with a full-wave (2-diode) rectifier and filter capacitor.
The voltage will be about 33V peak, so about 170W total (including rectifier losses) with a large capacitor.
With a linear regulator you will get 5A out of it, plus about 50W of waste heat. With a buck switching regulator you could get perhaps 6A depending on the efficiency of the regulator.
All in all, though you'd be better off buying a decent brand of commercial off-line switcher that can supply 24VDC regulated at 7A or 10A or 15A for most, not all, applications. A 14.6A (350W) supply is less than $50 US, almost 90% efficient, and weighs relatively little. |
H: How to display high frequency signals on a small display?
I'm working on a project to build an oscilloscope using the Arduino Mega2560. I've built the system using an 128x160 display, and I'm having difficulty showing a range of frequencies on the display.
The system I have developed measures the input signal with a 1ms delay between each measurement, doing this 120 times placing each reading in an array. I found I have to use a 1ms delay else it captures low frequencies too fast and will only show parts of waveform. Using this system, the scope only measures up to about 400Hz before Nyquist sets in and the waveform becomes distorted.
I measure frequency (top left) by checking the array and finding how many times the signal crossed 0. To stop the signal flying around the screen, i find the first value when it crossed 0 and draw the signal from there. Only 74 values from the 120 array are displayed.
Is there an mathematical way from the information given such that if frequency is above 'x' change delay, such that the system could auto range and measure upto 100kHz and display the signal on screen, is this possible?
AI: This is a problem with many aspects to it, but at the very minimum, you should not be tying the number of samples you take to the resolution of your display. Instead, take samples as fast as you can or, if you have an analog anti-aliasing filter (as you should), at or above the Nyquist rate for the filter's bandwidth.
Then, when you paint the samples you have taken on the screen, you can choose how to do so. Some simple to implement ways:
For each column of the screen, find all the samples which fall into that range, and fill from the minimum level to the maximum level of those samples. This will avoid creating additional aliasing, and is a common display technique in audio editors.
Draw all the samples individually as points, no matter how many points end up on the same column. This shows more detail but requires more interpretation from the user.
Besides avoiding unnecessary aliasing, separating sampling and display also allows you to implement single-shot capture followed by zooming/panning the view, which will help with the usability of your low-resolution display.
As to auto-ranging: once you have sampled as best you can, you can then apply your frequency counting or whatever other algorithm to that data to choose a starting zoom. But if you sample slowly then you have already thrown out data, and that's a problem. (You might have a problem with storing enough data to work over a wide frequency range without external RAM, though.)
Depending on your goals, it might be an interesting exercise to implement an oscilloscope on a PC using sound-card input. That way, you can play with signal processing and painting algorithms with fewer resource constraints; and USB sound-cards can be readily found with up to 192 kHz sampling rate (though often AC-coupled). Then you can take what you learned and figure out how to fit it onto the Arduino. |
H: Wiring Optical Encoder according to datasheet
I've had success wiring a mechanical CUI encoder according to their datasheet. Values are spot-on for a hardware debouncing and diagram simple to understand for me.
Nevertheless, I prefer for my application a better tactile feedback for the user, so I researched a bit, and it seems like Grayhill 62AG Series would fit perfectly.
Now, looking at their datasheet, I'm surprised how much the wiring changes from the CUI wiring. I suspect this is due to it being an optical encoder vs mechanical to the CUI (?).
Here is the datasheet extract :
What is the thing next to the two capacitors ?
What is the LED's purpose between +5V and GND ?
I actually have doubt whether this is the internal wiring of the encoder, or the recommended wiring for it...
AI: The encoder works by breaking the path of light from the LED, the diode in the encoder to the photo-transistors (the things beside the caps).
A slotted or printed glass disk turns interrupting the light between them.
When lit the transistors turn on, acting sort of like switches.
There are two sensors positioned to provide quadrature. |
H: Are the offset voltages in a dual/quad op amp correlated?
On a single piece of silicon on which there is more then one op amp, are the input offset voltages at all correlated, i.e. would they be expected to be same direction and similar magnitude?
AI: No, you can't assume anything about correlation between opamps on the same chip unless the datasheet explicitly says so. I don't remember ever seeing a datasheet say anything about offset voltages of opamps on a chip relative to each other.
Think about it: offset voltages are due to the slight mismatches between transistors in a chip. Some transistor parameters are random, but others may correlate with where they are on the wafer. However, the input transistors of an opamp are already near each other, and likely much closer to each other than the input transistors of other opamps on the same chip. This doesn't leave much mechanism for the offset voltages between nearby opamps to be correlated somehow. |
H: Connecting Voltage Regulators 7812 in Parallel for High Current
Could I use two L7812 voltage regulator ICs in parallel to get 12 volt and more current that with just one?
AI: No, that is a bad idea. The two regulators won't have exactly the same output voltage. The one with the higher output voltage will take more current. You can't guarantee that both regulators will put out their maximum current when you try to draw 2x the output current.
Another drawback to your approach is that you have a diode drop between the regulated voltage and the output voltage.
Here is how to get more current from a single regulator:
At low currents, R1 only drops a little voltage, and the regulator works as intended. When the current gets to about 700 mA, the 700 mV that causes across R1 starts to turn on Q1. Q1 then shunts input current around the regulator.
In this case, the current thru the regulator is limited to about ¾ A. As more current is demanded, it goes thru Q1.
One drawback of this approach is that the overall regulator has about 750 mV higher dropout than just the bare regulator without the transistor around it.
However, if you're going to go thru all that trouble, you apparently need a decent amount of regulated current. A linear regulator will dissipate a lot in heat. Having to get rid of the heat is large and expensive.
You really should look at some buck switchers. You haven't said much about your application, but it sounds like a switcher would be more appropriate here.
Let's look at the power dissipation more closely. It seems your AC input is 18 V. I'll assume that means 18 V RMS sine. That means the peaks of the waveform is 25.5 V. That is going thru a full wave bridge, so there are two diode drops. You are apparently expecting a few amps, so lets say 750 mV per diode drop. That makes the peaks the caps get chared to 24.0 V.
You don't show the values of the caps, so we can't compute droop between the peaks. Just to pick something for sake of example, let's say the droop is 4 V. We can approximate the input waveform to the regulator as a sawtooth from 20 to 24 V, which averages to 22 V.
Let's say the output current is 1.5 A. I'll assume you wouldn't be asking to put multiple 7812 in parallel if you only needed 1 A.
So now we have 22 V in, and 12 V at 1.5 A out. Any linear regulator, whether a single chip or something more complicated will dissipate the current times the voltage drop as heat. In this case, that is 10 V times 1.5 A, which comes out to 15 W. That's quite a lot of heat to get rid of. You would probably end up with a heat sink the size of your fist at least.
Now compare that to a buck converter. Nowadays you can get buck switchers that are 90% efficient. Let's work thru the numbers assuming 85%. That is certainly attainable. The output power is (12 V)(1.5 A) = 18 W. The input power is therefore (18 W)/85% = 21.2 W. That means the switcher will dissipate (21.2 W)-(18 W) = 3.2 W. That's much more manageable.
Even better, that 3.2 W won't be dissipated by a single component. The switch will dissipate some, so will the inductor, and so will the diode, or the transistor working as a synchronous rectifier. Actually, if the switcher used synchronous rectification, it would likely be more than 85% efficient. But still, dissipating a watt or two here and there is a lot easier than dissipating 15 W.
Use a switcher. |
H: I-type register format maximum size of a constant
The above picture is an I-type format register. I am confused as to why the largest constant possible is $$2^{15}$$ Should the largest possible constant be $$2^{16} -1$$
AI: In the MIPS architecture, the immediate field of I-type instructions is a signed 16-bit value in two's complement. One of those 16 bits is the sign bit, the other 15 remain for the magnitude.
Therefore, the range is -2^15 (-32768) to 2^15-1 (32767); that's still 2^16 different values in total. |
H: Formulas for AC Synchronous motors
I have this questions:
At what frequency must a 4-pole motor be supplied so that its synchronous speed is
1200 rev/min?
The nameplate of a standard 50 Hz induction motor quotes full load speed as 2950
rev/min. Find the pole number and the rated slip.
A 4-pole, 60 Hz induction motor runs with a slip of 4%. Find:
(a) the speed;
(b) the rotor frequency;
A 440 V, 60 Hz induction motor is to be used on a 50 Hz supply. What voltage should be
used?
Why can an induction motor never run at its synchronous speed?
Choose suitable pole numbers of cage induction motors for the following applications:
a. a grindstone to run at about 3500 rev/min when the supply is 60 Hz;
b. a pump drive to run at approximately 700 rev/min from a 50 Hz supply;
I now the number of poles and slip formulas. Is there any other formula that could help me for this task?
AI: S = f x 120 / N
Where:
S = Synchronous speed in RPM
f = frequency in Hz
N = number of motor poles
120 = a mathematical constant
% Slip = (S - Full load RPM / S) x 100
Use those two formulae to solve all of the above.
By the way, your thread title says "synchronous motors", which would not be inclusive of "slip". |
H: Is it possible to use `.*` in SystemVerilog to register interfaces' elements?
Let's say I have one interface, I'd like to
interface myIf;
logic a;
logic b;
logic c;
logic d;
logic e;
logic f;
endinterface
interface mypartIf;
logic b;
logic c;
logic d;
endinterface
module top (
input clk,
myIf interf
)
mypartIf part();
always_ff @(posedge clk) begin
part.* <= interf.*; // should match b,c,d names in both interfaces
end
endmodule
Of course this example doesn't work.
I could replace mypartIf with a struct and register the struct but in that case I'll have a different namespace.
typedef struct packed {
logic b;
logic c;
logic d;
} mypartIf;
interface myIf;
logic a;
mypartIf othernamespace; // HERE
logic e;
logic f;
endinterface
module top (
input clk,
myIf interf
)
mypartIf part;
always_ff @(posedge clk) begin
part <= interf.othernamespace; // This should work
end
endmodule
I would like to make it as simple as possible, name matching would be a good solution without adding struct. Moreover adding struct doesn't allow me to use crossing fields.
What is the best practices to use crossing elements like this ?
AI: No, you can’t do this. An interface only helps you collect a group of signals and make connections to other ports as a group. You still need to access all the signals individually inside the module as if they were separate ports.
If you want to access the values as a group use the struct. Just make sure you put the typedef for the struct in a common package. Then you will not have a namespace issue. |
H: Why use more than one contact in VLSI layout?
I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer using contacts. What is the use of the vertical metals which again connect the same diffusion with these metals? I mean why two contacts are used?
AI: Dual via placement (or "wire pairing", or "double-cut vias") is a layout technique used in ASIC designs to improve reliability of chips and make them up to automotive or military requirements. |
H: Step Response of Ideal Inductor with Current Source
I'm taking an electronics course to get a physics minor (I'm an applied math major) and today, the professor shows a diagram of an ideal current source connected to an ideal inductor. Crazy stuff I know.
The problem I'm having is that the book and his lecture notes do not treat the independent current source as an actual independent current source. That is, the current is a function with respect to time t, rather than some numerical value like 1A. Hence it is a dependent current source. (Obviously this was done to make the problem easy and/or solvable.)
Despite the lack of care given for using the appropriate symbols, it made me wonder what the actual response would be for an ideal independent current source connected to an ideal inductor. I am a math major after all.
It's been a semester or two since I took ODEs and PDEs, so my differential equations are a bit fuzzy. But I have a feeling that a Heaviside step function and Laplace transforms are not going to work here.
I would argue that the voltage across the inductor would be indeterminate at the edge of the current step and zero after that. Essentially a discontinuous function that approaches infinity at t=0 and then 0 for t>0.
Obviously this isn't physically realizable, but I was curious how one would go about solving this even if the solution diverges.
So my question. How would you attempt to solve this problem? Heaviside step function and Laplace transform or some other method? Also, what change is needed to make this problem solvable? For instance, would a parallel resistor of some finite value do the trick (so you could convert to a Thevenin equivalent circuit)?
AI: That is, the current is a function with respect to time t, rather than some numerical value like 1A. Hence it is a dependent current source.
You're misunderstanding how independent and dependent sources are usually defined.
A dependent current or voltage source is one who's value depends on some other circuit variable, such as a branch current or the difference between two node voltages.
An independent current or voltage source is one that doesn't depend on other circuit variables.
An independent current or voltage source that does vary over time is an entirely common device and used all the time in useful circuit models.
it made me wonder what the actual response would be for an ideal independent current source connected to an ideal inductor. ... I would argue that the voltage across the inductor would be indeterminate at the edge of the current step and zero after that.
Yes, this is correct.
Of course, real current sources never have perfectly discontinuous output functions (there is always a non-zero rise or fall time), and real inductors have interwinding capacitance, so this is never an issue in practice (although knowing the source rise-time and inductor parasitics might be an issue).
You could also approach this problem with a limit function: consider some well-behaved function for the current variation over time, and take the limit as the rise-time goes to zero.
How would you attempt to solve this problem? Heaviside step function and Laplace transform or some other method?
I've never had to use a Laplace transform to solve a circuit in the real world, though someone like you with a more math-oriented background might choose to do it that way.
I'd solve it by just knowing that the voltage must be a delta function to produce an instantaneous change in the current through an ideal inductor.
Also, what change is needed to make this problem solvable? For instance, would a parallel resistor of some finite value do the trick
As mentioned above, typically a real inductor has an interwinding capacitance. This is a capacitive parasitic that appears in parallel with the inductor. This is the first parasitic I'd add to make this model more realistic and avoid singularities in the circuit solution. |
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