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H: Something is wrong with my understanding of this D-Flip flop design
I am a little rusty with flip-flops.
Consider this diagram:
This is a 4 channel stereo digital switcher. I am trying to understand the flip flop and the OR parts.
Because this is a 4 channel switcher, my feeling says that the flip-flops and the OR gates will be providing 4 different outputs and I am trying to understand how it works.
Lets talk about FF1 and FF2.
When the circuit is first powered, C15 is an "short circuit" and will let 5 volts reach R17, making FF1 clock be 1 for a brief period of time and then charge and "cut" the current to R17, making it 0 volts. So, we see clock going from 1 to 0, during startup.
Because this D-Flip-flop CD4013 will not do anything on 1 to 0 clock transition, I think FF1 will be with the following states after startup: (Q = 1), (Q' = 0), (D = 1).
Because of the wiring between FF1 and FF2, after startup FF2 clock will be 1, (Q = 0), (Q' = 1) and (D = 1).
At this point the OR ports will be with these states (from top down):
N1 (0, 0).... output 0
N2 (1, 0).... output 1
N3 (0, 1).... output 1
N4 (1, 1).... output 1
Then I press S1. We have a transition from 0 to 1 on FF1 clock.
FF1 changes to the following states: (Q = 1), (Q' = 0 = D)
Nothing happens on FF2.
The OR ports are now
N1 (1, 0).... output 1
N2 (0, 0).... output 0
N3 (1, 1).... output 1
N4 (1, 0).... output 1
I press S1 again. We have a transition from 0 to 1 on FF1 clock.
FF1 changes to the following states: (Q = 0), (Q' = 1 = D)
Now the clock of FF2 changes from 0 to 1
So, FF2 changes to: (Q = 1), (Q' = 0 = D)
The OR ports are now
N1 (0, 1).... output 1
N2 (1, 1).... output 1
N3 (0, 0).... output 0
N4 (0, 1).... output 1
I press S1 again. We have a transition from 0 to 1 on FF1 clock.
FF1 changes to the following states: (Q = 1), (Q' = 0 = D)
Nothing happens on FF2.
The OR ports are now
N1 (1, 1).... output 1
N2 (0, 1).... output 1
N3 (1, 0).... output 1
N4 (0, 0).... output 0
So, in sequence, the OR ports will produce, from top down:
0111
1011
1101
1110
But here is the problem, 4066 is a switch. Looking at my numbers I see a zero changing position. But in that case, I would expect the inverse of that, I mean
1000
0100
0010
0001
or a 1 changing position, so this 1 could select one of the four channels of IC3 and IC4 as stated by the 4066 data sheet.
Where is my error?
AI: The diagram is incorrect. The CD4001 is a NOR gate, so both inputs have to be logic '0' for the output to be a logic '1', so your original 'expected' chart is correct. The symbol used in the schematic is wrong. It should have a dot on the output to indicate inversion.
The CD4001 NOR gate is used to make sure only one channel at a time is selected. At power reset, Channel 1 is selected.
This chart is correct, and it is what is taking place in the circuit.
1000 Channel 1
0100 Channel 2
0010 Channel 3
0001 Channel 4 |
H: Kirchhoff's Current & Voltage Laws
What are Kirchnoff's current and voltage laws? I've tried doing some research but most explanations are quite complex.
Also how can I solve the attached question using these laws??
AI: Hopefully this puts the two laws in somewhat simpler forms for you;
Kirchoff's Current Law states (as you have probably seen) that the sum of currents entering a node is equal to the sum of currents leaving it. Think of a junction of water pipes where three pipes meet at a T-shaped junction. The flow of water into the junction must be equal to the flow of water out, otherwise water would be appearing out of nowhere. Similarly, in an electric circuit the flow of charge into the junction must be equal to the flow of water out, otherwise charge would be appearing out of nowhere.
Kirchoff's Voltage Law is probably the trickier one to understand. Basically it says that if you start at a node in a circuit and you follow some closed loop around the circuit back to the same node you have to be at the same voltage you started at. A mathematician would say this is because the electrostatic field is conservative. In more understandable terms, it is because voltage is a potential difference i.e. the difference in potential energy a charge would have if you moved it from one point to the other. A good analogy here is gravity, a mass has gravitational potential energy proportional to its height above some reference, say sea level. To change the potential energy you move the mass up or down, it doesn't matter what path you take between your two end points. I might move a mass 100m up then l00m to my left and then 100 m back down to the height I started at, the mass has the same gravitational potential energy I started with because it is at the same height even though it is in a different position. Relating back to electric circuits, if I move around a loop in a circuit, I end up back at the same 'height' with the same voltage. |
H: What should the single-ended impedance be for LVDS?
For LVDS, it seems like the traces are usually specified as 100 ohm differential impedance. What should the single end impedance be from each trace to ground?
I'm looking at PCB impedance calculators, for example the nice list here: https://www.fedevel.com/welldoneblog/2011/08/pcb-impedance-calculator-single-ended-differential-pair/
Using http://www.skottanselektronik.com/impcalc_en.html, I can put in er=3.66 and w=0.30 t=0.035 h=0.17 s=0.7 (all in mm) and I get Z0=50.52 ohm, Zdiff=100.1 ohm. Is this correct for LVDS?
(This is supposed to match the OSHPark 4-layer stackup)
It seems that by adjusting w (width) and s (spacing), different combination of Z0 and Zdiff can be obtained; Zdiff seems to be < 2*Z0, and approaches 2*Z0 as s gets large. At closer spacing Zdiff can be much less than 2*Z0, for example w=0.17 s=0.10 produces Z0=69 ohm and Zdiff=100 ohm. Is this also okay for LVDS? Is it better than 50/100?
This is my first time dealing with LVDS, sorry if this is too basic a question but I couldn't easily find an answer anywhere. The part I'm using supports LVDS1.8 per IEEE 1596.3-1996, if that helps.
AI: LVDS uses 100 ohm differential impedance, which if implemented with two isolated lines would require two lines of 50 ohm impedance.
Do not get confused with coupled lines that appear to have a different Zdiff to Z0 ratio.
At closer spacing Zdiff can be much less than 2*Z0, for example w=0.17 s=0.10 produces Z0=69 ohm and Zdiff=100 ohm. Is this also okay for LVDS? Is it better than 50/100?
Think about what the Z0 of a 'single line' might mean. What are you doing with the other line of the diff pair? Has it been moved away to infinity? If so, you've changed the geometry between measurement and use, so it's meaningless. Are you grounding it? If so, you're driving the diff pair differently between measurement and use, so it's meaningless. Are you driving it with the inverted signal? Now you're measuring it and using it the same way. This inverted drive to the other line creates a zero voltage plane (aka an electric wall, or a virtual ground) between the lines, and pulls the impedance of the line you're measuring down below what it would be if you ignored or grounded the other line.
Unfortunately the skottanselektronik.com line calculator you used presents you with this meaningless Z0 figure to confuse you. Substituting those figures back into its single line microstrip calculator gives exactly the same Z0 figure. This demonstrates that it's giving you the impedance when the other line is moved away to infinity, which is a different geometry to what you're using, so meaningless.
When you use a line calculator with a proper 'diff pair' mode, it will take account of the geometry and the correct driving conditions, and provide you with a pair of lines that has 100 ohms differential impedance, and two lines of 50 ohms impedance when the other line is driven with an inverted signal. If you do something else with the other line, then sure, its single ended impedance will calculate higher than 50 ohms.
A rule of thumb for FR4. An isolated single line above ground will have 50 ohms impedance if it's twice as wide as the substrate thickness. Two coupled lines driven differentially will be narrower than that, due to the extra loading from the virtual ground between the two traces.
Bonus points, you do not need to read this if you are a digital engineer, but it may be interesting for the RF guys. There are two relevant impedances with two coupled lines, Zodd and Zeven. Zodd is just half the Zdiff we've been discussing so far, the impedance of one line when the lines are driven differentially. Zeven is the impedance when the other is driven in phase. What does this do to the space between the lines? It increases the impedance, by shielding some of the ground that the line would see otherwise, it introduces a 'magnetic wall' in the jargon. Now while you'd never drive a pair of lines like this with logic signals, which is why the digital guy need not have read this far, if an RF guy sends a signal into one line of the pair, that unbalanced signal can be thought of as the sum of an even mode and an odd mode, which then propagate into different impedances, and we introduce the new (big) subject of RF couplers! The skottanselektronik calculator does not give a Zeven figure. |
H: (PSPICE) Memristor-Based IF Neuron Circuit: What is this NMOS?
This is a memristor-based IF neuron circuit.
My question is, i'm trying to simulate this circuit in PSPICE. However, I am unsure what the N-MOSFET characteristics (M1) are in the circuit diagram. I do not see any parameters in the paper. Do I just choose an arbitrary N-Mosfet from the mosfet library in PSPICE? What about it's Pspice model characteristics (vdd, bias current, etc)?
I don't see any characteristics about the MOSFET in the paper...unless i'm just missing it.
Paper Link: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6331427&tag=1
AI: It seems that \$A_2\$ works as comparator (with hysteresis, because of \$R_2\$) so its output is digital. Also the following inverter operates digitally.
So you can assume that the MOSFET is used simply as analog switch and the only thing you have to care about is that it is turned on properly when \$V_K\$ is high, i.e. that \$V_{th}\$ of the MOSFET (not the \$V_{th}\$ shown in the circuit diagram) is small enough; or just use the more abstract voltage controlled Switch element of PSPICE instead of a MOSFET: |
H: The problem with "dirty" power supplies
I have a buck converter with an operating frequency of 180khz.
I want to power a microcontroller (raspberry pi) with it at 5v.
I understand the 180khz noise is not desirable for use with a microcontroller.
Would a capacitor across the output of the converter help remove the 180khz noise? How do I find the right one if so?
Many thanks in advance.
AI: Ideally, your power supply will have zero noise; but in the real world there will be noise.
Practically speaking, for a one off project you should just try it out and see if it causes problems.
For systems that need to be very reliable, it may make sense to do analysis of what the pi is specified to handle, vs what is measured from the power supply. However, even in this case the systems are too complicated to exhaustively simulate what might happen, so there's still going to be empirical testing and "best practices" involved.
If you find that there are issues, you have various options to remedy them. The simplest and most practical is to switch to a different type or model of power supply. Building a filter may also work, but it can be difficult because digital devices require quick bursts of power that the filter may interfere with. If you go this route, you'll probably want an LC low pass filter.
I've powered raspberry pi's many times using switching power supplies without additional filtering, so it's definitely possible.
TLDR; I would recommend trying it. If you have issues I would try a different power supply. |
H: What does it mean bipolar or unipolar junction in a transistor?
I can't find the definition of unipolar and bipolar junction in a transistor, for example BJTs has a bipolar junction and MOS-FET has a unipolar junction, what does it mean unipolar and bipolar junction?
AI: It doesn't have anything to do with the junction. The terminology stems from the charge carriers involving current flow in the device. BJT is called bipolar because the current in a BJT flows due to both electron and hole carriers, whereas the current in a Field Effect Transistor (FET) flows due to either electron carriers for N-type FET or hole carriers for P-type FET, hence they're called unipolar transistors. |
H: Dependency of conductivity on temperature of extrinsic semiconductor
For an extrinsic semiconductor, how can we explain the following dependency of conductivity on temperature as shown here:
My thoughts:
At 0 K there is no energy available, hence no electrons can flow from the valence band to the conduction band, so σ = 0 at T = 0 K.
Now as T increases, energy increases, and hence σ increases.
Now how does σ decrease as T is further increased from 300 K?
AI: As you keep on increasing the temperature, the concentration of minority carriers goes on increasing due to thermal generation. At a particular temperature, the concentrations of both the carriers are the same, i.e., the material becomes intrinsic again. Beyond 300K, as the semiconductor is going from being extrinsic to becoming intrinsic, the conductivity decreases (conductivity of extrinsic > conductivity of intrinsic).
Beyond Tc, the semiconductor completely behaves as an intrinsic one and it's conductivity increases with temperature. |
H: With a AC to DC converter can I put in DC to get AC?
With a old laptop power supply can I put in DC to get AC?
AI: No... it only works in the AC to DC direction. |
H: Smoothing capacitor burns out while I am trying full wave rectifier
I am new to Electronics. I am trying the Full wave rectifier.
I use a transformer and 4 1n5408 diodes (Vdrop is 1.2V) and try to get 24VDC output from 220VAC 50Hz. I measure the AC output (of the transformer) and it is 24VAC. I measure the output after these 4 diodes, it is about 23VDC.
Everything goes fine until I put the smoothing capacitor, no load yet. It is a 3300uF 25V electrolytic capacitor. When I turn on the power, the capacitor gets hot really fast, changes its shape and is going to explode.
I check the polarity, it is correct. So my question is:
Is it because my capacitor has a "too close" maximum voltage? If it is how should I choose a capacitor voltage for this circuit?
Another question though, I have seen this formula around while searching for my problem: C = I(load)/2.f.V(ripple). So if I need Vr = 2V and I(load) = 2A I need to use a 2/(2.50.2) = 0.01F = 10000uF Capacitor right?
Thank you all, really sorry for my English.
AI: The voltage you are measuring without the capacitor is the average DC level. However the capacitor must withstand the maximum AC level, which is 1.414× the average.
As such your capacitor needs to be rated at least double your DC voltage, i.e. 50V. However, to account for tolerances and aging 75 or 100V would be even better.
The cap also needs to be in the right way around.
The capacitor is charged to the peak level every half cycle of the AC and the ripple is caused by the capacitor discharging through the load. Notice, in the image above, the average DC level is now higher than without the capacitor.
Note: With no load to drain the capacitor it will charge up to the peak level and stay there with virtually zero ripple. As such you can expect to measure close to 32.5V across the capacitor with your multimeter with no load. |
H: 16bit DAC with 24bit SPI?
My design requires a 16-bit DAC with 100kS/s plus and SPI communication.
Strangely to me, the cheapest 16-bit DACs that meet the requirement (parametric search) have a 24-bit SPI word, like the AD5662 (pdf) I'm trying to use. The least significant 16-bits are the output value to update and the upper 8-bits are configuration (only 2 of the 8 are actually used). This mode of operation is inconvenient for my 16-bit micro-controller, as the associated ADC in the design has a 16-bit SPI word, ADC161S626 (pdf). This means my micro-controller needs to write x3 8-bit packets instead of x1 16-bit.
Why do manufactures do this? What would be the best way of perform the communication?
If both DAC and ADC were 16-bit SPI word I could read and write at the same time without having to reconfigure the SPI module and data in the micro-controller.
AI: You are making too much of a minor inconvenience.
First, you probably can do two 16 bit transfers. The device will respond with zeros or garbage in the extra 8 bits, and you ignore them in your firmware.
However, the logical thing to do is three 8-bit transfers. Surely your micro can be set up to transfer 8-bit chunks.
At 100 kS/s, you have 10 µs per sample. That's a "long" time for SPI that can probably be clocked at 10 MHz (I didn't check the datasheet, but such speed is usually supported by such devices). Each bit therefore takes 100 ns. Transferring 24 bits therefore takes 2.4 µs just for the bits, plus a little overhead to select and de-select the chip.
Overall, you should be able to transfer the necessary data in about ¼ the available time, certainly within ⅓ the available time.
There is no problem here. You just have to architect the firmware up front, taking the specific characteristics of this D/A into account.
As for why the manufacturers do this? Two whole bytes are used for the data. You said yourself that some status and configuration is also transmitted, so that obviously takes at least a part of one more byte. Most SPI masters have hardware that transfers whole bytes, so they document the extra bits as being in a whole byte. They correctly realize this is really no big deal to firmware writers. |
H: One PSU powering one high power device & one low power device
If one was to power a (potentially) multi-amp device and an arduino with an external LM7812 12v voltage regulator to a 19v laptop charger (in parallel), would the arduino be safe when the multi-amp device started pulling lots of current?
AI: Your question is similar to this example:
The water tower in my town can supply 76 households simultaneously. If 40 households has their shower running, will I, number 41, also get water when I take my shower? Or is the water tower unable to give me water?
Extra information:
\$19.5V×3.9A=76W\$
\$5V×2A=10W\$
\$4\$ buck converters => \$40 W\$
Yes, they will take their showers, you are not going to take their water, nor will they take your water.
You could even attach 3 buck converters more and have 6 W to spare for the Arduino nano. The Arduino nano will not consume 6 W, it will take what it needs. The remaining W that is not taken stays at the water tower, it stays in the electrical grid. |
H: Sony vaio keyboard dongle - Power issues connecting to another computer
I have stripped down a very early (2002) vaio all-in-one desktop which has a keyboard with a built in protective cover which I would really like to use on another computer. The dongle was placed under a cover on the outside of the casing and has the rating 5v 100ma on the back. The cable was designed to go straight to a connector on the mainboard and appeared to be USB, I adapted a usb cable to connect but when I plug it in the dongle has too high amperage and windows complains. Is there anything I can do to enable this to connect? The device is seen by windows but cannot power it.
CN2 is for a connect button, CN1 is USB from bottom, Ground data(+) data(-) +5v
AI: Assuming that your device is actually recognized by Windows as a HID-Keyboard and is overcurrent for the port.
The default HID drivers and the OEM extensions define the parameters (including current allowed). See here for a good starting description.
One way you might get around your problem is to use a 1 port Hub/extension cable or a non-powered Hub between your device and the computer. The Hub is by default 100 mA (or 500 mA in some cases) so the computer port is configured for that amount of current (check the error you get in Device Manager).
There are many cheap non-powered Hubs available, for example an active extension cable like this or a non-powered Hub like this.
The USB system is configured from the Root out, so with a Hub in the cable the computer port is configured to allow the current defined by its descriptors. |
H: Calculate inductance for 3-phase double ckt line
I have attached the problem with the solution given in my workbook. I attempted the problem and ended up getting a different answer.
Is my solution wrong ?
Please help me to understand the problem.
AI: It's mainly due to rounding errors in the written example. For instance, it calculates a value as being 0.243 but if you do the math yourself it is 0.2437. When they calculate 0.221, it would be more accurate to use 0.2214. When they calculate 0.235 based on those previous values it is closer to 0.236. When you follow it all through you get a value of 0.61345 i.e. very close to what you got.
Beware of rounding errors. |
H: Electrical safety: Cracks on wiring
Today I installed a couple of light bulbs with my friend. The two wires coming from the ceiling we connected to the lamps using connection strips.
On close examination we noticed that one of the wires had a small crack in it - it was maybe one quarter or a third through the diameter of the wire, I cannot say for sure. My friend, who has a lot more experience in electrical installation than I do, said that such a wire is a fire hazard because the crack means the wire has a smaller diameter in that spot than intended and therefore higher resistance and it therefore dissipates power and could get hotter than expected when powered on.
This sounded strange to me but I didn't argue him at the spot because I wasn't sure myself. Now that I think about it I can't say I agree with him: Even if there is a crack across the diameter of the wire, wouldn't this simply mean that there is extra resistance along the length of the wire as a whole (seen from the "root" of the wires in the electrical system) and just mean there is less current flowing in the lamp?
So which one of us is right? Does such a crack introduce a fire hazard or not, and why?
AI: Your friend is correct.
(If it is actually a crack, as opposed to a lengthwise scrape or something then you should definitely not use the wire, as it will be more likely to break at that point in case of flexing, but that's beside the point.)
Let's model the crack — the temporary reduction in diameter — as a piece of wire of narrower diameter. Suppose the simple model of a short wire of cross-sectional area \$A\$ in the middle of two sections of cross-sectional area \$2A\$, all of the same length. (We can assume there are more equivalent sections off the ends modeling the rest of the wire.)
A wire of twice the cross-sectional area has half the resistance, same as two resistors in parallel, and the power dissipated in a resistor is \$P = I^2R\$. Since this is all actually the same wire (or, a series circuit of resistances), we know that the current through them is the same.
Therefore, the half-area section is itself producing twice the amount of heat. Not only that, but the heat is somewhat concentrated into a smaller volume (the narrower wire). (In a really short length this would not be as much of an issue because all the full-size wire near it will conduct heat away well.) Thus, it reaches a higher temperature, which could result in melting the wire or its insulation.
It is true that the additional resistance will reduce the voltage seen by the lamp, but the increased heat in the wire becomes a problem well before the lowered voltage affects the current in the circuit significantly, because the resistance of the wire is much smaller than that of the bulb. (Especially with modern light bulbs that contain internal power supply circuits — they won't necessarily react to reduced voltage by consistently drawing less current.) |
H: What kind of capacitors are these small, cube-shaped surface-mount components?
Complete newbie question...
I'm troubleshooting a PCB that includes 4x very small cube-shaped components, labeled C2, C3, C5, and C6 so I presume they're capacitors. They're soldered in parallel and there's no visible markings on them, but appear to be ceramic and are approximately 1mm on all dimensions.
AI: As winny said, they're multi-layer ceramic capacitors. They're almost never marked, so the only way to figure out what they are is to measure them with an LCR meter. You'll have to take them out of the circuit to get an accurate reading unfortunately.
For debugging, a quick check you may want to perform is to see if there's a short across these caps. Of course that could mean a short anywhere in the power net, but MLCC's like this often fail shorted. This is especially common when they're subject to mechanical or thermal stress. The soldering job makes that seem like a likely possibility. |
H: How to wire a high-current relay?
Background:
I am designing a small Arduino-driven circuit to control a ~3/4 hp AC hoist motor. The hoist motor includes a starter-capacitor. The Arduino drives a transistor which in turn drives a power relay that switches the motor on and off. I am not an electrical engineer, so I'm using a Factor of Safety of 2 or higher throughout the circuit to avoid component damage/burnout.
The particular relay I had in mind is supposed to be capable of handling up to 30A sustained (more than 4 times the max-load current of my motor) at double the nominal operating voltage. My intent is to run two of them in series for safety (to handle one failed-closed relay) and for wear-leveling of the contacts.
Consulting an ampacity chart, it looks to me like I need 10AWG copper wire (about 5.3mm^2 conductor area) to handle 30A. But as you can see from the relay datasheet, the load pins are ridiculously tiny: each is roughly equivalent to 17AWG (1.6mm^2). Unfortunately Digikey does not carry a socket with solder cups or terminal lugs for this particular relay, and I'm having a very hard time soldering 10AWG wire to a 17AWG pin.
Questions:
How can the relay pins carry so much current with such a tiny conductor?
Is 10AWG really the right size of wire to carry 7A AC with an inductive load?
How should I go about wiring this relay to the rest of my circuit?
AI: Since motors have a surge current starting up that is up to 5x the max load rated crrent, if you say the hoist motor is rated for 15A then expect up 75A starting surge which reduces while increasing in speed to match the load torque=current demand.
In this hoist motor case, I would be looking towards OMRON or PANASONIC Relays rated for 75 to 90A if you want to do more than 1k cycles, which I estimate from TE's datasheet.
https://www3.panasonic.biz/ac/e_download/control/relay/power/catalog/mech_eng_hepv.pdf?via=ok
read all the fine print.
The thermal terminals imply heavy wire needed to remove heat from relay contacts and extend life. AWG 10 will give you more torque and than 16 AWG but it depends on length and voltage drop for surge currents. So you must look up this value for Ohms/m * 75A. A 10% drop may be acceptible for you, 5% or 20% drop for others, but the lower the torque and start voltage, the longer it takes to reduce the current. |
H: 5v clock feeding 3.3v microcontroller - resistor+zener acceptable?
So I've used a resistor and diode to level-shift from 5v to 3.3v, but that's been for general logic - the fastest thing I've done with that is 9600 bps serial.
I now have a need to feed a 3.3v powered microcontroller (an ATXMega32E5) from a 10 MHz clock signal, which I only presently have available as a 5v square wave (an output from an NB3N551 powered at 5v).
I propose to use a 10 kΩ series resistor followed by a 3.3v zener diode. Circuitlab simulation seems to show this would work, but I am not sure I trust it to be a complete enough simulation.
simulate this circuit – Schematic created using CircuitLab
Is that simple zener clipper likely to work acceptably, or is something more sophisticated called for?
AI: If capacitance (track + diode+ load) is 30pF at 0V with 10k the rise time ~ 300ns in a 50 ns half cycle. Even a Rohm low capacitance zener=3pF + 3pF optimal load is 60 ns rise time. No good. Use an active level converter. |
H: 2 Center Tapped Transformers together
I bought 2 center tapped transformers because I need to make 30V 2A center tapped transformer equivalent and I couldn't find anything with a 120V input.
So I got a 18V 2A center tapped transformer and a 12V 2A center tapped transformer.
18V, 2A Center Tapped (9-0-9) Transformer
12V, 2A Center Tapped (6-0-6) Transformer
How can I connect the secondary together so I get a 30V 2A center tapped transformer equivalent?
AI: Basically you can't. If you connect the secondaries of your transformers in series, you will get 30V across them but the common connection will not be a center tap since one side will be at 18V and the other at 12V. If you got 2 of the 18V transformers, you would get a center tapped 36V transformer by connecting the secondaries in series. Two of the 12v transformers connected in series will give you a 24V center tapped transformer. You really need 2 15V transformers and they don't have to be center tapped. When you connect them in series, the common point becomes the center tap of the 30V transformer. |
H: Converting ST link v2 to Jlink
Has anyone had any succes with converting a ST link v2 to a Jlink using the software that Segger provides? I have not had any success, even with using instructions they provided and was wondering if any one had any succuess/ guidance.
AI: The conversion tool you're referring to is only intended for use with the on-board ST-Link debuggers included on ST's Discovery and Nucleo development boards. It does not work on standalone ST-Link debuggers. |
H: Deriving two independently stoppable clocks from one clock
I am trying to do some complex, pipelined computations in FPGA that involves storing partial results in block ram and retrieving them later. The problem is, the number of partial results that needs to be stored is very hard to reason about and depends heavily on implementation details. What I want to achieve instead is to divide the circuit into a producer and a consumer, and halt the producer when the system runs out of block ram by stopping its clock, as shown in the ascii drawing below.
input clock |-------| -----------------------------------------------
-------------| ????? | individually controllable clocks in same domain
|-------| -----------------------------------------------
Is this achievable?
Thanks
AI: In an FPGA design, you don't typically want to actually stop a clock signal.
If you do so, it's called a "gated clock", and having one in your design will make it harder for your synthesis tool to optimize the design and to achieve timing closure.
Instead, you simply de-assert the EN (enable) input on all the flip-flops that you don't want to respond to the clock at some particular time.
In this case, it could mean de-asserting the EN inputs on all the flip-flops in the upstream blocks when the downstream blocks are not ready for new data.
I don't know enough VHDL to write it off the top of my head, but in Verilog, you can infer a flip-flop with an EN signal with something like
always @(posedge clk or posedge reset) begin
if reset
out <= 0;
else if enable begin
out <= ...
end
end |
H: SPI clock - slow frequency but fast rise time issue with waveforms
Background on the issue:
I currently have an SPI bus between an Atmel ATSAM3X8E and a Spansion FL164K flash memory chip.
SPI has always been super reliable for me in past projects, but this design is being very temperamental (the routing is far from ideal). Some boards work fine, some have very occasional data loss in the SPI comms, some have nearly constant data loss. The data loss that I refer to is most easily reproduced by constantly polling the ready flag during a ~50 second erase. Mostly the busy response is 0x03 (0b00000011), but occasionally comes back as not busy - 0x00 (0b00000000).
Fortunately I can reproduce the fault on the bench, and fortunately I can also make the problem go away. Unfortunately though, connecting a passive probe is one of the things that makes the issue go away, so I can't 'see' the fault. And I'm not happy to call it fixed if I am not certain what I am actually fixing.
Circuit design info:
The SPI bus is routed to 3 things - SPI flash, SD card (which is not installed), and a basic 6 pin header
The red pad in the bottom right is the MCU (clk source), the stub that comes off immediately goes to an n-channel FET which drives an LED, the SOIC8 IC with the red pad is the SPI flash, the 6 pin header above it is unpopulated, and the blue pad at the left side at of the trace is an unpopulated SD card connector.
The actual distance from the MCU to the SPI flash is ~35mm, and the SPI flash to the SD card pad is ~30mm. The stub to the FET is ~25mm and the stub to the header is ~8mm.
The layout is far from ideal, and I understand that, but the intention was to only run it at <1MHz, so I incorrectly assumed that transmission line theory/terminations/reflections were not needed.
Ways that I can already prevent the problem:
Add a ceramic capacitor from CLK to ground in the 6 pin header (I have tried values from 18p to 330p). All of them slow the rise time, and the problem doesn't persist
Add a 1k resistor from CLK to ground.
Attach a scope probe
Touch the CLK line with my finger
So basically any way of adding capacitance or loading to the circuit seems to make the reads 100% reliable.
Waveforms (taken with a Rigol DS1054Z with the 100MHz option, and a 150MHz passive probe using a ground spring):
Note: a scope probe is obviously connected for all these (which stops the problem happening). The waveforms we see here are not actually bad enough to cause the problem, but hopefully give an idea of what could be bad enough to cause the issue when the capacitance of the probe is removed.
Note 2: These shots were taken at a 5MHz clock rate, but the problem seems to manifest at anywhere from 100kHz to 20MHz.
On initial inspection the clock signal looks good (albeit very fast ~8ns rise time).
But a closeup shows a bit of a step halfway up
And at the fastest time scale, this is what I see.
Finally, the questions
Is a step in the rising waveform typical of transmission line reflections or something else?
Given that the read issue occurs regardless of clock frequency, I assume that the rise time (8ns with probe attached) must be combining with the poor routing to cause the data issues. But don't fast rise times cause ringing, not a stepped waveform? Is it common for a scope probe to dampen ringing that otherwise occurs?
Looking at the waveform, what actually happens inside the slave to cause an issue? (the SPI slave double clocks because of that step? or the SPI flash isn't getting it's specified 0.1v/ns slew rate? or something else that I don't understand yet?)
Finally, what else could I do to try to assess the signal without loading (fixing) the signal, short of spending $$$ on an active probe that may or may not make a difference?
As you can tell, higher frequency theory is not my area of expertise, so I appreciate anyone's experiences in this area.
AI: Fast rise times will cause lots of crosstalk, as you've mentioned this is independent of frequency. It's hard to see in the image what's traces and what's the grid. Parallel routes, or stacking routes on multiple layers make it worse. As you've done, a capacitor can slow the rise time, but you do need to be careful not to violate set up/hold times.
You may be seeing some reflections due to an impedance mismatch. I've seen source termination used on SPI clock lines to account for this. You want the output resistance plus your source resistor to equal the impedance of your trace.
I'm not familiar with the MCU you're using, but check the datasheet to see if you have any control of the slew rate, you might be able to slow it down. This is common on FPGAs which I'm more familiar with, but I have seen it on some MCUs I've worked with. |
H: Is the formula for inductive reactance the same when considering rectified AC?
Is the formula X\$_L\$ = 2\$\pi\$fL still true for rectified (but unfiltered) AC (in which case the frequency f, and therefore the reactance, would be doubled in the case of full-wave rectification)?
I forgot to add a parasitic resistor in series with the inductor. The inductor is not ideal as depicted in the image above.
AI: The answer to your question is NO.
With such a waveform for voltage (or current) the reactance is not defined by the same formula used with sinusoidal steady state inputs and outputs (with or without the modification in the factor 2 for the frequency) because the concepts of reactance, impedance and phasors only apply to sinusoidal steady state.
Applicability of the concept of impedance
Sinusoids, cosinusoids and their complex relatives, exponentials, have the very special property that they retain their waveform shape in linear time invariant circuits. The reason for this all boils down to the self-similarity of the exponential function, but you can think of a more 'real' explanation considering that the derivative of a sine is a cosine (another sinusoidal function, just shifted) and likewise, the derivative of a cosine is a sine (ok, with a sign change, it can still register as a phase shift). And the constitutive relation of (linear, time-invariant) inductors and capacitors are linear relationship involving derivatives.
So, basically: sinusoidal voltage or current IN ---> sinusoidal current or voltage OUT.
The only effect a circuit with R, L and C can have on a sinusoid is to attenuate it and to phase shift it.
One can describe this effect with a mathematical quantity that include these two pieces of information. And guess what, a complex number does just that.
The impedance is described by this complex number. You have a sinusoidal stimulus, and a sinusoidal response. When described by phasors, their ratio is just a complex number - the impedance, or the admittance depending on how you like to see it - describing how much the response has been attenuated and shifted in phase.
Inapplicability of the concept of impedance
BUT all of this simplified machinery can work only if you have sinusoidal IN and sinusoidal OUT. It does not work with other waveform shapes because they get 'distorted' by derivatives (and integrals).
This means that When you feed a R-L-C linear time invariant circuit with a nonsinusoidal input, the concept of impedance can no longer be used because it would be meaningless.
We can see that by solving the differential equations governing the circuit or... by simply using a simulator :-)
I ran a couple of LTSpice simulations feeding an inductor with a full-wave rectified sinusoidal voltage and current generators controlled by this voltage:
I had to use voltage controlled voltage and current generators to make sure the L circuit did not load the rectifier (which it does, and a lot).
The results are strikingly different.
When a voltage V(out2) with that shape is forced across an inductor, we get a current that builds up indefinitely, as shown by the purple waveform I(L2). This is not surprising, since to get the current we need to integrate the voltage over time and since V(out2) never go negative, we can only add, and add, and add...
But if a current I(L1) with that shape is forced into an inductor, we get a periodic distorted triangular-like voltage V(out) across it. The reason for this strikingly different behavior is that now to get the shape of the voltage we have to take the derivative of the current.
It worth noting that the concept of impedance requires that the signals be both sinusoidal and steady state. The above example has used a piecewise sinusoidal stimulus and although in each period the derivative and integral are still sinusoidal in shape, the overall waveform shape is not. When the derivative is involved we have discontinuities (in the above simulation they are softened because the input signal was, since I have used real diodes in my full-wave rectifier); when the integral is involved, we have a build up due to the value of the integration constant set by the boundary conditions.
In either case, since derivatives and integrals of functions that are not exponentials, sines or cosines return in general functions with a different shape, you can no longer describe the effect the inductor has on the stimulus waveform as a simple attenuation and phase shift. The bottom line is that you can kiss the concept of impedance goodbye.
Fourier analysis to the rescue
You can still use the useful impedance concept, though, if you apply it within its limits.
If you decompose the non-sinusoidal input signal into a sum of sinusoids (even a series, or an integral if it is not periodic) of different frequencies, you can use the concept of impedance on each single sinusoidal component to find the sinusoidal components of the output signal and then reconstruct the resulting waveform. |
H: AC analysis on transient model of Buck converter
I'm unable to understand why can't we run AC analysis on a transient model of Buck converter.
AI: AC analsyis (in the sense the term is used in SPICE) assumes all components in the circuit are linear.
A buck converter only works if some components (the switches) operate nonlinearly.
Therefore, an AC analysis will not capture the useful behavior of a buck converter.
That said, if you consider only frequencies well below the switching frequency, you may be able to use an AC equivalent circuit, with the the switches and inductor modeled as a controlled source, to analyze the control loop and verify such things as the loop stability and phase margin. |
H: Export pads as a pdf file in Altium
I'm not used to working on Altium Designer(17.1). I couldnt find how can I export only pad layouts to making a stencil schematic.
It is good to export as a pdf file if it possible.
AI: In a PcbDoc go to File -> Fabrication Outputs -> Final
There you get a print view of all layers. You can select the ones you want and print to pdf. Make sure you have the scaling you want.
In the configuration you can select for each page the layers you want to see. By selecting "Create Mask Set" you get the Paste and Overlay layers only. Remove the Mechanical. |
H: What is the difference between SOT 23 and SOT 23-3 package types?
I am faced with two types of packaging:
SOT 23
SOT 23-3
Is there some difference between them?
Based an article in Wikipedia it seems like there are no differences.
AI: In the beginning of the surface mount era was SOT 23, which had three pins. It was used mainly to replace the very popular TO-18 and TO-92 3 pin leaded transistor packages, the name means Small Outline Transistor. As such, three pins in a triangular configuration was easy to read, as it echoed the three pin leaded package.
As densities increased, it was noticed that the SOT 23 had 'missing leads', and the package could be increased to up to 6 leads without increasing significantly the area it consumed. 5 leads was an especially useful package, as it permitted a single op-amp or single 2-input logic gate to be implemented. So SOT 23-5 and SOT 23-6 were born.
Where a manufacturer's data sheet covers only single transistors, they tend to use only the original SOT 23 designation. Where a manufacturer is providing (let's say) diodes, diode pairs and diode triples in 3 and 6 pin versions of the SOT 23 package, they'll sometimes refer to the 3 pin version as SOT 23-3 to distinguish it from the SOT 23-6, but sometimes just call it SOT 23. It's up to the manufacturer.
Note that SOT 23 and SOT 23-3 are just names, they don't have any definition. They have just entered the language through use and custom. JEDEC formally standardises dimensions, its TO-236AB package outline is the JEDEC title for what is known as SOT 23 and SOT 23-3. |
H: Stability of a BIBO transfer function
Why is this transfer function unstable? The poles are \$0\$ and \$-4\$, so they are in the negative half-plane, theoretically it was to be stable. Can anyone explain to me what makes it unstable?
$$G(s)=\frac{10}{s^2+4s}$$
AI: G(s) is equivalent to an integrator (\$\frac{1}{s}\$) followed by \$\frac{10}{s+4}\$ and, given that integrators are unstable, the whole TF is unstable. The pole at 0,0 means it is on the cusp of instability so, in any practical implementation that doesn't use it (say) within a feedback loop that might create stability, it is unstable. |
H: If I need to access memory cell by cell, should I shift or index?
I have a piece of memory which I need to access cell by cell:
parameter RAM_LENGTH = 1024;
reg [7:0] mem [RAM_LENGTH - 1:0];
I need to iterate cells sequentially. It looks like there are at least two ways to do this. The first approach is to index memory as if it were C array of bytes:
reg [7:0] ram_addr = 0;
reg [7:0] current;
and then
current = mem[ram_addr];
ram_addr = ram_addr + 1;
This is cheap for CPU. But what if Verilog builder will attempt to build a 1024 channel 8 byte width multiplexer for me? This would be a digital circuit of tremendous size that this memory may not deserve. Or is the Verilog builder smart enough to implement access by index more reasonably?
The alternative approach would be to shift the cells every time the value is needed:
current <= mem[0];
for (i = 1; i < RAM_LENGTH; i++)
mem[i] <= mem[i-1];
in this case, I would hope from the builder to generate a shift register rather than overgrown multiplexer, as all values that define the loop are constants.
Which approach is more reasonable and would be typically used by an experienced Verlilog developer?
AI: Both approaches are viable, depending on what you want the synthesized implementation to be.
The indexed version would typically be used if you want the memory to be implemented using the internal block ram in the target device. In this case, the clock speed is limited by the memory access time.
The shift register version will use the registers in the logic cells, or in the case of Xilinx could use the SRL shift register mode of the LUTs. The shift register mode could potentially be faster, but it will use more routing and LUT resources.
In any case, you can always directly instantiate FPGA specific logic blocks in order to remove any ambiguity about how things get synthesized. The "generate custom IP" functions of FPGA development environments allow you to generate custom sized memories, FIFOs, shift registers, etc. |
H: What is the equation for capacitance with aysmmetric plates?
The general equation for capacitance:
\$C = \frac{\varepsilon_0 \ * A }{d} \$
C capacitance
\$\varepsilon_0\$ permitivity of free space
A area of equally sized plates
d seperation distance between plates
I cant seem to find an equation whereby the equation features two areas i.e A1 and A2 (representative areas of each plate)
Does such an equation exist (I'm sure it does, somewhere)?
Failing that how reasonable a result would I expect to find if assuming A as the smallest area of the two plates?
Background:
Working on implementing my own proximity sensor whereby the first plate is the sensor head itself, but the second plate is the object the sensor detects i.e. the object is bigger than the sensor head.
AI: I'd consider using the microstrip model and then think of ways to develop it: -
Where the formulas quoted on this website calculator are: -
This is a starting point and I would urge you to look at other website calculators and compare formulas. There should be a site that gives a derivation of proof that might allow you to reduce the ground plane from being infinitely wide/long to something more akin to your problem.
The model above assumes an infinite ground plane so it will give a slightly higher value for capacitance. |
H: Is this interface just a low pass filter?
I found the following BNC input output box for two channels(left side inputs, right side outputs):
The grounds of the BNCs are connected via the metallic case. I checked this with multi-meter continuity test.
Then I read the cap and resistor values and drew and simulated this interface for one channel as follows:
Could this be just a low pass filter? Anything related to common-mode? What are these 10nF caps?
AI: It is a low pass filter.
C1 does the low frequency filtering, together with R1, making a time constant of 220uS, which gives a -3dB frequency of about 720 Hz, which agrees with your graph.
At much higher frequencies, the residual inductance of C1, due to its leads and large physical size, stop the filter working, and the stopband rises again. If a filter based on C1 alone was to be used to stop RF pickup by an amplifier, it may not work too well.
The 10nF capacitors are intended to suppress this higher frequency transmission. Being a lower value and having shorter leads, they have less residual series inductance, and so filter to higher frequencies. C2 works well for this purpose.
Unfortunately C3 does not work well, as it is in shunt with C1. At some frequency where C1 has gone inductive, C3 will form a parallel tuned circuit with the inductance of C2, actually enhancing the transmission of this frequency through the filter.
Fortunately, people are rarely bitten by this mistake. In this filter, C2 may well provide enough attenuation that the C1/C3 resonance does not cause an actual problem. Or it may be used in an environment where there are no problem transmitters at the specific resonance frequency. When the large capacitor is a lossy electrolytic, it will rarely have sufficient Q to form a resonance.
All that would be needed to eliminate the C1/C3 problem is a resistor of a few ohms between C2 and C3 to 'de-Q' their resonance. Ferrite beads are often used for this purpose when the voltage drop of an extra resistor cannot be tolerated in (for instance) power supply filtering. |
H: Op amp voltage follower saturates (high-rail) at 0V
I have 3 op amps, and they perform in two different ways, but I am not sure why. I want to buy another op amp that behaves a specific way, but I'm not sure what spec causes it to behave like this.
Here are the 3 op amps I'm using. I will refer to them as A, B, and C respectively from now on.
A) NJM072CAG-TE2 - Acts Strange
B) RC4558P - Acts strange
C) LM324DR - Acts Ideal
After a lot of hassle, I decided to use them in a very basic way to test their properties using a voltage follower circuit with supplies (V-)=0V and (V+)=5V (now we won't have to deal with gain and such).
I hooked up Vin to a variable power supply (0-5V), and I measured Vout with an arduino and made graphs. As I increased the voltage from 0->5V and back down, here's what the output looked like for each of the three op amps. Red=Vin, Blue=Vout
A) NJM072CAG-TE2
B) RC4558P
C) LM324DR
Notice how A and B output a high voltage when the input is 0 (it stays this way until about 1.0V).
So my overall question is: How can I know if an op amp will "Saturate" or not at 0V (Like A & B) instead of following the voltage properly (Like C)?
Thanks in advance!
AI: The first device (7812) is a voltage regulator and not an op-amp so that's easy to answer. See EDIT below following OP changing their mind.
The 2nd device (RC4558) is not a rail-to-rail op-amp and it's output cannot get within 1 volts of either supply rail. See VOM (Maximum output voltage swing) in the data sheet. The VICR (Common-mode input voltage range) is also limited so you shouldn't use inputs too close to the power rails without unexpected results.
The LM324 is OK getting to the negative (0 volt) rail but has limits like the RC4558 when getting to the positive rail.
You also need to ensure that there is enough suipply voltage on the op-amp or it won't adequately perform. For instance, the RC4558 needs a minimum supply rail of 10 volts and not 5 volts. It's all there in the data sheet but you have to get used to the terminology used.
EDIT following change by OP.
The NJM072 has both input and output voltage restrictions specified in the data sheet. Input common mode range is not guaranteed to be better than +/-11 volts on a +/- 15 volt supply. The output swing is similarly problematic (+/-12 volts on a +/- 15 volt supply). Minimum supply for this op-amp is 8 volts. |
H: Solving a parallel RL circuit for the r and l values
I've a parallel RL circuit:
simulate this circuit – Schematic created using CircuitLab
And I know that (the RMS input-current) \$\overline{\text{I}}_{\space\text{in}}=2\$ A, (the RMS input-voltage) \$\overline{\text{V}}_{\space\text{in}}=200\$ V, the input frequency is \$50\$ Hz and \$\overline{\text{P}}_{\space\text{in}}=69.44\$ W now I need to find \$\text{R}\$ and \$\text{L}\$:
$$
\begin{cases}
\overline{\text{I}}_{\space\text{in}}=\frac{\overline{\text{V}}_{\space\text{in}}}{\left|\underline{\text{Z}}_{\space\text{in}}\right|}=\frac{\overline{\text{V}}_{\space\text{in}}}{\sqrt{\frac{R\omega L}{R^2+(\omega L)^2}}}\\
\\
P=\overline{\text{V}}_{\space\text{in}}\cdot\overline{\text{I}}_{\space\text{in}}\cdot\cos\left(\varphi_{\space\text{in}}\right)=\overline{\text{V}}_{\space\text{in}}\cdot\overline{\text{I}}_{\space\text{in}}\cdot\cos\left(\frac{\pi}{2}-\arctan\left(\frac{\omega L}{R}\right)\right)
\end{cases}\tag1
$$
Using the given values:
$$
\begin{cases}
2=\frac{200}{\sqrt{\frac{R\cdot2\pi\cdot50L}{R^2+(2\pi\cdot50L)^2}}}\\
\\
69.44=200\cdot2\cdot\cos\left(\frac{\pi}{2}-\arctan\left(\frac{2\pi\cdot50L}{R}\right)\right)
\end{cases}\tag2
$$
But when I tried to solve the system I get imaginary numbers, what is my mistake?
EDIT:
I can write:
$$\cos\left(\frac{\pi}{2}-\arctan\left(\frac{2\pi\cdot50L}{R}\right)\right)=\frac{2\pi\cdot50L}{R}\cdot\frac{1}{\sqrt{1+\left(\frac{2\pi\cdot50L}{R}\right)^2}}\tag3$$
So, I get:
$$
\begin{cases}
2=\frac{200}{\sqrt{\frac{R\cdot2\pi\cdot50L}{R^2+(2\pi\cdot50L)^2}}}\\
\\
69.44=200\cdot2\cdot\frac{2\pi\cdot50L}{R}\cdot\frac{1}{\sqrt{1+\left(\frac{2\pi\cdot50L}{R}\right)^2}}
\end{cases}\tag4
$$
Now, for example we get:
$$2=\frac{200}{\sqrt{\frac{R\cdot2\pi\cdot50L}{R^2+(2\pi\cdot50L)^2}}}\space\Longleftrightarrow\space L=\frac{R\pm Ri\sqrt{3999999999999}}{200000000\pi}\tag5$$
AI: Try and find R first.
You know the applied voltage and you know the power. All that power is dissipated in the resistor so, 69.44 = \$\frac{200^2}{R}\$ hence R = 576.04 ohms.
Can you solve it from here? Hints are not needed any more because the OP spotted his mistake so: -
Knowing apparent power (400 VI) and active power (69.44 watts) you can calculate reactive power as \$\sqrt{400^2-69.44^2}\$ = 393.926 VIr.
Reactive power is the reactive watts taken by the inductor hence \$X_L\$ is \$\frac{200^2}{393.926}\$ = 101.542 ohms. Hence L = 323 mH. |
H: Replicate PCB design on stripboard
I'm thinking about making a DIY project (this one).
I'm a complete n00b, I just have some theoretical knowledge about electronics from some university courses, and I'd like to learn some more. I was thinking about avoiding to buy the kit PCB (which is double sided) and, since I have the schematics, trying to replicate it on a stripboard. Is this reasonable, and which workflow should I follow? Make a solderless breadboard prototype based on the PCB design and then a final model on the stripboard or redesigning the layout on a CAD software? I don't know if there is a best practice about this or if it's even possible.
Thank you.
AI: If you want to use stripboard, there are CAD stripboard layout editors (e.g. VeeCAD - see Stripboard/veroboard/matrix board design software).
These editors allow you to arrange the circuit and plan links/breaks, then you print it on paper, stick the paper on the stripboard, do the soldering.
This is better than trying to optimize the layout by breadboarding since repeatedly moving components around will probably cause them damage (and is slower to do).
As an aside, if you would "like to learn some more" (electronics design), is doing a load of soldering really going to help? |
H: Required velocity of each wheel in 3-wheel omni bot
I'm using a 3-wheeled omni bot which can move in any horizontal direction (example: https://www.robotshop.com/en/3wd-48mm-omni-wheel-mobile-robot.html).
Given an object velocity (velocity at which the entire bot should move) and an angle it should move in (degrees), how can I determine the required speed of each wheel?
I tried the following, but have experienced some strange results:
const int wheel1Deg = (90 - (90 - angle)) % 360;
const int wheel2Deg = (90 - (210 - angle)) % 360;
const int wheel3Deg = (90 - (330 - angle)) % 360;
Setpoint = cos ( wheel1Deg * PI / 180.0 );
.....etc
AI: This is a simple trig problem:
S = desired speed
a = desired angle of travel relative to wheel
If the robot is oriented with a wheel sideways on the front of the robot, then wheel offsets will be 90, 210, 330 (front, right, left).
a = desired angle of travel + offset angle of wheel
sin(a) = M / s
M = S * sin(a)
Repeat for each wheel.
Once you write the code, do a quick check for a=0 and make sure M=S and for a=90 and make sure M=0.
(edit: angles corrected, my bad) |
H: Induction motor - d-q model
I would like to simulate an induction motor in Matlab/Simulink using the d-q model.
I have found a paper that describes the whole procedure but I have this problem.
I am trying to create this block :
This block defines the following equation.
I can not figure out what the parameter *u in the matrix gain stands for and how this block defines the equation.
Edit: I do not have the Simulink model. The pictures are screenshots taken from the paper that I study.
AI: u in Simulink indicates the input signal of the block, therefore the gain of that block is KS. I would expect KS to be the matrix you have in the equation, but we can't know for sure from the screenshot.
What you can guess is that, as an 3x1 array of van, vbn and vcn is given as an input to the block, and an 1x2 array with vqsS and vdsS is returned, the gain should be a 2x3 matrix. |
H: Extending Output of a fixed Linear Voltage Regulator
I am working on extending output voltage of a fixed linear voltage regulator.Yes, I accept I could go for the variable voltage regulator.But I am in need to use a fixed voltage regulator.
My query is regarding the derivation of Output Voltage (V0) given in
Datasheet
Can you help me to figure out how this equation rolls out?
AI: The output voltage \$V_O\$ will be whatever the regulator voltage is plus whatever the voltage is at the top of \$R2\$.
\$V_O = V_{XX} + (I_{R2}) * R2\$
So, to determine the voltage at the top of \$R2\$ you need to know the current going through it, \$I_{R2}\$.
That will be \$I_Q\$, the quiescent current of the device plus whatever current goes through \$R1\$.
\$V_O = V_{XX} + (I_Q + I_{R1}) * R2\$
Since \$R1\$ has the regulator voltage across it, we know:
\$I_{R1} = V_{XX}/R1\$
So, substituting for \$I_{R1}\$, we get:
=> \$V_O = V_{XX} + (I_Q + V_{XX}/R1) * R2\$
=> \$V_O = V_{XX} + V_{XX}.R2/R1 + I_Q.R2\$
=> \$V_O= V_{XX}.(1 + R2/R1) + I_Q.R2\$
Note: This circuit should never be used if the input voltage exceeds the maximum input voltage, \$V_I\$, of the regulator chosen. I have seen folks try to use this method in an attempt to "shoe-horn" the device to work at higher voltages, and, although once in a steady state it will work ok, sooner or later the initial start-up, or shut-down voltages will kill the device if you do not surround it with protection devices. |
H: Unequal length Transmission line
I know that a transmission line is essentially two wires with some series resistance and inductance and some parallel capacitance - when there is a change in the voltage between them at a point the charge in the capacitance moves and thus a current is flowing in opposite directions in both wires.
In the case that a transmission line is terminated with an open circuit - the voltage and current waveform are reflected back when they reach the termination point.
But what happens if one wire is longer than the other? - I assume that the voltage and current reflect at the point at which the short wire ends, and the voltage and current in the extra section of long line never sees any change - is that right?
EDIT:
To add some information, these are long wires I'm talking about - roughly 1KM in total. I'm looking at the effect of having open circuits at different points and how this changes the voltage and current on both wires and on both sides of the break.
The signal propagating down the wire is of the order 10s of MHz
AI: Considerations:
In my opinion The other answers I saw in this post accurately define the practical results of your question, I very much liked @Norm's answer since he likened it to a cutting the internal wire of a co-axial cable. I will attempt to explain a perhaps more theory based solution by starting with a transient discussion of waves to which steady state could then be interpreted from.
Consider the simple schematic at the end of this post as a reference for my answer, the "Mutual C" represents the break point.
Assumptions:
Please pardon the fact that I didn't model the transmission line using all circuit parameters, it is enough just to place that parasitic capacitance to get my point across.
Background:
In traveling wave theory, you'd expect a wave to propagate to the end of the conductor (just like water would in a pipe), but to really represent this moving voltage and current wave we have to use inductors and capacitors to show that there is a "time delay" in the voltage and current signals. This is a transfer of energy.
Answer:
I know that a transmission line is essentially two wires with some series resistance and inductance and some parallel capacitance
You nailed the point right here, and if you use an entirely ideal model the theory will fall apart here. Notice that by simply adding in some parasitic and non-ideal devices we can get a better idea as to what will happen.
the voltage and current in the extra section of long line never sees any change - is that right?
Not quite, consider my follow up question; if there was no voltage or current change at that longer line, then what do you think the voltage would be at the end of that longer line at steady state?
Let's look into this:
A voltage impulse will travel from the source to the break point and charge up the line. There will be reflection at the break point as if it was an open circuit (slightly different but safe to assume).
The beauty of transients is that the circuit does not "know" that that wire "goes nowhere" until the energy reflects and cancels. So there will be an energy wave in the form of a voltage impulse that then travels to the end of the longer line. From here you would find a partial reflection and partial dissipation by an "antenna-like" effect and by parasitic impedances. The current in this path will be negligible from the other sources but it's existence is what validates our schematic. This will continue until there is a standing voltage across all points.
Now remember that question I asked up there? Well now you can say that at steady state the voltage at the end of both wires will approximately be equal in magnitude to the source voltage (given some losses). This agrees with our open-circuit theory of voltage.
simulate this circuit – Schematic created using CircuitLab |
H: How stable are temperature controlled crystal oscillators?
This question is not as obvious as it might seem. Consider this, concerning Rubidium clocks:
All commercial rubidium frequency standards operate by disciplining a
crystal oscillator to the rubidium hyperfine transition...
So at a fixed temperature, and over a few seconds (say 10 seconds), is a regular crystal oscillator stable to part per billion accuracy?
AI: Your question is addressed by Allan variance. Yes, a decent crystal oscillator is quite stable over a time frame of a few seconds, but not as stable as one disciplined by a rubidium cell. The long-term stability of a quartz oscillator suffers from aging. From one to ten seconds, a good quartz oscillator can be stable to about one part in 10^11: |
H: Baker Clamp application for PNP Transistor
I have an issue related to Baker Clamp application for PNP Transistor. I know how to implement the Baker Clamp for NPN Transistor. However I do not know how to do it for PNP. So could anyone can suggest me a schematic?
Secondly, can the Baker Clamp reduce the turn-off time of PNP transistor?
Thank you very much in advance.
AI: How about this one?
simulate this circuit – Schematic created using CircuitLab |
H: Unrealistic ESR calculated from DF
I was calculating ESR for this ceramic capacitor, Samsung P/N CL21A226MQQNNWE.
Per the datasheet, DF is given as 0.1 max at 120 Hz.
Per formula, ESR = 0.1 / (2 * Pi * 120 * 22uF) = 6 Ohms.
What am I doing wrong, or is the ESR really 6 Ohms? That just seems way too high for a ceramic capacitor.
I feel a bit silly asking this, but hey, if I am confused someone else probably will be, too.
ADDENDUM
Basically, the ESR for MLCC capacitors is surprisingly high at low frequencies. However, in my application, the ESR at higher frequencies is what was of interest. The graphs provided by several answers were super helpful and show how much the ESR changes with frequency. This is not something I knew about when I asked the question. I just knew that MLCC's supposedly had very low ESR (everybody knows this, so it must be true, right?). Anyway, now everything makes sense.
AI: This is correct only as a line f* diode bridge cap. Tan delta is std at 120Hz.
It is unwise to use as that*.
Unlike some or most e-caps this ceramic cap drops to 3 mohms near SRF ,~1MHz
Look for the PDF with my graph (re-search) hint Samsung site
Answer: char. Data.pdf http://www.samsungsem.com/global/support/product-search/mlcc/1205485_4290.jsp |
H: Calculate Inductance of a three phase transmission line
I was trying to solve the above problem. As I have done many similar problems, I attempted it in the following way
But I was shocked when I checked the solution given in my workbook.
Please help me to understand this problem.
AI: The coupling of other phases tends to oppose to induction of each phase slightly. You are close. |
H: Safely disconnecting an inductor
How is it possible to safely disconnect/turn off an inductor that has current through it without causing a huge backward voltage? Even dropping from a circuit with low current, it the current will still be going from finite to 0, in a very small space of time (how would you calculate this time?), causing a big voltage spike. How can inductors possibly be safe if disconnecting them is so dangerous?
AI: You use a flyback diode.
Knowing the name, you can search regarding your specific application, such as for a relay. |
H: EMI determine farfield from nearfield probing
So I went to the chamber and failed at 900MHz. Then sniffing around with my E-field probe and my spectrum analyzer I found the source. Next I made some modifications that reduced what I saw with the probe by 3dB. My question is should I expect to see a 3dB reduction now when I go back to the chamber?
I'm sure it will be lower but I don't know if it will be linearly lower or not.
AI: The short answer is no! You cannot extrapolate from close proximity E field (or B field) measurements to a proper test set up in a lab. Near field is the region where em radiation need not be both E and B fields, but in the far field, after some propagation distance proportional to the wave length, the E and B fields merge (as in they are both present). You can have a radiator emmiting B fields which are invisible to an E field probe up close, but would be picked up by an E field probe in the far field measurement. The reverse is also possible with B field probes.
The long answer is it depends on the source, the fix, and the testing standard.
You need power and antennas to radiate at any given frequency, which means in practice you can either have high currents or long current paths causing your failure. Given the high frequency I'm going to guess a good radiator rather than a high current. If your fix involved snubbing or terminating (ie, stopping the noise at source) then you've got a good chance of seing some improvement, but if your fix involved tin foil or ferrites (ie, blocking the noise from getting to your probe) i would say its 50/50.
Be aware that the test houses I've worked with have a 6dB error tolerance, and things can easily change by that much just by a different setup of the same equipment. (Different cable routing etc). 3dB isn't all that much in the grand scheme of things. It could easily be just the probe on your bench in a slightly different position. |
H: Input flexibility for powered vs. unpowered sensors
I would like to design a flexible input interface for my embedded device, which will see a mixture of sensors connected. The sensors themselves (e.g. thermistors) will be two-wire, with the data/signal wire being pulled up to 5V prior to interfacing with an ADC. The issue I'm trying to address is that some sensors will interface with my device, which will then provide 5V pullup and GND, whereas some sensors will have an external 5V pullup and GND, with the single data/signal line interfacing with the device.
Example of case 1 (unpowered):
Example of case 2 (powered):
Is there a way I can design the device circuitry to account for both scenarios? I would ensure the device GND is shared with the powered sensor GND, so my focus is on the 5V pullup. Can I use an IC of some sort to enable/disable the pullup resistor, such that the line up to 5V is open-circuited for powered sensors?
AI: Some sort of analogue switch or FET in series with the pull-up will do fine here.
simulate this circuit – Schematic created using CircuitLab
NOTE: This is a P-Channel MOSFET, and note that the Source is at the top. This is because with MOSFETs, you need to be able to control/know what Vg and Vs are (i.e. to control it with Vgs). We don't know what the sensor voltage is/could be, so we need to tie that to the drain. We know 5V (when O/C) is at the Source, and so we can turn it on by changing the voltage relative to this at the Gate.
Since N-Channel MOSFETs are off when Vgs is 0V (i.e. when we would have 5V at the gate, too), and on when Vgs is positive (e.g. 5V), we would need greater than 5V to turn it on in this case (i.e. some sort of monster 10V I/O microcontroller). On the contrary, with P-Channel MOSFETs, they are off when Vgs is 0V too (i.e. when we have 5V at the gate), and are ON when Vgs is negative (e.g. -5V). When we make the microcontroller apply logic low (0V) to the gate, the Vgs is (0-5) = -5V, and so the P-Channel MOSFET will turn on, and the data line will be pulled high.
Edit following some additional queries/clarifications in the comments below: I'm considering using the following circuit to provide the necessary 0V Vgs to turn off the p-channel MOSFET. As this circuit inverts the logic, the default microcontroller GPIO output (low) will cause a 5V level to be applied to the MOSFET Gate, which will result in a 0V Vgs, turning off the MOSFET. Applying a high signal to the transistor will drive 0V to the MOSFET Gate, cause a -5V Vgs, turning on the MOSFET. |
H: Series RLC Circuit reduction possible?
This might be a dumb question, but with a circuit like this one:
Are we allowed to add the resistances and capacitance in series to get a single resistor, capacitor, and inductor? Can elements in series be reduced despite components in between them? If not, how else would we be able to reduce this circuit so we can get the ideal form to apply equations?
AI: In your circuit the differential equation given by KVL is
$$IR_1+\frac{1}{C_1}\int{I}dt+L\frac{dI}{dt}+R_2I+\frac{1}{C_2}\int{I}dt= 0$$
which can be shown to be equal to
$$I(R_1+R_2)+(\frac{1}{C_1}+\frac{1}{C_2})\int{I}dt+L\frac{dI}{dt}= 0$$
which can be rewritten as:
$$IR+\frac{1}{C}\int{I}dt+L\frac{dI}{dt}= 0$$
where $$R=R_1+R_2$$
is the equivalent series resistance and
$$C=1/C_1+1/C_2$$
is the equivalent series capacitance in the circuit.
So yes, you can rewrite this in this manner and you will see the same differential equations governing the system's current. Thus, this shouldn't pose a problem in your analysis. The only concern I would have is if phase information might be lost when combining the capacitances, but I don't think that it will be. |
H: How to connect two (or more) BJTs (collector of Q1 to base of Q2 for instance) and still make their bias voltages independent?
The question is in the title. I'm learning about how to use BJTs and was wondering how I could connect them in blocks the way bias voltages (thus operation modes) are not being dependant.
Thank you!
AI: A capacitor coupling will do the job easily. The capacitance is chosen to be large such that at DC, the capacitor will be open and the circuits will become independent of each other. Their bias voltages will be independent. |
H: What's wrong with my taillight verilog design?
I'm working on a T-bird car taillight design code, here is my design:
B means brake, all lights on at break,
when turn left lights on sequence: 000000 -> 001000 ->011000->111000
turn right lights on sequence: 000000 -> 000001 ->000011->000111
module taillight (clka, clkb, restart,brake,right,left,lc,lb,la, ra,rb,rc,state);
input clka, clkb, restart,brake,right,left;
output lc,lb,la, ra,rb,rc;
output[2:0] state;
wire clka, clkb, restart,brake,right,left;
reg lc,lb,la, ra,rb,rc;
parameter SIZE = 3;
parameter IDLE = 3'b000, l1 = 3'b001, l2 = 3'b011, l3 = 3'b010,
B = 3'b100, r1 = 3'b101, r2 = 3'b111, r3 = 3'b110;
//internal variable
reg [SIZE-1:0] state ;// Seq part of the FSM
wire [SIZE-1:0] c_state ;// Internal state reg
reg [SIZE-1:0] n_state ;// combo part of FSM
assign c_state = fsm_function(state,brake,right,left,restart);
//----------Function for Combo Logic-----------------
function [SIZE-1:0] fsm_function;
input [SIZE-1:0] state,brake,right,left,restart;
case(state)
IDLE: begin
if (!restart&&!brake&&!right&&!left) begin
fsm_function = IDLE;
end else if(!restart&&!brake&&!right&&left) begin
fsm_function = l1;
end else if(!restart&&!brake&&right&&!left) begin
fsm_function = r1;
end else if(!restart&&(brake||(right&&left))) begin
fsm_function = B;
end
end
l1: begin
if (!brake) begin
fsm_function = l2;
end else begin
fsm_function = B;
end
end
l2: begin
if (!brake) begin
fsm_function = l3;
end else begin
fsm_function = B;
end
end
l3: begin
if (!brake) begin
fsm_function = IDLE;
end else begin
fsm_function = B;
end
end
r1: begin
if (!brake) begin
fsm_function = r2;
end else begin
fsm_function = B;
end
end
r2: begin
if (!brake) begin
fsm_function = r3;
end else begin
fsm_function = B;
end
end
r3: begin
if (!brake) begin
fsm_function = IDLE;
end else begin
fsm_function = B;
end
end
B: begin
fsm_function = IDLE;
end
default : fsm_function = IDLE;
endcase
endfunction
//----------Seq Logic-----------------------------
always @ (posedge clka)
begin : FSM_SEQ
if (restart == 1'b1) begin
n_state <= IDLE;
end else begin
n_state <= c_state;
end
end
//----------Output Logic——————————————
always @ (posedge clkb)
begin : OUTPUT_LOGIC
case(n_state)
IDLE: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b000000;
end
l1: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b001000;
end
l2: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b011000;
end
l3: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b111000;
end
r1: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b000001;
end
r2: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b000011;
end
r3: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b000111;
end
B: begin
state <= n_state;
{lc,lb,la,ra,rb,rc} <= 6'b111111;
end
endcase
end // End Of Block OUTPUT_LOGIC
endmodule // End of Module twoP_FSM
my testbench is like:
module taillight_tb();
reg in_clka, in_clkb, in_restart,in_brake,in_right,in_left;
wire out_lc,out_lb,out_la, out_ra,out_rb,out_rc;
wire [2:0] out_state;
integer i;
parameter [5:0] value = 6'b000000;
//create an FSM instance.
taillight U1 (.clka (in_clka),
.clkb (in_clkb),
.restart (in_restart),
.brake (in_brake),
.right (in_right),
.left (in_left),
.lc (out_lc),
.lb (out_lb),
.la (out_la),
.rc (out_rc),
.rb (out_rb),
.ra (out_ra),
.state (out_state)
);
initial
begin
for(i=0;i<64;i=i+1)
begin
{in_clka, in_clkb, in_restart,in_brake,in_right,in_left}=value+i;
#1;
end
$dumpfile ("taillight_tb.vcd");
$dumpvars;
$display ("in_clka,\t in_clkb,\t in_restart,\t in_brake, \t in_right, \t in_left \t out_lc, \t out_lb, \t out$
$stop;
end
endmodule
But when I test my code on moldesim, the waveform looks like this:
AI: state is only being updated on the rising edge of clkb, where it takes the value of n_state, and n_state is only updated at the rising edge of clka, where it takes the value of c_state. The only thing that matters is the state of the other inputs when clka rises, but you have the clock lines as the two slowest lines, so there's a whole lot of not much happening.
If you reverse the order of bits in the for loop, you'll at least have a lot more going on.
You generally want the clocks to be the highest frequency signals.
There are a few other issues you might have. You generally need to make sure that input signals have a minimum setup and hold time around the clock edge. If you have asynchronous signals coming in, you can just run the signal through a few flip flops to mitigate any resulting instability. Similarly, people tend to run chips off of a single clock. If you can't guarantee the timing between the two clocks, you can run into the same setup and hold time violations, which will make your design very unstable. |
H: Shaded pole motor speed control
I've recently been given a 24W 230VAC 2 pole shaded pole motor(Mellor Electric AC1004) to make a fan out of. This fan needs to have a variable output speed depending on the temperature of the room. I am quite new to motors and was wondering how to make the motor speed variable. I have done some research and seen that by just varying the voltage the speed can be reduced, however I believe this is not the best way to go about this. I've also seen people use Triac based dimmers in order to accomplish the same thing as well as VFD's but they are quite expensive(VFD's) and i don't think they are suitable to this. I would like some input as to what method would be best. Thanks.
AI: Voltage-only control of a Shaded Pole (SP) motor is an acceptable method and is the most common. It doesn't work on other types of AC motors, but because of some of the inherent design aspects of what make a SP motor work in the first place, the torque / speed relationship is more or less linear, or can be made to appear so. The point is, you CAN use a single phase output VFD if you have money to burn, but a "dimmer switch" works fine and will not hurt that motor. |
H: I want to find voltage across 5 ohm resistance by thevenins theorem
i want to know that wether my answer is right or wrong and if it is where?
AI: Looks correct. I didn't use thevinin's theorem, but I got the same answer as you by doing some algebra on the node voltages. I2, I1, etc below are the currents into node A, through the 2 ohm, 1 ohm, etc resistors respectively. They must sum to zero, since current that enters the node must also leave it somewhere. A is the voltage at point A. I've set the voltage at point B to zero. (since you have to do that somewhere).
I2 = (20-A)/2
I1 = (-10-A)
I5 = -A/5
I4 = (12-A)/4
I1+I2+I4+I5 = 0
10 - A/2 -10 -A -A/5 +3 -A/4 = 0
10 - 10A/20 -10 -4A/20 +3 -5A/20 = 0
60 - 10A -20A -4A -5A = 0
60 = 39A
A = 60/39 = 1.538 |
H: lm318n as noninverting amplifier
I am trying to amplify an audio signal generated by a hydrophone. I am trying to work from this (very general) circuit diagram I have found online and in an electronics textbook I own.
simulate this circuit – Schematic created using CircuitLab
However, I am confused about what input and outputs correspond to what. The hydrophone is attach to a coaxial cable, which is diagrammed as such on its data sheet.
As of now I am using a connecter to break out the coaxial cable to a "positive", and "negative" wire. So, currently, my circuit is as such, with ground representing the 0v terminal on the bench top power supply I am using.
simulate this circuit
When I measure my Vout with an oscilloscope with the power supply turned on, I get a randomly oscillating garbage output, so clearly I am doing something wrong. Are all of my input and outputs correct. Should I be completing the circuit by connect Vout to gnd, or the + terminal of my hydrophone?
AI: The LM318 is quite a lively amplifier.
As a minimum, you need to make the following changes
a) Bypass the power supplies close to the package with small value capacitors
b) Raise the feedback resistor values, 100ohms is too low
c) Provide a DC bias path to your amplifier input
d) Decouple the transducer input
simulate this circuit – Schematic created using CircuitLab
While the data sheet says this amplifier will be stable at unity gain, so more stable at the gain of two here, all that will be for naught if you've built a bird's nest on a proto-board.
A good way to get oscillatory performance out of an otherwise good amplifier is to drive a pure capacitive load with it, like a coaxial cable into an oscilloscope. Decouple the output with a few 10s of ohms series resistor (R4) so the amplifier isn't driving the capacitance directly.
The data sheet does talk about stability modifications you can make with extra capacitors connected to pins not shown on this simple schematic. If you are still having problems, read these parts carefully.
Excess capacitance to ground at the amplifier -ve input, through perhaps a bird's nest board, or bad PCB layout, can also destabilise an amplifier. A few 10s of pF placed across R1 (C4) can sometimes restore stability in these cases.
If R3 is too low a value for your transducer, check the amplifier data sheet to see how high a value you can use. It is possible to bootstrap this resistor to reduce the loading if needed. Although unlikely to be necessary at this low gain, a capacitor in series with R2 reduces the DC gain of the amplifier to unity, to allow a large input offset voltage due to a large R3 value to be tolerated. |
H: ULN2803a relay connection
A motion sensor and a relay should be connected with an atmega328p. I soldered my circuit on a perfboard and have 5V power and ground rails on it.
Can I use the rail for the COM port of the ULN2803a or do I need to remove the VCC, jdVCC jumper on my relay and connect a separate power supply to it? And take connect the COM port to that VCC?
It strikes me as a bit strange that I would need that many power sources for such a simple project, including the socket for the lamp that should be controlled with the relay, I'd need 3 sockets for this project.
Also, am I under the correct impression, that the use of the ULN2803a inverts my logic? Without I switched the relay ON with LOW, now HIGH provides the ON state.
And on a side note, any suggestions on how to improve my schematics are welcome. I'm just starting out and I would image that my schematic probably isn't that well to read.
Regarding the diodes:
On the product pictures on my 8CH relay these are labeled D1-D8.
AI: The ULN2003/2803 uses a Darlington output stage and this drops about a volt when activated so, if your 5 volt relays need a minimum voltage that is greater than 4 volts you might have problems. I'd consider using logic level MOSFETs directly driven from the IO pins. You will also need flyback diodes across the relays.
Also, am I under the correct impression, that the use of the ULN2803a
inverts my logic?
If you connect your load (the relay) between output and Vcc (5 volts) then a logic 1 at the input will drive current through the relay coil.
And on a side note, any suggestions on how to improve my schematics
are welcome. I'm just starting out and I would image that my schematic
probably isn't that well to read.
It's not bad - I've seen a lot worse. I'd consider using the GND/0 volt triangle symbol in several more places and removing the GND connections that string across your diagram. It just makes it easier to follow.
Can I use the rail for the COM port
Yes you can but my preference would be to get rid of the 2803 and use MOSFETs and flyback diodes for reasons already mentioned. |
H: How are load currents balanced in a distribution system?
Below I drew a simplistic view of a distribution transformer which supplies a particular public area for example some households and shops ect.:
Va, Vb and Vc are three phases(line voltages) of the transformer.
In my previous question I've asked about why balancing the line currents i.e making Ia, Ib and Ib close is important.
Now imagine Z1, Z2 and Z3 are initially same. Let's say they represent same type of electric owens. And we can say Ia, Ib and Ic are initially equal.
And now imagine one of the electric oven Z3 is plugged of from the mains.
In this case, will the system automatically equalize Ia, Ib and Ic again for the sake of a balanced system? Where and how is that done practically? Is there a control mechanism unit for that purpose?
AI: In this case, will the system automatically equalize Ia, Ib and Ic
again for the sake of a balanced system?
No it won't automatically balance and, as a result there will be some current passing down the neutral wire to the 3 phase power source. Previously, with all three loads balanced, neutral current would have been zero.
How are load currents balanced in a distribution system?
Statistically, with many households and factories, the currents are reasonably balanced in full load scenarios but nothing is perfect and current imbalances do take place. |
H: Mains power LED
I want to make a power LED in a small device I'm making, using 220V.
Are my conclusions correct?
simulate this circuit – Schematic created using CircuitLab
Assumptions
The forward voltage of D1 is negligible (due to 220V mains power)
Calculations
Amperage: V = I * R <=> I = V / R = 220 / 22000 = 10 mA
Wattage: P = V * I = 220 * 0.01 = 2.2 W
LED amperage: 10 mA / 2 = 5 mA (because of 50% duty cycle due to AC power)
Conclusions
It is safe to use a 3W, 22 kOhm resistor (well within 2.2 W).
The LED would led up like 5 mA (in a DC setup), which is bright enough for a notification LED.
AI: You need a diode across the LED to prevent large reverse voltages destroying it. LEDs are usually only rated for about 5 to 10 volts in reverse.
Wattage: P = V * I = 220 * 0.01 = 2.2 W
This assumes the extra diode is used i.e. conduction on both half cycles. I would use a 3 watt minimum rated resistor. |
H: Using low pass filter for a differential ended receiver system?
I want to use anti-aliasing filters in different scenarios. Below is the topology for how to use a passive LP filter in the case of a single ended transducer and single ended data acquisition:
How should the RC the connection be:
1-) If the source is diff ended and the data acq. is also diff ended?
2-) If the source is single ended and the data acq. is diff ended?
Could you illustrate these two cases by drawing like mine above.
Edit regarding an answer:
AI: If the source is diff ended and the data acq. is also diff ended?
If the DAQ input is differential then you need to attenuate the differential signal at higher frequencies so, use resistors in series with each input and a capacitor directly across the DAQ input after the resistors.
If the source is single ended and the data acq. is diff ended?
You do exactly the same because you don't want to imbalance the impedance of lines that could pick up external inteference (common-mode) and, due to those impedance imbalances, convert a common mode interference to a differential interference.
You might also need to consider impedance balancing at the source and cabling between source and DAQ. You might also need common mode decoupling capacitors to help reduce noise. This is for noise reduction rather than anti-alias filtering. |
H: How to efficient use Solar Panel to charge a 12V battery 10Ah?
I have tested my solar panel and i have these values :
Conneteced in series produces :
Around 136V and 16mA(closed circuit)
Connected in parallel produces : Arround 15V and 450mA(closed circuit)
I want from this panel to be able to charge a 12V battery of 10Ah but also many other energy storage devices such as SuperCapacitors in the near future etc. etc.
So my goal here is to be able to at least give at the charger controller from the panel around 13V-15V and 1Amp or at least the closest to 1Amp.
What could be my best bet to do so :
Step down the series connection from 136V to 15V and raise the mAmps to where i need or use the parallel connection and give that straight to the battery charger and let the charger do the volts and amps regulations accordinng to battery/supercaps needs ?
I am on my first step of having the solar panel and try to find with these
values my best way to charge 12V batteries and or SuperCaps (making portable for these 2 options)
Any suggestion or new way of doing it will be fine also and much appreciated.
AI: Let's summarize. You have a panel that puts out 450 mA at 15 V. You want 15 V at 1 A.
This is clearly not going to happen. (15 V)(450 mA) = 6.8 W, which is the power your panel can put out. However, you want (15 V)(1 A) = 15 W. You can't create power from thin air. Physics can be inconvenient like that.
As a sanity check, let's look at the power from the series combination. (136 V)(16 mA) = 2.2 W. That means there is something wrong the series hookup, or maybe all cells weren't as fully illuminated as when you did the parallel test.
In either case, the best numbers we have still say that the panel puts out less than half the power you want. Get a bigger panel or lower your power requirements. No amount of conversion or parallel/series re-arrangement can fix this.
Switching power supplies can change the volts times amps tradeoff over a wide range with reasonable efficiency, but they can't make more power out than in. In fact, the power out will always be at least a little less than the power in due to some inevitable inefficiency. |
H: How did I break this optocoupler?
I'm trying to use an H11AA1 (datasheet) optocoupler to test when my doorbell is pressed (I'm in an apartment building):
simulate this circuit – Schematic created using CircuitLab
It worked when I first tested it, but then it stopped working less than a day later. I have a second optocoupler (which I bought with the idea that I would almost certainly break the first one somehow), and if I swap it in it works. The input part is supposedly rated for 230VAC, so I don't think the issue is there.
I've disconnected it all for now out of fear of breaking the second optocoupler. What did I do wrong?
AI: What might you be missing: -
The raw input has just internal diodes and these get messed up from anywhere between 1 volts and 3 volts. Use a resistor. 8 V AC is too much to put on the input. +/- 60 mA is the current limit into the device - stay away from this limit. |
H: What is the difference between modulating with cosine and exponential function?
Say I have an information signal x(t) with frequency f0 and I want to shift it on the spectrum to a much higher f1.
I would have 1) \$y(t)=x(t) \cos(\omega_1 t)\$ and by looking at the spectrum I'd see it's perfectly shifted.
I read you can also do the same by doing this:
2) \$y(t)=x(t) e^{j\omega_1 t}\$. If we only look at the real part we get almost the same as above with a cosine but it's perfectly symmetrical. What I don't understand is why?
If we take \$e^{j\omega_1 t} = \cos(\omega_1 t)+j \sin(\omega_1 t)\$ and look at the real part we only have a cosine. Isn't that the same as above? How is it that signal 1) and 2) are different?
edit: maybe it gets clearer with a picture, black is the information signal
AI: Considerations:
Instead of re-writing all the math, I'd like to direct you to this answer by @Matt L. over in math stackexchange to help you understand what happens when you multiply by cosine.
Meaning of multiplying by sin
Notice the 1/2 that shows up when using just cosine.
Answer:
If we only look at the real part we get almost the same as above with a cosine but it's perfectly symmetrical. What I don't understand is why?
You're right, if you only look at the real part when multiplying by the exponential then you in fact get the exact same thing as cosine (except the magnitude).
Even in your expansion using Euler's formula you can see this:
$$ e^{jwt} = Re{(e^{jwt})} + Im{(e^{jwt})} $$
$$ e^{jwt} = cos(wt) + jsin(wt) $$
$$Re(e^{jwt}) = cos(wt) $$
You are also correct in your drawing that using only one exponential will create only a single shift in one direction. Furthermore, this single multiplication (as in your second drawing) shifts the full power to right side and hence you don't see a 1/2 magnitude multiplication (like you see with the cosine).
This is where you must pause and realize that this multiplication in practice is actually not possible. We can create phase shifts but you cannot make sin because it is inherently not real, and thus you cannot make the signal in the second drawing because it isn't real.
So multiply by \$e^{jwt}\$ as much as you'd like but remember when you actually take this to the field you will only see the real quantities. |
H: NPN transistor controlling a PNP transistor
I can't understand why Multisim tells me that R2 and R1 will burn out after a while.
What are the correct resistor values that I should use. Or am I doing something wrong?
When a 3.3 V signal is received, the output of the PNP needs to be 24 V. Otherwise, it is to be 0 V.
Simulation works OK when I toggle the switches. However, when I leave the switch on for about 3 secs, R1 and R2 burn out and the PNP output does not work.
AI: \$P=V×I=\frac{V^2}{R}\$
Here is the power draw for the two, presumably broken, resistors:
1 kΩ resistor \$\rightarrow\frac{(\sim24)^2}{1000}=576\text{ mW}\$
2.2 kΩ resistor \$\rightarrow\frac{(\sim24)^2}{2200}=261\text{ mW}\$
A resistor that would be safe would be 1 W resistors in this case, they are pretty bulky. I doubt that multisim selects those on default. 1/2 W and 1/4 W are way more common.
I don't have multisim available right now, but I think that the rated power is in the settings of the resistors, might be worth a look.
If I were to make this circuit, then I might have used 10 kΩ or higher. But it all depends on what you are actually trying to do.
The 1 kΩ resistor can be a 1 W resistor, or higher, not a 1/2 W or 1/4 W resistor.
The 2.2 kΩ resistor can be a 1/2 W resistor, or higher, not a 1/4 W resistor.
The power dissipated for a 10 kΩ resistor in the same setting is \$P = \frac{(\sim24)^2}{10000}=57.6\text{ mW}\$
With a 10kΩ resistor you can use a 1/4 W resistor, you can even go as low as 1/16 W resistor. |
H: Uncommon mosfet usage
Occasionally I am faced with a problem where I am faced with a device that needs two of it's inputs to be shorted together for something to activate (Think smoke machine or gate motor).
This is the circuit I have been using:
simulate this circuit – Schematic created using CircuitLab
The idea is that the resistance of the mosfet goes down when a signal is applied which simulates the short circuit. My concern is that this feels very unconventional.
Is this an acceptable method of doing this? are there more professional methods?
note: it isn't as simple as sending a '0' signal. That often isn't how these systems work.
thanks.
AI: The answer is, it depends.
If the gate drive is floating this will work fine, though note it has a polarity due to the intrinsic diode in the MOSFET.
simulate this circuit – Schematic created using CircuitLab
This however.. will not.
simulate this circuit
If you need to do multiples, you would need a common ground everywhere.
simulate this circuit
A better method would be to use a relay or better still an opto-coupled MOSFET.
The latter is also bi-polar due to the back-to-back MOSFETS which block the diodes. |
H: Is it bad for an RF amplifier to leave it on with no input?
I work in a physics lab where we have some inaccessible experiments. One of them involves an RF power amplifier (a ZHL-32A+ from Minicircuits) driving a 50Ohm load that we can't access, but we can control its signal.
Sometime we have to leave this for long periods (~months) not in use. When we're doing this, is it better for the amplifier's aging to leave it with no input RF or with the normal signal? We don't have the option to turn its power off fully.
AI: These amplifiers (especially from minicircuits) are definitely designed for 24/7 usage throughout years. So, as long as you cool it sufficient (and radiation might be enough, considering it comes in a package including a large heatsink), you should be fine for decades.
If you can control the signal going in: simply don't put in any signal, but e.g. terminate the input with a 50Ω terminator¹. That will minimize power consumption and thus heatup.
the terminator of the passive component type, not of the Sarah Connor type. |
H: Wien Bridge Oscillator
So I built the Wien bridge oscillator without automatic gain control and I am using a preset to tune the circuit instead.
My question is this, so when I reduce the gain of the op-amp to something smaller than 3, I can see the oscillations die out slowly on my oscilloscope. When I turn the preset and increase the gain to maybe 3.2 I still get stable oscillations, but larger Vpp and no clipping. Considering the Barkhausen criterion shouldn't the circuit render unstable, and the oscillations begin to clip?
This only happens when I increase the gain to larger values than 3.4. For a gain approximately equal to 3.3 I get a very weird sine wave almost about to clip. I'm curious to why this behaviour is incremental, I thought for a gain greater than 3, it should automatically clip.
For reference I am using the UA741 and my circuit is configured the same as the picture I included.
Values of capacitors are 10nF and resistors are 1060 ohm to obtain 15kHz oscillations. R4 is equivalent to my preset (20k) and R3 is composed of two resistors in serioes of 20k each.
AI: When I turn the preset and increase the gain to maybe 3.2 I still get
stable oscillations, but larger Vpp and no clipping. Considering the
Barkhausen criterion shouldn't the circuit render unstable, and the
oscillations begin to clip?
Slew rate limiting is something to consider: -
Picture source
If your peak voltage is 10 volts (at 15 kHz) then the maximum rate of change is 0.94 volts per micro second. Given that the 741 self-limits at 0.5 volts per microsecond this is the likely cause of the output amplitude appearing reasonably stable with some distortion. You might see something like this at the output (blue): -
Picture source
As can be seen (in this exaggerated scenario), if the input sine wave (red) increased in amplitude, there would be no increase in the output amplitude. This is a form of output amplitude limiting. In your particular scenario, I suspect that the limiting is only marginal but enough to act as a form of amplitude stabilization.
Reasons not to use a 741 - maybe you have found a good reason to use a 741 op-amp? |
H: cross correlation reverse order
I have a quick question.
I was wondering about the order of cross correlation of two signals.
Suppose there are two correlated signals. \$y(t)\$ and \$e(t)\$.
Does the following expression hold?
\$R_{ye}(-1) = R_{ey}(1)\$
Which is equivalent to:
\$\bar{E}(y(t)e(t+1))=\bar{E}(e(t)y(t-1))\$
Thanks very much in advance,
Mike
AI: Yes you have this property for all cross-correlations as a cross-correlation is a convolution without rotating the second vector. This means if you swap the vectors of your cross-correlation, the result will be mirrored. |
H: Protecting BJT base-emitter junction from breakdown voltage
I was playing with a BJT based circuit and I learned about the breakdown voltage of BE junction.
I came out with a solution of connecting a diode in series, with higher breakdown voltage. But I am not sure if connecting in the bottom and top are both same
where the zener BE is the model of the base-emitter junction.
If I connect the protection diode in the emitter (D2) I will certainly avoid the stress in BE junction. Does it act in same way if I connect the dioe to the base? (D3)?
The bjt has a breakdown of 6V. so if I apply like 12V (limited with a high resistor) I see a voltage of around 7V, which makes sense since 6V is just the minimum specified. The current through the gate is very low, since I work with 12V and limiting resistors of 270k. when I breakdown the junction and 47k as pullup. The BJT in the bench is a BC846ALT1G.
EDIT: since the complete circuit could depends on the collector state, here is a sketch of the circuit:
The emitter of Q2 is the one which I try to connect to 12V (VCC) with 270k, while the collector of Q2 is always connected to 12V. Basically I want to bypass a resistor with a BJT where the OUTPUT goes to another circuitry which uses a pull down of the same size. The load driven by the Q2 emitter is 270k/2 Ohm, since the other pulldown is 270k as well, there is nothing else.
I was trying to understand the situation more deeply in order to apply less changes as possible.
Q1 is kept conducting or open (applying a current limited voltage on base, like 5V or 0V) and works as it is supposed to work.
The reverse junction which I am referring to is on the Q2 BE junction.
AI: As you draw it, there's no difference assuming you've either not connected the BJT's collector or shorted it to the base.
In a real circuit there might be a difference as then the collector might come into play.
So depending on the complete circuit it could make a difference if the extra diode is in series with the base or the emitter.
In most circuits the low base-emitter breakdown voltage is not an issue. In some circuits it can be though. |
H: Techniques for building 'Bed of Nails' testing board
When testing a complete circuit board a 'Bed of Nails' can significantly reduce time and errors.
What are some techniques for making a DIY Bed of Nails?
Specifically, looking for what kinds of materials work best, how to trace the board properly to make the holes in the right place, in other words, it's the little things that experienced people know but for a beginner would be a lifesaver.
AI: Having the board artwork helps, but if you don't, you can use a sacrificial blank PCB as your template.
Fix the blank PCB the appropriate way up, usually bottom side up, to your bed of nails substrate material. The latter needs to be thick enough to provide the mechanical stability. You can even use two layers for the bed of nails substrate, later separated by a gap, and mechanically joined together by the pogo-pins.
You can use good double sided tape to securely adhere the blank board to the substrates so they do not move relative to one another while you drill.
Then, using a drill press, drill holes wherever you need a test pin, through the PCB and on through the substrates. Use the appropriate sized drill bit for the pogo-pins.
You should also drill alignment holes for larger pins in the bed of nails that will mate with whatever mounting holes you have on the PCB. These pins on the bed of nails should be conical at the tips and longer than the pogo-pins so the board lines up BEFORE it makes contact with the test pins. |
H: How to make a PCB
I never made a PCB before, just breadboarding.
And now I have a very simple circuit, but I'm wondering what is the most practical way to convert it to a PCB.
Circuit:
simulate this circuit – Schematic created using CircuitLab
I want to use a small PCB board, 2x8cm like this:
I think the following is something that should work:
TOP
A B C D E F
o o o o o o
V1 VCC X--o o o o o o
o <Res 960-> D
1
o o CH1 SW1_ _
V1 GND X--o o o o o o
o o o o o o
BOTTOM
A B C D E F
o o o o o o
V1 VCC X--o--o o o o o
|
REL VCC x--o X o o X X
REL GND x--o o X--X X--X
|
V1 GND x--o o o o o o
o o o o o o
My questions:
The relay has 3 pins which are spread (two on the left, CH1 in the middle), is it a good practice to keep them together (but at the cost of more soldering or not)?
The Relay CH1 and Switch wires are in the middle of the board (part).... is this 'good practice' or better to always keep them at the side (but again at the cost of more soldering?)
AI: The board you show is basically just something to hold your components in place. Works the same as your breadboard except with solder to make the connections. Electrically the placement of parts is rather irrelevant. So choose a configuration that is easy to use. For example if you put the LED directly next to the button then you will likely cover the LED while operating the button and can't see it. If you put the button right next to the relay it might be hard to reach, better to put it some distance from the relay so it is clear all around.
There is also another variant called a Stripboard that has all holes in one direction connected. You then cut (a 3mm drill nicely does that) the strip where you don't want a connection. With this kind of board you can often place your parts such that you don't need any or far fewer wires. |
H: What is a pin header with a wall on one side called?
What do we call a Pin header that has wall of one side to ensure you don't connect it wrong(Male side) and on female side there is a slot opening for the wall so it sits and fits perfectly?
Sorry I don't have a picture, I have just seen it but don't know what the name is hence can't find to buy.
The one in this pic for SPI and RS232.
AI: A latching pin header is what I think you refer to: - |
H: Transimpedence amplifier output from 0 to 3V
I have this circuit configuration using the Lm324an op amp with a 5V rail (needs to be 5V) an infrared led and a photodiode. At the minute using a using a 1M resistor the output swings to rails when I place the light source closer to the photodiode however I would like the output to vary from 0 to 3V. How can I modify or at to the circuit to achieve this? I am also unsure what values of resistor and capacitance to pick.
AI: TIA low voltage has challenges:
high diode pF at low voltage reverse bias.
poor CM V input range
poor output swing
stray capacitance with 1 to 10M feedback
lots of web designs avoid these constraints
https://www.maximintegrated.com/en/app-notes/index.mvp/id/5129
Bias +in |
H: What could have gone wrong with my TLP222A?
I'm using a TLP222A to switch a 24V load that never pulls more than about 200mA. My circuit looks like this, ignore that the chip name is wrong.
I have 4 of these connected to 4 GPIO pins. 2 of them have, for no reason I can discern, stopped working. They show 1.15V at the input, which to me implies that the diode inside is conducting normally. The GPIO seems fine. But the output is floating, like the chip is broken.
I'm confident that I did not pull more than the on state current of 500mA nor anywhere near the peak 1A. I also used 220ohm resistors to supply 10mA to the diode, which is also well below its maximum rating.
Not really sure what else to look for, here. :/
Edit: as requested, here is a link to one of the industrial LEDs I am driving. This is the load. There are 4 of them, each on separate SSR's.
AI: What is the load you switch?
It's actually just a simple LED (it just accepts industrial voltage -
24V)
No it isn't.
It's an LED module that can run from AC or DC and has in all probability, a bridge rectifier and smoothing capacitor that has an inrush current. The data sheet states this: -
Maximum inrush current max. 500 mA
That is right at the limit of your TLP222A's capabilities and will seriously degrade the life of that product. Toshiba say this: -
Note: Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the absolute
maximum ratings. |
H: 2D DIY capacitive panel
I'm planning on replacing lights with smart bulbs (e.g. Yeelight RGBW) and replacing light switches with capacitive panels connected to Arduinos which will send data to RPi, which will then control the lights.
I want to make the panels by myself, like here. They will contain some round slider for RGB color and sliders for RGB brightness and White brightness, as well as bulb selection and power button.
My question is, can I use single sheet of copper (or tape), with multiple connection points, to make a single panel, where Arduino will calculate the coordinates from the multiple points? It's in case I want to change the layout, the only thing I would need to do is replace one sheet of paper and some layout file for the Pi (it will decide what to send according to the layout).
I've seen some Instructables for single-dimensional sliders, where they connect each end of the slider to a pin, so I think it will be possible.
How many points would be ideal? Could I just triangulate it from 3 values? Or would one for each corner be better? Or even 5 like one in the middle?
Also is the capacitance linear with distance? Is there any formula?
And another question: I have lots of copper tape left from guitar shielding, but it corrodes over time. Will the capacitance change with it corrosion, rendering it useless?
Thank you for all your answers.
AI: My question is, can I use single sheet of copper (or tape), with multiple connection points, to make a single panel, where Arduino will calculate the coordinates from the multiple points?
No. Due to the high conductivity of copper it will not be possible to differentiate between different points on the surface.
It's in case I want to change the layout, the only thing I would need to do is replace one sheet of paper and some layout file for the Pi (it will decide what to send according to the layout).
To do this you would need to create a matrix of pads with sufficient "pixels" for your most demanding application.
I've seen some Instructables for single-dimensional sliders, where they connect each end of the slider to a pin, so I think it will be possible.
I haven't and you haven't provided a link.
How many points would be ideal? Could I just triangulate it from 3 values? Or would one for each corner be better? Or even 5 like one in the middle?
How do you imagine such a scheme would work?
Also is the capacitance linear with distance? Is there any formula?
If you mean with distance along the strip from the connection point then no.
I have lots of copper tape left from guitar shielding, but it corrodes over time. Will the capacitance change with it corrosion, rendering it useless?
The copper oxide layer should be quite thin and should not affect the conductivity of the tape significantly. You can spray it with a protective coating to prevent this. A PCB conformal coating may be suitable as it is designed to protect copper. |
H: What does Pin type I mean on the ESP32 datasheet
On page 3 of the esp32-wroom datasheet (PDF) it shows a series of pins with type "I".
What does pin type I mean? Are these different to the pin type I/O pins? If so, how?
AI: Some pins can be input and output: I/O (or sometimes General Purpose I/O: GPIO).
Some pins can be outputs only: O.
Some pins can be inputs only: I.
Some pins can be power: P (note that some datasheets will differentiate between input power and ground).
And some pins can be not connected: NC. |
H: Are these two transformers the same?
I am wondering if I can use two normal transformers to form a center-tap transformer..
Here's what it looks like:
If I use the right number of turns, would the transformer on the left same as the center-tap transformer on the right? Or how could I make them equivalent?
I am trying to get the left transformer working as the center tap transformer: provide positive and negative voltage at pin 3 and pin 4 with pin 5 connects to ground.
Thanks!
AI: I think the wording of your question is leading some readers astray.
You can indeed use two identical transformers to give the effect of a single centre-tapped transformer. You would connect them like (assuming 120V/12V transformers):
simulate this circuit – Schematic created using CircuitLab
If the full output is zero rather than 24 volts, reverse the secondary connections on one transformer.
You can also buy transformers with dual primaries and dual secondaries - they can be connected as above, or with the primaries in series for 240V input. |
H: How to identify temp setting on a CH-152-35 thermostat
Pictured is a CH-152-35 thermostat. It is similar but not identical to the one described at http://www.wako-clinac.co.jp/product_en/ch-152-35_en/index.html
I don't have a way to heat this thermostat in a controlled fashion until the switch opens- So I cannot determine its temperature setting by experimentation.
There is more information than just the part number printed on the side of it. I am thinking that perhaps the "195" on the second row of text is the temperature rating - but I cannot find anything via Google that takes my idea from a guess to a fact.
Can someone please tell me if that "195" number is indeed the temperature setting for the thermostat and if the "4131" at bottom is useful information?
As a further help, maybe explain if this is standard marking technique for this type of component and where a reference for these markings might live?
AI: Here is an example datasheet for similar thermostats.
You will note that there is not only just a nominal temperature, but the thermostat may be open or close at temperatures beyond the switching region, there is a (usually large) hysteresis which may be above, below or above and below the nominal temperature, and a tolerance. Of course there are electrical and life ratings as well, and usually safety agency approval numbers.
Chances are the second number is the temperature, and the bottom number is a date code, but that's just a (reasonable) guess. |
H: Figuring out wattage
I know I can take volts * amps to figure out watts, but what if the device accepts a range of volts? So if I have a device that takes 100-240 volts, and is 2 amps, what is the wattage being used? Does it change as different volts are use?
AI: If the device includes a switch-mode power supply, the stated current will be drawn at the lowest supply voltage. The device should draw a constant power, so it will draw lower current with higher supply voltages. |
H: Attiny4 - Possible Errata Found With PWM
I have searched the AtTiny data sheet and not found anything about this. I'm experiencing a weird PWM bug. When I expect 100% on I'm getting less. I'm using an inverted PWM scheme, so setting it equal to 0 should be full on, but my scope shows a ~95% on duty pulse.
Below I posted applicable setup code, then the function I call occasionally in my main() to change the PWM rate... When I set the OCR0B=0, I do not get a full on PWM.
I'll also note all other PWM settings appear to work correctly, the duty cycle matches what is expected.
Anyone want to take a look to check I'm sane before I complain to Microchip/Atmel?
//Setup Pins:
DDRB = DDRB | 0b00000010; //set B1 output and B2 to input.
PUEB = PUEB | 0b00000100; //Pullup on B2
//Setup Timer:
//output pin is OC0B (PB1)
//Set PWM Fast Mode 8 Bit, enable output on all PWM pins (only 1 on tiny5).
TCCR0A = 1<<COM0A1 | 1<<COM0B1 | 1<<COM0A0 | 1<<COM0B0 | 1<<WGM01; //COM0A0 COM0B0 set to 1 for inverting PWM.
//Set PWM top [ICR0] to 5bit (this allows effective 31khz pwm)
ICR0 = TOP_PWM; //Set TOP...
//Set PWM Mode Fast 8 bit & No pre-scaler.
TCCR0B = 1<<CS00 | 1<<WGM02 | 1<<WGM03;
OCR0B = TOP_PWM; //Start with 0 output.
//Setup INO0 (External Interrupt):
EICRA = 1<<ISC00 | 1<<ISC01; //Enable rising edge interrupt
EIMSK = 1<<INT0; //Enable INT0
----------------------------------------------------------------
/******************************************
* Function to decide what speed to set.
* NOTE: All alterations to motor speed should
* be done in this function!
* Also note that inverse PWM is used,
* so 0 is full speed, and TOP_PWM is stopped.
******************************************/
void speedLogic()
{
//Speed logic
if (speed_state == 0)
speed = TOP_PWM;//Off
else if (speed_state == 1)
speed = 24; //Slow
else if (speed_state == 2)
speed = 16; //Med
else if (speed_state == 3)
speed = 0; //Fast (3=91% Otherwise 0=100%)
else
speed = TOP_PWM;
//Set PWM Reg
OCR0B = speed;
//Increment State Variable
speed_state++;
if (speed_state > 3)
speed_state = 0;
}
AI: I believe, it is a feature not a bug. Citing from the datasheet (page 94):
The extreme values for the OCR0x registers represents special cases
when generating a PWM waveform output in the Fast PWM mode. If the
OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow
spike for each TOP+1 timer clock cycle. Setting the OCR0x equal to TOP
will result in a constant high or low output (depending on the
polarity of the output which is controlled by COM0x[1:0]).
This describes your observation pretty well. With 5 bit PWM (32 steps, right?) the duty cycle should be 97 % (not 95 %), but it is probably good enough for approximately. |
H: RC Op-Amp Circuit Analysis
I am trying to calculate the gain Vout/Vin of the circuit below. I'm not really sure where to start, can anybody help?
AI: Assume that:
no current flows into the input of the opamp
the input voltages of the opamp are the same
Then write down and solve the Kirchoff equations. |
H: How much electricity does a 1 GW plant actually produce if the plant's efficiency is 20%?
I'm trying to see what percentage of total electricity demand will be met by solar power in some year x. Let's say I have data saying that the total electricity demand in country A is 1000 billion units (BU) in 2025. Let's also say that the installed solar power capacity in that country in 2025 is 200 GW.
How much electricity will these power plants with a cumulative capacity of 200 GW produce? I also have information that solar power plants in these countries run with an efficiency of 20%, but I'm just confused. What does a 200 GW power plant actually mean (how much electricity will it produce, say, in an hour?) and if the efficiency is 20%, how does it change my analysis?
AI: A power plant rated at 1GW can produce 1GW of power, at the rated conditions.
If it has an efficiency of 20%, then it will be consuming 5GW of energy in some form to do that.
If the power plant is (say) thermal steam, then the calculations are fairly easy, because we can assume that it can do this continuously, as long as fuel arrives. It will generate 1GWh of energy in 1 hour. Note that 20% efficiency is pretty poor, archaic even, for a combustion based plant, but might be reasonable for geothermal (low temperature) sources.
If the power plant is solar, then
(A) it's weather dependent (don't work well in cloudy weather)
(B) time of day dependent (don't work as well when the sun is low in the sky) and
(C) the efficiency is less relevant than for fuel burning plant, as it gets whatever sun it does for free all the time (subject to a and b above), though cost of plant, installation and real estate to deploy it will increase with lower intercept efficiency, so that will continue to be improved by manufacturers
We come back to the rating conditions. Is that 1GW at solar max, best time of day? Or is it average between the hours of (say) 10am and 4pm? For what the 1GW means, you will need to read the fine print for what it really means.
Once you know what it means, as a function of time of day, and as a function of seasonal weather, then you can integrate the amount of energy that the solar plant will produce over a day, or a year. |
H: 2 pole RC instead of LC filter in Buck
What if I use second order RC filter instead of LC filter in Buck, even it gives roll-off of 40db/decade.
Why is LC preferred?
AI: Inductors and capacitors give and take reactive power. This means that they charge and discharge power.
Resistors consume real power, the only way of getting that real power back is by converting the dissipated heat back into electricity, which is not realistic.
Inductors stores its energy in its magnetic field.
The energy in the magnetic field comes back in the form of electricity without any extra fuzz.
Capacitors stores its energy in its electric field.
The energy in the electric field comes back in the form of electricity without any extra fuzz.
Resistors waste energy in itself by heating up.
The energy in the resistor in the form of heat is difficult to turn back into electricity. Most of the heat will heat the air around it through convection. Using a resistor is simply too inefficient.
So if you want a filter that is efficient, then you don't want heat, heat is the result of energy being wasted. Instead of wasting energy, it can instead go to the load, which is your ultimate goal.
Edit:
Compare two LP filters. One RC and one LC based. The load will be entirely resistive.
Link to simulation.
Upper graph's are the power consumed by each component in the LC based filter.
Bottom graph's are the power consumed by each component in the RC based filter.
The L and C graph's are entirely reactive while the R graph's are entirely real.
Notice how the average power in the L and C in the LC filter is 0. No energy is lost in the form of heat. The CLK is a square wave that goes from 0 to 5 V and has a duty cycle of 50%. The 1 kΩ load gets all the energy which results in 2.5 V across the load.
Notice how the average power in the R in the RC filter is not 0. It is wasting it in the form of heat. And look at the 1 kΩ load, it is not at 2.5 V, it is at 2.3 V. The 0.2 V lost is due to the R in the RC filter, \$P=\frac{V^2}{R}\$.
Something else that might be interesting to see is that the amplitude of the RC filter's power is much larger than the ones for LC, so the LC filter is much "kinder" to its power supply. It causes less noise than the RC filter. |
H: What does "LB" out mean in a DC-DC buck converter?
Teacher gave me a schematic,and it includes a DC/DC buck converter with "LB" input and output,but i have no idea what the "LB" is,so i want to ask that does someone know what may the "LB" be?
AI: "LB" stands for "low battery".
They are the input and output pins for a comparator and voltage reference (internal to the device) which can be wired to detect a low battery voltage and provide a shutdown signal.
For example, see this Linear Technology datasheet, page 4:
http://cds.linear.com/docs/en/datasheet/126535fb.pdf
"LBOUT (Pin 3): Open-Drain Output of the Low-Battery
Comparator. This pin will sink current when Pin 4 (LBIN)
goes below 1.25V. During shutdown, this pin is high
impedance.
LBIN (Pin 4): The (–) Input of the Low-Battery Comparator.
The (+) input is connected to a reference voltage of 1.25V." |
H: Single board computer (SBC) with industrial grade
I was using single board computer (Raspberry Pi, Beaglebone) to develop prototypes. A new requirement is that the prototype should satisfy "industrial grade" with regarding to (for example):
Temperature (e.g. -40 to 85 degree)
humidity
life cycle (e.g. 10 years)
mean time between failure (MTBF) (e.g. > 80,000 ~ 100,000 hours)
For another example, I find one of the issue is: many SBC uses SD card to load OS. I guess most SD card cannot run for years without stopping.
Meanwhile, the SBC should also support similar functionalities (e.g. Linux OS, required physical interfaces, enough memory). (I guess this is not a potential problem).
How can I find such industrial grade SBCs? Many commercial products (e.g. firewall hardware) can satisfy industrial grade. Where do their SBCs come from?
AI: The rating of a product for environmental conditions is more than the sum of its components.
So, yes, you sure don't want to use an SBC with the cheapest allwinner SoC but rather something based on chips that are specified for a larger temperature range(look at the SoCs of eg. NXP and TI), but the rating of your overall product stems from your product design - for example, a chip that is solidly connected thermally to the case might happily work at 65°C environment temperature, because it won't get much warmer when cooling is good.
To get a device certified for industrial environmental conditions, you need to do the whole-system testing of the complete device; looking at its components won't get you far. |
H: Relay with notifications circuit
(see update at the end)
This is a continuation of my previous question about a relay: Question
What I want is a notification LED for both power and if a switch is on, which controls the relay.
Below is the circuit I have in mind:
simulate this circuit – Schematic created using CircuitLab
Below are my calculations and reasons.
S1: Adapter 9V DC
D1: Voltage reducer, 1N4148, Vfw = 0.7 V
D2: Power indicator, Blue 3mm, Vfw 2.8-3.2 V. 5 mA is enough for a LED indicator.
R1: Resistor for power voltage indicator LED. V = I*R. R = V / I = (9 – 0.7 – 2.8) / 0.005 = 1,100 R -> 1,000 R … A will be V / R = (9 – 0.7 – 2.8) / 1000 = 5.5 mA.
For minimum: A will be V / R = (9 – 0.7 – 3.2) / 1000 = 5,1 mA.
Relay_vcc will be 9 – 0.7 – 2.8 = 5.5 V, which is in spec (5 V , 120% is 6 V). The minimum value is 9 – 0.7 – 3.2 = 5.1 V
D3: Switch indicator LED. Should be around 5 mA. Green 3mm, VFw = 1.8-2.2 V
R3: Resistor for switch indicator LED. V = I * R. R = V / I = (9 – 0.7 – 1.8) / 0.005 = 6.5 / 0.005 = 1300 R -> 1200 R, resulting in I = V / R = 6.5 / 1200 = 5.4 mA. In case of Vfw = 2.2 : V / R = (9 – 0.7 – 2.2) / 1200 = 5.1 mA
I'm wondering mostly if I miss something, and if my values are 'ok'.
I hope this is not a too broad question, the reason I ask is since in my previous question I forgot to add the extra diode, so supplying around 6-7 V to the VCC (since I missed the 1N4148 diode).
UPDATE
I found out:
CH1 does not need has requirement regarding current, in examples from Arduino there is not a resistor between a GPIO and CH1 (or IN).
VCC probably uses the nominal current for the coil, which is about 75 mA.
However, my main question is:
Since VCC of the relay needs 75 mA, and D2 will burn when 75 mA is applied, but also D2 is used as voltage limiter, what should I do?
I read in other threads that a resistor divider is not good for relays, and the only other way I can think of is adding 5 or 6 1N4148 diodes, reducing the voltage to 9 - (5 * 0.7) = 5.5 V.
(Btw, the best solution is to use a 9 V relay module, or use 5 V input. Since I don't have the first one, I am going to use a 5V cable and cut it or check for some bracket).
AI: Step back to the actual requirements. Apparently you have a relay module that takes power, ground, and a control signal. You will control the module with a pushbutton. You want two indicator LEDs. One for power applied to the module, and one to indicate the relay is activated. Apparently the relay module requires 5 V power and signal, although that is not clear. The available power is 9 V.
Here is a solution:
IC1 makes 5 V from the input voltage. This always powers the relay module.
The 5 V also always lights LED D1. If D1 is a typical green LED with 2.1 V forward drop, then the current thru it will be about 5 mA. That's plenty good enough for most modern LEDs used as indicators indoors.
R2 and D2 work the same way, but are only powered when the pushbutton SW1 is pressed. Pressing the pushbutton also drives the control input to the relay module high. R3 makes sure the control input is low when the pushbutton is off.
While this does what it appears you want, the whole thing seems rather silly. If you want to control a relay from a pushbutton, just put the pushbutton in series with the relay coil. You can connect a LED to ground both before and after the pushbutton to indicate power and relay on. There is no need for a relay "module". |
H: Using an NPN tranistor as a switch for two bipolar stepper motors
this is my first electronics project which requires controlling 2 different stepper motors with two motor drivers (L293D). I have found that the number of GPIO pins on my microcontroller (ESP8266) is 9. However, i require 10. I have found on the arduino website a method of using a transistors as switches as shown below which would reduce the amount of pins needed on the microcontroller.
My question is what do the wires control 1 and 2 lead to? is it just back to the GPIO pins of the microcontroller and i code for when the transistors turn on and off, or is there another piece of equipment in between? Also, where do I start from when choose what resistors and transistors to use? Thanks
AI: In the data sheet you can see the following extract: -
It shows inverters (highlighted in green by me) doing exactly the same as the transistors in your circuit. There are extra inverters also shown but these can be presumed to indicate that the control A and control B signal sources are from a logic device.
My question is what do the wires control 1 and 2 lead to? is it just
back to the GPIO pins of the microcontroller and i code for when the
transistors turn on and off, or is there another piece of equipment in
between?
They are fed from your GPIO pins and you code appropriately. Although the extract shows extra inverters, these are not needed and you can directly drive from your GPIO pins if they produce a logic 1 level in excess of 2.3 volts.
what resistors and transistors to use?
I'd use inverters (74HCT types) and not transistors but if you are keen to use transistors virtually any common transistor will do. In fact I can't think of one that wouldn't work OK. The resistor values shown in your picture are appropriate. |
H: How do manufacturers limit bandwidth in oscilloscopes?
I would like to know how do manufacturers limit the bandwidth through software options in oscilloscopes? If i have a MSO with 1GS/s, but e.g. just have 70Mhz out of possible 200Mhz (via software option), do the digital channels sample at 1GS/s or are they as well slowed down? I always read of bandwidth upgrades, but the sample rate seems not to be affected. Is this correct? And how do manufacturers limit the bandwidth? Just by not enabling the necessary horizontal scale or how does it work?
Thank you!
AI: You should realize that sample rate (1 GS/s) and Bandwidth (70 MHz) are different things!!!
They are related in that a certain sample rate dictates the maximum bandwidth of the signals which can be sampled accurately. This is set by the Nyquist frequency
The Bandwidth of the oscilloscope is most often limited in the frontend of the oscilloscope. The frontend is the input amplifier including protection circuits and range switching (which changes the voltage gain of the frontend). There might also be an anti-aliasing filter (a low-pass filter) present.
On way to make the frontend's Bandwidth changeable by software is by simply switching on/off a capacitor. This is done in the Rigol DS1054Z as shown by Dave from the EEVBlog in this video. That capacitor can simply be part of an RC Lowpass filter (the anti aliasing filter!) which sets the Bandwidth.
It is theoretically possible to (also) limit the sample rate and/or do post-processing to limit the bandwidth but this can result in aliasing effects and requires processing power. Switching a capacitor is much, much simpler. Also, that would limit the oscilloscope's bandwidth in the same way as it always has in analog oscilloscopes. You can view a 100 MHz signal on a 70 MHz oscilloscope but the 100 MHz will be attenuated. So you might measure 1 Vpp while the signal is really 1.5 Vpp for example. |
H: TP4056 Lithium Charger cut off voltage
This module that I got from ebay
has a cut-off voltage of 2.5V which is way too low. At that point your Lipo is probably dead. Anyone succeeded in increasing this to higher voltage? I would like to have it at 3.3V .
AI: On many of these typical lipo chargers the small 6 pin chip is the over/under protection component. If that part is a DW01 (as it looks to be), then all of the parameters are preset internally.
Even if you added a resistive divider to the sense pin you would be altering both the overcharge and undercharge values.
Here is the data sheet for the DW01 chip: http://www.ic-fortune.com/upload/Download/DW01x-DS-17_EN_53550.pdf
So if this does not match your requirements you need to buy a new board and/or try returning the original one. |
H: Capacitor charging not working according to t = rc
I have researched about capacitor charging time, with its charge being at 63% after 1 time constant, being t = RC. I am trying to repeat this by myself, using a 16V 1000µF capacitor, a 1KΩ resistor, and a constant power supply (~7.3 volts, ~1.9 milliamps) from a solar panel, which, as I understand capacitor charging (I may be totally wrong about this, if so please correct me) one time constant should be equal to t = RC = (1KΩ)(1000µF)= 1 second.
Theoretically, after 1 second, the capacitor should be at 63% of its capacity. For it to be at 99% of its capacity, 5 time constants must pass by. I tried this, and I waited for 5 seconds, disconnected the capacitor from the solar panel and resistor, and using a multimeter measured the capacitor's voltage, which didn't even reach 1.5 volts at any of the many times I tried.
I don't understand it, is it that the way I am trying to find the charging time is wrong, as a consequence of informing myself totally wrongly, or that the capacitor that I am using is defective?
AI: Your understanding of the capacitor is correct, your understanding of the power supply is wrong.
At initial connection the cap will try to draw 7.3mA through that 1K resistor assuming the voltage is a solid 7.3V.
Unfortunately, the solar panel can only supply 1.9mA.
On it's own, at that level the capacitor will take a lot longer to charge. (>28S)
However, what also happens is the voltage at the panel will fall since it is being over-loaded. That further reduces the charge current extending the time even longer.
In other words, basically, the solar panel is presenting a large terminal resistance at the currents you are demanding, which affects the time constant.
How you are illuminating the solar panel also matters. Depending on the type of lamp, there may be a significant AC component to the light. That can cause the solar panel to be "dark" for a fraction of the cycle, at which time, it acts as a diode shorting out your circuit. |
H: LVDS signal to FPGA
I need to receive 42 pairs of LVDS signals to a FPGA.
All i want is that the FPGA converts the differential pairs in normal std_logic signals.
And i need to choose a xilinx FPGA with enough pins that support LVDS signaling.
I'm a bit confused and don't know which kind of FPGA to choose depending on the standards I/O LVDS or LVDS_25
I don't really know how the standards work or how do they convert the signals
Any help would be much appreciated
Thank you
AI: LVDS and LVDS_25 are most likely electrically the same. I don't know which family you're looking at, but in the Spartan-6 there are also two LVDS standards, LVDS_25 and LVDS_33. They are electrically the same (see below from DS162), so they will work the same as far as interfacing with other LVDS parts. The distinction is that you use LVDS_33 when your bank voltage is 3.3V and LVDS_25 for 2.5V.
You can confirm this by looking at the input and output levels in the datasheet of the part you're evaluating. |
H: What is the recommended fully-charged voltage for NiMH AA batteries?
I have done research on different batteries and cannot find a maximum OR minimum voltage to keep NiMH AA batteries within. It seems that typically battery chargers will measure the negative voltage CHANGE or the temperature, but are not designed to hit a certain voltage limit.
I have seen some claim that 1.5V is a good upper limit and 0.9V a good lower limit, but my question essentially boils down to:
What do most electronics want and expect from the AA batteries they run on?
For reference, here is the datasheet I found for Eneloop AAs
AI: I have done research on different batteries and cannot find a maximum
OR minimum voltage to keep NiMH AA batteries within.
Well the very first hit when googling "NiMH AA battery data sheet" gave me this information: -
If different batteries are specified at different levels then there is no generic upper and lower limit.
What do most electronics want and expect from the AA batteries they
run on?
Most people regard the voltage output as being 1.2 volts nominally. |
H: LED light intensity drop using 200k range resistors.
I recently had an experiment in school where I used resistors that were 130k, 140k, 150k, 160k and 170k ohm to dim a red LED. The light intensity was then measured with a Pasco light sensor. The circuit was powered by a 9v battery.
I was wondering, how could I predict how much the light intensity will drop as I change the resistors out?
Thanks in advance!
AI: By consulting the LED's datasheet's forward current/voltage and luminous intensity/forward current curves:
Source: https://cdn-shop.adafruit.com/datasheets/WP7113SRD-D.pdf
Now, by calculating the current through the LED:
I = ( 9V - V(LED)) / R
You can then look up that current on the luminous intensity chart to get the luminous intensity as a percentage of the value given for 20 mA; on this datasheet it is given as 250 mcd. |
H: Putting two sallen key filters in series
Can I put two sallen key filters in series without putting a buffer in between them (in order to analyse it mathematically correct)?
I know that when the output impedance of the first sallen key filter is much lower than the input impedance of the first sallen key filter.
AI: The output impedance of a Sallen-Key filter is zero, with an ideal op-amp of course, and very close to zero with a real op-amp. One stage can drive another stage without interaction.
Cascading Sallen-Key stages is a standard way to build up a higher order filter. |
H: Oscilloscope displays the derivative of the signal instead of the actual signal
I have a Tektronix TDS 2024B Oscilloscope. For some reason it displays the derivative of the signal. It cannot be the "Math" feature as it only computes addition or subtraction of 2 signals supplied through CH1 and CH2. I even tried to restore the factory settings but it didn't solve the issue either.
Do you have any suggestions on how to make it display the signal itself instead of the derivative?
The signal I am supplying: (A square wave with 25% duty cycle.)
The measured signal:
As suggested by Spehro Pefhany I connected the probe to probe comp and this is what I got:
Then I did the same with a different probe, and this is what I got:
I guess this result validates your hypothesis that the initial probe/cable is broken.
Andre, this is a picture of the initial probe I was using. I am not sure if it has any shielding at all as it is thinner than a regular coaxial cable. Let me know what you think.
AI: Maybe your probe or BNC cable is broken.
Try connecting it to the probe comp input and see what you get. (Connect both the probe and the ground wire to the two lugs). Also try channels 2, 3 or 4 rather than just channel 1.
BTW, the TPS2024 (not TDS2024, which is the one you have) has four completely isolated channels. As such you must connect the ground on each channel you are using to the appropriate spot. Otherwise you could see something much like that. If you are used to 'scopes with a common ground/earth this might be confusing at first, but it is a heck of a useful (and a bit expensive) feature.
Edit: For those who think it possible that setting this scope to AC coupling could produce this waveform, it's true if you don't look at the numbers involved, but not at 250usec/cm sweep. Here is the waveform with AC coupling:
You can see a bit of slope towards zero on the flat portions of the waveform, and it is centered so that the average is 0V, but otherwise it looks pretty much as the DC-coupled waveform would look. |
H: Linear and non-linear attenuator
[edit 3/2/18] There are problems with the title and wording of this question. I would edit, but to do so would alter the relationship between the question and the answer that I accepted. So, I have re-asked the question in a way that better describes what I was trying to learn. You can find the new version of this question here.
This is a newbie question. The manufacturer's data sheet for a material shows its attenuation curve over a range of frequencies. Does that curve represent the material's linearity of its attenuation? Or, does linearity mean that if the input waveform is sinusoidal, the attenuated signal will also be sinusoidal? Or, does it mean something else?
My understanding from the answer to a previous question is that high field strength can cause an attenuator to become non-linear, so that it attenuates more or less at a particular frequency, depending on the detail of the non-linearity. What does this mean? Is it that 1) the manufacturer's attenuation curve is altered, so that attenuation is enhanced or diminished at certain frequencies relative to when it's operating linearly, or 2) e.g., an input sine wave is output as a square wave, or 3) an input signal at one frequency is output at a different frequency, or 4) something else?
AI: You are mistaking "linear" with "flat over frequency". The "attenuation vs frequency" curve has nothing to do with linearity.
Mathematically, "linearity" means that when if input signal A produces output signal B, then n x A produces n x B. That is, the output is proportional to the input.
Linearity DOES mean that if the input signal is sinusoidal, the output signal will also be sinusoidal. But it also means more than than - if the input signal is a superposition of sinusoidal components (which any periodic signal is), then the output signal will be a superposition of sinusoidal components at the same frequencies. A linear circuit will never output a signal component at a frequency which was not present at the input.
However, linearity does NOT imply that each frequency will be affected the same. For example, an attenuator could reduce the 1GHz component by 3dB and the 2GHz component by 4dB, and still be linear.
So, what happens when your material gets hit with a high enough power wave that it goes nonlinear? Depends on the material and how it's being used, but in general, the attenuation curves (which are presumably listed in dB) will change. Without knowing the specific material properties, I can't say for sure whether the attenuation will increase or decrease.
In a nonlinear mode, it is possible for an input signal at one frequency to produce output signals at other frequencies - specifically, integer multiples of the original frequency. In some circuits, it is possible this will mean a sinusoidal input producing a square wave output.
If the input signal is composed of two or more frequencies (f1 and f2), then the output signal of a nonlinear circuit can include any frequency of the form (n x f1) +/- (m x f2) (for integer m and n). Researching "mixing products" for more info.
P.S. - the amount of power required to make a bulk material go nonlinear is probably pretty high. Typically, for most every day applications it's safe to assume materials are linear - although of course every project is different and I have no idea what either your material or your application is. |
H: LC-Filter for DPS5005 power supply
I bought a DPS5005 unit in order to setup a cheap power supply. The module seems to be quite popular and has often been described as remarkably good for its low price of about 35 $. However, even under load (2 A flowing through a 0.1 Ohm resistor) I get short 450 mV peaks at a frequency of 35 kHz. These are independent of the power supply that is used as source for the DPS5005.
To smooth the output, I plan to implement an LC-Filter. The formula to compute the cutoff frequency is
$$f=\frac{1}{2 \pi \sqrt{LC}}$$
with the inductance L of the coil and the capacitance C of the capacitor.
As cutoff frequency, I'd like to have something in the range of 10 kHz. According to the formula, I could realize this for example using a 47 uH inductor and a 60 uF capacitor.
Is it sufficient to simply use an electrolytic capacitor? Or should I use a combination of a small ceramic and a big electrolytic capacitor? And since electrolytic capacitors in the mF-range are available, is a bigger capacitance a better choice?
Any tips/hints/empirical values?
Edit: Here are two plots of my measurement:
The first shows an overview. The sample frequency is too low - therefore the variance in the amplitude of the spikes. But I hope it gives an idea of the problem.
The second is a closeup of one of the spikes. I marked the data points by dots.
Edit: According to the post of EE_socal, I have modified the probing setup and indeed, the peaks are much lower. Here is an image of the setup:
And these are the new plots of the signal:
Edit: EE_socal suggested in his answer to add a ferrite bead, bulk capacitor, and small ceramic capacitor. Following this advice, I tested a 80 Ohm @ 10 Mhz, 110 Ohm @ 25 Mhz ferrite bead together with electrolytic 47uF and ceramic 0.1uF capacitors. The peaks have vanished leaving a peak-to-peak amplitude of <0.1 V, which is sufficient for my requirements.
Here is a plot of the filtered supply voltage:
AI: The best way to probe would be with a very short ground spring tip, something like this:
Let's assume the noise spike you measured is really there or at least some it is there. The width is very short on the order of nano-sec. This is typical of noise originating from very fast edges on the switch node and coupling to the output through the parasitic capacitance of the inductor. The best filter for this is a ceramic capacitor and ferrite bead as they are effective at these frequencies and the ferrite bead is largely resistive which reduces the chance of ringing. However I don't know how you plan to add such a filter to the off the shelf power supply you are using. |
H: VFD? to power aircraft non-motor/inductive load OR power conversion
QUESTION: Is it plausible to test power, out of aircraft, a mostly solid state device ie Microwave Oven? Can a VFD be programmed to run with inverter circuits. If so, 3 phase + ground output of VFD is 4 wire load compatable? PHOT0 1 vfd
POWER SOURCE, VFD = 1.5kw 1ph to 3ph, Chinese manual only, seller mistake
LOAD, Aircraft Microwave Oven = 1.5kw 115v 4 wire 3ph 380-600Hz power requirement
BUDGET $1000~ yes you can spend $20,000 for a ground support generator
Load design, aircraft microwaves have a entirely different primary power design.
3 phase 400hz power is fed thru a RFI line filter for each phase. This power then goes thru power conversion mosfet circuits and AC to DC inverters. Anything to avoid using a transformer. Only one conventional transformer is used to power the magnatron filament, not counting the switching xformers on the boards.
UPDATE METHOD to power 115vac @400hz 1500va Oven
Super advice. Yes the maximum power consumption is 1500W, the intent was to power up and check the brains of the unit with the 1500va VFD and not cook. I have now repaired a 1968 Unitron frequency converter. Producing 2000vA 3ph-200ac in /2 ph-115 out @400hz. The QUESTION now is the oven requires 3ph at 115v, I have only produced the 400hz variable. Im already fooling the frequency converter with "fake" 3ph (3phase motor/cap running off 1ph 220v). Based on the schematic attached, how would it be possible to make "fake" 115vac power?
This is the 3ph Power management schematic.
AI: This is very unlikely to work well.
Figure 1. PWM approximation to a sine wave. Source: VFDS.
VFDs use PWM from their internal DC bus which in turn is full-wave mains and will be close to \$ \sqrt 2 V_{RMS} \$. A motor can tolerate this as its inductance will act as a low-pass filter. Your microwave oven, more than likely, will not tolerate it.
You probably require a 400 Hz sine inverter for the task. |
H: Parallel a diode to solid state relay load is a short circuit?
I'm trying to use a solid state relay control a 12v dc air pump, so I was reading the "Solid State Relays Common Precautions"(like below).
http://omronfs.omron.com/en_US/ecb/products/pdf/precautions_ssr.pdf
When I read the paragraph shown in the screen, I'm wondering if I parallel a diode to the load, I'm I making a short circuit since there won't be much resistance in the dioade so the current will just bypass the load and go through the dioade?
AI: You need to connect the diode the correct way (reverse biased, as shown), otherwise it will indeed conduct when the SSR turns on and likely destroy the SSR and quite possibly the diode.
When connected as shown, it is reverse biased until the SSR turns off, upon which the inductive load will cause the diode to become briefly forward biased until the energy in the magnetic field is absorbed by the coil resistance and diode forward drop. Otherwise the voltage across the load would increase to potentially damaging (to the SSR) levels.
Consider the below schematic- the switches represent the SSR and the stuff in the boxes represents your pump motor.
simulate this circuit – Schematic created using CircuitLab
The switches open at t=0 and current is 1A through each circuit at that time. As you can see in the below simulation, the voltage across the switches increases to a bit over 12V and then drops back to 12V when the diode stops conducting about 2.5ms later.
If I remove D2, the difference is dramatic:
The voltage across SW1 spikes to about 900V, before dropping back. |
H: Using Extra-Wide Traces
I am currently laying out the board for an audio amplifier I am working on. The power requirements aren't very high - there won't be much more than 500mA flowing through any given trace. However, I have ample space on my board, so I was thinking about using wide rectangular fills (40-50mil wide), like the following:
Having wider traces minimizes resistance, an in addition to being much wider than they need to be, I find a layout like this to be aesthetically pleasing. However, could any issues arise from routing like this instead of using thinner traces? In other words, is there a reason why I should only make traces as wide as they need to be?
AI: Usually that's just fine.
The parasitic capacitance to your ground plane will be a lot higher. In many cases that won't cause any problems (and may be better in the case of supply rails) but occasionally it can cause issues such as oscillation.
It can also cause excessive unwanted coupling affecting whatever is on the other side of the PCB if the voltage changes quickly on the trace. |
H: Confusion about a step down transformer use
This might sound a dumb question but I couldn't find an answer myself. I have come across this transformer. It has selectable I guess primary 215V to 400V, and a fixed secondary 115V. I know that nominal mains is around 115V in the US.
I first thought It is to step down lets say European nominal mains to US standard 115V. But then I though in what scenario can this be used. Theres is an ocean between two continents.
Can you give me a practical example/reason when could this be beneficial to use in the US?
AI: In the USA there are various common AC (60 Hz) voltages distributed to residences and business. These voltages are typically either three-phase (industrial & commercial customers) or single-phase (residential customers and small businesses). The single-phase residential is nominally 230 volts line to line, and 115 volts neutral-ground to each line. This is fairly universal across the USA for residences.
In the business and industrial sector there are many more types of distributed voltages, most of which are three-phase. Some common voltages are 240 and 440. (these are all 60 cycle, and expressed as RMS voltages) There are other higher voltages distributed to industrial customers, again typically three-phase.
So, to answer your question, when you need to power a 115 volt device, and all that is available is 220 or 440, this is one situation where the transformer you reference would come into play.
In general, a 50 Hz transformer can be used with 60 Hz power, but a 60 Hz cannot be used with 50 Hz power. So, that's another factor that might come into play if you wanted to use an "American" transformer in Europe. |
H: Read and write simultaneously from different indices of an associative array in system verilog
Is it possible to read and write simultaneously (In parallel) from different indices of an associative array in System Verilog ?
AI: There's nothing to stop you from doing that. But like any variable you read and write from different processes, it's up to to you to make sure the data is valid and prevent race conditions. |
H: Questions About Charging Lithum Ion Batteries
I have a few questions about charging Lithium Ion Batteries aka a collection of cells...im learnin...lol
1) I am looking to setup 14x18650 cells to make a 51.8v module in series. I know I need its best to use a BMS (purchased). I also got a smart charger that is designed to charge 14s modules. Can I use both at the same time? Or will they interfere with each other?
2) The charger in question is 52v but it is also rated at 3A. Am I missing something. I understand that to charge a 14s you would basically do 4.2v x 14 = 58.8v. But I thought in this case you would only charge it at standard amps of in this case 2.2A / 2 = 1A? Wont 3 amps be way over?
This project is for learning mostly so I am not planning to use this in real "production" capacity.
Thank you for your assistance!
AI: Q1) Can you use BMS and charger at the same time.
Well it is not clear what you mean by a smart charger. If it is a bulk charger (i.e. just two wires connecting to the battery's bulk voltage) then you for sure want to use the charger in series with the BMS. The BMS is what is going to open circuit the charging line when one of the cells reaches 4.2v.
If it is a balance charger, (i.e. in addition to the two bulk wires there are a bunch of small wires/balance leads also connecting the charger to the battery) well you can still charge it with the BMS on there. You will need redundant balance leads though, or partially disconnect the BMS. But I am betting you have just a regular bulk charger.
Q2. Charger specs.
The charger is likely speced for a 52v battery. If you test the output it will probably go up to 58.8 ish volts. That would just be the nominal rating most likely.
Regarding the current: If the charger is rated to deliver 3amps, and you are hooking it up to a pack that is 14s x 1p (one cell in parallel only) then you will but charging the cells too fast really. The cells might be able to take it (check the datasheet for max charging rate) but there is a direct relationship between rate of charge and rate of wear on the battery. If you charge that fast, even if your battery can take it without failing you can expect your batteries to wear out quicker. |
H: Triangular Symbol in a A circuit
What is the meaning of the triangle above with "5v" written next to it? is that a ground symbol or an input voltage symbol?
AI: Here's some hints to what it may be
It says 5 V, it does not say \$V_{in}\$
it is a constant 5 V |
H: I have a heater in a 3 phase (415V AC, 230V per phase) timber kiln drawing 43A per phase. How many kW is this?
I'm new to this subject, but I want to learn. I have an electric heated timber kiln and I want to replace the electric heater with an equivalent rated oil burner, therefore I need to calculate the output power of the heater from the available information. The electric heater has an input of 3 phase 415V AC, 230V per phase. The amps per phase when the heater is running is 43A.
Is the power = 230V x 43A x 3 = 29670W ?
AI: Your calculation is correct. You have 30 kW of electrical heating.
For rough oil calculation you can work on a figure of 10 kWh heating per litre of oil. For 30 kW oil heating you will burn 3 L/hour assuming 100% of heat gets into the kiln. De-rate for flue losses. 85 to 90% is probably a good value for a condensing boiler.
But why do you want to burn non-renewable oil? Shouldn't you be burning renewable timber? Timber will give you about 4 to 4.5 kWh/kg and you're already in that business. |
H: How to redesign the circuit such that the switching threshold is VDD/2.
he switching threshold is the input voltage where the output crosses VDD/2. I want to redesign the circuit such that the witching threshold is VDD/2.
AI: Design each to have the same Vgs(th) at 1.5V and similar RdsOn (although Nch tends to be lower. (Vt is 1.5 for CD4000 Logic I recall)
Verify by measuring input voltage and supply current and self bias with a 10k negative feedback R , It can be 10M but then DMM will load it.
Then verify transfer function with and without load and see the change.
/tinyurl.com/y7zmjpsw or
/tinyurl.com/y9yrywqn |
H: Circuit with Zener-Diode not working (simulation do)
Hello,
I have the circuit shown above. Its made to measure analogue voltages up to 10V and converting currents up to 20mA to a voltage output.
10V or 20mA = ~3.3V output
Now I want to test the voltage measurement functionality:
Vgate = 0V
V_I_IN = 0V to 10V
The Zener Diode has a nominal Vz=3.6V
The output voltage is linear up to 4V Input, if I go higher the output voltage rises slowly.
Voltage measured at Vgate=0V
at J7 = 0V
There are no mistakes in the pcb layout, checked it very often.
Datasheet Zener
What could be the error?
Here is the simulation result:
AI: Your mistake is in understanding how a zener diode works. It just doesn't turn into a clamp at 3.6 volts and below this voltage looks like an open circuit.
If you read the data sheet you will see that this zener (MMBZ5227) with a reverse voltage of 1 volt applied will take a current of 15 uA. Now imagine what happens as you approach the zener voltage (where it is taking 20 mA). The 15 uA might double or quadruple at 2 volts and this current flows through the 100 k resistor and produces an error voltage. As you get higher in voltage this current rapidly increases towards the 20 mA current.
Picture source.
If you look at the knee point in the above picture you can see that current is conducting at lower voltages. This has the effect of lowering the 49.9k resistor value as applied voltage is increased. |
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