text stringlengths 83 79.5k |
|---|
H: From delay to distance?
I need to estimate the distance of a link having only delay values. How can I do that? I need to estimate this distance for ethernet and optical fiber links. I thought of doing it using the propagation speed over ethernet and fiber, but I don't know if it's correct and also I can't find those values anywhere.
For instance, one of my values is 0.7 ms. How much that corresponds (in length) in case of shared ethernet connection, and in case of optical fiber?
Any thoughts?
Thanks
AI: The speed of light in vacuum is about 0.3 m/ns, so in your 700 us delay, that's a distance of 700k * 0.3 = 210 km.
The speed of light in plastic insulated ethernet is 60-70% of that, and is similar for typical optical fibre, so 140 km.
Does your 0.7 ms include formatting and processing delays in the ethernet interfaces? That needs to be deducted from the calculated distance as well. |
H: How can I correct these Verilog syntax and declaration errors?
I am currently working on an Arduino to NIOS II Compiler that I am using on GitHub. I have provided a link to the compiler here: https://github.com/dimag0g/nios_duino. The issue I am having is that I am unable to compile my top level file because of two errors, one of them regarding syntax and the other regarding module declaration.
Below is my code for my top level module:
/*
*FPGA Interconnect Module for the NVSRAM Database, SRAM PUF, & UI
*SRAM PUF connected through GPIO pins to parallel IO
*NVSRAM database connected through GPIO pins to I2C module
*User Interface connect through UART/USB to NIOS
*/
module sawblade_project (
input wire CLOCK_50_B5B, // Clock signal
input wire [35:0] GPIO, // I/O pins for
input wire LEDR0, // Connect to PIO 13 to verify the code is working
output wire UART_TX, // UART ports for UI computer
input wire UART_RX // Uart ports for UI computer
);
//tie SRAM_VCC_CNTRL high, BLE low & BHE high
always begin
GPIO[32] = 1; //SRAM_VCC_Control tied high
GPIO[33] = 0; //BLE tied low (active low)
GPIO[35] = 1; //BHE tied high (active low)
end
//instantiate nios_duino module
nios_duino u0 (
.clk_0_ext_clk(CLOCK_50_B5B), //Clock signal @ 50 MHz
.clk_in_reset_reset_n(KEY1), //Clock reset signal
.cpu_reset_cpu_resetrequest(KEY0), //CPU Reset request signal
.cpu_reset_cpu_resettaken(LEDR1), //CPU Reset taken signal
.i2c_0_ext_sda_in(GPIO[20]), //SDA for NVSRAM database
.i2c_0_ext_scl_in(GPIO[19]), //SCL for NVSRAM database
.i2c_0_ext_sda_oe(1), //I2C data buffer tied high
.i2c_0_ext_scl_oe(1), //I2C clock buffer tied high
.pio_0_ext_export[12:0](GPIO[12:0]), //GPIO to PIO IP
.pio_0_ext_export[13](LEDR0), //LED signal @ PIO 13 to ensure compiler operation
.pio_0_ext_export[19:14](GPIO[18:13]), //GPIO to PIO IP
.pio_0_ext_export[30:20](GPIO[31:21]), //GPIO to PIO IP
.pio_0_ext_export[31](GPIO[34]), //GPIO to PIO IP
.uart_0_ext_rxd(UART_RX), //UART receiving line for UI interface
.uart_0_ext_txd(UART_TX) //UART transmission line for UI interface
);
endmodule
This time, I made sure not to compile either the template files that came with my project once I generated the code using the Platform Designer (SOPC Builder). Nevertheless, I am still receiving this error from the compiler:
Error (10170): Verilog HDL syntax error at sawblade_project.v(31) near text: "["; expecting
")". Check for and fix any syntax errors that appear immediately before or at the specified
keyword.
Could this error be because I am not instantiating the pio_0_ext_export bus correctly, or is there another issue entirely?
In addition I am also having a module declaration error with one of the submodules:
Error (10228): Verilog HDL error at nios_duino_sysid_qsys_0.v(34): module
"nios_duino_sysid_qsys_0" cannot be declared more than once
However, I have checked the code for this submodule and that does not appear to be the case, especially since this submodule code was generated by the Platform Designer and was not edited by me. Here is the code for the nios_duino_sysid_qsys_0 module for reference:
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_duino_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1623863076 : 17149200;
endmodule
AI: There are a couple of issues here, one is with the assignment to an input, and the other is trying to index part of a port with .portName[bitRange](connection) being invalid syntax.
In terms of the second case, if you want to assign multiple different signals to a single multi-bit port, you should instead use concatenation:
.pio_0_ext_export({GPIO[34], GPIO[31:21], GPIO[18:13], LEDR0, GPIO[12:0]})
However this doesn't get around the first issue of trying to assign some GPIO pins to be inputs. Looking at your code, it seems you want those hard-wired pins to actually be outputs. If this is the case, you can simply change that line to:
inout [35:0] GPIO,
This will make the port bidirectional - pins can be inputs or outputs. Then your assignment will be possible. However not quite as written. Your port is still a wire type, so assignment in a procedural block is not possible. Instead, replace the always block with:
assign GPIO[32] = 1; //SRAM_VCC_Control tied high
assign GPIO[33] = 0; //BLE tied low (active low)
assign GPIO[35] = 1; //BHE tied high (active low)
The latter error message about multiple module definitions sounds like you have multiple files declaring the same module.
Have you by any chance included a file called nios_duino_sysid_qsys_0_bb.v or other duplicate files in your project? |
H: Frequency-dependent behavior of a resistor in time domain simulation
I know for a fact that to take into account frequency-dependent behavior in time domain simulation, equivalent electrical networks that reproduce the same frequency behavior are used, as it happens, an RL ladder circuit (Cauer circuit) as the one seen below are implemented:
It is always a matter of fitting the module of the impedance and never the phase. Since a frequency-dependent resistance has a zero phase no matter the frequency, how do you guys approach the fact that an equivalent passive circuit reproducing the same behavior (R(f)) -might(*)- have an additional phase to it and it has never been addressed(**) in previous research work.
Also, I know this is more a mathematical question than physical, but what would you guys suggest as a technique when it comes to computing the values of the parameters R_i L_i that will eventually give a network that has the same frequency behavior as R(f) (or ultimately L(f))?
(*) It eventually does have a non-null phase since we have inductances in the equivalent circuit...
(**) Or I still haven't come across it...
AI: Your doubts are well founded. A frequency-varying pure resistance is not a physical thing. As the real part of an impedance changes with frequency, the imaginary part of the impedance is constrained to vary in a particular way. This is due to causality. (look up kramer-kroning relations) So, you can't build a circuit that that varies resistance with frequency without some phase shift in it. However, the constraints concern DC to Daylight, and if you are only interested in a limited frequency range, you can get close to a pure real impedance over that frequency range. (easier in low bandwidths, harder in high bandwidth cases).
But... you want a time domain simulation... which means you do want to get something that works over all frequencies. (high frequencies are the edges of your response, low frequencies are the flat places in your response.) I would guess that the equivalent circuits of the people modeling dielectric losses and such are "close enough" for their needs. |
H: Waveform result of an equation
I have this waveform and I would like to have the Y.
I know that the equation is Y = D' + E' + F'.
Where it has ' it means NOT.
As I see it, the only thing I did, and I am not sure if it is right, was this:
If I got it right, this is it:
AI: Do the analysis graphically.
Any red section in D, E or F will cause Y to be true.
You will also see that D is not required to generate Y. |
H: How do I convert a switch’s single output into a double output per keypress?
I am new to electronics compared to many here I’m sure, but I have some experience with Arduinos and basic circuits and PCBs. If for example I had two mechanical keyboard switches wired up to an Arduino board (one ground wire and two for the signals), and they are designed to trigger only once upon a keypress, how can I wire them and to what in what way so that at any time I can convert their signals to double their usual output and cause the signal to trigger twice rapidly per keypress (or more)? I have read about different switches such as SPST, DPDT, etc, but if that is the kind of stuff that is needed I am not entirely sure how to apply that. Anyways thank you.
AI: You can't wire them that way - the switch is designed to make contact exactly once.
However, you don't have to - you have a microcontroller that can be programmed to do anything when it sees that single impulse, including, for example, pulling an output pin low twice. |
H: What's the saturation speed of a transistor and the wires between inside a modern CPU?
I'm tinkering with a specialized CPU design and I'd like to calculate/estimate the saturation time of a circuit that may eventually be part of a CPU made with current technology.
For this I need to know:
How long do I need to provide signal to a transistor for it to saturate?
How long it takes for the wires between to propagate a signal?
Do I have to maintain the signal on the wire the entire time for it to propagate a signal?
Assuming optimal temperatures
AI: I'm tinkering with a specialized CPU design and I'd like to calculate/estimate the saturation time of a circuit that may eventually be part of a CPU made with current technology.
Then you need to do what real CPU designers do: simulate it. Most tools will provide gate-level simulation which is accurate enough. For specialized purposes you can also do physical-level simulation with SPICE.
For this I need to know:
How long do I need to provide signal to a transistor for it to saturate?
The gate of a FET is effectively a capacitor; the time taken is that to charge the capacitor to an acceptable level so that the voltage level on the output of the gate has risen to a threshold, such as 80% or 90% of VDD ("rise delay" / "fall delay").
How long it takes for the wires between to propagate a signal?
It depends. Usually the Elmore Delay Model is good enough; in order to use that you need to first select your silicon process then ask the vendor what the resistance and capacitance per unit length of wire are.
Do I have to maintain the signal on the wire the entire time for it to propagate a signal?
Usually the wires on a chip are short enough that the answer is "yes". It's not like a transmission line between chips, where you can send pulses, it's more like a funny-shaped capacitor that you have to pour charge into in order to raise/lower its voltage to a target level. |
H: Charge and discharge cycles for optimum battery health
My new laptop, ASUS Zephyrus G15 has an option to cap the battery charging at 60% for "greatly extending battery life". That's great; but I've also heard that a battery should never be plugged in and that it should always have charge and discharge cycles for optimum battery health.
Should I keep my laptop always plugged in, capped at 60%, or should I keep removing the charger to keep the battery levels between 20-60%?
This answer mentions that the ideal battery percentage is around 70% - does this mean I should keep my laptop always plugged in with the 60% cap? Is what I've heard about charge and discharge cycles incorrect?
AI: It depends on the chemistry of the battery.
The cycles you are referring to is to avoid what is called the memory effect and happens in nickel-cadmium and nickel–metal hydride batteries.
From that, there are myth that batteries should be charged / discharged periodically, which is incorrect for most chemistries.
Your laptop has a Li-Ion battery that does not have memory effect, in the contrary, charge and discharge cycle actually damages the electrodes as they they physically increase and decrease in size, causing particles to get into the electrolyte, reducing the battery capacity.
Cycles also creates dendrites, that aren't good.
For the best lifetime, cap charging at 60% and always have it plugged in. |
H: What are the boundaries around pads in KiCad PcbNew and what are their functions?
I am learning to design PCBs in KiCad. Right now I am using footprints I found online.
In PcbNew I find there is a boundary surrounding each pad. In footprints found in KiCad, these boundaries don't overlap with the boundary of the adjacent pad. In a few footprints I downloaded from the Internet, I find the boundaries overlapping. In the below screenshot of the PcbNew components, green arrows are the overlapping boundaries and pink arrows are non-overlapping boundaries.
What is the function of these boundaries? Is there a problem if they overlap? If yes, what are those problems and how can I edit them so that they don't overlap?
AI: The boundaries you are referring to are visual aids associated with constraints.
These constraints are there to help you with regards to the fabrication technology or other creepage considerations.
Such settings are associated with the PCB project, not the footprint.
With the default board configuration (0.2mm) clearance and a standard SOT23 footprint, it can be seen that there is overlap between pin1-pin2 and pin2-pin3 boundary.
NOTE: overlap of such outlines are fine, it is when the outline of one touches the copper of another... then there is a DRC violation
Now the rules can be changed and as you can see, changing it to 0.1mm reduces these rings and now they don't overlap
You can then create named constraints where different nets might require larger clearance consideration (controlled impedance? higher voltage)
Once you start assigning netclasses the new (v5.99) constraints manager permits you to write rich design constraints.
NOTE: do not shrink the clearance downto a value that permits the layout to be completed, shrink it to the value it need and this is typically downto your fabricators capability w.r.t. copper thickness.
A recent 1oz card I did had the DEFAULT clearance set to 0.13 (with isolated nets with 0.3mm) while an associated 3oz card had the DEFAULT clearance set to 0.26mm |
H: 2P circuit breaker, Ground wiring
i need to test some outlets and im using a 25A 2P circuit breaker, from what i researched i need to connect neutral and hot to the circuit breaker and from there to the outlet. My question is, do I need to connect the ground wire directly to the outlet or is there another way? Thanks, Pedro.
AI: The ground wire should not be connected through the breaker, and directly to the ground.
Connecting it through the breaker would be a safety hazard. |
H: DC-DC fixed voltage output converter and EMI Design, where to begin and roadmap?
I'm in a group of people tasked to design and implement a DC-DC converter with an output voltage of 24 volts, with an input voltage from 9 to 36V, with an EMI filter, which must comply with the EN50155 standard.
Read lots of papers but still having trouble where to start.
Should I begin with common mode and differential mode chokes design?
But in which range of frequencies must I attenuate?
I found formulas to find ferrite core permeability and circular mils. But still don't know where to start or simulate these in a program.
Hope to get a direction and instructions from an experienced person.
AI: You mention EN 50155, so Railway Applications - Onboard. The reference EMC standard is indeed the EN 50121-3-2 for immunity, and EN 61000-6-4 for emissions (Industrial env.).
Now, it seems you are focusing on emissions: of course a DC/DC switching converter will have common mode emissions, that are relevant for compliance to conducted limits (up to 30 MHz) and radiated (above 30 MHz). This is the division of frequency ranges as per CISPR and EN 61000-6-4. be careful that the rolling stock item (e.g. loco or electro-train, or what) must pass EN 50121-3-1 that measures radiated emissions starting from 150 kHz. So, radiated emissions between 0.15 and 30 MHz from the DC/DC and its cables may be relevant to the overall compliance.
Then, the DC/DC conv may disturb others, as it will supply for sure some signaling or telecom equipment, maybe in the driver cab, or some Wifi AP along the train, or similar. In particular for special equipment such as driver's console, rather than a WiFi AP, the protocols used to send signals back and forth may be susceptible to coupling of noise through the respective functional grounds or to crosstalk. You do not have specs for this, because it's not compulsory, but knowing possible victims ("neighbors") and possible coupling paths beforehand will increase acceptance of your DC/DC product.
To come down to some figures, without knowing your power rating (i.e. the size of your DC/DC) usually a common-mode inductor around some mH works quite well; consider that if you include capacitors, they will need "ground", and onboard that ground is chassis, and everybody -- almost -- connects to it. So better relying on a good cm inductor.
Frequency range: you must simulate first, measure then the emissions of your DC/DC to understand which type of ferrite you need: considering low frequency (the mentioned 150 kHz for compliance to standards, lower than that for compliance with "neighbors"), you need "soft" ferrite, e.g. 3E25 by Ferroxcube or equivalent (you need to build up the some mH we spoke of); high frequency can be cured with a ferrite toroid directly on the cable.
Of course, this is approximate and based on experience, pointing the finger to the major issues and elements. You should be more quantitative, considering the converter architecture, typical waveforms and so on. |
H: Using microprocessor over microcontroller in ECU?
What are the benefits/advantages of using microprocessor than microcontroller in ECU(which are used in automotive applications)
AI: a Microprocessor, can be way more powerful, but way more complex to implement and require much more work than an MCU.
An MCU is basically a computer on its own that contains a microprocessor, ram and flash, while a microprocessor will not.
Beyond the clock speed, microprocessor often have more advanced instruction handling, a larger instruction set, higher cache memory, making them better performers.
Our days sees more and more powerful MCU, some of which can even run at few hundred Mhz, and run OS like Linux, although it does not compare to processors that runs in the Ghz range.
The main component is the instruction speed, measured in IPS (instruction per second) or sometimes in DMIPS.
A high-end ARM based MCU like STM32F7x6 is capable of 462 DMIPS at 216Mhz, while an intel I7 handle 56'000 DMIPS at 3Ghz so effectively 120x faster.
Beside the raw processing speed, it means also how fast an algorithm can be executed.
In terms of automotive, the importance of speed is for the control of ABS, Airbags and so forth, as the system latency is of outmost importance, as ms/us response time, translate to meters traveled in a vehicle at high speed.
At 120km/h a vehicle travels 33m/s, if the ABS algorithm takes 1ms to execute, that is 33cm traveled, if it takes 120ms it's 4 meters.
There of, the algorithm to deploy airbags, trigger ABS, or other safety systems needs to run as fast as possible, and may be the difference between life and death. |
H: STM32MP157c SPI clock will not idle high
I am trying to run crystalfonts lcd cfaf240320a0024sc (https://www.crystalfontz.com/product/cfaf240320a0024sc-240x320-full-color-touchscreen-tft-2-4) with stm32mpu over SPI. The LCD controller is ST7789
I am using STM32MP157c that comes with octavo OSD32MP1-BRK.
OpenSTLinux kernel version is 5.4
I can interface the LCD easily with an arduino/seeduino. But it doesn't work with the octavo.
I wrote a clone of the arduino example program (https://www.crystalfontz.com/products/document/4222/CFAF240320A0-024SC_Arduino_SPI_bring_up.zip) using Linux userspace spidev interface. One thing I notice is that even though I have set CPOL=1, the clock never idles high. It always goes back to low.
I am using the following device tree block:
&spi6 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi6_pins_mx>;
pinctrl-1 = <&spi6_sleep_pins_mx>;
cs-gpios = <&gpioz 3 0>;
status = "okay";
spi-cpol = <1>;
spi-cpha = <0>;
spidev6: spidev6@0{
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
reg = <0>;
spi-cpol = <1>;
spi-cpha = <0>;
};
};
Also I have tried to pull up the relevant pins in the pinconfig block, and tried without this as well, but no luck:
spi6_pins_mx: spi6-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 2, AF8)>; /* SPI6_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('Z', 1, AF8)>; /* SPI6_MISO */
bias-disable;
};
pins3 {
pinmux = <STM32_PINMUX('Z', 0, AF8)>; /* SPI6_SCK */
bias-pull-up;
slew-rate = <1>;
};
};
I have even tested with the LCD detached but it still idles low. I have verified that my device tree changes are running by turning onboard LEDs on and off.
Just before the SPI starts to transmit it becomes high and after the transmission is finished, it becomes low again. This is not acceptable as many cheap LCDs do not have a CS pin and they read based on clock edge not CS.
In the userspace spidev program, I am using the same SPI mode (2) as well
AI: The datasheet is pretty clear: "If CPOL is set, the SCK pin has a
high-level idle state.", so it should be idle high.
However, you do have pinctrl-1 set to spi6_sleep_pins_mx and you're not showing what value this has. And the spi-stm32 driver uses runtime PM, which will automatically switch the pins to the "sleep" pin mux configuration when the SPI controller is not in use (after a certain timeout). It could be what you're seeing here. Try to disable runtime PM for the SPI controller. |
H: MOSFET to drive LED, never turns fully off
I have the following circuit (see attached) where I am using a SI2302 MOSFET to switch an LED using a micro-controller (internal pull down.)
The problem I am seeing:
Upon switching between 3.3V (HIGH) and 0V (LOW) on the gate, the voltage measured on the drain pin switches between 0.6 and 0.7 volts, which makes the LED just slightly brighter/dimmer when switching, but it won't turn it on or off fully.
I would expect to see approximately 3.3 volts at the drain when the MCU output is low (MOSFET not conducting) and approximately 0 volts at the drain when the MCU output is high (MOSFET fully conducting).
I have read through some similar posts, but the issue there was that the MOSFET was probably broken or soldered the wrong way around.
I have 6 of these circuits in parallel and all show the same issue.
UPDATE:
Gate is driven by an STM32L051.
Tried it with an external 10k pulldown resistor between gate and source. Same outcome.
Tried it by disabling the STM32 and manually switching the Gate. Same outcome.
FINAL UPDATE:
It was my bad, I soldered SI2303 instead of SI2302. Thank you all very much!
AI: If you are seeing 0.6V across the MOSFET then it's highly likely that you are measuring the forward drop of the body diode. So, either
a) The MOSFET is misplaced (i.e. mirrored order -- D to S and vice-versa), or
b) That's a PMOS instead.
For (b), the body diode is reversed compared to an NMOS. So, even if you connect it as supposed, the body diode will always be forward-biased. |
H: Create this design with only NAND gates
How can I do that with NAND gates?
I have done this
with "blue" color if it doesn't seem well. It is A and C.
AI: Well, the first logical step would probably be to turn those AND gates into NAND gates, by adding two "bubbles" at the output of each.
Afterwards, review the concept of Bubble Pushing, then apply it in order to turn the rest of the components into NAND gates. |
H: Calculate intensity from a photodiode using voltage
I am running a photodiode through an op-amp circuit (trans-impedance amplifier.) I have been told I should characterize this device. I'm assuming he means using the voltage I get at a given distance and link this with the intensity of light by use of an equation.
I moved the sensor back 5mm at a time taking readings etc., etc.
I plotted it on a graph of voltage against \$\frac {1}{\text{distance}^2}\$ giving a slope of 109.38V/cm^2
I plan on using this relationship:
$$I \propto x^{-2} $$
Therefore
$$I=k \times x^2 $$
where $$I = \text{intensity} $$
Would \$\frac{k}{x^2}\$ not just be the same as the gradient of my graph?
I just can't seem to wrap my head around this and it's driving me up the wall.
Any help would be greatly appreciated.
I have attached the graph if it sheds any light on the problem:
This is the photodiode I'm using, detecting at a wavelength of 310nm.
I think I am getting there. This is the current equation I have. I used two equations and substituted them into each other to work out k.
I'm sorry I forgot to mention that I was using an LED for this. The power values are between 1mW and 2mW at I'm assuming the device is at 1mW as it's limited at 20mA of current at 5V.
Data sheet for the LED.
AI: For the measured voltage \$v\$ your graph shows
$$
v = 109.4\,\text{V/cm}^2 \times \frac{1}{d^2} + 0.86\,\text{V}
$$
The op-amp circuit translates the current through the photodiode into a voltage via the relationship
$$
i_{\text{diode}} = 100\,\text{nA/V} \times v
$$
Photodiodes produce a current based on the amount of power they receive. At low power levels this relationship is linear. The responsivity constant \$R\$ has units of amps per watt. Therefore the power received by the photodiode is:
$$
P_\text{diode} = \frac{1}{R}\times 100\,\text{nA/V} \times v
$$
$$
= \frac{1}{R}\times 100\,\text{nA/V} \times \left( 109.4\,\text{V/cm}^2 \times \frac{1}{d^2} + 0.86\,\text{V} \right)
$$
Intensity is power per unit area. In this experiment we are only measuring the total power received by the photodiode, so we can only talk about an average intensity which is \$P_\text{diode}\$ divided by the photodiode's surface area, \$\sigma_\text{diode}\$. This gives us:
$$
I_\text{avg} = \frac{P_\text{diode}}{\sigma_\text{diode}}
= \frac{1}{\sigma_\text{diode}R}\times 100\,\text{nA/V} \times \left( 109.4\,\text{V/cm}^2 \times \frac{1}{d^2} + 0.86\,\text{V} \right)
$$
You don't know the constants \$R\$ and \$\sigma_\text{diode}\$, but you can see from this formula that \$I_\text{avg}\$ is basically proportional to \$1/d^2\$. |
H: How do power grid systems supply power to new loads coming online?
I know that in a power system there are no energy storage elements. Due to this, as soon as power is generated by the generators it is transmitted to the end user where the power is utilized.
Say a power system is stable at the moment (energy supply is equal to the energy consumption.) If new equipment is connected to the power system (say 5 MW) it is energized as soon as it is connected.
Where does that additional 5 MW of power come from instantly until the power system frequency goes down and the active power governors speed up the generators? (Obviously there is a time delay.)
AI: Where that additional 5MW of power came from instantly until the
power system frequency go down and active power governors speed up the
generators (obviously there is a time delay)?
The voltage on the line sags when loads are switched on (which is dependent on resistance and inductance in physical wires; if they were superconducting wires, the load and source would react almost instantaneously). When large loads are switched on and the grid can't source the power instantly because the wire inductance and resistance prevents it, the voltage sags and can cause a brownout (the same thing happens in your house when you turn on a vacuum and the lights dim for a bit).
Usually in the case of larger loads the power company needs to be notified so that they can be ready to avoid a local brownout. The power generation on the other end must provide more current (to match the current being drawn at the other end by the load) or the voltage will drop and no one likes that.
In the short term, capacitors and DFR's (Distributed Feeder Regulators) and other regulators can make up some of the difference, but they can only cover line regulation for short amounts of time with small amounts of power.
If too much power is drawn, the power generation facility might 'trip' and a blackout will occur until generation is restored. |
H: Is there a preferable way to distribute layers in a 4 layer PCB?
I'm routing a PCB and, due to its small size, I'm thinking to use 4 layers. I'm planning to use top, bottom and two internal layers.
Summarizing:
TopLayer : GND plane
Midlayer1: 5Vcc plane
MidLayer2: 3.3Vcc plane
Bottom layer: GND plane
It will have 3 ICs only (one 8 bit level shifter, one 8 bit bus switch and a 5 to 3.3 V regulator) and smaller components like TVS diodes, clamping diodes, resistors and capacitors. The current is not high, the purpose is to digital communications only. Frequency is not defined, but it will be no greater than 1 MHz.
I don't know if there is a generical rule for it, but someone know if Is there a preferable distributions of layers? A rule of thumb or something?
EDITED:
Due to some doubts and discussion I will refine the informationhere. The PCB will need to be very small, so I choose this distribution:
TopLayer : GND plane + components + signals
Midlayer1: 5Vcc plane
MidLayer2: 3.3Vcc plane
Bottom layer: GND plane + components + signals
AI: There are two main conventions, but no rule of thumb as PCB layer stackups are design dependent. These are two general conventions:
Source: Electromagnetic Compatibility Engineering by Henry W. Ott
Using grounds on the outside to help with EMC, the grounds function as a shield that signals on the inside might use. Both schemes in figure 16-14 are good for shielding signals with either two grounds on the outside or a power plane and ground.
The problem with the scheme in figure 16-14 is the components are on the top layer, so you would need to use a lot of vias to route the signals to an inside mid-layer.
The scheme in figure 16-15 uses signals on the top and bottom and grounds in the middle, and in my opinon much easier to route, and is the scheme that I see used the most often.
I would use grounds in the middle and signals on the outside, it works for most designs. I use this scheme:
Signal+Power+Components
Ground
Power
Signals
Or this one:
Signal+Power+Components
Ground
Power+few signals
Power+Signals
As far as frequency goes, any traces over (generally) 50MHz will need to use transmission lines. In that case you do need to worry about many more things like the width of the traces and height between layers. At 1MHz losses are much less, you may have to worry about signals radiating off the board and causing interference (mainly with DC DC converters or clocks).
One Nice thing about having a ground layer in a middle layer is it creates a small amount of capacitance between planes and it keeps a continuous ground plane both of which work to reduce EMI and EMC problems in a design. If you don't have a continuous ground plane currents must go around components and it can add inductance and resistance to a ground plane.
With components on top layer becomes difficult to keep it continuous ground plane, this can also be a problem with ground loops or common mode voltage noise as a non continuous ground plane will have more resistance and inductance between the load and the source, especially on the low side of the load. If you do decide to go with grounds on the outer layer make sure they are continuous as possible.
Components on both sides does not really create issues for either stack up as it's only a matter of routing, however signal layers on the outside is much easier to route especially if you're going for more compact design |
H: Custom/Varying delays on a HSpice digital vector file
I've been trying to find a way to set custom timings for signals coming from a digital vector file in a simple test circuit with 4 inputs and 4 outputs as shown.
simulate this circuit – Schematic created using CircuitLab
I used 4 of these to easily observe input/output behavior.
My digital vector file code is :
radix 1111
vname v<4> v<3> v<2> v<1>
io iiii
tunit ns
period 10
trise 0.01
tfall 0.01
vih 1
vil 0
0000
0001
0010
0011
as well as some more tabular data that isn't included.
So for example, I want 0000 to occur at 0ns, then 0001 at 15 ns, then 0010 at 16 ns, and 0011 at 20ns. It seems like there is no way to set a custom delay in the .vec file using vector file commands other than inserting a bunch of 0000's so I was wondering if it would be possible to do that through the actual .sp file that uses my digital vector file.
If it helps, this is how I used the vector file in my spice file:
r9 vout<4> 0 1e3
r8 v<4> vout<4> 1e3
r7 vout<3> 0 1e3
r6 v<3> vout<3> 1e3
r5 vout<2> 0 1e3
r4 v<2> vout<2> 1e3
r1 vout<1> 0 1e3
r0 v<1> vout<1> 1e3
.vec 'tabvec.vec'
.print v(*)
.probe v(*)
.options post
.tran 1n 200n
AI: So for example, I want 0000 to occur at 0ns, then 0001 at 15 ns, then 0010 at 16 ns, and 0011 at 20ns. ...
In this PDF file:
https://www.bioee.ee.columbia.edu/courses/cad/html/vector_file.pdf
on page 39 it says the following about tabular data:
So I'd try not using the period directive and adding timestamps to your tabular data. That page of the PDF also contains this example:
; format: time vector
0 000101010
10 011010101
20 000101010 |
H: Can an RCD do the job of an ordinary fuse?
Suppose we have a short circuit somewhere in a house. Does a residual-current device (RCD) stop the current in this situation exactly as an ordinary fuse does? or it's not reliable for this?
AI: An RCD/GFCI alone does not do the job of an ordinary fuse, which is to interrupt an overcurrent condition; rather its purpose is to detect imbalances in current that suggest dangerous leakage or ground faults.
However, it is common to see devices which are marketed, engineered, and certified to have both RCD and overcurrent protection functions. An example is the GFCI circuit breakers for the North American market which have both an overcurrent and an RCD trip, and are installed in home distribution panels similarly to traditional circuit breakers. Likewise, in the European market, such a device is called an RCBO. |
H: Creating a finished product with STM32 platform
I have the STM32 discovery board and I used it with external components to make a simple project. Now my question is: where do I go from here, how do I go from my breadboard + STM to one sleek PCB design with the STM32 platform?
AI: You'll need to have the design drawn up in some PCB design software some free choices include but not limited to:
Eagle
KiCad
There are plenty of tutorials (this one specifically for STM32 in kicad) on how to start this process and produce a board.
You draw up the schematic, draw up the footprints for each part (or find a library that someone else has drawn up) then draw up the PCB which replicates the design of the schematic with PCB artwork. *Make sure that you double check the design, and improper design means extra cutting and soldering of wires on the board after its manufactured)
Once the design done you send the pcb files to a manufacturer, (Like PCBway or oshcut) and they send you back some PCB's. You will then either need to send this to an assembler with the parts, or you could hand solder them yourself (also plenty of tutorials like this one out there) . |
H: Simplifying a Boolean expression with four variables
Below is a problem I attempted from one of the popular books on Computer Architecture. After nearly two pages of work, I am not close to the answer. I am thinking there should be a much easier way.
Note: I am not currently taking any courses and I am not planning on taking any courses. That is, I am not currently a student and I am not planning on becoming one.
Problem:
Prove the following Boolean equation using algebraic manipulations:
$$ WY + \bar{W}Y\bar{Z} + WXZ + \bar{W}X\bar{Y}
= WY + \bar{W}X\bar{Z} + \bar{X} Y \bar{Z} + X\bar{Y}Z $$
Answer:
\begin{align*}
\bar{W}Y\bar{Z} + WXZ + \bar{W}X\bar{Y} &=
\overline {
\overline { \bar{W}Y\bar{Z} + WXZ + \bar{W}X\bar{Y} }
} \\
%
\bar{W}Y\bar{Z} + WXZ + \bar{W}X\bar{Y} &=
\overline {
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z})(W + \bar{X} + Y)
} \\
%
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z}) &=
W (\bar{W} + \bar{X} + \bar{Z}) +
\bar{Y}(\bar{W} + \bar{X} + \bar{Z}) +
Z (\bar{W} + \bar{X} + \bar{Z}) \\
%
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z}) &=
W \bar{W} + W \bar{X} + W \bar{Z} +
\bar{Y}(\bar{W} + \bar{X} + \bar{Z}) +
Z (\bar{W} + \bar{X} + \bar{Z}) \\
%
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z}) &=
W \bar{X} + W \bar{Z} +
\bar{Y}\bar{W} + \bar{X}\bar{Y} + \bar{Z}\bar{Y} +
\bar{W}Z + \bar{X}Z + \bar{Z}Z \\
%
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z}) &=
W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z \\
\end{align*}
\begin{align*}
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z})(W + \bar{X} + Y) &= \\
W
( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
+
\bar{X} ( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
+ Y( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
\\
%
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z})(W + \bar{X} + Y) = \\
W \bar{X} + W \bar{Z} + W \bar{Y} \bar{Z} + W \bar{X}Z \\
+
\bar{X} ( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
+ Y( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
%
\\
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z})(W + \bar{X} + Y) = \\
W \bar{X} + W \bar{Z} + W \bar{Y} \bar{Z} \\
+
\bar{X} ( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
+ Y( W \bar{X} + W \bar{Z} +
\bar{W} \bar{Y} + \bar{X}\bar{Y} + \bar{Y} \bar{Z} +
\bar{W}Z + \bar{X}Z ) \\
%
\bar{X} ( W \bar{X} + W \bar{Z} + \bar{W} \bar{Y}
+ \bar{X}\bar{Y} + \bar{Y} \bar{Z} + \bar{W}Z + \bar{X}Z ) &= \\
W \bar{X} + W \bar{X} \bar{Z} + \bar{W} \bar{X} \bar{Y}
+ \bar{X}\bar{Y} + \bar{X} \bar{Y} \bar{Z} + \bar{W} \bar{X} Z + \bar{X}Z \\
%
\\
\bar{X} ( W \bar{X} + W \bar{Z} + \bar{W} \bar{Y}
+ \bar{X}\bar{Y} + \bar{Y} \bar{Z} + \bar{W}Z + \bar{X}Z ) &= \\
W \bar{X} + \bar{W} \bar{X} \bar{Y}
+ \bar{X}\bar{Y} + \bar{W} \bar{X} Z + \bar{X}Z \\
\end{align*}
\begin{align*}
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z})(W + \bar{X} + Y) = \\
W \bar{X} + W \bar{Z} + W \bar{Y} \bar{Z} \\
+
W \bar{X} + \bar{W} \bar{X} \bar{Y}
+ \bar{X}\bar{Y} + \bar{W} \bar{X} Z + \bar{X}Z \\
+ W \bar{X} Y + W \bar{Z} Y +
\bar{W}Y Z + \bar{X} Y Z \\
%
\\
(W + \bar{Y} + Z)(\bar{W} + \bar{X} + \bar{Z})(W + \bar{X} + Y) = \\
W \bar{X} + W \bar{Z} + W \bar{Y} \bar{Z} \\
+
W \bar{X} +
+ \bar{X}\bar{Y} + \bar{W} \bar{X} Z + \bar{X}Z \\
+ W Y \bar{Z} +
\bar{W}Y Z \\
%
\bar{W}Y\bar{Z} + WXZ + \bar{W}X\bar{Y} &= \\
\overline {
W \bar{X} + W \bar{Z} + W \bar{Y} \bar{Z}
+
W \bar{X}
+ \bar{X}\bar{Y} + \bar{W} \bar{X} Z + \bar{X}Z
+ W Y \bar{Z} + \bar{W}Y Z
} \\
\end{align*}
AI: Bob, just keep in mind that all terms (I use that term, advisedly, as you should keep in mind what a mathematician means when they say 'term' or 'factor') can be expanded to all variables by populating them with all possible permutations of the unstated variables. So when I write \$X\;Y\;Z\$ in the context of four variables, \$W\$, \$X\$, \$Y\$, and \$Z\$, you must recognize that this is the same thing as \$\overline{W}\;X\;Y\;Z+W\;X\;Y\;Z\$ as you can apply the distributive property to see that \$\overline{W}\;X\;Y\;Z+W\;X\;Y\;Z=\left(\overline{W}+W\right)X\;Y\;Z\$ and that is the same as \$\left(True\right)X\;Y\;Z=X\;Y\;Z\$.
In your case, just examine each term of the left-hand expression, in turn, and verify that all of its meaning can also be found in a term of the right-hand expression. Similarly, examine each term of the right-hand expression, in turn, and verify that all of its meaning can also be found in a term of the left-hand expression. If both sides cross-correlate, then you are done and you know they are equivalent.
Your equation is:
$$\begin{align*}
W Y + \overline{W} Y \overline{Z} + W X Z + \overline{W} X \overline{Y} &= W Y + \overline{W} X \overline{Z} + \overline{X} Y \overline{Z} + X \overline{Y} Z
\end{align*}$$
Working the left-side expression, first, I'll take each left-side term one at a time. I'll highlight each step by underlining the terms I'm examining and raising them up a bit. That way you'll know how it is that I'm saying "this side" is matched by "that side":
$$\begin{smallmatrix}
\underline{^{W Y}} &=& \underline{^{W Y}} &+& \overline{W} X \overline{Z} &+& \overline{X} Y \overline{Z} &+& X \overline{Y} Z
\\\\
\underline{^{\overline{W} XY \overline{Z}+\overline{W} \overline{X} Y \overline{Z}}} &=& W Y &+& \left[\underline{^{\overline{W} X Y\overline{Z}}}+\overline{W} X \overline{Y}\overline{Z}\right] &+& \left[W\overline{X} Y \overline{Z}+\underline{^{\overline{W}\overline{X} Y \overline{Z}}}\right] &+& X \overline{Y} Z
\\\\
\underline{^{W X Y Z+W X \overline{Y}Z}} &=& \left[\underline{^{W X Y Z}}+{W X Y \overline{Z}}+W\overline{X}Y\right] &+& \overline{W} X \overline{Z} &+& \overline{X} Y \overline{Z} &+& \left[\underline{^{W X \overline{Y} Z}}+\overline{W} X \overline{Y} Z\right]
\\\\
\underline{^{\overline{W} X \overline{Y}Z+\overline{W} X \overline{Y}\overline{Z}}}&=& W Y &+& \left[{\overline{W} X Y\overline{Z}}+\underline{^{\overline{W} X \overline{Y}\overline{Z}}}\right] &+& \overline{X} Y \overline{Z} &+& \left[{W X \overline{Y} Z}+\underline{^{\overline{W} X \overline{Y} Z}}\right]
\end{smallmatrix}$$
Now. Do the same thing for each term of the right-side expression, reflecting backwards to the left side. If there is a mapping in both directions, you've proved the equivalence.
This is the hard way, though. user287001 is just saying that if you expand out all the terms on both sides, then you'll have your answer already. It's actually easier to just expand the left side out and then expand the right side out and then just compare terms. The way I show you above takes more bookkeeping, so to speak. So I probably wouldn't do it that way. Use the approach user287001 mentioned. You are less likely to make an error that way.
Alternatively, if you need to make a different kind of proof, you can take the above approach to detect (find) the hidden equivalences and then just expand those terms and recombine them back. In this way, you can either manipulate the left-side expression so that it becomes the right-side expression, or visa versa. Your call.
Given the above work already done, this is how I'd go:
$$\begin{smallmatrix}
W Y &+& \overline{W} X \overline{Z} &+& \overline{X} Y \overline{Z} &+& X \overline{Y} Z
\\\\
\left[{W X Y Z}+{W X Y Z}+{W X Y \overline{Z}}+W\overline{X}Y\right] &+& \left[{\overline{W} X Y\overline{Z}}+{\overline{W} X \overline{Y}\overline{Z}}\right] &+& \left[W\overline{X} Y \overline{Z}+{\overline{W}\overline{X} Y \overline{Z}}\right] &+& \left[{W X \overline{Y} Z}+{\overline{W} X \overline{Y} Z}\right]
\\\\
\left[{W X Y Z}+W\overline{X} Y \overline{Z}+{W X Y \overline{Z}}+W\overline{X}Y\right] &+& \left[{\overline{W} X Y\overline{Z}}+{\overline{W}\overline{X} Y \overline{Z}}\right] &+& \left[{W X Y Z}+{W X \overline{Y} Z}\right] &+& \left[{\overline{W} X \overline{Y}\overline{Z}}+{\overline{W} X \overline{Y} Z}\right]
\\\\
\left[\left({W X Y Z}+{W X Y \overline{Z}}\right)+\left(W\overline{X}Y+W\overline{X} Y \overline{Z}\right)\right] &+& {\overline{W} Y\overline{Z}} &+& {W X Z} &+& {\overline{W} X \overline{Y}}
\\\\
\left[W X Y +W\overline{X}Y\right] &+& {\overline{W} Y\overline{Z}} &+& {W X Z} &+& {\overline{W} X \overline{Y}}
\\\\
W Y &+& {\overline{W} Y\overline{Z}} &+& {W X Z} &+& {\overline{W} X \overline{Y}}
\end{smallmatrix}$$
Take a careful look at how I expand terms going from the first line to the second line. Then take another very careful look at how I swap terms around when going from the second line to the third line. I've introduced no new terms -- no cheating. Then see how I combine terms back, in moving from the third line to the fourth and fifth lines.
It's a proof. The first line is your right-side expression and the last line is your left-side expression. They are equivalent. |
H: RL circuit with thyristor not working as expected
I'm trying to simulate the following circuit to test how it works:
The control circuit uses a PIC 18F4550.
The isolation circuit, and main circuit are these:
Unfortunately when I try to simulate this circuit on proteus,
i get the following signals as result
When I connect this circuit with a resistor and with ground connected
to the base of the circuit like this:
I get the expected result:
But if I add the inductor, the program doesn't show anything on the oscilloscope
What am I doing wrong?, What's the right way to connect the ground on this circuit?
Are there some additional considerations i should keep in mind?
AI: You need to check your connections. The first picture you're showing doesn't have the best drawn conections, but you can infer that the commanding pulse is applied relative to the common point of the two SCRs.
Then, in your 1st schematic, you have grounded the common point, while in the 2nd you haven't. Both are not driven correctly, but it shows carelesness.
And the load you're using has a 400 mH inductor, which is a lot in terms of the time constant involved (40 seconds), so you may want to reduce it at least by a factor of 10.
With these in mind, here's the reworked schematic:
The driving is done relative to the common point of the two SCRs while the load has the same 100 Ω resistor but with a .stepped value for the inductance, whose current is plotted: 1 mH (black), 10 mH (blue), 100 mH (red), and 1 H (green).
The SCR used is a simple approximation with two BJTs, but it works pretty decent and it's at the basis of many commercial models for SCRs (Littlefuse, for example). The diodes are randomly chosen. |
H: Multiple timers with ultra low power
I want to blink 3 different coloured LED's with different timing repetitions.
Red - every 2 minutes.
Green - every 25 minutes.
Blue - every 2 hours.
Components in the circuit:-
3 different coloured LED's
Small vibration motor (heptic alert)
Small battery 150-300 mAh.
micro-usb to charge the battery
As I want to maximise the battery life I am confused which IC's or MCU's to use for this application. The vibration motor will function with all 3 LED's. To find a balance with cost and battery consumption is really difficult.
The timer IC I found with very low power consumption is TPL5010. But I will have to use 3 of these to control 3 LED's. If I use a cheap MCU like ATTINY9 it doesn't have a RTC for time keeping.
To achieve lower power consumption the LED's can be turned on and off with quick intervals but is an MCU necessary for this?
What is the best way to achieve my application? Thank you!
AI: You don't need that timer IC at all, nor an RTC. Modern microcontrollers have low-power timers, which you can simply program to wake you up in a few seconds, or a minute, or two. There's no advantage to not implementing this functionality on a microcontroller; you just program your microcontroller to set a timer to wake in two minutes, change the LED state, program the timer to wake in two minutes (or 1 minute, should this be an odd multiple of 24th minute, and you need to activate the 25 minute LED). Every time you wake up, you check which LED's state to change.
The total parts cost of this is probably 3 LEDs, a sufficiently low voltage source (battery) so that you don't need a series resistor for these LEDs, a microcontroller, and a decoupling capacitor; if your timing needs to be exact, a crystal oscillator. No other approach will be as precise, cheap or easy.
As long as they are on long enough that you can see the LEDs light up, the total power consumption (over a day) of the microcontroller will almost certainly be lower than that of the LEDs, significantly so. An LED takes ~ 10 mA, a modern MCU in low-power timer mode ~ 50 µA. |
H: RS485 medium range communication
Hi, i don’t know if this is the right place to ask but i’m out of ideas so if i need to delete this please tell me.
Also, please note that i have little to no experience in electronic so if i make a mistake i’d be glad to know. Thanks.
Back to the question, i wanted to make 2 raspberry pi communicate over an old pair of wire about 100m (~330 feet) long.
The giant doubt that i have is, can a raspberry provide enough current/voltage to power an RS485 with that range?
Can i estimate a data rate?
Also a bit off-topic question. If thr RS485 protocol is said to be asynchronous, then why most implementations that i see are synchronous? What am i missing?
AI: This Maxim application note might be worthwhile reading:
How Far and How Fast Can you Go With RS-485? - Application Note 3884
https://pdfserv.maximintegrated.com/en/an/AN3884.pdf
In particular, it has this to say about data rate and transmission distance:
The maximum recommended data rate in the RS-485 standard from 1998 is 10Mbps, which can be
achieved at a maximum cable length of 40ft (12m). The absolute maximum distance is 4000ft (1.2km) of
cable, at which point, data rate is limited to 100kbps.These were the specifications made in the original
standard, which by the time of this app note’s publication is already 20 years old! Modern applications
involving RS-485 often have data rates several times 10Mbps, and require higher speeds over longer
distances. New RS-485 transceivers and cables are pushing the limit of RS-485 far beyond its original
definitions
The giant doubt that i have is, can a raspberry provide enough current/voltage to power an RS485 with that range?
You will be using RS485 transcievers, so you won't be driving the lines directly from the RPi's GPIO lines. Search for "RS485 module raspberry pi/arduino" for products. |
H: If a voltage source is current limited does this actually mean that the voltage across the load is limited?
For the past while I've been struggling to wrap my head around electricity.
One thing that has puzzled me to no end is the relationship between current and voltage.
On paper it's a really simple linear relationship. More voltage over a fixed resistance? That's more current. More resistance with a fixed voltage? Less current.
However, it seems to me that this rule is often broken. For example, Van de Graaff generators can create millions of volts across the human body, yet somehow with this massive voltage there is a limit to current. There is a quite popular video where a professor explains this is because current is low. However, if the human body is say 200k ohms shouldn't that be multiple amps?
It wasn't until a few days ago while daydreaming that I think I figured it out.
If current is limited by a series resistance then that means as the resistance of the load drops, the series resistance of the supply makes up a larger portion of the total resistance, and thus the voltage across the load drops, thus decreasing the overall current.
Does this mean then that a high voltage source with low current is actually low voltage across the load?
This seems to be the only way I can think of that current could be limited while obeying ohms law. Basically current limiting = voltage across the load limiting.
I am fully aware this post is probably full of painful misconceptions and so I would love any help anyone can provide. I feel electronics is often talked about in various forms of abstraction that make it extremely hard and frustrating for me to understand the fundamentals of what is happening. I struggle to live in a land of abstractions.
AI: A Van de Graaff generator is more like a capacitor than a battery. When a capacitor discharges through a resistor the initial current is \$V/R\$ as Ohm's law says it is, but the outgoing current quickly decreases the voltage on the capacitor. The result is a rapid decrease in the current provided by the cap.
A battery's voltage is (in the ideal case) unaffected by the current it provides.
If current is limited by a series resistance then that means as the resistance of the load drops, the series resistance of the supply makes up a larger portion of the total resistance, and thus the voltage across the load drops, thus decreasing the overall current.
This is, in fact, a pretty accurate view of most voltage sources - including batteries and power supplies - and it's the way voltage sources are modeled when you want to get realistic results.
Here's what a capacitor's discharge curve looks like:
Source: https://binaryupdates.com/how-capacitor-works-with-dc/graph-of-capacitor-discharging-current-and-voltage/
It's an exponentially falling curve. The time constant is \$R\times C\$ where \$C\$ is the capacitance and \$R\$ is the resistance of the discharge path. After one time constant the capacitor's voltage (and current) reduces by 63%. |
H: Two pins on ADV7123 Video DAC is tied to ground
Apologies if the question doesn't make any sense. I'm self-taught and very new to Electrical Engineering.
I'm working on a little project with a DE1-SoC FPGA development board and found out that the video DAC (ADV7123) on the DE1-SoC has 3 10-bit colour channels. However, it seems like on the DE1-SoC board only 8 of the bits are connected to the FPGA itself and the two LSB of the colour information is tied to ground, as seen in this schematic:
If I understand this correctly, does this mean that it would be impossible to achieve full brightness on any of the colour channels, or is there some configuration specifically with the ADV7123 that allows it to achieve full brightness, even with two bits tied to ground?
AI: In theory, using a 8-bit output interface to drive a 10-bit input will never reach the full maximum value.
The 10-bit maximum code is 1023 but the input will only reach a maximum code of 1020 with the 8 input bits.
However, the error is insignificant and this is common practice when converting between 8-bit and 10-bit interfaces.
The error for the maximum brightness is only 1020/1023 or about 0.3%.
Sure, it can be compensated by setting the reference current to be 0.3% higher, but it will not matter.
The DACs and the current references themselves are less accurate than the error of converting an 8-bit interface to 10-bit interface.
It would also require that the 75 ohm termination resistors at the DAC and at the receiving device use resistors with tolerance better than 1%, which is unlikely.
So don't worry, the DAC connection is good enough. |
H: If voltage and current are inverse to each other, how do we get higher power?
I am dazzled; I'm young (teen) so am not too good, but I am wondering if current is proportional to voltage, how do we get high power?
What I'm trying to say is that if we were to have a 5 V supply, from a battery or lab bench power supply, how do we make it like 10 A?
AI: if current is proportional to voltage, …
This is the case for resistors (or more generally resistive loads like incandescent light bulbs, toasters etc).
There's other kinds of loads, too, where the development of voltage over time matters (like for capacitors or inductors), or where the current-per-voltage dependency is not proportional, but exponential (like in a diode), but that's stuff you might learn later.
Important here is that the load defines this relationship: You apply a voltage, the load defines how much current flows through it.
What I'm trying to say is that if we were to have a 5 V supply, from a battery or lab bench power supply, how do we make it like 10 A?
We can't. Physics won't let us adjust current when we have a fixed load and a fixed voltage. If we want more current, we will have to increase the voltage. |
H: What is a cheap device for measuring low-power IoT devices?
what are some cheap (around 50 USD) devices for measuring and logging the power consumption for low-power devices (like IoT, for example)?
AI: Andreas Spiess just did a video comparing various products to do just that.
His conclusion was that the Nordic Power Profiler Kit II was the best value option for most applications. |
H: Driving transmission line
I want to drive a high capacitance transmission line with a 3.3V, 200MHz square wave. The transmission line has a capacitance of 48pF/m, impedance is 150Ohm.
Someone recommended me to drive the line with a MOSFET push-pull stage. How do I know hoch much current will be sourced into the transmission line?
AI: The transmission line has a capacitance of 48pF/m, impedance is
150Ohm.
If the transmission line is terminated in the correct impedance (150 Ω) and, is driven directly by the 3.3 volt peak amplitude square wave then, the peak current is identical to driving a 150 Ω load directly i.e. 22 mA peak.
At this frequency, when driving a transmission line, the capacitance per metre is of no-consequence because the transmission line behaves like errr... um... a transmission line.
This is because the transmission line has inductance per metre and, when you go about calculating the impedance of the transmission line you'll find this: -
$$Z_0 = \sqrt{\dfrac{L}{C}}$$
Hence, with your values, L = 1.08 μH
You can also drive the t-line with a series impedance of 150 Ω if the t-line output runs into an open circuit (impedance higher than a few kΩ is practical).
Scenario A and scenario B side by side: -
The graph is for the current from the source. Red is current from source into a t-line terminated in 150 Ω Blue is a source-series termination of 150 Ω and an open circuit t-line. |
H: From sine wave to square wave
I want to make a square wave generator with an LM311.
I have a variable sine wave source from 1Hz to 16kHz. The amplitude can vary between 0.5V to 11.4V.
I tried to use the comparator circuit below but couldn't get an acceptable result.
Sine wave configuration:
Blue is the output of the comparator, yellow is the sine wave:
Edit: After I added the pull-up resistor and made the supply bipolar (+12/-12V) I get the result below which is quite fine but has little distortions such as spikes. Peak values are on the other hand are not even near to the desired output. The wave oscillates between -11V and 750mV
Edit2: In real circuit I get the result below. What should I do to flatten the wave? Why is this happening?
AI: The LM311 isn't a dual output op-amp or comparator; it has a floating output BJT that can be wired in various configurations but, not like you showed in your question: -
In addition you need a pull-up or pull-down resistor to make it work. You'll also need to make sure that the input sinewave is halfway between the power rails regarding DC offset.
Also, don't expect spectacular performance at 16 kHz because it's quite a slow device: - |
H: Extra pin for shielding with CAN bus connector
I am presently using a 4 wire bus for CAN (CANH,CANL,PWR,GND). This is used all across the design for various boards. Now the cable needs to be shielded.
Would this imply using 5 pin connectors and crimping the shield into one of them (which is then connected to ground) Or is there a different way to this?
How is the drain cable connected to housing or ground when you're making a million units?
AI: If a designer is worried about radiating cables then shielding is a good idea, in most designs the shield pin would be tied to chassis ground. The scheme extends the chassis and prevents EMI from interfering from the inner conductors and prevents radiation from the conductors from reaching the outside world. In either case the return currents from the radiation flow down the cable through the shield to the board, The most designs it's best to direct these currents to chassis ground and away from the PCB to prevent common mode noise.
As a designer you need to decide if radiation would be a problem which would typically result from other switching loads on your design. Just the canned bus will probably not be enough of a potential radiator to justify shielding, there should be another reason. |
H: M8 connectors and their coding
A quick read on the internet shows that M8 connectors are coded.
The little info online I can find says A-coded is the most common style, typically used for sensors and actuators. B-coded is is mostly used for fieldbus connections.
This is what they look like:
What I am not understanding is why is one used for field bus and not the other? What's the difference between the two. They both have an indentation to prevent connecting incorrectly. What other reason could there be?
I need to pick a connector for CANbus and want to go with the M8 series as it is durable but wasn't sure if I should stick to B-coding or A-coding.
AI: Engineers follow industrial standards.
The canonical source in this case is CANopen CiA 303-1, chapter 7.2 which specifies A type. This applies to M12. If you use M8 then go with the very same pin-out and coding. See the pic below. The square means A coding. |
H: Control one relay via multiple 12 V DC signals
I'm seeking help designing a circuit wherein we would have multiple 12 V DC signal inputs, with the goal of:
If one or more 12 V signals is ON, the main relay is energised and closed.
Basically, we have a vent fan that serves multiple appliances. When any appliance reaches a specified temperature, it sends out a continuous 12 VDC signal. This is intended to activate a relay to run a ventilation fan.
Because of the number of these appliances in use, we use one large fan, ducted to all appliances. We are manually switching the fan on and off at this time but I am aware of the 12 V heat-triggered output on each appliance and would like to take advantage of it (especially so the fan doesn't run all weekend when not needed).
What exceeds my knowledge is how to design the circuit with an "any or all" function, where either, any one 12 V signal by itself, or any number of 12 V signals at once, would turn on a relay.
(total # of collectively vented appliances, each with its own 12 V sender, is 7)
Each signal is sent via a two-wire DC lead (pos & neg).
Thanks in advance for any comments/thoughts.
Edit: the 12v signals need to be isolated from one another, so the most basic way I've thought of doing this is to have 7 "pilot" relays, one for each incoming 12v signal, and those relays would be switching a single "bus" 115v current that subsequently activates the main relay. But I am wondering if there's a better/more efficient design that would work.
AI: Since you need isolation, you will need a relay for each appliance.
Even if you didn't strictly need the isolation, it would be recommended since it might be hard to safely share the same voltage (ground) reference among all 7 appliances.
I would locate the individual relays at each appliance and only bring the parallel combination of the relay contact outputs to the fan control circuit. That way you won't have to worry about a voltage drop in the 12V circuits due to wire length.
Here's a schematic for two appliances. Expand for more.
simulate this circuit – Schematic created using CircuitLab |
H: Multiplex Controllino (Arduino) 0-10V input using SSRs
I have to read six 0 - 10 V analog signals but I only have one 0 - 10 V input on the Controllino. I figure I could use six solid state relays and multiplex the signals.
When a relay is on it'll allow only one signal through then I turn it off and move on to the other signal and so on.
However, with multiple SSRs connected to the input when one analog signal changes the others also change in the same direction. I.e. if the input voltage goes up, the rest of readings also go up (though not by the same amount)
I think the output capacitance of the SSR may be affecting me here. I tried adding a pulldown resistor but that didn't work. I slowed the readings down to 2 s and that also had no effect, I imagine because the capacitance has no path to discharge.
I'm not sure how to address this (apart from not using SSRs) but I'll take any recommendations. See below for my schematic, the editor didn't have an SSR symbol so I used a regular relay.
simulate this circuit – Schematic created using CircuitLab
AI: Two parameters suggest that an SSR is not a good choice for this application.
Table 1. From the datasheet.
An analogue switch would be a better choice. You may need to add a potential divider for each input. The CD4016 is one such device that I used 40 years ago. I'm sure there are others now.
Can you also add in an explanation as to why those parameters and their values would mean that I shouldn't use it in this application?
I don't understand the minimum load current specification myself. I would have expected the FET to behave like a resistor independent of current.
The leakage current will allow up to 1 μA through the device and this will charge up the input capacitance on your ADC. |
H: Can I switch 85V / 3kHz AC using this solid state relay?
I got this part, and I am wondering if I could use it to use it to switch ~85V @ 3000Hz.
It's not working though, and the label on the chip says 50 Hz.
Is frequency the reason it's not working?
I have ~4.8V on the "Channel 1" pin (brown wire), but I cannot measure any output, nor does the EL-wire light up, that is attached (black wires.)
AI: The datasheet only says 50/60Hz and there are no frequency characteristics listed beyond that. It does say that its based off of the M0C2A-60 triac (of which there is no information for) but many triac circuits are 'tuned' with snubbers for zero crossing detection. A different frequency than 50/60Hz would interfere with the zero crossing operation.
I'd just say use a 'normal' relay. Another form of SSR that might work are the ones based off of FETs. |
H: Dimensions of Hakko FX-888D heater
I accidentally bought a look-alike of the Hakko FX-888D. The supplier's Ts&Cs included prohibitive conditions around a refund, so I'm trying to live with it. I don't want to send good money chasing after bad, so I'd like to figure out if there are any genuine Hakko tips I can use.
The tip fits over the ceramic part of the heater - the white part in the photo. The dimensions (measured using the ruler in the picture) of visible part of the fake heater are:
diameter (green line): 3.5mm
length (yellow line): 25mm
I've spent some time on the Hakko website trying to find the comparable dimensions of the genuine product, but it hasn't been very productive.
What are the comparable dimensions of the Hakko FX-888D?
AI: I've measured the iron I use at work (a genuine Hakko FX-8801, the iron that goes with the FX-888D station), and the exposed ceramic heating element has a diameter of 3.8 mm and a length of 22.5 mm. The tips should fit your iron, though they may be a looser fit than the genuine one (on which they are already a somewhat loose fit, anyway). |
H: Are impedance calculations only specific to sinusoidal inputs?
All impedance formulae we've derived in my course and calculations e.g. combined impedances in series have all assumed sinusoidal steady state.
My question is, does the notion of "impedance" exist for other period functions other than sine waves e.g. a saw wave? Or are the reactance calculations only relevant for sinusoidal inputs?
AI: Impedance as the math law between current and voltage is generalized with Laplace Transforms to arbitary currents and voltages - no need even be periodic ones. For example an inductor with inductance L has Laplace domain impedance =sL where s is the complex number variable used in Laplace transforms. Of course, it's not useful to calculate the numeric value of sL except in certain special cases. That useful case is fixed frequency sine voltages and currents as you obviously guessed. The sL is used in formula derivations.
Impedance is used in a mathematically rigorous way more widely than in electric circuits. It's known in acoustics and electromagnetic field theory. For ex. the vacuum and approximately also plain air in radio frequencies have electromagnetic wave impedance about 377 ohm which is the ratio of the electric and magnetic field strengths which belong to the same wave in the same point at the same moment of time. There's no demand of sinusoidal time domain wave forms.
Then in lousy everyday talk we can say for ex. "the speaker has 8 ohm impedance". We talk about a nominal value. With a certain sinusoidal voltage the actual electric impedance may be that 8 ohm, but generally it's something else depending on frequency. We call it still 8 ohm speaker. |
H: How to set up an oscilloscope with a 10000 turns 0.05A transformer and an AC power supply, in order to generate a hysteresis curve of the transformer?
I am a high school student investigating how varying the current output affects the shape of the hysteresis curve of a transformer.
To measure the hysteresis curve of the transformer's core, I tried to connect my digital storage oscilloscope with a transformer of 10000 turns 0.05A. I also tried to connect them to my AC power supply. I plan to vary the AC current to see how it would affect the shape of the hysteresis curve's shape.
I am unsure about how to connect all three of them together.
The oscilloscope is already set in the XY mode.
Here is the equipment. Am I missing any necessary equipment? How should I set them up?
AI: The SATZ ZP9130 power supply pictured is a DC power supply. You can't directly connect it to the transformer to measure the hysteresis curve - you need AC for that. You could use a simple two-transistor multivibrator circuit to produce the AC from DC, and feed it to the transformer. But that's probably not what you were meant to do. You need to ask for an AC supply for this experiment :)
Now, perhaps you can be manually flipping the current direction by reversing the plugs and observe hysteresis based on such transients alone. In theory - sure. But those power supplies are rather crappy, so:
They can't really handle full current output for very long - their output stages overheat rather quickly.
Disconnecting the inductance of the transformer primary winding while current flows in the circuit will generate high "kick-back" voltage, and is likely to destroy the output stage of the power supply.
This will cause the pass transistor to fail shorted, i.e. it won't regulate anymore, and the output will be a DC voltage somewhere above 20V, and the voltage selector switch won't change it. You'll also lose the secondary overload protection in the supply that way, although it was lousy to begin with. |
H: RDS measurement on P-Channel MOSFET
I want to measure the Rds-ON of a P-Channel MOSFET and I have setup the test circuit as follows:
I keep the source at constant +10V and vary the step the gate voltage up in the increments of 1V. Then I measure the resistance across the drain & source. However, the RDS values I measure are around 5-5.6 ohms vs the 0.3 ohms as per datasheet. I am using 4 wire measurement and for N-Channel MOSFETs this setup seems to work. So I wonder why it apparently doesn't work for P-Channel MOSFETs.
I tried with other P-Channel MOSFETs and also get considerably high values. So it's not just one MOSFET. For a rough comparison, I tested it on a component tester and even that gives lower RDS ~ 1-1.5 ohms. I understand that I can't trust the component tester results too much but it should be ok for indicative results.
What could be going wrong with the measurements? and is there a better way to measure RDS that would give me accurate results?
AI: A much better way to measure RDs would be to use a power supply in current mode and step the current, at each current step also record the voltage, you'll get a current to voltage plot and the slope of that is RDson. You could then do that for each gate voltage step.
It's probably better to fix the gate voltage and then vary the voltage and current.
A more comprehensive description is found here: https://goughlui.com/2020/04/20/experiment-measuring-mosfet-rds-vs-vgs-with-a-power-supply-rs-ngm202/ |
H: Driving a raw Dot-Matrix LC Display
So, I have this raw 32x32px monochrome reflective dot-matrix LC panel which I got from a toy. It looks like this:
I would like to drive it in my own circuit. I know how to drive LED matrices using shift registers etc. However the display in question has not 64, but 84 pins. The part number on the back is JS171012, but for that I have found zero results on the internet.
Is it possible to find out what those extra 10 pins do (I assume some of them are GND and VCC?) and use this display in my circuit? I'm using an ESP32 as my microcontroller, and I have a CPU core free so I can do the constant updating on there.
AI: Driving a LCD display is a lot like driving a matrix LED display with some differences.
Like an matrix LED display or a multi digit seven-segment display, the LCD elements will be organized into groups which share a common pin. These groups are often referred to as "backplanes". So your first task will be to identify those groups and the common pins.
Then you can refer to this Microchip app note:
AVR241: Direct driving of LCD display using general IO
http://ww1.microchip.com/downloads/en/AppNotes/doc2569.pdf
Basically you generate the AC wave form by connecting two GPIO pins to the two ends of the LCD element and toggle them either in phase or out of phase with respect to each other. In phase means the GPIO pins have the same output, out of phase means they have the opposite output level -- i.e. when one GPIO pin is HIGH the other is LOW and vice-versa. If the GPIO pins are in phase the segment will not be energized and if out of phase the segment will be energized.
You need to keep toggling the GPIO pins, and that can consume a lot of microcontroller's time if it doesn't have dedicated hardware to help it. That's why LCD driver chips (e.g. like an NXP PCF85162 or similar driver) is usually used.
Driving a large number of LCD elements also require a lot of I/O pins which is another reason why the task is off-loaded to special driver chips. But driving a small number of segments is feasible with the average MCU. |
H: How do I fix my induction motor speed control circuit?
I have designed a speed control circuit for an induction motor. The circuit consists of a zero cross detector circuit whose output pulse is the input to a 555 timer. The 555 timer is used to generate a PWM wave that is then inputted into an optocoupler. The TRIAC control circuit then applies a chopped AC waveform to the induction motor. The 1st picture is the chopped waveform (incorrect) applied to the motor (used lamp in multisim as there is no motor), the 2nd picture is how the chopped waveform should look and the 3rd picture is the circuit diagram. I am having trouble (with the negative half cycle) with getting the waveform in the 1st picture to look like the correct waveform in the 2nd picture. Can you guys please help me fix the design?
AI: The opto-isolator you are using will not function correctly when the voltage is reversed.
The base-emitter junction of the isolator will break down with only a few volts negative and then drive current into the triac so turning it on and giving the result you are seeing. |
H: Short circuit analysis
Im given the next distribution line with a generator and a load
The generator is set at \$23\,kV\$ the line impedance is \$9.5\Omega +j19.055\Omega\$ and the aparent power is \$1.5MW+j2MVars\$ in the load and the load voltage is the \$20.44\,kV\$ of the picture.
Now the idea is to check it for short circuit conditions, and I have been told the program can't simulate it.
So I'm guessing the load has to be disconnected/opened. If there is no load all the power is going to bus 2(I'm supposing bus 2 is grounded) but then if there is no load in bus 2 then only a small fraction of (real) power would be consumed by bus 2 and the transmission line.
Thats the correct power flow idea?
Also how can be calculated the aparent,reactive and real power of the line and the generator under these conditions?
AI: Usually when we do fault calculations we ignore load flow and assume the voltage behind reactance of the generators have a flat profile (all 1.0 or 1.05pu etc). You could also use the load flow first to find that prefault generator emf if desired for the particular load level of interest.
Depending on the time frame of interest (sub-transient, transient, or synchronous) you would use the appropriate impedance for the generator (e.g. \${X_d}'', X_d’, \text{or}\, X_d\$).
What you will find is that for three-phase faults at your load bus the only power out of the generator will be \$I^2R\$ losses in the generator windings and transmission line. No power can be transmitted through a three-phase zero-voltage fault so nothing gets to the load. You will find that most of what you will see is reactive power to the fault.
$$P=\frac{EVsin\theta}{X_T}$$
$$Q=\frac{E^2-EVcos\theta}{X_T}$$
Where \$E\$ is sending end voltage, \$V\$ is receiving and voltage, and \$X_T\$ is total reactance between the two buses (neglects resistance).
For a simple system like you show, the calculation for a three-phase fault is easy. For unbalanced faults you can work by hand using symmetrical components easy enough. Actually, since you don’t have any transformers it would be easy to just do any of these using three-phase variables.
UPDATE: Answering comment question about three-phase fault calculation.
In this example the voltage behind generator reactance is \$1.0\$ pu. The machine reactance used is the subtransient \$X_d''=j0.20 pu\$ and the line impedance is \$Z=j0.1375 pu\$. This example is from my lecture notes on symmetrical components. The three-phase fault is just as easily solved without symmet. |
H: Does a floating load on a transformer have no voltage difference with ground?
I think I know the answer, but I'm unsure. I'm studying for my FE, and in the practice exam is the following question:
An ideal transformer connects a 120-V, 60-Hz voltage source to a load. One terminal of the voltage source is grounded. The load is ungrounded. The circuit and transformer are operating normally (not in a fault condition). A person whose body is contacting the ground is in proximity to the circuit. If the person touches the circuit, which point likey has the highest risk of resulting in shock?
simulate this circuit – Schematic created using CircuitLab
The correct answer is A. I can justify this in several ways, but what confused me was the explanation in the back of the practice exam: It says that point C and D have no differential voltage to ground.
Could someone please explain why this is the case?
My hypothesis (formed from half remembered lectures) is that because the transformer is inducing a current in the secondary coil, the current must flow through the coil and cannot flow through only part of it to jump to the ground.
AI: The transformer secondary current is fully contained in the load and in wires C and D. There is no loop formed to ground (ideal transformer, wires and load, no stray leakage.)
If a grounded person touches the secondary at a single point, that point will assume the GND voltage, but again since there's no loop between the (grounded) primary and secondary, no current will flow to GND or through the person (only by definition of an ‘ideal transformer.’ More about that below.) They could touch the secondary anywhere, so long as they touch it at single point.
Given one and only one point ground on the secondary, the rest of the secondary loop will be at different voltages than the contact point. If a second ground-referenced contact is made to one of those different voltages on the secondary, there will be current. But that's not the case being asked.
This quiz question notwithstanding, a real system with leakage and capacitance will actually have both a transient current when you touch the secondary as its capacitance is charged to the ground voltage, and a continuous leakage current coupling from primary to secondary.
There are regulations that set limits on this leakage to non-hazardous levels for consumer devices: 3mA for isolated low-voltage devices, like a USB power adapter.
Higher-voltage secondaries will have hazardous levels of leakage even if they're fully floating just because of their physical size, and so are usually grounded and/or insulated against accidental contact.
tl; dr: even a 'floating' secondary can kill you. Use caution. |
H: Superglue on plug
I was fixing a junky device whose charging cable fell off, And when I superglued it back on, I accidentally got some inside the connecting area (?) and it will no longer charge. What’s the best way to remove the superglue?
AI: Try to scrape it off the gold parts without damaging the gold or the plastic too much.
A wooden toothpick dipped in acetone may work well for this.
These gold parts are the contacts that are used for charging, the nickel plated parts are less important |
H: ATtiny13A - PWM x 3, ADC x 2
I want to control 1 RGB LED and 2 potentiometers by ATtiny13A.
I want control the RGB LED by 3 PWM ports and read values of 2 potentiometers by 2 ADC ports.
Is it available by ATtiny13A?
Can I program it by Arduino?
AI: ATTINY13A with only 512 program words is a bit small for arduino
and it has only 2 PWM outputs (so you'll be doing the third in software)
if you want a challenge it's probably possible to accomplish your task. |
H: What happens when an electrical load is supplied to a motor via a switch and the motor doesn't turn?
I'm not from an electrical engineering background. But I'd like to understand what happens when I have the following:
Electrical 'main power' switch ------> 'small switch' ------> electrical motor
In this case, when both switches are ON but the electrical motor is faulty (it doesn't turn, just buzzes) what is happening to the electrical load (if that's the correct term). I expected the electrical motor to start smoking in this scenario but it was the 'small switch' that got fried. The 'small switch' had an Input voltage of AC 90-250V 50/60 Hz and a Max. load: 10 amp. Neither of which would be exceeded by the 'main power' switch.
AI: The current through a stalled (not rotating) motor is much higher than the current when it gets up to speed because the rotation of the motor produces a back-emf that opposes the supply voltage and reduces the current to less than you would expect just from the resistance of the motor windings.
Normally, as you said, it's the motor that gets hot and possibly becomes damaged in this situation, but in your case it seems that the switch gives out first — probably the motor's stall current exceeds its 10 amp rating. Which indicates that this is not a very safe switch to use with this motor, or that the switch needs to be protected by a fuse or circuit breaker that will trip at 10 amps or less. |
H: Will this circuit work on a Raspberry Pi?
There a lot of articles on websites regarding the use of LDRs connected to a Raspberry Pi. As an example, using an ADC or using a built in library.
I'm interested with my own design below and since I do not have a Raspberry Pi, I do not know if this work.
Theoretically, will this work and has anyone tried this before?
In this circuit, I using an open loop gain comparator with 3 different voltage references: 1V,2V and 3V. When the LDR is at low brightness, U2A will turn on as shown below, at moderate brightness, U1B turn on and- at full brightness all opamps turn on giving out 2V output voltage
Example:
At low brightness, U2A will turn on give 2V.
These three opamps are connected to 3 GPIOs of a Raspberry Pi which are set as input.
The pseudo-code below will display the seven segment by output result 1,2 and 3:
if(pin7==high&&pin8=low&&pin9==low)
{display 1}
if(pin7==high&&pin8==high&&pin9==low)
{display 2}
if(pin7==high&&pin8==high&&pin9==high)
{display 3}
AI: Your U1:A is exceeding its maximum input voltage: The LM358 wants at least 1 V (datasheet ON Semi, Fig. 4, p. 6) headroom between positive input and supply voltage, and you only have 0.5 V. |
H: Can any AC circuit be treated as DC by using complex numbers?
I am a physics undergrad, looking for ways to solve complex circuits efficiently.
I have recently started to learn about complex number applications in AC circuits and its advantage over phasor methods.
What I want to know is that suppose I am given a complex AC circuit and I am required to find its impedance and phase factors. Can I do this by imagining the AC circuit to be a DC circuit at every instant, treating capacitors and inductors as if they were resistors and following the parallel/series combination methods of resistance addition?
Note: I am mainly interested in sinusoidally varying voltage sources and resistors, capacitors and inductors.
Please forgive the question to be too obvious as I am from a physics and not electrical engineering background.
AI: Can I do this by imagining the AC circuit to be a DC circuit at every instant, treating capacitors and inductors as if they were resistors and following the parallel/series combination methods of resistance addition?
Yes, but it would be better to use more accurate language, it will be less to unlearn later.
Treat inductors and capacitors as impedances. The combination of impedances in series and parallel follows the same formulae for that of resistances in series and parallel, which are just pure real impedances.
This is how a simulator like SPICE computes the AC gain of a circuit at a particular frequency. It computes the impedance of each component at that frequency, then generates a large impedance matrix to give all the voltages as impedance * currents, and solves the resulting system of equations, all in complex numbers. This is why a zero impedance loop, or a floating node, will give you a 'singular matrix' error. |
H: Power output of a CC amplifier
I've been learning about electronics from the book Electronics Fundamentals, and have just finished the chapter about BJTs. Decided to put the newly gained knowledge to use and designed the following ASK transmitter \w an amplifier to play around with Arduino.
Will the transmitted power output be ~100mW and can it be improved?
AI: Your supply voltage is 5 volts - take note
To get 100 mW out into a 50 Ω load you need an output RMS voltage of \$\sqrt{100\text{ mW} \times 50\text { }\Omega}\$ = 2.236 volts.
This has a peak value of 3.162 volts and therefore a peak-to-peak value of 6.324 volts i.e. greater than your 5 volt supply rail.
Will the transmitted power output be ~100mW and can it be improved?
No, your power output will not be 100 mW - it might reach 63 mW on a good day because that's all the voltage you can extract from a 5 volt supply without using a transformer or a larger supply voltage. |
H: How frequency-dependent is an air inductance?
For a winding on a magnetic material, the value of the inductance is greatly impacted and is also frequency-dependent given the behavior of the magnetic material according to frequency. My question is, for a winding with no magnetic material, does the inductance vary with frequency? If yes(*), how can I explain it?
(*) I am more inclined to say that the permeability of the air does not vary with frequency. I am not sure though..
AI: When frequency rises both the inductance and the resistance of any length of wire changes, even if there's no magnetic core (dry air at normal pressure has almost the same permeability of vacuum).
This is due mainly to skin effect and proximity effect.
There is a math-heavy explanation of the phaenomena here: The Influence of Frequency upon the Self-Inductance of Coils - by J.G.Coffin, Clark University, Worcester, Mass. (this is a scan of an old document, but references basic EM theory).
Excerpts:
When currents of low frequency pass through the wires of a coil, the
current distributes itself uniformly over the cross sections of the
wires. With increasing frequency,this uniform current density no
longer prevails, but, as is well known, at least for straight wires,
the current density becomes greater at the surface of the wire at the
expense of that of the interior. The corresponding lines of magnetic
force become differently distributed, and in consequence the
self-inductance suffers a change. A short calculation will show the
direction and amount of the change for circuits in which the curvature
of the wire may be assumed negligible, and the theory derived for
straight wires used. The theory of this distribution of the current
density in straight wires, which has been thoroughly worked out by
Lord Rayleigh and by Stefan, is not applicable without modification to
the distribution of current density in coils of wire. The following
argument shows that the effect of increasing frequency is to diminish
self-inductance.
Here is another relevant article.
Excerpts:
Whenever you alter the path of current, you
alter the inductance. Because the skin effect modifies the
distribution of current within the conductor, it must also change the
inductance of that conductor. You can observe this in very careful
measurements of transmission-line inductance at high and low
frequencies.
[...]
POINTS TO REMEMBER
The distribution of current at high frequencies minimizes inductance.
At DC, the path of least DC resistance creates a slightly higher inductance.
Good models for skin effect take into account changes in both resistance and inductance with frequency. |
H: Why is my op-amp integrator charging up to the DC voltage supplied (instead of the rails)?
This is the op-amp integrator I am simulating. Theoretically I should get a ramp signal saturating at the op-amp rails, however I get the signal shown. Can anyone help me understand why?
AI: The presence of the feedback resistor \$R_5\$ means that this is not a mathematically "ideal" op amp integrator, which would have infinite gain at DC. The circuit is a "practical" op amp integrator which takes into account the non-idealities of a real op amp (finite gain, input bias currents, output cannot exceed the power supplies, etc.). In a "practical" op amp integrator a feedback resistor is placed in parallel with the feedback capacitance, which lowers the DC gain and prevents the op amp from saturating at one of the power supply rails.
In this case the DC gain is $$-\frac{R_5}{R_6} = -1$$
This can be deduced by inspection, noting the fact that at DC a capacitor is an open circuit so at DC the capacitor can be removed and all you are left with is a simple inverting amplifier. Therefore, with a 3 V DC input the output is -3 V at steady state. If you increased the DC gain and/or reduced the power supply voltages and/or increased the DC input's amplitude then you would eventually see the op amp saturate. However, you generally want to avoid letting the op amp saturate so it's a good thing that this practical op amp circuit does not cause the op amp to saturate. |
H: Output capacitors of DC-DC converters
I am trying to understand what type of output capacitor is a better option.
Suppose I require a 10uF output capacitor at the output of the buck converter, which one should I pick - aluminum electrolytic , ceramic or tantalum? (All SMD.)
I read that the aluminum has good ESR which would help in the stability of the DC-DC control loop, but it is big in size. So, size is the disadvantage over here.
Ceramic capacitors have 100 times smaller ESR when compared to the aluminum one, and they come in very small sizes. So, this is an advantage when size is a bigger constraint.
I couldn't find any big advantages or disadvantages of tantalum. Can someone tell me the benefits and disadvantages of using tantalum?
Please also tell me which cap would be ideal for the DC-DC converter output - aluminum, ceramic or tantalum?
AI: I would avoid tantalum unless you have no other option; one of their more common failure modes is to burst into flames.
I don't know where you read that aluminum electrolytics have good ESR compared to ceramic, but they just flat-out don't; they tend to have some of the highest ESR of any capacitor type. Even low-ESR aluminum caps can be multiple orders of magnitude higher ESR than comparable MLCCs or film capacitors.
For an application like this, I would use an MLCC since the exact capacitance value doesn't matter, and it isn't too large; 10 μF MLCCs are pretty cheap. If you needed much more than that, though, aluminum electrolytic would be the way to go.
I'd also like to note that you overlooked one very important type of capacitor: film capacitors. Film caps tend to be available in larger capacitances than ceramic, are more stable with temperature and applied voltage than high-κ ceramics, are available in higher voltage and temperature ratings than MLCCs or electrolytics, and have comparably low ESR to ceramics. It wouldn't be worth the price to use for just an output filter capacitor, but whenever you need something stable and high-performance, film is often the best choice. |
H: What electronic component can send pulses?
In analog hardware synthesizers, an electric pulse is sent by an oscillator to a sound-emitting device for it to create sound at the desired frequency.
What device generates this pulse?
What is the standard schematic symbol for this electronic component?
AI: These circuits can vary and there is no specific single component , electrically, that can be pointed to as the "output", it is usually a circuit, which might be integrated into an IC or other device.
Quoting from another answer of mine on an unrelated question https://electronics.stackexchange.com/a/550721/1729
It is important to understand, ahead of time, what your work product is trying to communicate, an electrical design consists of many different documents and deliverables. A schematic as a design asset needs to be specific as possible. It is simultaneously defining the implementation and serves as a documentation for other designers. In extreme cases some professional shops go as far as define a symbol for every part number. A simplified schematic has a different use case (publication in academic paper) than a production worthy schematic.
If you are making certain types of system diagrams it is ok to use generic symbols for various elements. With the knowledge that they convey incomplete information.
For example a pulse source can be pulse square wave inside a circle. Generally a symbol inside a circle is indicating to a reader that there is more complexity inside the device. |
H: KVL in the frequency domain - Why is the sum of phasors 0 and not just the real part of the sum?
In many proofs of Kirchhoff's voltage law for the frequency domain, the time-domain KVL is originally used and then the time-dependent part (\$e^{jwt}\$) is removed, leaving only the real part of the sum of phasors to equal zero, for example in the textbook "Electric Circuits" by Nilsson and Riedel:
$$v_1 + v_2 + ... + v_n = 0$$
$$\therefore Vm_1cos(wt+A_1)+Vm_2cos(wt+A_2) + ... + Vm_ncos(wt+A_n)=0$$
$$\therefore Real [(\vec V_1 + \vec V_2 + ... + \vec V_n)e^{jwt}]=0$$
Then, this "real part" notation is simply removed, stating that the sum of phasors is simply equal to zero.
$$\vec V_1 + \vec V_2 + ... + \vec V_n$$
Why is this the case? Where can this be proved?
AI: The expression
$$\text{Re}\, [(\vec V_1 + \vec V_2 + ... + \vec V_n)e^{j\omega t}]=0$$
must hold for all values of \$t\$; this means that it needs to hold when \$e^{j\omega t} = 1\$ and when \$e^{j\omega t} = j\$ (as well as all linear combinations of the above); this is only satisfied when the sum of the complex phasors is zero (both real and imaginary parts) |
H: Polarity of fuse? Amptrap A30QS500-4
Could someone explain reason behind diode pictogram (symbol) on an Amptrap A30QS500-4 fuse?
Why would a fuse have polarity, does it?
How can I find the polarity of it? I tried to check it with multimeter and it buzzes on both orientations.
AI: Well, you learn something new everyday.
The symbol means it is a fuse intended to protect semiconductors.
From page 5 of this Eaton Protecting semiconductors with high speed fuses application guide:
The fuse you have is definitely a semiconductor protection fuse. The Amptrap A30QS500-4 datasheet is clear on that point:
A30QS Amp-Trap® high speed fuses are intended for the protection of Power Semiconductors such as diodes, phase control SCRs and other power semiconductor devices. The A30QS is recommended for new applications providing solutions for your critical protection needs at 300V and less semiconductors.
The "aR" indicates what specific task the fuse is for:
aR class fuses only provide partial-range breaking capacity (short-circuit protection only) for the protection of power semiconductors (IEC Utilization category). Note: aR fuses are often faster (with a lower I²t value) than a comparable gS or gR fuse. An aR class fuse must not be used as a replacement for a gR class fuse. |
H: Lser of capacitor not equivalent to a separate inductor in LTspice?
I just noticed a strange issue in LTspice and I am wondering what I am doing wrong. This is about capacitors with series resistance and inductance:
Example 1: A simple bandpass. Behavior seems ok.
Example 2: same circuit ?! The cap C1 has Lser=1n. Behavior is different
Why?
AI: It looks like just by adding Lser=1n inductance the LTspcie decided (by default) to add some parallel capacitance.
\$C_{par} \approx \frac{1}{4\pi^2F^2 * L} \approx\frac{1}{4*\pi^2*16GHz^2*1nH} \approx 0.0989pF\$
To check this try to set Cpar=0 in LTspcie. |
H: Problem simulating electrolytic capacitor at high frequency (GHz+ range)
simulate this circuit – Schematic created using CircuitLab
I am simulating a circuit in LTspice in which I use an aluminum electrolytic:
C=100µF, Rser=0.25, Lser=5n
Due to some other components, I now see an L-C resonance at several GHz in AC simulations, which runs through the L of the electrolytic and small parasitic C of some other components, effectively about 1 pF.
From experience, I know this is absurd. An aluminum electrolytic doesn't participate in such high frequency resonances. Its series resistance seems to be very large at high frequencies and in fact I use them to damp resonances.
How can I tune the circuit model of the electrolytic capacitor to get a more reasonable high frequency behavior?
Merely raising the series resistance makes it useless at normal frequencies of course. Is there a comprehensive way? (For example, multiple components or other methods.)
(Might be related)
AI: I don't know where you are seeing the pole past 1GHz, here is my sim:
I did add some series resistance on the voltage source, because in the physical world you'll have at least 10mΩ on any source.
One thing that could be happening is cshunt could be changing things (it adds a capactior to ground on every node, which is more realistic for a PCB as each trace will have some capacitance to a ground plane if you have one in your design) Also the above plot is with cshunt disabled, in the one below cshunt is 1pf. One problem also would be the return path inductance/resistance to the source which would need to be modled. Also I would suspect you would need transmission lines to carry any kind of GHz bandwidth.
When all is said and done GHz get's filtered out pretty quick in the real world as any kind of copper has parasitic inductance and that would impede GHz signals
If you are looking at the GHz+ range, you would probably want to model each element of the capacitor and its capacitance to a local plane on the PCB, I kind of did this in this answer here. Why does Samsung include useless capacitors?
(and take each volume of the capacitor and PCB and come up with a parametric model for the whole capacitor) YMMV because materials also make a difference so it would probably be best to analyze it with a network analyzer or GHz source (which I have no experience with).
Edit:
One interesting thing is adding ESR and ESL of the wire with cshunt and I did get the frequency to 'pop'.
While I think you could get some resonance on the PCB, I think you'd have to get a much detailed model (the input from the voltage source needs to be a waveguide/transmission line because attenuation would sink most GHz signals)
here is also this one where cshunt is negated and I added in two 1pf caps and it looks much more normal, the real world could be somewhere in between the model above and below |
H: How to calculate the maximum PWM frequency of a MOSFET switch circuit?
How do you calculate the maximum PWM frequency of a P-channel MOSFET being used as a switch?
The driver is a PMD3001 totem pole IC.
The P-channel MOSFET is a DMP3007.
AI: Determining the maximum frequency at which this circuit can operate isn't that easy.
However, there are some speed limiting factors we can have a look at:
How fast can we turn the MOSFET on and off? The MOSFET gate behaves somewhat similar to a capacitor. In the datasheet we see a value for "input capacitance" on page 2, this \$C_{in}\$ = 2.8 nF.
A current is needed to charge/discharge this gate capacitance. The maximum current which the PMD3001 can deliver is 1 A (yes, there's also a 2 A stated but that cannot be repeated like it is when using PWM).
Suppose the gate capacitance of the MOSFET is fully empty so 0 V and the supply voltage is 24 V. Now we want the driver to charge the gate as fast as possible so we pull the output of the driver to Ground. Assuming that the driver behaves like an ideal switch, there would be 24 V across R1. That means 24 V / 10 ohm = 2.4 A flowing. Oops! That's more than the PMD3001 can handle! You need to limit the current to 1 A. So we need R1 = 24 Ohm.
If you would use a 10 V supply, then 10 Ohm would be OK.
So we're charging a 2.8 nF capacitor with 1 A. If we then also use a supply of 10 V the charging will take approximately 28 ns. You want this charging to be a small part of one PWM cycle so let's assume that this 28 ns is only 1% of a complete cycle. Then the cycle time would be 100 x as large so 2800 ns. A repitition rate of 2800 ns means a frequency of 1/2800 ns = 357 kHz.
This is a simple "first order" calculation with lots of assumptions so there are no guarantees!
You would do better to put this circuit in a simulator (like LTSpice) and simulate it!
Then you would also discover that this circuit is not going to work properly!
Why is that? Let me draw the schematic on a transistor level:
simulate this circuit – Schematic created using CircuitLab
The PMD3001 you selected only contains an NPN and a PNP which are configured as a "totempole driver". Both transistors operate as emitter followers and that means they do not amplify the voltage.
To fully switch off your MOSFET you would need to apply the full supply voltage (5 V - 24 V) to its gate. This circuit cannot do that unless your PWM signal rises to the same voltage (5 V - 24 V).
If you would apply a PWM signal of 0 / 3.3 V then the MOSFET will never be off. That's not what you want I guess. I suggest that you find a more suitable driver. |
H: KiCad footprint for a diode
How do I determine what kind of footprint is needed for the RBR20NS60A diode? Its datasheet is linked here.
AI: The Datasheet states the footprint, right on top of the first page:
Package Code TO-263S
JEITA Code SC-83
ROHM Code TO-263S
So, that's your footprint. Look for TO-263S or SC-83.
Either your EDA tool has a footprint like that, or you'll have to design it yourself; no big deal, really, in Kicad that's not very hard; page 6 of the datasheet shows the recommended pad pattern. |
H: Why is my LED circuit drawing 50% more mA than I calculated?
I am having trouble with an LED circuit I am designing.
I am supplying 24 volts from a benchtop supply and have 7 blue LEDs (datasheet) and an 82 ohm resistor in series.
I calculated that with a forward voltage of 3.2V and a 20mA forward current I would need an 82 ohm resistor and my circuit should draw 20mA. According to my supply I am drawing around 30ma.
I tried with a digital multimeter and got the same result.
What am I missing? Is it just possible that both of my meters are wrong, or is this to be expected and this is just fine?
Ultimately this will be a flashing light bar for an RC car.
I included the transistor in the schematic below but even when I isolate just the LED and resistor part of the circuit I run into the same issue.
AI: This is almost certainly within tolerance of expected behavior for these LEDs.
A quick way to see this is to do a back-of-the-envelope sensitivity analysis.
What's the current if the LED forward voltage drops are exactly 3.2 V each (the datasheet "typical" value)?
$$\frac {24 \ \text{V} - 7 \cdot 3.2 \ \text{V}} {82 \ \Omega} = 19.5 \ \text{mA}$$
What happens if the LED forward voltage drop is only 3.1 V each (an insignificant 0.1 V difference from a manufacturing tolerance perspective, since they're only promising 3.2 V typ and 4.0 V max)?
$$\frac {24 \ \text{V} - 7 \cdot 3.1 \ \text{V}} {82 \ \Omega} = 28.0 \ \text{mA}$$
So for your circuit design, we get +44% more current if the LED forward voltage drop is off by just 0.1 V.
(This analysis neglects the fact that the higher current would cause a slightly higher voltage drop than it would at the specified 20mA. However, it still shows that the overall current is very sensitive to the LED voltage drop.) |
H: How does a transformer operate with a short in the windings
I'm trying to learn more about transformers that are failing. From my understanding transformers create heat. From too much load or current on the secondary side of a step-down transformer, the heat can damage the insulation and cause a short on some of the secondary side turns.
Now that we have a short in one or a few of the windings. How does the transformer behave under normal rated conditions? Say the secondary had 90 turns and now has 88 turns from two shorts. It seems the transformer should almost behave the same as when it had 90 windings. This is the part I think I'm wrong. Do the shorted windings increase current heat loss? Do the shorted windings increase eddy current/hysteresis loss? Or do the two shorted windings have really minimal effect?
If it is true that a few shorts can have large negative effects, they would cause more heat and could potentially lead to more insulation damage? My other assumption is that extra heat from the damaged secondary would be noticed in a decrease of output voltage because the transformer is getting very hot then its internal resistance will increase.
AI: So the key here is the difference between shorts on the primary winding and the secondary, which each behave very differently. Your intuition about shorting only 2 windings being negligible makes some sense if we are talking about the primary, in fact we do that with inductors all the time to adjust its inductance, just short out part of the inductor.
Consider that in a secondary however that if you short the entire secondary, as one would expect, you will get thermal runaway just as shorting any power source directly might cause. You will have huge currents running through that will burn everything up as its limited only by the resistance of the wire.
But consider now a secondary with 2 turns shorted and 98 behaving normally. In this case you have the 98 acting as a normal secondary, nothing special there. But the 2-turns that are shorted acts like a second secondary (for lack of a better term) but this secondary is shorted and just like shorting any secondary will induce a large current flow limited only by the wire resistor and ultimately thermal runaway.
So in short, the reason a short on the secondary will be so devastating so quickly is because the shorted portion will act like an independent secondary that has its outputs shorted and thus induce high current and glowing red wire. |
H: Reference input current value for TL1431CL5T voltage reference
There appear to be some mismatch for Iref value between the table and the graph for part TL1431CL5T. In the table it specifies the maximum value as 3uA where as in the graph it specifies as 1.7uA at -40C and 1.6uA at -20C. Can anyone please explain why the values between the table and the graph are different?.
Many Thanks!
AI: You have to recognize the difference between the typical values in a datasheet and the minimum and maximum values. The typical values are what you would measure in most of the parts and generally at room temperature. The minimum and maximum values are the guaranteed values that no part would exceed. In this case, the typical reference current is 1.5 ua as shown in the table at room temperature. The maximum value is 2.5 ua with no minimum specified. Over the full operating temperature range, the maximum could go as high as 3 ua. The graph is meant to show how the current varies over the temperature range for a typical part with a room temperature current of about 1.5 ua. If the actual reference current is different from typical (it could be higher and it could be lower), you would need to adjust the vertical scale to estimate how much the current would vary with temperature. |
H: How power Arduino Mega 2560?
I want to run Arduino Mega 2560 outdoor for long time.
I found this choices:
1 - 12 V power jack: It makes the board so hot so I skip it.
2 - Vin: It makes the board so hot so I skip it too.
3- 5 V pin: It worked. I heard it makes Arduino unstable because it bypasses the regulator inside it.
How can I solve this? Will 5 V pin work good?
AI: 5V pin will work good yes. this powers the MCU directly and without issues.
Regarding the issue of the "Regulator bypass",this may be a problem because you put 5V in the output of the Regulator (instead of its input).
IF the circuit is designed correctly, the regulator should have a diode (D1), which directs the 5V that you put in its output, to its input like this:
simulate this circuit – Schematic created using CircuitLab
Even if the diode is not there, It should not make the Arduino unstable. |
H: How is the current drawn by a Peltier determined for a given voltage and given Th?
I have 12V 20A SMPS for building a cloud chamber.
I have a question about configuring the Peltiers. I don't know how much current a Peltier draws for a given V at given Th (hot side °C)
In my understanding:
For example, a TEC1-12710 supplied with 12V, maintaining Th=25°C, has resistance of 1.08 ohm, so it draws I=(V/R)=11.1A. To get high Δt(around 55°c) the Peltier should draw 7.5 to 8A at 12V
I don't know how a semiconductor Peltier works at this step:
Please correct me if I wrongly understand the concepts.
AI: A peltier appears almost like a resistor. In your case, the resistor will be about 1.1 Ohm. Your question is, if driving it with 12 V is ok: Yes it is fine, and in fact almost the optimum voltage to achieve the lowest possible cold side temperature. The resistance will be also larger for higher current, and the 1.08 Ohm are likely given for a very small current. Even with the same Th, the resistance will rise as you push more current, because the semiconductor parts inside heat up.
Don't worry if the current will be 7 or 9 or 11 A.. You will put in a certain power, and the higher the power, the stronger the heat transfer. To maximize power you can do two things:
You have to establish good cooling for the hot side. A lower average temperature reduces resistance and increases power
Increase voltage, but 12 V is already plenty for this Peltier.
With good cooling at constant voltage of 12 V, you should reach Delta T of 60 K |
H: Pull-Up Resistor to 5V on 3.3V Output
I'm using a 74LVC245 buffer, which is a 3.3V chip with 5V tolerant inputs. What will happen if one of the chip's outputs is enabled and is connected to an external device with a 2K pull-up resistor to 5V? I welcome suggestions on other ways to do this, but I'm mainly interested in analysis of what happens with this specific setup.
simulate this circuit – Schematic created using CircuitLab
The 74LVC245 datasheet states that the voltage range applied to any output in the high or low state must be between -0.5V and VCC + 0.5V. There's also a footnote that says the output negative-voltage rating may be exceeded if the output current rating is observed. I assume this refers to the output clamp current, which is -50 mA for Vo less than 0V.
Here's where I'm confused. Whether the D0 output is either driving high or low, there will be a voltage drop across R1. Won't that keep the voltage at D0 always within the range allowed by the datasheet? If D0 is outputting a logical low value, the voltage will be 0V and current will be -2.5 mA (5 / 2K). If D0 is outputting a logical high value, the voltage will be 3.3V and current will be -0.85 mA (1.7 / 2K).
I'm particularly unsure about what happens when D0 is a logical high value at 3.3V. Current will be flowing into D0 - where does it go, and through what structure in the chip? Is there a clamp diode to the 3.3V supply here? The fact that the datasheet gives a spec for max clamp current below 0V but not above 3.3V makes me think there is not a positive clamp diode. So does the current just flow into the 3.3V supply through the output transistor? Is it likely to cause problems to have a small backfeed current like this, or is 0.85 mA too small for most worries? If it matters, this is a hobby-level project, not a scientific application requiring stringent specs.
AI: CMOS outputs are impemented with MOSFETs, which have parasitic body diodes.
However, the LVC logic family has "IOFF" circuitry to prevent a current from flowing into an output when the power is off. A current can flow into such an output only if it actively drives low or high; that current flows through the active MOSFET into GND or VCC.
(source: TI's How to Select Little Logic)
The datasheet specifies a current limit only for negative excess voltages because that limit applies to the diode between GND and the output; no such diode is active for positive voltages. If you apply a voltage above VCC to an output driving high, the current is limited only by the MOSFET's impedance:
(source: TI's Input and Output Characteristics of Digital Integrated Circuits at 3.3-V Supply Voltage)
Current flowing into VCC is usually a bad idea, because most power supplies cannot sink current. You could use a Zener diode (or better a TL431) to clamp the voltage, or connect a 3.3 kΩ resistor between 3.3 V and GND to shunt the excess current to ground.
If this is not a bidirectional bus, consider using a buffer with open-drain outputs (e.g., 74xx07); the pull-up ensures that the 5 V device sees a valid high level. Alternatively, use a level shifter to get proper 5 V signals. |
H: 20dB/decade vs 6dB per octave - Loop Stability
I am reading about the control loop stability of the DC-DC Converters.
And I read this criteria that the slope of the gain curve at 0dB (unity gain) should be 20dB/decade. But they don't tell why.
Question 1:
Can someone tell me why the slope should be that 20dB/decade and not any other value for the loop stability criteria?
And in some places they also use 6dB/octave. Like, why only these numbers : 20dB/decade or 6dB/octave? or in cases, multiples like 40dB/decade?
Question 2:
Can someone explain on why the slope is defined as 20dB/decade and 6dB/octave and not any other value?
AI: This requirement is is part of the (simplified) Nyquist criterion for stability. It is derived from the fact that the slope of the magnitude function is related to a corresponding phase shift (Bode relation). This rule applies for all transfer functions which have "minimal-phase" properties (no delay within the feedback circuit, no zeros in the right half of the s-plane).
This criterion says that a magnitude slope of -20dB/dec causes a phase shift of -90deg and a slope of -40dB/dec is related to a phase shift of -180deg.
Because a negative feedback loop contains already a phase inversion (-180deg) an additional phase shift of -180deg (equivalent to -40dB/dec) could bring the circuit to the stability limit (loop gain with 360deg phase shift).
For this reason, we require that at such a frequency (with 360deg=0deg phase shift) the loop gain must be below unity (0 dB). Alternatively, we require that at the 0dB-crossing the phase must not yet have reached the critical value of 360deg.
That means: When the magnitude slope at the zero-crossing would be, for example, -35dB/dec. the closed-loop would be stable - however, with a rather small safety margin (phase margin).
For a slope of -20dB/dec, we have a sufficient margin of app. 60 deg. For this reason, a good amplifier with feedback should have a loop gain with a magnitude that crosses the 0dB-line with a slope of app (-30----20) dB/dec
Comment: Sometimes people are confused because in some publications the loop gain phase contains the phase inversion (-180deg) at the summing junction and in some other publications the loop gain does NOT contain this negative sign. That is the reason for the two different formulations of the stability limit: Loop gain phase of -180deg or -360deg.
For my opinion, the negative sign should always be included because it is a part of the loop. More than that, there are feedback loops where the negative sign (for negative feedback) is NOT located at the summing junction but at any other place within the loop. Therefore, I suggest that the loop gain definition should always contain the minus sign - and the stability limit is based on the 360deg criterion.
Finally, tt should be mentioned, in this context, that loop gain simulations, of course, contain the complete loop (including the neg. sign). |
H: What is this SO8 part with all legs on one side connected together?
I believe this to be a voltage regulator of some kind (it's failed, and is resulting in a dead short straight through). However neither I nor Google Image Search is having any luck identifying the manufacturer mark. Does this look at all familiar to anyone?
(If anyone knows what the component is, that'd be even more awesome, but at least with the manufacturer I can look it up in their catalogue. Google doesn't know what a EDJ3207 is either, by the way.)
AI: While I was writing up the post someone looked over my metaphorical shoulder and said 'oh, yes, that's an Excelliance P-channel MOSFET, probably the EMB45P03' and handed me the datasheet. Sigh.
https://datasheetspdf.com/pdf/1111730/ExcellianceMOS/EMB45P03A/1 |
H: Transimpedance (I to V) converter using op amp
I was reading about the I to V converter using an op-amp.
Doesn't the addition of the \$R_{\text{L}}\$ resistor affect the \$I_{\text{R}}\$ current? Because the same current that flows through the feedback resistor would also flow through the \$R_{\text{L}}\$ resistor, right? If that's the case, what is the usage of the \$R_{\text{L}}\$ resistor and how would it not affect the working of the I to V converter?
AI: An ideal op amp has infinite impedance at its inputs but zero impedance at its output. That means that no current flows into its inputs, so by KCL $$I_{\text{R}} = I_{\text{in}}$$ regardless of anything else in the circuit.
However, because the op amp's output is low impedance it can either source or sink current as needed (which it will do in order to keep both its inputs at ground). Therefore, by KCL the current \$I_\text{L}\$ through \$R_\text{L}\$ is the sum of \$I_{\text{R}}\$ and the current sourced by the op amp's output -- which in general means that \$I_\text{L}\$ is not equal to \$I_{\text{R}}\$.
By Ohm's Law $$I_\text{L} = \frac{V_{\text{out}}}{R_{\text{L}}}$$
and, since the op amp's inverting input is at ground, we have
$$V_{\text{out}} = -I_{\text{in}}R$$
Therefore
$$I_\text{L} = \frac{-I_{\text{in}}R}{R_{\text{L}}} = \frac{-I_{\text{R}}R}{R_{\text{L}}}$$
The purpose of \$R_{\text{L}}\$ is to model the load resistance, which in general is not infinite. The fact that \$R_{\text{L}}\$ does not affect the operation of the transimpedance amplifier (except in an edge case like \$R_{\text{L}} = 0\$) is a good thing. |
H: How to calculate mAh draw from a battery?
I'm trying to calculate the "drained" capacity from the battery each second so I can get the nearest possible capacity used.
This is how I'm getting this.
dischargingCurrentSum - Is the sum of the "current" which I get every second, milliamps-second
For example
1s = 300mA
2s = 380mA
3s = 540mA
When I sum this it's 1220mAs
dischargingUpdateCount - Is the count of entries, to be precise each second is one entry, in this case, it will be 3, it helps me to determine the arithmetic mean.
currentTimeUnix - This is the current time, it the exact same time of calculation in milliseconds (each second)
dischargingStartTime - This is the time when discharging started also in milliseconds
/1000 - is to convert milliseconds to seconds
/3600 - is to get the mAh
Formula:
drainedMah = dischargingCurrentSum / dischargingUpdateCount * (currentTimeUnix - dischargingStartTime) / 1000 / 3600
I'm not sure what I have missed here, at the first time it counts normally, but after a while, it became way more than the actual battery capacity is.
AI: And when I sum this it's 1220mA
More precisely, since you are taking the measurement every second you have 1220 mA seconds. Capacity is measured in units of current times time -- for instance, milliamp hours. A typical AA battery has a capacity of around 2000 mA hours.
1220 mA seconds equals 0.34 mA hours.
drainedMah = dischargingCurrentSum / dischargingUpdateCount * (currentTimeUnix - dischargingStartTime) / 1000 / 3600
I'm not sure what's going on in the formula.
Suppose you take a current reading in milliamps every second and let \$S\$ be that sum of all of the current readings. Then
\$S\$ is the total charge extracted from the battery in milliamp-seconds
\$S/3600\$ is that value in millamp-hours
\$S/3600/1000\$ is that value in amp-hours
In response to your comment...
If you take one reading per second, the average discharge current is either:
sumOfAllReadings / timeElapsedInSeconds, or
sumOfAllReadings / numberOfReadings
The formula, as it is written, is multiplying by elapsed time, not dividing by it.
Note this will produce a current which has units of amps, not a capacity. |
H: Switching motor through contactor using 5V mcu signal
Is the following procedure safe/ok?
MCU turns on the optocoupler (MOC3063, datasheet)
Optocoupler output turns on a triac (BT139-600, rated 16A, 600V AC)
Triac supplies 220V AC voltage to the bobbin of a contactor (contactor ratings: 25A, single phase, 240V AC max for contact, 220V AC bobbin)
The contactor switches a submersible well water pump. (Rated 1.5HP (=1500W), 230V AC, 5.2A)
I've read here and there that,
Do I need a diac for triac? Don't know where and how to use one.
Do I need a snubber circuit to protect the triac from the inductive kickback of contactor bobbin?
Are these ratings (the motor, the triac, and the optocoupler) matched and ok?
P.S. I'd be very happy to get rid of the triac, as I just read about them this week, and have no experience working with them.
Any suggestions to serve this purpose (switching such motor through contactor using 5V mcu signal) is welcomed.
Also I can't use Solid State Relays (SSR).
Thanks.
AI: Relay boards with opto inputs are online (cheap) 4ch will replace everything between uC and contractor coils. An RC snubber will extend the life if you want >>50k cycles. |
H: Connecting single/multiple 12V cooling fan to a 12V 30A power supply
I'm a beginner in electronics. Currently trying to set up 3 cooling fans (DC 12V 0.1A) in my 3D printer.
If I were to connect all 3 of them in parallel straight into 12V 30A power supply unit, will it overload the cooling fans since its working amp is at 0.1A only? or does the PSU regulates the amp's output for whatever the working amps are?
AI: No it wont overload it, this will work perfectly fine. As long as the voltage is correct, and the power supply can provide as much or more current than the device or devices need, then you are good. The current rating of that power supply is simply telling you the maximum it delivers, the actual amount it delivers will be determined by the load's resistance (in this case the fans).
So yes any DC power supply that provides 0.3A (0.1A x 3) or more power will work for you. |
H: Bits are toggled in step 1 or 9's complement is done using subtraction?
In base 2, I want to subtract x-y using adder. Where, x = (1011)2 and y = (0101)2
[For verification, in decimal x=(11)10, y = (5)10. So, we are seeking (6)10 as the answer ]
In base 2 using adder we are looking for (1011)2-(0101)2 = (?)2
Or, actually we are looking for (1011)2+[-(0101)]2 = (?)2
Procedure:
Step 1: Find 1's complement of y = (0101)2
(1111)2-(0101)2 = (1010)2
Step 2: I'll add 1 to get 2's complement
(1010)2 + (1)2 = (1011)2 --- result 1
Step 3: Now, I'll add x = (1011)2 to result 1
which is 2's complement of y = (0101)2
(1011)2 + (0101)2 = (10110)2 --- result 2
Here, in (10110)2 we get End Around Carry which happens to be 1 at most significant bit in (10110)2.
We remove End Around Carry from the result 2 and get the answer (0110)2 = (6)10
So, finally, my questions here is to know following:
Even though, we want to carry subtraction using addition, we still have to carry subtraction to find 1's complement [as show in step 1]. So, we still require subtractor to carry 1' complement. If that is the case, then why we take pain to carry unnecessary procedure of subtracting numbers using adder (addition)?
Or, please let me know, how actually, subtraction is carried using adder in absence of subtractor?
AI: Using an adder makes it easier than using a subtractor, less logic, easier to understand, etc.
In grade school we learned a - b = a + (-b). And our first computer class we learned about this thing called twos complement and that to get the "twos complement" you invert and add one. So a - b = a + (-b) = a + (~b) + 1
1 plus one
1011 a
+1010 ~b
=====
fill it in
10111
1011
+1010
=====
0110
1011 - 0101, (unsigned) 12-5 = 6
1011 - 0101, (signed) -5 -5 = -10 (which cannot be represented in 4 bits)
So unsigned this is good, the carry out indicates not borrow, some architectures invert the carry out into the carry bit/flag indicating a borrow, some do not invert.
For signed numbers we see that the carry in and carry out of the msbit do not match (or another way to see it is the msbits match but the result doesnt) so this is a signed overflow the result will not fit in four bits.
So lets try 5 bits
11011 - 00101 -5 - 5 = -10
1
11011
+ 11010
========
110111
11011
+ 11010
========
10110
(~10110)+1 = 01001 + 1 = 01010
And there we go, the carry out indicates not borrow, which you use to look for greater than less than. And we do not have a signed overflow. So although you might not have asked this this shows both signed and unsigned work using an adder.
Super trivial to use an adder to do subtraction, this is the beauty of ones complement. Using an adder to do subtraction is beautiful and simple. |
H: Crystal Oscillator
What are the markings mean on this crystal that I found on a motherboard? Thanks.
AI: The first letter A signifies it is made by Abracon
the next part 24.0 indicates it is a 24 Mhz crystal.
The F indicates the month the crystal was made, letters A to J are possible, this crystal was manufactured in June.
The 7 is the last digit of the year it was manufactured in. So this was likely made in 2007.
The last letter K is an internal code used for tracing the product (such as which machine or facility it was made at). |
H: Current Feedback/Sense Circuit
I am trying to understand the circuit from this datasheet so I can use it in a project. The issue I am having is how the current feedback works (circled below). OUT_IFB is the current feedback for the output circuit.
The circuit has two resistors in series (R15 and R16) which are both 4.7kohm and that I thought were originally part of a voltage divider. However, R15 connects to a microcontroller which has very high impedance so almost no current is flowing through this branch.
Is it possible that C13 and R16 are making and RC filter? If so, what is the purpose of R15/R18?
Any insight would be appreciated. Here is the datasheet, the circuit was taken from page 28.
AI: R18 is the switch current sense resistor.
I'm not sure about R15, but R16 and C13 form a "special" kind of low pass filter called a leading edge blanking filter. R7 and C18 do the same job.
Whenever the MOSFET turns on, a sudden spike of current flows through the MOSFET and the current sense resistor (due to the parasitic capacitances of various components around the MOSFET). This spike has the capability of triggering the current limit circuit and closing the MOSFET, which is unwanted as the inductor current (which is the current that needs to be limited) doesn't contribute to the current spike and it causes the MOSFET to be turned off prematurely.
The leading edge blanking filter is designed to have a cutoff frequency well above the switching frequency so as not to attenuate or average the true inductor (or switch) current but to just "blank" or suppress the initial current spike.
Take a look at the voltage across the current sense resistor in this simulation:
Here's a closeup:
As you can see, there is a huge spike cause by a sudden flow of current through the current sense resistor due to parasitics.
In the picture below, you can see the effect of the leading edge blanking filter:
and here's a closeup:
You can clearly see how the filter removes those spikes. |
H: Meaning of circle passing through -1 (nyquist plotting)
I'm using MATLAB to plot a few functions in nyquist plots. I'm learning nyquist plots and I'm quite new to the concept.
I plotted the nyquist plot for (s3 + s2 + 2s + 2)/(s2 - 9) [unstable system] and got the following plot:
In the figure there is a circle going through -1. What does it signify? Can you explain in simple terms since I'm a beginner?
AI: It is the unit circle. It is centered at origin and has radius 1. It represents all points on the GH-plane which have a gain of 1.
The phase margin of the system depends on the angle of the transfer function when the gain is 1. So, all the points on your Nyquist contour which touch / cross this circle are points at which you can evaluate a phase margin.
The circle is just a helpful visual indicator to help us judge the scale of the plot and get a quick idea of the points where the contour has unity gain.
Since you seem to be using Matlab, right click on the plot and select the option to show all the margins of the system and note that the phase margins are marked at the point where the contour crosses this circle which represents gain of 1.
Similar to phase margin, the gain margin depends on the points on the negative real axis. That line is already present in the plot as a part of the x axis, so it is not as quickly noticed as the circle. |
H: How to wire two open-drain logic outputs to a three pin bi-color LED
I am very new to working with electronics; my main experience is in programming. I am working on a project and intend to use this MCP73833/4 Li-Ion Charger. It has two "Charge Status Output" pins in an open drain configuration. This table shows the state of the pins depending on the current state of charge.
The two states I care about are "Charge In Progress" and "Charge Complete". So for those two status, there will be one pin in low state, the other in high impedance. This is where my lack of knowledge creeps up.
I've been reading other answers about setting up LED's to open-drain pins, but none of it has fully made sense to me. I understand that when a pin is in a low state, it's connected to ground. So in the case of a three pin bi-color LED, I assume it'd be best to use a common anode configuration and the pins connected to their appropriate cathodes? Also, how do I set it up that the low state allows the flow of current through the LED without running too much current through the pin itself? I found this information in the datasheet, but I'm not sure I understand what each of it means:
The columns from left to right are "Parameters", "Symbol", "Min", "Typical", "Max", "Units", and "Conditions". I don't think I fully understand the significance of this information. Any help pointing me in the right direction to learn about this would be greatly appreciated.
Thanks for your time!
AI: The output voltage is rated at a sink current of 4 mA, though it will typically sink 15 mA. Max sink current current is an odd specification in this part of the data sheet. Usually you'll have a min sink current specified in the electrical characteristics, and a max in absolute maximum ratings.
10 mA is a reasonable nominal current to run through a LED, most will handle 20 mA, and most will be pretty bright with much less. High accuracy is not needed for this application.
You can limit the current using a series resistor between the open drain output and the LED.
You need to know the nominal forward voltage drop of your LED, and the supply voltage you'll be running it from. Assume the open drain output will go down to 0 V, this will give you a conservative approximation. The voltage across the resistor will now be Vsupply - Vled.
Divide that voltage by your wanted current, ie multiply by 100 for 10 mA, and that will give you the resistor value in ohms. |
H: What is the input impedance of a differential amplifier?
I have this circuit:
How would we calculate the input impedance of the differential amplifier?
I have read answers that says that the inverting impedance side will just be R1=200 ohm.
I have also read answers that say that the input impedance on the inverting side is this long formula:
The longer formula I found here.
I have also seen many other variations for what the input impedance of the differential amplifier on the inverting side and I'm lost.
Who is correct?
AI: Short answer
Using the values in your circuit, the common mode input impedance (to ground) is 602 Ω per input wire. The differential input impedance is 400 Ω. That's the short answer.
And, this assumes that the input voltage is sufficiently low so as not to cause op-amp saturation and, that the input frequency is low enough so that the gain-bandwidth-product of the op-amp produces enough open-loop gain so that we can assume ideal op-amp operation.
Simulations (a sanity check): -
I have also seen many other variations for what the input impedance of
the differential amplifier on the inverting side and I'm lost. Who is
correct?
There does appear to be a fair degree of BS about this basically simple circuit on the web (this site and wiki) so, if you don't believe me or still have doubts, use a simulator.
Some people over-analyse this circuit and get fixated on the two input voltages being independent. Quite easily you can mess up an analysis by doing this and, you'd likely observe that the individual currents into each input resistor are unequal in magnitude. But, this is because the applied analysis is imposing unreasonable constraints (compared to realistic and practical situations).
Inevitably, some folk conclude that the impedances into the two input resistors are unequal but, the reality is that you have a true differential balanced and bipolar input current (important) plus a superimposed common-mode current that "appears" to mess up the bipolar and balanced differential input currents.
In other words, don't mix up differential and common mode currents when making an analysis. If you do, you'll get confused. Example: -
This scenario DOES NOT allow you to conclude that for a regular differential signal source, the input impedances are not balanced.
And, just for further clarity, if the CM voltage source is raised to 3 volts we see this: -
This adequately demonstrates the distinction between CM currents and differential currents and perfectly proves that, for the circuit above (R1 = R2 and R3 = R4), the differential impedance remains constant and the common-mode impedance remains balanced. |
H: Calculation for Resistor in Phototransistor Emitter
I decided to ask here for help, I am still new at electronics, I have been trying to figure out the definitions and graphs of this phototransistor, the PT1302 (datasheet here), my doubt is how can I calculate the value of a resistor below the emitter, the \$V_\text{out}\$ is connected to an Op-Amp, (from which I have successfully calculated all the resistors and values for components). From what I read, the given formula for the resistor in this particular arrangement is:
I know that the \$0.6V\$ correspond to the \$V_\text{CE}\$/\$V_\text{CEO}\$ in the datasheet, but I don't know if I am missing a formula to calculate Ic or the current or gain through collector to emitter.
And here is the matter, how can I compute \$R_1\$ or \$I_\text{C}\$ for the formula?.
if I am not wrong \$R_1\$ is
$$
R_1=\frac{V_\text{CC}-V_\text{CE}}{I_\text{C}}. \label{1}\tag{1}
$$
I would really appreciate any feedback, comment, observation or example.
AI: If the phototransistor is used as a switch, i.e. you do not want to use it for measuring the incident light intensity, then the right way to dimension the value of \$R_1\$ is to choose arbitrarily a maximum collector current \$I_\text{C}\$ (to say the truth, the choice is not entirely arbitrary: I'll give some detail on this in the notes), read from the datasheet what is the maximum value of \$V_\text{CE}=V_{\text{CE}_\text{(sat)}}\$ and then use formula \eqref{1} in the form
$$
R_1=\frac{V_\text{CC}-V_{\text{CE}_\text{(sat)}}}{I_\text{C}}
$$
Some notes on the "abitrary" choice of \$I_\text{C}\$.
While from the theoretical point of view the choice of \$I_\text{C}\$ is entirely arbitrary, from the practical point of view there are some limits. The most notable one is the maximum admissible value for this current, found in the "Absolute Maximum Ratings" table of the datasheet. For the device you are using, this is \$20\text{mA}\$: however, if you want to use it as a switch i.e. if you want to have \$V_\text{E}= V_\text{CC}-V_{\text{CE}_\text{(sat)}}\$ even at the lowest levels of incident radiation intensity, you should choose a far lower value: for example \$I_\text{C}\simeq 100\mu\text{A}\$ can be a good choice.
On the use as a "linear" radiation detector: if you are using the device for a linear application i.e. to measure light intensity, then the chosen value for \${I_\text{C}}\$ should be a half of the maximum collector current allowable by the power dissipation limits of the device. this is due to the fact that in such a way, you enhance the dynamic range of the output of the device. |
H: 8-channel/octal equivalent of 74HC125
I have a 12v powered 16-channel relay board, that required 5v logic level signals to control the relays. However, I am using a Raspberry Pi to control this, which has 3.3v logic level outputs. I have previously used a 74HC125 to convert 3.3v logic to 5v logic, but this is only a 4 channel device, so instead of using 4 of these, is there an IC available that will allow me to use 2 or even 1 to drive the relay board.
The 74HC125 is labeled as a "Quad Buffer/Line Driver". I have found the 74HC541 which is similarly labeled as a "Octal Buffer/Line Driver", which I think seems like a good fit.
AI: The 74HCT541 (not the HC version!) will work fine for your application.
The difference between the HC and HCT version is that the HCT version accepts TTL input signals which have a lower "high" signal voltage. The HC chip expects your Raspberry Pi to output 0V/5V (CMOS levels), while the HCT chip accepts TTL levels (roughly 0V/3V). The latter is exactly what you need. |
H: Why there is capacitor in series in high speed designs like SGMII?
Why we are connecting capacitor in series in high speed designs like SGMII. If it is to remove DC voltages, why we are not using on other signals like I2C, SPI and so on. What is the major purpose. Can anyone explain in easy way??
AI: The data is differential and encoded to have no DC component. To allow connecting together chips that have different supply voltages at the SGMII interface, or simply to allow them to use their own DC biasing for the transmitters and receivers, the capacitors are there to block DC and can pass the high frequency AC data signals just fine.
Interfaces such as I2C, SPI and so on are not encoded and need to preserve the DC bias component, and usually the devices all need to use same supply voltages too. SGMII uses high speed differential serdes blocks with CML IO interfaces, I2C and SPI use just CMOS IO interfaces. |
H: Explain this behavior using PWM to control a fan
I bought a fan designed to exhaust attic spaces. It's a 12" fan that came with a 50 watt solar panel. In full sunlight, I thought it was blowing a bit hard for my liking, so I bought a PWM speed controller to control the fan speed. The particular one I bought supposedly operates at a frequency of 15 kHz. However, there's an audible sound at a much lower pitch depending on how I adjust the pot. Speaking of pot, that brings me to my real question.
With the pot dialed all the way counterclockwise, the fan stops. That's expected. As I rotate the pot clockwise, the fan speeds up. It achieves maximum speed when the pot is about in the middle position. When I rotate it clockwise some more, the fan slows down.
Meanwhile, voltage at the input is 19V+ when the pot is at counterclockwisemost position. Voltage at output is very low, unsurprisingly. At maximum fan speed (at the time I took readings) input voltage was around 13V, and output voltage around 8V. If I rotated the pot clockwise from that position, input voltage and output voltage both decreased. That is what's surprising to me. It seems to me that input voltage should decrease because the load is increasing, but I'd expect the output voltage to increase, since more time at full voltage is included in each cycle, or so I thought.
If it helps, I can provide links to what I ordered.
I'm also wondering why there was an audible noise when the pot was dialed mostly clockwise. Some sort of harmonic I suppose.
Edit: I thought dialing the pot all the way clockwise would be equivalent to not having the PWM at all, but that obviously is not the case.
AI: It achieves maximum speed when the pot is about in the middle
position. When I rotate it clockwise some more, the fan slows down...
At maximum fan speed (at the time I took readings) input voltage was
around 13V, and output voltage around 8V. If I rotated the pot
clockwise from that position, input voltage and output voltage both
decreased.
The solar panel limits the current the motor can draw. Current determines motor torque and the fan needs more torque to spin faster, so the panel limits how fast the motor can spin the fan. If you had connected the solar panel directly to the fan you should have gotten the same voltage and speed as you did with the PWM control full on.
But how could the motor speed be higher with the PWM control only half way up? At 50% PWM the motor is drawing current from the power supply only during the 50% 'on' portion of each PWM period. During the other 50% of the time the motor is generating the same current via the inductance of its windings, which is recirculated through it via the flyback diode in the controller. Therefore the motor current is double the average supply current. If the controller has sufficient bulk capacitance on its input the solar panel only has to deliver (close to) the 50% lower average current.
This is balanced out by the average voltage across the motor being only half the supply voltage. So the power is the same, but the motor is getting lower voltage at higher current. In effect the PWM controller is 'transforming' the voltage and current like a buck-mode DC/DC converter does, using the motor windings at its inductance.
Solar panel output voltage drops slowly as current increases until it gets close to the current limit (determined by light intensity), then drops rapidly to zero if you try to draw more current. Maximum output power is obtained at the 'knee' of this curve. By adjusting the PWM control for maximum motor speed you have achieved the best match between solar panel output power and motor power consumption, which in a solar controller is called MPPT (Maximum Power Point Tracking).
I'm also wondering why there was an audible noise when the pot was
dialed mostly clockwise. Some sort of harmonic I suppose.
The motor commutation frequency may have been beating with the PWM frequency to produce an audible difference frequency, the sound being produced by the PWM current pulses making the motor vibrate mechanically. This might only occur at high PWM ratio when the controller is unable to smooth out large changes in panel voltage when it is in current limit. |
H: What are the names of power supply connectors in this picture?
What are the names of power supply connectors in this picture?
AI: I would call them “bulkhead turrets” or case-mounted turrets or “stand-off and feed-through” power and ground terminals.
But it appears some Mfg’s call them “ Threaded Turret Standardized Terminals”
“ PCB solder pin with threaded feedthru pin” for power ?
“Threaded double turret” for gnd..? |
H: Poles and Zeros in Second Order System
I was reading about second order systems and forced/natural responses:
I just want to explain my understanding of what generates the forced and natural responses and want to ask if it is correct:
The input poles of the input function decide the form of the forced response - step, etc.
The system poles decide the form of the natural response.
The amplitude of the forced and natural responses are dictated by ALL of the poles - both input and system.
I don't know if my explanation is correct because if you consider a system that is completely underdamped, that will just continue to oscillate at the output when a step input. In that case, we never even see the form of the forced response at the output (another step) or is the forced response there but just overshadowed by the natural oscillation?
AI: In that case, we never even see the form of the forced response at the output.
We do! The resulting oscillation is actually shifted up by the step part! Notice that the response is always above zero. this is because the step shifted the sinusoid part of the oscillation (which is otherwise symmetric about zero).
is the forced response there but just overshadowed by the natural oscillation?
Yes.
sys = tf([100], [1, 0.1, 100])
step(sys, 10); |
H: Battery Voltage Dropper
simulate this circuit – Schematic created using CircuitLab
I am looking to understand this circuit better. The main question is:
Is it true that the battery will start draining and stop when its Voltage is 12.16V (D1 Zener voltage) and will not continue to drop voltage?
The simulator tells me that around 12.16 Volts the current will be Zero. Is this real, that the circuit current really becomes Zero at around 12.16V in real life?
Something is telling me that the simulations are too theoretical :)
Also, there are Zener Diodes of almost all voltages, right? or does the industry limit the availability of these?
The simulators all have DC Sweep but all are from 0 to a positive voltage not, for example, from 24 Volts to 10Volts. How can I simulate a voltage dropping as in a battery in a simulator?
AI: You are correct that it is not so simple in practice, although it is fairly close. Here's a short list of some of the things that makes your circuit deviate from the simulation:
Every component has a manufacturing tolerance, or variation. The datasheet tells us that VZ can vary between 11.4 and 12.6 volts right from the start.
A Zener diode does not magically start and stop conducting fully at the Zener voltage, it has a gradual curve. Sometimes this is given in the datasheet.
Even below the Zener voltage there will be a leakage current, the datasheet again tells us that it is around 5 µA for this device, but I expect it to vary between components, and vary strongly depending on the temperature.
About the Zener voltage selection, you can probably get whatever you want if you order hundreds of thousands, but since it is impractical to stock many different voltages, manufacturers typically limit their selection to a fixed set. |
H: Combine multiple power supplies with shared negative
I have a computer power supply that supplies 24V, 12V and 5V. The 24V rail is dead but all other outputs work. (I need to figure out what's busted).
Can I add a 24V power supply alongside the existing one? Is there any problem with having the existing PSU and the new one (black wire) connected to negative from BOTH PSUs?
Yellow wire is 24V. Black wires are negative. As per the manual, it says all negatives are "shared":
Pic of the plan:
AI: assuming your new 24V supply has an isolated output, you can disconnect the exiting 24 wire connect a new one and share the negative. Electrically that will be fine.
However you may find that your device needs the 24V to turn or before or after the 5V comes on. If that's the case there's a potential for the device to be damaged. |
H: super capacitor's maximum charge current
I am designing a backup system based on a supercap and an LTC4041.
The calculations by the guidlines in the datasheet brought me to the folowing parameters:
Capacity:2.4F
Charge current: 1A
charge voltage: 4.5v
As I researched this field I noticed that the capacitors ESR is important for the charge current.
How can I Know what is the maximum charge current for the supercap? (FT0H225ZF for example)
AI: The datasheet includes a chart how to select a charging resistance based on capacitor family and capacitance.
For the FT series 2.2F capacitor you ask, the charging resistor is 51 ohms.
Which means you can't achieve your required 1A charging current. |
H: What will happen if the input voltage of the buck-boost converter goes below the recommended input?
I am doing a solar panel project, but I don't have much knowledge about electronics.
I am planning to use a buck-boost converter that gives me a stable output (12V.)
What happens when the input voltage goes below the recommended voltage (5V?)
Will it cut off or give the wrong output?
REES52 Converter Buck Boost Adjustable Regulator
AI: Most DC-DC chips have an input undervoltage lockout, so if the input voltage drops too low, it's probably going to shut down.
Then, since it is no longer drawing current, the input voltage will rise, and it will turn on again.
So it will cycle between on and off. Whatever you plug at the output may not like that very much.
If the design is too cheap though, and if the manufacturer used MOSFETs that need a bit more gate voltage to fully turn on than the undervoltage threshold of the chip driving them, then it will work with the MOSFETs in linear mode, which will make them overheat and burn.
There's no way to be sure without looking at what the actual devices are.
For a solar panel you should really use a smarter DC-DC like a MPPT. Buck-boost is not that useful, since on a solar panel, when the voltage drops it means there's not enough power (ie, sunlight) available anyway.
At constant output power, boosting the voltage will draw more current from the input, which will make the solar panel voltage drop even more if there isn't enough sunlight. So if you use a buck-boost, you'll have a bit of a "binary" system: either there is enough sunlight to provide the output power you need, and it'll work, or there is not enough sunlight and it will not work at all.
For example you can't use that to charge a battery, because the output charge current setting is constant.
A smarter "MPPT" solar controller will adjust the battery charge current to draw just the right amount of power from the solar panel so its voltage doesn't drop. So it will always give you some power even if the weather is a bit cloudy, your battery will take longer to charge but it will charge. With the buck boost it won't charge at all. |
H: Linear regulator dropping voltage
I have a simple component that plays a song when I pull the input pin high. It operates at 3V and everything works fine when I provide power from my bench power supply(I can also see that it draws 0.15A current when operating). I want to build it into a product that has a 5V 2.1A adapter as a power supply so I added an LM317T voltage regulator. I configured the regulator with R1=390Ω and R2=560Ω according to Figure 6. of the datasheet and when I test the output without load it does provide 3V but when I use it to drive the audio component the output voltage drops to ~2V and the audio is played in a slow and distorted way. At first I just had these two resistors but since then I also added all the recommended capacitors(but not the recommended protection diodes, Figure 7.) but it still has the same behavior. According to the datasheet the LM317T should be able to provide 2.2A of current. My questions are: what am I doing wrong and how to fix it?
Edit: the schematic is the same as Figure 6. Tried to draw it in kicad if it helps(this is the simpler version, I've tried with the caps as well from Figure 7 without the protection diodes):
@Justme: Normal speaker not a piezo(8Ω 0.5w)
@brhans: I took a picture(it's the left regulator):
@audioguru: I'll test that and get back to you but I doubt it, it should be able to provide 2.1A
Took a picture of the component as well, it's from an old alarm clock. The cables are: red=3v, gray: GND, green: input signal(3V), and the two yellow ones are going into the speaker(+/-).
AI: @erdeszt Indeed you got the answer all by yourself. Page 5 of the datasheet shows TYPICAL minimum drop-out voltages. It's not guaranteed. And they hover around 2V. The LM317 is NOT an "LDO" (not a 'low voltage dropout" regulator). You are asking it to drop less voltage than it's capable of. It's a VERY old design (40 years?) Modern LDO's would have NO PROBLEM handling this. You can easily find one that's "fixed" at 3.0V. Further, note the LM317 has a MINIMUM output current ... If you're not pulling enough from it, the output floats around. Modern LDO don't do that either.
I knew that was your problem just reading your first paragraph. I was quite happy to see you'd found the solution yourself. Well done :) BTW, 3.3V is a standard "digital" voltage, and PROBABLY would be OK here. But if you don't KNOW that to be true, you do take some small risk by using it. |
H: Understanding Specification & Datasheet For Center Tap Power Transformer
In a desire to better understand transformers, I have purchased a simple power transformer:
It is the model 187C24, manufactured by Hammond. I'm having trouble understanding the data sheet. I have added the relevant part of the data sheet above. The complete data sheet can be found here.
If I understand the data sheet correctly, the primary coil has a single primary coil between terminals 2 and 3. It also has a secondary coil between terminals 5 and 8. There is a center tap on the secondary coil, terminal 7.
The data sheet also says that if I put 115 VAC in, the transformer will output 24 VAC. According to this previous question, that means if I put 115 VAC across 2 and 3, I will get 24 VAC across 5 and 8.
I don't want to work with 115 VAC for safety reasons. Therefore, I instead used a signal generator to create a 60 Hz, 1.15 Vrms signal. I then applied this signal to terminals 2 and 3. I expected that there would be 0.24 Vrms across the 5 and 8.
I used an oscilloscope to view voltage across terminals 5 and 8, and found the output to be 0.298 Vrms. This is 25% larger than I expected the output to be.
Why do my results differ substantially from the data sheet?
I don't know enough to judge the reason, but I have two guesses:
This transformer behaves differently at low voltages/low currents
The tolerance of this transformer is really low
My particular transformer is defective.
AI: The rated output voltage of a transformer secondary is given under a rated load current.
The unloaded output voltage will be higher. |
H: Question about optocoupler and transistor
i intend to isolate the microcontroller pwm signal, because in reality the V3 source will be a high voltage source, therefore i think i need to isolate the microcontroller in case there's exist leakage in the MOSFET. My question is, will this design works? I want the output from the optocoupler emmiter transistor nearly the same (voltage drop is not a problem), so i can still control the mosfet with the pwm signal also protect the microcontroller from the high voltage. Thanks!
AI: A possible problem, is that the rise/fall time of the optoisolator
output is specified at 2 us or less, into a 100 ohm load. Because
you have a 10k ohm load, the rise time could be as much as 200 us,
and that's problematic with a PWM base frequency much over 1 kHz.
Any slow slewing of the gate of the MOSFET will result in heat
dissipation in that component. Another photocoupler, like APS1551S,
might be better; there's builtin amplification and low delays. |
H: How can MOSFET drain be used as ground for a load?
I'm trying to understand how the schematic from this github repo works. It uses an RTC to turn on an arduino, via a npn transistor and a mosfet.
I'm novice with electronics, so this might be a simple circuit. Specifically, I don't understand the combination of the npn and the mosfet. I get that the RTC pin is turning on the npn transistor to allow current to flow, and that somehow that connects the arduino to ground, but I don't get how the grounding part works.
how does connecting the mosfet drain to arduino ground permit current to flow?
how is current flowing back from arduino ground to vcc ground?
what is the role of the capacitors?
why is the npn emitter connected to mosfet collector?
I'm sure I have some basic misconceptions, hopefully the above is enough for y'all to help me identify them?
Also, if y'all can help me identify the names of patterns used in this circuit, it'd help me.
Also, ps, what tools might I use to simulate circuits like this one and learn on my own how/what/why? I'm aware of sparkfun's tutorials and some courses on udemy, but what are other go-tos?
Thanks!
Edit: related, Using a DS3231 RTC alarm + MOSFETS to turn on a MCU
AI: As the comments say, this circuit is terrible. More importantly, it's poorly-drawn. The MOSFET is upside-down, and both the MOSFET source and the BJT emitter are connected to ground. Here's what's going on:
R3 and Q1 form a simple inverter that inverts the square wave output from the RTC.
The inverted square wave is connected to the gate of Q2.
When turned on, Q2 connects the Arduino's ground pin to the circuit ground. When turned off, Q2 disconnects the ground, (theoretically) powering off the Arduino.
Switching an IC's ground connection is a bad idea for a number of reasons. Don't do it!
I'm not sure if the capacitors are really meant to be 0.1 millifarads or if they're the standard 0.1 microfarads. It's standard practice to have a 0.1 microfarad capacitor between a digital IC's power and ground pins to ensure a steady supply voltage during switching. If they really meant 0.1 millifarads (100 microfarads), the capacitor is probably a bad attempt at keeping the Arduino running after its power is switched off.
Microfarads should always be written μF or uF. In old schematics, mF was used as an abbreviation for microfarads. For this reason, it's best to avoid millifarads and the mF abbreviation and just use microfarads.
UPDATE: The intersections between wires are unclear -- another way this schematic is poorly-drawn. The normal way to show this is to have a dot at connected intersections. Another way is to have one wire curve to the side to show an unconnected intersection. Here are some examples:
The thickness of the lines shouldn't matter and is probably an artifact of converting the schematic to a PNG.
In your schematic, dots are used only to show some pin connections (which is wrong). Based on the function of the circuit, here are the actual connections:
RTC SQW is connected only to the base of Q1, not to VCC..
The gate of Q2 is connected only to the collector of Q1, not to ground.
The emitter of Q1 and the source of Q2 are both connected to ground. |
H: Signal attenuation due to theoretical, lossless transmission line
Would the series inductance and shunt capacitance of a theoretical, lossless transmission line create signal attenuation? If so, how much and how could I calculate it?
Imagine an ideal, lossless transmission line connected between an ideal voltage source (0 output impedance) and a perfectly-resistive 50ohm load. The transmission line can be modeled as a set of lumped series ideal inductors and lumped shunt ideal capacitors (remember, it's lossless, so there should be no resistive values). Let's use the lumped inductance and capacitance values provided by wcalc here. This calculator gives roughly \$167\,\text{nH/m}\$ and \$67\,\text{pF/m}\$. Let's take \$1\,\text{m}\$ of this cable so that the total series inductance is \$167\,\text{nH}\$ and shunt capacitance is \$67\,\text{pF}\$. The total equivalent circuit is then shown in the schematic below.
Imagine our signal frequency to be \$1\,\text{GHz}\$.
I would then expect the gain of this circuit (the output voltage is measured across the resistor and the input voltage is the voltage from the source) to be approximately \$-53\,\text{dB}\$.
I used the following python code to calculate the gain:
import numpy as np
frequency = 1e9
omega = 2 * np.pi * frequency
inductance = 167e-9
capacitance = 67e-12
zl = 1j * omega * inductance
zc = 1j / (omega * capacitance)
z1 = zl
z2 = 1 / (1 / zc + 1 / 50)
g = 1 / (1 + z1 / z2)
g_db = 20 * np.log10(np.abs(g))
print("gain: {:.0f} dB".format(g_db))
Is this calculation correct? The signal loss seems very excessive to me. If I erred somewhere in the analysis (which I expect I did), can you point out where I went wrong?
AI: The calculation is correct. The analysis is well...not technically wrong but a bit misguided. Let's start by highlighting this statement in your question:
The transmission line can be modeled as a set of lumped series ideal
inductors and lumped shunt ideal capacitors (remember, it's lossless,
so there should be no resistive values).
This is saying that a transmission line, which uses the concept of "distributed" elements, can be modeled as "lumped" elements. The limitations of this type of modeling are what's missing in your understanding. You can approximate a line using lumps, but the resultant accuracy is highly dependent on the # of lumps...especially at higher and higher frequencies. The theory is that the ideal line is modeled as the # of lumps \$\rightarrow \infty\$.
You chose the number of lumps to be equal to 1...which is a tad less than \$\infty\$. I played around in SPICE and found that I can get somewhat decent flatness at and around 1GHz if I use 13 lumps. I plotted a few different "# of lumps" to show the difference, as shown below.
Since we're already in SPICE, I'd like to point out a nice tool you can use for modeling distributed elements if you already have the "per unit length" values. The component in LTspice's library called ltline (lossy transmission line) uses the SPICE3 LTRA model which takes the following main parameters:
If we use this model for your problem (we only need L, C and len), we can get a nicer result without using 13 lumped elements taking up twice your screen width. |
H: What does referred to mean in induction motors?
What does the term referred to mean?
And how if it's a stator reactance it still says referred to stator?
AI: And how if it's a stator reactance it still says referred to stator?
That's a typo - it should say rotor leakage reactance (referred to stator).
The term referred comes from transformers. If you have an N:1 step-down transformer then a 1 Ω load on the secondary is seen to behave like an \$N^2\$ load at the primary. Hence the term referred.
is there a transformer ratio in motors?
There certainly is inside induction motors and it's usually in the realm of 1000:1 stepping down from stator to rotor. |
H: Why is the current flowing into the power supply?
I tried to make a latch , and observed that there was current flowing through the PMOS into Vdd for some time duration. But then during that time the voltage across the drain is less than Vdd. Can someone tell me how this is even possible ?
I have attached the graph and the circuit with the question. Please let me know if I need to provide more info.
AI: Note that this current flowing back into the supply flows only for a fraction of a nano-second!
What happens is easier to explain with a much simpler circuit like a CMOS inverter. In your latch the same situation will occur when the latch changes state.
I have drawn 3 inverter circuits. The left circuit is a standard inverter, nothing new.
The middle circuit is the same inverter but I have added a capacitor in parallel with the Gate-Source of the PMOS. This capacitor represents the \$C_{GS}\$ inside the PMOS. I have also indicated the voltages at the gate and source of the PMOS when the input (source V_LOW) is low, so 0 V.
The 3rd circuit on the right shows the same (middle) circuit again but now the input source (V_HIGH) has just become high so 3 V (assume Vdd = 3 V as well). Now pay attention to the top plate of the capacitor \$C_{GS3}\$, note that it is at 6 V! How can that be? That's higher than the supply voltage!
simulate this circuit – Schematic created using CircuitLab
Look back to the circuit in the middle and see how we charged \$C_{GS2}\$ to 3 V. Then in circuit number 3 we raised the voltage at the bottom plate of the capacitor (the gate of the PMOS) to 3 V, since the capacitor is still charged to 3 V that means the top plate of the capacitor (the source of the PMOS) will be lifted to 6 V.
But the supply is 3 V! Yes so that capacitor \$C_{GS2}\$ will now discharge through the supply and that is the current that you're seeing flowing back into the supply.
Since the current is quite small and the duration of the current is very short, this is not really an issue. In CMOS logic circuits we only need to add sufficient supply decoupling capacitors which will then absorb this small current. |
H: CANopen - explanation of TPDO and RPDO
I am working on a project that uses the CANopen protocol. I have a problem with understanding the use of TPDO and RPDO. In some articles, RPDO is described as a request calling TPDO from another node, and in others as a contract to handle the received TPDO. The free canopen-stack and CanOpenNode libraries use the second approach to RPDO, it is not possible to send an RPDO 'request'.
But I am not able to understand why TPDO and RPDO, according to the recommendations of the standard, have different COB-IDs (CAN message identifier).
The COB-ID for TPDO1 has the range 0x181-0x1FF (0x180 + node_id) and the RPDO1 range is 0x201-0x27F (0x200 + node_id).
Example:
Node_1 - node id = 1
TPDO1 (COB ID = 0x181)
Node_2 - node_id = 2
RPDO1 (COB_ID = 0x201)
In the example above, I am unable to receive the data because the COB-IDs are not equal. To receive TPDO1 from Node_1 it is necessary to configure RPDO1 in Node_2 to COB-ID equal to TPDO1 Node_1.
My conclusions are that e.g. TPDO1 address (0x181) is RPDO1 for another node with id different from 1. Am I correct?
So why are there two address pools, TPDO and RPDO.
Or did these libraries apply their implementation of this case?
ANSWER TO @Lundin:
AI: But I am not able to understand why TPDO and RPDO, according to the recommendations of the standard
These are just standardized default COBID. Like there exists default PDO mapping and communication settings. They have to be set to something out of the box.
In the example above, I am unable to receive the data because the COB-IDs are not equal.
CANopen is not "plug & play". One node's TPDO has to be "routed" to another node's RPDO. Just like you say, you have to change the COBID somewhere or the nodes won't be able to communicate. Every CANopen bus needs a design plan: what nodes will there be, what should they send, how should they send it and how often, etc.
I'm not sure exactly what was the design rationale for the default PDO COBID (other than that they have fairly high CAN arbitration priority), but since all nodes have different COBID you wouldn't get "plug & play" no matter.
And keep in mind that CAN communication is not necessarily point-to-point! It is just as often one node communicating with several others.
It's quite convenient to have them at default locations. Imagine a likely scenario where is 1 "smart" PLC node and 10 "dumb" actuator/sensor nodes. You could then configure the "dumb" nodes to node id 1 to 10, then have the PLC listen to COBID 181h, 182h, etc. You'll only need to change COBIDs at at one place, in the PLC. And it's easy to expand and add more nodes. If there was one address pool, you might have been forced to change COBID at both sides.
Now if all of the nodes in that example were both actuators and sensors at once, and each node had the same COBID for TPDO and RPDO, that would be quite a mess. You'd get collisions - keep in mind that data isn't part of the CAN arbitration, so multiple nodes sending the same COBID but with different payload at the same time leads to error frames. That's the only time when there is an actual packet collision on a CAN bus. |
H: Hearing the radio by touching a jack plug
Here is what happened to me a few days ago:
I own an amplified speaker with a jack plug. Usually, when I touch the jack plug with my finger I hear a "hum" sound. On this specific day, on a specific location, I heard the radio (repeating the experiment with other people, it is always the same radio channel.)
How can you explain this phenomenon?
My understanding of radio frequency modulation/demodulation is very poor, but I understand that when you receive the radio-waves, you get all the radio channels at once and you need to demodulate it before you can hear the radio of your choice. So, what acted as a demodulator in this situation?
AI: Here is a circuit having four "components" that can act as a radio receiver. When each component is optimized, reception can be too loud to bear:
simulate this circuit – Schematic created using CircuitLab
In your scenario:
YOU are the antenna, connected to the jack tip
In the amplified speaker, there exists a semiconductor junction serving as D1
Needless to say, there is a speaker serving as SPKR1
A path to ground must exists - the amplified speaker requires a DC source that is likely grounded via the power plug. If your amplified speaker were powered by a battery, then a ground is not present, and any radio signals would not be detected.
You are not a wonderful antenna. So this scenario likely occurs only if a radio station's transmitting antenna is nearby. This would also account for you hearing ONE station that dominates stations further away.
simulate this circuit
In the amplifier of an amplified speaker, hundreds of semiconductor junctions exist, each of which is capable of non-linear operation - a key requirement of this kind of radio. It is likely that one junction, perhaps in a transistor nearest the input jack serves as D1...the audio it produces is amplified by the remaining part of the amplifier.
You mention hum as well. In this case, you also act as a kind of antenna, transferring local electric fields into the input jack. However, in this case there is no radio carrier wave and a non-linear element like D1 is NOT required. The electric field at the input jack is amplified directly. |
H: Sizing capacitor to avoid/supress current spike?
On a rather weak 5 V supply I need to power a circuit requiring around 650 mA in short spikes (20-50 ms). Outside of the spikes the circuit requires about 30 mA. The supply is able to supply sustained approximately 150 mA. Is there a formula - or guideline - for calculating the correct capacitor for such an application?
And, a follow-up question to the above question: Say, somehow, I figured out that 300 uF is "enough". Would there be any issue in selecting a "higher" value (for example 500 uF or 750 uF) instead?
AI: Excess current (beyond PSU capability) need is 500 mA, for up to 50 ms. This equals \$Q_x=\$ 25 mC of charge needed in excess during the spike. For maximum ripple \$V_r=\$ 100 mV, you will need a capacitance of \$C=Q_x/V_r=\$ 250 mF. Also you need to replenish the charge in the times between the spikes and you have only 100 mA current available, so the spikes must not occur more often than about 250 ms.
This is a really large capacitance which will cause all sorts of issues during startup and shutdown. It will also consume a lot of cost and space. Part of the problem is, that the frequency of interest here (20 Hz'ish) is in the range that you don't normally cover with bulk caps, but with PSU feedback instead. It is probably much easier to change the PSU and make it more responsive. In that case, you might only need bulk capacitance to provide charge for maybe 1 ms.
Another option could be super capacitors, which come in several F sizes, but have a rather low voltage rating. The issue with startup and shutdown will remain however. |
H: Taking into account the mutual inductive coupling analytically in LTSPICE
I am trying to take into account the mutual inductive coupling between three turns in LTspice differently. Instead of defining the inductive coupling coefficient K, I am using the analytical expression of the induced emf in the turn: emf_1 = M_i_j * d(I_j)/dt (1) by using behavioral voltage sources. Please refer to the figure below for illustration:
To do so and to validate my model I am comparing the voltage distributions in both cases (where the mutual inductive coupling is taken into account by LTspice and when I introduce the well known expression of emf (see equation (1) above)). In frequency domain, all seems to be good. However, when I run my simulation in time domain I get the same voltage distribution, expect for the input current of the input voltage: It is of 10^38A values!!!!!
How can I explain this? Or said differently, what am I doing wrong?
Thanks in advance :)
AI: I said in comments: -
Your alternative implementation does not appear to follow the correct
sign/dot notation as your first (k-coupled) circuit.
Meaning that if you naturally assumed that all the inductors of the alternate implementation had pin 1 (shown in red) in the same place i.e. like this: -
...Then there are some sign errors in your formulas (purple stuff).
@Andyaka I have taken time to understand your comment. You were right it was a pin number problem. Thank you so much! |
H: Compensation Loop of a mixed system
I have a system which is a mixed system. The system is an analog and numerical system. I modelized the analog part and I know its transfer function which I do not want to modify. The numerical part is used for doing the compensation of the system. I want to trick the compensation part.
Nevertheless for correctly design the compensation, and as I more used to think in the Laplace domain, I decided to study my whole system into the continuous domain. And I did the compensation that I wanted to have. But as my compensation is done by a numerical part, I need to convert my compensation transfer function from the continuous domain to the discrete domain. But as discrete transfer function is not equal to continuous transfer function, my compensation done in the continuous domain is probably not the right if I think correclty... especially because I have a very slow sampling rate and it cleary degrades the phase... Actually I should consider to add the effect of the discrete transfer into the s domain and then do the compensation.
My question is how can I do for adding the effect of the discrete transfer function into the s domain, considering a Euler Method for discretizing ?
More details :
The final system will be the following and the only part that can be changed is the compensation part :
Thank you very much and have a nice day,
For doing the compensation, I modelized the plant transfer function and the "feedback elements" transfer functions in the s domain. Then for having the margins that I wanted to have, I designed the transfer function of the compensation in the S domain as follow :
And then I pass my continuous transfer function to the z domain through the Euler method rather than than the bilinear transform as it it lowers the order of the transfer function and it then lowers the complexity of the code.
But It seems to me not the right solution as when I did the compensation in the s domain, i supposed no delay introduced by the software, so my system would be stable if my compensation introduced no delay. But when I set my system to the z domain I introduced a delay by setting the sampling rate, which in my case is 100 µs and the bandwith of the system is 5 KHz. I have some doubts ... I should introduced a Pade approximation for taking into account the delay, isn't it ?
AI: And then I pass my continuous transfer function to the z domain through the Euler method rather than than the bilinear transform as it it lowers the order of the transfer function and it then lowers the complexity of the code.
AFAIK, bi-linear transform doesn't increase the order of the system. See below example. Both transfer function denominators (not the numerator) are degree 3.
sys = tf([1, 1, 1], [1, 3, 3, 1])
s^2 + s + 1
y1: ---------------------
s^3 + 3 s^2 + 3 s + 1
Continuous-time model.
c2d(sys, 0.001, 'tustin')
0.0004995 z^3 - 0.000499 z^2 - 0.0004995 z + 0.000499
y1: -----------------------------------------------------
z^3 - 2.997 z^2 + 2.994 z - 0.997
Sampling time: 0.001 s
Discrete-time model.
i supposed no delay introduced by the software, so my system would be stable if my compensation introduced no delay.
The process of holding a sample at the input of the plant for one time period introduces an effective low pass filtering action. Which can be modelled in s-domain while doing the design.
From Wikipedia
The fact that practical digital-to-analog converters (DAC) do not output a sequence of dirac impulses, xs(t) (that, if ideally low-pass filtered, would result in the unique underlying bandlimited signal before sampling), but instead output a sequence of rectangular pulses, xZOH(t) (a piecewise constant function), means that there is an inherent effect of the ZOH on the effective frequency response of the DAC, resulting in a mild roll-off of gain at the higher frequencies ..
This drop is a consequence of the hold property of a conventional DAC, and is not due to the sample and hold that might precede a conventional analog-to-digital converter (ADC).
But when I set my system to the z domain I introduced a delay by setting the sampling rate, which in my case is 100 µs and the bandwith of the system is 5 KHz.
Bandwidth is 5kHz. the sampling frequency is 10kHz. You are right at the border of the sampling theorem. Try for at least 5x or 10x times 5kHz. |
H: Converting SPI/I2S to SAI peripheral setup help
Just a quick question, I just need some help figuring out what is what.
The device that I am working with is the: STM32H753ZI reference
I am coming from the I2S peripheral and wanting to setup the SAI peripheral with the I2S configuration
I am curious if anyone can tell me what is what
The SAI has
Audio Data Size
Frame length
and Slot numbers
For the I2S equivalents I believe
Audio Data Size = DATALEN
Frame Length = CHANNEL LENGTH
But what the heck is slots?
AI: Slots are audio channels. For example, I2S only has two channels or slots per frame, but other audio interfaces such as AC97 needs 13 slots so there are more than two channels or slots per frame.
Frame length is how many clocks there are to send all the slots. For example I2S can have a frame length of 64 bits to allow for up to 32 bits per slot.
Audio data size is how many bits of actual audio data there is per slot, as a 32-bit slot can be used to carry only 20 or 24 bits of audio. |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.