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H: Electronics Newbie : Can you switch from two voltage sources with a MOSFET?
Title and image describes it all, can you use one mosfet to switch two things with different voltages from one microcontroller pin?
AI: It depends on what's connected to J5 and J12. Without knowing the details, I would say you'll likely have problems with J5 in this configuration when the FET is OFF.
Think about voltages with the FET off: J5, pin 1 would be +5V and J5, pin 2 would be ~12V (through J12), and you'd have a -7V reverse voltage on the connected J5 device. If the J5 device can tolerate a large reverse voltage, it might work, but not recommended at first glance.
Consider adding another FET controlled by the same GPIO line instead... |
H: For multiplexers, what are the pros and cons of Three-State Buffers vs "Straight Gates"?
This came up from my previous question when looking more closely at multiplexers. Wikipedia article shows two ways of implementing them. One with some Three-State Buffers, and the other that's just "straight gates", but notice those AND gates have 3 inputs.
So is there any significant engineering different between a tri-state buffer and a 3-input AND gate? Is one more expensive to manufacture than the other? Does one cause bigger design issues? More power requirements?
What are the advantages/disadvantages of them for the purposes of multiplexers?
(My foreseen application is CPUs and other computer architecture.)
AI: For small multiplexers it doesn't matter. Large ones, a gate-implemented mux will take more area and have longer delay. So these use a different structure. More about than in a moment.
3-state buffers don't work well on ICs as this approach can leave the output line floating. This can be overcome with a 'weak keeper' on the line, but there's another way.
Chips with large selectors (like RAMs) don't use 3-state buffers or data path gates to construct multiplexers. Instead, they use transmission gates. These reduce the transistor count for the select element to just two FETs per selected data line. They also have less delay than either a gate or 3-state buffer approach.
Bonus: transmission gates work in both directions. This is used to some advantage in RAMs which share the same path for read and write. They also work on analog signals. |
H: RMS Current calculation from MCP3008
How to find RMS value of current from ADC value gets from CT??? . I have done like below
Made a burden resistor and voltage divider circuit for CT
MCP3008 connected with Jetson through SPI
5V to VDD
5V to VREF
From CT circuit output connected to ADC0 pin of MCP3008
I have plotted the ADC values received , it looks like a sine wave.
And i have converted the ADC values to corresponding Voltage
(adcnum * 5 / 1024 - 2.5 ) *1000.0 /66.0 ;
plotted voltage its in sine wave
And for RMS current i have used ( VMax / sqrt(2) ) / calibration_value
But The problem is when we calibrated RMS current with mains it will not matching when after certain hours or day.
is this equation for RMS current correct ?? and how to cirrect the RMS noise
image attached is ADC plot and CRO wave
AI: simulate this circuit – Schematic created using CircuitLab
HPF: High pass FIR filter of 20HZ , used to eliminate DC bias
X^2 : Squaring each sample
MAV: Collecting squared sample in a large Moving Average Filter
SQRT: Calculate square root of the entire MAV |
H: HAL_UART_Transmit_DMA function sending wrong data
I am trying to use UART with DMA,
before the DMA I tried polling method with while(HAL_UART_Transmit(&huart2, (uint8_t *)rs485TxBuffer, 17, 100) != HAL_OK); function and I could communicate successfully,
When I using the
while(HAL_UART_Transmit_DMA(&huart2, (uint8_t *)rs485TxBuffer, 17)!= HAL_OK);
function, data not sending correctly, just first byte correct another bytes are wrong. Why this happened ? How can I solve this problem ?
This is my initilizing sequence:
MX_DMA_Init();
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_USART2_UART_Init();
Below lines try to send data:
while(1U)
{
// Communication Test Block //
while(HAL_UART_Transmit_DMA(&huart2, (uint8_t *)rs485TxBuffer, 17)!= HAL_OK);
// while(HAL_UART_Transmit(&huart2, (uint8_t *)rs485TxBuffer, 17, 100) != HAL_OK);
}
This is the initilizing functions:
..
else if(huart->Instance==USART2)
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**USART2 GPIO Configuration
PD5 ------> USART2_TX
PD6 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART2_RS485_TX_Pin|USART2_RS485_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USART2 DMA Init */
/* USART2_RX Init */
hdma_usart2_rx.Instance = DMA1_Stream5;
hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4;
hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_usart2_rx.Init.Mode = DMA_NORMAL;
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
/* USART2_TX Init */
hdma_usart2_tx.Instance = DMA1_Stream6;
hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4;
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
This is the interrupt function in stm32f4xx_it.c
void DMA1_Stream5_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
/* USER CODE END DMA1_Stream5_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_rx);
/* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
/* USER CODE END DMA1_Stream5_IRQn 1 */
}
/**
* @brief This function handles DMA1 stream6 global interrupt.
*/
void DMA1_Stream6_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
/* USER CODE END DMA1_Stream6_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_tx);
/* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
/* USER CODE END DMA1_Stream6_IRQn 1 */
}
/**
* @brief This function handles USART2 global interrupt.
*/
void USART2_IRQHandler(void)
{
/* USER CODE BEGIN USART2_IRQn 0 */
// SerialPrint("Hi");
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
EDIT:
I tried these method but not worked for me.
while(1U)
{
// Communication Test Block //
HAL_UART_Transmit_DMA(&huart2, (uint8_t *)rs485TxBuffer, 17);
while(!dmaTransmitCompletedFlag);
dmaTransmitCompletedFlag = 0;
}
..
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
dmaTransmitCompletedFlag = 1;
}
AI: Problem:
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
These two should be set to byte alignment. It's set to halfword, so it does DMA on 2 bytes, but the UART register only has 1 byte, so half the bytes fall into a black hole:
uint8_t rs485TxBuffer[17]={0x02,0x0A,0x00,0x01,0x00,0x00,0x00,0x01,0x0D,..}
but I see the data like 02 00 00 00 0D 00 00 84 0A 02 04 on the line.
Only the bytes in bold are transmitted:
0x02,0x0A,0x00,0x01,0x00,0x00,0x00,0x01,0x0D
Also you can enable the UART FIFO.
About this code:
while(HAL_UART_Transmit_DMA(&huart2, (uint8_t *)rs485TxBuffer, 17)!= HAL_OK);
If the DMA core is busy, HAL_UART_Transmit_DMA will return HAL_BUSY. So the while(); will wait. When the DMA core is available, it will initiate the transfer and return HAL_OK. Note this while() exits after the transfer is initiated, but it does not wait for the transfer to finish. The transfer will happen in the background, which is the point of DMA. But if you touch some UART registers, or use HAL_UART_Transmit while the DMA is running, then it could mess with it and that would explain your problems. To know if the transfer is finished, use the interrupt. And if you use a global variable, set it to volatile. |
H: Switch capacitive load with a PMOS
I want to switch a capacitive load with a PMOS once while running, then the continous current is maximum 13mA. The capcitive load is 2x10uF X5R, 1x1uF X5R and 1x100nF X5R, so pretty low series resistance and so I expect a pretty high current. Since the continous load is so low, I don't want to pick a huge FET if possible and I think by switching slower, the maximum current will anyway be way lower.
Here is the schematics:
(The 0ohm resistor is only in case I want to bridge it)
Further I made an LTSpice simulation, this shows a pretty large current of 26A, but I could not pick the same MOSFET anyway:
Do you think this is possible to achieve with a smaller FET or should I pick one with around 60A peak?
AI: Switching the FET quickly will result in large current to charge the caps, and depending on how much capacitance there is on the 48V rail it might also cause the voltage to dip.
You can simply slow down the FET turn-on by adding a capacitor between gate and source, and increasing the values of R4 and R8.
Here Q1 acts as a current source to slowly charge C1, and R1/R2 divide that voltage to make a slow rising Vgs to turn on the FET very slowly. Inrush current is tiny. |
H: High voltage buck converter, voltage limiting bypass
I am designing a system for a 3.5 kW wind turbine that has a large input voltage range, from 0 up to say 750 VDC. The output voltage should not exceed 600 VDC. I would like to make a voltage limiting circuit. Do not worry I do not test any of this in my barn or backyard. I do my experiments in a university in a laboratory environment surrounded by professionals.
I came across some problems for this application:
I believe ideally the buck converter should do nothing (gets bypassed) up to 600 VDC. The reason is that operating the buck converter introduces energy loss which I want to avoid. Bypassing seems not to be very simple:
Using a relay at this DC voltage there is a lot of arcing, a relay wears out quickly and it is also dangerous.
Using a semiconductor such as a power MOSFET or IGBT requires high side switching. High side switching with a bootstrap circuit does not work if you would like to have the switch fully closed (duty cycle = 1). Using a charge pump is possible I believe, but the typical ICs go up to 60 VDC. I could design a high voltage charge pump. This is not my preferred choice since I think it is going to be difficult to properly and reliably control expensive and delicate power electronics.
Perhaps using a P-channel MOSFET would be more do-able. The R_on resistance losses are bit higher but perhaps could be acceptable. However, they do not seem to be available for such high voltages.
AI: Any ideas, suggestions or comments?
I would use a little dc-to-dc converter to produce (say) an isolated 15 volts supply for the high side MOSFET switch. Ones that are definitely suitable and superior are Recom's RxxPxx series of 1 watt converters: -
This means you can use an N channel MOSFET (more available at 1200 volt rating for instance). Then, I'd us an FOD8343 high-speed gate drive opto-coupler to control the MOSFET and provide bags of isolation: -
For the switching element I'd probably use a TO-247 SiC 1200 volt N channel MOSFET. You can get on-resistances as low as 20 milli ohm and this seems like it would fit the bill (3500 watts and 750 volts implies a current of about 5 amps).
You also have to be fairly conservative on voltage ratings; even a short wire (inductance) and moderate di/dt can easily cause transients of a couple of hundred volts that sit on top of the 750 volts. You can easily eat into 1200 volts is what I'm trying to say.
Then, I'd probably consider making this device the buck regulator switch and ensure that when the voltage dropped below 600 volts, the device stayed on (something that a buck converter naturally does by the way).
If you are switching fast, you have to consider the isolation component's (Recom and FOD8343) transient immunity and both the device recommended above are as good as any I can find. |
H: Help with a RS232 (+-12 Volts) to USB converter
I have a device I want to communicate to with the following signals:
This is a programmable power supply, an IPS-405. I have determined from the image above, which is all that is available in the manual, that I need a RS232 to USB converter (null modem) that works at 12 Volts, but I haven't been able to find any, or there is a lot of confusion regarding this converters.
Since I am trying to avoid buying a cable that does not work and have to return it later, can anyone recommend where to buy a RS232 to USB converter with these characteristics? Or chipsets? I have been looking at PL2303 but some reviews mention it works at +-6V, so I guess it also depends on the cable.
EDIT 1
So according to this schematic: https://ibb.co/NxJ1xpt, which seems to be of the PSU or a very similar model, the 12V signal is probably just feeding the optocouples and it is not a RS232 signal. I am still confused about what kind of cable I need to interact with this PSU though, I would rather avoid having to build a custom one.
EDIT 2
I also looked at the datasheet of the Winbond UC with the TXD/RXD signals, and noticed that the ranges of Input/Output for the TXD and RXD signals are in the range of 0V to 5V it seems: https://ibb.co/n3Ybpfq.
So it looks like a 12V input, a normal UART and a RS232 connector.
AI: Almost none of the USB to RS-232 adapters will use 12V. They typically use charge pumps to boost 5V or 3.3V to acceptable RS-232 levels, i.e. the output just has to exceed 5V when connected into standard RS-232 load,
But you don't know if the device really needs 12V on that pin. It might be an RS-232 input after all, and the manual might simply mean to connect DTR there to see when the port is used.
Also the pinout is very atypical because pins 2&3 need to be crossed but pin 4 is connected directly. Null modem cables do swap pins 2&3 but also 4&6. You need a custom cable.
Edit:
After seeing the schematics, the optocoupler N13 LED must be off when idle and on when PC transmits. I think pin 2 is TXD from PC and pin 4 is GND. The optocoupler N14 LED is on when idle, so if again pin 4 is GND, pin 3 is RXD to PC, and therefore pin 1 is the DTR signal for providing bias voltage for PC.
There is a good chance that it will simply work with any USB to RS-232 serial adapter, but you still need a special cable to connect the pins as drawn.
A straight through cable will connect pins as follows : 5-5 and 4-4 but will also connect 2-2 and 3-3. A null-modem cable will connect 5-5, 2-3, 3-2 as expected, but will also connect 4-6 and 6-4.
You need to modify the cable somehow to make the connection 4-4 between devices. |
H: Issue at programming the power supply via RS232 interface
I’m trying to program DC power supply which I recently bought via RS232 interface. When I try to send commands, I always get '0' value as a return no matter which command I sent. I’m hoping someone to point my mistake.
Device: UNI-T UTP3305C
COM Settings;
Baudrate: 9600
Parity: None
Data Bit: 8
Stop Bit: 1
Datasheet: https://www.uni-trend.com/uploadfile/cloud/English%20manual/Benchtop%20Instrument/UTP3000C%20English%20manual.pdf
AI: This looks like a rebranded Korad.
The firmware is a bit buggy and there's a very short timeout, so if you enter commands manually it won't work, it will timeout before you've finished typing the command. You have to send the whole command at once.
Try this Python3 code.
#!/usr/bin/python
import serial, time, sys, re
class KoradException( Exception ):
pass
class KD3005P( object ):
def __init__( self, serial_port, debug=False ):
# Open serial port. Note: RTS CTS does not seem to work
self._ser = serial.Serial( serial_port, baudrate=9600, bytesize=serial.EIGHTBITS,
parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_ONE, timeout=0.1,
rtscts=True, write_timeout=0.5 )
self.serial_port = serial_port
self._debug = debug
self._wait_until = 0.
self.id = ""
self.set_name( "" )
self.retries = 1
self.id = self.get_idn()
self.retries = 4
self.set_name( "" )
print("Initialized", self.name)
def set_name( self, name ):
self.name = name + " " + self.id + " " + self.serial_port
# serial transaction, string or bytes input, bytes output
def _tx( self, command, recv_bytes ):
# serial.write() wants bytes, not str
if not isinstance( command, bytes ):
command = command.encode("ascii")
self._ser.flushInput()
self._ser.write( command )
response = self._ser.read( recv_bytes )
if( isinstance( response, bytes )):
response = response.decode("ascii")
if len(response) != recv_bytes :
msg = "%s: %s Response %r is %d bytes, expected %d bytes\n" % (self.name, command, response, len(response), recv_bytes)
sys.stderr.write( msg )
raise KoradException( msg )
if self._debug:
print( "%s: %s %r" % (self.name, command, response) )
return response
def _com( self, command, recv_bytes=0 ):
# serial.write() wants bytes, not str
if not isinstance( command, bytes ):
command = command.encode("ascii")
# This power supply uses RCP - Retarded Communication Protocol.
#
# Some commands make the micro busy for a while during which it does not listen to new commands.
# Since there are no ACKlownedge messages, if a command is not supposed to return any response,
# it is impossible to know if it was executed or not.
#
# However, if the command we're about to send is supposed to return a known length response
# that can be validated, then if we get a valid response, we know the micro was ready!
# These commands are IOUT? VOUT? ISET? VSET? ; it is easy to check if the return is a valid float.
# Status and others that return just a byte cannot be validated, the byte could be leftover garbage.
#
first_command = "IOUT1?"
if command in ("IOUT1?", "ISET1?", "VOUT1?", "VSET1?"):
first_command = command
for retry in range( self.retries ):
try: response = self._tx( first_command, 5 )
except KoradException: continue
# validate response
if first_command[:1]=="V" and re.match( r"^\d\d\.\d\d$", response ): break
if first_command[:1]=="I" and re.match( r"^\d\.\d\d\d$", response ): break
sys.stderr.write( "%s: -1- %s Response %r is not a float\n" % (self.name, first_command, response) )
time.sleep(0.2)
else:
raise KoradException( "%s: -1- %s too many retries, giving up\n" % (self.name, first_command) )
# If the test command was actually the command we wanted to do, then it's done.
# return the float result. If we used IOUT1, we got the result for free, maybe do something with it?
if first_command == "IOUT1?": self.last_iout1 =float(response)
if first_command == command: return response
# now execute the command we came here for originally.
for retry in range( 4 ):
try: return self._tx( command, recv_bytes )
except KoradException: time.sleep(0.2)
else:
raise KoradException( "%s: -2- %s too many retries, giving up\n" % (self.name, first_command) )
def on( self ):
self._com('OUT1')
def off( self ):
self._com('OUT0')
def get_idn( self ):
return self._com('*IDN?',30)
# Is it in constant current mode?
def get_cc( self ):
return not (1 & self._com( "STATUS?", 1 )[0] )
# Returns set() of "ON"/"OFF" and "CC"/"CV"
def get_status( self ):
r = self._com( "STATUS?", 1 )[0]
s = set()
if r & 1: s.add("CV")
else: s.add("CC")
if r & 64: s.add("ON")
else: s.add("OFF")
return s
def get_current_setpoint( self ):
return float( self._com('ISET1?',5) )
def get_voltage_setpoint( self ):
return float( self._com('VSET1?',5) )
def get_current( self ):
return float( self._com('IOUT1?',5) )
def get_voltage( self ):
return float( self._com('VOUT1?',5) )
def _set( self, command, value, validate=True ):
for retry in range( 4 ):
self._com( command+":"+value )
if not validate:
return
readback = self._com( command+'?',5)
if readback == value:
return
print( self.name, "Retry", command, "got:", readback )
raise KoradException( "%s: -2- %s:%s too many retries, giving up\n" % (self.name, command, value) )
def set_current( self, value, validate=True ):
value = "%05.03f" % min( max(value,0), 5.095 )
self._set( 'ISET1', value, validate )
def set_voltage( self, value, validate=False ):
value = "%05.02f" % min( max(value,0), 30 )
self._set( 'VSET1', value, validate )
def set_ocp( self, value ):
if value: self._com( 'OCP1' )
else: self._com( 'OCP0' ) |
H: Sensor output current vs voltage reading options for accuracy
I am trying to choose between two sensor output types.
Either 0-10V or 4-20mA.
I am using the INA219B to measure current right now but I am wondering if getting a different output sensor would be more accurate.
I understand current and voltage are very different things but in this case they mean the same thing for me, how much load is on the pressure sensor (0-100% or level height.)
I am using a 1 ohm shunt resistor to measure the current for now but I can change this if it is a problem.
I am trying to measure very small changes (down to the millimeter or below of a column of diesel fuel) on a pressure sensor. The more accuracy or resolution I can get the better.
The basic calculations I have done are that to measure 1mm I either need to measure every 10mV or 16uA depending on what I choose (I am using a 1M sensor.)
I am leaning towards every 10mV being the easier one of the 2 to measure.
I have also thought about changing this whole thing to a low noise temperature compensated op-amp design, but I have little or no idea where to start with that and as I only have 12V to work with I would only be amplifying the current in this situation to get an easier reading.
As this runs off battery, I don’t like the idea of that.
If anyone has experience with measuring sensor output with the INA219B in both voltage readings and current your input would be a great help.
AI: Voltage or current output sensor have tradeoff.
Current allows a better immunity to noise if you have long wires, but requires a shunt or transimpedance amplifier which will introduce uncertainties.
The accuracy of the sensor may also depend on the type of output and will be indicated on the datasheet.
If you use a shunt, make sure to use a 4-point kelvin shunt. 1ohm will give you fairly low voltages and high-end amplifier will be required, with low input offset will be needed.
In your case, (current version) depending on the sensor max voltage output, 10ohm/100ohm shunt will give you way more signal, which will be easier to measure.
The voltage version of the sensor has a bigger range, if you don't have long wires or noise issues, you'd rather go this direction. |
H: Amplitude vs Magnitude
Consider the relation between the output and input voltages: $$V_o=\frac{V_i}{2}(j-1)$$ where j is an imaginary number, and $$V_i=5sin(1000t)$$ Now, to find the amplitude of \$ V_o \$, should we look at the real part, i.e., $$\frac{-V_i}{2}=\frac{-5}{2}sin(1000t)$$ and say that the amplitude is.$$\frac{5}{2}$$
OR should we take the magnitude of $$\frac{V_o}{V_i}$$ and say that the amplitude is $$\mid V_o\mid= \mid V_i \mid\mid \frac{1}{2}(j-1) \mid$$ where
$$\mid V_i \mid = 5$$
AI: Complex notation is a useful representation of a real-world signal, which itself does not contain any imaginary part. So, in complex notation:
Amplitude is the magnitude of the complex number (btw as Andy says, you lost a square root along the way)
Phase is the argument of the complex number
Splitting the real and imaginary parts is useful for other things. For example:
If the variable is a power, then the real and imaginary parts correspond to active power and reactive power.
If you use IQ demodulation, and multiply your signal with a sine and a cosine, the averaged and lowpass-filtered outputs of these two multipliers will correspond to the real and imaginary parts of the complex variable that represents your signal. |
H: Can someone help me make this circuit work?
I am trying to implement the circuit described in this paper in LTspice. The circuit is shown below:
The paper claims that the circuit can be used to measure the resonant frequency of the coupled LC tank. By changing the voltage of the varactor diode, the frequency of oscillation of the Colpitt's oscillator is changed to generate a frequency sweep. At the resonant frequency, the emitter current (or voltage Ve) is maximum. However, on simulating the circuit, I get the same value of Ve. The waveform of Ve is as shown below:
It does not change with the varactor diode capacitance, even though I have designed the circuit such that resonance should have occured when the varactor diode voltage will be 5V.
Edit: I am including the output of the oscillator as well:
AI: First of all, try replacing V1 by a step pulse (ok, included in LTSpice as parameter). Some time, it helps. Oscillation must be seen.
Ok. Simulations done for understanding the basic schematic.I only change R1 and R2 (polarization).
All made with microcap 12 from http://www.spectrum-soft.com/index.shtm
Basically, it is a "grid dip meter" for the "old radioamators" :) .
The essential variable is then K1 (coupling to the tag ... or another L with Cparasitic circuit tank, if you want to know what is its self-resonnant frequency). And the "knob" is C5. Here restricted in a "certain band" of frequencies.
Let's go. Sorry for the numerous pictures. Is it possible to "send" files ?
The pictures are tran or ac=sin analysis (see low noted T(Secs) or F(Hz)). The parameter (if one) is noted in the high of the picture. The value noted -> line in grey color (in principle, if I made it :) ). DC Supply (5V) is in serial with sin generator (1V, would be 1mV, relative) (for ac and tran analysis), some interference seen in tran analysis ... Note that magnitude output is important (some 15 v peak, no "load"). C5 is the simulated varactor. Good luck for the next step ...
Some other things. VE may need a "compagnon" voltage (With 2 resistors). Differential measuring and a "stable power supply" with good decoupling capacitor.
After reviewing and simulating, unfortunaly or happyly ... I made an error in the schematic ! Do you see it ?
For more information, look for the operation of the coupled circuits, primary and secondary tuned. Here is a simulation when the coupling k changes ... k=0.01 is line in red. |
H: Automated toggle circuit
I'm trying to build a automated toggle circuit which toggles in a certain frequency determined by an RC time constant. I made a circuit which i planned to toggle between 5V and transistor saturation voltage ( ground ). It does the toggle but only just once. I want the circuit to do it repeatedly like switching two outputs in a certain frequency (Not too high, like with a period of half a second or near that).
simulate this circuit – Schematic created using CircuitLab
I want when Vo1 = 5V while Vo2 is grounded and switch the states for example in 1 seconds repeatedly.
If you say that i can do it with integrated circuits, logic gates or with a 555 timer, i know i can but i want to bulid it with electrical components by myself for educational purposes, to gain more understanding.
Is my circuit design totally wrong ? How can i improve it or rebuild to manipulate those two outputs (Vo1, Vo2) with transistors and capacitors in order to make them automaticly toggle between their states in a certain frequency ?
Note : I Forgot to put the voltage source on top of the circuit. It's 5V on the top.
AI: The circuit you are looking for is called an "astable multivibrator" (astable because it runs continuously). There is a very classic two transistor circuit that works by cross-coupling the collectors and bases of two transistors, such that when one switches on, it starts charging a capacitor which will eventually do the same to the other one.
Your circuit needs to somehow implement the same idea - or of course you you could build and experiment with the one that is already well known. |
H: How does the inductor current ripple influence a switch-mode power supply?
I am looking into several DC/DC switching controllers. When talking about component selection, many datasheets and application notes say that inductor ripple should be kept around 20-40% of the inductor current (TI buck-boost design application note).
What is the reasoning behind this advice? More specifically, I understand that a high current ripple can damage the output capacitor network. Why is the advice not to minimize the inductor ripple altogether, and what are the other effects that the inductor ripple current has on the SMPS?
AI: The main tradeoffs are as follows:
Higher inductor ripple:
Pros:
Smaller inductor size, better transient response to load step and release.
Cons:
Higher core and AC losses therefore lower efficiency, and higher output voltage ripple for similar output capacitance. (Or more output capacitance needed for the same output voltage ripple).
The converter may not be able to operate at higher ambient temperatures due to higher losses in the inductor pushing the temperature closer to the limit.
For voltage mode the double poles will move to higher frequency (due to lower inductance) for similar output capacitance, meaning the loop might be harder to compensate or may have less phase margin, or you would need higher output C.
Higher input ripple may also need more input capacitance.
The transition from CCM to DCM will happen at lower load currents, which may or may not be an issue.
The 20-40% ripple current rule is just a guideline, but it's an excellent starting point. Personally I think 20% is too low unless you don't need good load transient response and have plenty of space for a larger inductor. |
H: Low Current (<500mA) Transient Current Suppression Methodologies
I am looking into possible methods of protecting against small current transients for use with a laser module and am having trouble finding information, partly because I am unsure what exactly to be looking for.
The laser generally runs around 180mA in small bursts when the system is in use and I have plenty of active protection in the way of microcontrollers in the system but my concern is possible transients that could damage the laser if there is no power to the system or if the processors are otherwise in a state unable to handle such small transients. I am speaking specifically of not allowing anything above, say, 300mA through the laser. I have tried searching for components having to do with current and transient suppression but they typically deal with power and EMI/EMC levels which are far outside of what I am looking for.
There is a small set of Transient Current Suppressors (TCS) by Bourns such as the TCS-DL004-500-WH which appear to be very close to what I am looking for although this appears to be proprietary technology and the range of max currents is small (250, 500 and 750 mA).
I am really looking for anything that might be similar or if there are particular circuit topologies that would generally do well dealing with this situation I am unsure what those would be or what to even start researching.
Anything to point me in a more targeted direction would be greatly appreciated.
AI: I suggest a twofold strategy:
use low inductance capacitive shunting around your laser diode. The laser has an instantaneous resistance of several ohms (Vf / 180mA). So build something that is in the mohms for frequencies above e.g. 10 MHz, e.g. using MLCCs. In addition, you can add an inductor/bead in series with the laser.
a semiconductor current limiter inline with your laser diode. This can be either the conventional two-transistor "constant current sink" circuit. Or even a single depletion MOSFET + resistor. Since these circuits take some ns to "act", it is important to have (1) in addition.
Taken together, these should limit current spikes between DC and ~1GHz. The integrated parts that you mention, likely use a variation of (2). If you use your own MOSFET + resistor instead, you will have better control of blocking voltage and limit current. You will probably also save component cost. |
H: What makes signal lines hot swappable?
In MAX14780E datasheet, it's explicitly featured as "hot swappable", however in AM26C31 datasheet this isn't mentioned. Moreover, I suspect that I burnt one of the AM26C31 ICs while hot swapping.
I'm aware that hot swapping is also related with the connector (GND and power should make the first contact) but electromechanical part of story is out of interest in this question.
Are the driver chips burnt only because of the rising voltage caused by dI/dt during the disconnection? If so, is placing a TVS between RS422 driver (and receiver?) and connector enough to prevent from such effects?
AI: The hot swap feature of MAX14780E does not mean the RS-485/RS-422 bus side, as most RS-485/RS-422 transceivers are obviously hot-swappable on the bus side by definition.
For this chip, the hot-swappability means the logic level side.
It simply means that when you supply power to the chip, the RE/DE inputs have safety mechanisms that prevent the chip from accidentally driving the bus while the powers are still rising and stabilizing and the RE/DE inputs can also be at indeterminate voltages while the power is still turning on.
If you do that to a standard chip that has no hot-swap feature, it is not guaranteed and it may drive the data bus momentarily until power has stabilized, so this may corrupt ongoing transactions. |
H: ESD pins of CM1624
I am considering to design SD interface with a CPU. For ESD and EMI, there are some ICs that can prevent these issues with RLC filter and TVS diodes such as CM1624. What I am wondering about is that what are for ESD1 and ESD3 pins of CM1624?
Thanks.
AI: Those are just extra pins you can use for any arbitrary purpose, like for the card insertion or write protection contacts of the SD card holder. |
H: 1 input 2 outputs logic
I have a system that can only supply very low current > 10mA at 12v. It has one output that will pull high or low depending on if it is powered on or not. I have another device I would like to control based on that output, it has an up, common, and down. When connecting up and common it turns on, when connecting down and common it turns off.
I was originally going to use a 5 pole relay to do the switching from common to the respective up and down (NC: common -> down) (NO: common -> up) but because the system is such low current I can't trigger the coil on the relay.
Could someone point me in the right direction for doing this with transistors?
I have a very very basic understanding but I have been using circuit lab to try to build such a thing that sends output1 low, output2 high when given a high input, and then when given a low input sends output1 high, output2 low but I haven't had much luck.
For further clarification
I have a controller that has a 12v power supply capable of 10mA (current limited internally), it has a switched output that can do 12v at 2.5mA (again current limited internally)
I then have a system that has a floating (meaning I can bring the voltage up or down it's not ground referenced) and it has "common", "up", and "down" terminals. To turn it on you need to allow current to flow from common to up, to turn it off you need to allow it to flow from common to down. This system is also limited, and a perfect 1mA flows from common to either up or down when connecting it.
So these systems are very low current and protected.
I am thinking I need something like a NOT Gate and maybe a regular Gate if such things exist to pull "up" or "down" to "common" depending on if the input (output of the first thing) is high or low.
AI: If the relay would work for you and the only problem is that your control signal can't supply enough current to activate the relay, use this scheme to drive the relay:
Source: https://electronics.stackexchange.com/a/56097/95488
The "load" is your relay coil. +Vs is your 12V supply. Try 2K for RB. The transistor can be any common NPN type -- 2n3904, 2n2222. Put in the protection diode. See the source link for more details.
Update: Based on the comments, if the control signal will be either +12V or 0V you could do this:
simulate this circuit – Schematic created using CircuitLab
If the control signal only outputs something like 0 or 5V you can use the circuit on the right to invert it.
The 2K resistor is picked for about 5mA of LED current.
Instead of using the NPN transistor on the left you might be able to drive the optocoupler LED directly from the control signal if it can supply enough current.
For the transistor side of the optocouplers, connect COM to the collectors and UP and DOWN to emitters. That will allow current to flow from COM to each of those terminals. |
H: How do terminate the coax shield of AC coupled LVDS signal? (isolated grounds)
I have an LVDS clock signal that goes to several PCB cards. Frequency: 100Hz --> 20MHz
I am going to use a fan out IC to supply each card with it's own buffered CLK signal; I am not going do a 'Multidrop Connection'.
PCB cards are isolated from each other and the LVDS driver (floating SMUs).
Some cards may not be isolated from the LVDS driver.
The LVDS clock signal is feed into the PCB card(s) using (x2) 50ohm coax cables.
The signal is AC terminated to 50ohms and biased by the receiver IC.
How should I terminate the coax shield?
*I do not have and earth/chassis ground in this system. It is a prototype, the PCBs are not enclosed.
There is a PCB card (12v) Supply Voltage reference that powers the on-board isolated DCDC converters on the card(s).
However I do not want to use this at the moment because some PCB cards may not be isolated, doing this will cause ground loops. And the grounding scheme of LVDS is still undetermined, I have not designed that part yet.
Basically I want something that will 'work' regardless of how the PCB card(s) and the LVDS driver are referenced, without a chassis ground.
Is there a solution I could do that will be satisfactory?
Thanks.
He is the circuit:
proposed solution 1
proposed solution 2
AI: Of your drawn circuits, the last one with caps to GND2 will be best to shunt Common Mode noise. The one with caps to the common mode voltage will be worse, because you want to clamp the shield voltage to a low impedance node (e.g. GND)
However, the use of two physically separate cables for the LVDS lanes is questionable. You form a large loop, into which magnetic fields can couple and become differential mode signals. I anticipate this will create tons of jitter. Probably you are better off with a little impedance mismatch and proper UTP/STP cabling. You can add some resistor in parallel/series to the driver to adapt it to the TP cable.
At the minimum, twist the two BNC cables together tightly. |
H: Building a 1S Li-ion battery pack with all the cells in parallel and using a DC to DC converter to get higher voltage
I want to build a 12 V battery for my Mac Mini and possibly a 36 V battery pack for a electric scooter I plan to make later using some old 18650 cells. I have read that a lot of battery management systems (BMS), especially cheap ones, can harm your cells or just stop working.
So my question is, would it be possible and safe to connect all cells in parallel so they balance themselves and just use a DC to DC boost converter to get the right voltage output? And will it be inefficient?
And what is the best way to protect them from creating a domino effect if one cell would be shorted: glass fuses, a short thin wire that will break under high current, etc?
AI: "Some old Li-Ion cells" are the worst things to make a battery of, no matter if it is parallel, serial or mixed.
They will differ in both capacity and state-of-charge vs voltage curves, so no BMS will make them play together for long.
You can, of course, spend some time with a battery analyzer and match some of them for series connections. If they are of the same brand and model, you may as well connect them in parallel.
Good luck if you expect all of them to age at similar rate.
I am not saying it is not going to work, it is simply a waste of time and resources.
As far as I remember, Mac Mini is like ~30W max. Not that it is impossible, but it is still quite unusual combination of parameters that will hardly be efficient.
And you will hardly find 30W 3.6V input DC-DC converter off-the-shelf, you will have to make it yourself.
Now wait, you will want a monitor for your mac mini as well, ... ? 20-50W more to go.
The scooter - 100-300W at 3.6 volt is quite a challenge. The connecting wires will probably heavier than both the batteries and the dc-dc together.
A battery shorting in your setup is your least concern. The usual failure mode for Li-Ions is to fail open and not short. Most factory-made battery packs that feature parallel connections are simply welded together.
A thermal fuses are probably a better option than glass ones. A calibrated nickel stripe for welding them together is even better. |
H: Why would a multimeter give an unexpected current reading?
I assume that the multimeter should read 2A for a 2A power supply, why is it only 0.358A?
Edit: After watching a video on the basics of using a multimeter, I realised that as well as short circuiting a power supply (which will break your multimeter), I was using the terminals incorrectly; the 20A fuse has indeed blown. Luckily it was a cheap multimeter, so was a relatively inexpensive lesson.
AI: Your meter is acting as a short across the output of the adapter, since an ammeter has a very low resistance shunt for measuring current.
It's probable that the short causes a kind of hiccup current limit, meaning the output shuts down for a period then restarts. This may be too fast to see on your meter, so the meter is reading the average current, not the peak. (Or it could be fold-back limiting as well as others have mentioned.)
An ammeter is meant to be put in series with the load, so if you put it in series and gradually increase the load to the point of current limit you should be able to measure the max current out of the adapter. |
H: How do I use the 'generate' keyword in Verilog
I am trying to create a basic example of the use of the 'generate' keyword in Verilog, in EDA Playground. However, it gives me errors that I don't understand.
module CrossBar( clkIn,
inputs,
switches,
outputs);
parameter NUM_IO = 4;
parameter NUM_SWITCH_BITS = 2;
input clkIn; // These are 1-bit variable declarations
input [NUM_IO-1:0] inputs;
input [NUM_SWITCH_BITS-1:0] switches [NUM_IO-1:0];
output reg [NUM_IO-1:0] outputs;
always @(posedge clkIn) // Each time the input clock goes high,
begin // execute the following code:
genvar i;
generate
for (i=0; i<NUM_IO; i=i+1) begin
outputs[i] = |(inputs & (4'b0001<<switches[i]));
end
endgenerate
end
endmodule
When I try to synthesize this, I get the following errors:
ERROR VCP2000 "Syntax error. Unexpected token: genvar[_GENVAR]. This is a Verilog keyword since IEEE Std 1364-2001 and cannot be used as an identifier. Use -v95 argument for compilation." "design.sv" 26 13
ERROR VCP2000 "Syntax error. Unexpected token: for[_FOR]." "design.sv" 28 12
ERROR VCP1023 "Compiler directive `timescale is not allowed inside a module." "testbench.sv" 10 11
It suggests adding the -v95 option, but that just makes everything worse.
AI: The generate loop would go outside of the always, but there is no need to complicate your code with a generate. The for loop on its own is sufficient:
module CrossBar( clkIn,
inputs,
switches,
outputs);
parameter NUM_IO = 4;
parameter NUM_SWITCH_BITS = 2;
input clkIn; // These are 1-bit variable declarations
input [NUM_IO-1:0] inputs;
input [NUM_SWITCH_BITS-1:0] switches [NUM_IO-1:0];
output reg [NUM_IO-1:0] outputs;
integer i;
always @(posedge clkIn) // Each time the input clock goes high,
begin // execute the following code:
for (i=0; i<NUM_IO; i=i+1) begin
outputs[i] <= |(inputs & (4'b0001<<switches[i]));
end
end
endmodule
I replaced genvar with integer.
I also changed the assignment to nonblocking (<=), which is recommended for sequential logic.
Here it is on EDA playground |
H: If I put an L298N between a 12V source and a 100W DC fan, what will happen?
The L298N stepper motor controller module has a driving current of 2A ("MAX single bridge", not sure what that means) and a maximum power of 25W. I don't understand what those power limits mean. Could it damage the module if the load exceeds those limits?
I'm not sure how much load the large DC fan draws (edit: seems to be 100W), and if I connect it directly to a LiFePO 12V 20AH battery, it depletes the charge quickly and spins at a high speed. If I connect it to a 12V 2A power supply, the fan works, but feebly. I don't have a bench power supply yet (but I have ordered one), so to my knowledge I don't have a way of measuring the fan's full potential load demand (but I'd be interested to hear if there is a way, without a variable power supply).
Edit: I tried using a multimeter to measure the current, but when I connect it in series, the fan doesn't work at all (I don't understand why; maybe because the multimeter is max 20A, so at 12V that'd only be 240W, which is about 25% of what I guess the fan's load is). My multimeter unfortunately doesn't have a current clamp (perhaps I should get a better multimeter).
If I put the L298N module between a 12V battery and a large fan (edit: seems to be 100W), could it burn the module out? If it would burn out, how would you prevent this? A resistor?
Edit: I've done some digging on the salvaged DC fan, and figured out from the wiring diagram that it perhaps draws (edit: 8.7A) on a 12V circuit. So, I guess it's a 100W fan and could always try to draw that amount of power? It also seems to come with a 0.8 Ohm resistor attached, but that's not actually connected to anything (the wiring diagram seems to suggest that it is used with the low fan speed relay).
Edit: I ordered a 12V 20A power supply (edit: seems to be overkill, as I now realise it's probably a 100W fan instead of 1000W), and plan to use the 0.8 Ohm resistor that comes with the salvaged fan. I also have a 12V 40A automotive relay that I plan to use (edit: but maybe that's overkill). I hope I can control this relay with a 3.3V IC. Someone please tell me if this is not correct.
AI: The 298 is not a good choice for this.
If you just want to switch the fan on or off, just use a low side MOSFET with generous Amperage rating.
This circuit uses IRLB8721 which is nice because it's available in hobbyist places, it's through-hole if you're prototyping this on breadboard, and it has a low Vgs so you can drive it from typical microcontrollers, and it has 30V tolerance (so the Zener might not be needed.) There are many, many other N-channel MOSFETs who have different trade-offs on the amps / drive strength / voltage tolerance spectrum. A parametric search for parts at a place like DigiKey will find many examples of exactly what you need. |
H: Shouldn't the Thevenin equivalent have the same behavior (regarding the transfer function) as the circuit it's derived from?
I am new to electronics and I have a little trouble applying the basics I learnt so far. My problem is basically that I don't understand why we consider the second circuit below as the Thevenin equivalent, even though the behaviour of the transfer function is different.
Here you can see the parallel RC circuit.
The supposed Thevenin equivalent.
Blue is the parallel RC-Circuit and green the Thevenin equivalent. I think the behaviour of the two circuits is apparent. Also, if we derive the transfer function for the circuits, we get two different solutions.
Transfer function for parallel RC-Circuit:
Transfer function for thevenin equivalent:
AI: The voltage of the Thevanized circuit is only half that of the original. |
H: How does pulsing current through a better conductor generate more heat?
We are pulsing 20A, 12V current for electrolysis through a 6% KOH solution between two steel plates. Because of steel shortages, we have switched to a steel plate that is very slightly thicker. We are suddenly seeing 40C more heat in the system. The thicker steel plate should mean less resistance and therefore less heat. So we're thinking that the heat comes from the KOH solution. Our engineer says that if we increase the KOH to 12%, it will allow more current per pulse, so more heat. But I'm thinking that greater conductivity in the water would mean less resistance and less heat. He says it would be better to drop the KOH to 3% to reduce the current flowing per pulse and therefore reduce the heat. What would be the correct approach and, more importantly, why?
AI: If the voltage is fixed, the lower the resistance, the more current and the more heat.
$$P = \frac{V^2}{R}$$
Where P is the power dissipated by a circuit element, V is the voltage across its terminals, and R is the element's effective resistance at the given voltage. |
H: What is the capacitor in this typical application for?
I've been looking at the TC1252 voltage regulator (datasheet available here), but can't figure out what the purpose of the second capacitor (connected between VOUT and GND) in the typical application circuit example (page 3).
EDIT: Schematic Below
simulate this circuit – Schematic created using CircuitLab
AI: You are referring to the output capacitor. Per the datasheet a minimum output capacitance of 1uF is required for stability. Most linear regulators require external output capacitance for their control loop to be stable. Note that the minimum is just that, and it is usually better to use the recommended value if you can. Most datasheets will indicate a recommended range. |
H: What's the name of this DC-DC topology?
I was helping some friends that wanted to add a light load to a DC power rail in an industrial installation. The voltage to this rail comes from an array of voltage sources, with one voltage source being selected at any given moment. The range of this rail is wide, 12 to 120 volts DC.
I'd usually use an incandescent light bulb (rated for 230AC) as a sort of constant-power/slightly resistive load, as it's simple, cheap, reliable and provides a visual feedback as well. However, in this case it would have consumed too much power towards the high end of the range.
So instead I went with the idea to use 12V light bulbs (two or more in series), with some regulation added to make them a constant-power load. While at it, I thought, "well we can throw in an inductor as well", then I pondered whether I can do the current regulation via a 555, so in the end I designed this:
simulate this circuit – Schematic created using CircuitLab
It is a crude DC-DC converter (PFM mode), that pushes approx. constant current thru the lamps:
R1, D1, Q1 form a no-frills linear regulator, providing around 12V to the 555;
When M1 is on, the current thru the lamps ramps up and is measured across the R3 shunt; when it exceeds around 2A, the trigger/threshold node exceeds 1.2V, and the On cycle stops;
This 1.2V is approx what the control voltage is (using D2 and D3 as a crude voltage reference);
The current thru the lamps then slowly diminishes, and a fixed amount of time (selected by R2/C2) is allowed for that; then the cycle starts again.
All in all, this is very much like a Buck converter, however the load is not ground referenced, which allows to use a NMOS for the switch (nifty!), and a very simple current measurement for the regulation.
I'm pretty sure I haven't invented something new, but I'm curious whether this topology has a name? Or it is just a transposition of Buck?
AI: What you have is a switch-mode constant current driver. Such a circuit is used to drive LEDs. Its not a buck converter per say, but it if you consider the voltage across the LEDs to be the output, then it is going to be lower than the input. It uses an inductor current limit control scheme to regulate the load current.
I simulated such a circuit a while ago. You can take a look at it if you want. In my circuit, I have fixed both the upper and lower current limits of the inductor and have used a PMOS, but it can be done using an NMOS as well. |
H: I2C and SPI which interface to use when?
I have seen I2C and SPI interfaces being used with EEPROMs and other ICs.
From an Hardware Perspective, what interface should be selected when ?
One obvious reason I can find is that, I2C uses only 2 pins whereas SPI uses 4 pins.
So, if we are short on IO pins, we can go for I2C or else SPI.
And I find that SPI has daisy chaining. So, any advantage with this?
And since I2C uses only 2 pins, what could the hardware issue that could possibly go wrong with the I2C interface?
Can someone please tell me which interface to use when? And what could be the hardware issue if we use I2C ?
AI: SPI can be faster as it is push-pulled lines, in the contrary to I2C that uses pullup resistors.
SPI can be daisy-chained, but usually it requires the slave device to be of the same type.
SPI will need a CS line for each device, while I2C works by addressing.
The SPI software stack is usually simpler than I2C.
I2C allows to have many devices on the same line, but often if you need several of the same devices, they will have the same address and thus it becomes a problem. Some devices can come with different address (different part number) but that increases the BOM and cost.
Given I2C is driven by pull-down, you can have devices with different voltages (FI 5V and 3V3), the bus voltage is set by the pull-up resistors that can be of the lower voltage chip.
Can someone please tell me which interface to use when? And what could
be the hardware issue if we use I2C ?
If you hesitate, go with SPI, it's (usually) easier to interface on a stack level, doesn't need external resistor, you don't need to care about addressing and it's faster.
More details here |
H: Does the number of turns in Turns Ratio matter in transformers?
Suppose we have two transformers with same turns ratio, \$N_2/N_1\$. First transformer \$A\$ is of \$100:10\$ and the second transformer \$B\$ is \$1000:100\$. Both have same turns ratio so both can step down the voltage by 10 times theoretically. If we assume size of wires are identical at primary and secondary, current and power ratings are same (I am not sure). But eventhough turns ratio is the same for both transformers, the number of turns is different in primary and secondary.
So my question is does the number of turns in turns ratio matter? I have a feeling that \$ B \$ has some advantages. But I am unable to figure out.
AI: Number of turns on a transformer matters greatly. The turns ratio is one of many considerations in designing a transformer. The following are high-level considerations when designing a transformer.
As Tobalt stated, magnetizing inductance is important. Too few turns will consume excess current, even without a load.
You need a minimum of turns to prevent saturation of the core. Number of turns controls the flux density. If the core saturates, your primary starts to look like a short circuit to the driver. You can also control when a transformer saturates by changing the effective core area.
Increasing number of turns will increase leakage inductance (can be modeled as a series inductance either in the primary or secondary leads) which may be undesirable. There are cases where leakage inductance is desirable. Leakage inductance can also be controlled by controlling the physical positioning of the windings and can increase the cost of increased build complexity.
Increasing the number of turns will lower the resonant frequency of the transformer (larger inductance, larger self-capacitance). You want to keep the resonant frequency above the highest frequency of operation by at least 5x (my rule of thumb).
Wire diameter and type (single, bunched, Litz) is important and affects the winding (copper) loss. For a transformer operated at a single frequency, there is an optimum wire diameter which balances AC copper losses (eddy losses: proximity effect which is prominent at frequencies below apx 1 MHz, and skin effect) and DC copper losses. Proximity effect can be reduced by using bunched or Litz wire, skin effect can be reduce by using Litz wire - both are expensive options. Copper loss is an important consideration in power transformers.
Core losses are affected by flux density. Less turns have a higher flux density which mean higher core loss. Core loss is an important consideration in power transformers |
H: Pull-Up resistor for a 74LVC1G06 Inverter
As part of dual mode display port design, Pin13 goes to 74LVC1G06 inverter input (see U89):
in case where I want to choose only HDMI I need to connect a pull-up to DP_0_PIN13.
from wikipedia : "Limited adapter speed – Although the pinout and digital signal values transmitted by the DP port are identical to a native DVI/HDMI source, the signals are transmitted at DisplayPort's native voltage (3.3 V) instead of the 5 V used by DVI and HDMI. As a result, dual-mode adapters must contain a level-shifter circuit which changes the voltage. The presence of this circuit places a limit on how quickly the adapter can operate, and therefore newer adapters are required for each higher speed added to the standard."
So I understand that DP_0_PIN13 should be connected pulled up to 3.3V. the question is how do I pick the resistor value?
AI: DP_0_PIN13 is pulled down by an 1M resistor. To effectively pull it up you need to raise it to at least 2V. The pull up and pull down resistors form a voltage divider. So anything less than 0.65M should do it.
I would go with a 470k resistor just to be sure. |
H: Differentiator and integrator - without op-amp
I am trying to understand the working and function of the integrator and differentiator circuits using op-amps.
Can someone tell me why we need to use op-amps for that function? Selecting just the right value of RC components (appropriate time constant values) according to our input signal would also perform the same function, right?
What advantage does the op-amp give us and what disadvantage does the usage of RC circuits for the differentiation and integration functions gives us?
AI: You don't need the opamp, in theory. A simple, passive, RC circuit gives you am integrator or differentiator (otherwise known as first order low pass/high pass filter).
One problem is output impedance and loading. The opamp allows you to create a similar circuit which has very low output impedance, and whose characteristic will not be significantly altered when connected to a real world load, in the order of kilohms to megohms.
Input impedance might also be an issue if the output impedance of the driving signal is not very low. This could also be solved by using an opamp buffer.
A second problem with a passive integrator is that it has an exponential response to a constant input, whereas an opamp integrtaor has a linear one (until it reaches its limit of course). |
H: Is it possible to control a latching (bistable) relay with a single MCU pin?
Controlling a latching relay, like HFD2/012-S-L2 (datasheet [PDF]) with two MCU pins is straightforward:
And here is the corresponding code:
void switchRelayTx() {
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_SET);
HAL_Delay(10);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
}
void switchRelayRx() {
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_15, GPIO_PIN_SET);
HAL_Delay(10);
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_15, GPIO_PIN_RESET);
}
But when you need >= 10 relays in the project you end up out of MCU pins very soon. Thus I wonder if it's possible to control such a relay with only one MCU pin, maybe by utilizing a High-Z pin state, and without too many additional external components? Off the top of my head, I couldn't come up with the schematic.
Simply putting an "I2C pin number extender" like PCF8574 is possible of course, but I'm curious if there is a little less brute-force solution. Using a regular relay is not an option in the project because of the extra current such relays consume. Using a single-coil latching relay could be an option though.
AI: Using a 3-state pin is a workable approach. Use a pair of comparators to detect when the pin is below 1/3 VCC for one coil and above 2/3 VCC for the other coil. Then your code defines 3 states: drive low, drive high or no drive. The I/O would be tied to a midpoint voltage.
The LM339 has an open-collector output with enough current for the coil, so it would replace the transistor. |
H: PCB LED BIN/Group select?
Beginner in electronics, I'm trying to make a PCB LED under KiCad.
Everything is fine, but I can not understand the BIN (Group) forward voltage of the led ...
For example with OSRAM OSLON Square LEDs :
https://www.osram.com/ecat/OSLON%C2%AE%20Square%20GH%20CSSRM4.24/com/en/class_pim_web_catalog_103489/prd_pim_device_10285510/
In general characteristics, we have :
- Forward Current : 100 mA - 1400 mA
- Forward Voltage : 1.80 V - 2.20 V
We need to select a BIN/Group :
It means that if I choose the BIN corresponding to E2, with a forward voltage of 2.0V maximum, the current would be about 700mA maximum (and not 1400mA) ?
If I select the bin F2, with a forward voltage of 2.20V maximum, the current would be ~1400 mA ?
This means that by choosing the BIN F2, I could not have a current of 700 mA ?
Sorry for the incomprehension, my project would be to use a 700mA driver, but I do not know which BIN choose ...
Thanks.
Best Regards.
AI: The If for the bins are the test current, which means the led will have 1.8V at 700mA for bin E1.
This is not the maximum rated current, which is also stated on the datasheet at 1'400mA.
If you drive the LEDs in current (LED Driver), it does not matter as long as you have enough overhead voltage.
If you limit the current with a resistor, you will have some slight intensity differences between the bins. |
H: Autodesk Eagle check via layers
is there a way with Eagle to check all the via ?
I want to be sure that they are all vias from 1-16 layers.
I found manually a via 1-15 ( my mistake during placing it )
Is there a way with the error/rule checking ?
AI: I am working with Eagle 9.6.2. Eagle has changed quite a lot in the last 5 years so there may be some differences.
Disable the option to place the vias that are not 1-16 in the first place. In DRC-> Layers remove the via options that you don't want. After that it should not be possible to use it.
Check the Manufacturing->Drills tab. All holes are displayed there and you may spot the intrudes here.
After generating you gerber data, check the drilling files. There only should be drill file named something like this drill_1_16.xln. Any other files indicating that you may have buried vias. |
H: Why impedance matching for only certain signals and not for other signals
I have a question.
Usually, in normal communication interfaces such as I2C, SPI or even normal GPIO interfaces, we don't associate them with impedance matching.
But for certain signals (I don't know which signals are those. But I have read high speed signals require impedance matching) , we require impedance matching.
Why is it for some signals you require impedance matching and for other signals we don't associate with impedance match. Even SPI also transfers data at a max rate of 10Mbps.
Where is the line drawn and why is it drawn?
AI: The important thing is the rise time (not the pulse repetition rate) of the signal, compared to the length of the trace.
If the signal can make several round trips of the line between the driver and receiver during the rise time of the signal, then we can ignore the transmission line effects. With a trace 200 mm long, which is about 1 ns electrical length assuming typical construction, a rise time of several nanoseconds will be slow enough to work unterminated. A sub-ns risetime will certainly cause problems unless the trace is properly terminated.
The easiest way to see what's going on is to use a simulator. This is the circuit I'm going to simulate. A 5 V step with a 10 nS risetime feeds a 100 Ω transmission line. The series termination resistors will either be 10 Ω for a mismatched driver, or 110 Ω (more or less matched, enough mismatch left to see what's going on). The shunt termination is either absent, or a nearly matched at 110 Ω.
simulate this circuit – Schematic created using CircuitLab
Let's start off with the ideal case, with shunt termination, below. The shun resistor is 110 Ω, the series resistor is 10 Ω, to represent a finite driver output impedance. This is expensive in terms of drive power, as the driver has to drive the full impedance of the line with the step, and the termination resistor at DC.
The line is 40 ns long, which means the input step has made its full swing well before any reflections return.
You can see the effect of the small mismatch as the reflections return, but they only produce a small ripple on the final waveform. The switching waveform is ideal at all points on the transmission line.
Now let's use a cheaper form of termination, series, below. The series resistor is 110 Ω with the shunt open circuit. The driver only has to drive 210 Ω with the step, and no DC driver power.
We only have a clean waveform at the end of the line. The start and midpoints of the line go up to 2.5 V initially, due to the voltage division between the series resistor and the line impedance. They stay there until the reflection returns from the end of the line and lifts the voltage to the full 5 V. If we had logic gates connected to those points, especially clock inputs, they could oscillate. Series termination can only be used to drive a single receiver at the end of the line.
What happens if we don't terminate a line this long? The series resistor is 10 Ω, a fairly strong driver with no attempt at matching, below.
Without the voltage division of the series resistor, the line goes up to more or less the full voltage at once. However, when the reflection returns, it now boosts the voltage to double, which will cause substrate diodes to conduct at the inputs to the gates. These are only designed to protect the inputs from EMI, and current through them could disturb normal operation, possibly even latchup.
Even worse, when the next reflection occurs, the voltage dips below 2.5 V, meaning a clock input will see a second edge. As time goes on, the reflections subside, energy gradually being absorbed in the driver output resistance. At some point, the reflections will stop switching any clock inputs on the line.
Finally, let's have a look at a short line, below. It's still unterminated, with no shunt resistor and a 10 Ω series resistor. The input step risetime is still 10 ns, but the line has been shortened to 2 ns, roughly 16" or 400 mm of track on a board.
When the reflection gets back to the source end of the line, the source voltage has not risen very far, and the reflected signal is still quite small. Although you can see the reflections do influence the trajectory of the waveform, the signal is still 'clean enough'. There are no extra transitions crossing 2.5 V. The ringing at the top of the waveform will probably not be turning on any substrate diodes in the receiver.
At some point between 2 ns and 40 ns, the waveform will breach some threshold of acceptability. Perhaps >1 V overshoot? Perhaps the leading edge of the voltage waveform becoming non-monotonic? Perhaps the waveform dipping below the switching threshold? Any particular situation might have its own criterion for successful operation. But well away from the threshold, we can easily see what we mean by 'short enough to be OK', and 'long enough to give a problem'. |
H: Amplitude Modulation Equation (sine or cosine)
I got an exam tomorrow and I'm still confused with something. I'm sure most people are familiar with the general equation of Amplitude Modulation.
AM(t) = (Ac+m(t))cos ωc t
I found that there is another variant of which cosine is changed with sine.
AM(t) = (Ac+m(t))sin ωc t
And this also applied to both c(t) and m(t) somehow. My thought is that both can be used and it just depends on the waveform/equation given in questions. In my class we used only the one with cosine, so I never get the explanation for this.
AI: You are right, both can be used. The useful information you want to transmit through amplitude modulation is contained within the (Ac+m(t)) expression. So the fact that you use a sine or a cosine doesn't really matter in the end. |
H: How to power the raindrop sensor when needed on the same Input pin of ESP8266-01S?
I have to set up an ESP8266-01S to monitor temperature, raindrop and also water-flow while at the same time controlling a pump. There is also a request to only power the raindrop sensor when needed to read but not permanently to help the sensor live longer without being affected by electro-chemical effect.
Since the ESP8266-01S has only 4 pins available for use, can anyone advise me on how to power the raindrop sensor on demand without using an additional port expander?
AI: As a part of the question yesterday that has been complained on its feasibility (I did all the thought using my high school knowledge with little further reading so sometime, idea seemed to be stupid and blamed unreliable by some reviewer over here), I have successfully made a pump control for watering my root-top garden and answer the question myself.
Input: Control a pump using blynk app and ESP8266-01S hardware with following requirements:
Temperature sensor with DS18b20
Raindrop sensor: to stop/delay the pump from watering the garden when rain happened for more than 30 minutes and also keep the pump from longer operation if daily temperature is too high.
Water-flow detector: to prevent problem to pump
Design: The schematic is simple, just need a 5V power module(I used a mobile charger 700mA) and a single relay with ESP8266-01S module, ds18b20, water-flow switch, raindrop sensor, few headers and resistors. See my sketch on the link EasyEDA at the end of the post.
(Link on this part)
This board is a fully function wifi-relay that can switch AC power at 10A, 220VAC (max), has a built in 5V-3.3V regulator and all parts needed for the relay to work and to power ESP8266-01S.
I make the breadboard PCB to also use 3.3V power from the relay board as well. De-solder 2 headers and connect with 2 new headers on the PCB breadboard.
Link on this part
And here
Since raindrop sensor requires power for monitoring, its life will be shorten due to weather and electro-chemical reaction. I tried to use the following approach (that has been mentioned here using a MOSFET - IRFZ44N to power the module when needed and this will require another pin), but instead of a mosfet, i used a normal 2N3094 NPN transistor (and supply upto 200mA current). Since ESP8266-01S has only 4 pins and already used up all by other part, I decided to find a way to use the single Rx pin for both (1) The water flow detector and (2) Power the raindrop module. The boot will fail if Tx pin is pulled low at boot so I have to use a pull up Resistor (10K).
Yesterday, I made an unclear question on using a NPN transistor as a switch and it was responded as unreliable and not feasible.
After sometime of testing on breadboard, I successfully made this using the schematic as shown below:
R2 is a pull down resistor for Rx pin and R3 is to limit current to the base of the transistor.
To allow this to work, in the sketch, I used a timer to monitor rain every 10 minutes. In the function for updating rain status, I used the following approach. Perhaps, a current limit resistor(about 1K) is needed for protecting the Rx pin but I did not use as I have made the board soldered already and the transistor only draw current from the pin in just 1 second for reading rain status, so it would not be a big problem at all)
At input mode, if the flow detector work, transistor will also work and supply power to raindrop sensor.
and all done.
Thank you for allowing to post this work here! if anyone need the sketch, please post comment with your email then.
Link for the schematic is here!
https://oshwlab.com/ngocdd/pumcontroller
Here is some images on my work
Exit valve and flow detector set up
My rooftop garden here
Tip: For better soldering on PCB breadboard, I used this type of square routing on EasyEDA for correct placement and nice solder marks
Numbering for correct positioning of parts
Bottom view for soldering
That's is: I have the board with less than 6$. And then just play around with OTA firmware upload and revising of code... |
H: Difference between open and closed center toroid transformer
I just want to know, what is the difference between open center and closed center toroidal transformer. Open center meaning the toroid has a metal rod in the middle while the open center doesn't have anything in the middle.
Open: https://my.element14.com/vigortronix/vtx-146-050-215/50va-toroidal-transformer-2x15v/dp/2817652
Closed: https://my.element14.com/multicomp/mcta500-35/transformer-toroidal-2-x-35v-500va/dp/9532951
AI: What is the difference between open center and closed center toroidal transformer?
There is almost no difference. Just one is ready for mounting.
Large toroidal transformers are usually bolted this way simply because it is convenient. Smaller ones may be glued into a base, either horizontally or vertically, with nothing in the center.
Consider that the toroid itself is the "conductor" of magnetism. It has a high magnetic permeability, so the vast majority of magnetic flux is contained inside that.
Whether a rod is placed in the center of the toroid makes little difference to the operation inside the toroid. This rod is also at a right angle (perpendicular) to the flux inside the toroid (circular), so it has even less of an effect. So the rod does not act as a "shorted turn" or anything and is largely "invisible" to the toroid. |
H: True RMS Vs Area Under The Curve
I'm not sure if this is the correct place to ask the question, but here goes...
Using my DS1104z scope...
I measure a 60 Hz sine wave AC voltage and read 120 Vrms for a single waveform
but when I measure a single waveform using Math/ABS Function
( Displaying negative portion of waveform as positive )
I get and Area ( under the curve ) Of 1.81 Vs
Using the calculation
1.81 Vs X 60 Hz = 108.6 Volts
Shouldn't the Vrms And Calculated Area Voltage Match?
or am I missing something?
Thanks,
Bill
AI: What you're missing is the definition of RMS:
$$V_{RMS} = \sqrt{\frac{1}{τ}\int_t^{t+τ}V(t)^2\ dt}$$
What you're calling the calculated area value is
$$\frac{1}{τ}\int_t^{t+τ}{|V(t)|\ dt},$$
which is not the RMS of the signal.
(in math terms, I believe you would say the square root and integral operators don't commute, so you can't just pull the square root into the integral and cancel it out with the square.) |
H: Trying to simplify a Boolean expression to \$X + Y + Z\$
Problem:
Prove the following Boolean equation using algebraic manipulations:
$$ Y + \overline X Z + X \overline Y = X + Y + Z $$
Answer:
$$LHS = Y + \overline X Z + X \overline Y$$
\begin{align*}
LHS &= Y + X \overline Y + \overline X Z \\
LHS &= Y( 1 + X ) + \overline X Z \\
LHS &= Y + \overline X Z \\
\end{align*}
I cannot reduce the expression to X + Y+Z.
I think there
is a mistake in the problem.
Consider the following values:
\begin{align*}
X &= 1 \\
Y &= 1 \\
Z &= 0
\end{align*}
In this case, I claim the value
of the left hand side is 0 but the value of the right hand side is 1. Therefore, the identity is false. Do I have this right?
AI: Below you can find the steps I took to reach the answer in the solution. I think you made a mistake in your second step. |
H: Keeping ground traces separate from ground plane in Altium
I am building a sensorless ESC which uses low-side shunt resistors to detect current. Good practice dictates that traces of equal length and width be connected from the pads of the shunt resistor into the microcontroller, differential amplifier, etc., like in this picture. (my FET driver has a built-in diff amp).
I did this in Altium, but since the negative terminal of the shunt resistor is connected to ground, when I added a polygon pour ground plane, Altium decided to connect the trace to the plane, like this.
(I highlighted the original trace in Altium to make it obvious.)
Is there a way to avoid altium connecting the polygon pour to the trace?
Ideally the trace itself would be separate from the ground plane, but the other three sides of the solder pad (where the trace isn't) would still be connected to the ground plane.
AI: You need to change the net connection rules of your ground pour. Select the ground plane -> Properties panel. Select some option other than 'Pour Over All Same Net Objects'.
You can also create a 'Polygon Pour Cutout' (Place->Polygon Pour Cutout) around that trace, as changing the above rule might cause things to not connect to the ground pour nicely throughout the rest of your board. |
H: Is the answer to this JFET amplifier excercise right?
The problem is the following:
*TYU 4.14 For the circuit shown in Figure 4.59, the transistor parameters are:
IDSS = 6 mA, |VP| = 2 V, and λ = 0. (a) Calculate the quiescent drain current and
drain-to-source voltage of each transistor. (b) Determine the overall small-signal
voltage gain Av = vo/vi . (Ans. (a) IDQ1 = 1 mA, VSDQ1 = 12 V, IDQ2 = 1.27 mA,
VDSQ2 = 14.9 V; (b) Av = −2.05)
I am getting all results right except for Av. I am getting Av = -7.72 vs the book answer Av = -2.05.
Is the book correct?
The problem is from Microelectronics 4ed (Neamen), in page 263.
AI: Let us see what we get.
First, we need to find the \$I_{D1}\$ and \$I_{D2}\$.
How could the Gate-Source potential difference be neglected?
If we do some math we are going to get these results:
\$I_{D1} = 0.996258mA \approx 1mA\$ and \$I_{D2} = 1.27mA\$
Now we can find the JFET's transconductance
\$g_{m1} = \frac{2I_{DSS}}{|V_P|}*\sqrt{\frac{I_D}{I_{DSS}}} = 2.45mS\$
\$g_{m2} = 2.76mS\$
As you can see so far I've got the same result as you get.
Now the AC small-signal analysis. As you can see \$Q_1\$ is a common-source amplifier. And the voltage gain of this stage is:
$$A_{V1} = - g_{m1}*R_{D1} = -9.8V/V$$
The second stage is a common-drain amplifier.
And we can find the (voltage) gain of this stage this way:
simulate this circuit – Schematic created using CircuitLab
$$V_O = I_{S2}*R_{S2}||R_L = (V_{G2}-V_O)*g_{m2}*R_{S2}||R_L$$
$$V_O = g_{m2}(R_{S2}||R_L) V_{G2} - g_{m2}(R_{S2}||R_L) V_O$$
$$V_O + g_{m2}(R_{S2}||R_L) V_O = g_{m2}(R_{S2}||R_L) V_{G2}$$
$$V_O(1 +g_{m2}(R_{S2}||R_L)) = g_{m2}(R_{S2}||R_L) V_{G2}$$
$$V_O = \frac{ g_{m2}(R_{S2}||R_L) V_{G2}}{(1 + g_{m2}(R_{S2}||R_L))}$$
Therefore the voltage gain is:
$$A_{V2} = \frac{V_O}{V_{G2}} = \frac{g_{m2}(R_{S2}||R_L)}{(1 + g_{m2}(R_{S2}||R_L))} = \frac{R_{S2}||R_L}{\frac{1}{g_{m2}} +R_{S2}||R_L } = 0.786325 V/V$$
The overall voltage gain is:
$$A_V = A_{V1}*A_{V2} = -7.7V/V $$
So, to answer your question:
Is the answer to this JFET amplifier excercise right?
No, the answer given in the book is wrong, your answer is good. |
H: Does placement of resistor and cap in a button debouncing circuit make any noticeable difference?
I'm making a prototype PCB with an STM32 chip and I want a couple of tactile switches for various reasons. I have followed the button debouncing circuit as done on the dev board:
My PCB design is physically fairly large (250mm x 150mm) and the buttons are approximately 70mm away from the microcontroller (due to physical constraints). Now my question:
Do I want my resistor and cap (C40 and R45) to be physically close to the button or the microcontroller? Does it even matter?
AI: If you place the cap and resistor close to the MCU, then the trace connecting to the switch will also carry the transient spikes and noise from the bouncing event.
If you place the cap and resistor close to the switch, the bouncing transients will be filtered out, and the trace connecting to the MCU will have a lower dv/dt.
As others have said, given the dimensions in your application, it likely won't matter, but if the trace is routed near something sensitive, noise from switch actuation could couple onto it. |
H: What's are the material properties that distinguish a magnetic containment disk from an induction cooker?
My picture below shows a coil carrying AC current, generating an alternating magnetic field. On top of the coil I've drawn a disk of high-permeability metal. Such as carbon steel, or mu-metal.
If the disk is made of carbon steel, the oscillating magnetic field induces eddy currents which, thanks to the metal's high permeability, are "concentrated" in a thin layer close to the bottom, which is perfect for heat generation; it's an induction cooker.
But if the disk is made of mu-metal, the field high permeability of the material provides a "tighter" path for the magnetic field, and decreases the strength of the magnetic field beyond it, but without inducing currents, eddy currents, or an opposing magnetic field; it's a magnetic shield.
Mu-metal and carbon steel have many different material properties. Please can someone help me understand what the relevant differences are, and exactly how this results in such different behaviour? Thanks!
AI: Mu Metal has a very high permeability, meaning that it saturates very quickly in the presence of a strong magnetic field, and also exhibits low hysteresis loss. For cooking, a lossy magnetic material is desired, because the losses from eddy currents and hysteresis are converted to heat. In your induction cooker "high permeability" is relative; cast iron has a high permeability compared to non-ferritic alloys, but would not be considered a high permeability alloy by magnetics designers. The very features that make it a poor magnetic material in our world are just what is needed for induction cooking. Remember that designers of magnetic alloys are trying their very best to supply products that do not get hot when subjected to alternating current.
The extremely high permeability makes Mu Metal ideal for a shield for weak, slow moving or even static magnetic fields. Once saturated, Mu Metal is no longer as effective as a shield, and so "weak" is the operative word. But it is a very effective shield when used properly. We use concentric tubes of Mu Metal, which effectively eliminate the earth's field in the center, to provide a zero point for fluxgate magnetometers. |
H: Double secondary winding equal to center tap?
I am trying to create a power supply with both positive and negative voltages. Is it possible to use this transformer to create such a supply? : https://my.element14.com/vigortronix/vtx-146-050-215/50va-toroidal-transformer-2x15v/dp/2817652
Basically, want to use the center tap of a transfomer's secondary winding to create both negative and positive voltages with common ground. But I am not sure if the mentioned transformer's double secondary winding can be used to do such a thing. Is it two separate secondary windings without any connections in between? What if I connect two wires from each secondary winding together and use that as the GND ground? Will that method work? Or the voltages will be out of phase? Please need some help regarding this. Thank You.
AI: If you connect them together correctly you'll have the equivalent of a center-tapped winding.
You can think of the "dots" on the windings as the equivalent of (say) + polarity on a DC source such as a battery- you want to connect + to - to get them to add.
Note that it's equivalent to a center-tapped winding of \$2\cdot V_{Sec}\$, not \$V_{Sec}\$. |
H: How is this potentiometer connected? Is pin 2 not connected? It makes no sense
How is this potentiometer connected? Is pin 2 not connected? It makes no sense...
The resistance between pin 1 and 3 is always the same, so why is pin 2 not connected?
(Image source: Electronics Area - 8 LED VU meter circuit using LM324 IC)
I connected pin 3 to 12 V, pin 2 to the rest of the circuit, and left pin 1 not connected. It works fine, but I'm wondering if I just don't understand this drawing?
Thanks.
AI: It's connected as a rheostat. So you would either connect between the wiper and one end, or (better) tie the wiper to one end.
simulate this circuit – Schematic created using CircuitLab
A small detail but it makes the design better- it's good to pick the end you use so that the direction of the pot rotation makes the circuit behave in an expected way.
In this case, you might want to have the pot at maximum resistance when turned fully clockwise since that reduces the reference voltages and increases the bar graph display reading. |
H: When to set defaults for VHDL generics
VHDL generics can have a default value.
The rules for how they are overridden in instantiations and declarations seems to be rather complex, so I wanted to ask about the easiest and safest practices to lower the risk of simulation and synthesis mismatches due to avoidable code bugs or tool issues.
Here is a simple example. What would you do?
Definition:
entity counter is
generic(
G_NBITS : integer range 1 to 8 := 3
);
...
Declaration:
architecture behav of counter_tb is
component counter is
generic(
G_NBITS : integer range 1 to 8 := 4
);
Instantiation:
begin
counter_inst0 : counter
generic map (
G_NBITS => 5
)
AI: My thoughts
It's good practice to always mention a default value to generic during entity declaration because it makes sure that the entity can be synthesised and simulated as an individual module if needed.
Whatever default generic in the entity declaration can be overriden during component declaration in a top module*.
If there was a default generic in the entity declaration, and you want to use the same value in the top module, you can avoid using generic inside the component declaration.
If there was a default generic in the entity declaration, and you want to override it, you may do it so by overriding it inside the component declaration.
In VHDL, generic map gives the final level of overriding. It can override default generic assigned by component and/or entity. Again, this is not mandatory to do generic map, if you want the current default values.
I was never really a fan of component declarations in VHDL cluttering and 'duplicating' on a top module, so I prefer giving a default value to all generic during entity declaration. Then putting all component in a package, or use entity work.entity_name during generic map and port map. And override all generic during generic map () instead, if I want to.
Synthesisability
The rule is that: Simulator/synthesiser should be able to resolve the final value of generic of the instance at any of the three levels mentioned above.
The resolved value will be used for simulation as well as synthesis. If it's not able to resolve, it will throw errors during synthesis/simulation.
There will be no synthesis-simulation mismatch as the resolved value will be used to synthesise as well as to simulate the instance.
*Top module : is any other module/entity in the higher hierarchy which instantiates the entity in question. |
H: Converting analog voltage to drive interrupt signal in PIC microcontroller
I have a circuit that will output between 1v-4v when the circuit detect an event. When there is no event, the output voltage stays at 5v.
I want to use this as an interrupt input signal to my PIC18f4550 microcontroller so that when there is an event (i.e output voltage drop between 1v-4v), microcontroller will wake up and execute certain tasks.
Is there any simple circuit I can look into to convert this drop in voltage to 5v High digital signal that can be used as an interrupt input signal to microcontroller?
I do not wish to use analog input pins as ADC will requires constant polling to detect the change in input. I am looking for ways to work purely based on interrupts.
Update 1
I end up using comparator module and it is working fine. The only limitation was I could not use the internal comparator voltage reference module as it could not provide the reference voltage I need. I had to use additional wire with a simple voltage divider circuit to provide the necessary reference voltage. Otherwise, it works very well.
AI: The PIC18f4550 has analog comparator pins. You can supply an external voltage to defined the point at which they switch. An article about using them is here. |
H: Full bridge rectifier for a 5 ns pulse
I want to build a system to measure the time of flight for a long transmission line. The length of the transmission line is between 500 m and 3 km. The attenuation of the transmission line is 0.00981 dB/m. The impedance of the transmission line is 150 ohm. A 3 V pulse fed into a 3 km long transmission line will lead to a reflection with an amplitude of 100 mV.
I want to measure the time of flight. From previous measurements I know that the signal needs 1 ns to travel 20 cm.
My goal is to determine the length of the transmission line with a accuracy of 10 m.
My approach is to drive the transmission line with a high current output opamp, that outputs a 5 ns pulse with an amplitude of 3 V. Since the signal will be attenuated along the way, I am using a VGA (variable gain amplifier) to amplify the signal to around 3 V, so it can be read by a µController.
Infront of the VGA I am planning to place a Bandpass filter, to get rid of the noise floor and possible DC offsets. The passband will be from 200 MHz (1/5ns) to 2 GHz. I know that the bandpass filter will lead to a decrease in accuracy since the edges will become less "sharp" but thats negligible.
Infront of the VGA I placed a comparator to prevent switching uncertainties.
My problem now is:
The reflected pulse can either have a positive or a negative polarity, depending if the transmission lines end is short circuit or open end.
So I am trying to detect a pulse with a width of 5 ns that can have a negative polarity (short circuit at the end of the transmission line) but also a positive polarity (open end transmission line). The pulse occurs every 30 seconds. The voltage is 3 V, the current is 100 mA max.
What is the best way to detect this pulse with the best accuracy possible?
AI: simulate this circuit – Schematic created using CircuitLab
should do it.
Idea: an XOR is 0 when both inputs are the same, and 1 when they are different. XNOR inverts that: 1 if both are same, 0 if the inputs are different.
Since your input is AC coupled, as long as nothing happens, the upper input of the below circuit is at VCC · 3/4, and the lower one is at VCC · 1/4, so, one is high, the other low, and the output is 0.
When you get a positive pulse, it shifts the already positive input further up, so that input stays high, but it also shifts the lower input up, so it becomes high; now, both inputs are the same, and the XNOR outputs a 1.
When you get a negative pulse, that shifts your upper input down, so you get a low input on your upper input, and the lower input becomes even lower, so stays low. Both inputs are now low, XNOR outputs a 1.
Note that this relies on the protection diodes of your XNOR gate to deal with a bit of overvoltage, and undervoltage. Very often, that's not a problem. If it becomes a problem, a USB3 ESD diode array might be used to add needed protection.
It also relies on the signal level being high enough to shift these inputs – but the required sensitivity can be achieved through adjusting the resistor values. |
H: Help identify ECG signal acquisition using AD2
I have recently got into electronics. I have access to an Analog Discovery 2 (AD2) kit with signal generator and oscilloscope functions.
I have been trying to teach myself how to use this equipment by building small, simple circuits.My current experiment involves building an electrocardiogram (ECG.)
To implement this circuit, I am using an instrumentation amplifier followed by a bandpass filter. The signal obtained from the Einthoven's triangle input is filtered out after amplification.
The circuit is supplied by the 5V from the AD2:
The pins V1 and V2 correspond respectively to my left and right arm while my right leg is connected to ground.
This is the circuit I built and tried on myself:
I use the LM324's four op amps to implement the instrumentation amplifier and bandpass filter.
After rechecking my circuit several times, here is what my output signal looks like:
I can't seem to understand what is causing my output to look like this.
Why is the waveform so inconsistent with the simulation's waveform (electrocardiogram) from this website?
How can I fix this issue and obtain a better looking waveform ?
AI: As JRE said, you are missing some components common to EMG/ECG amplifiers that are crucial to their correct operation. If you re-implemented that circuit with precision components, it still would not work. I also have some degree of confidence that if you implemented a new circuit that has the necessary modifications, you can get a functional (albiet less performant) amplifier that's still based on non-precision parts.
The three basic components of an EMG/ECG/EEG amplifier are:
Instrumentation amplifier. This serves the purpose of providing gain to your millivolt signal to get it into a 'readable' voltage range, and removing common mode noise. Note that near-field effect 60Hz will not be effectively attenuated by just the common-mode rejection of an instrumentation amplifier.
Filtering. These amplifiers usually have multiple stages of active filters, which implement a comb filter + band pass filter combination. The comb filter in particular filters near-field 60Hz noise and harmonics. If your device is operating in a country that uses 50Hz, you'll need to account for that accordingly.
Input conditioning/DC offset compensation. This is the most subtle, but it is an absolute requirement and likely the main reason you aren't seeing any ECG artifacts at all from your circuit. The human body is under no obligation to produce neuromuscular signals centered at a DC offset which is between the supply rails of your circuit, even with a good electrode ground reference. Usually amplifier circuits have multiple stages of DC bias compensation (RC high pass with DC bias/voltage reference on each electrode input, and active low band-edge high pass on the output). The value you use as your reference depends on how you manage your supply rails; i.e. if you have matched positive and negative supply rails, you can use 0V as your reference, but if you want to go with a monopolar supply you'll need to establish a virtual ground. |
H: Why does my 120V 40W lightbulb only have 26 ohms across it?
I thought that if the voltage source is 120V and the lightbulb is 40W then the current would be 1/3 of an ampere meaning that the resistance of the lightbulb would be 360 ohms. But when I checked it with my multimeter, it was only 26 ohms. The multimeter is not wrong. If I check a 1K resistor with the multimeter it reads 1K.
AI: Filaments heat up to produce light and the tungsten they're made of will change resistance as this happens. The temperature change is let's say 3000K, the temperature coefficient of resistance for tungsten is 0.0045/K, so the resistance when the bulb is on will be about 13.5x what it is when it is cold. Plugging in your measured 26 ohms gives 351 ohms when hot. |
H: Choosing the right op amp for ECG application
My current experiment involves building an electrocardiogram (ECG) as in this previous question.
How should I go about finding the right op amp for this application?
In my attempt to implement the circuit, I'm currently using the LM324 Op Amp from National Instruments as this was what I had available.
I know that the signals I'm trying to detect are on the level of microvolts, therefore it is imperative to choose the right opamp.
This is the schematic of the connection:
My output waveform doesn't look quite satisfying.
I was told in the previous question's answer that the op amp might be the cause for this problem.
Can someone refer me to the best op amp for this application?
What are the conditions one should look for while choosing the right op-amp for an ECG project?
AI: It's certainly possible to make such a circuit work with bipolar op-amps like LM324, but it requires very good understanding of the many non-ideal behaviors of those parts, and the ways of working around them. By using LM324, you're converting a relatively simple problem into something even a professional would have to spend some time on.
Another problem is that when performance matters, the circuit diagram doesn't nearly have enough information: the actual physical implementation absolutely matters. You need photos of how your circuit is laid out, and how it's connected to the subject, what the electrodes are, what cable is used to connect, and so on.
As for op-amps: if you want to stay vintage, look for CA3130 cmos op-amps. They are not made anymore, so you'll usually get fakes if you buy them. They were released to market in the 70s, very soon after LM324 was made available.
Instead, since you're into retro electronics it'd seem, I'd suggest CA3130's successor: the CA3140, introduced in very late 70s or very early 80s. It is still being made by Renesas, and you can get it from reputable suppliers like DigiKey. Originally it was a National Semiconductors part, I believe.
Speaking from personal experience, I've made active EEG electrodes using CA3240 as a low-gain transconductance stage - one half of the dual was the non-inverting amplifier, the other was the cable driver. The output was a small current (on the order of 100uA). This lets you avoid a fully differential: one electrode is the ground. A pair of 9V batteries provided power on the other end of the cable - the power was floating. The cable receiver was something like LM324, since it had to rectify the current to drive two light bulbs that acted as isolators. Photoresistors were used as both feedback elements and the receivers on the other side of the isolation barrier.
Now, EMG differential pickups can be close together - an inch apart is plenty. This makes shielding easy, and the whole electrode can be assembled on copper-clad board acting as a ground plane.
The EKG is a bit of a different problem, since you need relatively long leads. The general idea is to minimize both the input capacitance and the average DC current. For the first, you'd use a shielded cable and drive the cable shield with the output of a voltage follower - that way you bootstrap the shield and reduce the effective cable capacitance at low frequencies (that you care about) by orders of magnitude. For the latter, either use very low input current parts (LM324 is about a million times worse than state of the art in that respect), or add a DC current servo that measures the leakage current and nulls it. This is generally tricky to do. Cable bootstrap will be the first step towards improvement, though. |
H: Altium Schematic Compilation Error
I have a very simple schematic layout which is for a board that gets 5V from a header pin, supplies 2 TRS audio jacks (J1, J2) and carries analog output from these jacks to an output through different header pins.
I'm trying to make convert this schematic into a PCB and I get the following error and I couldn't figure out how to resolve this. Help would be appreciated!
AI: As @Troutdog says in the comments, you need a component (schematic symbol and footprint) to provide connection points for 5V IN, CH0, CH1, and Ground.
When I want to have points to solder wires to a board, I often use a 1 pin component on the schematic, and a footprint consisting of a single pad on the PC board (You may have to make both the schematic symbol and footprint).
Alternatively, you could use a four pin header schematic symbol and footprint, but the single pad footprint lets you set the hole size in the pad to your liking and place the footprint where most convenient. |
H: 1-dB compression point is in the range of -20 to -25 dBm
I am reading the Razavi's textbook RF Microelectronics 2nd edition p. 18.
It says
1-dB compression point is typically in the range of -20 to -25 dBm (63.2 to 35.6 mVpp in 50-Ohms system) at the input of RF receivers.
I know the definition of dBm is a power level expressed in decibels (dB) with reference to one milliwatt (mW).
However, I still have trouble to calculte -20~-25 dBm and 63.2~35.6.
Could anyone please help me in this? or provide me with some relevant reference. Thanks!
AI: In order to go from dBm to Volts peak-to-peak you have to
Convert dBm to it's raw power value over an assumed \$1 \space\Omega \$ impedance. There's an intermediate step where we must first subtract 30 from the dBm value to yield dB.
Multiply the power value by the impedance of the system then take the square root. This value is the real RMS Voltage. This is from the classic \$P = \frac{V^2}{Z}\$.
Multiply the RMS Voltage by \$\sqrt{2}\$ to yield the absolute peak of the Voltage.
Multiply by 2 to yield the final peak-to-peak Voltage.
$$V_{RMS} = \sqrt{10^\frac{{dBm - 30}}{10}(50 \space\Omega)}$$
$$V_{peak} = \sqrt{2}V_{RMS}$$
$$V_{pp} = 2V_{peak}$$
For -20 dBm:
$$V_{RMS} = \sqrt{10^\frac{{-20 - 30}}{10}(50 \space\Omega)} = 22.4 \space mV$$
$$V_{peak} = \sqrt{2}(22.4 \space mV) = 31.6 \space mV$$
$$V_{pp} = 2(31.6 \space mV) = 63.2 \space mV$$
Repeating for -25 dBm:
$$V_{RMS} = \sqrt{10^\frac{{-25 - 30}}{10}(50 \space\Omega)} = 12.6 \space mV$$
$$V_{peak} = \sqrt{2}(12.6 \space mV) = 17.8 \space mV$$
$$V_{pp} = 2(17.8 \space mV) = 35.6 \space mV$$ |
H: As amounts of the 2 charges are given only by symbols , how do I determine the amount of charge of \$Q=CV~\$ of cylindrical capacitor?
The cylinder exists with the height \$d\$ and the radius \$a\$
The cylindrical shell surrounds that cylinder with the cocentric radius \$b\$
The space between of it has been filled with the dielectric of \$ \epsilon_{} \$
\$Q_{1},Q_{2} \$ are given to the inner,outer conductors respectively.
I want to calculate the capacitance of this capacitor.
First things to first, the electric field inside the dielectric is easily obtained by
$$ \left( 2\pi r \cdot d \right) E_{r} = \frac{ Q_{1} }{ \epsilon_{} } $$
$$ E_{r} = \frac{ Q_{1} }{ 2\pi rd \epsilon_{} } $$
To find out the voltage between the conductors,
$$ V= -\int_{b }^{ a} \frac{ Q_{1} }{ 2\pi rd \epsilon_{} } \,dr $$
$$ = \int_{a }^{ b} \frac{ Q_{1} }{ 2\pi rd \epsilon_{} } \,dr$$
$$ = \frac{ Q_{1} }{ 2\pi d \epsilon_{} } \int_{a }^{ b} \frac{ 1 }{ r} \,dr$$
$$ = \frac{ Q_{1} }{ 2\pi d \epsilon_{} } \ln\left( b/a \right) $$
The problem begins from here.
I attempted to use the general formula \$CV=Q\$
$$ C=\frac{ Q }{ V } $$
How the value of \$Q\$ is determined?
As the distributions of charges are one of the typical patterns like \$0<Q_{1}=-Q_{2} \leftrightarrow \left| Q_{1} \right| =\left| Q_{2} \right| \$
I can determine \$Q=Q_{1}\$ but how about it is not guaranteed of \$0<Q_{1}=-Q_{2} \leftrightarrow \left| Q_{1} \right| =\left| Q_{2} \right| \$
Or can I assume \$ \left| Q_{1} \right| =\left| Q_{2} \right|\$ forcefully?
By the way I assumed that the any electric field is vertical against the surface of the flank of the inner cylinder. Is it correct?
The inner conductor is given \$Q_{1}\$ but the distribution of the charges is undefined.
AI: The capacitor in a static electricity apparatus is sometimes just
a sphere on a stick. The capacitance of such an item is calculated
with the assumption of a very-large-container around the sphere, which
is grounded. This 'ground at infinity' means that a second electrode is
assumed to exist, with access to whatever charge it 'needs',and that
means the second electrode carries equal and opposite charge to the first. Exact dimensions of an outer container, if it is sufficiently
large, are irrelevant (the E-fields fall off with distance, all the capacitive field energy is near the sphere on the stick).
In circuits (not static electricity) a capacitor has two terminals,
but the same assumption can be made, that the (outer, usually) electrode is
grounded, i.e. has access to an inexhaustible charge reservoir, and
thus will always take on an equal and opposite charge to the inner.
Since the imbalance of charge on the two plates does not change the
capacitance (which is a dimension-geometry-and-materials dependent number), you
can safely assume that the outer holds charge -Q1, if that
helps the calculation. Then the 'Q' of your formula is the
charge on the inner electrode, Q1. |
H: JTAG while running off HSI RC Osc
I'm currently trying to decide if I need an external xtal for my design that's using a STM32F103xF mcu.
The accurate timing requirements I can see being necessary are for programming the device over USB and possibly with JTAG.
I've seen that USB 2.0 is specced to requiring a frequency deviation of no more than +- 0.25% which is quite outside the range of the F103 HSI, but I can't find if there's a set deviation requirement for JTAG.
The mcu has a deviation of -2 to +2.5% off the HSI RC Osc , does anyone know if this will suffice to flash over JTAG? If I can avoid putting an external XTAL on my board it would save a lot of headaches as I'm extremely space constrained but will do it if necessary to flash and debug the mcu.
AI: JTAG does not need an external clock for the MCU. You can for example program an empty STM32 MCU via JTAG. Flashing it via UART also does not require external clocks, as it adapts to any baud rate within limits.
Using USB requires an external clock or crystal. It reads in the datasheet too that HSE must be used for PLL in this case. |
H: How did they get 240V from one leg (L1)?
A neighbor lost his L2 connection to his house. The symptoms were as expected. Fifty percent of the lights and outlets did not work and all his 240V appliances (AC, fryer) did not work. The utility company Xcel came out and installed a "black box" that gave him back his 120V to the entire house.
What I figured they did was they disconnected L2 and just added a jumper from L1. This would mean he would have 120V throughout the house, but not 240V.
Nope, he had AC and he showed me the box they attached to the meter.
So, I am wondering what this black (yellow) box is.
Somehow Xcel created a second 120V out of phase 180-degree L2.
I can only think of two ways.
The are using the 120V and a VFD to create L1 0-degree and L2 180-degree.
The box has two transformers. Convert 120V to 60V with a center tap ground and then convert the 60V L1 and L2 up to 120V.
If you know what is in the "black box" can you include a link so I can find out more about this?
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. Two possible solutions using off-the-shelf transformers.
(a) shows a single-phase transformer connected so that the output is out-of-phase with the input. (Note the dots on the primary and secondary coils.) This produces 120 V between each phase and neutral and 240 V between phases.
(b) shows a similar solution using a centre-tapped transformer which may or may not have a secondary winding (which isn't required). Here voltage on the top half of the transformer induces a voltage on the bottom half.
Note that L1 will have to supply twice the current. This will result in some voltage drop and heating of the supply line but is probably deemed OK for a temporary fix.
I don't see how (b) would change the phase to create L2 by simply running it through a primary coil with a center tap.
simulate this circuit
Figure 2. (a) The original again and (b) the same circuit rearranged.
If you're willing to believe that Figure 1a or 2a works then have a look at 2b. Here I've just taken the secondary coil and moved it round to the "primary side" of the schematic representation. On the real transformer they're still on the same core and nothing has changed.
The reason it works is that the P winding is energised by L1-N and the S winding is energised by transformer action. It is important that the phasing is maintained - note the dots on XFMR1 which show the relationship between the voltages. If we swap the secondary winding orientation then L2 would be in phase with L1 and you'd have L1-N = 120 V and L2-N = 120 V but L1-L2 = 0 V. |
H: How to Identify my TFT LCD Driver Chip
This is one of my TFT LCD which I have no Technical details.
How can I find which driver chip they have used? I have previously interfaced TFT based on RA8875 driver. So I Have a basic idea.
I have read about chip ID for the driver. But Ra8875 did int mention anything like that as far as I remember.
Can we read through 16 bit interface on some register and find?
Regards
AI: Do a google search on the flexcable code FKJ50002 and you will find several hits. One of the first is https://evertdekker.com/?p=257 which presents a library for that same display and claims that the controller is an SSD2119. |
H: BJTs dangerously getting hotter as drawn current accumulating
I already ask a few questions on this project (so i won't explain everything again as it would be too long). I basically have a high power opamp (OPA462) to which i feed a signal (but i offset it with a voltage divider before in order to avoid negative output voltage values). Then i boost the output current with 2 BJTs (it's looks a lot like an AB amplifier):
Some of you told me to not test this circuit in real life, but i did. And it worked really good. I just had one unpredicted problem: my power supply is showing the current drawn by the circuit accumulating as soon as i am NOT sending any signal (so basically the circuit is just powered ON but no AC signal is being sent). But as soon as i send a signal, that current rising with time phenomenon disappears, but restarts immediatly as soon as the signal is OFF. When the current is rising, the transistors gets hot proportionally (i tested it several times and they seem to get a bit hot at around 300mA).
So my take on this is that that "current leak" is happening in the region where there is the BJTs and the power supply, so if you look at my circuit below , the problem should be happening from Vcc_U1 passing through BJT Q2 then BJT Q1 and finally to V3. And i guess than the voltage output of the opamp is the culprit.
You can see the current passing through the emitter of the BJTs shutting ON and OFF alternatively when there is a signal (so i guess in that case the V_be of the BJTs is well defined, meaning it's completly CLOSED or OPEN) BUT when no signal is sent, the output voltage of the opamp is just the constant offset value (60 volts).
I feel like this is where i should try to find the solution as this voltage may be giving a V_be not small enough to shut the 2 BJTS completly OFF. Is there a way to stop that current leak by reducing these V_be when the signal is OFF? But also when ON because there is room for improvement regarding Q2's performances (current is not complety 0mA as opposed to Q1)
/////////////////////////// WHEN THE SIGNAL IS ON /////////////////////
And here is what the BJTs's V_be looks like when the signal is ON :
////////////////////////// WHEN THE SIGNAL IS OFF //////////////////
And here is what the BJTs's V_be looks like when the signal is OFF :
Btw, i'm a noob in electronics so please keep the explanation as simple as possbile.
Thanks in advance for your precious help !
AI: my power supply is showing the current drawn by the circuit accumulating as soon as i am NOT sending any signal
That's what we EEs call the quiescent current or biasing current.
You can see the current passing through the emitter of the BJTs shutting ON and OFF alternatively
That means you have a "class AB output stage". Read more here.
Class A means the transistors always stay on.
Class B means the transisors "take turns" one is on, the other is of and vise versa.
You have a class AB stage, both transistors are on when the signal is small (or when there is no signal) only when the signal is somewhat large, the circuit operates in class B.
I suggest that you lower that biasing current so that the ciruit will operate closer to class B. Note that the closer you get to class B, the more signal distortion you might get at certain signal levels. This does not have to be an issue! It depends on how much signal distortion you can tolerate.
How do I lower that biasing current?
That current is mostly determined by the base-emitter voltages of the transistors. The base-emitters of Q1 and Q2 are in series and here their voltage is set by D1 and D2.
If you would lower the voltage across D1 and D2 that would lower the biasing current. Unfortunately, this is not so easy.
A much easier and safer option is to "burn" some of that voltage across some small resistors. I would add a small value resistor (start with 0.1 ohm) in series with the emitters of Q1 and Q2 and simulate to see what happens.
That part of your circuit would then look like:
simulate this circuit – Schematic created using CircuitLab |
H: Buck Converter Voltage waveform at the free wheeling diode cathode and anode
I am trying to understand the voltages at the free wheeling diode's cathode and anode in a buck converter.
During the ON-state (as in the above circuit diagram), I assume the voltage at the diode's cathode would be like a constant voltage (We can measure the switching frequency waveform at this node).
And at the diode anode, we would observe 0V in the case that node is taken as the ground reference.
Whereas in the OFF-state, since the diode would be forward biased, what would be the voltage at the diode anode and cathode?
At the diode cathode, we obviously would see the switching frequency (the LOW period in the switching frequency waveform). Am I correct? But since the diode is forward biased, would the voltage at the cathode go 0.7V (whatever the forward drop of the diode is) below the anode? So, if the anode was at 0V previously in the ON-state, would the voltage at the cathode be -0.7V during the OFF state? Because, since the diode conducts, we need the anode voltage to be 0.7V greater than the cathode. And since the anode is tied to a 0V reference, the cathode would be at -0.7V during the OFF period of the switching frequency, right?
Can someone explain whether my understanding is correct?
AI: Yes you are correct.
When the switch opens, the inductor attempts to keep the current flowing through itself, it generates a back emf which is created in an attempt to keep the current flowing.
When a back emf is generated by an inductor, the voltage at the end of the inductor that the current is flowing towards must rise or, if this voltage is held constant (as in your circuit example) then the voltage at the other end of the inductor must fall. So when the switch opens, the voltage at the left hand end of the inductor is driven down, forward biasing the diode and holding the diode's cathode at about 0.7V below ground. The current, which is being forced to flow in the inductor (current in inductors must change magnitude slowly) flows in a square, down through the load to ground, through the forward biased diode and back up through the inductor to complete a circuit. The current also adds charge to the capacitor. |
H: Buck Converter Switching Loop Area in Layout Should be small
I have seen recommendations in the datasheets of buck converters, that the switching loop area should be as small as possible. Can someone help me on what would happen if the switching area is large and how it might or cause harmonics?
Or rather, whether a large switching loop area would cause harmonics?
Can someone help me to understand the concept behind it , if possible some visualization with a 3D cross section of a PCB, please.
AI: The basic idea is to eliminate parasitic inductance and resistance in places with high di/dt currents. Since V=L*di/dt, extra unwanted inductance can create ringing, EMI, and large voltage spikes which may impact reliability and performance.
For example, the input capacitors on a buck converter can have large fast pulses of current every time the top switch turns on. If they are far from the drain of the top FET, or not connected solidly to ground, it can cause ringing and EMI.
Also if the source of the lower FET or the output caps are not connected directly to ground with a low impedance, you can have similar problems. Output ripple an spikes can be much worse if the output caps have additional series inductance due to layout.
Parasitics on the swich node can cause excess ringing which in some cases can exceed the VDS rating on the FET causing reliability issues and EMI. |
H: What causes harmonics in DC-DC Switching converters like Buck and Boost Converter
Can someone tell me what and how the harmonics are caused in the DC-DC Switching converters?
I tried to read this, but I am not understanding. Can someone please explain in simple terms
AI: Every signal in nature has its own natural harmonics along with itself. Fourier showed that every signal is made up of sine waves having integral multiplies of the natural frequency. This is true, even if the signal itself is a square wave or a random noise, or even an electromagnetic wave.
So, if your switching converter has a switching frequency of, say, 100kHz then it's obvious that there'll be 200kHz, 300kHz, 400kHz sine waves along with the switched voltage or current.
Of course, it's possible to control (e.g. tame) the amplitudes of these sine waves. |
H: Soldering Iron Temperature for Lead Free Solder (Sn99.3%, Cu0.7%)
Recently I bought this lead free solder (Sn99.3%, Cu0.7%), D0.6mm.
I have seen many suggest at least 350°C for soldering iron.
But I tried at around 225°C (between 200°C - 250°C), the solder still melt well.
All shinny
Some shinny some dull, as can see the right bottom, reflection of me taking photo
Funny thing is, the lead free solder surface should be dull as everyone is saying. For my trial, it gets shinny surface and of course dull surface also. And the solder flow I feel quite ok actually. Not like everyone is saying, hard to use.
Should I depend on lead free solder diameter size to determine temperature of soldering iron?
Or should I follow 350°C as the solder surface sometimes shinny and sometimes dull?
AI: I've been soldering with both lead-free and tin-lead soldering wires for 15 years, and I've never seen a Pb-free soldering wire melting easily at lower than 390 degrees Celcius.
In my experience, it depends on the diameter of the soldering wire, the size of the tip, and also the area of the copper that you are soldering to. For example, if you are soldering a component to a PCB where there's a pad with huge surrounding copper, you might want to increase the temp of the iron to even 450 degrees. I know, that sounds ridiculous but remember that copper can cool down the tip of the soldering iron. So you might want to use a larger tip or increase the temperature to a safer level.
Likewise, if you are using thinner (e.g. 0.75mm) Pb-free soldering wires, even 350 degrees could be enough.
To sum up, I personally recommend you try and see. Be careful though, you may kill the component or harm the PCB, if you keep the iron touching for too long, even if the iron is set to a relatively lower temperature.
PS: I hate Pb-Free solder wires, BTW. |
H: AC analysis of voltage divider CE amplifier - how are non-parallel resistors treated as parallel?
The textbook I'm reading (Electronics for Guitarists by Denton J. Dailey) has this to say about the AC equivalent of the circuit:
The power supply voltage source VCC provides a low resistance path to
ground for signals. This effectively places RC in parallel with RL. This
gives us RC'=RC||RL. Also, an AC input signal “sees” two paths to
ground via R1and R2, therefore the equivalent resistance from base to
ground is RB'=R1||R2
Neither of these points make much sense to me. What properties of a power supply make it provide a low-resistance path for AC signals, and even then, how does that translate to an equivalent load resistance RC||RL when the resistors are not in fact parallel with each other?
Similarly, what is meant by the AC signal "seeing" R1 as a path to ground? I thought maybe this was something to do with the change in current direction, but the signal is biased to always be positive.
AI: What properties of a power supply make it provide a low-resistance path for AC signals
In AC analysis you treat the DC power supply as a short.
This is justified by the rule of superposition. |
H: Accuracy of nema17 versus nema23 1.8 degree step
I am trying to decide on using a nema17 or nema23 for my 3d printer. I have already considered torque, but step accuracy is very important. I wouldn't mind moving the bed plate up and down much slower with a nema 17 if it was more accurate.
It seems that 5% accuracy on a 1.8 degree step is the benchmark. But can anyone offer some insight into which is typically more accurate or if they are the same.
AI: Short answer, it makes no difference whether you use NEMA 17 or NEMA 23 providing both supply enough torque to move your bed plate.
You need to define your need for both resolution and accuracy to make any real suggestions. If your need is a simple DIY 3D printer, then the comments below might help you.
Consider moving to a 0.9 degree stepper motor if you want better resolution using a fixed microstep setting. Microstepping is your Achilles Heel in getting good open loop positioning performance, you want to minimize it at all costs.
In a bed positioning role your number of steps/second is low, your major factors are step resolution and torque. Compare these two 1.8d NEMA 17/23 steppers to a 0.9d Moons stepper range. The 0.9d is still 5% step accuracy.
You could also consider using a geared stepper motor and reducing the microsteps, but at the accuracy extremes you'd need to make sure you always travel in one direction from a home position (this can work well for bed positioning).
If you truly are looking for higher accuracy (and not just resolution), you need to consider a closed loop positioning solution. You could do no better than change to a Clearpath servo to provide the best possible solution if your driver is Pulse/Direction. |
H: Do AC input optocouplers require an ESD protection?
I intend on using a circuit I designed for detecting an AC input line for control purposes. One of the inputs will be accessed by third party users and a cable might be connected with a decent length(>3m). The optocoupler I intend on using(VOL628A) has a diode max reverse voltage of 6V and the intended circuit is shown in the following image:
Since the diodes are connected in antiparallel, I was wondering if I should protect them from ESD. If an ESD voltage level should occur, each diode should clamp and protect the other. I know that the diodes react pretty slowly when it comes to ESD and there is a possibility that they get destroyed, but I was also struggling to find a TVS diode with a clamping voltage bellow 6V.
Therefore my question on whether or not should I use a TVS diode. Maybe you could recommend an alternative solution if TVS wouldn't help in this case.
AI: The forward current for the diodes in the opto is +/- 60 mA maximum. The series impedance is 4x 27 kΩ = 108 kΩ. With half the maximum rated current flowing from a threatening surge, the voltage across 108 kΩ is 3,240 volts. This is a scene setter.
For ESD, the event will be over so quickly that I doubt there would be any problem but, with an indirect lightning surge (as per EN61000-4-5) then you might find that a 4 kV surge (sourced from a 2 Ω source impedance) is long enough in duration to harm the resistors. This in turn might cause one to fail short circuit and then damage the opto.
In short, you need to pick the resistor types carefully and ensure they can survive the peak voltages associated with the surge. You won't really find that using a TVS across the opto input is going to help much. You might decide to absorb any residual energy that might get to the opto with a 10 nF capacitor across the input terminals. Do the math to see how big this value can be without upsetting 60 Hz operation. |
H: can somebody explain this sentence in better words?
what is the meaning of "reproducible Al values over time" and why should we need it to be reproducible over time???
and what is "production spread"?
AI: The text defines Ai as inductance in mH per 1000 turns and that it's only for cores with gapped centre leg.
The sentence confusing you is:
"Shimming core halves will not yield reproducible Ai values over time, temperature and production spread."
The manufacturer wants to mass-produce cores, making large numbers of them.
They want all the cores they make to be identical and stay that way forever. They want them to have the same characteristics and for those characteristics to never change. They can't be - but the goal is to get as close to it as possible.
When they make a core, they want to produce one with the same characteristics as the others. They want to their production line to reproduce those same characteristics in all the cores they make. They want reproducible characteristics.
They can't achieve it because the production process, materials and design cannot be perfect. There will be some inaccuracy in each core and their characteristics will vary between each one manufactured. When a quantity are made, the range which they vary by is the production spread. If you use shims, the characteristics can change too much and the spread can get too wide.
As a core ages over time, its characteristics will change. If you use shims, they can now change too much.
Across the full operating temperature range, a core's characteristics will change. If you use shims, they can now change too much.
So what it's saying is...
If you use shimming between the core halves, then you'll get too much variation between the all the cores you make.
The variations across all those cores are caused by (a) inconsistencies in the original manufacturing process, (b) the effects of temperature when operating and (c) the parts changing as they get older. |
H: What is the purpose of a 0 ohm resistor
I recently got a pack of different value resistors, but some of them were zero ohms. Is there any purpose in using 0 ohm resistors?
AI: Yes, zero Ohm “resistors” are very useful. When strategically place within a design and board layout, they can be used to enable or disable specific circuit options. You can really think of them as semi-permanent switches. When they are not soldered into the circuit, the circuit is broken and not enabled. When they are soldered into place, they allow current to flow through and enabling the circuit option.
For example, you may want the option of a general purpose output pin from a microcontroller to light an LED, or enable a motor. Using zero Ohm resistors in strategic places you can remove a resistor to disable ability for the microcontroller to enable the motor drive transistor, and place a resistor to enable the microcontroller to drive the LED transistor. Reciprocally, you can place the resistor to enable the motor drive transistor and remove the ability to drive the LED.
This is usually done to allow flexibility in the use of the PCB, or for experimental circuits. Their use can prevent the costly need of building multiple boards with only very slight differences. |
H: two hdmi cables with different resolutions
I'm using hdmi cable to connect my raspberry pi 4 to an ips display of 800X480. when I use one cable, it display one type of resolution, but when I use other cable, it display different type of resolution. how is this possible?
AI: For older HDMI versions, such as HDMI 1.4, there is no mechanism that makes it possible for the source (the Pi in your case) to get any feedback of the error rate of transmissions to the sink (your display).
The only information the source can gather is the the EDID information through the I2C/DDC link of the HDMI cable. This EDID information lists which resolutions, video timings, color formats etc are supported by the sink.
If you see different resolutions for different cables, the only thing I can think of is that somehow the communication over the EDID link broken. In that case, the source can select a video timing that all HDMI sinks must support (per HDMI specification.) One such resolution could be 640x480. |
H: How can I identify this QFN IC marked GX?
I'm trying to identify what this part could be based on the top marking, GX, but I've been totally unable to find it online. I'm pretty sure the packaging is QFN, it has 16 pins, and I know it has something to do with LVDS. It appears to have two LVDS inputs and either two LVDS outputs or one and a pair of single ended outputs that is uses to output to the microprocessor. The rest appear to be single ended, with one lead that goes into some kind of op-amp circuit which outputs into another lead on it.
I suppose what I'm looking for is any advice how I can find what this part is or how I can learn more about what it could be based on its pins. There are also some dashes on the case that I'm not sure the meaning of. There are the four dashes on the left side of the marking and another two on the right.
AI: Maybe a FSA2567UMX Low-Power, Dual SIM Card Analog Switch in an Ultrathin Molded Leadless Package (UMLP) 1.8 x 2.6 mm package. |
H: Basic RL curcuit problem
So I had an exam in basic electronics, which I passed but lost a lot of points on one seemingly easy task.
"Through the coil is passing a current equal to \$i_L=200\sin(10^5 t + 210°)\$. If R=5 Ohms and if L=46 microH, what is the current passing through the source?"
This is what I wrote:
Apologies for my horrible writing. I know I messed up on the impedance angle. But I don't understand why my amplitude of source current is wrong.
(The correct answer is \$i_E = 271,8\sin(10^5 t + 252,6°)\$)
AI: You have used an impedance triangle (and pythagoras) to calculate the total impedance. That technique would be used for a series RL circuit but not for a parallel combination.
To calculate the total (parallel) impedance use product/sum or 1/RT = 1/R + 1/XL
Using this method I get 3.385 angle +48degrees for the total impedance. |
H: P Channel MOSFET's drain will not turn off in simulation
So I have the P Channel MOSFET's Gate-Source voltage as 12-12 = 0V. This means the Drain and Source should be disconnected. However, I still see a 11.3V output from the drain. I have no idea what I am doing wrong. The threshold for the Vgs is -2V, and I am giving it 0V so it should be off. The DC power supplies are just 12V supplies.
My guess is that I should have a pull-down resistor from drain to the ground (around the LED and resistor) so that the drain pin is not floating when it is disconnected from the source. But, adding that resistor didn't solve the problem entirely.
AI: You've got the source and drain hooked up backwards. Notice that the body diode is forward biased and so it always be conducting. Swapping your drain and source connections should fix it. |
H: A/C voltage in the air?
I've been building a counter top dishwasher and just noticed that my sink is kind of grounded, around 30Megaohms resistance but 120V.
While checking that I also noticed the air near metal in my apartment has between 10-30V AC to the positive plug. Its enough to turn on small leds and confuse me to no end! I have no fancy technology, this is an old apartment with some copper and some pvc pipe.
My cheaper multimeter shows the same, and no current, this meters fuse is blown for current. Should i be worried/ Is this affecting my power bill?
AI: Any major bit of architectural metal (building frame, metal pipes,
siding or roofing) is expected to be bonded to ground. By making
a measurement from the HOT pin of a socket, you are measuring
capacitive coupling of the meter (and the hand holding the meter)
to that grounded metal. That's not a useful measurement.
Since your depicted outlet is a GCFI box, it's not enough
current to deliver a shock (or it'd trip the circuit OFF).
It doesn't indicate any 'voltage in the air' other than
the zero-volt grounded bits of the building. The power for that tiny
trickle of AC current came through the outlet's HOT wiring.
Safety significance attaches to CURRENT measurement (not voltage with
zero load) between touchable metal and the ground pin of
the power socket, with a human-body load attached (about
1000 ohms is typical). The HOT socket contact is not touchable, one hopes.
For safety, I'd recommend not leaving any probe in the power
socket. |
H: Why do non-synthesizable commands even exist in VHDL?
VHDL includes commands like access ,new and shared variable that are never synthesizable or while and loop that are still somewhat synthesizable but are never recommended to to be used.
So why do they even exist if they cant be synthesized and are only limited to simulation?
AI: Those parts of VHDL exist for use in testbenches.
Being able to simulate a VHDL design under a VHDL testbench is an essential step in the VHDL development process.
Verification is proving a design under a testbench that checks the design for expected behaviour and complains about deviations from it.
Verification is always recommended, even for small or tiny designs, but it is often mandatory. This may be under the rules of the company you work for or under the requirements of the market it's for e.g. military, aviation, safety.
Verification is essential for ASIC developments and so almost always mandatory.
So the capability to support complex and thorough testbenches is not a 'nice to have' in VHDL - it's as essential as supporting synthesis.
I would always simulate and prove a VHDL design under a testbench before trying it in a CPLD or FPGA. Simulation is where you aim to find and fix problems. Hardware testing is where you aim to prove the design, not debug it. |
H: How to calculate BCR421U LED driver external resistor to my specified current
I am using a BCR420U as a constant current for an LED indicator, the datasheet does not mention a formula for calculating the external resistor needed for a given current output, all I have is this graph.
My application uses 12-24 volts DC input and my enable will be tied to the input, so here is my first question. Would my higher enable voltage matter and the graph does not apply anymore?
I want to set my current to 5 mA so is it correct to use 20 ohms?
AI: On page 9 of the datasheet it says this:
So even if you used an infinite value for R_EXT ("absence of an external resistor") you could not expect to get less than 10 mA. |
H: About simulating an ac circuit in Pspice
Firstly, It's not homework. I already know the answer. But I couldn't see sinusoidal waves to calculate phase of voltage(V0) across the capacitor. Response of capacitor is look like damping. However, the circuit is not first or second order circuit. In addition to this, (-j12 ohm)= 0.084F is correct?
(The answer is 41.60V)
AI: But I couldn't see sinusoidal waves to calculate phase of voltage(V0) across the capacitor.
The AC analysis doesn't give you the time domain response. If you want the time domain response, you should do a transient analysis.
But in this case, the AC analysis is actually better. It will give you the phasor of the response across a range of frequencies from a single simulation run, rather than requiring a separate run for each frequency. That single simulation run will probably also be significantly faster than a transient run.
If you want to see the phase angle of the voltage across the capacitor, just plot the phase of the V(C6) phasor instead of its amplitude. Unfortunately the details of how to do that are specific to PSpice, which I'm not familiar with. But when you plot the phase, you will be able to simply read the phase of the plot rather than trying to compare two sine waves in a time domain plot, so it will be much more accurate.
However, the circuit is not first or second order circuit.
It has one energy storage element. Therefore it is a first-order circuit.
In addition to this, (-j12 ohm)= 0.084F is correct? (The answer is 41.60V)
You haven't specified an operating frequency, so nobody can answer this question for you.
That said, if you know the reactance of the capacitor, you don't even need to know the operating frequency to solve the problem. Also, the fact that reactance was provided instead of capacitance means you weren't meant to use a simulation to solve the problem either. |
H: How do phase errors appear in the NTSC color subcarrier?
So, NTSC uses a YIQ color space, with the I and Q channels encoded in a color subcarrier using QAM with the carrier suppressed.
NTSC had a reputation for poor color reproduction—“Never Twice the Same Color”—and when I look up articles that explain the reasoning for this, it says that the color problems are caused by phase errors in the color subcarrier. PAL, so I read, addresses the problem by alternating the phase on successive lines and averaging them out on the receiver, so phase errors result in reduced saturation rather than a hue shift.
My question is—how does the hue shift in NTSC appear in the first place? The color subcarrier is carrier suppressed, but synchronized to the color burst on the back porch. This means that there shouldn’t be any first-order phase errors.
So, what gives NTSC its bad reputation for color reproduction? Is it higher-order phase errors? What would cause a phase shift in the color subcarrier that wouldn’t cause an equal phase shift in the colorburst? Or does NTSC’s reputation have a different explanation?
AI: The NTSC system is sensitive to non-linear distortions, which cause dynamic phase changes, so that is why there can be differential phase errors.
Differential phase error simply means how much the brightness change affects the phase of the signal.
The burst is sent at blanking level, and thus color applied to bright levels can have these phase changes when compared to color applied to dim levels.
These nonlinearities may happen during amplification and RF modulation at the transmitter, during travel of the RF signal, or at reception and demodulation of the RF signal to baseband composite video.
The PAL system is just as sensitive too, but it simply works around the differential phase errors with the phase alternation to average out the phase difference. |
H: Lithium polymer battery charging and management
Can someone help me understand this type of lithium polymer battery charging and management. I have the following battery https://www.alibaba.com/product-detail/plug-1-5-3P-704260-704060_1600233788440.html?spm=a2700.galleryofferlist.normal_offer.d_title.5e6663bbOehjQ5
I have 2 questions:
Can I just plug this into a device without any battery management technology? As can be seen from the screen shot it says Discharge Cut-off Voltage is 3v so I'm deducting that its not going to damage the battery or set fire ect.
Do I recharge it with something like this? Or if you know of a better device. https://www.amazon.co.uk/gp/product/B074Q6LCXF/ref=ox_sc_act_title_1?smid=A25OOHM8C615QP&psc=1
AI: This circuitry you see at the output end of the battery:
is very likely a BMS -- battery management system -- which will enforce the charge cutoff voltage, discharge cutoff voltage and max discharge current specifications listed in the datasheet.
It might also enforce the max charge current, but I wouldn't count on it and it would be a good idea to make sure your charger limits this itself.
Do I recharge it with something like this?
That charger would work as it can only charge at 0.6A. You would need to adapt the plug, however, since the battery has a 3-pin plug.
You can make a suitable charger from a very inexpensive TP4056 module which you can find on Amazon, Ebay, Aliexpress, etc. The instructions are readily available on the web, for instance at:
https://microcontrollerslab.com/tp4056-linear-lithium-ion-battery-charging-module/
The TP4056 will enforce a 1A charge current limit which is within the specs of your battery. |
H: MOSFET drive circuit - purpose of C_BST and C_DRV
I was reading this application note from Texas Instruments, Fundamentals of MOSFET and IGBT Gate Driver Circuits,
(https://www.ti.com/lit/ml/slua618a/slua618a.pdf)
I don't understand - why is there a need for the C_DRV capacitor. Why is the C_BST alone not enough to supply the high side driver? The C_BST will always have V_DRV on it and when the FET is on, it will go to V_DRV + VIN to supply the high-side driver.
AI: why is there a need for the C_DRV capacitor.
On page 30 of TI app note it says:
Current starts to flow in R1 and R2 towards ground and the lower pnp transistor of the totempole driver turns on. As the gate of the main MOSFET discharges, the drain-to-source voltage increases and the source transitions to ground, allowing the rectifier to turn-on. During the off time of the main switch, the bootstrap capacitor is recharged to the VDRV level through the bootstrap diode. This current is supplied by the CDRV bypass capacitor of the ground referenced circuitry and it goes through DBST, CBST, and the conducting rectifier component. This is the basic operating principle of the bootstrap technique.
It appears that C_DRV is a bypass capacitor placed near the high-side driver to quickly provide current -- much like the purpose of capacitors placed at the output of a voltage regulator or the 0.1 uF bypass caps placed near logic chips. |
H: How to determine what kind of response this filter has
I have the next Sallen Key type filter
I have determined the transfer function and the coefficients of \$a_{0}\$ and \$a_{1̣̣}\$, based on
\$N(s)=\frac{Ka_{0}}{s^{n}+a_{n-1}s^{n-1}+....a_{1}s+a_{0}}\$
But then how do I use this to determine (or approximate) analytically what kind of response the filter has? (Butterworth, Chebyshev etc.)
This is besides making a frequency sweep using a simulator.
UPDATE
Derivating the transfer function.
I have named the node between the 47k resistances as \$V_{x}\$ and the node of the negative bias \$V_{y}\$
\$V_{out}=(1+\frac{R_{A}}{R_{B}})V_{y}\$
\$G=1+\frac{R_{A}}{R_{B}}=\frac{R_{A}+R_{B}}{R_{B}}\$
\$V_{y}=\frac{R_{B}}{R_{A}+R_{B}}V_{out}\$
Simplifying
\$V_{y}=\frac{V_{out}}{G}\$
using a voltage divider
\$V_{y}=\left(\frac{V_{x}}{R_{2}+\frac{1}{C_{2}s}}\right)\frac{1}{C_{2}s}=V_{x}\frac{1}{1+R_{2}C_{2}s}\$
\$V_{x}=(1+R_{2}C_{2}s)V_{y}\$
\$0=\frac{V_{x}-V_{in}}{R_{1}}+\frac{V_{x}-V_{y}}{R_{2}}+\frac{V_{x}-V_{out}}{\frac{1}{sC1}}\$
\$\frac{V_{x}-(1+R_{2}C_{2}s)V_{y}-V_{in}}{R_{1}}+\frac{(1+R_{2}C_{2}s)V_{y}-V_{y}}{R_{2}}+\frac{(1+R_{2}C_{2}s)V_{y}-V_{out}}{\frac{1}{sC1}}=0\$
\$\frac{(1+R_{2}C_{2}s)V_{y}}{R_{1}}-\frac{V_{in}}{R_{1}}+\frac{(1+R_{2}C_{2}s)V_{y}}{R_{2}}-\frac{V_{y}}{R_{2}}+\frac{(1+R_{2}C_{2}s)V_{y}}{\frac{1}{sC1}}-\frac{V_{o}}{\frac{1}{sC1}}=0\$
\$\frac{(1+R_{2}C_{2}s)V_{out}}{GR_{1}}-\frac{V_{in}}{R_{1}}+\frac{(1+R_{2}C_{2}s)V_{out}}{GR_{2}}-\frac{V_{out}}{GR_{2}}+\frac{(1+R_{2}C_{2}s)V_{out}}{\frac{G}{sC1}}-\frac{V_{o}}{\frac{1}{sC1}}=0\$
\$V_{out}\left[\frac{(1+R_{2}C_{2}s)}{GR_{1}}+\frac{(1+R_{2}C_{2}s)}{GR_{2}}-\frac{1}{GR_{2}}+\frac{(1+R_{2}C_{2}s)}{\frac{G}{sC1}}-\frac{1}{\frac{1}{sC1}}\right]=\frac{V_{in}}{R_{1}}\$
\$\frac{V_{out}}{G}\left[\frac{(1+R_{2}C_{2}s)}{R_{1}}+\frac{(1+R_{2}C_{2}s)}{R_{2}}-\frac{1}{R_{2}}+\frac{(1+R_{2}C_{2}s)}{\frac{1}{sC1}}-\frac{1}{\frac{1}{GsC1}}\right]=\frac{V_{in}}{R_{1}}\$
\$\frac{V_{out}}{G}\left[\frac{1}{R_{1}}+\frac{(R_{2}C_{2}s)}{R_{1}}+\frac{1}{R_{2}}+\frac{(R_{2}C_{2}s)}{R_{2}}-\frac{1}{R_{2}}+\frac{1}{\frac{1}{sC1}}+\frac{(R_{2}C_{2}s)}{\frac{1}{sC1}}-\frac{1}{\frac{1}{GsC1}}\right]=\frac{V_{in}}{R_{1}}\$
\$\frac{V_{out}}{G}\left[\frac{1}{R_{1}}+\frac{(R_{2}C_{2}s)}{R_{1}}+C_{2}s+sC1+sC1R_{2}C_{2}s-GsC_{1}\right]=\frac{V_{in}}{R_{1}}\$
\$\frac{V_{out}}{G}\left[\frac{1+R_{2}C_{2}s+R_{1}C_{2}s+R_{1}sC1+R_{1}sC1R_{2}C_{2}s-R_{1}GsC_{1}}{R_{1}}\right]=\frac{V_{in}}{R_{1}}\$
\$\frac{V_{out}}{G}\left[1+R_{2}C_{2}s+R_{1}C_{2}s+R_{1}sC1+R_{1}sC1R_{2}C_{2}s-R_{1}GsC_{1}\right]=V_{in}\$
\$\frac{V_{out}}{G}\left[s^{2}R_{1}R_{2}C1C_{2}+s(R_{1}C_{1}+R_{2}C_{2}+R_{1}C_{2}-GR_{1}C_{1})+1\right]=V_{in}\$
\$\frac{V_{out}}{G}\left[s^{2}R_{1}R_{2}C1C_{2}+s(R_{1}C_{1}-GR_{1}C_{1}+R_{2}C_{2}+R_{1}C_{2})+1\right]=V_{in}\$
\$\frac{V_{out}}{G}\left[s^{2}R_{1}R_{2}C1C_{2}+s(R_{1}C_{1}(1-G)+R_{2}C_{2}+R_{1}C_{2})+1\right]=V_{in}\$
\$\frac{V_{out}}{V_{i}}=\frac{G}{s^{2}R_{1}R_{2}C1C_{2}+s(R_{1}C_{1}(1-G)+R_{1}C_{2}+R_{2}C_{2})+1}\$
\$\frac{V_{out}}{V_{i}}=\frac{G}{s^{2}R_{1}R_{2}C1C_{2}+s(R_{1}C_{1}(1-G)+R_{1}C_{2}+R_{2}C_{2})+1}\$
\$\frac{V_{out}}{V_{i}}=\frac{\frac{G}{R_{1}R_{2}C1C_{2}}}{s^{2}+s(\frac{1}{R_{1}C_{1}}+\frac{1}{R_{1}C_{2}}+\frac{(1-G)}{R_{2}C_{2}})+\frac{1}{R_{1}R_{2}C1C_{2}}}\$
if \$R_{1}=R_{2}=R\$ and \$C_{1}=C_{2}=C\$
\$\frac{V_{out}}{V_{i}}=\frac{\frac{G}{R^{2}C^{2}}}{s^{2}+s(\frac{1}{RC}+\frac{1}{RC}+\frac{(1-G)}{RC})+\frac{1}{R^{2}C^{2}}}\$
\$\frac{V_{out}}{V_{i}}=\frac{\frac{G}{R^{2}C^{2}}}{s^{2}+s(\frac{(3-G)}{RC})+\frac{1}{R^{2}C^{2}}}\$
\$G=K\$
\$a_{0}=\frac{1}{R^{2}C^{2}}\$
\$a_{1}=\frac{3-G}{RC}\$
AI: Because you have the transfer function with all parts values you can compare this function with the general function - expressed NOT with coefficients (which have no direct relation to the kind of response) but with the pole data wp (pole frequency) and \$Q_p\$ (pole quality factor).
It is in particular the Qp value that gives you information on the kind of response.
Example: \$Q_p=0.7071\$ (Butterworth) and \$Q_p>0.7071\$ (Chebyshev).
Knowing the kind of filter response you can use filter tables to find the relation between wp and the corresponding cut-off frequency wc of the lowpass.
Transfer function (2nd order):
$$H(s)=\dfrac{A_o}{1+\dfrac{s}{\omega_pQ_p}+\dfrac{s^2}{\omega_p^2}}$$
Comment 1: In your circuit there are two equal \$R\$ and to equal \$C\$ values. In this special case ("equal component design") the pole \$Q\$ is \$Q_p=\dfrac{1}{3-v}\$ with \$v\$ = closed-loop opamp gain.
Comment 2: This "equal component design" has some disadvantages: It requires an "odd" gain value and the Qp value is very sensitive to gain variations. For this reason two other approaches are used very often (however, with "odd" and unequal values for R or C): Unity gain or gain of two (feedback with two equal resistors). |
H: Low frequency gain and extra element theorem
I was reading 'Fast Analytical Circuit Techniques' from Vatché Vorperian.
Problem 3.7 states:
This is the circuit we wish to analyze:
This is the equation we must obtain:
I fear I misunderstand something important. From what I understand, the theorem never states that \$A_o\$ is a DC gain.
My questions:
Why was \$C_E\$ left out of the expression of \$A_o\$ and \$A_o\$ referred to as a low-frequency gain!? Shouldn't \$A_o\$ simply be \$v_o(s)/v_{in}(s)\$ with \$R_f \rightarrow \infty\$, thus contain \$1/sC_E\$?
This brings me to my second question. Suppose you would have a circuit with two reactive elements (e.g. capacitors) and some resistive elements. Suppose you apply the EET to a resistor. From what I understand, you would have to calculate 3 expressions, namely the gain with the extra element nulled (\$A_o\$), the null driving point impedance \$\mathcal{L}^{(1)}\$ and the ordinary driving point impedance \$Z_{(1)}\$. From what I understand those 3 expressions should contain the expressions of the two reactive elements (since they aren't designated as extra elements).
There is the EET and the NEET. Is it technically possible to not use the NEET and only use the EET? For example say we have a resistive circuit from which we know the transfer function H(s). Say now we want to add a reactive element, a capacitor. We could technically apply the EET to have the new transfer function \$H_{C1}(s)\$ to add the new capacitor C1. Then, if we want to add a second capacitor C2, we could, starting from \$H_{C1}(s)\$, apply again the EET and get the new transfer function \$H_{C1,C2}(s)\$. Thus, the NEET in this case would be optional, no?
AI: When writing a transfer function, you try to approach a so-called low-entropy form in which a leading term is associated with a fraction made of a numerator \$N(s)\$ and a denominator \$D(s)\$. The leading term carries the unit while the fraction is unitless. For instance, if you consider the below circuit, you can write that \$H(s)=H_0\frac{1}{1+\frac{s}{\omega_p}}\$ in which \$H_0\$ is the dc gain obtained when \$s=0\$:
\$s=0\$ is like in a SPICE simulation: you open all the capacitors and short all the inductors then redraw the circuit and determine the gain. In the quick example, you immediately see that the dc gain is \$H_0=\frac{R_2}{R_2+R_1}\$. Then, to determine the pole, you reduce the stimulus to 0 V and replace the source by a short circuit. Then you temporarily disconnect the capacitor and "look" through its terminals the resistance \$R\$ you see. In this example, you see that \$R=R_1||R_2\$ which leads to \$\tau_1=C_1(R_1||R_2)\$ and immediately gives a pole located at \$\omega_p=\frac{1}{\tau_1}\$. And this is it, no need for equations, just inspection.
Now coming back to your questions:
if you want the low-frequency gain of this circuit analyzed for \$s=0\$, you have to remove the capacitor since, in dc, a cap. is an open-circuit (no current at steady-state). In this case, you analyze the circuit without \$C_E\$ but with \$R_f\$ still there. \$R_f\$ is your extra element and complicates the analysis. If you apply the extra-element theorem or EET, you start by letting \$R_f\$ go infinite (or reduce it to zero, you choose which one leads to a simpler intermediate circuit) and determine the gain in this mode. This is what Vatché did in Figure 2.13 (without \$C_E\$) and resulted in (2.41a) where \$A_0\$ is determined. Then you apply the EET involving \$R_f\$ and you have (2.47) where you see that the first term to the left is your \$A_0\$ of (2.45a) and the following fraction is \$\frac{1+\frac{R_n}{R_f}}{1+\frac{R_d}{R_f}}\$. However, the result is rearranged in a friendly way and Vatché truly excels in the exercise :)
If you apply the 2EET in the formal way, you certainly consider the two energy-storing elements in the intermediate steps but the final result is far from being a low-entropy version of the final transfer function. The best is to determine the time constants associated with each energy-storing elements and write \$D(s)=1+s(\tau_1+\tau_2)+s^2(\tau_1\tau^1_2)\$ if you adopt a slightly different formalism used in my book on FACTs. I have actually shown in Chapter 4 of my book that dealing with two energy-storing elements and applying the EET twice gives 4 possible expressions with different conditions for the intermediate reference calculations. I have adopted the simplest option which, like SPICE, considers open caps. and shorted inductors. However, you could adopt any combination you like but then need to juggle with the rest of the combinations.
As I said, you can apply the EET several times but the obtained expression becomes difficult to deal with. The best is use the general form which lets you determine transfer function up to the order \$n\$ by determining time constants associated with each energy-storing elements.
I have published many examples on the subject and you can have a look at my APEC 2016 seminar which introduces the subject. Good luck with the FACTs: the topic can seem difficult at first but when you master it, there is no going back to the classical method. |
H: Tips for placing small SMD components onto PCB
I am trying to assemble a PCB that has very small components, an example datasheet is below. I am using tweezers, microscope, and a stencil to apply the solder paste. But this is no match for shaky hands.
Most of the difficult components have pins underneath the modules like the picture below so there is little room for rework after the soldering. Does anyone have any methods they've found especially useful for placing small SMD components?
Also since I'll be using a reflow oven, would like to ask if there is a way to make the reflow curve more forgiving like extending time at max temp to allow solder to flow longer.
datasheet
AI: Tip #1:
Use low temperature 138°C bismuth based solder, you can get it in wire or paste for reflow.
This has many advantages, for the reflow, you can use a much lower heat curve, which is more forgiving, especially if you have plastic connectors.
Small "hobby" reflow oven often have uneven & unprecise temperature and using low temperature solder will give you way more headroom.
Another advantage, is that for prototyping, it will be much easier to replace components, rework and tweak things around.
Tip #2:
Apply the paste with the stencil in one swipe, especially with tight count components, this will reduce bridging.
Tip #3:
You will always have bridging in tight pitch component. Use solder flux and cupper wick, coat the wick with the solder flux and use that to remove bridging.
Tip #4:
Avoid component with pads underneath, like BGA, because you will never know if they are properly soldered without an X-Ray machine.
Stay with minimum 0603 component size unless you are really size constraint.
As for the shaking, steady the side of your palm on the table and work with the tweezers and your fingers.
You don't need to place them very accurately, you can always, once placed & before reflow, go under the microscope and push them around with the tweezers until they are properly placed. |
H: How to get 5V from 12V with server power supply unit?
My PSU has a connector for a GPU. It has +12 V, +3.3 V and GND pins (according to voltmeter).
I need to connect cages with HDDs to this connector. A HDD requires +12 V and +5V. Because the PSU doesn't provide +5V I'm going to convert either +12 V or +3.3 V to +5 V.
Usually a PSU specifies a maximum current for a given line (say 20 A for +5 V or 40 A for 12 V). The specifications for my PSU have no information about such limits for 3.3 V or 12 V; it only says that it's possible to connect a 300 W GPU to aforementioned PSU connector. I think that the +12bV line allows more current than the 3.3 V line.
I hope it's possible to use a DC-DC convertor to get +5 V from +12 V. +3.3 V is closer to 5 V but likely the +12 V allows more current. All HDDs consume about 30 A, so I think it's better to convert +12 V to +5 V. I'm going to use something like this DC DC converter.
I believe that I need to connect the +12 V wire and thr GND wire from the PSU connector to the input of this converter and two output wires to the SATA connector - please see schema below.
Will it work? Is this schema correct in general (my concern is the way how the wires connect to the converter. Is it correct to connect the first pair GND/+12 V to the converter and another pair GND/+12 V to the SATA connector)? Is it safe?
AI: There's no question what to convert here: the specs for the ATX Optional power supply specifies only 12 V power and sensing lines, from which you can't draw power. The HP-specific 10 pin version of that almost certainly doesn't provide much power over 3.3V over a long distance - that would be risky, as a 0.5V resistive drop due to cabling resistance is more sever at 3.3V than at 12V.
So, buck-convert your 12 V. (also, boosting 3.3V to 5V is usually technically more involved than going down in voltage).
Word of advise: 30A (at 5V: 150W!) is a lot, and these drives will all draw that at the same instant, namely on power on. make sure your power supply is potent enough to offer that amount of power!
I wouldn't even trust random amazon power supplies for private projects; for supplying hard drives in a server: certainly not. Get something from a name-brand power supply producer, through a reputable seller, like digikey, mouser, farnell, (tme), rs components… |
H: Problem of metastability: simulation of dual port ram
i simulate Dual Port Ram Register in VHDL and have some doubts about the metastability problem.
Dual Port Ram has 2 clock signal, one for Port A , the second for Port B. In my simulation I create two processes with 2 differentes clocks.
type memory_type is array(0 to adress_width) of std_logic_vector(data_width-1 downto 0); --> memory array
signal memory_sgnl : memory_type := (others => (others => '0'));;
begin
-- Port A
process(clk_a)
begin
if(rising_edge(clk)) then
if(rising_edge(clk_a)) then
if(we_a = '1') then
memory_sgnl (addr_a) := data_in;
end if;
data_out<= memory_sgnl (addr_a);
end if;
end process;
-- Port B
process(clk_b)
begin
if(rising_edge(clk)) then
if(rising_edge(clk_b)) then
if(we_b = '1') then
memory_sgnl (addr_b) := data_in;
end if;
data_out<= memory_sgnl (addr_b);
end if;
end process;
I have found a post here. Mr Jim Lewis made a suggestion how DP Ram with 2 clocks can be simulated. He did the same implementation. So i can conclude I did correctly.
BUT I have read We need to solve a problem metastability, because there 2 clock signal : clock time crossing.
clk_crossing: process(clk, rst)
begin
if rst ='1' then
--
a_clk_b <= '1';
a_clk_bb <= '1';
b_clk_b <= '1';
b_clk_bb <= '1';
elsif rising_edge(clk) then
a_clk_b <= a_clk;
a_clk_bb <= a_clk_b;
b_clk_b <= b_clk;
b_clk_bb <= b_clk_b;
end if; -- if rst ='1' then
end process clk_crossing;
and then the processes should be process(a_clk_bb ) and process(b_clk_bb )
Will be it correct? Did I understand correctly how to solve metastability question?
EDIT 1
The simulation of RAM is a "part" of SPI slave. SPI slave will send 8 bits vector data to RAM ( buffer of data). It has only one system clock and SPI clock + write_enb_signal ( FIFO is full and is ready to send data to RAM) . I thought Dual port RAm will work with system clk and write_enb_signal.
process(clk_a)
begin
if(rising_edge(clk)) then
if(rising_edge(clk_a)) then
...
in the simulation spi slave there is no additional clk signal for clk_a or clk_b...
Should I create one?
AI: The correct way to implement dual port RAM, or indeed anything in FPGA, is to use one system clock, with different clock enables for the two ports.
You should never use two clocks, or events from an unsynchronised domain, unless there is absolutely no alternative, for instance one clock sourced by external equipment. Synchronise the async event as early as possible to the system clock.
Once you have two asynchronous clocks reaching the same logic, metastability is unavoidable. However it can be mitigated down to an insignificant likelihood by waiting long enough, which often requires pipelined latches, in the clock resolution logic.
Matt Parker has the amusing concept of the ten.billion.human.second.century, which is about πx1019 (28:50 in to save you watching the whole video). Once you have a chance of something occurring that's less likely than that, you can more or less assume you're not going to see it in your lifetime, and neither is anyone else. Once your metastability likelihood is less than that, some people would consider it 'solved'. But it depends on how fast your system is running, how many of them you've deployed, and what the penalty is for failure, whether you'd want a bigger number or could tolerate a smaller one. Being able to predict a failure probability though is hard. You need two points on the probability/wait_time curve, and even if the failure rate with no pipelined latches is measurable, it will often not be easily measurable with just one latch. People use increased clock rates, and carefully set up the input conditions to provoke failure, to make these measurements. |
H: Timer maximum and minimum resolution
I am having a development board and it has system clock of 32 bit timer 48Mhz .if i want to find the maximum resolution with pre-scale value how to find it.
This pre-scale has 16 bits and how could i use it to make timer delay of 1 s or more
I know that 1/48Mhz = 0.02083us and 32 bit ==>2^32=4294967279
but how i make use of it
AI: Often in MCU, the peripherals, like timers, are not the Oscillator input.
You have PLLs that actually increases the frequency, and then divisor that reduces the frequency clock for some peripherals.
It means, Timer1 might have a different clock speed than Timer 2 for example. This is very dependent on the chip and the datasheet needs to be checked.
This is not to be confused with the prescaler, which is another addition to further reduce the clock speed on your timer.
If your timer really has a clock speed of 48Mhz, then it's quite simple, minimum resolution, 1 tick is 1/48Mhz, maximum is 1/48Mhz * 2^32 = 89 seconds.
If you use prescaler, then just multiply by the prescaler, so prescaler of 2 = 178.9s. |
H: How to tell if pins are I/O from schematic?
I am using the Fusion360 New Electronics Library to reproduce the footprint/schematic of the NHS3152-AZ.
Following along from Tutorial: Creating electronic components with Fusion 360, at min: 8:09 they assign pin configuration values (I/O, I, O) by cross-referencing with the datasheet.
However with the datasheet for NHS3152(pg6) you can see that pins have 2 names, eg: PIO0_9 & MOSI, with 2 different pin configurations: I/O and I.
What should I eneter for the pins? I/O each time?
I have a schematic of a DEMO, which is configured correctly.
From this schematic, can you understand the I/O pin configuration?
AI: This is configured by the software running on the microcontroller. You should make your schematic representative of what the function you will be using will be. In the DEMO schematic, they've listed both as they don't know ahead of time what the user's software is going to do.
Beware that there can be some issues with specifying a pin direction/function this if the pin is configured out of reset as something different and you expect ERC to flag any incompatibility. |
H: Gates output waveform
I want to do the waveform of X output. How can I do this?
I am trying to use Tinkercad. There is an oscilloscope so I can see the palm.
I couldn't get Tinkercad to represent the palm.
It doesn't have to be done using Tinkercad but I thought it would be easier.
AI: Ok, I see three oscilloscopes, but I don't see any function generators.
Here is a simple set-up showing how the function generator is connected to some input pins of the 7408:
Note that the oscilloscope is connected to an output of the 7408 -- in this case pin 9. Ground of the oscilloscope is, of course, connected to the ground of the circuit.
You'll need two function generators -- one for input A and another for input B.
Update: I've discovered that the Tinkercad function generators are rather limited, so I'm adding this Falstad simulation to this answer.
Falstad simulation
The real tricky part is setting up the wave forms for the two inputs. Here are a couple of tips to generate clock signals and setting up the scopes in Falstad:
For a 5V clock signal set the max. voltage to 2.5V and the DC offset to 2.5V
set the frequency to around 100 Hz
to facilitate monitoring digital inputs and outputs, use a "Voltmeter/Scope Probe" found in the "Outputs and Labels" menu
in the scope settings set the horizontal scale to 2 ms/div
also for scopes in the "Plots" settings only show voltage |
H: 12V with 3.7V backup battery. Which topology is better for battery life?
I have an STM32 based vehicle tracking circuit with an SIM808. I want to use it in vehicle with an LM2596 regulator and a 3.7V li-ion backup battery.
I searched and found out that there are two topologies as attached picture. I need to know which topology is better according to li-ion li-polymer cell internals and increase its lifetime.
Question 2: What is the recommended way to implement that topology?
Our load must continue its working during power switch without interruption.
AI: In brief, first topology is simpler but not recommended because the Li-Pol charger will never know when charging is ever terminated since there is a continual current drain (Isys) and Li-Pol chargers usually detect charge termination by the drawn current level of the charging battery (although if the normal current drain of the end equipment is very small then this may be ok in some applications). Second topology is preferred since it "multiplexes" and essentially separates the charging side, from the power supplying side, assuming the +12V is continuously available. If it is not, then the 3.7V battery would take over supplying the end-equipment... (I assume this is you requirement overall ?!) |
H: Why is the op-amp not able to amplify this voltage? It's a straight-forward non-inverting configuration with ideal op-amps(LTSpice simulations)
So I have the following configuration (pretty straight forward right?)
But following are the waveforms of V_induced(the voltage to be amplified) and V_induced_amplified. As you can see, the voltage is attenuated instead of amplified by 100 as is expected. There is also some unwanted offset. I can't for the life of me imagine why, since I am using ideal-opamps. Any suggestions are greatly appreciated.
AI: The "ideal" opamp is built only with a VCCS and an R||C on the output, but that doesn't mean it has unlimited bandwidth. If you R-Click on the symbol you'll see that there are two parameters to set: Aol -- the open loop gain, and GBW -- the gain-bandwidth product. By default, GBW = 10 MHz, so you can guess that the gain is subtantially reduced at your working frequency.
But if all you need is just an amplification factor, you'd be better off using a VCVS source (F2 -> e), or a VCCS + R (g), where R can be 1 Ω. |
H: Communication between PIC18F26K80 and DAC7612
I bought the DAC7612 and would like to make it communicate with a PIC18F26K80 microcontroller. It is specified on the Farnell website that you can use SPI communication, but there is nothing about SPI in the DAC7612 datasheet.
Indeed, the microcontroller must send 14 bits to the DAC (2 to choose the output of the DAC and 12 data bits). The SPI communication allows to send 8 bits at a time. It is therefore not possible to use it I guess.
So I decided to use bit banging but I don't get any voltage at the output of the DAC7612. However, I can observe with the oscilloscope the signals sent by the microcontroller (CLK, SDI, CS, LOADDACs). Here is the code:
void loadDAC(uint16_t d)
{
uint16_t dac;
uint8_t i;
dac = d | 0x2000; // DAC Port A
LOADDACS_SetHigh();
CS_DAC_SetLow(); // CS_DAC low level
__delay_us(0.03);
for(i = 0; i < 14u; i++)
{
if(dac & 0x2000)
SDO_DAC_SetHigh(); // SDO high level
else
SDO_DAC_SetLow(); // SDO low level
CLK_DAC_SetHigh(); // SCK high level
__delay_us(0.1);
CLK_DAC_SetLow(); // SCK low level
dac <<= 1;
}
__delay_us(0.03);
CS_DAC_SetHigh(); // CS_DAC high level
LOADDACS_SetLow();
__delay_us(0.03);
LOADDACS_SetHigh();
}
Thank you for reading.
Code for SPI Communication but still nothing:
dac_value =0xFFF; // 12 bits resolution
LOADDACS_SetHigh();
SPI_Open(SPI_DEFAULT);
CS_DAC_SetLow();
SSPBUF = (uint8_t)(dac_value >> 6)| 0x80; // 0x80 : select DAC Port A and send 4 MSB
while(!SSPSTATbits.BF);
SSPBUF = (uint8_t)(dac_value << 2 & 0x00FF); // Send 8 LSB
while(!SSPSTATbits.BF);
CS_DAC_SetHigh();
SPI_Close();
LOADDACS_SetLow();
__delay_us(0.03);
LOADDACS_SetHigh();
AI: In the bit-banged code you seem to be missing a delay between setting the output and setting the clock high (\$t_{DS}\$ in the datasheet and also \$t_{CL}\$). Not sure if this is significant though.
Your 0.03 us delay (but how accurate is that delay function and does it actually take a float argument?) is also exactly the minimum value and should be increased a bit. Maybe start with 1 us delays everywhere -- or even 10 us, then fine-tune.
You may also be missing a first high-to-low clock transition before the first iteration of the loop (clock should idle high), which would offset everything by one bit.
In your SPI code, you've left-aligned the 14 bits instead of right-aligning them, so everything is off by two bits and the device would use the 2 MSB of the value for output selection instead of A1 and A0 (which get shifted out). The first word for output A should be (dac >> 8) | 0x20 and the second word dac & 0xFF.
But, your SPI clock phase and polarity settings also look wrong -- I think it should be SPI_CPHA1 | SPI_CPOL1 instead of SPI_DEFAULT. As you've set it, the DAC will be off by one bit in the other direction.
So the net effect of the two mistakes is that everthing is shifted by one bit, just like for the bit-banged code! It will read A0 for A1 and the MSB of the value for A0. This produces the behaviour you describe: your A1 input doesn't matter, A0 = 1 (P odd) combines with the MSB of 0xFFF to give you register B (H-H in the truth table), and A0 = 0 (P even) combines with the MSB of 0xFFF to give you register A and B (L-X in the truth table). |
H: P-Channel MOSFET Reverse Polarity Protection
why is it always that a P-Channel MOSFET is used with reverse polarity protection?
Can we just use an N-Channel MOSFET?
AI: You can use an N-channel MOSFET for reverse polarity protection, as attested to by these SE questions:
NMOS FET selection for reverse polarity protection
How can I add N channel MOSFET for reverse polarity protection?
A lot of designers like to keep the grounds of their power supply and application circuit at the same potential and using an N-channel MOSFET means you introduce an element between them. Any return ground return current will increase the separation between these two potentials.
For a battery operated device this shouldn't be an issue, but perhaps the habit remains. After all, a diode for reverse polarity protection may also be used on the high side or low side, but in designs you always see it on the high side. |
H: Isolating the solenoid and driving relay power supply
I am using a relay module to drive a solenoid based on the output from my micro-controller which provides 5v signal. Following is what the circuit looks like:
My objective is to hook up both relay module and solenoid to separate power supply so that they do not create noise in my micro-controller circuit.
However, since relay module requires micro-controller output, Can I say that it has to share the same ground (i.e same power source as the micro-controller)? Meaning I can only provide separate power supply for blue color part and yellow color has to source the same power supply as micro-controller?
What is the common approach to isolate power for solenoid and relays?
AI: However, since relay module requires micro-controller output, Can I
say that it has to share the same ground (i.e same power source as the
micro-controller)? Meaning I can only provide separate power supply
for blue color part and yellow color has to source the same power
supply as micro-controller?
Yes, the 'output' from the relay to the microcontroller needs to be referenced to the same ground as the microcontroller. Otherwise when the microcontroller brings the port connected to the relay to a low or high voltage no current will flow.
However, the +5V on the switch side of the relay (or blue terminal block) can be connected to anything you want and functions as a switch.
What is the common approach to isolate power for solenoid and relays?
You can use different supplies, or you can use an isolated dc dc converter.
It may not be necessary to isolate the solenoid at all, isolating is typically used to separate power systems if the loads (especially switching loads) create noise for other loads or if there are problems with EMI (electromagnetic interference).
Isolation can come at cost (isolated supplies can be more costly than regular DC DC converters), you could probably just use two separate supplies and not keep them isolated. Make sure you have a good ground (if running wires make sure that they are low enough resistance to prevent common mode voltage (voltages are generated when running large current through resistance/wires). |
H: What are the corrections need to be done to the below statements in order to make them work properly in Verilog?
int t=-1'd1; //trying to assign -1 to t;
bit vb[7:0]; // simple declaration
bit matrix[0:1][0:7]='{'{0,1,0,0,0,0,0,0},'{0,0,1,0,0,0,0,0},'{1,0,0,1,0,0,0,0},'{0,0,0,0,1,0,0,0},'{0,0,0,0,0,1,0,1},'{0,0,0,0,0,0,1,0},'{0,0,0,0,1,0,0,1},'{0,0,0,0,0,0,0,0}};// initialising multi-dimensional array.
I am using QuestaSim to compile and simulate.
this is the report:
# -- Compiling module test
# ** Error: (vlog-13032) test.v(8): near "=": Syntax error.
# ** Error: (vlog-13032) test.v(9): near ";": Syntax error.
I am somewhat New to the Verilog. Please help me in fixing these errors.
AI: Your problem is you are writing SystemVerilog code in a file with *.v file extension. bit and int are SystemVerilog types that do not exist in Verilog.
Change your file extension to *.sv or use reg and integer types instead. |
H: Connect outer the Gates (AND ,OR)
I have the equation L=ABD+(A+B)(D+C).
I have this
I must connect those based on the equation.
What I did was to take the equation
L=ABD+(A+B)(D+C)
and make it simplier
so I have L=ABD+AD+AC+BD+BC
At my view I can't simplifie it more.
I must connect outter those Gates AND,OR based on my equation.
In the picture,on the left side I have the gate AND ,on the right of the picture I have the gate OR.
Now, about gate AND: I know I have input 1 and 2, the 3 is output. Also,4,5 are also inputs and 6 is output. 7 is the ground. 14 is output for Vcc.13,12 are used as inputs and 11 as output.
10 and 9 inputs and 8 output.
Similar we have and the OR gate.
I think that I can connect the Gate AND with OR by the outputs. I mean the gate AND output 3 can be connected with the inputs of gate OR.
From the equation, how can I do that based on the equation? because I can't understand.
AI: Here is a simple example. Suppose you want to compute ABD+AD. Follow these steps:
Using one AND gate, compute A AND B.
Using another AND gate compute A AND D.
Using another AND gate compute D and the result of step 1.
Using an OR gate compute the OR of the results of steps 2 and 3.
The desired output will be the output of the OR gate. |
H: Voltage/Current phase shift caused by capacitor/inductor
Im trying to understand exactly how a capacitor and inductor affect the RC and RL circuits and am not sure exactly what is correct. When I look online for phase shifts for these components it mostly talks about Current Leads Voltage by 90 degrees in a capacitor and Current Lags Voltage by 90 degrees in an inductor, which I understand. Where I'm not sure is how do we analyze the voltage phase shift when we add a capacitor, and the current phase shift when we add an inductor.
I have a an RC circuit setup and have notice that the original (pink) voltage is leading the RC (yellow) voltage, which makes sense as a capacitor resists change in voltage. I am having difficulty finding the mathematics to calculate this phase shift, which I find is different when I used different frequencies. Also, what is happening to the current (I don't have a shunt resistor yet to show a current waveform on my scope)? If the current leads the voltage by 90 degrees, it would lead me to believe that the original and RC current would have the same phase shift from each other.
Then with an inductor things would just be the opposite, the original voltage will lag the RL voltage by some phase (again couldn't find the math for this), and same with the original vs RL current by that same phase.
To sum it up:
What is the mathematics on calculating the phase shift of voltage for a capacitor/ current on an inductor?
Is my thoughts on what is happening to the voltage and current for each component correct?
AI: Vout = (Vs * Xc)/(R + Xc) where the angle of Vs is 0 degrees (the reference), the angle of Xc is -90 degrees and the angle of the resistance is 0 degrees.
The angles of the impedances represent the phase of the voltage with respect to the current.
You'll need to convert the denominator to rectangular form to do the addition and then convert back to polar form to do the division, or you could start with the denominator in rectangular form as R - jXc before converting it to polar form ready for the division.
If you make Vs = R = Xc = 1 then Vout will equal 0.707 at an angle of -45 degrees that is to say the output is lagging the input by 45 degrees at the cut-off (-3dB) frequency.
Now do the same for (Vs * R)/(R + Xc) to find the phase and voltage across the resistor with respect to the source voltage and you will get 0.707 at an angle of +45 degrees.
Once you have mastered those calculations you can vary the frequency to adjust the value of Xc and see how it adjusts the voltages across the components and the phases relative to Vs. Note though that there will always be 90 degrees between the voltage across the resistor and the voltage across the capacitor and the current will always be in phase with the voltage across the resistor.
You will find that as frequency varies, one component's phasor will move closer to the input voltage's phasor as the other component's phasor moves further from it thereby maintaining the 90 degrees angle between the resistance phasor and the capacitive reactance phasor. |
H: What is the "dangling transistor" in this operational amplifier equivalent schematic?
I was comparing the datasheets for the three related CMOS Op Amps from TI: TLC2252, TLC2262, and TLC2272. TLC2252 is the micropower version; TLC2272 is the high-performance version; TLC2262 is offered as a compromise between them.
The equivalent schematics only seem to differ in the area around Q9. In TLC2272, Q9 is part of a current mirror. In TLC2252, it is diode-connected. In TLC2262 just hanging there as a "one-terminal device" (unless the substrate connection is significant.)
Does Q9 have a function in TLC2262, or is this just an artifact of the manufacturing process? (I.e. are they all made from the same die and trimmed to make the three different versions?)
AI: It is intended to show how the 2262 is a compromise between the higher current & performance of the 2272 and ultra low current of the 2252. This is accommodated by the simple changes in the current mirrors from the same design, where the 2262 does not need Q9 to achieve this.
The 2252 reduces the bias current with the added R to lower the mirrored output, which also lowers the bandwidth and raises the impedance with only 50uA per channel. |
H: What does this schematic symbol looking like a capacitor with one side slightly folded over the other represent?
I'm not sure what this symbol represents:
It comes from figure 5-2 on page 19 of the data sheet for the ATSAM3U2CA-AU
Heres a picture of that page:
AI: This is one of the ways of representing a capacitor:
The extra line below is the ground connection.
The image is taken from the link below:
https://iastate.pressbooks.pub/electriccircuits/back-matter/appendix-c/ |
H: 4051 MUX as 8-Pole Switch
I am a beginner in electronics so please bear with me if this question seems stupid for you.
I have a circuit that I want to modify at certain points. All in all there are 8 modify points in the circuit and 8 modifications that short these points or place a capacitor in between them.
To put it in a nutshell I need to toggle 8 data lines.
I thought there were 8-pole 2-throw switches. Unfortunately I could find such switches. I read that a multiplexer would be a good idea.
However I never worked with them. I wondered if this is the right way:
Again sorry if this sketch seems hideous to you.
As you can see every 4051 MUX has a modified circuit as an output.
So I need eight multiplexers for every modification point.
Every multiplexer is controlled by a microcontroller like an arduino.
The microcontroller establishes the control sequence based on the output of a 74HC165 shift register. This shift register generates its output by checking which switch is closed.
I couldn't verify this schematic because I don't have the multiplexers yet. Could this work?
AI: Here's what the various analog switches in the CD405x family are like:
Source: https://www.ti.com/lit/ds/symlink/cd4051b.pdf
The CD4051 is a single pole, 8-throw switch. It requires 3 digital inputs to select the position of the switch.
The CD4053 is a 3-pole, 2-throw switch. It uses one digital input per channel to control the positions of the three switches.
By connecting the channel selector inputs together you could use 3 CD4053's to implement an 8-pole, 2-throw switch.
there are 8 modify points in the circuit and 8 modifications that short these points or place a capacitor in between them.
It seems that you could use a SPST switch like this:
If the switch is closed there is a short between A and B. Otherwise there is a cap between them.
The CD4066 contains four SPST analog switches, so you would only need two of them for an 8-pole switch.
Every multiplexer is controlled by a microcontroller like an arduino.
The way you are connecting the control signals from the Arduino to the multiplexers is fine. |
H: How to find the minimum and maximum voltage of this buck converter
I am using buck converter. 3.3V output & 2.5A part with 2.1MHz switching frequency.
I am powering my microcontroller with this 3.3V output. So, I'd like to find the output voltage tolerance of the buck converter.
Usually, to find the min and max output voltage of the converter, there would be some output voltage formula which would involve some resistors. So, I would take these resistor tolerances that would help me find the minimum and maximum output voltage.
Since, there are no feedback resistors in the the 3.3V output configuration, or any other formula, can someone tell me how to find the minimum and maximum output voltage for this part?
I am also using a 10uH part as inductor with 2x 10uF capacitor. Can someone also help me on how to calculate the output voltage and output ripple current? There are no calculated examples or formulas provided in the datasheet. Please help with the above.
AI: The datasheet lists 3.3V output min and max values on page 8, that's the FB voltage for your 3.3V regulator.
The output ripple will be dependent on if the load is light or heavy, as the chip can alter between PFM and PWM modes of operation. During light load in PFM mode, the ripple is usually higher than in PWM mode.
Formulas to calculate ripple due to output capacitance is on page 27.
Basically, the ripple depends on capacitor ESR, capacitor capacitance, and the current used to charge and discharge the capacitor.
But like the datasheet mentions, usually the capacitor capacitance and ESR are more defined by load transient requirements, so the effect of ripple much less. |
H: Buffer before invert before buffer
A friend asked me a question (we are both quite new to electronic circuitry and logic, though varying degrees of tinkering and comp. sci. education).
The question is, why would a buffer have an inverter on both ends of the I/O? An example image would be:
Thanks! This is interesting.
AI: A non-inverting buffer cannot be done directly, as the smallest building block you can make is an inverter, and two inverters make a buffer.
Two inverters in a row means it adds more delay, but it also has a higher output drive capability. Internally, it could have any even amount of inverters connected together to make a buffer with required drive ability, as each stage can roughly amplify the drive ability by about 4x.
Sometimes you see the inverting notation on logic gate inputs and outputs, it might simply mean that this is a buffer for an active-low signal, and both the input and output inverting notation is there to emphasize that. |
H: Is a sine wave (or any signal) that has no zero crossing still considered AC?
This question will most likely come down to semantics. A friend and I were discussing a point that his EE instructor made, that if you consider the output from a solar panel over more than a few days, it effectively is a cyclic wave, and thus is AC at that time scale. I disagreed with that point and said that it is still DC, albeit with variable output.
Now, while I agree that it's useful to consider the longer measurement period and explain to students how one might conclude it is an 11.6 µHz signal with a DC offset or something, I feel it is misleading to label it AC.
The output voltage is always positive or zero -- unless you measure that signal with reference to some arbitrary point other than one of the panel's terminals. In order to get a negative voltage one would have to measure with reference to a midpoint (e.g. between two serially-connected panels).
I liken the sub-1-Hz "signal" example to an analogy, and maintain that it is somewhat useful, but only as much as, say, water analogies are to explaining electrical phenomenon.
In any case, if I measure a signal where no polarity reversal occurs (at any time scale), should it be considered AC? If so, is "alternating" merely describing the change in amplitude/voltage? Again, if so, does that make current reversal due to polarity reversal a non-requirement to be considered AC?
(A related question asks if a square wave still considered DC. Perhaps a short version of my question is: "Is a square or sine wave with no zero crossing still considered AC?")
AI: This has been discussed (argued) several times on this site and the result is always both yes and no. My own take is:
If the polarity never actually reverses then it's not AC.
At the same time we can represent it as AC with a large DC offset.
Alternately we can represent it as DC with an AC ripple waveform superimposed.
I wouldn't bother getting into an argument about it - commenters please note. Take whichever view best suits the analysis you are doing or that seems most intuitive for a particular situation. |
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