repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
matthiasgoergens/zkvm | 2,175 | riscv-testdata/testdata/rv64ui/slti.S | # See LICENSE for license details.
#*****************************************************************************
# slti.S
#-----------------------------------------------------------------------------
#
# Test slti instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 );
TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 );
TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 );
TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 );
TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 );
TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 );
TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 );
TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff );
TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 );
TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff );
TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff );
TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 );
TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff );
TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 );
TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 );
TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,282 | riscv-testdata/testdata/rv64ui/lb.S | # See LICENSE for license details.
#*****************************************************************************
# lb.S
#-----------------------------------------------------------------------------
#
# Test lb instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat );
TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat );
TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat );
TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat );
# Test with negative offset
TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 );
TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 );
TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 );
TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0xffffffffffffffff, \
la x1, tdat; \
addi x1, x1, -32; \
lb x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x0000000000000000, \
la x1, tdat; \
addi x1, x1, -6; \
lb x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lb x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lb x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xff
tdat2: .byte 0x00
tdat3: .byte 0xf0
tdat4: .byte 0x0f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,861 | riscv-testdata/testdata/rv64ui/xori.S | # See LICENSE for license details.
#*****************************************************************************
# xori.S
#-----------------------------------------------------------------------------
#
# Test xori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f );
TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f );
TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,013 | riscv-testdata/testdata/rv64ui/bne.S | # See LICENSE for license details.
#*****************************************************************************
# bne.S
#-----------------------------------------------------------------------------
#
# Test bne instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bne, 0, 1 );
TEST_BR2_OP_TAKEN( 3, bne, 1, 0 );
TEST_BR2_OP_TAKEN( 4, bne, -1, 1 );
TEST_BR2_OP_TAKEN( 5, bne, 1, -1 );
TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 );
TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 );
TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
bne x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,633 | riscv-testdata/testdata/rv64ui/and.S | # See LICENSE for license details.
#*****************************************************************************
# and.S
#-----------------------------------------------------------------------------
#
# Test and instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, and, 0 );
TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,145 | riscv-testdata/testdata/rv64ui/add.S | # See LICENSE for license details.
#*****************************************************************************
# add.S
#-----------------------------------------------------------------------------
#
# Test add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
TEST_RR_ZEROSRC1( 35, add, 15, 15 );
TEST_RR_ZEROSRC2( 36, add, 32, 32 );
TEST_RR_ZEROSRC12( 37, add, 0 );
TEST_RR_ZERODEST( 38, add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,748 | riscv-testdata/testdata/rv64ui/sltu.S | # See LICENSE for license details.
#*****************************************************************************
# sltu.S
#-----------------------------------------------------------------------------
#
# Test sltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 );
TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 );
TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 );
TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 );
TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff );
TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff );
TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff );
TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 );
TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 );
TEST_RR_ZEROSRC1( 35, sltu, 1, -1 );
TEST_RR_ZEROSRC2( 36, sltu, 0, -1 );
TEST_RR_ZEROSRC12( 37, sltu, 0 );
TEST_RR_ZERODEST( 38, sltu, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,176 | riscv-testdata/testdata/rv64ui/srli.S | # See LICENSE for license details.
#*****************************************************************************
# srli.S
#-----------------------------------------------------------------------------
#
# Test srli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
#define TEST_SRLI(n, v, a) \
TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
TEST_SRLI( 2, 0xffffffff80000000, 0 );
TEST_SRLI( 3, 0xffffffff80000000, 1 );
TEST_SRLI( 4, 0xffffffff80000000, 7 );
TEST_SRLI( 5, 0xffffffff80000000, 14 );
TEST_SRLI( 6, 0xffffffff80000001, 31 );
TEST_SRLI( 7, 0xffffffffffffffff, 0 );
TEST_SRLI( 8, 0xffffffffffffffff, 1 );
TEST_SRLI( 9, 0xffffffffffffffff, 7 );
TEST_SRLI( 10, 0xffffffffffffffff, 14 );
TEST_SRLI( 11, 0xffffffffffffffff, 31 );
TEST_SRLI( 12, 0x0000000021212121, 0 );
TEST_SRLI( 13, 0x0000000021212121, 1 );
TEST_SRLI( 14, 0x0000000021212121, 7 );
TEST_SRLI( 15, 0x0000000021212121, 14 );
TEST_SRLI( 16, 0x0000000021212121, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 );
TEST_IMM_ZEROSRC1( 24, srli, 0, 4 );
TEST_IMM_ZERODEST( 25, srli, 33, 10 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,345 | riscv-testdata/testdata/rv64ui/addi.S | # See LICENSE for license details.
#*****************************************************************************
# addi.S
#-----------------------------------------------------------------------------
#
# Test addi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 );
TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 );
TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 );
TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 );
TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff );
TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 );
TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff );
TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 );
TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
TEST_IMM_ZERODEST( 25, addi, 33, 50 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,229 | riscv-testdata/testdata/rv64ui/sll.S | # See LICENSE for license details.
#*****************************************************************************
# sll.S
#-----------------------------------------------------------------------------
#
# Test sll instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 );
TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 );
TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff );
TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 );
TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
TEST_RR_ZEROSRC12( 42, sll, 0 );
TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,201 | riscv-testdata/testdata/rv64ui/sltiu.S | # See LICENSE for license details.
#*****************************************************************************
# sltiu.S
#-----------------------------------------------------------------------------
#
# Test sltiu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 );
TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 );
TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 );
TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 );
TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 );
TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 );
TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 );
TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff );
TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 );
TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff );
TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff );
TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 );
TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff );
TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 );
TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 );
TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 );
TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 );
TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 );
TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 );
TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff );
TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,389 | riscv-testdata/testdata/rv64ui/srlw.S | # See LICENSE for license details.
#*****************************************************************************
# srlw.S
#-----------------------------------------------------------------------------
#
# Test srlw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, srlw, 0xffffffff80000000, 0xffffffff80000000, 0 );
TEST_RR_OP( 3, srlw, 0x0000000040000000, 0xffffffff80000000, 1 );
TEST_RR_OP( 4, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_OP( 5, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_OP( 6, srlw, 0x0000000000000001, 0xffffffff80000001, 31 );
TEST_RR_OP( 7, srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, srlw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1 );
TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7 );
TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 );
TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 );
# Verify that shifts only use bottom five bits
TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 );
TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 );
TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
# Verify that shifts ignore top 32 (using true 64-bit values)
TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 );
TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
TEST_RR_ZEROSRC1( 40, srlw, 0, 15 );
TEST_RR_ZEROSRC2( 41, srlw, 32, 32 );
TEST_RR_ZEROSRC12( 42, srlw, 0 );
TEST_RR_ZERODEST( 43, srlw, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,290 | riscv-testdata/testdata/rv64ui/lh.S | # See LICENSE for license details.
#*****************************************************************************
# lh.S
#-----------------------------------------------------------------------------
#
# Test lh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat );
TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat );
TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat );
TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat );
# Test with negative offset
TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 );
TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 );
TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 );
TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lh x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0xffffffffffffff00, \
la x1, tdat; \
addi x1, x1, -5; \
lh x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lh x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lh x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0x00ff
tdat2: .half 0xff00
tdat3: .half 0x0ff0
tdat4: .half 0xf00f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,651 | riscv-testdata/testdata/rv64ui/xor.S | # See LICENSE for license details.
#*****************************************************************************
# xor.S
#-----------------------------------------------------------------------------
#
# Test xor instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, xor, 0 );
TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,452 | riscv-testdata/testdata/rv64ui/srl.S | # See LICENSE for license details.
#*****************************************************************************
# srl.S
#-----------------------------------------------------------------------------
#
# Test srl instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
#define TEST_SRL(n, v, a) \
TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
TEST_SRL( 2, 0xffffffff80000000, 0 );
TEST_SRL( 3, 0xffffffff80000000, 1 );
TEST_SRL( 4, 0xffffffff80000000, 7 );
TEST_SRL( 5, 0xffffffff80000000, 14 );
TEST_SRL( 6, 0xffffffff80000001, 31 );
TEST_SRL( 7, 0xffffffffffffffff, 0 );
TEST_SRL( 8, 0xffffffffffffffff, 1 );
TEST_SRL( 9, 0xffffffffffffffff, 7 );
TEST_SRL( 10, 0xffffffffffffffff, 14 );
TEST_SRL( 11, 0xffffffffffffffff, 31 );
TEST_SRL( 12, 0x0000000021212121, 0 );
TEST_SRL( 13, 0x0000000021212121, 1 );
TEST_SRL( 14, 0x0000000021212121, 7 );
TEST_SRL( 15, 0x0000000021212121, 14 );
TEST_SRL( 16, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
TEST_RR_ZEROSRC12( 42, srl, 0 );
TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,829 | riscv-testdata/testdata/rv64ui/ori.S | # See LICENSE for license details.
#*****************************************************************************
# ori.S
#-----------------------------------------------------------------------------
#
# Test ori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f );
TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f );
TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,597 | riscv-testdata/testdata/rv64ui/srai.S | # See LICENSE for license details.
#*****************************************************************************
# srai.S
#-----------------------------------------------------------------------------
#
# Test srai instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 );
TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 );
TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 );
TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 );
TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 );
TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 );
TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 );
TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 );
TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 );
TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_ZEROSRC1( 24, srai, 0, 4 );
TEST_IMM_ZERODEST( 25, srai, 33, 10 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,143 | riscv-testdata/testdata/rv32ud/ldst.S | # See LICENSE for license details.
#*****************************************************************************
# ldst.S
#-----------------------------------------------------------------------------
#
# This test verifies that flw, fld, fsw, and fsd work properly.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32UF
RVTEST_CODE_BEGIN
la s0, tdat
TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
.word 0xbf800000
.word 0x40000000
.word 0x40400000
.word 0xc0800000
.word 0xdeadbeef
.word 0xcafebabe
.word 0xabad1dea
.word 0x1337d00d
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,818 | riscv-testdata/testdata/rv32um/mul.S | # See LICENSE for license details.
#*****************************************************************************
# mul.S
#-----------------------------------------------------------------------------
#
# Test mul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
TEST_RR_ZEROSRC12( 28, mul, 0 );
TEST_RR_ZERODEST( 29, mul, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,960 | riscv-testdata/testdata/rv32um/mulhu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhu.S
#-----------------------------------------------------------------------------
#
# Test mulhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulhu, 0 );
TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,923 | riscv-testdata/testdata/rv32um/mulh.S | # See LICENSE for license details.
#*****************************************************************************
# mulh.S
#-----------------------------------------------------------------------------
#
# Test mulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulh, 0 );
TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,997 | riscv-testdata/testdata/rv32um/mulhsu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhsu.S
#-----------------------------------------------------------------------------
#
# Test mulhsu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,055 | riscv-testdata/testdata/rv64uzfh/fdiv.S | # See LICENSE for license details.
#*****************************************************************************
# fdiv.S
#-----------------------------------------------------------------------------
#
# Test f{div|sqrt}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_H(2, fdiv.h, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
TEST_FP_OP2_H(3, fdiv.h, 1,-0.9991093838555584, -1234, 1235.1 );
TEST_FP_OP2_H(4, fdiv.h, 0, 3.14159265, 3.14159265, 1.0 );
TEST_FP_OP1_H(5, fsqrt.h, 1, 1.7724538498928541, 3.14159265 );
TEST_FP_OP1_H(6, fsqrt.h, 0, 100, 10000 );
TEST_FP_OP1_H_DWORD_RESULT(7, fsqrt.h, 0x10, 0x00007e00, -1.0 );
TEST_FP_OP1_H(8, fsqrt.h, 1, 13.076696, 171.0);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,229 | riscv-testdata/testdata/rv64uzfh/fcvt.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt.S
#-----------------------------------------------------------------------------
#
# Test fcvt.h.{wu|w|lu|l}, fcvt.h.d, and fcvt.d.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_INT_FP_OP_H( 2, fcvt.h.w, 2.0, 2);
TEST_INT_FP_OP_H( 3, fcvt.h.w, -2.0, -2);
TEST_INT_FP_OP_H( 4, fcvt.h.wu, 2.0, 2);
TEST_INT_FP_OP_H( 5, fcvt.h.wu, 0h:7c00, -2);
#if __riscv_xlen >= 64
TEST_INT_FP_OP_H( 6, fcvt.h.l, 2.0, 2);
TEST_INT_FP_OP_H( 7, fcvt.h.l, -2.0, -2);
TEST_INT_FP_OP_H( 8, fcvt.h.lu, 2.0, 2);
TEST_INT_FP_OP_H( 9, fcvt.h.lu, 0h:7c00, -2);
#endif
TEST_FCVT_H_S( 10, -1.5, -1.5)
#if __riscv_xlen >= 64
TEST_FCVT_H_D( 11, -1.5, -1.5)
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,380 | riscv-testdata/testdata/rv64uzfh/fadd.S | # See LICENSE for license details.
#*****************************************************************************
# fadd.S
#-----------------------------------------------------------------------------
#
# Test f{add|sub|mul}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_H( 2, fadd.h, 0, 3.5, 2.5, 1.0 );
TEST_FP_OP2_H( 3, fadd.h, 1, -1234, -1235.1, 1.1 );
TEST_FP_OP2_H( 4, fadd.h, 1, 3.14, 3.13, 0.01 );
TEST_FP_OP2_H( 5, fsub.h, 0, 1.5, 2.5, 1.0 );
TEST_FP_OP2_H( 6, fsub.h, 1, -1234, -1235.1, -1.1 );
TEST_FP_OP2_H( 7, fsub.h, 1, 3.14, 3.15, 0.01 );
TEST_FP_OP2_H( 8, fmul.h, 0, 2.5, 2.5, 1.0 );
TEST_FP_OP2_H( 9, fmul.h, 0, 1235.1, -1235.1, -1.0 );
TEST_FP_OP2_H(10, fmul.h, 1, 1.1, 11.0, 0.1 );
# Is the canonical NaN generated for Inf - Inf?
TEST_FP_OP2_H(11, fsub.h, 0x10, qNaNh, Inf, Inf);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,496 | riscv-testdata/testdata/rv64uzfh/move.S | # See LICENSE for license details.
#*****************************************************************************
# move.S
#-----------------------------------------------------------------------------
#
# This test verifies that the fmv.h.x, fmv.x.h, and fsgnj[x|n].d instructions
# and the fcsr work properly.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
TEST_CASE(3, a0, 0x34, frsr a0)
TEST_CASE(4, a0, 0x14, frflags a0)
TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2)
TEST_CASE(6, a0, 0x54, frsr a0)
TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4)
TEST_CASE(8, a0, 0x50, frsr a0)
#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \
TEST_CASE(n, a0, 0x1234 | (-(new_sign) << 15), \
li a1, ((rs1_sign) << 15) | 0x1234; \
li a2, -(rs2_sign); \
fmv.h.x f1, a1; \
fmv.h.x f2, a2; \
insn f0, f1, f2; \
fmv.x.h a0, f0)
TEST_FSGNJS(10, fsgnj.h, 0, 0, 0)
TEST_FSGNJS(11, fsgnj.h, 1, 0, 1)
TEST_FSGNJS(12, fsgnj.h, 0, 1, 0)
TEST_FSGNJS(13, fsgnj.h, 1, 1, 1)
TEST_FSGNJS(20, fsgnjn.h, 1, 0, 0)
TEST_FSGNJS(21, fsgnjn.h, 0, 0, 1)
TEST_FSGNJS(22, fsgnjn.h, 1, 1, 0)
TEST_FSGNJS(23, fsgnjn.h, 0, 1, 1)
TEST_FSGNJS(30, fsgnjx.h, 0, 0, 0)
TEST_FSGNJS(31, fsgnjx.h, 1, 0, 1)
TEST_FSGNJS(32, fsgnjx.h, 1, 1, 0)
TEST_FSGNJS(33, fsgnjx.h, 0, 1, 1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,416 | riscv-testdata/testdata/rv64uzfh/fcvt_w.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt_w.S
#-----------------------------------------------------------------------------
#
# Test fcvt{wu|w|lu|l}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_INT_OP_H( 2, fcvt.w.h, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_H( 3, fcvt.w.h, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_H( 4, fcvt.w.h, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_H( 5, fcvt.w.h, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_H( 6, fcvt.w.h, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_H( 7, fcvt.w.h, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_H( 8, fcvt.w.h, 0x00, -2054, 0h:e803, rtz);
TEST_FP_INT_OP_H( 9, fcvt.w.h, 0x00, 2054, 0h:6803, rtz);
TEST_FP_INT_OP_H(12, fcvt.wu.h, 0x10, 0, -3.0, rtz);
TEST_FP_INT_OP_H(13, fcvt.wu.h, 0x10, 0, -1.0, rtz);
TEST_FP_INT_OP_H(14, fcvt.wu.h, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_H(15, fcvt.wu.h, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_H(16, fcvt.wu.h, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_H(17, fcvt.wu.h, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_H(18, fcvt.wu.h, 0x10, 0, 0h:e803, rtz);
TEST_FP_INT_OP_H(19, fcvt.wu.h, 0x00, 2054, 0h:6803, rtz);
#if __riscv_xlen >= 64
TEST_FP_INT_OP_H(22, fcvt.l.h, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_H(23, fcvt.l.h, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_H(24, fcvt.l.h, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_H(25, fcvt.l.h, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_H(26, fcvt.l.h, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_H(27, fcvt.l.h, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_H(32, fcvt.lu.h, 0x10, 0, -3.0, rtz);
TEST_FP_INT_OP_H(33, fcvt.lu.h, 0x10, 0, -1.0, rtz);
TEST_FP_INT_OP_H(34, fcvt.lu.h, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_H(35, fcvt.lu.h, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_H(36, fcvt.lu.h, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_H(37, fcvt.lu.h, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_H(38, fcvt.lu.h, 0x10, 0, 0h:e483, rtz);
#endif
# test negative NaN, negative infinity conversion
TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.h x1, f1)
TEST_CASE( 43, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.h x1, f1)
#if __riscv_xlen >= 64
TEST_CASE( 44, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.h x1, f1)
TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.h x1, f1)
#endif
# test positive NaN, positive infinity conversion
TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.h x1, f1)
TEST_CASE( 53, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.h x1, f1)
#if __riscv_xlen >= 64
TEST_CASE( 54, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.h x1, f1)
TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.h x1, f1)
#endif
# test NaN, infinity conversions to unsigned integer
TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.h x1, f1)
TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.h x1, f1)
TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.h x1, f1)
TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.h x1, f1)
#if __riscv_xlen >= 64
TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.h x1, f1)
TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.h x1, f1)
TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.h x1, f1)
TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.h x1, f1)
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
# -NaN, NaN, -inf, +inf
#tdat:
#.word 0xffffffff
#.word 0x7fffffff
#.word 0xff800000
#.word 0x7f800000
tdat:
.word 0xffffffff
.word 0xffff7fff
.word 0xfffffc00
.word 0xffff7c00
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,122 | riscv-testdata/testdata/rv64uzfh/recoding.S | # See LICENSE for license details.
#*****************************************************************************
# recoding.S
#-----------------------------------------------------------------------------
#
# Test corner cases of John Hauser's microarchitectural recoding scheme.
# There are twice as many recoded values as IEEE-754 values; some of these
# extras are redundant (e.g. Inf) and others are illegal (subnormals with
# too many bits set).
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
# Make sure infinities with different mantissas compare as equal.
flw f0, minf, a0
flw f1, three, a0
fmul.s f1, f1, f0
TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
# Likewise, but for zeroes.
fcvt.s.w f0, x0
li a0, 1
fcvt.s.w f1, a0
fmul.s f1, f1, f0
TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
minf: .float -Inf
three: .float 3.0
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,629 | riscv-testdata/testdata/rv64uzfh/fmadd.S | # See LICENSE for license details.
#*****************************************************************************
# fmadd.S
#-----------------------------------------------------------------------------
#
# Test f[n]m{add|sub}.h and f[n]m{add|sub}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP3_H( 2, fmadd.h, 0, 3.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_H( 3, fmadd.h, 1, 13.2, -1.0, -12.1, 1.1 );
TEST_FP_OP3_H( 4, fmadd.h, 0, -12.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_H( 5, fnmadd.h, 0, -3.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_H( 6, fnmadd.h, 1, -13.2, -1.0, -12.1, 1.1 );
TEST_FP_OP3_H( 7, fnmadd.h, 0, 12.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_H( 8, fmsub.h, 0, 1.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_H( 9, fmsub.h, 1, 11, -1.0, -12.1, 1.1 );
TEST_FP_OP3_H(10, fmsub.h, 0, -8.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_H(11, fnmsub.h, 0, -1.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_H(12, fnmsub.h, 1, -11, -1.0, -12.1, 1.1 );
TEST_FP_OP3_H(13, fnmsub.h, 0, 8.0, 2.0, -5.0, -2.0 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,111 | riscv-testdata/testdata/rv64uzfh/fclass.S | # See LICENSE for license details.
#*****************************************************************************
# fclass.S
#-----------------------------------------------------------------------------
#
# Test fclass.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
#define TEST_FCLASS_H(testnum, correct, input) \
TEST_CASE(testnum, a0, correct, li a0, input; fmv.h.x fa0, a0; \
fclass.h a0, fa0)
TEST_FCLASS_H( 2, 1 << 0, 0xfc00 )
TEST_FCLASS_H( 3, 1 << 1, 0xbc00 )
TEST_FCLASS_H( 4, 1 << 2, 0x83ff )
TEST_FCLASS_H( 5, 1 << 3, 0x8000 )
TEST_FCLASS_H( 6, 1 << 4, 0x0000 )
TEST_FCLASS_H( 7, 1 << 5, 0x03ff )
TEST_FCLASS_H( 8, 1 << 6, 0x3c00 )
TEST_FCLASS_H( 9, 1 << 7, 0x7c00 )
TEST_FCLASS_H(10, 1 << 8, 0x7c01 )
TEST_FCLASS_H(11, 1 << 9, 0x7e00 )
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,872 | riscv-testdata/testdata/rv64uzfh/fmin.S | # See LICENSE for license details.
#*****************************************************************************
# fmin.S
#-----------------------------------------------------------------------------
#
# Test f{min|max}.h instructinos.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_H( 2, fmin.h, 0, 1.0, 2.5, 1.0 );
TEST_FP_OP2_H( 3, fmin.h, 0, -1235.1, -1235.1, 1.1 );
TEST_FP_OP2_H( 4, fmin.h, 0, -1235.1, 1.1, -1235.1 );
TEST_FP_OP2_H( 5, fmin.h, 0, -1235.1, NaN, -1235.1 );
TEST_FP_OP2_H( 6, fmin.h, 0, 0.00000001, 3.14159265, 0.00000001 );
TEST_FP_OP2_H( 7, fmin.h, 0, -2.0, -1.0, -2.0 );
TEST_FP_OP2_H(12, fmax.h, 0, 2.5, 2.5, 1.0 );
TEST_FP_OP2_H(13, fmax.h, 0, 1.1, -1235.1, 1.1 );
TEST_FP_OP2_H(14, fmax.h, 0, 1.1, 1.1, -1235.1 );
TEST_FP_OP2_H(15, fmax.h, 0, -1235.1, NaN, -1235.1 );
TEST_FP_OP2_H(16, fmax.h, 0, 3.14159265, 3.14159265, 0.00000001 );
TEST_FP_OP2_H(17, fmax.h, 0, -1.0, -1.0, -2.0 );
# FMIN(hNaN, x) = x
TEST_FP_OP2_H(20, fmax.h, 0x10, 1.0, sNaNh, 1.0);
# FMIN(hNaN, hNaN) = canonical NaN
TEST_FP_OP2_H(21, fmax.h, 0x00, qNaNh, NaN, NaN);
# -0.0 < +0.0
TEST_FP_OP2_H(30, fmin.h, 0, -0.0, -0.0, 0.0 );
TEST_FP_OP2_H(31, fmin.h, 0, -0.0, 0.0, -0.0 );
TEST_FP_OP2_H(32, fmax.h, 0, 0.0, -0.0, 0.0 );
TEST_FP_OP2_H(33, fmax.h, 0, 0.0, 0.0, -0.0 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,912 | riscv-testdata/testdata/rv32uzbc/clmul.S | # See LICENSE for license details.
#*****************************************************************************
# clmul.S
#-----------------------------------------------------------------------------
#
# Test clmul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, clmul, 0x00005a00, 0x00007e00, 0xb6db6db7 );
TEST_RR_OP(33, clmul, 0x00005b40, 0x00007fc0, 0xb6db6db7 );
TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, clmul, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, clmul, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, clmul, 0x00000000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, clmul, 0xfffc324f, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, clmul, 0xfffc324f, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(34, clmul, 0x00000000, 0xff000000, 0xff000000 );
TEST_RR_OP(35, clmul, 0x55555555, 0xffffffff, 0xffffffff );
TEST_RR_OP(36, clmul, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(37, clmul, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 );
TEST_RR_ZEROSRC1( 26, clmul, 0, 31 );
TEST_RR_ZEROSRC2( 27, clmul, 0, 32 );
TEST_RR_ZEROSRC12( 28, clmul, 0 );
TEST_RR_ZERODEST( 29, clmul, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,896 | riscv-testdata/testdata/rv32uzbc/clmulh.S | # See LICENSE for license details.
#*****************************************************************************
# clmulh.S
#-----------------------------------------------------------------------------
#
# Test clmulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, clmulh, 0x00003600, 0x00007e00, 0xb6db6db7 );
TEST_RR_OP(33, clmulh, 0x000036c0, 0x00007fc0, 0xb6db6db7 );
TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, clmulh, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, clmulh, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, clmulh, 0x7fffc000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, clmulh, 0x000133cd, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, clmulh, 0x000133cd, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(34, clmulh, 0x55550000, 0xff000000, 0xff000000 );
TEST_RR_OP(35, clmulh, 0x55555555, 0xffffffff, 0xffffffff );
TEST_RR_OP(36, clmulh, 0x00000000, 0xffffffff, 0x00000001 );
TEST_RR_OP(37, clmulh, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 );
TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 );
TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 );
TEST_RR_ZEROSRC12( 28, clmulh, 0 );
TEST_RR_ZERODEST( 29, clmulh, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,896 | riscv-testdata/testdata/rv32uzbc/clmulr.S | # See LICENSE for license details.
#*****************************************************************************
# clmulr.S
#-----------------------------------------------------------------------------
#
# Test clmulr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, clmulr, 0x00006c00, 0x00007e00, 0xb6db6db7 );
TEST_RR_OP(33, clmulr, 0x00006d80, 0x00007fc0, 0xb6db6db7 );
TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, clmulr, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, clmulr, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, clmulr, 0xffff8000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, clmulr, 0x0002679b, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, clmulr, 0x0002679b, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(34, clmulr, 0xaaaa0000, 0xff000000, 0xff000000 );
TEST_RR_OP(35, clmulr, 0xaaaaaaaa, 0xffffffff, 0xffffffff );
TEST_RR_OP(36, clmulr, 0x00000001, 0xffffffff, 0x00000001 );
TEST_RR_OP(37, clmulr, 0x00000001, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 );
TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 );
TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 );
TEST_RR_ZEROSRC12( 28, clmulr, 0 );
TEST_RR_ZERODEST( 29, clmulr, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,981 | riscv-testdata/testdata/rv64uc/rvc.S | # See LICENSE for license details.
#*****************************************************************************
# rvc.S
#-----------------------------------------------------------------------------
#
# Test RVC corner cases.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
.align 2
.option push
.option norvc
#define RVC_TEST_CASE(n, r, v, code...) \
TEST_CASE (n, r, v, .option push; .option rvc; code; .align 2; .option pop)
// Make sure fetching a 4-byte instruction across a page boundary works.
li TESTNUM, 2
li a1, 666
TEST_CASE (2, a1, 667, \
j 1f; \
.align 3; \
data: \
.dword 0xfedcba9876543210; \
.dword 0xfedcba9876543210; \
.align 12; \
.skip 4094; \
1: addi a1, a1, 1)
li sp, 0x1234
RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020)
RVC_TEST_CASE (4, sp, 0x1234 + 496, c.addi16sp sp, 496)
RVC_TEST_CASE (5, sp, 0x1234 + 496 - 512, c.addi16sp sp, -512)
la a1, data
RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1))
#if __riscv_xlen == 64
RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1))
#endif
RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16)
RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16)
#if __riscv_xlen == 64
RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1)
#endif
RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12)
#if __riscv_xlen == 64
RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
#else
RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
#endif
RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10)
RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0)
RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0)
RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0)
RVC_TEST_CASE (18, s1, 4, li s1, 20; li a0, 6; c.and s1, a0)
#if __riscv_xlen == 64
RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0)
RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0)
#endif
RVC_TEST_CASE (21, s0, 0x12340, li s0, 0x1234; c.slli s0, 4)
RVC_TEST_CASE (30, ra, 0, \
li ra, 0; \
c.j 1f; \
c.j 2f; \
1:c.j 1f; \
2:j fail; \
1:)
RVC_TEST_CASE (31, x0, 0, \
li a0, 0; \
c.beqz a0, 1f; \
c.j 2f; \
1:c.j 1f; \
2:j fail; \
1:)
RVC_TEST_CASE (32, x0, 0, \
li a0, 1; \
c.bnez a0, 1f; \
c.j 2f; \
1:c.j 1f; \
2:j fail; \
1:)
RVC_TEST_CASE (33, x0, 0, \
li a0, 1; \
c.beqz a0, 1f; \
c.j 2f; \
1:c.j fail; \
2:)
RVC_TEST_CASE (34, x0, 0, \
li a0, 0; \
c.bnez a0, 1f; \
c.j 2f; \
1:c.j fail; \
2:)
RVC_TEST_CASE (35, ra, 0, \
la t0, 1f; \
li ra, 0; \
c.jr t0; \
c.j 2f; \
1:c.j 1f; \
2:j fail; \
1:)
RVC_TEST_CASE (36, ra, -2, \
la t0, 1f; \
li ra, 0; \
c.jalr t0; \
c.j 2f; \
1:c.j 1f; \
2:j fail; \
1:sub ra, ra, t0)
#if __riscv_xlen == 32
RVC_TEST_CASE (37, ra, -2, \
la t0, 1f; \
li ra, 0; \
c.jal 1f; \
c.j 2f; \
1:c.j 1f; \
2:j fail; \
1:sub ra, ra, t0)
#endif
la sp, data
RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp))
#if __riscv_xlen == 64
RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp))
#endif
RVC_TEST_CASE (42, t0, 0x246, li a0, 0x123; c.mv t0, a0; c.add t0, a0)
.option pop
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,379 | riscv-testdata/testdata/rv64uzba/sh1add_uw.S | # See LICENSE for license details.
#*****************************************************************************
# sh1add.uw.S
#-----------------------------------------------------------------------------
#
# Test sh1add.uw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh1add.uw, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh1add.uw, 0x00000003, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh1add.uw, 0x0000000d, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh1add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sh1add.uw, 0x0000000100000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, sh1add.uw, 0x00000000ffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sh1add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sh1add.uw, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sh1add.uw, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sh1add.uw, 0x0000000100007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sh1add.uw, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sh1add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sh1add.uw, 0x00000001ffffffff, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sh1add.uw, 0x00000001fffffffd, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, sh1add.uw, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh1add.uw, 37, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh1add.uw, 39, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh1add.uw, 39, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh1add.uw, 37, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh1add.uw, 39, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh1add.uw, 41, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add.uw, 37, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add.uw, 39, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add.uw, 41, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add.uw, 37, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add.uw, 39, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add.uw, 41, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add.uw, 37, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add.uw, 39, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add.uw, 41, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add.uw, 37, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add.uw, 39, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add.uw, 41, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh1add.uw, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh1add.uw, 64, 32 );
TEST_RR_ZEROSRC12( 37, sh1add.uw, 0 );
TEST_RR_ZERODEST( 38, sh1add.uw, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,380 | riscv-testdata/testdata/rv64uzba/sh2add_uw.S | # See LICENSE for license details.
#*****************************************************************************
# sh2add.uw.S
#-----------------------------------------------------------------------------
#
# Test sh2add.uw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh2add.uw, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh2add.uw, 0x00000005, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh2add.uw, 0x00000013, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh2add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sh2add.uw, 0x0000000200000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, sh2add.uw, 0x00000001ffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sh2add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sh2add.uw, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sh2add.uw, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sh2add.uw, 0x0000000200007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sh2add.uw, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sh2add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sh2add.uw, 0x00000003fffffffd, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sh2add.uw, 0x00000003fffffffb, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, sh2add.uw, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh2add.uw, 63, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh2add.uw, 67, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh2add.uw, 65, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh2add.uw, 63, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh2add.uw, 67, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh2add.uw, 71, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add.uw, 63, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add.uw, 67, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add.uw, 71, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add.uw, 63, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add.uw, 67, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add.uw, 71, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add.uw, 63, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add.uw, 67, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add.uw, 71, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add.uw, 63, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add.uw, 67, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add.uw, 71, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh2add.uw, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh2add.uw, 128, 32 );
TEST_RR_ZEROSRC12( 37, sh2add.uw, 0 );
TEST_RR_ZERODEST( 38, sh2add.uw, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,281 | riscv-testdata/testdata/rv64uzba/sh3add.S | # See LICENSE for license details.
#*****************************************************************************
# sh3add.S
#-----------------------------------------------------------------------------
#
# Test sh3add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh3add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sh3add, 0xfffffffc00000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, sh3add, 0xfffffffbffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sh3add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sh3add, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sh3add, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sh3add, 0xfffffffc00007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sh3add, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sh3add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sh3add, 0xfffffffffffffff9, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sh3add, 0xfffffffffffffff7, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, sh3add, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 );
TEST_RR_ZEROSRC12( 37, sh3add, 0 );
TEST_RR_ZERODEST( 38, sh3add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,263 | riscv-testdata/testdata/rv64uzba/sh2add.S | # See LICENSE for license details.
#*****************************************************************************
# sh2add.S
#-----------------------------------------------------------------------------
#
# Test sh2add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh2add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sh2add, 0xfffffffe00000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, sh2add, 0xfffffffdffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sh2add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sh2add, 0x00000001fffffffc, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sh2add, 0x0000000200007ffb, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sh2add, 0xfffffffe00007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sh2add, 0x00000001ffff7ffc, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sh2add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sh2add, 0xfffffffffffffffd, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sh2add, 0xfffffffffffffffb, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, sh2add, 0x0000000080000003, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 );
TEST_RR_ZEROSRC12( 37, sh2add, 0 );
TEST_RR_ZERODEST( 38, sh2add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,262 | riscv-testdata/testdata/rv64uzba/sh1add.S | # See LICENSE for license details.
#*****************************************************************************
# sh1add.S
#-----------------------------------------------------------------------------
#
# Test sh1add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh1add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sh1add, 0xffffffff00000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, sh1add, 0xfffffffeffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sh1add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sh1add, 0x00000000fffffffe, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sh1add, 0x0000000100007ffd, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sh1add, 0xffffffff00007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sh1add, 0x00000000ffff7ffe, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sh1add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sh1add, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sh1add, 0xfffffffffffffffd, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, sh1add, 0x0000000080000001, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 );
TEST_RR_ZEROSRC12( 37, sh1add, 0 );
TEST_RR_ZERODEST( 38, sh1add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,398 | riscv-testdata/testdata/rv64uzba/sh3add_uw.S | # See LICENSE for license details.
#*****************************************************************************
# sh3add_uw.S
#-----------------------------------------------------------------------------
#
# Test sh3add.uw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh3add.uw, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh3add.uw, 0x00000009, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh3add.uw, 0x0000001f, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh3add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sh3add.uw, 0x0000000400000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, sh3add.uw, 0x00000003ffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sh3add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sh3add.uw, 0x00000003fffffff8, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sh3add.uw, 0x0000000400007ff7, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sh3add.uw, 0x0000000400007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sh3add.uw, 0x00000003ffff7ff8, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sh3add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sh3add.uw, 0x00000007fffffff9, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sh3add.uw, 0x00000007fffffff7, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, sh3add.uw, 0x0000000080000007, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh3add.uw, 115, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh3add.uw, 123, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh3add.uw, 117, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh3add.uw, 115, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh3add.uw, 123, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh3add.uw, 131, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add.uw, 115, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add.uw, 123, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add.uw, 131, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add.uw, 115, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add.uw, 123, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add.uw, 131, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add.uw, 115, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add.uw, 123, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add.uw, 131, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add.uw, 115, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add.uw, 123, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add.uw, 131, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh3add.uw, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh3add.uw, 256, 32 );
TEST_RR_ZEROSRC12( 37, sh3add.uw, 0 );
TEST_RR_ZERODEST( 38, sh3add.uw, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,884 | riscv-testdata/testdata/rv64uzba/slli_uw.S | # See LICENSE for license details.
#*****************************************************************************
# slli_uw.S
#-----------------------------------------------------------------------------
#
# Test slli.uw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slli.uw, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, slli.uw, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, slli.uw, 0x00000000ffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, slli.uw, 0x00000001fffffffe, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, slli.uw, 0x0000007fffffff80, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, slli.uw, 0x00003fffffffc000, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, slli.uw, 0x7fffffff80000000, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, slli.uw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, slli.uw, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, slli.uw, 0x0000001090909080, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, slli.uw, 0x0000084848484000, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, slli.uw, 0x1090909080000000, 0x0000000021212121, 31 );
TEST_IMM_OP( 50, slli.uw, 0x8000000000000000, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, slli.uw, 0xffffff8000000000, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, slli.uw, 0x0909080000000000, 0x0000000021212121, 43 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slli.uw, 0x00000080, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, slli.uw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, slli.uw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, slli.uw, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 24, slli.uw, 0, 31 );
TEST_IMM_ZERODEST( 25, slli.uw, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,262 | riscv-testdata/testdata/rv64uzba/add_uw.S | # See LICENSE for license details.
#*****************************************************************************
# add_uw.S
#-----------------------------------------------------------------------------
#
# Test add.uw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, add.uw, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, add.uw, 0x00000002, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, add.uw, 0x0000000a, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, add.uw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, add.uw, 0x0000000080000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, add.uw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, add.uw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, add.uw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, add.uw, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, add.uw, 0x0000000080007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, add.uw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, add.uw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, add.uw, 0x0000000100000000, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, add.uw, 0x00000000fffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, add.uw, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, add.uw, 24, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, add.uw, 25, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, add.uw, 26, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, add.uw, 24, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, add.uw, 25, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, add.uw, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, add.uw, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, add.uw, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, add.uw, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, add.uw, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, add.uw, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, add.uw, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, add.uw, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, add.uw, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, add.uw, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, add.uw, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, add.uw, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, add.uw, 26, 15, 11 );
TEST_RR_ZEROSRC1( 35, add.uw, 15, 15 );
TEST_RR_ZEROSRC2( 36, add.uw, 32, 32 );
TEST_RR_ZEROSRC12( 37, add.uw, 0 );
TEST_RR_ZERODEST( 38, add.uw, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,818 | riscv-testdata/testdata/rv64uzbc/clmul.S | # See LICENSE for license details.
#*****************************************************************************
# clmul.S
#-----------------------------------------------------------------------------
#
# Test clmul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, clmul, 0x0000000000005a00, 0x0000000000007e00, 0x6db6db6db6db6db7 );
TEST_RR_OP(33, clmul, 0x0000000000005b40, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
TEST_RR_OP( 2, clmul, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, clmul, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, clmul, 0x00000009, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, clmul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, clmul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, clmul, 0x5555400000000000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP(30, clmul, 0xfffffffffffc324f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
TEST_RR_OP(31, clmul, 0xfffffffffffc324f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, clmul, 0x7f, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, clmul, 0x62, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, clmul, 0x51, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, clmul, 0x7f, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, clmul, 0x62, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, clmul, 0x69, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, clmul, 0x69, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, clmul, 0x69, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, clmul, 0x69, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, clmul, 0x7f, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, clmul, 0x62, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, clmul, 0x69, 15, 11 );
TEST_RR_ZEROSRC1( 26, clmul, 0, 31 );
TEST_RR_ZEROSRC2( 27, clmul, 0, 32 );
TEST_RR_ZEROSRC12( 28, clmul, 0 );
TEST_RR_ZERODEST( 29, clmul, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,798 | riscv-testdata/testdata/rv64uzbc/clmulh.S | # See LICENSE for license details.
#*****************************************************************************
# clmulh.S
#-----------------------------------------------------------------------------
#
# Test clmulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, clmulh, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 );
TEST_RR_OP(33, clmulh, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
TEST_RR_OP( 2, clmulh, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, clmulh, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, clmulh, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, clmulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, clmulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, clmulh, 0x555555557fffd555, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP(30, clmulh, 0x00000000000133cd, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
TEST_RR_OP(31, clmulh, 0x00000000000133cd, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, clmulh, 0, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, clmulh, 0, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, clmulh, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, clmulh, 0, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, clmulh, 0, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, clmulh, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulh, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulh, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulh, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulh, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulh, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulh, 0, 15, 11 );
TEST_RR_ZEROSRC1( 26, clmulh, 0, 31 );
TEST_RR_ZEROSRC2( 27, clmulh, 0, 32 );
TEST_RR_ZEROSRC12( 28, clmulh, 0 );
TEST_RR_ZERODEST( 29, clmulh, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,798 | riscv-testdata/testdata/rv64uzbc/clmulr.S | # See LICENSE for license details.
#*****************************************************************************
# clmulr.S
#-----------------------------------------------------------------------------
#
# Test clmulr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, clmulr, 0x0000000000002400, 0x0000000000007e00, 0x6db6db6db6db6db7 );
TEST_RR_OP(33, clmulr, 0x0000000000002480, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
TEST_RR_OP( 2, clmulr, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, clmulr, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, clmulr, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, clmulr, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, clmulr, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, clmulr, 0xaaaaaaaaffffaaaa, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP(30, clmulr, 0x000000000002679b, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
TEST_RR_OP(31, clmulr, 0x000000000002679b, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, clmulr, 0, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, clmulr, 0, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, clmulr, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, clmulr, 0, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, clmulr, 0, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, clmulr, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, clmulr, 0, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, clmulr, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, clmulr, 0, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, clmulr, 0, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, clmulr, 0, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, clmulr, 0, 15, 11 );
TEST_RR_ZEROSRC1( 26, clmulr, 0, 31 );
TEST_RR_ZEROSRC2( 27, clmulr, 0, 32 );
TEST_RR_ZEROSRC12( 28, clmulr, 0 );
TEST_RR_ZERODEST( 29, clmulr, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,732 | riscv-testdata/testdata/rv64um/mul.S | # See LICENSE for license details.
#*****************************************************************************
# mul.S
#-----------------------------------------------------------------------------
#
# Test mul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 );
TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
TEST_RR_ZEROSRC12( 28, mul, 0 );
TEST_RR_ZERODEST( 29, mul, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,420 | riscv-testdata/testdata/rv64um/mulw.S | # See LICENSE for license details.
#*****************************************************************************
# mulw.S
#-----------------------------------------------------------------------------
#
# Test mulw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
TEST_RR_ZEROSRC12( 28, mulw, 0 );
TEST_RR_ZERODEST( 29, mulw, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,781 | riscv-testdata/testdata/rv64um/mulhu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhu.S
#-----------------------------------------------------------------------------
#
# Test mulhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 );
TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 );
TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 );
TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 );
TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 );
TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 );
TEST_RR_ZEROSRC12( 28, mulhu, 0 );
TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,576 | riscv-testdata/testdata/rv64um/mulh.S | # See LICENSE for license details.
#*****************************************************************************
# mulh.S
#-----------------------------------------------------------------------------
#
# Test mulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 );
TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 );
TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 );
TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 );
TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 );
TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 );
TEST_RR_ZEROSRC12( 28, mulh, 0 );
TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,636 | riscv-testdata/testdata/rv64um/mulhsu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhsu.S
#-----------------------------------------------------------------------------
#
# Test mulhsu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 );
TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 );
TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 );
TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 );
TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 );
TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,180 | riscv-testdata/testdata/rv64ssvnapot/napot.S | # See LICENSE for license details.
#*****************************************************************************
# napot.S
#-----------------------------------------------------------------------------
#
# Test Svnapot
#
#include "riscv_test.h"
#include "test_macros.h"
#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
# error This test requires DRAM_BASE be SV39 superpage-aligned
#endif
#if __riscv_xlen != 64
# error This test requires RV64
#endif
RVTEST_RV64M
RVTEST_CODE_BEGIN
# Construct the page table
#define MY_VA 0x40201010
# VPN 2 == VPN 1 == VPN 0 == 0x1
# Page offset == 0x10
####
# Level 0 PTE contents
# PPN
la a0, my_data
srl a0, a0, 12
# adjust the PPN to be in NAPOT form
li a1, ~0xF
and a0, a0, a1
ori a0, a0, 0x8
# attributes
sll a0, a0, PTE_PPN_SHIFT
li a1, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D | PTE_N
or a0, a0, a1
# Level 0 PTE address
la a1, page_table
addi a1, a1, ((MY_VA >> 12) & 0x1FF) * 8
# Level 0 PTE store
sd a0, (a1)
####
# Level 1 PTE contents
la a0, page_table
srl a0, a0, 12
sll a0, a0, PTE_PPN_SHIFT
li a1, PTE_V
or a0, a0, a1
# Level 1 PTE address
la a1, page_table
addi a1, a1, ((MY_VA >> 21) & 0x1FF) * 8
li a2, 1 << 12
add a1, a1, a2
# Level 1 PTE store
sd a0, (a1)
####
# Level 2 PTE contents
la a0, page_table
li a1, 1 << 12
add a0, a0, a1
srl a0, a0, 12
sll a0, a0, PTE_PPN_SHIFT
li a1, PTE_V
or a0, a0, a1
# Level 2 PTE address
la a1, page_table
addi a1, a1, ((MY_VA >> 30) & 0x1FF) * 8
li a2, 2 << 12
add a1, a1, a2
# Level 2 PTE store
sd a0, (a1)
####
# Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT
la a0, my_data
li a1, ~0xFFFF
and a0, a0, a1
li a1, 0x8000 | (MY_VA & 0xFFF)
or a3, a0, a1
li a1, 0
sw a1, (a3)
####
li TESTNUM, 1
## Turn on VM
la a1, page_table
li a2, 2 << 12
add a1, a1, a2
srl a1, a1, 12
li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
or a0, a0, a1
csrw satp, a0
sfence.vma
# Set up MPRV with MPP=S and SUM=1, so loads and stores use S-mode and S can access U pages
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV | MSTATUS_SUM
csrs mstatus, a1
# Do a store to MY_VA
li a0, MY_VA
li a1, 42
napot_store:
sw a1, (a0)
# Clear MPRV
li a1, MSTATUS_MPRV
csrc mstatus, a1
# Do a load from the PA that would be written if the PTE were misinterpreted as non-NAPOT
lw a1, (a3)
# Check the result
li a0, 42
beq a1, a0, die
# Do a load from the PA for MY_VA
la a0, my_data
li a1, MY_VA & 0xFFFF
add a0, a0, a1
lw a1, (a0)
li a2, 42
# Check the result
bne a1, a2, die
####
RVTEST_PASS
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
# Skip if Svnapot is not implemented.
csrr t5, mcause
li t6, CAUSE_STORE_PAGE_FAULT
bne t5, t6, die
csrr t5, mepc
la t6, napot_store
bne t5, t6, die
csrr t5, mtval
li t6, MY_VA
beq t5, t6, pass
die:
RVTEST_FAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
.align 20
page_table: .dword 0
.align 20
my_data: .dword 0
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,054 | riscv-testdata/testdata/rv64uf/fdiv.S | # See LICENSE for license details.
#*****************************************************************************
# fdiv.S
#-----------------------------------------------------------------------------
#
# Test f{div|sqrt}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 );
TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 );
TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 );
TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 );
TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 );
TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,127 | riscv-testdata/testdata/rv64uf/fcvt.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt.S
#-----------------------------------------------------------------------------
#
# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2);
TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2);
TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2);
TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2);
#if __riscv_xlen >= 64
TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2);
TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2);
TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2);
TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2);
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,380 | riscv-testdata/testdata/rv64uf/fadd.S | # See LICENSE for license details.
#*****************************************************************************
# fadd.S
#-----------------------------------------------------------------------------
#
# Test f{add|sub|mul}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 );
TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 );
TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 );
TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 );
TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 );
TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 );
TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 );
TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 );
TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 );
# Is the canonical NaN generated for Inf - Inf?
TEST_FP_OP2_S(11, fsub.s, 0x10, qNaNf, Inf, Inf);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,504 | riscv-testdata/testdata/rv64uf/move.S | # See LICENSE for license details.
#*****************************************************************************
# move.S
#-----------------------------------------------------------------------------
#
# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions
# and the fcsr work properly.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
TEST_CASE(3, a0, 0x34, frsr a0)
TEST_CASE(4, a0, 0x14, frflags a0)
TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2)
TEST_CASE(6, a0, 0x54, frsr a0)
TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4)
TEST_CASE(8, a0, 0x50, frsr a0)
#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \
TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \
li a1, ((rs1_sign) << 31) | 0x12345678; \
li a2, -(rs2_sign); \
fmv.s.x f1, a1; \
fmv.s.x f2, a2; \
insn f0, f1, f2; \
fmv.x.s a0, f0)
TEST_FSGNJS(10, fsgnj.s, 0, 0, 0)
TEST_FSGNJS(11, fsgnj.s, 1, 0, 1)
TEST_FSGNJS(12, fsgnj.s, 0, 1, 0)
TEST_FSGNJS(13, fsgnj.s, 1, 1, 1)
TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0)
TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1)
TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0)
TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1)
TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0)
TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1)
TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0)
TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,360 | riscv-testdata/testdata/rv64uf/fcvt_w.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt_w.S
#-----------------------------------------------------------------------------
#
# Test fcvt{wu|w|lu|l}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_INT_OP_S( 2, fcvt.w.s, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_S( 3, fcvt.w.s, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_S( 4, fcvt.w.s, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_S( 5, fcvt.w.s, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_S( 6, fcvt.w.s, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_S( 7, fcvt.w.s, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_S( 8, fcvt.w.s, 0x10, -1<<31, -3e9, rtz);
TEST_FP_INT_OP_S( 9, fcvt.w.s, 0x10, (1<<31)-1, 3e9, rtz);
TEST_FP_INT_OP_S(12, fcvt.wu.s, 0x10, 0, -3.0, rtz);
TEST_FP_INT_OP_S(13, fcvt.wu.s, 0x10, 0, -1.0, rtz);
TEST_FP_INT_OP_S(14, fcvt.wu.s, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_S(15, fcvt.wu.s, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_S(16, fcvt.wu.s, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_S(17, fcvt.wu.s, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10, 0, -3e9, rtz);
TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000, 3e9, rtz);
#if __riscv_xlen >= 64
TEST_FP_INT_OP_S(22, fcvt.l.s, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_S(23, fcvt.l.s, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_S(24, fcvt.l.s, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_S(25, fcvt.l.s, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_S(26, fcvt.l.s, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_S(27, fcvt.l.s, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_S(32, fcvt.lu.s, 0x10, 0, -3.0, rtz);
TEST_FP_INT_OP_S(33, fcvt.lu.s, 0x10, 0, -1.0, rtz);
TEST_FP_INT_OP_S(34, fcvt.lu.s, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_S(35, fcvt.lu.s, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz);
#endif
# test negative NaN, negative infinity conversion
TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1)
TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1)
#if __riscv_xlen >= 64
TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1)
TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1)
#endif
# test positive NaN, positive infinity conversion
TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1)
TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1)
#if __riscv_xlen >= 64
TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1)
TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1)
#endif
# test NaN, infinity conversions to unsigned integer
TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1)
TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1)
TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1)
TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1)
#if __riscv_xlen >= 64
TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1)
TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1)
TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1)
TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1)
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
# -NaN, NaN, -inf, +inf
tdat:
.word 0xffffffff
.word 0x7fffffff
.word 0xff800000
.word 0x7f800000
tdat_d:
.dword 0xffffffffffffffff
.dword 0x7fffffffffffffff
.dword 0xfff0000000000000
.dword 0x7ff0000000000000
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,122 | riscv-testdata/testdata/rv64uf/recoding.S | # See LICENSE for license details.
#*****************************************************************************
# recoding.S
#-----------------------------------------------------------------------------
#
# Test corner cases of John Hauser's microarchitectural recoding scheme.
# There are twice as many recoded values as IEEE-754 values; some of these
# extras are redundant (e.g. Inf) and others are illegal (subnormals with
# too many bits set).
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
# Make sure infinities with different mantissas compare as equal.
flw f0, minf, a0
flw f1, three, a0
fmul.s f1, f1, f0
TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
# Likewise, but for zeroes.
fcvt.s.w f0, x0
li a0, 1
fcvt.s.w f1, a0
fmul.s f1, f1, f0
TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
minf: .float -Inf
three: .float 3.0
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,629 | riscv-testdata/testdata/rv64uf/fmadd.S | # See LICENSE for license details.
#*****************************************************************************
# fmadd.S
#-----------------------------------------------------------------------------
#
# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP3_S( 2, fmadd.s, 0, 3.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,872 | riscv-testdata/testdata/rv64uf/fmin.S | # See LICENSE for license details.
#*****************************************************************************
# fmin.S
#-----------------------------------------------------------------------------
#
# Test f{min|max}.s instructinos.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_S( 2, fmin.s, 0, 1.0, 2.5, 1.0 );
TEST_FP_OP2_S( 3, fmin.s, 0, -1235.1, -1235.1, 1.1 );
TEST_FP_OP2_S( 4, fmin.s, 0, -1235.1, 1.1, -1235.1 );
TEST_FP_OP2_S( 5, fmin.s, 0, -1235.1, NaN, -1235.1 );
TEST_FP_OP2_S( 6, fmin.s, 0, 0.00000001, 3.14159265, 0.00000001 );
TEST_FP_OP2_S( 7, fmin.s, 0, -2.0, -1.0, -2.0 );
TEST_FP_OP2_S(12, fmax.s, 0, 2.5, 2.5, 1.0 );
TEST_FP_OP2_S(13, fmax.s, 0, 1.1, -1235.1, 1.1 );
TEST_FP_OP2_S(14, fmax.s, 0, 1.1, 1.1, -1235.1 );
TEST_FP_OP2_S(15, fmax.s, 0, -1235.1, NaN, -1235.1 );
TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 );
TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 );
# FMAX(sNaN, x) = x
TEST_FP_OP2_S(20, fmax.s, 0x10, 1.0, sNaNf, 1.0);
# FMAX(qNaN, qNaN) = canonical NaN
TEST_FP_OP2_S(21, fmax.s, 0x00, qNaNf, NaN, NaN);
# -0.0 < +0.0
TEST_FP_OP2_S(30, fmin.s, 0, -0.0, -0.0, 0.0 );
TEST_FP_OP2_S(31, fmin.s, 0, -0.0, 0.0, -0.0 );
TEST_FP_OP2_S(32, fmax.s, 0, 0.0, -0.0, 0.0 );
TEST_FP_OP2_S(33, fmax.s, 0, 0.0, 0.0, -0.0 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,414 | riscv-testdata/testdata/rv64uf/fcmp.S | # See LICENSE for license details.
#*****************************************************************************
# fcmp.S
#-----------------------------------------------------------------------------
#
# Test f{eq|lt|le}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36)
TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36)
TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36)
TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36)
# Only sNaN should signal invalid for feq.
TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0)
TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN)
TEST_FP_CMP_OP_S(10, feq.s, 0x10, 0, sNaNf, 0)
# qNaN should signal invalid for fle/flt.
TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0)
TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN)
TEST_FP_CMP_OP_S(13, flt.s, 0x10, 0, sNaNf, 0)
TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0)
TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN)
TEST_FP_CMP_OP_S(16, fle.s, 0x10, 0, sNaNf, 0)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,521 | riscv-testdata/testdata/rv64ud/fdiv.S | # See LICENSE for license details.
#*****************************************************************************
# fdiv.S
#-----------------------------------------------------------------------------
#
# Test f{div|sqrt}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#if __riscv_xlen == 32
# Replace the functions with the 32-bit variants defined in test_macros.h
#undef TEST_FP_OP2_D
#define TEST_FP_OP2_D TEST_FP_OP2_D32
#undef TEST_FP_OP1_D
#define TEST_FP_OP1_D TEST_FP_OP1_D32
#undef TEST_FP_OP1_D_DWORD_RESULT
#define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
#endif
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 );
TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 );
TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 );
TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 );
TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 );
TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0);
TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,876 | riscv-testdata/testdata/rv64ud/fcvt.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt.S
#-----------------------------------------------------------------------------
#
# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#if __riscv_xlen == 32
# Replace the function with the 32-bit variant defined in test_macros.h
#undef TEST_INT_FP_OP_D
#define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
#undef TEST_FCVT_S_D
#define TEST_FCVT_S_D TEST_FCVT_S_D32
#endif
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_INT_FP_OP_D(2, fcvt.d.w, 2.0, 2);
TEST_INT_FP_OP_D(3, fcvt.d.w, -2.0, -2);
TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2);
TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2);
#if __riscv_xlen >= 64
TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2);
TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2);
TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2);
TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2);
#endif
TEST_FCVT_S_D(10, -1.5, -1.5)
TEST_FCVT_D_S(11, -1.5, -1.5)
#if __riscv_xlen >= 64
TEST_CASE(12, a0, 0x7ff8000000000000,
la a1, test_data_22;
ld a2, 0(a1);
fmv.d.x f2, a2;
fcvt.s.d f2, f2;
fcvt.d.s f2, f2;
fmv.x.d a0, f2;
)
#else
TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000,
la a1, test_data_22;
fld f2, 0(a1);
fcvt.s.d f2, f2;
fcvt.d.s f2, f2;
fsd f2, 0(a1);
lw a0, 0(a1);
lw a1, 4(a1)
)
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
test_data_22:
.dword 0x7ffcffffffff8004
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,553 | riscv-testdata/testdata/rv64ud/fadd.S | # See LICENSE for license details.
#*****************************************************************************
# fadd.S
#-----------------------------------------------------------------------------
#
# Test f{add|sub|mul}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#if __riscv_xlen == 32
# Replace the function with the 32-bit variant defined in test_macros.h
#undef TEST_FP_OP2_D
#define TEST_FP_OP2_D TEST_FP_OP2_D32
#endif
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_D( 2, fadd.d, 0, 3.5, 2.5, 1.0 );
TEST_FP_OP2_D( 3, fadd.d, 1, -1234, -1235.1, 1.1 );
TEST_FP_OP2_D( 4, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 );
TEST_FP_OP2_D( 5, fsub.d, 0, 1.5, 2.5, 1.0 );
TEST_FP_OP2_D( 6, fsub.d, 1, -1234, -1235.1, -1.1 );
TEST_FP_OP2_D( 7, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 );
TEST_FP_OP2_D( 8, fmul.d, 0, 2.5, 2.5, 1.0 );
TEST_FP_OP2_D( 9, fmul.d, 1, 1358.61, -1235.1, -1.1 );
TEST_FP_OP2_D(10, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 );
# Is the canonical NaN generated for Inf - Inf?
TEST_FP_OP2_D(11, fsub.d, 0x10, qNaN, Inf, Inf);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,659 | riscv-testdata/testdata/rv64ud/move.S | # See LICENSE for license details.
#*****************************************************************************
# move.S
#-----------------------------------------------------------------------------
#
# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#TODO: make 32-bit compatible version
#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \
TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \
li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \
li a2, -(rs2_sign); \
fmv.d.x f1, a1; \
fmv.d.x f2, a2; \
insn f0, f1, f2; \
fmv.x.d a0, f0)
TEST_FSGNJD(10, fsgnj.d, 0, 0, 0)
TEST_FSGNJD(11, fsgnj.d, 1, 0, 1)
TEST_FSGNJD(12, fsgnj.d, 0, 1, 0)
TEST_FSGNJD(13, fsgnj.d, 1, 1, 1)
TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0)
TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1)
TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0)
TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1)
TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0)
TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1)
TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0)
TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1)
// Test fsgnj.s in conjunction with double-precision moves
#define TEST_FSGNJS(n, rd, rs1, rs2) \
TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \
li a1, rs1; \
li a2, rs2; \
fmv.d.x f1, a1; \
fmv.d.x f2, a2; \
fsgnj.s f0, f1, f2; \
fmv.x.s a0, f0); \
TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \
li a1, rs1; \
li a2, rs2; \
fmv.d.x f1, a1; \
fmv.d.x f2, a2; \
fsgnj.s f0, f1, f2; \
fmv.x.d a0, f0)
TEST_FSGNJS(40, 0x7fc00000, 0x7ffffffe12345678, 0)
TEST_FSGNJS(41, 0x7fc00000, 0xfffffffe12345678, 0)
TEST_FSGNJS(42, 0x7fc00000, 0x7fffffff12345678, 0)
TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0)
TEST_FSGNJS(50, 0x7fc00000, 0x7ffffffe12345678, 0x80000000)
TEST_FSGNJS(51, 0x7fc00000, 0xfffffffe12345678, 0x80000000)
TEST_FSGNJS(52, 0x7fc00000, 0x7fffffff12345678, 0x80000000)
TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000)
TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000)
TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000)
TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000)
TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000)
// Test fsgnj.d in conjunction with single-precision moves
#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \
TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \
li a1, rs1; \
li a2, rs2; \
fmv.d.x f1, a1; \
fmv.d.x f2, a2; \
fsgnj.d f0, f1, f2; \
feq.s a0, f0, f0; \
addi a0, a0, -!(isnan); \
bnez a0, 1f; \
fmv.x.s a0, f0; \
1:); \
TEST_CASE(1##n, a0, rd, \
li a1, rs1; \
li a2, rs2; \
fmv.d.x f1, a1; \
fmv.d.x f2, a2; \
fsgnj.d f0, f1, f2; \
fmv.x.d a0, f0; \
1:)
TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111)
TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111)
TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111)
TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000)
TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111)
TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111)
TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111)
TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,731 | riscv-testdata/testdata/rv64ud/fcvt_w.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt_w.S
#-----------------------------------------------------------------------------
#
# Test fcvt{wu|w|lu|l}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz);
TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz);
TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz);
TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz);
TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz);
TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
#if __riscv_xlen >= 64
TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz);
TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz);
TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz);
TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz);
TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz);
TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz);
TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz);
TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz);
TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz);
TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz);
TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz);
TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz);
TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz);
TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz);
#endif
# test negative NaN, negative infinity conversion
TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1)
#if __riscv_xlen >= 64
TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1)
#endif
TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
#if __riscv_xlen >= 64
TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
#endif
# test positive NaN, positive infinity conversion
TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1)
#if __riscv_xlen >= 64
TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1)
#endif
TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
#if __riscv_xlen >= 64
TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
#endif
# test NaN, infinity conversions to unsigned integer
TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1)
TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1)
TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
#if __riscv_xlen >= 64
TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1)
TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1)
TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
# -NaN, NaN, -inf, +inf
tdat:
.word 0xffffffff
.word 0x7fffffff
.word 0xff800000
.word 0x7f800000
tdat_d:
.dword 0xffffffffffffffff
.dword 0x7fffffffffffffff
.dword 0xfff0000000000000
.dword 0x7ff0000000000000
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,686 | riscv-testdata/testdata/rv64ud/recoding.S | # See LICENSE for license details.
#*****************************************************************************
# recoding.S
#-----------------------------------------------------------------------------
#
# Test corner cases of John Hauser's microarchitectural recoding scheme.
# There are twice as many recoded values as IEEE-754 values; some of these
# extras are redundant (e.g. Inf) and others are illegal (subnormals with
# too many bits set).
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
# Make sure infinities with different mantissas compare as equal.
fld f0, minf, a0
fld f1, three, a0
fmul.d f1, f1, f0
TEST_CASE( 2, a0, 1, feq.d a0, f0, f1)
TEST_CASE( 3, a0, 1, fle.d a0, f0, f1)
TEST_CASE( 4, a0, 0, flt.d a0, f0, f1)
# Likewise, but for zeroes.
fcvt.d.w f0, x0
li a0, 1
fcvt.d.w f1, a0
fmul.d f1, f1, f0
TEST_CASE(5, a0, 1, feq.d a0, f0, f1)
TEST_CASE(6, a0, 1, fle.d a0, f0, f1)
TEST_CASE(7, a0, 0, flt.d a0, f0, f1)
# When converting small doubles to single-precision subnormals,
# ensure that the extra precision is discarded.
flw f0, big, a0
fld f1, tiny, a0
fcvt.s.d f1, f1
fmul.s f0, f0, f1
fmv.x.s a0, f0
lw a1, small
TEST_CASE(10, a0, 0, sub a0, a0, a1)
# Make sure FSD+FLD correctly saves and restores a single-precision value.
flw f0, three, a0
fadd.s f1, f0, f0
fadd.s f0, f0, f0
fsd f0, tiny, a0
fld f0, tiny, a0
TEST_CASE(20, a0, 1, feq.s a0, f0, f1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
minf: .double -Inf
three: .double 3.0
big: .float 1221
small: .float 2.9133121e-37
tiny: .double 2.3860049081905093e-40
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,803 | riscv-testdata/testdata/rv64ud/fmadd.S | # See LICENSE for license details.
#*****************************************************************************
# fmadd.S
#-----------------------------------------------------------------------------
#
# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#if __riscv_xlen == 32
# Replace the function with the 32-bit variant defined in test_macros.h
#undef TEST_FP_OP3_D
#define TEST_FP_OP3_D TEST_FP_OP3_D32
#endif
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 );
TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 );
TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 );
TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,028 | riscv-testdata/testdata/rv64ud/ldst.S | # See LICENSE for license details.
#*****************************************************************************
# ldst.S
#-----------------------------------------------------------------------------
#
# This test verifies that flw, fld, fsw, and fsd work properly.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
la s0, tdat
TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0))
TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0))
TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0))
TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0))
TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0))
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
.word 0xbf800000
.word 0x40000000
.word 0x40400000
.word 0xc0800000
.word 0xdeadbeef
.word 0xcafebabe
.word 0xabad1dea
.word 0x1337d00d
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,229 | riscv-testdata/testdata/rv64ud/fclass.S | # See LICENSE for license details.
#*****************************************************************************
# fclass.S
#-----------------------------------------------------------------------------
#
# Test fclass.d instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#if __riscv_xlen == 32
# Replace the function with the 32-bit variant defined in test_macros.h
#undef TEST_FCLASS_D
#define TEST_FCLASS_D TEST_FCLASS_D32
#endif
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 )
TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 )
TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 )
TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 )
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,044 | riscv-testdata/testdata/rv64ud/fmin.S | # See LICENSE for license details.
#*****************************************************************************
# fmin.S
#-----------------------------------------------------------------------------
#
# Test f{min|max}.d instructinos.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#if __riscv_xlen == 32
# Replace the function with the 32-bit variant defined in test_macros.h
#undef TEST_FP_OP2_D
#define TEST_FP_OP2_D TEST_FP_OP2_D32
#endif
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 );
TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 );
TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 );
TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 );
TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 );
TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 );
TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 );
TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 );
TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 );
TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 );
TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 );
TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 );
# FMAX(sNaN, x) = x
TEST_FP_OP2_D(20, fmax.d, 0x10, 1.0, sNaN, 1.0);
# FMAX(qNaN, qNaN) = canonical NaN
TEST_FP_OP2_D(21, fmax.d, 0x00, qNaN, NaN, NaN);
# -0.0 < +0.0
TEST_FP_OP2_D(30, fmin.d, 0, -0.0, -0.0, 0.0 );
TEST_FP_OP2_D(31, fmin.d, 0, -0.0, 0.0, -0.0 );
TEST_FP_OP2_D(32, fmax.d, 0, 0.0, -0.0, 0.0 );
TEST_FP_OP2_D(33, fmax.d, 0, 0.0, 0.0, -0.0 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,594 | riscv-testdata/testdata/rv64ud/fcmp.S | # See LICENSE for license details.
#*****************************************************************************
# fcmp.S
#-----------------------------------------------------------------------------
#
# Test f{eq|lt|le}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
#if __riscv_xlen == 32
# Replace the function with the 32-bit variant defined in test_macros.h
#undef TEST_FP_CMP_OP_D
#define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
#endif
TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36)
TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36)
TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36)
# Only sNaN should signal invalid for feq.
TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0)
TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN)
TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0)
# qNaN should signal invalid for fle/flt.
TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0)
TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN)
TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0)
TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0)
TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN)
TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,159 | riscv-testdata/testdata/rv64ud/structural.S | # See LICENSE for license details.
#*****************************************************************************
# structural.S
#-----------------------------------------------------------------------------
#
# This test verifies that the FPU correctly obviates structural hazards on its
# writeback port (e.g. fadd followed by fsgnj)
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN
li x12, 1
li x2, 0x3FF0000000000000
li x1, 0x3F800000
#define TEST(testnum, nops) \
test_ ## testnum: \
li TESTNUM, testnum; \
fmv.d.x f4, x0 ;\
fmv.s.x f3, x0 ;\
fmv.d.x f2, x2 ;\
fmv.s.x f1, x1 ;\
j 1f ;\
.align 5 ;\
1:fmul.d f4, f2, f2 ;\
nops ;\
fsgnj.s f3, f1, f1 ;\
fmv.x.d x4, f4 ;\
fmv.x.s x5, f3 ;\
beq x1, x5, 2f ;\
j fail;\
2:beq x2, x4, 2f ;\
j fail; \
2:fmv.d.x f2, zero ;\
fmv.s.x f1, zero ;\
TEST(1,;)
TEST(2,nop)
TEST(3,nop;nop)
TEST(4,nop;nop;nop)
TEST(5,nop;nop;nop;nop)
TEST(6,nop;nop;nop;nop;nop)
TEST(7,nop;nop;nop;nop;nop;nop)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matt-user/sbpf-amm | 4,548 | src/sbpf-amm/sbpf-amm.s | .equ NUM_ACCOUNTS, 0x0000
.equ AMM_PDA_HEADER, 0x0008
.equ AMM_PDA_KEY, 0x0010
.equ AMM_PDA_OWNER, 0x0030
.equ AMM_PDA_LAMPORTS, 0x0050
.equ AMM_PDA_DATA_LEN, 0x0058
.equ AMM_PDA_ID, 0x0060 // Pubkey (32 bytes)
.equ AMM_PDA_ADMIN, 0x0080 // Pubkey (32 bytes)
.equ AMM_PDA_FEE, 0x00a0 // u16 (2 bytes)
.equ ADMIN_PUBKEY_HEADER, 0x28b0
.equ ADMIN_PUBKEY_KEY, 0x28b8
.equ ADMIN_PUBKEY_OWNER, 0x28d8
.equ ADMIN_PUBKEY_LAMPORTS, 0x28f8
.equ ADMIN_PUBKEY_DATA_LEN, 0x2900
.equ ADMIN_PUBKEY_DATA, 0x2908
.equ OWNER_PUBKEY_HEADER, 0x5110
.equ OWNER_PUBKEY_KEY, 0x5118
.equ OWNER_PUBKEY_OWNER, 0x5138
.equ OWNER_PUBKEY_LAMPORTS, 0x5158
.equ OWNER_PUBKEY_DATA_LEN, 0x5160
.equ OWNER_PUBKEY_DATA, 0x5168
.equ SYSTEM_PROGRAM_HEADER, 0x7970
.equ SYSTEM_PROGRAM_KEY, 0x7978
.equ SYSTEM_PROGRAM_OWNER, 0x7998
.equ SYSTEM_PROGRAM_LAMPORTS, 0x79b8
.equ SYSTEM_PROGRAM_DATA_LEN, 0x79c0
.equ SYSTEM_PROGRAM_DATA, 0x79c8
.equ INSTRUCTION_DATA_LEN, 0xa1d0
.equ INSTRUCTION_DATA, 0xa1d8
.equ INSTRUCTION_DISCRIMINATOR, 0xa1d8 // u8 (1 bytes)
.equ INSTRUCTION_ID, 0xa1d9 // Pubkey (32 bytes)
.equ INSTRUCTION_FEE, 0xa1f9 // u16 (2 bytes)
.equ PROGRAM_ID, 0xa1fb
.globl entrypoint
entrypoint:
call parse_input
# Branch based on the instruction type.
ldxb r4, [r2 + 0]
jeq r4, 0x0, create_amm
jeq r4, 0x1, create_pool
jeq r4, 0x2, deposit_liquidity
jeq r4, 0x3, swap_tokens_for_tokens
jeq r4, 0x4, withdraw_liquidity
# Parse the program input and set r2 to the instruction data pointer.
# Based on: https://github.com/cavemanloverboy/asmr
parse_input:
# Save the original input pointer
mov64 r7, r1
# Load count of accounts (first 8 bytes)
ldxdw r5, [r1 + 0]
# Move pointer past the count
add64 r1, 8
# If no accounts, jump to the end
jeq r5, 0, 6f
2:
ldxb r6, [r1 + 0]
jne r6, 255, 5f
3:
ldxdw r8, [r1 + 72 + 8]
add64 r1, TOTAL_ACCOUNT_SIZE
add64 r1, r8
add64 r1, 7
and64 r1, 0xFFFFFFFFFFFFFFF8
sub64 r5, 1
jne r5, 0, 2b
ja 6f
5:
add64 r1, 8
sub64 r5, 1
jne r5, 0, 2b
6:
add64 r1, 8
mov64 r2, r1
mov64 r1, r7
exit
create_amm:
lddw r1, msg_create_amm
lddw r2, 10
call sol_log_
# Validate fee < 10000
ldxh r2, [r1 + INSTRUCTION_FEE] # Load fee (u16) from instruction data
lddw r3, 10000
jge r2, r3, error_invalid_fee
# Check that payer account is a signer
ldxdw r2, [r1 + OWNER_PUBKEY_HEADER]
jeq r2, 0, error_not_signer
# Store instruction data and admin account in AMM account
# Account 0: AMM PDA (already exists, to be updated)
# Account 1: Admin (read-only)
# Account 2: Payer (signer, mutable)
# Set the AMM account owner to our program
ldxdw r2, [r1 + PROGRAM_ID] # Load program ID
stxdw [r1 + AMM_PDA_OWNER], r2 # Store as owner
# Copy the id from instruction data to account data
mov r2, r1
add r2, INSTRUCTION_DATA # + 8 # Skip instruction discriminator, point to id
mov r3, r1
add r3, AMM_PDA_DATA
# add r3, 8 # Skip discriminator space
lddw r4, 32 # Copy 32 bytes for id
call memcpy
# Copy admin pubkey to account data
mov r2, r1
add r2, ADMIN_PUBKEY_KEY
mov r3, r1
add r3, AMM_PDA_DATA
add r3, 32 # Skip discriminator + id
lddw r4, 32 # Copy 32 bytes for admin
call memcpy
# Store fee in account data
ldxh r2, [r1 + INSTRUCTION_FEE] # Load fee
stxh [r1 + AMM_PDA_FEE], r2 # Store fee at offset 72
jmp success
success:
lddw r1, msg_success
lddw r2, 7
call sol_log_
exit
error_invalid_fee:
lddw r1, msg_invalid_fee
lddw r2, 13
call sol_log_
exit
error_not_signer:
lddw r1, msg_not_signer
lddw r2, 12
call sol_log_
exit
# Helper function to copy memory
memcpy:
jeq r4, 0, memcpy_done
ldxb r5, [r2 + 0]
stxb [r3 + 0], r5
add r2, 1
add r3, 1
sub r4, 1
jmp memcpy
memcpy_done:
exit
create_pool:
lddw r1, msg_create_pool
lddw r2, 11
call sol_log_
exit
deposit_liquidity:
lddw r1, msg_deposit_liquidity
lddw r2, 17
call sol_log_
exit
swap_tokens_for_tokens:
lddw r1, msg_swap_tokens_for_tokens
lddw r2, 22
call sol_log_
exit
withdraw_liquidity:
lddw r1, msg_withdraw_liquidity
lddw r2, 18
call sol_log_
exit
.rodata
msg_create_amm: .ascii "create_amm"
msg_create_pool: .ascii "create_pool"
msg_deposit_liquidity: .ascii "deposit_liquidity"
msg_swap_tokens_for_tokens: .ascii "swap_tokens_for_tokens"
msg_withdraw_liquidity: .ascii "withdraw_liquidity"
msg_success: .ascii "success"
msg_invalid_fee: .ascii "invalid_fee"
msg_not_signer: .ascii "not_signer" |
maubry-ortega/VesperOS | 1,233 | src/arch/x86_64/interrupts.S | // src/arch/x86_64/interrupts.S
.intel_syntax noprefix // Usar sintaxis de Intel para el ensamblador.
// Hacemos que los símbolos de nuestras funciones Rust sean visibles para el ensamblador.
.extern rust_timer_interrupt_handler
.extern rust_keyboard_interrupt_handler
// Macro para crear un manejador de interrupciones genérico.
// Esta es una práctica estándar en el desarrollo de sistemas operativos.
// No necesita manejar códigos de error para las interrupciones del PIC (timer, teclado).
.macro interrupt_handler_stub name, rust_handler_func
.global \name
\name:
// Guardar registros de propósito general
push rax
push rcx
push rdx
push rsi
push rdi
push r8
push r9
push r10
push r11
// Llamar a la rutina en Rust
call \rust_handler_func
// Restaurar registros en orden inverso.
pop r11
pop r10
pop r9
pop r8
pop rdi
pop rsi
pop rdx
pop rcx
pop rax
// Retornar de la interrupción
iretq
.endm
// Usamos la macro para crear los manejadores para el timer y el teclado.
interrupt_handler_stub timer_interrupt_stub, rust_timer_interrupt_handler
interrupt_handler_stub keyboard_interrupt_stub, rust_keyboard_interrupt_handler
|
max-cura/cs240lx-riscv-lab | 5,597 | staff/okboot/extern/elf.S | @ vim:ft=arm
@
@@
@@ FILE device/okboot/extern/elf.S
@@ AUTH mcura
@@ DESC Relocatable micro-stub that performs a series of memory-to-memory ELF
@@ PT_LOAD operations.
@@
@@ CHANGELOG:
@@ 31 Jan 25 (mcura)
@@ Created based on stub.S for version 2 bootloader (okboot)
#define _prefetch_flush(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c5, 4
#define _cln_inv_dcache_entire(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c14, 0
#define _inv_both_caches_entire(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c7, 0
#define _btac_flush(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c5, 6
#define _dsb(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c10, 4
.globl __symbol_relocation_elf
.globl __symbol_relocation_elf_end
#define ENABLE_DEBUG 0
#if ENABLE_DEBUG
# define putss(str) push {r0};adr r0,str;bl uart_puts;pop {r0}
# define putc(chr) push {r0};mov r0, chr; bl uart_write8;pop {r0}
# define putx(num) push {r0};mov r0, num; bl uart_write_u32x;pop {r0}
#else
# define putss(x)
# define putc(x)
# define putx(x)
#endif
# Elf32_Phdr
# p_type - ignore
# p_offset
# p_vaddr
# p_paddr - ignore
# p_filesz - ignore
# p_memsz
# p_flags - ignore
# p_align - ignore
#define P_OFFSET 0x4
#define P_VADDR 0x8
#define P_MEMSZ 0x14
#define PHDR_SIZE 0x20
@ r0 = pheaders : *const Elf32_Phdr
@ r1 = pheaders_count : usize
@ r2 = elf "file" base : *const u8
@ r3 = entry : word
__symbol_relocation_elf:
mov sp, #0x8000
putc(#'\n')
putss(str.begin_elf_reloc)
bl copy_segments
putss(str.finished_copy_segments)
bl clear_caches
bx r3
@ r0 = pheaders
@ r1 = pheaders_count
@ r2 = elf "file" base
.align 4
copy_segments: @ COPY ELF SEGMENTS
push {r0-r2, r4-r11, r14}
mov r9, r0
mov r10, r1
mov r11, r2
.phdr_loop:
putx(r9)
putx(r10)
ldr r0, [r9, #P_VADDR]
ldr r2, [r9, #P_MEMSZ]
movs r2, r2
beq .phdr_fill_zero
ldr r1, [r9, #P_OFFSET]
add r1, r1, r11
bl memcpy
b .phdr_loop2
.phdr_fill_zero:
bl memset
.phdr_loop2:
subs r10, r10, #1
beq .copy_segments.ret
add r9, r9, #PHDR_SIZE
b .phdr_loop
.copy_segments.ret:
pop {r0-r2, r4-r11, r15}
@ CLOBBERS: r4
clear_caches:
_dsb(r4)
_cln_inv_dcache_entire(r4)
_inv_both_caches_entire(r4)
_btac_flush(r4)
_prefetch_flush(r4)
_dsb(r4)
bx lr
@ --- UTILITY ROUTINES --
@ INPUT: r0 <- #0, len=r2
@ CLOBBER: r0, r4, r5, r6, r7, r8
memset:
.memset_try_coarse:
mov r4, #0
mvn r8, #0xf
ands r8, r2, r8
beq .memset_try_fine
mov r5, #0
mov r6, #0
mov r7, #0
.memset_loop_coarse:
stmia r0!, {r4, r5, r6, r7}
subs r8, r8, #0x10
bne .memset_loop_coarse
.memset_try_fine:
ands r8, r2, #0x0f
beq .memset_done
.memset_loop_fine:
str r4, [r0], +#4
subs r8, r8, #4
bne .memset_loop_fine
.memset_done:
bx lr
@ INPUT: r0 <- r1, len=r2
@ clobber: r0, r1, r4, r5, r6, r7, r8
memcpy:
.memcpy_try_coarse:
mvn r8, #0xf
ands r8, r2, r8
beq .memcpy_try_fine
.memcpy_loop_coarse:
ldmia r1!, {r4, r5, r6, r7}
stmia r0!, {r4, r5, r6, r7}
subs r8, r8, #0x10
bne .memcpy_loop_coarse
.memcpy_try_fine:
ands r8, r2, #0x0f
beq .memcpy_done
.memcpy_loop_fine:
ldr r4, [r1], +#4
str r4, [r0], +#4
subs r8, r8, #4
bne .memcpy_loop_fine
.memcpy_done:
bx lr
@ --- DEBUGGING ROUTINES ---
#if ENABLE_DEBUG
str.begin_elf_reloc: .asciz "[asm] beginning ELF relocation"
str.finished_copy_segments: .asciz "[asm] finished copying segments"
#else
str.begin_elf_reloc:
str.finished_copy_segments:
#endif
#if ENABLE_DEBUG
.parled.on:
push {r4, r10, r14}
_dsb(r4)
ldr r10, loc.gpio_base
mov r4, #(1 << 27)
str r4, [r10, #0x1c]
_dsb(r4)
pop {r4, r10, r15}
.parled.off:
push {r4, r10, r14}
_dsb(r4)
ldr r10, loc.gpio_base
mov r4, #(1 << 27)
str r4, [r10, #0x28]
_dsb(r4)
pop {r4, r10, r15}
.actled.on:
push {r4, r10, r14}
_dsb(r4)
ldr r10, loc.gpio_base
mov r4, #1
lsl r4, r4, #(47-32)
str r4, [r10, #0x2c]
_dsb(r4)
pop {r4, r10, r15}
.actled.off:
push {r4, r10, r14}
_dsb(r4)
ldr r10, loc.gpio_base
mov r4, #1
lsl r4, r4, #(47-32)
str r4, [r10, #0x20]
_dsb(r4)
pop {r4, r10, r15}
loc.gpio_base: .word 0x20200000
#define MU_STAT 0x64
#define MU_STAT_TX_READY 1
#define MU_LSR 0x54
#define MU_LSR_FIFO_CAN_WRITE 5
#define MU_IO 0x40
uart_puts:
push {r0, r1, lr}
mov r1, r0
.ascii_chars:
ldrb r0, [r1], +#1
cmp r0, #0
beq .newline_puts
bl uart_write8
b .ascii_chars
.newline_puts:
mov r0, #'\n'
bl uart_write8
pop {r0, r1, pc}
uart_write_u32x:
push {r0, r1, r2, r3, lr}
mov r3, #0xf
mov r2, r0
mov r1, #32
.digits:
sub r1, r1, #4
and r0, r2, r3, lsl r1
mov r0, r0, lsr r1
subs r0, r0, #10
addlt r0, r0, #('0' + 10)
addge r0, r0, #'a'
bl uart_write8
cmp r1, #0
beq .newline32
b .digits
.newline32:
mov r0, #'\n'
bl uart_write8
pop {r0, r1, r2, r3, pc}
uart_write8:
push {r1, r2, r14}
_dsb(r1)
ldr r2, loc.uart_base
.uart_busy:
ldr r1, [r2, #MU_LSR]
tst r1, #(1 << MU_LSR_FIFO_CAN_WRITE)
bne .uart_can_write @ if bit is set
b .uart_busy
.uart_can_write:
str r0, [r2, #MU_IO]
_dsb(r1)
pop {r1, r2, r15}
loc.uart_base: .word 0x20215000
#endif
@ --- TERMINATING SYMBOL ---
__symbol_relocation_elf_end:
nop
nop
|
max-cura/cs240lx-riscv-lab | 5,247 | staff/okboot/extern/stub.S | @ vim:ft=arm
@
@@
@@ FILE device/okboot/extern/stub.S
@@ AUTH mcura
@@ DESC Relocatable micro-stub that performs a `memcpy` and then jumps to an
@@ address. Part of the `theseus-device` crate. Primary symbol is
@@ `_relocation_stub`; relocatable segment is
@@
@@ [_relocation_stub, _relocation_stub_end)
@@
@@ Note that this has some additional functionality beyond merely a
@@ `memcpy` and branch; read the source for additional details (any
@@ description here will almost inevitably become de-synchronised with the
@@ code
@@
@@ CHANGELOG:
@@ 15 Apr 24 (mcura)
@@ Separated from boot.S in an effort to clean up code for debugging.
@@ 17 Jun 24 (mcura)
@@ More cleanup in preparation for bootloader v2
#define _prefetch_flush(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c5, 4
#define _cln_inv_dcache_entire(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c14, 0
#define _inv_both_caches_entire(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c7, 0
#define _btac_flush(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c5, 6
#define _dsb(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c10, 4
.globl __symbol_relocation_stub
.globl __symbol_relocation_stub_end
@
@ HACKING NOTES
@ 1. DO NOT MAKE ANY REFERENCE TO ANY SYMBOL NOT CONTAINED BETWEEN
@ _relocation_stub AND _relocation_stub_end! DOING SO MAY CAUSE DATA
@ CORRUPTION.
@
@ Note that this includes as well the use of `ldr {reg}, ={value}`, even
@ if `value` is not explicitly a symbol (e.g. `ldr r0, =0x8000` and
@ `ldr r0, =non_local_symbol` are both equally forbidden). This is
@ because `ldr {reg}, ={value}` will attempt to resolve to an immediate
@ `MOV`, and, failing that, will put `{value}` in the local data pool.
@ I (mcura) am personally unclear on the rules of placement for these
@ values, but prior experience (via disassembly) has shown the values
@ showing up after the end of the relocation boundary--and thus not being
@ moved by the stub.
@
@ --------------------------------------------------------------------------------------------------
@ SECTION: RELOCATION
@ --------------------------------------------------------------------------------------------------
@ INPUT: r0=dest r1=src r2=len r3=jump_to
__symbol_relocation_stub:
@ INPUT: r0, r1, r2
@ OUTPUT: N/A
@ CLOBBERS: r0, r1, r4, r5, r6, r7, r8
.fastreloc_copy:
@bl .actled.on
.fastreloc_try_coarse:
mvn r8, #0x0f
ands r8, r2, r8
beq .fastreloc_try_fine
.fastreloc_loop_coarse:
@ need ! to write the incremented value back to r1/r0 when the instruction
@ finishes
ldmia r1!, {r4, r5, r6, r7}
stmia r0!, {r4, r5, r6, r7}
subs r8, r8, #0x10
bne .fastreloc_loop_coarse
.fastreloc_try_fine:
ands r8, r2, #0x0f
beq .fastreloc_done
.fastreloc_loop_fine:
ldr r4, [r1], +#4
str r4, [r0], +#4
subs r8, r8, #4
bne .fastreloc_loop_fine
.fastreloc_done:
@bl .actled.off
b .postreloc
@ INPUT: r0, r1, r2
@ OUTPUT: N/A
@ CLOBBERS: r0, r1, r2, r4
.slowreloc_copy:
@bl .actled.on
teq r2, #0
beq .slowreloc_done
.slowreloc_loop:
ldr r4, [r1], +#4
str r4, [r0], +#4
subs r2, r2, #4
bne .slowreloc_loop
.slowreloc_done:
b .postreloc
.postreloc:
@ INPUT: N/A
@ OUTPUT: N/A
@ CLOBBERS: r4
.clear_caches:
_dsb(r4)
@ not
_cln_inv_dcache_entire(r4)
_inv_both_caches_entire(r4)
_btac_flush(r4)
_prefetch_flush(r4)
_dsb(r4)
.jump_to_loaded_program:
bx r3
@ --------------------------------------------------------------------------------------------------
@ SECTION: GPIO
@ --------------------------------------------------------------------------------------------------
@ INPUT: r10
@ OUTPUT: N/A
@ CLOBBERS: r4
.actled.on:
_dsb(r4)
mov r4, #1
lsl r4, r4, #(47-32)
str r4, [r10, #0x2c]
_dsb(r4)
bx lr
.actled.off:
_dsb(r4)
mov r4, #1
lsl r4, r4, #(47-32)
str r4, [r10, #0x20]
_dsb(r4)
bx lr
@ INPUT: N/A
@ OUTPUT: r10=loc.gpio_base
@ CLOBBERS: r4, r5, r7, r10
.gpio_setup:
_dsb(r4)
ldr r10, loc.gpio_base
#if 0
@ pin 27 output (activity LED on parthiv-pi hat)
ldr r5, [r10, #0x08]
mov r7, #7
mvn r7, r7, lsl #21
and r5, r5, r7
mov r7, #1
orr r5, r5, r7, lsl #21
str r5, [r10, #0x08]
@ pin 47 output (activity LED on Pi board)
ldr r5, [r10, #0x10]
mov r7, #7
mvn r7, r7, lsl #21
and r5, r5, r7
mov r7, #1
orr r5, r5, r7, lsl #21
str r5, [r10, #0x10]
@mov r4, #1
@lsl r4, r4, #(47-32)
@str r4, [r10, #0x2c]
@mov r4, #1
@lsl r4, r4, #(27)
@str r4, [r10, #0x1c]
#endif
_dsb(r4)
.gpio_setup.done:
b .fastreloc_copy
@b .slowreloc_copy
@ --------------------------------------------------------------------------------------------------
@ SECTION: TAIL
@ --------------------------------------------------------------------------------------------------
@
@ DATA POOL
@
loc.gpio_base: .word 0x20200000
@
@ END OF STUB
@
__symbol_relocation_stub_end:
nop
|
max-cura/cs240lx-riscv-lab | 1,535 | staff/okboot/extern/boot.S | @ vim:ft=arm
@
@ FILE extern/boot.S
@ DESC Generic system entry point
@
#ifndef CUSTOM_STACK
.extern __symbol_stack_end__
#define STACK_HIGH __symbol_stack_init__
#elif !defined(STACK_HIGH)
#error "CUSTOM_STACK is defined but STACK_HIGH is not"
#endif
#ifndef CUSTOM_SYMBOLS
#define EXTERN_KERNEL_FN __symbol_kstart
#define EXTERN_REBOOT_FN __symbol_kreboot
#elif !defined(EXTERN_KERNEL_FN) || !defined(EXTERN_REBOOT_FN)
#error "CUSTOM_SYMBOLS is defined but one of EXTERN_KERNEL_FN or EXTERN_REBOOT_FN is not"
#endif
.extern EXTERN_KERNEL_FN
.extern EXTERN_REBOOT_FN
#define EXTERN_BSS_START __symbol_bss_start__
#define EXTERN_BSS_END __symbol_bss_end__
.extern EXTERN_BSS_START
.extern EXTERN_BSS_END
#define SUPER_MODE 0b10011
#define MODE_MASK 0b11111
@ Op1=0, Rd=reg, CRn=c7, CRm=c5, Op2=4 : Flush prefetch buffer
#define _prefetch_flush(reg) \
mov reg, #0; \
mcr p15, 0, reg, c7, c5, 4
.section ".text.boot"
.globl _start
_start:
@ enter supervisor mode
mrs r0, cpsr
and r0, r0, #(~MODE_MASK)
orr r0, r0, #SUPER_MODE
@ disable IRQs (A2-11)
orr r0, r0, #(1 << 7)
msr cpsr, r0
_prefetch_flush(r1)
@ zero bss
mov r0, #0
ldr r1, =EXTERN_BSS_START
ldr r2, =EXTERN_BSS_END
subs r2, r2, r1
bcc _start.zero_bss.L1
_start.zero_bss.L0:
strb r0, [r1], #1
subs r2, r2, #1
bne _start.zero_bss.L0
_start.zero_bss.L1:
ldr sp, =STACK_HIGH
mov fp, #0
bl EXTERN_KERNEL_FN
bl EXTERN_REBOOT_FN
.loop: b .loop |
mbennett-labs/KarlsenMiner | 5,802 | src/keccakf1600_x86-64-osx.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.p2align 5
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp L$oop
.p2align 5
L$oop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz L$oop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.globl _KeccakF1600
.p2align 5
_KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
addq $200,%rsp
.cfi_adjust_cfa_offset -200
popq %r15
.cfi_adjust_cfa_offset -8
.cfi_restore %r15
popq %r14
.cfi_adjust_cfa_offset -8
.cfi_restore %r14
popq %r13
.cfi_adjust_cfa_offset -8
.cfi_restore %r13
popq %r12
.cfi_adjust_cfa_offset -8
.cfi_restore %r12
popq %rbp
.cfi_adjust_cfa_offset -8
.cfi_restore %rbp
popq %rbx
.cfi_adjust_cfa_offset -8
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.p2align 8
.quad 0,0,0,0,0,0,0,0
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
mbennett-labs/KarlsenMiner | 6,073 | src/keccakf1600_x86-64.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.type __KeccakF1600,@function
.align 32
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.align 32
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz .Loop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.size __KeccakF1600,.-__KeccakF1600
.globl KeccakF1600
.type KeccakF1600,@function
.align 32
KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
addq $200,%rsp
.cfi_adjust_cfa_offset -200
popq %r15
.cfi_adjust_cfa_offset -8
.cfi_restore %r15
popq %r14
.cfi_adjust_cfa_offset -8
.cfi_restore %r14
popq %r13
.cfi_adjust_cfa_offset -8
.cfi_restore %r13
popq %r12
.cfi_adjust_cfa_offset -8
.cfi_restore %r12
popq %rbp
.cfi_adjust_cfa_offset -8
.cfi_restore %rbp
popq %rbx
.cfi_adjust_cfa_offset -8
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.size KeccakF1600,.-KeccakF1600
.align 256
.quad 0,0,0,0,0,0,0,0
.type iotas,@object
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.size iotas,.-iotas
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.section .note.gnu.property,"a",@note
.long 4,2f-1f,5
.byte 0x47,0x4E,0x55,0
1: .long 0xc0000002,4,3
.align 8
2:
|
mcwall/feos | 1,195 | src/asm/boot.S | .option norvc
.section .data
.section .text.init
.global _start
_start:
# Any hardware threads (hart) that are not bootstrapping
# need to wait for an IPI
csrr t0, mhartid
bnez t0, 3f
# SATP should be zero, but let's make sure
csrw satp, zero
.option push
.option norelax
la gp, _global_pointer
.option pop
# The BSS section is expected to be zero
la a0, _bss_start
la a1, _bss_end
bgeu a0, a1, 2f
1:
sd zero, (a0)
addi a0, a0, 8
bltu a0, a1, 1b
2:
# Control registers, set the stack, mstatus, mepc,
# and mtvec to return to the main function.
# li t5, 0xffff;
# csrw medeleg, t5
# csrw mideleg, t5
la sp, _stack
# We use mret here so that the mstatus register
# is properly updated.
li t0, (0b11 << 11) | (1 << 7) | (1 << 3)
csrw mstatus, t0
la t1, kmain
csrw mepc, t1
la t2, asm_trap_vector
csrw mtvec, t2
li t3, (1 << 3) | (1 << 7) | (1 << 11)
csrw mie, t3
la ra, 4f
mret
3:
# Parked harts go here. We need to set these
# to only awaken if it receives a software interrupt,
# which we're going to call the SIPI (Software Intra-Processor Interrupt).
# We only use these to run user-space programs, although this may
# change.
4:
wfi
j 4b
|
MDavid102/Preh_Estadia-2024 | 20,364 | Week3/Week3_Activity2_CAN-CMSIS-Lib-final/CAN_Final_Lib/Startup/startup_stm32f407vgtx.s | /**
******************************************************************************
* @file startup_stm32f407vgtx.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F407VGTx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F407VGTx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* PVD through EXTI line detection interrupt */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word 0 /* Reserved */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3 global interrupts */
.word CAN1_TX_IRQHandler /* CAN1 TX interrupts */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 interrupts */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 interrupts */
.word CAN1_SCE_IRQHandler /* CAN1 SCE interrupt */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word USART3_IRQHandler /* USART3 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break interrupt and TIM12 global interrupt */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update interrupt and TIM13 global interrupt */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation interrupts and TIM14 global interrupt */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word FSMC_IRQHandler /* FSMC global interrupt */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word UART4_IRQHandler /* UART4 global interrupt */
.word UART5_IRQHandler /* UART5 global interrupt */
.word TIM6_DAC_IRQHandler /* TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt */
.word TIM7_IRQHandler /* TIM7 global interrupt */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word ETH_IRQHandler /* Ethernet global interrupt */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */
.word CAN2_TX_IRQHandler /* CAN2 TX interrupts */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 interrupts */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 interrupts */
.word CAN2_SCE_IRQHandler /* CAN2 SCE interrupt */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word OTG_HS_EP1_OUT_IRQHandler /* USB On The Go HS End Point 1 Out global interrupt */
.word OTG_HS_EP1_IN_IRQHandler /* USB On The Go HS End Point 1 In global interrupt */
.word OTG_HS_WKUP_IRQHandler /* USB On The Go HS Wakeup through EXTI interrupt */
.word OTG_HS_IRQHandler /* USB On The Go HS global interrupt */
.word DCMI_IRQHandler /* DCMI global interrupt */
.word CRYP_IRQHandler /* CRYP crypto global interrupt */
.word HASH_RNG_IRQHandler /* Hash and Rng global interrupt */
.word FPU_IRQHandler /* FPU interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 20,364 | Week2/Week2_Activity4_CMSISLib/CMISISExercise/Startup/startup_stm32f407vgtx.s | /**
******************************************************************************
* @file startup_stm32f407vgtx.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F407VGTx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F407VGTx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* PVD through EXTI line detection interrupt */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word 0 /* Reserved */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3 global interrupts */
.word CAN1_TX_IRQHandler /* CAN1 TX interrupts */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 interrupts */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 interrupts */
.word CAN1_SCE_IRQHandler /* CAN1 SCE interrupt */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word USART3_IRQHandler /* USART3 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break interrupt and TIM12 global interrupt */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update interrupt and TIM13 global interrupt */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation interrupts and TIM14 global interrupt */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word FSMC_IRQHandler /* FSMC global interrupt */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word UART4_IRQHandler /* UART4 global interrupt */
.word UART5_IRQHandler /* UART5 global interrupt */
.word TIM6_DAC_IRQHandler /* TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt */
.word TIM7_IRQHandler /* TIM7 global interrupt */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word ETH_IRQHandler /* Ethernet global interrupt */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */
.word CAN2_TX_IRQHandler /* CAN2 TX interrupts */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 interrupts */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 interrupts */
.word CAN2_SCE_IRQHandler /* CAN2 SCE interrupt */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word OTG_HS_EP1_OUT_IRQHandler /* USB On The Go HS End Point 1 Out global interrupt */
.word OTG_HS_EP1_IN_IRQHandler /* USB On The Go HS End Point 1 In global interrupt */
.word OTG_HS_WKUP_IRQHandler /* USB On The Go HS Wakeup through EXTI interrupt */
.word OTG_HS_IRQHandler /* USB On The Go HS global interrupt */
.word DCMI_IRQHandler /* DCMI global interrupt */
.word CRYP_IRQHandler /* CRYP crypto global interrupt */
.word HASH_RNG_IRQHandler /* Hash and Rng global interrupt */
.word FPU_IRQHandler /* FPU interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week2/Week2_Activity5_LibraryCreationExercise/ExerciseLibrary/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week2/Week2_Activity1_Led/BlinkLED_Register and document/Blink_led2/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week1/Questions, Exercise, Glossary, MCU documentation/BlinkLED_Register and document/Blink_led2/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week1/Questions, Exercise, Glossary, MCU documentation/BlinkLed_Bitwise and document/Blink_led/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 20,364 | Week3/Week3_Activity2_CAN-CMSIS-Lib-final/CAN_Final_Lib/Startup/startup_stm32f407vgtx.s | /**
******************************************************************************
* @file startup_stm32f407vgtx.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F407VGTx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F407VGTx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* PVD through EXTI line detection interrupt */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word 0 /* Reserved */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3 global interrupts */
.word CAN1_TX_IRQHandler /* CAN1 TX interrupts */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 interrupts */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 interrupts */
.word CAN1_SCE_IRQHandler /* CAN1 SCE interrupt */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word USART3_IRQHandler /* USART3 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break interrupt and TIM12 global interrupt */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update interrupt and TIM13 global interrupt */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation interrupts and TIM14 global interrupt */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word FSMC_IRQHandler /* FSMC global interrupt */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word UART4_IRQHandler /* UART4 global interrupt */
.word UART5_IRQHandler /* UART5 global interrupt */
.word TIM6_DAC_IRQHandler /* TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt */
.word TIM7_IRQHandler /* TIM7 global interrupt */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word ETH_IRQHandler /* Ethernet global interrupt */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */
.word CAN2_TX_IRQHandler /* CAN2 TX interrupts */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 interrupts */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 interrupts */
.word CAN2_SCE_IRQHandler /* CAN2 SCE interrupt */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word OTG_HS_EP1_OUT_IRQHandler /* USB On The Go HS End Point 1 Out global interrupt */
.word OTG_HS_EP1_IN_IRQHandler /* USB On The Go HS End Point 1 In global interrupt */
.word OTG_HS_WKUP_IRQHandler /* USB On The Go HS Wakeup through EXTI interrupt */
.word OTG_HS_IRQHandler /* USB On The Go HS global interrupt */
.word DCMI_IRQHandler /* DCMI global interrupt */
.word CRYP_IRQHandler /* CRYP crypto global interrupt */
.word HASH_RNG_IRQHandler /* Hash and Rng global interrupt */
.word FPU_IRQHandler /* FPU interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 20,364 | Week2/Week2_Activity4_CMSISLib/CMISISExercise/Startup/startup_stm32f407vgtx.s | /**
******************************************************************************
* @file startup_stm32f407vgtx.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F407VGTx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F407VGTx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* PVD through EXTI line detection interrupt */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word 0 /* Reserved */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3 global interrupts */
.word CAN1_TX_IRQHandler /* CAN1 TX interrupts */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 interrupts */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 interrupts */
.word CAN1_SCE_IRQHandler /* CAN1 SCE interrupt */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word USART3_IRQHandler /* USART3 global interrupt */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break interrupt and TIM12 global interrupt */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update interrupt and TIM13 global interrupt */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation interrupts and TIM14 global interrupt */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare interrupt */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word FSMC_IRQHandler /* FSMC global interrupt */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word UART4_IRQHandler /* UART4 global interrupt */
.word UART5_IRQHandler /* UART5 global interrupt */
.word TIM6_DAC_IRQHandler /* TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt */
.word TIM7_IRQHandler /* TIM7 global interrupt */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word ETH_IRQHandler /* Ethernet global interrupt */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line interrupt */
.word CAN2_TX_IRQHandler /* CAN2 TX interrupts */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 interrupts */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 interrupts */
.word CAN2_SCE_IRQHandler /* CAN2 SCE interrupt */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word OTG_HS_EP1_OUT_IRQHandler /* USB On The Go HS End Point 1 Out global interrupt */
.word OTG_HS_EP1_IN_IRQHandler /* USB On The Go HS End Point 1 In global interrupt */
.word OTG_HS_WKUP_IRQHandler /* USB On The Go HS Wakeup through EXTI interrupt */
.word OTG_HS_IRQHandler /* USB On The Go HS global interrupt */
.word DCMI_IRQHandler /* DCMI global interrupt */
.word CRYP_IRQHandler /* CRYP crypto global interrupt */
.word HASH_RNG_IRQHandler /* Hash and Rng global interrupt */
.word FPU_IRQHandler /* FPU interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week2/Week2_Activity5_LibraryCreationExercise/ExerciseLibrary/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week2/Week2_Activity1_Led/BlinkLED_Register and document/Blink_led2/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week1/Questions, Exercise, Glossary, MCU documentation/BlinkLED_Register and document/Blink_led2/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
MDavid102/Preh_Estadia-2024 | 18,902 | Week1/Questions, Exercise, Glossary, MCU documentation/BlinkLed_Bitwise and document/Blink_led/Startup/startup_stm32f411ceux.s | /**
******************************************************************************
* @file startup_stm32f411ceux.s
* @author Auto-generated by STM32CubeIDE
* @brief STM32F411CEUx device vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
******************************************************************************
* @attention
*
* Copyright (c) 2024 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32F411CEUx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window Watchdog interrupt */
.word PVD_IRQHandler /* EXTI Line 16 interrupt / PVD through EXTI */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamp interrupts through */
.word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt through the EXTI line */
.word FLASH_IRQHandler /* FLASH global interrupt */
.word RCC_IRQHandler /* RCC global interrupt */
.word EXTI0_IRQHandler /* EXTI Line0 interrupt */
.word EXTI1_IRQHandler /* EXTI Line1 interrupt */
.word EXTI2_IRQHandler /* EXTI Line2 interrupt */
.word EXTI3_IRQHandler /* EXTI Line3 interrupt */
.word EXTI4_IRQHandler /* EXTI Line4 interrupt */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream0 global interrupt */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream1 global interrupt */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream2 global interrupt */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream3 global interrupt */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream4 global interrupt */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream5 global interrupt */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream6 global interrupt */
.word ADC_IRQHandler /* ADC1 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break interrupt and TIM9 global interrupt */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update interrupt and TIM10 global interrupt */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation interrupts and TIM11 global interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */
.word TIM2_IRQHandler /* TIM2 global interrupt */
.word TIM3_IRQHandler /* TIM3 global interrupt */
.word TIM4_IRQHandler /* TIM4 global interrupt */
.word I2C1_EV_IRQHandler /* I2C1 event interrupt */
.word I2C1_ER_IRQHandler /* I2C1 error interrupt */
.word I2C2_EV_IRQHandler /* I2C2 event interrupt */
.word I2C2_ER_IRQHandler /* I2C2 error interrupt */
.word SPI1_IRQHandler /* SPI1 global interrupt */
.word SPI2_IRQHandler /* SPI2 global interrupt */
.word USART1_IRQHandler /* USART1 global interrupt */
.word USART2_IRQHandler /* USART2 global interrupt */
.word 0 /* Reserved */
.word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */
.word RTC_Alarm_IRQHandler /* RTC Alarms (A and B) through EXTI line interrupt */
.word OTG_FS_WKUP_IRQHandler /* USB On-The-Go FS Wakeup through EXTI line interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 global interrupt */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO global interrupt */
.word TIM5_IRQHandler /* TIM5 global interrupt */
.word SPI3_IRQHandler /* SPI3 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream0 global interrupt */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream1 global interrupt */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream2 global interrupt */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream3 global interrupt */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word OTG_FS_IRQHandler /* USB On The Go FS global interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream5 global interrupt */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream6 global interrupt */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream7 global interrupt */
.word USART6_IRQHandler /* USART6 global interrupt */
.word I2C3_EV_IRQHandler /* I2C3 event interrupt */
.word I2C3_ER_IRQHandler /* I2C3 error interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI 4 global interrupt */
.word SPI5_IRQHandler /* SPI 5 global interrupt */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SystemInit
/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/
|
meizeddin/PQ_Secure_X3DH | 48,276 | pswoosh-master/rust/ref0/src/arithmetic/fq.s | .att_syntax
.text
.p2align 5
.globl _fp_fromM
.globl fp_fromM
.globl _fp_toM
.globl fp_toM
.globl _fp_inv
.globl fp_inv
.globl _fp_expm_noct
.globl fp_expm_noct
.globl _fp_sqr
.globl fp_sqr
.globl _fp_mul
.globl fp_mul
.globl _fp_sub
.globl fp_sub
.globl _fp_add
.globl fp_add
.globl _bn_sqrn
.globl bn_sqrn
.globl _bn_muln
.globl bn_muln
.globl _bn_subn
.globl bn_subn
.globl _bn_addn
.globl bn_addn
.globl _bn_set0
.globl bn_set0
.globl _bn_copy
.globl bn_copy
.globl _bn_test0
.globl bn_test0
.globl _bn_eq
.globl bn_eq
_fp_fromM:
fp_fromM:
movq %rsp, %rax
leaq -72(%rsp), %rsp
andq $-8, %rsp
movq %rax, 64(%rsp)
movq %rbx, 32(%rsp)
movq %rbp, 40(%rsp)
movq %r12, 48(%rsp)
movq %r13, 56(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq -96(%rsp), %rsp
leaq Lfp_fromM$1(%rip), %r9
jmp L_fp_fromM$1
Lfp_fromM$1:
leaq 96(%rsp), %rsp
movq (%rsi), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
movq %rax, 8(%rdi)
movq 16(%rsi), %rax
movq %rax, 16(%rdi)
movq 24(%rsi), %rax
movq %rax, 24(%rdi)
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
movq 48(%rsp), %r12
movq 56(%rsp), %r13
movq 64(%rsp), %rsp
ret
_fp_toM:
fp_toM:
movq %rsp, %rax
leaq -80(%rsp), %rsp
andq $-8, %rsp
movq %rax, 72(%rsp)
movq %rbx, 32(%rsp)
movq %rbp, 40(%rsp)
movq %r12, 48(%rsp)
movq %r13, 56(%rsp)
movq %r14, 64(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq Lfp_toM$1(%rip), %r14
jmp L_fp_toM$1
Lfp_toM$1:
movq (%r13), %rax
movq %rax, (%rdi)
movq 8(%r13), %rax
movq %rax, 8(%rdi)
movq 16(%r13), %rax
movq %rax, 16(%rdi)
movq 24(%r13), %rax
movq %rax, 24(%rdi)
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
movq 48(%rsp), %r12
movq 56(%rsp), %r13
movq 64(%rsp), %r14
movq 72(%rsp), %rsp
ret
_fp_inv:
fp_inv:
movq %rsp, %rax
leaq -120(%rsp), %rsp
andq $-8, %rsp
movq %rax, 112(%rsp)
movq %rbx, 72(%rsp)
movq %rbp, 80(%rsp)
movq %r12, 88(%rsp)
movq %r13, 96(%rsp)
movq %r14, 104(%rsp)
movq %rdi, (%rsp)
movq (%rsi), %rax
movq %rax, 8(%rsp)
movq 8(%rsi), %rax
movq %rax, 16(%rsp)
movq 16(%rsi), %rax
movq %rax, 24(%rsp)
movq 24(%rsi), %rax
movq %rax, 32(%rsp)
leaq 8(%rsp), %rax
leaq 40(%rsp), %rdx
leaq glob_data + 72(%rip), %rcx
leaq -64(%rsp), %rsp
leaq Lfp_inv$1(%rip), %rsi
movq %rsi, 56(%rsp)
jmp L_fp_exp$1
Lfp_inv$1:
leaq 64(%rsp), %rsp
movq (%rsp), %rax
movq (%rdx), %rcx
movq %rcx, (%rax)
movq 8(%rdx), %rcx
movq %rcx, 8(%rax)
movq 16(%rdx), %rcx
movq %rcx, 16(%rax)
movq 24(%rdx), %rcx
movq %rcx, 24(%rax)
movq 72(%rsp), %rbx
movq 80(%rsp), %rbp
movq 88(%rsp), %r12
movq 96(%rsp), %r13
movq 104(%rsp), %r14
movq 112(%rsp), %rsp
ret
_fp_expm_noct:
fp_expm_noct:
movq %rsp, %rax
leaq -152(%rsp), %rsp
andq $-8, %rsp
movq %rax, 144(%rsp)
movq %rbx, 104(%rsp)
movq %rbp, 112(%rsp)
movq %r12, 120(%rsp)
movq %r13, 128(%rsp)
movq %r14, 136(%rsp)
movq %rdi, (%rsp)
movq (%rsi), %rax
movq %rax, 8(%rsp)
movq 8(%rsi), %rax
movq %rax, 16(%rsp)
movq 16(%rsi), %rax
movq %rax, 24(%rsp)
movq 24(%rsi), %rax
movq %rax, 32(%rsp)
leaq 8(%rsp), %rax
movq (%rdx), %rcx
movq %rcx, 40(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 56(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 64(%rsp)
leaq 40(%rsp), %rcx
leaq 72(%rsp), %rdx
leaq -64(%rsp), %rsp
leaq Lfp_expm_noct$1(%rip), %rsi
movq %rsi, 56(%rsp)
jmp L_fp_exp$1
Lfp_expm_noct$1:
leaq 64(%rsp), %rsp
movq (%rsp), %rax
movq (%rdx), %rcx
movq %rcx, (%rax)
movq 8(%rdx), %rcx
movq %rcx, 8(%rax)
movq 16(%rdx), %rcx
movq %rcx, 16(%rax)
movq 24(%rdx), %rcx
movq %rcx, 24(%rax)
movq 104(%rsp), %rbx
movq 112(%rsp), %rbp
movq 120(%rsp), %r12
movq 128(%rsp), %r13
movq 136(%rsp), %r14
movq 144(%rsp), %rsp
ret
_fp_sqr:
fp_sqr:
movq %rsp, %rax
leaq -104(%rsp), %rsp
andq $-8, %rsp
movq %rax, 96(%rsp)
movq %rbx, 64(%rsp)
movq %rbp, 72(%rsp)
movq %r12, 80(%rsp)
movq %r13, 88(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %r8
leaq 32(%rsp), %rax
leaq -96(%rsp), %rsp
leaq Lfp_sqr$1(%rip), %rbp
jmp L_fp_sqr$1
Lfp_sqr$1:
leaq 96(%rsp), %rsp
movq (%r12), %rax
movq %rax, (%rdi)
movq 8(%r12), %rax
movq %rax, 8(%rdi)
movq 16(%r12), %rax
movq %rax, 16(%rdi)
movq 24(%r12), %rax
movq %rax, 24(%rdi)
movq 64(%rsp), %rbx
movq 72(%rsp), %rbp
movq 80(%rsp), %r12
movq 88(%rsp), %r13
movq 96(%rsp), %rsp
ret
_fp_mul:
fp_mul:
movq %rsp, %rax
leaq -136(%rsp), %rsp
andq $-8, %rsp
movq %rax, 128(%rsp)
movq %rbx, 96(%rsp)
movq %rbp, 104(%rsp)
movq %r12, 112(%rsp)
movq %r13, 120(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %r10
movq (%rdx), %rax
movq %rax, 32(%rsp)
movq 8(%rdx), %rax
movq %rax, 40(%rsp)
movq 16(%rdx), %rax
movq %rax, 48(%rsp)
movq 24(%rdx), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %r8
leaq 64(%rsp), %rax
leaq -96(%rsp), %rsp
leaq Lfp_mul$1(%rip), %rbp
jmp L_fp_mul$1
Lfp_mul$1:
leaq 96(%rsp), %rsp
movq (%r12), %rax
movq %rax, (%rdi)
movq 8(%r12), %rax
movq %rax, 8(%rdi)
movq 16(%r12), %rax
movq %rax, 16(%rdi)
movq 24(%r12), %rax
movq %rax, 24(%rdi)
movq 96(%rsp), %rbx
movq 104(%rsp), %rbp
movq 112(%rsp), %r12
movq 120(%rsp), %r13
movq 128(%rsp), %rsp
ret
_fp_sub:
fp_sub:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rdx
leaq -32(%rsp), %rsp
leaq Lfp_sub$1(%rip), %rcx
jmp L_fp_sub$1
Lfp_sub$1:
leaq 32(%rsp), %rsp
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_fp_add:
fp_add:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rdx
leaq -32(%rsp), %rsp
leaq Lfp_add$1(%rip), %rcx
jmp L_fp_add$1
Lfp_add$1:
leaq 32(%rsp), %rsp
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_bn_sqrn:
bn_sqrn:
movq %rsp, %rax
leaq -104(%rsp), %rsp
andq $-8, %rsp
movq %rax, 96(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rsi
leaq 32(%rsp), %r8
movq (%rsi), %rax
mulq %rax
movq %rax, (%r8)
movq %rdx, %r9
xorq %r10, %r10
xorq %rcx, %rcx
movq (%rsi), %rax
movq 8(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r9
adcq %rdx, %r10
adcq %r11, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 8(%r8)
movq (%rsi), %rax
movq 16(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rcx
adcq %r11, %r9
movq 8(%rsi), %rax
mulq %rax
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %r9
movq %r10, %rax
xorq %r10, %r10
movq %rax, 16(%r8)
movq (%rsi), %rax
movq 24(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rcx
adcq %rdx, %r9
adcq %r11, %r10
movq 8(%rsi), %rax
movq 16(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rcx
adcq %rdx, %r9
adcq %r11, %r10
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%r8)
movq 8(%rsi), %rax
movq 24(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r9
adcq %rdx, %r10
adcq %r11, %rcx
movq 16(%rsi), %rax
mulq %rax
addq %rax, %r9
adcq %rdx, %r10
adcq $0, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 32(%r8)
movq 16(%rsi), %rax
movq 24(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rcx
adcq %r11, %r9
xorq %r11, %r11
movq %r10, 40(%r8)
movq 24(%rsi), %rax
mulq %rax
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %r11
xorq %rax, %rax
movq %rcx, 48(%r8)
movq %r9, 56(%r8)
movq (%r8), %rax
movq %rax, (%rdi)
movq 8(%r8), %rax
movq %rax, 8(%rdi)
movq 16(%r8), %rax
movq %rax, 16(%rdi)
movq 24(%r8), %rax
movq %rax, 24(%rdi)
movq 32(%r8), %rax
movq %rax, 32(%rdi)
movq 40(%r8), %rax
movq %rax, 40(%rdi)
movq 48(%r8), %rax
movq %rax, 48(%rdi)
movq 56(%r8), %rax
movq %rax, 56(%rdi)
movq 96(%rsp), %rsp
ret
_bn_muln:
bn_muln:
movq %rsp, %rax
leaq -144(%rsp), %rsp
andq $-8, %rsp
movq %rax, 136(%rsp)
movq %rbx, 128(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %r8
movq (%rdx), %rax
movq %rax, 32(%rsp)
movq 8(%rdx), %rax
movq %rax, 40(%rsp)
movq 16(%rdx), %rax
movq %rax, 48(%rsp)
movq 24(%rdx), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %r9
leaq 64(%rsp), %r11
movq (%r8), %rax
mulq (%r9)
movq %rax, (%r11)
movq %rdx, %r10
xorq %rcx, %rcx
xorq %rsi, %rsi
movq (%r8), %rax
mulq 8(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq 8(%r8), %rax
mulq (%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 8(%r11)
movq (%r8), %rax
mulq 16(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq 8(%r8), %rax
mulq 8(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq 16(%r8), %rax
mulq (%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 16(%r11)
movq (%r8), %rax
mulq 24(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq 8(%r8), %rax
mulq 16(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq 16(%r8), %rax
mulq 8(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq 24(%r8), %rax
mulq (%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 24(%r11)
movq 8(%r8), %rax
mulq 24(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq 16(%r8), %rax
mulq 16(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq 24(%r8), %rax
mulq 8(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 32(%r11)
movq 16(%r8), %rax
mulq 24(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq 24(%r8), %rax
mulq 16(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
xorq %rbx, %rbx
movq %rcx, 40(%r11)
movq 24(%r8), %rax
mulq 24(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rbx
xorq %rax, %rax
movq %rsi, 48(%r11)
movq %r10, 56(%r11)
movq (%r11), %rax
movq %rax, (%rdi)
movq 8(%r11), %rax
movq %rax, 8(%rdi)
movq 16(%r11), %rax
movq %rax, 16(%rdi)
movq 24(%r11), %rax
movq %rax, 24(%rdi)
movq 32(%r11), %rax
movq %rax, 32(%rdi)
movq 40(%r11), %rax
movq %rax, 40(%rdi)
movq 48(%r11), %rax
movq %rax, 48(%rdi)
movq 56(%r11), %rax
movq %rax, 56(%rdi)
movq 128(%rsp), %rbx
movq 136(%rsp), %rsp
ret
_bn_subn:
bn_subn:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rcx
movq (%rcx), %rdx
subq %rdx, (%rax)
movq 8(%rcx), %rdx
sbbq %rdx, 8(%rax)
movq 16(%rcx), %rdx
sbbq %rdx, 16(%rax)
movq 24(%rcx), %rcx
sbbq %rcx, 24(%rax)
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_bn_addn:
bn_addn:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_bn_set0:
bn_set0:
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
movq $0, 24(%rdi)
ret
_bn_copy:
bn_copy:
movq (%rsi), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
movq %rax, 8(%rdi)
movq 16(%rsi), %rax
movq %rax, 16(%rdi)
movq 24(%rsi), %rax
movq %rax, 24(%rdi)
ret
_bn_test0:
bn_test0:
movq %rsp, %r10
leaq -32(%rsp), %rsp
andq $-8, %rsp
movq (%rdi), %rax
movq %rax, (%rsp)
movq 8(%rdi), %rax
movq %rax, 8(%rsp)
movq 16(%rdi), %rax
movq %rax, 16(%rsp)
movq 24(%rdi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq $0, %rcx
movq $1, %rdx
movq (%rax), %rsi
orq 8(%rax), %rsi
orq 16(%rax), %rsi
orq 24(%rax), %rsi
andq %rsi, %rsi
cmove %rdx, %rcx
movq %rcx, %rax
movq %r10, %rsp
ret
_bn_eq:
bn_eq:
movq %rsp, %r11
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rdi), %rax
movq %rax, (%rsp)
movq 8(%rdi), %rax
movq %rax, 8(%rsp)
movq 16(%rdi), %rax
movq %rax, 16(%rsp)
movq 24(%rdi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rsi), %rcx
movq %rcx, 32(%rsp)
movq 8(%rsi), %rcx
movq %rcx, 40(%rsp)
movq 16(%rsi), %rcx
movq %rcx, 48(%rsp)
movq 24(%rsi), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rcx
leaq Lbn_eq$1(%rip), %r9
jmp L_bn_eq$1
Lbn_eq$1:
movq %rdx, %rax
movq %r11, %rsp
ret
L_fp_toM$1:
leaq glob_data + 0(%rip), %r9
leaq -96(%rsp), %rsp
leaq L_fp_toM$2(%rip), %rbp
jmp L_fp_mulU$1
L_fp_toM$2:
leaq 96(%rsp), %rsp
jmp *%r14
L_fp_fromM$1:
movq %rax, %rsi
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq (%rsi), %rax
movq %rax, 32(%rsp)
movq 8(%rsi), %rax
movq %rax, 40(%rsp)
movq 16(%rsi), %rax
movq %rax, 48(%rsp)
movq 24(%rsi), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %r10
xorq %r12, %r12
movq glob_data + 64(%rip), %r11
movq glob_data + 136(%rip), %rbp
xorq %r13, %r13
xorq %rcx, %rcx
xorq %r8, %r8
movq (%r10), %rax
addq %rax, %r13
adcq %r12, %rcx
adcq $0, %r8
movq %r13, %rax
mulq %r11
movq %rax, (%rsi)
mulq %rbp
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
leaq glob_data + 136(%rip), %rdx
movq (%rsi), %rax
mulq 8(%rdx)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 8(%r10), %rax
addq %rax, %rcx
adcq %r12, %r8
adcq $0, %r13
movq %rcx, %rax
mulq %r11
movq %rax, 8(%rsi)
mulq %rbp
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
leaq glob_data + 136(%rip), %rbx
movq (%rsi), %rax
mulq 16(%rbx)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 8(%rsi), %rax
mulq 8(%rbx)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 16(%r10), %rax
addq %rax, %r8
adcq %r12, %r13
adcq $0, %rcx
movq %r8, %rax
mulq %r11
movq %rax, 16(%rsi)
mulq %rbp
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
leaq glob_data + 136(%rip), %rbx
movq (%rsi), %rax
mulq 24(%rbx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 8(%rsi), %rax
mulq 16(%rbx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 16(%rsi), %rax
mulq 8(%rbx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 24(%r10), %rax
addq %rax, %r13
adcq %r12, %rcx
adcq $0, %r8
movq %r13, %rax
mulq %r11
movq %rax, 24(%rsi)
mulq %rbp
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
leaq glob_data + 136(%rip), %r11
movq 8(%rsi), %rax
mulq 24(%r11)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 16(%rsi), %rax
mulq 16(%r11)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 24(%rsi), %rax
mulq 8(%r11)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 32(%r10), %rax
addq %rax, %rcx
adcq %r12, %r8
adcq $0, %r13
movq %rcx, (%rsi)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %r11
movq 16(%rsi), %rax
mulq 24(%r11)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 24(%rsi), %rax
mulq 16(%r11)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 40(%r10), %rax
addq %rax, %r8
adcq %r12, %r13
adcq $0, %rcx
movq %r8, 8(%rsi)
xorq %r8, %r8
leaq glob_data + 136(%rip), %rdx
movq 24(%rsi), %rax
mulq 24(%rdx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 48(%r10), %rax
addq %rax, %r13
adcq %r12, %rcx
adcq $0, %r8
movq %r13, 16(%rsi)
xorq %rax, %rax
addq 56(%r10), %rcx
movq %rcx, 24(%rsi)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%rsi), %rcx
cmovb (%rax), %rcx
movq %rcx, (%rsi)
movq 8(%rsi), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%rsi)
movq 16(%rsi), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%rsi)
movq 24(%rsi), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%rsi)
jmp *%r9
L_fp_exp$1:
leaq 24(%rsp), %rsi
leaq glob_data + 32(%rip), %rdi
movq (%rax), %r8
movq %r8, (%rsi)
movq 8(%rax), %r8
movq %r8, 8(%rsi)
movq 16(%rax), %r8
movq %r8, 16(%rsi)
movq 24(%rax), %rax
movq %rax, 24(%rsi)
movq (%rdi), %rax
movq %rax, (%rdx)
movq 8(%rdi), %rax
movq %rax, 8(%rdx)
movq 16(%rdi), %rax
movq %rax, 16(%rdx)
movq 24(%rdi), %rax
movq %rax, 24(%rdx)
movq %rcx, (%rsp)
movq %rdx, 8(%rsp)
movq (%rsp), %rax
movq (%rax), %r14
movq $64, %rax
jmp L_fp_exp$17
L_fp_exp$18:
movq %rax, 16(%rsp)
shrq $1, %r14
jnb L_fp_exp$20
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$21(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$21:
leaq 96(%rsp), %rsp
L_fp_exp$20:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$19(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$19:
leaq 104(%rsp), %rsp
movq 16(%rsp), %rax
addq $-1, %rax
L_fp_exp$17:
cmpq $0, %rax
jne L_fp_exp$18
movq (%rsp), %rax
movq 8(%rax), %r14
movq $64, %rax
jmp L_fp_exp$12
L_fp_exp$13:
movq %rax, 16(%rsp)
shrq $1, %r14
jnb L_fp_exp$15
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$16(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$16:
leaq 96(%rsp), %rsp
L_fp_exp$15:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$14(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$14:
leaq 104(%rsp), %rsp
movq 16(%rsp), %rax
addq $-1, %rax
L_fp_exp$12:
cmpq $0, %rax
jne L_fp_exp$13
movq (%rsp), %rax
movq 16(%rax), %r14
movq $64, %rax
jmp L_fp_exp$7
L_fp_exp$8:
movq %rax, 16(%rsp)
shrq $1, %r14
jnb L_fp_exp$10
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$11(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$11:
leaq 96(%rsp), %rsp
L_fp_exp$10:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$9(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$9:
leaq 104(%rsp), %rsp
movq 16(%rsp), %rax
addq $-1, %rax
L_fp_exp$7:
cmpq $0, %rax
jne L_fp_exp$8
movq (%rsp), %rax
movq 24(%rax), %r14
movq $64, %rax
jmp L_fp_exp$2
L_fp_exp$3:
movq %rax, (%rsp)
shrq $1, %r14
jnb L_fp_exp$5
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$6(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$6:
leaq 96(%rsp), %rsp
L_fp_exp$5:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$4(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$4:
leaq 104(%rsp), %rsp
movq (%rsp), %rax
addq $-1, %rax
L_fp_exp$2:
cmpq $0, %rax
jne L_fp_exp$3
movq 8(%rsp), %rdx
jmp *56(%rsp)
L_fp_sqrU$1:
movq %rax, %r11
leaq 32(%rsp), %rbp
movq (%r11), %rax
mulq %rax
movq %rax, (%rbp)
movq %rdx, %rsi
xorq %rdi, %rdi
xorq %rcx, %rcx
movq (%r11), %rax
movq 8(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r8, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 8(%rbp)
movq (%r11), %rax
movq 16(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rdi
adcq %rdx, %rcx
adcq %r8, %rsi
movq 8(%r11), %rax
mulq %rax
addq %rax, %rdi
adcq %rdx, %rcx
adcq $0, %rsi
movq %rdi, %rax
xorq %rdi, %rdi
movq %rax, 16(%rbp)
movq (%r11), %rax
movq 24(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r8, %rdi
movq 8(%r11), %rax
movq 16(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r8, %rdi
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%rbp)
movq 8(%r11), %rax
movq 24(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r8, %rcx
movq 16(%r11), %rax
mulq %rax
addq %rax, %rsi
adcq %rdx, %rdi
adcq $0, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 32(%rbp)
movq 16(%r11), %rax
movq 24(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rdi
adcq %rdx, %rcx
adcq %r8, %rsi
xorq %r8, %r8
movq %rdi, 40(%rbp)
movq 24(%r11), %rax
mulq %rax
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r8
xorq %rax, %rax
movq %rcx, 48(%rbp)
movq %rsi, 56(%rbp)
xorq %r10, %r10
movq glob_data + 64(%rip), %rdi
movq glob_data + 136(%rip), %r8
xorq %r9, %r9
xorq %rsi, %rsi
xorq %rcx, %rcx
movq (%rbp), %rax
addq %rax, %r9
adcq %r10, %rsi
adcq $0, %rcx
movq %r9, %rax
mulq %rdi
movq %rax, (%r11)
mulq %r8
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
leaq glob_data + 136(%rip), %rdx
movq (%r11), %rax
mulq 8(%rdx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 8(%rbp), %rax
addq %rax, %rsi
adcq %r10, %rcx
adcq $0, %r9
movq %rsi, %rax
mulq %rdi
movq %rax, 8(%r11)
mulq %r8
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r11), %rax
mulq 16(%rbx)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 8(%r11), %rax
mulq 8(%rbx)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 16(%rbp), %rax
addq %rax, %rcx
adcq %r10, %r9
adcq $0, %rsi
movq %rcx, %rax
mulq %rdi
movq %rax, 16(%r11)
mulq %r8
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
leaq glob_data + 136(%rip), %rbx
movq (%r11), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 8(%r11), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r11), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%rbp), %rax
addq %rax, %r9
adcq %r10, %rsi
adcq $0, %rcx
movq %r9, %rax
mulq %rdi
movq %rax, 24(%r11)
mulq %r8
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
leaq glob_data + 136(%rip), %rdi
movq 8(%r11), %rax
mulq 24(%rdi)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 16(%r11), %rax
mulq 16(%rdi)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 24(%r11), %rax
mulq 8(%rdi)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 32(%rbp), %rax
addq %rax, %rsi
adcq %r10, %rcx
adcq $0, %r9
movq %rsi, (%r11)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdi
movq 16(%r11), %rax
mulq 24(%rdi)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 24(%r11), %rax
mulq 16(%rdi)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 40(%rbp), %rax
addq %rax, %rcx
adcq %r10, %r9
adcq $0, %rsi
movq %rcx, 8(%r11)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %rdx
movq 24(%r11), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 48(%rbp), %rax
addq %rax, %r9
adcq %r10, %rsi
adcq $0, %rcx
movq %r9, 16(%r11)
xorq %rax, %rax
addq 56(%rbp), %rsi
movq %rsi, 24(%r11)
movq (%r11), %rax
movq %rax, (%rsp)
movq 8(%r11), %rax
movq %rax, 8(%rsp)
movq 16(%r11), %rax
movq %rax, 16(%rsp)
movq 24(%r11), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r11), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r11)
movq 8(%r11), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r11)
movq 16(%r11), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r11)
movq 24(%r11), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r11)
jmp *96(%rsp)
L_fp_sqr$1:
movq %rax, %r12
leaq 32(%rsp), %r13
movq (%r8), %rax
mulq %rax
movq %rax, (%r13)
movq %rdx, %r9
xorq %rcx, %rcx
xorq %rsi, %rsi
movq (%r8), %rax
movq 8(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %r9
adcq %rdx, %rcx
adcq %r10, %rsi
movq %r9, %rax
xorq %r9, %r9
movq %rax, 8(%r13)
movq (%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r10, %r9
movq 8(%r8), %rax
mulq %rax
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r9
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 16(%r13)
movq (%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rsi
adcq %rdx, %r9
adcq %r10, %rcx
movq 8(%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rsi
adcq %rdx, %r9
adcq %r10, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 24(%r13)
movq 8(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %r9
adcq %rdx, %rcx
adcq %r10, %rsi
movq 16(%r8), %rax
mulq %rax
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq %r9, %rax
xorq %r9, %r9
movq %rax, 32(%r13)
movq 16(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r10, %r9
xorq %r10, %r10
movq %rcx, 40(%r13)
movq 24(%r8), %rax
mulq %rax
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r10
xorq %rax, %rax
movq %rsi, 48(%r13)
movq %r9, 56(%r13)
xorq %r8, %r8
movq glob_data + 64(%rip), %rcx
movq glob_data + 136(%rip), %r11
xorq %r9, %r9
xorq %rsi, %rsi
xorq %r10, %r10
movq (%r13), %rax
addq %rax, %r9
adcq %r8, %rsi
adcq $0, %r10
movq %r9, %rax
mulq %rcx
movq %rax, (%r12)
mulq %r11
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
leaq glob_data + 136(%rip), %rdx
movq (%r12), %rax
mulq 8(%rdx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 8(%r13), %rax
addq %rax, %rsi
adcq %r8, %r10
adcq $0, %r9
movq %rsi, %rax
mulq %rcx
movq %rax, 8(%r12)
mulq %r11
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 16(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rsi
movq 8(%r12), %rax
mulq 8(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rsi
movq 16(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rsi
movq %r10, %rax
mulq %rcx
movq %rax, 16(%r12)
mulq %r11
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rsi
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
movq 8(%r12), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
movq 16(%r12), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
movq 24(%r13), %rax
addq %rax, %r9
adcq %r8, %rsi
adcq $0, %r10
movq %r9, %rax
mulq %rcx
movq %rax, 24(%r12)
mulq %r11
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
leaq glob_data + 136(%rip), %rcx
movq 8(%r12), %rax
mulq 24(%rcx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 16(%r12), %rax
mulq 16(%rcx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 24(%r12), %rax
mulq 8(%rcx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 32(%r13), %rax
addq %rax, %rsi
adcq %r8, %r10
adcq $0, %r9
movq %rsi, (%r12)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %rsi
movq 16(%r12), %rax
mulq 24(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 24(%r12), %rax
mulq 16(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 40(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rcx
movq %r10, 8(%r12)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdx
movq 24(%r12), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq 48(%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %rsi
movq %r9, 16(%r12)
xorq %rax, %rax
addq 56(%r13), %rcx
movq %rcx, 24(%r12)
movq (%r12), %rax
movq %rax, (%rsp)
movq 8(%r12), %rax
movq %rax, 8(%rsp)
movq 16(%r12), %rax
movq %rax, 16(%rsp)
movq 24(%r12), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r12), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r12)
movq 8(%r12), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r12)
movq 16(%r12), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r12)
movq 24(%r12), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r12)
jmp *%rbp
L_fp_mulU$1:
movq %rax, %r13
leaq 32(%rsp), %r12
movq (%r13), %rax
mulq (%r9)
movq %rax, (%r12)
movq %rdx, %r8
xorq %rsi, %rsi
xorq %rcx, %rcx
movq (%r13), %rax
mulq 8(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq 8(%r13), %rax
mulq (%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq %r8, %rax
xorq %r8, %r8
movq %rax, 8(%r12)
movq (%r13), %rax
mulq 16(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq 8(%r13), %rax
mulq 8(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq 16(%r13), %rax
mulq (%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 16(%r12)
movq (%r13), %rax
mulq 24(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq 8(%r13), %rax
mulq 16(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq 16(%r13), %rax
mulq 8(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq 24(%r13), %rax
mulq (%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%r12)
movq 8(%r13), %rax
mulq 24(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r13), %rax
mulq 16(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%r13), %rax
mulq 8(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq %r8, %rax
xorq %r8, %r8
movq %rax, 32(%r12)
movq 16(%r13), %rax
mulq 24(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq 24(%r13), %rax
mulq 16(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 40(%r12)
movq 24(%r13), %rax
mulq 24(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
xorq %rax, %rax
movq %rcx, 48(%r12)
movq %r8, 56(%r12)
xorq %r10, %r10
movq glob_data + 64(%rip), %r8
movq glob_data + 136(%rip), %rcx
xorq %r9, %r9
xorq %r11, %r11
xorq %rsi, %rsi
movq (%r12), %rax
addq %rax, %r9
adcq %r10, %r11
adcq $0, %rsi
movq %r9, %rax
mulq %r8
movq %rax, (%r13)
mulq %rcx
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
leaq glob_data + 136(%rip), %rdx
movq (%r13), %rax
mulq 8(%rdx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 8(%r12), %rax
addq %rax, %r11
adcq %r10, %rsi
adcq $0, %r9
movq %r11, %rax
mulq %r8
movq %rax, 8(%r13)
mulq %rcx
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r13), %rax
mulq 16(%rbx)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r11
movq 8(%r13), %rax
mulq 8(%rbx)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r11
movq 16(%r12), %rax
addq %rax, %rsi
adcq %r10, %r9
adcq $0, %r11
movq %rsi, %rax
mulq %r8
movq %rax, 16(%r13)
mulq %rcx
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r11
leaq glob_data + 136(%rip), %rbx
movq (%r13), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
movq 8(%r13), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
movq 16(%r13), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
movq 24(%r12), %rax
addq %rax, %r9
adcq %r10, %r11
adcq $0, %rsi
movq %r9, %rax
mulq %r8
movq %rax, 24(%r13)
mulq %rcx
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
leaq glob_data + 136(%rip), %rcx
movq 8(%r13), %rax
mulq 24(%rcx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 16(%r13), %rax
mulq 16(%rcx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 24(%r13), %rax
mulq 8(%rcx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 32(%r12), %rax
addq %rax, %r11
adcq %r10, %rsi
adcq $0, %r9
movq %r11, (%r13)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %r8
movq 16(%r13), %rax
mulq 24(%r8)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %rcx
movq 24(%r13), %rax
mulq 16(%r8)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %rcx
movq 40(%r12), %rax
addq %rax, %rsi
adcq %r10, %r9
adcq $0, %rcx
movq %rsi, 8(%r13)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdx
movq 24(%r13), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq 48(%r12), %rax
addq %rax, %r9
adcq %r10, %rcx
adcq $0, %rsi
movq %r9, 16(%r13)
xorq %rax, %rax
addq 56(%r12), %rcx
movq %rcx, 24(%r13)
movq (%r13), %rax
movq %rax, (%rsp)
movq 8(%r13), %rax
movq %rax, 8(%rsp)
movq 16(%r13), %rax
movq %rax, 16(%rsp)
movq 24(%r13), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r13), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r13)
movq 8(%r13), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r13)
movq 16(%r13), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r13)
movq 24(%r13), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r13)
jmp *%rbp
L_fp_mul$1:
movq %rax, %r12
leaq 32(%rsp), %r13
movq (%r10), %rax
mulq (%r8)
movq %rax, (%r13)
movq %rdx, %r9
xorq %rsi, %rsi
xorq %rcx, %rcx
movq (%r10), %rax
mulq 8(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 8(%r10), %rax
mulq (%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 8(%r13)
movq (%r10), %rax
mulq 16(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 8(%r10), %rax
mulq 8(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 16(%r10), %rax
mulq (%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 16(%r13)
movq (%r10), %rax
mulq 24(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 8(%r10), %rax
mulq 16(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 16(%r10), %rax
mulq 8(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 24(%r10), %rax
mulq (%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%r13)
movq 8(%r10), %rax
mulq 24(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r10), %rax
mulq 16(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%r10), %rax
mulq 8(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 32(%r13)
movq 16(%r10), %rax
mulq 24(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 24(%r10), %rax
mulq 16(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
xorq %r11, %r11
movq %rsi, 40(%r13)
movq 24(%r10), %rax
mulq 24(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %r11
xorq %rax, %rax
movq %rcx, 48(%r13)
movq %r9, 56(%r13)
xorq %r8, %r8
movq glob_data + 64(%rip), %r11
movq glob_data + 136(%rip), %rsi
xorq %r9, %r9
xorq %rcx, %rcx
xorq %r10, %r10
movq (%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %r10
movq %r9, %rax
mulq %r11
movq %rax, (%r12)
mulq %rsi
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
leaq glob_data + 136(%rip), %rdx
movq (%r12), %rax
mulq 8(%rdx)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 8(%r13), %rax
addq %rax, %rcx
adcq %r8, %r10
adcq $0, %r9
movq %rcx, %rax
mulq %r11
movq %rax, 8(%r12)
mulq %rsi
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 16(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 8(%r12), %rax
mulq 8(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 16(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rcx
movq %r10, %rax
mulq %r11
movq %rax, 16(%r12)
mulq %rsi
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
movq 8(%r12), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
movq 16(%r12), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
movq 24(%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %r10
movq %r9, %rax
mulq %r11
movq %rax, 24(%r12)
mulq %rsi
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
leaq glob_data + 136(%rip), %rsi
movq 8(%r12), %rax
mulq 24(%rsi)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 16(%r12), %rax
mulq 16(%rsi)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 24(%r12), %rax
mulq 8(%rsi)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 32(%r13), %rax
addq %rax, %rcx
adcq %r8, %r10
adcq $0, %r9
movq %rcx, (%r12)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %rsi
movq 16(%r12), %rax
mulq 24(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 24(%r12), %rax
mulq 16(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 40(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rcx
movq %r10, 8(%r12)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdx
movq 24(%r12), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq 48(%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %rsi
movq %r9, 16(%r12)
xorq %rax, %rax
addq 56(%r13), %rcx
movq %rcx, 24(%r12)
movq (%r12), %rax
movq %rax, (%rsp)
movq 8(%r12), %rax
movq %rax, 8(%rsp)
movq 16(%r12), %rax
movq %rax, 16(%rsp)
movq 24(%r12), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r12), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r12)
movq 8(%r12), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r12)
movq 16(%r12), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r12)
movq 24(%r12), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r12)
jmp *%rbp
L_fp_sub$1:
movq (%rdx), %rsi
subq %rsi, (%rax)
movq 8(%rdx), %rsi
sbbq %rsi, 8(%rax)
movq 16(%rdx), %rsi
sbbq %rsi, 16(%rax)
movq 24(%rdx), %rdx
sbbq %rdx, 24(%rax)
leaq glob_data + 136(%rip), %rdx
movq (%rdx), %rsi
movq %rsi, (%rsp)
movq 8(%rdx), %rsi
movq %rsi, 8(%rsp)
movq 16(%rdx), %rsi
movq %rsi, 16(%rsp)
movq 24(%rdx), %rdx
movq %rdx, 24(%rsp)
movq $0, %rdx
movq (%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, (%rsp)
movq 8(%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, 8(%rsp)
movq 16(%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, 16(%rsp)
movq 24(%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, 24(%rsp)
movq %rsp, %rdx
movq (%rdx), %rsi
addq %rsi, (%rax)
movq 8(%rdx), %rsi
adcq %rsi, 8(%rax)
movq 16(%rdx), %rsi
adcq %rsi, 16(%rax)
movq 24(%rdx), %rdx
adcq %rdx, 24(%rax)
jmp *%rcx
L_fp_add$1:
movq (%rdx), %rsi
addq %rsi, (%rax)
movq 8(%rdx), %rsi
adcq %rsi, 8(%rax)
movq 16(%rdx), %rsi
adcq %rsi, 16(%rax)
movq 24(%rdx), %rdx
adcq %rdx, 24(%rax)
movq (%rax), %rdx
movq %rdx, (%rsp)
movq 8(%rax), %rdx
movq %rdx, 8(%rsp)
movq 16(%rax), %rdx
movq %rdx, 16(%rsp)
movq 24(%rax), %rdx
movq %rdx, 24(%rsp)
movq %rsp, %rdx
leaq glob_data + 104(%rip), %rsi
movq (%rsi), %r8
addq %r8, (%rdx)
movq 8(%rsi), %r8
adcq %r8, 8(%rdx)
movq 16(%rsi), %r8
adcq %r8, 16(%rdx)
movq 24(%rsi), %rsi
adcq %rsi, 24(%rdx)
movq (%rax), %rsi
cmovb (%rdx), %rsi
movq %rsi, (%rax)
movq 8(%rax), %rsi
cmovb 8(%rdx), %rsi
movq %rsi, 8(%rax)
movq 16(%rax), %rsi
cmovb 16(%rdx), %rsi
movq %rsi, 16(%rax)
movq 24(%rax), %rsi
cmovb 24(%rdx), %rsi
movq %rsi, 24(%rax)
jmp *%rcx
L_bn_sqrn$1:
movq (%r8), %rax
mulq %rax
movq %rax, (%r9)
movq %rdx, %r10
xorq %rsi, %rsi
xorq %rdi, %rdi
movq (%r8), %rax
movq 8(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rsi
adcq %r11, %rdi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 8(%r9)
movq (%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r11, %r10
movq 8(%r8), %rax
mulq %rax
addq %rax, %rsi
adcq %rdx, %rdi
adcq $0, %r10
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 16(%r9)
movq (%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rdi
adcq %rdx, %r10
adcq %r11, %rsi
movq 8(%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rdi
adcq %rdx, %r10
adcq %r11, %rsi
movq %rdi, %rax
xorq %rdi, %rdi
movq %rax, 24(%r9)
movq 8(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rsi
adcq %r11, %rdi
movq 16(%r8), %rax
mulq %rax
addq %rax, %r10
adcq %rdx, %rsi
adcq $0, %rdi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 32(%r9)
movq 16(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r11, %r10
xorq %r11, %r11
movq %rsi, 40(%r9)
movq 24(%r8), %rax
mulq %rax
addq %rax, %rdi
adcq %rdx, %r10
adcq $0, %r11
xorq %rax, %rax
movq %rdi, 48(%r9)
movq %r10, 56(%r9)
jmp *%rcx
L_bn_muln$1:
movq (%r8), %rax
mulq (%rbx)
movq %rax, (%r9)
movq %rdx, %rsi
xorq %rcx, %rcx
xorq %rdi, %rdi
movq (%r8), %rax
mulq 8(%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
movq 8(%r8), %rax
mulq (%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
xorq %r11, %r11
movq %rsi, 8(%r9)
movq (%r8), %rax
mulq 16(%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
movq 8(%r8), %rax
mulq 8(%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
movq 16(%r8), %rax
mulq (%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
xorq %rsi, %rsi
movq %rcx, 16(%r9)
movq (%r8), %rax
mulq 24(%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
movq 8(%r8), %rax
mulq 16(%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
movq 16(%r8), %rax
mulq 8(%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
movq 24(%r8), %rax
mulq (%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
xorq %rcx, %rcx
movq %rdi, 24(%r9)
movq 8(%r8), %rax
mulq 24(%rbx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r8), %rax
mulq 16(%rbx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%r8), %rax
mulq 8(%rbx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %rcx
xorq %rdi, %rdi
movq %r11, 32(%r9)
movq 16(%r8), %rax
mulq 24(%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
movq 24(%r8), %rax
mulq 16(%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
xorq %r11, %r11
movq %rsi, 40(%r9)
movq 24(%r8), %rax
mulq 24(%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
xorq %rax, %rax
movq %rcx, 48(%r9)
movq %rdi, 56(%r9)
jmp *%r10
L_bn_subc$1:
movq (%rcx), %rax
subq %rax, (%rdx)
movq 8(%rcx), %rax
sbbq %rax, 8(%rdx)
movq 16(%rcx), %rax
sbbq %rax, 16(%rdx)
movq 24(%rcx), %rax
sbbq %rax, 24(%rdx)
jmp *%rsi
L_bn_addc$1:
movq (%rcx), %rax
addq %rax, (%rdx)
movq 8(%rcx), %rax
adcq %rax, 8(%rdx)
movq 16(%rcx), %rax
adcq %rax, 16(%rdx)
movq 24(%rcx), %rax
adcq %rax, 24(%rdx)
jmp *%rsi
L_bn_test0$1:
movq (%rcx), %rax
orq 8(%rcx), %rax
orq 16(%rcx), %rax
orq 24(%rcx), %rax
andq %rax, %rax
jmp *%rdx
L_bn_eq$1:
movq $0, %rdx
movq $1, %rsi
movq $0, %rdi
movq (%rax), %r8
xorq (%rcx), %r8
orq %r8, %rdi
movq 8(%rax), %r8
xorq 8(%rcx), %r8
orq %r8, %rdi
movq 16(%rax), %r8
xorq 16(%rcx), %r8
orq %r8, %rdi
movq 24(%rax), %rax
xorq 24(%rcx), %rax
orq %rax, %rdi
andq %rdi, %rdi
cmove %rsi, %rdx
jmp *%r9
.data
.p2align 5
_glob_data:
glob_data:
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 16
.byte -32
.byte 15
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -4
.byte 3
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -1
.byte -2
.byte -2
.byte -2
.byte -2
.byte -2
.byte -2
.byte -2
.byte -1
.byte -2
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte 63
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -1
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -64
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte 1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte 63
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
|
meizeddin/PQ_Secure_X3DH | 48,276 | pswoosh-master/rust/ref0/src/arithmetic/fq.s | .att_syntax
.text
.p2align 5
.globl _fp_fromM
.globl fp_fromM
.globl _fp_toM
.globl fp_toM
.globl _fp_inv
.globl fp_inv
.globl _fp_expm_noct
.globl fp_expm_noct
.globl _fp_sqr
.globl fp_sqr
.globl _fp_mul
.globl fp_mul
.globl _fp_sub
.globl fp_sub
.globl _fp_add
.globl fp_add
.globl _bn_sqrn
.globl bn_sqrn
.globl _bn_muln
.globl bn_muln
.globl _bn_subn
.globl bn_subn
.globl _bn_addn
.globl bn_addn
.globl _bn_set0
.globl bn_set0
.globl _bn_copy
.globl bn_copy
.globl _bn_test0
.globl bn_test0
.globl _bn_eq
.globl bn_eq
_fp_fromM:
fp_fromM:
movq %rsp, %rax
leaq -72(%rsp), %rsp
andq $-8, %rsp
movq %rax, 64(%rsp)
movq %rbx, 32(%rsp)
movq %rbp, 40(%rsp)
movq %r12, 48(%rsp)
movq %r13, 56(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq -96(%rsp), %rsp
leaq Lfp_fromM$1(%rip), %r9
jmp L_fp_fromM$1
Lfp_fromM$1:
leaq 96(%rsp), %rsp
movq (%rsi), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
movq %rax, 8(%rdi)
movq 16(%rsi), %rax
movq %rax, 16(%rdi)
movq 24(%rsi), %rax
movq %rax, 24(%rdi)
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
movq 48(%rsp), %r12
movq 56(%rsp), %r13
movq 64(%rsp), %rsp
ret
_fp_toM:
fp_toM:
movq %rsp, %rax
leaq -80(%rsp), %rsp
andq $-8, %rsp
movq %rax, 72(%rsp)
movq %rbx, 32(%rsp)
movq %rbp, 40(%rsp)
movq %r12, 48(%rsp)
movq %r13, 56(%rsp)
movq %r14, 64(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq Lfp_toM$1(%rip), %r14
jmp L_fp_toM$1
Lfp_toM$1:
movq (%r13), %rax
movq %rax, (%rdi)
movq 8(%r13), %rax
movq %rax, 8(%rdi)
movq 16(%r13), %rax
movq %rax, 16(%rdi)
movq 24(%r13), %rax
movq %rax, 24(%rdi)
movq 32(%rsp), %rbx
movq 40(%rsp), %rbp
movq 48(%rsp), %r12
movq 56(%rsp), %r13
movq 64(%rsp), %r14
movq 72(%rsp), %rsp
ret
_fp_inv:
fp_inv:
movq %rsp, %rax
leaq -120(%rsp), %rsp
andq $-8, %rsp
movq %rax, 112(%rsp)
movq %rbx, 72(%rsp)
movq %rbp, 80(%rsp)
movq %r12, 88(%rsp)
movq %r13, 96(%rsp)
movq %r14, 104(%rsp)
movq %rdi, (%rsp)
movq (%rsi), %rax
movq %rax, 8(%rsp)
movq 8(%rsi), %rax
movq %rax, 16(%rsp)
movq 16(%rsi), %rax
movq %rax, 24(%rsp)
movq 24(%rsi), %rax
movq %rax, 32(%rsp)
leaq 8(%rsp), %rax
leaq 40(%rsp), %rdx
leaq glob_data + 72(%rip), %rcx
leaq -64(%rsp), %rsp
leaq Lfp_inv$1(%rip), %rsi
movq %rsi, 56(%rsp)
jmp L_fp_exp$1
Lfp_inv$1:
leaq 64(%rsp), %rsp
movq (%rsp), %rax
movq (%rdx), %rcx
movq %rcx, (%rax)
movq 8(%rdx), %rcx
movq %rcx, 8(%rax)
movq 16(%rdx), %rcx
movq %rcx, 16(%rax)
movq 24(%rdx), %rcx
movq %rcx, 24(%rax)
movq 72(%rsp), %rbx
movq 80(%rsp), %rbp
movq 88(%rsp), %r12
movq 96(%rsp), %r13
movq 104(%rsp), %r14
movq 112(%rsp), %rsp
ret
_fp_expm_noct:
fp_expm_noct:
movq %rsp, %rax
leaq -152(%rsp), %rsp
andq $-8, %rsp
movq %rax, 144(%rsp)
movq %rbx, 104(%rsp)
movq %rbp, 112(%rsp)
movq %r12, 120(%rsp)
movq %r13, 128(%rsp)
movq %r14, 136(%rsp)
movq %rdi, (%rsp)
movq (%rsi), %rax
movq %rax, 8(%rsp)
movq 8(%rsi), %rax
movq %rax, 16(%rsp)
movq 16(%rsi), %rax
movq %rax, 24(%rsp)
movq 24(%rsi), %rax
movq %rax, 32(%rsp)
leaq 8(%rsp), %rax
movq (%rdx), %rcx
movq %rcx, 40(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 56(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 64(%rsp)
leaq 40(%rsp), %rcx
leaq 72(%rsp), %rdx
leaq -64(%rsp), %rsp
leaq Lfp_expm_noct$1(%rip), %rsi
movq %rsi, 56(%rsp)
jmp L_fp_exp$1
Lfp_expm_noct$1:
leaq 64(%rsp), %rsp
movq (%rsp), %rax
movq (%rdx), %rcx
movq %rcx, (%rax)
movq 8(%rdx), %rcx
movq %rcx, 8(%rax)
movq 16(%rdx), %rcx
movq %rcx, 16(%rax)
movq 24(%rdx), %rcx
movq %rcx, 24(%rax)
movq 104(%rsp), %rbx
movq 112(%rsp), %rbp
movq 120(%rsp), %r12
movq 128(%rsp), %r13
movq 136(%rsp), %r14
movq 144(%rsp), %rsp
ret
_fp_sqr:
fp_sqr:
movq %rsp, %rax
leaq -104(%rsp), %rsp
andq $-8, %rsp
movq %rax, 96(%rsp)
movq %rbx, 64(%rsp)
movq %rbp, 72(%rsp)
movq %r12, 80(%rsp)
movq %r13, 88(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %r8
leaq 32(%rsp), %rax
leaq -96(%rsp), %rsp
leaq Lfp_sqr$1(%rip), %rbp
jmp L_fp_sqr$1
Lfp_sqr$1:
leaq 96(%rsp), %rsp
movq (%r12), %rax
movq %rax, (%rdi)
movq 8(%r12), %rax
movq %rax, 8(%rdi)
movq 16(%r12), %rax
movq %rax, 16(%rdi)
movq 24(%r12), %rax
movq %rax, 24(%rdi)
movq 64(%rsp), %rbx
movq 72(%rsp), %rbp
movq 80(%rsp), %r12
movq 88(%rsp), %r13
movq 96(%rsp), %rsp
ret
_fp_mul:
fp_mul:
movq %rsp, %rax
leaq -136(%rsp), %rsp
andq $-8, %rsp
movq %rax, 128(%rsp)
movq %rbx, 96(%rsp)
movq %rbp, 104(%rsp)
movq %r12, 112(%rsp)
movq %r13, 120(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %r10
movq (%rdx), %rax
movq %rax, 32(%rsp)
movq 8(%rdx), %rax
movq %rax, 40(%rsp)
movq 16(%rdx), %rax
movq %rax, 48(%rsp)
movq 24(%rdx), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %r8
leaq 64(%rsp), %rax
leaq -96(%rsp), %rsp
leaq Lfp_mul$1(%rip), %rbp
jmp L_fp_mul$1
Lfp_mul$1:
leaq 96(%rsp), %rsp
movq (%r12), %rax
movq %rax, (%rdi)
movq 8(%r12), %rax
movq %rax, 8(%rdi)
movq 16(%r12), %rax
movq %rax, 16(%rdi)
movq 24(%r12), %rax
movq %rax, 24(%rdi)
movq 96(%rsp), %rbx
movq 104(%rsp), %rbp
movq 112(%rsp), %r12
movq 120(%rsp), %r13
movq 128(%rsp), %rsp
ret
_fp_sub:
fp_sub:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rdx
leaq -32(%rsp), %rsp
leaq Lfp_sub$1(%rip), %rcx
jmp L_fp_sub$1
Lfp_sub$1:
leaq 32(%rsp), %rsp
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_fp_add:
fp_add:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rdx
leaq -32(%rsp), %rsp
leaq Lfp_add$1(%rip), %rcx
jmp L_fp_add$1
Lfp_add$1:
leaq 32(%rsp), %rsp
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_bn_sqrn:
bn_sqrn:
movq %rsp, %rax
leaq -104(%rsp), %rsp
andq $-8, %rsp
movq %rax, 96(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rsi
leaq 32(%rsp), %r8
movq (%rsi), %rax
mulq %rax
movq %rax, (%r8)
movq %rdx, %r9
xorq %r10, %r10
xorq %rcx, %rcx
movq (%rsi), %rax
movq 8(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r9
adcq %rdx, %r10
adcq %r11, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 8(%r8)
movq (%rsi), %rax
movq 16(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rcx
adcq %r11, %r9
movq 8(%rsi), %rax
mulq %rax
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %r9
movq %r10, %rax
xorq %r10, %r10
movq %rax, 16(%r8)
movq (%rsi), %rax
movq 24(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rcx
adcq %rdx, %r9
adcq %r11, %r10
movq 8(%rsi), %rax
movq 16(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rcx
adcq %rdx, %r9
adcq %r11, %r10
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%r8)
movq 8(%rsi), %rax
movq 24(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r9
adcq %rdx, %r10
adcq %r11, %rcx
movq 16(%rsi), %rax
mulq %rax
addq %rax, %r9
adcq %rdx, %r10
adcq $0, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 32(%r8)
movq 16(%rsi), %rax
movq 24(%rsi), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rcx
adcq %r11, %r9
xorq %r11, %r11
movq %r10, 40(%r8)
movq 24(%rsi), %rax
mulq %rax
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %r11
xorq %rax, %rax
movq %rcx, 48(%r8)
movq %r9, 56(%r8)
movq (%r8), %rax
movq %rax, (%rdi)
movq 8(%r8), %rax
movq %rax, 8(%rdi)
movq 16(%r8), %rax
movq %rax, 16(%rdi)
movq 24(%r8), %rax
movq %rax, 24(%rdi)
movq 32(%r8), %rax
movq %rax, 32(%rdi)
movq 40(%r8), %rax
movq %rax, 40(%rdi)
movq 48(%r8), %rax
movq %rax, 48(%rdi)
movq 56(%r8), %rax
movq %rax, 56(%rdi)
movq 96(%rsp), %rsp
ret
_bn_muln:
bn_muln:
movq %rsp, %rax
leaq -144(%rsp), %rsp
andq $-8, %rsp
movq %rax, 136(%rsp)
movq %rbx, 128(%rsp)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %r8
movq (%rdx), %rax
movq %rax, 32(%rsp)
movq 8(%rdx), %rax
movq %rax, 40(%rsp)
movq 16(%rdx), %rax
movq %rax, 48(%rsp)
movq 24(%rdx), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %r9
leaq 64(%rsp), %r11
movq (%r8), %rax
mulq (%r9)
movq %rax, (%r11)
movq %rdx, %r10
xorq %rcx, %rcx
xorq %rsi, %rsi
movq (%r8), %rax
mulq 8(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq 8(%r8), %rax
mulq (%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 8(%r11)
movq (%r8), %rax
mulq 16(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq 8(%r8), %rax
mulq 8(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq 16(%r8), %rax
mulq (%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 16(%r11)
movq (%r8), %rax
mulq 24(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq 8(%r8), %rax
mulq 16(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq 16(%r8), %rax
mulq 8(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq 24(%r8), %rax
mulq (%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 24(%r11)
movq 8(%r8), %rax
mulq 24(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq 16(%r8), %rax
mulq 16(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq 24(%r8), %rax
mulq 8(%r9)
addq %rax, %r10
adcq %rdx, %rcx
adcq $0, %rsi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 32(%r11)
movq 16(%r8), %rax
mulq 24(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
movq 24(%r8), %rax
mulq 16(%r9)
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r10
xorq %rbx, %rbx
movq %rcx, 40(%r11)
movq 24(%r8), %rax
mulq 24(%r9)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %rbx
xorq %rax, %rax
movq %rsi, 48(%r11)
movq %r10, 56(%r11)
movq (%r11), %rax
movq %rax, (%rdi)
movq 8(%r11), %rax
movq %rax, 8(%rdi)
movq 16(%r11), %rax
movq %rax, 16(%rdi)
movq 24(%r11), %rax
movq %rax, 24(%rdi)
movq 32(%r11), %rax
movq %rax, 32(%rdi)
movq 40(%r11), %rax
movq %rax, 40(%rdi)
movq 48(%r11), %rax
movq %rax, 48(%rdi)
movq 56(%r11), %rax
movq %rax, 56(%rdi)
movq 128(%rsp), %rbx
movq 136(%rsp), %rsp
ret
_bn_subn:
bn_subn:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rcx
movq (%rcx), %rdx
subq %rdx, (%rax)
movq 8(%rcx), %rdx
sbbq %rdx, 8(%rax)
movq 16(%rcx), %rdx
sbbq %rdx, 16(%rax)
movq 24(%rcx), %rcx
sbbq %rcx, 24(%rax)
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_bn_addn:
bn_addn:
movq %rsp, %r10
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rdx), %rcx
movq %rcx, 32(%rsp)
movq 8(%rdx), %rcx
movq %rcx, 40(%rsp)
movq 16(%rdx), %rcx
movq %rcx, 48(%rsp)
movq 24(%rdx), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%rax), %rcx
movq %rcx, (%rdi)
movq 8(%rax), %rcx
movq %rcx, 8(%rdi)
movq 16(%rax), %rcx
movq %rcx, 16(%rdi)
movq 24(%rax), %rax
movq %rax, 24(%rdi)
movq %r10, %rsp
ret
_bn_set0:
bn_set0:
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
movq $0, 24(%rdi)
ret
_bn_copy:
bn_copy:
movq (%rsi), %rax
movq %rax, (%rdi)
movq 8(%rsi), %rax
movq %rax, 8(%rdi)
movq 16(%rsi), %rax
movq %rax, 16(%rdi)
movq 24(%rsi), %rax
movq %rax, 24(%rdi)
ret
_bn_test0:
bn_test0:
movq %rsp, %r10
leaq -32(%rsp), %rsp
andq $-8, %rsp
movq (%rdi), %rax
movq %rax, (%rsp)
movq 8(%rdi), %rax
movq %rax, 8(%rsp)
movq 16(%rdi), %rax
movq %rax, 16(%rsp)
movq 24(%rdi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq $0, %rcx
movq $1, %rdx
movq (%rax), %rsi
orq 8(%rax), %rsi
orq 16(%rax), %rsi
orq 24(%rax), %rsi
andq %rsi, %rsi
cmove %rdx, %rcx
movq %rcx, %rax
movq %r10, %rsp
ret
_bn_eq:
bn_eq:
movq %rsp, %r11
leaq -64(%rsp), %rsp
andq $-8, %rsp
movq (%rdi), %rax
movq %rax, (%rsp)
movq 8(%rdi), %rax
movq %rax, 8(%rsp)
movq 16(%rdi), %rax
movq %rax, 16(%rsp)
movq 24(%rdi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
movq (%rsi), %rcx
movq %rcx, 32(%rsp)
movq 8(%rsi), %rcx
movq %rcx, 40(%rsp)
movq 16(%rsi), %rcx
movq %rcx, 48(%rsp)
movq 24(%rsi), %rcx
movq %rcx, 56(%rsp)
leaq 32(%rsp), %rcx
leaq Lbn_eq$1(%rip), %r9
jmp L_bn_eq$1
Lbn_eq$1:
movq %rdx, %rax
movq %r11, %rsp
ret
L_fp_toM$1:
leaq glob_data + 0(%rip), %r9
leaq -96(%rsp), %rsp
leaq L_fp_toM$2(%rip), %rbp
jmp L_fp_mulU$1
L_fp_toM$2:
leaq 96(%rsp), %rsp
jmp *%r14
L_fp_fromM$1:
movq %rax, %rsi
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq (%rsi), %rax
movq %rax, 32(%rsp)
movq 8(%rsi), %rax
movq %rax, 40(%rsp)
movq 16(%rsi), %rax
movq %rax, 48(%rsp)
movq 24(%rsi), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %r10
xorq %r12, %r12
movq glob_data + 64(%rip), %r11
movq glob_data + 136(%rip), %rbp
xorq %r13, %r13
xorq %rcx, %rcx
xorq %r8, %r8
movq (%r10), %rax
addq %rax, %r13
adcq %r12, %rcx
adcq $0, %r8
movq %r13, %rax
mulq %r11
movq %rax, (%rsi)
mulq %rbp
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
leaq glob_data + 136(%rip), %rdx
movq (%rsi), %rax
mulq 8(%rdx)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 8(%r10), %rax
addq %rax, %rcx
adcq %r12, %r8
adcq $0, %r13
movq %rcx, %rax
mulq %r11
movq %rax, 8(%rsi)
mulq %rbp
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
leaq glob_data + 136(%rip), %rbx
movq (%rsi), %rax
mulq 16(%rbx)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 8(%rsi), %rax
mulq 8(%rbx)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 16(%r10), %rax
addq %rax, %r8
adcq %r12, %r13
adcq $0, %rcx
movq %r8, %rax
mulq %r11
movq %rax, 16(%rsi)
mulq %rbp
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
leaq glob_data + 136(%rip), %rbx
movq (%rsi), %rax
mulq 24(%rbx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 8(%rsi), %rax
mulq 16(%rbx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 16(%rsi), %rax
mulq 8(%rbx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 24(%r10), %rax
addq %rax, %r13
adcq %r12, %rcx
adcq $0, %r8
movq %r13, %rax
mulq %r11
movq %rax, 24(%rsi)
mulq %rbp
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
leaq glob_data + 136(%rip), %r11
movq 8(%rsi), %rax
mulq 24(%r11)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 16(%rsi), %rax
mulq 16(%r11)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 24(%rsi), %rax
mulq 8(%r11)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %r13
movq 32(%r10), %rax
addq %rax, %rcx
adcq %r12, %r8
adcq $0, %r13
movq %rcx, (%rsi)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %r11
movq 16(%rsi), %rax
mulq 24(%r11)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 24(%rsi), %rax
mulq 16(%r11)
addq %rax, %r8
adcq %rdx, %r13
adcq $0, %rcx
movq 40(%r10), %rax
addq %rax, %r8
adcq %r12, %r13
adcq $0, %rcx
movq %r8, 8(%rsi)
xorq %r8, %r8
leaq glob_data + 136(%rip), %rdx
movq 24(%rsi), %rax
mulq 24(%rdx)
addq %rax, %r13
adcq %rdx, %rcx
adcq $0, %r8
movq 48(%r10), %rax
addq %rax, %r13
adcq %r12, %rcx
adcq $0, %r8
movq %r13, 16(%rsi)
xorq %rax, %rax
addq 56(%r10), %rcx
movq %rcx, 24(%rsi)
movq (%rsi), %rax
movq %rax, (%rsp)
movq 8(%rsi), %rax
movq %rax, 8(%rsp)
movq 16(%rsi), %rax
movq %rax, 16(%rsp)
movq 24(%rsi), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%rsi), %rcx
cmovb (%rax), %rcx
movq %rcx, (%rsi)
movq 8(%rsi), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%rsi)
movq 16(%rsi), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%rsi)
movq 24(%rsi), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%rsi)
jmp *%r9
L_fp_exp$1:
leaq 24(%rsp), %rsi
leaq glob_data + 32(%rip), %rdi
movq (%rax), %r8
movq %r8, (%rsi)
movq 8(%rax), %r8
movq %r8, 8(%rsi)
movq 16(%rax), %r8
movq %r8, 16(%rsi)
movq 24(%rax), %rax
movq %rax, 24(%rsi)
movq (%rdi), %rax
movq %rax, (%rdx)
movq 8(%rdi), %rax
movq %rax, 8(%rdx)
movq 16(%rdi), %rax
movq %rax, 16(%rdx)
movq 24(%rdi), %rax
movq %rax, 24(%rdx)
movq %rcx, (%rsp)
movq %rdx, 8(%rsp)
movq (%rsp), %rax
movq (%rax), %r14
movq $64, %rax
jmp L_fp_exp$17
L_fp_exp$18:
movq %rax, 16(%rsp)
shrq $1, %r14
jnb L_fp_exp$20
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$21(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$21:
leaq 96(%rsp), %rsp
L_fp_exp$20:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$19(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$19:
leaq 104(%rsp), %rsp
movq 16(%rsp), %rax
addq $-1, %rax
L_fp_exp$17:
cmpq $0, %rax
jne L_fp_exp$18
movq (%rsp), %rax
movq 8(%rax), %r14
movq $64, %rax
jmp L_fp_exp$12
L_fp_exp$13:
movq %rax, 16(%rsp)
shrq $1, %r14
jnb L_fp_exp$15
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$16(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$16:
leaq 96(%rsp), %rsp
L_fp_exp$15:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$14(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$14:
leaq 104(%rsp), %rsp
movq 16(%rsp), %rax
addq $-1, %rax
L_fp_exp$12:
cmpq $0, %rax
jne L_fp_exp$13
movq (%rsp), %rax
movq 16(%rax), %r14
movq $64, %rax
jmp L_fp_exp$7
L_fp_exp$8:
movq %rax, 16(%rsp)
shrq $1, %r14
jnb L_fp_exp$10
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$11(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$11:
leaq 96(%rsp), %rsp
L_fp_exp$10:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$9(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$9:
leaq 104(%rsp), %rsp
movq 16(%rsp), %rax
addq $-1, %rax
L_fp_exp$7:
cmpq $0, %rax
jne L_fp_exp$8
movq (%rsp), %rax
movq 24(%rax), %r14
movq $64, %rax
jmp L_fp_exp$2
L_fp_exp$3:
movq %rax, (%rsp)
shrq $1, %r14
jnb L_fp_exp$5
movq 8(%rsp), %rax
leaq 24(%rsp), %r9
leaq -96(%rsp), %rsp
leaq L_fp_exp$6(%rip), %rbp
jmp L_fp_mulU$1
L_fp_exp$6:
leaq 96(%rsp), %rsp
L_fp_exp$5:
leaq 24(%rsp), %rax
leaq -104(%rsp), %rsp
leaq L_fp_exp$4(%rip), %rcx
movq %rcx, 96(%rsp)
jmp L_fp_sqrU$1
L_fp_exp$4:
leaq 104(%rsp), %rsp
movq (%rsp), %rax
addq $-1, %rax
L_fp_exp$2:
cmpq $0, %rax
jne L_fp_exp$3
movq 8(%rsp), %rdx
jmp *56(%rsp)
L_fp_sqrU$1:
movq %rax, %r11
leaq 32(%rsp), %rbp
movq (%r11), %rax
mulq %rax
movq %rax, (%rbp)
movq %rdx, %rsi
xorq %rdi, %rdi
xorq %rcx, %rcx
movq (%r11), %rax
movq 8(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r8, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 8(%rbp)
movq (%r11), %rax
movq 16(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rdi
adcq %rdx, %rcx
adcq %r8, %rsi
movq 8(%r11), %rax
mulq %rax
addq %rax, %rdi
adcq %rdx, %rcx
adcq $0, %rsi
movq %rdi, %rax
xorq %rdi, %rdi
movq %rax, 16(%rbp)
movq (%r11), %rax
movq 24(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r8, %rdi
movq 8(%r11), %rax
movq 16(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r8, %rdi
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%rbp)
movq 8(%r11), %rax
movq 24(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r8, %rcx
movq 16(%r11), %rax
mulq %rax
addq %rax, %rsi
adcq %rdx, %rdi
adcq $0, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 32(%rbp)
movq 16(%r11), %rax
movq 24(%r11), %rdx
mulq %rdx
movq %rax, %r8
shlq $1, %rax
shldq $1, %r8, %rdx
movq $0, %r8
adcq %r8, %r8
addq %rax, %rdi
adcq %rdx, %rcx
adcq %r8, %rsi
xorq %r8, %r8
movq %rdi, 40(%rbp)
movq 24(%r11), %rax
mulq %rax
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r8
xorq %rax, %rax
movq %rcx, 48(%rbp)
movq %rsi, 56(%rbp)
xorq %r10, %r10
movq glob_data + 64(%rip), %rdi
movq glob_data + 136(%rip), %r8
xorq %r9, %r9
xorq %rsi, %rsi
xorq %rcx, %rcx
movq (%rbp), %rax
addq %rax, %r9
adcq %r10, %rsi
adcq $0, %rcx
movq %r9, %rax
mulq %rdi
movq %rax, (%r11)
mulq %r8
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
leaq glob_data + 136(%rip), %rdx
movq (%r11), %rax
mulq 8(%rdx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 8(%rbp), %rax
addq %rax, %rsi
adcq %r10, %rcx
adcq $0, %r9
movq %rsi, %rax
mulq %rdi
movq %rax, 8(%r11)
mulq %r8
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r11), %rax
mulq 16(%rbx)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 8(%r11), %rax
mulq 8(%rbx)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 16(%rbp), %rax
addq %rax, %rcx
adcq %r10, %r9
adcq $0, %rsi
movq %rcx, %rax
mulq %rdi
movq %rax, 16(%r11)
mulq %r8
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
leaq glob_data + 136(%rip), %rbx
movq (%r11), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 8(%r11), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r11), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%rbp), %rax
addq %rax, %r9
adcq %r10, %rsi
adcq $0, %rcx
movq %r9, %rax
mulq %rdi
movq %rax, 24(%r11)
mulq %r8
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
leaq glob_data + 136(%rip), %rdi
movq 8(%r11), %rax
mulq 24(%rdi)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 16(%r11), %rax
mulq 16(%rdi)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 24(%r11), %rax
mulq 8(%rdi)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 32(%rbp), %rax
addq %rax, %rsi
adcq %r10, %rcx
adcq $0, %r9
movq %rsi, (%r11)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdi
movq 16(%r11), %rax
mulq 24(%rdi)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 24(%r11), %rax
mulq 16(%rdi)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 40(%rbp), %rax
addq %rax, %rcx
adcq %r10, %r9
adcq $0, %rsi
movq %rcx, 8(%r11)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %rdx
movq 24(%r11), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 48(%rbp), %rax
addq %rax, %r9
adcq %r10, %rsi
adcq $0, %rcx
movq %r9, 16(%r11)
xorq %rax, %rax
addq 56(%rbp), %rsi
movq %rsi, 24(%r11)
movq (%r11), %rax
movq %rax, (%rsp)
movq 8(%r11), %rax
movq %rax, 8(%rsp)
movq 16(%r11), %rax
movq %rax, 16(%rsp)
movq 24(%r11), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r11), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r11)
movq 8(%r11), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r11)
movq 16(%r11), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r11)
movq 24(%r11), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r11)
jmp *96(%rsp)
L_fp_sqr$1:
movq %rax, %r12
leaq 32(%rsp), %r13
movq (%r8), %rax
mulq %rax
movq %rax, (%r13)
movq %rdx, %r9
xorq %rcx, %rcx
xorq %rsi, %rsi
movq (%r8), %rax
movq 8(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %r9
adcq %rdx, %rcx
adcq %r10, %rsi
movq %r9, %rax
xorq %r9, %r9
movq %rax, 8(%r13)
movq (%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r10, %r9
movq 8(%r8), %rax
mulq %rax
addq %rax, %rcx
adcq %rdx, %rsi
adcq $0, %r9
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 16(%r13)
movq (%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rsi
adcq %rdx, %r9
adcq %r10, %rcx
movq 8(%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rsi
adcq %rdx, %r9
adcq %r10, %rcx
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 24(%r13)
movq 8(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %r9
adcq %rdx, %rcx
adcq %r10, %rsi
movq 16(%r8), %rax
mulq %rax
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq %r9, %rax
xorq %r9, %r9
movq %rax, 32(%r13)
movq 16(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r10
shlq $1, %rax
shldq $1, %r10, %rdx
movq $0, %r10
adcq %r10, %r10
addq %rax, %rcx
adcq %rdx, %rsi
adcq %r10, %r9
xorq %r10, %r10
movq %rcx, 40(%r13)
movq 24(%r8), %rax
mulq %rax
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r10
xorq %rax, %rax
movq %rsi, 48(%r13)
movq %r9, 56(%r13)
xorq %r8, %r8
movq glob_data + 64(%rip), %rcx
movq glob_data + 136(%rip), %r11
xorq %r9, %r9
xorq %rsi, %rsi
xorq %r10, %r10
movq (%r13), %rax
addq %rax, %r9
adcq %r8, %rsi
adcq $0, %r10
movq %r9, %rax
mulq %rcx
movq %rax, (%r12)
mulq %r11
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
leaq glob_data + 136(%rip), %rdx
movq (%r12), %rax
mulq 8(%rdx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 8(%r13), %rax
addq %rax, %rsi
adcq %r8, %r10
adcq $0, %r9
movq %rsi, %rax
mulq %rcx
movq %rax, 8(%r12)
mulq %r11
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 16(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rsi
movq 8(%r12), %rax
mulq 8(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rsi
movq 16(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rsi
movq %r10, %rax
mulq %rcx
movq %rax, 16(%r12)
mulq %r11
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rsi
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
movq 8(%r12), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
movq 16(%r12), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
movq 24(%r13), %rax
addq %rax, %r9
adcq %r8, %rsi
adcq $0, %r10
movq %r9, %rax
mulq %rcx
movq %rax, 24(%r12)
mulq %r11
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %r10
leaq glob_data + 136(%rip), %rcx
movq 8(%r12), %rax
mulq 24(%rcx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 16(%r12), %rax
mulq 16(%rcx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 24(%r12), %rax
mulq 8(%rcx)
addq %rax, %rsi
adcq %rdx, %r10
adcq $0, %r9
movq 32(%r13), %rax
addq %rax, %rsi
adcq %r8, %r10
adcq $0, %r9
movq %rsi, (%r12)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %rsi
movq 16(%r12), %rax
mulq 24(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 24(%r12), %rax
mulq 16(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 40(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rcx
movq %r10, 8(%r12)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdx
movq 24(%r12), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq 48(%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %rsi
movq %r9, 16(%r12)
xorq %rax, %rax
addq 56(%r13), %rcx
movq %rcx, 24(%r12)
movq (%r12), %rax
movq %rax, (%rsp)
movq 8(%r12), %rax
movq %rax, 8(%rsp)
movq 16(%r12), %rax
movq %rax, 16(%rsp)
movq 24(%r12), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r12), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r12)
movq 8(%r12), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r12)
movq 16(%r12), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r12)
movq 24(%r12), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r12)
jmp *%rbp
L_fp_mulU$1:
movq %rax, %r13
leaq 32(%rsp), %r12
movq (%r13), %rax
mulq (%r9)
movq %rax, (%r12)
movq %rdx, %r8
xorq %rsi, %rsi
xorq %rcx, %rcx
movq (%r13), %rax
mulq 8(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq 8(%r13), %rax
mulq (%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq %r8, %rax
xorq %r8, %r8
movq %rax, 8(%r12)
movq (%r13), %rax
mulq 16(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq 8(%r13), %rax
mulq 8(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq 16(%r13), %rax
mulq (%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 16(%r12)
movq (%r13), %rax
mulq 24(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq 8(%r13), %rax
mulq 16(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq 16(%r13), %rax
mulq 8(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq 24(%r13), %rax
mulq (%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%r12)
movq 8(%r13), %rax
mulq 24(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r13), %rax
mulq 16(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%r13), %rax
mulq 8(%r9)
addq %rax, %r8
adcq %rdx, %rsi
adcq $0, %rcx
movq %r8, %rax
xorq %r8, %r8
movq %rax, 32(%r12)
movq 16(%r13), %rax
mulq 24(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq 24(%r13), %rax
mulq 16(%r9)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r8
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 40(%r12)
movq 24(%r13), %rax
mulq 24(%r9)
addq %rax, %rcx
adcq %rdx, %r8
adcq $0, %rsi
xorq %rax, %rax
movq %rcx, 48(%r12)
movq %r8, 56(%r12)
xorq %r10, %r10
movq glob_data + 64(%rip), %r8
movq glob_data + 136(%rip), %rcx
xorq %r9, %r9
xorq %r11, %r11
xorq %rsi, %rsi
movq (%r12), %rax
addq %rax, %r9
adcq %r10, %r11
adcq $0, %rsi
movq %r9, %rax
mulq %r8
movq %rax, (%r13)
mulq %rcx
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
leaq glob_data + 136(%rip), %rdx
movq (%r13), %rax
mulq 8(%rdx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 8(%r12), %rax
addq %rax, %r11
adcq %r10, %rsi
adcq $0, %r9
movq %r11, %rax
mulq %r8
movq %rax, 8(%r13)
mulq %rcx
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r13), %rax
mulq 16(%rbx)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r11
movq 8(%r13), %rax
mulq 8(%rbx)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r11
movq 16(%r12), %rax
addq %rax, %rsi
adcq %r10, %r9
adcq $0, %r11
movq %rsi, %rax
mulq %r8
movq %rax, 16(%r13)
mulq %rcx
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %r11
leaq glob_data + 136(%rip), %rbx
movq (%r13), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
movq 8(%r13), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
movq 16(%r13), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
movq 24(%r12), %rax
addq %rax, %r9
adcq %r10, %r11
adcq $0, %rsi
movq %r9, %rax
mulq %r8
movq %rax, 24(%r13)
mulq %rcx
addq %rax, %r9
adcq %rdx, %r11
adcq $0, %rsi
leaq glob_data + 136(%rip), %rcx
movq 8(%r13), %rax
mulq 24(%rcx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 16(%r13), %rax
mulq 16(%rcx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 24(%r13), %rax
mulq 8(%rcx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %r9
movq 32(%r12), %rax
addq %rax, %r11
adcq %r10, %rsi
adcq $0, %r9
movq %r11, (%r13)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %r8
movq 16(%r13), %rax
mulq 24(%r8)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %rcx
movq 24(%r13), %rax
mulq 16(%r8)
addq %rax, %rsi
adcq %rdx, %r9
adcq $0, %rcx
movq 40(%r12), %rax
addq %rax, %rsi
adcq %r10, %r9
adcq $0, %rcx
movq %rsi, 8(%r13)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdx
movq 24(%r13), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq 48(%r12), %rax
addq %rax, %r9
adcq %r10, %rcx
adcq $0, %rsi
movq %r9, 16(%r13)
xorq %rax, %rax
addq 56(%r12), %rcx
movq %rcx, 24(%r13)
movq (%r13), %rax
movq %rax, (%rsp)
movq 8(%r13), %rax
movq %rax, 8(%rsp)
movq 16(%r13), %rax
movq %rax, 16(%rsp)
movq 24(%r13), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r13), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r13)
movq 8(%r13), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r13)
movq 16(%r13), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r13)
movq 24(%r13), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r13)
jmp *%rbp
L_fp_mul$1:
movq %rax, %r12
leaq 32(%rsp), %r13
movq (%r10), %rax
mulq (%r8)
movq %rax, (%r13)
movq %rdx, %r9
xorq %rsi, %rsi
xorq %rcx, %rcx
movq (%r10), %rax
mulq 8(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 8(%r10), %rax
mulq (%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 8(%r13)
movq (%r10), %rax
mulq 16(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 8(%r10), %rax
mulq 8(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 16(%r10), %rax
mulq (%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 16(%r13)
movq (%r10), %rax
mulq 24(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 8(%r10), %rax
mulq 16(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 16(%r10), %rax
mulq 8(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq 24(%r10), %rax
mulq (%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %rsi
movq %rcx, %rax
xorq %rcx, %rcx
movq %rax, 24(%r13)
movq 8(%r10), %rax
mulq 24(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r10), %rax
mulq 16(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%r10), %rax
mulq 8(%r8)
addq %rax, %r9
adcq %rdx, %rsi
adcq $0, %rcx
movq %r9, %rax
xorq %r9, %r9
movq %rax, 32(%r13)
movq 16(%r10), %rax
mulq 24(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
movq 24(%r10), %rax
mulq 16(%r8)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %r9
xorq %r11, %r11
movq %rsi, 40(%r13)
movq 24(%r10), %rax
mulq 24(%r8)
addq %rax, %rcx
adcq %rdx, %r9
adcq $0, %r11
xorq %rax, %rax
movq %rcx, 48(%r13)
movq %r9, 56(%r13)
xorq %r8, %r8
movq glob_data + 64(%rip), %r11
movq glob_data + 136(%rip), %rsi
xorq %r9, %r9
xorq %rcx, %rcx
xorq %r10, %r10
movq (%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %r10
movq %r9, %rax
mulq %r11
movq %rax, (%r12)
mulq %rsi
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
leaq glob_data + 136(%rip), %rdx
movq (%r12), %rax
mulq 8(%rdx)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 8(%r13), %rax
addq %rax, %rcx
adcq %r8, %r10
adcq $0, %r9
movq %rcx, %rax
mulq %r11
movq %rax, 8(%r12)
mulq %rsi
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 16(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 8(%r12), %rax
mulq 8(%rbx)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 16(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rcx
movq %r10, %rax
mulq %r11
movq %rax, 16(%r12)
mulq %rsi
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
leaq glob_data + 136(%rip), %rbx
movq (%r12), %rax
mulq 24(%rbx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
movq 8(%r12), %rax
mulq 16(%rbx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
movq 16(%r12), %rax
mulq 8(%rbx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
movq 24(%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %r10
movq %r9, %rax
mulq %r11
movq %rax, 24(%r12)
mulq %rsi
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %r10
leaq glob_data + 136(%rip), %rsi
movq 8(%r12), %rax
mulq 24(%rsi)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 16(%r12), %rax
mulq 16(%rsi)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 24(%r12), %rax
mulq 8(%rsi)
addq %rax, %rcx
adcq %rdx, %r10
adcq $0, %r9
movq 32(%r13), %rax
addq %rax, %rcx
adcq %r8, %r10
adcq $0, %r9
movq %rcx, (%r12)
xorq %rcx, %rcx
leaq glob_data + 136(%rip), %rsi
movq 16(%r12), %rax
mulq 24(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 24(%r12), %rax
mulq 16(%rsi)
addq %rax, %r10
adcq %rdx, %r9
adcq $0, %rcx
movq 40(%r13), %rax
addq %rax, %r10
adcq %r8, %r9
adcq $0, %rcx
movq %r10, 8(%r12)
xorq %rsi, %rsi
leaq glob_data + 136(%rip), %rdx
movq 24(%r12), %rax
mulq 24(%rdx)
addq %rax, %r9
adcq %rdx, %rcx
adcq $0, %rsi
movq 48(%r13), %rax
addq %rax, %r9
adcq %r8, %rcx
adcq $0, %rsi
movq %r9, 16(%r12)
xorq %rax, %rax
addq 56(%r13), %rcx
movq %rcx, 24(%r12)
movq (%r12), %rax
movq %rax, (%rsp)
movq 8(%r12), %rax
movq %rax, 8(%rsp)
movq 16(%r12), %rax
movq %rax, 16(%rsp)
movq 24(%r12), %rax
movq %rax, 24(%rsp)
movq %rsp, %rax
leaq glob_data + 104(%rip), %rcx
movq (%rcx), %rdx
addq %rdx, (%rax)
movq 8(%rcx), %rdx
adcq %rdx, 8(%rax)
movq 16(%rcx), %rdx
adcq %rdx, 16(%rax)
movq 24(%rcx), %rcx
adcq %rcx, 24(%rax)
movq (%r12), %rcx
cmovb (%rax), %rcx
movq %rcx, (%r12)
movq 8(%r12), %rcx
cmovb 8(%rax), %rcx
movq %rcx, 8(%r12)
movq 16(%r12), %rcx
cmovb 16(%rax), %rcx
movq %rcx, 16(%r12)
movq 24(%r12), %rcx
cmovb 24(%rax), %rcx
movq %rcx, 24(%r12)
jmp *%rbp
L_fp_sub$1:
movq (%rdx), %rsi
subq %rsi, (%rax)
movq 8(%rdx), %rsi
sbbq %rsi, 8(%rax)
movq 16(%rdx), %rsi
sbbq %rsi, 16(%rax)
movq 24(%rdx), %rdx
sbbq %rdx, 24(%rax)
leaq glob_data + 136(%rip), %rdx
movq (%rdx), %rsi
movq %rsi, (%rsp)
movq 8(%rdx), %rsi
movq %rsi, 8(%rsp)
movq 16(%rdx), %rsi
movq %rsi, 16(%rsp)
movq 24(%rdx), %rdx
movq %rdx, 24(%rsp)
movq $0, %rdx
movq (%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, (%rsp)
movq 8(%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, 8(%rsp)
movq 16(%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, 16(%rsp)
movq 24(%rsp), %rsi
cmovnb %rdx, %rsi
movq %rsi, 24(%rsp)
movq %rsp, %rdx
movq (%rdx), %rsi
addq %rsi, (%rax)
movq 8(%rdx), %rsi
adcq %rsi, 8(%rax)
movq 16(%rdx), %rsi
adcq %rsi, 16(%rax)
movq 24(%rdx), %rdx
adcq %rdx, 24(%rax)
jmp *%rcx
L_fp_add$1:
movq (%rdx), %rsi
addq %rsi, (%rax)
movq 8(%rdx), %rsi
adcq %rsi, 8(%rax)
movq 16(%rdx), %rsi
adcq %rsi, 16(%rax)
movq 24(%rdx), %rdx
adcq %rdx, 24(%rax)
movq (%rax), %rdx
movq %rdx, (%rsp)
movq 8(%rax), %rdx
movq %rdx, 8(%rsp)
movq 16(%rax), %rdx
movq %rdx, 16(%rsp)
movq 24(%rax), %rdx
movq %rdx, 24(%rsp)
movq %rsp, %rdx
leaq glob_data + 104(%rip), %rsi
movq (%rsi), %r8
addq %r8, (%rdx)
movq 8(%rsi), %r8
adcq %r8, 8(%rdx)
movq 16(%rsi), %r8
adcq %r8, 16(%rdx)
movq 24(%rsi), %rsi
adcq %rsi, 24(%rdx)
movq (%rax), %rsi
cmovb (%rdx), %rsi
movq %rsi, (%rax)
movq 8(%rax), %rsi
cmovb 8(%rdx), %rsi
movq %rsi, 8(%rax)
movq 16(%rax), %rsi
cmovb 16(%rdx), %rsi
movq %rsi, 16(%rax)
movq 24(%rax), %rsi
cmovb 24(%rdx), %rsi
movq %rsi, 24(%rax)
jmp *%rcx
L_bn_sqrn$1:
movq (%r8), %rax
mulq %rax
movq %rax, (%r9)
movq %rdx, %r10
xorq %rsi, %rsi
xorq %rdi, %rdi
movq (%r8), %rax
movq 8(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rsi
adcq %r11, %rdi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 8(%r9)
movq (%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r11, %r10
movq 8(%r8), %rax
mulq %rax
addq %rax, %rsi
adcq %rdx, %rdi
adcq $0, %r10
movq %rsi, %rax
xorq %rsi, %rsi
movq %rax, 16(%r9)
movq (%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rdi
adcq %rdx, %r10
adcq %r11, %rsi
movq 8(%r8), %rax
movq 16(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rdi
adcq %rdx, %r10
adcq %r11, %rsi
movq %rdi, %rax
xorq %rdi, %rdi
movq %rax, 24(%r9)
movq 8(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %r10
adcq %rdx, %rsi
adcq %r11, %rdi
movq 16(%r8), %rax
mulq %rax
addq %rax, %r10
adcq %rdx, %rsi
adcq $0, %rdi
movq %r10, %rax
xorq %r10, %r10
movq %rax, 32(%r9)
movq 16(%r8), %rax
movq 24(%r8), %rdx
mulq %rdx
movq %rax, %r11
shlq $1, %rax
shldq $1, %r11, %rdx
movq $0, %r11
adcq %r11, %r11
addq %rax, %rsi
adcq %rdx, %rdi
adcq %r11, %r10
xorq %r11, %r11
movq %rsi, 40(%r9)
movq 24(%r8), %rax
mulq %rax
addq %rax, %rdi
adcq %rdx, %r10
adcq $0, %r11
xorq %rax, %rax
movq %rdi, 48(%r9)
movq %r10, 56(%r9)
jmp *%rcx
L_bn_muln$1:
movq (%r8), %rax
mulq (%rbx)
movq %rax, (%r9)
movq %rdx, %rsi
xorq %rcx, %rcx
xorq %rdi, %rdi
movq (%r8), %rax
mulq 8(%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
movq 8(%r8), %rax
mulq (%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
xorq %r11, %r11
movq %rsi, 8(%r9)
movq (%r8), %rax
mulq 16(%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
movq 8(%r8), %rax
mulq 8(%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
movq 16(%r8), %rax
mulq (%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
xorq %rsi, %rsi
movq %rcx, 16(%r9)
movq (%r8), %rax
mulq 24(%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
movq 8(%r8), %rax
mulq 16(%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
movq 16(%r8), %rax
mulq 8(%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
movq 24(%r8), %rax
mulq (%rbx)
addq %rax, %rdi
adcq %rdx, %r11
adcq $0, %rsi
xorq %rcx, %rcx
movq %rdi, 24(%r9)
movq 8(%r8), %rax
mulq 24(%rbx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %rcx
movq 16(%r8), %rax
mulq 16(%rbx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %rcx
movq 24(%r8), %rax
mulq 8(%rbx)
addq %rax, %r11
adcq %rdx, %rsi
adcq $0, %rcx
xorq %rdi, %rdi
movq %r11, 32(%r9)
movq 16(%r8), %rax
mulq 24(%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
movq 24(%r8), %rax
mulq 16(%rbx)
addq %rax, %rsi
adcq %rdx, %rcx
adcq $0, %rdi
xorq %r11, %r11
movq %rsi, 40(%r9)
movq 24(%r8), %rax
mulq 24(%rbx)
addq %rax, %rcx
adcq %rdx, %rdi
adcq $0, %r11
xorq %rax, %rax
movq %rcx, 48(%r9)
movq %rdi, 56(%r9)
jmp *%r10
L_bn_subc$1:
movq (%rcx), %rax
subq %rax, (%rdx)
movq 8(%rcx), %rax
sbbq %rax, 8(%rdx)
movq 16(%rcx), %rax
sbbq %rax, 16(%rdx)
movq 24(%rcx), %rax
sbbq %rax, 24(%rdx)
jmp *%rsi
L_bn_addc$1:
movq (%rcx), %rax
addq %rax, (%rdx)
movq 8(%rcx), %rax
adcq %rax, 8(%rdx)
movq 16(%rcx), %rax
adcq %rax, 16(%rdx)
movq 24(%rcx), %rax
adcq %rax, 24(%rdx)
jmp *%rsi
L_bn_test0$1:
movq (%rcx), %rax
orq 8(%rcx), %rax
orq 16(%rcx), %rax
orq 24(%rcx), %rax
andq %rax, %rax
jmp *%rdx
L_bn_eq$1:
movq $0, %rdx
movq $1, %rsi
movq $0, %rdi
movq (%rax), %r8
xorq (%rcx), %r8
orq %r8, %rdi
movq 8(%rax), %r8
xorq 8(%rcx), %r8
orq %r8, %rdi
movq 16(%rax), %r8
xorq 16(%rcx), %r8
orq %r8, %rdi
movq 24(%rax), %rax
xorq 24(%rcx), %rax
orq %rax, %rdi
andq %rdi, %rdi
cmove %rsi, %rdx
jmp *%r9
.data
.p2align 5
_glob_data:
glob_data:
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 16
.byte -32
.byte 15
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -4
.byte 3
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -1
.byte -2
.byte -2
.byte -2
.byte -2
.byte -2
.byte -2
.byte -2
.byte -1
.byte -2
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte 63
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -1
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
.byte -64
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte 1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte -1
.byte 63
.byte 0
.byte 0
.byte 0
.byte 0
.byte 0
|
MertensFlo/FeRTOS | 2,687 | fe_osi/src/riscv32.s | .option push
.option norelax
.section .text.asm
.align 2
.globl do_exit
.globl do_sleep
.globl do_alloc
.globl do_dealloc
.globl do_block
.globl do_task_spawn
.globl do_yield
.globl ipc_publish
.globl ipc_subscribe
.globl ipc_unsubscribe
.globl ipc_get_message
.globl do_get_heap_remaining
.globl do_register_interrupt
do_exit:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x0
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_sleep:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x1
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_alloc:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x2
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_dealloc:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x3
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_block:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x4
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_task_spawn:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x5
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_yield:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x6
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
ipc_publish:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x7
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
ipc_subscribe:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x8
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
ipc_unsubscribe:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0x9
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
ipc_get_message:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0xa
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_get_heap_remaining:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0xb
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
do_register_interrupt:
addi sp, sp, -16
sw ra, 12(sp)
sw fp, 8(sp)
addi fp, sp, 16
li a7, 0xc
ecall
lw fp, 8(sp)
lw ra, 12(sp)
addi sp, sp, 16
ret
.option pop
|
MertensFlo/FeRTOS | 1,338 | fe_osi/src/arm.s | .syntax unified
.section .text.asm
.global do_exit
.global do_sleep
.global do_alloc
.global do_dealloc
.global do_block
.global do_task_spawn
.global do_yield
.global ipc_publish
.global ipc_subscribe
.global ipc_unsubscribe
.global ipc_get_message
.global do_get_heap_remaining
.global do_register_interrupt
.thumb_func
do_exit:
PUSH { LR }
svc 0x0
POP { PC }
.thumb_func
do_sleep:
PUSH { LR }
svc 0x1
POP { PC }
.thumb_func
do_alloc:
PUSH { LR }
svc 0x2
POP { PC }
.thumb_func
do_dealloc:
PUSH { LR }
svc 0x3
POP { PC }
.thumb_func
do_block:
PUSH { LR }
svc 0x4
POP { PC }
.thumb_func
do_task_spawn:
PUSH { LR }
svc 0x5
POP { PC }
.thumb_func
do_yield:
PUSH { LR }
svc 0x6
POP { PC }
.thumb_func
ipc_publish:
PUSH { LR }
svc 0x7
POP { PC }
.thumb_func
ipc_subscribe:
PUSH { LR }
svc 0x8
POP { PC }
.thumb_func
ipc_unsubscribe:
PUSH { LR }
svc 0x9
POP { PC }
.thumb_func
ipc_get_message:
PUSH { LR }
svc 0xa
POP { PC }
.thumb_func
do_get_heap_remaining:
PUSH { LR }
svc 0xb
POP { PC }
.thumb_func
do_register_interrupt:
PUSH { LR }
svc 0xc
POP { PC }
|
MertensFlo/FeRTOS | 2,469 | fe_rtos/src/arch/arm/arm_syscall.s | .syntax unified
.section .text.asm
.weak sys_exit
.weak sys_sleep
.weak sys_alloc
.weak sys_dealloc
.weak sys_block
.weak sys_task_spawn
.weak sys_yield
.weak sys_ipc_publish
.weak sys_ipc_subscribe
.weak sys_ipc_unsubscribe
.weak sys_ipc_get_message
.weak sys_get_heap_remaining
.weak sys_interrupt_register
.global svc_handler
.equ max_svc, 12
///////////////////////////////////////////////////////////////////////////////
// Arm Cortex-M interrupt stack frame order:
// high address: xPSR
// | PC
// | LR
// | R12
// | R3
// | R2
// | R1
// low address: R0
///////////////////////////////////////////////////////////////////////////////
.thumb_func
//Do not overwrite R0-R3 because they hold the syscall params
svc_handler:
//////////////////////////////
//Retrieve the syscall number
//////////////////////////////
//Find the stacked PC
//Offest is 24(decimal) + (registers pushed * 4)
LDR R0, [SP, 0x18]
//Get the svc instruction
LDRH R0, [R0, -2]
//Get the syscall number from the instruction
BIC R0, R0, 0xFF00
//////////////////////////////
//Get the syscall address
//////////////////////////////
//Determine if the syscall number is valid
CMP R0, max_svc
BGT svc_handler_end
//If it is valid, grab the address of the function
ADR R1, svc_addr_table
LDR R0, [R1, R0, LSL 2]
//////////////////////////////
//Fix the stack
//////////////////////////////
//The old PC in the ISR stackframe is the new LR in the ISR stackframe
LDR R1, [SP, 0x18]
//Setting the LSB of LR to 1 indicates that we are in thumb mode
ORR R1, R1, 1
STR R1, [SP, 0x14]
//The new PC in the ISR stackframe is where we're jumping to
STR R0, [SP, 0x18]
.thumb_func
svc_handler_end:
BX LR
.align 4
svc_addr_table:
.word sys_exit // 0
.word sys_sleep // 1
.word sys_alloc // 2
.word sys_dealloc // 3
.word sys_block // 4
.word sys_task_spawn // 5
.word sys_yield // 6
.word sys_ipc_publish // 7
.word sys_ipc_subscribe // 8
.word sys_ipc_unsubscribe // 9
.word sys_ipc_get_message // 10
.word sys_get_heap_remaining // 11
.word sys_interrupt_register // 12
|
MertensFlo/FeRTOS | 4,010 | fe_rtos/src/arch/riscv32/riscv32.s | .option push
.option norelax
.section .text.asm
.align 2
.local interrupt_switch
.local Reset
.local syscall_handler
.local get_cur_task
.local set_cur_task
.local get_next_task
.global context_switch
.global disable_interrupts
.global enable_interrupts
.global set_mtie
.global get_mepc
.global set_mepc
.global setup_interrupts
.global _start
.global trigger_context_switch
.equ regsize, 0x4
.equ mie_init, 0xB0B
.equ mie_mtie, 0xB0
.equ mstatus_mie, 0xB
.equ mcause_uecall, 0x8
.equ mcause_mecall, 0xB
context_switch:
# a0 - Current Task
# S1 - Next Task
#Save the current mepc
csrr t0, mepc
sw t0, (sp)
call get_next_task
mv s1, a0
call get_cur_task
#Switch the stack pointers
#Save the current stack pointer
sw sp, (a0)
#Load the new stack pointer
lw sp, (s1)
# Grab the new mepc
lw t0, (sp)
csrw mepc, t0
#Set CUR_TASK = NEXT_TASK
mv a0, s1
call set_cur_task
j interrupt_handler_end
.align 2
interrupt_handler:
#Push everything onto the stack
sw x1, -1*regsize(sp)
# No need to save the stack pointer
sw x3, -3*regsize(sp)
sw x4, -4*regsize(sp)
sw x5, -5*regsize(sp)
sw x6, -6*regsize(sp)
sw x7, -7*regsize(sp)
sw x8, -8*regsize(sp)
sw x9, -9*regsize(sp)
sw x10, -10*regsize(sp)
sw x11, -11*regsize(sp)
sw x12, -12*regsize(sp)
sw x13, -13*regsize(sp)
sw x14, -14*regsize(sp)
sw x15, -15*regsize(sp)
sw x16, -16*regsize(sp)
sw x17, -17*regsize(sp)
sw x18, -18*regsize(sp)
sw x19, -19*regsize(sp)
sw x20, -20*regsize(sp)
sw x21, -21*regsize(sp)
sw x22, -22*regsize(sp)
sw x23, -23*regsize(sp)
sw x24, -24*regsize(sp)
sw x25, -25*regsize(sp)
sw x26, -26*regsize(sp)
sw x27, -27*regsize(sp)
sw x28, -28*regsize(sp)
sw x29, -29*regsize(sp)
sw x30, -30*regsize(sp)
sw x31, -31*regsize(sp)
addi sp, sp, -32*regsize
#Grab the cause of the interrupt
csrr t0, mcause
#If the interrupt is for a syscall, handle that separately
li t1, mcause_mecall
beq t0, t1, interrupt_handler_syscall
li t1, mcause_uecall
beq t0, t1, interrupt_handler_syscall
mv a0, t0
call interrupt_switch
j interrupt_handler_end
interrupt_handler_syscall:
call syscall_handler
interrupt_handler_end:
#Restore the registers
addi sp, sp, 32*regsize
lw x1, -1*regsize(sp)
# No need to load the stack pointer
lw x3, -3*regsize(sp)
lw x4, -4*regsize(sp)
lw x5, -5*regsize(sp)
lw x6, -6*regsize(sp)
lw x7, -7*regsize(sp)
lw x8, -8*regsize(sp)
lw x9, -9*regsize(sp)
lw x10, -10*regsize(sp)
lw x11, -11*regsize(sp)
lw x12, -12*regsize(sp)
lw x13, -13*regsize(sp)
lw x14, -14*regsize(sp)
lw x15, -15*regsize(sp)
lw x16, -16*regsize(sp)
lw x17, -17*regsize(sp)
lw x18, -18*regsize(sp)
lw x19, -19*regsize(sp)
lw x20, -20*regsize(sp)
lw x21, -21*regsize(sp)
lw x22, -22*regsize(sp)
lw x23, -23*regsize(sp)
lw x24, -24*regsize(sp)
lw x25, -25*regsize(sp)
lw x26, -26*regsize(sp)
lw x27, -27*regsize(sp)
lw x28, -28*regsize(sp)
lw x29, -29*regsize(sp)
lw x30, -30*regsize(sp)
lw x31, -31*regsize(sp)
mret
setup_interrupts:
#Set the interrupt handler
la t0, interrupt_handler
csrw mtvec, t0
#Enable all of the interrupts except for the timer.
#The timer will be enabled when the scheduling starts.
li t0, mie_init
csrs mie, t0
csrsi mstatus, mstatus_mie
ret
set_mtie:
li t0, mie_mtie
csrs mie, t0
ret
get_mepc:
csrr a0, mepc
ret
set_mepc:
csrw mepc, a0
ret
disable_interrupts:
csrci mstatus, mstatus_mie
ret
enable_interrupts:
csrsi mstatus, mstatus_mie
ret
trigger_context_switch:
addi sp, sp, -16
sw ra, 12(sp)
li a7, 0xff
ecall
lw ra, 12(sp)
addi sp, sp, 16
ret
.section .init, "ax"
_start:
la sp, __stack_top
call Reset
.option pop
|
MertensFlo/FeRTOS | 1,680 | fe_rtos/src/arch/riscv32/riscv32_syscall.s | .option push
.option norelax
.section .text.asm
.align 2
.local context_switch
.local sys_exit
.local sys_sleep
.local sys_alloc
.local sys_dealloc
.local sys_block
.local sys_task_spawn
.local sys_yield
.local sys_ipc_publish
.local sys_ipc_subscribe
.local sys_ipc_get_message
.local sys_get_heap_remaining
.local sys_interrupt_register
.global syscall_handler
.equ context_switch_number, 0xFF
.equ max_syscall, 12
syscall_handler:
#The syscall number is in a7
#First, since mepc points to the ecall instruction, we need to increment mepc
csrr t0, mepc
addi t0, t0, 4
csrw mepc, t0
#Check if this is a context switch
li t1, context_switch_number
beq a7, t1, context_switch
#Make sure a7 has a valid syscall number
li t1, max_syscall
bgt a7, t1, syscall_handler_end
#Set RA to the previous pc
sw t0, 31*4(sp)
##############################
#Set the new PC to the syscall
##############################
la t0, syscall_addr_table
#Calculate the offset in the address table
sll t1, a7, 2
add t0, t0, t1
lw t0, (t0)
csrw mepc, t0
syscall_handler_end:
ret
.align 2
syscall_addr_table:
.word sys_exit # 0
.word sys_sleep # 1
.word sys_alloc # 2
.word sys_dealloc # 3
.word sys_block # 4
.word sys_task_spawn # 5
.word sys_yield # 6
.word sys_ipc_publish # 7
.word sys_ipc_subscribe # 8
.word sys_ipc_unsubscribe # 9
.word sys_ipc_get_message # 10
.word sys_get_heap_remaining # 11
.word sys_interrupt_register # 12
.option pop
|
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