repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
mary-phuong/intercode-ctf | 1,136 | data/ctf/task_assets/81/chall_3.S | .arch armv8-a
.file "chall_3.c"
.text
.align 2
.global func1
.type func1, %function
func1:
stp x29, x30, [sp, -48]!
add x29, sp, 0
str w0, [x29, 28]
str wzr, [x29, 44]
b .L2
.L4:
ldr w0, [x29, 28]
and w0, w0, 1
cmp w0, 0
beq .L3
ldr w0, [x29, 44]
bl func2
str w0, [x29, 44]
.L3:
ldr w0, [x29, 28]
lsr w0, w0, 1
str w0, [x29, 28]
.L2:
ldr w0, [x29, 28]
cmp w0, 0
bne .L4
ldr w0, [x29, 44]
ldp x29, x30, [sp], 48
ret
.size func1, .-func1
.align 2
.global func2
.type func2, %function
func2:
sub sp, sp, #16
str w0, [sp, 12]
ldr w0, [sp, 12]
add w0, w0, 3
add sp, sp, 16
ret
.size func2, .-func2
.section .rodata
.align 3
.LC0:
.string "Result: %ld\n"
.text
.align 2
.global main
.type main, %function
main:
stp x29, x30, [sp, -48]!
add x29, sp, 0
str w0, [x29, 28]
str x1, [x29, 16]
ldr x0, [x29, 16]
add x0, x0, 8
ldr x0, [x0]
bl atoi
bl func1
str w0, [x29, 44]
adrp x0, .LC0
add x0, x0, :lo12:.LC0
ldr w1, [x29, 44]
bl printf
nop
ldp x29, x30, [sp], 48
ret
.size main, .-main
.ident "GCC: (Ubuntu/Linaro 7.5.0-3ubuntu1~18.04) 7.5.0"
.section .note.GNU-stack,"",@progbits
|
MassinissaDjellouli/CTFStuff | 23,728 | tools/ghidra_11.2.1_PUBLIC/Ghidra/Processors/HCS08/data/test-vectors/HCS08_tv.s | .hcs08
.area DIRECT (PAG)
;.setdp 0, DIRECT
;low_data1:
;.ds 1
.area PROGRAM (ABS)
.org 0x80
LOW_SUB_TEST:
RTS
.org 0x2000
HIGH_SUB_TEST:
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
ADC #0xFE
ADC *0xFE
ADC 0xFEDC
ADC 0xFEDC,X
ADC 0xFE,X
ADC ,X
; @if defined(HCS08) || defined(HC08)
; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP
ADC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP
ADC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
ADD #0xFE
ADD *0xFE
ADD 0xFEDC
ADD 0xFEDC,X
ADD 0xFE,X
ADD ,X
; @if defined(HCS08) || defined(HC08)
; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP
ADD 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP
ADD 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : AIS iopr8is is op=0xA7; iopr8is
AIS #0x7F
AIS #-0x7F
; @if defined(HCS08) || defined(HC08)
; : AIX iopr8is is op=0xAF; iopr8is
AIX #0x7F
AIX #-0x7F
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1
AND #0xFE
AND *0xFE
AND 0xFEDC
AND 0xFEDC,X
AND 0xFE,X
AND ,X
; @if defined(HCS08) || defined(HC08)
; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP
AND 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP
AND 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLA is op=0x48
ASLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLX is op=0x58
ASLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
ASL *0xFE
ASL 0xFE,X
ASL ,X
; @if defined(HCS08) || defined(HC08)
; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP
ASL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRA is op=0x47
ASRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRX is op=0x57
ASRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
ASR *0xFE
ASR 0xFE,X
ASR ,X
; @if defined(HCS08) || defined(HC08)
; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP
ASR 0xFE,S
BACKWARDS1:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCC REL is op=0x24; REL
BCC BACKWARDS1
BCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8
BCLR #0, *0xFE
BCLR #1, *0xED
BCLR #2, *0xDC
BCLR #3, *0xCB
BCLR #4, *0xBA
BCLR #5, *0xA9
BCLR #6, *0x98
BCLR #7, *0x87
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCS REL is op=0x25; REL
BCS BACKWARDS1
BCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BEQ REL is op=0x27; REL
BEQ BACKWARDS1
BEQ FORWARDS1
; @if defined(HCS08) || defined(HC08)
; : BGE REL is op=0x90; REL
BGE BACKWARDS1
BGE FORWARDS1
; @if defined(HCS08)
; : BGND is op=0x82
BGND
; @if defined(HCS08) || defined(HC08)
; : BGT REL is op=0x92; REL
BGT BACKWARDS1
BGT FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCC REL is op=0x28; REL
BHCC BACKWARDS1
BHCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCS REL is op=0x29; REL
BHCS BACKWARDS1
BHCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHI REL is op=0x22; REL
BHI BACKWARDS1
BHI FORWARDS1
; :BHS REL is op=0x24; REL See BCC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIH REL is op=0x2F; REL
BIH BACKWARDS1
BIH FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIL REL is op=0x2E; REL
BIL BACKWARDS1
BIL FORWARDS1
FORWARDS1:
BACKWARDS2:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
BIT #0xFE
BIT *0xFE
BIT 0xFEDC
BIT 0xFEDC,X
BIT 0xFE,X
BIT ,X
; @if defined(HCS08) || defined(HC08)
; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP
BIT 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP
BIT 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : BLE REL is op=0x93; REL
BLE BACKWARDS2
BLE FORWARDS2
; :BLO REL is op=0x25; REL see BCS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BLS REL is op=0x23; REL
BLS BACKWARDS2
BLS FORWARDS2
; @if defined(HCS08) || defined(HC08)
; : BLT REL is op=0x91; REL
BLT BACKWARDS2
BLT FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMC REL is op=0x2C; REL
BMC BACKWARDS2
BMC FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMI REL is op=0x2B; REL
BMI BACKWARDS2
BMI FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMS REL is op=0x2D; REL
BMS BACKWARDS2
BMS FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BNE REL is op=0x26; REL
BNE BACKWARDS2
BNE FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BPL REL is op=0x2A; REL
BPL BACKWARDS2
BPL FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRA REL is op=0x20; REL
BRA BACKWARDS2
BRA FORWARDS2
FORWARDS2:
BACKWARDS3:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL
BRCLR #0, *0xFE,BACKWARDS3
BRCLR #1, *0xED,BACKWARDS3
BRCLR #2, *0xDC,BACKWARDS3
BRCLR #3, *0xCB,BACKWARDS3
BRCLR #4, *0xBA,BACKWARDS3
BRCLR #5, *0xA9,BACKWARDS3
BRCLR #6, *0x98,BACKWARDS3
BRCLR #7, *0x87,BACKWARDS3
BRCLR #0, *0xFE,FORWARDS3
BRCLR #1, *0xED,FORWARDS3
BRCLR #2, *0xDC,FORWARDS3
BRCLR #3, *0xCB,FORWARDS3
BRCLR #4, *0xBA,FORWARDS3
BRCLR #5, *0xA9,FORWARDS3
BRCLR #6, *0x98,FORWARDS3
BRCLR #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; branch never is a two-byte nop
; : BRN REL is op=0x21; REL
BRN BACKWARDS3
BRN FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL
BRSET #0, *0xFE,BACKWARDS3
BRSET #1, *0xED,BACKWARDS3
BRSET #2, *0xDC,BACKWARDS3
BRSET #3, *0xCB,BACKWARDS3
BRSET #4, *0xBA,BACKWARDS3
BRSET #5, *0xA9,BACKWARDS3
BRSET #6, *0x98,BACKWARDS3
BRSET #7, *0x87,BACKWARDS3
BRSET #0, *0xFE,FORWARDS3
BRSET #1, *0xED,FORWARDS3
BRSET #2, *0xDC,FORWARDS3
BRSET #3, *0xCB,FORWARDS3
BRSET #4, *0xBA,FORWARDS3
BRSET #5, *0xA9,FORWARDS3
BRSET #6, *0x98,FORWARDS3
BRSET #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8
BSET #0, *0xFE
BSET #1, *0xED
BSET #2, *0xDC
BSET #3, *0xCB
BSET #4, *0xBA
BSET #5, *0xA9
BSET #6, *0x98
BSET #7, *0x87
FORWARDS3:
BACKWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSR REL is op=0xAD; REL
BSR BACKWARDS4
BSR FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL
CBEQ *0xFE, BACKWARDS4
CBEQ *0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL
CBEQA #0xFE, BACKWARDS4
CBEQA #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL
CBEQX #0xFE, BACKWARDS4
CBEQX #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8, X"+", REL is (op=0x61) & X; oprx8; REL
CBEQ *0xFE, X+, BACKWARDS4
CBEQ *0xFE, X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ ","X"+", REL is (op=0x71) & X; REL
CBEQ ,X+, BACKWARDS4
CBEQ ,X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL
CBEQ 0xFE,S, BACKWARDS4
CBEQ 0xFE,S, FORWARDS4
FORWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLC is op=0x98
CLC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLI is op=0x9A
CLI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRA is op=0x4F
CLRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRX is op=0x5F
CLRX
; @if defined(HCS08) || defined(HC08)
; : CLRH is op=0x8C
CLRH
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1
CLR *0xFE
CLR 0xFE,X
CLR ,X
; @if defined(HCS08) || defined(HC08)
; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP
CLR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
CMP #0xFE
CMP *0xFE
CMP 0xFEDC
CMP 0xFEDC,X
CMP 0xFE,X
CMP ,X
; @if defined(HCS08) || defined(HC08)
; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP
CMP 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP
CMP 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMA is op=0x43
COMA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMX is op=0x53
COMX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
COM *0xFE
COM 0xFE,X
COM ,X
; @if defined(HCS08) || defined(HC08)
; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP
COM 0xFE,S
; @if defined(HCS08)
; : CPHX opr16a_16 is (op=0x3E); opr16a_16
CPHX 0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX iopr16i is (op=0x65); iopr16i
CPHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX opr8a_16 is (op=0x75); opr8a_16
CPHX *0xFE
; @if defined(HCS08)
; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP
CPHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
CPX #0xFE
CPX *0xFE
CPX 0xFEDC
CPX 0xFEDC,X
CPX 0xFE,X
CPX ,X
; @if defined(HCS08) || defined(HC08)
; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP
CPX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP
CPX 0xFE,S
BACKWARDS5:
; @if defined(HCS08) || defined(HC08)
; : DAA is op=0x72
DAA
; @if defined(HCS08) || defined(HC08)
; : DBNZA REL is op=0x4B; REL
DBNZA BACKWARDS5
DBNZA FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZX REL is op=0x5B; REL
DBNZX BACKWARDS5
DBNZX FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL
DBNZ *0xFE, BACKWARDS5
DBNZ 0xFE,X, BACKWARDS5
DBNZ ,X, BACKWARDS5
DBNZ *0xFE, FORWARDS5
DBNZ 0xFE,X, FORWARDS5
DBNZ ,X, FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL
DBNZ 0xFE,S, BACKWARDS5
DBNZ 0xFE,S, FORWARDS5
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECA is op=0x4A
DECA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECX is op=0x5A
DECX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
DEC *0xFE
DEC 0xFE,X
DEC ,X
; @if defined(HCS08) || defined(HC08)
; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP
DEC 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : DIV is op=0x52
DIV
FORWARDS5:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
EOR #0xFE
EOR *0xFE
EOR 0xFEDC
EOR 0xFEDC,X
EOR 0xFE,X
EOR ,X
; @if defined(HCS08) || defined(HC08)
; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP
EOR 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP
EOR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCA is op=0x4C
INCA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCX is op=0x5C
INCX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
INC *0xFE
INC 0xFE,X
INC ,X
; @if defined(HCS08) || defined(HC08)
; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP
INC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR
JMP *LOW_SUB_TEST
JMP HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI
JMP 0xFEDC,X
JMP 0xFE,X
JMP ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR
JSR *LOW_SUB_TEST
JSR HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI
JSR 0xFEDC,X
JSR 0xFE,X
JSR ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1
LDA #0xFE
LDA *0xFE
LDA 0xFEDC
LDA 0xFEDC,X
LDA 0xFE,X
LDA ,X
; @if defined(HCS08) || defined(HC08)
; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP
LDA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP
LDA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : LDHX iopr16i is (op=0x45); iopr16i
LDHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : LDHX opr8a_16 is (op=0x55); opr8a_16
LDHX *0xFE
; @if defined(HCS08)
; : LDHX opr16a_16 is (op=0x32); opr16a_16
LDHX 0xFEDC
; @if defined(HCS08)
; : LDHX ","X is (op16=0x9EAE) & X
LDHX ,X
; @if defined(HCS08)
; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X
LDHX 0xFEDC,X
; @if defined(HCS08)
; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X
LDHX 0xFE,X
; @if defined(HCS08)
; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP
LDHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1
LDX #0xFE
LDX *0xFE
LDX 0xFEDC
LDX 0xFEDC,X
LDX 0xFE,X
LDX ,X
; @if defined(HCS08) || defined(HC08)
; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP
LDX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP
LDX 0xFE,S
; ## Logical Shift left is same as arithmetic shift left
; :LSLA is op=0x48
; :LSLX is op=0x58
; :LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRA is op=0x44
LSRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRX is op=0x54
LSRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
LSR *0xFE
LSR 0xFE,X
LSR ,X
; @if defined(HCS08) || defined(HC08)
; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP
LSR 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a
MOV *0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X
MOV 0xFE, X+
; @if defined(HCS08) || defined(HC08)
; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a
MOV #0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a
MOV ,X+, *0xFE
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : MUL is op=0x42
MUL
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGA is op=0x40
NEGA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGX is op=0x50
NEGX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
NEG *0xFE
NEG 0xFE,X
NEG ,X
; @if defined(HCS08) || defined(HC08)
; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP
NEG 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NOP is op = 0x9D
NOP
; @if defined(HCS08) || defined(HC08)
; : NSA is op = 0x62
NSA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1
ORA #0xFE
ORA *0xFE
ORA 0xFEDC
ORA 0xFEDC,X
ORA 0xFE,X
ORA ,X
; @if defined(HCS08) || defined(HC08)
; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP
ORA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP
ORA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : PSHA is op = 0x87
PSHA
; @if defined(HCS08) || defined(HC08)
; : PSHH is op = 0x8B
PSHH
; @if defined(HCS08) || defined(HC08)
; : PSHX is op = 0x89
PSHX
; @if defined(HCS08) || defined(HC08)
; : PULA is op = 0x86
PULA
; @if defined(HCS08) || defined(HC08)
; : PULH is op = 0x8A
PULH
; @if defined(HCS08) || defined(HC08)
; : PULX is op = 0x88
PULX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLA is op=0x49
ROLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLX is op=0x59
ROLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
ROL *0xFE
ROL 0xFE,X
ROL ,X
; @if defined(HCS08) || defined(HC08)
; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP
ROL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORA is op=0x46
RORA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORX is op=0x56
RORX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
ROR *0xFE
ROR 0xFE,X
ROR ,X
; @if defined(HCS08) || defined(HC08)
; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP
ROR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RSP is op = 0x9C
RSP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTI is op = 0x80
RTI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTS is op = 0x81
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
SBC #0xFE
SBC *0xFE
SBC 0xFEDC
SBC 0xFEDC,X
SBC 0xFE,X
SBC ,X
; @if defined(HCS08) || defined(HC08)
; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP
SBC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP
SBC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEC is op = 0x99
SEC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEI is op = 0x9B
SEI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1
STA *0xFE
STA 0xFEDC
STA 0xFEDC,X
STA 0xFE,X
STA ,X
; @if defined(HCS08) || defined(HC08)
; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP
STA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP
STA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : STHX opr8a_16 is (op=0x35); opr8a_16
STHX *0xFE
; @if defined(HCS08)
; : STHX opr16a_16 is (op=0x96); opr16a_16
STHX 0xFEDC
; @if defined(HCS08)
; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP
STHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STOP is op=0x8E
STOP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1
STX *0xFE
STX 0xFEDC
STX 0xFEDC,X
STX 0xFE,X
STX ,X
; @if defined(HCS08) || defined(HC08)
; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP
STX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP
STX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
SUB #0xFE
SUB *0xFE
SUB 0xFEDC
SUB 0xFEDC,X
SUB 0xFE,X
SUB ,X
; @if defined(HCS08) || defined(HC08)
; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP
SUB 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP
SUB 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SWI is op=0x83
SWI
; @if defined(HCS08) || defined(HC08)
; : TAP is op=0x84
TAP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TAX is op=0x97
TAX
; @if defined(HCS08) || defined(HC08)
; : TPA is op=0x85
TPA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTA is op=0x4D
TSTA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTX is op=0x5D
TSTX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
TST *0xFE
TST 0xFE,X
TST ,X
; @if defined(HCS08) || defined(HC08)
; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP
TST 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : TSX is op=0x95
TSX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TXA is op=0x9F
TXA
; @if defined(HCS08) || defined(HC08)
; : TXS is op=0x94
TXS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : WAIT is op=0x8f
WAIT
HERE:
BRA HERE
|
MassinissaDjellouli/CTFStuff | 23,835 | tools/ghidra_11.2.1_PUBLIC/Ghidra/Processors/HCS08/data/test-vectors/HC05_tv.s | .hc05
.area DIRECT (PAG)
;.setdp 0, DIRECT
;low_data1:
;.ds 1
.area PROGRAM (ABS)
.org 0x80
LOW_SUB_TEST:
RTS
.org 0x2000
HIGH_SUB_TEST:
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
ADC #0xFE
ADC *0xFE
ADC 0xFEDC
ADC 0xFEDC,X
ADC 0xFE,X
ADC ,X
; @if defined(HCS08) || defined(HC08)
; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP
; ADC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP
; ADC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
ADD #0xFE
ADD *0xFE
ADD 0xFEDC
ADD 0xFEDC,X
ADD 0xFE,X
ADD ,X
; @if defined(HCS08) || defined(HC08)
; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP
; ADD 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP
; ADD 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : AIS iopr8is is op=0xA7; iopr8is
; AIS #0x7F
; AIS #-0x7F
; @if defined(HCS08) || defined(HC08)
; : AIX iopr8is is op=0xAF; iopr8is
; AIX #0x7F
; AIX #-0x7F
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1
AND #0xFE
AND *0xFE
AND 0xFEDC
AND 0xFEDC,X
AND 0xFE,X
AND ,X
; @if defined(HCS08) || defined(HC08)
; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP
; AND 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP
; AND 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLA is op=0x48
ASLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLX is op=0x58
ASLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
ASL *0xFE
ASL 0xFE,X
ASL ,X
; @if defined(HCS08) || defined(HC08)
; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP
; ASL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRA is op=0x47
ASRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRX is op=0x57
ASRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
ASR *0xFE
ASR 0xFE,X
ASR ,X
; @if defined(HCS08) || defined(HC08)
; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP
; ASR 0xFE,S
BACKWARDS1:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCC REL is op=0x24; REL
BCC BACKWARDS1
BCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8
BCLR #0, *0xFE
BCLR #1, *0xED
BCLR #2, *0xDC
BCLR #3, *0xCB
BCLR #4, *0xBA
BCLR #5, *0xA9
BCLR #6, *0x98
BCLR #7, *0x87
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCS REL is op=0x25; REL
BCS BACKWARDS1
BCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BEQ REL is op=0x27; REL
BEQ BACKWARDS1
BEQ FORWARDS1
; @if defined(HCS08) || defined(HC08)
; : BGE REL is op=0x90; REL
; BGE BACKWARDS1
; BGE FORWARDS1
; @if defined(HCS08)
; : BGND is op=0x82
; BGND
; @if defined(HCS08) || defined(HC08)
; : BGT REL is op=0x92; REL
; BGT BACKWARDS1
; BGT FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCC REL is op=0x28; REL
BHCC BACKWARDS1
BHCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCS REL is op=0x29; REL
BHCS BACKWARDS1
BHCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHI REL is op=0x22; REL
BHI BACKWARDS1
BHI FORWARDS1
; :BHS REL is op=0x24; REL See BCC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIH REL is op=0x2F; REL
BIH BACKWARDS1
BIH FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIL REL is op=0x2E; REL
BIL BACKWARDS1
BIL FORWARDS1
FORWARDS1:
BACKWARDS2:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
BIT #0xFE
BIT *0xFE
BIT 0xFEDC
BIT 0xFEDC,X
BIT 0xFE,X
BIT ,X
; @if defined(HCS08) || defined(HC08)
; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP
; BIT 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP
; BIT 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : BLE REL is op=0x93; REL
; BLE BACKWARDS2
; BLE FORWARDS2
; :BLO REL is op=0x25; REL see BCS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BLS REL is op=0x23; REL
BLS BACKWARDS2
BLS FORWARDS2
; @if defined(HCS08) || defined(HC08)
; : BLT REL is op=0x91; REL
; BLT BACKWARDS2
; BLT FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMC REL is op=0x2C; REL
BMC BACKWARDS2
BMC FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMI REL is op=0x2B; REL
BMI BACKWARDS2
BMI FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMS REL is op=0x2D; REL
BMS BACKWARDS2
BMS FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BNE REL is op=0x26; REL
BNE BACKWARDS2
BNE FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BPL REL is op=0x2A; REL
BPL BACKWARDS2
BPL FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRA REL is op=0x20; REL
BRA BACKWARDS2
BRA FORWARDS2
FORWARDS2:
BACKWARDS3:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL
BRCLR #0, *0xFE,BACKWARDS3
BRCLR #1, *0xED,BACKWARDS3
BRCLR #2, *0xDC,BACKWARDS3
BRCLR #3, *0xCB,BACKWARDS3
BRCLR #4, *0xBA,BACKWARDS3
BRCLR #5, *0xA9,BACKWARDS3
BRCLR #6, *0x98,BACKWARDS3
BRCLR #7, *0x87,BACKWARDS3
BRCLR #0, *0xFE,FORWARDS3
BRCLR #1, *0xED,FORWARDS3
BRCLR #2, *0xDC,FORWARDS3
BRCLR #3, *0xCB,FORWARDS3
BRCLR #4, *0xBA,FORWARDS3
BRCLR #5, *0xA9,FORWARDS3
BRCLR #6, *0x98,FORWARDS3
BRCLR #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; branch never is a two-byte nop
; : BRN REL is op=0x21; REL
BRN BACKWARDS3
BRN FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL
BRSET #0, *0xFE,BACKWARDS3
BRSET #1, *0xED,BACKWARDS3
BRSET #2, *0xDC,BACKWARDS3
BRSET #3, *0xCB,BACKWARDS3
BRSET #4, *0xBA,BACKWARDS3
BRSET #5, *0xA9,BACKWARDS3
BRSET #6, *0x98,BACKWARDS3
BRSET #7, *0x87,BACKWARDS3
BRSET #0, *0xFE,FORWARDS3
BRSET #1, *0xED,FORWARDS3
BRSET #2, *0xDC,FORWARDS3
BRSET #3, *0xCB,FORWARDS3
BRSET #4, *0xBA,FORWARDS3
BRSET #5, *0xA9,FORWARDS3
BRSET #6, *0x98,FORWARDS3
BRSET #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8
BSET #0, *0xFE
BSET #1, *0xED
BSET #2, *0xDC
BSET #3, *0xCB
BSET #4, *0xBA
BSET #5, *0xA9
BSET #6, *0x98
BSET #7, *0x87
FORWARDS3:
BACKWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSR REL is op=0xAD; REL
BSR BACKWARDS4
BSR FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL
; CBEQ *0xFE, BACKWARDS4
; CBEQ *0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL
; CBEQA #0xFE, BACKWARDS4
; CBEQA #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL
; CBEQX #0xFE, BACKWARDS4
; CBEQX #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8, X"+", REL is (op=0x61) & X; oprx8; REL
; CBEQ *0xFE, X+, BACKWARDS4
; CBEQ *0xFE, X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ ","X"+", REL is (op=0x71) & X; REL
; CBEQ ,X+, BACKWARDS4
; CBEQ ,X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL
; CBEQ 0xFE,S, BACKWARDS4
; CBEQ 0xFE,S, FORWARDS4
FORWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLC is op=0x98
CLC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLI is op=0x9A
CLI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRA is op=0x4F
CLRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRX is op=0x5F
CLRX
; @if defined(HCS08) || defined(HC08)
; : CLRH is op=0x8C
; CLRH
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1
CLR *0xFE
CLR 0xFE,X
CLR ,X
; @if defined(HCS08) || defined(HC08)
; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP
; CLR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
CMP #0xFE
CMP *0xFE
CMP 0xFEDC
CMP 0xFEDC,X
CMP 0xFE,X
CMP ,X
; @if defined(HCS08) || defined(HC08)
; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP
; CMP 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP
; CMP 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMA is op=0x43
COMA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMX is op=0x53
COMX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
COM *0xFE
COM 0xFE,X
COM ,X
; @if defined(HCS08) || defined(HC08)
; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP
; COM 0xFE,S
; @if defined(HCS08)
; : CPHX opr16a_16 is (op=0x3E); opr16a_16
; CPHX 0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX iopr16i is (op=0x65); iopr16i
; CPHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX opr8a_16 is (op=0x75); opr8a_16
; CPHX *0xFE
; @if defined(HCS08)
; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP
; CPHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
CPX #0xFE
CPX *0xFE
CPX 0xFEDC
CPX 0xFEDC,X
CPX 0xFE,X
CPX ,X
; @if defined(HCS08) || defined(HC08)
; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP
; CPX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP
; CPX 0xFE,S
BACKWARDS5:
; @if defined(HCS08) || defined(HC08)
; : DAA is op=0x72
; DAA
; @if defined(HCS08) || defined(HC08)
; : DBNZA REL is op=0x4B; REL
; DBNZA BACKWARDS5
; DBNZA FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZX REL is op=0x5B; REL
; DBNZX BACKWARDS5
; DBNZX FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL
; DBNZ *0xFE, BACKWARDS5
; DBNZ 0xFE,X, BACKWARDS5
; DBNZ ,X, BACKWARDS5
; DBNZ *0xFE, FORWARDS5
; DBNZ 0xFE,X, FORWARDS5
; DBNZ ,X, FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL
; DBNZ 0xFE,S, BACKWARDS5
; DBNZ 0xFE,S, FORWARDS5
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECA is op=0x4A
DECA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECX is op=0x5A
DECX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
DEC *0xFE
DEC 0xFE,X
DEC ,X
; @if defined(HCS08) || defined(HC08)
; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP
; DEC 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : DIV is op=0x52
; DIV
FORWARDS5:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
EOR #0xFE
EOR *0xFE
EOR 0xFEDC
EOR 0xFEDC,X
EOR 0xFE,X
EOR ,X
; @if defined(HCS08) || defined(HC08)
; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP
; EOR 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP
; EOR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCA is op=0x4C
INCA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCX is op=0x5C
INCX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
INC *0xFE
INC 0xFE,X
INC ,X
; @if defined(HCS08) || defined(HC08)
; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP
; INC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR
JMP *LOW_SUB_TEST
JMP HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI
JMP 0xFEDC,X
JMP 0xFE,X
JMP ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR
JSR *LOW_SUB_TEST
JSR HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI
JSR 0xFEDC,X
JSR 0xFE,X
JSR ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1
LDA #0xFE
LDA *0xFE
LDA 0xFEDC
LDA 0xFEDC,X
LDA 0xFE,X
LDA ,X
; @if defined(HCS08) || defined(HC08)
; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP
; LDA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP
; LDA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : LDHX iopr16i is (op=0x45); iopr16i
; LDHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : LDHX opr8a_16 is (op=0x55); opr8a_16
; LDHX *0xFE
; @if defined(HCS08)
; : LDHX opr16a_16 is (op=0x32); opr16a_16
; LDHX 0xFEDC
; @if defined(HCS08)
; : LDHX ","X is (op16=0x9EAE) & X
; LDHX ,X
; @if defined(HCS08)
; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X
; LDHX 0xFEDC,X
; @if defined(HCS08)
; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X
; LDHX 0xFE,X
; @if defined(HCS08)
; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP
; LDHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1
LDX #0xFE
LDX *0xFE
LDX 0xFEDC
LDX 0xFEDC,X
LDX 0xFE,X
LDX ,X
; @if defined(HCS08) || defined(HC08)
; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP
; LDX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP
; LDX 0xFE,S
; ## Logical Shift left is same as arithmetic shift left
; :LSLA is op=0x48
; :LSLX is op=0x58
; :LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRA is op=0x44
LSRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRX is op=0x54
LSRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
LSR *0xFE
LSR 0xFE,X
LSR ,X
; @if defined(HCS08) || defined(HC08)
; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP
; LSR 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a
; MOV *0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X
; MOV 0xFE, X+
; @if defined(HCS08) || defined(HC08)
; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a
; MOV #0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a
; MOV ,X+, *0xFE
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : MUL is op=0x42
MUL
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGA is op=0x40
NEGA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGX is op=0x50
NEGX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
NEG *0xFE
NEG 0xFE,X
NEG ,X
; @if defined(HCS08) || defined(HC08)
; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP
; NEG 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NOP is op = 0x9D
NOP
; @if defined(HCS08) || defined(HC08)
; : NSA is op = 0x62
; NSA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1
ORA #0xFE
ORA *0xFE
ORA 0xFEDC
ORA 0xFEDC,X
ORA 0xFE,X
ORA ,X
; @if defined(HCS08) || defined(HC08)
; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP
; ORA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP
; ORA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : PSHA is op = 0x87
; PSHA
; @if defined(HCS08) || defined(HC08)
; : PSHH is op = 0x8B
; PSHH
; @if defined(HCS08) || defined(HC08)
; : PSHX is op = 0x89
; PSHX
; @if defined(HCS08) || defined(HC08)
; : PULA is op = 0x86
; PULA
; @if defined(HCS08) || defined(HC08)
; : PULH is op = 0x8A
; PULH
; @if defined(HCS08) || defined(HC08)
; : PULX is op = 0x88
; PULX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLA is op=0x49
ROLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLX is op=0x59
ROLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
ROL *0xFE
ROL 0xFE,X
ROL ,X
; @if defined(HCS08) || defined(HC08)
; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP
; ROL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORA is op=0x46
RORA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORX is op=0x56
RORX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
ROR *0xFE
ROR 0xFE,X
ROR ,X
; @if defined(HCS08) || defined(HC08)
; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP
; ROR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RSP is op = 0x9C
RSP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTI is op = 0x80
RTI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTS is op = 0x81
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
SBC #0xFE
SBC *0xFE
SBC 0xFEDC
SBC 0xFEDC,X
SBC 0xFE,X
SBC ,X
; @if defined(HCS08) || defined(HC08)
; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP
; SBC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP
; SBC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEC is op = 0x99
SEC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEI is op = 0x9B
SEI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1
STA *0xFE
STA 0xFEDC
STA 0xFEDC,X
STA 0xFE,X
STA ,X
; @if defined(HCS08) || defined(HC08)
; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP
; STA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP
; STA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : STHX opr8a_16 is (op=0x35); opr8a_16
; STHX *0xFE
; @if defined(HCS08)
; : STHX opr16a_16 is (op=0x96); opr16a_16
; STHX 0xFEDC
; @if defined(HCS08)
; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP
; STHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STOP is op=0x8E
STOP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1
STX *0xFE
STX 0xFEDC
STX 0xFEDC,X
STX 0xFE,X
STX ,X
; @if defined(HCS08) || defined(HC08)
; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP
; STX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP
; STX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
SUB #0xFE
SUB *0xFE
SUB 0xFEDC
SUB 0xFEDC,X
SUB 0xFE,X
SUB ,X
; @if defined(HCS08) || defined(HC08)
; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP
; SUB 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP
; SUB 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SWI is op=0x83
SWI
; @if defined(HCS08) || defined(HC08)
; : TAP is op=0x84
; TAP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TAX is op=0x97
TAX
; @if defined(HCS08) || defined(HC08)
; : TPA is op=0x85
; TPA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTA is op=0x4D
TSTA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTX is op=0x5D
TSTX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
TST *0xFE
TST 0xFE,X
TST ,X
; @if defined(HCS08) || defined(HC08)
; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP
; TST 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : TSX is op=0x95
; TSX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TXA is op=0x9F
TXA
; @if defined(HCS08) || defined(HC08)
; : TXS is op=0x94
; TXS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : WAIT is op=0x8f
WAIT
HERE:
BRA HERE
|
MassinissaDjellouli/CTFStuff | 23,737 | tools/ghidra_11.2.1_PUBLIC/Ghidra/Processors/HCS08/data/test-vectors/HC08_tv.s | .hc08
.area DIRECT (PAG)
;.setdp 0, DIRECT
;low_data1:
;.ds 1
.area PROGRAM (ABS)
.org 0x80
LOW_SUB_TEST:
RTS
.org 0x2000
HIGH_SUB_TEST:
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
ADC #0xFE
ADC *0xFE
ADC 0xFEDC
ADC 0xFEDC,X
ADC 0xFE,X
ADC ,X
; @if defined(HCS08) || defined(HC08)
; : ADC oprx16_8_SP is (op16=0x9ED9); oprx16_8_SP
ADC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADC oprx8_8_SP is (op16=0x9EE9); oprx8_8_SP
ADC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
ADD #0xFE
ADD *0xFE
ADD 0xFEDC
ADD 0xFEDC,X
ADD 0xFE,X
ADD ,X
; @if defined(HCS08) || defined(HC08)
; : ADD oprx16_8_SP is (op16=0x9EDB); oprx16_8_SP
ADD 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ADD oprx8_8_SP is (op16=0x9EEB); oprx8_8_SP
ADD 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : AIS iopr8is is op=0xA7; iopr8is
AIS #0x7F
AIS #-0x7F
; @if defined(HCS08) || defined(HC08)
; : AIX iopr8is is op=0xAF; iopr8is
AIX #0x7F
AIX #-0x7F
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : AND OP1 is (op=0xA4 | op=0xB4 | op=0xC4 | op=0xD4 | op=0xE4 | op=0xF4) ... & OP1
AND #0xFE
AND *0xFE
AND 0xFEDC
AND 0xFEDC,X
AND 0xFE,X
AND ,X
; @if defined(HCS08) || defined(HC08)
; : AND oprx16_8_SP is (op16=0x9ED4); oprx16_8_SP
AND 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : AND oprx8_8_SP is (op16=0x9EE4); oprx8_8_SP
AND 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLA is op=0x48
ASLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASLX is op=0x58
ASLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
ASL *0xFE
ASL 0xFE,X
ASL ,X
; @if defined(HCS08) || defined(HC08)
; : ASL oprx8_8_SP is (op16=0x9E68); oprx8_8_SP
ASL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRA is op=0x47
ASRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASRX is op=0x57
ASRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
ASR *0xFE
ASR 0xFE,X
ASR ,X
; @if defined(HCS08) || defined(HC08)
; : ASR oprx8_8_SP is (op16=0x9E67); oprx8_8_SP
ASR 0xFE,S
BACKWARDS1:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCC REL is op=0x24; REL
BCC BACKWARDS1
BCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCLR nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=1; opr8a_8
BCLR #0, *0xFE
BCLR #1, *0xED
BCLR #2, *0xDC
BCLR #3, *0xCB
BCLR #4, *0xBA
BCLR #5, *0xA9
BCLR #6, *0x98
BCLR #7, *0x87
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BCS REL is op=0x25; REL
BCS BACKWARDS1
BCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BEQ REL is op=0x27; REL
BEQ BACKWARDS1
BEQ FORWARDS1
; @if defined(HCS08) || defined(HC08)
; : BGE REL is op=0x90; REL
BGE BACKWARDS1
BGE FORWARDS1
; @if defined(HCS08)
; : BGND is op=0x82
; BGND
; @if defined(HCS08) || defined(HC08)
; : BGT REL is op=0x92; REL
BGT BACKWARDS1
BGT FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCC REL is op=0x28; REL
BHCC BACKWARDS1
BHCC FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHCS REL is op=0x29; REL
BHCS BACKWARDS1
BHCS FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BHI REL is op=0x22; REL
BHI BACKWARDS1
BHI FORWARDS1
; :BHS REL is op=0x24; REL See BCC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIH REL is op=0x2F; REL
BIH BACKWARDS1
BIH FORWARDS1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIL REL is op=0x2E; REL
BIL BACKWARDS1
BIL FORWARDS1
FORWARDS1:
BACKWARDS2:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
BIT #0xFE
BIT *0xFE
BIT 0xFEDC
BIT 0xFEDC,X
BIT 0xFE,X
BIT ,X
; @if defined(HCS08) || defined(HC08)
; : BIT oprx16_8_SP is (op16=0x9ED5); oprx16_8_SP
BIT 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : BIT oprx8_8_SP is (op16=0x9EE5); oprx8_8_SP
BIT 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : BLE REL is op=0x93; REL
BLE BACKWARDS2
BLE FORWARDS2
; :BLO REL is op=0x25; REL see BCS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BLS REL is op=0x23; REL
BLS BACKWARDS2
BLS FORWARDS2
; @if defined(HCS08) || defined(HC08)
; : BLT REL is op=0x91; REL
BLT BACKWARDS2
BLT FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMC REL is op=0x2C; REL
BMC BACKWARDS2
BMC FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMI REL is op=0x2B; REL
BMI BACKWARDS2
BMI FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BMS REL is op=0x2D; REL
BMS BACKWARDS2
BMS FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BNE REL is op=0x26; REL
BNE BACKWARDS2
BNE FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BPL REL is op=0x2A; REL
BPL BACKWARDS2
BPL FORWARDS2
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRA REL is op=0x20; REL
BRA BACKWARDS2
BRA FORWARDS2
FORWARDS2:
BACKWARDS3:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRCLR nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=1; opr8a_8; REL
BRCLR #0, *0xFE,BACKWARDS3
BRCLR #1, *0xED,BACKWARDS3
BRCLR #2, *0xDC,BACKWARDS3
BRCLR #3, *0xCB,BACKWARDS3
BRCLR #4, *0xBA,BACKWARDS3
BRCLR #5, *0xA9,BACKWARDS3
BRCLR #6, *0x98,BACKWARDS3
BRCLR #7, *0x87,BACKWARDS3
BRCLR #0, *0xFE,FORWARDS3
BRCLR #1, *0xED,FORWARDS3
BRCLR #2, *0xDC,FORWARDS3
BRCLR #3, *0xCB,FORWARDS3
BRCLR #4, *0xBA,FORWARDS3
BRCLR #5, *0xA9,FORWARDS3
BRCLR #6, *0x98,FORWARDS3
BRCLR #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; branch never is a two-byte nop
; : BRN REL is op=0x21; REL
BRN BACKWARDS3
BRN FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BRSET nIndex, opr8a_8, REL is op4_7=0 & nIndex & NthBit & op0_0=0; opr8a_8; REL
BRSET #0, *0xFE,BACKWARDS3
BRSET #1, *0xED,BACKWARDS3
BRSET #2, *0xDC,BACKWARDS3
BRSET #3, *0xCB,BACKWARDS3
BRSET #4, *0xBA,BACKWARDS3
BRSET #5, *0xA9,BACKWARDS3
BRSET #6, *0x98,BACKWARDS3
BRSET #7, *0x87,BACKWARDS3
BRSET #0, *0xFE,FORWARDS3
BRSET #1, *0xED,FORWARDS3
BRSET #2, *0xDC,FORWARDS3
BRSET #3, *0xCB,FORWARDS3
BRSET #4, *0xBA,FORWARDS3
BRSET #5, *0xA9,FORWARDS3
BRSET #6, *0x98,FORWARDS3
BRSET #7, *0x87,FORWARDS3
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSET nIndex, opr8a_8 is op4_7=1 & nIndex & NthBit & op0_0=0; opr8a_8
BSET #0, *0xFE
BSET #1, *0xED
BSET #2, *0xDC
BSET #3, *0xCB
BSET #4, *0xBA
BSET #5, *0xA9
BSET #6, *0x98
BSET #7, *0x87
FORWARDS3:
BACKWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : BSR REL is op=0xAD; REL
BSR BACKWARDS4
BSR FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ opr8a_8, REL is (op=0x31); opr8a_8; REL
CBEQ *0xFE, BACKWARDS4
CBEQ *0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQA iopr8i, REL is op=0x41; iopr8i; REL
CBEQA #0xFE, BACKWARDS4
CBEQA #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQX iopr8i, REL is op=0x51; iopr8i; REL
CBEQX #0xFE, BACKWARDS4
CBEQX #0xFE, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8, X"+", REL is (op=0x61) & X; oprx8; REL
CBEQ *0xFE, X+, BACKWARDS4
CBEQ *0xFE, X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ ","X"+", REL is (op=0x71) & X; REL
CBEQ ,X+, BACKWARDS4
CBEQ ,X+, FORWARDS4
; @if defined(HCS08) || defined(HC08)
; : CBEQ oprx8_8_SP, REL is (op16=0x9E61); oprx8_8_SP; REL
CBEQ 0xFE,S, BACKWARDS4
CBEQ 0xFE,S, FORWARDS4
FORWARDS4:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLC is op=0x98
CLC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLI is op=0x9A
CLI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRA is op=0x4F
CLRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLRX is op=0x5F
CLRX
; @if defined(HCS08) || defined(HC08)
; : CLRH is op=0x8C
CLRH
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CLR OP1 is (op=0x3F | op=0x6F | op=0x7F) ... & OP1
CLR *0xFE
CLR 0xFE,X
CLR ,X
; @if defined(HCS08) || defined(HC08)
; : CLR oprx8_8_SP is (op16=0x9E6F); oprx8_8_SP
CLR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
CMP #0xFE
CMP *0xFE
CMP 0xFEDC
CMP 0xFEDC,X
CMP 0xFE,X
CMP ,X
; @if defined(HCS08) || defined(HC08)
; : CMP oprx16_8_SP is (op16=0x9ED1); oprx16_8_SP
CMP 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CMP oprx8_8_SP is (op16=0x9EE1); oprx8_8_SP
CMP 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMA is op=0x43
COMA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COMX is op=0x53
COMX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
COM *0xFE
COM 0xFE,X
COM ,X
; @if defined(HCS08) || defined(HC08)
; : COM oprx8_8_SP is (op16=0x9E63); oprx8_8_SP
COM 0xFE,S
; @if defined(HCS08)
; : CPHX opr16a_16 is (op=0x3E); opr16a_16
; CPHX 0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX iopr16i is (op=0x65); iopr16i
CPHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : CPHX opr8a_16 is (op=0x75); opr8a_16
CPHX *0xFE
; @if defined(HCS08)
; : CPHX oprx8_16_SP is (op16=0x9EF3); oprx8_16_SP
; CPHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
CPX #0xFE
CPX *0xFE
CPX 0xFEDC
CPX 0xFEDC,X
CPX 0xFE,X
CPX ,X
; @if defined(HCS08) || defined(HC08)
; : CPX oprx16_8_SP is (op16=0x9ED3); oprx16_8_SP
CPX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : CPX oprx8_8_SP is (op16=0x9EE3); oprx8_8_SP
CPX 0xFE,S
BACKWARDS5:
; @if defined(HCS08) || defined(HC08)
; : DAA is op=0x72
DAA
; @if defined(HCS08) || defined(HC08)
; : DBNZA REL is op=0x4B; REL
DBNZA BACKWARDS5
DBNZA FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZX REL is op=0x5B; REL
DBNZX BACKWARDS5
DBNZX FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ OP1, REL is (op=0x3B | op=0x6B | op=0x7B) ... & OP1; REL
DBNZ *0xFE, BACKWARDS5
DBNZ 0xFE,X, BACKWARDS5
DBNZ ,X, BACKWARDS5
DBNZ *0xFE, FORWARDS5
DBNZ 0xFE,X, FORWARDS5
DBNZ ,X, FORWARDS5
; @if defined(HCS08) || defined(HC08)
; : DBNZ oprx8_8_SP, REL is (op16=0x9E6B); oprx8_8_SP; REL
DBNZ 0xFE,S, BACKWARDS5
DBNZ 0xFE,S, FORWARDS5
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECA is op=0x4A
DECA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DECX is op=0x5A
DECX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
DEC *0xFE
DEC 0xFE,X
DEC ,X
; @if defined(HCS08) || defined(HC08)
; : DEC oprx8_8_SP is (op16=0x9E6A); oprx8_8_SP
DEC 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : DIV is op=0x52
DIV
FORWARDS5:
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
EOR #0xFE
EOR *0xFE
EOR 0xFEDC
EOR 0xFEDC,X
EOR 0xFE,X
EOR ,X
; @if defined(HCS08) || defined(HC08)
; : EOR oprx16_8_SP is (op16=0x9ED8); oprx16_8_SP
EOR 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : EOR oprx8_8_SP is (op16=0x9EE8); oprx8_8_SP
EOR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCA is op=0x4C
INCA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INCX is op=0x5C
INCX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
INC *0xFE
INC 0xFE,X
INC ,X
; @if defined(HCS08) || defined(HC08)
; : INC oprx8_8_SP is (op16=0x9E6C); oprx8_8_SP
INC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDR is (op=0xBC | op=0xCC) ... & ADDR
JMP *LOW_SUB_TEST
JMP HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JMP ADDRI is (op=0xDC | op=0xEC | op=0xFC) ... & ADDRI
JMP 0xFEDC,X
JMP 0xFE,X
JMP ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDR is (op=0xBD | op=0xCD) ... & ADDR
JSR *LOW_SUB_TEST
JSR HIGH_SUB_TEST
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : JSR ADDRI is (op=0xDD | op=0xED | op=0xFD) ... & ADDRI
JSR 0xFEDC,X
JSR 0xFE,X
JSR ,X
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDA OP1 is (op=0xA6 | op=0xB6 | op=0xC6 | op=0xD6 | op=0xE6 | op=0xF6) ... & OP1
LDA #0xFE
LDA *0xFE
LDA 0xFEDC
LDA 0xFEDC,X
LDA 0xFE,X
LDA ,X
; @if defined(HCS08) || defined(HC08)
; : LDA oprx16_8_SP is (op16=0x9ED6); oprx16_8_SP
LDA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDA oprx8_8_SP is (op16=0x9EE6); oprx8_8_SP
LDA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : LDHX iopr16i is (op=0x45); iopr16i
LDHX #0xFEDC
; @if defined(HCS08) || defined(HC08)
; : LDHX opr8a_16 is (op=0x55); opr8a_16
LDHX *0xFE
; @if defined(HCS08)
; : LDHX opr16a_16 is (op=0x32); opr16a_16
; LDHX 0xFEDC
; @if defined(HCS08)
; : LDHX ","X is (op16=0x9EAE) & X
; LDHX ,X
; @if defined(HCS08)
; : LDHX oprx16_16_X is (op16=0x9EBE); oprx16_16_X
; LDHX 0xFEDC,X
; @if defined(HCS08)
; : LDHX oprx8_16_X is (op16=0x9ECE); oprx8_16_X
; LDHX 0xFE,X
; @if defined(HCS08)
; : LDHX oprx8_16_SP is (op16=0x9EFE); oprx8_16_SP
; LDHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LDX OP1 is (op=0xAE | op=0xBE | op=0xCE | op=0xDE | op=0xEE | op=0xFE) ... & OP1
LDX #0xFE
LDX *0xFE
LDX 0xFEDC
LDX 0xFEDC,X
LDX 0xFE,X
LDX ,X
; @if defined(HCS08) || defined(HC08)
; : LDX oprx16_8_SP is (op16=0x9EDE); oprx16_8_SP
LDX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : LDX oprx8_8_SP is (op16=0x9EEE); oprx8_8_SP
LDX 0xFE,S
; ## Logical Shift left is same as arithmetic shift left
; :LSLA is op=0x48
; :LSLX is op=0x58
; :LSL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRA is op=0x44
LSRA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSRX is op=0x54
LSRX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
LSR *0xFE
LSR 0xFE,X
LSR ,X
; @if defined(HCS08) || defined(HC08)
; : LSR oprx8_8_SP is (op16=0x9E64); oprx8_8_SP
LSR 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, op2_opr8a is (op=0x4E); opr8a_8; op2_opr8a
MOV *0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV opr8a_8, X"+" is (op=0x5E); opr8a_8 & X
MOV 0xFE, X+
; @if defined(HCS08) || defined(HC08)
; : MOV iopr8i, op2_opr8a is (op=0x6E); iopr8i; op2_opr8a
MOV #0xFE, *0x97
; @if defined(HCS08) || defined(HC08)
; : MOV ","X"+," op2_opr8a is (op=0x7E) & X; op2_opr8a
MOV ,X+, *0xFE
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : MUL is op=0x42
MUL
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGA is op=0x40
NEGA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEGX is op=0x50
NEGX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
NEG *0xFE
NEG 0xFE,X
NEG ,X
; @if defined(HCS08) || defined(HC08)
; : NEG oprx8_8_SP is (op16=0x9E60); oprx8_8_SP
NEG 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : NOP is op = 0x9D
NOP
; @if defined(HCS08) || defined(HC08)
; : NSA is op = 0x62
NSA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ORA OP1 is (op=0xAA | op=0xBA | op=0xCA | op=0xDA | op=0xEA | op=0xFA) ... & OP1
ORA #0xFE
ORA *0xFE
ORA 0xFEDC
ORA 0xFEDC,X
ORA 0xFE,X
ORA ,X
; @if defined(HCS08) || defined(HC08)
; : ORA oprx16_8_SP is (op16=0x9EDA); oprx16_8_SP
ORA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : ORA oprx8_8_SP is (op16=0x9EEA); oprx8_8_SP
ORA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : PSHA is op = 0x87
PSHA
; @if defined(HCS08) || defined(HC08)
; : PSHH is op = 0x8B
PSHH
; @if defined(HCS08) || defined(HC08)
; : PSHX is op = 0x89
PSHX
; @if defined(HCS08) || defined(HC08)
; : PULA is op = 0x86
PULA
; @if defined(HCS08) || defined(HC08)
; : PULH is op = 0x8A
PULH
; @if defined(HCS08) || defined(HC08)
; : PULX is op = 0x88
PULX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLA is op=0x49
ROLA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROLX is op=0x59
ROLX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
ROL *0xFE
ROL 0xFE,X
ROL ,X
; @if defined(HCS08) || defined(HC08)
; : ROL oprx8_8_SP is (op16=0x9E69); oprx8_8_SP
ROL 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORA is op=0x46
RORA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RORX is op=0x56
RORX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
ROR *0xFE
ROR 0xFE,X
ROR ,X
; @if defined(HCS08) || defined(HC08)
; : ROR oprx8_8_SP is (op16=0x9E66); oprx8_8_SP
ROR 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RSP is op = 0x9C
RSP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTI is op = 0x80
RTI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : RTS is op = 0x81
RTS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
SBC #0xFE
SBC *0xFE
SBC 0xFEDC
SBC 0xFEDC,X
SBC 0xFE,X
SBC ,X
; @if defined(HCS08) || defined(HC08)
; : SBC oprx16_8_SP is (op16=0x9ED2); oprx16_8_SP
SBC 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SBC oprx8_8_SP is (op16=0x9EE2); oprx8_8_SP
SBC 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEC is op = 0x99
SEC
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SEI is op = 0x9B
SEI
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STA OP1 is (op=0xB7 | op=0xC7 | op=0xD7 | op=0xE7 | op=0xF7) ... & OP1
STA *0xFE
STA 0xFEDC
STA 0xFEDC,X
STA 0xFE,X
STA ,X
; @if defined(HCS08) || defined(HC08)
; : STA oprx16_8_SP is (op16=0x9ED7); oprx16_8_SP
STA 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STA oprx8_8_SP is (op16=0x9EE7); oprx8_8_SP
STA 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : STHX opr8a_16 is (op=0x35); opr8a_16
STHX *0xFE
; @if defined(HCS08)
; : STHX opr16a_16 is (op=0x96); opr16a_16
; STHX 0xFEDC
; @if defined(HCS08)
; : STHX oprx8_16_SP is (op16=0x9EFF); oprx8_16_SP
; STHX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STOP is op=0x8E
STOP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : STX OP1 is (op=0xBF | op=0xCF | op=0xDF | op=0xEF | op=0xFF) ... & OP1
STX *0xFE
STX 0xFEDC
STX 0xFEDC,X
STX 0xFE,X
STX ,X
; @if defined(HCS08) || defined(HC08)
; : STX oprx16_8_SP is (op16=0x9EDF); oprx16_8_SP
STX 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : STX oprx8_8_SP is (op16=0x9EEF); oprx8_8_SP
STX 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
SUB #0xFE
SUB *0xFE
SUB 0xFEDC
SUB 0xFEDC,X
SUB 0xFE,X
SUB ,X
; @if defined(HCS08) || defined(HC08)
; : SUB oprx16_8_SP is (op16=0x9ED0); oprx16_8_SP
SUB 0xFEDC,S
; @if defined(HCS08) || defined(HC08)
; : SUB oprx8_8_SP is (op16=0x9EE0); oprx8_8_SP
SUB 0xFE,S
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : SWI is op=0x83
SWI
; @if defined(HCS08) || defined(HC08)
; : TAP is op=0x84
TAP
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TAX is op=0x97
TAX
; @if defined(HCS08) || defined(HC08)
; : TPA is op=0x85
TPA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTA is op=0x4D
TSTA
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TSTX is op=0x5D
TSTX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
TST *0xFE
TST 0xFE,X
TST ,X
; @if defined(HCS08) || defined(HC08)
; : TST oprx8_8_SP is (op16=0x9E6D); oprx8_8_SP
TST 0xFE,S
; @if defined(HCS08) || defined(HC08)
; : TSX is op=0x95
TSX
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : TXA is op=0x9F
TXA
; @if defined(HCS08) || defined(HC08)
; : TXS is op=0x94
TXS
; @if defined(HCS08) || defined(HC08) || defined(HC05)
; : WAIT is op=0x8f
WAIT
HERE:
BRA HERE
|
MassinissaDjellouli/CTFStuff | 2,272 | tools/ghidra_11.2.1_PUBLIC/docs/GhidraClass/Advanced/src/Examples/inline.s | .file "inline.c"
.intel_syntax noprefix
.section .rodata
.LC0:
.string "\nUsage: %s arg1 arg2\n\n"
.LC1:
.string "\nSum of %lu and %lu: %lu\n\n"
.text
.globl main
.type main, @function
main:
.LFB2:
sub rsp, 40
.LCFI0:
mov DWORD PTR [rsp+12], edi
mov QWORD PTR [rsp], rsi
cmp DWORD PTR [rsp+12], 3
je .L2
mov rax, QWORD PTR [rsp]
mov rax, QWORD PTR [rax]
mov rsi, rax
mov edi, OFFSET FLAT:.LC0
mov eax, 0
call printf
mov eax, 0
jmp .L3
.L2:
mov rax, QWORD PTR [rsp]
add rax, 8
mov rax, QWORD PTR [rax]
mov edx, 10
mov esi, 0
mov rdi, rax
call strtoul
mov QWORD PTR [rsp+24], rax
mov rax, QWORD PTR [rsp]
add rax, 16
mov rax, QWORD PTR [rax]
mov edx, 10
mov esi, 0
mov rdi, rax
call strtoul
mov QWORD PTR [rsp+16], rax
call adjustStack
mov rax, QWORD PTR [rsp+32]
mov rdx, QWORD PTR [rsp+40]
lea rcx, [rdx+rax]
mov rdx, QWORD PTR [rsp+32]
mov rax, QWORD PTR [rsp+40]
mov rsi, rax
mov edi, OFFSET FLAT:.LC1
mov eax, 0
call printf
call restoreStack
mov eax, 0
.L3:
add rsp, 40
.LCFI1:
ret
.LFE2:
.size main, .-main
.globl adjustStack
.type adjustStack, @function
adjustStack:
.LFB3:
pop rdi
sub rsp, 0x10
push rdi
ret
.LFE3:
.size adjustStack, .-adjustStack
.globl restoreStack
.type restoreStack, @function
restoreStack:
.LFB4:
pop rdi
add rsp, 0x10
push rdi
ret
.LFE4:
.size restoreStack, .-restoreStack
.section .eh_frame,"a",@progbits
.Lframe1:
.long .LECIE1-.LSCIE1
.LSCIE1:
.long 0
.byte 0x3
.string "zR"
.uleb128 0x1
.sleb128 -8
.uleb128 0x10
.uleb128 0x1
.byte 0x3
.byte 0xc
.uleb128 0x7
.uleb128 0x8
.byte 0x90
.uleb128 0x1
.align 8
.LECIE1:
.LSFDE1:
.long .LEFDE1-.LASFDE1
.LASFDE1:
.long .LASFDE1-.Lframe1
.long .LFB2
.long .LFE2-.LFB2
.uleb128 0
.byte 0x4
.long .LCFI0-.LFB2
.byte 0xe
.uleb128 0x30
.byte 0x4
.long .LCFI1-.LCFI0
.byte 0xe
.uleb128 0x8
.align 8
.LEFDE1:
.LSFDE3:
.long .LEFDE3-.LASFDE3
.LASFDE3:
.long .LASFDE3-.Lframe1
.long .LFB3
.long .LFE3-.LFB3
.uleb128 0
.align 8
.LEFDE3:
.LSFDE5:
.long .LEFDE5-.LASFDE5
.LASFDE5:
.long .LASFDE5-.Lframe1
.long .LFB4
.long .LFE4-.LFB4
.uleb128 0
.align 8
.LEFDE5:
.ident "GCC: (GNU) 4.8.5 20150623 (Red Hat 4.8.5-28)"
.section .note.GNU-stack,"",@progbits
|
MassinissaDjellouli/CTFStuff | 1,927 | tools/ghidra_11.2.1_PUBLIC/docs/GhidraClass/Advanced/src/Examples/compilerVsDecompiler.s | .file "compilerVsDecompiler.c"
.intel_syntax noprefix
.text
.p2align 4,,15
.globl calls_memcmp
.type calls_memcmp, @function
calls_memcmp:
.LFB3:
.cfi_startproc
mov rax, rdi
mov rcx, rdx
mov rdi, rsi
cmp rdx, rdx
mov rsi, rax
repz cmpsb
seta al
setb dl
sub al, dl
movsx eax, al
ret
.cfi_endproc
.LFE3:
.size calls_memcmp, .-calls_memcmp
.p2align 4,,15
.globl calls_memcmp_fixed_len
.type calls_memcmp_fixed_len, @function
calls_memcmp_fixed_len:
.LFB4:
.cfi_startproc
mov rax, rdi
mov ecx, 8
mov rdi, rsi
mov rsi, rax
repz cmpsb
seta al
setb dl
sub al, dl
movsx eax, al
ret
.cfi_endproc
.LFE4:
.size calls_memcmp_fixed_len, .-calls_memcmp_fixed_len
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nUsage: %s string1 string2 len\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nres1: %d res2: %d\n\n"
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB2:
.cfi_startproc
push r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
cmp edi, 4
push rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
push rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
mov rbx, rsi
je .L4
mov rsi, QWORD PTR [rsi]
mov edi, OFFSET FLAT:.LC0
xor eax, eax
call printf
.L5:
pop rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
pop rbp
.cfi_def_cfa_offset 16
xor eax, eax
pop r12
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
mov rdi, QWORD PTR [rsi+24]
mov edx, 10
xor esi, esi
call strtoul
mov rbp, QWORD PTR [rbx+16]
mov rbx, QWORD PTR [rbx+8]
mov rdx, rax
mov rsi, rbp
mov rdi, rbx
call calls_memcmp
mov rsi, rbp
mov r12d, eax
mov rdi, rbx
call calls_memcmp_fixed_len
mov esi, r12d
mov edx, eax
mov edi, OFFSET FLAT:.LC1
xor eax, eax
call printf
jmp .L5
.cfi_endproc
.LFE2:
.size main, .-main
.ident "GCC: (GNU) 4.8.5 20150623 (Red Hat 4.8.5-28)"
.section .note.GNU-stack,"",@progbits
|
MassinissaDjellouli/CTFStuff | 1,968 | tools/ghidra_11.2.1_PUBLIC/docs/GhidraClass/Advanced/src/Examples/switch.s | .file "switch.c"
.intel_syntax noprefix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nUsage: %s switch_var input\n\n"
.LC1:
.string "Returning %ld\n"
.section .text.startup,"ax",@progbits
.p2align 4,,15
.globl main
.type main, @function
main:
.LFB20:
.cfi_startproc
push rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
push rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
mov rbx, rsi
sub rsp, 8
.cfi_def_cfa_offset 32
cmp edi, 3
je .L12
mov rsi, QWORD PTR [rsi]
mov edi, OFFSET FLAT:.LC0
xor eax, eax
call printf
xor eax, eax
.L13:
add rsp, 8
.cfi_remember_state
.cfi_def_cfa_offset 24
pop rbx
.cfi_def_cfa_offset 16
pop rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
mov rdi, QWORD PTR [rsi+8]
mov edx, 10
xor esi, esi
call strtoul
mov rdi, QWORD PTR [rbx+16]
mov rbp, rax
mov edx, 10
xor esi, esi
call strtol
mov ecx, 10
mov rbx, rax
xor edx, edx
mov rax, rbp
div rcx
jmp [QWORD PTR array[0+rdx*8]]
.L2:
lea rbx, [rbx+rbx*4]
add rbx, 17
.L14:
mov rsi, rbx
mov edi, OFFSET FLAT:.LC1
xor eax, eax
call printf
mov eax, ebx
jmp .L13
.L11:
imul rbx, rbx, 14
add rbx, 53
jmp .L14
.L10:
imul rbx, rbx, 13
add rbx, 47
jmp .L14
.L9:
imul rbx, rbx, 12
add rbx, 43
jmp .L14
.L8:
imul rbx, rbx, 11
add rbx, 41
jmp .L14
.L7:
imul rbx, rbx, 10
add rbx, 37
jmp .L14
.L6:
lea rbx, [rbx+rbx*8]
add rbx, 31
jmp .L14
.L5:
lea rbx, [29+rbx*8]
jmp .L14
.L4:
imul rbx, rbx, 7
add rbx, 23
jmp .L14
.L3:
imul rbx, rbx, 6
add rbx, 19
jmp .L14
.cfi_endproc
.LFE20:
.size main, .-main
.globl array
.data
.align 32
.type array, @object
.size array, 80
array:
.quad OFFSET FLAT:.L2
.quad OFFSET FLAT:.L3
.quad OFFSET FLAT:.L4
.quad OFFSET FLAT:.L5
.quad OFFSET FLAT:.L6
.quad OFFSET FLAT:.L7
.quad OFFSET FLAT:.L8
.quad OFFSET FLAT:.L9
.quad OFFSET FLAT:.L10
.quad OFFSET FLAT:.L11
.ident "GCC: (GNU) 4.8.5 20150623 (Red Hat 4.8.5-28)"
.section .note.GNU-stack,"",@progbits
|
matoval/xv6-rust | 2,942 | bootloader/src/boot.S | # Start the first CPU: switch to 32-bit protected mode, jump into C.
# The BIOS loads this code from the first sector of the hard disk into
# memory at physical address 0x7c00 and starts executing in real mode
# with %cs=0 %ip=7c00.
.code16 # Assemble for 16-bit mode
.globl start
start:
cli # BIOS enabled interrupts; disable
# Zero data segment registers DS, ES, and SS.
xorw %ax,%ax # Set %ax to zero
movw %ax,%ds # -> Data Segment
movw %ax,%es # -> Extra Segment
movw %ax,%ss # -> Stack Segment
# Physical address line A20 is tied to zero so that the first PCs
# with 2 MB would run software that assumed 1 MB. Undo that.
seta20.1:
inb $0x64,%al # Wait for not busy
testb $0x2,%al
jnz seta20.1
movb $0xd1,%al # 0xd1 -> port 0x64
outb %al,$0x64
seta20.2:
inb $0x64,%al # Wait for not busy
testb $0x2,%al
jnz seta20.2
movb $0xdf,%al # 0xdf -> port 0x60
outb %al,$0x60
# Switch from real to protected mode. Use a bootstrap GDT that makes
# virtual addresses map directly to physical addresses so that the
# effective memory map doesn't change during the transition.
lgdt gdtdesc
movl %cr0, %eax
orl $1, %eax
movl %eax, %cr0
//PAGEBREAK!
# Complete the transition to 32-bit protected mode by using a long jmp
# to reload %cs and %eip. The segment descriptors are set up with no
# translation, so that the mapping is still the identity mapping.
ljmp $0x08, $start32
.code32 # Tell assembler to generate 32-bit code now.
start32:
# Set up the protected-mode data segment registers
movw $0x10, %ax # Our data segment selector
movw %ax, %ds # -> DS: Data Segment
movw %ax, %es # -> ES: Extra Segment
movw %ax, %ss # -> SS: Stack Segment
movw $0, %ax # Zero segments not ready for use
movw %ax, %fs # -> FS
movw %ax, %gs # -> GS
# Set up the stack pointer and call into C.
movl $start, %esp
call bootmain # this should be a Rust `#[no_mangle]` fn
# If bootmain returns (it shouldn't), trigger a Bochs
# breakpoint if running under Bochs, then loop.
movw $0x8a00, %ax # 0x8a00 -> port 0x8a00
movw %ax, %dx
outw %ax, %dx
movw $0x8ae0, %ax # 0x8ae0 -> port 0x8a00
outw %ax, %dx
spin:
jmp spin
# Bootstrap GDT
.p2align 2 # force 4 byte alignment
gdt:
.quad 0x000000000000000 # null seg
.quad 0x00cf9a000000ffff # code seg
.quad 0x00cf92000000ffff # data seg
gdtdesc:
.word (gdtdesc - gdt - 1) # sizeof(gdt) - 1
.long gdt # address gdt |
MatthewZelriche/Lantern-OS | 1,796 | bootloaders/raspi/src/main.S | .section ".text.boot"
.globl kstart
kstart:
# Set up a temporary stack for the primary core before we transition over to rust code
ldr x1, =__STACK_START
mov sp, x1
# Zero BSS, if such a section exists
ldr x2, =__BSS_END
ldr x3, =__BSS_START
zero_bss:
# Check if we zeroed out all the BSS data
cmp x2, x3
beq to_rust
# Zero out 8 bytes of BSS and loop
str xzr, [x3]
add x3, x3, #8
bl zero_bss
to_rust:
# Prep the switch from EL2 -> EL1
# We need to set up some register state to configure how our eret will function
# First we fake a program status where we are telling the cpu to "return" to EL1, using SP_EL1
# We also inform the cpu that all interrupts in EL1 should be masked (we are not yet set up for them)
ldr x9, =453
msr spsr_el2, x9
# We must also disable trap interrupts for vectorized and floating point instructions in EL1, otherwise
# we will trigger an exception return back to EL2 and crash the CPU (because EL2 will never have an
# exception handler installed)
ldr x9, =3145728
msr cpacr_el1, x9
# In addition, we have to make sure the EL1 stack pointer is valid
mov x9, xzr
mov x9, sp
msr sp_el1, x9
# Next inform the CPU that we want EL1 to be running in 64 bit mode
ldr x9, =2147483648
msr hcr_el2, x9
# TODO: When we enable the MMU, there will be some additional registers we have to set here!
# TODO
# Finally, before we "return", we need to specify the address we are returning to
adr x9, bootloader_main
msr elr_el2, x9
# Off we go!
# When jumping to rust entry point function:
# x0 contains the address of the start of the DTB
eret |
matthiasgoergens/zkvm | 2,493 | riscv-testdata/testdata/rv64si/icache-alias.S | # See LICENSE for license details.
#*****************************************************************************
# icache-alias.S
#-----------------------------------------------------------------------------
#
# Test that instruction memory appears to be physically addressed, i.e.,
# that disagreements in the low-order VPN and PPN bits don't cause the
# wrong instruction to be fetched. It also tests that changing a page
# mapping takes effect without executing FENCE.I.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
li TESTNUM, 2
# Set up intermediate page tables
la t0, page_table_3
srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
ori t0, t0, PTE_V
sd t0, page_table_2, t1
la t0, page_table_2
srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
ori t0, t0, PTE_V
sd t0, page_table_1, t1
# Set up leaf mappings where va[12] != pa[12]
la t0, code_page_1
srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
ori t0, t0, PTE_V | PTE_X | PTE_A
sd t0, page_table_3 + 8, t1
la t0, code_page_2
srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
ori t0, t0, PTE_V | PTE_X | PTE_A
sd t0, page_table_3 + 0, t1
# Turn on VM
li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
csrw satp, a1
sfence.vma
# Enter supervisor mode and make sure correct page is accessed
la a2, 1f
csrwi mepc, 0
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
csrs mstatus, a1
mret
1:
li TESTNUM, 2
addi a0, a0, -321
bnez a0, fail
li TESTNUM, 3
la a2, 1f
li t0, RISCV_PGSIZE
csrw mepc, t0
mret
1:
addi a0, a0, -123
bnez a0, fail
li TESTNUM, 4
la a2, 1f
csrwi mepc, 0
mret
.align 2
1:
addi a0, a0, -321
bnez a0, fail
li TESTNUM, 5
# Change mapping and try again
la t0, code_page_1
srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
ori t0, t0, PTE_V | PTE_X | PTE_A
sd t0, page_table_3 + 0, t1
sfence.vma
la a2, 1f
csrwi mepc, 0
mret
.align 2
1:
addi a0, a0, -123
bnez a0, fail
RVTEST_PASS
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
csrr t0, mcause
add t0, t0, -CAUSE_STORE_PAGE_FAULT
bnez t0, fail
jr a2
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
.align 12
page_table_1: .dword 0
.align 12
page_table_2: .dword 0
.align 12
page_table_3: .dword 0
.align 13
code_page_1:
li a0, 123
sw x0, (x0)
.align 12
code_page_2:
li a0, 321
sw x0, (x0)
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,707 | riscv-testdata/testdata/rv64si/ma_fetch.S | # See LICENSE for license details.
#*****************************************************************************
# ma_fetch.S
#-----------------------------------------------------------------------------
#
# Test misaligned fetch trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_BEGIN
#ifdef __MACHINE_MODE
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define stval mtval
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
#endif
.align 2
.option norvc
# Without RVC, the jalr should trap, and the handler will skip ahead.
# With RVC, the jalr should not trap, and "j fail" should get skipped.
li TESTNUM, 2
li t1, 0
la t0, 1f
jalr t1, t0, 2
1:
.option rvc
c.j 1f
c.j 2f
.option norvc
1:
j fail
2:
// This test should pass, since JALR ignores the target LSB
li TESTNUM, 3
la t0, 1f
jalr t1, t0, 1
1:
j 1f
j fail
1:
li TESTNUM, 4
li t1, 0
la t0, 1f
jalr t1, t0, 3
1:
.option rvc
c.j 1f
c.j 2f
.option norvc
1:
j fail
2:
# Like test 2, but with jal instead of jalr.
li TESTNUM, 5
li t1, 0
la t0, 1f
jal t1, 2f
1:
.option rvc
c.j 1f
2:
c.j 2f
.option norvc
1:
j fail
2:
# Like test 2, but with a taken branch instead of jalr.
li TESTNUM, 6
li t1, 0
la t0, 1f
beqz x0, 2f
1:
.option rvc
c.j 1f
2:
c.j 2f
.option norvc
1:
j fail
2:
# Not-taken branches should not trap, even without RVC.
li TESTNUM, 7
bnez x0, 1f
j 2f
.option rvc
c.j 1f
1:
c.j 1f
.option norvc
1:
j fail
2:
#ifdef __MACHINE_MODE
# Skip if C cannot be enabled
csrsi misa, 1 << ('c' - 'a')
csrr t2, misa
andi t2, t2, 1 << ('c' - 'a')
beqz t2, pass
# Skip if C cannot be disabled
csrci misa, 1 << ('c' - 'a')
csrr t2, misa
andi t2, t2, 1 << ('c' - 'a')
bnez t2, pass
# Skip if clearing misa.C does not set IALIGN=32
csrr t0, mtvec
la t1, 1f
addi t1, t1, 2
csrw mtvec, t1
j 1f
.option rvc
c.nop
1:
j pass
.option norvc
2:
csrw mtvec, t0
csrsi misa, 1 << ('c' - 'a')
# IALIGN=32 cannot be set if doing so would cause a misaligned instruction
# exception on the next instruction fetch. (This test assumes no other
# extensions that support misalignment are present.)
li TESTNUM, 8
csrr t2, misa
andi t2, t2, 1 << ('c' - 'a')
beqz t2, pass
.option rvc
c.nop
csrci misa, 1 << ('c' - 'a')
1:
c.nop
.option norvc
csrr t2, misa
andi t2, t2, 1 << ('c' - 'a')
beqz t2, fail
# IALIGN=32, mret to a misaligned mepc should succeed,
# masking off mepc[1].
la t0, 1f
addi t0, t0, -2
csrw mepc, t0
csrci misa, 1 << ('c' - 'a')
li t2, MSTATUS_MPP
csrs mstatus, t2
mret
# mret should transfer control to this branch. Otherwise, it will
# transfer control two bytes into the branch, which happens to be the
# illegal instruction c.unimp.
beqz x0, 1f
1:
csrsi misa, 1 << ('c' - 'a')
#endif
j pass
TEST_PASSFAIL
.align 2
.global stvec_handler
stvec_handler:
# tests 2, 4, 5, 6, and 8 should trap
li a0, 2
beq TESTNUM, a0, 1f
li a0, 4
beq TESTNUM, a0, 1f
li a0, 5
beq TESTNUM, a0, 1f
li a0, 6
beq TESTNUM, a0, 1f
j fail
1:
# verify that return address was not written
bnez t1, fail
# verify trap cause
li a1, CAUSE_MISALIGNED_FETCH
csrr a0, scause
bne a0, a1, fail
# verify that epc == &jalr (== t0 - 4)
csrr a1, sepc
addi a1, a1, 4
bne t0, a1, fail
# verify that tval == 0 or tval == t0+2.
csrr a0, stval
beqz a0, 1f
addi a0, a0, -2
bne a0, t0, fail
1:
addi a1, a1, 8
csrw sepc, a1
sret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,539 | riscv-testdata/testdata/rv64si/csr.S | # See LICENSE for license details.
#*****************************************************************************
# csr.S
#-----------------------------------------------------------------------------
#
# Test CSRRx and CSRRxI instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_BEGIN
#ifdef __MACHINE_MODE
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
#undef SSTATUS_SPP
#define SSTATUS_SPP MSTATUS_MPP
#endif
# For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.)
#if __riscv_xlen == 64
# If running in M mode, use mstatus.MPP to check existence of U mode.
# Otherwise, if in S mode, then U mode must exist and we don't need to check.
#ifdef __MACHINE_MODE
li t0, MSTATUS_MPP
csrc mstatus, t0
csrr t1, mstatus
and t0, t0, t1
bnez t0, 1f
#endif
# If U mode is present, UXL should be 2 (XLEN = 64-bit)
TEST_CASE(18, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
#ifdef __MACHINE_MODE
j 2f
1:
# If U mode is not present, UXL should be 0
TEST_CASE(19, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
2:
#endif
#endif
TEST_CASE(20, a0, 0, csrw sscratch, zero; csrr a0, sscratch);
TEST_CASE(21, a0, 0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF);
TEST_CASE(22, a0, 0x1f, csrrsi x0, sscratch, 0x10; csrr a0, sscratch);
csrwi sscratch, 3
TEST_CASE( 2, a0, 3, csrr a0, sscratch);
TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1);
TEST_CASE( 4, a2, 2, csrrsi a2, sscratch, 4);
TEST_CASE( 5, a3, 6, csrrwi a3, sscratch, 2);
TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
TEST_CASE( 7, a1, 0xbad1dea, li a0, 0x0001dea; csrrc a1, sscratch, a0);
TEST_CASE( 8, a1, 0xbad0000, li a0, 0x000beef; csrrs a1, sscratch, a0);
TEST_CASE( 9, a0, 0xbadbeef, li a0, 0xbad1dea; csrrw a0, sscratch, a0);
TEST_CASE(10, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
TEST_CASE(11, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
TEST_CASE(12, a0, 0xbadbeef, csrr a0, sscratch);
#ifdef __MACHINE_MODE
# Is F extension present?
csrr a0, misa
andi a0, a0, (1 << ('F' - 'A'))
beqz a0, 1f
# If so, make sure FP stores have no effect when mstatus.FS is off.
li a1, MSTATUS_FS
csrs mstatus, a1
#ifdef __riscv_flen
fmv.s.x f0, x0
csrc mstatus, a1
la a1, fsw_data
TEST_CASE(13, a0, 1, fsw f0, (a1); lw a0, (a1));
#else
# Fail if this test is compiled without F but executed on a core with F.
TEST_CASE(13, zero, 1)
#endif
1:
# Figure out if 'U' is set in misa
csrr a0, misa # a0 = csr(misa)
srli a0, a0, 20 # a0 = a0 >> 20
andi a0, a0, 1 # a0 = a0 & 1
beqz a0, finish # if no user mode, skip the rest of these checks
# Enable access to the cycle counter
csrwi mcounteren, 1
# Figure out if 'S' is set in misa
csrr a0, misa # a0 = csr(misa)
srli a0, a0, 18 # a0 = a0 >> 20
andi a0, a0, 1 # a0 = a0 & 1
beqz a0, 1f
# Enable access to the cycle counter
csrwi scounteren, 1
1:
#endif /* __MACHINE_MODE */
# jump to user land
li t0, SSTATUS_SPP
csrc sstatus, t0
la t0, 1f
csrw sepc, t0
sret
1:
# Make sure writing the cycle counter causes an exception.
# Don't run in supervisor, as we don't delegate illegal instruction traps.
#ifdef __MACHINE_MODE
TEST_CASE(14, a0, 255, li a0, 255; csrrw a0, cycle, x0);
#endif
# Make sure reading status in user mode causes an exception.
# Don't run in supervisor, as we don't delegate illegal instruction traps.
#ifdef __MACHINE_MODE
TEST_CASE(15, a0, 255, li a0, 255; csrr a0, sstatus)
#else
TEST_CASE(15, x0, 0, nop)
#endif
finish:
RVTEST_PASS
# We should only fall through to this if scall failed.
TEST_PASSFAIL
.align 2
.global stvec_handler
stvec_handler:
# Trapping on tests 13-15 is good news.
li t0, 13
bltu TESTNUM, t0, 1f
li t0, 15
bleu TESTNUM, t0, privileged
1:
# catch RVTEST_PASS and kick it up to M-mode
csrr t0, scause
li t1, CAUSE_USER_ECALL
bne t0, t1, fail
RVTEST_PASS
privileged:
# Make sure scause indicates a lack of privilege.
csrr t0, scause
li t1, CAUSE_ILLEGAL_INSTRUCTION
bne t0, t1, fail
# Return to user mode, but skip the trapping instruction.
csrr t0, sepc
addi t0, t0, 4
csrw sepc, t0
sret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
fsw_data: .word 1
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,626 | riscv-testdata/testdata/rv64si/dirty.S | # See LICENSE for license details.
#*****************************************************************************
# dirty.S
#-----------------------------------------------------------------------------
#
# Test VM referenced and dirty bits.
#
#include "riscv_test.h"
#include "test_macros.h"
#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
# error This test requires DRAM_BASE be SV39 superpage-aligned
#endif
RVTEST_RV64M
RVTEST_CODE_BEGIN
# Turn on VM
li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
la a1, page_table_1
srl a1, a1, RISCV_PGSHIFT
or a1, a1, a0
csrw satp, a1
sfence.vma
# Set up MPRV with MPP=S, so loads and stores use S-mode
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
csrs mstatus, a1
# Try a faulting store to make sure dirty bit is not set
li TESTNUM, 2
li t2, 1
sw t2, dummy - DRAM_BASE, a0
# Set SUM=1 so user memory access is permitted
li TESTNUM, 3
li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
csrs mstatus, a1
# Make sure SUM=1 works
lw t0, dummy - DRAM_BASE
bnez t0, die
# Try a non-faulting store to make sure dirty bit is set
sw t2, dummy - DRAM_BASE, a0
# Make sure it succeeded
lw t0, dummy - DRAM_BASE
bne t0, t2, die
# Leave MPRV
li t0, MSTATUS_MPRV
csrc mstatus, t0
# Make sure D bit is set
lw t0, page_table_1
li a0, PTE_A | PTE_D
and t0, t0, a0
bne t0, a0, die
# Enter MPRV again
li t0, MSTATUS_MPRV
csrs mstatus, t0
# Make sure that superpage entries trap when PPN LSBs are set.
li TESTNUM, 4
lw a0, page_table_1 - DRAM_BASE
or a0, a0, 1 << PTE_PPN_SHIFT
sw a0, page_table_1 - DRAM_BASE, t0
sfence.vma
sw a0, page_table_1 - DRAM_BASE, t0
j die
RVTEST_PASS
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
csrr t0, mcause
add t0, t0, -CAUSE_STORE_PAGE_FAULT
bnez t0, die
li t1, 2
bne TESTNUM, t1, 1f
# Make sure D bit is clear
lw t0, page_table_1
and t1, t0, PTE_D
bnez t1, die
skip:
csrr t0, mepc
add t0, t0, 4
csrw mepc, t0
mret
1:
li t1, 3
bne TESTNUM, t1, 1f
# The implementation doesn't appear to set D bits in HW.
# Make sure the D bit really is clear.
lw t0, page_table_1
and t1, t0, PTE_D
bnez t1, die
# Set the D bit.
or t0, t0, PTE_D
sw t0, page_table_1, t1
sfence.vma
mret
1:
li t1, 4
bne TESTNUM, t1, 1f
j pass
1:
die:
RVTEST_FAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
.align 12
page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A
dummy: .dword 0
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,956 | riscv-testdata/testdata/rv64si/scall.S | # See LICENSE for license details.
#*****************************************************************************
# scall.S
#-----------------------------------------------------------------------------
#
# Test syscall trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_BEGIN
#ifdef __MACHINE_MODE
#define sscratch mscratch
#define sstatus mstatus
#define scause mcause
#define stvec mtvec
#define sepc mepc
#define sret mret
#define stvec_handler mtvec_handler
#undef SSTATUS_SPP
#define SSTATUS_SPP MSTATUS_MPP
#endif
li TESTNUM, 2
# This is the expected trap code.
li t1, CAUSE_USER_ECALL
#ifdef __MACHINE_MODE
# If running in M mode, use mstatus.MPP to check existence of U mode.
# Otherwise, if in S mode, then U mode must exist and we don't need to check.
li t0, MSTATUS_MPP
csrc mstatus, t0
csrr t2, mstatus
and t0, t0, t2
beqz t0, 1f
# If U mode doesn't exist, mcause should indicate ECALL from M mode.
li t1, CAUSE_MACHINE_ECALL
#endif
1:
li t0, SSTATUS_SPP
csrc sstatus, t0
la t0, 1f
csrw sepc, t0
sret
1:
li TESTNUM, 1
do_scall:
scall
j fail
TEST_PASSFAIL
# Depending on the test environment, the M-mode version of this test might
# not actually invoke the following handler. Instead, the usual ECALL
# handler in the test environment might detect the CAUSE_USER_ECALL or
# CAUSE_MACHINE_ECALL exception and mark the test as having passed.
# Either way, we'll get the coverage we desire: such a handler must check
# both mcause and TESTNUM, just like the following handler.
.align 2
.global stvec_handler
stvec_handler:
csrr t0, scause
# Check if CLIC mode
csrr t2, stvec
andi t2, t2, 2
# Skip masking if non-CLIC mode
beqz t2, skip_mask
andi t0, t0, 255
skip_mask:
bne t0, t1, fail
la t2, do_scall
csrr t0, sepc
bne t0, t2, fail
j pass
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,248 | riscv-testdata/testdata/rv32uzbb/rori.S | # See LICENSE for license details.
#*****************************************************************************
# rori.S
#-----------------------------------------------------------------------------
#
# Test rori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, rori, 0x00000001, 0x00000001, 0 );
TEST_IMM_OP( 3, rori, 0x80000000, 0x00000001, 1 );
TEST_IMM_OP( 4, rori, 0x02000000, 0x00000001, 7 );
TEST_IMM_OP( 5, rori, 0x00040000, 0x00000001, 14 );
TEST_IMM_OP( 6, rori, 0x00000002, 0x00000001, 31 );
TEST_IMM_OP( 7, rori, 0xffffffff, 0xffffffff, 0 );
TEST_IMM_OP( 8, rori, 0xffffffff, 0xffffffff, 1 );
TEST_IMM_OP( 9, rori, 0xffffffff, 0xffffffff, 7 );
TEST_IMM_OP( 10, rori, 0xffffffff, 0xffffffff, 14 );
TEST_IMM_OP( 11, rori, 0xffffffff, 0xffffffff, 31 );
TEST_IMM_OP( 12, rori, 0x21212121, 0x21212121, 0 );
TEST_IMM_OP( 13, rori, 0x90909090, 0x21212121, 1 );
TEST_IMM_OP( 14, rori, 0x42424242, 0x21212121, 7 );
TEST_IMM_OP( 15, rori, 0x84848484, 0x21212121, 14 );
TEST_IMM_OP( 16, rori, 0x42424242, 0x21212121, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x02000000, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x02000000, 0x00000001, 7 );
TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x00040000, 0x00000001, 14 );
TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x00000002, 0x00000001, 31 );
TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x02000000, 0x00000001, 7 );
TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x00040000, 0x00000001, 14 );
TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x00000002, 0x00000001, 31 );
TEST_IMM_ZEROSRC1( 27, rori, 0, 31 );
TEST_IMM_ZERODEST( 28, rori, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,253 | riscv-testdata/testdata/rv32uzbb/rev8.S | # See LICENSE for license details.
#*****************************************************************************
# rev8.S
#-----------------------------------------------------------------------------
#
# Test rev8 instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, rev8, 0x00000000, 0x00000000);
TEST_R_OP( 3, rev8, 0x01000000, 0x00000001);
TEST_R_OP( 4, rev8, 0x03000000, 0x00000003);
TEST_R_OP( 5, rev8, 0x0080ffff, 0xffff8000 );
TEST_R_OP( 6, rev8, 0x00008000, 0x00800000 );
TEST_R_OP( 7, rev8, 0x0080ffff, 0xffff8000 );
TEST_R_OP( 8, rev8, 0xff7f0000, 0x00007fff);
TEST_R_OP( 9, rev8, 0xffffff7f, 0x7fffffff);
TEST_R_OP( 10, rev8, 0xffff0700, 0x0007ffff );
TEST_R_OP( 11, rev8, 0x00000080, 0x80000000);
TEST_R_OP( 12, rev8, 0x00501f12, 0x121f5000);
TEST_R_OP( 13, rev8, 0x00000000, 0x00000000);
TEST_R_OP( 14, rev8, 0x0e000000, 0x0000000e);
TEST_R_OP( 15, rev8, 0x41134020, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d000000, 13);
TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b000000, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d000000, 13);
TEST_R_DEST_BYPASS( 29, 1, rev8, 0x13000000, 19);
TEST_R_DEST_BYPASS( 20, 2, rev8, 0x22000000, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, rev8, 0x00807f00, 0x007f8000 );
TEST_R_OP( 22, rev8, 0x00808000, 0x00808000 );
TEST_R_OP( 23, rev8, 0x00808001, 0x01808000 );
TEST_R_OP( 24, rev8, 0xff7f0000, 0x00007fff);
TEST_R_OP( 25, rev8, 0xffffff7f, 0x7fffffff);
TEST_R_OP( 26, rev8, 0xffff0700, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,648 | riscv-testdata/testdata/rv32uzbb/rol.S | # See LICENSE for license details.
#*****************************************************************************
# rol.S
#-----------------------------------------------------------------------------
#
# Test rol instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, rol, 0x00000001, 0x00000001, 0 );
TEST_RR_OP( 3, rol, 0x00000002, 0x00000001, 1 );
TEST_RR_OP( 4, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_OP( 5, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_OP( 6, rol, 0x80000000, 0x00000001, 31 );
TEST_RR_OP( 7, rol, 0xffffffff, 0xffffffff, 0 );
TEST_RR_OP( 8, rol, 0xffffffff, 0xffffffff, 1 );
TEST_RR_OP( 9, rol, 0xffffffff, 0xffffffff, 7 );
TEST_RR_OP( 10, rol, 0xffffffff, 0xffffffff, 14 );
TEST_RR_OP( 11, rol, 0xffffffff, 0xffffffff, 31 );
TEST_RR_OP( 12, rol, 0x21212121, 0x21212121, 0 );
TEST_RR_OP( 13, rol, 0x42424242, 0x21212121, 1 );
TEST_RR_OP( 14, rol, 0x90909090, 0x21212121, 7 );
TEST_RR_OP( 15, rol, 0x48484848, 0x21212121, 14 );
TEST_RR_OP( 16, rol, 0x90909090, 0x21212121, 31 );
# Verify that rotates only use bottom five bits
TEST_RR_OP( 17, rol, 0x21212121, 0x21212121, 0xffffffe0 );
TEST_RR_OP( 18, rol, 0x42424242, 0x21212121, 0xffffffe1 );
TEST_RR_OP( 19, rol, 0x90909090, 0x21212121, 0xffffffe7 );
TEST_RR_OP( 20, rol, 0x48484848, 0x21212121, 0xffffffee );
TEST_RR_OP( 21, rol, 0x90909090, 0x21212121, 0xffffffff );
# Verify that rotates ignore top 32 (using true 64-bit values)
TEST_RR_OP( 44, rol, 0x12345678, 0x12345678, 0 );
TEST_RR_OP( 45, rol, 0x23456781, 0x12345678, 4 );
TEST_RR_OP( 46, rol, 0x92345678, 0x92345678, 0 );
TEST_RR_OP( 47, rol, 0x93456789, 0x99345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, rol, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x80000000, 0x00000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x80000000, 0x00000001, 31 );
TEST_RR_ZEROSRC1( 40, rol, 0, 15 );
TEST_RR_ZEROSRC2( 41, rol, 32, 32 );
TEST_RR_ZEROSRC12( 42, rol, 0 );
TEST_RR_ZERODEST( 43, rol, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,011 | riscv-testdata/testdata/rv32uzbb/ctz.S | # See LICENSE for license details.
#*****************************************************************************
# ctz.S
#-----------------------------------------------------------------------------
#
# Test ctz instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, ctz, 32, 0x00000000);
TEST_R_OP( 3, ctz, 0, 0x00000001);
TEST_R_OP( 4, ctz, 0, 0x00000003);
TEST_R_OP( 5, ctz, 15, 0xffff8000 );
TEST_R_OP( 6, ctz, 23, 0x00800000 );
TEST_R_OP( 7, ctz, 15, 0xffff8000 );
TEST_R_OP( 8, ctz, 0, 0x00007fff);
TEST_R_OP( 9, ctz, 0, 0x7fffffff);
TEST_R_OP( 10, ctz, 0, 0x0007ffff );
TEST_R_OP( 11, ctz, 31, 0x80000000);
TEST_R_OP( 12, ctz, 12, 0x121f5000);
TEST_R_OP( 13, ctz, 30, 0xc0000000);
TEST_R_OP( 14, ctz, 1, 0x0000000e);
TEST_R_OP( 15, ctz, 0, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13);
TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13);
TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19);
TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, ctz, 15, 0x007f8000 );
TEST_R_OP( 22, ctz, 15, 0x00808000 );
TEST_R_OP( 23, ctz, 12, 0x01809000 );
TEST_R_OP( 24, ctz, 0, 0x00007fff);
TEST_R_OP( 25, ctz, 0, 0x7fffffff);
TEST_R_OP( 26, ctz, 0, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,400 | riscv-testdata/testdata/rv32uzbb/ror.S | # See LICENSE for license details.
#*****************************************************************************
# ror.S
#-----------------------------------------------------------------------------
#
# Test ror instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, ror, 0x00000001, 0x00000001, 0 );
TEST_RR_OP( 3, ror, 0x80000000, 0x00000001, 1 );
TEST_RR_OP( 4, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_OP( 5, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_OP( 6, ror, 0x00000002, 0x00000001, 31 );
TEST_RR_OP( 7, ror, 0xffffffff, 0xffffffff, 0 );
TEST_RR_OP( 8, ror, 0xffffffff, 0xffffffff, 1 );
TEST_RR_OP( 9, ror, 0xffffffff, 0xffffffff, 7 );
TEST_RR_OP( 10, ror, 0xffffffff, 0xffffffff, 14 );
TEST_RR_OP( 11, ror, 0xffffffff, 0xffffffff, 31 );
TEST_RR_OP( 12, ror, 0x21212121, 0x21212121, 0 );
TEST_RR_OP( 13, ror, 0x90909090, 0x21212121, 1 );
TEST_RR_OP( 14, ror, 0x42424242, 0x21212121, 7 );
TEST_RR_OP( 15, ror, 0x84848484, 0x21212121, 14 );
TEST_RR_OP( 16, ror, 0x42424242, 0x21212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, ror, 0x21212121, 0x21212121, 0xffffffc0 );
TEST_RR_OP( 18, ror, 0x90909090, 0x21212121, 0xffffffc1 );
TEST_RR_OP( 19, ror, 0x42424242, 0x21212121, 0xffffffc7 );
TEST_RR_OP( 20, ror, 0x84848484, 0x21212121, 0xffffffce );
TEST_RR_OP( 21, ror, 0x42424242, 0x21212121, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, ror, 0x60000000, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, ror, 0x00000002, 0x00000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x00000002, 0x00000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x00000002, 0x00000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x00000002, 0x00000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x02000000, 0x00000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x00040000, 0x00000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x00000002, 0x00000001, 31 );
TEST_RR_ZEROSRC1( 40, ror, 0, 15 );
TEST_RR_ZEROSRC2( 41, ror, 32, 32 );
TEST_RR_ZEROSRC12( 42, ror, 0 );
TEST_RR_ZERODEST( 43, ror, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,250 | riscv-testdata/testdata/rv32uzbb/orc_b.S | # See LICENSE for license details.
#*****************************************************************************
# orc.b.S
#-----------------------------------------------------------------------------
#
# Test orc.b instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, orc.b, 0x00000000, 0x00000000);
TEST_R_OP( 3, orc.b, 0x000000ff, 0x00000001);
TEST_R_OP( 4, orc.b, 0x000000ff, 0x00000003);
TEST_R_OP( 5, orc.b, 0xffffff00, 0xffff8000 );
TEST_R_OP( 6, orc.b, 0x00ff0000, 0x00800000 );
TEST_R_OP( 7, orc.b, 0xffffff00, 0xffff8000 );
TEST_R_OP( 8, orc.b, 0x0000ffff, 0x00007fff);
TEST_R_OP( 9, orc.b, 0xffffffff, 0x7fffffff);
TEST_R_OP( 10, orc.b, 0x00ffffff, 0x0007ffff );
TEST_R_OP( 11, orc.b, 0xff000000, 0x80000000);
TEST_R_OP( 12, orc.b, 0xffffff00, 0x121f5000);
TEST_R_OP( 13, orc.b, 0x00000000, 0x00000000);
TEST_R_OP( 14, orc.b, 0x000000ff, 0x0000000e);
TEST_R_OP( 15, orc.b, 0xffffffff, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13);
TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13);
TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19);
TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, orc.b, 0x00ffff00, 0x007f8000 );
TEST_R_OP( 22, orc.b, 0x00ffff00, 0x00808000 );
TEST_R_OP( 23, orc.b, 0xffffff00, 0x01808000 );
TEST_R_OP( 24, orc.b, 0x0000ffff, 0x00007fff);
TEST_R_OP( 25, orc.b, 0xffffffff, 0x7fffffff);
TEST_R_OP( 26, orc.b, 0x00ffffff, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,009 | riscv-testdata/testdata/rv32uzbb/clz.S | # See LICENSE for license details.
#*****************************************************************************
# clz.S
#-----------------------------------------------------------------------------
#
# Test clz instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, clz, 32, 0x00000000);
TEST_R_OP( 3, clz, 31, 0x00000001);
TEST_R_OP( 4, clz, 30, 0x00000003);
TEST_R_OP( 5, clz, 0, 0xffff8000 );
TEST_R_OP( 6, clz, 8, 0x00800000 );
TEST_R_OP( 7, clz, 0, 0xffff8000 );
TEST_R_OP( 8, clz, 17, 0x00007fff);
TEST_R_OP( 9, clz, 1, 0x7fffffff);
TEST_R_OP( 10, clz, 13, 0x0007ffff );
TEST_R_OP( 11, clz, 0, 0x80000000);
TEST_R_OP( 12, clz, 3, 0x121f5000);
TEST_R_OP( 13, clz, 5, 0x04000000);
TEST_R_OP( 14, clz, 28, 0x0000000e);
TEST_R_OP( 15, clz, 2, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, clz, 28, 13);
TEST_R_SRC1_EQ_DEST( 17, clz, 28, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, clz, 28, 13);
TEST_R_DEST_BYPASS( 29, 1, clz, 27, 19);
TEST_R_DEST_BYPASS( 20, 2, clz, 26, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, clz, 5, 0x070f8000 );
TEST_R_OP( 22, clz, 4, 0x08008000 );
TEST_R_OP( 23, clz, 3, 0x18008000 );
TEST_R_OP( 24, clz, 17, 0x00007fff);
TEST_R_OP( 25, clz, 1, 0x7fffffff);
TEST_R_OP( 26, clz, 13, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,036 | riscv-testdata/testdata/rv32uzbb/cpop.S | # See LICENSE for license details.
#*****************************************************************************
# cpop.S
#-----------------------------------------------------------------------------
#
# Test cpop instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, cpop, 0, 0x00000000);
TEST_R_OP( 3, cpop, 1, 0x00000001);
TEST_R_OP( 4, cpop, 2, 0x00000003);
TEST_R_OP( 5, cpop, 17, 0xffff8000 );
TEST_R_OP( 6, cpop, 1, 0x00800000 );
TEST_R_OP( 7, cpop, 18, 0xffff6000 );
TEST_R_OP( 8, cpop, 15, 0x00007fff);
TEST_R_OP( 9, cpop, 31, 0x7fffffff);
TEST_R_OP( 10, cpop, 19, 0x0007ffff );
TEST_R_OP( 11, cpop, 1, 0x80000000);
TEST_R_OP( 12, cpop, 9, 0x121f5000);
TEST_R_OP( 13, cpop, 0, 0x00000000);
TEST_R_OP( 14, cpop, 3, 0x0000000e);
TEST_R_OP( 15, cpop, 7, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13);
TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13);
TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19);
TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, cpop, 8, 0x007f8000 );
TEST_R_OP( 22, cpop, 2, 0x00808000 );
TEST_R_OP( 23, cpop, 3, 0x01808000 );
TEST_R_OP( 24, cpop, 17, 0x30007fff);
TEST_R_OP( 25, cpop, 30, 0x77ffffff);
TEST_R_OP( 26, cpop, 19, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,396 | riscv-testdata/testdata/rv64mi/illegal.S | # See LICENSE for license details.
#*****************************************************************************
# illegal.S
#-----------------------------------------------------------------------------
#
# Test illegal instruction trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
.align 2
.option norvc
li TESTNUM, 2
bad2:
.word 0
j fail
# Skip the rest of the test if S-mode is not present.
li t0, MSTATUS_MPP
csrc mstatus, t0
li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
csrs mstatus, t1
csrr t2, mstatus
and t2, t2, t0
bne t1, t2, pass
# Test vectored interrupts if they are supported.
test_vectored_interrupts:
csrwi mip, MIP_SSIP
csrwi mie, MIP_SSIP
la t0, mtvec_handler + 1
csrrw s0, mtvec, t0
csrr t0, mtvec
andi t0, t0, 1
beqz t0, msip
csrsi mstatus, MSTATUS_MIE
1:
j 1b
msip:
csrw mtvec, s0
# Delegate supervisor software interrupts so WFI won't stall.
csrwi mideleg, MIP_SSIP
# Enter supervisor mode.
la t0, 1f
csrw mepc, t0
li t0, MSTATUS_MPP
csrc mstatus, t0
li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
csrs mstatus, t1
mret
1:
# Make sure WFI doesn't trap when TW=0.
wfi
# Check if paging is supported (Set SUM & MXR and read it back)
and t0, t0, zero
li t0, (SSTATUS_SUM | SSTATUS_MXR)
csrc sstatus, t0
and t1, t1, zero
li t1, (SSTATUS_SUM | SSTATUS_MXR)
csrs sstatus, t1
csrr t2, sstatus
and t2, t2, t0
beqz t2, bare_s_1
csrc sstatus, t0
# Make sure SFENCE.VMA and satp don't trap when TVM=0.
sfence.vma
csrr t0, satp
bad5:
.word 0
j fail
bad6:
# Make sure SFENCE.VMA and satp do trap when TVM=1.
sfence.vma
j fail
bad7:
csrr t0, satp
j fail
test_tsr:
# Make sure SRET doesn't trap when TSR=0.
la t0, bad8
csrw sepc, t0
li t0, SSTATUS_SPP
csrs sstatus, t0
li t0, SSTATUS_SPIE
csrc sstatus, t0
sret
bad8:
.word 0
j fail
# Make sure SRET does trap when TSR=1.
la t0, 1f
csrw sepc, t0
bad9:
sret
1:
j fail
j skip_bare_s
bare_s_1:
# Make sure SFENCE.VMA trap when TVM=0.
sfence.vma
j fail
bare_s_2:
# Set TVM=1. TVM should stay 0 and SFENCE.VMA should still trap
sfence.vma
j fail
# And access to satp should not trap
csrr t0, satp
bare_s_3:
.word 0
j fail
j test_tsr
skip_bare_s:
TEST_PASSFAIL
.align 8
.global mtvec_handler
mtvec_handler:
j synchronous_exception
j msip
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
j fail
synchronous_exception:
li t1, CAUSE_ILLEGAL_INSTRUCTION
csrr t0, mcause
bne t0, t1, fail
csrr t0, mepc
# Make sure mtval contains either 0 or the instruction word.
csrr t2, mtval
beqz t2, 1f
lhu t1, 0(t0)
xor t2, t2, t1
lhu t1, 2(t0)
slli t1, t1, 16
xor t2, t2, t1
bnez t2, fail
1:
la t1, bad2
beq t0, t1, 2f
la t1, bad5
beq t0, t1, 5f
la t1, bad6
beq t0, t1, 6f
la t1, bad7
beq t0, t1, 7f
la t1, bad8
beq t0, t1, 8f
la t1, bad9
beq t0, t1, 9f
la t1, bare_s_1
beq t0, t1, 5f
la t1, bare_s_2
beq t0, t1, 7f
la t1, bare_s_3
beq t0, t1, 7f
j fail
2:
6:
7:
addi t0, t0, 8
csrw mepc, t0
mret
5:
li t1, MSTATUS_TVM
csrs mstatus, t1
j 2b
8:
li t1, MSTATUS_TSR
csrs mstatus, t1
j 2b
9:
j 2b
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,285 | riscv-testdata/testdata/rv64mi/ma_addr.S | # See LICENSE for license details.
#*****************************************************************************
# ma_addr.S
#-----------------------------------------------------------------------------
#
# Test misaligned ld/st trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
.align 2
.option norvc
la s0, data
# indicate it's a load test
li s1, CAUSE_MISALIGNED_LOAD
li s2, CAUSE_LOAD_ACCESS
#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
/* Check that a misaligned load either writes the correct value, or
takes an exception and performs no writeback. */
#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
li TESTNUM, testnum; \
la t2, 1f; \
addi t1, base, offset; \
insn t1, offset(base); \
li t2, res; \
bne t1, t2, fail; \
1:
MISALIGNED_LOAD_TEST(2, lh, s0, 1, SEXT(0xbbcc, 16))
MISALIGNED_LOAD_TEST(3, lhu, s0, 1, 0xbbcc)
MISALIGNED_LOAD_TEST(4, lw, s0, 1, SEXT(0x99aabbcc, 32))
MISALIGNED_LOAD_TEST(5, lw, s0, 2, SEXT(0x8899aabb, 32))
MISALIGNED_LOAD_TEST(6, lw, s0, 3, SEXT(0x778899aa, 32))
#if __riscv_xlen == 64
MISALIGNED_LOAD_TEST(7, lwu, s0, 1, 0x99aabbcc)
MISALIGNED_LOAD_TEST(8, lwu, s0, 2, 0x8899aabb)
MISALIGNED_LOAD_TEST(9, lwu, s0, 3, 0x778899aa)
MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc)
MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb)
MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa)
MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899)
MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788)
MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677)
MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566)
#endif
# indicate it's a store test
li s1, CAUSE_MISALIGNED_STORE
li s2, CAUSE_STORE_ACCESS
/* Check that a misaligned store has some effect and takes no exception,
or takes no effect and generates an exception. This is not very
thorough. */
#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \
li TESTNUM, testnum; \
la t2, 1f; \
addi t1, base, offset; \
insn x0, offset(base); \
lb t1, (offset - 1)(base); \
beqz t1, fail; \
lb t1, (offset + size)(base); \
beqz t1, fail; \
lb t1, (offset + 0)(base); \
bnez t1, fail; \
lb t1, (offset + size - 1)(base); \
bnez t1, fail; \
1:
MISALIGNED_STORE_TEST(22, sh, s0, 1, 2)
MISALIGNED_STORE_TEST(23, sw, s0, 5, 4)
MISALIGNED_STORE_TEST(24, sw, s0, 10, 4)
MISALIGNED_STORE_TEST(25, sw, s0, 15, 4)
#if __riscv_xlen == 64
MISALIGNED_STORE_TEST(26, sd, s0, 25, 8)
MISALIGNED_STORE_TEST(27, sd, s0, 34, 8)
MISALIGNED_STORE_TEST(28, sd, s0, 43, 8)
MISALIGNED_STORE_TEST(29, sd, s0, 52, 8)
MISALIGNED_STORE_TEST(30, sd, s0, 61, 8)
MISALIGNED_STORE_TEST(31, sd, s0, 70, 8)
MISALIGNED_STORE_TEST(32, sd, s0, 79, 8)
#endif
TEST_PASSFAIL
.align 3
.global mtvec_handler
mtvec_handler:
csrr t0, mcause
beq t0, s1, 1f
beq t0, s2, 1f
j fail
1:
csrr t0, mtval
beqz t0, 1f
bne t0, t1, fail
lb t0, (t0)
beqz t0, fail
1:
csrw mepc, t2
mret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
data:
.align 3
.word 0xaabbccdd
.word 0x66778899
.word 0x22334455
.word 0xeeffee11
.fill 0xff, 1, 80
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,119 | riscv-testdata/testdata/rv64mi/ld-misaligned.S | # See LICENSE for license details.
#*****************************************************************************
# lw-unaligned.S
#-----------------------------------------------------------------------------
#
# Test that misaligned loads work or raise the correct exception
# This test assumes the target is little-endian
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
TEST_LD_OP( 2, ld, 0x0807060504030201, 0, tdat );
TEST_LD_OP( 3, ld, 0x0908070605040302, 1, tdat );
TEST_LD_OP( 4, ld, 0x0a09080706050403, 2, tdat );
TEST_LD_OP( 5, ld, 0x0b0a090807060504, 3, tdat );
TEST_LD_OP( 6, ld, 0x0c0b0a0908070605, 4, tdat );
TEST_LD_OP( 7, ld, 0x0d0c0b0a09080706, 5, tdat );
TEST_LD_OP( 8, ld, 0x0e0d0c0b0a090807, 6, tdat );
TEST_LD_OP( 9, ld, 0x0f0e0d0c0b0a0908, 7, tdat );
2:
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
MISALIGNED_LOAD_HANDLER
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
.byte 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
.byte 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,361 | riscv-testdata/testdata/rv64mi/zicntr.S | # See LICENSE for license details.
#*****************************************************************************
# zicntr.S
#-----------------------------------------------------------------------------
#
# Test if Zicntr is implemented correctly
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
# Make sure reading the cycle counter in four ways doesn't trap.
TEST_CASE( 2, x0, 0, csrrc x0, cycle, x0);
TEST_CASE( 3, x0, 0, csrrs x0, cycle, x0);
TEST_CASE( 4, x0, 0, csrrci x0, cycle, 0);
TEST_CASE( 5, x0, 0, csrrsi x0, cycle, 0);
TEST_CASE( 6, x0, 0, csrrc x0, instret, x0);
TEST_CASE( 7, x0, 0, csrrs x0, instret, x0);
TEST_CASE( 8, x0, 0, csrrci x0, instret, 0);
TEST_CASE( 9, x0, 0, csrrsi x0, instret, 0);
#if __riscv_xlen == 32
TEST_CASE(12, x0, 0, csrrc x0, cycleh, x0);
TEST_CASE(13, x0, 0, csrrs x0, cycleh, x0);
TEST_CASE(14, x0, 0, csrrci x0, cycleh, 0);
TEST_CASE(15, x0, 0, csrrsi x0, cycleh, 0);
TEST_CASE(16, x0, 0, csrrc x0, instreth, x0);
TEST_CASE(17, x0, 0, csrrs x0, instreth, x0);
TEST_CASE(18, x0, 0, csrrci x0, instreth, 0);
TEST_CASE(19, x0, 0, csrrsi x0, instreth, 0);
#endif
2:
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
j fail
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,157 | riscv-testdata/testdata/rv64mi/access.S | # See LICENSE for license details.
#*****************************************************************************
# access.S
#-----------------------------------------------------------------------------
#
# Test access-exception behavior.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
.align 2
# Flipping just the MSB should result in an illegal address for RV64.
la t2, fail
li t0, 1 << (__riscv_xlen - 1)
xor t0, t0, t2
# jalr to an illegal address should commit (hence should write rd).
# after the pc is set to rs1, an access exception should be raised.
li TESTNUM, 2
li t1, CAUSE_FETCH_ACCESS
la s1, 1f
li t2, 0
jalr t2, t0
1:
# A load to an illegal address should not commit.
li TESTNUM, 3
li t1, CAUSE_LOAD_ACCESS
la s1, 1f
mv t2, s1
lb t2, (t0)
j fail
1:
j pass
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
li a0, 2
beq TESTNUM, a0, 2f
li a0, 3
beq TESTNUM, a0, 2f
j fail
2:
bne t2, s1, fail
csrr t2, mcause
bne t2, t1, fail
csrw mepc, s1
mret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,052 | riscv-testdata/testdata/rv64mi/sd-misaligned.S | # See LICENSE for license details.
#*****************************************************************************
# sd-unaligned.S
#-----------------------------------------------------------------------------
#
# Test that misaligned stores work or raise the correct exception
# This test assumes the target is little-endian
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
TEST_ST_OP( 2, ld, sd, 0x0102030405060708, 0, tdat );
TEST_ST_OP( 3, ld, sd, 0x090a0b0c0d0e0f10, 1, tdat );
TEST_ST_OP( 4, ld, sd, 0x1112131415161718, 2, tdat );
TEST_ST_OP( 5, ld, sd, 0x191a1b1c1d1e1f20, 3, tdat );
TEST_ST_OP( 6, ld, sd, 0x2122232425262728, 4, tdat );
TEST_ST_OP( 7, ld, sd, 0x292a2b2c2d2e2f30, 5, tdat );
TEST_ST_OP( 8, ld, sd, 0x3132333435363738, 6, tdat );
TEST_ST_OP( 9, ld, sd, 0x393a3b3c3d3e3f40, 7, tdat );
2:
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
MISALIGNED_STORE_HANDLER
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
.zero 16
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,833 | riscv-testdata/testdata/rv64mi/breakpoint.S | # See LICENSE for license details.
#*****************************************************************************
# breakpoint.S
#-----------------------------------------------------------------------------
#
# Test breakpoints, if they are implemented.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGIN
# Set up breakpoint to trap on M-mode fetches.
li TESTNUM, 2
# Set tcontrol.mte, otherwise breakpoints are disabled. This may trap,
# because tcontrol is an optional register.
la a0, 1f
csrrw a0, mtvec, a0
li a1, 0x8
csrs tcontrol, a1
.p2align 2
1:
csrw mtvec, a0
# Enable interrupts; see https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
csrsi mstatus, MSTATUS_MIE
# Skip tselect if hard-wired.
csrw tselect, x0
csrr a1, tselect
bne x0, a1, pass
la a2, 1f
csrw tdata2, a2
li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE
csrw tdata1, a0
# Skip if breakpoint type is unsupported.
csrr a1, tdata1
bne a0, a1, 2f
.align 2
1:
# Trap handler should skip this instruction.
beqz x0, fail
# Make sure reads don't trap.
li TESTNUM, 3
lw a0, (a2)
2:
# Set up breakpoint to trap on M-mode reads.
li TESTNUM, 4
li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD
csrw tdata1, a0
# Skip if breakpoint type is unsupported.
csrr a1, tdata1
bne a0, a1, 2f
la a2, data1
csrw tdata2, a2
# Trap handler should skip this instruction.
lw a2, (a2)
beqz a2, fail
# Make sure writes don't trap.
li TESTNUM, 5
sw x0, (a2)
2:
# Set up breakpoint to trap on M-mode stores.
li TESTNUM, 6
li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_STORE
csrw tdata1, a0
# Skip if breakpoint type is unsupported.
csrr a1, tdata1
bne a0, a1, 2f
# Trap handler should skip this instruction.
sw a2, (a2)
# Make sure store didn't succeed.
li TESTNUM, 7
lw a2, (a2)
bnez a2, fail
# Try to set up a second breakpoint.
li a0, 1
csrw tselect, a0
csrr a1, tselect
bne a0, a1, pass
li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD
csrw tdata1, a0
la a3, data2
csrw tdata2, a3
# Make sure the second breakpoint triggers.
li TESTNUM, 8
lw a3, (a3)
beqz a3, fail
# Make sure the first breakpoint still triggers.
li TESTNUM, 10
la a2, data1
sw a2, (a2)
li TESTNUM, 11
lw a2, (a2)
bnez a2, fail
2:
TEST_PASSFAIL
.align 2
.global mtvec_handler
mtvec_handler:
# Only even-numbered tests should trap.
andi t0, TESTNUM, 1
bnez t0, fail
li t0, CAUSE_BREAKPOINT
csrr t1, mcause
bne t0, t1, fail
csrr t0, mepc
addi t0, t0, 4
csrw mepc, t0
mret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
data1: .word 0
data2: .word 0
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,806 | riscv-testdata/testdata/rv64uzbb/rori.S | # See LICENSE for license details.
#*****************************************************************************
# rori.S
#-----------------------------------------------------------------------------
#
# Test rori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, rori, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, rori, 0x8000000000000000, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, rori, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, rori, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, rori, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, rori, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, rori, 0xffffffffffffffff, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, rori, 0xffffffffffffffff, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, rori, 0xffffffffffffffff, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, rori, 0xffffffffffffffff, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, rori, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, rori, 0x8000000010909090, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, rori, 0x4200000000424242, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, rori, 0x8484000000008484, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, rori, 0x4242424200000000, 0x0000000021212121, 31 );
TEST_IMM_OP( 17, rori, 0x0000000000000002, 0x0000000000000001, 63 );
TEST_IMM_OP( 18, rori, 0xffffffffffffffff, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 19, rori, 0x0004242424200000, 0x0000000021212121, 43 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 20, rori, 0x0200000000000000, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 21, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 22, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 23, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 24, 0, rori, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 25, 1, rori, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 26, 2, rori, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 27, rori, 0, 31 );
TEST_IMM_ZERODEST( 28, rori, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,667 | riscv-testdata/testdata/rv64uzbb/zext_h.S | # See LICENSE for license details.
#*****************************************************************************
# sext_h.S
#-----------------------------------------------------------------------------
#
# Test zext.h instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, zext.h, 0x0000000000000000, 0x0000000000000000);
TEST_R_OP( 3, zext.h, 0x0000000000000001, 0x0000000000000001);
TEST_R_OP( 4, zext.h, 0x0000000000000003, 0x0000000000000003);
TEST_R_OP( 5, zext.h, 0x0000000000008000, 0xffffffffffff8000 );
TEST_R_OP( 6, zext.h, 0x0000000000000000, 0x0000000000800000 );
TEST_R_OP( 7, zext.h, 0x0000000000008000, 0x0004ffffffff8000 );
TEST_R_OP( 8, zext.h, 0x0000000000007fff, 0x0000000000007fff);
TEST_R_OP( 9, zext.h, 0x000000000000ffff, 0x000000007fffffff);
TEST_R_OP( 10, zext.h, 0x000000000000ffff, 0x000000000007ffff );
TEST_R_OP( 11, zext.h, 0x0000000000000000, 0xffffffff80000000);
TEST_R_OP( 12, zext.h, 0x0000000000005000, 0x00ff578f121f5000);
TEST_R_OP( 13, zext.h, 0x0000000000000000, 0x8000000000000000);
TEST_R_OP( 14, zext.h, 0x000000000000000e, 0x000000000000000e);
TEST_R_OP( 15, zext.h, 0x0000000000001341, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, zext.h, 0x000000000000000d, 13);
TEST_R_SRC1_EQ_DEST( 17, zext.h, 0x000000000000000b, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, zext.h, 0x000000000000000d, 13);
TEST_R_DEST_BYPASS( 29, 1, zext.h, 0x0000000000000013, 19);
TEST_R_DEST_BYPASS( 20, 2, zext.h, 0x0000000000000022, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, zext.h, 0x0000000000008000, 0x00000000007f8000 );
TEST_R_OP( 22, zext.h, 0x0000000000008000, 0x0000000000808000 );
TEST_R_OP( 23, zext.h, 0x0000000000008000, 0x0000000001808000 );
TEST_R_OP( 24, zext.h, 0x0000000000007fff, 0x0000000300007fff);
TEST_R_OP( 25, zext.h, 0x000000000000ffff, 0x000000077fffffff);
TEST_R_OP( 26, zext.h, 0x000000000000ffff, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,897 | riscv-testdata/testdata/rv64uzbb/minu.S | # See LICENSE for license details.
#*****************************************************************************
# minu.S
#-----------------------------------------------------------------------------
#
# Test minu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, minu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, minu, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, minu, 0x00000003, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, minu, 0x00000003, 0x00000007, 0x00000003 );
TEST_RR_OP( 6, minu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 7, minu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 8, minu, 0x80000000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 9, minu, 0x00000000, 0x00000000, 0x00007fff );
TEST_RR_OP( 10, minu, 0x00000000, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 11, minu, 0x00007fff, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 12, minu, 0x00007fff, 0x80000000, 0x00007fff );
TEST_RR_OP( 13, minu, 0x7fffffff, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 14, minu, 0x00000000, 0x00000000, 0xffffffff );
TEST_RR_OP( 15, minu, 0x00000001, 0xffffffff, 0x00000001 );
TEST_RR_OP( 16, minu, 0xffffffff, 0xffffffff, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, minu, 13, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, minu, 11, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, minu, 13, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, minu, 11, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, minu, 13, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, minu, 12, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, minu, 13, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, minu, 11, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, minu, 13, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, minu, 10, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, minu, 13, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, minu, 9, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, minu, 13, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, minu, 8, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, minu, 13, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, minu, 7, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, minu, 13, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, minu, 6, 6, 13 );
TEST_RR_ZEROSRC1( 35, minu, 0, -1 );
TEST_RR_ZEROSRC2( 36, minu, 0, -1 );
TEST_RR_ZEROSRC12( 37, minu, 0 );
TEST_RR_ZERODEST( 38, minu, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,616 | riscv-testdata/testdata/rv64uzbb/roriw.S | # See LICENSE for license details.
#*****************************************************************************
# rori.S
#-----------------------------------------------------------------------------
#
# Test rori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, roriw, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, roriw, 0xffffffff80000000, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, roriw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, roriw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, roriw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, roriw, 0xffffffffffffffff, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, roriw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, roriw, 0xffffffff90909090, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, roriw, 0x0000000042424242, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, roriw, 0xffffffff84848484, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, roriw, 0x0000000042424242, 0x0000000021212121, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 20, roriw, 0x0000000002000000, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 21, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 22, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 23, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 24, 0, roriw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 25, 1, roriw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 26, 2, roriw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 27, roriw, 0, 31 );
TEST_IMM_ZERODEST( 28, roriw, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,063 | riscv-testdata/testdata/rv64uzbb/cpopw.S | # See LICENSE for license details.
#*****************************************************************************
# cpopw.S
#-----------------------------------------------------------------------------
#
# Test cpopw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, cpopw, 0, 0x00000000);
TEST_R_OP( 3, cpopw, 1, 0x00000001);
TEST_R_OP( 4, cpopw, 2, 0x00000003);
TEST_R_OP( 5, cpopw, 17, 0xffff8000 );
TEST_R_OP( 6, cpopw, 1, 0x00800000 );
TEST_R_OP( 7, cpopw, 18, 0xffff6000 );
TEST_R_OP( 8, cpopw, 15, 0x00007fff);
TEST_R_OP( 9, cpopw, 31, 0x7fffffff);
TEST_R_OP( 10, cpopw, 19, 0x0007ffff );
TEST_R_OP( 11, cpopw, 1, 0x80000000);
TEST_R_OP( 12, cpopw, 9, 0x121f5000);
TEST_R_OP( 13, cpopw, 0, 0x00000000);
TEST_R_OP( 14, cpopw, 3, 0x0000000e);
TEST_R_OP( 15, cpopw, 7, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, cpopw, 3, 13);
TEST_R_SRC1_EQ_DEST( 17, cpopw, 3, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, cpopw, 3, 13);
TEST_R_DEST_BYPASS( 29, 1, cpopw, 3, 19);
TEST_R_DEST_BYPASS( 20, 2, cpopw, 2, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, cpopw, 8, 0x007f8000 );
TEST_R_OP( 22, cpopw, 2, 0x00808000 );
TEST_R_OP( 23, cpopw, 3, 0x01808000 );
TEST_R_OP( 24, cpopw, 17, 0x30007fff);
TEST_R_OP( 25, cpopw, 30, 0x77ffffff);
TEST_R_OP( 26, cpopw, 19, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,551 | riscv-testdata/testdata/rv64uzbb/andn.S | # See LICENSE for license details.
#*****************************************************************************
# andn.S
#-----------------------------------------------------------------------------
#
# Test and instruction.
# This test is forked from and.S
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_OP( 3, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_OP( 4, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_OP( 5, andn, 0x00000000000f000f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 );
#if __riscv_xlen == 64
TEST_RR_OP( 50, andn, 0x0f000f000f000f00, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 );
TEST_RR_OP( 51, andn, 0x00f000f000f000f0, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f );
TEST_RR_OP( 52, andn, 0x000f000f000f000f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_EQ_DEST( 8, andn, 0x0000000000000000, 0xffffffffff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, andn, 0xfffffffff000f000, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, andn, 0x000000000f000f00, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, andn, 0x0000000000f000f0, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_ZEROSRC1( 24, andn, 0, 0xffffffffff00ff00 );
TEST_RR_ZEROSRC2( 25, andn, 0x0000000000ff00ff, 0x0000000000ff00ff );
TEST_RR_ZEROSRC12( 26, andn, 0 );
TEST_RR_ZERODEST( 27, andn, 0x0000000011111111, 0x0000000022222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,667 | riscv-testdata/testdata/rv64uzbb/sext_h.S | # See LICENSE for license details.
#*****************************************************************************
# sext_h.S
#-----------------------------------------------------------------------------
#
# Test sext.h instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, sext.h, 0x0000000000000000, 0x0000000000000000);
TEST_R_OP( 3, sext.h, 0x0000000000000001, 0x0000000000000001);
TEST_R_OP( 4, sext.h, 0x0000000000000003, 0x0000000000000003);
TEST_R_OP( 5, sext.h, 0xffffffffffff8000, 0xffffffffffff8000 );
TEST_R_OP( 6, sext.h, 0x0000000000000000, 0x0000000000800000 );
TEST_R_OP( 7, sext.h, 0xffffffffffff8000, 0x0004ffffffff8000 );
TEST_R_OP( 8, sext.h, 0x0000000000007fff, 0x0000000000007fff);
TEST_R_OP( 9, sext.h, 0xffffffffffffffff, 0x000000007fffffff);
TEST_R_OP( 10, sext.h, 0xffffffffffffffff, 0x000000000007ffff );
TEST_R_OP( 11, sext.h, 0x0000000000000000, 0xffffffff80000000);
TEST_R_OP( 12, sext.h, 0x0000000000005000, 0x00ff578f121f5000);
TEST_R_OP( 13, sext.h, 0x0000000000000000, 0x8000000000000000);
TEST_R_OP( 14, sext.h, 0x000000000000000e, 0x000000000000000e);
TEST_R_OP( 15, sext.h, 0x0000000000001341, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, sext.h, 0x000000000000000d, 13);
TEST_R_SRC1_EQ_DEST( 17, sext.h, 0x000000000000000b, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, sext.h, 0x000000000000000d, 13);
TEST_R_DEST_BYPASS( 29, 1, sext.h, 0x0000000000000013, 19);
TEST_R_DEST_BYPASS( 20, 2, sext.h, 0x0000000000000022, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, sext.h, 0xffffffffffff8000, 0x00000000007f8000 );
TEST_R_OP( 22, sext.h, 0xffffffffffff8000, 0x0000000000808000 );
TEST_R_OP( 23, sext.h, 0xffffffffffff8000, 0x0000000001808000 );
TEST_R_OP( 24, sext.h, 0x0000000000007fff, 0x0000000300007fff);
TEST_R_OP( 25, sext.h, 0xffffffffffffffff, 0x000000077fffffff);
TEST_R_OP( 26, sext.h, 0xffffffffffffffff, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,613 | riscv-testdata/testdata/rv64uzbb/rev8.S | # See LICENSE for license details.
#*****************************************************************************
# rev8.S
#-----------------------------------------------------------------------------
#
# Test rev8 instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, rev8, 0x0000000000000000, 0x0000000000000000);
TEST_R_OP( 3, rev8, 0x0100000000000000, 0x0000000000000001);
TEST_R_OP( 4, rev8, 0x0300000000000000, 0x0000000000000003);
TEST_R_OP( 5, rev8, 0x0080ffffffffffff, 0xffffffffffff8000 );
TEST_R_OP( 6, rev8, 0x0000800000000000, 0x0000000000800000 );
TEST_R_OP( 7, rev8, 0x0080ffffffff0400, 0x0004ffffffff8000 );
TEST_R_OP( 8, rev8, 0xff7f000000000000, 0x0000000000007fff);
TEST_R_OP( 9, rev8, 0xffffff7f00000000, 0x000000007fffffff);
TEST_R_OP( 10, rev8, 0xffff070000000000, 0x000000000007ffff );
TEST_R_OP( 11, rev8, 0x00000080ffffffff, 0xffffffff80000000);
TEST_R_OP( 12, rev8, 0x00501f128f57ff00, 0x00ff578f121f5000);
TEST_R_OP( 13, rev8, 0x0000000000000080, 0x8000000000000000);
TEST_R_OP( 14, rev8, 0x0e00000000000000, 0x000000000000000e);
TEST_R_OP( 15, rev8, 0x41134020030000a0, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, rev8, 0x0d00000000000000, 13);
TEST_R_SRC1_EQ_DEST( 17, rev8, 0x0b00000000000000, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, rev8, 0x0d00000000000000, 13);
TEST_R_DEST_BYPASS( 29, 1, rev8, 0x1300000000000000, 19);
TEST_R_DEST_BYPASS( 20, 2, rev8, 0x2200000000000000, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, rev8, 0x00807f0000000000, 0x00000000007f8000 );
TEST_R_OP( 22, rev8, 0x0080800000000000, 0x0000000000808000 );
TEST_R_OP( 23, rev8, 0x0080800100000000, 0x0000000001808000 );
TEST_R_OP( 24, rev8, 0xff7f000003000000, 0x0000000300007fff);
TEST_R_OP( 25, rev8, 0xffffff7f07000000, 0x000000077fffffff);
TEST_R_OP( 26, rev8, 0xffff07000f000000, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,222 | riscv-testdata/testdata/rv64uzbb/max.S | # See LICENSE for license details.
#*****************************************************************************
# max.S
#-----------------------------------------------------------------------------
#
# Test max instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, max, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
TEST_RR_OP( 3, max, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 );
TEST_RR_OP( 4, max, 0x0000000000000007, 0x0000000000000003, 0x0000000000000007 );
TEST_RR_OP( 5, max, 0x0000000000000007, 0x0000000000000007, 0x0000000000000003 );
TEST_RR_OP( 6, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 7, max, 0x0000000000000000, 0xffffffff80000000, 0x0000000000000000 );
TEST_RR_OP( 8, max, 0xffffffffffff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 9, max, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 10, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 11, max, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 12, max, 0x0000000000007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 13, max, 0x000000007fffffff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 14, max, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 15, max, 0x0000000000000001, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 16, max, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, max, 14, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, max, 13, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, max, 13, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, max, 13, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, max, 14, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, max, 13, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, max, 14, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, max, 13, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, max, 15, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, max, 13, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, max, 16, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, max, 13, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, max, 17, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, max, 13, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, max, 18, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, max, 13, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, max, 19, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, max, 13, 6, 13 );
TEST_RR_ZEROSRC1( 35, max, 0, -1 );
TEST_RR_ZEROSRC2( 36, max, 0, -1 );
TEST_RR_ZEROSRC12( 37, max, 0 );
TEST_RR_ZERODEST( 38, max, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,360 | riscv-testdata/testdata/rv64uzbb/rolw.S | # See LICENSE for license details.
#*****************************************************************************
# rolw.S
#-----------------------------------------------------------------------------
#
# Test rolw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, rolw, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, rolw, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_RR_OP( 4, rolw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_OP( 5, rolw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, rolw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_OP( 7, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, rolw, 0xffffffffffffffff, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, rolw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, rolw, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_RR_OP( 14, rolw, 0xffffffff90909090, 0x0000000021212121, 7 );
TEST_RR_OP( 15, rolw, 0x0000000048484848, 0x0000000021212121, 14 );
TEST_RR_OP( 16, rolw, 0xffffffff90909090, 0x0000000021212121, 31 );
# Verify that rotates only use bottom five bits
TEST_RR_OP( 17, rolw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
TEST_RR_OP( 18, rolw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 );
TEST_RR_OP( 19, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffe7 );
TEST_RR_OP( 20, rolw, 0x0000000048484848, 0x0000000021212121, 0xffffffffffffffee );
TEST_RR_OP( 21, rolw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffff );
# Verify that rotates ignore top 32 (using true 64-bit values)
TEST_RR_OP( 44, rolw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_RR_OP( 45, rolw, 0x0000000023456781, 0xffffffff12345678, 4 );
TEST_RR_OP( 46, rolw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_RR_OP( 47, rolw, 0xffffffff93456789, 0x0000000099345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, rolw, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, rolw, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, rolw, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, rolw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, rolw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, rolw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, rolw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, rolw, 0, 15 );
TEST_RR_ZEROSRC2( 41, rolw, 32, 32 );
TEST_RR_ZEROSRC12( 42, rolw, 0 );
TEST_RR_ZERODEST( 43, rolw, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,230 | riscv-testdata/testdata/rv64uzbb/rol.S | # See LICENSE for license details.
#*****************************************************************************
# rol.S
#-----------------------------------------------------------------------------
#
# Test rol instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, rol, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, rol, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_RR_OP( 4, rol, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_OP( 5, rol, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, rol, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_OP( 7, rol, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, rol, 0xffffffffffffffff, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, rol, 0xffffffffffffffff, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, rol, 0xffffffffffffffff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, rol, 0xffffffffffffffff, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, rol, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, rol, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_RR_OP( 14, rol, 0x0000001090909080, 0x0000000021212121, 7 );
TEST_RR_OP( 15, rol, 0x0000084848484000, 0x0000000021212121, 14 );
TEST_RR_OP( 16, rol, 0x1090909080000000, 0x0000000021212121, 31 );
# Verify that rotates only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, rol, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, rol, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, rol, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, rol, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, rol, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffff );
TEST_RR_OP( 50, rol, 0x8000000000000000, 0x0000000000000001, 63 );
TEST_RR_OP( 51, rol, 0xffffffffffffffff, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, rol, 0x0909080000000109, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, rol, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, rol, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, rol, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, rol, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, rol, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, rol, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, rol, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, rol, 0, 15 );
TEST_RR_ZEROSRC2( 41, rol, 32, 32 );
TEST_RR_ZEROSRC12( 42, rol, 0 );
TEST_RR_ZERODEST( 43, rol, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,220 | riscv-testdata/testdata/rv64uzbb/min.S | # See LICENSE for license details.
#*****************************************************************************
# min.S
#-----------------------------------------------------------------------------
#
# Test min instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
TEST_RR_OP( 3, min, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001 );
TEST_RR_OP( 4, min, 0x0000000000000003, 0x0000000000000003, 0x0000000000000007 );
TEST_RR_OP( 5, min, 0x0000000000000003, 0x0000000000000007, 0x0000000000000003 );
TEST_RR_OP( 6, min, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 7, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
TEST_RR_OP( 8, min, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 9, min, 0x0000000000000000, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 10, min, 0x0000000000000000, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 11, min, 0x0000000000007fff, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 12, min, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 13, min, 0xffffffffffff8000, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 14, min, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 15, min, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 16, min, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, min, 13, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, min, 11, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, min, 13, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, min, 11, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, min, 13, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, min, 12, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, min, 13, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, min, 11, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, min, 13, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, min, 10, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, min, 13, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, min, 9, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, min, 13, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, min, 8, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, min, 13, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, min, 7, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, min, 13, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, min, 6, 6, 13 );
TEST_RR_ZEROSRC1( 35, min, -1, -1 );
TEST_RR_ZEROSRC2( 36, min, -1, -1 );
TEST_RR_ZEROSRC12( 37, min, 0 );
TEST_RR_ZERODEST( 38, min, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,171 | riscv-testdata/testdata/rv64uzbb/ctz.S | # See LICENSE for license details.
#*****************************************************************************
# ctz.S
#-----------------------------------------------------------------------------
#
# Test ctz instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, ctz, 64, 0x0000000000000000);
TEST_R_OP( 3, ctz, 0, 0x0000000000000001);
TEST_R_OP( 4, ctz, 0, 0x0000000000000003);
TEST_R_OP( 5, ctz, 15, 0xffffffffffff8000 );
TEST_R_OP( 6, ctz, 23, 0x0000000000800000 );
TEST_R_OP( 7, ctz, 15, 0x0004ffffffff8000 );
TEST_R_OP( 8, ctz, 0, 0x0000000000007fff);
TEST_R_OP( 9, ctz, 0, 0x000000007fffffff);
TEST_R_OP( 10, ctz, 0, 0x000000000007ffff );
TEST_R_OP( 11, ctz, 31, 0xffffffff80000000);
TEST_R_OP( 12, ctz, 12, 0x00ff578f121f5000);
TEST_R_OP( 13, ctz, 63, 0x8000000000000000);
TEST_R_OP( 14, ctz, 1, 0x000000000000000e);
TEST_R_OP( 15, ctz, 0, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, ctz, 0, 13);
TEST_R_SRC1_EQ_DEST( 17, ctz, 0, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, ctz, 0, 13);
TEST_R_DEST_BYPASS( 29, 1, ctz, 0, 19);
TEST_R_DEST_BYPASS( 20, 2, ctz, 1, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, ctz, 15, 0x00000000007f8000 );
TEST_R_OP( 22, ctz, 15, 0x0000000000808000 );
TEST_R_OP( 23, ctz, 12, 0x0000000001809000 );
TEST_R_OP( 24, ctz, 0, 0x0000000300007fff);
TEST_R_OP( 25, ctz, 0, 0x000000077fffffff);
TEST_R_OP( 26, ctz, 0, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,231 | riscv-testdata/testdata/rv64uzbb/ror.S | # See LICENSE for license details.
#*****************************************************************************
# ror.S
#-----------------------------------------------------------------------------
#
# Test ror instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, ror, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, ror, 0x8000000000000000, 0x0000000000000001, 1 );
TEST_RR_OP( 4, ror, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_RR_OP( 5, ror, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, ror, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_RR_OP( 7, ror, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, ror, 0xffffffffffffffff, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, ror, 0xffffffffffffffff, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, ror, 0xffffffffffffffff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, ror, 0xffffffffffffffff, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, ror, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, ror, 0x8000000010909090, 0x0000000021212121, 1 );
TEST_RR_OP( 14, ror, 0x4200000000424242, 0x0000000021212121, 7 );
TEST_RR_OP( 15, ror, 0x8484000000008484, 0x0000000021212121, 14 );
TEST_RR_OP( 16, ror, 0x4242424200000000, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, ror, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, ror, 0x8000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, ror, 0x4200000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, ror, 0x8484000000008484, 0x0000000021212121, 0xffffffffffffffce );
TEST_RR_OP( 21, ror, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff );
TEST_RR_OP( 50, ror, 0x0000000000000002, 0x0000000000000001, 63 );
TEST_RR_OP( 51, ror, 0xffffffffffffffff, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, ror, 0x0004242424200000, 0x0000000021212121, 43 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, ror, 0x0200000000000000, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, ror, 0x0004000000000000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, ror, 0x6000000000000000, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, ror, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, ror, 0x0200000000000000, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, ror, 0x0004000000000000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, ror, 0x0000000200000000, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, ror, 0, 15 );
TEST_RR_ZEROSRC2( 41, ror, 32, 32 );
TEST_RR_ZEROSRC12( 42, ror, 0 );
TEST_RR_ZERODEST( 43, ror, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,537 | riscv-testdata/testdata/rv64uzbb/xnor.S | # See LICENSE for license details.
#*****************************************************************************
# xnor.S
#-----------------------------------------------------------------------------
#
# Test xnor instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_OP( 3, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_OP( 4, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_OP( 5, xnor, 0xffffffffff00ff00, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 );
#if __riscv_xlen == 64
TEST_RR_OP( 50, xnor, 0x00ff00ff00ff00ff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 );
TEST_RR_OP( 51, xnor, 0xf00ff00ff00ff00f, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f );
TEST_RR_OP( 52, xnor, 0xff00ff00ff00ff00, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, xnor, 0xffffffffffffffff, 0xffffffffff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, xnor, 0x000000000ff00ff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, xnor, 0x0000000000ff00ff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, xnor, 0xfffffffff00ff00f, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_ZEROSRC1( 24, xnor, 0x0000000000ff00ff, 0xffffffffff00ff00 );
TEST_RR_ZEROSRC2( 25, xnor, 0xffffffffff00ff00, 0x0000000000ff00ff );
TEST_RR_ZEROSRC12( 26, xnor, -1 );
TEST_RR_ZERODEST( 27, xnor, 0x0000000011111111, 0x0000000022222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,570 | riscv-testdata/testdata/rv64uzbb/orc_b.S | # See LICENSE for license details.
#*****************************************************************************
# orc.b.S
#-----------------------------------------------------------------------------
#
# Test orc.b instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, orc.b, 0x0000000000000000, 0x0000000000000000);
TEST_R_OP( 3, orc.b, 0x00000000000000ff, 0x0000000000000001);
TEST_R_OP( 4, orc.b, 0x00000000000000ff, 0x0000000000000003);
TEST_R_OP( 5, orc.b, 0xffffffffffffff00, 0xffffffffffff8000 );
TEST_R_OP( 6, orc.b, 0x0000000000ff0000, 0x0000000000800000 );
TEST_R_OP( 7, orc.b, 0x00ffffffffffff00, 0x0004ffffffff8000 );
TEST_R_OP( 8, orc.b, 0x000000000000ffff, 0x0000000000007fff);
TEST_R_OP( 9, orc.b, 0x00000000ffffffff, 0x000000007fffffff);
TEST_R_OP( 10, orc.b, 0x0000000000ffffff, 0x000000000007ffff );
TEST_R_OP( 11, orc.b, 0xffffffffff000000, 0xffffffff80000000);
TEST_R_OP( 12, orc.b, 0x00ffffffffffff00, 0x00ff578f121f5000);
TEST_R_OP( 13, orc.b, 0xff00000000000000, 0x8000000000000000);
TEST_R_OP( 14, orc.b, 0x00000000000000ff, 0x000000000000000e);
TEST_R_OP( 15, orc.b, 0xff0000ffffffffff, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, orc.b, 0xff, 13);
TEST_R_SRC1_EQ_DEST( 17, orc.b, 0xff, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, orc.b, 0xff, 13);
TEST_R_DEST_BYPASS( 29, 1, orc.b, 0xff, 19);
TEST_R_DEST_BYPASS( 20, 2, orc.b, 0xff, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, orc.b, 0x0000000000ffff00, 0x00000000007f8000 );
TEST_R_OP( 22, orc.b, 0x0000000000ffff00, 0x0000000000808000 );
TEST_R_OP( 23, orc.b, 0x00000000ffffff00, 0x0000000001808000 );
TEST_R_OP( 24, orc.b, 0x000000ff0000ffff, 0x0000000300007fff);
TEST_R_OP( 25, orc.b, 0x000000ffffffffff, 0x000000077fffffff);
TEST_R_OP( 26, orc.b, 0x000000ff00ffffff, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,174 | riscv-testdata/testdata/rv64uzbb/clz.S | # See LICENSE for license details.
#*****************************************************************************
# clz.S
#-----------------------------------------------------------------------------
#
# Test clz instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, clz, 64, 0x0000000000000000);
TEST_R_OP( 3, clz, 63, 0x0000000000000001);
TEST_R_OP( 4, clz, 62, 0x0000000000000003);
TEST_R_OP( 5, clz, 0, 0xffffffffffff8000 );
TEST_R_OP( 6, clz, 40, 0x0000000000800000 );
TEST_R_OP( 7, clz, 13, 0x0004ffffffff8000 );
TEST_R_OP( 8, clz, 49, 0x0000000000007fff);
TEST_R_OP( 9, clz, 33, 0x000000007fffffff);
TEST_R_OP( 10, clz, 45, 0x000000000007ffff );
TEST_R_OP( 11, clz, 0, 0xffffffff80000000);
TEST_R_OP( 12, clz, 8, 0x00ff578f121f5000);
TEST_R_OP( 13, clz, 0, 0x8000000000000000);
TEST_R_OP( 14, clz, 60, 0x000000000000000e);
TEST_R_OP( 15, clz, 0, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, clz, 60, 13);
TEST_R_SRC1_EQ_DEST( 17, clz, 60, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, clz, 60, 13);
TEST_R_DEST_BYPASS( 29, 1, clz, 59, 19);
TEST_R_DEST_BYPASS( 20, 2, clz, 58, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, clz, 37, 0x00000000070f8000 );
TEST_R_OP( 22, clz, 36, 0x0000000008008000 );
TEST_R_OP( 23, clz, 35, 0x0000000018008000 );
TEST_R_OP( 24, clz, 30, 0x0000000300007fff);
TEST_R_OP( 25, clz, 29, 0x000000077fffffff);
TEST_R_OP( 26, clz, 28, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,490 | riscv-testdata/testdata/rv64uzbb/orn.S | # See LICENSE for license details.
#*****************************************************************************
# orn.S
#-----------------------------------------------------------------------------
#
# Test orn instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_OP( 3, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_OP( 4, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_OP( 5, orn, 0xffffffffff0fff0f, 0xfffffffff00ff00f, 0xfffffffff0f0f0f0 );
#if __riscv_xlen == 64
TEST_RR_OP( 50, orn, 0x0fff0fff0fff0fff, 0x0ff00ff00ff00ff0, 0xf0f0f0f0f0f0f0f0 );
TEST_RR_OP( 51, orn, 0xf0fff0fff0fff0ff, 0x00ff00ff00ff00ff, 0x0f0f0f0f0f0f0f0f );
TEST_RR_OP( 52, orn, 0xff0fff0fff0fff0f, 0xf00ff00ff00ff00f, 0xf0f0f0f0f0f0f0f0 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, orn, 0xffffffffffffffff, 0xffffffffff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, orn, 0xfffffffffff0fff0, 0xffffffffff00ff00, 0x000000000f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, orn, 0x000000000fff0fff, 0x000000000ff00ff0, 0xfffffffff0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, orn, 0xfffffffff0fff0ff, 0x0000000000ff00ff, 0x000000000f0f0f0f );
TEST_RR_ZEROSRC1( 24, orn, 0x0000000000ff00ff, 0xffffffffff00ff00 );
TEST_RR_ZEROSRC2( 25, orn, -1, 0x0000000000ff00ff );
TEST_RR_ZEROSRC12( 26, orn, -1 );
TEST_RR_ZERODEST( 27, orn, 0x0000000011111111, 0x0000000022222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,903 | riscv-testdata/testdata/rv64uzbb/maxu.S | # See LICENSE for license details.
#*****************************************************************************
# maxu.S
#-----------------------------------------------------------------------------
#
# Test maxu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, maxu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, maxu, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, maxu, 0x00000007, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, maxu, 0x00000007, 0x00000007, 0x00000003 );
TEST_RR_OP( 6, maxu, 0xffff8000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 7, maxu, 0x80000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 8, maxu, 0xffff8000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 9, maxu, 0x00007fff, 0x00000000, 0x00007fff );
TEST_RR_OP( 10, maxu, 0x7fffffff, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 11, maxu, 0x7fffffff, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 12, maxu, 0x80000000, 0x80000000, 0x00007fff );
TEST_RR_OP( 13, maxu, 0xffff8000, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 14, maxu, 0xffffffff, 0x00000000, 0xffffffff );
TEST_RR_OP( 15, maxu, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP( 16, maxu, 0xffffffff, 0xffffffff, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, maxu, 14, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, maxu, 13, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, maxu, 13, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, maxu, 13, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, maxu, 14, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, maxu, 13, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, maxu, 14, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, maxu, 13, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, maxu, 15, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, maxu, 13, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, maxu, 16, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, maxu, 13, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, maxu, 17, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, maxu, 13, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, maxu, 18, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, maxu, 13, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, maxu, 19, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, maxu, 13, 6, 13 );
TEST_RR_ZEROSRC1( 35, maxu, -1, -1 );
TEST_RR_ZEROSRC2( 36, maxu, -1, -1 );
TEST_RR_ZEROSRC12( 37, maxu, 0 );
TEST_RR_ZERODEST( 38, maxu, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,068 | riscv-testdata/testdata/rv64uzbb/rorw.S | # See LICENSE for license details.
#*****************************************************************************
# rorw.S
#-----------------------------------------------------------------------------
#
# Test rorw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, rorw, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, rorw, 0xffffffff80000000, 0x0000000000000001, 1 );
TEST_RR_OP( 4, rorw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_RR_OP( 5, rorw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, rorw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_RR_OP( 7, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, rorw, 0xffffffffffffffff, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, rorw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, rorw, 0xffffffff90909090, 0x0000000021212121, 1 );
TEST_RR_OP( 14, rorw, 0x0000000042424242, 0x0000000021212121, 7 );
TEST_RR_OP( 15, rorw, 0xffffffff84848484, 0x0000000021212121, 14 );
TEST_RR_OP( 16, rorw, 0x0000000042424242, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, rorw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, rorw, 0xffffffff90909090, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, rorw, 0xffffffff84848484, 0x0000000021212121, 0xffffffffffffffce );
TEST_RR_OP( 21, rorw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, rorw, 0x0000000002000000, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, rorw, 0x0000000000040000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, rorw, 0x0000000060000000, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, rorw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, rorw, 0x0000000002000000, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, rorw, 0x0000000000040000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, rorw, 0x0000000000000002, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, rorw, 0, 15 );
TEST_RR_ZEROSRC2( 41, rorw, 32, 32 );
TEST_RR_ZEROSRC12( 42, rorw, 0 );
TEST_RR_ZERODEST( 43, rorw, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,667 | riscv-testdata/testdata/rv64uzbb/sext_b.S | # See LICENSE for license details.
#*****************************************************************************
# sext_b.S
#-----------------------------------------------------------------------------
#
# Test sext.b instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, sext.b, 0x0000000000000000, 0x0000000000000000);
TEST_R_OP( 3, sext.b, 0x0000000000000001, 0x0000000000000001);
TEST_R_OP( 4, sext.b, 0x0000000000000003, 0x0000000000000003);
TEST_R_OP( 5, sext.b, 0x0000000000000000, 0xffffffffffff8000 );
TEST_R_OP( 6, sext.b, 0x0000000000000000, 0x0000000000800000 );
TEST_R_OP( 7, sext.b, 0x0000000000000000, 0x0004ffffffff8000 );
TEST_R_OP( 8, sext.b, 0xffffffffffffffff, 0x0000000000007fff);
TEST_R_OP( 9, sext.b, 0xffffffffffffffff, 0x000000007fffffff);
TEST_R_OP( 10, sext.b, 0xffffffffffffffff, 0x000000000007ffff );
TEST_R_OP( 11, sext.b, 0x0000000000000000, 0xffffffff80000000);
TEST_R_OP( 12, sext.b, 0x0000000000000000, 0x00ff578f121f5000);
TEST_R_OP( 13, sext.b, 0x0000000000000000, 0x8000000000000000);
TEST_R_OP( 14, sext.b, 0x000000000000000e, 0x000000000000000e);
TEST_R_OP( 15, sext.b, 0x0000000000000041, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, sext.b, 0x000000000000000d, 13);
TEST_R_SRC1_EQ_DEST( 17, sext.b, 0x000000000000000b, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, sext.b, 0x000000000000000d, 13);
TEST_R_DEST_BYPASS( 29, 1, sext.b, 0x0000000000000013, 19);
TEST_R_DEST_BYPASS( 20, 2, sext.b, 0x0000000000000022, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, sext.b, 0x0000000000000000, 0x00000000007f8000 );
TEST_R_OP( 22, sext.b, 0x0000000000000000, 0x0000000000808000 );
TEST_R_OP( 23, sext.b, 0x0000000000000000, 0x0000000001808000 );
TEST_R_OP( 24, sext.b, 0xffffffffffffffff, 0x0000000300007fff);
TEST_R_OP( 25, sext.b, 0xffffffffffffffff, 0x000000077fffffff);
TEST_R_OP( 26, sext.b, 0xffffffffffffffff, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,038 | riscv-testdata/testdata/rv64uzbb/ctzw.S | # See LICENSE for license details.
#*****************************************************************************
# ctzw.S
#-----------------------------------------------------------------------------
#
# Test ctzw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, ctzw, 32, 0x00000000);
TEST_R_OP( 3, ctzw, 0, 0x00000001);
TEST_R_OP( 4, ctzw, 0, 0x00000003);
TEST_R_OP( 5, ctzw, 15, 0xffff8000 );
TEST_R_OP( 6, ctzw, 23, 0x00800000 );
TEST_R_OP( 7, ctzw, 15, 0xffff8000 );
TEST_R_OP( 8, ctzw, 0, 0x00007fff);
TEST_R_OP( 9, ctzw, 0, 0x7fffffff);
TEST_R_OP( 10, ctzw, 0, 0x0007ffff );
TEST_R_OP( 11, ctzw, 31, 0x80000000);
TEST_R_OP( 12, ctzw, 12, 0x121f5000);
TEST_R_OP( 13, ctzw, 30, 0xc0000000);
TEST_R_OP( 14, ctzw, 1, 0x0000000e);
TEST_R_OP( 15, ctzw, 0, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, ctzw, 0, 13);
TEST_R_SRC1_EQ_DEST( 17, ctzw, 0, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, ctzw, 0, 13);
TEST_R_DEST_BYPASS( 29, 1, ctzw, 0, 19);
TEST_R_DEST_BYPASS( 20, 2, ctzw, 1, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, ctzw, 15, 0x007f8000 );
TEST_R_OP( 22, ctzw, 15, 0x00808000 );
TEST_R_OP( 23, ctzw, 12, 0x01809000 );
TEST_R_OP( 24, ctzw, 0, 0x00007fff);
TEST_R_OP( 25, ctzw, 0, 0x7fffffff);
TEST_R_OP( 26, ctzw, 0, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,036 | riscv-testdata/testdata/rv64uzbb/clzw.S | # See LICENSE for license details.
#*****************************************************************************
# clzw.S
#-----------------------------------------------------------------------------
#
# Test clzw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, clzw, 32, 0x00000000);
TEST_R_OP( 3, clzw, 31, 0x00000001);
TEST_R_OP( 4, clzw, 30, 0x00000003);
TEST_R_OP( 5, clzw, 0, 0xffff8000 );
TEST_R_OP( 6, clzw, 8, 0x00800000 );
TEST_R_OP( 7, clzw, 0, 0xffff8000 );
TEST_R_OP( 8, clzw, 17, 0x00007fff);
TEST_R_OP( 9, clzw, 1, 0x7fffffff);
TEST_R_OP( 10, clzw, 13, 0x0007ffff );
TEST_R_OP( 11, clzw, 0, 0x80000000);
TEST_R_OP( 12, clzw, 3, 0x121f5000);
TEST_R_OP( 13, clzw, 5, 0x04000000);
TEST_R_OP( 14, clzw, 28, 0x0000000e);
TEST_R_OP( 15, clzw, 2, 0x20401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, clzw, 28, 13);
TEST_R_SRC1_EQ_DEST( 17, clzw, 28, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, clzw, 28, 13);
TEST_R_DEST_BYPASS( 29, 1, clzw, 27, 19);
TEST_R_DEST_BYPASS( 20, 2, clzw, 26, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, clzw, 5, 0x070f8000 );
TEST_R_OP( 22, clzw, 4, 0x08008000 );
TEST_R_OP( 23, clzw, 3, 0x18008000 );
TEST_R_OP( 24, clzw, 17, 0x00007fff);
TEST_R_OP( 25, clzw, 1, 0x7fffffff);
TEST_R_OP( 26, clzw, 13, 0x0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,193 | riscv-testdata/testdata/rv64uzbb/cpop.S | # See LICENSE for license details.
#*****************************************************************************
# cpop.S
#-----------------------------------------------------------------------------
#
# Test cpop instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_R_OP( 2, cpop, 0, 0x0000000000000000);
TEST_R_OP( 3, cpop, 1, 0x0000000000000001);
TEST_R_OP( 4, cpop, 2, 0x0000000000000003);
TEST_R_OP( 5, cpop, 49, 0xffffffffffff8000 );
TEST_R_OP( 6, cpop, 1, 0x0000000000800000 );
TEST_R_OP( 7, cpop, 34, 0x0004ffffffff8000 );
TEST_R_OP( 8, cpop, 15, 0x0000000000007fff);
TEST_R_OP( 9, cpop, 31, 0x000000007fffffff);
TEST_R_OP( 10, cpop, 19, 0x000000000007ffff );
TEST_R_OP( 11, cpop, 33, 0xffffffff80000000);
TEST_R_OP( 12, cpop, 27, 0x00ff578f121f5000);
TEST_R_OP( 13, cpop, 1, 0x8000000000000000);
TEST_R_OP( 14, cpop, 3, 0x000000000000000e);
TEST_R_OP( 15, cpop, 11, 0xa000000320401341);
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_R_SRC1_EQ_DEST( 16, cpop, 3, 13);
TEST_R_SRC1_EQ_DEST( 17, cpop, 3, 11);
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_R_DEST_BYPASS( 18, 0, cpop, 3, 13);
TEST_R_DEST_BYPASS( 29, 1, cpop, 3, 19);
TEST_R_DEST_BYPASS( 20, 2, cpop, 2, 34);
#-------------------------------------------------------------
# Other tests
#-------------------------------------------------------------
TEST_R_OP( 21, cpop, 8, 0x00000000007f8000 );
TEST_R_OP( 22, cpop, 2, 0x0000000000808000 );
TEST_R_OP( 23, cpop, 3, 0x0000000001808000 );
TEST_R_OP( 24, cpop, 17, 0x0000000300007fff);
TEST_R_OP( 25, cpop, 34, 0x000000077fffffff);
TEST_R_OP( 26, cpop, 23, 0x0000000f0007ffff);
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,077 | riscv-testdata/testdata/rv64ua/amomaxu_w.S | # See LICENSE for license details.
#*****************************************************************************
# amomaxu_d.S
#-----------------------------------------------------------------------------
#
# Test amomaxu.w instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
TEST_CASE(2, a4, 0xffffffff80000000, \
li a0, 0xffffffff80000000; \
li a1, 0xfffffffffffff800; \
la a3, amo_operand; \
sw a0, 0(a3); \
amomaxu.w a4, a1, 0(a3); \
)
TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
TEST_CASE(4, a4, 0, \
li a1, 0xffffffffffffffff; \
sw x0, 0(a3); \
amomaxu.w a4, a1, 0(a3); \
)
TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
TEST_CASE(6, a4, 1, \
li a0, 0x0000000000000001; \
li a1, 0x8000000000000000; \
la a3, amo_operand; \
sw a0, 0(a3); \
amomaxu.w a4, a1, 0(a3); \
)
TEST_CASE(7, a5, 1, lw a5, 0(a3))
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
.bss
.align 3
amo_operand:
.dword 0
|
matthiasgoergens/zkvm | 1,089 | riscv-testdata/testdata/rv64ua/amomin_w.S | # See LICENSE for license details.
#*****************************************************************************
# amomin_d.S
#-----------------------------------------------------------------------------
#
# Test amomin.w instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
TEST_CASE(2, a4, 0xffffffff80000000, \
li a0, 0xffffffff80000000; \
li a1, 0xfffffffffffff800; \
la a3, amo_operand; \
sw a0, 0(a3); \
amomin.w a4, a1, 0(a3); \
)
TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
TEST_CASE(4, a4, 0, \
li a1, 0xffffffffffffffff; \
sw x0, 0(a3); \
amomin.w a4, a1, 0(a3); \
)
TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
TEST_CASE(6, a4, 1, \
li a0, 0x0000000000000001; \
li a1, 0x0000000080000000; \
la a3, amo_operand; \
sw a0, 0(a3); \
amomin.w a4, a1, 0(a3); \
)
TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3))
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
.bss
.align 3
amo_operand:
.dword 0
|
matthiasgoergens/zkvm | 2,116 | riscv-testdata/testdata/rv64ua/lrsc.S | # See LICENSE for license details.
#*****************************************************************************
# lrsr.S
#-----------------------------------------------------------------------------
#
# Test LR/SC instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
# get a unique core id
la a0, coreid
li a1, 1
amoadd.w a2, a1, (a0)
# for now, only run this on core 0
1:li a3, 1
bgeu a2, a3, 1b
1: lw a1, (a0)
bltu a1, a3, 1b
# make sure that sc without a reservation fails.
TEST_CASE( 2, a4, 1, \
la a0, foo; \
li a5, 0xdeadbeef; \
sc.w a4, a5, (a0); \
)
# make sure the failing sc did not commit into memory
TEST_CASE( 3, a4, 0, \
lw a4, foo; \
)
#
# Disable test case 4 for now. It assumes a <1K reservation granule, when
# in reality any size granule is valid. After discussion in issue #315,
# decided to simply disable the test for now.
# (See https://github.com/riscv/riscv-tests/issues/315)
#
## make sure that sc with the wrong reservation fails.
## TODO is this actually mandatory behavior?
#TEST_CASE( 4, a4, 1, \
# la a0, foo; \
# la a1, fooTest3; \
# lr.w a1, (a1); \
# sc.w a4, a1, (a0); \
#)
#define LOG_ITERATIONS 10
# have each core add its coreid+1 to foo 1024 times
la a0, foo
li a1, 1<<LOG_ITERATIONS
addi a2, a2, 1
1: lr.w a4, (a0)
add a4, a4, a2
sc.w a4, a4, (a0)
bnez a4, 1b
addi a1, a1, -1
bnez a1, 1b
# wait for all cores to finish
la a0, barrier
li a1, 1
amoadd.w x0, a1, (a0)
1: lw a1, (a0)
blt a1, a3, 1b
fence
# expected result is 512*ncores*(ncores+1)
TEST_CASE( 5, a0, 0, \
lw a0, foo; \
slli a1, a3, LOG_ITERATIONS-1; \
1:sub a0, a0, a1; \
addi a3, a3, -1; \
bgez a3, 1b
)
# make sure that sc-after-successful-sc fails.
TEST_CASE( 6, a1, 2, \
la a0, foo; \
1:lr.w a1, (a0); \
sc.w a1, x0, (a0); \
bnez a1, 1b; \
sc.w a1, x0, (a0); \
/* make sure that sc-after-failed-sc fails, too */ \
sc.w a2, x0, (a0); \
add a1, a1, a2
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
coreid: .word 0
barrier: .word 0
foo: .word 0
.skip 1024
fooTest3: .word 0
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,038 | riscv-testdata/testdata/rv64ua/amomax_w.S | # See LICENSE for license details.
#*****************************************************************************
# amomax_d.S
#-----------------------------------------------------------------------------
#
# Test amomax.w instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
TEST_CASE(2, a4, 0xffffffff80000000, \
li a0, 0xffffffff80000000; \
li a1, 0xfffffffffffff800; \
la a3, amo_operand; \
sw a0, 0(a3); \
amomax.w a4, a1, 0(a3); \
)
TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
TEST_CASE(4, a4, 0, \
li a1, 1; \
sw x0, 0(a3); \
amomax.w a4, a1, 0(a3); \
)
TEST_CASE(5, a5, 1, lw a5, 0(a3))
TEST_CASE(6, a4, 1, \
li a0, 0x0000000000000001; \
li a1, 0x0000000080000000; \
la a3, amo_operand; \
sw a0, 0(a3); \
amomax.w a4, a1, 0(a3); \
)
TEST_CASE(7, a5, 1, lw a5, 0(a3))
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
.bss
.align 3
amo_operand:
.dword 0
|
matthiasgoergens/zkvm | 1,060 | riscv-testdata/testdata/rv64ua/amominu_w.S | # See LICENSE for license details.
#*****************************************************************************
# amominu_d.S
#-----------------------------------------------------------------------------
#
# Test amominu.w instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
TEST_CASE(2, a4, 0xffffffff80000000, \
li a0, 0xffffffff80000000; \
li a1, 0xfffffffffffff800; \
la a3, amo_operand; \
sw a0, 0(a3); \
amominu.w a4, a1, 0(a3); \
)
TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
TEST_CASE(4, a4, 0, \
li a1, 0xffffffffffffffff; \
sw x0, 0(a3); \
amominu.w a4, a1, 0(a3); \
)
TEST_CASE(5, a5, 0, lw a5, 0(a3))
TEST_CASE(6, a4, 1, \
li a0, 0x0000000000000001; \
li a1, 0x8000000000000000; \
la a3, amo_operand; \
sw a0, 0(a3); \
amominu.w a4, a1, 0(a3); \
)
TEST_CASE(7, a5, 0, lw a5, 0(a3))
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
.bss
.align 3
amo_operand:
.dword 0
|
matthiasgoergens/zkvm | 3,001 | riscv-testdata/testdata/rv32uzba/sh3add.S | # See LICENSE for license details.
#*****************************************************************************
# sh3add.S
#-----------------------------------------------------------------------------
#
# Test sh3add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh3add, 0xffff8000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, sh3add, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, sh3add, 0xffff8000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 8, sh3add, 0x00007fff, 0x00000000, 0x00007fff );
TEST_RR_OP( 9, sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff );
TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff );
TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 );
TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff );
TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 );
TEST_RR_ZEROSRC12( 37, sh3add, 0 );
TEST_RR_ZERODEST( 38, sh3add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,983 | riscv-testdata/testdata/rv32uzba/sh2add.S | # See LICENSE for license details.
#*****************************************************************************
# sh2add.S
#-----------------------------------------------------------------------------
#
# Test sh2add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh2add, 0xffff8000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, sh2add, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, sh2add, 0xffff8000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 8, sh2add, 0x00007fff, 0x00000000, 0x00007fff );
TEST_RR_OP( 9, sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff );
TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff );
TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 );
TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff );
TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 );
TEST_RR_ZEROSRC12( 37, sh2add, 0 );
TEST_RR_ZERODEST( 38, sh2add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,982 | riscv-testdata/testdata/rv32uzba/sh1add.S | # See LICENSE for license details.
#*****************************************************************************
# sh1add.S
#-----------------------------------------------------------------------------
#
# Test sh1add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sh1add, 0xffff8000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, sh1add, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, sh1add, 0xffff8000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 8, sh1add, 0x00007fff, 0x00000000, 0x00007fff );
TEST_RR_OP( 9, sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff );
TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff );
TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff );
TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 );
TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 );
TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 );
TEST_RR_ZEROSRC12( 37, sh1add, 0 );
TEST_RR_ZERODEST( 38, sh1add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,869 | riscv-testdata/testdata/rv64uzbs/binvi.S | # See LICENSE for license details.
#*****************************************************************************
# binvi.S
#-----------------------------------------------------------------------------
#
# Test binvi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, binvi, 0x0000000000000000, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, binvi, 0x0000000000000003, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, binvi, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, binvi, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, binvi, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, binvi, 0xfffffffffffffffe, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, binvi, 0xfffffffffffffffd, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, binvi, 0xffffffffffffff7f, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, binvi, 0xffffffffffffbfff, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, binvi, 0xffffffff7fffffff, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, binvi, 0x0000000021212120, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, binvi, 0x0000000021212123, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, binvi, 0x00000000212121a1, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, binvi, 0x0000000021216121, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, binvi, 0x00000000a1212121, 0x0000000021212121, 31 );
#if __riscv_xlen == 64
TEST_IMM_OP( 50, binvi, 0x8000000000000001, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, binvi, 0xffffff7fffffffff, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, binvi, 0x0000080021212121, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, binvi, 0x00000081, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, binvi, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, binvi, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, binvi, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 24, binvi, 0x00008000, 15 );
TEST_IMM_ZERODEST( 25, binvi, 1024, 10 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,285 | riscv-testdata/testdata/rv64uzbs/binv.S | # See LICENSE for license details.
#*****************************************************************************
# binv.S
#-----------------------------------------------------------------------------
#
# Test binv instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, binv, 0x0000000000000000, 0x0000000000000001, 0 );
TEST_RR_OP( 3, binv, 0x0000000000000003, 0x0000000000000001, 1 );
TEST_RR_OP( 4, binv, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_OP( 5, binv, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_OP( 6, binv, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_OP( 7, binv, 0xfffffffffffffffe, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, binv, 0xfffffffffffffffd, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, binv, 0xffffffffffffff7f, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, binv, 0xffffffffffffbfff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, binv, 0xffffffff7fffffff, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, binv, 0x0000000021212120, 0x0000000021212121, 0 );
TEST_RR_OP( 13, binv, 0x0000000021212123, 0x0000000021212121, 1 );
TEST_RR_OP( 14, binv, 0x00000000212121a1, 0x0000000021212121, 7 );
TEST_RR_OP( 15, binv, 0x0000000021216121, 0x0000000021212121, 14 );
TEST_RR_OP( 16, binv, 0x00000000a1212121, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, binv, 0x0000000021212120, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, binv, 0x0000000021212123, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, binv, 0x00000000212121a1, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, binv, 0x0000000021216121, 0x0000000021212121, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, binv, 0x8000000021212121, 0x0000000021212121, 0xffffffffffffffff );
TEST_RR_OP( 50, binv, 0x8000000000000001, 0x0000000000000001, 63 );
TEST_RR_OP( 51, binv, 0xffffff7fffffffff, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, binv, 0x0000080021212121, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, binv, 0x00000081, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, binv, 0x00004001, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, binv, 11, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, binv, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, binv, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, binv, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, binv, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, binv, 0x00008000, 15 );
TEST_RR_ZEROSRC2( 41, binv, 33, 32 );
TEST_RR_ZEROSRC12( 42, binv, 1 );
TEST_RR_ZERODEST( 43, binv, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,823 | riscv-testdata/testdata/rv64uzbs/bset.S | # See LICENSE for license details.
#*****************************************************************************
# bset.S
#-----------------------------------------------------------------------------
#
# Test bset instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 );
TEST_RR_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 );
TEST_RR_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_RR_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 );
TEST_RR_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 );
TEST_RR_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 );
TEST_RR_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_RR_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_RR_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_RR_OP( 12, bset, 0x21212121, 0x21212121, 0 );
TEST_RR_OP( 13, bset, 0x21212123, 0x21212121, 1 );
TEST_RR_OP( 14, bset, 0x212121a1, 0x21212121, 7 );
TEST_RR_OP( 15, bset, 0x21212121, 0x21212121, 13 );
TEST_RR_OP( 16, bset, 0x84848484, 0x84848484, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, bset, 0x21212121, 0x21212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, bset, 0x21212123, 0x21212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, bset, 0x212121a1, 0x21212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, bset, 0x8484c484, 0x84848484, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, bset, 0xc484848421212121, 0xc484848421212121, 0xffffffffffffffff );
TEST_RR_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 );
TEST_RR_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, bset, 0x00000081, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, bset, 0x00005551, 0x00005551, 14 );
TEST_RR_SRC12_EQ_DEST( 24, bset, 11, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, bset, 0xff00ff01, 0xff00ff00, 0 );
TEST_RR_DEST_BYPASS( 26, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 );
TEST_RR_DEST_BYPASS( 27, 2, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, bset, 0xff00ff01, 0xff00ff00, 0 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, bset, 0xff00ff01, 0xff00ff00, 0 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, bset, 0x0ff00ff0, 0x0ff00ff0, 27 );
TEST_RR_ZEROSRC1( 40, bset, 0x00008000, 15 );
TEST_RR_ZEROSRC2( 41, bset, 33, 32 );
TEST_RR_ZEROSRC12( 42, bset, 1 );
TEST_RR_ZERODEST( 43, bset, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,312 | riscv-testdata/testdata/rv64uzbs/bexti.S | # See LICENSE for license details.
#*****************************************************************************
# bexti.S
#-----------------------------------------------------------------------------
#
# Test bexti instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, bexti, 0, 0xff00ff00, 0 );
TEST_IMM_OP( 3, bexti, 1, 0x00ff00ff, 1 );
TEST_IMM_OP( 4, bexti, 1, 0xff00ff00, 8 );
TEST_IMM_OP( 5, bexti, 0, 0x0ff00ff0, 14 );
TEST_IMM_OP( 6, bexti, 1, 0x0ff00ff0, 27 );
TEST_IMM_OP( 7, bexti, 1, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, bexti, 1, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, bexti, 1, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, bexti, 1, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, bexti, 1, 0xffffffffffffffff, 27 );
TEST_IMM_OP( 12, bexti, 1, 0x21212121, 0 );
TEST_IMM_OP( 13, bexti, 0, 0x21212121, 1 );
TEST_IMM_OP( 14, bexti, 0, 0x21212121, 7 );
TEST_IMM_OP( 15, bexti, 1, 0x21212121, 13 );
TEST_IMM_OP( 16, bexti, 1, 0x84848484, 31 );
#if __riscv_xlen == 64
TEST_IMM_OP( 50, bexti, 0, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, bexti, 1, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, bexti, 1, 0xffffffff00000000, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, bexti, 0, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, bexti, 1, 0xff00ff00, 8 );
TEST_IMM_DEST_BYPASS( 19, 1, bexti, 0, 0x0ff00ff0, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, bexti, 1, 0x0ff00ff0, 27 );
TEST_IMM_SRC1_BYPASS( 21, 0, bexti, 1, 0xff00ff00, 8 );
TEST_IMM_SRC1_BYPASS( 22, 1, bexti, 0, 0x0ff00ff0, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, bexti, 1, 0x0ff00ff0, 27 );
TEST_IMM_ZEROSRC1( 24, bexti, 0, 31 );
TEST_IMM_ZERODEST( 25, bexti, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,378 | riscv-testdata/testdata/rv64uzbs/bext.S | # See LICENSE for license details.
#*****************************************************************************
# bext.S
#-----------------------------------------------------------------------------
#
# Test bext instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, bext, 0, 0xff00ff00, 0 );
TEST_RR_OP( 3, bext, 1, 0x00ff00ff, 1 );
TEST_RR_OP( 4, bext, 1, 0xff00ff00, 8 );
TEST_RR_OP( 5, bext, 0, 0x0ff00ff0, 14 );
TEST_RR_OP( 6, bext, 1, 0x0ff00ff0, 27 );
TEST_RR_OP( 7, bext, 1, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, bext, 1, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, bext, 1, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, bext, 1, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, bext, 1, 0xffffffffffffffff, 27 );
TEST_RR_OP( 12, bext, 1, 0x21212121, 0 );
TEST_RR_OP( 13, bext, 0, 0x21212121, 1 );
TEST_RR_OP( 14, bext, 0, 0x21212121, 7 );
TEST_RR_OP( 15, bext, 1, 0x21212121, 13 );
TEST_RR_OP( 16, bext, 1, 0x84848484, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, bext, 1, 0x21212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, bext, 0, 0x21212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, bext, 0, 0x21212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, bext, 0, 0x84848484, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, bext, 1, 0xc484848421212121, 0xffffffffffffffff );
TEST_RR_OP( 50, bext, 0, 0x0000000000000001, 63 );
TEST_RR_OP( 51, bext, 1, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, bext, 1, 0xffffffff00000000, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, bext, 0, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, bext, 1, 0x00005551, 14 );
TEST_RR_SRC12_EQ_DEST( 24, bext, 0, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, bext, 0, 0xff00ff00, 0 );
TEST_RR_DEST_BYPASS( 26, 1, bext, 1, 0x00ff00ff, 1 );
TEST_RR_DEST_BYPASS( 27, 2, bext, 1, 0xff00ff00, 8 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, bext, 0, 0xff00ff00, 0 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, bext, 1, 0x00ff00ff, 1 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, bext, 1, 0xff00ff00, 8 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, bext, 0, 0xff00ff00, 0 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, bext, 1, 0x00ff00ff, 1 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, bext, 1, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, bext, 1, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, bext, 0, 0x0ff00ff0, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, bext, 1, 0x0ff00ff0, 27 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, bext, 1, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, bext, 0, 0x0ff00ff0, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, bext, 1, 0x0ff00ff0, 27 );
TEST_RR_ZEROSRC1( 40, bext, 0, 15 );
TEST_RR_ZEROSRC2( 41, bext, 0, 32 );
TEST_RR_ZEROSRC12( 42, bext, 0 );
TEST_RR_ZERODEST( 43, bext, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,811 | riscv-testdata/testdata/rv64uzbs/bclr.S | # See LICENSE for license details.
#*****************************************************************************
# bclr.S
#-----------------------------------------------------------------------------
#
# Test bclr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, bclr, 0xff00ff00, 0xff00ff00, 0 );
TEST_RR_OP( 3, bclr, 0x00ff00fd, 0x00ff00ff, 1 );
TEST_RR_OP( 4, bclr, 0xff00fe00, 0xff00ff00, 8 );
TEST_RR_OP( 5, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 );
TEST_RR_OP( 6, bclr, 0x07f00ff0, 0x0ff00ff0, 27 );
TEST_RR_OP( 7, bclr, 0xfffffffffffffffe, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, bclr, 0xfffffffffffffffd, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, bclr, 0xffffffffffffff7f, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, bclr, 0xffffffffffffbfff, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, bclr, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 );
TEST_RR_OP( 12, bclr, 0x21212120, 0x21212121, 0 );
TEST_RR_OP( 13, bclr, 0x21212121, 0x21212121, 1 );
TEST_RR_OP( 14, bclr, 0x21212121, 0x21212121, 7 );
TEST_RR_OP( 15, bclr, 0x21210121, 0x21212121, 13 );
TEST_RR_OP( 16, bclr, 0x04848484, 0x84848484, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, bclr, 0x21212120, 0x21212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, bclr, 0x21212121, 0x21212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, bclr, 0x84848484, 0x84848484, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, bclr, 0x4484848421212121, 0xc484848421212121, 0xffffffffffffffff );
TEST_RR_OP( 50, bclr, 0x0000000000000001, 0x0000000000000001, 63 );
TEST_RR_OP( 51, bclr, 0xffffff7fffffffff, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, bclr, 0xfffff7ff00000000, 0xffffffff00000000, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, bclr, 0x00000001, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, bclr, 0x00001551, 0x00005551, 14 );
TEST_RR_SRC12_EQ_DEST( 24, bclr, 3, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, bclr, 0xff00ff00, 0xff00ff00, 0 );
TEST_RR_DEST_BYPASS( 26, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 );
TEST_RR_DEST_BYPASS( 27, 2, bclr, 0xff00fe00, 0xff00ff00, 8 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, bclr, 0xff00ff00, 0xff00ff00, 0 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, bclr, 0xff00fe00, 0xff00ff00, 8 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, bclr, 0xff00ff00, 0xff00ff00, 0 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, bclr, 0x00ff00fd, 0x00ff00ff, 1 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, bclr, 0xff00fe00, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, bclr, 0xff00fe00, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, bclr, 0x07f00ff0, 0x0ff00ff0, 27 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, bclr, 0xff00fe00, 0xff00ff00, 8 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, bclr, 0x0ff00ff0, 0x0ff00ff0, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, bclr, 0x07f00ff0, 0x0ff00ff0, 27 );
TEST_RR_ZEROSRC1( 40, bclr, 0, 15 );
TEST_RR_ZEROSRC2( 41, bclr, 32, 32 );
TEST_RR_ZEROSRC12( 42, bclr, 0 );
TEST_RR_ZERODEST( 43, bclr, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,585 | riscv-testdata/testdata/rv64uzbs/bseti.S | # See LICENSE for license details.
#*****************************************************************************
# bset.S
#-----------------------------------------------------------------------------
#
# Test bset instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, bset, 0xff00ff01, 0xff00ff00, 0 );
TEST_IMM_OP( 3, bset, 0x00ff00ff, 0x00ff00ff, 1 );
TEST_IMM_OP( 4, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_IMM_OP( 5, bset, 0x0ff04ff0, 0x0ff00ff0, 14 );
TEST_IMM_OP( 6, bset, 0x0ff00ff0, 0x0ff00ff0, 27 );
TEST_IMM_OP( 7, bset, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 8, bset, 0x0000000000000003, 0x0000000000000001, 1 );
TEST_IMM_OP( 9, bset, 0x0000000000000081, 0x0000000000000001, 7 );
TEST_IMM_OP( 10, bset, 0x0000000000004001, 0x0000000000000001, 14 );
TEST_IMM_OP( 11, bset, 0x0000000080000001, 0x0000000000000001, 31 );
TEST_IMM_OP( 12, bset, 0x21212121, 0x21212121, 0 );
TEST_IMM_OP( 13, bset, 0x21212123, 0x21212121, 1 );
TEST_IMM_OP( 14, bset, 0x212121a1, 0x21212121, 7 );
TEST_IMM_OP( 15, bset, 0x21212121, 0x21212121, 13 );
TEST_IMM_OP( 16, bset, 0x84848484, 0x84848484, 31 );
#if __riscv_xlen == 64
TEST_IMM_OP( 50, bset, 0x8000000000000001, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, bset, 0xffffffffffffffff, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, bset, 0xffffffff00000000, 0xffffffff00000000, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, bset, 0x00000081, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, bset, 0xff00ff01, 0xff00ff00, 0 );
TEST_IMM_DEST_BYPASS( 19, 1, bset, 0x00ff00ff, 0x00ff00ff, 1 );
TEST_IMM_DEST_BYPASS( 20, 2, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_IMM_SRC1_BYPASS( 21, 0, bset, 0xff00ff00, 0xff00ff00, 8 );
TEST_IMM_SRC1_BYPASS( 22, 1, bset, 0x0ff04ff0, 0x0ff00ff0, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, bset, 0x0ff00ff0, 0x0ff00ff0, 27 );
TEST_IMM_ZEROSRC1( 24, bset, 0x00008000, 15 );
TEST_IMM_ZERODEST( 25, bset, 1024, 10 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,600 | riscv-testdata/testdata/rv64uzbs/bclri.S | # See LICENSE for license details.
#*****************************************************************************
# bclri.S
#-----------------------------------------------------------------------------
#
# Test bclri instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, bclri, 0xff00ff00, 0xff00ff00, 0 );
TEST_IMM_OP( 3, bclri, 0x00ff00fd, 0x00ff00ff, 1 );
TEST_IMM_OP( 4, bclri, 0xff00fe00, 0xff00ff00, 8 );
TEST_IMM_OP( 5, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 );
TEST_IMM_OP( 6, bclri, 0x07f00ff0, 0x0ff00ff0, 27 );
TEST_IMM_OP( 7, bclri, 0xfffffffffffffffe, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, bclri, 0xfffffffffffffffd, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, bclri, 0xffffffffffffff7f, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, bclri, 0xffffffffffffbfff, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, bclri, 0xfffffffff7ffffff, 0xffffffffffffffff, 27 );
TEST_IMM_OP( 12, bclri, 0x21212120, 0x21212121, 0 );
TEST_IMM_OP( 13, bclri, 0x21212121, 0x21212121, 1 );
TEST_IMM_OP( 14, bclri, 0x21212121, 0x21212121, 7 );
TEST_IMM_OP( 15, bclri, 0x21210121, 0x21212121, 13 );
TEST_IMM_OP( 16, bclri, 0x04848484, 0x84848484, 31 );
#if __riscv_xlen == 64
TEST_IMM_OP( 50, bclri, 0x0000000000000001, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, bclri, 0xffffff7fffffffff, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, bclri, 0xfffff7ff00000000, 0xffffffff00000000, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, bclri, 0x00000001, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, bclri, 0xff00fe00, 0xff00ff00, 8 );
TEST_IMM_DEST_BYPASS( 19, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 );
TEST_IMM_SRC1_BYPASS( 21, 0, bclri, 0xff00fe00, 0xff00ff00, 8 );
TEST_IMM_SRC1_BYPASS( 22, 1, bclri, 0x0ff00ff0, 0x0ff00ff0, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, bclri, 0x07f00ff0, 0x0ff00ff0, 27 );
TEST_IMM_ZEROSRC1( 24, bclri, 0, 31 );
TEST_IMM_ZERODEST( 25, bclri, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,184 | riscv-testdata/testdata/rv64ui/addw.S | # See LICENSE for license details.
#*****************************************************************************
# addw.S
#-----------------------------------------------------------------------------
#
# Test addw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, addw, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, addw, 0x00000002, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, addw, 0x0000000a, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 );
TEST_RR_ZEROSRC1( 35, addw, 15, 15 );
TEST_RR_ZEROSRC2( 36, addw, 32, 32 );
TEST_RR_ZEROSRC12( 37, addw, 0 );
TEST_RR_ZERODEST( 38, addw, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,028 | riscv-testdata/testdata/rv64ui/blt.S | # See LICENSE for license details.
#*****************************************************************************
# blt.S
#-----------------------------------------------------------------------------
#
# Test blt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, blt, 0, 1 );
TEST_BR2_OP_TAKEN( 3, blt, -1, 1 );
TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 );
TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 );
TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
blt x0, x1, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,538 | riscv-testdata/testdata/rv64ui/bgeu.S | # See LICENSE for license details.
#*****************************************************************************
# bgeu.S
#-----------------------------------------------------------------------------
#
# Test bgeu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 );
TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 24, x1, 3, \
li x1, 1; \
bgeu x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,680 | riscv-testdata/testdata/rv64ui/andi.S | # See LICENSE for license details.
#*****************************************************************************
# andi.S
#-----------------------------------------------------------------------------
#
# Test andi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,358 | riscv-testdata/testdata/rv64ui/sllw.S | # See LICENSE for license details.
#*****************************************************************************
# sllw.S
#-----------------------------------------------------------------------------
#
# Test sllw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sllw, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, sllw, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_RR_OP( 4, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_OP( 5, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_OP( 7, sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7 );
TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 );
TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 );
# Verify that shifts only use bottom five bits
TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 );
TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 );
TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee );
TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff );
# Verify that shifts ignore top 32 (using true 64-bit values)
TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 );
TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, sllw, 0, 15 );
TEST_RR_ZEROSRC2( 41, sllw, 32, 32 );
TEST_RR_ZEROSRC12( 42, sllw, 0 );
TEST_RR_ZERODEST( 43, sllw, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,750 | riscv-testdata/testdata/rv64ui/sd.S | # See LICENSE for license details.
#*****************************************************************************
# sd.S
#-----------------------------------------------------------------------------
#
# Test sd instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0, tdat );
TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8, tdat );
TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16, tdat );
TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat );
# Test with negative offset
TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 );
TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 );
TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8, tdat8 );
TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x5, 0x1234567812345678, \
la x1, tdat9; \
li x2, 0x1234567812345678; \
addi x4, x1, -32; \
sd x2, 32(x4); \
ld x5, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x5821309858213098, \
la x1, tdat9; \
li x2, 0x5821309858213098; \
addi x1, x1, -3; \
sd x2, 11(x1); \
la x4, tdat10; \
ld x5, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .dword 0xdeadbeefdeadbeef
tdat2: .dword 0xdeadbeefdeadbeef
tdat3: .dword 0xdeadbeefdeadbeef
tdat4: .dword 0xdeadbeefdeadbeef
tdat5: .dword 0xdeadbeefdeadbeef
tdat6: .dword 0xdeadbeefdeadbeef
tdat7: .dword 0xdeadbeefdeadbeef
tdat8: .dword 0xdeadbeefdeadbeef
tdat9: .dword 0xdeadbeefdeadbeef
tdat10: .dword 0xdeadbeefdeadbeef
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,827 | riscv-testdata/testdata/rv64ui/slli.S | # See LICENSE for license details.
#*****************************************************************************
# slli.S
#-----------------------------------------------------------------------------
#
# Test slli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 );
#if __riscv_xlen == 64
TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
TEST_IMM_ZERODEST( 25, slli, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,366 | riscv-testdata/testdata/rv64ui/bltu.S | # See LICENSE for license details.
#*****************************************************************************
# bltu.S
#-----------------------------------------------------------------------------
#
# Test bltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
bltu x0, x1, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,149 | riscv-testdata/testdata/rv64ui/bge.S | # See LICENSE for license details.
#*****************************************************************************
# bge.S
#-----------------------------------------------------------------------------
#
# Test bge instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bge, 0, 0 );
TEST_BR2_OP_TAKEN( 3, bge, 1, 1 );
TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
TEST_BR2_OP_TAKEN( 5, bge, 1, 0 );
TEST_BR2_OP_TAKEN( 6, bge, 1, -1 );
TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 );
TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 );
TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 24, x1, 3, \
li x1, 1; \
bge x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,975 | riscv-testdata/testdata/rv64ui/srliw.S | # See LICENSE for license details.
#*****************************************************************************
# srliw.S
#-----------------------------------------------------------------------------
#
# Test srliw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, srliw, 0xffffffff80000000, 0xffffffff80000000, 0 );
TEST_IMM_OP( 3, srliw, 0x0000000040000000, 0xffffffff80000000, 1 );
TEST_IMM_OP( 4, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_IMM_OP( 5, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_IMM_OP( 6, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
TEST_IMM_OP( 7, srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, srliw, 0x000000007fffffff, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 );
# Verify that shifts ignore top 32 (using true 64-bit values)
TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 );
TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 );
TEST_IMM_ZERODEST( 25, srliw, 31, 28 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,389 | riscv-testdata/testdata/rv64ui/sraw.S | # See LICENSE for license details.
#*****************************************************************************
# sraw.S
#-----------------------------------------------------------------------------
#
# Test sraw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sraw, 0xffffffff80000000, 0xffffffff80000000, 0 );
TEST_RR_OP( 3, sraw, 0xffffffffc0000000, 0xffffffff80000000, 1 );
TEST_RR_OP( 4, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_OP( 5, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_OP( 6, sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_RR_OP( 7, sraw, 0x000000007fffffff, 0x000000007fffffff, 0 );
TEST_RR_OP( 8, sraw, 0x000000003fffffff, 0x000000007fffffff, 1 );
TEST_RR_OP( 9, sraw, 0x0000000000ffffff, 0x000000007fffffff, 7 );
TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 );
TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 );
TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0 );
TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7 );
TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
# Verify that shifts only use bottom five bits
TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 );
TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 );
TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 );
TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee );
TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
# Verify that shifts ignore top 32 (using true 64-bit values)
TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 );
TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_ZEROSRC1( 40, sraw, 0, 15 );
TEST_RR_ZEROSRC2( 41, sraw, 32, 32 );
TEST_RR_ZEROSRC12( 42, sraw, 0 );
TEST_RR_ZERODEST( 43, sraw, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,371 | riscv-testdata/testdata/rv64ui/addiw.S | # See LICENSE for license details.
#*****************************************************************************
# addiw.S
#-----------------------------------------------------------------------------
#
# Test addiw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, addiw, 0x00000000, 0x00000000, 0x000 );
TEST_IMM_OP( 3, addiw, 0x00000002, 0x00000001, 0x001 );
TEST_IMM_OP( 4, addiw, 0x0000000a, 0x00000003, 0x007 );
TEST_IMM_OP( 5, addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
TEST_IMM_OP( 6, addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
TEST_IMM_OP( 7, addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 );
TEST_IMM_OP( 8, addiw, 0x00000000000007ff, 0x00000000, 0x7ff );
TEST_IMM_OP( 9, addiw, 0x000000007fffffff, 0x7fffffff, 0x000 );
TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff );
TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 );
TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 );
TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 );
TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 );
TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13, 9 );
TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 );
TEST_IMM_ZERODEST( 25, addiw, 33, 50 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,122 | riscv-testdata/testdata/rv64ui/sub.S | # See LICENSE for license details.
#*****************************************************************************
# sub.S
#-----------------------------------------------------------------------------
#
# Test sub instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
TEST_RR_ZEROSRC12( 36, sub, 0 );
TEST_RR_ZERODEST( 37, sub, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,302 | riscv-testdata/testdata/rv64ui/lbu.S | # See LICENSE for license details.
#*****************************************************************************
# lbu.S
#-----------------------------------------------------------------------------
#
# Test lbu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat );
TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat );
TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat );
TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat );
# Test with negative offset
TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 );
TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 );
TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 );
TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lbu x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x0000000000000000, \
la x1, tdat; \
addi x1, x1, -6; \
lbu x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lbu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lbu x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xff
tdat2: .byte 0x00
tdat3: .byte 0xf0
tdat4: .byte 0x0f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,114 | riscv-testdata/testdata/rv64ui/sraiw.S | # See LICENSE for license details.
#*****************************************************************************
# sraiw.S
#-----------------------------------------------------------------------------
#
# Test sraiw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, sraiw, 0xffffffff80000000, 0xffffffff80000000, 0 );
TEST_IMM_OP( 3, sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1 );
TEST_IMM_OP( 4, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_OP( 5, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_OP( 6, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_OP( 7, sraiw, 0x000000007fffffff, 0x000000007fffffff, 0 );
TEST_IMM_OP( 8, sraiw, 0x000000003fffffff, 0x000000007fffffff, 1 );
TEST_IMM_OP( 9, sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7 );
TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 );
TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 );
TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0 );
TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7 );
TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
# Verify that shifts ignore top 32 (using true 64-bit values)
TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 );
TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 );
TEST_IMM_ZERODEST( 25, sraiw, 31, 28 );
TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28)
TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 3,160 | riscv-testdata/testdata/rv64ui/subw.S | # See LICENSE for license details.
#*****************************************************************************
# subw.S
#-----------------------------------------------------------------------------
#
# Test subw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
TEST_RR_OP( 3, subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
TEST_RR_OP( 4, subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
TEST_RR_OP( 5, subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
TEST_RR_OP( 7, subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 );
TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 );
TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 );
TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 );
TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 );
TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 );
TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 );
TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 );
TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 );
TEST_RR_ZEROSRC1( 34, subw, 15, -15 );
TEST_RR_ZEROSRC2( 35, subw, 32, 32 );
TEST_RR_ZEROSRC12( 36, subw, 0 );
TEST_RR_ZERODEST( 37, subw, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,610 | riscv-testdata/testdata/rv64ui/sb.S | # See LICENSE for license details.
#*****************************************************************************
# sb.S
#-----------------------------------------------------------------------------
#
# Test sb instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat );
TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat );
TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat );
TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat );
# Test with negative offset
TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 );
TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 );
TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 );
TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x5, 0x78, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sb x2, 32(x4); \
lb x5, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0xffffffffffffff98, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -6; \
sb x2, 7(x1); \
la x4, tdat10; \
lb x5, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
li a0, 0xef
la a1, tdat
sb a0, 3(a1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xef
tdat2: .byte 0xef
tdat3: .byte 0xef
tdat4: .byte 0xef
tdat5: .byte 0xef
tdat6: .byte 0xef
tdat7: .byte 0xef
tdat8: .byte 0xef
tdat9: .byte 0xef
tdat10: .byte 0xef
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,949 | riscv-testdata/testdata/rv64ui/slt.S | # See LICENSE for license details.
#*****************************************************************************
# slt.S
#-----------------------------------------------------------------------------
#
# Test slt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 );
TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 );
TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 );
TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 );
TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 );
TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 );
TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
TEST_RR_ZEROSRC12( 37, slt, 0 );
TEST_RR_ZERODEST( 38, slt, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,028 | riscv-testdata/testdata/rv64ui/beq.S | # See LICENSE for license details.
#*****************************************************************************
# beq.S
#-----------------------------------------------------------------------------
#
# Test beq instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
beq x0, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 15,420 | riscv-testdata/testdata/rv64ui/ma_data.S | # See LICENSE for license details.
#*****************************************************************************
# ma_data.S
#-----------------------------------------------------------------------------
#
# Test misaligned ld/st data.
# Based on rv64mi-ma_addr.S
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
la s0, data
#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
/* Check that a misaligned load reads the correct value. */
#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
li TESTNUM, testnum; \
li t1, res; \
insn t2, offset(base); \
bne t1, t2, fail; \
1:
# within quadword
MISALIGNED_LOAD_TEST(1, lh, s0, 1, SEXT(0x0201, 16))
MISALIGNED_LOAD_TEST(2, lhu, s0, 1, 0x0201)
MISALIGNED_LOAD_TEST(3, lw, s0, 1, SEXT(0x04030201, 32))
MISALIGNED_LOAD_TEST(4, lw, s0, 2, SEXT(0x05040302, 32))
MISALIGNED_LOAD_TEST(5, lw, s0, 3, SEXT(0x06050403, 32))
#if __riscv_xlen == 64
MISALIGNED_LOAD_TEST(6, lwu, s0, 1, 0x04030201)
MISALIGNED_LOAD_TEST(7, lwu, s0, 2, 0x05040302)
MISALIGNED_LOAD_TEST(8, lwu, s0, 3, 0x06050403)
MISALIGNED_LOAD_TEST(9, ld, s0, 1, 0x0807060504030201)
MISALIGNED_LOAD_TEST(10, ld, s0, 2, 0x0908070605040302)
MISALIGNED_LOAD_TEST(11, ld, s0, 3, 0x0a09080706050403)
MISALIGNED_LOAD_TEST(12, ld, s0, 4, 0x0b0a090807060504)
MISALIGNED_LOAD_TEST(13, ld, s0, 5, 0x0c0b0a0908070605)
MISALIGNED_LOAD_TEST(14, ld, s0, 6, 0x0d0c0b0a09080706)
MISALIGNED_LOAD_TEST(15, ld, s0, 7, 0x0e0d0c0b0a090807)
#endif
# octword crossing
MISALIGNED_LOAD_TEST(16, lh, s0, 31, SEXT(0x201f, 16))
MISALIGNED_LOAD_TEST(17, lhu, s0, 31, 0x201f)
MISALIGNED_LOAD_TEST(18, lw, s0, 29, SEXT(0x201f1e1d, 32))
MISALIGNED_LOAD_TEST(19, lw, s0, 30, SEXT(0x21201f1e, 32))
MISALIGNED_LOAD_TEST(20, lw, s0, 31, SEXT(0x2221201f, 32))
#if __riscv_xlen == 64
MISALIGNED_LOAD_TEST(21, lwu, s0, 29, 0x201f1e1d)
MISALIGNED_LOAD_TEST(22, lwu, s0, 30, 0x21201f1e)
MISALIGNED_LOAD_TEST(23, lwu, s0, 31, 0x2221201f)
MISALIGNED_LOAD_TEST(24, ld, s0, 25, 0x201f1e1d1c1b1a19)
MISALIGNED_LOAD_TEST(25, ld, s0, 26, 0x21201f1e1d1c1b1a)
MISALIGNED_LOAD_TEST(26, ld, s0, 27, 0x2221201f1e1d1c1b)
MISALIGNED_LOAD_TEST(27, ld, s0, 28, 0x232221201f1e1d1c)
MISALIGNED_LOAD_TEST(28, ld, s0, 29, 0x24232221201f1e1d)
MISALIGNED_LOAD_TEST(29, ld, s0, 30, 0x2524232221201f1e)
MISALIGNED_LOAD_TEST(30, ld, s0, 31, 0x262524232221201f)
#endif
# cacheline crossing
MISALIGNED_LOAD_TEST(31, lh, s0, 63, SEXT(0x403f, 16))
MISALIGNED_LOAD_TEST(32, lhu, s0, 63, 0x403f)
MISALIGNED_LOAD_TEST(33, lw, s0, 61, SEXT(0x403f3e3d, 32))
MISALIGNED_LOAD_TEST(34, lw, s0, 62, SEXT(0x41403f3e, 32))
MISALIGNED_LOAD_TEST(35, lw, s0, 63, SEXT(0x4241403f, 32))
#if __riscv_xlen == 64
MISALIGNED_LOAD_TEST(36, lwu, s0, 61, 0x403f3e3d)
MISALIGNED_LOAD_TEST(37, lwu, s0, 62, 0x41403f3e)
MISALIGNED_LOAD_TEST(38, lwu, s0, 63, 0x4241403f)
MISALIGNED_LOAD_TEST(39, ld, s0, 57, 0x403f3e3d3c3b3a39)
MISALIGNED_LOAD_TEST(40, ld, s0, 58, 0x41403f3e3d3c3b3a)
MISALIGNED_LOAD_TEST(41, ld, s0, 59, 0x4241403f3e3d3c3b)
MISALIGNED_LOAD_TEST(42, ld, s0, 60, 0x434241403f3e3d3c)
MISALIGNED_LOAD_TEST(43, ld, s0, 61, 0x44434241403f3e3d)
MISALIGNED_LOAD_TEST(44, ld, s0, 62, 0x4544434241403f3e)
MISALIGNED_LOAD_TEST(45, ld, s0, 63, 0x464544434241403f)
#endif
/* Check that a misaligned store writes the correct value. */
#define MISALIGNED_STORE_TEST(testnum, st_insn, ld_insn, base, offset, st_data) \
li TESTNUM, testnum; \
li t1, st_data; \
st_insn t1, offset(base); \
ld_insn t2, offset(base); \
bne t1, t2, fail; \
1:
# within quadword
MISALIGNED_STORE_TEST(46, sh, lh, s0, 1, SEXT(0x8180, 16))
MISALIGNED_STORE_TEST(47, sh, lhu, s0, 1, 0x8382)
MISALIGNED_STORE_TEST(48, sw, lw, s0, 1, SEXT(0x87868584, 32))
MISALIGNED_STORE_TEST(49, sw, lw, s0, 2, SEXT(0x8b8a8988, 32))
MISALIGNED_STORE_TEST(50, sw, lw, s0, 3, SEXT(0x8f8e8d8c, 32))
#if __riscv_xlen == 64
MISALIGNED_STORE_TEST(51, sw, lwu, s0, 1, 0x93929190)
MISALIGNED_STORE_TEST(52, sw, lwu, s0, 2, 0x97969594)
MISALIGNED_STORE_TEST(53, sw, lwu, s0, 3, 0x9b9a9998)
MISALIGNED_STORE_TEST(54, sd, ld, s0, 1, 0xa3a2a1a09f9e9d9c)
MISALIGNED_STORE_TEST(55, sd, ld, s0, 2, 0xabaaa9a8a7a6a5a4)
MISALIGNED_STORE_TEST(56, sd, ld, s0, 3, 0xb3b2b1b0afaeadac)
MISALIGNED_STORE_TEST(57, sd, ld, s0, 4, 0xbbbab9b8b7b6b5b4)
MISALIGNED_STORE_TEST(58, sd, ld, s0, 5, 0xc3c2c1c0bfbebdbc)
MISALIGNED_STORE_TEST(59, sd, ld, s0, 6, 0xcbcac9c8c7c6c5c4)
MISALIGNED_STORE_TEST(60, sd, ld, s0, 7, 0xd3d2d1d0cfcecdcc)
#endif
# octword crossing
MISALIGNED_STORE_TEST(61, sh, lh, s0, 31, SEXT(0xd5d4, 16))
MISALIGNED_STORE_TEST(62, sh, lhu, s0, 31, 0xd7d6)
MISALIGNED_STORE_TEST(63, sw, lw, s0, 29, SEXT(0xdbdad9d8, 32))
MISALIGNED_STORE_TEST(64, sw, lw, s0, 30, SEXT(0xdfdedddc, 32))
MISALIGNED_STORE_TEST(65, sw, lw, s0, 31, SEXT(0xe3e2e1e0, 32))
#if __riscv_xlen == 64
MISALIGNED_STORE_TEST(66, sw, lwu, s0, 29, 0xe7e6e5e4)
MISALIGNED_STORE_TEST(67, sw, lwu, s0, 30, 0xebeae9e8)
MISALIGNED_STORE_TEST(68, sw, lwu, s0, 31, 0xefeeedec)
MISALIGNED_STORE_TEST(69, sd, ld, s0, 25, 0xf7f6f5f4f3f2f1f0)
MISALIGNED_STORE_TEST(70, sd, ld, s0, 26, 0xfffefdfcfbfaf9f8)
MISALIGNED_STORE_TEST(71, sd, ld, s0, 27, 0x0706050403020100)
MISALIGNED_STORE_TEST(72, sd, ld, s0, 28, 0x0f0e0d0c0b0a0908)
MISALIGNED_STORE_TEST(73, sd, ld, s0, 29, 0x1716151413121110)
MISALIGNED_STORE_TEST(74, sd, ld, s0, 30, 0x1f1e1d1c1b1a1918)
MISALIGNED_STORE_TEST(75, sd, ld, s0, 31, 0x2726252423222120)
#endif
# cacheline crossing
MISALIGNED_STORE_TEST(76, sh, lh, s0, 63, SEXT(0x3534, 16))
MISALIGNED_STORE_TEST(77, sh, lhu, s0, 63, 0x3736)
MISALIGNED_STORE_TEST(78, sw, lw, s0, 61, SEXT(0x3b3a3938, 32))
MISALIGNED_STORE_TEST(79, sw, lw, s0, 62, SEXT(0x3f3e3d3c, 32))
MISALIGNED_STORE_TEST(80, sw, lw, s0, 63, SEXT(0x43424140, 32))
#if __riscv_xlen == 64
MISALIGNED_STORE_TEST(81, sw, lwu, s0, 61, 0x47464544)
MISALIGNED_STORE_TEST(82, sw, lwu, s0, 62, 0x4b4a4948)
MISALIGNED_STORE_TEST(83, sw, lwu, s0, 63, 0x4f4e4d4c)
MISALIGNED_STORE_TEST(84, sd, ld, s0, 57, 0x5756555453525150)
MISALIGNED_STORE_TEST(85, sd, ld, s0, 58, 0x5f5e5d5c5b5a5958)
MISALIGNED_STORE_TEST(86, sd, ld, s0, 59, 0x6766656463626160)
MISALIGNED_STORE_TEST(87, sd, ld, s0, 60, 0x6f6e6d6c6b6a6968)
MISALIGNED_STORE_TEST(88, sd, ld, s0, 61, 0x7776757473727170)
MISALIGNED_STORE_TEST(89, sd, ld, s0, 62, 0x7f7e7d7c7b7a7978)
MISALIGNED_STORE_TEST(90, sd, ld, s0, 63, 0x8786858483828180)
#endif
/* Check that a misaligned store writes the correct value, checked by a narrower load. */
#define MISMATCHED_STORE_TEST(testnum, st_insn, ld_insn, base, st_offset, ld_offset, st_data, ld_data) \
li TESTNUM, testnum; \
li t1, st_data; \
li t2, ld_data; \
st_insn t1, st_offset(base); \
ld_insn t3, ld_offset(base); \
bne t2, t3, fail; \
1:
# within quadword
MISMATCHED_STORE_TEST(91, sh, lb, s0, 1, 1, 0x9998, SEXT(0x98, 8))
MISMATCHED_STORE_TEST(92, sh, lb, s0, 1, 2, 0x9b9a, SEXT(0x9b, 8))
MISMATCHED_STORE_TEST(93, sh, lbu, s0, 1, 1, 0x9d9c, 0x9c)
MISMATCHED_STORE_TEST(94, sh, lbu, s0, 1, 2, 0x9f9e, 0x9f)
MISMATCHED_STORE_TEST(95, sw, lb, s0, 1, 1, 0xa3a2a1a0, SEXT(0xa0, 8))
MISMATCHED_STORE_TEST(96, sw, lbu, s0, 2, 3, 0xa7a6a5a4, 0xa5)
MISMATCHED_STORE_TEST(97, sw, lh, s0, 3, 4, 0xabaaa9a8, SEXT(0xaaa9, 16))
MISMATCHED_STORE_TEST(98, sw, lhu, s0, 3, 5, 0xafaeadac, 0xafae)
#if __riscv_xlen == 64
MISMATCHED_STORE_TEST(99, sd, lb, s0, 1, 7, 0xb7b6b5b4b3b2b1b0, SEXT(0xb6, 8))
MISMATCHED_STORE_TEST(100, sd, lbu, s0, 2, 3, 0xbfbebdbcbbbab9b8, 0xb9)
MISMATCHED_STORE_TEST(101, sd, lh, s0, 3, 9, 0xc7c6c5c4c3c2c1c0, SEXT(0xc7c6, 16))
MISMATCHED_STORE_TEST(102, sd, lhu, s0, 4, 5, 0xcfcecdcccbcac9c8, 0xcac9)
MISMATCHED_STORE_TEST(103, sd, lw, s0, 5, 9, 0xd7d6d5d4d3d2d1d0, SEXT(0xd7d6d5d4, 32))
MISMATCHED_STORE_TEST(104, sd, lw, s0, 6, 8, 0xdfdedddcdbdad9d8, SEXT(0xdddcdbda, 32))
MISMATCHED_STORE_TEST(105, sd, lwu, s0, 7, 8, 0xe7e6e5e4e3e2e1e0, 0xe4e3e2e1)
#endif
# octword crossing
MISMATCHED_STORE_TEST(106, sh, lb, s0, 31, 31, 0xe9e8, SEXT(0xe8, 8))
MISMATCHED_STORE_TEST(107, sh, lb, s0, 31, 32, 0xebea, SEXT(0xeb, 8))
MISMATCHED_STORE_TEST(108, sh, lbu, s0, 31, 31, 0xedec, 0xec)
MISMATCHED_STORE_TEST(109, sh, lbu, s0, 31, 32, 0xefee, 0xef)
MISMATCHED_STORE_TEST(110, sw, lb, s0, 29, 29, 0xf3f2f1f0, SEXT(0xf0, 8))
MISMATCHED_STORE_TEST(111, sw, lbu, s0, 30, 32, 0xf7f6f5f4, 0xf6)
MISMATCHED_STORE_TEST(112, sw, lh, s0, 29, 31, 0xfbfaf9f8, SEXT(0xfbfa, 16))
MISMATCHED_STORE_TEST(113, sw, lhu, s0, 31, 31, 0xfffefdfc, 0xfdfc)
#if __riscv_xlen == 64
MISMATCHED_STORE_TEST(114, sd, lb, s0, 25, 32, 0x0706050403020100, SEXT(0x07, 8))
MISMATCHED_STORE_TEST(115, sd, lbu, s0, 26, 33, 0x0f0e0d0c0b0a0908, 0x0f)
MISMATCHED_STORE_TEST(116, sd, lh, s0, 27, 31, 0x1716151413121110, SEXT(0x1514, 16))
MISMATCHED_STORE_TEST(117, sd, lhu, s0, 28, 31, 0x1f1e1d1c1b1a1918, 0x1c1b)
MISMATCHED_STORE_TEST(118, sd, lw, s0, 29, 29, 0x2726252423222120, SEXT(0x23222120, 32))
MISMATCHED_STORE_TEST(119, sd, lw, s0, 30, 30, 0x2f2e2d2c2b2a2928, SEXT(0x2b2a2928, 32))
MISMATCHED_STORE_TEST(120, sd, lwu, s0, 31, 31, 0x3736353433323130, 0x33323130)
#endif
# cacheline crossing
MISMATCHED_STORE_TEST(121, sh, lb, s0, 63, 63, 0x4948, SEXT(0x48, 8))
MISMATCHED_STORE_TEST(122, sh, lb, s0, 63, 64, 0x4b4a, SEXT(0x4b, 8))
MISMATCHED_STORE_TEST(123, sh, lbu, s0, 63, 63, 0x4d4c, 0x4c)
MISMATCHED_STORE_TEST(124, sh, lbu, s0, 63, 64, 0x4f4e, 0x4f)
MISMATCHED_STORE_TEST(125, sw, lb, s0, 61, 61, 0x53525150, SEXT(0x50, 8))
MISMATCHED_STORE_TEST(126, sw, lbu, s0, 62, 64, 0x57565554, 0x56)
MISMATCHED_STORE_TEST(127, sw, lh, s0, 61, 63, 0x5b5a5958, SEXT(0x5b5a, 16))
MISMATCHED_STORE_TEST(128, sw, lhu, s0, 63, 63, 0x5f5e5d5c, 0x5d5c)
#if __riscv_xlen == 64
MISMATCHED_STORE_TEST(129, sd, lb, s0, 57, 64, 0x6766656463626160, SEXT(0x67, 8))
MISMATCHED_STORE_TEST(130, sd, lbu, s0, 58, 65, 0x6f6e6d6c6b6a6968, 0x6f)
MISMATCHED_STORE_TEST(131, sd, lh, s0, 59, 63, 0x7776757473727170, SEXT(0x7574, 16))
MISMATCHED_STORE_TEST(132, sd, lhu, s0, 60, 63, 0x7f7e7d7c7b7a7978, 0x7c7b)
MISMATCHED_STORE_TEST(133, sd, lw, s0, 61, 61, 0x8786858483828180, SEXT(0x83828180, 32))
MISMATCHED_STORE_TEST(134, sd, lw, s0, 62, 62, 0x8f8e8d8c8b8a8988, SEXT(0x8b8a8988, 32))
MISMATCHED_STORE_TEST(135, sd, lwu, s0, 63, 63, 0x9796959493929190, 0x93929190)
#endif
/* Memory contents at this point should be:
.word 0x10080000
.word 0x30282018
.word 0x34333231
.word 0x0f373635
.word 0x13121110
.word 0x17161514
.word 0x10080018
.word 0x30282018
.word 0x34333231
.word 0x27373635
.word 0x2b2a2928
.word 0x2f2e2d2c
.word 0x33323130
.word 0x37363534
.word 0x70686038
.word 0x90888078
.word 0x94939291
.word 0x47979695
.word 0x4b4a4948
.word 0x4f4e4d4c
.word 0x53525150
.word 0x57565554
.word 0x5b5a5958
.word 0x5f5e5d5c
.word 0x63626160
.word 0x67666564
.word 0x6b6a6968
.word 0x6f6e6d6c
.word 0x73727170
.word 0x77767574
.word 0x7b7a7978
.word 0x7f7e7d7c
*/
/* Check that a misaligned store writes the correct value, checked by a wider load. */
#if __riscv_xlen == 64
# within quadword
MISMATCHED_STORE_TEST(136, sb, lh, s0, 1, 1, 0x98, SEXT(0xb898, 16))
MISMATCHED_STORE_TEST(137, sb, lhu, s0, 2, 1, 0x99, 0x9998)
MISMATCHED_STORE_TEST(138, sh, lw, s0, 1, 1, 0x9b9a, SEXT(0xc8c09b9a, 32))
MISMATCHED_STORE_TEST(139, sh, lw, s0, 3, 2, 0x9d9c, SEXT(0xd09d9c9b, 32))
MISMATCHED_STORE_TEST(140, sh, lw, s0, 5, 3, 0x9f9e, SEXT(0x9f9e9d9c, 32))
MISMATCHED_STORE_TEST(141, sb, lwu, s0, 2, 1, 0xa0, 0x9d9ca09a)
MISMATCHED_STORE_TEST(142, sh, lwu, s0, 3, 2, 0xa2a1, 0x9ea2a1a0)
MISMATCHED_STORE_TEST(143, sh, lwu, s0, 5, 3, 0xa4a3, 0xa4a3a2a1)
MISMATCHED_STORE_TEST(144, sb, ld, s0, 2, 1, 0xa5, 0xe1e0a4a3a2a1a59a)
MISMATCHED_STORE_TEST(145, sh, ld, s0, 7, 2, 0xa7a6, 0xe2a7a6a4a3a2a1a5)
MISMATCHED_STORE_TEST(146, sh, ld, s0, 9, 3, 0xa9a8, 0xa9a8a7a6a4a3a2a1)
MISMATCHED_STORE_TEST(147, sw, ld, s0, 5, 4, 0xadacabaa, 0xe4a9a8adacabaaa2)
MISMATCHED_STORE_TEST(148, sw, ld, s0, 7, 5, 0xb1b0afae, 0xe5e4b1b0afaeabaa)
MISMATCHED_STORE_TEST(149, sw, ld, s0, 9, 6, 0xb5b4b3b2, 0xe6b5b4b3b2afaeab)
MISMATCHED_STORE_TEST(150, sw, ld, s0, 11, 7, 0xb9b8b7b6, 0xb9b8b7b6b3b2afae)
# octword crossing
MISMATCHED_STORE_TEST(151, sb, lh, s0, 31, 31, 0xba, SEXT(0x31ba, 16))
MISMATCHED_STORE_TEST(152, sb, lhu, s0, 32, 31, 0xbb, 0xbbba)
MISMATCHED_STORE_TEST(153, sh, lw, s0, 30, 30, 0xbdbc, SEXT(0x32bbbdbc, 32))
MISMATCHED_STORE_TEST(154, sh, lw, s0, 31, 30, 0xbfbe, SEXT(0x32bfbebc, 32))
MISMATCHED_STORE_TEST(155, sh, lw, s0, 32, 30, 0xc1c0, SEXT(0xc1c0bebc, 32))
MISMATCHED_STORE_TEST(156, sb, lwu, s0, 32, 31, 0xc2, 0x33c1c2be)
MISMATCHED_STORE_TEST(157, sh, lwu, s0, 31, 29, 0xc4c3, 0xc4c3bc20)
MISMATCHED_STORE_TEST(158, sh, lwu, s0, 32, 30, 0xc6c5, 0xc6c5c3bc)
MISMATCHED_STORE_TEST(159, sb, ld, s0, 32, 25, 0xc7, 0xc7c3bc2018100800)
MISMATCHED_STORE_TEST(160, sh, ld, s0, 31, 26, 0xc9c8, 0xc6c9c8bc20181008)
MISMATCHED_STORE_TEST(161, sh, ld, s0, 31, 27, 0xcbca, 0x33c6cbcabc201810)
MISMATCHED_STORE_TEST(162, sw, ld, s0, 32, 28, 0xcfcecdcc, 0xcfcecdcccabc2018)
MISMATCHED_STORE_TEST(163, sw, ld, s0, 31, 29, 0xd3d2d1d0, 0x35cfd3d2d1d0bc20)
MISMATCHED_STORE_TEST(164, sw, ld, s0, 30, 30, 0xd7d6d5d4, 0x3635cfd3d7d6d5d4)
MISMATCHED_STORE_TEST(165, sw, ld, s0, 29, 31, 0xdbdad9d8, 0x373635cfd3d7dbda)
# cacheline crossing
MISMATCHED_STORE_TEST(166, sb, lh, s0, 63, 63, 0xdc, SEXT(0x91dc, 16))
MISMATCHED_STORE_TEST(167, sb, lhu, s0, 64, 63, 0xdd, 0xdddc)
MISMATCHED_STORE_TEST(168, sh, lw, s0, 62, 62, 0xdfde, SEXT(0x92dddfde, 32))
MISMATCHED_STORE_TEST(169, sh, lw, s0, 63, 62, 0xe1e0, SEXT(0x92e1e0de, 32))
MISMATCHED_STORE_TEST(170, sh, lw, s0, 64, 62, 0xe3e2, SEXT(0xe3e2e0de, 32))
MISMATCHED_STORE_TEST(171, sb, lwu, s0, 64, 63, 0xe4, 0x93e3e4e0)
MISMATCHED_STORE_TEST(172, sh, lwu, s0, 63, 61, 0xe6e5, 0xe6e5de80)
MISMATCHED_STORE_TEST(173, sh, lwu, s0, 64, 62, 0xe8e7, 0xe8e7e5de)
MISMATCHED_STORE_TEST(174, sb, ld, s0, 64, 57, 0xe9, 0xe9e5de8078706860)
MISMATCHED_STORE_TEST(175, sh, ld, s0, 63, 58, 0xebea, 0xe8ebeade80787068)
MISMATCHED_STORE_TEST(176, sh, ld, s0, 63, 59, 0xedec, 0x93e8edecde807870)
MISMATCHED_STORE_TEST(177, sw, ld, s0, 64, 60, 0xf1f0efee, 0xf1f0efeeecde8078)
MISMATCHED_STORE_TEST(178, sw, ld, s0, 63, 61, 0xf5f4f3f2, 0x95f1f5f4f3f2de80)
MISMATCHED_STORE_TEST(179, sw, ld, s0, 62, 62, 0xf9f8f7f6, 0x9695f1f5f9f8f7f6)
MISMATCHED_STORE_TEST(180, sw, ld, s0, 61, 63, 0xfdfcfbfa, 0x979695f1f5f9fdfc)
#endif
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
data:
.align 3
.word 0x03020100
.word 0x07060504
.word 0x0b0a0908
.word 0x0f0e0d0c
.word 0x13121110
.word 0x17161514
.word 0x1b1a1918
.word 0x1f1e1d1c
.word 0x23222120
.word 0x27262524
.word 0x2b2a2928
.word 0x2f2e2d2c
.word 0x33323130
.word 0x37363534
.word 0x3b3a3938
.word 0x3f3e3d3c
.word 0x43424140
.word 0x47464544
.word 0x4b4a4948
.word 0x4f4e4d4c
.word 0x53525150
.word 0x57565554
.word 0x5b5a5958
.word 0x5f5e5d5c
.word 0x63626160
.word 0x67666564
.word 0x6b6a6968
.word 0x6f6e6d6c
.word 0x73727170
.word 0x77767574
.word 0x7b7a7978
.word 0x7f7e7d7c
.fill 0xff, 1, 80
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,345 | riscv-testdata/testdata/rv64ui/ld.S | # See LICENSE for license details.
#*****************************************************************************
# ld.S
#-----------------------------------------------------------------------------
#
# Test ld instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0, tdat );
TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8, tdat );
TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat );
TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat );
# Test with negative offset
TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 );
TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 );
TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8, tdat4 );
TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
ld x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
ld x5, 11(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
ld x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
ld x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .dword 0x00ff00ff00ff00ff
tdat2: .dword 0xff00ff00ff00ff00
tdat3: .dword 0x0ff00ff00ff00ff0
tdat4: .dword 0xf00ff00ff00ff00f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,087 | riscv-testdata/testdata/rv64ui/jal.S | # See LICENSE for license details.
#*****************************************************************************
# jal.S
#-----------------------------------------------------------------------------
#
# Test jal instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Test 2: Basic test
#-------------------------------------------------------------
test_2:
li TESTNUM, 2
li ra, 0
jal x4, target_2
linkaddr_2:
nop
nop
j fail
target_2:
la x2, linkaddr_2
bne x2, x4, fail
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 3, ra, 3, \
li ra, 1; \
jal x0, 1f; \
addi ra, ra, 1; \
addi ra, ra, 1; \
addi ra, ra, 1; \
addi ra, ra, 1; \
1: addi ra, ra, 1; \
addi ra, ra, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,680 | riscv-testdata/testdata/rv64ui/sw.S | # See LICENSE for license details.
#*****************************************************************************
# sw.S
#-----------------------------------------------------------------------------
#
# Test sw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat );
TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat );
TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat );
TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat );
# Test with negative offset
TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 );
TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 );
TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 );
TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x5, 0x12345678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sw x2, 32(x4); \
lw x5, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x58213098, \
la x1, tdat9; \
li x2, 0x58213098; \
addi x1, x1, -3; \
sw x2, 7(x1); \
la x4, tdat10; \
lw x5, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0xdeadbeef
tdat2: .word 0xdeadbeef
tdat3: .word 0xdeadbeef
tdat4: .word 0xdeadbeef
tdat5: .word 0xdeadbeef
tdat6: .word 0xdeadbeef
tdat7: .word 0xdeadbeef
tdat8: .word 0xdeadbeef
tdat9: .word 0xdeadbeef
tdat10: .word 0xdeadbeef
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,623 | riscv-testdata/testdata/rv64ui/or.S | # See LICENSE for license details.
#*****************************************************************************
# or.S
#-----------------------------------------------------------------------------
#
# Test or instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, or, 0 );
TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,642 | riscv-testdata/testdata/rv64ui/sh.S | # See LICENSE for license details.
#*****************************************************************************
# sh.S
#-----------------------------------------------------------------------------
#
# Test sh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
# Test with negative offset
TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 );
TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 );
TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 );
TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x5, 0x5678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sh x2, 32(x4); \
lh x5, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x3098, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -5; \
sh x2, 7(x1); \
la x4, tdat10; \
lh x5, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
li a0, 0xbeef
la a1, tdat
sh a0, 6(a1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0xbeef
tdat2: .half 0xbeef
tdat3: .half 0xbeef
tdat4: .half 0xbeef
tdat5: .half 0xbeef
tdat6: .half 0xbeef
tdat7: .half 0xbeef
tdat8: .half 0xbeef
tdat9: .half 0xbeef
tdat10: .half 0xbeef
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,326 | riscv-testdata/testdata/rv64ui/lwu.S | # See LICENSE for license details.
#*****************************************************************************
# lwu.S
#-----------------------------------------------------------------------------
#
# Test lwu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0, tdat );
TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4, tdat );
TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8, tdat );
TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat );
# Test with negative offset
TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 );
TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8, tdat4 );
TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4, tdat4 );
TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x0000000000ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
lwu x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x00000000ff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
lwu x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lwu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lwu x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0x00ff00ff
tdat2: .word 0xff00ff00
tdat3: .word 0x0ff00ff0
tdat4: .word 0xf00ff00f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,959 | riscv-testdata/testdata/rv64ui/slliw.S | # See LICENSE for license details.
#*****************************************************************************
# slliw.S
#-----------------------------------------------------------------------------
#
# Test slliw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slliw, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, slliw, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
# Verify that shifts ignore top 32 (using true 64-bit values)
TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 );
TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 );
TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 );
TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 );
TEST_IMM_ZERODEST( 25, slliw, 31, 28 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,308 | riscv-testdata/testdata/rv64ui/lw.S | # See LICENSE for license details.
#*****************************************************************************
# lw.S
#-----------------------------------------------------------------------------
#
# Test lw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat );
TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat );
TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat );
TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat );
# Test with negative offset
TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 );
TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 );
TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 );
TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x0000000000ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
lw x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0xffffffffff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
lw x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lw x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lw x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0x00ff00ff
tdat2: .word 0xff00ff00
tdat3: .word 0x0ff00ff0
tdat4: .word 0xf00ff00f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 2,310 | riscv-testdata/testdata/rv64ui/lhu.S | # See LICENSE for license details.
#*****************************************************************************
# lhu.S
#-----------------------------------------------------------------------------
#
# Test lhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat );
TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat );
TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat );
TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat );
# Test with negative offset
TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 );
TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 );
TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 );
TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lhu x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x000000000000ff00, \
la x1, tdat; \
addi x1, x1, -5; \
lhu x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lhu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lhu x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0x00ff
tdat2: .half 0xff00
tdat3: .half 0x0ff0
tdat4: .half 0xf00f
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 4,022 | riscv-testdata/testdata/rv64ui/sra.S | # See LICENSE for license details.
#*****************************************************************************
# sra.S
#-----------------------------------------------------------------------------
#
# Test sra instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 );
TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 );
TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 );
TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 );
TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 );
TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 );
TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 );
TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 );
TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 );
TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 );
TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 );
TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 );
TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce );
TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
TEST_RR_ZEROSRC12( 42, sra, 0 );
TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
matthiasgoergens/zkvm | 1,735 | riscv-testdata/testdata/rv64ui/jalr.S | # See LICENSE for license details.
#*****************************************************************************
# jalr.S
#-----------------------------------------------------------------------------
#
# Test jalr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Test 2: Basic test
#-------------------------------------------------------------
test_2:
li TESTNUM, 2
li t0, 0
la t1, target_2
jalr t0, t1, 0
linkaddr_2:
j fail
target_2:
la t1, linkaddr_2
bne t0, t1, fail
#-------------------------------------------------------------
# Test 3: Basic test2, rs = rd
#-------------------------------------------------------------
test_3:
li TESTNUM, 3
la t0, target_3
jalr t0, t0, 0
linkaddr_3:
j fail
target_3:
la t1, linkaddr_3
bne t0, t1, fail
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
.option push
.align 2
.option norvc
TEST_CASE( 7, t0, 4, \
li t0, 1; \
la t1, 1f; \
jr t1, -4; \
addi t0, t0, 1; \
addi t0, t0, 1; \
addi t0, t0, 1; \
addi t0, t0, 1; \
1: addi t0, t0, 1; \
addi t0, t0, 1; \
)
.option pop
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
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