repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
nopjne/DaisyDrive64 | 39,200 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h757xx.s | ;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h757xx.s
;* Author : MCD Application Team
;* Description : STM32H757xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD DSI_IRQHandler ; DSI global Interrupt
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK CM7_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM7_SEV_IRQHandler
B CM7_SEV_IRQHandler
PUBWEAK CM4_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM4_SEV_IRQHandler
B CM4_SEV_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK DSI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DSI_IRQHandler
B DSI_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK HSEM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM2_IRQHandler
B HSEM2_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK WWDG_RST_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_RST_IRQHandler
B WWDG_RST_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK HOLD_CORE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HOLD_CORE_IRQHandler
B HOLD_CORE_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 37,710 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h742xx.s | ;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h742xx.s
;* Author : MCD Application Team
;* Description : STM32H742xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD 0 ; Reserved
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
NordicPlayground/nRF51-ble-bcast-mesh | 22,572 | nRF51/bootloader/arm/arm_startup_nrf52.s | ;/* Copyright (c) 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
IF :DEF: __STARTUP_CONFIG
#include "startup_config.h"
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 8192
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
IF :DEF: __STARTUP_CONFIG
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 8192
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0 ; Reserved
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD NFCT_IRQHandler
DCD GPIOTE_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
DCD QDEC_IRQHandler
DCD COMP_LPCOMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
DCD SWI2_EGU2_IRQHandler
DCD SWI3_EGU3_IRQHandler
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler
DCD TIMER4_IRQHandler
DCD PWM0_IRQHandler
DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MWU_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
DCD SPIM2_SPIS2_SPI2_IRQHandler
DCD RTC2_IRQHandler
DCD I2S_IRQHandler
DCD FPU_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT NFCT_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_EGU2_IRQHandler [WEAK]
EXPORT SWI3_EGU3_IRQHandler [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PDM_IRQHandler [WEAK]
EXPORT MWU_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
NFCT_IRQHandler
GPIOTE_IRQHandler
SAADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
COMP_LPCOMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_EGU2_IRQHandler
SWI3_EGU3_IRQHandler
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
PWM0_IRQHandler
PDM_IRQHandler
MWU_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler
RTC2_IRQHandler
I2S_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
NordicPlayground/nRF51-ble-bcast-mesh | 8,726 | nRF51/bootloader/arm/arm_startup_nrf51.s | ; Copyright (c) 2013, Nordic Semiconductor ASA
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; * Neither the name of Nordic Semiconductor ASA nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; NOTE: Template files (including this one) are application specific and therefore
; expected to be copied into the application project folder prior to its use!
; Description message
Stack_Size EQU 2048
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 2048
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_IRQHandler ;LPCOMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
NordicPlayground/nRF51-ble-bcast-mesh | 22,572 | nRF51/examples/BLE_Gateway/arm/arm_startup_nrf52.s | ;/* Copyright (c) 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
IF :DEF: __STARTUP_CONFIG
#include "startup_config.h"
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 8192
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
IF :DEF: __STARTUP_CONFIG
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 8192
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0 ; Reserved
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD NFCT_IRQHandler
DCD GPIOTE_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
DCD QDEC_IRQHandler
DCD COMP_LPCOMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
DCD SWI2_EGU2_IRQHandler
DCD SWI3_EGU3_IRQHandler
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler
DCD TIMER4_IRQHandler
DCD PWM0_IRQHandler
DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MWU_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
DCD SPIM2_SPIS2_SPI2_IRQHandler
DCD RTC2_IRQHandler
DCD I2S_IRQHandler
DCD FPU_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT NFCT_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_EGU2_IRQHandler [WEAK]
EXPORT SWI3_EGU3_IRQHandler [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PDM_IRQHandler [WEAK]
EXPORT MWU_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
NFCT_IRQHandler
GPIOTE_IRQHandler
SAADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
COMP_LPCOMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_EGU2_IRQHandler
SWI3_EGU3_IRQHandler
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
PWM0_IRQHandler
PDM_IRQHandler
MWU_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler
RTC2_IRQHandler
I2S_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
NordicPlayground/nRF51-ble-bcast-mesh | 8,700 | nRF51/examples/BLE_Gateway/arm/arm_startup_nrf51.s | ; Copyright (c) 2013, Nordic Semiconductor ASA
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; * Neither the name of Nordic Semiconductor ASA nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; NOTE: Template files (including this one) are application specific and therefore
; expected to be copied into the application project folder prior to its use!
; Description message
Stack_Size EQU 2048
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_IRQHandler ;LPCOMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
NordicPlayground/nRF51-ble-bcast-mesh | 8,700 | nRF51/examples/ping_pong/arm/arm_startup_nrf51.s | ; Copyright (c) 2013, Nordic Semiconductor ASA
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; * Neither the name of Nordic Semiconductor ASA nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; NOTE: Template files (including this one) are application specific and therefore
; expected to be copied into the application project folder prior to its use!
; Description message
Stack_Size EQU 2048
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_IRQHandler ;LPCOMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
NordicPlayground/nRF51-ble-bcast-mesh | 7,643 | nRF51/examples/ping_pong/gcc/gcc_startup_nrf51.s | /*
Copyright (c) 2015, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
NOTE: Template files (including this one) are application specific and therefore
expected to be copied into the application project folder prior to its use!
*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 2048
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 1024
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .Vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long POWER_CLOCK_IRQHandler
.long RADIO_IRQHandler
.long UART0_IRQHandler
.long SPI0_TWI0_IRQHandler
.long SPI1_TWI1_IRQHandler
.long 0 /*Reserved */
.long GPIOTE_IRQHandler
.long ADC_IRQHandler
.long TIMER0_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
.long RTC0_IRQHandler
.long TEMP_IRQHandler
.long RNG_IRQHandler
.long ECB_IRQHandler
.long CCM_AAR_IRQHandler
.long WDT_IRQHandler
.long RTC1_IRQHandler
.long QDEC_IRQHandler
.long LPCOMP_IRQHandler
.long SWI0_IRQHandler
.long SWI1_IRQHandler
.long SWI2_IRQHandler
.long SWI3_IRQHandler
.long SWI4_IRQHandler
.long SWI5_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.size __Vectors, . - __Vectors
/* Reset Handler */
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
.equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.fnstart
/* Make sure ALL RAM banks are powered on */
MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
ORRS R2, R1
STR R2, [R0]
LDR R0, =NRF_POWER_RAMONB_ADDRESS
LDR R2, [R0]
ORRS R2, R1
STR R2, [R0]
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
LDR R0, =SystemInit
BLX R0
LDR R0, =_start
BX R0
.pool
.cantunwind
.fnend
.size Reset_Handler,.-Reset_Handler
.section ".text"
/* Dummy Exception Handlers (infinite loops which can be modified) */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ POWER_CLOCK_IRQHandler
IRQ RADIO_IRQHandler
IRQ UART0_IRQHandler
IRQ SPI0_TWI0_IRQHandler
IRQ SPI1_TWI1_IRQHandler
IRQ GPIOTE_IRQHandler
IRQ ADC_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ RTC0_IRQHandler
IRQ TEMP_IRQHandler
IRQ RNG_IRQHandler
IRQ ECB_IRQHandler
IRQ CCM_AAR_IRQHandler
IRQ WDT_IRQHandler
IRQ RTC1_IRQHandler
IRQ QDEC_IRQHandler
IRQ LPCOMP_IRQHandler
IRQ SWI0_IRQHandler
IRQ SWI1_IRQHandler
IRQ SWI2_IRQHandler
IRQ SWI3_IRQHandler
IRQ SWI4_IRQHandler
IRQ SWI5_IRQHandler
.end
|
NordicPlayground/nRF51-ble-bcast-mesh | 8,726 | nRF51/examples/Template project/arm/arm_startup_nrf51.s | ; Copyright (c) 2013, Nordic Semiconductor ASA
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; * Neither the name of Nordic Semiconductor ASA nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; NOTE: Template files (including this one) are application specific and therefore
; expected to be copied into the application project folder prior to its use!
; Description message
Stack_Size EQU 2048
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 2048
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_IRQHandler ;LPCOMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
NordicPlayground/nRF51-ble-bcast-mesh | 8,700 | nRF51/examples/Bandwidth_test/arm/arm_startup_nrf51.s | ; Copyright (c) 2013, Nordic Semiconductor ASA
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; * Neither the name of Nordic Semiconductor ASA nor the names of its
; contributors may be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; NOTE: Template files (including this one) are application specific and therefore
; expected to be copied into the application project folder prior to its use!
; Description message
Stack_Size EQU 2048
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
Heap_Size EQU 0
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
DCD RADIO_IRQHandler ;RADIO
DCD UART0_IRQHandler ;UART0
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
DCD 0 ;Reserved
DCD GPIOTE_IRQHandler ;GPIOTE
DCD ADC_IRQHandler ;ADC
DCD TIMER0_IRQHandler ;TIMER0
DCD TIMER1_IRQHandler ;TIMER1
DCD TIMER2_IRQHandler ;TIMER2
DCD RTC0_IRQHandler ;RTC0
DCD TEMP_IRQHandler ;TEMP
DCD RNG_IRQHandler ;RNG
DCD ECB_IRQHandler ;ECB
DCD CCM_AAR_IRQHandler ;CCM_AAR
DCD WDT_IRQHandler ;WDT
DCD RTC1_IRQHandler ;RTC1
DCD QDEC_IRQHandler ;QDEC
DCD LPCOMP_IRQHandler ;LPCOMP
DCD SWI0_IRQHandler ;SWI0
DCD SWI1_IRQHandler ;SWI1
DCD SWI2_IRQHandler ;SWI2
DCD SWI3_IRQHandler ;SWI3
DCD SWI4_IRQHandler ;SWI4
DCD SWI5_IRQHandler ;SWI5
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
ORRS R2, R2, R1
STR R2, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_IRQHandler [WEAK]
EXPORT SWI1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
EXPORT SWI3_IRQHandler [WEAK]
EXPORT SWI4_IRQHandler [WEAK]
EXPORT SWI5_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UART0_IRQHandler
SPI0_TWI0_IRQHandler
SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
ADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
LPCOMP_IRQHandler
SWI0_IRQHandler
SWI1_IRQHandler
SWI2_IRQHandler
SWI3_IRQHandler
SWI4_IRQHandler
SWI5_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
NordicPlayground/nrf52-quadcopter | 22,352 | Firmware/pca10040/s132/arm5_no_packs/RTE/Device/nRF52832_xxAA/arm_startup_nrf52.s | ;/* Copyright (c) 2012 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
IF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 8192
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
IF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 8192
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0 ; Reserved
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD NFCT_IRQHandler
DCD GPIOTE_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
DCD QDEC_IRQHandler
DCD COMP_LPCOMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
DCD SWI2_EGU2_IRQHandler
DCD SWI3_EGU3_IRQHandler
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler
DCD TIMER4_IRQHandler
DCD PWM0_IRQHandler
DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MWU_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
DCD SPIM2_SPIS2_SPI2_IRQHandler
DCD RTC2_IRQHandler
DCD I2S_IRQHandler
DCD FPU_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT NFCT_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_EGU2_IRQHandler [WEAK]
EXPORT SWI3_EGU3_IRQHandler [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PDM_IRQHandler [WEAK]
EXPORT MWU_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
NFCT_IRQHandler
GPIOTE_IRQHandler
SAADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
COMP_LPCOMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_EGU2_IRQHandler
SWI3_EGU3_IRQHandler
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
PWM0_IRQHandler
PDM_IRQHandler
MWU_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler
RTC2_IRQHandler
I2S_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
normaldotcom/canable2-fw | 12,697 | src/startup_stm32g431xx.s | /**
******************************************************************************
* @file startup_stm32g431xx.s
* @author MCD Application Team
* @brief STM32G431xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word 0
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word 0
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word 0
.word 0
.word DMA2_Channel6_IRQHandler
.word 0
.word 0
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 5,360 | Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S | ;/* ----------------------------------------------------------------------
; * Project: CMSIS DSP Library
; * Title: arm_bitreversal2.S
; * Description: arm_bitreversal_32 function done in assembly for maximum speed.
; * Called after doing an fft to reorder the output.
; * The function is loop unrolled by 2. arm_bitreversal_16 as well.
; *
; * $Date: 27. January 2017
; * $Revision: V.1.5.1
; *
; * Target Processor: Cortex-M cores
; * -------------------------------------------------------------------- */
;/*
; * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
#if defined ( __CC_ARM ) /* Keil */
#define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
#define LABEL
#elif defined ( __IASMARM__ ) /* IAR */
#define CODESECT SECTION `.text`:CODE
#define PROC
#define LABEL
#define ENDP
#define EXPORT PUBLIC
#elif defined ( __CSMC__ ) /* Cosmic */
#define CODESECT switch .text
#define THUMB
#define EXPORT xdef
#define PROC :
#define LABEL :
#define ENDP
#define arm_bitreversal_32 _arm_bitreversal_32
#elif defined ( __TI_ARM__ ) /* TI ARM */
#define THUMB .thumb
#define CODESECT .text
#define EXPORT .global
#define PROC : .asmfunc
#define LABEL :
#define ENDP .endasmfunc
#define END
#elif defined ( __GNUC__ ) /* GCC */
#define THUMB .thumb
#define CODESECT .section .text
#define EXPORT .global
#define PROC :
#define LABEL :
#define ENDP
#define END
.syntax unified
#endif
CODESECT
THUMB
;/*
;* @brief In-place bit reversal function.
;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
;* @param[in] bitRevLen bit reversal table length
;* @param[in] *pBitRevTab points to bit reversal table.
;* @return none.
;*/
EXPORT arm_bitreversal_32
EXPORT arm_bitreversal_16
#if defined ( __CC_ARM ) /* Keil */
#elif defined ( __IASMARM__ ) /* IAR */
#elif defined ( __CSMC__ ) /* Cosmic */
#elif defined ( __TI_ARM__ ) /* TI ARM */
#elif defined ( __GNUC__ ) /* GCC */
.type arm_bitreversal_16, %function
.type arm_bitreversal_32, %function
#endif
#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS) || defined(ARM_MATH_ARMV8MBL)
arm_bitreversal_32 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_32_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
LDR r5,[r2,#4]
LDR r4,[r6,#4]
STR r5,[r6,#4]
STR r4,[r2,#4]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r6}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_16_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
LSRS r2,r2,#1
LSRS r6,r6,#1
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r6}
BX lr
ENDP
#else
arm_bitreversal_32 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8
ADD r9,r0,r9
ADD r2,r0,r2
ADD r12,r0,r12
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
LDR r7,[r9,#4]
LDR r6,[r8,#4]
LDR r5,[r2,#4]
LDR r4,[r12,#4]
STR r6,[r9,#4]
STR r7,[r8,#4]
STR r5,[r12,#4]
STR r4,[r2,#4]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r9}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8,LSR #1
ADD r9,r0,r9,LSR #1
ADD r2,r0,r2,LSR #1
ADD r12,r0,r12,LSR #1
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r9}
BX lr
ENDP
#endif
END
|
normaldotcom/canable2-fw | 1,912 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S |
#if defined (__CC_ARM)
#if (defined (ARM_MATH_CM0))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_CM0P))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_CM3))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_CM4))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_CM7))
#include "ARMCC\startup_armv7-m.s"
#elif (defined (ARM_MATH_ARMV8MBL))
#include "ARMCC\startup_armv6-m.s"
#elif (defined (ARM_MATH_ARMV8MML))
#include "ARMCC\startup_armv7-m.s"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if (defined (ARM_MATH_CM0))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM0P))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM3))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM4))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM7))
#include "ARMCLANG\startup_armv7-m.S"
#elif (defined (ARM_MATH_ARMV8MBL))
#include "ARMCLANG\startup_armv6-m.S"
#elif (defined (ARM_MATH_ARMV8MML))
#include "ARMCLANG\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#elif defined (__GNUC__)
#if (defined (ARM_MATH_CM0))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM0P))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_CM3))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM4))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_CM7))
#include "GCC\startup_armv7-m.S"
#elif (defined (ARM_MATH_ARMV8MBL))
#include "GCC\startup_armv6-m.S"
#elif (defined (ARM_MATH_ARMV8MML))
#include "GCC\startup_armv7-m.S"
#else
#error "No appropriate startup file found!"
#endif
#else
#error "Compiler not supported!"
#endif
|
normaldotcom/canable2-fw | 6,394 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s | ;/* File: startup_armv6-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END
|
normaldotcom/canable2-fw | 7,083 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s | ;/* File: startup_armv7-m.s
; * Purpose: startup file for armv7-m architecture devices.
; * Should be used with ARMCC
; * Version: V2.00
; * Date: 16 November 2015
; *
; */
;/* Copyright (c) 2011 - 2014 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
; //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
BKPT #0
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
BKPT #0
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
BKPT #0
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
BKPT #0
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
BKPT #0
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
;/*
; __user_setup_stackheap() returns the:
; - heap base in r0 (if the program uses the heap)
; - stack base in sp
; - heap limit in r2 (if the program uses the heap and uses two-region memory).
; */
EXPORT __user_setup_stackheap
__user_setup_stackheap PROC
LDR R0, = __initial_sp
MOV SP, R0
IF Heap_Size > 0
LDR R2, = __heap_limit
LDR R0, = __heap_base
ELSE
MOV R0, #0
MOV R2, #0
ENDIF
BX LR
ENDP
;/*
;__user_initial_stackheap() returns the:
; - heap base in r0
; - stack base in r1, that is, the highest address in the stack region
; - heap limit in r2
; - stack limit in r3, that is, the lowest address in the stack region.
; */
;
;/* DEPRICATED
; EXPORT __user_initial_stackheap
;
;__user_initial_stackheap PROC
; LDR R0, = Heap_Mem
; LDR R1, =(Stack_Mem + Stack_Size)
; LDR R2, = (Heap_Mem + Heap_Size)
; LDR R3, = Stack_Mem
; BX LR
; ENDP
; */
ALIGN
ENDIF
END
|
normaldotcom/canable2-fw | 7,347 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S | /* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with GCC for ARM Embedded Processors
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
bkpt #0
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
.end
|
normaldotcom/canable2-fw | 7,290 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S | /* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with GCC for ARM Embedded Processors
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
bkpt #0
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
.end
|
normaldotcom/canable2-fw | 6,458 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S | /* File: startup_armv7-m.S
* Purpose: startup file for armv7-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl MemManage_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
.thumb_func
MemManage_Handler:
bkpt #0
b .
.globl BusFault_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
.thumb_func
BusFault_Handler:
bkpt #0
b .
.globl UsageFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
.thumb_func
UsageFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl DebugMon_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
.thumb_func
DebugMon_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end
|
normaldotcom/canable2-fw | 5,756 | Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S | /* File: startup_armv6-m.S
* Purpose: startup file for armv6-m architecture devices.
* Should be used with ARMCLANG
* Version: V2.00
* Date: 16 November 2015
*
*/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
.syntax unified
.arch armv6-m
/* .eabi_attribute Tag_ABI_align8_preserved,1 www.support.code-red-tech.com/CodeRedWiki/Preserve8 */
.eabi_attribute 25, 1 /* Tag_ABI_align_preserved */
/*
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Stack_Size, 0x00000400
.section STACK, "w"
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
__StackTop: /* formerly known as __initial_sp */
/*
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
*/
.equ Heap_Size, 0x00000C00
.section HEAP, "w"
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
__HeapLimit:
.section RESET, "x"
.align 2
.globl __Vectors
.globl __Vectors_End
.globl __Vectors_Size
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
__Vectors_End:
.equ __Vectors_Size, __Vectors_End - __Vectors
.text
.thumb
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
.thumb_func
Reset_Handler:
bl SystemInit
bl __main
.globl NMI_Handler
.weak NMI_Handler
.type NMI_Handler, %function
.thumb_func
NMI_Handler:
bkpt #0
b .
.globl HardFault_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
.thumb_func
HardFault_Handler:
bkpt #0
b .
.globl SVC_Handler
.weak SVC_Handler
.type SVC_Handler, %function
.thumb_func
SVC_Handler:
bkpt #0
b .
.globl PendSV_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
.thumb_func
PendSV_Handler:
bkpt #0
b .
.globl SysTick_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
.thumb_func
SysTick_Handler:
bkpt #0
b .
.global __use_two_region_memory
/*
__user_setup_stackheap() returns the:
- heap base in r0 (if the program uses the heap)
- stack base in sp
- heap limit in r2 (if the program uses the heap and uses two-region memory).
*/
.globl __user_setup_stackheap
.type __user_setup_stackheap, %function
.thumb_func
__user_setup_stackheap:
ldr r0, =__StackTop
mov sp, r0
.if Heap_Size
ldr r0, =__HeapBase
ldr r2, =__HeapLimit
.else
mov r0, #0
mov r2, #0
.endif
bx lr
/*
__user_initial_stackheap() returns the:
- heap base in r0
- stack base in r1, that is, the highest address in the stack region
- heap limit in r2
- stack limit in r3, that is, the lowest address in the stack region.
*/
/* DEPRICATED
.globl __user_initial_stackheap
.type __user_initial_stackheap, %function
.thumb_func
__user_initial_stackheap:
ldr r0, = __HeapBase
ldr r1, = __StackTop
ldr r2, = __HeapLimit
ldr r3, = __StackLimit
bx lr
*/
.end
|
normaldotcom/canable2-fw | 21,066 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g483xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g483xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G483xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT ADC5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT TIM20_BRK_IRQHandler [WEAK]
EXPORT TIM20_UP_IRQHandler [WEAK]
EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
EXPORT TIM20_CC_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
LPTIM1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
ADC5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
TIM20_BRK_IRQHandler
TIM20_UP_IRQHandler
TIM20_TRG_COM_IRQHandler
TIM20_CC_IRQHandler
FPU_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPI4_IRQHandler
AES_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
QUADSPI_IRQHandler
DMA1_Channel8_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMA2_Channel8_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 22,425 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g484xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g484xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G484xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD HRTIM1_TIMF_IRQHandler ; HRTIM Timer F global Interrupt
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD AES_IRQHandler ; AES global interrupt
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT ADC5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT HRTIM1_TIMF_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT TIM20_BRK_IRQHandler [WEAK]
EXPORT TIM20_UP_IRQHandler [WEAK]
EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
EXPORT TIM20_CC_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT FDCAN3_IT0_IRQHandler [WEAK]
EXPORT FDCAN3_IT1_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
LPTIM1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
ADC5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
HRTIM1_TIMF_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
TIM20_BRK_IRQHandler
TIM20_UP_IRQHandler
TIM20_TRG_COM_IRQHandler
TIM20_CC_IRQHandler
FPU_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPI4_IRQHandler
AES_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN2_IT1_IRQHandler
FDCAN3_IT0_IRQHandler
FDCAN3_IT1_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
QUADSPI_IRQHandler
DMA1_Channel8_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMA2_Channel8_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 20,911 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g473xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g473xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G473xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT ADC5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT TIM20_BRK_IRQHandler [WEAK]
EXPORT TIM20_UP_IRQHandler [WEAK]
EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
EXPORT TIM20_CC_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
LPTIM1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
ADC5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
TIM20_BRK_IRQHandler
TIM20_UP_IRQHandler
TIM20_TRG_COM_IRQHandler
TIM20_CC_IRQHandler
FPU_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPI4_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
QUADSPI_IRQHandler
DMA1_Channel8_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMA2_Channel8_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 20,146 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g471xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g471xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G471xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
LPTIM1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
FPU_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPI4_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
QUADSPI_IRQHandler
DMA1_Channel8_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMA2_Channel8_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 19,563 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g441xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g441xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G441xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD AES_IRQHandler ; AES global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
LPTIM1_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
FPU_IRQHandler
AES_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
DMA2_Channel6_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 19,476 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g431xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g431xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G431xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
LPTIM1_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
FPU_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
DMA2_Channel6_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 19,393 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32gbk1cb.s | ;*******************************************************************************
;* @File Name : startup_stm32gbk1cb.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32GBK1CB Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
LPTIM1_IRQHandler
SPI3_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
FPU_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
DMA2_Channel6_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 22,338 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g474xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g474xx.s
;* @Author : MCD Application Team
;* @Brief : Vector table for MDK-ARM toolchain
;*******************************************************************************
;* Description : STM32G474xx Mainstream devices vector table for
;* MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400;
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200;
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD HRTIM1_TIMF_IRQHandler ; HRTIM Timer F global Interrupt
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_DAC_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT ADC5_IRQHandler [WEAK]
EXPORT UCPD1_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT HRTIM1_TIMF_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT TIM20_BRK_IRQHandler [WEAK]
EXPORT TIM20_UP_IRQHandler [WEAK]
EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
EXPORT TIM20_CC_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT FDCAN3_IT0_IRQHandler [WEAK]
EXPORT FDCAN3_IT1_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT DMAMUX_OVR_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT CORDIC_IRQHandler [WEAK]
EXPORT FMAC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
RTC_TAMP_LSECSS_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
LPTIM1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_DAC_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
ADC5_IRQHandler
UCPD1_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
HRTIM1_TIMF_IRQHandler
CRS_IRQHandler
SAI1_IRQHandler
TIM20_BRK_IRQHandler
TIM20_UP_IRQHandler
TIM20_TRG_COM_IRQHandler
TIM20_CC_IRQHandler
FPU_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPI4_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN2_IT1_IRQHandler
FDCAN3_IT0_IRQHandler
FDCAN3_IT1_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
DMAMUX_OVR_IRQHandler
QUADSPI_IRQHandler
DMA1_Channel8_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMA2_Channel8_IRQHandler
CORDIC_IRQHandler
FMAC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
normaldotcom/canable2-fw | 14,363 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s | /**
******************************************************************************
* @file startup_stm32g483xx.s
* @author MCD Application Team
* @brief STM32G483xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word LPTIM1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_DAC_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word ADC5_IRQHandler
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word AES_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_DAC_IRQHandler
.thumb_set TIM7_DAC_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak ADC5_IRQHandler
.thumb_set ADC5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 15,788 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s | /**
******************************************************************************
* @file startup_stm32g484xx.s
* @author MCD Application Team
* @brief STM32G484xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word LPTIM1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_DAC_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word ADC5_IRQHandler
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word HRTIM1_Master_IRQHandler
.word HRTIM1_TIMA_IRQHandler
.word HRTIM1_TIMB_IRQHandler
.word HRTIM1_TIMC_IRQHandler
.word HRTIM1_TIMD_IRQHandler
.word HRTIM1_TIME_IRQHandler
.word HRTIM1_FLT_IRQHandler
.word HRTIM1_TIMF_IRQHandler
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word AES_IRQHandler
.word FDCAN2_IT0_IRQHandler
.word FDCAN2_IT1_IRQHandler
.word FDCAN3_IT0_IRQHandler
.word FDCAN3_IT1_IRQHandler
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_DAC_IRQHandler
.thumb_set TIM7_DAC_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak ADC5_IRQHandler
.thumb_set ADC5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak HRTIM1_TIMF_IRQHandler
.thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak FDCAN3_IT0_IRQHandler
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
.weak FDCAN3_IT1_IRQHandler
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 14,283 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s | /**
******************************************************************************
* @file startup_stm32g473xx.s
* @author MCD Application Team
* @brief STM32G473xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word LPTIM1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_DAC_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word ADC5_IRQHandler
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_DAC_IRQHandler
.thumb_set TIM7_DAC_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak ADC5_IRQHandler
.thumb_set ADC5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 13,537 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s | /**
******************************************************************************
* @file startup_stm32g471xx.s
* @author MCD Application Team
* @brief STM32G471xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word 0
.word 0
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word LPTIM1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 12,776 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s | /**
******************************************************************************
* @file startup_stm32g441xx.s
* @author MCD Application Team
* @brief STM32G441xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word 0
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word 0
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word AES_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word 0
.word 0
.word DMA2_Channel6_IRQHandler
.word 0
.word 0
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 12,697 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s | /**
******************************************************************************
* @file startup_stm32g431xx.s
* @author MCD Application Team
* @brief STM32G431xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word 0
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word 0
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word 0
.word 0
.word DMA2_Channel6_IRQHandler
.word 0
.word 0
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 12,573 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s | /**
******************************************************************************
* @file startup_stm32gbk1cb.s
* @author MCD Application Team
* @brief STM32GBK1CB devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word 0
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word 0
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word 0
.word 0
.word DMA2_Channel6_IRQHandler
.word 0
.word 0
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 15,710 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s | /**
******************************************************************************
* @file startup_stm32g474xx.s
* @author MCD Application Team
* @brief STM32G474xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word LPTIM1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_DAC_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word ADC5_IRQHandler
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word HRTIM1_Master_IRQHandler
.word HRTIM1_TIMA_IRQHandler
.word HRTIM1_TIMB_IRQHandler
.word HRTIM1_TIMC_IRQHandler
.word HRTIM1_TIMD_IRQHandler
.word HRTIM1_TIME_IRQHandler
.word HRTIM1_FLT_IRQHandler
.word HRTIM1_TIMF_IRQHandler
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word 0
.word FDCAN2_IT0_IRQHandler
.word FDCAN2_IT1_IRQHandler
.word FDCAN3_IT0_IRQHandler
.word FDCAN3_IT1_IRQHandler
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_DAC_IRQHandler
.thumb_set TIM7_DAC_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak ADC5_IRQHandler
.thumb_set ADC5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak HRTIM1_TIMF_IRQHandler
.thumb_set HRTIM1_TIMF_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak FDCAN3_IT0_IRQHandler
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
.weak FDCAN3_IT1_IRQHandler
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 23,352 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g483xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g483xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G483xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_DAC_IRQHandler
B TIM7_DAC_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK ADC5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC5_IRQHandler
B ADC5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK TIM20_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_BRK_IRQHandler
B TIM20_BRK_IRQHandler
PUBWEAK TIM20_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_UP_IRQHandler
B TIM20_UP_IRQHandler
PUBWEAK TIM20_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_TRG_COM_IRQHandler
B TIM20_TRG_COM_IRQHandler
PUBWEAK TIM20_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_CC_IRQHandler
B TIM20_CC_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK DMA1_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel8_IRQHandler
B DMA1_Channel8_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMA2_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel8_IRQHandler
B DMA2_Channel8_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 25,521 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g484xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g484xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G484xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD HRTIM1_TIMF_IRQHandler ; HRTIM Timer F global Interrupt
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD AES_IRQHandler ; AES global interrupt
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_DAC_IRQHandler
B TIM7_DAC_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK ADC5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC5_IRQHandler
B ADC5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK HRTIM1_TIMF_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMF_IRQHandler
B HRTIM1_TIMF_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK TIM20_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_BRK_IRQHandler
B TIM20_BRK_IRQHandler
PUBWEAK TIM20_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_UP_IRQHandler
B TIM20_UP_IRQHandler
PUBWEAK TIM20_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_TRG_COM_IRQHandler
B TIM20_TRG_COM_IRQHandler
PUBWEAK TIM20_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_CC_IRQHandler
B TIM20_CC_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK FDCAN3_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN3_IT0_IRQHandler
B FDCAN3_IT0_IRQHandler
PUBWEAK FDCAN3_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN3_IT1_IRQHandler
B FDCAN3_IT1_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK DMA1_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel8_IRQHandler
B DMA1_Channel8_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMA2_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel8_IRQHandler
B DMA2_Channel8_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 23,163 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g473xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g473xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G473xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_DAC_IRQHandler
B TIM7_DAC_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK ADC5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC5_IRQHandler
B ADC5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK TIM20_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_BRK_IRQHandler
B TIM20_BRK_IRQHandler
PUBWEAK TIM20_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_UP_IRQHandler
B TIM20_UP_IRQHandler
PUBWEAK TIM20_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_TRG_COM_IRQHandler
B TIM20_TRG_COM_IRQHandler
PUBWEAK TIM20_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_CC_IRQHandler
B TIM20_CC_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK DMA1_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel8_IRQHandler
B DMA1_Channel8_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMA2_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel8_IRQHandler
B DMA2_Channel8_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 21,991 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g471xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g471xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G471xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_IRQHandler
B COMP4_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK DMA1_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel8_IRQHandler
B DMA1_Channel8_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMA2_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel8_IRQHandler
B DMA2_Channel8_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 20,956 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g441xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g441xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G441xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD AES_IRQHandler ; AES global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_IRQHandler
B COMP4_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES_IRQHandler
B AES_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 20,825 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g431xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g431xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G431xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_IRQHandler
B COMP4_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 20,705 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32gbk1cb.s | ;*******************************************************************************
;* @File Name : startup_stm32gbk1cb.s
;* @Author : MCD Application Team
;* @Brief : STM32GBK1CB Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD 0 ; Reserved
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_IRQHandler ; COMP4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_IRQHandler
B COMP4_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
normaldotcom/canable2-fw | 25,392 | Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g474xx.s | ;*******************************************************************************
;* @File Name : startup_stm32g474xx.s
;* @Author : MCD Application Team
;* @Brief : STM32G474xx Devices vector
;*******************************************************************************
;* Description : This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors
DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD ADC5_IRQHandler ; ADC5
DCD UCPD1_IRQHandler ; UCPD1
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD HRTIM1_TIMF_IRQHandler ; HRTIM Timer F global Interrupt
DCD CRS_IRQHandler ; CRS Interrupt
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt
DCD QUADSPI_IRQHandler ; QUADSPI
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8
DCD CORDIC_IRQHandler ; CORDIC
DCD FMAC_IRQHandler ; FMAC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK RTC_TAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_TAMP_LSECSS_IRQHandler
B RTC_TAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_DAC_IRQHandler
B TIM7_DAC_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK ADC5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC5_IRQHandler
B ADC5_IRQHandler
PUBWEAK UCPD1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UCPD1_IRQHandler
B UCPD1_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK HRTIM1_TIMF_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMF_IRQHandler
B HRTIM1_TIMF_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK TIM20_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_BRK_IRQHandler
B TIM20_BRK_IRQHandler
PUBWEAK TIM20_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_UP_IRQHandler
B TIM20_UP_IRQHandler
PUBWEAK TIM20_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_TRG_COM_IRQHandler
B TIM20_TRG_COM_IRQHandler
PUBWEAK TIM20_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_CC_IRQHandler
B TIM20_CC_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK FDCAN3_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN3_IT0_IRQHandler
B FDCAN3_IT0_IRQHandler
PUBWEAK FDCAN3_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN3_IT1_IRQHandler
B FDCAN3_IT1_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK DMAMUX_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX_OVR_IRQHandler
B DMAMUX_OVR_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK DMA1_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel8_IRQHandler
B DMA1_Channel8_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK DMA2_Channel8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel8_IRQHandler
B DMA2_Channel8_IRQHandler
PUBWEAK CORDIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CORDIC_IRQHandler
B CORDIC_IRQHandler
PUBWEAK FMAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMAC_IRQHandler
B FMAC_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nrdmn/elbrus-docs | 10,207 | linux-e2k-loader-0.01.s | ; Linux/E2k loader, rev. 0.01
bits 16
org 0x7c00
; set up stack
cli
mov ax,0x1000
mov ss,ax
mov sp,0xfffe
sti
; clear direction
cld
; check if video mode is 3 ...
mov ah,0xf
int 0x10
cmp al,0x3
jz .video_mode_correctly_set
; ... if not, set video mode to 3
mov ax,0x3
int 0x10
.video_mode_correctly_set:
; write the video mode into the boot info struct
mov byte [cs:boot_info.vga_mode],0x3
; read sector 1, head 0, cylinder 0 of drive #0 to 2003:0000
mov ah,0x20
mov es,ax ; segment=0x2003
mov ds,ax
xor bx,bx ; offset=0
mov dx,0x80 ; head=0, drive=0x80
mov cx,0x1 ; cylinder=0, sector=1
mov ax,0x201 ; read one sector
int 0x13
lea si,[mbr_read_failed]
jc print_error
; look for active partition in mbr partition table
add bx,0x1be
.look_for_active_partition:
cmp byte [bx],0x80
jz load_rest_of_bootloader
add bl,0x10
cmp bl,0xfe
jnz .look_for_active_partition
lea si,[no_active_partition]
print_error:
mov ah,0xe
xor bx,bx
.print_error_loop:
cs lodsb
int 0x10
cmp al,0x0
jnz .print_error_loop
; clear interrupts and halt
cli
hlt
load_rest_of_bootloader:
; check if partition type is 0xe2
cmp byte [bx+0x4],0xe2
lea si,[bad_partition_type]
jnz print_error
mov dh,[bx+0x1] ; read heads from partition table entry
mov cx,[bx+0x2] ; read cylinders and sectors from partition table entry
xor ax,ax
mov es,ax
mov ds,ax
mov [read_window.heads],dh
mov [read_window.cylinders_and_sectors],cx
lds bx,[0x104] ; load pointer to drive #0's fixed disk parameter table
mov ecx,[bx] ; read number of cylinders
mov [cs:boot_info.cylinders],ecx
mov cl,[bx+0xe] ; read number of sectors per track
mov [cs:drive_sectors],cl
mov [cs:boot_info.sectors],cl
mov ds,ax
mov al,0x1
call shift_read_window
; load 3 sectors from disk to 0x7e00
mov bx,main
mov ax,0x203
int 0x13
lea si,[loader_read_failed]
jc print_error
; check bootloader signature
cmp dword [pvk],'PVK!'
lea si,[bad_loader]
jnz print_error
; fully loaded the bootloader!
jmp main
; shift read window by al sectors
shift_read_window:
mov cx,[read_window.cylinders_and_sectors]
mov dh,[read_window.heads]
mov bx,cx
and bx,strict word 0x3f ; extract sectors
xor ah,ah
add bx,ax ; bx = sectors + al
.loop:
; check if drive's number of sectors is not greater
; than read window's sector
cmp bx,[drive_sectors]
jbe .done
; if it is greater, subtract drive's number of sectors per track
; from read window's sector
sub bx,[drive_sectors]
; and increment read window's head
inc dh
; check if disk's number of heads if below read window's head
cmp dh,[boot_info.heads]
jb .loop
; set read window's head to zero and increment cylinder
; then jump back
xor dh,dh
inc ch
jnz .loop
add cx,strict word 0x40
jmp near .loop
.done:
; decrement cylinder
and cx,strict word -0x40
; extract sector
or cx,bx
mov [read_window.cylinders_and_sectors],cx
mov [read_window.heads],dh
ret
read_window:
.heads db 0
.cylinders_and_sectors dw 0
drive_sectors dw 0
times 256-($-$$) db 0
boot_info:
.signature dw 0x8086
.cylinders dw 0
.heads db 0
.sectors db 0
.vga_mode db 3
.num_banks db 1 ; number of memory banks
.kernel_base_lo dd 0
.kernel_base_hi dd 0
.kernel_size_lo dd 0
.kernel_size_hi dd 0
.ramdisk_base_lo dd 0
.ramdisk_base_hi dd 0
.ramdisk_size_lo dd 0
.ramdisk_size_hi dd 0
times 128 db 0
bad_partition_type db 'Bad partition type', 0
bad_loader db 'Bad loader', 0
loader_read_failed db 'Loader read failed', 0
mbr_read_failed db 'MBR read failed', 0
no_active_partition db 'No active partition', 0
db 0
dw 0xaa55
main:
lea si,[version]
call puts
lgdt [gdt]
mov al,0x7f
call shift_read_window
; if kernel_base_lo is 0, set it to 0x100000
cmp strict dword [boot_info.kernel_base_lo],strict dword 0
jnz .kernel_base_set
mov strict dword [boot_info.kernel_base_lo],0x100000
.kernel_base_set:
; if ramdisk_base_lo is 0, put it directly behind the kernel
; and round up to nearest 4K
cmp strict dword [boot_info.ramdisk_base_lo],strict dword 0
jnz .ramdisk_base_set
mov eax,[boot_info.kernel_base_lo]
add eax,[boot_info.kernel_size_lo]
add eax,0xfff
and eax,0xfffff000
mov [boot_info.ramdisk_base_lo],eax
.ramdisk_base_set:
; {kernel,ramdisk}_{base,size} must be below 4G
xor eax,eax
cmp [boot_info.kernel_base_hi],eax
jnz .wrong_memory_layout
cmp [boot_info.kernel_size_hi],eax
jnz .wrong_memory_layout
cmp [boot_info.ramdisk_base_hi],eax
jnz .wrong_memory_layout
cmp [boot_info.ramdisk_size_hi],eax
jnz .wrong_memory_layout
; query memory map
mov ax,0xe801
int 0x15
shl eax,10 ; memory between 1M and 16M, in bytes
shl ebx,16 ; memory above 16M, in bytes
add eax,ebx ; memory above 1M, in bytes
add eax,0x100000 ; add 1M to get total memory in bytes
lea si,[bios_accessible_memory_size]
call puts
call print_hex_dword
; is end of kernel above BIOS accessible memory area?
mov ebx,[boot_info.kernel_base_lo]
mov edi,ebx
add ebx,[boot_info.kernel_size_lo]
cmp ebx,eax
ja .wrong_memory_layout
; is end of ramdisk above BIOS accessible memory area?
mov ecx,[boot_info.ramdisk_base_lo]
mov esi,ecx
add ecx,[boot_info.ramdisk_size_lo]
cmp ecx,eax
ja .wrong_memory_layout
; is ramdisk base above kernel base?
cmp edi,esi
ja .ramdisk_base_above_kernel_base
; is end of kernel below or at ramdisk base?
cmp ebx,esi
jbe .ok
.wrong_memory_layout:
lea si,[wrong_memory_layout_requested]
jmp print_error
.ramdisk_base_above_kernel_base:
; is kernel base above end of ramdisk?
cmp ecx,edi
ja .wrong_memory_layout
.ok:
; kernel and ramdisk do not overlap and are within BIOS accessible memory
lea si,[kernel]
mov ebp,[boot_info.kernel_size_lo]
mov edi,[boot_info.kernel_base_lo]
call copy_from_disk
mov ebp,[boot_info.ramdisk_size_lo]
test ebp,ebp
jz .switch_to_e2k
lea si,[ramdisk]
mov edi,[boot_info.ramdisk_base_lo]
call copy_from_disk
.switch_to_e2k:
jmp near .magic
.magic:
icebp
db 0xee, 0xbc ; what's this?
dd boot_info
; This function copys from disk to memory in chunks of 1/30th
; of size and outputs a progress bar with one '*' per chunk.
; edi: base
; ebp: size
copy_from_disk:
; print description
call puts
; print size
mov eax,ebp
call print_hex_dword
; convert size to sectors
add ebp,0x1ff
shr ebp,9
; print from
lea si,[from]
call puts
; print base
mov eax,edi
call print_hex_dword
; print progress bar
lea si,[progress_bar]
call puts
; divide size by 30
mov eax,ebp
xor edx,edx
mov ecx,30
div ecx
mov [progress_bar.size_1_30th],eax ; write quotient
mov [progress_bar.size_remainder],edx ; write remainder
mov ecx,ebp
sub ecx,eax
mov [progress_bar.remaining],ecx
mov [progress_bar.sectors_copied],edx
.loop:
; check if less than 1/30th is remaining
mov ecx,[progress_bar.remaining]
cmp ebp,ecx
ja .1
; print one '*' per 1/30th
xor bx,bx
mov ax,0xe2a
int 0x10
sub ecx,[progress_bar.size_1_30th]
mov eax,[progress_bar.sectors_copied]
add eax,[progress_bar.size_remainder]
mov [progress_bar.sectors_copied],eax
jnc .2
dec ecx ; decrement chunks remaining
.2:
mov [progress_bar.remaining],ecx
.1:
; read up to 0x7f sectors from disk
mov dl,0x80
mov dh,[read_window.heads]
mov cx,[read_window.cylinders_and_sectors]
mov ax,0x3000
mov es,ax
xor bx,bx
mov si,0x7f
cmp ebp,strict dword 0x7f
cmovbe si,bp
mov ax,si
mov ah,2
int 0x13
jc .print_read_error
mov ax,si
call shift_read_window
; enable protected mode
cli
mov eax,cr0
or eax,strict dword 1
mov cr0,eax
jmp 0x10:.protected_mode_enabled
.protected_mode_enabled:
bits 32
; copy si sectors to base
mov ax,8
db 0x66 ; TODO I'm unable to get nasm to print these
mov ds,ax ; two movs with a 0x66 (16 bit operand size)
db 0x66 ; prefix, so I manually add the prefixes here
mov es,ax ;
xor ecx,ecx
mov cx,si
shl ecx,7
mov esi,0x30000
rep movsd
jmp 0x18:.disable_protected_mode
.disable_protected_mode:
bits 16
mov ax,0x20
mov ds,ax
mov es,ax
mov eax,cr0
and al,0xfe
mov cr0,eax
jmp 0:.protected_mode_disabled
.protected_mode_disabled:
; reset ds and es
mov ax,cs
mov ds,ax
mov es,ax
sti
; loop while size is > 0x7f
cmp ebp,strict dword 0x7f
jbe .ret
sub ebp,strict dword 0x7f
jmp .loop
.ret:
ret
.print_read_error:
lea si,[read_error]
jmp print_error
puts:
push ax
push bx
mov ah,0xe
xor bx,bx
lodsb
.1:
int 0x10
lodsb
cmp al,0
jnz .1
pop bx
pop ax
ret
putchar:
push bx
xor bx,bx
mov ah,0xe
int 0x10
pop bx
ret
print_hex_digit:
add al,0x30
cmp al,0x3a
jb .1
add al,0x7
.1:
call putchar
ret
print_hex_byte:
mov al,bl
shr al,4
call print_hex_digit
mov al,bl
and al,0xf
call print_hex_digit
ret
print_hex_dword:
push ax
push ebx
mov ebx,eax
rol ebx,8
call print_hex_byte
rol ebx,8
call print_hex_byte
rol ebx,8
call print_hex_byte
rol ebx,8
call print_hex_byte
mov al,0x20
call putchar
pop ebx
pop ax
ret
version db 'Linux/E2k loader, rev. 0.01', 13, 10, 0
kernel db 13, 10, 'kernel 0x', 0
ramdisk db 13, 10, 'ramdisk 0x', 0
read_error db 'read error', 0
from db 'from 0x', 0
bios_accessible_memory_size db 'BIOS accessible memory size 0x', 0
wrong_memory_layout_requested db 'wrong memory layout requested', 0
progress_bar:
db '['
times 30 db '.'
db ']'
times 31 db 8 ; these are backspaces
db 0
.size_1_30th dd 0
.size_remainder dd 0
.remaining dd 0
.sectors_copied dd 0
gdt:
; structure of a descriptor:
; dw segment limit 0-15
; dw base address 0-15
; db base address 16-23
; db db access byte
; db flags and segment limit 16-19
; db base address 24-31
; base address 0x8140, segment limit 0x27, 16 bit
dw 0x0027, 0x8140
db 0x00, 0x00, 0x00, 0x00
; base address 0xff000000, segment limit 0xf0000000, 32 bit
dw 0x0000, 0x0000
db 0x00, 0x00, 0xff, 0xff
; base address 0xffcf9200, segment limit 0xf0000000, 32 bit
dw 0x0000, 0x9200
db 0xcf, 0x00, 0xff, 0xff
; base address 0xff4f9b00, segment limit 0xf0000000, 32 bit
dw 0x0000, 0x9b00
db 0x4f, 0x00, 0xff, 0xff
; base address 0xff009a00, segment limit 0xf0000000, 32 bit
dw 0x0000, 0x9a00
db 0x00, 0x00, 0xff, 0xff
; base address 0x9a00, segment limit 0, 16 bit
dw 0x0000, 0x9200
db 0x00, 0x00, 0x00, 0x00
times 2044-($-$$) db 0
pvk db 'PVK!'
|
ntu-ssl/rr-artifact | 6,493 | openssl-1.1.0l/crypto/ia64cpuid.S | // Copyright 2004-2017 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under the OpenSSL license (the "License"). You may not use
// this file except in compliance with the License. You can obtain a copy
// in the file LICENSE in the source distribution or at
// https://www.openssl.org/source/license.html
// Works on all IA-64 platforms: Linux, HP-UX, Win64i...
// On Win64i compile with ias.exe.
.text
#if defined(_HPUX_SOURCE) && !defined(_LP64)
#define ADDP addp4
#else
#define ADDP add
#endif
.global OPENSSL_cpuid_setup#
.proc OPENSSL_cpuid_setup#
OPENSSL_cpuid_setup:
{ .mib; br.ret.sptk.many b0 };;
.endp OPENSSL_cpuid_setup#
.global OPENSSL_rdtsc#
.proc OPENSSL_rdtsc#
OPENSSL_rdtsc:
{ .mib; mov r8=ar.itc
br.ret.sptk.many b0 };;
.endp OPENSSL_rdtsc#
.global OPENSSL_atomic_add#
.proc OPENSSL_atomic_add#
.align 32
OPENSSL_atomic_add:
{ .mii; ld4 r2=[r32]
nop.i 0
nop.i 0 };;
.Lspin:
{ .mii; mov ar.ccv=r2
add r8=r2,r33
mov r3=r2 };;
{ .mmi; mf;;
cmpxchg4.acq r2=[r32],r8,ar.ccv
nop.i 0 };;
{ .mib; cmp.ne p6,p0=r2,r3
nop.i 0
(p6) br.dpnt .Lspin };;
{ .mib; nop.m 0
sxt4 r8=r8
br.ret.sptk.many b0 };;
.endp OPENSSL_atomic_add#
// Returns a structure comprising pointer to the top of stack of
// the caller and pointer beyond backing storage for the current
// register frame. The latter is required, because it might be
// insufficient to wipe backing storage for the current frame
// (as this procedure does), one might have to go further, toward
// higher addresses to reach for whole "retroactively" saved
// context...
.global OPENSSL_wipe_cpu#
.proc OPENSSL_wipe_cpu#
.align 32
OPENSSL_wipe_cpu:
.prologue
.fframe 0
.save ar.pfs,r2
.save ar.lc,r3
{ .mib; alloc r2=ar.pfs,0,96,0,96
mov r3=ar.lc
brp.loop.imp .L_wipe_top,.L_wipe_end-16
};;
{ .mii; mov r9=ar.bsp
mov r8=pr
mov ar.lc=96 };;
.body
{ .mii; add r9=96*8-8,r9
mov ar.ec=1 };;
// One can sweep double as fast, but then we can't guarantee
// that backing storage is wiped...
.L_wipe_top:
{ .mfi; st8 [r9]=r0,-8
mov f127=f0
mov r127=r0 }
{ .mfb; nop.m 0
nop.f 0
br.ctop.sptk .L_wipe_top };;
.L_wipe_end:
{ .mfi; mov r11=r0
mov f6=f0
mov r14=r0 }
{ .mfi; mov r15=r0
mov f7=f0
mov r16=r0 }
{ .mfi; mov r17=r0
mov f8=f0
mov r18=r0 }
{ .mfi; mov r19=r0
mov f9=f0
mov r20=r0 }
{ .mfi; mov r21=r0
mov f10=f0
mov r22=r0 }
{ .mfi; mov r23=r0
mov f11=f0
mov r24=r0 }
{ .mfi; mov r25=r0
mov f12=f0
mov r26=r0 }
{ .mfi; mov r27=r0
mov f13=f0
mov r28=r0 }
{ .mfi; mov r29=r0
mov f14=f0
mov r30=r0 }
{ .mfi; mov r31=r0
mov f15=f0
nop.i 0 }
{ .mfi; mov f16=f0 }
{ .mfi; mov f17=f0 }
{ .mfi; mov f18=f0 }
{ .mfi; mov f19=f0 }
{ .mfi; mov f20=f0 }
{ .mfi; mov f21=f0 }
{ .mfi; mov f22=f0 }
{ .mfi; mov f23=f0 }
{ .mfi; mov f24=f0 }
{ .mfi; mov f25=f0 }
{ .mfi; mov f26=f0 }
{ .mfi; mov f27=f0 }
{ .mfi; mov f28=f0 }
{ .mfi; mov f29=f0 }
{ .mfi; mov f30=f0 }
{ .mfi; add r9=96*8+8,r9
mov f31=f0
mov pr=r8,0x1ffff }
{ .mib; mov r8=sp
mov ar.lc=r3
br.ret.sptk b0 };;
.endp OPENSSL_wipe_cpu#
.global OPENSSL_cleanse#
.proc OPENSSL_cleanse#
OPENSSL_cleanse:
{ .mib; cmp.eq p6,p0=0,r33 // len==0
ADDP r32=0,r32
(p6) br.ret.spnt b0 };;
{ .mib; and r2=7,r32
cmp.leu p6,p0=15,r33 // len>=15
(p6) br.cond.dptk .Lot };;
.Little:
{ .mib; st1 [r32]=r0,1
cmp.ltu p6,p7=1,r33 } // len>1
{ .mbb; add r33=-1,r33 // len--
(p6) br.cond.dptk .Little
(p7) br.ret.sptk.many b0 };;
.Lot:
{ .mib; cmp.eq p6,p0=0,r2
(p6) br.cond.dptk .Laligned };;
{ .mmi; st1 [r32]=r0,1;;
and r2=7,r32 }
{ .mib; add r33=-1,r33
br .Lot };;
.Laligned:
{ .mmi; st8 [r32]=r0,8
and r2=-8,r33 // len&~7
add r33=-8,r33 };; // len-=8
{ .mib; cmp.ltu p6,p0=8,r2 // ((len+8)&~7)>8
(p6) br.cond.dptk .Laligned };;
{ .mbb; cmp.eq p6,p7=r0,r33
(p7) br.cond.dpnt .Little
(p6) br.ret.sptk.many b0 };;
.endp OPENSSL_cleanse#
.global CRYPTO_memcmp#
.proc CRYPTO_memcmp#
.align 32
.skip 16
CRYPTO_memcmp:
.prologue
{ .mib; mov r8=0
cmp.eq p6,p0=0,r34 // len==0?
(p6) br.ret.spnt b0 };;
.save ar.pfs,r2
{ .mib; alloc r2=ar.pfs,3,5,0,8
.save ar.lc,r3
mov r3=ar.lc
brp.loop.imp .Loop_cmp_ctop,.Loop_cmp_cend-16
}
{ .mib; sub r10=r34,r0,1
.save pr,r9
mov r9=pr };;
{ .mii; ADDP r16=0,r32
mov ar.lc=r10
mov ar.ec=4 }
{ .mib; ADDP r17=0,r33
mov pr.rot=1<<16 };;
.Loop_cmp_ctop:
{ .mib; (p16) ld1 r32=[r16],1
(p18) xor r34=r34,r38 }
{ .mib; (p16) ld1 r36=[r17],1
(p19) or r8=r8,r35
br.ctop.sptk .Loop_cmp_ctop };;
.Loop_cmp_cend:
{ .mib; cmp.ne p6,p0=0,r8
mov ar.lc=r3 };;
{ .mib;
(p6) mov r8=1
mov pr=r9,0x1ffff
br.ret.sptk.many b0 };;
.endp CRYPTO_memcmp#
.global OPENSSL_instrument_bus#
.proc OPENSSL_instrument_bus#
OPENSSL_instrument_bus:
{ .mmi; mov r2=r33
ADDP r32=0,r32 }
{ .mmi; mov r8=ar.itc;;
mov r10=r0
mov r9=r8 };;
{ .mmi; fc r32;;
ld4 r8=[r32] };;
{ .mmi; mf
mov ar.ccv=r8
add r8=r8,r10 };;
{ .mmi; cmpxchg4.acq r3=[r32],r8,ar.ccv
};;
.Loop:
{ .mmi; mov r8=ar.itc;;
sub r10=r8,r9 // diff=tick-lasttick
mov r9=r8 };; // lasttick=tick
{ .mmi; fc r32;;
ld4 r8=[r32] };;
{ .mmi; mf
mov ar.ccv=r8
add r8=r8,r10 };;
{ .mmi; cmpxchg4.acq r3=[r32],r8,ar.ccv
add r33=-1,r33
add r32=4,r32 };;
{ .mib; cmp4.ne p6,p0=0,r33
(p6) br.cond.dptk .Loop };;
{ .mib; sub r8=r2,r33
br.ret.sptk.many b0 };;
.endp OPENSSL_instrument_bus#
.global OPENSSL_instrument_bus2#
.proc OPENSSL_instrument_bus2#
OPENSSL_instrument_bus2:
{ .mmi; mov r2=r33 // put aside cnt
ADDP r32=0,r32 }
{ .mmi; mov r8=ar.itc;;
mov r10=r0
mov r9=r8 };;
{ .mmi; fc r32;;
ld4 r8=[r32] };;
{ .mmi; mf
mov ar.ccv=r8
add r8=r8,r10 };;
{ .mmi; cmpxchg4.acq r3=[r32],r8,ar.ccv
};;
{ .mmi; mov r8=ar.itc;;
sub r10=r8,r9
mov r9=r8 };;
.Loop2:
{ .mmi; mov r11=r10 // lastdiff=diff
add r34=-1,r34 };; // --max
{ .mmi; fc r32;;
ld4 r8=[r32]
cmp4.eq p6,p0=0,r34 };;
{ .mmi; mf
mov ar.ccv=r8
add r8=r8,r10 };;
{ .mmb; cmpxchg4.acq r3=[r32],r8,ar.ccv
(p6) br.cond.spnt .Ldone2 };;
{ .mmi; mov r8=ar.itc;;
sub r10=r8,r9 // diff=tick-lasttick
mov r9=r8 };; // lasttick=tick
{ .mmi; cmp.ne p6,p0=r10,r11;; // diff!=lastdiff
(p6) add r33=-1,r33 };; // conditional --cnt
{ .mib; cmp4.ne p7,p0=0,r33
(p6) add r32=4,r32 // conditional ++out
(p7) br.cond.dptk .Loop2 };;
.Ldone2:
{ .mib; sub r8=r2,r33
br.ret.sptk.many b0 };;
.endp OPENSSL_instrument_bus2#
|
ntu-ssl/rr-artifact | 12,351 | openssl-1.1.0l/crypto/sparccpuid.S | ! Copyright 2005-2016 The OpenSSL Project Authors. All Rights Reserved.
!
! Licensed under the OpenSSL license (the "License"). You may not use
! this file except in compliance with the License. You can obtain a copy
! in the file LICENSE in the source distribution or at
! https://www.openssl.org/source/license.html
#ifdef OPENSSL_FIPSCANISTER
#include <openssl/fipssyms.h>
#endif
#if defined(__SUNPRO_C) && defined(__sparcv9)
# define ABI64 /* They've said -xarch=v9 at command line */
#elif defined(__GNUC__) && defined(__arch64__)
# define ABI64 /* They've said -m64 at command line */
#endif
#ifdef ABI64
.register %g2,#scratch
.register %g3,#scratch
# define FRAME -192
# define BIAS 2047
#else
# define FRAME -96
# define BIAS 0
#endif
.text
.align 32
.global OPENSSL_wipe_cpu
.type OPENSSL_wipe_cpu,#function
! Keep in mind that this does not excuse us from wiping the stack!
! This routine wipes registers, but not the backing store [which
! resides on the stack, toward lower addresses]. To facilitate for
! stack wiping I return pointer to the top of stack of the *caller*.
OPENSSL_wipe_cpu:
save %sp,FRAME,%sp
nop
#ifdef __sun
#include <sys/trap.h>
ta ST_CLEAN_WINDOWS
#else
call .walk.reg.wins
#endif
nop
call .PIC.zero.up
mov .zero-(.-4),%o0
ld [%o0],%f0
ld [%o0],%f1
subcc %g0,1,%o0
! Following is V9 "rd %ccr,%o0" instruction. However! V8
! specification says that it ("rd %asr2,%o0" in V8 terms) does
! not cause illegal_instruction trap. It therefore can be used
! to determine if the CPU the code is executing on is V8- or
! V9-compliant, as V9 returns a distinct value of 0x99,
! "negative" and "borrow" bits set in both %icc and %xcc.
.word 0x91408000 !rd %ccr,%o0
cmp %o0,0x99
bne .v8
nop
! Even though we do not use %fp register bank,
! we wipe it as memcpy might have used it...
.word 0xbfa00040 !fmovd %f0,%f62
.word 0xbba00040 !...
.word 0xb7a00040
.word 0xb3a00040
.word 0xafa00040
.word 0xaba00040
.word 0xa7a00040
.word 0xa3a00040
.word 0x9fa00040
.word 0x9ba00040
.word 0x97a00040
.word 0x93a00040
.word 0x8fa00040
.word 0x8ba00040
.word 0x87a00040
.word 0x83a00040 !fmovd %f0,%f32
.v8: fmovs %f1,%f31
clr %o0
fmovs %f0,%f30
clr %o1
fmovs %f1,%f29
clr %o2
fmovs %f0,%f28
clr %o3
fmovs %f1,%f27
clr %o4
fmovs %f0,%f26
clr %o5
fmovs %f1,%f25
clr %o7
fmovs %f0,%f24
clr %l0
fmovs %f1,%f23
clr %l1
fmovs %f0,%f22
clr %l2
fmovs %f1,%f21
clr %l3
fmovs %f0,%f20
clr %l4
fmovs %f1,%f19
clr %l5
fmovs %f0,%f18
clr %l6
fmovs %f1,%f17
clr %l7
fmovs %f0,%f16
clr %i0
fmovs %f1,%f15
clr %i1
fmovs %f0,%f14
clr %i2
fmovs %f1,%f13
clr %i3
fmovs %f0,%f12
clr %i4
fmovs %f1,%f11
clr %i5
fmovs %f0,%f10
clr %g1
fmovs %f1,%f9
clr %g2
fmovs %f0,%f8
clr %g3
fmovs %f1,%f7
clr %g4
fmovs %f0,%f6
clr %g5
fmovs %f1,%f5
fmovs %f0,%f4
fmovs %f1,%f3
fmovs %f0,%f2
add %fp,BIAS,%i0 ! return pointer to caller´s top of stack
ret
restore
.zero: .long 0x0,0x0
.PIC.zero.up:
retl
add %o0,%o7,%o0
#ifdef DEBUG
.global walk_reg_wins
.type walk_reg_wins,#function
walk_reg_wins:
#endif
.walk.reg.wins:
save %sp,FRAME,%sp
cmp %i7,%o7
be 2f
clr %o0
cmp %o7,0 ! compiler never cleans %o7...
be 1f ! could have been a leaf function...
clr %o1
call .walk.reg.wins
nop
1: clr %o2
clr %o3
clr %o4
clr %o5
clr %o7
clr %l0
clr %l1
clr %l2
clr %l3
clr %l4
clr %l5
clr %l6
clr %l7
add %o0,1,%i0 ! used for debugging
2: ret
restore
.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
.global OPENSSL_atomic_add
.type OPENSSL_atomic_add,#function
.align 32
OPENSSL_atomic_add:
#ifndef ABI64
subcc %g0,1,%o2
.word 0x95408000 !rd %ccr,%o2, see comment above
cmp %o2,0x99
be .v9
nop
save %sp,FRAME,%sp
ba .enter
nop
#ifdef __sun
! Note that you do not have to link with libthread to call thr_yield,
! as libc provides a stub, which is overloaded the moment you link
! with *either* libpthread or libthread...
#define YIELD_CPU thr_yield
#else
! applies at least to Linux and FreeBSD... Feedback expected...
#define YIELD_CPU sched_yield
#endif
.spin: call YIELD_CPU
nop
.enter: ld [%i0],%i2
cmp %i2,-4096
be .spin
mov -1,%i2
swap [%i0],%i2
cmp %i2,-1
be .spin
add %i2,%i1,%i2
stbar
st %i2,[%i0]
sra %i2,%g0,%i0
ret
restore
.v9:
#endif
ld [%o0],%o2
1: add %o1,%o2,%o3
.word 0xd7e2100a !cas [%o0],%o2,%o3, compare [%o0] with %o2 and swap %o3
cmp %o2,%o3
bne 1b
mov %o3,%o2 ! cas is always fetching to dest. register
add %o1,%o2,%o0 ! OpenSSL expects the new value
retl
sra %o0,%g0,%o0 ! we return signed int, remember?
.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
.global _sparcv9_rdtick
.align 32
_sparcv9_rdtick:
subcc %g0,1,%o0
.word 0x91408000 !rd %ccr,%o0
cmp %o0,0x99
bne .notick
xor %o0,%o0,%o0
.word 0x91410000 !rd %tick,%o0
retl
.word 0x93323020 !srlx %o0,32,%o1
.notick:
retl
xor %o1,%o1,%o1
.type _sparcv9_rdtick,#function
.size _sparcv9_rdtick,.-_sparcv9_rdtick
.global _sparcv9_vis1_probe
.align 8
_sparcv9_vis1_probe:
add %sp,BIAS+2,%o1
.word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0
retl
.word 0x81b00d80 !fxor %f0,%f0,%f0
.type _sparcv9_vis1_probe,#function
.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
! Probe and instrument VIS1 instruction. Output is number of cycles it
! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
! is slow (documented to be 6 cycles on T2) and the core is in-order
! single-issue, it should be possible to distinguish Tx reliably...
! Observed return values are:
!
! UltraSPARC IIe 7
! UltraSPARC III 7
! UltraSPARC T1 24
! SPARC T4 65(*)
!
! (*) result has lesser to do with VIS instruction latencies, rdtick
! appears that slow, but it does the trick in sense that FP and
! VIS code paths are still slower than integer-only ones.
!
! Numbers for T2 and SPARC64 V-VII are more than welcomed.
!
! It would be possible to detect specifically US-T1 by instrumenting
! fmul8ulx16, which is emulated on T1 and as such accounts for quite
! a lot of %tick-s, couple of thousand on Linux...
.global _sparcv9_vis1_instrument
.align 8
_sparcv9_vis1_instrument:
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x91410000 !rd %tick,%o0
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x93410000 !rd %tick,%o1
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x95410000 !rd %tick,%o2
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x97410000 !rd %tick,%o3
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x99410000 !rd %tick,%o4
! calculate intervals
sub %o1,%o0,%o0
sub %o2,%o1,%o1
sub %o3,%o2,%o2
sub %o4,%o3,%o3
! find minimum value
cmp %o0,%o1
.word 0x38680002 !bgu,a %xcc,.+8
mov %o1,%o0
cmp %o0,%o2
.word 0x38680002 !bgu,a %xcc,.+8
mov %o2,%o0
cmp %o0,%o3
.word 0x38680002 !bgu,a %xcc,.+8
mov %o3,%o0
retl
nop
.type _sparcv9_vis1_instrument,#function
.size _sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument
.global _sparcv9_vis2_probe
.align 8
_sparcv9_vis2_probe:
retl
.word 0x81b00980 !bshuffle %f0,%f0,%f0
.type _sparcv9_vis2_probe,#function
.size _sparcv9_vis2_probe,.-_sparcv9_vis2_probe
.global _sparcv9_fmadd_probe
.align 8
_sparcv9_fmadd_probe:
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
retl
.word 0x81b80440 !fmaddd %f0,%f0,%f2,%f0
.type _sparcv9_fmadd_probe,#function
.size _sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe
.global _sparcv9_rdcfr
.align 8
_sparcv9_rdcfr:
retl
.word 0x91468000 !rd %asr26,%o0
.type _sparcv9_rdcfr,#function
.size _sparcv9_rdcfr,.-_sparcv9_rdcfr
.global _sparcv9_vis3_probe
.align 8
_sparcv9_vis3_probe:
retl
.word 0x81b022a0 !xmulx %g0,%g0,%g0
.type _sparcv9_vis3_probe,#function
.size _sparcv9_vis3_probe,.-_sparcv9_vis3_probe
.global _sparcv9_random
.align 8
_sparcv9_random:
retl
.word 0x91b002a0 !random %o0
.type _sparcv9_random,#function
.size _sparcv9_random,.-_sparcv9_vis3_probe
.global _sparcv9_fjaesx_probe
.align 8
_sparcv9_fjaesx_probe:
.word 0x81b09206 !faesencx %f2,%f6,%f0
retl
nop
.size _sparcv9_fjaesx_probe,.-_sparcv9_fjaesx_probe
.global OPENSSL_cleanse
.align 32
OPENSSL_cleanse:
cmp %o1,14
nop
#ifdef ABI64
bgu %xcc,.Lot
#else
bgu .Lot
#endif
cmp %o1,0
bne .Little
nop
retl
nop
.Little:
stb %g0,[%o0]
subcc %o1,1,%o1
bnz .Little
add %o0,1,%o0
retl
nop
.align 32
.Lot:
#ifndef ABI64
subcc %g0,1,%g1
! see above for explanation
.word 0x83408000 !rd %ccr,%g1
cmp %g1,0x99
bne .v8lot
nop
#endif
.v9lot: andcc %o0,7,%g0
bz .v9aligned
nop
stb %g0,[%o0]
sub %o1,1,%o1
ba .v9lot
add %o0,1,%o0
.align 16,0x01000000
.v9aligned:
.word 0xc0720000 !stx %g0,[%o0]
sub %o1,8,%o1
andcc %o1,-8,%g0
#ifdef ABI64
.word 0x126ffffd !bnz %xcc,.v9aligned
#else
.word 0x124ffffd !bnz %icc,.v9aligned
#endif
add %o0,8,%o0
cmp %o1,0
bne .Little
nop
retl
nop
#ifndef ABI64
.v8lot: andcc %o0,3,%g0
bz .v8aligned
nop
stb %g0,[%o0]
sub %o1,1,%o1
ba .v8lot
add %o0,1,%o0
nop
.v8aligned:
st %g0,[%o0]
sub %o1,4,%o1
andcc %o1,-4,%g0
bnz .v8aligned
add %o0,4,%o0
cmp %o1,0
bne .Little
nop
retl
nop
#endif
.type OPENSSL_cleanse,#function
.size OPENSSL_cleanse,.-OPENSSL_cleanse
.global CRYPTO_memcmp
.align 16
CRYPTO_memcmp:
cmp %o2,0
#ifdef ABI64
beq,pn %xcc,.Lno_data
#else
beq .Lno_data
#endif
xor %g1,%g1,%g1
nop
.Loop_cmp:
ldub [%o0],%o3
add %o0,1,%o0
ldub [%o1],%o4
add %o1,1,%o1
subcc %o2,1,%o2
xor %o3,%o4,%o4
#ifdef ABI64
bnz %xcc,.Loop_cmp
#else
bnz .Loop_cmp
#endif
or %o4,%g1,%g1
sub %g0,%g1,%g1
srl %g1,31,%g1
.Lno_data:
retl
mov %g1,%o0
.type CRYPTO_memcmp,#function
.size CRYPTO_memcmp,.-CRYPTO_memcmp
.global _sparcv9_vis1_instrument_bus
.align 8
_sparcv9_vis1_instrument_bus:
mov %o1,%o3 ! save cnt
.word 0x99410000 !rd %tick,%o4 ! tick
mov %o4,%o5 ! lasttick = tick
set 0,%g4 ! diff
andn %o0,63,%g1
.word 0xc1985e00 !ldda [%g1]0xf0,%f0 ! block load
.word 0x8143e040 !membar #Sync
.word 0xc1b85c00 !stda %f0,[%g1]0xe0 ! block store and commit
.word 0x8143e040 !membar #Sync
ld [%o0],%o4
add %o4,%g4,%g4
.word 0xc9e2100c !cas [%o0],%o4,%g4
.Loop: .word 0x99410000 !rd %tick,%o4
sub %o4,%o5,%g4 ! diff=tick-lasttick
mov %o4,%o5 ! lasttick=tick
andn %o0,63,%g1
.word 0xc1985e00 !ldda [%g1]0xf0,%f0 ! block load
.word 0x8143e040 !membar #Sync
.word 0xc1b85c00 !stda %f0,[%g1]0xe0 ! block store and commit
.word 0x8143e040 !membar #Sync
ld [%o0],%o4
add %o4,%g4,%g4
.word 0xc9e2100c !cas [%o0],%o4,%g4
subcc %o1,1,%o1 ! --$cnt
bnz .Loop
add %o0,4,%o0 ! ++$out
retl
mov %o3,%o0
.type _sparcv9_vis1_instrument_bus,#function
.size _sparcv9_vis1_instrument_bus,.-_sparcv9_vis1_instrument_bus
.global _sparcv9_vis1_instrument_bus2
.align 8
_sparcv9_vis1_instrument_bus2:
mov %o1,%o3 ! save cnt
sll %o1,2,%o1 ! cnt*=4
.word 0x99410000 !rd %tick,%o4 ! tick
mov %o4,%o5 ! lasttick = tick
set 0,%g4 ! diff
andn %o0,63,%g1
.word 0xc1985e00 !ldda [%g1]0xf0,%f0 ! block load
.word 0x8143e040 !membar #Sync
.word 0xc1b85c00 !stda %f0,[%g1]0xe0 ! block store and commit
.word 0x8143e040 !membar #Sync
ld [%o0],%o4
add %o4,%g4,%g4
.word 0xc9e2100c !cas [%o0],%o4,%g4
.word 0x99410000 !rd %tick,%o4 ! tick
sub %o4,%o5,%g4 ! diff=tick-lasttick
mov %o4,%o5 ! lasttick=tick
mov %g4,%g5 ! lastdiff=diff
.Loop2:
andn %o0,63,%g1
.word 0xc1985e00 !ldda [%g1]0xf0,%f0 ! block load
.word 0x8143e040 !membar #Sync
.word 0xc1b85c00 !stda %f0,[%g1]0xe0 ! block store and commit
.word 0x8143e040 !membar #Sync
ld [%o0],%o4
add %o4,%g4,%g4
.word 0xc9e2100c !cas [%o0],%o4,%g4
subcc %o2,1,%o2 ! --max
bz .Ldone2
nop
.word 0x99410000 !rd %tick,%o4 ! tick
sub %o4,%o5,%g4 ! diff=tick-lasttick
mov %o4,%o5 ! lasttick=tick
cmp %g4,%g5
mov %g4,%g5 ! lastdiff=diff
.word 0x83408000 !rd %ccr,%g1
and %g1,4,%g1 ! isolate zero flag
xor %g1,4,%g1 ! flip zero flag
subcc %o1,%g1,%o1 ! conditional --$cnt
bnz .Loop2
add %o0,%g1,%o0 ! conditional ++$out
.Ldone2:
srl %o1,2,%o1
retl
sub %o3,%o1,%o0
.type _sparcv9_vis1_instrument_bus2,#function
.size _sparcv9_vis1_instrument_bus2,.-_sparcv9_vis1_instrument_bus2
.section ".init",#alloc,#execinstr
call OPENSSL_cpuid_setup
nop
|
ntu-ssl/rr-artifact | 3,424 | openssl-1.1.0l/crypto/s390xcpuid.S | .text
// Copyright 2009-2016 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under the OpenSSL license (the "License"). You may not use
// this file except in compliance with the License. You can obtain a copy
// in the file LICENSE in the source distribution or at
// https://www.openssl.org/source/license.html
.globl OPENSSL_s390x_facilities
.type OPENSSL_s390x_facilities,@function
.align 16
OPENSSL_s390x_facilities:
lghi %r0,0
larl %r4,OPENSSL_s390xcap_P
stg %r0,8(%r4) # wipe capability vectors
stg %r0,16(%r4)
stg %r0,24(%r4)
stg %r0,32(%r4)
stg %r0,40(%r4)
stg %r0,48(%r4)
stg %r0,56(%r4)
stg %r0,64(%r4)
stg %r0,72(%r4)
.long 0xb2b04000 # stfle 0(%r4)
brc 8,.Ldone
lghi %r0,1
.long 0xb2b04000 # stfle 0(%r4)
.Ldone:
lmg %r2,%r3,0(%r4)
tmhl %r2,0x4000 # check for message-security-assist
jz .Lret
lghi %r0,0 # query kimd capabilities
la %r1,16(%r4)
.long 0xb93e0002 # kimd %r0,%r2
lghi %r0,0 # query km capability vector
la %r1,32(%r4)
.long 0xb92e0042 # km %r4,%r2
lghi %r0,0 # query kmc capability vector
la %r1,48(%r4)
.long 0xb92f0042 # kmc %r4,%r2
tmhh %r3,0x0004 # check for message-security-assist-4
jz .Lret
lghi %r0,0 # query kmctr capability vector
la %r1,64(%r4)
.long 0xb92d2042 # kmctr %r4,%r2,%r2
.Lret:
br %r14
.size OPENSSL_s390x_facilities,.-OPENSSL_s390x_facilities
.globl OPENSSL_rdtsc
.type OPENSSL_rdtsc,@function
.align 16
OPENSSL_rdtsc:
stck 16(%r15)
lg %r2,16(%r15)
br %r14
.size OPENSSL_rdtsc,.-OPENSSL_rdtsc
.globl OPENSSL_atomic_add
.type OPENSSL_atomic_add,@function
.align 16
OPENSSL_atomic_add:
l %r1,0(%r2)
.Lspin: lr %r0,%r1
ar %r0,%r3
cs %r1,%r0,0(%r2)
brc 4,.Lspin
lgfr %r2,%r0 # OpenSSL expects the new value
br %r14
.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
.globl OPENSSL_wipe_cpu
.type OPENSSL_wipe_cpu,@function
.align 16
OPENSSL_wipe_cpu:
xgr %r0,%r0
xgr %r1,%r1
lgr %r2,%r15
xgr %r3,%r3
xgr %r4,%r4
lzdr %f0
lzdr %f1
lzdr %f2
lzdr %f3
lzdr %f4
lzdr %f5
lzdr %f6
lzdr %f7
br %r14
.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
.globl OPENSSL_cleanse
.type OPENSSL_cleanse,@function
.align 16
OPENSSL_cleanse:
#if !defined(__s390x__) && !defined(__s390x)
llgfr %r3,%r3
#endif
lghi %r4,15
lghi %r0,0
clgr %r3,%r4
jh .Lot
clgr %r3,%r0
bcr 8,%r14
.Little:
stc %r0,0(%r2)
la %r2,1(%r2)
brctg %r3,.Little
br %r14
.align 4
.Lot: tmll %r2,7
jz .Laligned
stc %r0,0(%r2)
la %r2,1(%r2)
brctg %r3,.Lot
.Laligned:
srlg %r4,%r3,3
.Loop: stg %r0,0(%r2)
la %r2,8(%r2)
brctg %r4,.Loop
lghi %r4,7
ngr %r3,%r4
jnz .Little
br %r14
.size OPENSSL_cleanse,.-OPENSSL_cleanse
.globl CRYPTO_memcmp
.type CRYPTO_memcmp,@function
.align 16
CRYPTO_memcmp:
#if !defined(__s390x__) && !defined(__s390x)
llgfr %r4,%r4
#endif
lghi %r5,0
clgr %r4,%r5
je .Lno_data
.Loop_cmp:
llgc %r0,0(%r2)
la %r2,1(%r2)
llgc %r1,0(%r3)
la %r3,1(%r3)
xr %r1,%r0
or %r5,%r1
brctg %r4,.Loop_cmp
lnr %r5,%r5
srl %r5,31
.Lno_data:
lgr %r2,%r5
br %r14
.size CRYPTO_memcmp,.-CRYPTO_memcmp
.globl OPENSSL_instrument_bus
.type OPENSSL_instrument_bus,@function
.align 16
OPENSSL_instrument_bus:
lghi %r2,0
br %r14
.size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
.globl OPENSSL_instrument_bus2
.type OPENSSL_instrument_bus2,@function
.align 16
OPENSSL_instrument_bus2:
lghi %r2,0
br %r14
.size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
.section .init
brasl %r14,OPENSSL_cpuid_setup
|
ntu-ssl/rr-artifact | 21,881 | openssl-1.1.0l/crypto/md5/asm/md5-ia64.S | /*
*
* Copyright 2005-2016 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the OpenSSL license (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
/* Copyright (c) 2005 Hewlett-Packard Development Company, L.P.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
// Common registers are assigned as follows:
//
// COMMON
//
// t0 Const Tbl Ptr TPtr
// t1 Round Constant TRound
// t4 Block residual LenResid
// t5 Residual Data DTmp
//
// {in,out}0 Block 0 Cycle RotateM0
// {in,out}1 Block Value 12 M12
// {in,out}2 Block Value 8 M8
// {in,out}3 Block Value 4 M4
// {in,out}4 Block Value 0 M0
// {in,out}5 Block 1 Cycle RotateM1
// {in,out}6 Block Value 13 M13
// {in,out}7 Block Value 9 M9
// {in,out}8 Block Value 5 M5
// {in,out}9 Block Value 1 M1
// {in,out}10 Block 2 Cycle RotateM2
// {in,out}11 Block Value 14 M14
// {in,out}12 Block Value 10 M10
// {in,out}13 Block Value 6 M6
// {in,out}14 Block Value 2 M2
// {in,out}15 Block 3 Cycle RotateM3
// {in,out}16 Block Value 15 M15
// {in,out}17 Block Value 11 M11
// {in,out}18 Block Value 7 M7
// {in,out}19 Block Value 3 M3
// {in,out}20 Scratch Z
// {in,out}21 Scratch Y
// {in,out}22 Scratch X
// {in,out}23 Scratch W
// {in,out}24 Digest A A
// {in,out}25 Digest B B
// {in,out}26 Digest C C
// {in,out}27 Digest D D
// {in,out}28 Active Data Ptr DPtr
// in28 Dummy Value -
// out28 Dummy Value -
// bt0 Coroutine Link QUICK_RTN
//
/// These predicates are used for computing the padding block(s) and
/// are shared between the driver and digest co-routines
//
// pt0 Extra Pad Block pExtra
// pt1 Load next word pLoad
// pt2 Skip next word pSkip
// pt3 Search for Pad pNoPad
// pt4 Pad Word 0 pPad0
// pt5 Pad Word 1 pPad1
// pt6 Pad Word 2 pPad2
// pt7 Pad Word 3 pPad3
#define DTmp r19
#define LenResid r18
#define QUICK_RTN b6
#define TPtr r14
#define TRound r15
#define pExtra p6
#define pLoad p7
#define pNoPad p9
#define pPad0 p10
#define pPad1 p11
#define pPad2 p12
#define pPad3 p13
#define pSkip p8
#define A_ out24
#define B_ out25
#define C_ out26
#define D_ out27
#define DPtr_ out28
#define M0_ out4
#define M1_ out9
#define M10_ out12
#define M11_ out17
#define M12_ out1
#define M13_ out6
#define M14_ out11
#define M15_ out16
#define M2_ out14
#define M3_ out19
#define M4_ out3
#define M5_ out8
#define M6_ out13
#define M7_ out18
#define M8_ out2
#define M9_ out7
#define RotateM0_ out0
#define RotateM1_ out5
#define RotateM2_ out10
#define RotateM3_ out15
#define W_ out23
#define X_ out22
#define Y_ out21
#define Z_ out20
#define A in24
#define B in25
#define C in26
#define D in27
#define DPtr in28
#define M0 in4
#define M1 in9
#define M10 in12
#define M11 in17
#define M12 in1
#define M13 in6
#define M14 in11
#define M15 in16
#define M2 in14
#define M3 in19
#define M4 in3
#define M5 in8
#define M6 in13
#define M7 in18
#define M8 in2
#define M9 in7
#define RotateM0 in0
#define RotateM1 in5
#define RotateM2 in10
#define RotateM3 in15
#define W in23
#define X in22
#define Y in21
#define Z in20
/* register stack configuration for md5_block_asm_data_order(): */
#define MD5_NINP 3
#define MD5_NLOC 0
#define MD5_NOUT 29
#define MD5_NROT 0
/* register stack configuration for helpers: */
#define _NINPUTS MD5_NOUT
#define _NLOCALS 0
#define _NOUTPUT 0
#define _NROTATE 24 /* this must be <= _NINPUTS */
#if defined(_HPUX_SOURCE) && !defined(_LP64)
#define ADDP addp4
#else
#define ADDP add
#endif
#if defined(_HPUX_SOURCE) || defined(B_ENDIAN)
#define HOST_IS_BIG_ENDIAN
#endif
// Macros for getting the left and right portions of little-endian words
#define GETLW(dst, src, align) dep.z dst = src, 32 - 8 * align, 8 * align
#define GETRW(dst, src, align) extr.u dst = src, 8 * align, 32 - 8 * align
// MD5 driver
//
// Reads an input block, then calls the digest block
// subroutine and adds the results to the accumulated
// digest. It allocates 32 outs which the subroutine
// uses as it's inputs and rotating
// registers. Initializes the round constant pointer and
// takes care of saving/restoring ar.lc
//
/// INPUT
//
// in0 Context Ptr CtxPtr0
// in1 Input Data Ptr DPtrIn
// in2 Integral Blocks BlockCount
// rp Return Address -
//
/// CODE
//
// v2 Input Align InAlign
// t0 Shared w/digest -
// t1 Shared w/digest -
// t2 Shared w/digest -
// t3 Shared w/digest -
// t4 Shared w/digest -
// t5 Shared w/digest -
// t6 PFS Save PFSSave
// t7 ar.lc Save LCSave
// t8 Saved PR PRSave
// t9 2nd CtxPtr CtxPtr1
// t10 Table Base CTable
// t11 Table[0] CTable0
// t13 Accumulator A AccumA
// t14 Accumulator B AccumB
// t15 Accumulator C AccumC
// t16 Accumulator D AccumD
// pt0 Shared w/digest -
// pt1 Shared w/digest -
// pt2 Shared w/digest -
// pt3 Shared w/digest -
// pt4 Shared w/digest -
// pt5 Shared w/digest -
// pt6 Shared w/digest -
// pt7 Shared w/digest -
// pt8 Not Aligned pOff
// pt8 Blocks Left pAgain
#define AccumA r27
#define AccumB r28
#define AccumC r29
#define AccumD r30
#define CTable r24
#define CTable0 r25
#define CtxPtr0 in0
#define CtxPtr1 r23
#define DPtrIn in1
#define BlockCount in2
#define InAlign r10
#define LCSave r21
#define PFSSave r20
#define PRSave r22
#define pAgain p63
#define pOff p63
.text
/* md5_block_asm_data_order(MD5_CTX *c, const void *data, size_t num)
where:
c: a pointer to a structure of this type:
typedef struct MD5state_st
{
MD5_LONG A,B,C,D;
MD5_LONG Nl,Nh;
MD5_LONG data[MD5_LBLOCK];
unsigned int num;
}
MD5_CTX;
data: a pointer to the input data (may be misaligned)
num: the number of 16-byte blocks to hash (i.e., the length
of DATA is 16*NUM.
*/
.type md5_block_asm_data_order, @function
.global md5_block_asm_data_order
.align 32
.proc md5_block_asm_data_order
md5_block_asm_data_order:
.md5_block:
.prologue
{ .mmi
.save ar.pfs, PFSSave
alloc PFSSave = ar.pfs, MD5_NINP, MD5_NLOC, MD5_NOUT, MD5_NROT
ADDP CtxPtr1 = 8, CtxPtr0
mov CTable = ip
}
{ .mmi
ADDP DPtrIn = 0, DPtrIn
ADDP CtxPtr0 = 0, CtxPtr0
.save ar.lc, LCSave
mov LCSave = ar.lc
}
;;
{ .mmi
add CTable = .md5_tbl_data_order#-.md5_block#, CTable
and InAlign = 0x3, DPtrIn
}
{ .mmi
ld4 AccumA = [CtxPtr0], 4
ld4 AccumC = [CtxPtr1], 4
.save pr, PRSave
mov PRSave = pr
.body
}
;;
{ .mmi
ld4 AccumB = [CtxPtr0]
ld4 AccumD = [CtxPtr1]
dep DPtr_ = 0, DPtrIn, 0, 2
} ;;
#ifdef HOST_IS_BIG_ENDIAN
rum psr.be;; // switch to little-endian
#endif
{ .mmb
ld4 CTable0 = [CTable], 4
cmp.ne pOff, p0 = 0, InAlign
(pOff) br.cond.spnt.many .md5_unaligned
} ;;
// The FF load/compute loop rotates values three times, so that
// loading into M12 here produces the M0 value, M13 -> M1, etc.
.md5_block_loop0:
{ .mmi
ld4 M12_ = [DPtr_], 4
mov TPtr = CTable
mov TRound = CTable0
} ;;
{ .mmi
ld4 M13_ = [DPtr_], 4
mov A_ = AccumA
mov B_ = AccumB
} ;;
{ .mmi
ld4 M14_ = [DPtr_], 4
mov C_ = AccumC
mov D_ = AccumD
} ;;
{ .mmb
ld4 M15_ = [DPtr_], 4
add BlockCount = -1, BlockCount
br.call.sptk.many QUICK_RTN = md5_digest_block0
} ;;
// Now, we add the new digest values and do some clean-up
// before checking if there's another full block to process
{ .mmi
add AccumA = AccumA, A_
add AccumB = AccumB, B_
cmp.ne pAgain, p0 = 0, BlockCount
}
{ .mib
add AccumC = AccumC, C_
add AccumD = AccumD, D_
(pAgain) br.cond.dptk.many .md5_block_loop0
} ;;
.md5_exit:
#ifdef HOST_IS_BIG_ENDIAN
sum psr.be;; // switch back to big-endian mode
#endif
{ .mmi
st4 [CtxPtr0] = AccumB, -4
st4 [CtxPtr1] = AccumD, -4
mov pr = PRSave, 0x1ffff ;;
}
{ .mmi
st4 [CtxPtr0] = AccumA
st4 [CtxPtr1] = AccumC
mov ar.lc = LCSave
} ;;
{ .mib
mov ar.pfs = PFSSave
br.ret.sptk.few rp
} ;;
#define MD5UNALIGNED(offset) \
.md5_process##offset: \
{ .mib ; \
nop 0x0 ; \
GETRW(DTmp, DTmp, offset) ; \
} ;; \
.md5_block_loop##offset: \
{ .mmi ; \
ld4 Y_ = [DPtr_], 4 ; \
mov TPtr = CTable ; \
mov TRound = CTable0 ; \
} ;; \
{ .mmi ; \
ld4 M13_ = [DPtr_], 4 ; \
mov A_ = AccumA ; \
mov B_ = AccumB ; \
} ;; \
{ .mii ; \
ld4 M14_ = [DPtr_], 4 ; \
GETLW(W_, Y_, offset) ; \
mov C_ = AccumC ; \
} \
{ .mmi ; \
mov D_ = AccumD ;; \
or M12_ = W_, DTmp ; \
GETRW(DTmp, Y_, offset) ; \
} \
{ .mib ; \
ld4 M15_ = [DPtr_], 4 ; \
add BlockCount = -1, BlockCount ; \
br.call.sptk.many QUICK_RTN = md5_digest_block##offset; \
} ;; \
{ .mmi ; \
add AccumA = AccumA, A_ ; \
add AccumB = AccumB, B_ ; \
cmp.ne pAgain, p0 = 0, BlockCount ; \
} \
{ .mib ; \
add AccumC = AccumC, C_ ; \
add AccumD = AccumD, D_ ; \
(pAgain) br.cond.dptk.many .md5_block_loop##offset ; \
} ;; \
{ .mib ; \
nop 0x0 ; \
nop 0x0 ; \
br.cond.sptk.many .md5_exit ; \
} ;;
.align 32
.md5_unaligned:
//
// Because variable shifts are expensive, we special case each of
// the four alignements. In practice, this won't hurt too much
// since only one working set of code will be loaded.
//
{ .mib
ld4 DTmp = [DPtr_], 4
cmp.eq pOff, p0 = 1, InAlign
(pOff) br.cond.dpnt.many .md5_process1
} ;;
{ .mib
cmp.eq pOff, p0 = 2, InAlign
nop 0x0
(pOff) br.cond.dpnt.many .md5_process2
} ;;
MD5UNALIGNED(3)
MD5UNALIGNED(1)
MD5UNALIGNED(2)
.endp md5_block_asm_data_order
// MD5 Perform the F function and load
//
// Passed the first 4 words (M0 - M3) and initial (A, B, C, D) values,
// computes the FF() round of functions, then branches to the common
// digest code to finish up with GG(), HH, and II().
//
// INPUT
//
// rp Return Address -
//
// CODE
//
// v0 PFS bit bucket PFS
// v1 Loop Trip Count LTrip
// pt0 Load next word pMore
/* For F round: */
#define LTrip r9
#define PFS r8
#define pMore p6
/* For GHI rounds: */
#define T r9
#define U r10
#define V r11
#define COMPUTE(a, b, s, M, R) \
{ \
.mii ; \
ld4 TRound = [TPtr], 4 ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ \
.mmi ; \
add a = Z, b ; \
mov R = M ; \
nop 0x0 ; \
} ;;
#define LOOP(a, b, s, M, R, label) \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ .mib ; \
add a = Z, b ; \
mov R = M ; \
br.ctop.sptk.many label ; \
} ;;
// G(B, C, D) = (B & D) | (C & ~D)
#define G(a, b, c, d, M) \
{ .mmi ; \
add Z = M, TRound ; \
and Y = b, d ; \
andcm X = c, d ; \
} ;; \
{ .mii ; \
add Z = Z, a ; \
or Y = Y, X ;; \
add Z = Z, Y ; \
} ;;
// H(B, C, D) = B ^ C ^ D
#define H(a, b, c, d, M) \
{ .mmi ; \
add Z = M, TRound ; \
xor Y = b, c ; \
nop 0x0 ; \
} ;; \
{ .mii ; \
add Z = Z, a ; \
xor Y = Y, d ;; \
add Z = Z, Y ; \
} ;;
// I(B, C, D) = C ^ (B | ~D)
//
// However, since we have an andcm operator, we use the fact that
//
// Y ^ Z == ~Y ^ ~Z
//
// to rewrite the expression as
//
// I(B, C, D) = ~C ^ (~B & D)
#define I(a, b, c, d, M) \
{ .mmi ; \
add Z = M, TRound ; \
andcm Y = d, b ; \
andcm X = -1, c ; \
} ;; \
{ .mii ; \
add Z = Z, a ; \
xor Y = Y, X ;; \
add Z = Z, Y ; \
} ;;
#define GG4(label) \
G(A, B, C, D, M0) \
COMPUTE(A, B, 5, M0, RotateM0) \
G(D, A, B, C, M1) \
COMPUTE(D, A, 9, M1, RotateM1) \
G(C, D, A, B, M2) \
COMPUTE(C, D, 14, M2, RotateM2) \
G(B, C, D, A, M3) \
LOOP(B, C, 20, M3, RotateM3, label)
#define HH4(label) \
H(A, B, C, D, M0) \
COMPUTE(A, B, 4, M0, RotateM0) \
H(D, A, B, C, M1) \
COMPUTE(D, A, 11, M1, RotateM1) \
H(C, D, A, B, M2) \
COMPUTE(C, D, 16, M2, RotateM2) \
H(B, C, D, A, M3) \
LOOP(B, C, 23, M3, RotateM3, label)
#define II4(label) \
I(A, B, C, D, M0) \
COMPUTE(A, B, 6, M0, RotateM0) \
I(D, A, B, C, M1) \
COMPUTE(D, A, 10, M1, RotateM1) \
I(C, D, A, B, M2) \
COMPUTE(C, D, 15, M2, RotateM2) \
I(B, C, D, A, M3) \
LOOP(B, C, 21, M3, RotateM3, label)
#define FFLOAD(a, b, c, d, M, N, s) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
add Z = Z, Y ;; \
dep.z Y = Z, 32, 32 ; \
} ;; \
{ .mii ; \
nop 0x0 ; \
shrp Z = Z, Y, 64 - s ;; \
add a = Z, b ; \
} ;;
#define FFLOOP(a, b, c, d, M, N, s, dest) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
add Z = Z, Y ;; \
dep.z Y = Z, 32, 32 ; \
} ;; \
{ .mii ; \
nop 0x0 ; \
shrp Z = Z, Y, 64 - s ;; \
add a = Z, b ; \
} \
{ .mib ; \
cmp.ne pMore, p0 = 0, LTrip ; \
add LTrip = -1, LTrip ; \
br.ctop.dptk.many dest ; \
} ;;
.type md5_digest_block0, @function
.align 32
.proc md5_digest_block0
.prologue
md5_digest_block0:
.altrp QUICK_RTN
.body
{ .mmi
alloc PFS = ar.pfs, _NINPUTS, _NLOCALS, _NOUTPUT, _NROTATE
mov LTrip = 2
mov ar.lc = 3
} ;;
{ .mii
cmp.eq pMore, p0 = r0, r0
mov ar.ec = 0
nop 0x0
} ;;
.md5_FF_round0:
FFLOAD(A, B, C, D, M12, RotateM0, 7)
FFLOAD(D, A, B, C, M13, RotateM1, 12)
FFLOAD(C, D, A, B, M14, RotateM2, 17)
FFLOOP(B, C, D, A, M15, RotateM3, 22, .md5_FF_round0)
//
// !!! Fall through to md5_digest_GHI
//
.endp md5_digest_block0
.type md5_digest_GHI, @function
.align 32
.proc md5_digest_GHI
.prologue
.regstk _NINPUTS, _NLOCALS, _NOUTPUT, _NROTATE
md5_digest_GHI:
.altrp QUICK_RTN
.body
//
// The following sequence shuffles the block counstants round for the
// next round:
//
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
// 1 6 11 0 5 10 14 4 9 14 3 8 13 2 7 12
//
{ .mmi
mov Z = M0
mov Y = M15
mov ar.lc = 3
}
{ .mmi
mov X = M2
mov W = M9
mov V = M4
} ;;
{ .mmi
mov M0 = M1
mov M15 = M12
mov ar.ec = 1
}
{ .mmi
mov M2 = M11
mov M9 = M14
mov M4 = M5
} ;;
{ .mmi
mov M1 = M6
mov M12 = M13
mov U = M3
}
{ .mmi
mov M11 = M8
mov M14 = M7
mov M5 = M10
} ;;
{ .mmi
mov M6 = Y
mov M13 = X
mov M3 = Z
}
{ .mmi
mov M8 = W
mov M7 = V
mov M10 = U
} ;;
.md5_GG_round:
GG4(.md5_GG_round)
// The following sequence shuffles the block constants round for the
// next round:
//
// 1 6 11 0 5 10 14 4 9 14 3 8 13 2 7 12
// 5 8 11 14 1 4 7 10 13 0 3 6 9 12 15 2
{ .mmi
mov Z = M0
mov Y = M1
mov ar.lc = 3
}
{ .mmi
mov X = M3
mov W = M5
mov V = M6
} ;;
{ .mmi
mov M0 = M4
mov M1 = M11
mov ar.ec = 1
}
{ .mmi
mov M3 = M9
mov U = M8
mov T = M13
} ;;
{ .mmi
mov M4 = Z
mov M11 = Y
mov M5 = M7
}
{ .mmi
mov M6 = M14
mov M8 = M12
mov M13 = M15
} ;;
{ .mmi
mov M7 = W
mov M14 = V
nop 0x0
}
{ .mmi
mov M9 = X
mov M12 = U
mov M15 = T
} ;;
.md5_HH_round:
HH4(.md5_HH_round)
// The following sequence shuffles the block constants round for the
// next round:
//
// 5 8 11 14 1 4 7 10 13 0 3 6 9 12 15 2
// 0 7 14 5 12 3 10 1 8 15 6 13 4 11 2 9
{ .mmi
mov Z = M0
mov Y = M15
mov ar.lc = 3
}
{ .mmi
mov X = M10
mov W = M1
mov V = M4
} ;;
{ .mmi
mov M0 = M9
mov M15 = M12
mov ar.ec = 1
}
{ .mmi
mov M10 = M11
mov M1 = M6
mov M4 = M13
} ;;
{ .mmi
mov M9 = M14
mov M12 = M5
mov U = M3
}
{ .mmi
mov M11 = M8
mov M6 = M7
mov M13 = M2
} ;;
{ .mmi
mov M14 = Y
mov M5 = X
mov M3 = Z
}
{ .mmi
mov M8 = W
mov M7 = V
mov M2 = U
} ;;
.md5_II_round:
II4(.md5_II_round)
{ .mib
nop 0x0
nop 0x0
br.ret.sptk.many QUICK_RTN
} ;;
.endp md5_digest_GHI
#define FFLOADU(a, b, c, d, M, P, N, s, offset) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
GETLW(W, P, offset) ; \
add Z = Z, Y ; \
} ;; \
{ .mii ; \
or W = W, DTmp ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ .mii ; \
add a = Z, b ; \
GETRW(DTmp, P, offset) ; \
mov P = W ; \
} ;;
#define FFLOOPU(a, b, c, d, M, P, N, s, offset) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
(pMore) GETLW(W, P, offset) ; \
add Z = Z, Y ; \
} ;; \
{ .mii ; \
(pMore) or W = W, DTmp ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ .mii ; \
add a = Z, b ; \
(pMore) GETRW(DTmp, P, offset) ; \
(pMore) mov P = W ; \
} \
{ .mib ; \
cmp.ne pMore, p0 = 0, LTrip ; \
add LTrip = -1, LTrip ; \
br.ctop.sptk.many .md5_FF_round##offset ; \
} ;;
#define MD5FBLOCK(offset) \
.type md5_digest_block##offset, @function ; \
\
.align 32 ; \
.proc md5_digest_block##offset ; \
.prologue ; \
.altrp QUICK_RTN ; \
.body ; \
md5_digest_block##offset: \
{ .mmi ; \
alloc PFS = ar.pfs, _NINPUTS, _NLOCALS, _NOUTPUT, _NROTATE ; \
mov LTrip = 2 ; \
mov ar.lc = 3 ; \
} ;; \
{ .mii ; \
cmp.eq pMore, p0 = r0, r0 ; \
mov ar.ec = 0 ; \
nop 0x0 ; \
} ;; \
\
.pred.rel "mutex", pLoad, pSkip ; \
.md5_FF_round##offset: \
FFLOADU(A, B, C, D, M12, M13, RotateM0, 7, offset) \
FFLOADU(D, A, B, C, M13, M14, RotateM1, 12, offset) \
FFLOADU(C, D, A, B, M14, M15, RotateM2, 17, offset) \
FFLOOPU(B, C, D, A, M15, RotateM0, RotateM3, 22, offset) \
\
{ .mib ; \
nop 0x0 ; \
nop 0x0 ; \
br.cond.sptk.many md5_digest_GHI ; \
} ;; \
.endp md5_digest_block##offset
MD5FBLOCK(1)
MD5FBLOCK(2)
MD5FBLOCK(3)
.align 64
.type md5_constants, @object
md5_constants:
.md5_tbl_data_order: // To ensure little-endian data
// order, code as bytes.
data1 0x78, 0xa4, 0x6a, 0xd7 // 0
data1 0x56, 0xb7, 0xc7, 0xe8 // 1
data1 0xdb, 0x70, 0x20, 0x24 // 2
data1 0xee, 0xce, 0xbd, 0xc1 // 3
data1 0xaf, 0x0f, 0x7c, 0xf5 // 4
data1 0x2a, 0xc6, 0x87, 0x47 // 5
data1 0x13, 0x46, 0x30, 0xa8 // 6
data1 0x01, 0x95, 0x46, 0xfd // 7
data1 0xd8, 0x98, 0x80, 0x69 // 8
data1 0xaf, 0xf7, 0x44, 0x8b // 9
data1 0xb1, 0x5b, 0xff, 0xff // 10
data1 0xbe, 0xd7, 0x5c, 0x89 // 11
data1 0x22, 0x11, 0x90, 0x6b // 12
data1 0x93, 0x71, 0x98, 0xfd // 13
data1 0x8e, 0x43, 0x79, 0xa6 // 14
data1 0x21, 0x08, 0xb4, 0x49 // 15
data1 0x62, 0x25, 0x1e, 0xf6 // 16
data1 0x40, 0xb3, 0x40, 0xc0 // 17
data1 0x51, 0x5a, 0x5e, 0x26 // 18
data1 0xaa, 0xc7, 0xb6, 0xe9 // 19
data1 0x5d, 0x10, 0x2f, 0xd6 // 20
data1 0x53, 0x14, 0x44, 0x02 // 21
data1 0x81, 0xe6, 0xa1, 0xd8 // 22
data1 0xc8, 0xfb, 0xd3, 0xe7 // 23
data1 0xe6, 0xcd, 0xe1, 0x21 // 24
data1 0xd6, 0x07, 0x37, 0xc3 // 25
data1 0x87, 0x0d, 0xd5, 0xf4 // 26
data1 0xed, 0x14, 0x5a, 0x45 // 27
data1 0x05, 0xe9, 0xe3, 0xa9 // 28
data1 0xf8, 0xa3, 0xef, 0xfc // 29
data1 0xd9, 0x02, 0x6f, 0x67 // 30
data1 0x8a, 0x4c, 0x2a, 0x8d // 31
data1 0x42, 0x39, 0xfa, 0xff // 32
data1 0x81, 0xf6, 0x71, 0x87 // 33
data1 0x22, 0x61, 0x9d, 0x6d // 34
data1 0x0c, 0x38, 0xe5, 0xfd // 35
data1 0x44, 0xea, 0xbe, 0xa4 // 36
data1 0xa9, 0xcf, 0xde, 0x4b // 37
data1 0x60, 0x4b, 0xbb, 0xf6 // 38
data1 0x70, 0xbc, 0xbf, 0xbe // 39
data1 0xc6, 0x7e, 0x9b, 0x28 // 40
data1 0xfa, 0x27, 0xa1, 0xea // 41
data1 0x85, 0x30, 0xef, 0xd4 // 42
data1 0x05, 0x1d, 0x88, 0x04 // 43
data1 0x39, 0xd0, 0xd4, 0xd9 // 44
data1 0xe5, 0x99, 0xdb, 0xe6 // 45
data1 0xf8, 0x7c, 0xa2, 0x1f // 46
data1 0x65, 0x56, 0xac, 0xc4 // 47
data1 0x44, 0x22, 0x29, 0xf4 // 48
data1 0x97, 0xff, 0x2a, 0x43 // 49
data1 0xa7, 0x23, 0x94, 0xab // 50
data1 0x39, 0xa0, 0x93, 0xfc // 51
data1 0xc3, 0x59, 0x5b, 0x65 // 52
data1 0x92, 0xcc, 0x0c, 0x8f // 53
data1 0x7d, 0xf4, 0xef, 0xff // 54
data1 0xd1, 0x5d, 0x84, 0x85 // 55
data1 0x4f, 0x7e, 0xa8, 0x6f // 56
data1 0xe0, 0xe6, 0x2c, 0xfe // 57
data1 0x14, 0x43, 0x01, 0xa3 // 58
data1 0xa1, 0x11, 0x08, 0x4e // 59
data1 0x82, 0x7e, 0x53, 0xf7 // 60
data1 0x35, 0xf2, 0x3a, 0xbd // 61
data1 0xbb, 0xd2, 0xd7, 0x2a // 62
data1 0x91, 0xd3, 0x86, 0xeb // 63
.size md5_constants#,64*4
|
ntu-ssl/rr-artifact | 28,335 | openssl-1.1.0l/crypto/bn/asm/sparcv8.S | .ident "sparcv8.s, Version 1.4"
.ident "SPARC v8 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
/*
* ====================================================================
* Copyright 1999-2016 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the OpenSSL license (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
* ====================================================================
*/
/*
* This is my modest contributon to OpenSSL project (see
* http://www.openssl.org/ for more information about it) and is
* a drop-in SuperSPARC ISA replacement for crypto/bn/bn_asm.c
* module. For updates see http://fy.chalmers.se/~appro/hpe/.
*
* See bn_asm.sparc.v8plus.S for more details.
*/
/*
* Revision history.
*
* 1.1 - new loop unrolling model(*);
* 1.2 - made gas friendly;
* 1.3 - fixed problem with /usr/ccs/lib/cpp;
* 1.4 - some retunes;
*
* (*) see bn_asm.sparc.v8plus.S for details
*/
.section ".text",#alloc,#execinstr
.file "bn_asm.sparc.v8.S"
.align 32
.global bn_mul_add_words
/*
* BN_ULONG bn_mul_add_words(rp,ap,num,w)
* BN_ULONG *rp,*ap;
* int num;
* BN_ULONG w;
*/
bn_mul_add_words:
cmp %o2,0
bg,a .L_bn_mul_add_words_proceed
ld [%o1],%g2
retl
clr %o0
.L_bn_mul_add_words_proceed:
andcc %o2,-4,%g0
bz .L_bn_mul_add_words_tail
clr %o5
.L_bn_mul_add_words_loop:
ld [%o0],%o4
ld [%o1+4],%g3
umul %o3,%g2,%g2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
st %o4,[%o0]
addx %g1,0,%o5
ld [%o0+4],%o4
ld [%o1+8],%g2
umul %o3,%g3,%g3
dec 4,%o2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g3,%o4
st %o4,[%o0+4]
addx %g1,0,%o5
ld [%o0+8],%o4
ld [%o1+12],%g3
umul %o3,%g2,%g2
inc 16,%o1
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
st %o4,[%o0+8]
addx %g1,0,%o5
ld [%o0+12],%o4
umul %o3,%g3,%g3
inc 16,%o0
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g3,%o4
st %o4,[%o0-4]
addx %g1,0,%o5
andcc %o2,-4,%g0
bnz,a .L_bn_mul_add_words_loop
ld [%o1],%g2
tst %o2
bnz,a .L_bn_mul_add_words_tail
ld [%o1],%g2
.L_bn_mul_add_words_return:
retl
mov %o5,%o0
nop
.L_bn_mul_add_words_tail:
ld [%o0],%o4
umul %o3,%g2,%g2
addcc %o4,%o5,%o4
rd %y,%g1
addx %g1,0,%g1
addcc %o4,%g2,%o4
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_add_words_return
st %o4,[%o0]
ld [%o1+4],%g2
ld [%o0+4],%o4
umul %o3,%g2,%g2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_add_words_return
st %o4,[%o0+4]
ld [%o1+8],%g2
ld [%o0+8],%o4
umul %o3,%g2,%g2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
st %o4,[%o0+8]
retl
addx %g1,0,%o0
.type bn_mul_add_words,#function
.size bn_mul_add_words,(.-bn_mul_add_words)
.align 32
.global bn_mul_words
/*
* BN_ULONG bn_mul_words(rp,ap,num,w)
* BN_ULONG *rp,*ap;
* int num;
* BN_ULONG w;
*/
bn_mul_words:
cmp %o2,0
bg,a .L_bn_mul_words_proceeed
ld [%o1],%g2
retl
clr %o0
.L_bn_mul_words_proceeed:
andcc %o2,-4,%g0
bz .L_bn_mul_words_tail
clr %o5
.L_bn_mul_words_loop:
ld [%o1+4],%g3
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
addx %g1,0,%o5
st %g2,[%o0]
ld [%o1+8],%g2
umul %o3,%g3,%g3
addcc %g3,%o5,%g3
rd %y,%g1
dec 4,%o2
addx %g1,0,%o5
st %g3,[%o0+4]
ld [%o1+12],%g3
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
inc 16,%o1
st %g2,[%o0+8]
addx %g1,0,%o5
umul %o3,%g3,%g3
addcc %g3,%o5,%g3
rd %y,%g1
inc 16,%o0
addx %g1,0,%o5
st %g3,[%o0-4]
andcc %o2,-4,%g0
nop
bnz,a .L_bn_mul_words_loop
ld [%o1],%g2
tst %o2
bnz,a .L_bn_mul_words_tail
ld [%o1],%g2
.L_bn_mul_words_return:
retl
mov %o5,%o0
nop
.L_bn_mul_words_tail:
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_words_return
st %g2,[%o0]
nop
ld [%o1+4],%g2
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_words_return
st %g2,[%o0+4]
ld [%o1+8],%g2
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
st %g2,[%o0+8]
retl
addx %g1,0,%o0
.type bn_mul_words,#function
.size bn_mul_words,(.-bn_mul_words)
.align 32
.global bn_sqr_words
/*
* void bn_sqr_words(r,a,n)
* BN_ULONG *r,*a;
* int n;
*/
bn_sqr_words:
cmp %o2,0
bg,a .L_bn_sqr_words_proceeed
ld [%o1],%g2
retl
clr %o0
.L_bn_sqr_words_proceeed:
andcc %o2,-4,%g0
bz .L_bn_sqr_words_tail
clr %o5
.L_bn_sqr_words_loop:
ld [%o1+4],%g3
umul %g2,%g2,%o4
st %o4,[%o0]
rd %y,%o5
st %o5,[%o0+4]
ld [%o1+8],%g2
umul %g3,%g3,%o4
dec 4,%o2
st %o4,[%o0+8]
rd %y,%o5
st %o5,[%o0+12]
nop
ld [%o1+12],%g3
umul %g2,%g2,%o4
st %o4,[%o0+16]
rd %y,%o5
inc 16,%o1
st %o5,[%o0+20]
umul %g3,%g3,%o4
inc 32,%o0
st %o4,[%o0-8]
rd %y,%o5
st %o5,[%o0-4]
andcc %o2,-4,%g2
bnz,a .L_bn_sqr_words_loop
ld [%o1],%g2
tst %o2
nop
bnz,a .L_bn_sqr_words_tail
ld [%o1],%g2
.L_bn_sqr_words_return:
retl
clr %o0
.L_bn_sqr_words_tail:
umul %g2,%g2,%o4
st %o4,[%o0]
deccc %o2
rd %y,%o5
bz .L_bn_sqr_words_return
st %o5,[%o0+4]
ld [%o1+4],%g2
umul %g2,%g2,%o4
st %o4,[%o0+8]
deccc %o2
rd %y,%o5
nop
bz .L_bn_sqr_words_return
st %o5,[%o0+12]
ld [%o1+8],%g2
umul %g2,%g2,%o4
st %o4,[%o0+16]
rd %y,%o5
st %o5,[%o0+20]
retl
clr %o0
.type bn_sqr_words,#function
.size bn_sqr_words,(.-bn_sqr_words)
.align 32
.global bn_div_words
/*
* BN_ULONG bn_div_words(h,l,d)
* BN_ULONG h,l,d;
*/
bn_div_words:
wr %o0,%y
udiv %o1,%o2,%o0
retl
nop
.type bn_div_words,#function
.size bn_div_words,(.-bn_div_words)
.align 32
.global bn_add_words
/*
* BN_ULONG bn_add_words(rp,ap,bp,n)
* BN_ULONG *rp,*ap,*bp;
* int n;
*/
bn_add_words:
cmp %o3,0
bg,a .L_bn_add_words_proceed
ld [%o1],%o4
retl
clr %o0
.L_bn_add_words_proceed:
andcc %o3,-4,%g0
bz .L_bn_add_words_tail
clr %g1
ba .L_bn_add_words_warn_loop
addcc %g0,0,%g0 ! clear carry flag
.L_bn_add_words_loop:
ld [%o1],%o4
.L_bn_add_words_warn_loop:
ld [%o2],%o5
ld [%o1+4],%g3
ld [%o2+4],%g4
dec 4,%o3
addxcc %o5,%o4,%o5
st %o5,[%o0]
ld [%o1+8],%o4
ld [%o2+8],%o5
inc 16,%o1
addxcc %g3,%g4,%g3
st %g3,[%o0+4]
ld [%o1-4],%g3
ld [%o2+12],%g4
inc 16,%o2
addxcc %o5,%o4,%o5
st %o5,[%o0+8]
inc 16,%o0
addxcc %g3,%g4,%g3
st %g3,[%o0-4]
addx %g0,0,%g1
andcc %o3,-4,%g0
bnz,a .L_bn_add_words_loop
addcc %g1,-1,%g0
tst %o3
bnz,a .L_bn_add_words_tail
ld [%o1],%o4
.L_bn_add_words_return:
retl
mov %g1,%o0
.L_bn_add_words_tail:
addcc %g1,-1,%g0
ld [%o2],%o5
addxcc %o5,%o4,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_add_words_return
st %o5,[%o0]
ld [%o1+4],%o4
addcc %g1,-1,%g0
ld [%o2+4],%o5
addxcc %o5,%o4,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_add_words_return
st %o5,[%o0+4]
ld [%o1+8],%o4
addcc %g1,-1,%g0
ld [%o2+8],%o5
addxcc %o5,%o4,%o5
st %o5,[%o0+8]
retl
addx %g0,0,%o0
.type bn_add_words,#function
.size bn_add_words,(.-bn_add_words)
.align 32
.global bn_sub_words
/*
* BN_ULONG bn_sub_words(rp,ap,bp,n)
* BN_ULONG *rp,*ap,*bp;
* int n;
*/
bn_sub_words:
cmp %o3,0
bg,a .L_bn_sub_words_proceed
ld [%o1],%o4
retl
clr %o0
.L_bn_sub_words_proceed:
andcc %o3,-4,%g0
bz .L_bn_sub_words_tail
clr %g1
ba .L_bn_sub_words_warm_loop
addcc %g0,0,%g0 ! clear carry flag
.L_bn_sub_words_loop:
ld [%o1],%o4
.L_bn_sub_words_warm_loop:
ld [%o2],%o5
ld [%o1+4],%g3
ld [%o2+4],%g4
dec 4,%o3
subxcc %o4,%o5,%o5
st %o5,[%o0]
ld [%o1+8],%o4
ld [%o2+8],%o5
inc 16,%o1
subxcc %g3,%g4,%g4
st %g4,[%o0+4]
ld [%o1-4],%g3
ld [%o2+12],%g4
inc 16,%o2
subxcc %o4,%o5,%o5
st %o5,[%o0+8]
inc 16,%o0
subxcc %g3,%g4,%g4
st %g4,[%o0-4]
addx %g0,0,%g1
andcc %o3,-4,%g0
bnz,a .L_bn_sub_words_loop
addcc %g1,-1,%g0
tst %o3
nop
bnz,a .L_bn_sub_words_tail
ld [%o1],%o4
.L_bn_sub_words_return:
retl
mov %g1,%o0
.L_bn_sub_words_tail:
addcc %g1,-1,%g0
ld [%o2],%o5
subxcc %o4,%o5,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_sub_words_return
st %o5,[%o0]
nop
ld [%o1+4],%o4
addcc %g1,-1,%g0
ld [%o2+4],%o5
subxcc %o4,%o5,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_sub_words_return
st %o5,[%o0+4]
ld [%o1+8],%o4
addcc %g1,-1,%g0
ld [%o2+8],%o5
subxcc %o4,%o5,%o5
st %o5,[%o0+8]
retl
addx %g0,0,%o0
.type bn_sub_words,#function
.size bn_sub_words,(.-bn_sub_words)
#define FRAME_SIZE -96
/*
* Here is register usage map for *all* routines below.
*/
#define t_1 %o0
#define t_2 %o1
#define c_1 %o2
#define c_2 %o3
#define c_3 %o4
#define ap(I) [%i1+4*I]
#define bp(I) [%i2+4*I]
#define rp(I) [%i0+4*I]
#define a_0 %l0
#define a_1 %l1
#define a_2 %l2
#define a_3 %l3
#define a_4 %l4
#define a_5 %l5
#define a_6 %l6
#define a_7 %l7
#define b_0 %i3
#define b_1 %i4
#define b_2 %i5
#define b_3 %o5
#define b_4 %g1
#define b_5 %g2
#define b_6 %g3
#define b_7 %g4
.align 32
.global bn_mul_comba8
/*
* void bn_mul_comba8(r,a,b)
* BN_ULONG *r,*a,*b;
*/
bn_mul_comba8:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
ld bp(0),b_0
umul a_0,b_0,c_1 !=!mul_add_c(a[0],b[0],c1,c2,c3);
ld bp(1),b_1
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
umul a_0,b_1,t_1 !=!mul_add_c(a[0],b[1],c2,c3,c1);
ld ap(1),a_1
addcc c_2,t_1,c_2
rd %y,t_2
addxcc %g0,t_2,c_3 !=
addx %g0,%g0,c_1
ld ap(2),a_2
umul a_1,b_0,t_1 !mul_add_c(a[1],b[0],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
st c_2,rp(1) !r[1]=c2;
addx c_1,%g0,c_1 !=
umul a_2,b_0,t_1 !mul_add_c(a[2],b[0],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx %g0,%g0,c_2
ld bp(2),b_2
umul a_1,b_1,t_1 !mul_add_c(a[1],b[1],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
ld bp(3),b_3
addx c_2,%g0,c_2 !=
umul a_0,b_2,t_1 !mul_add_c(a[0],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
st c_3,rp(2) !r[2]=c3;
umul a_0,b_3,t_1 !mul_add_c(a[0],b[3],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
umul a_1,b_2,t_1 !=!mul_add_c(a[1],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
ld ap(3),a_3
umul a_2,b_1,t_1 !mul_add_c(a[2],b[1],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
ld ap(4),a_4
umul a_3,b_0,t_1 !mul_add_c(a[3],b[0],c1,c2,c3);!=
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_4,b_0,t_1 !mul_add_c(a[4],b[0],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
umul a_3,b_1,t_1 !mul_add_c(a[3],b[1],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_2,b_2,t_1 !=!mul_add_c(a[2],b[2],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
ld bp(4),b_4
umul a_1,b_3,t_1 !mul_add_c(a[1],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
ld bp(5),b_5
umul a_0,b_4,t_1 !=!mul_add_c(a[0],b[4],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(4) !r[4]=c2;
umul a_0,b_5,t_1 !mul_add_c(a[0],b[5],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
umul a_1,b_4,t_1 !mul_add_c(a[1],b[4],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_2,b_3,t_1 !=!mul_add_c(a[2],b[3],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_3,b_2,t_1 !mul_add_c(a[3],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
ld ap(5),a_5
umul a_4,b_1,t_1 !mul_add_c(a[4],b[1],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
ld ap(6),a_6
addx c_2,%g0,c_2 !=
umul a_5,b_0,t_1 !mul_add_c(a[5],b[0],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
st c_3,rp(5) !r[5]=c3;
umul a_6,b_0,t_1 !mul_add_c(a[6],b[0],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
umul a_5,b_1,t_1 !=!mul_add_c(a[5],b[1],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_4,b_2,t_1 !mul_add_c(a[4],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
umul a_3,b_3,t_1 !mul_add_c(a[3],b[3],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_2,b_4,t_1 !mul_add_c(a[2],b[4],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
ld bp(6),b_6
addx c_3,%g0,c_3 !=
umul a_1,b_5,t_1 !mul_add_c(a[1],b[5],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
ld bp(7),b_7
umul a_0,b_6,t_1 !mul_add_c(a[0],b[6],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
st c_1,rp(6) !r[6]=c1;
addx c_3,%g0,c_3 !=
umul a_0,b_7,t_1 !mul_add_c(a[0],b[7],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx %g0,%g0,c_1
umul a_1,b_6,t_1 !mul_add_c(a[1],b[6],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_2,b_5,t_1 !mul_add_c(a[2],b[5],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_3,b_4,t_1 !=!mul_add_c(a[3],b[4],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
umul a_4,b_3,t_1 !mul_add_c(a[4],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_5,b_2,t_1 !mul_add_c(a[5],b[2],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
ld ap(7),a_7
umul a_6,b_1,t_1 !=!mul_add_c(a[6],b[1],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
umul a_7,b_0,t_1 !mul_add_c(a[7],b[0],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
st c_2,rp(7) !r[7]=c2;
umul a_7,b_1,t_1 !mul_add_c(a[7],b[1],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
umul a_6,b_2,t_1 !=!mul_add_c(a[6],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_5,b_3,t_1 !mul_add_c(a[5],b[3],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
umul a_4,b_4,t_1 !mul_add_c(a[4],b[4],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_3,b_5,t_1 !mul_add_c(a[3],b[5],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_2,b_6,t_1 !=!mul_add_c(a[2],b[6],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_1,b_7,t_1 !mul_add_c(a[1],b[7],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !
addx c_2,%g0,c_2
st c_3,rp(8) !r[8]=c3;
umul a_2,b_7,t_1 !mul_add_c(a[2],b[7],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
umul a_3,b_6,t_1 !=!mul_add_c(a[3],b[6],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_4,b_5,t_1 !mul_add_c(a[4],b[5],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
umul a_5,b_4,t_1 !mul_add_c(a[5],b[4],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_6,b_3,t_1 !mul_add_c(a[6],b[3],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_7,b_2,t_1 !=!mul_add_c(a[7],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(9) !r[9]=c1;
umul a_7,b_3,t_1 !mul_add_c(a[7],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
umul a_6,b_4,t_1 !mul_add_c(a[6],b[4],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_5,b_5,t_1 !=!mul_add_c(a[5],b[5],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
umul a_4,b_6,t_1 !mul_add_c(a[4],b[6],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_3,b_7,t_1 !mul_add_c(a[3],b[7],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(10) !r[10]=c2;
umul a_4,b_7,t_1 !=!mul_add_c(a[4],b[7],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2 !=
umul a_5,b_6,t_1 !mul_add_c(a[5],b[6],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
umul a_6,b_5,t_1 !mul_add_c(a[6],b[5],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_7,b_4,t_1 !mul_add_c(a[7],b[4],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(11) !r[11]=c3;
addx c_2,%g0,c_2 !=
umul a_7,b_5,t_1 !mul_add_c(a[7],b[5],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
umul a_6,b_6,t_1 !mul_add_c(a[6],b[6],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_5,b_7,t_1 !mul_add_c(a[5],b[7],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
st c_1,rp(12) !r[12]=c1;
addx c_3,%g0,c_3 !=
umul a_6,b_7,t_1 !mul_add_c(a[6],b[7],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx %g0,%g0,c_1
umul a_7,b_6,t_1 !mul_add_c(a[7],b[6],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(13) !r[13]=c2;
umul a_7,b_7,t_1 !=!mul_add_c(a[7],b[7],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
nop !=
st c_3,rp(14) !r[14]=c3;
st c_1,rp(15) !r[15]=c1;
ret
restore %g0,%g0,%o0
.type bn_mul_comba8,#function
.size bn_mul_comba8,(.-bn_mul_comba8)
.align 32
.global bn_mul_comba4
/*
* void bn_mul_comba4(r,a,b)
* BN_ULONG *r,*a,*b;
*/
bn_mul_comba4:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
ld bp(0),b_0
umul a_0,b_0,c_1 !=!mul_add_c(a[0],b[0],c1,c2,c3);
ld bp(1),b_1
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
umul a_0,b_1,t_1 !=!mul_add_c(a[0],b[1],c2,c3,c1);
ld ap(1),a_1
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc %g0,t_2,c_3
addx %g0,%g0,c_1
ld ap(2),a_2
umul a_1,b_0,t_1 !=!mul_add_c(a[1],b[0],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(1) !r[1]=c2;
umul a_2,b_0,t_1 !mul_add_c(a[2],b[0],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
ld bp(2),b_2
umul a_1,b_1,t_1 !=!mul_add_c(a[1],b[1],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
ld bp(3),b_3
umul a_0,b_2,t_1 !mul_add_c(a[0],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
st c_3,rp(2) !r[2]=c3;
umul a_0,b_3,t_1 !=!mul_add_c(a[0],b[3],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3 !=
umul a_1,b_2,t_1 !mul_add_c(a[1],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
ld ap(3),a_3
umul a_2,b_1,t_1 !mul_add_c(a[2],b[1],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_3,b_0,t_1 !=!mul_add_c(a[3],b[0],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_3,b_1,t_1 !mul_add_c(a[3],b[1],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
umul a_2,b_2,t_1 !mul_add_c(a[2],b[2],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_1,b_3,t_1 !=!mul_add_c(a[1],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(4) !r[4]=c2;
umul a_2,b_3,t_1 !mul_add_c(a[2],b[3],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
umul a_3,b_2,t_1 !mul_add_c(a[3],b[2],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(5) !r[5]=c3;
addx c_2,%g0,c_2 !=
umul a_3,b_3,t_1 !mul_add_c(a[3],b[3],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
st c_1,rp(6) !r[6]=c1;
st c_2,rp(7) !r[7]=c2;
ret
restore %g0,%g0,%o0
.type bn_mul_comba4,#function
.size bn_mul_comba4,(.-bn_mul_comba4)
.align 32
.global bn_sqr_comba8
bn_sqr_comba8:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
ld ap(1),a_1
umul a_0,a_0,c_1 !=!sqr_add_c(a,0,c1,c2,c3);
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
ld ap(2),a_2
umul a_0,a_1,t_1 !=!sqr_add_c2(a,1,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc %g0,t_2,c_3
addx %g0,%g0,c_1 !=
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3
st c_2,rp(1) !r[1]=c2;
addx c_1,%g0,c_1 !=
umul a_2,a_0,t_1 !sqr_add_c2(a,2,0,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx %g0,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
ld ap(3),a_3
umul a_1,a_1,t_1 !sqr_add_c(a,1,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
st c_3,rp(2) !r[2]=c3;
umul a_0,a_3,t_1 !=!sqr_add_c2(a,3,0,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3 !=
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
ld ap(4),a_4
addx c_3,%g0,c_3 !=
umul a_1,a_2,t_1 !sqr_add_c2(a,2,1,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_4,a_0,t_1 !sqr_add_c2(a,4,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_3,a_1,t_1 !sqr_add_c2(a,3,1,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
ld ap(5),a_5
umul a_2,a_2,t_1 !sqr_add_c(a,2,c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
st c_2,rp(4) !r[4]=c2;
addx c_1,%g0,c_1 !=
umul a_0,a_5,t_1 !sqr_add_c2(a,5,0,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx %g0,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_1,a_4,t_1 !sqr_add_c2(a,4,1,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
ld ap(6),a_6
umul a_2,a_3,t_1 !sqr_add_c2(a,3,2,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
st c_3,rp(5) !r[5]=c3;
umul a_6,a_0,t_1 !sqr_add_c2(a,6,0,c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
addcc c_1,t_1,c_1 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_5,a_1,t_1 !sqr_add_c2(a,5,1,c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
addcc c_1,t_1,c_1 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_4,a_2,t_1 !sqr_add_c2(a,4,2,c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
addcc c_1,t_1,c_1 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
ld ap(7),a_7
umul a_3,a_3,t_1 !=!sqr_add_c(a,3,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(6) !r[6]=c1;
umul a_0,a_7,t_1 !sqr_add_c2(a,7,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_1,a_6,t_1 !sqr_add_c2(a,6,1,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_2,a_5,t_1 !sqr_add_c2(a,5,2,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_3,a_4,t_1 !sqr_add_c2(a,4,3,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
st c_2,rp(7) !r[7]=c2;
umul a_7,a_1,t_1 !sqr_add_c2(a,7,1,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
addcc c_3,t_1,c_3 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_6,a_2,t_1 !sqr_add_c2(a,6,2,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
addcc c_3,t_1,c_3 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_5,a_3,t_1 !sqr_add_c2(a,5,3,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
addcc c_3,t_1,c_3 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_4,a_4,t_1 !sqr_add_c(a,4,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(8) !r[8]=c3;
addx c_2,%g0,c_2 !=
umul a_2,a_7,t_1 !sqr_add_c2(a,7,2,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_3,a_6,t_1 !sqr_add_c2(a,6,3,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_4,a_5,t_1 !sqr_add_c2(a,5,4,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(9) !r[9]=c1;
umul a_7,a_3,t_1 !sqr_add_c2(a,7,3,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_6,a_4,t_1 !sqr_add_c2(a,6,4,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_5,a_5,t_1 !sqr_add_c(a,5,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(10) !r[10]=c2;
umul a_4,a_7,t_1 !=!sqr_add_c2(a,7,4,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2 !=
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_5,a_6,t_1 !=!sqr_add_c2(a,6,5,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
st c_3,rp(11) !r[11]=c3;
addx c_2,%g0,c_2 !=
umul a_7,a_5,t_1 !sqr_add_c2(a,7,5,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_6,a_6,t_1 !sqr_add_c(a,6,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
st c_1,rp(12) !r[12]=c1;
umul a_6,a_7,t_1 !sqr_add_c2(a,7,6,c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2 !=
addxcc c_3,t_2,c_3
st c_2,rp(13) !r[13]=c2;
addx c_1,%g0,c_1 !=
umul a_7,a_7,t_1 !sqr_add_c(a,7,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
st c_3,rp(14) !r[14]=c3;
st c_1,rp(15) !r[15]=c1;
ret
restore %g0,%g0,%o0
.type bn_sqr_comba8,#function
.size bn_sqr_comba8,(.-bn_sqr_comba8)
.align 32
.global bn_sqr_comba4
/*
* void bn_sqr_comba4(r,a)
* BN_ULONG *r,*a;
*/
bn_sqr_comba4:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
umul a_0,a_0,c_1 !sqr_add_c(a,0,c1,c2,c3);
ld ap(1),a_1 !=
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
ld ap(2),a_2
umul a_0,a_1,t_1 !=!sqr_add_c2(a,1,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc %g0,t_2,c_3
addx %g0,%g0,c_1 !=
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(1) !r[1]=c2;
umul a_2,a_0,t_1 !sqr_add_c2(a,2,0,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
ld ap(3),a_3
umul a_1,a_1,t_1 !sqr_add_c(a,1,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(2) !r[2]=c3;
addx c_2,%g0,c_2 !=
umul a_0,a_3,t_1 !sqr_add_c2(a,3,0,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_1,a_2,t_1 !sqr_add_c2(a,2,1,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_3,a_1,t_1 !sqr_add_c2(a,3,1,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_2,a_2,t_1 !sqr_add_c(a,2,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(4) !r[4]=c2;
umul a_2,a_3,t_1 !=!sqr_add_c2(a,3,2,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2 !=
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
st c_3,rp(5) !r[5]=c3;
addx c_2,%g0,c_2 !=
umul a_3,a_3,t_1 !sqr_add_c(a,3,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
st c_1,rp(6) !r[6]=c1;
st c_2,rp(7) !r[7]=c2;
ret
restore %g0,%g0,%o0
.type bn_sqr_comba4,#function
.size bn_sqr_comba4,(.-bn_sqr_comba4)
.align 32
|
ntu-ssl/rr-artifact | 45,641 | openssl-1.1.0l/crypto/bn/asm/ia64.S | .explicit
.text
.ident "ia64.S, Version 2.1"
.ident "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
// Copyright 2001-2016 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under the OpenSSL license (the "License"). You may not use
// this file except in compliance with the License. You can obtain a copy
// in the file LICENSE in the source distribution or at
// https://www.openssl.org/source/license.html
//
// ====================================================================
// Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
// project.
//
// Rights for redistribution and usage in source and binary forms are
// granted according to the OpenSSL license. Warranty of any kind is
// disclaimed.
// ====================================================================
//
// Version 2.x is Itanium2 re-tune. Few words about how Itanum2 is
// different from Itanium to this module viewpoint. Most notably, is it
// "wider" than Itanium? Can you experience loop scalability as
// discussed in commentary sections? Not really:-( Itanium2 has 6
// integer ALU ports, i.e. it's 2 ports wider, but it's not enough to
// spin twice as fast, as I need 8 IALU ports. Amount of floating point
// ports is the same, i.e. 2, while I need 4. In other words, to this
// module Itanium2 remains effectively as "wide" as Itanium. Yet it's
// essentially different in respect to this module, and a re-tune was
// required. Well, because some instruction latencies has changed. Most
// noticeably those intensively used:
//
// Itanium Itanium2
// ldf8 9 6 L2 hit
// ld8 2 1 L1 hit
// getf 2 5
// xma[->getf] 7[+1] 4[+0]
// add[->st8] 1[+1] 1[+0]
//
// What does it mean? You might ratiocinate that the original code
// should run just faster... Because sum of latencies is smaller...
// Wrong! Note that getf latency increased. This means that if a loop is
// scheduled for lower latency (as they were), then it will suffer from
// stall condition and the code will therefore turn anti-scalable, e.g.
// original bn_mul_words spun at 5*n or 2.5 times slower than expected
// on Itanium2! What to do? Reschedule loops for Itanium2? But then
// Itanium would exhibit anti-scalability. So I've chosen to reschedule
// for worst latency for every instruction aiming for best *all-round*
// performance.
// Q. How much faster does it get?
// A. Here is the output from 'openssl speed rsa dsa' for vanilla
// 0.9.6a compiled with gcc version 2.96 20000731 (Red Hat
// Linux 7.1 2.96-81):
//
// sign verify sign/s verify/s
// rsa 512 bits 0.0036s 0.0003s 275.3 2999.2
// rsa 1024 bits 0.0203s 0.0011s 49.3 894.1
// rsa 2048 bits 0.1331s 0.0040s 7.5 250.9
// rsa 4096 bits 0.9270s 0.0147s 1.1 68.1
// sign verify sign/s verify/s
// dsa 512 bits 0.0035s 0.0043s 288.3 234.8
// dsa 1024 bits 0.0111s 0.0135s 90.0 74.2
//
// And here is similar output but for this assembler
// implementation:-)
//
// sign verify sign/s verify/s
// rsa 512 bits 0.0021s 0.0001s 549.4 9638.5
// rsa 1024 bits 0.0055s 0.0002s 183.8 4481.1
// rsa 2048 bits 0.0244s 0.0006s 41.4 1726.3
// rsa 4096 bits 0.1295s 0.0018s 7.7 561.5
// sign verify sign/s verify/s
// dsa 512 bits 0.0012s 0.0013s 891.9 756.6
// dsa 1024 bits 0.0023s 0.0028s 440.4 376.2
//
// Yes, you may argue that it's not fair comparison as it's
// possible to craft the C implementation with BN_UMULT_HIGH
// inline assembler macro. But of course! Here is the output
// with the macro:
//
// sign verify sign/s verify/s
// rsa 512 bits 0.0020s 0.0002s 495.0 6561.0
// rsa 1024 bits 0.0086s 0.0004s 116.2 2235.7
// rsa 2048 bits 0.0519s 0.0015s 19.3 667.3
// rsa 4096 bits 0.3464s 0.0053s 2.9 187.7
// sign verify sign/s verify/s
// dsa 512 bits 0.0016s 0.0020s 613.1 510.5
// dsa 1024 bits 0.0045s 0.0054s 221.0 183.9
//
// My code is still way faster, huh:-) And I believe that even
// higher performance can be achieved. Note that as keys get
// longer, performance gain is larger. Why? According to the
// profiler there is another player in the field, namely
// BN_from_montgomery consuming larger and larger portion of CPU
// time as keysize decreases. I therefore consider putting effort
// to assembler implementation of the following routine:
//
// void bn_mul_add_mont (BN_ULONG *rp,BN_ULONG *np,int nl,BN_ULONG n0)
// {
// int i,j;
// BN_ULONG v;
//
// for (i=0; i<nl; i++)
// {
// v=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2);
// nrp++;
// rp++;
// if (((nrp[-1]+=v)&BN_MASK2) < v)
// for (j=0; ((++nrp[j])&BN_MASK2) == 0; j++) ;
// }
// }
//
// It might as well be beneficial to implement even combaX
// variants, as it appears as it can literally unleash the
// performance (see comment section to bn_mul_comba8 below).
//
// And finally for your reference the output for 0.9.6a compiled
// with SGIcc version 0.01.0-12 (keep in mind that for the moment
// of this writing it's not possible to convince SGIcc to use
// BN_UMULT_HIGH inline assembler macro, yet the code is fast,
// i.e. for a compiler generated one:-):
//
// sign verify sign/s verify/s
// rsa 512 bits 0.0022s 0.0002s 452.7 5894.3
// rsa 1024 bits 0.0097s 0.0005s 102.7 2002.9
// rsa 2048 bits 0.0578s 0.0017s 17.3 600.2
// rsa 4096 bits 0.3838s 0.0061s 2.6 164.5
// sign verify sign/s verify/s
// dsa 512 bits 0.0018s 0.0022s 547.3 459.6
// dsa 1024 bits 0.0051s 0.0062s 196.6 161.3
//
// Oh! Benchmarks were performed on 733MHz Lion-class Itanium
// system running Redhat Linux 7.1 (very special thanks to Ray
// McCaffity of Williams Communications for providing an account).
//
// Q. What's the heck with 'rum 1<<5' at the end of every function?
// A. Well, by clearing the "upper FP registers written" bit of the
// User Mask I want to excuse the kernel from preserving upper
// (f32-f128) FP register bank over process context switch, thus
// minimizing bus bandwidth consumption during the switch (i.e.
// after PKI opration completes and the program is off doing
// something else like bulk symmetric encryption). Having said
// this, I also want to point out that it might be good idea
// to compile the whole toolkit (as well as majority of the
// programs for that matter) with -mfixed-range=f32-f127 command
// line option. No, it doesn't prevent the compiler from writing
// to upper bank, but at least discourages to do so. If you don't
// like the idea you have the option to compile the module with
// -Drum=nop.m in command line.
//
#if defined(_HPUX_SOURCE) && !defined(_LP64)
#define ADDP addp4
#else
#define ADDP add
#endif
#if 1
//
// bn_[add|sub]_words routines.
//
// Loops are spinning in 2*(n+5) ticks on Itanuim (provided that the
// data reside in L1 cache, i.e. 2 ticks away). It's possible to
// compress the epilogue and get down to 2*n+6, but at the cost of
// scalability (the neat feature of this implementation is that it
// shall automagically spin in n+5 on "wider" IA-64 implementations:-)
// I consider that the epilogue is short enough as it is to trade tiny
// performance loss on Itanium for scalability.
//
// BN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
//
.global bn_add_words#
.proc bn_add_words#
.align 64
.skip 32 // makes the loop body aligned at 64-byte boundary
bn_add_words:
.prologue
.save ar.pfs,r2
{ .mii; alloc r2=ar.pfs,4,12,0,16
cmp4.le p6,p0=r35,r0 };;
{ .mfb; mov r8=r0 // return value
(p6) br.ret.spnt.many b0 };;
{ .mib; sub r10=r35,r0,1
.save ar.lc,r3
mov r3=ar.lc
brp.loop.imp .L_bn_add_words_ctop,.L_bn_add_words_cend-16
}
{ .mib; ADDP r14=0,r32 // rp
.save pr,r9
mov r9=pr };;
.body
{ .mii; ADDP r15=0,r33 // ap
mov ar.lc=r10
mov ar.ec=6 }
{ .mib; ADDP r16=0,r34 // bp
mov pr.rot=1<<16 };;
.L_bn_add_words_ctop:
{ .mii; (p16) ld8 r32=[r16],8 // b=*(bp++)
(p18) add r39=r37,r34
(p19) cmp.ltu.unc p56,p0=r40,r38 }
{ .mfb; (p0) nop.m 0x0
(p0) nop.f 0x0
(p0) nop.b 0x0 }
{ .mii; (p16) ld8 r35=[r15],8 // a=*(ap++)
(p58) cmp.eq.or p57,p0=-1,r41 // (p20)
(p58) add r41=1,r41 } // (p20)
{ .mfb; (p21) st8 [r14]=r42,8 // *(rp++)=r
(p0) nop.f 0x0
br.ctop.sptk .L_bn_add_words_ctop };;
.L_bn_add_words_cend:
{ .mii;
(p59) add r8=1,r8 // return value
mov pr=r9,0x1ffff
mov ar.lc=r3 }
{ .mbb; nop.b 0x0
br.ret.sptk.many b0 };;
.endp bn_add_words#
//
// BN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num)
//
.global bn_sub_words#
.proc bn_sub_words#
.align 64
.skip 32 // makes the loop body aligned at 64-byte boundary
bn_sub_words:
.prologue
.save ar.pfs,r2
{ .mii; alloc r2=ar.pfs,4,12,0,16
cmp4.le p6,p0=r35,r0 };;
{ .mfb; mov r8=r0 // return value
(p6) br.ret.spnt.many b0 };;
{ .mib; sub r10=r35,r0,1
.save ar.lc,r3
mov r3=ar.lc
brp.loop.imp .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16
}
{ .mib; ADDP r14=0,r32 // rp
.save pr,r9
mov r9=pr };;
.body
{ .mii; ADDP r15=0,r33 // ap
mov ar.lc=r10
mov ar.ec=6 }
{ .mib; ADDP r16=0,r34 // bp
mov pr.rot=1<<16 };;
.L_bn_sub_words_ctop:
{ .mii; (p16) ld8 r32=[r16],8 // b=*(bp++)
(p18) sub r39=r37,r34
(p19) cmp.gtu.unc p56,p0=r40,r38 }
{ .mfb; (p0) nop.m 0x0
(p0) nop.f 0x0
(p0) nop.b 0x0 }
{ .mii; (p16) ld8 r35=[r15],8 // a=*(ap++)
(p58) cmp.eq.or p57,p0=0,r41 // (p20)
(p58) add r41=-1,r41 } // (p20)
{ .mbb; (p21) st8 [r14]=r42,8 // *(rp++)=r
(p0) nop.b 0x0
br.ctop.sptk .L_bn_sub_words_ctop };;
.L_bn_sub_words_cend:
{ .mii;
(p59) add r8=1,r8 // return value
mov pr=r9,0x1ffff
mov ar.lc=r3 }
{ .mbb; nop.b 0x0
br.ret.sptk.many b0 };;
.endp bn_sub_words#
#endif
#if 0
#define XMA_TEMPTATION
#endif
#if 1
//
// BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
//
.global bn_mul_words#
.proc bn_mul_words#
.align 64
.skip 32 // makes the loop body aligned at 64-byte boundary
bn_mul_words:
.prologue
.save ar.pfs,r2
#ifdef XMA_TEMPTATION
{ .mfi; alloc r2=ar.pfs,4,0,0,0 };;
#else
{ .mfi; alloc r2=ar.pfs,4,12,0,16 };;
#endif
{ .mib; mov r8=r0 // return value
cmp4.le p6,p0=r34,r0
(p6) br.ret.spnt.many b0 };;
{ .mii; sub r10=r34,r0,1
.save ar.lc,r3
mov r3=ar.lc
.save pr,r9
mov r9=pr };;
.body
{ .mib; setf.sig f8=r35 // w
mov pr.rot=0x800001<<16
// ------^----- serves as (p50) at first (p27)
brp.loop.imp .L_bn_mul_words_ctop,.L_bn_mul_words_cend-16
}
#ifndef XMA_TEMPTATION
{ .mmi; ADDP r14=0,r32 // rp
ADDP r15=0,r33 // ap
mov ar.lc=r10 }
{ .mmi; mov r40=0 // serves as r35 at first (p27)
mov ar.ec=13 };;
// This loop spins in 2*(n+12) ticks. It's scheduled for data in Itanium
// L2 cache (i.e. 9 ticks away) as floating point load/store instructions
// bypass L1 cache and L2 latency is actually best-case scenario for
// ldf8. The loop is not scalable and shall run in 2*(n+12) even on
// "wider" IA-64 implementations. It's a trade-off here. n+24 loop
// would give us ~5% in *overall* performance improvement on "wider"
// IA-64, but would hurt Itanium for about same because of longer
// epilogue. As it's a matter of few percents in either case I've
// chosen to trade the scalability for development time (you can see
// this very instruction sequence in bn_mul_add_words loop which in
// turn is scalable).
.L_bn_mul_words_ctop:
{ .mfi; (p25) getf.sig r36=f52 // low
(p21) xmpy.lu f48=f37,f8
(p28) cmp.ltu p54,p50=r41,r39 }
{ .mfi; (p16) ldf8 f32=[r15],8
(p21) xmpy.hu f40=f37,f8
(p0) nop.i 0x0 };;
{ .mii; (p25) getf.sig r32=f44 // high
.pred.rel "mutex",p50,p54
(p50) add r40=r38,r35 // (p27)
(p54) add r40=r38,r35,1 } // (p27)
{ .mfb; (p28) st8 [r14]=r41,8
(p0) nop.f 0x0
br.ctop.sptk .L_bn_mul_words_ctop };;
.L_bn_mul_words_cend:
{ .mii; nop.m 0x0
.pred.rel "mutex",p51,p55
(p51) add r8=r36,r0
(p55) add r8=r36,r0,1 }
{ .mfb; nop.m 0x0
nop.f 0x0
nop.b 0x0 }
#else // XMA_TEMPTATION
setf.sig f37=r0 // serves as carry at (p18) tick
mov ar.lc=r10
mov ar.ec=5;;
// Most of you examining this code very likely wonder why in the name
// of Intel the following loop is commented out? Indeed, it looks so
// neat that you find it hard to believe that it's something wrong
// with it, right? The catch is that every iteration depends on the
// result from previous one and the latter isn't available instantly.
// The loop therefore spins at the latency of xma minus 1, or in other
// words at 6*(n+4) ticks:-( Compare to the "production" loop above
// that runs in 2*(n+11) where the low latency problem is worked around
// by moving the dependency to one-tick latent integer ALU. Note that
// "distance" between ldf8 and xma is not latency of ldf8, but the
// *difference* between xma and ldf8 latencies.
.L_bn_mul_words_ctop:
{ .mfi; (p16) ldf8 f32=[r33],8
(p18) xma.hu f38=f34,f8,f39 }
{ .mfb; (p20) stf8 [r32]=f37,8
(p18) xma.lu f35=f34,f8,f39
br.ctop.sptk .L_bn_mul_words_ctop };;
.L_bn_mul_words_cend:
getf.sig r8=f41 // the return value
#endif // XMA_TEMPTATION
{ .mii; nop.m 0x0
mov pr=r9,0x1ffff
mov ar.lc=r3 }
{ .mfb; rum 1<<5 // clear um.mfh
nop.f 0x0
br.ret.sptk.many b0 };;
.endp bn_mul_words#
#endif
#if 1
//
// BN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
//
.global bn_mul_add_words#
.proc bn_mul_add_words#
.align 64
.skip 48 // makes the loop body aligned at 64-byte boundary
bn_mul_add_words:
.prologue
.save ar.pfs,r2
{ .mmi; alloc r2=ar.pfs,4,4,0,8
cmp4.le p6,p0=r34,r0
.save ar.lc,r3
mov r3=ar.lc };;
{ .mib; mov r8=r0 // return value
sub r10=r34,r0,1
(p6) br.ret.spnt.many b0 };;
{ .mib; setf.sig f8=r35 // w
.save pr,r9
mov r9=pr
brp.loop.imp .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
}
.body
{ .mmi; ADDP r14=0,r32 // rp
ADDP r15=0,r33 // ap
mov ar.lc=r10 }
{ .mii; ADDP r16=0,r32 // rp copy
mov pr.rot=0x2001<<16
// ------^----- serves as (p40) at first (p27)
mov ar.ec=11 };;
// This loop spins in 3*(n+10) ticks on Itanium and in 2*(n+10) on
// Itanium 2. Yes, unlike previous versions it scales:-) Previous
// version was performing *all* additions in IALU and was starving
// for those even on Itanium 2. In this version one addition is
// moved to FPU and is folded with multiplication. This is at cost
// of propagating the result from previous call to this subroutine
// to L2 cache... In other words negligible even for shorter keys.
// *Overall* performance improvement [over previous version] varies
// from 11 to 22 percent depending on key length.
.L_bn_mul_add_words_ctop:
.pred.rel "mutex",p40,p42
{ .mfi; (p23) getf.sig r36=f45 // low
(p20) xma.lu f42=f36,f8,f50 // low
(p40) add r39=r39,r35 } // (p27)
{ .mfi; (p16) ldf8 f32=[r15],8 // *(ap++)
(p20) xma.hu f36=f36,f8,f50 // high
(p42) add r39=r39,r35,1 };; // (p27)
{ .mmi; (p24) getf.sig r32=f40 // high
(p16) ldf8 f46=[r16],8 // *(rp1++)
(p40) cmp.ltu p41,p39=r39,r35 } // (p27)
{ .mib; (p26) st8 [r14]=r39,8 // *(rp2++)
(p42) cmp.leu p41,p39=r39,r35 // (p27)
br.ctop.sptk .L_bn_mul_add_words_ctop};;
.L_bn_mul_add_words_cend:
{ .mmi; .pred.rel "mutex",p40,p42
(p40) add r8=r35,r0
(p42) add r8=r35,r0,1
mov pr=r9,0x1ffff }
{ .mib; rum 1<<5 // clear um.mfh
mov ar.lc=r3
br.ret.sptk.many b0 };;
.endp bn_mul_add_words#
#endif
#if 1
//
// void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
//
.global bn_sqr_words#
.proc bn_sqr_words#
.align 64
.skip 32 // makes the loop body aligned at 64-byte boundary
bn_sqr_words:
.prologue
.save ar.pfs,r2
{ .mii; alloc r2=ar.pfs,3,0,0,0
sxt4 r34=r34 };;
{ .mii; cmp.le p6,p0=r34,r0
mov r8=r0 } // return value
{ .mfb; ADDP r32=0,r32
nop.f 0x0
(p6) br.ret.spnt.many b0 };;
{ .mii; sub r10=r34,r0,1
.save ar.lc,r3
mov r3=ar.lc
.save pr,r9
mov r9=pr };;
.body
{ .mib; ADDP r33=0,r33
mov pr.rot=1<<16
brp.loop.imp .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16
}
{ .mii; add r34=8,r32
mov ar.lc=r10
mov ar.ec=18 };;
// 2*(n+17) on Itanium, (n+17) on "wider" IA-64 implementations. It's
// possible to compress the epilogue (I'm getting tired to write this
// comment over and over) and get down to 2*n+16 at the cost of
// scalability. The decision will very likely be reconsidered after the
// benchmark program is profiled. I.e. if perfomance gain on Itanium
// will appear larger than loss on "wider" IA-64, then the loop should
// be explicitly split and the epilogue compressed.
.L_bn_sqr_words_ctop:
{ .mfi; (p16) ldf8 f32=[r33],8
(p25) xmpy.lu f42=f41,f41
(p0) nop.i 0x0 }
{ .mib; (p33) stf8 [r32]=f50,16
(p0) nop.i 0x0
(p0) nop.b 0x0 }
{ .mfi; (p0) nop.m 0x0
(p25) xmpy.hu f52=f41,f41
(p0) nop.i 0x0 }
{ .mib; (p33) stf8 [r34]=f60,16
(p0) nop.i 0x0
br.ctop.sptk .L_bn_sqr_words_ctop };;
.L_bn_sqr_words_cend:
{ .mii; nop.m 0x0
mov pr=r9,0x1ffff
mov ar.lc=r3 }
{ .mfb; rum 1<<5 // clear um.mfh
nop.f 0x0
br.ret.sptk.many b0 };;
.endp bn_sqr_words#
#endif
#if 1
// Apparently we win nothing by implementing special bn_sqr_comba8.
// Yes, it is possible to reduce the number of multiplications by
// almost factor of two, but then the amount of additions would
// increase by factor of two (as we would have to perform those
// otherwise performed by xma ourselves). Normally we would trade
// anyway as multiplications are way more expensive, but not this
// time... Multiplication kernel is fully pipelined and as we drain
// one 128-bit multiplication result per clock cycle multiplications
// are effectively as inexpensive as additions. Special implementation
// might become of interest for "wider" IA-64 implementation as you'll
// be able to get through the multiplication phase faster (there won't
// be any stall issues as discussed in the commentary section below and
// you therefore will be able to employ all 4 FP units)... But these
// Itanium days it's simply too hard to justify the effort so I just
// drop down to bn_mul_comba8 code:-)
//
// void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
//
.global bn_sqr_comba8#
.proc bn_sqr_comba8#
.align 64
bn_sqr_comba8:
.prologue
.save ar.pfs,r2
#if defined(_HPUX_SOURCE) && !defined(_LP64)
{ .mii; alloc r2=ar.pfs,2,1,0,0
addp4 r33=0,r33
addp4 r32=0,r32 };;
{ .mii;
#else
{ .mii; alloc r2=ar.pfs,2,1,0,0
#endif
mov r34=r33
add r14=8,r33 };;
.body
{ .mii; add r17=8,r34
add r15=16,r33
add r18=16,r34 }
{ .mfb; add r16=24,r33
br .L_cheat_entry_point8 };;
.endp bn_sqr_comba8#
#endif
#if 1
// I've estimated this routine to run in ~120 ticks, but in reality
// (i.e. according to ar.itc) it takes ~160 ticks. Are those extra
// cycles consumed for instructions fetch? Or did I misinterpret some
// clause in Itanium µ-architecture manual? Comments are welcomed and
// highly appreciated.
//
// On Itanium 2 it takes ~190 ticks. This is because of stalls on
// result from getf.sig. I do nothing about it at this point for
// reasons depicted below.
//
// However! It should be noted that even 160 ticks is darn good result
// as it's over 10 (yes, ten, spelled as t-e-n) times faster than the
// C version (compiled with gcc with inline assembler). I really
// kicked compiler's butt here, didn't I? Yeah! This brings us to the
// following statement. It's damn shame that this routine isn't called
// very often nowadays! According to the profiler most CPU time is
// consumed by bn_mul_add_words called from BN_from_montgomery. In
// order to estimate what we're missing, I've compared the performance
// of this routine against "traditional" implementation, i.e. against
// following routine:
//
// void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
// { r[ 8]=bn_mul_words( &(r[0]),a,8,b[0]);
// r[ 9]=bn_mul_add_words(&(r[1]),a,8,b[1]);
// r[10]=bn_mul_add_words(&(r[2]),a,8,b[2]);
// r[11]=bn_mul_add_words(&(r[3]),a,8,b[3]);
// r[12]=bn_mul_add_words(&(r[4]),a,8,b[4]);
// r[13]=bn_mul_add_words(&(r[5]),a,8,b[5]);
// r[14]=bn_mul_add_words(&(r[6]),a,8,b[6]);
// r[15]=bn_mul_add_words(&(r[7]),a,8,b[7]);
// }
//
// The one below is over 8 times faster than the one above:-( Even
// more reasons to "combafy" bn_mul_add_mont...
//
// And yes, this routine really made me wish there were an optimizing
// assembler! It also feels like it deserves a dedication.
//
// To my wife for being there and to my kids...
//
// void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
//
#define carry1 r14
#define carry2 r15
#define carry3 r34
.global bn_mul_comba8#
.proc bn_mul_comba8#
.align 64
bn_mul_comba8:
.prologue
.save ar.pfs,r2
#if defined(_HPUX_SOURCE) && !defined(_LP64)
{ .mii; alloc r2=ar.pfs,3,0,0,0
addp4 r33=0,r33
addp4 r34=0,r34 };;
{ .mii; addp4 r32=0,r32
#else
{ .mii; alloc r2=ar.pfs,3,0,0,0
#endif
add r14=8,r33
add r17=8,r34 }
.body
{ .mii; add r15=16,r33
add r18=16,r34
add r16=24,r33 }
.L_cheat_entry_point8:
{ .mmi; add r19=24,r34
ldf8 f32=[r33],32 };;
{ .mmi; ldf8 f120=[r34],32
ldf8 f121=[r17],32 }
{ .mmi; ldf8 f122=[r18],32
ldf8 f123=[r19],32 };;
{ .mmi; ldf8 f124=[r34]
ldf8 f125=[r17] }
{ .mmi; ldf8 f126=[r18]
ldf8 f127=[r19] }
{ .mmi; ldf8 f33=[r14],32
ldf8 f34=[r15],32 }
{ .mmi; ldf8 f35=[r16],32;;
ldf8 f36=[r33] }
{ .mmi; ldf8 f37=[r14]
ldf8 f38=[r15] }
{ .mfi; ldf8 f39=[r16]
// -------\ Entering multiplier's heaven /-------
// ------------\ /------------
// -----------------\ /-----------------
// ----------------------\/----------------------
xma.hu f41=f32,f120,f0 }
{ .mfi; xma.lu f40=f32,f120,f0 };; // (*)
{ .mfi; xma.hu f51=f32,f121,f0 }
{ .mfi; xma.lu f50=f32,f121,f0 };;
{ .mfi; xma.hu f61=f32,f122,f0 }
{ .mfi; xma.lu f60=f32,f122,f0 };;
{ .mfi; xma.hu f71=f32,f123,f0 }
{ .mfi; xma.lu f70=f32,f123,f0 };;
{ .mfi; xma.hu f81=f32,f124,f0 }
{ .mfi; xma.lu f80=f32,f124,f0 };;
{ .mfi; xma.hu f91=f32,f125,f0 }
{ .mfi; xma.lu f90=f32,f125,f0 };;
{ .mfi; xma.hu f101=f32,f126,f0 }
{ .mfi; xma.lu f100=f32,f126,f0 };;
{ .mfi; xma.hu f111=f32,f127,f0 }
{ .mfi; xma.lu f110=f32,f127,f0 };;//
// (*) You can argue that splitting at every second bundle would
// prevent "wider" IA-64 implementations from achieving the peak
// performance. Well, not really... The catch is that if you
// intend to keep 4 FP units busy by splitting at every fourth
// bundle and thus perform these 16 multiplications in 4 ticks,
// the first bundle *below* would stall because the result from
// the first xma bundle *above* won't be available for another 3
// ticks (if not more, being an optimist, I assume that "wider"
// implementation will have same latency:-). This stall will hold
// you back and the performance would be as if every second bundle
// were split *anyway*...
{ .mfi; getf.sig r16=f40
xma.hu f42=f33,f120,f41
add r33=8,r32 }
{ .mfi; xma.lu f41=f33,f120,f41 };;
{ .mfi; getf.sig r24=f50
xma.hu f52=f33,f121,f51 }
{ .mfi; xma.lu f51=f33,f121,f51 };;
{ .mfi; st8 [r32]=r16,16
xma.hu f62=f33,f122,f61 }
{ .mfi; xma.lu f61=f33,f122,f61 };;
{ .mfi; xma.hu f72=f33,f123,f71 }
{ .mfi; xma.lu f71=f33,f123,f71 };;
{ .mfi; xma.hu f82=f33,f124,f81 }
{ .mfi; xma.lu f81=f33,f124,f81 };;
{ .mfi; xma.hu f92=f33,f125,f91 }
{ .mfi; xma.lu f91=f33,f125,f91 };;
{ .mfi; xma.hu f102=f33,f126,f101 }
{ .mfi; xma.lu f101=f33,f126,f101 };;
{ .mfi; xma.hu f112=f33,f127,f111 }
{ .mfi; xma.lu f111=f33,f127,f111 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r25=f41
xma.hu f43=f34,f120,f42 }
{ .mfi; xma.lu f42=f34,f120,f42 };;
{ .mfi; getf.sig r16=f60
xma.hu f53=f34,f121,f52 }
{ .mfi; xma.lu f52=f34,f121,f52 };;
{ .mfi; getf.sig r17=f51
xma.hu f63=f34,f122,f62
add r25=r25,r24 }
{ .mfi; xma.lu f62=f34,f122,f62
mov carry1=0 };;
{ .mfi; cmp.ltu p6,p0=r25,r24
xma.hu f73=f34,f123,f72 }
{ .mfi; xma.lu f72=f34,f123,f72 };;
{ .mfi; st8 [r33]=r25,16
xma.hu f83=f34,f124,f82
(p6) add carry1=1,carry1 }
{ .mfi; xma.lu f82=f34,f124,f82 };;
{ .mfi; xma.hu f93=f34,f125,f92 }
{ .mfi; xma.lu f92=f34,f125,f92 };;
{ .mfi; xma.hu f103=f34,f126,f102 }
{ .mfi; xma.lu f102=f34,f126,f102 };;
{ .mfi; xma.hu f113=f34,f127,f112 }
{ .mfi; xma.lu f112=f34,f127,f112 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r18=f42
xma.hu f44=f35,f120,f43
add r17=r17,r16 }
{ .mfi; xma.lu f43=f35,f120,f43 };;
{ .mfi; getf.sig r24=f70
xma.hu f54=f35,f121,f53 }
{ .mfi; mov carry2=0
xma.lu f53=f35,f121,f53 };;
{ .mfi; getf.sig r25=f61
xma.hu f64=f35,f122,f63
cmp.ltu p7,p0=r17,r16 }
{ .mfi; add r18=r18,r17
xma.lu f63=f35,f122,f63 };;
{ .mfi; getf.sig r26=f52
xma.hu f74=f35,f123,f73
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r18,r17
xma.lu f73=f35,f123,f73
add r18=r18,carry1 };;
{ .mfi;
xma.hu f84=f35,f124,f83
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r18,carry1
xma.lu f83=f35,f124,f83 };;
{ .mfi; st8 [r32]=r18,16
xma.hu f94=f35,f125,f93
(p7) add carry2=1,carry2 }
{ .mfi; xma.lu f93=f35,f125,f93 };;
{ .mfi; xma.hu f104=f35,f126,f103 }
{ .mfi; xma.lu f103=f35,f126,f103 };;
{ .mfi; xma.hu f114=f35,f127,f113 }
{ .mfi; mov carry1=0
xma.lu f113=f35,f127,f113
add r25=r25,r24 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r27=f43
xma.hu f45=f36,f120,f44
cmp.ltu p6,p0=r25,r24 }
{ .mfi; xma.lu f44=f36,f120,f44
add r26=r26,r25 };;
{ .mfi; getf.sig r16=f80
xma.hu f55=f36,f121,f54
(p6) add carry1=1,carry1 }
{ .mfi; xma.lu f54=f36,f121,f54 };;
{ .mfi; getf.sig r17=f71
xma.hu f65=f36,f122,f64
cmp.ltu p6,p0=r26,r25 }
{ .mfi; xma.lu f64=f36,f122,f64
add r27=r27,r26 };;
{ .mfi; getf.sig r18=f62
xma.hu f75=f36,f123,f74
(p6) add carry1=1,carry1 }
{ .mfi; cmp.ltu p6,p0=r27,r26
xma.lu f74=f36,f123,f74
add r27=r27,carry2 };;
{ .mfi; getf.sig r19=f53
xma.hu f85=f36,f124,f84
(p6) add carry1=1,carry1 }
{ .mfi; xma.lu f84=f36,f124,f84
cmp.ltu p6,p0=r27,carry2 };;
{ .mfi; st8 [r33]=r27,16
xma.hu f95=f36,f125,f94
(p6) add carry1=1,carry1 }
{ .mfi; xma.lu f94=f36,f125,f94 };;
{ .mfi; xma.hu f105=f36,f126,f104 }
{ .mfi; mov carry2=0
xma.lu f104=f36,f126,f104
add r17=r17,r16 };;
{ .mfi; xma.hu f115=f36,f127,f114
cmp.ltu p7,p0=r17,r16 }
{ .mfi; xma.lu f114=f36,f127,f114
add r18=r18,r17 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r20=f44
xma.hu f46=f37,f120,f45
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r18,r17
xma.lu f45=f37,f120,f45
add r19=r19,r18 };;
{ .mfi; getf.sig r24=f90
xma.hu f56=f37,f121,f55 }
{ .mfi; xma.lu f55=f37,f121,f55 };;
{ .mfi; getf.sig r25=f81
xma.hu f66=f37,f122,f65
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r19,r18
xma.lu f65=f37,f122,f65
add r20=r20,r19 };;
{ .mfi; getf.sig r26=f72
xma.hu f76=f37,f123,f75
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r20,r19
xma.lu f75=f37,f123,f75
add r20=r20,carry1 };;
{ .mfi; getf.sig r27=f63
xma.hu f86=f37,f124,f85
(p7) add carry2=1,carry2 }
{ .mfi; xma.lu f85=f37,f124,f85
cmp.ltu p7,p0=r20,carry1 };;
{ .mfi; getf.sig r28=f54
xma.hu f96=f37,f125,f95
(p7) add carry2=1,carry2 }
{ .mfi; st8 [r32]=r20,16
xma.lu f95=f37,f125,f95 };;
{ .mfi; xma.hu f106=f37,f126,f105 }
{ .mfi; mov carry1=0
xma.lu f105=f37,f126,f105
add r25=r25,r24 };;
{ .mfi; xma.hu f116=f37,f127,f115
cmp.ltu p6,p0=r25,r24 }
{ .mfi; xma.lu f115=f37,f127,f115
add r26=r26,r25 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r29=f45
xma.hu f47=f38,f120,f46
(p6) add carry1=1,carry1 }
{ .mfi; cmp.ltu p6,p0=r26,r25
xma.lu f46=f38,f120,f46
add r27=r27,r26 };;
{ .mfi; getf.sig r16=f100
xma.hu f57=f38,f121,f56
(p6) add carry1=1,carry1 }
{ .mfi; cmp.ltu p6,p0=r27,r26
xma.lu f56=f38,f121,f56
add r28=r28,r27 };;
{ .mfi; getf.sig r17=f91
xma.hu f67=f38,f122,f66
(p6) add carry1=1,carry1 }
{ .mfi; cmp.ltu p6,p0=r28,r27
xma.lu f66=f38,f122,f66
add r29=r29,r28 };;
{ .mfi; getf.sig r18=f82
xma.hu f77=f38,f123,f76
(p6) add carry1=1,carry1 }
{ .mfi; cmp.ltu p6,p0=r29,r28
xma.lu f76=f38,f123,f76
add r29=r29,carry2 };;
{ .mfi; getf.sig r19=f73
xma.hu f87=f38,f124,f86
(p6) add carry1=1,carry1 }
{ .mfi; xma.lu f86=f38,f124,f86
cmp.ltu p6,p0=r29,carry2 };;
{ .mfi; getf.sig r20=f64
xma.hu f97=f38,f125,f96
(p6) add carry1=1,carry1 }
{ .mfi; st8 [r33]=r29,16
xma.lu f96=f38,f125,f96 };;
{ .mfi; getf.sig r21=f55
xma.hu f107=f38,f126,f106 }
{ .mfi; mov carry2=0
xma.lu f106=f38,f126,f106
add r17=r17,r16 };;
{ .mfi; xma.hu f117=f38,f127,f116
cmp.ltu p7,p0=r17,r16 }
{ .mfi; xma.lu f116=f38,f127,f116
add r18=r18,r17 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r22=f46
xma.hu f48=f39,f120,f47
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r18,r17
xma.lu f47=f39,f120,f47
add r19=r19,r18 };;
{ .mfi; getf.sig r24=f110
xma.hu f58=f39,f121,f57
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r19,r18
xma.lu f57=f39,f121,f57
add r20=r20,r19 };;
{ .mfi; getf.sig r25=f101
xma.hu f68=f39,f122,f67
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r20,r19
xma.lu f67=f39,f122,f67
add r21=r21,r20 };;
{ .mfi; getf.sig r26=f92
xma.hu f78=f39,f123,f77
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r21,r20
xma.lu f77=f39,f123,f77
add r22=r22,r21 };;
{ .mfi; getf.sig r27=f83
xma.hu f88=f39,f124,f87
(p7) add carry2=1,carry2 }
{ .mfi; cmp.ltu p7,p0=r22,r21
xma.lu f87=f39,f124,f87
add r22=r22,carry1 };;
{ .mfi; getf.sig r28=f74
xma.hu f98=f39,f125,f97
(p7) add carry2=1,carry2 }
{ .mfi; xma.lu f97=f39,f125,f97
cmp.ltu p7,p0=r22,carry1 };;
{ .mfi; getf.sig r29=f65
xma.hu f108=f39,f126,f107
(p7) add carry2=1,carry2 }
{ .mfi; st8 [r32]=r22,16
xma.lu f107=f39,f126,f107 };;
{ .mfi; getf.sig r30=f56
xma.hu f118=f39,f127,f117 }
{ .mfi; xma.lu f117=f39,f127,f117 };;//
//-------------------------------------------------//
// Leaving muliplier's heaven... Quite a ride, huh?
{ .mii; getf.sig r31=f47
add r25=r25,r24
mov carry1=0 };;
{ .mii; getf.sig r16=f111
cmp.ltu p6,p0=r25,r24
add r26=r26,r25 };;
{ .mfb; getf.sig r17=f102 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,r25
add r27=r27,r26 };;
{ .mfb; nop.m 0x0 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r27,r26
add r28=r28,r27 };;
{ .mii; getf.sig r18=f93
add r17=r17,r16
mov carry3=0 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r28,r27
add r29=r29,r28 };;
{ .mii; getf.sig r19=f84
cmp.ltu p7,p0=r17,r16 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r29,r28
add r30=r30,r29 };;
{ .mii; getf.sig r20=f75
add r18=r18,r17 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r30,r29
add r31=r31,r30 };;
{ .mfb; getf.sig r21=f66 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r18,r17
add r19=r19,r18 }
{ .mfb; nop.m 0x0 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r31,r30
add r31=r31,carry2 };;
{ .mfb; getf.sig r22=f57 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r19,r18
add r20=r20,r19 }
{ .mfb; nop.m 0x0 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r31,carry2 };;
{ .mfb; getf.sig r23=f48 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r20,r19
add r21=r21,r20 }
{ .mii;
(p6) add carry1=1,carry1 }
{ .mfb; st8 [r33]=r31,16 };;
{ .mfb; getf.sig r24=f112 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r21,r20
add r22=r22,r21 };;
{ .mfb; getf.sig r25=f103 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r22,r21
add r23=r23,r22 };;
{ .mfb; getf.sig r26=f94 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r23,r22
add r23=r23,carry1 };;
{ .mfb; getf.sig r27=f85 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p8=r23,carry1};;
{ .mii; getf.sig r28=f76
add r25=r25,r24
mov carry1=0 }
{ .mii; st8 [r32]=r23,16
(p7) add carry2=1,carry3
(p8) add carry2=0,carry3 };;
{ .mfb; nop.m 0x0 }
{ .mii; getf.sig r29=f67
cmp.ltu p6,p0=r25,r24
add r26=r26,r25 };;
{ .mfb; getf.sig r30=f58 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,r25
add r27=r27,r26 };;
{ .mfb; getf.sig r16=f113 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r27,r26
add r28=r28,r27 };;
{ .mfb; getf.sig r17=f104 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r28,r27
add r29=r29,r28 };;
{ .mfb; getf.sig r18=f95 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r29,r28
add r30=r30,r29 };;
{ .mii; getf.sig r19=f86
add r17=r17,r16
mov carry3=0 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r30,r29
add r30=r30,carry2 };;
{ .mii; getf.sig r20=f77
cmp.ltu p7,p0=r17,r16
add r18=r18,r17 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r30,carry2 };;
{ .mfb; getf.sig r21=f68 }
{ .mii; st8 [r33]=r30,16
(p6) add carry1=1,carry1 };;
{ .mfb; getf.sig r24=f114 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r18,r17
add r19=r19,r18 };;
{ .mfb; getf.sig r25=f105 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r19,r18
add r20=r20,r19 };;
{ .mfb; getf.sig r26=f96 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r20,r19
add r21=r21,r20 };;
{ .mfb; getf.sig r27=f87 }
{ .mii; (p7) add carry3=1,carry3
cmp.ltu p7,p0=r21,r20
add r21=r21,carry1 };;
{ .mib; getf.sig r28=f78
add r25=r25,r24 }
{ .mib; (p7) add carry3=1,carry3
cmp.ltu p7,p8=r21,carry1};;
{ .mii; st8 [r32]=r21,16
(p7) add carry2=1,carry3
(p8) add carry2=0,carry3 }
{ .mii; mov carry1=0
cmp.ltu p6,p0=r25,r24
add r26=r26,r25 };;
{ .mfb; getf.sig r16=f115 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,r25
add r27=r27,r26 };;
{ .mfb; getf.sig r17=f106 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r27,r26
add r28=r28,r27 };;
{ .mfb; getf.sig r18=f97 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r28,r27
add r28=r28,carry2 };;
{ .mib; getf.sig r19=f88
add r17=r17,r16 }
{ .mib;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r28,carry2 };;
{ .mii; st8 [r33]=r28,16
(p6) add carry1=1,carry1 }
{ .mii; mov carry2=0
cmp.ltu p7,p0=r17,r16
add r18=r18,r17 };;
{ .mfb; getf.sig r24=f116 }
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r18,r17
add r19=r19,r18 };;
{ .mfb; getf.sig r25=f107 }
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r19,r18
add r19=r19,carry1 };;
{ .mfb; getf.sig r26=f98 }
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r19,carry1};;
{ .mii; st8 [r32]=r19,16
(p7) add carry2=1,carry2 }
{ .mfb; add r25=r25,r24 };;
{ .mfb; getf.sig r16=f117 }
{ .mii; mov carry1=0
cmp.ltu p6,p0=r25,r24
add r26=r26,r25 };;
{ .mfb; getf.sig r17=f108 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,r25
add r26=r26,carry2 };;
{ .mfb; nop.m 0x0 }
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,carry2 };;
{ .mii; st8 [r33]=r26,16
(p6) add carry1=1,carry1 }
{ .mfb; add r17=r17,r16 };;
{ .mfb; getf.sig r24=f118 }
{ .mii; mov carry2=0
cmp.ltu p7,p0=r17,r16
add r17=r17,carry1 };;
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r17,carry1};;
{ .mii; st8 [r32]=r17
(p7) add carry2=1,carry2 };;
{ .mfb; add r24=r24,carry2 };;
{ .mib; st8 [r33]=r24 }
{ .mib; rum 1<<5 // clear um.mfh
br.ret.sptk.many b0 };;
.endp bn_mul_comba8#
#undef carry3
#undef carry2
#undef carry1
#endif
#if 1
// It's possible to make it faster (see comment to bn_sqr_comba8), but
// I reckon it doesn't worth the effort. Basically because the routine
// (actually both of them) practically never called... So I just play
// same trick as with bn_sqr_comba8.
//
// void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
//
.global bn_sqr_comba4#
.proc bn_sqr_comba4#
.align 64
bn_sqr_comba4:
.prologue
.save ar.pfs,r2
#if defined(_HPUX_SOURCE) && !defined(_LP64)
{ .mii; alloc r2=ar.pfs,2,1,0,0
addp4 r32=0,r32
addp4 r33=0,r33 };;
{ .mii;
#else
{ .mii; alloc r2=ar.pfs,2,1,0,0
#endif
mov r34=r33
add r14=8,r33 };;
.body
{ .mii; add r17=8,r34
add r15=16,r33
add r18=16,r34 }
{ .mfb; add r16=24,r33
br .L_cheat_entry_point4 };;
.endp bn_sqr_comba4#
#endif
#if 1
// Runs in ~115 cycles and ~4.5 times faster than C. Well, whatever...
//
// void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
//
#define carry1 r14
#define carry2 r15
.global bn_mul_comba4#
.proc bn_mul_comba4#
.align 64
bn_mul_comba4:
.prologue
.save ar.pfs,r2
#if defined(_HPUX_SOURCE) && !defined(_LP64)
{ .mii; alloc r2=ar.pfs,3,0,0,0
addp4 r33=0,r33
addp4 r34=0,r34 };;
{ .mii; addp4 r32=0,r32
#else
{ .mii; alloc r2=ar.pfs,3,0,0,0
#endif
add r14=8,r33
add r17=8,r34 }
.body
{ .mii; add r15=16,r33
add r18=16,r34
add r16=24,r33 };;
.L_cheat_entry_point4:
{ .mmi; add r19=24,r34
ldf8 f32=[r33] }
{ .mmi; ldf8 f120=[r34]
ldf8 f121=[r17] };;
{ .mmi; ldf8 f122=[r18]
ldf8 f123=[r19] }
{ .mmi; ldf8 f33=[r14]
ldf8 f34=[r15] }
{ .mfi; ldf8 f35=[r16]
xma.hu f41=f32,f120,f0 }
{ .mfi; xma.lu f40=f32,f120,f0 };;
{ .mfi; xma.hu f51=f32,f121,f0 }
{ .mfi; xma.lu f50=f32,f121,f0 };;
{ .mfi; xma.hu f61=f32,f122,f0 }
{ .mfi; xma.lu f60=f32,f122,f0 };;
{ .mfi; xma.hu f71=f32,f123,f0 }
{ .mfi; xma.lu f70=f32,f123,f0 };;//
// Major stall takes place here, and 3 more places below. Result from
// first xma is not available for another 3 ticks.
{ .mfi; getf.sig r16=f40
xma.hu f42=f33,f120,f41
add r33=8,r32 }
{ .mfi; xma.lu f41=f33,f120,f41 };;
{ .mfi; getf.sig r24=f50
xma.hu f52=f33,f121,f51 }
{ .mfi; xma.lu f51=f33,f121,f51 };;
{ .mfi; st8 [r32]=r16,16
xma.hu f62=f33,f122,f61 }
{ .mfi; xma.lu f61=f33,f122,f61 };;
{ .mfi; xma.hu f72=f33,f123,f71 }
{ .mfi; xma.lu f71=f33,f123,f71 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r25=f41
xma.hu f43=f34,f120,f42 }
{ .mfi; xma.lu f42=f34,f120,f42 };;
{ .mfi; getf.sig r16=f60
xma.hu f53=f34,f121,f52 }
{ .mfi; xma.lu f52=f34,f121,f52 };;
{ .mfi; getf.sig r17=f51
xma.hu f63=f34,f122,f62
add r25=r25,r24 }
{ .mfi; mov carry1=0
xma.lu f62=f34,f122,f62 };;
{ .mfi; st8 [r33]=r25,16
xma.hu f73=f34,f123,f72
cmp.ltu p6,p0=r25,r24 }
{ .mfi; xma.lu f72=f34,f123,f72 };;//
//-------------------------------------------------//
{ .mfi; getf.sig r18=f42
xma.hu f44=f35,f120,f43
(p6) add carry1=1,carry1 }
{ .mfi; add r17=r17,r16
xma.lu f43=f35,f120,f43
mov carry2=0 };;
{ .mfi; getf.sig r24=f70
xma.hu f54=f35,f121,f53
cmp.ltu p7,p0=r17,r16 }
{ .mfi; xma.lu f53=f35,f121,f53 };;
{ .mfi; getf.sig r25=f61
xma.hu f64=f35,f122,f63
add r18=r18,r17 }
{ .mfi; xma.lu f63=f35,f122,f63
(p7) add carry2=1,carry2 };;
{ .mfi; getf.sig r26=f52
xma.hu f74=f35,f123,f73
cmp.ltu p7,p0=r18,r17 }
{ .mfi; xma.lu f73=f35,f123,f73
add r18=r18,carry1 };;
//-------------------------------------------------//
{ .mii; st8 [r32]=r18,16
(p7) add carry2=1,carry2
cmp.ltu p7,p0=r18,carry1 };;
{ .mfi; getf.sig r27=f43 // last major stall
(p7) add carry2=1,carry2 };;
{ .mii; getf.sig r16=f71
add r25=r25,r24
mov carry1=0 };;
{ .mii; getf.sig r17=f62
cmp.ltu p6,p0=r25,r24
add r26=r26,r25 };;
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,r25
add r27=r27,r26 };;
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r27,r26
add r27=r27,carry2 };;
{ .mii; getf.sig r18=f53
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r27,carry2 };;
{ .mfi; st8 [r33]=r27,16
(p6) add carry1=1,carry1 }
{ .mii; getf.sig r19=f44
add r17=r17,r16
mov carry2=0 };;
{ .mii; getf.sig r24=f72
cmp.ltu p7,p0=r17,r16
add r18=r18,r17 };;
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r18,r17
add r19=r19,r18 };;
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r19,r18
add r19=r19,carry1 };;
{ .mii; getf.sig r25=f63
(p7) add carry2=1,carry2
cmp.ltu p7,p0=r19,carry1};;
{ .mii; st8 [r32]=r19,16
(p7) add carry2=1,carry2 }
{ .mii; getf.sig r26=f54
add r25=r25,r24
mov carry1=0 };;
{ .mii; getf.sig r16=f73
cmp.ltu p6,p0=r25,r24
add r26=r26,r25 };;
{ .mii;
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,r25
add r26=r26,carry2 };;
{ .mii; getf.sig r17=f64
(p6) add carry1=1,carry1
cmp.ltu p6,p0=r26,carry2 };;
{ .mii; st8 [r33]=r26,16
(p6) add carry1=1,carry1 }
{ .mii; getf.sig r24=f74
add r17=r17,r16
mov carry2=0 };;
{ .mii; cmp.ltu p7,p0=r17,r16
add r17=r17,carry1 };;
{ .mii; (p7) add carry2=1,carry2
cmp.ltu p7,p0=r17,carry1};;
{ .mii; st8 [r32]=r17,16
(p7) add carry2=1,carry2 };;
{ .mii; add r24=r24,carry2 };;
{ .mii; st8 [r33]=r24 }
{ .mib; rum 1<<5 // clear um.mfh
br.ret.sptk.many b0 };;
.endp bn_mul_comba4#
#undef carry2
#undef carry1
#endif
#if 1
//
// BN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)
//
// In the nutshell it's a port of my MIPS III/IV implementation.
//
#define AT r14
#define H r16
#define HH r20
#define L r17
#define D r18
#define DH r22
#define I r21
#if 0
// Some preprocessors (most notably HP-UX) appear to be allergic to
// macros enclosed to parenthesis [as these three were].
#define cont p16
#define break p0 // p20
#define equ p24
#else
cont=p16
break=p0
equ=p24
#endif
.global abort#
.global bn_div_words#
.proc bn_div_words#
.align 64
bn_div_words:
.prologue
.save ar.pfs,r2
{ .mii; alloc r2=ar.pfs,3,5,0,8
.save b0,r3
mov r3=b0
.save pr,r10
mov r10=pr };;
{ .mmb; cmp.eq p6,p0=r34,r0
mov r8=-1
(p6) br.ret.spnt.many b0 };;
.body
{ .mii; mov H=r32 // save h
mov ar.ec=0 // don't rotate at exit
mov pr.rot=0 }
{ .mii; mov L=r33 // save l
mov r36=r0 };;
.L_divw_shift: // -vv- note signed comparison
{ .mfi; (p0) cmp.lt p16,p0=r0,r34 // d
(p0) shladd r33=r34,1,r0 }
{ .mfb; (p0) add r35=1,r36
(p0) nop.f 0x0
(p16) br.wtop.dpnt .L_divw_shift };;
{ .mii; mov D=r34
shr.u DH=r34,32
sub r35=64,r36 };;
{ .mii; setf.sig f7=DH
shr.u AT=H,r35
mov I=r36 };;
{ .mib; cmp.ne p6,p0=r0,AT
shl H=H,r36
(p6) br.call.spnt.clr b0=abort };; // overflow, die...
{ .mfi; fcvt.xuf.s1 f7=f7
shr.u AT=L,r35 };;
{ .mii; shl L=L,r36
or H=H,AT };;
{ .mii; nop.m 0x0
cmp.leu p6,p0=D,H;;
(p6) sub H=H,D }
{ .mlx; setf.sig f14=D
movl AT=0xffffffff };;
///////////////////////////////////////////////////////////
{ .mii; setf.sig f6=H
shr.u HH=H,32;;
cmp.eq p6,p7=HH,DH };;
{ .mfb;
(p6) setf.sig f8=AT
(p7) fcvt.xuf.s1 f6=f6
(p7) br.call.sptk b6=.L_udiv64_32_b6 };;
{ .mfi; getf.sig r33=f8 // q
xmpy.lu f9=f8,f14 }
{ .mfi; xmpy.hu f10=f8,f14
shrp H=H,L,32 };;
{ .mmi; getf.sig r35=f9 // tl
getf.sig r31=f10 };; // th
.L_divw_1st_iter:
{ .mii; (p0) add r32=-1,r33
(p0) cmp.eq equ,cont=HH,r31 };;
{ .mii; (p0) cmp.ltu p8,p0=r35,D
(p0) sub r34=r35,D
(equ) cmp.leu break,cont=r35,H };;
{ .mib; (cont) cmp.leu cont,break=HH,r31
(p8) add r31=-1,r31
(cont) br.wtop.spnt .L_divw_1st_iter };;
///////////////////////////////////////////////////////////
{ .mii; sub H=H,r35
shl r8=r33,32
shl L=L,32 };;
///////////////////////////////////////////////////////////
{ .mii; setf.sig f6=H
shr.u HH=H,32;;
cmp.eq p6,p7=HH,DH };;
{ .mfb;
(p6) setf.sig f8=AT
(p7) fcvt.xuf.s1 f6=f6
(p7) br.call.sptk b6=.L_udiv64_32_b6 };;
{ .mfi; getf.sig r33=f8 // q
xmpy.lu f9=f8,f14 }
{ .mfi; xmpy.hu f10=f8,f14
shrp H=H,L,32 };;
{ .mmi; getf.sig r35=f9 // tl
getf.sig r31=f10 };; // th
.L_divw_2nd_iter:
{ .mii; (p0) add r32=-1,r33
(p0) cmp.eq equ,cont=HH,r31 };;
{ .mii; (p0) cmp.ltu p8,p0=r35,D
(p0) sub r34=r35,D
(equ) cmp.leu break,cont=r35,H };;
{ .mib; (cont) cmp.leu cont,break=HH,r31
(p8) add r31=-1,r31
(cont) br.wtop.spnt .L_divw_2nd_iter };;
///////////////////////////////////////////////////////////
{ .mii; sub H=H,r35
or r8=r8,r33
mov ar.pfs=r2 };;
{ .mii; shr.u r9=H,I // remainder if anybody wants it
mov pr=r10,0x1ffff }
{ .mfb; br.ret.sptk.many b0 };;
// Unsigned 64 by 32 (well, by 64 for the moment) bit integer division
// procedure.
//
// inputs: f6 = (double)a, f7 = (double)b
// output: f8 = (int)(a/b)
// clobbered: f8,f9,f10,f11,pred
pred=p15
// One can argue that this snippet is copyrighted to Intel
// Corporation, as it's essentially identical to one of those
// found in "Divide, Square Root and Remainder" section at
// http://www.intel.com/software/products/opensource/libraries/num.htm.
// Yes, I admit that the referred code was used as template,
// but after I realized that there hardly is any other instruction
// sequence which would perform this operation. I mean I figure that
// any independent attempt to implement high-performance division
// will result in code virtually identical to the Intel code. It
// should be noted though that below division kernel is 1 cycle
// faster than Intel one (note commented splits:-), not to mention
// original prologue (rather lack of one) and epilogue.
.align 32
.skip 16
.L_udiv64_32_b6:
frcpa.s1 f8,pred=f6,f7;; // [0] y0 = 1 / b
(pred) fnma.s1 f9=f7,f8,f1 // [5] e0 = 1 - b * y0
(pred) fmpy.s1 f10=f6,f8;; // [5] q0 = a * y0
(pred) fmpy.s1 f11=f9,f9 // [10] e1 = e0 * e0
(pred) fma.s1 f10=f9,f10,f10;; // [10] q1 = q0 + e0 * q0
(pred) fma.s1 f8=f9,f8,f8 //;; // [15] y1 = y0 + e0 * y0
(pred) fma.s1 f9=f11,f10,f10;; // [15] q2 = q1 + e1 * q1
(pred) fma.s1 f8=f11,f8,f8 //;; // [20] y2 = y1 + e1 * y1
(pred) fnma.s1 f10=f7,f9,f6;; // [20] r2 = a - b * q2
(pred) fma.s1 f8=f10,f8,f9;; // [25] q3 = q2 + r2 * y2
fcvt.fxu.trunc.s1 f8=f8 // [30] q = trunc(q3)
br.ret.sptk.many b6;;
.endp bn_div_words#
#endif
|
ntu-ssl/rr-artifact | 46,995 | openssl-1.1.0l/crypto/bn/asm/pa-risc2W.s | ; Copyright 2000-2016 The OpenSSL Project Authors. All Rights Reserved.
;
; Licensed under the OpenSSL license (the "License"). You may not use
; this file except in compliance with the License. You can obtain a copy
; in the file LICENSE in the source distribution or at
; https://www.openssl.org/source/license.html
;
; PA-RISC 64-bit implementation of bn_asm code
;
; This code is approximately 2x faster than the C version
; for RSA/DSA.
;
; See http://devresource.hp.com/ for more details on the PA-RISC
; architecture. Also see the book "PA-RISC 2.0 Architecture"
; by Gerry Kane for information on the instruction set architecture.
;
; Code written by Chris Ruemmler (with some help from the HP C
; compiler).
;
; The code compiles with HP's assembler
;
.level 2.0W
.space $TEXT$
.subspa $CODE$,QUAD=0,ALIGN=8,ACCESS=0x2c,CODE_ONLY
;
; Global Register definitions used for the routines.
;
; Some information about HP's runtime architecture for 64-bits.
;
; "Caller save" means the calling function must save the register
; if it wants the register to be preserved.
; "Callee save" means if a function uses the register, it must save
; the value before using it.
;
; For the floating point registers
;
; "caller save" registers: fr4-fr11, fr22-fr31
; "callee save" registers: fr12-fr21
; "special" registers: fr0-fr3 (status and exception registers)
;
; For the integer registers
; value zero : r0
; "caller save" registers: r1,r19-r26
; "callee save" registers: r3-r18
; return register : r2 (rp)
; return values ; r28 (ret0,ret1)
; Stack pointer ; r30 (sp)
; global data pointer ; r27 (dp)
; argument pointer ; r29 (ap)
; millicode return ptr ; r31 (also a caller save register)
;
; Arguments to the routines
;
r_ptr .reg %r26
a_ptr .reg %r25
b_ptr .reg %r24
num .reg %r24
w .reg %r23
n .reg %r23
;
; Globals used in some routines
;
top_overflow .reg %r29
high_mask .reg %r22 ; value 0xffffffff80000000L
;------------------------------------------------------------------------------
;
; bn_mul_add_words
;
;BN_ULONG bn_mul_add_words(BN_ULONG *r_ptr, BN_ULONG *a_ptr,
; int num, BN_ULONG w)
;
; arg0 = r_ptr
; arg1 = a_ptr
; arg2 = num
; arg3 = w
;
; Local register definitions
;
fm1 .reg %fr22
fm .reg %fr23
ht_temp .reg %fr24
ht_temp_1 .reg %fr25
lt_temp .reg %fr26
lt_temp_1 .reg %fr27
fm1_1 .reg %fr28
fm_1 .reg %fr29
fw_h .reg %fr7L
fw_l .reg %fr7R
fw .reg %fr7
fht_0 .reg %fr8L
flt_0 .reg %fr8R
t_float_0 .reg %fr8
fht_1 .reg %fr9L
flt_1 .reg %fr9R
t_float_1 .reg %fr9
tmp_0 .reg %r31
tmp_1 .reg %r21
m_0 .reg %r20
m_1 .reg %r19
ht_0 .reg %r1
ht_1 .reg %r3
lt_0 .reg %r4
lt_1 .reg %r5
m1_0 .reg %r6
m1_1 .reg %r7
rp_val .reg %r8
rp_val_1 .reg %r9
bn_mul_add_words
.export bn_mul_add_words,entry,NO_RELOCATION,LONG_RETURN
.proc
.callinfo frame=128
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
NOP ; Needed to make the loop 16-byte aligned
NOP ; Needed to make the loop 16-byte aligned
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
STD %r7,32(%sp) ; save r7
STD %r8,40(%sp) ; save r8
STD %r9,48(%sp) ; save r9
COPY %r0,%ret0 ; return 0 by default
DEPDI,Z 1,31,1,top_overflow ; top_overflow = 1 << 32
STD w,56(%sp) ; store w on stack
CMPIB,>= 0,num,bn_mul_add_words_exit ; if (num <= 0) then exit
LDO 128(%sp),%sp ; bump stack
;
; The loop is unrolled twice, so if there is only 1 number
; then go straight to the cleanup code.
;
CMPIB,= 1,num,bn_mul_add_words_single_top
FLDD -72(%sp),fw ; load up w into fp register fw (fw_h/fw_l)
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
; PA-RISC 2.0 chips have two fully pipelined multipliers, thus
; two 32-bit mutiplies can be issued per cycle.
;
bn_mul_add_words_unroll2
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)
LDD 0(r_ptr),rp_val ; rp[0]
LDD 8(r_ptr),rp_val_1 ; rp[1]
XMPYU fht_0,fw_l,fm1 ; m1[0] = fht_0*fw_l
XMPYU fht_1,fw_l,fm1_1 ; m1[1] = fht_1*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1[0]
FSTD fm1_1,-48(%sp) ; -48(sp) = m1[1]
XMPYU flt_0,fw_h,fm ; m[0] = flt_0*fw_h
XMPYU flt_1,fw_h,fm_1 ; m[1] = flt_1*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m[0]
FSTD fm_1,-40(%sp) ; -40(sp) = m[1]
XMPYU fht_0,fw_h,ht_temp ; ht_temp = fht_0*fw_h
XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp_1 = fht_1*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht_temp
FSTD ht_temp_1,-56(%sp) ; -56(sp) = ht_temp_1
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt_temp
FSTD lt_temp_1,-64(%sp) ; -64(sp) = lt_temp_1
LDD -8(%sp),m_0 ; m[0]
LDD -40(%sp),m_1 ; m[1]
LDD -16(%sp),m1_0 ; m1[0]
LDD -48(%sp),m1_1 ; m1[1]
LDD -24(%sp),ht_0 ; ht[0]
LDD -56(%sp),ht_1 ; ht[1]
ADD,L m1_0,m_0,tmp_0 ; tmp_0 = m[0] + m1[0];
ADD,L m1_1,m_1,tmp_1 ; tmp_1 = m[1] + m1[1];
LDD -32(%sp),lt_0
LDD -64(%sp),lt_1
CMPCLR,*>>= tmp_0,m1_0, %r0 ; if (m[0] < m1[0])
ADD,L ht_0,top_overflow,ht_0 ; ht[0] += (1<<32)
CMPCLR,*>>= tmp_1,m1_1,%r0 ; if (m[1] < m1[1])
ADD,L ht_1,top_overflow,ht_1 ; ht[1] += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m[0]>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1[0] = m[0]<<32
EXTRD,U tmp_1,31,32,m_1 ; m[1]>>32
DEPD,Z tmp_1,31,32,m1_1 ; m1[1] = m[1]<<32
ADD,L ht_0,m_0,ht_0 ; ht[0]+= (m[0]>>32)
ADD,L ht_1,m_1,ht_1 ; ht[1]+= (m[1]>>32)
ADD lt_0,m1_0,lt_0 ; lt[0] = lt[0]+m1[0];
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
ADD lt_1,m1_1,lt_1 ; lt[1] = lt[1]+m1[1];
ADD,DC ht_1,%r0,ht_1 ; ht[1]++
ADD %ret0,lt_0,lt_0 ; lt[0] = lt[0] + c;
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
ADD lt_0,rp_val,lt_0 ; lt[0] = lt[0]+rp[0]
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
LDO -2(num),num ; num = num - 2;
ADD ht_0,lt_1,lt_1 ; lt[1] = lt[1] + ht_0 (c);
ADD,DC ht_1,%r0,ht_1 ; ht[1]++
STD lt_0,0(r_ptr) ; rp[0] = lt[0]
ADD lt_1,rp_val_1,lt_1 ; lt[1] = lt[1]+rp[1]
ADD,DC ht_1,%r0,%ret0 ; ht[1]++
LDO 16(a_ptr),a_ptr ; a_ptr += 2
STD lt_1,8(r_ptr) ; rp[1] = lt[1]
CMPIB,<= 2,num,bn_mul_add_words_unroll2 ; go again if more to do
LDO 16(r_ptr),r_ptr ; r_ptr += 2
CMPIB,=,N 0,num,bn_mul_add_words_exit ; are we done, or cleanup last one
;
; Top of loop aligned on 64-byte boundary
;
bn_mul_add_words_single_top
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
LDD 0(r_ptr),rp_val ; rp[0]
LDO 8(a_ptr),a_ptr ; a_ptr++
XMPYU fht_0,fw_l,fm1 ; m1 = ht*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1
XMPYU flt_0,fw_h,fm ; m = lt*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m
XMPYU fht_0,fw_h,ht_temp ; ht_temp = ht*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt
LDD -8(%sp),m_0
LDD -16(%sp),m1_0 ; m1 = temp1
ADD,L m_0,m1_0,tmp_0 ; tmp_0 = m + m1;
LDD -24(%sp),ht_0
LDD -32(%sp),lt_0
CMPCLR,*>>= tmp_0,m1_0,%r0 ; if (m < m1)
ADD,L ht_0,top_overflow,ht_0 ; ht += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1 = m<<32
ADD,L ht_0,m_0,ht_0 ; ht+= (m>>32)
ADD lt_0,m1_0,tmp_0 ; tmp_0 = lt+m1;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD %ret0,tmp_0,lt_0 ; lt = lt + c;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD lt_0,rp_val,lt_0 ; lt = lt+rp[0]
ADD,DC ht_0,%r0,%ret0 ; ht++
STD lt_0,0(r_ptr) ; rp[0] = lt
bn_mul_add_words_exit
.EXIT
LDD -80(%sp),%r9 ; restore r9
LDD -88(%sp),%r8 ; restore r8
LDD -96(%sp),%r7 ; restore r7
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3 ; restore r3
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
;
; arg0 = rp
; arg1 = ap
; arg2 = num
; arg3 = w
bn_mul_words
.proc
.callinfo frame=128
.entry
.EXPORT bn_mul_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
STD %r7,32(%sp) ; save r7
COPY %r0,%ret0 ; return 0 by default
DEPDI,Z 1,31,1,top_overflow ; top_overflow = 1 << 32
STD w,56(%sp) ; w on stack
CMPIB,>= 0,num,bn_mul_words_exit
LDO 128(%sp),%sp ; bump stack
;
; See if only 1 word to do, thus just do cleanup
;
CMPIB,= 1,num,bn_mul_words_single_top
FLDD -72(%sp),fw ; load up w into fp register fw (fw_h/fw_l)
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
; PA-RISC 2.0 chips have two fully pipelined multipliers, thus
; two 32-bit mutiplies can be issued per cycle.
;
bn_mul_words_unroll2
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)
XMPYU fht_0,fw_l,fm1 ; m1[0] = fht_0*fw_l
XMPYU fht_1,fw_l,fm1_1 ; m1[1] = ht*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1
FSTD fm1_1,-48(%sp) ; -48(sp) = m1
XMPYU flt_0,fw_h,fm ; m = lt*fw_h
XMPYU flt_1,fw_h,fm_1 ; m = lt*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m
FSTD fm_1,-40(%sp) ; -40(sp) = m
XMPYU fht_0,fw_h,ht_temp ; ht_temp = fht_0*fw_h
XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp = ht*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht
FSTD ht_temp_1,-56(%sp) ; -56(sp) = ht
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt
FSTD lt_temp_1,-64(%sp) ; -64(sp) = lt
LDD -8(%sp),m_0
LDD -40(%sp),m_1
LDD -16(%sp),m1_0
LDD -48(%sp),m1_1
LDD -24(%sp),ht_0
LDD -56(%sp),ht_1
ADD,L m1_0,m_0,tmp_0 ; tmp_0 = m + m1;
ADD,L m1_1,m_1,tmp_1 ; tmp_1 = m + m1;
LDD -32(%sp),lt_0
LDD -64(%sp),lt_1
CMPCLR,*>>= tmp_0,m1_0, %r0 ; if (m < m1)
ADD,L ht_0,top_overflow,ht_0 ; ht += (1<<32)
CMPCLR,*>>= tmp_1,m1_1,%r0 ; if (m < m1)
ADD,L ht_1,top_overflow,ht_1 ; ht += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1 = m<<32
EXTRD,U tmp_1,31,32,m_1 ; m>>32
DEPD,Z tmp_1,31,32,m1_1 ; m1 = m<<32
ADD,L ht_0,m_0,ht_0 ; ht+= (m>>32)
ADD,L ht_1,m_1,ht_1 ; ht+= (m>>32)
ADD lt_0,m1_0,lt_0 ; lt = lt+m1;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD lt_1,m1_1,lt_1 ; lt = lt+m1;
ADD,DC ht_1,%r0,ht_1 ; ht++
ADD %ret0,lt_0,lt_0 ; lt = lt + c (ret0);
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD ht_0,lt_1,lt_1 ; lt = lt + c (ht_0)
ADD,DC ht_1,%r0,ht_1 ; ht++
STD lt_0,0(r_ptr) ; rp[0] = lt
STD lt_1,8(r_ptr) ; rp[1] = lt
COPY ht_1,%ret0 ; carry = ht
LDO -2(num),num ; num = num - 2;
LDO 16(a_ptr),a_ptr ; ap += 2
CMPIB,<= 2,num,bn_mul_words_unroll2
LDO 16(r_ptr),r_ptr ; rp++
CMPIB,=,N 0,num,bn_mul_words_exit ; are we done?
;
; Top of loop aligned on 64-byte boundary
;
bn_mul_words_single_top
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
XMPYU fht_0,fw_l,fm1 ; m1 = ht*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1
XMPYU flt_0,fw_h,fm ; m = lt*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m
XMPYU fht_0,fw_h,ht_temp ; ht_temp = ht*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt
LDD -8(%sp),m_0
LDD -16(%sp),m1_0
ADD,L m_0,m1_0,tmp_0 ; tmp_0 = m + m1;
LDD -24(%sp),ht_0
LDD -32(%sp),lt_0
CMPCLR,*>>= tmp_0,m1_0,%r0 ; if (m < m1)
ADD,L ht_0,top_overflow,ht_0 ; ht += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1 = m<<32
ADD,L ht_0,m_0,ht_0 ; ht+= (m>>32)
ADD lt_0,m1_0,lt_0 ; lt= lt+m1;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD %ret0,lt_0,lt_0 ; lt = lt + c;
ADD,DC ht_0,%r0,ht_0 ; ht++
COPY ht_0,%ret0 ; copy carry
STD lt_0,0(r_ptr) ; rp[0] = lt
bn_mul_words_exit
.EXIT
LDD -96(%sp),%r7 ; restore r7
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3 ; restore r3
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
;
; arg0 = rp
; arg1 = ap
; arg2 = num
;
bn_sqr_words
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_sqr_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
NOP
STD %r5,16(%sp) ; save r5
CMPIB,>= 0,num,bn_sqr_words_exit
LDO 128(%sp),%sp ; bump stack
;
; If only 1, the goto straight to cleanup
;
CMPIB,= 1,num,bn_sqr_words_single_top
DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
bn_sqr_words_unroll2
FLDD 0(a_ptr),t_float_0 ; a[0]
FLDD 8(a_ptr),t_float_1 ; a[1]
XMPYU fht_0,flt_0,fm ; m[0]
XMPYU fht_1,flt_1,fm_1 ; m[1]
FSTD fm,-24(%sp) ; store m[0]
FSTD fm_1,-56(%sp) ; store m[1]
XMPYU flt_0,flt_0,lt_temp ; lt[0]
XMPYU flt_1,flt_1,lt_temp_1 ; lt[1]
FSTD lt_temp,-16(%sp) ; store lt[0]
FSTD lt_temp_1,-48(%sp) ; store lt[1]
XMPYU fht_0,fht_0,ht_temp ; ht[0]
XMPYU fht_1,fht_1,ht_temp_1 ; ht[1]
FSTD ht_temp,-8(%sp) ; store ht[0]
FSTD ht_temp_1,-40(%sp) ; store ht[1]
LDD -24(%sp),m_0
LDD -56(%sp),m_1
AND m_0,high_mask,tmp_0 ; m[0] & Mask
AND m_1,high_mask,tmp_1 ; m[1] & Mask
DEPD,Z m_0,30,31,m_0 ; m[0] << 32+1
DEPD,Z m_1,30,31,m_1 ; m[1] << 32+1
LDD -16(%sp),lt_0
LDD -48(%sp),lt_1
EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m[0]&Mask >> 32-1
EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 = m[1]&Mask >> 32-1
LDD -8(%sp),ht_0
LDD -40(%sp),ht_1
ADD,L ht_0,tmp_0,ht_0 ; ht[0] += tmp_0
ADD,L ht_1,tmp_1,ht_1 ; ht[1] += tmp_1
ADD lt_0,m_0,lt_0 ; lt = lt+m
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
STD lt_0,0(r_ptr) ; rp[0] = lt[0]
STD ht_0,8(r_ptr) ; rp[1] = ht[1]
ADD lt_1,m_1,lt_1 ; lt = lt+m
ADD,DC ht_1,%r0,ht_1 ; ht[1]++
STD lt_1,16(r_ptr) ; rp[2] = lt[1]
STD ht_1,24(r_ptr) ; rp[3] = ht[1]
LDO -2(num),num ; num = num - 2;
LDO 16(a_ptr),a_ptr ; ap += 2
CMPIB,<= 2,num,bn_sqr_words_unroll2
LDO 32(r_ptr),r_ptr ; rp += 4
CMPIB,=,N 0,num,bn_sqr_words_exit ; are we done?
;
; Top of loop aligned on 64-byte boundary
;
bn_sqr_words_single_top
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
XMPYU fht_0,flt_0,fm ; m
FSTD fm,-24(%sp) ; store m
XMPYU flt_0,flt_0,lt_temp ; lt
FSTD lt_temp,-16(%sp) ; store lt
XMPYU fht_0,fht_0,ht_temp ; ht
FSTD ht_temp,-8(%sp) ; store ht
LDD -24(%sp),m_0 ; load m
AND m_0,high_mask,tmp_0 ; m & Mask
DEPD,Z m_0,30,31,m_0 ; m << 32+1
LDD -16(%sp),lt_0 ; lt
LDD -8(%sp),ht_0 ; ht
EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m&Mask >> 32-1
ADD m_0,lt_0,lt_0 ; lt = lt+m
ADD,L ht_0,tmp_0,ht_0 ; ht += tmp_0
ADD,DC ht_0,%r0,ht_0 ; ht++
STD lt_0,0(r_ptr) ; rp[0] = lt
STD ht_0,8(r_ptr) ; rp[1] = ht
bn_sqr_words_exit
.EXIT
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;BN_ULONG bn_add_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)
;
; arg0 = rp
; arg1 = ap
; arg2 = bp
; arg3 = n
t .reg %r22
b .reg %r21
l .reg %r20
bn_add_words
.proc
.entry
.callinfo
.EXPORT bn_add_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.align 64
CMPIB,>= 0,n,bn_add_words_exit
COPY %r0,%ret0 ; return 0 by default
;
; If 2 or more numbers do the loop
;
CMPIB,= 1,n,bn_add_words_single_top
NOP
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
bn_add_words_unroll2
LDD 0(a_ptr),t
LDD 0(b_ptr),b
ADD t,%ret0,t ; t = t+c;
ADD,DC %r0,%r0,%ret0 ; set c to carry
ADD t,b,l ; l = t + b[0]
ADD,DC %ret0,%r0,%ret0 ; c+= carry
STD l,0(r_ptr)
LDD 8(a_ptr),t
LDD 8(b_ptr),b
ADD t,%ret0,t ; t = t+c;
ADD,DC %r0,%r0,%ret0 ; set c to carry
ADD t,b,l ; l = t + b[0]
ADD,DC %ret0,%r0,%ret0 ; c+= carry
STD l,8(r_ptr)
LDO -2(n),n
LDO 16(a_ptr),a_ptr
LDO 16(b_ptr),b_ptr
CMPIB,<= 2,n,bn_add_words_unroll2
LDO 16(r_ptr),r_ptr
CMPIB,=,N 0,n,bn_add_words_exit ; are we done?
bn_add_words_single_top
LDD 0(a_ptr),t
LDD 0(b_ptr),b
ADD t,%ret0,t ; t = t+c;
ADD,DC %r0,%r0,%ret0 ; set c to carry (could use CMPCLR??)
ADD t,b,l ; l = t + b[0]
ADD,DC %ret0,%r0,%ret0 ; c+= carry
STD l,0(r_ptr)
bn_add_words_exit
.EXIT
BVE (%rp)
NOP
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;BN_ULONG bn_sub_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)
;
; arg0 = rp
; arg1 = ap
; arg2 = bp
; arg3 = n
t1 .reg %r22
t2 .reg %r21
sub_tmp1 .reg %r20
sub_tmp2 .reg %r19
bn_sub_words
.proc
.callinfo
.EXPORT bn_sub_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
CMPIB,>= 0,n,bn_sub_words_exit
COPY %r0,%ret0 ; return 0 by default
;
; If 2 or more numbers do the loop
;
CMPIB,= 1,n,bn_sub_words_single_top
NOP
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
bn_sub_words_unroll2
LDD 0(a_ptr),t1
LDD 0(b_ptr),t2
SUB t1,t2,sub_tmp1 ; t3 = t1-t2;
SUB sub_tmp1,%ret0,sub_tmp1 ; t3 = t3- c;
CMPCLR,*>> t1,t2,sub_tmp2 ; clear if t1 > t2
LDO 1(%r0),sub_tmp2
CMPCLR,*= t1,t2,%r0
COPY sub_tmp2,%ret0
STD sub_tmp1,0(r_ptr)
LDD 8(a_ptr),t1
LDD 8(b_ptr),t2
SUB t1,t2,sub_tmp1 ; t3 = t1-t2;
SUB sub_tmp1,%ret0,sub_tmp1 ; t3 = t3- c;
CMPCLR,*>> t1,t2,sub_tmp2 ; clear if t1 > t2
LDO 1(%r0),sub_tmp2
CMPCLR,*= t1,t2,%r0
COPY sub_tmp2,%ret0
STD sub_tmp1,8(r_ptr)
LDO -2(n),n
LDO 16(a_ptr),a_ptr
LDO 16(b_ptr),b_ptr
CMPIB,<= 2,n,bn_sub_words_unroll2
LDO 16(r_ptr),r_ptr
CMPIB,=,N 0,n,bn_sub_words_exit ; are we done?
bn_sub_words_single_top
LDD 0(a_ptr),t1
LDD 0(b_ptr),t2
SUB t1,t2,sub_tmp1 ; t3 = t1-t2;
SUB sub_tmp1,%ret0,sub_tmp1 ; t3 = t3- c;
CMPCLR,*>> t1,t2,sub_tmp2 ; clear if t1 > t2
LDO 1(%r0),sub_tmp2
CMPCLR,*= t1,t2,%r0
COPY sub_tmp2,%ret0
STD sub_tmp1,0(r_ptr)
bn_sub_words_exit
.EXIT
BVE (%rp)
NOP
.PROCEND ;in=23,24,25,26,29;out=28;
;------------------------------------------------------------------------------
;
; unsigned long bn_div_words(unsigned long h, unsigned long l, unsigned long d)
;
; arg0 = h
; arg1 = l
; arg2 = d
;
; This is mainly just modified assembly from the compiler, thus the
; lack of variable names.
;
;------------------------------------------------------------------------------
bn_div_words
.proc
.callinfo CALLER,FRAME=272,ENTRY_GR=%r10,SAVE_RP,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_div_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.IMPORT BN_num_bits_word,CODE,NO_RELOCATION
.IMPORT __iob,DATA
.IMPORT fprintf,CODE,NO_RELOCATION
.IMPORT abort,CODE,NO_RELOCATION
.IMPORT $$div2U,MILLICODE
.entry
STD %r2,-16(%r30)
STD,MA %r3,352(%r30)
STD %r4,-344(%r30)
STD %r5,-336(%r30)
STD %r6,-328(%r30)
STD %r7,-320(%r30)
STD %r8,-312(%r30)
STD %r9,-304(%r30)
STD %r10,-296(%r30)
STD %r27,-288(%r30) ; save gp
COPY %r24,%r3 ; save d
COPY %r26,%r4 ; save h (high 64-bits)
LDO -1(%r0),%ret0 ; return -1 by default
CMPB,*= %r0,%arg2,$D3 ; if (d == 0)
COPY %r25,%r5 ; save l (low 64-bits)
LDO -48(%r30),%r29 ; create ap
.CALL ;in=26,29;out=28;
B,L BN_num_bits_word,%r2
COPY %r3,%r26
LDD -288(%r30),%r27 ; restore gp
LDI 64,%r21
CMPB,= %r21,%ret0,$00000012 ;if (i == 64) (forward)
COPY %ret0,%r24 ; i
MTSARCM %r24
DEPDI,Z -1,%sar,1,%r29
CMPB,*<<,N %r29,%r4,bn_div_err_case ; if (h > 1<<i) (forward)
$00000012
SUBI 64,%r24,%r31 ; i = 64 - i;
CMPCLR,*<< %r4,%r3,%r0 ; if (h >= d)
SUB %r4,%r3,%r4 ; h -= d
CMPB,= %r31,%r0,$0000001A ; if (i)
COPY %r0,%r10 ; ret = 0
MTSARCM %r31 ; i to shift
DEPD,Z %r3,%sar,64,%r3 ; d <<= i;
SUBI 64,%r31,%r19 ; 64 - i; redundent
MTSAR %r19 ; (64 -i) to shift
SHRPD %r4,%r5,%sar,%r4 ; l>> (64-i)
MTSARCM %r31 ; i to shift
DEPD,Z %r5,%sar,64,%r5 ; l <<= i;
$0000001A
DEPDI,Z -1,31,32,%r19
EXTRD,U %r3,31,32,%r6 ; dh=(d&0xfff)>>32
EXTRD,U %r3,63,32,%r8 ; dl = d&0xffffff
LDO 2(%r0),%r9
STD %r3,-280(%r30) ; "d" to stack
$0000001C
DEPDI,Z -1,63,32,%r29 ;
EXTRD,U %r4,31,32,%r31 ; h >> 32
CMPB,*=,N %r31,%r6,$D2 ; if ((h>>32) != dh)(forward) div
COPY %r4,%r26
EXTRD,U %r4,31,32,%r25
COPY %r6,%r24
.CALL ;in=23,24,25,26;out=20,21,22,28,29; (MILLICALL)
B,L $$div2U,%r2
EXTRD,U %r6,31,32,%r23
DEPD %r28,31,32,%r29
$D2
STD %r29,-272(%r30) ; q
AND %r5,%r19,%r24 ; t & 0xffffffff00000000;
EXTRD,U %r24,31,32,%r24 ; ???
FLDD -272(%r30),%fr7 ; q
FLDD -280(%r30),%fr8 ; d
XMPYU %fr8L,%fr7L,%fr10
FSTD %fr10,-256(%r30)
XMPYU %fr8L,%fr7R,%fr22
FSTD %fr22,-264(%r30)
XMPYU %fr8R,%fr7L,%fr11
XMPYU %fr8R,%fr7R,%fr23
FSTD %fr11,-232(%r30)
FSTD %fr23,-240(%r30)
LDD -256(%r30),%r28
DEPD,Z %r28,31,32,%r2
LDD -264(%r30),%r20
ADD,L %r20,%r2,%r31
LDD -232(%r30),%r22
DEPD,Z %r22,31,32,%r22
LDD -240(%r30),%r21
B $00000024 ; enter loop
ADD,L %r21,%r22,%r23
$0000002A
LDO -1(%r29),%r29
SUB %r23,%r8,%r23
$00000024
SUB %r4,%r31,%r25
AND %r25,%r19,%r26
CMPB,*<>,N %r0,%r26,$00000046 ; (forward)
DEPD,Z %r25,31,32,%r20
OR %r20,%r24,%r21
CMPB,*<<,N %r21,%r23,$0000002A ;(backward)
SUB %r31,%r6,%r31
;-------------Break path---------------------
$00000046
DEPD,Z %r23,31,32,%r25 ;tl
EXTRD,U %r23,31,32,%r26 ;t
AND %r25,%r19,%r24 ;tl = (tl<<32)&0xfffffff0000000L
ADD,L %r31,%r26,%r31 ;th += t;
CMPCLR,*>>= %r5,%r24,%r0 ;if (l<tl)
LDO 1(%r31),%r31 ; th++;
CMPB,*<<=,N %r31,%r4,$00000036 ;if (n < th) (forward)
LDO -1(%r29),%r29 ;q--;
ADD,L %r4,%r3,%r4 ;h += d;
$00000036
ADDIB,=,N -1,%r9,$D1 ;if (--count == 0) break (forward)
SUB %r5,%r24,%r28 ; l -= tl;
SUB %r4,%r31,%r24 ; h -= th;
SHRPD %r24,%r28,32,%r4 ; h = ((h<<32)|(l>>32));
DEPD,Z %r29,31,32,%r10 ; ret = q<<32
b $0000001C
DEPD,Z %r28,31,32,%r5 ; l = l << 32
$D1
OR %r10,%r29,%r28 ; ret |= q
$D3
LDD -368(%r30),%r2
$D0
LDD -296(%r30),%r10
LDD -304(%r30),%r9
LDD -312(%r30),%r8
LDD -320(%r30),%r7
LDD -328(%r30),%r6
LDD -336(%r30),%r5
LDD -344(%r30),%r4
BVE (%r2)
.EXIT
LDD,MB -352(%r30),%r3
bn_div_err_case
MFIA %r6
ADDIL L'bn_div_words-bn_div_err_case,%r6,%r1
LDO R'bn_div_words-bn_div_err_case(%r1),%r6
ADDIL LT'__iob,%r27,%r1
LDD RT'__iob(%r1),%r26
ADDIL L'C$4-bn_div_words,%r6,%r1
LDO R'C$4-bn_div_words(%r1),%r25
LDO 64(%r26),%r26
.CALL ;in=24,25,26,29;out=28;
B,L fprintf,%r2
LDO -48(%r30),%r29
LDD -288(%r30),%r27
.CALL ;in=29;
B,L abort,%r2
LDO -48(%r30),%r29
LDD -288(%r30),%r27
B $D0
LDD -368(%r30),%r2
.PROCEND ;in=24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
; Registers to hold 64-bit values to manipulate. The "L" part
; of the register corresponds to the upper 32-bits, while the "R"
; part corresponds to the lower 32-bits
;
; Note, that when using b6 and b7, the code must save these before
; using them because they are callee save registers
;
;
; Floating point registers to use to save values that
; are manipulated. These don't collide with ftemp1-6 and
; are all caller save registers
;
a0 .reg %fr22
a0L .reg %fr22L
a0R .reg %fr22R
a1 .reg %fr23
a1L .reg %fr23L
a1R .reg %fr23R
a2 .reg %fr24
a2L .reg %fr24L
a2R .reg %fr24R
a3 .reg %fr25
a3L .reg %fr25L
a3R .reg %fr25R
a4 .reg %fr26
a4L .reg %fr26L
a4R .reg %fr26R
a5 .reg %fr27
a5L .reg %fr27L
a5R .reg %fr27R
a6 .reg %fr28
a6L .reg %fr28L
a6R .reg %fr28R
a7 .reg %fr29
a7L .reg %fr29L
a7R .reg %fr29R
b0 .reg %fr30
b0L .reg %fr30L
b0R .reg %fr30R
b1 .reg %fr31
b1L .reg %fr31L
b1R .reg %fr31R
;
; Temporary floating point variables, these are all caller save
; registers
;
ftemp1 .reg %fr4
ftemp2 .reg %fr5
ftemp3 .reg %fr6
ftemp4 .reg %fr7
;
; The B set of registers when used.
;
b2 .reg %fr8
b2L .reg %fr8L
b2R .reg %fr8R
b3 .reg %fr9
b3L .reg %fr9L
b3R .reg %fr9R
b4 .reg %fr10
b4L .reg %fr10L
b4R .reg %fr10R
b5 .reg %fr11
b5L .reg %fr11L
b5R .reg %fr11R
b6 .reg %fr12
b6L .reg %fr12L
b6R .reg %fr12R
b7 .reg %fr13
b7L .reg %fr13L
b7R .reg %fr13R
c1 .reg %r21 ; only reg
temp1 .reg %r20 ; only reg
temp2 .reg %r19 ; only reg
temp3 .reg %r31 ; only reg
m1 .reg %r28
c2 .reg %r23
high_one .reg %r1
ht .reg %r6
lt .reg %r5
m .reg %r4
c3 .reg %r3
SQR_ADD_C .macro A0L,A0R,C1,C2,C3
XMPYU A0L,A0R,ftemp1 ; m
FSTD ftemp1,-24(%sp) ; store m
XMPYU A0R,A0R,ftemp2 ; lt
FSTD ftemp2,-16(%sp) ; store lt
XMPYU A0L,A0L,ftemp3 ; ht
FSTD ftemp3,-8(%sp) ; store ht
LDD -24(%sp),m ; load m
AND m,high_mask,temp2 ; m & Mask
DEPD,Z m,30,31,temp3 ; m << 32+1
LDD -16(%sp),lt ; lt
LDD -8(%sp),ht ; ht
EXTRD,U temp2,32,33,temp1 ; temp1 = m&Mask >> 32-1
ADD temp3,lt,lt ; lt = lt+m
ADD,L ht,temp1,ht ; ht += temp1
ADD,DC ht,%r0,ht ; ht++
ADD C1,lt,C1 ; c1=c1+lt
ADD,DC ht,%r0,ht ; ht++
ADD C2,ht,C2 ; c2=c2+ht
ADD,DC C3,%r0,C3 ; c3++
.endm
SQR_ADD_C2 .macro A0L,A0R,A1L,A1R,C1,C2,C3
XMPYU A0L,A1R,ftemp1 ; m1 = bl*ht
FSTD ftemp1,-16(%sp) ;
XMPYU A0R,A1L,ftemp2 ; m = bh*lt
FSTD ftemp2,-8(%sp) ;
XMPYU A0R,A1R,ftemp3 ; lt = bl*lt
FSTD ftemp3,-32(%sp)
XMPYU A0L,A1L,ftemp4 ; ht = bh*ht
FSTD ftemp4,-24(%sp) ;
LDD -8(%sp),m ; r21 = m
LDD -16(%sp),m1 ; r19 = m1
ADD,L m,m1,m ; m+m1
DEPD,Z m,31,32,temp3 ; (m+m1<<32)
LDD -24(%sp),ht ; r24 = ht
CMPCLR,*>>= m,m1,%r0 ; if (m < m1)
ADD,L ht,high_one,ht ; ht+=high_one
EXTRD,U m,31,32,temp1 ; m >> 32
LDD -32(%sp),lt ; lt
ADD,L ht,temp1,ht ; ht+= m>>32
ADD lt,temp3,lt ; lt = lt+m1
ADD,DC ht,%r0,ht ; ht++
ADD ht,ht,ht ; ht=ht+ht;
ADD,DC C3,%r0,C3 ; add in carry (c3++)
ADD lt,lt,lt ; lt=lt+lt;
ADD,DC ht,%r0,ht ; add in carry (ht++)
ADD C1,lt,C1 ; c1=c1+lt
ADD,DC,*NUV ht,%r0,ht ; add in carry (ht++)
LDO 1(C3),C3 ; bump c3 if overflow,nullify otherwise
ADD C2,ht,C2 ; c2 = c2 + ht
ADD,DC C3,%r0,C3 ; add in carry (c3++)
.endm
;
;void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
; arg0 = r_ptr
; arg1 = a_ptr
;
bn_sqr_comba8
.PROC
.CALLINFO FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_sqr_comba8,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.ENTRY
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 32(a_ptr),a4
FLDD 40(a_ptr),a5
FLDD 48(a_ptr),a6
FLDD 56(a_ptr),a7
SQR_ADD_C a0L,a0R,c1,c2,c3
STD c1,0(r_ptr) ; r[0] = c1;
COPY %r0,c1
SQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1
STD c2,8(r_ptr) ; r[1] = c2;
COPY %r0,c2
SQR_ADD_C a1L,a1R,c3,c1,c2
SQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2
STD c3,16(r_ptr) ; r[2] = c3;
COPY %r0,c3
SQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3
SQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3
STD c1,24(r_ptr) ; r[3] = c1;
COPY %r0,c1
SQR_ADD_C a2L,a2R,c2,c3,c1
SQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1
SQR_ADD_C2 a4L,a4R,a0L,a0R,c2,c3,c1
STD c2,32(r_ptr) ; r[4] = c2;
COPY %r0,c2
SQR_ADD_C2 a5L,a5R,a0L,a0R,c3,c1,c2
SQR_ADD_C2 a4L,a4R,a1L,a1R,c3,c1,c2
SQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2
STD c3,40(r_ptr) ; r[5] = c3;
COPY %r0,c3
SQR_ADD_C a3L,a3R,c1,c2,c3
SQR_ADD_C2 a4L,a4R,a2L,a2R,c1,c2,c3
SQR_ADD_C2 a5L,a5R,a1L,a1R,c1,c2,c3
SQR_ADD_C2 a6L,a6R,a0L,a0R,c1,c2,c3
STD c1,48(r_ptr) ; r[6] = c1;
COPY %r0,c1
SQR_ADD_C2 a7L,a7R,a0L,a0R,c2,c3,c1
SQR_ADD_C2 a6L,a6R,a1L,a1R,c2,c3,c1
SQR_ADD_C2 a5L,a5R,a2L,a2R,c2,c3,c1
SQR_ADD_C2 a4L,a4R,a3L,a3R,c2,c3,c1
STD c2,56(r_ptr) ; r[7] = c2;
COPY %r0,c2
SQR_ADD_C a4L,a4R,c3,c1,c2
SQR_ADD_C2 a5L,a5R,a3L,a3R,c3,c1,c2
SQR_ADD_C2 a6L,a6R,a2L,a2R,c3,c1,c2
SQR_ADD_C2 a7L,a7R,a1L,a1R,c3,c1,c2
STD c3,64(r_ptr) ; r[8] = c3;
COPY %r0,c3
SQR_ADD_C2 a7L,a7R,a2L,a2R,c1,c2,c3
SQR_ADD_C2 a6L,a6R,a3L,a3R,c1,c2,c3
SQR_ADD_C2 a5L,a5R,a4L,a4R,c1,c2,c3
STD c1,72(r_ptr) ; r[9] = c1;
COPY %r0,c1
SQR_ADD_C a5L,a5R,c2,c3,c1
SQR_ADD_C2 a6L,a6R,a4L,a4R,c2,c3,c1
SQR_ADD_C2 a7L,a7R,a3L,a3R,c2,c3,c1
STD c2,80(r_ptr) ; r[10] = c2;
COPY %r0,c2
SQR_ADD_C2 a7L,a7R,a4L,a4R,c3,c1,c2
SQR_ADD_C2 a6L,a6R,a5L,a5R,c3,c1,c2
STD c3,88(r_ptr) ; r[11] = c3;
COPY %r0,c3
SQR_ADD_C a6L,a6R,c1,c2,c3
SQR_ADD_C2 a7L,a7R,a5L,a5R,c1,c2,c3
STD c1,96(r_ptr) ; r[12] = c1;
COPY %r0,c1
SQR_ADD_C2 a7L,a7R,a6L,a6R,c2,c3,c1
STD c2,104(r_ptr) ; r[13] = c2;
COPY %r0,c2
SQR_ADD_C a7L,a7R,c3,c1,c2
STD c3, 112(r_ptr) ; r[14] = c3
STD c1, 120(r_ptr) ; r[15] = c1
.EXIT
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;-----------------------------------------------------------------------------
;
;void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
; arg0 = r_ptr
; arg1 = a_ptr
;
bn_sqr_comba4
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_sqr_comba4,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 32(a_ptr),a4
FLDD 40(a_ptr),a5
FLDD 48(a_ptr),a6
FLDD 56(a_ptr),a7
SQR_ADD_C a0L,a0R,c1,c2,c3
STD c1,0(r_ptr) ; r[0] = c1;
COPY %r0,c1
SQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1
STD c2,8(r_ptr) ; r[1] = c2;
COPY %r0,c2
SQR_ADD_C a1L,a1R,c3,c1,c2
SQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2
STD c3,16(r_ptr) ; r[2] = c3;
COPY %r0,c3
SQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3
SQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3
STD c1,24(r_ptr) ; r[3] = c1;
COPY %r0,c1
SQR_ADD_C a2L,a2R,c2,c3,c1
SQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1
STD c2,32(r_ptr) ; r[4] = c2;
COPY %r0,c2
SQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2
STD c3,40(r_ptr) ; r[5] = c3;
COPY %r0,c3
SQR_ADD_C a3L,a3R,c1,c2,c3
STD c1,48(r_ptr) ; r[6] = c1;
STD c2,56(r_ptr) ; r[7] = c2;
.EXIT
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;---------------------------------------------------------------------------
MUL_ADD_C .macro A0L,A0R,B0L,B0R,C1,C2,C3
XMPYU A0L,B0R,ftemp1 ; m1 = bl*ht
FSTD ftemp1,-16(%sp) ;
XMPYU A0R,B0L,ftemp2 ; m = bh*lt
FSTD ftemp2,-8(%sp) ;
XMPYU A0R,B0R,ftemp3 ; lt = bl*lt
FSTD ftemp3,-32(%sp)
XMPYU A0L,B0L,ftemp4 ; ht = bh*ht
FSTD ftemp4,-24(%sp) ;
LDD -8(%sp),m ; r21 = m
LDD -16(%sp),m1 ; r19 = m1
ADD,L m,m1,m ; m+m1
DEPD,Z m,31,32,temp3 ; (m+m1<<32)
LDD -24(%sp),ht ; r24 = ht
CMPCLR,*>>= m,m1,%r0 ; if (m < m1)
ADD,L ht,high_one,ht ; ht+=high_one
EXTRD,U m,31,32,temp1 ; m >> 32
LDD -32(%sp),lt ; lt
ADD,L ht,temp1,ht ; ht+= m>>32
ADD lt,temp3,lt ; lt = lt+m1
ADD,DC ht,%r0,ht ; ht++
ADD C1,lt,C1 ; c1=c1+lt
ADD,DC ht,%r0,ht ; bump c3 if overflow,nullify otherwise
ADD C2,ht,C2 ; c2 = c2 + ht
ADD,DC C3,%r0,C3 ; add in carry (c3++)
.endm
;
;void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
; arg0 = r_ptr
; arg1 = a_ptr
; arg2 = b_ptr
;
bn_mul_comba8
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_mul_comba8,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
FSTD %fr12,32(%sp) ; save r6
FSTD %fr13,40(%sp) ; save r7
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 32(a_ptr),a4
FLDD 40(a_ptr),a5
FLDD 48(a_ptr),a6
FLDD 56(a_ptr),a7
FLDD 0(b_ptr),b0
FLDD 8(b_ptr),b1
FLDD 16(b_ptr),b2
FLDD 24(b_ptr),b3
FLDD 32(b_ptr),b4
FLDD 40(b_ptr),b5
FLDD 48(b_ptr),b6
FLDD 56(b_ptr),b7
MUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3
STD c1,0(r_ptr)
COPY %r0,c1
MUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1
MUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1
STD c2,8(r_ptr)
COPY %r0,c2
MUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2
MUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2
MUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2
STD c3,16(r_ptr)
COPY %r0,c3
MUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3
MUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3
MUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3
MUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3
STD c1,24(r_ptr)
COPY %r0,c1
MUL_ADD_C a4L,a4R,b0L,b0R,c2,c3,c1
MUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1
MUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1
MUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1
MUL_ADD_C a0L,a0R,b4L,b4R,c2,c3,c1
STD c2,32(r_ptr)
COPY %r0,c2
MUL_ADD_C a0L,a0R,b5L,b5R,c3,c1,c2
MUL_ADD_C a1L,a1R,b4L,b4R,c3,c1,c2
MUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2
MUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2
MUL_ADD_C a4L,a4R,b1L,b1R,c3,c1,c2
MUL_ADD_C a5L,a5R,b0L,b0R,c3,c1,c2
STD c3,40(r_ptr)
COPY %r0,c3
MUL_ADD_C a6L,a6R,b0L,b0R,c1,c2,c3
MUL_ADD_C a5L,a5R,b1L,b1R,c1,c2,c3
MUL_ADD_C a4L,a4R,b2L,b2R,c1,c2,c3
MUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3
MUL_ADD_C a2L,a2R,b4L,b4R,c1,c2,c3
MUL_ADD_C a1L,a1R,b5L,b5R,c1,c2,c3
MUL_ADD_C a0L,a0R,b6L,b6R,c1,c2,c3
STD c1,48(r_ptr)
COPY %r0,c1
MUL_ADD_C a0L,a0R,b7L,b7R,c2,c3,c1
MUL_ADD_C a1L,a1R,b6L,b6R,c2,c3,c1
MUL_ADD_C a2L,a2R,b5L,b5R,c2,c3,c1
MUL_ADD_C a3L,a3R,b4L,b4R,c2,c3,c1
MUL_ADD_C a4L,a4R,b3L,b3R,c2,c3,c1
MUL_ADD_C a5L,a5R,b2L,b2R,c2,c3,c1
MUL_ADD_C a6L,a6R,b1L,b1R,c2,c3,c1
MUL_ADD_C a7L,a7R,b0L,b0R,c2,c3,c1
STD c2,56(r_ptr)
COPY %r0,c2
MUL_ADD_C a7L,a7R,b1L,b1R,c3,c1,c2
MUL_ADD_C a6L,a6R,b2L,b2R,c3,c1,c2
MUL_ADD_C a5L,a5R,b3L,b3R,c3,c1,c2
MUL_ADD_C a4L,a4R,b4L,b4R,c3,c1,c2
MUL_ADD_C a3L,a3R,b5L,b5R,c3,c1,c2
MUL_ADD_C a2L,a2R,b6L,b6R,c3,c1,c2
MUL_ADD_C a1L,a1R,b7L,b7R,c3,c1,c2
STD c3,64(r_ptr)
COPY %r0,c3
MUL_ADD_C a2L,a2R,b7L,b7R,c1,c2,c3
MUL_ADD_C a3L,a3R,b6L,b6R,c1,c2,c3
MUL_ADD_C a4L,a4R,b5L,b5R,c1,c2,c3
MUL_ADD_C a5L,a5R,b4L,b4R,c1,c2,c3
MUL_ADD_C a6L,a6R,b3L,b3R,c1,c2,c3
MUL_ADD_C a7L,a7R,b2L,b2R,c1,c2,c3
STD c1,72(r_ptr)
COPY %r0,c1
MUL_ADD_C a7L,a7R,b3L,b3R,c2,c3,c1
MUL_ADD_C a6L,a6R,b4L,b4R,c2,c3,c1
MUL_ADD_C a5L,a5R,b5L,b5R,c2,c3,c1
MUL_ADD_C a4L,a4R,b6L,b6R,c2,c3,c1
MUL_ADD_C a3L,a3R,b7L,b7R,c2,c3,c1
STD c2,80(r_ptr)
COPY %r0,c2
MUL_ADD_C a4L,a4R,b7L,b7R,c3,c1,c2
MUL_ADD_C a5L,a5R,b6L,b6R,c3,c1,c2
MUL_ADD_C a6L,a6R,b5L,b5R,c3,c1,c2
MUL_ADD_C a7L,a7R,b4L,b4R,c3,c1,c2
STD c3,88(r_ptr)
COPY %r0,c3
MUL_ADD_C a7L,a7R,b5L,b5R,c1,c2,c3
MUL_ADD_C a6L,a6R,b6L,b6R,c1,c2,c3
MUL_ADD_C a5L,a5R,b7L,b7R,c1,c2,c3
STD c1,96(r_ptr)
COPY %r0,c1
MUL_ADD_C a6L,a6R,b7L,b7R,c2,c3,c1
MUL_ADD_C a7L,a7R,b6L,b6R,c2,c3,c1
STD c2,104(r_ptr)
COPY %r0,c2
MUL_ADD_C a7L,a7R,b7L,b7R,c3,c1,c2
STD c3,112(r_ptr)
STD c1,120(r_ptr)
.EXIT
FLDD -88(%sp),%fr13
FLDD -96(%sp),%fr12
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;-----------------------------------------------------------------------------
;
;void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
; arg0 = r_ptr
; arg1 = a_ptr
; arg2 = b_ptr
;
bn_mul_comba4
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_mul_comba4,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
FSTD %fr12,32(%sp) ; save r6
FSTD %fr13,40(%sp) ; save r7
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 0(b_ptr),b0
FLDD 8(b_ptr),b1
FLDD 16(b_ptr),b2
FLDD 24(b_ptr),b3
MUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3
STD c1,0(r_ptr)
COPY %r0,c1
MUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1
MUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1
STD c2,8(r_ptr)
COPY %r0,c2
MUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2
MUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2
MUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2
STD c3,16(r_ptr)
COPY %r0,c3
MUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3
MUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3
MUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3
MUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3
STD c1,24(r_ptr)
COPY %r0,c1
MUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1
MUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1
MUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1
STD c2,32(r_ptr)
COPY %r0,c2
MUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2
MUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2
STD c3,40(r_ptr)
COPY %r0,c3
MUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3
STD c1,48(r_ptr)
STD c2,56(r_ptr)
.EXIT
FLDD -88(%sp),%fr13
FLDD -96(%sp),%fr12
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
.SPACE $TEXT$
.SUBSPA $CODE$
.SPACE $PRIVATE$,SORT=16
.IMPORT $global$,DATA
.SPACE $TEXT$
.SUBSPA $CODE$
.SUBSPA $LIT$,ACCESS=0x2c
C$4
.ALIGN 8
.STRINGZ "Division would overflow (%d)\n"
.END
|
ntu-ssl/rr-artifact | 13,351 | openssl-1.1.0l/crypto/bn/asm/s390x.S | .ident "s390x.S, version 1.1"
// ====================================================================
// Copyright 2007-2016 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under the OpenSSL license (the "License"). You may not use
// this file except in compliance with the License. You can obtain a copy
// in the file LICENSE in the source distribution or at
// https://www.openssl.org/source/license.html
// ====================================================================
.text
#define zero %r0
// BN_ULONG bn_mul_add_words(BN_ULONG *r2,BN_ULONG *r3,int r4,BN_ULONG r5);
.globl bn_mul_add_words
.type bn_mul_add_words,@function
.align 4
bn_mul_add_words:
lghi zero,0 // zero = 0
la %r1,0(%r2) // put rp aside [to give way to]
lghi %r2,0 // return value
ltgfr %r4,%r4
bler %r14 // if (len<=0) return 0;
stmg %r6,%r13,48(%r15)
lghi %r2,3
lghi %r12,0 // carry = 0
slgr %r1,%r3 // rp-=ap
nr %r2,%r4 // len%4
sra %r4,2 // cnt=len/4
jz .Loop1_madd // carry is incidentally cleared if branch taken
algr zero,zero // clear carry
lg %r7,0(%r3) // ap[0]
lg %r9,8(%r3) // ap[1]
mlgr %r6,%r5 // *=w
brct %r4,.Loop4_madd
j .Loop4_madd_tail
.Loop4_madd:
mlgr %r8,%r5
lg %r11,16(%r3) // ap[i+2]
alcgr %r7,%r12 // +=carry
alcgr %r6,zero
alg %r7,0(%r3,%r1) // +=rp[i]
stg %r7,0(%r3,%r1) // rp[i]=
mlgr %r10,%r5
lg %r13,24(%r3)
alcgr %r9,%r6
alcgr %r8,zero
alg %r9,8(%r3,%r1)
stg %r9,8(%r3,%r1)
mlgr %r12,%r5
lg %r7,32(%r3)
alcgr %r11,%r8
alcgr %r10,zero
alg %r11,16(%r3,%r1)
stg %r11,16(%r3,%r1)
mlgr %r6,%r5
lg %r9,40(%r3)
alcgr %r13,%r10
alcgr %r12,zero
alg %r13,24(%r3,%r1)
stg %r13,24(%r3,%r1)
la %r3,32(%r3) // i+=4
brct %r4,.Loop4_madd
.Loop4_madd_tail:
mlgr %r8,%r5
lg %r11,16(%r3)
alcgr %r7,%r12 // +=carry
alcgr %r6,zero
alg %r7,0(%r3,%r1) // +=rp[i]
stg %r7,0(%r3,%r1) // rp[i]=
mlgr %r10,%r5
lg %r13,24(%r3)
alcgr %r9,%r6
alcgr %r8,zero
alg %r9,8(%r3,%r1)
stg %r9,8(%r3,%r1)
mlgr %r12,%r5
alcgr %r11,%r8
alcgr %r10,zero
alg %r11,16(%r3,%r1)
stg %r11,16(%r3,%r1)
alcgr %r13,%r10
alcgr %r12,zero
alg %r13,24(%r3,%r1)
stg %r13,24(%r3,%r1)
la %r3,32(%r3) // i+=4
la %r2,1(%r2) // see if len%4 is zero ...
brct %r2,.Loop1_madd // without touching condition code:-)
.Lend_madd:
lgr %r2,zero // return value
alcgr %r2,%r12 // collect even carry bit
lmg %r6,%r13,48(%r15)
br %r14
.Loop1_madd:
lg %r7,0(%r3) // ap[i]
mlgr %r6,%r5 // *=w
alcgr %r7,%r12 // +=carry
alcgr %r6,zero
alg %r7,0(%r3,%r1) // +=rp[i]
stg %r7,0(%r3,%r1) // rp[i]=
lgr %r12,%r6
la %r3,8(%r3) // i++
brct %r2,.Loop1_madd
j .Lend_madd
.size bn_mul_add_words,.-bn_mul_add_words
// BN_ULONG bn_mul_words(BN_ULONG *r2,BN_ULONG *r3,int r4,BN_ULONG r5);
.globl bn_mul_words
.type bn_mul_words,@function
.align 4
bn_mul_words:
lghi zero,0 // zero = 0
la %r1,0(%r2) // put rp aside
lghi %r2,0 // i=0;
ltgfr %r4,%r4
bler %r14 // if (len<=0) return 0;
stmg %r6,%r10,48(%r15)
lghi %r10,3
lghi %r8,0 // carry = 0
nr %r10,%r4 // len%4
sra %r4,2 // cnt=len/4
jz .Loop1_mul // carry is incidentally cleared if branch taken
algr zero,zero // clear carry
.Loop4_mul:
lg %r7,0(%r2,%r3) // ap[i]
mlgr %r6,%r5 // *=w
alcgr %r7,%r8 // +=carry
stg %r7,0(%r2,%r1) // rp[i]=
lg %r9,8(%r2,%r3)
mlgr %r8,%r5
alcgr %r9,%r6
stg %r9,8(%r2,%r1)
lg %r7,16(%r2,%r3)
mlgr %r6,%r5
alcgr %r7,%r8
stg %r7,16(%r2,%r1)
lg %r9,24(%r2,%r3)
mlgr %r8,%r5
alcgr %r9,%r6
stg %r9,24(%r2,%r1)
la %r2,32(%r2) // i+=4
brct %r4,.Loop4_mul
la %r10,1(%r10) // see if len%4 is zero ...
brct %r10,.Loop1_mul // without touching condition code:-)
.Lend_mul:
alcgr %r8,zero // collect carry bit
lgr %r2,%r8
lmg %r6,%r10,48(%r15)
br %r14
.Loop1_mul:
lg %r7,0(%r2,%r3) // ap[i]
mlgr %r6,%r5 // *=w
alcgr %r7,%r8 // +=carry
stg %r7,0(%r2,%r1) // rp[i]=
lgr %r8,%r6
la %r2,8(%r2) // i++
brct %r10,.Loop1_mul
j .Lend_mul
.size bn_mul_words,.-bn_mul_words
// void bn_sqr_words(BN_ULONG *r2,BN_ULONG *r2,int r4)
.globl bn_sqr_words
.type bn_sqr_words,@function
.align 4
bn_sqr_words:
ltgfr %r4,%r4
bler %r14
stmg %r6,%r7,48(%r15)
srag %r1,%r4,2 // cnt=len/4
jz .Loop1_sqr
.Loop4_sqr:
lg %r7,0(%r3)
mlgr %r6,%r7
stg %r7,0(%r2)
stg %r6,8(%r2)
lg %r7,8(%r3)
mlgr %r6,%r7
stg %r7,16(%r2)
stg %r6,24(%r2)
lg %r7,16(%r3)
mlgr %r6,%r7
stg %r7,32(%r2)
stg %r6,40(%r2)
lg %r7,24(%r3)
mlgr %r6,%r7
stg %r7,48(%r2)
stg %r6,56(%r2)
la %r3,32(%r3)
la %r2,64(%r2)
brct %r1,.Loop4_sqr
lghi %r1,3
nr %r4,%r1 // cnt=len%4
jz .Lend_sqr
.Loop1_sqr:
lg %r7,0(%r3)
mlgr %r6,%r7
stg %r7,0(%r2)
stg %r6,8(%r2)
la %r3,8(%r3)
la %r2,16(%r2)
brct %r4,.Loop1_sqr
.Lend_sqr:
lmg %r6,%r7,48(%r15)
br %r14
.size bn_sqr_words,.-bn_sqr_words
// BN_ULONG bn_div_words(BN_ULONG h,BN_ULONG l,BN_ULONG d);
.globl bn_div_words
.type bn_div_words,@function
.align 4
bn_div_words:
dlgr %r2,%r4
lgr %r2,%r3
br %r14
.size bn_div_words,.-bn_div_words
// BN_ULONG bn_add_words(BN_ULONG *r2,BN_ULONG *r3,BN_ULONG *r4,int r5);
.globl bn_add_words
.type bn_add_words,@function
.align 4
bn_add_words:
la %r1,0(%r2) // put rp aside
lghi %r2,0 // i=0
ltgfr %r5,%r5
bler %r14 // if (len<=0) return 0;
stg %r6,48(%r15)
lghi %r6,3
nr %r6,%r5 // len%4
sra %r5,2 // len/4, use sra because it sets condition code
jz .Loop1_add // carry is incidentally cleared if branch taken
algr %r2,%r2 // clear carry
.Loop4_add:
lg %r0,0(%r2,%r3)
alcg %r0,0(%r2,%r4)
stg %r0,0(%r2,%r1)
lg %r0,8(%r2,%r3)
alcg %r0,8(%r2,%r4)
stg %r0,8(%r2,%r1)
lg %r0,16(%r2,%r3)
alcg %r0,16(%r2,%r4)
stg %r0,16(%r2,%r1)
lg %r0,24(%r2,%r3)
alcg %r0,24(%r2,%r4)
stg %r0,24(%r2,%r1)
la %r2,32(%r2) // i+=4
brct %r5,.Loop4_add
la %r6,1(%r6) // see if len%4 is zero ...
brct %r6,.Loop1_add // without touching condition code:-)
.Lexit_add:
lghi %r2,0
alcgr %r2,%r2
lg %r6,48(%r15)
br %r14
.Loop1_add:
lg %r0,0(%r2,%r3)
alcg %r0,0(%r2,%r4)
stg %r0,0(%r2,%r1)
la %r2,8(%r2) // i++
brct %r6,.Loop1_add
j .Lexit_add
.size bn_add_words,.-bn_add_words
// BN_ULONG bn_sub_words(BN_ULONG *r2,BN_ULONG *r3,BN_ULONG *r4,int r5);
.globl bn_sub_words
.type bn_sub_words,@function
.align 4
bn_sub_words:
la %r1,0(%r2) // put rp aside
lghi %r2,0 // i=0
ltgfr %r5,%r5
bler %r14 // if (len<=0) return 0;
stg %r6,48(%r15)
lghi %r6,3
nr %r6,%r5 // len%4
sra %r5,2 // len/4, use sra because it sets condition code
jnz .Loop4_sub // borrow is incidentally cleared if branch taken
slgr %r2,%r2 // clear borrow
.Loop1_sub:
lg %r0,0(%r2,%r3)
slbg %r0,0(%r2,%r4)
stg %r0,0(%r2,%r1)
la %r2,8(%r2) // i++
brct %r6,.Loop1_sub
j .Lexit_sub
.Loop4_sub:
lg %r0,0(%r2,%r3)
slbg %r0,0(%r2,%r4)
stg %r0,0(%r2,%r1)
lg %r0,8(%r2,%r3)
slbg %r0,8(%r2,%r4)
stg %r0,8(%r2,%r1)
lg %r0,16(%r2,%r3)
slbg %r0,16(%r2,%r4)
stg %r0,16(%r2,%r1)
lg %r0,24(%r2,%r3)
slbg %r0,24(%r2,%r4)
stg %r0,24(%r2,%r1)
la %r2,32(%r2) // i+=4
brct %r5,.Loop4_sub
la %r6,1(%r6) // see if len%4 is zero ...
brct %r6,.Loop1_sub // without touching condition code:-)
.Lexit_sub:
lghi %r2,0
slbgr %r2,%r2
lcgr %r2,%r2
lg %r6,48(%r15)
br %r14
.size bn_sub_words,.-bn_sub_words
#define c1 %r1
#define c2 %r5
#define c3 %r8
#define mul_add_c(ai,bi,c1,c2,c3) \
lg %r7,ai*8(%r3); \
mlg %r6,bi*8(%r4); \
algr c1,%r7; \
alcgr c2,%r6; \
alcgr c3,zero
// void bn_mul_comba8(BN_ULONG *r2,BN_ULONG *r3,BN_ULONG *r4);
.globl bn_mul_comba8
.type bn_mul_comba8,@function
.align 4
bn_mul_comba8:
stmg %r6,%r8,48(%r15)
lghi c1,0
lghi c2,0
lghi c3,0
lghi zero,0
mul_add_c(0,0,c1,c2,c3);
stg c1,0*8(%r2)
lghi c1,0
mul_add_c(0,1,c2,c3,c1);
mul_add_c(1,0,c2,c3,c1);
stg c2,1*8(%r2)
lghi c2,0
mul_add_c(2,0,c3,c1,c2);
mul_add_c(1,1,c3,c1,c2);
mul_add_c(0,2,c3,c1,c2);
stg c3,2*8(%r2)
lghi c3,0
mul_add_c(0,3,c1,c2,c3);
mul_add_c(1,2,c1,c2,c3);
mul_add_c(2,1,c1,c2,c3);
mul_add_c(3,0,c1,c2,c3);
stg c1,3*8(%r2)
lghi c1,0
mul_add_c(4,0,c2,c3,c1);
mul_add_c(3,1,c2,c3,c1);
mul_add_c(2,2,c2,c3,c1);
mul_add_c(1,3,c2,c3,c1);
mul_add_c(0,4,c2,c3,c1);
stg c2,4*8(%r2)
lghi c2,0
mul_add_c(0,5,c3,c1,c2);
mul_add_c(1,4,c3,c1,c2);
mul_add_c(2,3,c3,c1,c2);
mul_add_c(3,2,c3,c1,c2);
mul_add_c(4,1,c3,c1,c2);
mul_add_c(5,0,c3,c1,c2);
stg c3,5*8(%r2)
lghi c3,0
mul_add_c(6,0,c1,c2,c3);
mul_add_c(5,1,c1,c2,c3);
mul_add_c(4,2,c1,c2,c3);
mul_add_c(3,3,c1,c2,c3);
mul_add_c(2,4,c1,c2,c3);
mul_add_c(1,5,c1,c2,c3);
mul_add_c(0,6,c1,c2,c3);
stg c1,6*8(%r2)
lghi c1,0
mul_add_c(0,7,c2,c3,c1);
mul_add_c(1,6,c2,c3,c1);
mul_add_c(2,5,c2,c3,c1);
mul_add_c(3,4,c2,c3,c1);
mul_add_c(4,3,c2,c3,c1);
mul_add_c(5,2,c2,c3,c1);
mul_add_c(6,1,c2,c3,c1);
mul_add_c(7,0,c2,c3,c1);
stg c2,7*8(%r2)
lghi c2,0
mul_add_c(7,1,c3,c1,c2);
mul_add_c(6,2,c3,c1,c2);
mul_add_c(5,3,c3,c1,c2);
mul_add_c(4,4,c3,c1,c2);
mul_add_c(3,5,c3,c1,c2);
mul_add_c(2,6,c3,c1,c2);
mul_add_c(1,7,c3,c1,c2);
stg c3,8*8(%r2)
lghi c3,0
mul_add_c(2,7,c1,c2,c3);
mul_add_c(3,6,c1,c2,c3);
mul_add_c(4,5,c1,c2,c3);
mul_add_c(5,4,c1,c2,c3);
mul_add_c(6,3,c1,c2,c3);
mul_add_c(7,2,c1,c2,c3);
stg c1,9*8(%r2)
lghi c1,0
mul_add_c(7,3,c2,c3,c1);
mul_add_c(6,4,c2,c3,c1);
mul_add_c(5,5,c2,c3,c1);
mul_add_c(4,6,c2,c3,c1);
mul_add_c(3,7,c2,c3,c1);
stg c2,10*8(%r2)
lghi c2,0
mul_add_c(4,7,c3,c1,c2);
mul_add_c(5,6,c3,c1,c2);
mul_add_c(6,5,c3,c1,c2);
mul_add_c(7,4,c3,c1,c2);
stg c3,11*8(%r2)
lghi c3,0
mul_add_c(7,5,c1,c2,c3);
mul_add_c(6,6,c1,c2,c3);
mul_add_c(5,7,c1,c2,c3);
stg c1,12*8(%r2)
lghi c1,0
mul_add_c(6,7,c2,c3,c1);
mul_add_c(7,6,c2,c3,c1);
stg c2,13*8(%r2)
lghi c2,0
mul_add_c(7,7,c3,c1,c2);
stg c3,14*8(%r2)
stg c1,15*8(%r2)
lmg %r6,%r8,48(%r15)
br %r14
.size bn_mul_comba8,.-bn_mul_comba8
// void bn_mul_comba4(BN_ULONG *r2,BN_ULONG *r3,BN_ULONG *r4);
.globl bn_mul_comba4
.type bn_mul_comba4,@function
.align 4
bn_mul_comba4:
stmg %r6,%r8,48(%r15)
lghi c1,0
lghi c2,0
lghi c3,0
lghi zero,0
mul_add_c(0,0,c1,c2,c3);
stg c1,0*8(%r3)
lghi c1,0
mul_add_c(0,1,c2,c3,c1);
mul_add_c(1,0,c2,c3,c1);
stg c2,1*8(%r2)
lghi c2,0
mul_add_c(2,0,c3,c1,c2);
mul_add_c(1,1,c3,c1,c2);
mul_add_c(0,2,c3,c1,c2);
stg c3,2*8(%r2)
lghi c3,0
mul_add_c(0,3,c1,c2,c3);
mul_add_c(1,2,c1,c2,c3);
mul_add_c(2,1,c1,c2,c3);
mul_add_c(3,0,c1,c2,c3);
stg c1,3*8(%r2)
lghi c1,0
mul_add_c(3,1,c2,c3,c1);
mul_add_c(2,2,c2,c3,c1);
mul_add_c(1,3,c2,c3,c1);
stg c2,4*8(%r2)
lghi c2,0
mul_add_c(2,3,c3,c1,c2);
mul_add_c(3,2,c3,c1,c2);
stg c3,5*8(%r2)
lghi c3,0
mul_add_c(3,3,c1,c2,c3);
stg c1,6*8(%r2)
stg c2,7*8(%r2)
stmg %r6,%r8,48(%r15)
br %r14
.size bn_mul_comba4,.-bn_mul_comba4
#define sqr_add_c(ai,c1,c2,c3) \
lg %r7,ai*8(%r3); \
mlgr %r6,%r7; \
algr c1,%r7; \
alcgr c2,%r6; \
alcgr c3,zero
#define sqr_add_c2(ai,aj,c1,c2,c3) \
lg %r7,ai*8(%r3); \
mlg %r6,aj*8(%r3); \
algr c1,%r7; \
alcgr c2,%r6; \
alcgr c3,zero; \
algr c1,%r7; \
alcgr c2,%r6; \
alcgr c3,zero
// void bn_sqr_comba8(BN_ULONG *r2,BN_ULONG *r3);
.globl bn_sqr_comba8
.type bn_sqr_comba8,@function
.align 4
bn_sqr_comba8:
stmg %r6,%r8,48(%r15)
lghi c1,0
lghi c2,0
lghi c3,0
lghi zero,0
sqr_add_c(0,c1,c2,c3);
stg c1,0*8(%r2)
lghi c1,0
sqr_add_c2(1,0,c2,c3,c1);
stg c2,1*8(%r2)
lghi c2,0
sqr_add_c(1,c3,c1,c2);
sqr_add_c2(2,0,c3,c1,c2);
stg c3,2*8(%r2)
lghi c3,0
sqr_add_c2(3,0,c1,c2,c3);
sqr_add_c2(2,1,c1,c2,c3);
stg c1,3*8(%r2)
lghi c1,0
sqr_add_c(2,c2,c3,c1);
sqr_add_c2(3,1,c2,c3,c1);
sqr_add_c2(4,0,c2,c3,c1);
stg c2,4*8(%r2)
lghi c2,0
sqr_add_c2(5,0,c3,c1,c2);
sqr_add_c2(4,1,c3,c1,c2);
sqr_add_c2(3,2,c3,c1,c2);
stg c3,5*8(%r2)
lghi c3,0
sqr_add_c(3,c1,c2,c3);
sqr_add_c2(4,2,c1,c2,c3);
sqr_add_c2(5,1,c1,c2,c3);
sqr_add_c2(6,0,c1,c2,c3);
stg c1,6*8(%r2)
lghi c1,0
sqr_add_c2(7,0,c2,c3,c1);
sqr_add_c2(6,1,c2,c3,c1);
sqr_add_c2(5,2,c2,c3,c1);
sqr_add_c2(4,3,c2,c3,c1);
stg c2,7*8(%r2)
lghi c2,0
sqr_add_c(4,c3,c1,c2);
sqr_add_c2(5,3,c3,c1,c2);
sqr_add_c2(6,2,c3,c1,c2);
sqr_add_c2(7,1,c3,c1,c2);
stg c3,8*8(%r2)
lghi c3,0
sqr_add_c2(7,2,c1,c2,c3);
sqr_add_c2(6,3,c1,c2,c3);
sqr_add_c2(5,4,c1,c2,c3);
stg c1,9*8(%r2)
lghi c1,0
sqr_add_c(5,c2,c3,c1);
sqr_add_c2(6,4,c2,c3,c1);
sqr_add_c2(7,3,c2,c3,c1);
stg c2,10*8(%r2)
lghi c2,0
sqr_add_c2(7,4,c3,c1,c2);
sqr_add_c2(6,5,c3,c1,c2);
stg c3,11*8(%r2)
lghi c3,0
sqr_add_c(6,c1,c2,c3);
sqr_add_c2(7,5,c1,c2,c3);
stg c1,12*8(%r2)
lghi c1,0
sqr_add_c2(7,6,c2,c3,c1);
stg c2,13*8(%r2)
lghi c2,0
sqr_add_c(7,c3,c1,c2);
stg c3,14*8(%r2)
stg c1,15*8(%r2)
lmg %r6,%r8,48(%r15)
br %r14
.size bn_sqr_comba8,.-bn_sqr_comba8
// void bn_sqr_comba4(BN_ULONG *r2,BN_ULONG *r3);
.globl bn_sqr_comba4
.type bn_sqr_comba4,@function
.align 4
bn_sqr_comba4:
stmg %r6,%r8,48(%r15)
lghi c1,0
lghi c2,0
lghi c3,0
lghi zero,0
sqr_add_c(0,c1,c2,c3);
stg c1,0*8(%r2)
lghi c1,0
sqr_add_c2(1,0,c2,c3,c1);
stg c2,1*8(%r2)
lghi c2,0
sqr_add_c(1,c3,c1,c2);
sqr_add_c2(2,0,c3,c1,c2);
stg c3,2*8(%r2)
lghi c3,0
sqr_add_c2(3,0,c1,c2,c3);
sqr_add_c2(2,1,c1,c2,c3);
stg c1,3*8(%r2)
lghi c1,0
sqr_add_c(2,c2,c3,c1);
sqr_add_c2(3,1,c2,c3,c1);
stg c2,4*8(%r2)
lghi c2,0
sqr_add_c2(3,2,c3,c1,c2);
stg c3,5*8(%r2)
lghi c3,0
sqr_add_c(3,c1,c2,c3);
stg c1,6*8(%r2)
stg c2,7*8(%r2)
lmg %r6,%r8,48(%r15)
br %r14
.size bn_sqr_comba4,.-bn_sqr_comba4
|
ntu-ssl/rr-artifact | 33,288 | openssl-1.1.0l/crypto/bn/asm/sparcv8plus.S | .ident "sparcv8plus.s, Version 1.4"
.ident "SPARC v9 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
/*
* ====================================================================
* Copyright 1999-2016 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the OpenSSL license (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
* ====================================================================
*/
/*
* This is my modest contributon to OpenSSL project (see
* http://www.openssl.org/ for more information about it) and is
* a drop-in UltraSPARC ISA replacement for crypto/bn/bn_asm.c
* module. For updates see http://fy.chalmers.se/~appro/hpe/.
*
* Questions-n-answers.
*
* Q. How to compile?
* A. With SC4.x/SC5.x:
*
* cc -xarch=v8plus -c bn_asm.sparc.v8plus.S -o bn_asm.o
*
* and with gcc:
*
* gcc -mcpu=ultrasparc -c bn_asm.sparc.v8plus.S -o bn_asm.o
*
* or if above fails (it does if you have gas installed):
*
* gcc -E bn_asm.sparc.v8plus.S | as -xarch=v8plus /dev/fd/0 -o bn_asm.o
*
* Quick-n-dirty way to fuse the module into the library.
* Provided that the library is already configured and built
* (in 0.9.2 case with no-asm option):
*
* # cd crypto/bn
* # cp /some/place/bn_asm.sparc.v8plus.S .
* # cc -xarch=v8plus -c bn_asm.sparc.v8plus.S -o bn_asm.o
* # make
* # cd ../..
* # make; make test
*
* Quick-n-dirty way to get rid of it:
*
* # cd crypto/bn
* # touch bn_asm.c
* # make
* # cd ../..
* # make; make test
*
* Q. V8plus architecture? What kind of beast is that?
* A. Well, it's rather a programming model than an architecture...
* It's actually v9-compliant, i.e. *any* UltraSPARC, CPU under
* special conditions, namely when kernel doesn't preserve upper
* 32 bits of otherwise 64-bit registers during a context switch.
*
* Q. Why just UltraSPARC? What about SuperSPARC?
* A. Original release did target UltraSPARC only. Now SuperSPARC
* version is provided along. Both version share bn_*comba[48]
* implementations (see comment later in code for explanation).
* But what's so special about this UltraSPARC implementation?
* Why didn't I let compiler do the job? Trouble is that most of
* available compilers (well, SC5.0 is the only exception) don't
* attempt to take advantage of UltraSPARC's 64-bitness under
* 32-bit kernels even though it's perfectly possible (see next
* question).
*
* Q. 64-bit registers under 32-bit kernels? Didn't you just say it
* doesn't work?
* A. You can't address *all* registers as 64-bit wide:-( The catch is
* that you actually may rely upon %o0-%o5 and %g1-%g4 being fully
* preserved if you're in a leaf function, i.e. such never calling
* any other functions. All functions in this module are leaf and
* 10 registers is a handful. And as a matter of fact none-"comba"
* routines don't require even that much and I could even afford to
* not allocate own stack frame for 'em:-)
*
* Q. What about 64-bit kernels?
* A. What about 'em? Just kidding:-) Pure 64-bit version is currently
* under evaluation and development...
*
* Q. What about shared libraries?
* A. What about 'em? Kidding again:-) Code does *not* contain any
* code position dependencies and it's safe to include it into
* shared library as is.
*
* Q. How much faster does it go?
* A. Do you have a good benchmark? In either case below is what I
* experience with crypto/bn/expspeed.c test program:
*
* v8plus module on U10/300MHz against bn_asm.c compiled with:
*
* cc-5.0 -xarch=v8plus -xO5 -xdepend +7-12%
* cc-4.2 -xarch=v8plus -xO5 -xdepend +25-35%
* egcs-1.1.2 -mcpu=ultrasparc -O3 +35-45%
*
* v8 module on SS10/60MHz against bn_asm.c compiled with:
*
* cc-5.0 -xarch=v8 -xO5 -xdepend +7-10%
* cc-4.2 -xarch=v8 -xO5 -xdepend +10%
* egcs-1.1.2 -mv8 -O3 +35-45%
*
* As you can see it's damn hard to beat the new Sun C compiler
* and it's in first place GNU C users who will appreciate this
* assembler implementation:-)
*/
/*
* Revision history.
*
* 1.0 - initial release;
* 1.1 - new loop unrolling model(*);
* - some more fine tuning;
* 1.2 - made gas friendly;
* - updates to documentation concerning v9;
* - new performance comparison matrix;
* 1.3 - fixed problem with /usr/ccs/lib/cpp;
* 1.4 - native V9 bn_*_comba[48] implementation (15% more efficient)
* resulting in slight overall performance kick;
* - some retunes;
* - support for GNU as added;
*
* (*) Originally unrolled loop looked like this:
* for (;;) {
* op(p+0); if (--n==0) break;
* op(p+1); if (--n==0) break;
* op(p+2); if (--n==0) break;
* op(p+3); if (--n==0) break;
* p+=4;
* }
* I unroll according to following:
* while (n&~3) {
* op(p+0); op(p+1); op(p+2); op(p+3);
* p+=4; n=-4;
* }
* if (n) {
* op(p+0); if (--n==0) return;
* op(p+2); if (--n==0) return;
* op(p+3); return;
* }
*/
#ifdef OPENSSL_FIPSCANISTER
#include <openssl/fipssyms.h>
#endif
#if defined(__SUNPRO_C) && defined(__sparcv9)
/* They've said -xarch=v9 at command line */
.register %g2,#scratch
.register %g3,#scratch
# define FRAME_SIZE -192
#elif defined(__GNUC__) && defined(__arch64__)
/* They've said -m64 at command line */
.register %g2,#scratch
.register %g3,#scratch
# define FRAME_SIZE -192
#else
# define FRAME_SIZE -96
#endif
/*
* GNU assembler can't stand stuw:-(
*/
#define stuw st
.section ".text",#alloc,#execinstr
.file "bn_asm.sparc.v8plus.S"
.align 32
.global bn_mul_add_words
/*
* BN_ULONG bn_mul_add_words(rp,ap,num,w)
* BN_ULONG *rp,*ap;
* int num;
* BN_ULONG w;
*/
bn_mul_add_words:
sra %o2,%g0,%o2 ! signx %o2
brgz,a %o2,.L_bn_mul_add_words_proceed
lduw [%o1],%g2
retl
clr %o0
nop
nop
nop
.L_bn_mul_add_words_proceed:
srl %o3,%g0,%o3 ! clruw %o3
andcc %o2,-4,%g0
bz,pn %icc,.L_bn_mul_add_words_tail
clr %o5
.L_bn_mul_add_words_loop: ! wow! 32 aligned!
lduw [%o0],%g1
lduw [%o1+4],%g3
mulx %o3,%g2,%g2
add %g1,%o5,%o4
nop
add %o4,%g2,%o4
stuw %o4,[%o0]
srlx %o4,32,%o5
lduw [%o0+4],%g1
lduw [%o1+8],%g2
mulx %o3,%g3,%g3
add %g1,%o5,%o4
dec 4,%o2
add %o4,%g3,%o4
stuw %o4,[%o0+4]
srlx %o4,32,%o5
lduw [%o0+8],%g1
lduw [%o1+12],%g3
mulx %o3,%g2,%g2
add %g1,%o5,%o4
inc 16,%o1
add %o4,%g2,%o4
stuw %o4,[%o0+8]
srlx %o4,32,%o5
lduw [%o0+12],%g1
mulx %o3,%g3,%g3
add %g1,%o5,%o4
inc 16,%o0
add %o4,%g3,%o4
andcc %o2,-4,%g0
stuw %o4,[%o0-4]
srlx %o4,32,%o5
bnz,a,pt %icc,.L_bn_mul_add_words_loop
lduw [%o1],%g2
brnz,a,pn %o2,.L_bn_mul_add_words_tail
lduw [%o1],%g2
.L_bn_mul_add_words_return:
retl
mov %o5,%o0
.L_bn_mul_add_words_tail:
lduw [%o0],%g1
mulx %o3,%g2,%g2
add %g1,%o5,%o4
dec %o2
add %o4,%g2,%o4
srlx %o4,32,%o5
brz,pt %o2,.L_bn_mul_add_words_return
stuw %o4,[%o0]
lduw [%o1+4],%g2
lduw [%o0+4],%g1
mulx %o3,%g2,%g2
add %g1,%o5,%o4
dec %o2
add %o4,%g2,%o4
srlx %o4,32,%o5
brz,pt %o2,.L_bn_mul_add_words_return
stuw %o4,[%o0+4]
lduw [%o1+8],%g2
lduw [%o0+8],%g1
mulx %o3,%g2,%g2
add %g1,%o5,%o4
add %o4,%g2,%o4
stuw %o4,[%o0+8]
retl
srlx %o4,32,%o0
.type bn_mul_add_words,#function
.size bn_mul_add_words,(.-bn_mul_add_words)
.align 32
.global bn_mul_words
/*
* BN_ULONG bn_mul_words(rp,ap,num,w)
* BN_ULONG *rp,*ap;
* int num;
* BN_ULONG w;
*/
bn_mul_words:
sra %o2,%g0,%o2 ! signx %o2
brgz,a %o2,.L_bn_mul_words_proceeed
lduw [%o1],%g2
retl
clr %o0
nop
nop
nop
.L_bn_mul_words_proceeed:
srl %o3,%g0,%o3 ! clruw %o3
andcc %o2,-4,%g0
bz,pn %icc,.L_bn_mul_words_tail
clr %o5
.L_bn_mul_words_loop: ! wow! 32 aligned!
lduw [%o1+4],%g3
mulx %o3,%g2,%g2
add %g2,%o5,%o4
nop
stuw %o4,[%o0]
srlx %o4,32,%o5
lduw [%o1+8],%g2
mulx %o3,%g3,%g3
add %g3,%o5,%o4
dec 4,%o2
stuw %o4,[%o0+4]
srlx %o4,32,%o5
lduw [%o1+12],%g3
mulx %o3,%g2,%g2
add %g2,%o5,%o4
inc 16,%o1
stuw %o4,[%o0+8]
srlx %o4,32,%o5
mulx %o3,%g3,%g3
add %g3,%o5,%o4
inc 16,%o0
stuw %o4,[%o0-4]
srlx %o4,32,%o5
andcc %o2,-4,%g0
bnz,a,pt %icc,.L_bn_mul_words_loop
lduw [%o1],%g2
nop
nop
brnz,a,pn %o2,.L_bn_mul_words_tail
lduw [%o1],%g2
.L_bn_mul_words_return:
retl
mov %o5,%o0
.L_bn_mul_words_tail:
mulx %o3,%g2,%g2
add %g2,%o5,%o4
dec %o2
srlx %o4,32,%o5
brz,pt %o2,.L_bn_mul_words_return
stuw %o4,[%o0]
lduw [%o1+4],%g2
mulx %o3,%g2,%g2
add %g2,%o5,%o4
dec %o2
srlx %o4,32,%o5
brz,pt %o2,.L_bn_mul_words_return
stuw %o4,[%o0+4]
lduw [%o1+8],%g2
mulx %o3,%g2,%g2
add %g2,%o5,%o4
stuw %o4,[%o0+8]
retl
srlx %o4,32,%o0
.type bn_mul_words,#function
.size bn_mul_words,(.-bn_mul_words)
.align 32
.global bn_sqr_words
/*
* void bn_sqr_words(r,a,n)
* BN_ULONG *r,*a;
* int n;
*/
bn_sqr_words:
sra %o2,%g0,%o2 ! signx %o2
brgz,a %o2,.L_bn_sqr_words_proceeed
lduw [%o1],%g2
retl
clr %o0
nop
nop
nop
.L_bn_sqr_words_proceeed:
andcc %o2,-4,%g0
nop
bz,pn %icc,.L_bn_sqr_words_tail
nop
.L_bn_sqr_words_loop: ! wow! 32 aligned!
lduw [%o1+4],%g3
mulx %g2,%g2,%o4
stuw %o4,[%o0]
srlx %o4,32,%o5
stuw %o5,[%o0+4]
nop
lduw [%o1+8],%g2
mulx %g3,%g3,%o4
dec 4,%o2
stuw %o4,[%o0+8]
srlx %o4,32,%o5
stuw %o5,[%o0+12]
lduw [%o1+12],%g3
mulx %g2,%g2,%o4
srlx %o4,32,%o5
stuw %o4,[%o0+16]
inc 16,%o1
stuw %o5,[%o0+20]
mulx %g3,%g3,%o4
inc 32,%o0
stuw %o4,[%o0-8]
srlx %o4,32,%o5
andcc %o2,-4,%g2
stuw %o5,[%o0-4]
bnz,a,pt %icc,.L_bn_sqr_words_loop
lduw [%o1],%g2
nop
brnz,a,pn %o2,.L_bn_sqr_words_tail
lduw [%o1],%g2
.L_bn_sqr_words_return:
retl
clr %o0
.L_bn_sqr_words_tail:
mulx %g2,%g2,%o4
dec %o2
stuw %o4,[%o0]
srlx %o4,32,%o5
brz,pt %o2,.L_bn_sqr_words_return
stuw %o5,[%o0+4]
lduw [%o1+4],%g2
mulx %g2,%g2,%o4
dec %o2
stuw %o4,[%o0+8]
srlx %o4,32,%o5
brz,pt %o2,.L_bn_sqr_words_return
stuw %o5,[%o0+12]
lduw [%o1+8],%g2
mulx %g2,%g2,%o4
srlx %o4,32,%o5
stuw %o4,[%o0+16]
stuw %o5,[%o0+20]
retl
clr %o0
.type bn_sqr_words,#function
.size bn_sqr_words,(.-bn_sqr_words)
.align 32
.global bn_div_words
/*
* BN_ULONG bn_div_words(h,l,d)
* BN_ULONG h,l,d;
*/
bn_div_words:
sllx %o0,32,%o0
or %o0,%o1,%o0
udivx %o0,%o2,%o0
retl
srl %o0,%g0,%o0 ! clruw %o0
.type bn_div_words,#function
.size bn_div_words,(.-bn_div_words)
.align 32
.global bn_add_words
/*
* BN_ULONG bn_add_words(rp,ap,bp,n)
* BN_ULONG *rp,*ap,*bp;
* int n;
*/
bn_add_words:
sra %o3,%g0,%o3 ! signx %o3
brgz,a %o3,.L_bn_add_words_proceed
lduw [%o1],%o4
retl
clr %o0
.L_bn_add_words_proceed:
andcc %o3,-4,%g0
bz,pn %icc,.L_bn_add_words_tail
addcc %g0,0,%g0 ! clear carry flag
.L_bn_add_words_loop: ! wow! 32 aligned!
dec 4,%o3
lduw [%o2],%o5
lduw [%o1+4],%g1
lduw [%o2+4],%g2
lduw [%o1+8],%g3
lduw [%o2+8],%g4
addccc %o5,%o4,%o5
stuw %o5,[%o0]
lduw [%o1+12],%o4
lduw [%o2+12],%o5
inc 16,%o1
addccc %g1,%g2,%g1
stuw %g1,[%o0+4]
inc 16,%o2
addccc %g3,%g4,%g3
stuw %g3,[%o0+8]
inc 16,%o0
addccc %o5,%o4,%o5
stuw %o5,[%o0-4]
and %o3,-4,%g1
brnz,a,pt %g1,.L_bn_add_words_loop
lduw [%o1],%o4
brnz,a,pn %o3,.L_bn_add_words_tail
lduw [%o1],%o4
.L_bn_add_words_return:
clr %o0
retl
movcs %icc,1,%o0
nop
.L_bn_add_words_tail:
lduw [%o2],%o5
dec %o3
addccc %o5,%o4,%o5
brz,pt %o3,.L_bn_add_words_return
stuw %o5,[%o0]
lduw [%o1+4],%o4
lduw [%o2+4],%o5
dec %o3
addccc %o5,%o4,%o5
brz,pt %o3,.L_bn_add_words_return
stuw %o5,[%o0+4]
lduw [%o1+8],%o4
lduw [%o2+8],%o5
addccc %o5,%o4,%o5
stuw %o5,[%o0+8]
clr %o0
retl
movcs %icc,1,%o0
.type bn_add_words,#function
.size bn_add_words,(.-bn_add_words)
.global bn_sub_words
/*
* BN_ULONG bn_sub_words(rp,ap,bp,n)
* BN_ULONG *rp,*ap,*bp;
* int n;
*/
bn_sub_words:
sra %o3,%g0,%o3 ! signx %o3
brgz,a %o3,.L_bn_sub_words_proceed
lduw [%o1],%o4
retl
clr %o0
.L_bn_sub_words_proceed:
andcc %o3,-4,%g0
bz,pn %icc,.L_bn_sub_words_tail
addcc %g0,0,%g0 ! clear carry flag
.L_bn_sub_words_loop: ! wow! 32 aligned!
dec 4,%o3
lduw [%o2],%o5
lduw [%o1+4],%g1
lduw [%o2+4],%g2
lduw [%o1+8],%g3
lduw [%o2+8],%g4
subccc %o4,%o5,%o5
stuw %o5,[%o0]
lduw [%o1+12],%o4
lduw [%o2+12],%o5
inc 16,%o1
subccc %g1,%g2,%g2
stuw %g2,[%o0+4]
inc 16,%o2
subccc %g3,%g4,%g4
stuw %g4,[%o0+8]
inc 16,%o0
subccc %o4,%o5,%o5
stuw %o5,[%o0-4]
and %o3,-4,%g1
brnz,a,pt %g1,.L_bn_sub_words_loop
lduw [%o1],%o4
brnz,a,pn %o3,.L_bn_sub_words_tail
lduw [%o1],%o4
.L_bn_sub_words_return:
clr %o0
retl
movcs %icc,1,%o0
nop
.L_bn_sub_words_tail: ! wow! 32 aligned!
lduw [%o2],%o5
dec %o3
subccc %o4,%o5,%o5
brz,pt %o3,.L_bn_sub_words_return
stuw %o5,[%o0]
lduw [%o1+4],%o4
lduw [%o2+4],%o5
dec %o3
subccc %o4,%o5,%o5
brz,pt %o3,.L_bn_sub_words_return
stuw %o5,[%o0+4]
lduw [%o1+8],%o4
lduw [%o2+8],%o5
subccc %o4,%o5,%o5
stuw %o5,[%o0+8]
clr %o0
retl
movcs %icc,1,%o0
.type bn_sub_words,#function
.size bn_sub_words,(.-bn_sub_words)
/*
* Code below depends on the fact that upper parts of the %l0-%l7
* and %i0-%i7 are zeroed by kernel after context switch. In
* previous versions this comment stated that "the trouble is that
* it's not feasible to implement the mumbo-jumbo in less V9
* instructions:-(" which apparently isn't true thanks to
* 'bcs,a %xcc,.+8; inc %rd' pair. But the performance improvement
* results not from the shorter code, but from elimination of
* multicycle none-pairable 'rd %y,%rd' instructions.
*
* Andy.
*/
/*
* Here is register usage map for *all* routines below.
*/
#define t_1 %o0
#define t_2 %o1
#define c_12 %o2
#define c_3 %o3
#define ap(I) [%i1+4*I]
#define bp(I) [%i2+4*I]
#define rp(I) [%i0+4*I]
#define a_0 %l0
#define a_1 %l1
#define a_2 %l2
#define a_3 %l3
#define a_4 %l4
#define a_5 %l5
#define a_6 %l6
#define a_7 %l7
#define b_0 %i3
#define b_1 %i4
#define b_2 %i5
#define b_3 %o4
#define b_4 %o5
#define b_5 %o7
#define b_6 %g1
#define b_7 %g4
.align 32
.global bn_mul_comba8
/*
* void bn_mul_comba8(r,a,b)
* BN_ULONG *r,*a,*b;
*/
bn_mul_comba8:
save %sp,FRAME_SIZE,%sp
mov 1,t_2
lduw ap(0),a_0
sllx t_2,32,t_2
lduw bp(0),b_0 !=
lduw bp(1),b_1
mulx a_0,b_0,t_1 !mul_add_c(a[0],b[0],c1,c2,c3);
srlx t_1,32,c_12
stuw t_1,rp(0) !=!r[0]=c1;
lduw ap(1),a_1
mulx a_0,b_1,t_1 !mul_add_c(a[0],b[1],c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(2),a_2
mulx a_1,b_0,t_1 !=!mul_add_c(a[1],b[0],c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12 !=
stuw t_1,rp(1) !r[1]=c2;
or c_12,c_3,c_12
mulx a_2,b_0,t_1 !mul_add_c(a[2],b[0],c3,c1,c2);
addcc c_12,t_1,c_12 !=
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw bp(2),b_2 !=
mulx a_1,b_1,t_1 !mul_add_c(a[1],b[1],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
lduw bp(3),b_3
mulx a_0,b_2,t_1 !mul_add_c(a[0],b[2],c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(2) !r[2]=c3;
or c_12,c_3,c_12 !=
mulx a_0,b_3,t_1 !mul_add_c(a[0],b[3],c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_1,b_2,t_1 !=!mul_add_c(a[1],b[2],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
lduw ap(3),a_3
mulx a_2,b_1,t_1 !mul_add_c(a[2],b[1],c1,c2,c3);
addcc c_12,t_1,c_12 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(4),a_4
mulx a_3,b_0,t_1 !=!mul_add_c(a[3],b[0],c1,c2,c3);!=
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12 !=
stuw t_1,rp(3) !r[3]=c1;
or c_12,c_3,c_12
mulx a_4,b_0,t_1 !mul_add_c(a[4],b[0],c2,c3,c1);
addcc c_12,t_1,c_12 !=
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,b_1,t_1 !=!mul_add_c(a[3],b[1],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_2,b_2,t_1 !=!mul_add_c(a[2],b[2],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw bp(4),b_4 !=
mulx a_1,b_3,t_1 !mul_add_c(a[1],b[3],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
lduw bp(5),b_5
mulx a_0,b_4,t_1 !mul_add_c(a[0],b[4],c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(4) !r[4]=c2;
or c_12,c_3,c_12 !=
mulx a_0,b_5,t_1 !mul_add_c(a[0],b[5],c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_1,b_4,t_1 !mul_add_c(a[1],b[4],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_2,b_3,t_1 !mul_add_c(a[2],b[3],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_3,b_2,t_1 !mul_add_c(a[3],b[2],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
lduw ap(5),a_5
mulx a_4,b_1,t_1 !mul_add_c(a[4],b[1],c3,c1,c2);
addcc c_12,t_1,c_12 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(6),a_6
mulx a_5,b_0,t_1 !=!mul_add_c(a[5],b[0],c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12 !=
stuw t_1,rp(5) !r[5]=c3;
or c_12,c_3,c_12
mulx a_6,b_0,t_1 !mul_add_c(a[6],b[0],c1,c2,c3);
addcc c_12,t_1,c_12 !=
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_5,b_1,t_1 !=!mul_add_c(a[5],b[1],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_4,b_2,t_1 !=!mul_add_c(a[4],b[2],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,b_3,t_1 !=!mul_add_c(a[3],b[3],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_2,b_4,t_1 !=!mul_add_c(a[2],b[4],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw bp(6),b_6 !=
mulx a_1,b_5,t_1 !mul_add_c(a[1],b[5],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
lduw bp(7),b_7
mulx a_0,b_6,t_1 !mul_add_c(a[0],b[6],c1,c2,c3);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(6) !r[6]=c1;
or c_12,c_3,c_12 !=
mulx a_0,b_7,t_1 !mul_add_c(a[0],b[7],c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_1,b_6,t_1 !mul_add_c(a[1],b[6],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_2,b_5,t_1 !mul_add_c(a[2],b[5],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_3,b_4,t_1 !mul_add_c(a[3],b[4],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_4,b_3,t_1 !mul_add_c(a[4],b[3],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_5,b_2,t_1 !mul_add_c(a[5],b[2],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
lduw ap(7),a_7
mulx a_6,b_1,t_1 !=!mul_add_c(a[6],b[1],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_7,b_0,t_1 !=!mul_add_c(a[7],b[0],c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12 !=
stuw t_1,rp(7) !r[7]=c2;
or c_12,c_3,c_12
mulx a_7,b_1,t_1 !=!mul_add_c(a[7],b[1],c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_6,b_2,t_1 !mul_add_c(a[6],b[2],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_5,b_3,t_1 !mul_add_c(a[5],b[3],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_4,b_4,t_1 !mul_add_c(a[4],b[4],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_3,b_5,t_1 !mul_add_c(a[3],b[5],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_2,b_6,t_1 !mul_add_c(a[2],b[6],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_1,b_7,t_1 !mul_add_c(a[1],b[7],c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
srlx t_1,32,c_12
stuw t_1,rp(8) !r[8]=c3;
or c_12,c_3,c_12
mulx a_2,b_7,t_1 !=!mul_add_c(a[2],b[7],c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
mulx a_3,b_6,t_1 !mul_add_c(a[3],b[6],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_4,b_5,t_1 !mul_add_c(a[4],b[5],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_5,b_4,t_1 !mul_add_c(a[5],b[4],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_6,b_3,t_1 !mul_add_c(a[6],b[3],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_7,b_2,t_1 !mul_add_c(a[7],b[2],c1,c2,c3);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(9) !r[9]=c1;
or c_12,c_3,c_12 !=
mulx a_7,b_3,t_1 !mul_add_c(a[7],b[3],c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_6,b_4,t_1 !mul_add_c(a[6],b[4],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_5,b_5,t_1 !mul_add_c(a[5],b[5],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_4,b_6,t_1 !mul_add_c(a[4],b[6],c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_3,b_7,t_1 !mul_add_c(a[3],b[7],c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(10) !r[10]=c2;
or c_12,c_3,c_12 !=
mulx a_4,b_7,t_1 !mul_add_c(a[4],b[7],c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_5,b_6,t_1 !mul_add_c(a[5],b[6],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_6,b_5,t_1 !mul_add_c(a[6],b[5],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_7,b_4,t_1 !mul_add_c(a[7],b[4],c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(11) !r[11]=c3;
or c_12,c_3,c_12 !=
mulx a_7,b_5,t_1 !mul_add_c(a[7],b[5],c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_6,b_6,t_1 !mul_add_c(a[6],b[6],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_5,b_7,t_1 !mul_add_c(a[5],b[7],c1,c2,c3);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(12) !r[12]=c1;
or c_12,c_3,c_12 !=
mulx a_6,b_7,t_1 !mul_add_c(a[6],b[7],c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_7,b_6,t_1 !mul_add_c(a[7],b[6],c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
st t_1,rp(13) !r[13]=c2;
or c_12,c_3,c_12 !=
mulx a_7,b_7,t_1 !mul_add_c(a[7],b[7],c3,c1,c2);
addcc c_12,t_1,t_1
srlx t_1,32,c_12 !=
stuw t_1,rp(14) !r[14]=c3;
stuw c_12,rp(15) !r[15]=c1;
ret
restore %g0,%g0,%o0 !=
.type bn_mul_comba8,#function
.size bn_mul_comba8,(.-bn_mul_comba8)
.align 32
.global bn_mul_comba4
/*
* void bn_mul_comba4(r,a,b)
* BN_ULONG *r,*a,*b;
*/
bn_mul_comba4:
save %sp,FRAME_SIZE,%sp
lduw ap(0),a_0
mov 1,t_2
lduw bp(0),b_0
sllx t_2,32,t_2 !=
lduw bp(1),b_1
mulx a_0,b_0,t_1 !mul_add_c(a[0],b[0],c1,c2,c3);
srlx t_1,32,c_12
stuw t_1,rp(0) !=!r[0]=c1;
lduw ap(1),a_1
mulx a_0,b_1,t_1 !mul_add_c(a[0],b[1],c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(2),a_2
mulx a_1,b_0,t_1 !=!mul_add_c(a[1],b[0],c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12 !=
stuw t_1,rp(1) !r[1]=c2;
or c_12,c_3,c_12
mulx a_2,b_0,t_1 !mul_add_c(a[2],b[0],c3,c1,c2);
addcc c_12,t_1,c_12 !=
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw bp(2),b_2 !=
mulx a_1,b_1,t_1 !mul_add_c(a[1],b[1],c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3 !=
lduw bp(3),b_3
mulx a_0,b_2,t_1 !mul_add_c(a[0],b[2],c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(2) !r[2]=c3;
or c_12,c_3,c_12 !=
mulx a_0,b_3,t_1 !mul_add_c(a[0],b[3],c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
mulx a_1,b_2,t_1 !mul_add_c(a[1],b[2],c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8 !=
add c_3,t_2,c_3
lduw ap(3),a_3
mulx a_2,b_1,t_1 !mul_add_c(a[2],b[1],c1,c2,c3);
addcc c_12,t_1,c_12 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,b_0,t_1 !mul_add_c(a[3],b[0],c1,c2,c3);!=
addcc c_12,t_1,t_1 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(3) !=!r[3]=c1;
or c_12,c_3,c_12
mulx a_3,b_1,t_1 !mul_add_c(a[3],b[1],c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_2,b_2,t_1 !mul_add_c(a[2],b[2],c2,c3,c1);
addcc c_12,t_1,c_12 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_1,b_3,t_1 !mul_add_c(a[1],b[3],c2,c3,c1);
addcc c_12,t_1,t_1 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(4) !=!r[4]=c2;
or c_12,c_3,c_12
mulx a_2,b_3,t_1 !mul_add_c(a[2],b[3],c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,b_2,t_1 !mul_add_c(a[3],b[2],c3,c1,c2);
addcc c_12,t_1,t_1 !=
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(5) !=!r[5]=c3;
or c_12,c_3,c_12
mulx a_3,b_3,t_1 !mul_add_c(a[3],b[3],c1,c2,c3);
addcc c_12,t_1,t_1
srlx t_1,32,c_12 !=
stuw t_1,rp(6) !r[6]=c1;
stuw c_12,rp(7) !r[7]=c2;
ret
restore %g0,%g0,%o0
.type bn_mul_comba4,#function
.size bn_mul_comba4,(.-bn_mul_comba4)
.align 32
.global bn_sqr_comba8
bn_sqr_comba8:
save %sp,FRAME_SIZE,%sp
mov 1,t_2
lduw ap(0),a_0
sllx t_2,32,t_2
lduw ap(1),a_1
mulx a_0,a_0,t_1 !sqr_add_c(a,0,c1,c2,c3);
srlx t_1,32,c_12
stuw t_1,rp(0) !r[0]=c1;
lduw ap(2),a_2
mulx a_0,a_1,t_1 !=!sqr_add_c2(a,1,0,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(1) !r[1]=c2;
or c_12,c_3,c_12
mulx a_2,a_0,t_1 !sqr_add_c2(a,2,0,c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(3),a_3
mulx a_1,a_1,t_1 !sqr_add_c(a,1,c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(2) !r[2]=c3;
or c_12,c_3,c_12
mulx a_0,a_3,t_1 !sqr_add_c2(a,3,0,c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(4),a_4
mulx a_1,a_2,t_1 !sqr_add_c2(a,2,1,c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
st t_1,rp(3) !r[3]=c1;
or c_12,c_3,c_12
mulx a_4,a_0,t_1 !sqr_add_c2(a,4,0,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,a_1,t_1 !sqr_add_c2(a,3,1,c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(5),a_5
mulx a_2,a_2,t_1 !sqr_add_c(a,2,c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(4) !r[4]=c2;
or c_12,c_3,c_12
mulx a_0,a_5,t_1 !sqr_add_c2(a,5,0,c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_1,a_4,t_1 !sqr_add_c2(a,4,1,c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(6),a_6
mulx a_2,a_3,t_1 !sqr_add_c2(a,3,2,c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(5) !r[5]=c3;
or c_12,c_3,c_12
mulx a_6,a_0,t_1 !sqr_add_c2(a,6,0,c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_5,a_1,t_1 !sqr_add_c2(a,5,1,c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_4,a_2,t_1 !sqr_add_c2(a,4,2,c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(7),a_7
mulx a_3,a_3,t_1 !=!sqr_add_c(a,3,c1,c2,c3);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(6) !r[6]=c1;
or c_12,c_3,c_12
mulx a_0,a_7,t_1 !sqr_add_c2(a,7,0,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_1,a_6,t_1 !sqr_add_c2(a,6,1,c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_2,a_5,t_1 !sqr_add_c2(a,5,2,c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,a_4,t_1 !sqr_add_c2(a,4,3,c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(7) !r[7]=c2;
or c_12,c_3,c_12
mulx a_7,a_1,t_1 !sqr_add_c2(a,7,1,c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_6,a_2,t_1 !sqr_add_c2(a,6,2,c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_5,a_3,t_1 !sqr_add_c2(a,5,3,c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_4,a_4,t_1 !sqr_add_c(a,4,c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(8) !r[8]=c3;
or c_12,c_3,c_12
mulx a_2,a_7,t_1 !sqr_add_c2(a,7,2,c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_3,a_6,t_1 !sqr_add_c2(a,6,3,c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_4,a_5,t_1 !sqr_add_c2(a,5,4,c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(9) !r[9]=c1;
or c_12,c_3,c_12
mulx a_7,a_3,t_1 !sqr_add_c2(a,7,3,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_6,a_4,t_1 !sqr_add_c2(a,6,4,c2,c3,c1);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_5,a_5,t_1 !sqr_add_c(a,5,c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(10) !r[10]=c2;
or c_12,c_3,c_12
mulx a_4,a_7,t_1 !sqr_add_c2(a,7,4,c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_5,a_6,t_1 !sqr_add_c2(a,6,5,c3,c1,c2);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(11) !r[11]=c3;
or c_12,c_3,c_12
mulx a_7,a_5,t_1 !sqr_add_c2(a,7,5,c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_6,a_6,t_1 !sqr_add_c(a,6,c1,c2,c3);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(12) !r[12]=c1;
or c_12,c_3,c_12
mulx a_6,a_7,t_1 !sqr_add_c2(a,7,6,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(13) !r[13]=c2;
or c_12,c_3,c_12
mulx a_7,a_7,t_1 !sqr_add_c(a,7,c3,c1,c2);
addcc c_12,t_1,t_1
srlx t_1,32,c_12
stuw t_1,rp(14) !r[14]=c3;
stuw c_12,rp(15) !r[15]=c1;
ret
restore %g0,%g0,%o0
.type bn_sqr_comba8,#function
.size bn_sqr_comba8,(.-bn_sqr_comba8)
.align 32
.global bn_sqr_comba4
/*
* void bn_sqr_comba4(r,a)
* BN_ULONG *r,*a;
*/
bn_sqr_comba4:
save %sp,FRAME_SIZE,%sp
mov 1,t_2
lduw ap(0),a_0
sllx t_2,32,t_2
lduw ap(1),a_1
mulx a_0,a_0,t_1 !sqr_add_c(a,0,c1,c2,c3);
srlx t_1,32,c_12
stuw t_1,rp(0) !r[0]=c1;
lduw ap(2),a_2
mulx a_0,a_1,t_1 !sqr_add_c2(a,1,0,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(1) !r[1]=c2;
or c_12,c_3,c_12
mulx a_2,a_0,t_1 !sqr_add_c2(a,2,0,c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
lduw ap(3),a_3
mulx a_1,a_1,t_1 !sqr_add_c(a,1,c3,c1,c2);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(2) !r[2]=c3;
or c_12,c_3,c_12
mulx a_0,a_3,t_1 !sqr_add_c2(a,3,0,c1,c2,c3);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_1,a_2,t_1 !sqr_add_c2(a,2,1,c1,c2,c3);
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(3) !r[3]=c1;
or c_12,c_3,c_12
mulx a_3,a_1,t_1 !sqr_add_c2(a,3,1,c2,c3,c1);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,c_12
bcs,a %xcc,.+8
add c_3,t_2,c_3
mulx a_2,a_2,t_1 !sqr_add_c(a,2,c2,c3,c1);
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(4) !r[4]=c2;
or c_12,c_3,c_12
mulx a_2,a_3,t_1 !sqr_add_c2(a,3,2,c3,c1,c2);
addcc c_12,t_1,c_12
clr c_3
bcs,a %xcc,.+8
add c_3,t_2,c_3
addcc c_12,t_1,t_1
bcs,a %xcc,.+8
add c_3,t_2,c_3
srlx t_1,32,c_12
stuw t_1,rp(5) !r[5]=c3;
or c_12,c_3,c_12
mulx a_3,a_3,t_1 !sqr_add_c(a,3,c1,c2,c3);
addcc c_12,t_1,t_1
srlx t_1,32,c_12
stuw t_1,rp(6) !r[6]=c1;
stuw c_12,rp(7) !r[7]=c2;
ret
restore %g0,%g0,%o0
.type bn_sqr_comba4,#function
.size bn_sqr_comba4,(.-bn_sqr_comba4)
.align 32
|
ntu-ssl/rr-artifact | 48,919 | openssl-1.1.0l/crypto/bn/asm/pa-risc2.s | ; Copyright 1998-2016 The OpenSSL Project Authors. All Rights Reserved.
;
; Licensed under the OpenSSL license (the "License"). You may not use
; this file except in compliance with the License. You can obtain a copy
; in the file LICENSE in the source distribution or at
; https://www.openssl.org/source/license.html
;
; PA-RISC 2.0 implementation of bn_asm code, based on the
; 64-bit version of the code. This code is effectively the
; same as the 64-bit version except the register model is
; slightly different given all values must be 32-bit between
; function calls. Thus the 64-bit return values are returned
; in %ret0 and %ret1 vs just %ret0 as is done in 64-bit
;
;
; This code is approximately 2x faster than the C version
; for RSA/DSA.
;
; See http://devresource.hp.com/ for more details on the PA-RISC
; architecture. Also see the book "PA-RISC 2.0 Architecture"
; by Gerry Kane for information on the instruction set architecture.
;
; Code written by Chris Ruemmler (with some help from the HP C
; compiler).
;
; The code compiles with HP's assembler
;
.level 2.0N
.space $TEXT$
.subspa $CODE$,QUAD=0,ALIGN=8,ACCESS=0x2c,CODE_ONLY
;
; Global Register definitions used for the routines.
;
; Some information about HP's runtime architecture for 32-bits.
;
; "Caller save" means the calling function must save the register
; if it wants the register to be preserved.
; "Callee save" means if a function uses the register, it must save
; the value before using it.
;
; For the floating point registers
;
; "caller save" registers: fr4-fr11, fr22-fr31
; "callee save" registers: fr12-fr21
; "special" registers: fr0-fr3 (status and exception registers)
;
; For the integer registers
; value zero : r0
; "caller save" registers: r1,r19-r26
; "callee save" registers: r3-r18
; return register : r2 (rp)
; return values ; r28,r29 (ret0,ret1)
; Stack pointer ; r30 (sp)
; millicode return ptr ; r31 (also a caller save register)
;
; Arguments to the routines
;
r_ptr .reg %r26
a_ptr .reg %r25
b_ptr .reg %r24
num .reg %r24
n .reg %r23
;
; Note that the "w" argument for bn_mul_add_words and bn_mul_words
; is passed on the stack at a delta of -56 from the top of stack
; as the routine is entered.
;
;
; Globals used in some routines
;
top_overflow .reg %r23
high_mask .reg %r22 ; value 0xffffffff80000000L
;------------------------------------------------------------------------------
;
; bn_mul_add_words
;
;BN_ULONG bn_mul_add_words(BN_ULONG *r_ptr, BN_ULONG *a_ptr,
; int num, BN_ULONG w)
;
; arg0 = r_ptr
; arg1 = a_ptr
; arg3 = num
; -56(sp) = w
;
; Local register definitions
;
fm1 .reg %fr22
fm .reg %fr23
ht_temp .reg %fr24
ht_temp_1 .reg %fr25
lt_temp .reg %fr26
lt_temp_1 .reg %fr27
fm1_1 .reg %fr28
fm_1 .reg %fr29
fw_h .reg %fr7L
fw_l .reg %fr7R
fw .reg %fr7
fht_0 .reg %fr8L
flt_0 .reg %fr8R
t_float_0 .reg %fr8
fht_1 .reg %fr9L
flt_1 .reg %fr9R
t_float_1 .reg %fr9
tmp_0 .reg %r31
tmp_1 .reg %r21
m_0 .reg %r20
m_1 .reg %r19
ht_0 .reg %r1
ht_1 .reg %r3
lt_0 .reg %r4
lt_1 .reg %r5
m1_0 .reg %r6
m1_1 .reg %r7
rp_val .reg %r8
rp_val_1 .reg %r9
bn_mul_add_words
.export bn_mul_add_words,entry,NO_RELOCATION,LONG_RETURN
.proc
.callinfo frame=128
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
NOP ; Needed to make the loop 16-byte aligned
NOP ; needed to make the loop 16-byte aligned
STD %r5,16(%sp) ; save r5
NOP
STD %r6,24(%sp) ; save r6
STD %r7,32(%sp) ; save r7
STD %r8,40(%sp) ; save r8
STD %r9,48(%sp) ; save r9
COPY %r0,%ret1 ; return 0 by default
DEPDI,Z 1,31,1,top_overflow ; top_overflow = 1 << 32
CMPIB,>= 0,num,bn_mul_add_words_exit ; if (num <= 0) then exit
LDO 128(%sp),%sp ; bump stack
;
; The loop is unrolled twice, so if there is only 1 number
; then go straight to the cleanup code.
;
CMPIB,= 1,num,bn_mul_add_words_single_top
FLDD -184(%sp),fw ; (-56-128) load up w into fw (fw_h/fw_l)
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
; PA-RISC 2.0 chips have two fully pipelined multipliers, thus
; two 32-bit mutiplies can be issued per cycle.
;
bn_mul_add_words_unroll2
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)
LDD 0(r_ptr),rp_val ; rp[0]
LDD 8(r_ptr),rp_val_1 ; rp[1]
XMPYU fht_0,fw_l,fm1 ; m1[0] = fht_0*fw_l
XMPYU fht_1,fw_l,fm1_1 ; m1[1] = fht_1*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1[0]
FSTD fm1_1,-48(%sp) ; -48(sp) = m1[1]
XMPYU flt_0,fw_h,fm ; m[0] = flt_0*fw_h
XMPYU flt_1,fw_h,fm_1 ; m[1] = flt_1*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m[0]
FSTD fm_1,-40(%sp) ; -40(sp) = m[1]
XMPYU fht_0,fw_h,ht_temp ; ht_temp = fht_0*fw_h
XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp_1 = fht_1*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht_temp
FSTD ht_temp_1,-56(%sp) ; -56(sp) = ht_temp_1
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt_temp
FSTD lt_temp_1,-64(%sp) ; -64(sp) = lt_temp_1
LDD -8(%sp),m_0 ; m[0]
LDD -40(%sp),m_1 ; m[1]
LDD -16(%sp),m1_0 ; m1[0]
LDD -48(%sp),m1_1 ; m1[1]
LDD -24(%sp),ht_0 ; ht[0]
LDD -56(%sp),ht_1 ; ht[1]
ADD,L m1_0,m_0,tmp_0 ; tmp_0 = m[0] + m1[0];
ADD,L m1_1,m_1,tmp_1 ; tmp_1 = m[1] + m1[1];
LDD -32(%sp),lt_0
LDD -64(%sp),lt_1
CMPCLR,*>>= tmp_0,m1_0, %r0 ; if (m[0] < m1[0])
ADD,L ht_0,top_overflow,ht_0 ; ht[0] += (1<<32)
CMPCLR,*>>= tmp_1,m1_1,%r0 ; if (m[1] < m1[1])
ADD,L ht_1,top_overflow,ht_1 ; ht[1] += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m[0]>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1[0] = m[0]<<32
EXTRD,U tmp_1,31,32,m_1 ; m[1]>>32
DEPD,Z tmp_1,31,32,m1_1 ; m1[1] = m[1]<<32
ADD,L ht_0,m_0,ht_0 ; ht[0]+= (m[0]>>32)
ADD,L ht_1,m_1,ht_1 ; ht[1]+= (m[1]>>32)
ADD lt_0,m1_0,lt_0 ; lt[0] = lt[0]+m1[0];
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
ADD lt_1,m1_1,lt_1 ; lt[1] = lt[1]+m1[1];
ADD,DC ht_1,%r0,ht_1 ; ht[1]++
ADD %ret1,lt_0,lt_0 ; lt[0] = lt[0] + c;
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
ADD lt_0,rp_val,lt_0 ; lt[0] = lt[0]+rp[0]
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
LDO -2(num),num ; num = num - 2;
ADD ht_0,lt_1,lt_1 ; lt[1] = lt[1] + ht_0 (c);
ADD,DC ht_1,%r0,ht_1 ; ht[1]++
STD lt_0,0(r_ptr) ; rp[0] = lt[0]
ADD lt_1,rp_val_1,lt_1 ; lt[1] = lt[1]+rp[1]
ADD,DC ht_1,%r0,%ret1 ; ht[1]++
LDO 16(a_ptr),a_ptr ; a_ptr += 2
STD lt_1,8(r_ptr) ; rp[1] = lt[1]
CMPIB,<= 2,num,bn_mul_add_words_unroll2 ; go again if more to do
LDO 16(r_ptr),r_ptr ; r_ptr += 2
CMPIB,=,N 0,num,bn_mul_add_words_exit ; are we done, or cleanup last one
;
; Top of loop aligned on 64-byte boundary
;
bn_mul_add_words_single_top
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
LDD 0(r_ptr),rp_val ; rp[0]
LDO 8(a_ptr),a_ptr ; a_ptr++
XMPYU fht_0,fw_l,fm1 ; m1 = ht*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1
XMPYU flt_0,fw_h,fm ; m = lt*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m
XMPYU fht_0,fw_h,ht_temp ; ht_temp = ht*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt
LDD -8(%sp),m_0
LDD -16(%sp),m1_0 ; m1 = temp1
ADD,L m_0,m1_0,tmp_0 ; tmp_0 = m + m1;
LDD -24(%sp),ht_0
LDD -32(%sp),lt_0
CMPCLR,*>>= tmp_0,m1_0,%r0 ; if (m < m1)
ADD,L ht_0,top_overflow,ht_0 ; ht += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1 = m<<32
ADD,L ht_0,m_0,ht_0 ; ht+= (m>>32)
ADD lt_0,m1_0,tmp_0 ; tmp_0 = lt+m1;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD %ret1,tmp_0,lt_0 ; lt = lt + c;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD lt_0,rp_val,lt_0 ; lt = lt+rp[0]
ADD,DC ht_0,%r0,%ret1 ; ht++
STD lt_0,0(r_ptr) ; rp[0] = lt
bn_mul_add_words_exit
.EXIT
EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1
LDD -80(%sp),%r9 ; restore r9
LDD -88(%sp),%r8 ; restore r8
LDD -96(%sp),%r7 ; restore r7
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3 ; restore r3
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)
;
; arg0 = rp
; arg1 = ap
; arg3 = num
; w on stack at -56(sp)
bn_mul_words
.proc
.callinfo frame=128
.entry
.EXPORT bn_mul_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
NOP
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
STD %r7,32(%sp) ; save r7
COPY %r0,%ret1 ; return 0 by default
DEPDI,Z 1,31,1,top_overflow ; top_overflow = 1 << 32
CMPIB,>= 0,num,bn_mul_words_exit
LDO 128(%sp),%sp ; bump stack
;
; See if only 1 word to do, thus just do cleanup
;
CMPIB,= 1,num,bn_mul_words_single_top
FLDD -184(%sp),fw ; (-56-128) load up w into fw (fw_h/fw_l)
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
; PA-RISC 2.0 chips have two fully pipelined multipliers, thus
; two 32-bit mutiplies can be issued per cycle.
;
bn_mul_words_unroll2
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
FLDD 8(a_ptr),t_float_1 ; load up 64-bit value (fr8L) ht(L)/lt(R)
XMPYU fht_0,fw_l,fm1 ; m1[0] = fht_0*fw_l
XMPYU fht_1,fw_l,fm1_1 ; m1[1] = ht*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1
FSTD fm1_1,-48(%sp) ; -48(sp) = m1
XMPYU flt_0,fw_h,fm ; m = lt*fw_h
XMPYU flt_1,fw_h,fm_1 ; m = lt*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m
FSTD fm_1,-40(%sp) ; -40(sp) = m
XMPYU fht_0,fw_h,ht_temp ; ht_temp = fht_0*fw_h
XMPYU fht_1,fw_h,ht_temp_1 ; ht_temp = ht*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht
FSTD ht_temp_1,-56(%sp) ; -56(sp) = ht
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
XMPYU flt_1,fw_l,lt_temp_1 ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt
FSTD lt_temp_1,-64(%sp) ; -64(sp) = lt
LDD -8(%sp),m_0
LDD -40(%sp),m_1
LDD -16(%sp),m1_0
LDD -48(%sp),m1_1
LDD -24(%sp),ht_0
LDD -56(%sp),ht_1
ADD,L m1_0,m_0,tmp_0 ; tmp_0 = m + m1;
ADD,L m1_1,m_1,tmp_1 ; tmp_1 = m + m1;
LDD -32(%sp),lt_0
LDD -64(%sp),lt_1
CMPCLR,*>>= tmp_0,m1_0, %r0 ; if (m < m1)
ADD,L ht_0,top_overflow,ht_0 ; ht += (1<<32)
CMPCLR,*>>= tmp_1,m1_1,%r0 ; if (m < m1)
ADD,L ht_1,top_overflow,ht_1 ; ht += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1 = m<<32
EXTRD,U tmp_1,31,32,m_1 ; m>>32
DEPD,Z tmp_1,31,32,m1_1 ; m1 = m<<32
ADD,L ht_0,m_0,ht_0 ; ht+= (m>>32)
ADD,L ht_1,m_1,ht_1 ; ht+= (m>>32)
ADD lt_0,m1_0,lt_0 ; lt = lt+m1;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD lt_1,m1_1,lt_1 ; lt = lt+m1;
ADD,DC ht_1,%r0,ht_1 ; ht++
ADD %ret1,lt_0,lt_0 ; lt = lt + c (ret1);
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD ht_0,lt_1,lt_1 ; lt = lt + c (ht_0)
ADD,DC ht_1,%r0,ht_1 ; ht++
STD lt_0,0(r_ptr) ; rp[0] = lt
STD lt_1,8(r_ptr) ; rp[1] = lt
COPY ht_1,%ret1 ; carry = ht
LDO -2(num),num ; num = num - 2;
LDO 16(a_ptr),a_ptr ; ap += 2
CMPIB,<= 2,num,bn_mul_words_unroll2
LDO 16(r_ptr),r_ptr ; rp++
CMPIB,=,N 0,num,bn_mul_words_exit ; are we done?
;
; Top of loop aligned on 64-byte boundary
;
bn_mul_words_single_top
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
XMPYU fht_0,fw_l,fm1 ; m1 = ht*fw_l
FSTD fm1,-16(%sp) ; -16(sp) = m1
XMPYU flt_0,fw_h,fm ; m = lt*fw_h
FSTD fm,-8(%sp) ; -8(sp) = m
XMPYU fht_0,fw_h,ht_temp ; ht_temp = ht*fw_h
FSTD ht_temp,-24(%sp) ; -24(sp) = ht
XMPYU flt_0,fw_l,lt_temp ; lt_temp = lt*fw_l
FSTD lt_temp,-32(%sp) ; -32(sp) = lt
LDD -8(%sp),m_0
LDD -16(%sp),m1_0
ADD,L m_0,m1_0,tmp_0 ; tmp_0 = m + m1;
LDD -24(%sp),ht_0
LDD -32(%sp),lt_0
CMPCLR,*>>= tmp_0,m1_0,%r0 ; if (m < m1)
ADD,L ht_0,top_overflow,ht_0 ; ht += (1<<32)
EXTRD,U tmp_0,31,32,m_0 ; m>>32
DEPD,Z tmp_0,31,32,m1_0 ; m1 = m<<32
ADD,L ht_0,m_0,ht_0 ; ht+= (m>>32)
ADD lt_0,m1_0,lt_0 ; lt= lt+m1;
ADD,DC ht_0,%r0,ht_0 ; ht++
ADD %ret1,lt_0,lt_0 ; lt = lt + c;
ADD,DC ht_0,%r0,ht_0 ; ht++
COPY ht_0,%ret1 ; copy carry
STD lt_0,0(r_ptr) ; rp[0] = lt
bn_mul_words_exit
.EXIT
EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1
LDD -96(%sp),%r7 ; restore r7
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3 ; restore r3
.PROCEND
;----------------------------------------------------------------------------
;
;void bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num)
;
; arg0 = rp
; arg1 = ap
; arg2 = num
;
bn_sqr_words
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_sqr_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
NOP
STD %r5,16(%sp) ; save r5
CMPIB,>= 0,num,bn_sqr_words_exit
LDO 128(%sp),%sp ; bump stack
;
; If only 1, the goto straight to cleanup
;
CMPIB,= 1,num,bn_sqr_words_single_top
DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
bn_sqr_words_unroll2
FLDD 0(a_ptr),t_float_0 ; a[0]
FLDD 8(a_ptr),t_float_1 ; a[1]
XMPYU fht_0,flt_0,fm ; m[0]
XMPYU fht_1,flt_1,fm_1 ; m[1]
FSTD fm,-24(%sp) ; store m[0]
FSTD fm_1,-56(%sp) ; store m[1]
XMPYU flt_0,flt_0,lt_temp ; lt[0]
XMPYU flt_1,flt_1,lt_temp_1 ; lt[1]
FSTD lt_temp,-16(%sp) ; store lt[0]
FSTD lt_temp_1,-48(%sp) ; store lt[1]
XMPYU fht_0,fht_0,ht_temp ; ht[0]
XMPYU fht_1,fht_1,ht_temp_1 ; ht[1]
FSTD ht_temp,-8(%sp) ; store ht[0]
FSTD ht_temp_1,-40(%sp) ; store ht[1]
LDD -24(%sp),m_0
LDD -56(%sp),m_1
AND m_0,high_mask,tmp_0 ; m[0] & Mask
AND m_1,high_mask,tmp_1 ; m[1] & Mask
DEPD,Z m_0,30,31,m_0 ; m[0] << 32+1
DEPD,Z m_1,30,31,m_1 ; m[1] << 32+1
LDD -16(%sp),lt_0
LDD -48(%sp),lt_1
EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m[0]&Mask >> 32-1
EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 = m[1]&Mask >> 32-1
LDD -8(%sp),ht_0
LDD -40(%sp),ht_1
ADD,L ht_0,tmp_0,ht_0 ; ht[0] += tmp_0
ADD,L ht_1,tmp_1,ht_1 ; ht[1] += tmp_1
ADD lt_0,m_0,lt_0 ; lt = lt+m
ADD,DC ht_0,%r0,ht_0 ; ht[0]++
STD lt_0,0(r_ptr) ; rp[0] = lt[0]
STD ht_0,8(r_ptr) ; rp[1] = ht[1]
ADD lt_1,m_1,lt_1 ; lt = lt+m
ADD,DC ht_1,%r0,ht_1 ; ht[1]++
STD lt_1,16(r_ptr) ; rp[2] = lt[1]
STD ht_1,24(r_ptr) ; rp[3] = ht[1]
LDO -2(num),num ; num = num - 2;
LDO 16(a_ptr),a_ptr ; ap += 2
CMPIB,<= 2,num,bn_sqr_words_unroll2
LDO 32(r_ptr),r_ptr ; rp += 4
CMPIB,=,N 0,num,bn_sqr_words_exit ; are we done?
;
; Top of loop aligned on 64-byte boundary
;
bn_sqr_words_single_top
FLDD 0(a_ptr),t_float_0 ; load up 64-bit value (fr8L) ht(L)/lt(R)
XMPYU fht_0,flt_0,fm ; m
FSTD fm,-24(%sp) ; store m
XMPYU flt_0,flt_0,lt_temp ; lt
FSTD lt_temp,-16(%sp) ; store lt
XMPYU fht_0,fht_0,ht_temp ; ht
FSTD ht_temp,-8(%sp) ; store ht
LDD -24(%sp),m_0 ; load m
AND m_0,high_mask,tmp_0 ; m & Mask
DEPD,Z m_0,30,31,m_0 ; m << 32+1
LDD -16(%sp),lt_0 ; lt
LDD -8(%sp),ht_0 ; ht
EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m&Mask >> 32-1
ADD m_0,lt_0,lt_0 ; lt = lt+m
ADD,L ht_0,tmp_0,ht_0 ; ht += tmp_0
ADD,DC ht_0,%r0,ht_0 ; ht++
STD lt_0,0(r_ptr) ; rp[0] = lt
STD ht_0,8(r_ptr) ; rp[1] = ht
bn_sqr_words_exit
.EXIT
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;BN_ULONG bn_add_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)
;
; arg0 = rp
; arg1 = ap
; arg2 = bp
; arg3 = n
t .reg %r22
b .reg %r21
l .reg %r20
bn_add_words
.proc
.entry
.callinfo
.EXPORT bn_add_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.align 64
CMPIB,>= 0,n,bn_add_words_exit
COPY %r0,%ret1 ; return 0 by default
;
; If 2 or more numbers do the loop
;
CMPIB,= 1,n,bn_add_words_single_top
NOP
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
bn_add_words_unroll2
LDD 0(a_ptr),t
LDD 0(b_ptr),b
ADD t,%ret1,t ; t = t+c;
ADD,DC %r0,%r0,%ret1 ; set c to carry
ADD t,b,l ; l = t + b[0]
ADD,DC %ret1,%r0,%ret1 ; c+= carry
STD l,0(r_ptr)
LDD 8(a_ptr),t
LDD 8(b_ptr),b
ADD t,%ret1,t ; t = t+c;
ADD,DC %r0,%r0,%ret1 ; set c to carry
ADD t,b,l ; l = t + b[0]
ADD,DC %ret1,%r0,%ret1 ; c+= carry
STD l,8(r_ptr)
LDO -2(n),n
LDO 16(a_ptr),a_ptr
LDO 16(b_ptr),b_ptr
CMPIB,<= 2,n,bn_add_words_unroll2
LDO 16(r_ptr),r_ptr
CMPIB,=,N 0,n,bn_add_words_exit ; are we done?
bn_add_words_single_top
LDD 0(a_ptr),t
LDD 0(b_ptr),b
ADD t,%ret1,t ; t = t+c;
ADD,DC %r0,%r0,%ret1 ; set c to carry (could use CMPCLR??)
ADD t,b,l ; l = t + b[0]
ADD,DC %ret1,%r0,%ret1 ; c+= carry
STD l,0(r_ptr)
bn_add_words_exit
.EXIT
BVE (%rp)
EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1
.PROCEND ;in=23,24,25,26,29;out=28;
;----------------------------------------------------------------------------
;
;BN_ULONG bn_sub_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)
;
; arg0 = rp
; arg1 = ap
; arg2 = bp
; arg3 = n
t1 .reg %r22
t2 .reg %r21
sub_tmp1 .reg %r20
sub_tmp2 .reg %r19
bn_sub_words
.proc
.callinfo
.EXPORT bn_sub_words,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
CMPIB,>= 0,n,bn_sub_words_exit
COPY %r0,%ret1 ; return 0 by default
;
; If 2 or more numbers do the loop
;
CMPIB,= 1,n,bn_sub_words_single_top
NOP
;
; This loop is unrolled 2 times (64-byte aligned as well)
;
bn_sub_words_unroll2
LDD 0(a_ptr),t1
LDD 0(b_ptr),t2
SUB t1,t2,sub_tmp1 ; t3 = t1-t2;
SUB sub_tmp1,%ret1,sub_tmp1 ; t3 = t3- c;
CMPCLR,*>> t1,t2,sub_tmp2 ; clear if t1 > t2
LDO 1(%r0),sub_tmp2
CMPCLR,*= t1,t2,%r0
COPY sub_tmp2,%ret1
STD sub_tmp1,0(r_ptr)
LDD 8(a_ptr),t1
LDD 8(b_ptr),t2
SUB t1,t2,sub_tmp1 ; t3 = t1-t2;
SUB sub_tmp1,%ret1,sub_tmp1 ; t3 = t3- c;
CMPCLR,*>> t1,t2,sub_tmp2 ; clear if t1 > t2
LDO 1(%r0),sub_tmp2
CMPCLR,*= t1,t2,%r0
COPY sub_tmp2,%ret1
STD sub_tmp1,8(r_ptr)
LDO -2(n),n
LDO 16(a_ptr),a_ptr
LDO 16(b_ptr),b_ptr
CMPIB,<= 2,n,bn_sub_words_unroll2
LDO 16(r_ptr),r_ptr
CMPIB,=,N 0,n,bn_sub_words_exit ; are we done?
bn_sub_words_single_top
LDD 0(a_ptr),t1
LDD 0(b_ptr),t2
SUB t1,t2,sub_tmp1 ; t3 = t1-t2;
SUB sub_tmp1,%ret1,sub_tmp1 ; t3 = t3- c;
CMPCLR,*>> t1,t2,sub_tmp2 ; clear if t1 > t2
LDO 1(%r0),sub_tmp2
CMPCLR,*= t1,t2,%r0
COPY sub_tmp2,%ret1
STD sub_tmp1,0(r_ptr)
bn_sub_words_exit
.EXIT
BVE (%rp)
EXTRD,U %ret1,31,32,%ret0 ; for 32-bit, return in ret0/ret1
.PROCEND ;in=23,24,25,26,29;out=28;
;------------------------------------------------------------------------------
;
; unsigned long bn_div_words(unsigned long h, unsigned long l, unsigned long d)
;
; arg0 = h
; arg1 = l
; arg2 = d
;
; This is mainly just output from the HP C compiler.
;
;------------------------------------------------------------------------------
bn_div_words
.PROC
.EXPORT bn_div_words,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR,RTNVAL=GR,LONG_RETURN
.IMPORT BN_num_bits_word,CODE
;--- not PIC .IMPORT __iob,DATA
;--- not PIC .IMPORT fprintf,CODE
.IMPORT abort,CODE
.IMPORT $$div2U,MILLICODE
.CALLINFO CALLER,FRAME=144,ENTRY_GR=%r9,SAVE_RP,ARGS_SAVED,ORDERING_AWARE
.ENTRY
STW %r2,-20(%r30) ;offset 0x8ec
STW,MA %r3,192(%r30) ;offset 0x8f0
STW %r4,-188(%r30) ;offset 0x8f4
DEPD %r5,31,32,%r6 ;offset 0x8f8
STD %r6,-184(%r30) ;offset 0x8fc
DEPD %r7,31,32,%r8 ;offset 0x900
STD %r8,-176(%r30) ;offset 0x904
STW %r9,-168(%r30) ;offset 0x908
LDD -248(%r30),%r3 ;offset 0x90c
COPY %r26,%r4 ;offset 0x910
COPY %r24,%r5 ;offset 0x914
DEPD %r25,31,32,%r4 ;offset 0x918
CMPB,*<> %r3,%r0,$0006000C ;offset 0x91c
DEPD %r23,31,32,%r5 ;offset 0x920
MOVIB,TR -1,%r29,$00060002 ;offset 0x924
EXTRD,U %r29,31,32,%r28 ;offset 0x928
$0006002A
LDO -1(%r29),%r29 ;offset 0x92c
SUB %r23,%r7,%r23 ;offset 0x930
$00060024
SUB %r4,%r31,%r25 ;offset 0x934
AND %r25,%r19,%r26 ;offset 0x938
CMPB,*<>,N %r0,%r26,$00060046 ;offset 0x93c
DEPD,Z %r25,31,32,%r20 ;offset 0x940
OR %r20,%r24,%r21 ;offset 0x944
CMPB,*<<,N %r21,%r23,$0006002A ;offset 0x948
SUB %r31,%r2,%r31 ;offset 0x94c
$00060046
$0006002E
DEPD,Z %r23,31,32,%r25 ;offset 0x950
EXTRD,U %r23,31,32,%r26 ;offset 0x954
AND %r25,%r19,%r24 ;offset 0x958
ADD,L %r31,%r26,%r31 ;offset 0x95c
CMPCLR,*>>= %r5,%r24,%r0 ;offset 0x960
LDO 1(%r31),%r31 ;offset 0x964
$00060032
CMPB,*<<=,N %r31,%r4,$00060036 ;offset 0x968
LDO -1(%r29),%r29 ;offset 0x96c
ADD,L %r4,%r3,%r4 ;offset 0x970
$00060036
ADDIB,=,N -1,%r8,$D0 ;offset 0x974
SUB %r5,%r24,%r28 ;offset 0x978
$0006003A
SUB %r4,%r31,%r24 ;offset 0x97c
SHRPD %r24,%r28,32,%r4 ;offset 0x980
DEPD,Z %r29,31,32,%r9 ;offset 0x984
DEPD,Z %r28,31,32,%r5 ;offset 0x988
$0006001C
EXTRD,U %r4,31,32,%r31 ;offset 0x98c
CMPB,*<>,N %r31,%r2,$00060020 ;offset 0x990
MOVB,TR %r6,%r29,$D1 ;offset 0x994
STD %r29,-152(%r30) ;offset 0x998
$0006000C
EXTRD,U %r3,31,32,%r25 ;offset 0x99c
COPY %r3,%r26 ;offset 0x9a0
EXTRD,U %r3,31,32,%r9 ;offset 0x9a4
EXTRD,U %r4,31,32,%r8 ;offset 0x9a8
.CALL ARGW0=GR,ARGW1=GR,RTNVAL=GR ;in=25,26;out=28;
B,L BN_num_bits_word,%r2 ;offset 0x9ac
EXTRD,U %r5,31,32,%r7 ;offset 0x9b0
LDI 64,%r20 ;offset 0x9b4
DEPD %r7,31,32,%r5 ;offset 0x9b8
DEPD %r8,31,32,%r4 ;offset 0x9bc
DEPD %r9,31,32,%r3 ;offset 0x9c0
CMPB,= %r28,%r20,$00060012 ;offset 0x9c4
COPY %r28,%r24 ;offset 0x9c8
MTSARCM %r24 ;offset 0x9cc
DEPDI,Z -1,%sar,1,%r19 ;offset 0x9d0
CMPB,*>>,N %r4,%r19,$D2 ;offset 0x9d4
$00060012
SUBI 64,%r24,%r31 ;offset 0x9d8
CMPCLR,*<< %r4,%r3,%r0 ;offset 0x9dc
SUB %r4,%r3,%r4 ;offset 0x9e0
$00060016
CMPB,= %r31,%r0,$0006001A ;offset 0x9e4
COPY %r0,%r9 ;offset 0x9e8
MTSARCM %r31 ;offset 0x9ec
DEPD,Z %r3,%sar,64,%r3 ;offset 0x9f0
SUBI 64,%r31,%r26 ;offset 0x9f4
MTSAR %r26 ;offset 0x9f8
SHRPD %r4,%r5,%sar,%r4 ;offset 0x9fc
MTSARCM %r31 ;offset 0xa00
DEPD,Z %r5,%sar,64,%r5 ;offset 0xa04
$0006001A
DEPDI,Z -1,31,32,%r19 ;offset 0xa08
AND %r3,%r19,%r29 ;offset 0xa0c
EXTRD,U %r29,31,32,%r2 ;offset 0xa10
DEPDI,Z -1,63,32,%r6 ;offset 0xa14
MOVIB,TR 2,%r8,$0006001C ;offset 0xa18
EXTRD,U %r3,63,32,%r7 ;offset 0xa1c
$D2
;--- not PIC ADDIL LR'__iob-$global$,%r27,%r1 ;offset 0xa20
;--- not PIC LDIL LR'C$7,%r21 ;offset 0xa24
;--- not PIC LDO RR'__iob-$global$+32(%r1),%r26 ;offset 0xa28
;--- not PIC .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR ;in=24,25,26;out=28;
;--- not PIC B,L fprintf,%r2 ;offset 0xa2c
;--- not PIC LDO RR'C$7(%r21),%r25 ;offset 0xa30
.CALL ;
B,L abort,%r2 ;offset 0xa34
NOP ;offset 0xa38
B $D3 ;offset 0xa3c
LDW -212(%r30),%r2 ;offset 0xa40
$00060020
COPY %r4,%r26 ;offset 0xa44
EXTRD,U %r4,31,32,%r25 ;offset 0xa48
COPY %r2,%r24 ;offset 0xa4c
.CALL ;in=23,24,25,26;out=20,21,22,28,29; (MILLICALL)
B,L $$div2U,%r31 ;offset 0xa50
EXTRD,U %r2,31,32,%r23 ;offset 0xa54
DEPD %r28,31,32,%r29 ;offset 0xa58
$00060022
STD %r29,-152(%r30) ;offset 0xa5c
$D1
AND %r5,%r19,%r24 ;offset 0xa60
EXTRD,U %r24,31,32,%r24 ;offset 0xa64
STW %r2,-160(%r30) ;offset 0xa68
STW %r7,-128(%r30) ;offset 0xa6c
FLDD -152(%r30),%fr4 ;offset 0xa70
FLDD -152(%r30),%fr7 ;offset 0xa74
FLDW -160(%r30),%fr8L ;offset 0xa78
FLDW -128(%r30),%fr5L ;offset 0xa7c
XMPYU %fr8L,%fr7L,%fr10 ;offset 0xa80
FSTD %fr10,-136(%r30) ;offset 0xa84
XMPYU %fr8L,%fr7R,%fr22 ;offset 0xa88
FSTD %fr22,-144(%r30) ;offset 0xa8c
XMPYU %fr5L,%fr4L,%fr11 ;offset 0xa90
XMPYU %fr5L,%fr4R,%fr23 ;offset 0xa94
FSTD %fr11,-112(%r30) ;offset 0xa98
FSTD %fr23,-120(%r30) ;offset 0xa9c
LDD -136(%r30),%r28 ;offset 0xaa0
DEPD,Z %r28,31,32,%r31 ;offset 0xaa4
LDD -144(%r30),%r20 ;offset 0xaa8
ADD,L %r20,%r31,%r31 ;offset 0xaac
LDD -112(%r30),%r22 ;offset 0xab0
DEPD,Z %r22,31,32,%r22 ;offset 0xab4
LDD -120(%r30),%r21 ;offset 0xab8
B $00060024 ;offset 0xabc
ADD,L %r21,%r22,%r23 ;offset 0xac0
$D0
OR %r9,%r29,%r29 ;offset 0xac4
$00060040
EXTRD,U %r29,31,32,%r28 ;offset 0xac8
$00060002
$L2
LDW -212(%r30),%r2 ;offset 0xacc
$D3
LDW -168(%r30),%r9 ;offset 0xad0
LDD -176(%r30),%r8 ;offset 0xad4
EXTRD,U %r8,31,32,%r7 ;offset 0xad8
LDD -184(%r30),%r6 ;offset 0xadc
EXTRD,U %r6,31,32,%r5 ;offset 0xae0
LDW -188(%r30),%r4 ;offset 0xae4
BVE (%r2) ;offset 0xae8
.EXIT
LDW,MB -192(%r30),%r3 ;offset 0xaec
.PROCEND ;in=23,25;out=28,29;fpin=105,107;
;----------------------------------------------------------------------------
;
; Registers to hold 64-bit values to manipulate. The "L" part
; of the register corresponds to the upper 32-bits, while the "R"
; part corresponds to the lower 32-bits
;
; Note, that when using b6 and b7, the code must save these before
; using them because they are callee save registers
;
;
; Floating point registers to use to save values that
; are manipulated. These don't collide with ftemp1-6 and
; are all caller save registers
;
a0 .reg %fr22
a0L .reg %fr22L
a0R .reg %fr22R
a1 .reg %fr23
a1L .reg %fr23L
a1R .reg %fr23R
a2 .reg %fr24
a2L .reg %fr24L
a2R .reg %fr24R
a3 .reg %fr25
a3L .reg %fr25L
a3R .reg %fr25R
a4 .reg %fr26
a4L .reg %fr26L
a4R .reg %fr26R
a5 .reg %fr27
a5L .reg %fr27L
a5R .reg %fr27R
a6 .reg %fr28
a6L .reg %fr28L
a6R .reg %fr28R
a7 .reg %fr29
a7L .reg %fr29L
a7R .reg %fr29R
b0 .reg %fr30
b0L .reg %fr30L
b0R .reg %fr30R
b1 .reg %fr31
b1L .reg %fr31L
b1R .reg %fr31R
;
; Temporary floating point variables, these are all caller save
; registers
;
ftemp1 .reg %fr4
ftemp2 .reg %fr5
ftemp3 .reg %fr6
ftemp4 .reg %fr7
;
; The B set of registers when used.
;
b2 .reg %fr8
b2L .reg %fr8L
b2R .reg %fr8R
b3 .reg %fr9
b3L .reg %fr9L
b3R .reg %fr9R
b4 .reg %fr10
b4L .reg %fr10L
b4R .reg %fr10R
b5 .reg %fr11
b5L .reg %fr11L
b5R .reg %fr11R
b6 .reg %fr12
b6L .reg %fr12L
b6R .reg %fr12R
b7 .reg %fr13
b7L .reg %fr13L
b7R .reg %fr13R
c1 .reg %r21 ; only reg
temp1 .reg %r20 ; only reg
temp2 .reg %r19 ; only reg
temp3 .reg %r31 ; only reg
m1 .reg %r28
c2 .reg %r23
high_one .reg %r1
ht .reg %r6
lt .reg %r5
m .reg %r4
c3 .reg %r3
SQR_ADD_C .macro A0L,A0R,C1,C2,C3
XMPYU A0L,A0R,ftemp1 ; m
FSTD ftemp1,-24(%sp) ; store m
XMPYU A0R,A0R,ftemp2 ; lt
FSTD ftemp2,-16(%sp) ; store lt
XMPYU A0L,A0L,ftemp3 ; ht
FSTD ftemp3,-8(%sp) ; store ht
LDD -24(%sp),m ; load m
AND m,high_mask,temp2 ; m & Mask
DEPD,Z m,30,31,temp3 ; m << 32+1
LDD -16(%sp),lt ; lt
LDD -8(%sp),ht ; ht
EXTRD,U temp2,32,33,temp1 ; temp1 = m&Mask >> 32-1
ADD temp3,lt,lt ; lt = lt+m
ADD,L ht,temp1,ht ; ht += temp1
ADD,DC ht,%r0,ht ; ht++
ADD C1,lt,C1 ; c1=c1+lt
ADD,DC ht,%r0,ht ; ht++
ADD C2,ht,C2 ; c2=c2+ht
ADD,DC C3,%r0,C3 ; c3++
.endm
SQR_ADD_C2 .macro A0L,A0R,A1L,A1R,C1,C2,C3
XMPYU A0L,A1R,ftemp1 ; m1 = bl*ht
FSTD ftemp1,-16(%sp) ;
XMPYU A0R,A1L,ftemp2 ; m = bh*lt
FSTD ftemp2,-8(%sp) ;
XMPYU A0R,A1R,ftemp3 ; lt = bl*lt
FSTD ftemp3,-32(%sp)
XMPYU A0L,A1L,ftemp4 ; ht = bh*ht
FSTD ftemp4,-24(%sp) ;
LDD -8(%sp),m ; r21 = m
LDD -16(%sp),m1 ; r19 = m1
ADD,L m,m1,m ; m+m1
DEPD,Z m,31,32,temp3 ; (m+m1<<32)
LDD -24(%sp),ht ; r24 = ht
CMPCLR,*>>= m,m1,%r0 ; if (m < m1)
ADD,L ht,high_one,ht ; ht+=high_one
EXTRD,U m,31,32,temp1 ; m >> 32
LDD -32(%sp),lt ; lt
ADD,L ht,temp1,ht ; ht+= m>>32
ADD lt,temp3,lt ; lt = lt+m1
ADD,DC ht,%r0,ht ; ht++
ADD ht,ht,ht ; ht=ht+ht;
ADD,DC C3,%r0,C3 ; add in carry (c3++)
ADD lt,lt,lt ; lt=lt+lt;
ADD,DC ht,%r0,ht ; add in carry (ht++)
ADD C1,lt,C1 ; c1=c1+lt
ADD,DC,*NUV ht,%r0,ht ; add in carry (ht++)
LDO 1(C3),C3 ; bump c3 if overflow,nullify otherwise
ADD C2,ht,C2 ; c2 = c2 + ht
ADD,DC C3,%r0,C3 ; add in carry (c3++)
.endm
;
;void bn_sqr_comba8(BN_ULONG *r, BN_ULONG *a)
; arg0 = r_ptr
; arg1 = a_ptr
;
bn_sqr_comba8
.PROC
.CALLINFO FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_sqr_comba8,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.ENTRY
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 32(a_ptr),a4
FLDD 40(a_ptr),a5
FLDD 48(a_ptr),a6
FLDD 56(a_ptr),a7
SQR_ADD_C a0L,a0R,c1,c2,c3
STD c1,0(r_ptr) ; r[0] = c1;
COPY %r0,c1
SQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1
STD c2,8(r_ptr) ; r[1] = c2;
COPY %r0,c2
SQR_ADD_C a1L,a1R,c3,c1,c2
SQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2
STD c3,16(r_ptr) ; r[2] = c3;
COPY %r0,c3
SQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3
SQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3
STD c1,24(r_ptr) ; r[3] = c1;
COPY %r0,c1
SQR_ADD_C a2L,a2R,c2,c3,c1
SQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1
SQR_ADD_C2 a4L,a4R,a0L,a0R,c2,c3,c1
STD c2,32(r_ptr) ; r[4] = c2;
COPY %r0,c2
SQR_ADD_C2 a5L,a5R,a0L,a0R,c3,c1,c2
SQR_ADD_C2 a4L,a4R,a1L,a1R,c3,c1,c2
SQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2
STD c3,40(r_ptr) ; r[5] = c3;
COPY %r0,c3
SQR_ADD_C a3L,a3R,c1,c2,c3
SQR_ADD_C2 a4L,a4R,a2L,a2R,c1,c2,c3
SQR_ADD_C2 a5L,a5R,a1L,a1R,c1,c2,c3
SQR_ADD_C2 a6L,a6R,a0L,a0R,c1,c2,c3
STD c1,48(r_ptr) ; r[6] = c1;
COPY %r0,c1
SQR_ADD_C2 a7L,a7R,a0L,a0R,c2,c3,c1
SQR_ADD_C2 a6L,a6R,a1L,a1R,c2,c3,c1
SQR_ADD_C2 a5L,a5R,a2L,a2R,c2,c3,c1
SQR_ADD_C2 a4L,a4R,a3L,a3R,c2,c3,c1
STD c2,56(r_ptr) ; r[7] = c2;
COPY %r0,c2
SQR_ADD_C a4L,a4R,c3,c1,c2
SQR_ADD_C2 a5L,a5R,a3L,a3R,c3,c1,c2
SQR_ADD_C2 a6L,a6R,a2L,a2R,c3,c1,c2
SQR_ADD_C2 a7L,a7R,a1L,a1R,c3,c1,c2
STD c3,64(r_ptr) ; r[8] = c3;
COPY %r0,c3
SQR_ADD_C2 a7L,a7R,a2L,a2R,c1,c2,c3
SQR_ADD_C2 a6L,a6R,a3L,a3R,c1,c2,c3
SQR_ADD_C2 a5L,a5R,a4L,a4R,c1,c2,c3
STD c1,72(r_ptr) ; r[9] = c1;
COPY %r0,c1
SQR_ADD_C a5L,a5R,c2,c3,c1
SQR_ADD_C2 a6L,a6R,a4L,a4R,c2,c3,c1
SQR_ADD_C2 a7L,a7R,a3L,a3R,c2,c3,c1
STD c2,80(r_ptr) ; r[10] = c2;
COPY %r0,c2
SQR_ADD_C2 a7L,a7R,a4L,a4R,c3,c1,c2
SQR_ADD_C2 a6L,a6R,a5L,a5R,c3,c1,c2
STD c3,88(r_ptr) ; r[11] = c3;
COPY %r0,c3
SQR_ADD_C a6L,a6R,c1,c2,c3
SQR_ADD_C2 a7L,a7R,a5L,a5R,c1,c2,c3
STD c1,96(r_ptr) ; r[12] = c1;
COPY %r0,c1
SQR_ADD_C2 a7L,a7R,a6L,a6R,c2,c3,c1
STD c2,104(r_ptr) ; r[13] = c2;
COPY %r0,c2
SQR_ADD_C a7L,a7R,c3,c1,c2
STD c3, 112(r_ptr) ; r[14] = c3
STD c1, 120(r_ptr) ; r[15] = c1
.EXIT
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;-----------------------------------------------------------------------------
;
;void bn_sqr_comba4(BN_ULONG *r, BN_ULONG *a)
; arg0 = r_ptr
; arg1 = a_ptr
;
bn_sqr_comba4
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_sqr_comba4,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 32(a_ptr),a4
FLDD 40(a_ptr),a5
FLDD 48(a_ptr),a6
FLDD 56(a_ptr),a7
SQR_ADD_C a0L,a0R,c1,c2,c3
STD c1,0(r_ptr) ; r[0] = c1;
COPY %r0,c1
SQR_ADD_C2 a1L,a1R,a0L,a0R,c2,c3,c1
STD c2,8(r_ptr) ; r[1] = c2;
COPY %r0,c2
SQR_ADD_C a1L,a1R,c3,c1,c2
SQR_ADD_C2 a2L,a2R,a0L,a0R,c3,c1,c2
STD c3,16(r_ptr) ; r[2] = c3;
COPY %r0,c3
SQR_ADD_C2 a3L,a3R,a0L,a0R,c1,c2,c3
SQR_ADD_C2 a2L,a2R,a1L,a1R,c1,c2,c3
STD c1,24(r_ptr) ; r[3] = c1;
COPY %r0,c1
SQR_ADD_C a2L,a2R,c2,c3,c1
SQR_ADD_C2 a3L,a3R,a1L,a1R,c2,c3,c1
STD c2,32(r_ptr) ; r[4] = c2;
COPY %r0,c2
SQR_ADD_C2 a3L,a3R,a2L,a2R,c3,c1,c2
STD c3,40(r_ptr) ; r[5] = c3;
COPY %r0,c3
SQR_ADD_C a3L,a3R,c1,c2,c3
STD c1,48(r_ptr) ; r[6] = c1;
STD c2,56(r_ptr) ; r[7] = c2;
.EXIT
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;---------------------------------------------------------------------------
MUL_ADD_C .macro A0L,A0R,B0L,B0R,C1,C2,C3
XMPYU A0L,B0R,ftemp1 ; m1 = bl*ht
FSTD ftemp1,-16(%sp) ;
XMPYU A0R,B0L,ftemp2 ; m = bh*lt
FSTD ftemp2,-8(%sp) ;
XMPYU A0R,B0R,ftemp3 ; lt = bl*lt
FSTD ftemp3,-32(%sp)
XMPYU A0L,B0L,ftemp4 ; ht = bh*ht
FSTD ftemp4,-24(%sp) ;
LDD -8(%sp),m ; r21 = m
LDD -16(%sp),m1 ; r19 = m1
ADD,L m,m1,m ; m+m1
DEPD,Z m,31,32,temp3 ; (m+m1<<32)
LDD -24(%sp),ht ; r24 = ht
CMPCLR,*>>= m,m1,%r0 ; if (m < m1)
ADD,L ht,high_one,ht ; ht+=high_one
EXTRD,U m,31,32,temp1 ; m >> 32
LDD -32(%sp),lt ; lt
ADD,L ht,temp1,ht ; ht+= m>>32
ADD lt,temp3,lt ; lt = lt+m1
ADD,DC ht,%r0,ht ; ht++
ADD C1,lt,C1 ; c1=c1+lt
ADD,DC ht,%r0,ht ; bump c3 if overflow,nullify otherwise
ADD C2,ht,C2 ; c2 = c2 + ht
ADD,DC C3,%r0,C3 ; add in carry (c3++)
.endm
;
;void bn_mul_comba8(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
; arg0 = r_ptr
; arg1 = a_ptr
; arg2 = b_ptr
;
bn_mul_comba8
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_mul_comba8,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
FSTD %fr12,32(%sp) ; save r6
FSTD %fr13,40(%sp) ; save r7
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 32(a_ptr),a4
FLDD 40(a_ptr),a5
FLDD 48(a_ptr),a6
FLDD 56(a_ptr),a7
FLDD 0(b_ptr),b0
FLDD 8(b_ptr),b1
FLDD 16(b_ptr),b2
FLDD 24(b_ptr),b3
FLDD 32(b_ptr),b4
FLDD 40(b_ptr),b5
FLDD 48(b_ptr),b6
FLDD 56(b_ptr),b7
MUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3
STD c1,0(r_ptr)
COPY %r0,c1
MUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1
MUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1
STD c2,8(r_ptr)
COPY %r0,c2
MUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2
MUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2
MUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2
STD c3,16(r_ptr)
COPY %r0,c3
MUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3
MUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3
MUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3
MUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3
STD c1,24(r_ptr)
COPY %r0,c1
MUL_ADD_C a4L,a4R,b0L,b0R,c2,c3,c1
MUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1
MUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1
MUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1
MUL_ADD_C a0L,a0R,b4L,b4R,c2,c3,c1
STD c2,32(r_ptr)
COPY %r0,c2
MUL_ADD_C a0L,a0R,b5L,b5R,c3,c1,c2
MUL_ADD_C a1L,a1R,b4L,b4R,c3,c1,c2
MUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2
MUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2
MUL_ADD_C a4L,a4R,b1L,b1R,c3,c1,c2
MUL_ADD_C a5L,a5R,b0L,b0R,c3,c1,c2
STD c3,40(r_ptr)
COPY %r0,c3
MUL_ADD_C a6L,a6R,b0L,b0R,c1,c2,c3
MUL_ADD_C a5L,a5R,b1L,b1R,c1,c2,c3
MUL_ADD_C a4L,a4R,b2L,b2R,c1,c2,c3
MUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3
MUL_ADD_C a2L,a2R,b4L,b4R,c1,c2,c3
MUL_ADD_C a1L,a1R,b5L,b5R,c1,c2,c3
MUL_ADD_C a0L,a0R,b6L,b6R,c1,c2,c3
STD c1,48(r_ptr)
COPY %r0,c1
MUL_ADD_C a0L,a0R,b7L,b7R,c2,c3,c1
MUL_ADD_C a1L,a1R,b6L,b6R,c2,c3,c1
MUL_ADD_C a2L,a2R,b5L,b5R,c2,c3,c1
MUL_ADD_C a3L,a3R,b4L,b4R,c2,c3,c1
MUL_ADD_C a4L,a4R,b3L,b3R,c2,c3,c1
MUL_ADD_C a5L,a5R,b2L,b2R,c2,c3,c1
MUL_ADD_C a6L,a6R,b1L,b1R,c2,c3,c1
MUL_ADD_C a7L,a7R,b0L,b0R,c2,c3,c1
STD c2,56(r_ptr)
COPY %r0,c2
MUL_ADD_C a7L,a7R,b1L,b1R,c3,c1,c2
MUL_ADD_C a6L,a6R,b2L,b2R,c3,c1,c2
MUL_ADD_C a5L,a5R,b3L,b3R,c3,c1,c2
MUL_ADD_C a4L,a4R,b4L,b4R,c3,c1,c2
MUL_ADD_C a3L,a3R,b5L,b5R,c3,c1,c2
MUL_ADD_C a2L,a2R,b6L,b6R,c3,c1,c2
MUL_ADD_C a1L,a1R,b7L,b7R,c3,c1,c2
STD c3,64(r_ptr)
COPY %r0,c3
MUL_ADD_C a2L,a2R,b7L,b7R,c1,c2,c3
MUL_ADD_C a3L,a3R,b6L,b6R,c1,c2,c3
MUL_ADD_C a4L,a4R,b5L,b5R,c1,c2,c3
MUL_ADD_C a5L,a5R,b4L,b4R,c1,c2,c3
MUL_ADD_C a6L,a6R,b3L,b3R,c1,c2,c3
MUL_ADD_C a7L,a7R,b2L,b2R,c1,c2,c3
STD c1,72(r_ptr)
COPY %r0,c1
MUL_ADD_C a7L,a7R,b3L,b3R,c2,c3,c1
MUL_ADD_C a6L,a6R,b4L,b4R,c2,c3,c1
MUL_ADD_C a5L,a5R,b5L,b5R,c2,c3,c1
MUL_ADD_C a4L,a4R,b6L,b6R,c2,c3,c1
MUL_ADD_C a3L,a3R,b7L,b7R,c2,c3,c1
STD c2,80(r_ptr)
COPY %r0,c2
MUL_ADD_C a4L,a4R,b7L,b7R,c3,c1,c2
MUL_ADD_C a5L,a5R,b6L,b6R,c3,c1,c2
MUL_ADD_C a6L,a6R,b5L,b5R,c3,c1,c2
MUL_ADD_C a7L,a7R,b4L,b4R,c3,c1,c2
STD c3,88(r_ptr)
COPY %r0,c3
MUL_ADD_C a7L,a7R,b5L,b5R,c1,c2,c3
MUL_ADD_C a6L,a6R,b6L,b6R,c1,c2,c3
MUL_ADD_C a5L,a5R,b7L,b7R,c1,c2,c3
STD c1,96(r_ptr)
COPY %r0,c1
MUL_ADD_C a6L,a6R,b7L,b7R,c2,c3,c1
MUL_ADD_C a7L,a7R,b6L,b6R,c2,c3,c1
STD c2,104(r_ptr)
COPY %r0,c2
MUL_ADD_C a7L,a7R,b7L,b7R,c3,c1,c2
STD c3,112(r_ptr)
STD c1,120(r_ptr)
.EXIT
FLDD -88(%sp),%fr13
FLDD -96(%sp),%fr12
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;-----------------------------------------------------------------------------
;
;void bn_mul_comba4(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b)
; arg0 = r_ptr
; arg1 = a_ptr
; arg2 = b_ptr
;
bn_mul_comba4
.proc
.callinfo FRAME=128,ENTRY_GR=%r3,ARGS_SAVED,ORDERING_AWARE
.EXPORT bn_mul_comba4,ENTRY,PRIV_LEV=3,NO_RELOCATION,LONG_RETURN
.entry
.align 64
STD %r3,0(%sp) ; save r3
STD %r4,8(%sp) ; save r4
STD %r5,16(%sp) ; save r5
STD %r6,24(%sp) ; save r6
FSTD %fr12,32(%sp) ; save r6
FSTD %fr13,40(%sp) ; save r7
;
; Zero out carries
;
COPY %r0,c1
COPY %r0,c2
COPY %r0,c3
LDO 128(%sp),%sp ; bump stack
DEPDI,Z 1,31,1,high_one ; Create Value 1 << 32
;
; Load up all of the values we are going to use
;
FLDD 0(a_ptr),a0
FLDD 8(a_ptr),a1
FLDD 16(a_ptr),a2
FLDD 24(a_ptr),a3
FLDD 0(b_ptr),b0
FLDD 8(b_ptr),b1
FLDD 16(b_ptr),b2
FLDD 24(b_ptr),b3
MUL_ADD_C a0L,a0R,b0L,b0R,c1,c2,c3
STD c1,0(r_ptr)
COPY %r0,c1
MUL_ADD_C a0L,a0R,b1L,b1R,c2,c3,c1
MUL_ADD_C a1L,a1R,b0L,b0R,c2,c3,c1
STD c2,8(r_ptr)
COPY %r0,c2
MUL_ADD_C a2L,a2R,b0L,b0R,c3,c1,c2
MUL_ADD_C a1L,a1R,b1L,b1R,c3,c1,c2
MUL_ADD_C a0L,a0R,b2L,b2R,c3,c1,c2
STD c3,16(r_ptr)
COPY %r0,c3
MUL_ADD_C a0L,a0R,b3L,b3R,c1,c2,c3
MUL_ADD_C a1L,a1R,b2L,b2R,c1,c2,c3
MUL_ADD_C a2L,a2R,b1L,b1R,c1,c2,c3
MUL_ADD_C a3L,a3R,b0L,b0R,c1,c2,c3
STD c1,24(r_ptr)
COPY %r0,c1
MUL_ADD_C a3L,a3R,b1L,b1R,c2,c3,c1
MUL_ADD_C a2L,a2R,b2L,b2R,c2,c3,c1
MUL_ADD_C a1L,a1R,b3L,b3R,c2,c3,c1
STD c2,32(r_ptr)
COPY %r0,c2
MUL_ADD_C a2L,a2R,b3L,b3R,c3,c1,c2
MUL_ADD_C a3L,a3R,b2L,b2R,c3,c1,c2
STD c3,40(r_ptr)
COPY %r0,c3
MUL_ADD_C a3L,a3R,b3L,b3R,c1,c2,c3
STD c1,48(r_ptr)
STD c2,56(r_ptr)
.EXIT
FLDD -88(%sp),%fr13
FLDD -96(%sp),%fr12
LDD -104(%sp),%r6 ; restore r6
LDD -112(%sp),%r5 ; restore r5
LDD -120(%sp),%r4 ; restore r4
BVE (%rp)
LDD,MB -128(%sp),%r3
.PROCEND
;--- not PIC .SPACE $TEXT$
;--- not PIC .SUBSPA $CODE$
;--- not PIC .SPACE $PRIVATE$,SORT=16
;--- not PIC .IMPORT $global$,DATA
;--- not PIC .SPACE $TEXT$
;--- not PIC .SUBSPA $CODE$
;--- not PIC .SUBSPA $LIT$,ACCESS=0x2c
;--- not PIC C$7
;--- not PIC .ALIGN 8
;--- not PIC .STRINGZ "Division would overflow (%d)\n"
.END
|
ntu-ssl/rr-artifact | 41,622 | openssl-1.1.0l/crypto/aes/asm/aes-ia64.S | // Copyright 2004-2016 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under the OpenSSL license (the "License"). You may not use
// this file except in compliance with the License. You can obtain a copy
// in the file LICENSE in the source distribution or at
// https://www.openssl.org/source/license.html
//
// ====================================================================
// Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
// project. Rights for redistribution and usage in source and binary
// forms are granted according to the OpenSSL license.
// ====================================================================
//
// What's wrong with compiler generated code? Compiler never uses
// variable 'shr' which is pairable with 'extr'/'dep' instructions.
// Then it uses 'zxt' which is an I-type, but can be replaced with
// 'and' which in turn can be assigned to M-port [there're double as
// much M-ports as there're I-ports on Itanium 2]. By sacrificing few
// registers for small constants (255, 24 and 16) to be used with
// 'shr' and 'and' instructions I can achieve better ILP, Instruction
// Level Parallelism, and performance. This code outperforms GCC 3.3
// generated code by over factor of 2 (two), GCC 3.4 - by 70% and
// HP C - by 40%. Measured best-case scenario, i.e. aligned
// big-endian input, ECB timing on Itanium 2 is (18 + 13*rounds)
// ticks per block, or 9.25 CPU cycles per byte for 128 bit key.
// Version 1.2 mitigates the hazard of cache-timing attacks by
// a) compressing S-boxes from 8KB to 2KB+256B, b) scheduling
// references to S-boxes for L2 cache latency, c) prefetching T[ed]4
// prior last round. As result performance dropped to (26 + 15*rounds)
// ticks per block or 11 cycles per byte processed with 128-bit key.
// This is ~16% deterioration. For reference Itanium 2 L1 cache has
// 64 bytes line size and L2 - 128 bytes...
.ident "aes-ia64.S, version 1.2"
.ident "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
.explicit
.text
rk0=r8; rk1=r9;
pfssave=r2;
lcsave=r10;
prsave=r3;
maskff=r11;
twenty4=r14;
sixteen=r15;
te00=r16; te11=r17; te22=r18; te33=r19;
te01=r20; te12=r21; te23=r22; te30=r23;
te02=r24; te13=r25; te20=r26; te31=r27;
te03=r28; te10=r29; te21=r30; te32=r31;
// these are rotating...
t0=r32; s0=r33;
t1=r34; s1=r35;
t2=r36; s2=r37;
t3=r38; s3=r39;
te0=r40; te1=r41; te2=r42; te3=r43;
#if defined(_HPUX_SOURCE) && !defined(_LP64)
# define ADDP addp4
#else
# define ADDP add
#endif
// Offsets from Te0
#define TE0 0
#define TE2 2
#if defined(_HPUX_SOURCE) || defined(B_ENDIAN)
#define TE1 3
#define TE3 1
#else
#define TE1 1
#define TE3 3
#endif
// This implies that AES_KEY comprises 32-bit key schedule elements
// even on LP64 platforms.
#ifndef KSZ
# define KSZ 4
# define LDKEY ld4
#endif
.proc _ia64_AES_encrypt#
// Input: rk0-rk1
// te0
// te3 as AES_KEY->rounds!!!
// s0-s3
// maskff,twenty4,sixteen
// Output: r16,r20,r24,r28 as s0-s3
// Clobber: r16-r31,rk0-rk1,r32-r43
.align 32
_ia64_AES_encrypt:
.prologue
.altrp b6
.body
{ .mmi; alloc r16=ar.pfs,12,0,0,8
LDKEY t0=[rk0],2*KSZ
mov pr.rot=1<<16 }
{ .mmi; LDKEY t1=[rk1],2*KSZ
add te1=TE1,te0
add te3=-3,te3 };;
{ .mib; LDKEY t2=[rk0],2*KSZ
mov ar.ec=2 }
{ .mib; LDKEY t3=[rk1],2*KSZ
add te2=TE2,te0
brp.loop.imp .Le_top,.Le_end-16 };;
{ .mmi; xor s0=s0,t0
xor s1=s1,t1
mov ar.lc=te3 }
{ .mmi; xor s2=s2,t2
xor s3=s3,t3
add te3=TE3,te0 };;
.align 32
.Le_top:
{ .mmi; (p0) LDKEY t0=[rk0],2*KSZ // 0/0:rk[0]
(p0) and te33=s3,maskff // 0/0:s3&0xff
(p0) extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
{ .mmi; (p0) LDKEY t1=[rk1],2*KSZ // 0/1:rk[1]
(p0) and te30=s0,maskff // 0/1:s0&0xff
(p0) shr.u te00=s0,twenty4 };; // 0/0:s0>>24
{ .mmi; (p0) LDKEY t2=[rk0],2*KSZ // 1/2:rk[2]
(p0) shladd te33=te33,3,te3 // 1/0:te0+s0>>24
(p0) extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
{ .mmi; (p0) LDKEY t3=[rk1],2*KSZ // 1/3:rk[3]
(p0) shladd te30=te30,3,te3 // 1/1:te3+s0
(p0) shr.u te01=s1,twenty4 };; // 1/1:s1>>24
{ .mmi; (p0) ld4 te33=[te33] // 2/0:te3[s3&0xff]
(p0) shladd te22=te22,3,te2 // 2/0:te2+s2>>8&0xff
(p0) extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
{ .mmi; (p0) ld4 te30=[te30] // 2/1:te3[s0]
(p0) shladd te23=te23,3,te2 // 2/1:te2+s3>>8
(p0) shr.u te02=s2,twenty4 };; // 2/2:s2>>24
{ .mmi; (p0) ld4 te22=[te22] // 3/0:te2[s2>>8]
(p0) shladd te20=te20,3,te2 // 3/2:te2+s0>>8
(p0) extr.u te21=s1,8,8 } // 3/3:s1>>8&0xff
{ .mmi; (p0) ld4 te23=[te23] // 3/1:te2[s3>>8]
(p0) shladd te00=te00,3,te0 // 3/0:te0+s0>>24
(p0) shr.u te03=s3,twenty4 };; // 3/3:s3>>24
{ .mmi; (p0) ld4 te20=[te20] // 4/2:te2[s0>>8]
(p0) shladd te21=te21,3,te2 // 4/3:te3+s2
(p0) extr.u te11=s1,16,8 } // 4/0:s1>>16&0xff
{ .mmi; (p0) ld4 te00=[te00] // 4/0:te0[s0>>24]
(p0) shladd te01=te01,3,te0 // 4/1:te0+s1>>24
(p0) shr.u te13=s3,sixteen };; // 4/2:s3>>16
{ .mmi; (p0) ld4 te21=[te21] // 5/3:te2[s1>>8]
(p0) shladd te11=te11,3,te1 // 5/0:te1+s1>>16
(p0) extr.u te12=s2,16,8 } // 5/1:s2>>16&0xff
{ .mmi; (p0) ld4 te01=[te01] // 5/1:te0[s1>>24]
(p0) shladd te02=te02,3,te0 // 5/2:te0+s2>>24
(p0) and te31=s1,maskff };; // 5/2:s1&0xff
{ .mmi; (p0) ld4 te11=[te11] // 6/0:te1[s1>>16]
(p0) shladd te12=te12,3,te1 // 6/1:te1+s2>>16
(p0) extr.u te10=s0,16,8 } // 6/3:s0>>16&0xff
{ .mmi; (p0) ld4 te02=[te02] // 6/2:te0[s2>>24]
(p0) shladd te03=te03,3,te0 // 6/3:te1+s0>>16
(p0) and te32=s2,maskff };; // 6/3:s2&0xff
{ .mmi; (p0) ld4 te12=[te12] // 7/1:te1[s2>>16]
(p0) shladd te31=te31,3,te3 // 7/2:te3+s1&0xff
(p0) and te13=te13,maskff} // 7/2:s3>>16&0xff
{ .mmi; (p0) ld4 te03=[te03] // 7/3:te0[s3>>24]
(p0) shladd te32=te32,3,te3 // 7/3:te3+s2
(p0) xor t0=t0,te33 };; // 7/0:
{ .mmi; (p0) ld4 te31=[te31] // 8/2:te3[s1]
(p0) shladd te13=te13,3,te1 // 8/2:te1+s3>>16
(p0) xor t0=t0,te22 } // 8/0:
{ .mmi; (p0) ld4 te32=[te32] // 8/3:te3[s2]
(p0) shladd te10=te10,3,te1 // 8/3:te1+s0>>16
(p0) xor t1=t1,te30 };; // 8/1:
{ .mmi; (p0) ld4 te13=[te13] // 9/2:te1[s3>>16]
(p0) ld4 te10=[te10] // 9/3:te1[s0>>16]
(p0) xor t0=t0,te00 };; // 9/0: !L2 scheduling
{ .mmi; (p0) xor t1=t1,te23 // 10[9]/1:
(p0) xor t2=t2,te20 // 10[9]/2:
(p0) xor t3=t3,te21 };; // 10[9]/3:
{ .mmi; (p0) xor t0=t0,te11 // 11[10]/0:done!
(p0) xor t1=t1,te01 // 11[10]/1:
(p0) xor t2=t2,te02 };; // 11[10]/2: !L2 scheduling
{ .mmi; (p0) xor t3=t3,te03 // 12[10]/3:
(p16) cmp.eq p0,p17=r0,r0 };; // 12[10]/clear (p17)
{ .mmi; (p0) xor t1=t1,te12 // 13[11]/1:done!
(p0) xor t2=t2,te31 // 13[11]/2:
(p0) xor t3=t3,te32 } // 13[11]/3:
{ .mmi; (p17) add te0=2048,te0 // 13[11]/
(p17) add te1=2048+64-TE1,te1};; // 13[11]/
{ .mib; (p0) xor t2=t2,te13 // 14[12]/2:done!
(p17) add te2=2048+128-TE2,te2} // 14[12]/
{ .mib; (p0) xor t3=t3,te10 // 14[12]/3:done!
(p17) add te3=2048+192-TE3,te3 // 14[12]/
br.ctop.sptk .Le_top };;
.Le_end:
{ .mmi; ld8 te12=[te0] // prefetch Te4
ld8 te31=[te1] }
{ .mmi; ld8 te10=[te2]
ld8 te32=[te3] }
{ .mmi; LDKEY t0=[rk0],2*KSZ // 0/0:rk[0]
and te33=s3,maskff // 0/0:s3&0xff
extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
{ .mmi; LDKEY t1=[rk1],2*KSZ // 0/1:rk[1]
and te30=s0,maskff // 0/1:s0&0xff
shr.u te00=s0,twenty4 };; // 0/0:s0>>24
{ .mmi; LDKEY t2=[rk0],2*KSZ // 1/2:rk[2]
add te33=te33,te0 // 1/0:te0+s0>>24
extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
{ .mmi; LDKEY t3=[rk1],2*KSZ // 1/3:rk[3]
add te30=te30,te0 // 1/1:te0+s0
shr.u te01=s1,twenty4 };; // 1/1:s1>>24
{ .mmi; ld1 te33=[te33] // 2/0:te0[s3&0xff]
add te22=te22,te0 // 2/0:te0+s2>>8&0xff
extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
{ .mmi; ld1 te30=[te30] // 2/1:te0[s0]
add te23=te23,te0 // 2/1:te0+s3>>8
shr.u te02=s2,twenty4 };; // 2/2:s2>>24
{ .mmi; ld1 te22=[te22] // 3/0:te0[s2>>8]
add te20=te20,te0 // 3/2:te0+s0>>8
extr.u te21=s1,8,8 } // 3/3:s1>>8&0xff
{ .mmi; ld1 te23=[te23] // 3/1:te0[s3>>8]
add te00=te00,te0 // 3/0:te0+s0>>24
shr.u te03=s3,twenty4 };; // 3/3:s3>>24
{ .mmi; ld1 te20=[te20] // 4/2:te0[s0>>8]
add te21=te21,te0 // 4/3:te0+s2
extr.u te11=s1,16,8 } // 4/0:s1>>16&0xff
{ .mmi; ld1 te00=[te00] // 4/0:te0[s0>>24]
add te01=te01,te0 // 4/1:te0+s1>>24
shr.u te13=s3,sixteen };; // 4/2:s3>>16
{ .mmi; ld1 te21=[te21] // 5/3:te0[s1>>8]
add te11=te11,te0 // 5/0:te0+s1>>16
extr.u te12=s2,16,8 } // 5/1:s2>>16&0xff
{ .mmi; ld1 te01=[te01] // 5/1:te0[s1>>24]
add te02=te02,te0 // 5/2:te0+s2>>24
and te31=s1,maskff };; // 5/2:s1&0xff
{ .mmi; ld1 te11=[te11] // 6/0:te0[s1>>16]
add te12=te12,te0 // 6/1:te0+s2>>16
extr.u te10=s0,16,8 } // 6/3:s0>>16&0xff
{ .mmi; ld1 te02=[te02] // 6/2:te0[s2>>24]
add te03=te03,te0 // 6/3:te0+s0>>16
and te32=s2,maskff };; // 6/3:s2&0xff
{ .mmi; ld1 te12=[te12] // 7/1:te0[s2>>16]
add te31=te31,te0 // 7/2:te0+s1&0xff
dep te33=te22,te33,8,8} // 7/0:
{ .mmi; ld1 te03=[te03] // 7/3:te0[s3>>24]
add te32=te32,te0 // 7/3:te0+s2
and te13=te13,maskff};; // 7/2:s3>>16&0xff
{ .mmi; ld1 te31=[te31] // 8/2:te0[s1]
add te13=te13,te0 // 8/2:te0+s3>>16
dep te30=te23,te30,8,8} // 8/1:
{ .mmi; ld1 te32=[te32] // 8/3:te0[s2]
add te10=te10,te0 // 8/3:te0+s0>>16
shl te00=te00,twenty4};; // 8/0:
{ .mii; ld1 te13=[te13] // 9/2:te0[s3>>16]
dep te33=te11,te33,16,8 // 9/0:
shl te01=te01,twenty4};; // 9/1:
{ .mii; ld1 te10=[te10] // 10/3:te0[s0>>16]
dep te31=te20,te31,8,8 // 10/2:
shl te02=te02,twenty4};; // 10/2:
{ .mii; xor t0=t0,te33 // 11/0:
dep te32=te21,te32,8,8 // 11/3:
shl te12=te12,sixteen};; // 11/1:
{ .mii; xor r16=t0,te00 // 12/0:done!
dep te31=te13,te31,16,8 // 12/2:
shl te03=te03,twenty4};; // 12/3:
{ .mmi; xor t1=t1,te01 // 13/1:
xor t2=t2,te02 // 13/2:
dep te32=te10,te32,16,8};; // 13/3:
{ .mmi; xor t1=t1,te30 // 14/1:
xor r24=t2,te31 // 14/2:done!
xor t3=t3,te32 };; // 14/3:
{ .mib; xor r20=t1,te12 // 15/1:done!
xor r28=t3,te03 // 15/3:done!
br.ret.sptk b6 };;
.endp _ia64_AES_encrypt#
// void AES_encrypt (const void *in,void *out,const AES_KEY *key);
.global AES_encrypt#
.proc AES_encrypt#
.align 32
AES_encrypt:
.prologue
.save ar.pfs,pfssave
{ .mmi; alloc pfssave=ar.pfs,3,1,12,0
and out0=3,in0
mov r3=ip }
{ .mmi; ADDP in0=0,in0
mov loc0=psr.um
ADDP out11=KSZ*60,in2 };; // &AES_KEY->rounds
{ .mmi; ld4 out11=[out11] // AES_KEY->rounds
add out8=(AES_Te#-AES_encrypt#),r3 // Te0
.save pr,prsave
mov prsave=pr }
{ .mmi; rum 1<<3 // clear um.ac
.save ar.lc,lcsave
mov lcsave=ar.lc };;
.body
#if defined(_HPUX_SOURCE) // HPUX is big-endian, cut 15+15 cycles...
{ .mib; cmp.ne p6,p0=out0,r0
add out0=4,in0
(p6) br.dpnt.many .Le_i_unaligned };;
{ .mmi; ld4 out1=[in0],8 // s0
and out9=3,in1
mov twenty4=24 }
{ .mmi; ld4 out3=[out0],8 // s1
ADDP rk0=0,in2
mov sixteen=16 };;
{ .mmi; ld4 out5=[in0] // s2
cmp.ne p6,p0=out9,r0
mov maskff=0xff }
{ .mmb; ld4 out7=[out0] // s3
ADDP rk1=KSZ,in2
br.call.sptk.many b6=_ia64_AES_encrypt };;
{ .mib; ADDP in0=4,in1
ADDP in1=0,in1
(p6) br.spnt .Le_o_unaligned };;
{ .mii; mov psr.um=loc0
mov ar.pfs=pfssave
mov ar.lc=lcsave };;
{ .mmi; st4 [in1]=r16,8 // s0
st4 [in0]=r20,8 // s1
mov pr=prsave,0x1ffff };;
{ .mmb; st4 [in1]=r24 // s2
st4 [in0]=r28 // s3
br.ret.sptk.many b0 };;
#endif
.align 32
.Le_i_unaligned:
{ .mmi; add out0=1,in0
add out2=2,in0
add out4=3,in0 };;
{ .mmi; ld1 r16=[in0],4
ld1 r17=[out0],4 }//;;
{ .mmi; ld1 r18=[out2],4
ld1 out1=[out4],4 };; // s0
{ .mmi; ld1 r20=[in0],4
ld1 r21=[out0],4 }//;;
{ .mmi; ld1 r22=[out2],4
ld1 out3=[out4],4 };; // s1
{ .mmi; ld1 r24=[in0],4
ld1 r25=[out0],4 }//;;
{ .mmi; ld1 r26=[out2],4
ld1 out5=[out4],4 };; // s2
{ .mmi; ld1 r28=[in0]
ld1 r29=[out0] }//;;
{ .mmi; ld1 r30=[out2]
ld1 out7=[out4] };; // s3
{ .mii;
dep out1=r16,out1,24,8 //;;
dep out3=r20,out3,24,8 }//;;
{ .mii; ADDP rk0=0,in2
dep out5=r24,out5,24,8 //;;
dep out7=r28,out7,24,8 };;
{ .mii; ADDP rk1=KSZ,in2
dep out1=r17,out1,16,8 //;;
dep out3=r21,out3,16,8 }//;;
{ .mii; mov twenty4=24
dep out5=r25,out5,16,8 //;;
dep out7=r29,out7,16,8 };;
{ .mii; mov sixteen=16
dep out1=r18,out1,8,8 //;;
dep out3=r22,out3,8,8 }//;;
{ .mii; mov maskff=0xff
dep out5=r26,out5,8,8 //;;
dep out7=r30,out7,8,8 };;
{ .mib; br.call.sptk.many b6=_ia64_AES_encrypt };;
.Le_o_unaligned:
{ .mii; ADDP out0=0,in1
extr.u r17=r16,8,8 // s0
shr.u r19=r16,twenty4 }//;;
{ .mii; ADDP out1=1,in1
extr.u r18=r16,16,8
shr.u r23=r20,twenty4 }//;; // s1
{ .mii; ADDP out2=2,in1
extr.u r21=r20,8,8
shr.u r22=r20,sixteen }//;;
{ .mii; ADDP out3=3,in1
extr.u r25=r24,8,8 // s2
shr.u r27=r24,twenty4 };;
{ .mii; st1 [out3]=r16,4
extr.u r26=r24,16,8
shr.u r31=r28,twenty4 }//;; // s3
{ .mii; st1 [out2]=r17,4
extr.u r29=r28,8,8
shr.u r30=r28,sixteen }//;;
{ .mmi; st1 [out1]=r18,4
st1 [out0]=r19,4 };;
{ .mmi; st1 [out3]=r20,4
st1 [out2]=r21,4 }//;;
{ .mmi; st1 [out1]=r22,4
st1 [out0]=r23,4 };;
{ .mmi; st1 [out3]=r24,4
st1 [out2]=r25,4
mov pr=prsave,0x1ffff }//;;
{ .mmi; st1 [out1]=r26,4
st1 [out0]=r27,4
mov ar.pfs=pfssave };;
{ .mmi; st1 [out3]=r28
st1 [out2]=r29
mov ar.lc=lcsave }//;;
{ .mmi; st1 [out1]=r30
st1 [out0]=r31 }
{ .mfb; mov psr.um=loc0 // restore user mask
br.ret.sptk.many b0 };;
.endp AES_encrypt#
// *AES_decrypt are autogenerated by the following script:
#if 0
#!/usr/bin/env perl
print "// *AES_decrypt are autogenerated by the following script:\n#if 0\n";
open(PROG,'<'.$0); while(<PROG>) { print; } close(PROG);
print "#endif\n";
while(<>) {
$process=1 if (/\.proc\s+_ia64_AES_encrypt/);
next if (!$process);
#s/te00=s0/td00=s0/; s/te00/td00/g;
s/te11=s1/td13=s3/; s/te11/td13/g;
#s/te22=s2/td22=s2/; s/te22/td22/g;
s/te33=s3/td31=s1/; s/te33/td31/g;
#s/te01=s1/td01=s1/; s/te01/td01/g;
s/te12=s2/td10=s0/; s/te12/td10/g;
#s/te23=s3/td23=s3/; s/te23/td23/g;
s/te30=s0/td32=s2/; s/te30/td32/g;
#s/te02=s2/td02=s2/; s/te02/td02/g;
s/te13=s3/td11=s1/; s/te13/td11/g;
#s/te20=s0/td20=s0/; s/te20/td20/g;
s/te31=s1/td33=s3/; s/te31/td33/g;
#s/te03=s3/td03=s3/; s/te03/td03/g;
s/te10=s0/td12=s2/; s/te10/td12/g;
#s/te21=s1/td21=s1/; s/te21/td21/g;
s/te32=s2/td30=s0/; s/te32/td30/g;
s/td/te/g;
s/AES_encrypt/AES_decrypt/g;
s/\.Le_/.Ld_/g;
s/AES_Te#/AES_Td#/g;
print;
exit if (/\.endp\s+AES_decrypt/);
}
#endif
.proc _ia64_AES_decrypt#
// Input: rk0-rk1
// te0
// te3 as AES_KEY->rounds!!!
// s0-s3
// maskff,twenty4,sixteen
// Output: r16,r20,r24,r28 as s0-s3
// Clobber: r16-r31,rk0-rk1,r32-r43
.align 32
_ia64_AES_decrypt:
.prologue
.altrp b6
.body
{ .mmi; alloc r16=ar.pfs,12,0,0,8
LDKEY t0=[rk0],2*KSZ
mov pr.rot=1<<16 }
{ .mmi; LDKEY t1=[rk1],2*KSZ
add te1=TE1,te0
add te3=-3,te3 };;
{ .mib; LDKEY t2=[rk0],2*KSZ
mov ar.ec=2 }
{ .mib; LDKEY t3=[rk1],2*KSZ
add te2=TE2,te0
brp.loop.imp .Ld_top,.Ld_end-16 };;
{ .mmi; xor s0=s0,t0
xor s1=s1,t1
mov ar.lc=te3 }
{ .mmi; xor s2=s2,t2
xor s3=s3,t3
add te3=TE3,te0 };;
.align 32
.Ld_top:
{ .mmi; (p0) LDKEY t0=[rk0],2*KSZ // 0/0:rk[0]
(p0) and te31=s1,maskff // 0/0:s3&0xff
(p0) extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
{ .mmi; (p0) LDKEY t1=[rk1],2*KSZ // 0/1:rk[1]
(p0) and te32=s2,maskff // 0/1:s0&0xff
(p0) shr.u te00=s0,twenty4 };; // 0/0:s0>>24
{ .mmi; (p0) LDKEY t2=[rk0],2*KSZ // 1/2:rk[2]
(p0) shladd te31=te31,3,te3 // 1/0:te0+s0>>24
(p0) extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
{ .mmi; (p0) LDKEY t3=[rk1],2*KSZ // 1/3:rk[3]
(p0) shladd te32=te32,3,te3 // 1/1:te3+s0
(p0) shr.u te01=s1,twenty4 };; // 1/1:s1>>24
{ .mmi; (p0) ld4 te31=[te31] // 2/0:te3[s3&0xff]
(p0) shladd te22=te22,3,te2 // 2/0:te2+s2>>8&0xff
(p0) extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
{ .mmi; (p0) ld4 te32=[te32] // 2/1:te3[s0]
(p0) shladd te23=te23,3,te2 // 2/1:te2+s3>>8
(p0) shr.u te02=s2,twenty4 };; // 2/2:s2>>24
{ .mmi; (p0) ld4 te22=[te22] // 3/0:te2[s2>>8]
(p0) shladd te20=te20,3,te2 // 3/2:te2+s0>>8
(p0) extr.u te21=s1,8,8 } // 3/3:s1>>8&0xff
{ .mmi; (p0) ld4 te23=[te23] // 3/1:te2[s3>>8]
(p0) shladd te00=te00,3,te0 // 3/0:te0+s0>>24
(p0) shr.u te03=s3,twenty4 };; // 3/3:s3>>24
{ .mmi; (p0) ld4 te20=[te20] // 4/2:te2[s0>>8]
(p0) shladd te21=te21,3,te2 // 4/3:te3+s2
(p0) extr.u te13=s3,16,8 } // 4/0:s1>>16&0xff
{ .mmi; (p0) ld4 te00=[te00] // 4/0:te0[s0>>24]
(p0) shladd te01=te01,3,te0 // 4/1:te0+s1>>24
(p0) shr.u te11=s1,sixteen };; // 4/2:s3>>16
{ .mmi; (p0) ld4 te21=[te21] // 5/3:te2[s1>>8]
(p0) shladd te13=te13,3,te1 // 5/0:te1+s1>>16
(p0) extr.u te10=s0,16,8 } // 5/1:s2>>16&0xff
{ .mmi; (p0) ld4 te01=[te01] // 5/1:te0[s1>>24]
(p0) shladd te02=te02,3,te0 // 5/2:te0+s2>>24
(p0) and te33=s3,maskff };; // 5/2:s1&0xff
{ .mmi; (p0) ld4 te13=[te13] // 6/0:te1[s1>>16]
(p0) shladd te10=te10,3,te1 // 6/1:te1+s2>>16
(p0) extr.u te12=s2,16,8 } // 6/3:s0>>16&0xff
{ .mmi; (p0) ld4 te02=[te02] // 6/2:te0[s2>>24]
(p0) shladd te03=te03,3,te0 // 6/3:te1+s0>>16
(p0) and te30=s0,maskff };; // 6/3:s2&0xff
{ .mmi; (p0) ld4 te10=[te10] // 7/1:te1[s2>>16]
(p0) shladd te33=te33,3,te3 // 7/2:te3+s1&0xff
(p0) and te11=te11,maskff} // 7/2:s3>>16&0xff
{ .mmi; (p0) ld4 te03=[te03] // 7/3:te0[s3>>24]
(p0) shladd te30=te30,3,te3 // 7/3:te3+s2
(p0) xor t0=t0,te31 };; // 7/0:
{ .mmi; (p0) ld4 te33=[te33] // 8/2:te3[s1]
(p0) shladd te11=te11,3,te1 // 8/2:te1+s3>>16
(p0) xor t0=t0,te22 } // 8/0:
{ .mmi; (p0) ld4 te30=[te30] // 8/3:te3[s2]
(p0) shladd te12=te12,3,te1 // 8/3:te1+s0>>16
(p0) xor t1=t1,te32 };; // 8/1:
{ .mmi; (p0) ld4 te11=[te11] // 9/2:te1[s3>>16]
(p0) ld4 te12=[te12] // 9/3:te1[s0>>16]
(p0) xor t0=t0,te00 };; // 9/0: !L2 scheduling
{ .mmi; (p0) xor t1=t1,te23 // 10[9]/1:
(p0) xor t2=t2,te20 // 10[9]/2:
(p0) xor t3=t3,te21 };; // 10[9]/3:
{ .mmi; (p0) xor t0=t0,te13 // 11[10]/0:done!
(p0) xor t1=t1,te01 // 11[10]/1:
(p0) xor t2=t2,te02 };; // 11[10]/2: !L2 scheduling
{ .mmi; (p0) xor t3=t3,te03 // 12[10]/3:
(p16) cmp.eq p0,p17=r0,r0 };; // 12[10]/clear (p17)
{ .mmi; (p0) xor t1=t1,te10 // 13[11]/1:done!
(p0) xor t2=t2,te33 // 13[11]/2:
(p0) xor t3=t3,te30 } // 13[11]/3:
{ .mmi; (p17) add te0=2048,te0 // 13[11]/
(p17) add te1=2048+64-TE1,te1};; // 13[11]/
{ .mib; (p0) xor t2=t2,te11 // 14[12]/2:done!
(p17) add te2=2048+128-TE2,te2} // 14[12]/
{ .mib; (p0) xor t3=t3,te12 // 14[12]/3:done!
(p17) add te3=2048+192-TE3,te3 // 14[12]/
br.ctop.sptk .Ld_top };;
.Ld_end:
{ .mmi; ld8 te10=[te0] // prefetch Td4
ld8 te33=[te1] }
{ .mmi; ld8 te12=[te2]
ld8 te30=[te3] }
{ .mmi; LDKEY t0=[rk0],2*KSZ // 0/0:rk[0]
and te31=s1,maskff // 0/0:s3&0xff
extr.u te22=s2,8,8 } // 0/0:s2>>8&0xff
{ .mmi; LDKEY t1=[rk1],2*KSZ // 0/1:rk[1]
and te32=s2,maskff // 0/1:s0&0xff
shr.u te00=s0,twenty4 };; // 0/0:s0>>24
{ .mmi; LDKEY t2=[rk0],2*KSZ // 1/2:rk[2]
add te31=te31,te0 // 1/0:te0+s0>>24
extr.u te23=s3,8,8 } // 1/1:s3>>8&0xff
{ .mmi; LDKEY t3=[rk1],2*KSZ // 1/3:rk[3]
add te32=te32,te0 // 1/1:te0+s0
shr.u te01=s1,twenty4 };; // 1/1:s1>>24
{ .mmi; ld1 te31=[te31] // 2/0:te0[s3&0xff]
add te22=te22,te0 // 2/0:te0+s2>>8&0xff
extr.u te20=s0,8,8 } // 2/2:s0>>8&0xff
{ .mmi; ld1 te32=[te32] // 2/1:te0[s0]
add te23=te23,te0 // 2/1:te0+s3>>8
shr.u te02=s2,twenty4 };; // 2/2:s2>>24
{ .mmi; ld1 te22=[te22] // 3/0:te0[s2>>8]
add te20=te20,te0 // 3/2:te0+s0>>8
extr.u te21=s1,8,8 } // 3/3:s1>>8&0xff
{ .mmi; ld1 te23=[te23] // 3/1:te0[s3>>8]
add te00=te00,te0 // 3/0:te0+s0>>24
shr.u te03=s3,twenty4 };; // 3/3:s3>>24
{ .mmi; ld1 te20=[te20] // 4/2:te0[s0>>8]
add te21=te21,te0 // 4/3:te0+s2
extr.u te13=s3,16,8 } // 4/0:s1>>16&0xff
{ .mmi; ld1 te00=[te00] // 4/0:te0[s0>>24]
add te01=te01,te0 // 4/1:te0+s1>>24
shr.u te11=s1,sixteen };; // 4/2:s3>>16
{ .mmi; ld1 te21=[te21] // 5/3:te0[s1>>8]
add te13=te13,te0 // 5/0:te0+s1>>16
extr.u te10=s0,16,8 } // 5/1:s2>>16&0xff
{ .mmi; ld1 te01=[te01] // 5/1:te0[s1>>24]
add te02=te02,te0 // 5/2:te0+s2>>24
and te33=s3,maskff };; // 5/2:s1&0xff
{ .mmi; ld1 te13=[te13] // 6/0:te0[s1>>16]
add te10=te10,te0 // 6/1:te0+s2>>16
extr.u te12=s2,16,8 } // 6/3:s0>>16&0xff
{ .mmi; ld1 te02=[te02] // 6/2:te0[s2>>24]
add te03=te03,te0 // 6/3:te0+s0>>16
and te30=s0,maskff };; // 6/3:s2&0xff
{ .mmi; ld1 te10=[te10] // 7/1:te0[s2>>16]
add te33=te33,te0 // 7/2:te0+s1&0xff
dep te31=te22,te31,8,8} // 7/0:
{ .mmi; ld1 te03=[te03] // 7/3:te0[s3>>24]
add te30=te30,te0 // 7/3:te0+s2
and te11=te11,maskff};; // 7/2:s3>>16&0xff
{ .mmi; ld1 te33=[te33] // 8/2:te0[s1]
add te11=te11,te0 // 8/2:te0+s3>>16
dep te32=te23,te32,8,8} // 8/1:
{ .mmi; ld1 te30=[te30] // 8/3:te0[s2]
add te12=te12,te0 // 8/3:te0+s0>>16
shl te00=te00,twenty4};; // 8/0:
{ .mii; ld1 te11=[te11] // 9/2:te0[s3>>16]
dep te31=te13,te31,16,8 // 9/0:
shl te01=te01,twenty4};; // 9/1:
{ .mii; ld1 te12=[te12] // 10/3:te0[s0>>16]
dep te33=te20,te33,8,8 // 10/2:
shl te02=te02,twenty4};; // 10/2:
{ .mii; xor t0=t0,te31 // 11/0:
dep te30=te21,te30,8,8 // 11/3:
shl te10=te10,sixteen};; // 11/1:
{ .mii; xor r16=t0,te00 // 12/0:done!
dep te33=te11,te33,16,8 // 12/2:
shl te03=te03,twenty4};; // 12/3:
{ .mmi; xor t1=t1,te01 // 13/1:
xor t2=t2,te02 // 13/2:
dep te30=te12,te30,16,8};; // 13/3:
{ .mmi; xor t1=t1,te32 // 14/1:
xor r24=t2,te33 // 14/2:done!
xor t3=t3,te30 };; // 14/3:
{ .mib; xor r20=t1,te10 // 15/1:done!
xor r28=t3,te03 // 15/3:done!
br.ret.sptk b6 };;
.endp _ia64_AES_decrypt#
// void AES_decrypt (const void *in,void *out,const AES_KEY *key);
.global AES_decrypt#
.proc AES_decrypt#
.align 32
AES_decrypt:
.prologue
.save ar.pfs,pfssave
{ .mmi; alloc pfssave=ar.pfs,3,1,12,0
and out0=3,in0
mov r3=ip }
{ .mmi; ADDP in0=0,in0
mov loc0=psr.um
ADDP out11=KSZ*60,in2 };; // &AES_KEY->rounds
{ .mmi; ld4 out11=[out11] // AES_KEY->rounds
add out8=(AES_Td#-AES_decrypt#),r3 // Te0
.save pr,prsave
mov prsave=pr }
{ .mmi; rum 1<<3 // clear um.ac
.save ar.lc,lcsave
mov lcsave=ar.lc };;
.body
#if defined(_HPUX_SOURCE) // HPUX is big-endian, cut 15+15 cycles...
{ .mib; cmp.ne p6,p0=out0,r0
add out0=4,in0
(p6) br.dpnt.many .Ld_i_unaligned };;
{ .mmi; ld4 out1=[in0],8 // s0
and out9=3,in1
mov twenty4=24 }
{ .mmi; ld4 out3=[out0],8 // s1
ADDP rk0=0,in2
mov sixteen=16 };;
{ .mmi; ld4 out5=[in0] // s2
cmp.ne p6,p0=out9,r0
mov maskff=0xff }
{ .mmb; ld4 out7=[out0] // s3
ADDP rk1=KSZ,in2
br.call.sptk.many b6=_ia64_AES_decrypt };;
{ .mib; ADDP in0=4,in1
ADDP in1=0,in1
(p6) br.spnt .Ld_o_unaligned };;
{ .mii; mov psr.um=loc0
mov ar.pfs=pfssave
mov ar.lc=lcsave };;
{ .mmi; st4 [in1]=r16,8 // s0
st4 [in0]=r20,8 // s1
mov pr=prsave,0x1ffff };;
{ .mmb; st4 [in1]=r24 // s2
st4 [in0]=r28 // s3
br.ret.sptk.many b0 };;
#endif
.align 32
.Ld_i_unaligned:
{ .mmi; add out0=1,in0
add out2=2,in0
add out4=3,in0 };;
{ .mmi; ld1 r16=[in0],4
ld1 r17=[out0],4 }//;;
{ .mmi; ld1 r18=[out2],4
ld1 out1=[out4],4 };; // s0
{ .mmi; ld1 r20=[in0],4
ld1 r21=[out0],4 }//;;
{ .mmi; ld1 r22=[out2],4
ld1 out3=[out4],4 };; // s1
{ .mmi; ld1 r24=[in0],4
ld1 r25=[out0],4 }//;;
{ .mmi; ld1 r26=[out2],4
ld1 out5=[out4],4 };; // s2
{ .mmi; ld1 r28=[in0]
ld1 r29=[out0] }//;;
{ .mmi; ld1 r30=[out2]
ld1 out7=[out4] };; // s3
{ .mii;
dep out1=r16,out1,24,8 //;;
dep out3=r20,out3,24,8 }//;;
{ .mii; ADDP rk0=0,in2
dep out5=r24,out5,24,8 //;;
dep out7=r28,out7,24,8 };;
{ .mii; ADDP rk1=KSZ,in2
dep out1=r17,out1,16,8 //;;
dep out3=r21,out3,16,8 }//;;
{ .mii; mov twenty4=24
dep out5=r25,out5,16,8 //;;
dep out7=r29,out7,16,8 };;
{ .mii; mov sixteen=16
dep out1=r18,out1,8,8 //;;
dep out3=r22,out3,8,8 }//;;
{ .mii; mov maskff=0xff
dep out5=r26,out5,8,8 //;;
dep out7=r30,out7,8,8 };;
{ .mib; br.call.sptk.many b6=_ia64_AES_decrypt };;
.Ld_o_unaligned:
{ .mii; ADDP out0=0,in1
extr.u r17=r16,8,8 // s0
shr.u r19=r16,twenty4 }//;;
{ .mii; ADDP out1=1,in1
extr.u r18=r16,16,8
shr.u r23=r20,twenty4 }//;; // s1
{ .mii; ADDP out2=2,in1
extr.u r21=r20,8,8
shr.u r22=r20,sixteen }//;;
{ .mii; ADDP out3=3,in1
extr.u r25=r24,8,8 // s2
shr.u r27=r24,twenty4 };;
{ .mii; st1 [out3]=r16,4
extr.u r26=r24,16,8
shr.u r31=r28,twenty4 }//;; // s3
{ .mii; st1 [out2]=r17,4
extr.u r29=r28,8,8
shr.u r30=r28,sixteen }//;;
{ .mmi; st1 [out1]=r18,4
st1 [out0]=r19,4 };;
{ .mmi; st1 [out3]=r20,4
st1 [out2]=r21,4 }//;;
{ .mmi; st1 [out1]=r22,4
st1 [out0]=r23,4 };;
{ .mmi; st1 [out3]=r24,4
st1 [out2]=r25,4
mov pr=prsave,0x1ffff }//;;
{ .mmi; st1 [out1]=r26,4
st1 [out0]=r27,4
mov ar.pfs=pfssave };;
{ .mmi; st1 [out3]=r28
st1 [out2]=r29
mov ar.lc=lcsave }//;;
{ .mmi; st1 [out1]=r30
st1 [out0]=r31 }
{ .mfb; mov psr.um=loc0 // restore user mask
br.ret.sptk.many b0 };;
.endp AES_decrypt#
// leave it in .text segment...
.align 64
.global AES_Te#
.type AES_Te#,@object
AES_Te: data4 0xc66363a5,0xc66363a5, 0xf87c7c84,0xf87c7c84
data4 0xee777799,0xee777799, 0xf67b7b8d,0xf67b7b8d
data4 0xfff2f20d,0xfff2f20d, 0xd66b6bbd,0xd66b6bbd
data4 0xde6f6fb1,0xde6f6fb1, 0x91c5c554,0x91c5c554
data4 0x60303050,0x60303050, 0x02010103,0x02010103
data4 0xce6767a9,0xce6767a9, 0x562b2b7d,0x562b2b7d
data4 0xe7fefe19,0xe7fefe19, 0xb5d7d762,0xb5d7d762
data4 0x4dababe6,0x4dababe6, 0xec76769a,0xec76769a
data4 0x8fcaca45,0x8fcaca45, 0x1f82829d,0x1f82829d
data4 0x89c9c940,0x89c9c940, 0xfa7d7d87,0xfa7d7d87
data4 0xeffafa15,0xeffafa15, 0xb25959eb,0xb25959eb
data4 0x8e4747c9,0x8e4747c9, 0xfbf0f00b,0xfbf0f00b
data4 0x41adadec,0x41adadec, 0xb3d4d467,0xb3d4d467
data4 0x5fa2a2fd,0x5fa2a2fd, 0x45afafea,0x45afafea
data4 0x239c9cbf,0x239c9cbf, 0x53a4a4f7,0x53a4a4f7
data4 0xe4727296,0xe4727296, 0x9bc0c05b,0x9bc0c05b
data4 0x75b7b7c2,0x75b7b7c2, 0xe1fdfd1c,0xe1fdfd1c
data4 0x3d9393ae,0x3d9393ae, 0x4c26266a,0x4c26266a
data4 0x6c36365a,0x6c36365a, 0x7e3f3f41,0x7e3f3f41
data4 0xf5f7f702,0xf5f7f702, 0x83cccc4f,0x83cccc4f
data4 0x6834345c,0x6834345c, 0x51a5a5f4,0x51a5a5f4
data4 0xd1e5e534,0xd1e5e534, 0xf9f1f108,0xf9f1f108
data4 0xe2717193,0xe2717193, 0xabd8d873,0xabd8d873
data4 0x62313153,0x62313153, 0x2a15153f,0x2a15153f
data4 0x0804040c,0x0804040c, 0x95c7c752,0x95c7c752
data4 0x46232365,0x46232365, 0x9dc3c35e,0x9dc3c35e
data4 0x30181828,0x30181828, 0x379696a1,0x379696a1
data4 0x0a05050f,0x0a05050f, 0x2f9a9ab5,0x2f9a9ab5
data4 0x0e070709,0x0e070709, 0x24121236,0x24121236
data4 0x1b80809b,0x1b80809b, 0xdfe2e23d,0xdfe2e23d
data4 0xcdebeb26,0xcdebeb26, 0x4e272769,0x4e272769
data4 0x7fb2b2cd,0x7fb2b2cd, 0xea75759f,0xea75759f
data4 0x1209091b,0x1209091b, 0x1d83839e,0x1d83839e
data4 0x582c2c74,0x582c2c74, 0x341a1a2e,0x341a1a2e
data4 0x361b1b2d,0x361b1b2d, 0xdc6e6eb2,0xdc6e6eb2
data4 0xb45a5aee,0xb45a5aee, 0x5ba0a0fb,0x5ba0a0fb
data4 0xa45252f6,0xa45252f6, 0x763b3b4d,0x763b3b4d
data4 0xb7d6d661,0xb7d6d661, 0x7db3b3ce,0x7db3b3ce
data4 0x5229297b,0x5229297b, 0xdde3e33e,0xdde3e33e
data4 0x5e2f2f71,0x5e2f2f71, 0x13848497,0x13848497
data4 0xa65353f5,0xa65353f5, 0xb9d1d168,0xb9d1d168
data4 0x00000000,0x00000000, 0xc1eded2c,0xc1eded2c
data4 0x40202060,0x40202060, 0xe3fcfc1f,0xe3fcfc1f
data4 0x79b1b1c8,0x79b1b1c8, 0xb65b5bed,0xb65b5bed
data4 0xd46a6abe,0xd46a6abe, 0x8dcbcb46,0x8dcbcb46
data4 0x67bebed9,0x67bebed9, 0x7239394b,0x7239394b
data4 0x944a4ade,0x944a4ade, 0x984c4cd4,0x984c4cd4
data4 0xb05858e8,0xb05858e8, 0x85cfcf4a,0x85cfcf4a
data4 0xbbd0d06b,0xbbd0d06b, 0xc5efef2a,0xc5efef2a
data4 0x4faaaae5,0x4faaaae5, 0xedfbfb16,0xedfbfb16
data4 0x864343c5,0x864343c5, 0x9a4d4dd7,0x9a4d4dd7
data4 0x66333355,0x66333355, 0x11858594,0x11858594
data4 0x8a4545cf,0x8a4545cf, 0xe9f9f910,0xe9f9f910
data4 0x04020206,0x04020206, 0xfe7f7f81,0xfe7f7f81
data4 0xa05050f0,0xa05050f0, 0x783c3c44,0x783c3c44
data4 0x259f9fba,0x259f9fba, 0x4ba8a8e3,0x4ba8a8e3
data4 0xa25151f3,0xa25151f3, 0x5da3a3fe,0x5da3a3fe
data4 0x804040c0,0x804040c0, 0x058f8f8a,0x058f8f8a
data4 0x3f9292ad,0x3f9292ad, 0x219d9dbc,0x219d9dbc
data4 0x70383848,0x70383848, 0xf1f5f504,0xf1f5f504
data4 0x63bcbcdf,0x63bcbcdf, 0x77b6b6c1,0x77b6b6c1
data4 0xafdada75,0xafdada75, 0x42212163,0x42212163
data4 0x20101030,0x20101030, 0xe5ffff1a,0xe5ffff1a
data4 0xfdf3f30e,0xfdf3f30e, 0xbfd2d26d,0xbfd2d26d
data4 0x81cdcd4c,0x81cdcd4c, 0x180c0c14,0x180c0c14
data4 0x26131335,0x26131335, 0xc3ecec2f,0xc3ecec2f
data4 0xbe5f5fe1,0xbe5f5fe1, 0x359797a2,0x359797a2
data4 0x884444cc,0x884444cc, 0x2e171739,0x2e171739
data4 0x93c4c457,0x93c4c457, 0x55a7a7f2,0x55a7a7f2
data4 0xfc7e7e82,0xfc7e7e82, 0x7a3d3d47,0x7a3d3d47
data4 0xc86464ac,0xc86464ac, 0xba5d5de7,0xba5d5de7
data4 0x3219192b,0x3219192b, 0xe6737395,0xe6737395
data4 0xc06060a0,0xc06060a0, 0x19818198,0x19818198
data4 0x9e4f4fd1,0x9e4f4fd1, 0xa3dcdc7f,0xa3dcdc7f
data4 0x44222266,0x44222266, 0x542a2a7e,0x542a2a7e
data4 0x3b9090ab,0x3b9090ab, 0x0b888883,0x0b888883
data4 0x8c4646ca,0x8c4646ca, 0xc7eeee29,0xc7eeee29
data4 0x6bb8b8d3,0x6bb8b8d3, 0x2814143c,0x2814143c
data4 0xa7dede79,0xa7dede79, 0xbc5e5ee2,0xbc5e5ee2
data4 0x160b0b1d,0x160b0b1d, 0xaddbdb76,0xaddbdb76
data4 0xdbe0e03b,0xdbe0e03b, 0x64323256,0x64323256
data4 0x743a3a4e,0x743a3a4e, 0x140a0a1e,0x140a0a1e
data4 0x924949db,0x924949db, 0x0c06060a,0x0c06060a
data4 0x4824246c,0x4824246c, 0xb85c5ce4,0xb85c5ce4
data4 0x9fc2c25d,0x9fc2c25d, 0xbdd3d36e,0xbdd3d36e
data4 0x43acacef,0x43acacef, 0xc46262a6,0xc46262a6
data4 0x399191a8,0x399191a8, 0x319595a4,0x319595a4
data4 0xd3e4e437,0xd3e4e437, 0xf279798b,0xf279798b
data4 0xd5e7e732,0xd5e7e732, 0x8bc8c843,0x8bc8c843
data4 0x6e373759,0x6e373759, 0xda6d6db7,0xda6d6db7
data4 0x018d8d8c,0x018d8d8c, 0xb1d5d564,0xb1d5d564
data4 0x9c4e4ed2,0x9c4e4ed2, 0x49a9a9e0,0x49a9a9e0
data4 0xd86c6cb4,0xd86c6cb4, 0xac5656fa,0xac5656fa
data4 0xf3f4f407,0xf3f4f407, 0xcfeaea25,0xcfeaea25
data4 0xca6565af,0xca6565af, 0xf47a7a8e,0xf47a7a8e
data4 0x47aeaee9,0x47aeaee9, 0x10080818,0x10080818
data4 0x6fbabad5,0x6fbabad5, 0xf0787888,0xf0787888
data4 0x4a25256f,0x4a25256f, 0x5c2e2e72,0x5c2e2e72
data4 0x381c1c24,0x381c1c24, 0x57a6a6f1,0x57a6a6f1
data4 0x73b4b4c7,0x73b4b4c7, 0x97c6c651,0x97c6c651
data4 0xcbe8e823,0xcbe8e823, 0xa1dddd7c,0xa1dddd7c
data4 0xe874749c,0xe874749c, 0x3e1f1f21,0x3e1f1f21
data4 0x964b4bdd,0x964b4bdd, 0x61bdbddc,0x61bdbddc
data4 0x0d8b8b86,0x0d8b8b86, 0x0f8a8a85,0x0f8a8a85
data4 0xe0707090,0xe0707090, 0x7c3e3e42,0x7c3e3e42
data4 0x71b5b5c4,0x71b5b5c4, 0xcc6666aa,0xcc6666aa
data4 0x904848d8,0x904848d8, 0x06030305,0x06030305
data4 0xf7f6f601,0xf7f6f601, 0x1c0e0e12,0x1c0e0e12
data4 0xc26161a3,0xc26161a3, 0x6a35355f,0x6a35355f
data4 0xae5757f9,0xae5757f9, 0x69b9b9d0,0x69b9b9d0
data4 0x17868691,0x17868691, 0x99c1c158,0x99c1c158
data4 0x3a1d1d27,0x3a1d1d27, 0x279e9eb9,0x279e9eb9
data4 0xd9e1e138,0xd9e1e138, 0xebf8f813,0xebf8f813
data4 0x2b9898b3,0x2b9898b3, 0x22111133,0x22111133
data4 0xd26969bb,0xd26969bb, 0xa9d9d970,0xa9d9d970
data4 0x078e8e89,0x078e8e89, 0x339494a7,0x339494a7
data4 0x2d9b9bb6,0x2d9b9bb6, 0x3c1e1e22,0x3c1e1e22
data4 0x15878792,0x15878792, 0xc9e9e920,0xc9e9e920
data4 0x87cece49,0x87cece49, 0xaa5555ff,0xaa5555ff
data4 0x50282878,0x50282878, 0xa5dfdf7a,0xa5dfdf7a
data4 0x038c8c8f,0x038c8c8f, 0x59a1a1f8,0x59a1a1f8
data4 0x09898980,0x09898980, 0x1a0d0d17,0x1a0d0d17
data4 0x65bfbfda,0x65bfbfda, 0xd7e6e631,0xd7e6e631
data4 0x844242c6,0x844242c6, 0xd06868b8,0xd06868b8
data4 0x824141c3,0x824141c3, 0x299999b0,0x299999b0
data4 0x5a2d2d77,0x5a2d2d77, 0x1e0f0f11,0x1e0f0f11
data4 0x7bb0b0cb,0x7bb0b0cb, 0xa85454fc,0xa85454fc
data4 0x6dbbbbd6,0x6dbbbbd6, 0x2c16163a,0x2c16163a
// Te4:
data1 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
data1 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
data1 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
data1 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
data1 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
data1 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
data1 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
data1 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
data1 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
data1 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
data1 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
data1 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
data1 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
data1 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
data1 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
data1 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
data1 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
data1 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
data1 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
data1 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
data1 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
data1 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
data1 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
data1 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
data1 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
data1 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
data1 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
data1 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
data1 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
data1 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
data1 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
data1 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
.size AES_Te#,2048+256 // HP-UX assembler fails to ".-AES_Te#"
.align 64
.global AES_Td#
.type AES_Td#,@object
AES_Td: data4 0x51f4a750,0x51f4a750, 0x7e416553,0x7e416553
data4 0x1a17a4c3,0x1a17a4c3, 0x3a275e96,0x3a275e96
data4 0x3bab6bcb,0x3bab6bcb, 0x1f9d45f1,0x1f9d45f1
data4 0xacfa58ab,0xacfa58ab, 0x4be30393,0x4be30393
data4 0x2030fa55,0x2030fa55, 0xad766df6,0xad766df6
data4 0x88cc7691,0x88cc7691, 0xf5024c25,0xf5024c25
data4 0x4fe5d7fc,0x4fe5d7fc, 0xc52acbd7,0xc52acbd7
data4 0x26354480,0x26354480, 0xb562a38f,0xb562a38f
data4 0xdeb15a49,0xdeb15a49, 0x25ba1b67,0x25ba1b67
data4 0x45ea0e98,0x45ea0e98, 0x5dfec0e1,0x5dfec0e1
data4 0xc32f7502,0xc32f7502, 0x814cf012,0x814cf012
data4 0x8d4697a3,0x8d4697a3, 0x6bd3f9c6,0x6bd3f9c6
data4 0x038f5fe7,0x038f5fe7, 0x15929c95,0x15929c95
data4 0xbf6d7aeb,0xbf6d7aeb, 0x955259da,0x955259da
data4 0xd4be832d,0xd4be832d, 0x587421d3,0x587421d3
data4 0x49e06929,0x49e06929, 0x8ec9c844,0x8ec9c844
data4 0x75c2896a,0x75c2896a, 0xf48e7978,0xf48e7978
data4 0x99583e6b,0x99583e6b, 0x27b971dd,0x27b971dd
data4 0xbee14fb6,0xbee14fb6, 0xf088ad17,0xf088ad17
data4 0xc920ac66,0xc920ac66, 0x7dce3ab4,0x7dce3ab4
data4 0x63df4a18,0x63df4a18, 0xe51a3182,0xe51a3182
data4 0x97513360,0x97513360, 0x62537f45,0x62537f45
data4 0xb16477e0,0xb16477e0, 0xbb6bae84,0xbb6bae84
data4 0xfe81a01c,0xfe81a01c, 0xf9082b94,0xf9082b94
data4 0x70486858,0x70486858, 0x8f45fd19,0x8f45fd19
data4 0x94de6c87,0x94de6c87, 0x527bf8b7,0x527bf8b7
data4 0xab73d323,0xab73d323, 0x724b02e2,0x724b02e2
data4 0xe31f8f57,0xe31f8f57, 0x6655ab2a,0x6655ab2a
data4 0xb2eb2807,0xb2eb2807, 0x2fb5c203,0x2fb5c203
data4 0x86c57b9a,0x86c57b9a, 0xd33708a5,0xd33708a5
data4 0x302887f2,0x302887f2, 0x23bfa5b2,0x23bfa5b2
data4 0x02036aba,0x02036aba, 0xed16825c,0xed16825c
data4 0x8acf1c2b,0x8acf1c2b, 0xa779b492,0xa779b492
data4 0xf307f2f0,0xf307f2f0, 0x4e69e2a1,0x4e69e2a1
data4 0x65daf4cd,0x65daf4cd, 0x0605bed5,0x0605bed5
data4 0xd134621f,0xd134621f, 0xc4a6fe8a,0xc4a6fe8a
data4 0x342e539d,0x342e539d, 0xa2f355a0,0xa2f355a0
data4 0x058ae132,0x058ae132, 0xa4f6eb75,0xa4f6eb75
data4 0x0b83ec39,0x0b83ec39, 0x4060efaa,0x4060efaa
data4 0x5e719f06,0x5e719f06, 0xbd6e1051,0xbd6e1051
data4 0x3e218af9,0x3e218af9, 0x96dd063d,0x96dd063d
data4 0xdd3e05ae,0xdd3e05ae, 0x4de6bd46,0x4de6bd46
data4 0x91548db5,0x91548db5, 0x71c45d05,0x71c45d05
data4 0x0406d46f,0x0406d46f, 0x605015ff,0x605015ff
data4 0x1998fb24,0x1998fb24, 0xd6bde997,0xd6bde997
data4 0x894043cc,0x894043cc, 0x67d99e77,0x67d99e77
data4 0xb0e842bd,0xb0e842bd, 0x07898b88,0x07898b88
data4 0xe7195b38,0xe7195b38, 0x79c8eedb,0x79c8eedb
data4 0xa17c0a47,0xa17c0a47, 0x7c420fe9,0x7c420fe9
data4 0xf8841ec9,0xf8841ec9, 0x00000000,0x00000000
data4 0x09808683,0x09808683, 0x322bed48,0x322bed48
data4 0x1e1170ac,0x1e1170ac, 0x6c5a724e,0x6c5a724e
data4 0xfd0efffb,0xfd0efffb, 0x0f853856,0x0f853856
data4 0x3daed51e,0x3daed51e, 0x362d3927,0x362d3927
data4 0x0a0fd964,0x0a0fd964, 0x685ca621,0x685ca621
data4 0x9b5b54d1,0x9b5b54d1, 0x24362e3a,0x24362e3a
data4 0x0c0a67b1,0x0c0a67b1, 0x9357e70f,0x9357e70f
data4 0xb4ee96d2,0xb4ee96d2, 0x1b9b919e,0x1b9b919e
data4 0x80c0c54f,0x80c0c54f, 0x61dc20a2,0x61dc20a2
data4 0x5a774b69,0x5a774b69, 0x1c121a16,0x1c121a16
data4 0xe293ba0a,0xe293ba0a, 0xc0a02ae5,0xc0a02ae5
data4 0x3c22e043,0x3c22e043, 0x121b171d,0x121b171d
data4 0x0e090d0b,0x0e090d0b, 0xf28bc7ad,0xf28bc7ad
data4 0x2db6a8b9,0x2db6a8b9, 0x141ea9c8,0x141ea9c8
data4 0x57f11985,0x57f11985, 0xaf75074c,0xaf75074c
data4 0xee99ddbb,0xee99ddbb, 0xa37f60fd,0xa37f60fd
data4 0xf701269f,0xf701269f, 0x5c72f5bc,0x5c72f5bc
data4 0x44663bc5,0x44663bc5, 0x5bfb7e34,0x5bfb7e34
data4 0x8b432976,0x8b432976, 0xcb23c6dc,0xcb23c6dc
data4 0xb6edfc68,0xb6edfc68, 0xb8e4f163,0xb8e4f163
data4 0xd731dcca,0xd731dcca, 0x42638510,0x42638510
data4 0x13972240,0x13972240, 0x84c61120,0x84c61120
data4 0x854a247d,0x854a247d, 0xd2bb3df8,0xd2bb3df8
data4 0xaef93211,0xaef93211, 0xc729a16d,0xc729a16d
data4 0x1d9e2f4b,0x1d9e2f4b, 0xdcb230f3,0xdcb230f3
data4 0x0d8652ec,0x0d8652ec, 0x77c1e3d0,0x77c1e3d0
data4 0x2bb3166c,0x2bb3166c, 0xa970b999,0xa970b999
data4 0x119448fa,0x119448fa, 0x47e96422,0x47e96422
data4 0xa8fc8cc4,0xa8fc8cc4, 0xa0f03f1a,0xa0f03f1a
data4 0x567d2cd8,0x567d2cd8, 0x223390ef,0x223390ef
data4 0x87494ec7,0x87494ec7, 0xd938d1c1,0xd938d1c1
data4 0x8ccaa2fe,0x8ccaa2fe, 0x98d40b36,0x98d40b36
data4 0xa6f581cf,0xa6f581cf, 0xa57ade28,0xa57ade28
data4 0xdab78e26,0xdab78e26, 0x3fadbfa4,0x3fadbfa4
data4 0x2c3a9de4,0x2c3a9de4, 0x5078920d,0x5078920d
data4 0x6a5fcc9b,0x6a5fcc9b, 0x547e4662,0x547e4662
data4 0xf68d13c2,0xf68d13c2, 0x90d8b8e8,0x90d8b8e8
data4 0x2e39f75e,0x2e39f75e, 0x82c3aff5,0x82c3aff5
data4 0x9f5d80be,0x9f5d80be, 0x69d0937c,0x69d0937c
data4 0x6fd52da9,0x6fd52da9, 0xcf2512b3,0xcf2512b3
data4 0xc8ac993b,0xc8ac993b, 0x10187da7,0x10187da7
data4 0xe89c636e,0xe89c636e, 0xdb3bbb7b,0xdb3bbb7b
data4 0xcd267809,0xcd267809, 0x6e5918f4,0x6e5918f4
data4 0xec9ab701,0xec9ab701, 0x834f9aa8,0x834f9aa8
data4 0xe6956e65,0xe6956e65, 0xaaffe67e,0xaaffe67e
data4 0x21bccf08,0x21bccf08, 0xef15e8e6,0xef15e8e6
data4 0xbae79bd9,0xbae79bd9, 0x4a6f36ce,0x4a6f36ce
data4 0xea9f09d4,0xea9f09d4, 0x29b07cd6,0x29b07cd6
data4 0x31a4b2af,0x31a4b2af, 0x2a3f2331,0x2a3f2331
data4 0xc6a59430,0xc6a59430, 0x35a266c0,0x35a266c0
data4 0x744ebc37,0x744ebc37, 0xfc82caa6,0xfc82caa6
data4 0xe090d0b0,0xe090d0b0, 0x33a7d815,0x33a7d815
data4 0xf104984a,0xf104984a, 0x41ecdaf7,0x41ecdaf7
data4 0x7fcd500e,0x7fcd500e, 0x1791f62f,0x1791f62f
data4 0x764dd68d,0x764dd68d, 0x43efb04d,0x43efb04d
data4 0xccaa4d54,0xccaa4d54, 0xe49604df,0xe49604df
data4 0x9ed1b5e3,0x9ed1b5e3, 0x4c6a881b,0x4c6a881b
data4 0xc12c1fb8,0xc12c1fb8, 0x4665517f,0x4665517f
data4 0x9d5eea04,0x9d5eea04, 0x018c355d,0x018c355d
data4 0xfa877473,0xfa877473, 0xfb0b412e,0xfb0b412e
data4 0xb3671d5a,0xb3671d5a, 0x92dbd252,0x92dbd252
data4 0xe9105633,0xe9105633, 0x6dd64713,0x6dd64713
data4 0x9ad7618c,0x9ad7618c, 0x37a10c7a,0x37a10c7a
data4 0x59f8148e,0x59f8148e, 0xeb133c89,0xeb133c89
data4 0xcea927ee,0xcea927ee, 0xb761c935,0xb761c935
data4 0xe11ce5ed,0xe11ce5ed, 0x7a47b13c,0x7a47b13c
data4 0x9cd2df59,0x9cd2df59, 0x55f2733f,0x55f2733f
data4 0x1814ce79,0x1814ce79, 0x73c737bf,0x73c737bf
data4 0x53f7cdea,0x53f7cdea, 0x5ffdaa5b,0x5ffdaa5b
data4 0xdf3d6f14,0xdf3d6f14, 0x7844db86,0x7844db86
data4 0xcaaff381,0xcaaff381, 0xb968c43e,0xb968c43e
data4 0x3824342c,0x3824342c, 0xc2a3405f,0xc2a3405f
data4 0x161dc372,0x161dc372, 0xbce2250c,0xbce2250c
data4 0x283c498b,0x283c498b, 0xff0d9541,0xff0d9541
data4 0x39a80171,0x39a80171, 0x080cb3de,0x080cb3de
data4 0xd8b4e49c,0xd8b4e49c, 0x6456c190,0x6456c190
data4 0x7bcb8461,0x7bcb8461, 0xd532b670,0xd532b670
data4 0x486c5c74,0x486c5c74, 0xd0b85742,0xd0b85742
// Td4:
data1 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
data1 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
data1 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
data1 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
data1 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
data1 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
data1 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
data1 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
data1 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
data1 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
data1 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
data1 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
data1 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
data1 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
data1 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
data1 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
data1 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
data1 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
data1 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
data1 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
data1 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
data1 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
data1 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
data1 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
data1 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
data1 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
data1 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
data1 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
data1 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
data1 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
data1 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
data1 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
.size AES_Td#,2048+256 // HP-UX assembler fails to ".-AES_Td#"
|
NUS-CG3207/labs | 6,849 | docs/code_templates/Asst_01/arm_assembly_sample.s | ;----------------------------------------------------------------------------------
;-- License terms :
;-- You are free to use this code as long as you
;-- (i) DO NOT post it on any public repository;
;-- (ii) use it only for educational purposes;
;-- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of ARM Holdings or other entities.
;-- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose;
;-- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course CG3207 at the National University of Singapore);
;-- (vi) retain this notice in this file or any files derived from this.
;----------------------------------------------------------------------------------
AREA MYCODE, CODE, READONLY, ALIGN=9 ; 2^9 = 512 bytes (enough space for 128 words). Each section is aligned to an address divisible by 512.
ENTRY
; ------- <code memory (ROM mapped to Instruction Memory) begins>
; Total number of instructions should not exceed 127 (126 excluding the last line 'halt B halt').
LDR R1, LEDS ; Read the location LEDs to get a pointer to (address of) the LEDs into R1. R1 content will be 0x00000C00 after this step is executed.
LDR R2, DIPS ; Read the location DIPs to get a pointer to (address of) the DIPs into R2. R2 content will be 0x00000C04 after this step is executed.
main_loop
LDR R3, DELAY_VAL ; Read the location DELAY_VAL (tentatively, 4) to get the number of iterations in the delay loop into R3.
LDR R4, [R2] ; Read the location pointed to by R2 (i.e., DIPs) and get the value into R4.
STR R4, [R1] ; Write R4 content into the location pointed by R1 (i.e., LEDs). If you get an access violation notification, you haven't applied the MMIO.ini file.
delay_loop
SUBS R3, R3, #1 ; Implement a delay loop. Run the loop by the number of iterations specified in R3.
BNE delay_loop ; A delay loop is the equivalent of for(i=0; i<R3; i++){}; - a loop which runs R3 times without doing anything.
;B main_loop ; Go back to line 18. Uncomment this line if you wish to go back and loop
; which you might want to do when simulating reading DIPs and writing the value to LEDs continously
; some random instructions below to illustrate the use of PC as an operand, loads, stores etc - doesn't do anything meaningful. Try them out nevertheless.
MOV R1, R15 ; It is interesting to note that R15 is read as PC+8 in ARM7. Here, R1 = PC+8 = 0x1C + 8 = 0x24. Does it make sense to have PC=0x1C? - yes, as this is the 7th instruction.
LDR R0, constant1 ;
STR R5, variable1 ; PC relative STRs are supported in ARM7 (ARMv3 ISA), unlike LPC1769/ARM Cortex M3 or STM32L4/ARM Cortex M4 (ARMv7M ISA)
LDR R5, variable1 ; load from a variable only after storing something to it (variables are in RAM - a volatile memory)
LDR R2, variable1_addr ; to get the address of variable1 in R2.
; instead of the pseudo-instruction LDR R2, =variable1, use LDR R2, variable1_addr and variable1_addr DCD variable1
STR R0, [R2] ; store using address of variable 1 as a pointer. *R2 = R0;
STR R0, [R2,#4] ; *(R2+4) = R0; this will cause an access violation as the simulator will see that there is no memory/variable allocated at 0x00000804.
; It will work fine on hardware (i.e., in a real system) though, just that you should be sure that the location that you are writing to is something that is ok to
; write to (i.e., there is a real writeable hardware/memory mapped to that location, and you are not accidentally overwriting something else,
; and some other part of the code wont accidentally overwrite this (the simulator checks this, real hardware will happily allow you to shoot yourself in the foot).
halt
B halt ; infinite loop to halt computation. // A program should not "terminate" without an operating system to return control to
; good idea to keep halt B halt as the last line of your code. Not really necessary if your program loops infinitely though
; ------- <\code memory (ROM mapped to Instruction Memory) ends>
AREA CONSTANTS, DATA, READONLY, ALIGN=9
; ------- <constant memory (ROM mapped to Data Memory) begins>
; All constants should be declared in this section. This section is read only (Only LDR, no STR).
; Total number of constants should not exceed 128 (124 excluding the 4 used for peripheral pointers).
; If a variable is accessed multiple times, it is better to store the address in a register and use it rather than load it repeatedly.
;Peripheral pointers
LEDS
DCD 0x00000C00 ; Address of LEDs. //volatile unsigned int * const LEDS = (unsigned int*)0x00000C00;
DIPS
DCD 0x00000C04 ; Address of DIP switches. //volatile unsigned int * const DIPS = (unsigned int*)0x00000C04;
PBS
DCD 0x00000C08 ; Address of Push Buttons. Optionally used in Lab 2 and later
CONSOLE
DCD 0x00000C0C ; Address of UART. Optionally used in Lab 2 and later
CONSOLE_IN_valid
DCD 0x00000C10 ; Address of UART. Optionally used in Lab 2 and later
CONSOLE_OUT_ready
DCD 0x00000C14 ; Address of UART. Optionally used in Lab 2 and later
SEVENSEG
DCD 0x00000C18 ; Address of 7-Segment LEDs. Optionally used in Lab 2 and later
; Rest of the constants should be declared below.
ZERO
DCD 0x00000000 ; constant 0
LSB_MASK
DCD 0x000000FF ; constant 0xFF
DELAY_VAL
DCD 0x00000002 ; delay time.
variable1_addr
DCD variable1 ; address of variable1. Required since we are avoiding pseudo-instructions // unsigned int * const variable1_addr = &variable1;
constant1
DCD 0xABCD1234 ; // const unsigned int constant1 = 0xABCD1234;
string1
DCB "\r\nWelcome to CG3207..\r\n",0 ; // unsigned char string1[] = "Hello World!"; // assembler will issue a warning if the string size is not a multiple of 4, but the warning is safe to ignore
stringptr
DCD string1 ;
; ------- <constant memory (ROM mapped to Data Memory) ends>
AREA VARIABLES, DATA, READWRITE, ALIGN=9
; ------- <variable memory (RAM mapped to Data Memory) begins>
; All variables should be declared in this section. This section is read-write.
; Total number of variables should not exceed 128.
; No initialization possible in this region. In other words, you should write to a location before you can read from it (i.e., write to a location using STR before reading using LDR).
variable1
DCD 0x00000000 ; // unsigned int variable1;
; ------- <variable memory (RAM mapped to Data Memory) ends>
END
;const int* x; // x is a non-constant pointer to constant data
;int const* x; // x is a non-constant pointer to constant data
;int*const x; // x is a constant pointer to non-constant data
|
nxp-mcuxpresso/OpenART | 47,998 | bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/arm/startup_MIMXRT1064.s | ; * -------------------------------------------------------------------------
; * @file: startup_MIMXRT1064.s
; * @purpose: CMSIS Cortex-M7 Core Device Startup File
; * MIMXRT1064
; * @version: 0.1
; * @date: 2018-6-22
; * @build: b180820
; * -------------------------------------------------------------------------
; *
; * Copyright 1997-2016 Freescale Semiconductor, Inc.
; * Copyright 2016-2018 NXP
; *
; * SPDX-License-Identifier: BSD-3-Clause
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete
DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete
DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete
DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete
DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete
DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete
DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete
DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete
DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete
DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete
DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete
DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete
DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete
DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete
DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete
DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete
DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31
DCD CTI0_ERROR_IRQHandler ;CTI0_Error
DCD CTI1_ERROR_IRQHandler ;CTI1_Error
DCD CORE_IRQHandler ;CorePlatform exception IRQ
DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt
DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt
DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt
DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt
DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt
DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt
DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt
DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt
DCD LPI2C1_IRQHandler ;LPI2C1 interrupt
DCD LPI2C2_IRQHandler ;LPI2C2 interrupt
DCD LPI2C3_IRQHandler ;LPI2C3 interrupt
DCD LPI2C4_IRQHandler ;LPI2C4 interrupt
DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources
DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources
DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources
DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources
DCD CAN1_IRQHandler ;CAN1 interrupt
DCD CAN2_IRQHandler ;CAN2 interrupt
DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ
DCD KPP_IRQHandler ;Keypad nterrupt
DCD TSC_DIG_IRQHandler ;TSC interrupt
DCD GPR_IRQ_IRQHandler ;GPR interrupt
DCD LCDIF_IRQHandler ;LCDIF interrupt
DCD CSI_IRQHandler ;CSI interrupt
DCD PXP_IRQHandler ;PXP interrupt
DCD WDOG2_IRQHandler ;WDOG2 interrupt
DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ
DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ
DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event)
DCD CSU_IRQHandler ;CSU interrupt
DCD DCP_IRQHandler ;DCP_IRQ interrupt
DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt
DCD Reserved68_IRQHandler ;Reserved interrupt
DCD TRNG_IRQHandler ;TRNG interrupt
DCD SJC_IRQHandler ;SJC interrupt
DCD BEE_IRQHandler ;BEE interrupt
DCD SAI1_IRQHandler ;SAI1 interrupt
DCD SAI2_IRQHandler ;SAI1 interrupt
DCD SAI3_RX_IRQHandler ;SAI3 interrupt
DCD SAI3_TX_IRQHandler ;SAI3 interrupt
DCD SPDIF_IRQHandler ;SPDIF interrupt
DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt
DCD Reserved78_IRQHandler ;Reserved interrupt
DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt
DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt
DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD USB_PHY2_IRQHandler ;USBPHY (UTMI1), Interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
DCD ADC2_IRQHandler ;ADC2 interrupt
DCD DCDC_IRQHandler ;DCDC interrupt
DCD Reserved86_IRQHandler ;Reserved interrupt
DCD Reserved87_IRQHandler ;Reserved interrupt
DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO
DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO
DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO
DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO
DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO
DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO
DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO
DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO
DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15
DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31
DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15
DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31
DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15
DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31
DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15
DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31
DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15
DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31
DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt
DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt
DCD WDOG1_IRQHandler ;WDOG1 interrupt
DCD RTWDOG_IRQHandler ;RTWDOG interrupt
DCD EWM_IRQHandler ;EWM interrupt
DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt
DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt
DCD GPC_IRQHandler ;GPC interrupt
DCD SRC_IRQHandler ;SRC interrupt
DCD Reserved115_IRQHandler ;Reserved interrupt
DCD GPT1_IRQHandler ;GPT1 interrupt
DCD GPT2_IRQHandler ;GPT2 interrupt
DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt
DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt
DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt
DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt
DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt
DCD FLEXSPI2_IRQHandler ;FlexSPI2 interrupt
DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt
DCD SEMC_IRQHandler ;Reserved interrupt
DCD USDHC1_IRQHandler ;USDHC1 interrupt
DCD USDHC2_IRQHandler ;USDHC2 interrupt
DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2
DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1
DCD ENET_IRQHandler ;ENET interrupt
DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt
DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt
DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt
DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt
DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt
DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt
DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt
DCD PIT_IRQHandler ;PIT interrupt
DCD ACMP1_IRQHandler ;ACMP interrupt
DCD ACMP2_IRQHandler ;ACMP interrupt
DCD ACMP3_IRQHandler ;ACMP interrupt
DCD ACMP4_IRQHandler ;ACMP interrupt
DCD Reserved143_IRQHandler ;Reserved interrupt
DCD Reserved144_IRQHandler ;Reserved interrupt
DCD ENC1_IRQHandler ;ENC1 interrupt
DCD ENC2_IRQHandler ;ENC2 interrupt
DCD ENC3_IRQHandler ;ENC3 interrupt
DCD ENC4_IRQHandler ;ENC4 interrupt
DCD TMR1_IRQHandler ;TMR1 interrupt
DCD TMR2_IRQHandler ;TMR2 interrupt
DCD TMR3_IRQHandler ;TMR3 interrupt
DCD TMR4_IRQHandler ;TMR4 interrupt
DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt
DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt
DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt
DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt
DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt
DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt
DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt
DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt
DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt
DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt
DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt
DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt
DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt
DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt
DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt
DCD ENET2_IRQHandler ;ENET2 interrupt
DCD ENET2_1588_Timer_IRQHandler ;ENET2_1588_Timer interrupt
DCD CAN3_IRQHandler ;CAN3 interrupt
DCD Reserved171_IRQHandler ;Reserved interrupt
DCD FLEXIO3_IRQHandler ;FLEXIO3 interrupt
DCD GPIO6_7_8_9_IRQHandler ;GPIO6, GPIO7, GPIO8, GPIO9 interrupt
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
DCD DefaultISR ;240
DCD DefaultISR ;241
DCD DefaultISR ;242
DCD DefaultISR ;243
DCD DefaultISR ;244
DCD DefaultISR ;245
DCD DefaultISR ;246
DCD DefaultISR ;247
DCD DefaultISR ;248
DCD DefaultISR ;249
DCD DefaultISR ;250
DCD DefaultISR ;251
DCD DefaultISR ;252
DCD DefaultISR ;253
DCD DefaultISR ;254
DCD 0xFFFFFFFF ; Reserved for user TRIM value
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__Vectors
STR R1, [R0]
LDR R2, [R1]
MSR MSP, R2
LDR R0, =SystemInit
BLX R0
CPSIE i ; Unmask interrupts
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
DMA0_DMA16_IRQHandler\
PROC
EXPORT DMA0_DMA16_IRQHandler [WEAK]
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
ENDP
DMA1_DMA17_IRQHandler\
PROC
EXPORT DMA1_DMA17_IRQHandler [WEAK]
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
ENDP
DMA2_DMA18_IRQHandler\
PROC
EXPORT DMA2_DMA18_IRQHandler [WEAK]
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
ENDP
DMA3_DMA19_IRQHandler\
PROC
EXPORT DMA3_DMA19_IRQHandler [WEAK]
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
ENDP
DMA4_DMA20_IRQHandler\
PROC
EXPORT DMA4_DMA20_IRQHandler [WEAK]
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
ENDP
DMA5_DMA21_IRQHandler\
PROC
EXPORT DMA5_DMA21_IRQHandler [WEAK]
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
ENDP
DMA6_DMA22_IRQHandler\
PROC
EXPORT DMA6_DMA22_IRQHandler [WEAK]
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
ENDP
DMA7_DMA23_IRQHandler\
PROC
EXPORT DMA7_DMA23_IRQHandler [WEAK]
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
ENDP
DMA8_DMA24_IRQHandler\
PROC
EXPORT DMA8_DMA24_IRQHandler [WEAK]
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
ENDP
DMA9_DMA25_IRQHandler\
PROC
EXPORT DMA9_DMA25_IRQHandler [WEAK]
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
ENDP
DMA10_DMA26_IRQHandler\
PROC
EXPORT DMA10_DMA26_IRQHandler [WEAK]
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
ENDP
DMA11_DMA27_IRQHandler\
PROC
EXPORT DMA11_DMA27_IRQHandler [WEAK]
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
ENDP
DMA12_DMA28_IRQHandler\
PROC
EXPORT DMA12_DMA28_IRQHandler [WEAK]
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
ENDP
DMA13_DMA29_IRQHandler\
PROC
EXPORT DMA13_DMA29_IRQHandler [WEAK]
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
ENDP
DMA14_DMA30_IRQHandler\
PROC
EXPORT DMA14_DMA30_IRQHandler [WEAK]
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
ENDP
DMA15_DMA31_IRQHandler\
PROC
EXPORT DMA15_DMA31_IRQHandler [WEAK]
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
ENDP
DMA_ERROR_IRQHandler\
PROC
EXPORT DMA_ERROR_IRQHandler [WEAK]
LDR R0, =DMA_ERROR_DriverIRQHandler
BX R0
ENDP
LPUART1_IRQHandler\
PROC
EXPORT LPUART1_IRQHandler [WEAK]
LDR R0, =LPUART1_DriverIRQHandler
BX R0
ENDP
LPUART2_IRQHandler\
PROC
EXPORT LPUART2_IRQHandler [WEAK]
LDR R0, =LPUART2_DriverIRQHandler
BX R0
ENDP
LPUART3_IRQHandler\
PROC
EXPORT LPUART3_IRQHandler [WEAK]
LDR R0, =LPUART3_DriverIRQHandler
BX R0
ENDP
LPUART4_IRQHandler\
PROC
EXPORT LPUART4_IRQHandler [WEAK]
LDR R0, =LPUART4_DriverIRQHandler
BX R0
ENDP
LPUART5_IRQHandler\
PROC
EXPORT LPUART5_IRQHandler [WEAK]
LDR R0, =LPUART5_DriverIRQHandler
BX R0
ENDP
LPUART6_IRQHandler\
PROC
EXPORT LPUART6_IRQHandler [WEAK]
LDR R0, =LPUART6_DriverIRQHandler
BX R0
ENDP
LPUART7_IRQHandler\
PROC
EXPORT LPUART7_IRQHandler [WEAK]
LDR R0, =LPUART7_DriverIRQHandler
BX R0
ENDP
LPUART8_IRQHandler\
PROC
EXPORT LPUART8_IRQHandler [WEAK]
LDR R0, =LPUART8_DriverIRQHandler
BX R0
ENDP
LPI2C1_IRQHandler\
PROC
EXPORT LPI2C1_IRQHandler [WEAK]
LDR R0, =LPI2C1_DriverIRQHandler
BX R0
ENDP
LPI2C2_IRQHandler\
PROC
EXPORT LPI2C2_IRQHandler [WEAK]
LDR R0, =LPI2C2_DriverIRQHandler
BX R0
ENDP
LPI2C3_IRQHandler\
PROC
EXPORT LPI2C3_IRQHandler [WEAK]
LDR R0, =LPI2C3_DriverIRQHandler
BX R0
ENDP
LPI2C4_IRQHandler\
PROC
EXPORT LPI2C4_IRQHandler [WEAK]
LDR R0, =LPI2C4_DriverIRQHandler
BX R0
ENDP
LPSPI1_IRQHandler\
PROC
EXPORT LPSPI1_IRQHandler [WEAK]
LDR R0, =LPSPI1_DriverIRQHandler
BX R0
ENDP
LPSPI2_IRQHandler\
PROC
EXPORT LPSPI2_IRQHandler [WEAK]
LDR R0, =LPSPI2_DriverIRQHandler
BX R0
ENDP
LPSPI3_IRQHandler\
PROC
EXPORT LPSPI3_IRQHandler [WEAK]
LDR R0, =LPSPI3_DriverIRQHandler
BX R0
ENDP
LPSPI4_IRQHandler\
PROC
EXPORT LPSPI4_IRQHandler [WEAK]
LDR R0, =LPSPI4_DriverIRQHandler
BX R0
ENDP
CAN1_IRQHandler\
PROC
EXPORT CAN1_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN2_IRQHandler\
PROC
EXPORT CAN2_IRQHandler [WEAK]
LDR R0, =CAN2_DriverIRQHandler
BX R0
ENDP
SAI1_IRQHandler\
PROC
EXPORT SAI1_IRQHandler [WEAK]
LDR R0, =SAI1_DriverIRQHandler
BX R0
ENDP
SAI2_IRQHandler\
PROC
EXPORT SAI2_IRQHandler [WEAK]
LDR R0, =SAI2_DriverIRQHandler
BX R0
ENDP
SAI3_RX_IRQHandler\
PROC
EXPORT SAI3_RX_IRQHandler [WEAK]
LDR R0, =SAI3_RX_DriverIRQHandler
BX R0
ENDP
SAI3_TX_IRQHandler\
PROC
EXPORT SAI3_TX_IRQHandler [WEAK]
LDR R0, =SAI3_TX_DriverIRQHandler
BX R0
ENDP
SPDIF_IRQHandler\
PROC
EXPORT SPDIF_IRQHandler [WEAK]
LDR R0, =SPDIF_DriverIRQHandler
BX R0
ENDP
FLEXIO1_IRQHandler\
PROC
EXPORT FLEXIO1_IRQHandler [WEAK]
LDR R0, =FLEXIO1_DriverIRQHandler
BX R0
ENDP
FLEXIO2_IRQHandler\
PROC
EXPORT FLEXIO2_IRQHandler [WEAK]
LDR R0, =FLEXIO2_DriverIRQHandler
BX R0
ENDP
FLEXSPI2_IRQHandler\
PROC
EXPORT FLEXSPI2_IRQHandler [WEAK]
LDR R0, =FLEXSPI2_DriverIRQHandler
BX R0
ENDP
FLEXSPI_IRQHandler\
PROC
EXPORT FLEXSPI_IRQHandler [WEAK]
LDR R0, =FLEXSPI_DriverIRQHandler
BX R0
ENDP
USDHC1_IRQHandler\
PROC
EXPORT USDHC1_IRQHandler [WEAK]
LDR R0, =USDHC1_DriverIRQHandler
BX R0
ENDP
USDHC2_IRQHandler\
PROC
EXPORT USDHC2_IRQHandler [WEAK]
LDR R0, =USDHC2_DriverIRQHandler
BX R0
ENDP
ENET_IRQHandler\
PROC
EXPORT ENET_IRQHandler [WEAK]
LDR R0, =ENET_DriverIRQHandler
BX R0
ENDP
ENET_1588_Timer_IRQHandler\
PROC
EXPORT ENET_1588_Timer_IRQHandler [WEAK]
LDR R0, =ENET_1588_Timer_DriverIRQHandler
BX R0
ENDP
ENET2_IRQHandler\
PROC
EXPORT ENET2_IRQHandler [WEAK]
LDR R0, =ENET2_DriverIRQHandler
BX R0
ENDP
ENET2_1588_Timer_IRQHandler\
PROC
EXPORT ENET2_1588_Timer_IRQHandler [WEAK]
LDR R0, =ENET2_1588_Timer_DriverIRQHandler
BX R0
ENDP
CAN3_IRQHandler\
PROC
EXPORT CAN3_IRQHandler [WEAK]
LDR R0, =CAN3_DriverIRQHandler
BX R0
ENDP
FLEXIO3_IRQHandler\
PROC
EXPORT FLEXIO3_IRQHandler [WEAK]
LDR R0, =FLEXIO3_DriverIRQHandler
BX R0
ENDP
Default_Handler\
PROC
EXPORT DMA0_DMA16_DriverIRQHandler [WEAK]
EXPORT DMA1_DMA17_DriverIRQHandler [WEAK]
EXPORT DMA2_DMA18_DriverIRQHandler [WEAK]
EXPORT DMA3_DMA19_DriverIRQHandler [WEAK]
EXPORT DMA4_DMA20_DriverIRQHandler [WEAK]
EXPORT DMA5_DMA21_DriverIRQHandler [WEAK]
EXPORT DMA6_DMA22_DriverIRQHandler [WEAK]
EXPORT DMA7_DMA23_DriverIRQHandler [WEAK]
EXPORT DMA8_DMA24_DriverIRQHandler [WEAK]
EXPORT DMA9_DMA25_DriverIRQHandler [WEAK]
EXPORT DMA10_DMA26_DriverIRQHandler [WEAK]
EXPORT DMA11_DMA27_DriverIRQHandler [WEAK]
EXPORT DMA12_DMA28_DriverIRQHandler [WEAK]
EXPORT DMA13_DMA29_DriverIRQHandler [WEAK]
EXPORT DMA14_DMA30_DriverIRQHandler [WEAK]
EXPORT DMA15_DMA31_DriverIRQHandler [WEAK]
EXPORT DMA_ERROR_DriverIRQHandler [WEAK]
EXPORT CTI0_ERROR_IRQHandler [WEAK]
EXPORT CTI1_ERROR_IRQHandler [WEAK]
EXPORT CORE_IRQHandler [WEAK]
EXPORT LPUART1_DriverIRQHandler [WEAK]
EXPORT LPUART2_DriverIRQHandler [WEAK]
EXPORT LPUART3_DriverIRQHandler [WEAK]
EXPORT LPUART4_DriverIRQHandler [WEAK]
EXPORT LPUART5_DriverIRQHandler [WEAK]
EXPORT LPUART6_DriverIRQHandler [WEAK]
EXPORT LPUART7_DriverIRQHandler [WEAK]
EXPORT LPUART8_DriverIRQHandler [WEAK]
EXPORT LPI2C1_DriverIRQHandler [WEAK]
EXPORT LPI2C2_DriverIRQHandler [WEAK]
EXPORT LPI2C3_DriverIRQHandler [WEAK]
EXPORT LPI2C4_DriverIRQHandler [WEAK]
EXPORT LPSPI1_DriverIRQHandler [WEAK]
EXPORT LPSPI2_DriverIRQHandler [WEAK]
EXPORT LPSPI3_DriverIRQHandler [WEAK]
EXPORT LPSPI4_DriverIRQHandler [WEAK]
EXPORT CAN1_DriverIRQHandler [WEAK]
EXPORT CAN2_DriverIRQHandler [WEAK]
EXPORT FLEXRAM_IRQHandler [WEAK]
EXPORT KPP_IRQHandler [WEAK]
EXPORT TSC_DIG_IRQHandler [WEAK]
EXPORT GPR_IRQ_IRQHandler [WEAK]
EXPORT LCDIF_IRQHandler [WEAK]
EXPORT CSI_IRQHandler [WEAK]
EXPORT PXP_IRQHandler [WEAK]
EXPORT WDOG2_IRQHandler [WEAK]
EXPORT SNVS_HP_WRAPPER_IRQHandler [WEAK]
EXPORT SNVS_HP_WRAPPER_TZ_IRQHandler [WEAK]
EXPORT SNVS_LP_WRAPPER_IRQHandler [WEAK]
EXPORT CSU_IRQHandler [WEAK]
EXPORT DCP_IRQHandler [WEAK]
EXPORT DCP_VMI_IRQHandler [WEAK]
EXPORT Reserved68_IRQHandler [WEAK]
EXPORT TRNG_IRQHandler [WEAK]
EXPORT SJC_IRQHandler [WEAK]
EXPORT BEE_IRQHandler [WEAK]
EXPORT SAI1_DriverIRQHandler [WEAK]
EXPORT SAI2_DriverIRQHandler [WEAK]
EXPORT SAI3_RX_DriverIRQHandler [WEAK]
EXPORT SAI3_TX_DriverIRQHandler [WEAK]
EXPORT SPDIF_DriverIRQHandler [WEAK]
EXPORT PMU_EVENT_IRQHandler [WEAK]
EXPORT Reserved78_IRQHandler [WEAK]
EXPORT TEMP_LOW_HIGH_IRQHandler [WEAK]
EXPORT TEMP_PANIC_IRQHandler [WEAK]
EXPORT USB_PHY1_IRQHandler [WEAK]
EXPORT USB_PHY2_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT DCDC_IRQHandler [WEAK]
EXPORT Reserved86_IRQHandler [WEAK]
EXPORT Reserved87_IRQHandler [WEAK]
EXPORT GPIO1_INT0_IRQHandler [WEAK]
EXPORT GPIO1_INT1_IRQHandler [WEAK]
EXPORT GPIO1_INT2_IRQHandler [WEAK]
EXPORT GPIO1_INT3_IRQHandler [WEAK]
EXPORT GPIO1_INT4_IRQHandler [WEAK]
EXPORT GPIO1_INT5_IRQHandler [WEAK]
EXPORT GPIO1_INT6_IRQHandler [WEAK]
EXPORT GPIO1_INT7_IRQHandler [WEAK]
EXPORT GPIO1_Combined_0_15_IRQHandler [WEAK]
EXPORT GPIO1_Combined_16_31_IRQHandler [WEAK]
EXPORT GPIO2_Combined_0_15_IRQHandler [WEAK]
EXPORT GPIO2_Combined_16_31_IRQHandler [WEAK]
EXPORT GPIO3_Combined_0_15_IRQHandler [WEAK]
EXPORT GPIO3_Combined_16_31_IRQHandler [WEAK]
EXPORT GPIO4_Combined_0_15_IRQHandler [WEAK]
EXPORT GPIO4_Combined_16_31_IRQHandler [WEAK]
EXPORT GPIO5_Combined_0_15_IRQHandler [WEAK]
EXPORT GPIO5_Combined_16_31_IRQHandler [WEAK]
EXPORT FLEXIO1_DriverIRQHandler [WEAK]
EXPORT FLEXIO2_DriverIRQHandler [WEAK]
EXPORT WDOG1_IRQHandler [WEAK]
EXPORT RTWDOG_IRQHandler [WEAK]
EXPORT EWM_IRQHandler [WEAK]
EXPORT CCM_1_IRQHandler [WEAK]
EXPORT CCM_2_IRQHandler [WEAK]
EXPORT GPC_IRQHandler [WEAK]
EXPORT SRC_IRQHandler [WEAK]
EXPORT Reserved115_IRQHandler [WEAK]
EXPORT GPT1_IRQHandler [WEAK]
EXPORT GPT2_IRQHandler [WEAK]
EXPORT PWM1_0_IRQHandler [WEAK]
EXPORT PWM1_1_IRQHandler [WEAK]
EXPORT PWM1_2_IRQHandler [WEAK]
EXPORT PWM1_3_IRQHandler [WEAK]
EXPORT PWM1_FAULT_IRQHandler [WEAK]
EXPORT FLEXSPI2_DriverIRQHandler [WEAK]
EXPORT FLEXSPI_DriverIRQHandler [WEAK]
EXPORT SEMC_IRQHandler [WEAK]
EXPORT USDHC1_DriverIRQHandler [WEAK]
EXPORT USDHC2_DriverIRQHandler [WEAK]
EXPORT USB_OTG2_IRQHandler [WEAK]
EXPORT USB_OTG1_IRQHandler [WEAK]
EXPORT ENET_DriverIRQHandler [WEAK]
EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK]
EXPORT XBAR1_IRQ_0_1_IRQHandler [WEAK]
EXPORT XBAR1_IRQ_2_3_IRQHandler [WEAK]
EXPORT ADC_ETC_IRQ0_IRQHandler [WEAK]
EXPORT ADC_ETC_IRQ1_IRQHandler [WEAK]
EXPORT ADC_ETC_IRQ2_IRQHandler [WEAK]
EXPORT ADC_ETC_ERROR_IRQ_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT ACMP1_IRQHandler [WEAK]
EXPORT ACMP2_IRQHandler [WEAK]
EXPORT ACMP3_IRQHandler [WEAK]
EXPORT ACMP4_IRQHandler [WEAK]
EXPORT Reserved143_IRQHandler [WEAK]
EXPORT Reserved144_IRQHandler [WEAK]
EXPORT ENC1_IRQHandler [WEAK]
EXPORT ENC2_IRQHandler [WEAK]
EXPORT ENC3_IRQHandler [WEAK]
EXPORT ENC4_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT PWM2_0_IRQHandler [WEAK]
EXPORT PWM2_1_IRQHandler [WEAK]
EXPORT PWM2_2_IRQHandler [WEAK]
EXPORT PWM2_3_IRQHandler [WEAK]
EXPORT PWM2_FAULT_IRQHandler [WEAK]
EXPORT PWM3_0_IRQHandler [WEAK]
EXPORT PWM3_1_IRQHandler [WEAK]
EXPORT PWM3_2_IRQHandler [WEAK]
EXPORT PWM3_3_IRQHandler [WEAK]
EXPORT PWM3_FAULT_IRQHandler [WEAK]
EXPORT PWM4_0_IRQHandler [WEAK]
EXPORT PWM4_1_IRQHandler [WEAK]
EXPORT PWM4_2_IRQHandler [WEAK]
EXPORT PWM4_3_IRQHandler [WEAK]
EXPORT PWM4_FAULT_IRQHandler [WEAK]
EXPORT ENET2_DriverIRQHandler [WEAK]
EXPORT ENET2_1588_Timer_DriverIRQHandler [WEAK]
EXPORT CAN3_DriverIRQHandler [WEAK]
EXPORT Reserved171_IRQHandler [WEAK]
EXPORT FLEXIO3_DriverIRQHandler [WEAK]
EXPORT GPIO6_7_8_9_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_ERROR_DriverIRQHandler
CTI0_ERROR_IRQHandler
CTI1_ERROR_IRQHandler
CORE_IRQHandler
LPUART1_DriverIRQHandler
LPUART2_DriverIRQHandler
LPUART3_DriverIRQHandler
LPUART4_DriverIRQHandler
LPUART5_DriverIRQHandler
LPUART6_DriverIRQHandler
LPUART7_DriverIRQHandler
LPUART8_DriverIRQHandler
LPI2C1_DriverIRQHandler
LPI2C2_DriverIRQHandler
LPI2C3_DriverIRQHandler
LPI2C4_DriverIRQHandler
LPSPI1_DriverIRQHandler
LPSPI2_DriverIRQHandler
LPSPI3_DriverIRQHandler
LPSPI4_DriverIRQHandler
CAN1_DriverIRQHandler
CAN2_DriverIRQHandler
FLEXRAM_IRQHandler
KPP_IRQHandler
TSC_DIG_IRQHandler
GPR_IRQ_IRQHandler
LCDIF_IRQHandler
CSI_IRQHandler
PXP_IRQHandler
WDOG2_IRQHandler
SNVS_HP_WRAPPER_IRQHandler
SNVS_HP_WRAPPER_TZ_IRQHandler
SNVS_LP_WRAPPER_IRQHandler
CSU_IRQHandler
DCP_IRQHandler
DCP_VMI_IRQHandler
Reserved68_IRQHandler
TRNG_IRQHandler
SJC_IRQHandler
BEE_IRQHandler
SAI1_DriverIRQHandler
SAI2_DriverIRQHandler
SAI3_RX_DriverIRQHandler
SAI3_TX_DriverIRQHandler
SPDIF_DriverIRQHandler
PMU_EVENT_IRQHandler
Reserved78_IRQHandler
TEMP_LOW_HIGH_IRQHandler
TEMP_PANIC_IRQHandler
USB_PHY1_IRQHandler
USB_PHY2_IRQHandler
ADC1_IRQHandler
ADC2_IRQHandler
DCDC_IRQHandler
Reserved86_IRQHandler
Reserved87_IRQHandler
GPIO1_INT0_IRQHandler
GPIO1_INT1_IRQHandler
GPIO1_INT2_IRQHandler
GPIO1_INT3_IRQHandler
GPIO1_INT4_IRQHandler
GPIO1_INT5_IRQHandler
GPIO1_INT6_IRQHandler
GPIO1_INT7_IRQHandler
GPIO1_Combined_0_15_IRQHandler
GPIO1_Combined_16_31_IRQHandler
GPIO2_Combined_0_15_IRQHandler
GPIO2_Combined_16_31_IRQHandler
GPIO3_Combined_0_15_IRQHandler
GPIO3_Combined_16_31_IRQHandler
GPIO4_Combined_0_15_IRQHandler
GPIO4_Combined_16_31_IRQHandler
GPIO5_Combined_0_15_IRQHandler
GPIO5_Combined_16_31_IRQHandler
FLEXIO1_DriverIRQHandler
FLEXIO2_DriverIRQHandler
WDOG1_IRQHandler
RTWDOG_IRQHandler
EWM_IRQHandler
CCM_1_IRQHandler
CCM_2_IRQHandler
GPC_IRQHandler
SRC_IRQHandler
Reserved115_IRQHandler
GPT1_IRQHandler
GPT2_IRQHandler
PWM1_0_IRQHandler
PWM1_1_IRQHandler
PWM1_2_IRQHandler
PWM1_3_IRQHandler
PWM1_FAULT_IRQHandler
FLEXSPI2_DriverIRQHandler
FLEXSPI_DriverIRQHandler
SEMC_IRQHandler
USDHC1_DriverIRQHandler
USDHC2_DriverIRQHandler
USB_OTG2_IRQHandler
USB_OTG1_IRQHandler
ENET_DriverIRQHandler
ENET_1588_Timer_DriverIRQHandler
XBAR1_IRQ_0_1_IRQHandler
XBAR1_IRQ_2_3_IRQHandler
ADC_ETC_IRQ0_IRQHandler
ADC_ETC_IRQ1_IRQHandler
ADC_ETC_IRQ2_IRQHandler
ADC_ETC_ERROR_IRQ_IRQHandler
PIT_IRQHandler
ACMP1_IRQHandler
ACMP2_IRQHandler
ACMP3_IRQHandler
ACMP4_IRQHandler
Reserved143_IRQHandler
Reserved144_IRQHandler
ENC1_IRQHandler
ENC2_IRQHandler
ENC3_IRQHandler
ENC4_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
PWM2_0_IRQHandler
PWM2_1_IRQHandler
PWM2_2_IRQHandler
PWM2_3_IRQHandler
PWM2_FAULT_IRQHandler
PWM3_0_IRQHandler
PWM3_1_IRQHandler
PWM3_2_IRQHandler
PWM3_3_IRQHandler
PWM3_FAULT_IRQHandler
PWM4_0_IRQHandler
PWM4_1_IRQHandler
PWM4_2_IRQHandler
PWM4_3_IRQHandler
PWM4_FAULT_IRQHandler
ENET2_DriverIRQHandler
ENET2_1588_Timer_DriverIRQHandler
CAN3_DriverIRQHandler
Reserved171_IRQHandler
FLEXIO3_DriverIRQHandler
GPIO6_7_8_9_IRQHandler
DefaultISR
LDR R0, =DefaultISR
BX R0
ENDP
ALIGN
END
|
nxp-mcuxpresso/OpenART | 46,933 | bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/gcc/startup_MIMXRT1064.S | /* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1064.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1064 */
/* @version: 0.1 */
/* @date: 2018-6-22 */
/* @build: b180820 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/
.long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/
.long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/
.long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/
.long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/
.long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/
.long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/
.long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/
.long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/
.long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/
.long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/
.long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/
.long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/
.long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/
.long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/
.long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/
.long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/
.long CTI0_ERROR_IRQHandler /* CTI0_Error*/
.long CTI1_ERROR_IRQHandler /* CTI1_Error*/
.long CORE_IRQHandler /* CorePlatform exception IRQ*/
.long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/
.long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/
.long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/
.long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/
.long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/
.long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/
.long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/
.long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/
.long LPI2C1_IRQHandler /* LPI2C1 interrupt*/
.long LPI2C2_IRQHandler /* LPI2C2 interrupt*/
.long LPI2C3_IRQHandler /* LPI2C3 interrupt*/
.long LPI2C4_IRQHandler /* LPI2C4 interrupt*/
.long LPSPI1_IRQHandler /* LPSPI1 single interrupt vector for all sources*/
.long LPSPI2_IRQHandler /* LPSPI2 single interrupt vector for all sources*/
.long LPSPI3_IRQHandler /* LPSPI3 single interrupt vector for all sources*/
.long LPSPI4_IRQHandler /* LPSPI4 single interrupt vector for all sources*/
.long CAN1_IRQHandler /* CAN1 interrupt*/
.long CAN2_IRQHandler /* CAN2 interrupt*/
.long FLEXRAM_IRQHandler /* FlexRAM address out of range Or access hit IRQ*/
.long KPP_IRQHandler /* Keypad nterrupt*/
.long TSC_DIG_IRQHandler /* TSC interrupt*/
.long GPR_IRQ_IRQHandler /* GPR interrupt*/
.long LCDIF_IRQHandler /* LCDIF interrupt*/
.long CSI_IRQHandler /* CSI interrupt*/
.long PXP_IRQHandler /* PXP interrupt*/
.long WDOG2_IRQHandler /* WDOG2 interrupt*/
.long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/
.long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/
.long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/
.long CSU_IRQHandler /* CSU interrupt*/
.long DCP_IRQHandler /* DCP_IRQ interrupt*/
.long DCP_VMI_IRQHandler /* DCP_VMI_IRQ interrupt*/
.long Reserved68_IRQHandler /* Reserved interrupt*/
.long TRNG_IRQHandler /* TRNG interrupt*/
.long SJC_IRQHandler /* SJC interrupt*/
.long BEE_IRQHandler /* BEE interrupt*/
.long SAI1_IRQHandler /* SAI1 interrupt*/
.long SAI2_IRQHandler /* SAI1 interrupt*/
.long SAI3_RX_IRQHandler /* SAI3 interrupt*/
.long SAI3_TX_IRQHandler /* SAI3 interrupt*/
.long SPDIF_IRQHandler /* SPDIF interrupt*/
.long PMU_EVENT_IRQHandler /* Brown-out event interrupt*/
.long Reserved78_IRQHandler /* Reserved interrupt*/
.long TEMP_LOW_HIGH_IRQHandler /* TempSensor low/high interrupt*/
.long TEMP_PANIC_IRQHandler /* TempSensor panic interrupt*/
.long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/
.long USB_PHY2_IRQHandler /* USBPHY (UTMI1), Interrupt*/
.long ADC1_IRQHandler /* ADC1 interrupt*/
.long ADC2_IRQHandler /* ADC2 interrupt*/
.long DCDC_IRQHandler /* DCDC interrupt*/
.long Reserved86_IRQHandler /* Reserved interrupt*/
.long Reserved87_IRQHandler /* Reserved interrupt*/
.long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/
.long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/
.long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/
.long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/
.long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/
.long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/
.long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/
.long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/
.long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
.long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
.long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
.long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
.long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
.long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
.long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
.long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
.long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
.long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
.long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/
.long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/
.long WDOG1_IRQHandler /* WDOG1 interrupt*/
.long RTWDOG_IRQHandler /* RTWDOG interrupt*/
.long EWM_IRQHandler /* EWM interrupt*/
.long CCM_1_IRQHandler /* CCM IRQ1 interrupt*/
.long CCM_2_IRQHandler /* CCM IRQ2 interrupt*/
.long GPC_IRQHandler /* GPC interrupt*/
.long SRC_IRQHandler /* SRC interrupt*/
.long Reserved115_IRQHandler /* Reserved interrupt*/
.long GPT1_IRQHandler /* GPT1 interrupt*/
.long GPT2_IRQHandler /* GPT2 interrupt*/
.long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/
.long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/
.long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/
.long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/
.long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/
.long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/
.long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/
.long SEMC_IRQHandler /* Reserved interrupt*/
.long USDHC1_IRQHandler /* USDHC1 interrupt*/
.long USDHC2_IRQHandler /* USDHC2 interrupt*/
.long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/
.long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/
.long ENET_IRQHandler /* ENET interrupt*/
.long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/
.long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/
.long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/
.long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/
.long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/
.long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/
.long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/
.long PIT_IRQHandler /* PIT interrupt*/
.long ACMP1_IRQHandler /* ACMP interrupt*/
.long ACMP2_IRQHandler /* ACMP interrupt*/
.long ACMP3_IRQHandler /* ACMP interrupt*/
.long ACMP4_IRQHandler /* ACMP interrupt*/
.long Reserved143_IRQHandler /* Reserved interrupt*/
.long Reserved144_IRQHandler /* Reserved interrupt*/
.long ENC1_IRQHandler /* ENC1 interrupt*/
.long ENC2_IRQHandler /* ENC2 interrupt*/
.long ENC3_IRQHandler /* ENC3 interrupt*/
.long ENC4_IRQHandler /* ENC4 interrupt*/
.long TMR1_IRQHandler /* TMR1 interrupt*/
.long TMR2_IRQHandler /* TMR2 interrupt*/
.long TMR3_IRQHandler /* TMR3 interrupt*/
.long TMR4_IRQHandler /* TMR4 interrupt*/
.long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/
.long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/
.long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/
.long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/
.long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/
.long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/
.long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/
.long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/
.long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/
.long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/
.long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/
.long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/
.long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
.long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
.long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/
.long ENET2_IRQHandler /* ENET2 interrupt*/
.long ENET2_1588_Timer_IRQHandler /* ENET2_1588_Timer interrupt*/
.long CAN3_IRQHandler /* CAN3 interrupt*/
.long Reserved171_IRQHandler /* Reserved interrupt*/
.long FLEXIO3_IRQHandler /* FLEXIO3 interrupt*/
.long GPIO6_7_8_9_IRQHandler /* GPIO6, GPIO7, GPIO8, GPIO9 interrupt*/
.long DefaultISR /* 174*/
.long DefaultISR /* 175*/
.long DefaultISR /* 176*/
.long DefaultISR /* 177*/
.long DefaultISR /* 178*/
.long DefaultISR /* 179*/
.long DefaultISR /* 180*/
.long DefaultISR /* 181*/
.long DefaultISR /* 182*/
.long DefaultISR /* 183*/
.long DefaultISR /* 184*/
.long DefaultISR /* 185*/
.long DefaultISR /* 186*/
.long DefaultISR /* 187*/
.long DefaultISR /* 188*/
.long DefaultISR /* 189*/
.long DefaultISR /* 190*/
.long DefaultISR /* 191*/
.long DefaultISR /* 192*/
.long DefaultISR /* 193*/
.long DefaultISR /* 194*/
.long DefaultISR /* 195*/
.long DefaultISR /* 196*/
.long DefaultISR /* 197*/
.long DefaultISR /* 198*/
.long DefaultISR /* 199*/
.long DefaultISR /* 200*/
.long DefaultISR /* 201*/
.long DefaultISR /* 202*/
.long DefaultISR /* 203*/
.long DefaultISR /* 204*/
.long DefaultISR /* 205*/
.long DefaultISR /* 206*/
.long DefaultISR /* 207*/
.long DefaultISR /* 208*/
.long DefaultISR /* 209*/
.long DefaultISR /* 210*/
.long DefaultISR /* 211*/
.long DefaultISR /* 212*/
.long DefaultISR /* 213*/
.long DefaultISR /* 214*/
.long DefaultISR /* 215*/
.long DefaultISR /* 216*/
.long DefaultISR /* 217*/
.long DefaultISR /* 218*/
.long DefaultISR /* 219*/
.long DefaultISR /* 220*/
.long DefaultISR /* 221*/
.long DefaultISR /* 222*/
.long DefaultISR /* 223*/
.long DefaultISR /* 224*/
.long DefaultISR /* 225*/
.long DefaultISR /* 226*/
.long DefaultISR /* 227*/
.long DefaultISR /* 228*/
.long DefaultISR /* 229*/
.long DefaultISR /* 230*/
.long DefaultISR /* 231*/
.long DefaultISR /* 232*/
.long DefaultISR /* 233*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.long DefaultISR /* 240*/
.long DefaultISR /* 241*/
.long DefaultISR /* 242*/
.long DefaultISR /* 243*/
.long DefaultISR /* 244*/
.long DefaultISR /* 245*/
.long DefaultISR /* 246*/
.long DefaultISR /* 247*/
.long DefaultISR /* 248*/
.long DefaultISR /* 249*/
.long DefaultISR /* 250*/
.long DefaultISR /* 251*/
.long DefaultISR /* 252*/
.long DefaultISR /* 253*/
.long DefaultISR /* 254*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#if 1
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#else
subs r3, r2
ble .LC3
.LC2:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC2
.LC3:
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
movs r0,0
.LC4:
cmp r2,r3
itt lt
strlt r0,[r2],#4
blt .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC5:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC5
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak DMA0_DMA16_IRQHandler
.type DMA0_DMA16_IRQHandler, %function
DMA0_DMA16_IRQHandler:
ldr r0,=DMA0_DMA16_DriverIRQHandler
bx r0
.size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
.align 1
.thumb_func
.weak DMA1_DMA17_IRQHandler
.type DMA1_DMA17_IRQHandler, %function
DMA1_DMA17_IRQHandler:
ldr r0,=DMA1_DMA17_DriverIRQHandler
bx r0
.size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
.align 1
.thumb_func
.weak DMA2_DMA18_IRQHandler
.type DMA2_DMA18_IRQHandler, %function
DMA2_DMA18_IRQHandler:
ldr r0,=DMA2_DMA18_DriverIRQHandler
bx r0
.size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
.align 1
.thumb_func
.weak DMA3_DMA19_IRQHandler
.type DMA3_DMA19_IRQHandler, %function
DMA3_DMA19_IRQHandler:
ldr r0,=DMA3_DMA19_DriverIRQHandler
bx r0
.size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
.align 1
.thumb_func
.weak DMA4_DMA20_IRQHandler
.type DMA4_DMA20_IRQHandler, %function
DMA4_DMA20_IRQHandler:
ldr r0,=DMA4_DMA20_DriverIRQHandler
bx r0
.size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
.align 1
.thumb_func
.weak DMA5_DMA21_IRQHandler
.type DMA5_DMA21_IRQHandler, %function
DMA5_DMA21_IRQHandler:
ldr r0,=DMA5_DMA21_DriverIRQHandler
bx r0
.size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
.align 1
.thumb_func
.weak DMA6_DMA22_IRQHandler
.type DMA6_DMA22_IRQHandler, %function
DMA6_DMA22_IRQHandler:
ldr r0,=DMA6_DMA22_DriverIRQHandler
bx r0
.size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
.align 1
.thumb_func
.weak DMA7_DMA23_IRQHandler
.type DMA7_DMA23_IRQHandler, %function
DMA7_DMA23_IRQHandler:
ldr r0,=DMA7_DMA23_DriverIRQHandler
bx r0
.size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
.align 1
.thumb_func
.weak DMA8_DMA24_IRQHandler
.type DMA8_DMA24_IRQHandler, %function
DMA8_DMA24_IRQHandler:
ldr r0,=DMA8_DMA24_DriverIRQHandler
bx r0
.size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
.align 1
.thumb_func
.weak DMA9_DMA25_IRQHandler
.type DMA9_DMA25_IRQHandler, %function
DMA9_DMA25_IRQHandler:
ldr r0,=DMA9_DMA25_DriverIRQHandler
bx r0
.size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
.align 1
.thumb_func
.weak DMA10_DMA26_IRQHandler
.type DMA10_DMA26_IRQHandler, %function
DMA10_DMA26_IRQHandler:
ldr r0,=DMA10_DMA26_DriverIRQHandler
bx r0
.size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
.align 1
.thumb_func
.weak DMA11_DMA27_IRQHandler
.type DMA11_DMA27_IRQHandler, %function
DMA11_DMA27_IRQHandler:
ldr r0,=DMA11_DMA27_DriverIRQHandler
bx r0
.size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
.align 1
.thumb_func
.weak DMA12_DMA28_IRQHandler
.type DMA12_DMA28_IRQHandler, %function
DMA12_DMA28_IRQHandler:
ldr r0,=DMA12_DMA28_DriverIRQHandler
bx r0
.size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
.align 1
.thumb_func
.weak DMA13_DMA29_IRQHandler
.type DMA13_DMA29_IRQHandler, %function
DMA13_DMA29_IRQHandler:
ldr r0,=DMA13_DMA29_DriverIRQHandler
bx r0
.size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
.align 1
.thumb_func
.weak DMA14_DMA30_IRQHandler
.type DMA14_DMA30_IRQHandler, %function
DMA14_DMA30_IRQHandler:
ldr r0,=DMA14_DMA30_DriverIRQHandler
bx r0
.size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
.align 1
.thumb_func
.weak DMA15_DMA31_IRQHandler
.type DMA15_DMA31_IRQHandler, %function
DMA15_DMA31_IRQHandler:
ldr r0,=DMA15_DMA31_DriverIRQHandler
bx r0
.size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
.align 1
.thumb_func
.weak DMA_ERROR_IRQHandler
.type DMA_ERROR_IRQHandler, %function
DMA_ERROR_IRQHandler:
ldr r0,=DMA_ERROR_DriverIRQHandler
bx r0
.size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler
.align 1
.thumb_func
.weak LPUART1_IRQHandler
.type LPUART1_IRQHandler, %function
LPUART1_IRQHandler:
ldr r0,=LPUART1_DriverIRQHandler
bx r0
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
.align 1
.thumb_func
.weak LPUART2_IRQHandler
.type LPUART2_IRQHandler, %function
LPUART2_IRQHandler:
ldr r0,=LPUART2_DriverIRQHandler
bx r0
.size LPUART2_IRQHandler, . - LPUART2_IRQHandler
.align 1
.thumb_func
.weak LPUART3_IRQHandler
.type LPUART3_IRQHandler, %function
LPUART3_IRQHandler:
ldr r0,=LPUART3_DriverIRQHandler
bx r0
.size LPUART3_IRQHandler, . - LPUART3_IRQHandler
.align 1
.thumb_func
.weak LPUART4_IRQHandler
.type LPUART4_IRQHandler, %function
LPUART4_IRQHandler:
ldr r0,=LPUART4_DriverIRQHandler
bx r0
.size LPUART4_IRQHandler, . - LPUART4_IRQHandler
.align 1
.thumb_func
.weak LPUART5_IRQHandler
.type LPUART5_IRQHandler, %function
LPUART5_IRQHandler:
ldr r0,=LPUART5_DriverIRQHandler
bx r0
.size LPUART5_IRQHandler, . - LPUART5_IRQHandler
.align 1
.thumb_func
.weak LPUART6_IRQHandler
.type LPUART6_IRQHandler, %function
LPUART6_IRQHandler:
ldr r0,=LPUART6_DriverIRQHandler
bx r0
.size LPUART6_IRQHandler, . - LPUART6_IRQHandler
.align 1
.thumb_func
.weak LPUART7_IRQHandler
.type LPUART7_IRQHandler, %function
LPUART7_IRQHandler:
ldr r0,=LPUART7_DriverIRQHandler
bx r0
.size LPUART7_IRQHandler, . - LPUART7_IRQHandler
.align 1
.thumb_func
.weak LPUART8_IRQHandler
.type LPUART8_IRQHandler, %function
LPUART8_IRQHandler:
ldr r0,=LPUART8_DriverIRQHandler
bx r0
.size LPUART8_IRQHandler, . - LPUART8_IRQHandler
.align 1
.thumb_func
.weak LPI2C1_IRQHandler
.type LPI2C1_IRQHandler, %function
LPI2C1_IRQHandler:
ldr r0,=LPI2C1_DriverIRQHandler
bx r0
.size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler
.align 1
.thumb_func
.weak LPI2C2_IRQHandler
.type LPI2C2_IRQHandler, %function
LPI2C2_IRQHandler:
ldr r0,=LPI2C2_DriverIRQHandler
bx r0
.size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler
.align 1
.thumb_func
.weak LPI2C3_IRQHandler
.type LPI2C3_IRQHandler, %function
LPI2C3_IRQHandler:
ldr r0,=LPI2C3_DriverIRQHandler
bx r0
.size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler
.align 1
.thumb_func
.weak LPI2C4_IRQHandler
.type LPI2C4_IRQHandler, %function
LPI2C4_IRQHandler:
ldr r0,=LPI2C4_DriverIRQHandler
bx r0
.size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler
.align 1
.thumb_func
.weak LPSPI1_IRQHandler
.type LPSPI1_IRQHandler, %function
LPSPI1_IRQHandler:
ldr r0,=LPSPI1_DriverIRQHandler
bx r0
.size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler
.align 1
.thumb_func
.weak LPSPI2_IRQHandler
.type LPSPI2_IRQHandler, %function
LPSPI2_IRQHandler:
ldr r0,=LPSPI2_DriverIRQHandler
bx r0
.size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler
.align 1
.thumb_func
.weak LPSPI3_IRQHandler
.type LPSPI3_IRQHandler, %function
LPSPI3_IRQHandler:
ldr r0,=LPSPI3_DriverIRQHandler
bx r0
.size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler
.align 1
.thumb_func
.weak LPSPI4_IRQHandler
.type LPSPI4_IRQHandler, %function
LPSPI4_IRQHandler:
ldr r0,=LPSPI4_DriverIRQHandler
bx r0
.size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler
.align 1
.thumb_func
.weak CAN1_IRQHandler
.type CAN1_IRQHandler, %function
CAN1_IRQHandler:
ldr r0,=CAN1_DriverIRQHandler
bx r0
.size CAN1_IRQHandler, . - CAN1_IRQHandler
.align 1
.thumb_func
.weak CAN2_IRQHandler
.type CAN2_IRQHandler, %function
CAN2_IRQHandler:
ldr r0,=CAN2_DriverIRQHandler
bx r0
.size CAN2_IRQHandler, . - CAN2_IRQHandler
.align 1
.thumb_func
.weak SAI1_IRQHandler
.type SAI1_IRQHandler, %function
SAI1_IRQHandler:
ldr r0,=SAI1_DriverIRQHandler
bx r0
.size SAI1_IRQHandler, . - SAI1_IRQHandler
.align 1
.thumb_func
.weak SAI2_IRQHandler
.type SAI2_IRQHandler, %function
SAI2_IRQHandler:
ldr r0,=SAI2_DriverIRQHandler
bx r0
.size SAI2_IRQHandler, . - SAI2_IRQHandler
.align 1
.thumb_func
.weak SAI3_RX_IRQHandler
.type SAI3_RX_IRQHandler, %function
SAI3_RX_IRQHandler:
ldr r0,=SAI3_RX_DriverIRQHandler
bx r0
.size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler
.align 1
.thumb_func
.weak SAI3_TX_IRQHandler
.type SAI3_TX_IRQHandler, %function
SAI3_TX_IRQHandler:
ldr r0,=SAI3_TX_DriverIRQHandler
bx r0
.size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler
.align 1
.thumb_func
.weak SPDIF_IRQHandler
.type SPDIF_IRQHandler, %function
SPDIF_IRQHandler:
ldr r0,=SPDIF_DriverIRQHandler
bx r0
.size SPDIF_IRQHandler, . - SPDIF_IRQHandler
.align 1
.thumb_func
.weak FLEXIO1_IRQHandler
.type FLEXIO1_IRQHandler, %function
FLEXIO1_IRQHandler:
ldr r0,=FLEXIO1_DriverIRQHandler
bx r0
.size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler
.align 1
.thumb_func
.weak FLEXIO2_IRQHandler
.type FLEXIO2_IRQHandler, %function
FLEXIO2_IRQHandler:
ldr r0,=FLEXIO2_DriverIRQHandler
bx r0
.size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler
.align 1
.thumb_func
.weak FLEXSPI2_IRQHandler
.type FLEXSPI2_IRQHandler, %function
FLEXSPI2_IRQHandler:
ldr r0,=FLEXSPI2_DriverIRQHandler
bx r0
.size FLEXSPI2_IRQHandler, . - FLEXSPI2_IRQHandler
.align 1
.thumb_func
.weak FLEXSPI_IRQHandler
.type FLEXSPI_IRQHandler, %function
FLEXSPI_IRQHandler:
ldr r0,=FLEXSPI_DriverIRQHandler
bx r0
.size FLEXSPI_IRQHandler, . - FLEXSPI_IRQHandler
.align 1
.thumb_func
.weak USDHC1_IRQHandler
.type USDHC1_IRQHandler, %function
USDHC1_IRQHandler:
ldr r0,=USDHC1_DriverIRQHandler
bx r0
.size USDHC1_IRQHandler, . - USDHC1_IRQHandler
.align 1
.thumb_func
.weak USDHC2_IRQHandler
.type USDHC2_IRQHandler, %function
USDHC2_IRQHandler:
ldr r0,=USDHC2_DriverIRQHandler
bx r0
.size USDHC2_IRQHandler, . - USDHC2_IRQHandler
.align 1
.thumb_func
.weak ENET_IRQHandler
.type ENET_IRQHandler, %function
ENET_IRQHandler:
ldr r0,=ENET_DriverIRQHandler
bx r0
.size ENET_IRQHandler, . - ENET_IRQHandler
.align 1
.thumb_func
.weak ENET_1588_Timer_IRQHandler
.type ENET_1588_Timer_IRQHandler, %function
ENET_1588_Timer_IRQHandler:
ldr r0,=ENET_1588_Timer_DriverIRQHandler
bx r0
.size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler
.align 1
.thumb_func
.weak ENET2_IRQHandler
.type ENET2_IRQHandler, %function
ENET2_IRQHandler:
ldr r0,=ENET2_DriverIRQHandler
bx r0
.size ENET2_IRQHandler, . - ENET2_IRQHandler
.align 1
.thumb_func
.weak ENET2_1588_Timer_IRQHandler
.type ENET2_1588_Timer_IRQHandler, %function
ENET2_1588_Timer_IRQHandler:
ldr r0,=ENET2_1588_Timer_DriverIRQHandler
bx r0
.size ENET2_1588_Timer_IRQHandler, . - ENET2_1588_Timer_IRQHandler
.align 1
.thumb_func
.weak CAN3_IRQHandler
.type CAN3_IRQHandler, %function
CAN3_IRQHandler:
ldr r0,=CAN3_DriverIRQHandler
bx r0
.size CAN3_IRQHandler, . - CAN3_IRQHandler
.align 1
.thumb_func
.weak FLEXIO3_IRQHandler
.type FLEXIO3_IRQHandler, %function
FLEXIO3_IRQHandler:
ldr r0,=FLEXIO3_DriverIRQHandler
bx r0
.size FLEXIO3_IRQHandler, . - FLEXIO3_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler DMA0_DMA16_DriverIRQHandler
def_irq_handler DMA1_DMA17_DriverIRQHandler
def_irq_handler DMA2_DMA18_DriverIRQHandler
def_irq_handler DMA3_DMA19_DriverIRQHandler
def_irq_handler DMA4_DMA20_DriverIRQHandler
def_irq_handler DMA5_DMA21_DriverIRQHandler
def_irq_handler DMA6_DMA22_DriverIRQHandler
def_irq_handler DMA7_DMA23_DriverIRQHandler
def_irq_handler DMA8_DMA24_DriverIRQHandler
def_irq_handler DMA9_DMA25_DriverIRQHandler
def_irq_handler DMA10_DMA26_DriverIRQHandler
def_irq_handler DMA11_DMA27_DriverIRQHandler
def_irq_handler DMA12_DMA28_DriverIRQHandler
def_irq_handler DMA13_DMA29_DriverIRQHandler
def_irq_handler DMA14_DMA30_DriverIRQHandler
def_irq_handler DMA15_DMA31_DriverIRQHandler
def_irq_handler DMA_ERROR_DriverIRQHandler
def_irq_handler CTI0_ERROR_IRQHandler
def_irq_handler CTI1_ERROR_IRQHandler
def_irq_handler CORE_IRQHandler
def_irq_handler LPUART1_DriverIRQHandler
def_irq_handler LPUART2_DriverIRQHandler
def_irq_handler LPUART3_DriverIRQHandler
def_irq_handler LPUART4_DriverIRQHandler
def_irq_handler LPUART5_DriverIRQHandler
def_irq_handler LPUART6_DriverIRQHandler
def_irq_handler LPUART7_DriverIRQHandler
def_irq_handler LPUART8_DriverIRQHandler
def_irq_handler LPI2C1_DriverIRQHandler
def_irq_handler LPI2C2_DriverIRQHandler
def_irq_handler LPI2C3_DriverIRQHandler
def_irq_handler LPI2C4_DriverIRQHandler
def_irq_handler LPSPI1_DriverIRQHandler
def_irq_handler LPSPI2_DriverIRQHandler
def_irq_handler LPSPI3_DriverIRQHandler
def_irq_handler LPSPI4_DriverIRQHandler
def_irq_handler CAN1_DriverIRQHandler
def_irq_handler CAN2_DriverIRQHandler
def_irq_handler FLEXRAM_IRQHandler
def_irq_handler KPP_IRQHandler
def_irq_handler TSC_DIG_IRQHandler
def_irq_handler GPR_IRQ_IRQHandler
def_irq_handler LCDIF_IRQHandler
def_irq_handler CSI_IRQHandler
def_irq_handler PXP_IRQHandler
def_irq_handler WDOG2_IRQHandler
def_irq_handler SNVS_HP_WRAPPER_IRQHandler
def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler
def_irq_handler SNVS_LP_WRAPPER_IRQHandler
def_irq_handler CSU_IRQHandler
def_irq_handler DCP_IRQHandler
def_irq_handler DCP_VMI_IRQHandler
def_irq_handler Reserved68_IRQHandler
def_irq_handler TRNG_IRQHandler
def_irq_handler SJC_IRQHandler
def_irq_handler BEE_IRQHandler
def_irq_handler SAI1_DriverIRQHandler
def_irq_handler SAI2_DriverIRQHandler
def_irq_handler SAI3_RX_DriverIRQHandler
def_irq_handler SAI3_TX_DriverIRQHandler
def_irq_handler SPDIF_DriverIRQHandler
def_irq_handler PMU_EVENT_IRQHandler
def_irq_handler Reserved78_IRQHandler
def_irq_handler TEMP_LOW_HIGH_IRQHandler
def_irq_handler TEMP_PANIC_IRQHandler
def_irq_handler USB_PHY1_IRQHandler
def_irq_handler USB_PHY2_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler ADC2_IRQHandler
def_irq_handler DCDC_IRQHandler
def_irq_handler Reserved86_IRQHandler
def_irq_handler Reserved87_IRQHandler
def_irq_handler GPIO1_INT0_IRQHandler
def_irq_handler GPIO1_INT1_IRQHandler
def_irq_handler GPIO1_INT2_IRQHandler
def_irq_handler GPIO1_INT3_IRQHandler
def_irq_handler GPIO1_INT4_IRQHandler
def_irq_handler GPIO1_INT5_IRQHandler
def_irq_handler GPIO1_INT6_IRQHandler
def_irq_handler GPIO1_INT7_IRQHandler
def_irq_handler GPIO1_Combined_0_15_IRQHandler
def_irq_handler GPIO1_Combined_16_31_IRQHandler
def_irq_handler GPIO2_Combined_0_15_IRQHandler
def_irq_handler GPIO2_Combined_16_31_IRQHandler
def_irq_handler GPIO3_Combined_0_15_IRQHandler
def_irq_handler GPIO3_Combined_16_31_IRQHandler
def_irq_handler GPIO4_Combined_0_15_IRQHandler
def_irq_handler GPIO4_Combined_16_31_IRQHandler
def_irq_handler GPIO5_Combined_0_15_IRQHandler
def_irq_handler GPIO5_Combined_16_31_IRQHandler
def_irq_handler FLEXIO1_DriverIRQHandler
def_irq_handler FLEXIO2_DriverIRQHandler
def_irq_handler WDOG1_IRQHandler
def_irq_handler RTWDOG_IRQHandler
def_irq_handler EWM_IRQHandler
def_irq_handler CCM_1_IRQHandler
def_irq_handler CCM_2_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler SRC_IRQHandler
def_irq_handler Reserved115_IRQHandler
def_irq_handler GPT1_IRQHandler
def_irq_handler GPT2_IRQHandler
def_irq_handler PWM1_0_IRQHandler
def_irq_handler PWM1_1_IRQHandler
def_irq_handler PWM1_2_IRQHandler
def_irq_handler PWM1_3_IRQHandler
def_irq_handler PWM1_FAULT_IRQHandler
def_irq_handler FLEXSPI2_DriverIRQHandler
def_irq_handler FLEXSPI_DriverIRQHandler
def_irq_handler SEMC_IRQHandler
def_irq_handler USDHC1_DriverIRQHandler
def_irq_handler USDHC2_DriverIRQHandler
def_irq_handler USB_OTG2_IRQHandler
def_irq_handler USB_OTG1_IRQHandler
def_irq_handler ENET_DriverIRQHandler
def_irq_handler ENET_1588_Timer_DriverIRQHandler
def_irq_handler XBAR1_IRQ_0_1_IRQHandler
def_irq_handler XBAR1_IRQ_2_3_IRQHandler
def_irq_handler ADC_ETC_IRQ0_IRQHandler
def_irq_handler ADC_ETC_IRQ1_IRQHandler
def_irq_handler ADC_ETC_IRQ2_IRQHandler
def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler
def_irq_handler PIT_IRQHandler
def_irq_handler ACMP1_IRQHandler
def_irq_handler ACMP2_IRQHandler
def_irq_handler ACMP3_IRQHandler
def_irq_handler ACMP4_IRQHandler
def_irq_handler Reserved143_IRQHandler
def_irq_handler Reserved144_IRQHandler
def_irq_handler ENC1_IRQHandler
def_irq_handler ENC2_IRQHandler
def_irq_handler ENC3_IRQHandler
def_irq_handler ENC4_IRQHandler
def_irq_handler TMR1_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler TMR4_IRQHandler
def_irq_handler PWM2_0_IRQHandler
def_irq_handler PWM2_1_IRQHandler
def_irq_handler PWM2_2_IRQHandler
def_irq_handler PWM2_3_IRQHandler
def_irq_handler PWM2_FAULT_IRQHandler
def_irq_handler PWM3_0_IRQHandler
def_irq_handler PWM3_1_IRQHandler
def_irq_handler PWM3_2_IRQHandler
def_irq_handler PWM3_3_IRQHandler
def_irq_handler PWM3_FAULT_IRQHandler
def_irq_handler PWM4_0_IRQHandler
def_irq_handler PWM4_1_IRQHandler
def_irq_handler PWM4_2_IRQHandler
def_irq_handler PWM4_3_IRQHandler
def_irq_handler PWM4_FAULT_IRQHandler
def_irq_handler ENET2_DriverIRQHandler
def_irq_handler ENET2_1588_Timer_DriverIRQHandler
def_irq_handler CAN3_DriverIRQHandler
def_irq_handler Reserved171_IRQHandler
def_irq_handler FLEXIO3_DriverIRQHandler
def_irq_handler GPIO6_7_8_9_IRQHandler
.end
|
nxp-mcuxpresso/OpenART | 42,874 | bsp/imxrt/libraries/MIMXRT1064/MIMXRT1064/iar/startup_MIMXRT1064.s | ; -------------------------------------------------------------------------
; @file: startup_MIMXRT1064.s
; @purpose: CMSIS Cortex-M7 Core Device Startup File
; MIMXRT1064
; @version: 0.1
; @date: 2018-6-22
; @build: b180820
; -------------------------------------------------------------------------
;
; Copyright 1997-2016 Freescale Semiconductor, Inc.
; Copyright 2016-2018 NXP
;
; SPDX-License-Identifier: BSD-3-Clause
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
__vector_table_0x1c
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete
DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete
DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete
DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete
DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete
DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete
DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete
DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete
DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete
DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete
DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete
DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete
DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete
DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete
DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete
DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete
DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31
DCD CTI0_ERROR_IRQHandler ;CTI0_Error
DCD CTI1_ERROR_IRQHandler ;CTI1_Error
DCD CORE_IRQHandler ;CorePlatform exception IRQ
DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt
DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt
DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt
DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt
DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt
DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt
DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt
DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt
DCD LPI2C1_IRQHandler ;LPI2C1 interrupt
DCD LPI2C2_IRQHandler ;LPI2C2 interrupt
DCD LPI2C3_IRQHandler ;LPI2C3 interrupt
DCD LPI2C4_IRQHandler ;LPI2C4 interrupt
DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources
DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources
DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources
DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources
DCD CAN1_IRQHandler ;CAN1 interrupt
DCD CAN2_IRQHandler ;CAN2 interrupt
DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ
DCD KPP_IRQHandler ;Keypad nterrupt
DCD TSC_DIG_IRQHandler ;TSC interrupt
DCD GPR_IRQ_IRQHandler ;GPR interrupt
DCD LCDIF_IRQHandler ;LCDIF interrupt
DCD CSI_IRQHandler ;CSI interrupt
DCD PXP_IRQHandler ;PXP interrupt
DCD WDOG2_IRQHandler ;WDOG2 interrupt
DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ
DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ
DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event)
DCD CSU_IRQHandler ;CSU interrupt
DCD DCP_IRQHandler ;DCP_IRQ interrupt
DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt
DCD Reserved68_IRQHandler ;Reserved interrupt
DCD TRNG_IRQHandler ;TRNG interrupt
DCD SJC_IRQHandler ;SJC interrupt
DCD BEE_IRQHandler ;BEE interrupt
DCD SAI1_IRQHandler ;SAI1 interrupt
DCD SAI2_IRQHandler ;SAI1 interrupt
DCD SAI3_RX_IRQHandler ;SAI3 interrupt
DCD SAI3_TX_IRQHandler ;SAI3 interrupt
DCD SPDIF_IRQHandler ;SPDIF interrupt
DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt
DCD Reserved78_IRQHandler ;Reserved interrupt
DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt
DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt
DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD USB_PHY2_IRQHandler ;USBPHY (UTMI1), Interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
DCD ADC2_IRQHandler ;ADC2 interrupt
DCD DCDC_IRQHandler ;DCDC interrupt
DCD Reserved86_IRQHandler ;Reserved interrupt
DCD Reserved87_IRQHandler ;Reserved interrupt
DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO
DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO
DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO
DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO
DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO
DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO
DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO
DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO
DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15
DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31
DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15
DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31
DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15
DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31
DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15
DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31
DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15
DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31
DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt
DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt
DCD WDOG1_IRQHandler ;WDOG1 interrupt
DCD RTWDOG_IRQHandler ;RTWDOG interrupt
DCD EWM_IRQHandler ;EWM interrupt
DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt
DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt
DCD GPC_IRQHandler ;GPC interrupt
DCD SRC_IRQHandler ;SRC interrupt
DCD Reserved115_IRQHandler ;Reserved interrupt
DCD GPT1_IRQHandler ;GPT1 interrupt
DCD GPT2_IRQHandler ;GPT2 interrupt
DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt
DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt
DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt
DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt
DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt
DCD FLEXSPI2_IRQHandler ;FlexSPI2 interrupt
DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt
DCD SEMC_IRQHandler ;Reserved interrupt
DCD USDHC1_IRQHandler ;USDHC1 interrupt
DCD USDHC2_IRQHandler ;USDHC2 interrupt
DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2
DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1
DCD ENET_IRQHandler ;ENET interrupt
DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt
DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt
DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt
DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt
DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt
DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt
DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt
DCD PIT_IRQHandler ;PIT interrupt
DCD ACMP1_IRQHandler ;ACMP interrupt
DCD ACMP2_IRQHandler ;ACMP interrupt
DCD ACMP3_IRQHandler ;ACMP interrupt
DCD ACMP4_IRQHandler ;ACMP interrupt
DCD Reserved143_IRQHandler ;Reserved interrupt
DCD Reserved144_IRQHandler ;Reserved interrupt
DCD ENC1_IRQHandler ;ENC1 interrupt
DCD ENC2_IRQHandler ;ENC2 interrupt
DCD ENC3_IRQHandler ;ENC3 interrupt
DCD ENC4_IRQHandler ;ENC4 interrupt
DCD TMR1_IRQHandler ;TMR1 interrupt
DCD TMR2_IRQHandler ;TMR2 interrupt
DCD TMR3_IRQHandler ;TMR3 interrupt
DCD TMR4_IRQHandler ;TMR4 interrupt
DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt
DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt
DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt
DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt
DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt
DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt
DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt
DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt
DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt
DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt
DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt
DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt
DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt
DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt
DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt
DCD ENET2_IRQHandler ;ENET2 interrupt
DCD ENET2_1588_Timer_IRQHandler ;ENET2_1588_Timer interrupt
DCD CAN3_IRQHandler ;CAN3 interrupt
DCD Reserved171_IRQHandler ;Reserved interrupt
DCD FLEXIO3_IRQHandler ;FLEXIO3 interrupt
DCD GPIO6_7_8_9_IRQHandler ;GPIO6, GPIO7, GPIO8, GPIO9 interrupt
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
DCD DefaultISR ;240
DCD DefaultISR ;241
DCD DefaultISR ;242
DCD DefaultISR ;243
DCD DefaultISR ;244
DCD DefaultISR ;245
DCD DefaultISR ;246
DCD DefaultISR ;247
DCD DefaultISR ;248
DCD DefaultISR ;249
DCD DefaultISR ;250
DCD DefaultISR ;251
DCD DefaultISR ;252
DCD DefaultISR ;253
DCD DefaultISR ;254
DCD 0xFFFFFFFF ; Reserved for user TRIM value
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__vector_table
STR R1, [R0]
LDR R2, [R1]
MSR MSP, R2
LDR R0, =SystemInit
BLX R0
CPSIE I ; Unmask interrupts
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B .
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B .
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK DMA0_DMA16_IRQHandler
PUBWEAK DMA0_DMA16_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA0_DMA16_IRQHandler
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
PUBWEAK DMA1_DMA17_IRQHandler
PUBWEAK DMA1_DMA17_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA1_DMA17_IRQHandler
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
PUBWEAK DMA2_DMA18_IRQHandler
PUBWEAK DMA2_DMA18_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA2_DMA18_IRQHandler
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
PUBWEAK DMA3_DMA19_IRQHandler
PUBWEAK DMA3_DMA19_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA3_DMA19_IRQHandler
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
PUBWEAK DMA4_DMA20_IRQHandler
PUBWEAK DMA4_DMA20_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA4_DMA20_IRQHandler
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
PUBWEAK DMA5_DMA21_IRQHandler
PUBWEAK DMA5_DMA21_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA5_DMA21_IRQHandler
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
PUBWEAK DMA6_DMA22_IRQHandler
PUBWEAK DMA6_DMA22_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA6_DMA22_IRQHandler
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
PUBWEAK DMA7_DMA23_IRQHandler
PUBWEAK DMA7_DMA23_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA7_DMA23_IRQHandler
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
PUBWEAK DMA8_DMA24_IRQHandler
PUBWEAK DMA8_DMA24_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA8_DMA24_IRQHandler
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
PUBWEAK DMA9_DMA25_IRQHandler
PUBWEAK DMA9_DMA25_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA9_DMA25_IRQHandler
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
PUBWEAK DMA10_DMA26_IRQHandler
PUBWEAK DMA10_DMA26_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA10_DMA26_IRQHandler
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
PUBWEAK DMA11_DMA27_IRQHandler
PUBWEAK DMA11_DMA27_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA11_DMA27_IRQHandler
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
PUBWEAK DMA12_DMA28_IRQHandler
PUBWEAK DMA12_DMA28_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA12_DMA28_IRQHandler
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
PUBWEAK DMA13_DMA29_IRQHandler
PUBWEAK DMA13_DMA29_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA13_DMA29_IRQHandler
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
PUBWEAK DMA14_DMA30_IRQHandler
PUBWEAK DMA14_DMA30_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA14_DMA30_IRQHandler
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
PUBWEAK DMA15_DMA31_IRQHandler
PUBWEAK DMA15_DMA31_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA15_DMA31_IRQHandler
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
PUBWEAK DMA_ERROR_IRQHandler
PUBWEAK DMA_ERROR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA_ERROR_IRQHandler
LDR R0, =DMA_ERROR_DriverIRQHandler
BX R0
PUBWEAK CTI0_ERROR_IRQHandler
PUBWEAK CTI1_ERROR_IRQHandler
PUBWEAK CORE_IRQHandler
PUBWEAK LPUART1_IRQHandler
PUBWEAK LPUART1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART1_IRQHandler
LDR R0, =LPUART1_DriverIRQHandler
BX R0
PUBWEAK LPUART2_IRQHandler
PUBWEAK LPUART2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART2_IRQHandler
LDR R0, =LPUART2_DriverIRQHandler
BX R0
PUBWEAK LPUART3_IRQHandler
PUBWEAK LPUART3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART3_IRQHandler
LDR R0, =LPUART3_DriverIRQHandler
BX R0
PUBWEAK LPUART4_IRQHandler
PUBWEAK LPUART4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART4_IRQHandler
LDR R0, =LPUART4_DriverIRQHandler
BX R0
PUBWEAK LPUART5_IRQHandler
PUBWEAK LPUART5_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART5_IRQHandler
LDR R0, =LPUART5_DriverIRQHandler
BX R0
PUBWEAK LPUART6_IRQHandler
PUBWEAK LPUART6_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART6_IRQHandler
LDR R0, =LPUART6_DriverIRQHandler
BX R0
PUBWEAK LPUART7_IRQHandler
PUBWEAK LPUART7_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART7_IRQHandler
LDR R0, =LPUART7_DriverIRQHandler
BX R0
PUBWEAK LPUART8_IRQHandler
PUBWEAK LPUART8_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART8_IRQHandler
LDR R0, =LPUART8_DriverIRQHandler
BX R0
PUBWEAK LPI2C1_IRQHandler
PUBWEAK LPI2C1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C1_IRQHandler
LDR R0, =LPI2C1_DriverIRQHandler
BX R0
PUBWEAK LPI2C2_IRQHandler
PUBWEAK LPI2C2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C2_IRQHandler
LDR R0, =LPI2C2_DriverIRQHandler
BX R0
PUBWEAK LPI2C3_IRQHandler
PUBWEAK LPI2C3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C3_IRQHandler
LDR R0, =LPI2C3_DriverIRQHandler
BX R0
PUBWEAK LPI2C4_IRQHandler
PUBWEAK LPI2C4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C4_IRQHandler
LDR R0, =LPI2C4_DriverIRQHandler
BX R0
PUBWEAK LPSPI1_IRQHandler
PUBWEAK LPSPI1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI1_IRQHandler
LDR R0, =LPSPI1_DriverIRQHandler
BX R0
PUBWEAK LPSPI2_IRQHandler
PUBWEAK LPSPI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI2_IRQHandler
LDR R0, =LPSPI2_DriverIRQHandler
BX R0
PUBWEAK LPSPI3_IRQHandler
PUBWEAK LPSPI3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI3_IRQHandler
LDR R0, =LPSPI3_DriverIRQHandler
BX R0
PUBWEAK LPSPI4_IRQHandler
PUBWEAK LPSPI4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI4_IRQHandler
LDR R0, =LPSPI4_DriverIRQHandler
BX R0
PUBWEAK CAN1_IRQHandler
PUBWEAK CAN1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN2_IRQHandler
PUBWEAK CAN2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN2_IRQHandler
LDR R0, =CAN2_DriverIRQHandler
BX R0
PUBWEAK FLEXRAM_IRQHandler
PUBWEAK KPP_IRQHandler
PUBWEAK TSC_DIG_IRQHandler
PUBWEAK GPR_IRQ_IRQHandler
PUBWEAK LCDIF_IRQHandler
PUBWEAK CSI_IRQHandler
PUBWEAK PXP_IRQHandler
PUBWEAK WDOG2_IRQHandler
PUBWEAK SNVS_HP_WRAPPER_IRQHandler
PUBWEAK SNVS_HP_WRAPPER_TZ_IRQHandler
PUBWEAK SNVS_LP_WRAPPER_IRQHandler
PUBWEAK CSU_IRQHandler
PUBWEAK DCP_IRQHandler
PUBWEAK DCP_VMI_IRQHandler
PUBWEAK Reserved68_IRQHandler
PUBWEAK TRNG_IRQHandler
PUBWEAK SJC_IRQHandler
PUBWEAK BEE_IRQHandler
PUBWEAK SAI1_IRQHandler
PUBWEAK SAI1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI1_IRQHandler
LDR R0, =SAI1_DriverIRQHandler
BX R0
PUBWEAK SAI2_IRQHandler
PUBWEAK SAI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI2_IRQHandler
LDR R0, =SAI2_DriverIRQHandler
BX R0
PUBWEAK SAI3_RX_IRQHandler
PUBWEAK SAI3_RX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI3_RX_IRQHandler
LDR R0, =SAI3_RX_DriverIRQHandler
BX R0
PUBWEAK SAI3_TX_IRQHandler
PUBWEAK SAI3_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI3_TX_IRQHandler
LDR R0, =SAI3_TX_DriverIRQHandler
BX R0
PUBWEAK SPDIF_IRQHandler
PUBWEAK SPDIF_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPDIF_IRQHandler
LDR R0, =SPDIF_DriverIRQHandler
BX R0
PUBWEAK PMU_EVENT_IRQHandler
PUBWEAK Reserved78_IRQHandler
PUBWEAK TEMP_LOW_HIGH_IRQHandler
PUBWEAK TEMP_PANIC_IRQHandler
PUBWEAK USB_PHY1_IRQHandler
PUBWEAK USB_PHY2_IRQHandler
PUBWEAK ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
PUBWEAK DCDC_IRQHandler
PUBWEAK Reserved86_IRQHandler
PUBWEAK Reserved87_IRQHandler
PUBWEAK GPIO1_INT0_IRQHandler
PUBWEAK GPIO1_INT1_IRQHandler
PUBWEAK GPIO1_INT2_IRQHandler
PUBWEAK GPIO1_INT3_IRQHandler
PUBWEAK GPIO1_INT4_IRQHandler
PUBWEAK GPIO1_INT5_IRQHandler
PUBWEAK GPIO1_INT6_IRQHandler
PUBWEAK GPIO1_INT7_IRQHandler
PUBWEAK GPIO1_Combined_0_15_IRQHandler
PUBWEAK GPIO1_Combined_16_31_IRQHandler
PUBWEAK GPIO2_Combined_0_15_IRQHandler
PUBWEAK GPIO2_Combined_16_31_IRQHandler
PUBWEAK GPIO3_Combined_0_15_IRQHandler
PUBWEAK GPIO3_Combined_16_31_IRQHandler
PUBWEAK GPIO4_Combined_0_15_IRQHandler
PUBWEAK GPIO4_Combined_16_31_IRQHandler
PUBWEAK GPIO5_Combined_0_15_IRQHandler
PUBWEAK GPIO5_Combined_16_31_IRQHandler
PUBWEAK FLEXIO1_IRQHandler
PUBWEAK FLEXIO1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXIO1_IRQHandler
LDR R0, =FLEXIO1_DriverIRQHandler
BX R0
PUBWEAK FLEXIO2_IRQHandler
PUBWEAK FLEXIO2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXIO2_IRQHandler
LDR R0, =FLEXIO2_DriverIRQHandler
BX R0
PUBWEAK WDOG1_IRQHandler
PUBWEAK RTWDOG_IRQHandler
PUBWEAK EWM_IRQHandler
PUBWEAK CCM_1_IRQHandler
PUBWEAK CCM_2_IRQHandler
PUBWEAK GPC_IRQHandler
PUBWEAK SRC_IRQHandler
PUBWEAK Reserved115_IRQHandler
PUBWEAK GPT1_IRQHandler
PUBWEAK GPT2_IRQHandler
PUBWEAK PWM1_0_IRQHandler
PUBWEAK PWM1_1_IRQHandler
PUBWEAK PWM1_2_IRQHandler
PUBWEAK PWM1_3_IRQHandler
PUBWEAK PWM1_FAULT_IRQHandler
PUBWEAK FLEXSPI2_IRQHandler
PUBWEAK FLEXSPI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXSPI2_IRQHandler
LDR R0, =FLEXSPI2_DriverIRQHandler
BX R0
PUBWEAK FLEXSPI_IRQHandler
PUBWEAK FLEXSPI_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXSPI_IRQHandler
LDR R0, =FLEXSPI_DriverIRQHandler
BX R0
PUBWEAK SEMC_IRQHandler
PUBWEAK USDHC1_IRQHandler
PUBWEAK USDHC1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
USDHC1_IRQHandler
LDR R0, =USDHC1_DriverIRQHandler
BX R0
PUBWEAK USDHC2_IRQHandler
PUBWEAK USDHC2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
USDHC2_IRQHandler
LDR R0, =USDHC2_DriverIRQHandler
BX R0
PUBWEAK USB_OTG2_IRQHandler
PUBWEAK USB_OTG1_IRQHandler
PUBWEAK ENET_IRQHandler
PUBWEAK ENET_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_IRQHandler
LDR R0, =ENET_DriverIRQHandler
BX R0
PUBWEAK ENET_1588_Timer_IRQHandler
PUBWEAK ENET_1588_Timer_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_1588_Timer_IRQHandler
LDR R0, =ENET_1588_Timer_DriverIRQHandler
BX R0
PUBWEAK XBAR1_IRQ_0_1_IRQHandler
PUBWEAK XBAR1_IRQ_2_3_IRQHandler
PUBWEAK ADC_ETC_IRQ0_IRQHandler
PUBWEAK ADC_ETC_IRQ1_IRQHandler
PUBWEAK ADC_ETC_IRQ2_IRQHandler
PUBWEAK ADC_ETC_ERROR_IRQ_IRQHandler
PUBWEAK PIT_IRQHandler
PUBWEAK ACMP1_IRQHandler
PUBWEAK ACMP2_IRQHandler
PUBWEAK ACMP3_IRQHandler
PUBWEAK ACMP4_IRQHandler
PUBWEAK Reserved143_IRQHandler
PUBWEAK Reserved144_IRQHandler
PUBWEAK ENC1_IRQHandler
PUBWEAK ENC2_IRQHandler
PUBWEAK ENC3_IRQHandler
PUBWEAK ENC4_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
PUBWEAK PWM2_0_IRQHandler
PUBWEAK PWM2_1_IRQHandler
PUBWEAK PWM2_2_IRQHandler
PUBWEAK PWM2_3_IRQHandler
PUBWEAK PWM2_FAULT_IRQHandler
PUBWEAK PWM3_0_IRQHandler
PUBWEAK PWM3_1_IRQHandler
PUBWEAK PWM3_2_IRQHandler
PUBWEAK PWM3_3_IRQHandler
PUBWEAK PWM3_FAULT_IRQHandler
PUBWEAK PWM4_0_IRQHandler
PUBWEAK PWM4_1_IRQHandler
PUBWEAK PWM4_2_IRQHandler
PUBWEAK PWM4_3_IRQHandler
PUBWEAK PWM4_FAULT_IRQHandler
PUBWEAK ENET2_IRQHandler
PUBWEAK ENET2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET2_IRQHandler
LDR R0, =ENET2_DriverIRQHandler
BX R0
PUBWEAK ENET2_1588_Timer_IRQHandler
PUBWEAK ENET2_1588_Timer_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET2_1588_Timer_IRQHandler
LDR R0, =ENET2_1588_Timer_DriverIRQHandler
BX R0
PUBWEAK CAN3_IRQHandler
PUBWEAK CAN3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN3_IRQHandler
LDR R0, =CAN3_DriverIRQHandler
BX R0
PUBWEAK Reserved171_IRQHandler
PUBWEAK FLEXIO3_IRQHandler
PUBWEAK FLEXIO3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXIO3_IRQHandler
LDR R0, =FLEXIO3_DriverIRQHandler
BX R0
PUBWEAK GPIO6_7_8_9_IRQHandler
PUBWEAK DefaultISR
SECTION .text:CODE:REORDER:NOROOT(1)
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_ERROR_DriverIRQHandler
CTI0_ERROR_IRQHandler
CTI1_ERROR_IRQHandler
CORE_IRQHandler
LPUART1_DriverIRQHandler
LPUART2_DriverIRQHandler
LPUART3_DriverIRQHandler
LPUART4_DriverIRQHandler
LPUART5_DriverIRQHandler
LPUART6_DriverIRQHandler
LPUART7_DriverIRQHandler
LPUART8_DriverIRQHandler
LPI2C1_DriverIRQHandler
LPI2C2_DriverIRQHandler
LPI2C3_DriverIRQHandler
LPI2C4_DriverIRQHandler
LPSPI1_DriverIRQHandler
LPSPI2_DriverIRQHandler
LPSPI3_DriverIRQHandler
LPSPI4_DriverIRQHandler
CAN1_DriverIRQHandler
CAN2_DriverIRQHandler
FLEXRAM_IRQHandler
KPP_IRQHandler
TSC_DIG_IRQHandler
GPR_IRQ_IRQHandler
LCDIF_IRQHandler
CSI_IRQHandler
PXP_IRQHandler
WDOG2_IRQHandler
SNVS_HP_WRAPPER_IRQHandler
SNVS_HP_WRAPPER_TZ_IRQHandler
SNVS_LP_WRAPPER_IRQHandler
CSU_IRQHandler
DCP_IRQHandler
DCP_VMI_IRQHandler
Reserved68_IRQHandler
TRNG_IRQHandler
SJC_IRQHandler
BEE_IRQHandler
SAI1_DriverIRQHandler
SAI2_DriverIRQHandler
SAI3_RX_DriverIRQHandler
SAI3_TX_DriverIRQHandler
SPDIF_DriverIRQHandler
PMU_EVENT_IRQHandler
Reserved78_IRQHandler
TEMP_LOW_HIGH_IRQHandler
TEMP_PANIC_IRQHandler
USB_PHY1_IRQHandler
USB_PHY2_IRQHandler
ADC1_IRQHandler
ADC2_IRQHandler
DCDC_IRQHandler
Reserved86_IRQHandler
Reserved87_IRQHandler
GPIO1_INT0_IRQHandler
GPIO1_INT1_IRQHandler
GPIO1_INT2_IRQHandler
GPIO1_INT3_IRQHandler
GPIO1_INT4_IRQHandler
GPIO1_INT5_IRQHandler
GPIO1_INT6_IRQHandler
GPIO1_INT7_IRQHandler
GPIO1_Combined_0_15_IRQHandler
GPIO1_Combined_16_31_IRQHandler
GPIO2_Combined_0_15_IRQHandler
GPIO2_Combined_16_31_IRQHandler
GPIO3_Combined_0_15_IRQHandler
GPIO3_Combined_16_31_IRQHandler
GPIO4_Combined_0_15_IRQHandler
GPIO4_Combined_16_31_IRQHandler
GPIO5_Combined_0_15_IRQHandler
GPIO5_Combined_16_31_IRQHandler
FLEXIO1_DriverIRQHandler
FLEXIO2_DriverIRQHandler
WDOG1_IRQHandler
RTWDOG_IRQHandler
EWM_IRQHandler
CCM_1_IRQHandler
CCM_2_IRQHandler
GPC_IRQHandler
SRC_IRQHandler
Reserved115_IRQHandler
GPT1_IRQHandler
GPT2_IRQHandler
PWM1_0_IRQHandler
PWM1_1_IRQHandler
PWM1_2_IRQHandler
PWM1_3_IRQHandler
PWM1_FAULT_IRQHandler
FLEXSPI2_DriverIRQHandler
FLEXSPI_DriverIRQHandler
SEMC_IRQHandler
USDHC1_DriverIRQHandler
USDHC2_DriverIRQHandler
USB_OTG2_IRQHandler
USB_OTG1_IRQHandler
ENET_DriverIRQHandler
ENET_1588_Timer_DriverIRQHandler
XBAR1_IRQ_0_1_IRQHandler
XBAR1_IRQ_2_3_IRQHandler
ADC_ETC_IRQ0_IRQHandler
ADC_ETC_IRQ1_IRQHandler
ADC_ETC_IRQ2_IRQHandler
ADC_ETC_ERROR_IRQ_IRQHandler
PIT_IRQHandler
ACMP1_IRQHandler
ACMP2_IRQHandler
ACMP3_IRQHandler
ACMP4_IRQHandler
Reserved143_IRQHandler
Reserved144_IRQHandler
ENC1_IRQHandler
ENC2_IRQHandler
ENC3_IRQHandler
ENC4_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
PWM2_0_IRQHandler
PWM2_1_IRQHandler
PWM2_2_IRQHandler
PWM2_3_IRQHandler
PWM2_FAULT_IRQHandler
PWM3_0_IRQHandler
PWM3_1_IRQHandler
PWM3_2_IRQHandler
PWM3_3_IRQHandler
PWM3_FAULT_IRQHandler
PWM4_0_IRQHandler
PWM4_1_IRQHandler
PWM4_2_IRQHandler
PWM4_3_IRQHandler
PWM4_FAULT_IRQHandler
ENET2_DriverIRQHandler
ENET2_1588_Timer_DriverIRQHandler
CAN3_DriverIRQHandler
Reserved171_IRQHandler
FLEXIO3_DriverIRQHandler
GPIO6_7_8_9_IRQHandler
DefaultISR
B DefaultISR
END
|
nxp-mcuxpresso/OpenART | 54,491 | bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/arm/startup_MIMXRT1176_cm4.S | /* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1176_cm4.s */
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
/* MIMXRT1176_cm4 */
/* @version: 0.1 */
/* @date: 2018-3-5 */
/* @build: b200610 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2020 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
.section .isr_vector, "a"
.align 2
.globl __Vectors
__Vectors:
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/
.long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/
.long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/
.long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/
.long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/
.long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/
.long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/
.long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/
.long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/
.long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/
.long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/
.long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/
.long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/
.long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/
.long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/
.long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/
.long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/
.long Reserved33_IRQHandler /* Reserved interrupt*/
.long Reserved34_IRQHandler /* Reserved interrupt*/
.long CORE_IRQHandler /* CorePlatform exception IRQ*/
.long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/
.long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/
.long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/
.long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/
.long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/
.long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/
.long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/
.long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/
.long LPUART9_IRQHandler /* LPUART9 TX interrupt and RX interrupt*/
.long LPUART10_IRQHandler /* LPUART10 TX interrupt and RX interrupt*/
.long LPUART11_IRQHandler /* LPUART11 TX interrupt and RX interrupt*/
.long LPUART12_IRQHandler /* LPUART12 TX interrupt and RX interrupt*/
.long LPI2C1_IRQHandler /* LPI2C1 interrupt*/
.long LPI2C2_IRQHandler /* LPI2C2 interrupt*/
.long LPI2C3_IRQHandler /* LPI2C3 interrupt*/
.long LPI2C4_IRQHandler /* LPI2C4 interrupt*/
.long LPI2C5_IRQHandler /* LPI2C5 interrupt*/
.long LPI2C6_IRQHandler /* LPI2C6 interrupt*/
.long LPSPI1_IRQHandler /* LPSPI1 interrupt request line to the core*/
.long LPSPI2_IRQHandler /* LPSPI2 interrupt request line to the core*/
.long LPSPI3_IRQHandler /* LPSPI3 interrupt request line to the core*/
.long LPSPI4_IRQHandler /* LPSPI4 interrupt request line to the core*/
.long LPSPI5_IRQHandler /* LPSPI5 interrupt request line to the core*/
.long LPSPI6_IRQHandler /* LPSPI6 interrupt request line to the core*/
.long CAN1_IRQHandler /* CAN1 interrupt*/
.long CAN1_ERROR_IRQHandler /* CAN1 error interrupt*/
.long CAN2_IRQHandler /* CAN2 interrupt*/
.long CAN2_ERROR_IRQHandler /* CAN2 error interrupt*/
.long CAN3_IRQHandler /* CAN3 interrupt*/
.long CAN3_ERROR_IRQHandler /* CAN3 erro interrupt*/
.long Reserved66_IRQHandler /* Reserved interrupt*/
.long KPP_IRQHandler /* Keypad nterrupt*/
.long Reserved68_IRQHandler /* Reserved interrupt*/
.long GPR_IRQ_IRQHandler /* GPR interrupt*/
.long LCDIF1_IRQHandler /* LCDIF1 interrupt*/
.long LCDIF2_IRQHandler /* LCDIF2 interrupt*/
.long CSI_IRQHandler /* CSI interrupt*/
.long PXP_IRQHandler /* PXP interrupt*/
.long MIPI_CSI_IRQHandler /* MIPI_CSI interrupt*/
.long MIPI_DSI_IRQHandler /* MIPI_DSI interrupt*/
.long GPU2D_IRQHandler /* GPU2D interrupt*/
.long GPIO12_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO12 signal 0 throughout 15*/
.long GPIO12_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO13 signal 16 throughout 31*/
.long DAC_IRQHandler /* DAC interrupt*/
.long KEY_MANAGER_IRQHandler /* PUF interrupt*/
.long WDOG2_IRQHandler /* WDOG2 interrupt*/
.long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/
.long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/
.long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/
.long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ0*/
.long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ1*/
.long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ2*/
.long CAAM_IRQ3_IRQHandler /* CAAM interrupt queue for JQ3*/
.long CAAM_RECORVE_ERRPR_IRQHandler /* CAAM interrupt for recoverable error*/
.long CAAM_RTC_IRQHandler /* CAAM interrupt for RTC*/
.long Reserved91_IRQHandler /* Reserved interrupt*/
.long SAI1_IRQHandler /* SAI1 interrupt*/
.long SAI2_IRQHandler /* SAI1 interrupt*/
.long SAI3_RX_IRQHandler /* SAI3 interrupt*/
.long SAI3_TX_IRQHandler /* SAI3 interrupt*/
.long SAI4_RX_IRQHandler /* SAI4 interrupt*/
.long SAI4_TX_IRQHandler /* SAI4 interrupt*/
.long SPDIF_IRQHandler /* SPDIF interrupt*/
.long ANATOP_TEMP_INT_IRQHandler /* ANATOP interrupt*/
.long ANATOP_TEMP_LOW_HIGH_IRQHandler /* ANATOP interrupt*/
.long ANATOP_TEMP_PANIC_IRQHandler /* ANATOP interrupt*/
.long ANATOP_LP8_BROWNOUT_IRQHandler /* ANATOP interrupt*/
.long ANATOP_LP0_BROWNOUT_IRQHandler /* ANATOP interrupt*/
.long ADC1_IRQHandler /* ADC1 interrupt*/
.long ADC2_IRQHandler /* ADC2 interrupt*/
.long USBPHY1_IRQHandler /* USBPHY1 interrupt*/
.long USBPHY2_IRQHandler /* USBPHY2 interrupt*/
.long RDC_IRQHandler /* RDC interrupt*/
.long GPIO13_Combined_0_31_IRQHandler /* Combined interrupt indication for GPIO13 signal 0 throughout 31*/
.long SFA_IRQHandler /* SFA interrupt*/
.long DCIC1_IRQHandler /* DCIC1 interrupt*/
.long DCIC2_IRQHandler /* DCIC2 interrupt*/
.long ASRC_IRQHandler /* ASRC interrupt*/
.long FLEXRAM_ECC_IRQHandler /* FlexRAM ECC fatal interrupt*/
.long GPIO7_8_9_10_11_IRQHandler /* GPIO7, GPIO8, GPIO9, GPIO10, GPIO11 interrupt*/
.long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
.long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
.long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
.long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
.long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
.long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
.long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
.long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
.long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
.long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
.long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/
.long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/
.long WDOG1_IRQHandler /* WDOG1 interrupt*/
.long RTWDOG4_IRQHandler /* RTWDOG4 interrupt*/
.long EWM_IRQHandler /* EWM interrupt*/
.long OCOTP_READ_FUSE_ERROR_IRQHandler /* OCOTP read fuse error interrupt*/
.long OCOTP_READ_DONE_ERROR_IRQHandler /* OCOTP read fuse done interrupt*/
.long GPC_IRQHandler /* GPC interrupt*/
.long MUB_IRQHandler /* MUB interrupt*/
.long GPT1_IRQHandler /* GPT1 interrupt*/
.long GPT2_IRQHandler /* GPT2 interrupt*/
.long GPT3_IRQHandler /* GPT3 interrupt*/
.long GPT4_IRQHandler /* GPT4 interrupt*/
.long GPT5_IRQHandler /* GPT5 interrupt*/
.long GPT6_IRQHandler /* GPT6 interrupt*/
.long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/
.long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/
.long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/
.long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/
.long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/
.long FLEXSPI1_IRQHandler /* FlexSPI1 interrupt*/
.long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/
.long SEMC_IRQHandler /* SEMC interrupt*/
.long USDHC1_IRQHandler /* USDHC1 interrupt*/
.long USDHC2_IRQHandler /* USDHC2 interrupt*/
.long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/
.long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/
.long ENET_IRQHandler /* ENET interrupt*/
.long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/
.long ENET_MAC0_Tx_Rx_Done_0_IRQHandler /* ENET 1G MAC0 transmit/receive done 0*/
.long ENET_MAC0_Tx_Rx_Done_1_IRQHandler /* ENET 1G MAC0 transmit/receive done 1*/
.long ENET_1G_IRQHandler /* ENET 1G interrupt*/
.long ENET_1G_1588_Timer_IRQHandler /* ENET_1G_1588_Timer interrupt*/
.long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/
.long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/
.long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/
.long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/
.long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/
.long ADC_ETC_IRQ3_IRQHandler /* ADCETC IRQ3 interrupt*/
.long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/
.long Reserved166_IRQHandler /* Reserved interrupt*/
.long Reserved167_IRQHandler /* Reserved interrupt*/
.long Reserved168_IRQHandler /* Reserved interrupt*/
.long Reserved169_IRQHandler /* Reserved interrupt*/
.long Reserved170_IRQHandler /* Reserved interrupt*/
.long PIT1_IRQHandler /* PIT1 interrupt*/
.long PIT2_IRQHandler /* PIT2 interrupt*/
.long ACMP1_IRQHandler /* ACMP interrupt*/
.long ACMP2_IRQHandler /* ACMP interrupt*/
.long ACMP3_IRQHandler /* ACMP interrupt*/
.long ACMP4_IRQHandler /* ACMP interrupt*/
.long Reserved177_IRQHandler /* Reserved interrupt*/
.long Reserved178_IRQHandler /* Reserved interrupt*/
.long Reserved179_IRQHandler /* Reserved interrupt*/
.long Reserved180_IRQHandler /* Reserved interrupt*/
.long ENC1_IRQHandler /* ENC1 interrupt*/
.long ENC2_IRQHandler /* ENC2 interrupt*/
.long ENC3_IRQHandler /* ENC3 interrupt*/
.long ENC4_IRQHandler /* ENC4 interrupt*/
.long Reserved185_IRQHandler /* Reserved interrupt*/
.long Reserved186_IRQHandler /* Reserved interrupt*/
.long TMR1_IRQHandler /* TMR1 interrupt*/
.long TMR2_IRQHandler /* TMR2 interrupt*/
.long TMR3_IRQHandler /* TMR3 interrupt*/
.long TMR4_IRQHandler /* TMR4 interrupt*/
.long SEMA4_CP0_IRQHandler /* SEMA4 CP0 interrupt*/
.long SEMA4_CP1_IRQHandler /* SEMA4 CP1 interrupt*/
.long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/
.long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/
.long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/
.long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/
.long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/
.long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/
.long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/
.long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/
.long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/
.long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/
.long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/
.long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/
.long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
.long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
.long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/
.long Reserved208_IRQHandler /* Reserved interrupt*/
.long Reserved209_IRQHandler /* Reserved interrupt*/
.long Reserved210_IRQHandler /* Reserved interrupt*/
.long Reserved211_IRQHandler /* Reserved interrupt*/
.long Reserved212_IRQHandler /* Reserved interrupt*/
.long Reserved213_IRQHandler /* Reserved interrupt*/
.long Reserved214_IRQHandler /* Reserved interrupt*/
.long Reserved215_IRQHandler /* Reserved interrupt*/
.long Reserved216_IRQHandler /* Reserved interrupt*/
.long Reserved217_IRQHandler /* Reserved interrupt*/
.long PDM_EVENT_IRQHandler /* PDM event interrupt*/
.long PDM_ERROR_IRQHandler /* PDM error interrupt*/
.long EMVSIM1_IRQHandler /* EMVSIM1 interrupt*/
.long EMVSIM2_IRQHandler /* EMVSIM2 interrupt*/
.long MECC1_INIT_IRQHandler /* MECC1 init*/
.long MECC1_FATAL_INIT_IRQHandler /* MECC1 fatal init*/
.long MECC2_INIT_IRQHandler /* MECC2 init*/
.long MECC2_FATAL_INIT_IRQHandler /* MECC2 fatal init*/
.long XECC_FLEXSPI1_INIT_IRQHandler /* XECC init*/
.long XECC_FLEXSPI1_FATAL_INIT_IRQHandler /* XECC fatal init*/
.long XECC_FLEXSPI2_INIT_IRQHandler /* XECC init*/
.long XECC_FLEXSPI2_FATAL_INIT_IRQHandler /* XECC fatal init*/
.long XECC_SEMC_INIT_IRQHandler /* XECC init*/
.long XECC_SEMC_FATAL_INIT_IRQHandler /* XECC fatal init*/
.long ENET_QOS_IRQHandler /* ENET_QOS interrupt*/
.long ENET_QOS_PMT_IRQHandler /* ENET_QOS_PMT interrupt*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.long DefaultISR /* 240*/
.long DefaultISR /* 241*/
.long DefaultISR /* 242*/
.long DefaultISR /* 243*/
.long DefaultISR /* 244*/
.long DefaultISR /* 245*/
.long DefaultISR /* 246*/
.long DefaultISR /* 247*/
.long DefaultISR /* 248*/
.long DefaultISR /* 249*/
.long DefaultISR /* 250*/
.long DefaultISR /* 251*/
.long DefaultISR /* 252*/
.long DefaultISR /* 253*/
.long DefaultISR /* 254*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __Vectors, . - __Vectors
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__Vectors
str r1, [r0]
ldr r2, [r1]
msr msp, r2
ldr r0,=SystemInit
blx r0
cpsie i /* Unmask interrupts */
ldr r0,=__main
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak DMA0_DMA16_IRQHandler
.type DMA0_DMA16_IRQHandler, %function
DMA0_DMA16_IRQHandler:
ldr r0,=DMA0_DMA16_DriverIRQHandler
bx r0
.size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
.align 1
.thumb_func
.weak DMA1_DMA17_IRQHandler
.type DMA1_DMA17_IRQHandler, %function
DMA1_DMA17_IRQHandler:
ldr r0,=DMA1_DMA17_DriverIRQHandler
bx r0
.size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
.align 1
.thumb_func
.weak DMA2_DMA18_IRQHandler
.type DMA2_DMA18_IRQHandler, %function
DMA2_DMA18_IRQHandler:
ldr r0,=DMA2_DMA18_DriverIRQHandler
bx r0
.size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
.align 1
.thumb_func
.weak DMA3_DMA19_IRQHandler
.type DMA3_DMA19_IRQHandler, %function
DMA3_DMA19_IRQHandler:
ldr r0,=DMA3_DMA19_DriverIRQHandler
bx r0
.size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
.align 1
.thumb_func
.weak DMA4_DMA20_IRQHandler
.type DMA4_DMA20_IRQHandler, %function
DMA4_DMA20_IRQHandler:
ldr r0,=DMA4_DMA20_DriverIRQHandler
bx r0
.size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
.align 1
.thumb_func
.weak DMA5_DMA21_IRQHandler
.type DMA5_DMA21_IRQHandler, %function
DMA5_DMA21_IRQHandler:
ldr r0,=DMA5_DMA21_DriverIRQHandler
bx r0
.size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
.align 1
.thumb_func
.weak DMA6_DMA22_IRQHandler
.type DMA6_DMA22_IRQHandler, %function
DMA6_DMA22_IRQHandler:
ldr r0,=DMA6_DMA22_DriverIRQHandler
bx r0
.size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
.align 1
.thumb_func
.weak DMA7_DMA23_IRQHandler
.type DMA7_DMA23_IRQHandler, %function
DMA7_DMA23_IRQHandler:
ldr r0,=DMA7_DMA23_DriverIRQHandler
bx r0
.size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
.align 1
.thumb_func
.weak DMA8_DMA24_IRQHandler
.type DMA8_DMA24_IRQHandler, %function
DMA8_DMA24_IRQHandler:
ldr r0,=DMA8_DMA24_DriverIRQHandler
bx r0
.size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
.align 1
.thumb_func
.weak DMA9_DMA25_IRQHandler
.type DMA9_DMA25_IRQHandler, %function
DMA9_DMA25_IRQHandler:
ldr r0,=DMA9_DMA25_DriverIRQHandler
bx r0
.size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
.align 1
.thumb_func
.weak DMA10_DMA26_IRQHandler
.type DMA10_DMA26_IRQHandler, %function
DMA10_DMA26_IRQHandler:
ldr r0,=DMA10_DMA26_DriverIRQHandler
bx r0
.size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
.align 1
.thumb_func
.weak DMA11_DMA27_IRQHandler
.type DMA11_DMA27_IRQHandler, %function
DMA11_DMA27_IRQHandler:
ldr r0,=DMA11_DMA27_DriverIRQHandler
bx r0
.size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
.align 1
.thumb_func
.weak DMA12_DMA28_IRQHandler
.type DMA12_DMA28_IRQHandler, %function
DMA12_DMA28_IRQHandler:
ldr r0,=DMA12_DMA28_DriverIRQHandler
bx r0
.size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
.align 1
.thumb_func
.weak DMA13_DMA29_IRQHandler
.type DMA13_DMA29_IRQHandler, %function
DMA13_DMA29_IRQHandler:
ldr r0,=DMA13_DMA29_DriverIRQHandler
bx r0
.size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
.align 1
.thumb_func
.weak DMA14_DMA30_IRQHandler
.type DMA14_DMA30_IRQHandler, %function
DMA14_DMA30_IRQHandler:
ldr r0,=DMA14_DMA30_DriverIRQHandler
bx r0
.size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
.align 1
.thumb_func
.weak DMA15_DMA31_IRQHandler
.type DMA15_DMA31_IRQHandler, %function
DMA15_DMA31_IRQHandler:
ldr r0,=DMA15_DMA31_DriverIRQHandler
bx r0
.size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
.align 1
.thumb_func
.weak DMA_ERROR_IRQHandler
.type DMA_ERROR_IRQHandler, %function
DMA_ERROR_IRQHandler:
ldr r0,=DMA_ERROR_DriverIRQHandler
bx r0
.size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler
.align 1
.thumb_func
.weak LPUART1_IRQHandler
.type LPUART1_IRQHandler, %function
LPUART1_IRQHandler:
ldr r0,=LPUART1_DriverIRQHandler
bx r0
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
.align 1
.thumb_func
.weak LPUART2_IRQHandler
.type LPUART2_IRQHandler, %function
LPUART2_IRQHandler:
ldr r0,=LPUART2_DriverIRQHandler
bx r0
.size LPUART2_IRQHandler, . - LPUART2_IRQHandler
.align 1
.thumb_func
.weak LPUART3_IRQHandler
.type LPUART3_IRQHandler, %function
LPUART3_IRQHandler:
ldr r0,=LPUART3_DriverIRQHandler
bx r0
.size LPUART3_IRQHandler, . - LPUART3_IRQHandler
.align 1
.thumb_func
.weak LPUART4_IRQHandler
.type LPUART4_IRQHandler, %function
LPUART4_IRQHandler:
ldr r0,=LPUART4_DriverIRQHandler
bx r0
.size LPUART4_IRQHandler, . - LPUART4_IRQHandler
.align 1
.thumb_func
.weak LPUART5_IRQHandler
.type LPUART5_IRQHandler, %function
LPUART5_IRQHandler:
ldr r0,=LPUART5_DriverIRQHandler
bx r0
.size LPUART5_IRQHandler, . - LPUART5_IRQHandler
.align 1
.thumb_func
.weak LPUART6_IRQHandler
.type LPUART6_IRQHandler, %function
LPUART6_IRQHandler:
ldr r0,=LPUART6_DriverIRQHandler
bx r0
.size LPUART6_IRQHandler, . - LPUART6_IRQHandler
.align 1
.thumb_func
.weak LPUART7_IRQHandler
.type LPUART7_IRQHandler, %function
LPUART7_IRQHandler:
ldr r0,=LPUART7_DriverIRQHandler
bx r0
.size LPUART7_IRQHandler, . - LPUART7_IRQHandler
.align 1
.thumb_func
.weak LPUART8_IRQHandler
.type LPUART8_IRQHandler, %function
LPUART8_IRQHandler:
ldr r0,=LPUART8_DriverIRQHandler
bx r0
.size LPUART8_IRQHandler, . - LPUART8_IRQHandler
.align 1
.thumb_func
.weak LPUART9_IRQHandler
.type LPUART9_IRQHandler, %function
LPUART9_IRQHandler:
ldr r0,=LPUART9_DriverIRQHandler
bx r0
.size LPUART9_IRQHandler, . - LPUART9_IRQHandler
.align 1
.thumb_func
.weak LPUART10_IRQHandler
.type LPUART10_IRQHandler, %function
LPUART10_IRQHandler:
ldr r0,=LPUART10_DriverIRQHandler
bx r0
.size LPUART10_IRQHandler, . - LPUART10_IRQHandler
.align 1
.thumb_func
.weak LPUART11_IRQHandler
.type LPUART11_IRQHandler, %function
LPUART11_IRQHandler:
ldr r0,=LPUART11_DriverIRQHandler
bx r0
.size LPUART11_IRQHandler, . - LPUART11_IRQHandler
.align 1
.thumb_func
.weak LPUART12_IRQHandler
.type LPUART12_IRQHandler, %function
LPUART12_IRQHandler:
ldr r0,=LPUART12_DriverIRQHandler
bx r0
.size LPUART12_IRQHandler, . - LPUART12_IRQHandler
.align 1
.thumb_func
.weak LPI2C1_IRQHandler
.type LPI2C1_IRQHandler, %function
LPI2C1_IRQHandler:
ldr r0,=LPI2C1_DriverIRQHandler
bx r0
.size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler
.align 1
.thumb_func
.weak LPI2C2_IRQHandler
.type LPI2C2_IRQHandler, %function
LPI2C2_IRQHandler:
ldr r0,=LPI2C2_DriverIRQHandler
bx r0
.size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler
.align 1
.thumb_func
.weak LPI2C3_IRQHandler
.type LPI2C3_IRQHandler, %function
LPI2C3_IRQHandler:
ldr r0,=LPI2C3_DriverIRQHandler
bx r0
.size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler
.align 1
.thumb_func
.weak LPI2C4_IRQHandler
.type LPI2C4_IRQHandler, %function
LPI2C4_IRQHandler:
ldr r0,=LPI2C4_DriverIRQHandler
bx r0
.size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler
.align 1
.thumb_func
.weak LPI2C5_IRQHandler
.type LPI2C5_IRQHandler, %function
LPI2C5_IRQHandler:
ldr r0,=LPI2C5_DriverIRQHandler
bx r0
.size LPI2C5_IRQHandler, . - LPI2C5_IRQHandler
.align 1
.thumb_func
.weak LPI2C6_IRQHandler
.type LPI2C6_IRQHandler, %function
LPI2C6_IRQHandler:
ldr r0,=LPI2C6_DriverIRQHandler
bx r0
.size LPI2C6_IRQHandler, . - LPI2C6_IRQHandler
.align 1
.thumb_func
.weak LPSPI1_IRQHandler
.type LPSPI1_IRQHandler, %function
LPSPI1_IRQHandler:
ldr r0,=LPSPI1_DriverIRQHandler
bx r0
.size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler
.align 1
.thumb_func
.weak LPSPI2_IRQHandler
.type LPSPI2_IRQHandler, %function
LPSPI2_IRQHandler:
ldr r0,=LPSPI2_DriverIRQHandler
bx r0
.size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler
.align 1
.thumb_func
.weak LPSPI3_IRQHandler
.type LPSPI3_IRQHandler, %function
LPSPI3_IRQHandler:
ldr r0,=LPSPI3_DriverIRQHandler
bx r0
.size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler
.align 1
.thumb_func
.weak LPSPI4_IRQHandler
.type LPSPI4_IRQHandler, %function
LPSPI4_IRQHandler:
ldr r0,=LPSPI4_DriverIRQHandler
bx r0
.size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler
.align 1
.thumb_func
.weak LPSPI5_IRQHandler
.type LPSPI5_IRQHandler, %function
LPSPI5_IRQHandler:
ldr r0,=LPSPI5_DriverIRQHandler
bx r0
.size LPSPI5_IRQHandler, . - LPSPI5_IRQHandler
.align 1
.thumb_func
.weak LPSPI6_IRQHandler
.type LPSPI6_IRQHandler, %function
LPSPI6_IRQHandler:
ldr r0,=LPSPI6_DriverIRQHandler
bx r0
.size LPSPI6_IRQHandler, . - LPSPI6_IRQHandler
.align 1
.thumb_func
.weak CAN1_IRQHandler
.type CAN1_IRQHandler, %function
CAN1_IRQHandler:
ldr r0,=CAN1_DriverIRQHandler
bx r0
.size CAN1_IRQHandler, . - CAN1_IRQHandler
.align 1
.thumb_func
.weak CAN1_ERROR_IRQHandler
.type CAN1_ERROR_IRQHandler, %function
CAN1_ERROR_IRQHandler:
ldr r0,=CAN1_ERROR_DriverIRQHandler
bx r0
.size CAN1_ERROR_IRQHandler, . - CAN1_ERROR_IRQHandler
.align 1
.thumb_func
.weak CAN2_IRQHandler
.type CAN2_IRQHandler, %function
CAN2_IRQHandler:
ldr r0,=CAN2_DriverIRQHandler
bx r0
.size CAN2_IRQHandler, . - CAN2_IRQHandler
.align 1
.thumb_func
.weak CAN2_ERROR_IRQHandler
.type CAN2_ERROR_IRQHandler, %function
CAN2_ERROR_IRQHandler:
ldr r0,=CAN2_ERROR_DriverIRQHandler
bx r0
.size CAN2_ERROR_IRQHandler, . - CAN2_ERROR_IRQHandler
.align 1
.thumb_func
.weak CAN3_IRQHandler
.type CAN3_IRQHandler, %function
CAN3_IRQHandler:
ldr r0,=CAN3_DriverIRQHandler
bx r0
.size CAN3_IRQHandler, . - CAN3_IRQHandler
.align 1
.thumb_func
.weak CAN3_ERROR_IRQHandler
.type CAN3_ERROR_IRQHandler, %function
CAN3_ERROR_IRQHandler:
ldr r0,=CAN3_ERROR_DriverIRQHandler
bx r0
.size CAN3_ERROR_IRQHandler, . - CAN3_ERROR_IRQHandler
.align 1
.thumb_func
.weak SAI1_IRQHandler
.type SAI1_IRQHandler, %function
SAI1_IRQHandler:
ldr r0,=SAI1_DriverIRQHandler
bx r0
.size SAI1_IRQHandler, . - SAI1_IRQHandler
.align 1
.thumb_func
.weak SAI2_IRQHandler
.type SAI2_IRQHandler, %function
SAI2_IRQHandler:
ldr r0,=SAI2_DriverIRQHandler
bx r0
.size SAI2_IRQHandler, . - SAI2_IRQHandler
.align 1
.thumb_func
.weak SAI3_RX_IRQHandler
.type SAI3_RX_IRQHandler, %function
SAI3_RX_IRQHandler:
ldr r0,=SAI3_RX_DriverIRQHandler
bx r0
.size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler
.align 1
.thumb_func
.weak SAI3_TX_IRQHandler
.type SAI3_TX_IRQHandler, %function
SAI3_TX_IRQHandler:
ldr r0,=SAI3_TX_DriverIRQHandler
bx r0
.size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler
.align 1
.thumb_func
.weak SAI4_RX_IRQHandler
.type SAI4_RX_IRQHandler, %function
SAI4_RX_IRQHandler:
ldr r0,=SAI4_RX_DriverIRQHandler
bx r0
.size SAI4_RX_IRQHandler, . - SAI4_RX_IRQHandler
.align 1
.thumb_func
.weak SAI4_TX_IRQHandler
.type SAI4_TX_IRQHandler, %function
SAI4_TX_IRQHandler:
ldr r0,=SAI4_TX_DriverIRQHandler
bx r0
.size SAI4_TX_IRQHandler, . - SAI4_TX_IRQHandler
.align 1
.thumb_func
.weak SPDIF_IRQHandler
.type SPDIF_IRQHandler, %function
SPDIF_IRQHandler:
ldr r0,=SPDIF_DriverIRQHandler
bx r0
.size SPDIF_IRQHandler, . - SPDIF_IRQHandler
.align 1
.thumb_func
.weak ASRC_IRQHandler
.type ASRC_IRQHandler, %function
ASRC_IRQHandler:
ldr r0,=ASRC_DriverIRQHandler
bx r0
.size ASRC_IRQHandler, . - ASRC_IRQHandler
.align 1
.thumb_func
.weak FLEXIO1_IRQHandler
.type FLEXIO1_IRQHandler, %function
FLEXIO1_IRQHandler:
ldr r0,=FLEXIO1_DriverIRQHandler
bx r0
.size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler
.align 1
.thumb_func
.weak FLEXIO2_IRQHandler
.type FLEXIO2_IRQHandler, %function
FLEXIO2_IRQHandler:
ldr r0,=FLEXIO2_DriverIRQHandler
bx r0
.size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler
.align 1
.thumb_func
.weak FLEXSPI1_IRQHandler
.type FLEXSPI1_IRQHandler, %function
FLEXSPI1_IRQHandler:
ldr r0,=FLEXSPI1_DriverIRQHandler
bx r0
.size FLEXSPI1_IRQHandler, . - FLEXSPI1_IRQHandler
.align 1
.thumb_func
.weak FLEXSPI2_IRQHandler
.type FLEXSPI2_IRQHandler, %function
FLEXSPI2_IRQHandler:
ldr r0,=FLEXSPI2_DriverIRQHandler
bx r0
.size FLEXSPI2_IRQHandler, . - FLEXSPI2_IRQHandler
.align 1
.thumb_func
.weak USDHC1_IRQHandler
.type USDHC1_IRQHandler, %function
USDHC1_IRQHandler:
ldr r0,=USDHC1_DriverIRQHandler
bx r0
.size USDHC1_IRQHandler, . - USDHC1_IRQHandler
.align 1
.thumb_func
.weak USDHC2_IRQHandler
.type USDHC2_IRQHandler, %function
USDHC2_IRQHandler:
ldr r0,=USDHC2_DriverIRQHandler
bx r0
.size USDHC2_IRQHandler, . - USDHC2_IRQHandler
.align 1
.thumb_func
.weak ENET_IRQHandler
.type ENET_IRQHandler, %function
ENET_IRQHandler:
ldr r0,=ENET_DriverIRQHandler
bx r0
.size ENET_IRQHandler, . - ENET_IRQHandler
.align 1
.thumb_func
.weak ENET_1588_Timer_IRQHandler
.type ENET_1588_Timer_IRQHandler, %function
ENET_1588_Timer_IRQHandler:
ldr r0,=ENET_1588_Timer_DriverIRQHandler
bx r0
.size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler
.align 1
.thumb_func
.weak ENET_MAC0_Tx_Rx_Done_0_IRQHandler
.type ENET_MAC0_Tx_Rx_Done_0_IRQHandler, %function
ENET_MAC0_Tx_Rx_Done_0_IRQHandler:
ldr r0,=ENET_MAC0_Tx_Rx_Done_0_DriverIRQHandler
bx r0
.size ENET_MAC0_Tx_Rx_Done_0_IRQHandler, . - ENET_MAC0_Tx_Rx_Done_0_IRQHandler
.align 1
.thumb_func
.weak ENET_MAC0_Tx_Rx_Done_1_IRQHandler
.type ENET_MAC0_Tx_Rx_Done_1_IRQHandler, %function
ENET_MAC0_Tx_Rx_Done_1_IRQHandler:
ldr r0,=ENET_MAC0_Tx_Rx_Done_1_DriverIRQHandler
bx r0
.size ENET_MAC0_Tx_Rx_Done_1_IRQHandler, . - ENET_MAC0_Tx_Rx_Done_1_IRQHandler
.align 1
.thumb_func
.weak ENET_1G_IRQHandler
.type ENET_1G_IRQHandler, %function
ENET_1G_IRQHandler:
ldr r0,=ENET_1G_DriverIRQHandler
bx r0
.size ENET_1G_IRQHandler, . - ENET_1G_IRQHandler
.align 1
.thumb_func
.weak ENET_1G_1588_Timer_IRQHandler
.type ENET_1G_1588_Timer_IRQHandler, %function
ENET_1G_1588_Timer_IRQHandler:
ldr r0,=ENET_1G_1588_Timer_DriverIRQHandler
bx r0
.size ENET_1G_1588_Timer_IRQHandler, . - ENET_1G_1588_Timer_IRQHandler
.align 1
.thumb_func
.weak PDM_EVENT_IRQHandler
.type PDM_EVENT_IRQHandler, %function
PDM_EVENT_IRQHandler:
ldr r0,=PDM_EVENT_DriverIRQHandler
bx r0
.size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler
.align 1
.thumb_func
.weak PDM_ERROR_IRQHandler
.type PDM_ERROR_IRQHandler, %function
PDM_ERROR_IRQHandler:
ldr r0,=PDM_ERROR_DriverIRQHandler
bx r0
.size PDM_ERROR_IRQHandler, . - PDM_ERROR_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI1_INIT_IRQHandler
.type XECC_FLEXSPI1_INIT_IRQHandler, %function
XECC_FLEXSPI1_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI1_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI1_INIT_IRQHandler, . - XECC_FLEXSPI1_INIT_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI1_FATAL_INIT_IRQHandler
.type XECC_FLEXSPI1_FATAL_INIT_IRQHandler, %function
XECC_FLEXSPI1_FATAL_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI1_FATAL_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI1_FATAL_INIT_IRQHandler, . - XECC_FLEXSPI1_FATAL_INIT_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI2_INIT_IRQHandler
.type XECC_FLEXSPI2_INIT_IRQHandler, %function
XECC_FLEXSPI2_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI2_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI2_INIT_IRQHandler, . - XECC_FLEXSPI2_INIT_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI2_FATAL_INIT_IRQHandler
.type XECC_FLEXSPI2_FATAL_INIT_IRQHandler, %function
XECC_FLEXSPI2_FATAL_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI2_FATAL_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI2_FATAL_INIT_IRQHandler, . - XECC_FLEXSPI2_FATAL_INIT_IRQHandler
.align 1
.thumb_func
.weak ENET_QOS_IRQHandler
.type ENET_QOS_IRQHandler, %function
ENET_QOS_IRQHandler:
ldr r0,=ENET_QOS_DriverIRQHandler
bx r0
.size ENET_QOS_IRQHandler, . - ENET_QOS_IRQHandler
.align 1
.thumb_func
.weak ENET_QOS_PMT_IRQHandler
.type ENET_QOS_PMT_IRQHandler, %function
ENET_QOS_PMT_IRQHandler:
ldr r0,=ENET_QOS_PMT_DriverIRQHandler
bx r0
.size ENET_QOS_PMT_IRQHandler, . - ENET_QOS_PMT_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler DMA0_DMA16_DriverIRQHandler
def_irq_handler DMA1_DMA17_DriverIRQHandler
def_irq_handler DMA2_DMA18_DriverIRQHandler
def_irq_handler DMA3_DMA19_DriverIRQHandler
def_irq_handler DMA4_DMA20_DriverIRQHandler
def_irq_handler DMA5_DMA21_DriverIRQHandler
def_irq_handler DMA6_DMA22_DriverIRQHandler
def_irq_handler DMA7_DMA23_DriverIRQHandler
def_irq_handler DMA8_DMA24_DriverIRQHandler
def_irq_handler DMA9_DMA25_DriverIRQHandler
def_irq_handler DMA10_DMA26_DriverIRQHandler
def_irq_handler DMA11_DMA27_DriverIRQHandler
def_irq_handler DMA12_DMA28_DriverIRQHandler
def_irq_handler DMA13_DMA29_DriverIRQHandler
def_irq_handler DMA14_DMA30_DriverIRQHandler
def_irq_handler DMA15_DMA31_DriverIRQHandler
def_irq_handler DMA_ERROR_DriverIRQHandler
def_irq_handler Reserved33_IRQHandler
def_irq_handler Reserved34_IRQHandler
def_irq_handler CORE_IRQHandler
def_irq_handler LPUART1_DriverIRQHandler
def_irq_handler LPUART2_DriverIRQHandler
def_irq_handler LPUART3_DriverIRQHandler
def_irq_handler LPUART4_DriverIRQHandler
def_irq_handler LPUART5_DriverIRQHandler
def_irq_handler LPUART6_DriverIRQHandler
def_irq_handler LPUART7_DriverIRQHandler
def_irq_handler LPUART8_DriverIRQHandler
def_irq_handler LPUART9_DriverIRQHandler
def_irq_handler LPUART10_DriverIRQHandler
def_irq_handler LPUART11_DriverIRQHandler
def_irq_handler LPUART12_DriverIRQHandler
def_irq_handler LPI2C1_DriverIRQHandler
def_irq_handler LPI2C2_DriverIRQHandler
def_irq_handler LPI2C3_DriverIRQHandler
def_irq_handler LPI2C4_DriverIRQHandler
def_irq_handler LPI2C5_DriverIRQHandler
def_irq_handler LPI2C6_DriverIRQHandler
def_irq_handler LPSPI1_DriverIRQHandler
def_irq_handler LPSPI2_DriverIRQHandler
def_irq_handler LPSPI3_DriverIRQHandler
def_irq_handler LPSPI4_DriverIRQHandler
def_irq_handler LPSPI5_DriverIRQHandler
def_irq_handler LPSPI6_DriverIRQHandler
def_irq_handler CAN1_DriverIRQHandler
def_irq_handler CAN1_ERROR_DriverIRQHandler
def_irq_handler CAN2_DriverIRQHandler
def_irq_handler CAN2_ERROR_DriverIRQHandler
def_irq_handler CAN3_DriverIRQHandler
def_irq_handler CAN3_ERROR_DriverIRQHandler
def_irq_handler Reserved66_IRQHandler
def_irq_handler KPP_IRQHandler
def_irq_handler Reserved68_IRQHandler
def_irq_handler GPR_IRQ_IRQHandler
def_irq_handler LCDIF1_IRQHandler
def_irq_handler LCDIF2_IRQHandler
def_irq_handler CSI_IRQHandler
def_irq_handler PXP_IRQHandler
def_irq_handler MIPI_CSI_IRQHandler
def_irq_handler MIPI_DSI_IRQHandler
def_irq_handler GPU2D_IRQHandler
def_irq_handler GPIO12_Combined_0_15_IRQHandler
def_irq_handler GPIO12_Combined_16_31_IRQHandler
def_irq_handler DAC_IRQHandler
def_irq_handler KEY_MANAGER_IRQHandler
def_irq_handler WDOG2_IRQHandler
def_irq_handler SNVS_HP_WRAPPER_IRQHandler
def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler
def_irq_handler SNVS_LP_WRAPPER_IRQHandler
def_irq_handler CAAM_IRQ0_IRQHandler
def_irq_handler CAAM_IRQ1_IRQHandler
def_irq_handler CAAM_IRQ2_IRQHandler
def_irq_handler CAAM_IRQ3_IRQHandler
def_irq_handler CAAM_RECORVE_ERRPR_IRQHandler
def_irq_handler CAAM_RTC_IRQHandler
def_irq_handler Reserved91_IRQHandler
def_irq_handler SAI1_DriverIRQHandler
def_irq_handler SAI2_DriverIRQHandler
def_irq_handler SAI3_RX_DriverIRQHandler
def_irq_handler SAI3_TX_DriverIRQHandler
def_irq_handler SAI4_RX_DriverIRQHandler
def_irq_handler SAI4_TX_DriverIRQHandler
def_irq_handler SPDIF_DriverIRQHandler
def_irq_handler ANATOP_TEMP_INT_IRQHandler
def_irq_handler ANATOP_TEMP_LOW_HIGH_IRQHandler
def_irq_handler ANATOP_TEMP_PANIC_IRQHandler
def_irq_handler ANATOP_LP8_BROWNOUT_IRQHandler
def_irq_handler ANATOP_LP0_BROWNOUT_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler ADC2_IRQHandler
def_irq_handler USBPHY1_IRQHandler
def_irq_handler USBPHY2_IRQHandler
def_irq_handler RDC_IRQHandler
def_irq_handler GPIO13_Combined_0_31_IRQHandler
def_irq_handler SFA_IRQHandler
def_irq_handler DCIC1_IRQHandler
def_irq_handler DCIC2_IRQHandler
def_irq_handler ASRC_DriverIRQHandler
def_irq_handler FLEXRAM_ECC_IRQHandler
def_irq_handler GPIO7_8_9_10_11_IRQHandler
def_irq_handler GPIO1_Combined_0_15_IRQHandler
def_irq_handler GPIO1_Combined_16_31_IRQHandler
def_irq_handler GPIO2_Combined_0_15_IRQHandler
def_irq_handler GPIO2_Combined_16_31_IRQHandler
def_irq_handler GPIO3_Combined_0_15_IRQHandler
def_irq_handler GPIO3_Combined_16_31_IRQHandler
def_irq_handler GPIO4_Combined_0_15_IRQHandler
def_irq_handler GPIO4_Combined_16_31_IRQHandler
def_irq_handler GPIO5_Combined_0_15_IRQHandler
def_irq_handler GPIO5_Combined_16_31_IRQHandler
def_irq_handler FLEXIO1_DriverIRQHandler
def_irq_handler FLEXIO2_DriverIRQHandler
def_irq_handler WDOG1_IRQHandler
def_irq_handler RTWDOG4_IRQHandler
def_irq_handler EWM_IRQHandler
def_irq_handler OCOTP_READ_FUSE_ERROR_IRQHandler
def_irq_handler OCOTP_READ_DONE_ERROR_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler MUB_IRQHandler
def_irq_handler GPT1_IRQHandler
def_irq_handler GPT2_IRQHandler
def_irq_handler GPT3_IRQHandler
def_irq_handler GPT4_IRQHandler
def_irq_handler GPT5_IRQHandler
def_irq_handler GPT6_IRQHandler
def_irq_handler PWM1_0_IRQHandler
def_irq_handler PWM1_1_IRQHandler
def_irq_handler PWM1_2_IRQHandler
def_irq_handler PWM1_3_IRQHandler
def_irq_handler PWM1_FAULT_IRQHandler
def_irq_handler FLEXSPI1_DriverIRQHandler
def_irq_handler FLEXSPI2_DriverIRQHandler
def_irq_handler SEMC_IRQHandler
def_irq_handler USDHC1_DriverIRQHandler
def_irq_handler USDHC2_DriverIRQHandler
def_irq_handler USB_OTG2_IRQHandler
def_irq_handler USB_OTG1_IRQHandler
def_irq_handler ENET_DriverIRQHandler
def_irq_handler ENET_1588_Timer_DriverIRQHandler
def_irq_handler ENET_MAC0_Tx_Rx_Done_0_DriverIRQHandler
def_irq_handler ENET_MAC0_Tx_Rx_Done_1_DriverIRQHandler
def_irq_handler ENET_1G_DriverIRQHandler
def_irq_handler ENET_1G_1588_Timer_DriverIRQHandler
def_irq_handler XBAR1_IRQ_0_1_IRQHandler
def_irq_handler XBAR1_IRQ_2_3_IRQHandler
def_irq_handler ADC_ETC_IRQ0_IRQHandler
def_irq_handler ADC_ETC_IRQ1_IRQHandler
def_irq_handler ADC_ETC_IRQ2_IRQHandler
def_irq_handler ADC_ETC_IRQ3_IRQHandler
def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler
def_irq_handler Reserved166_IRQHandler
def_irq_handler Reserved167_IRQHandler
def_irq_handler Reserved168_IRQHandler
def_irq_handler Reserved169_IRQHandler
def_irq_handler Reserved170_IRQHandler
def_irq_handler PIT1_IRQHandler
def_irq_handler PIT2_IRQHandler
def_irq_handler ACMP1_IRQHandler
def_irq_handler ACMP2_IRQHandler
def_irq_handler ACMP3_IRQHandler
def_irq_handler ACMP4_IRQHandler
def_irq_handler Reserved177_IRQHandler
def_irq_handler Reserved178_IRQHandler
def_irq_handler Reserved179_IRQHandler
def_irq_handler Reserved180_IRQHandler
def_irq_handler ENC1_IRQHandler
def_irq_handler ENC2_IRQHandler
def_irq_handler ENC3_IRQHandler
def_irq_handler ENC4_IRQHandler
def_irq_handler Reserved185_IRQHandler
def_irq_handler Reserved186_IRQHandler
def_irq_handler TMR1_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler TMR4_IRQHandler
def_irq_handler SEMA4_CP0_IRQHandler
def_irq_handler SEMA4_CP1_IRQHandler
def_irq_handler PWM2_0_IRQHandler
def_irq_handler PWM2_1_IRQHandler
def_irq_handler PWM2_2_IRQHandler
def_irq_handler PWM2_3_IRQHandler
def_irq_handler PWM2_FAULT_IRQHandler
def_irq_handler PWM3_0_IRQHandler
def_irq_handler PWM3_1_IRQHandler
def_irq_handler PWM3_2_IRQHandler
def_irq_handler PWM3_3_IRQHandler
def_irq_handler PWM3_FAULT_IRQHandler
def_irq_handler PWM4_0_IRQHandler
def_irq_handler PWM4_1_IRQHandler
def_irq_handler PWM4_2_IRQHandler
def_irq_handler PWM4_3_IRQHandler
def_irq_handler PWM4_FAULT_IRQHandler
def_irq_handler Reserved208_IRQHandler
def_irq_handler Reserved209_IRQHandler
def_irq_handler Reserved210_IRQHandler
def_irq_handler Reserved211_IRQHandler
def_irq_handler Reserved212_IRQHandler
def_irq_handler Reserved213_IRQHandler
def_irq_handler Reserved214_IRQHandler
def_irq_handler Reserved215_IRQHandler
def_irq_handler Reserved216_IRQHandler
def_irq_handler Reserved217_IRQHandler
def_irq_handler PDM_EVENT_DriverIRQHandler
def_irq_handler PDM_ERROR_DriverIRQHandler
def_irq_handler EMVSIM1_IRQHandler
def_irq_handler EMVSIM2_IRQHandler
def_irq_handler MECC1_INIT_IRQHandler
def_irq_handler MECC1_FATAL_INIT_IRQHandler
def_irq_handler MECC2_INIT_IRQHandler
def_irq_handler MECC2_FATAL_INIT_IRQHandler
def_irq_handler XECC_FLEXSPI1_INIT_DriverIRQHandler
def_irq_handler XECC_FLEXSPI1_FATAL_INIT_DriverIRQHandler
def_irq_handler XECC_FLEXSPI2_INIT_DriverIRQHandler
def_irq_handler XECC_FLEXSPI2_FATAL_INIT_DriverIRQHandler
def_irq_handler XECC_SEMC_INIT_IRQHandler
def_irq_handler XECC_SEMC_FATAL_INIT_IRQHandler
def_irq_handler ENET_QOS_DriverIRQHandler
def_irq_handler ENET_QOS_PMT_DriverIRQHandler
.end
|
nxp-mcuxpresso/OpenART | 55,305 | bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/arm/startup_MIMXRT1176_cm7.S | /* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1176_cm7.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1176_cm7 */
/* @version: 0.1 */
/* @date: 2018-3-5 */
/* @build: b200610 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2020 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
.section .isr_vector, "a"
.align 2
.globl __Vectors
__Vectors:
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/
.long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/
.long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/
.long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/
.long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/
.long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/
.long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/
.long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/
.long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/
.long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/
.long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/
.long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/
.long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/
.long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/
.long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/
.long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/
.long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/
.long CTI0_ERROR_IRQHandler /* CTI0_Error*/
.long CTI1_ERROR_IRQHandler /* CTI1_Error*/
.long CORE_IRQHandler /* CorePlatform exception IRQ*/
.long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/
.long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/
.long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/
.long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/
.long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/
.long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/
.long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/
.long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/
.long LPUART9_IRQHandler /* LPUART9 TX interrupt and RX interrupt*/
.long LPUART10_IRQHandler /* LPUART10 TX interrupt and RX interrupt*/
.long LPUART11_IRQHandler /* LPUART11 TX interrupt and RX interrupt*/
.long LPUART12_IRQHandler /* LPUART12 TX interrupt and RX interrupt*/
.long LPI2C1_IRQHandler /* LPI2C1 interrupt*/
.long LPI2C2_IRQHandler /* LPI2C2 interrupt*/
.long LPI2C3_IRQHandler /* LPI2C3 interrupt*/
.long LPI2C4_IRQHandler /* LPI2C4 interrupt*/
.long LPI2C5_IRQHandler /* LPI2C5 interrupt*/
.long LPI2C6_IRQHandler /* LPI2C6 interrupt*/
.long LPSPI1_IRQHandler /* LPSPI1 interrupt request line to the core*/
.long LPSPI2_IRQHandler /* LPSPI2 interrupt request line to the core*/
.long LPSPI3_IRQHandler /* LPSPI3 interrupt request line to the core*/
.long LPSPI4_IRQHandler /* LPSPI4 interrupt request line to the core*/
.long LPSPI5_IRQHandler /* LPSPI5 interrupt request line to the core*/
.long LPSPI6_IRQHandler /* LPSPI6 interrupt request line to the core*/
.long CAN1_IRQHandler /* CAN1 interrupt*/
.long CAN1_ERROR_IRQHandler /* CAN1 error interrupt*/
.long CAN2_IRQHandler /* CAN2 interrupt*/
.long CAN2_ERROR_IRQHandler /* CAN2 error interrupt*/
.long CAN3_IRQHandler /* CAN3 interrupt*/
.long CAN3_ERROR_IRQHandler /* CAN3 erro interrupt*/
.long FLEXRAM_IRQHandler /* FlexRAM address out of range Or access hit IRQ*/
.long KPP_IRQHandler /* Keypad nterrupt*/
.long Reserved68_IRQHandler /* Reserved interrupt*/
.long GPR_IRQ_IRQHandler /* GPR interrupt*/
.long LCDIF1_IRQHandler /* LCDIF1 interrupt*/
.long LCDIF2_IRQHandler /* LCDIF2 interrupt*/
.long CSI_IRQHandler /* CSI interrupt*/
.long PXP_IRQHandler /* PXP interrupt*/
.long MIPI_CSI_IRQHandler /* MIPI_CSI interrupt*/
.long MIPI_DSI_IRQHandler /* MIPI_DSI interrupt*/
.long GPU2D_IRQHandler /* GPU2D interrupt*/
.long GPIO6_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO6 signal 0 throughout 15*/
.long GPIO6_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO6 signal 16 throughout 31*/
.long DAC_IRQHandler /* DAC interrupt*/
.long KEY_MANAGER_IRQHandler /* PUF interrupt*/
.long WDOG2_IRQHandler /* WDOG2 interrupt*/
.long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/
.long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/
.long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/
.long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ0*/
.long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ1*/
.long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ2*/
.long CAAM_IRQ3_IRQHandler /* CAAM interrupt queue for JQ3*/
.long CAAM_RECORVE_ERRPR_IRQHandler /* CAAM interrupt for recoverable error*/
.long CAAM_RTC_IRQHandler /* CAAM interrupt for RTC*/
.long Reserved91_IRQHandler /* Reserved interrupt*/
.long SAI1_IRQHandler /* SAI1 interrupt*/
.long SAI2_IRQHandler /* SAI1 interrupt*/
.long SAI3_RX_IRQHandler /* SAI3 interrupt*/
.long SAI3_TX_IRQHandler /* SAI3 interrupt*/
.long SAI4_RX_IRQHandler /* SAI4 interrupt*/
.long SAI4_TX_IRQHandler /* SAI4 interrupt*/
.long SPDIF_IRQHandler /* SPDIF interrupt*/
.long ANATOP_TEMP_INT_IRQHandler /* ANATOP interrupt*/
.long ANATOP_TEMP_LOW_HIGH_IRQHandler /* ANATOP interrupt*/
.long ANATOP_TEMP_PANIC_IRQHandler /* ANATOP interrupt*/
.long ANATOP_LP8_BROWNOUT_IRQHandler /* ANATOP interrupt*/
.long ANATOP_LP0_BROWNOUT_IRQHandler /* ANATOP interrupt*/
.long ADC1_IRQHandler /* ADC1 interrupt*/
.long ADC2_IRQHandler /* ADC2 interrupt*/
.long USBPHY1_IRQHandler /* USBPHY1 interrupt*/
.long USBPHY2_IRQHandler /* USBPHY2 interrupt*/
.long RDC_IRQHandler /* RDC interrupt*/
.long GPIO13_Combined_0_31_IRQHandler /* Combined interrupt indication for GPIO13 signal 0 throughout 31*/
.long SFA_IRQHandler /* SFA interrupt*/
.long DCIC1_IRQHandler /* DCIC1 interrupt*/
.long DCIC2_IRQHandler /* DCIC2 interrupt*/
.long ASRC_IRQHandler /* ASRC interrupt*/
.long FLEXRAM_ECC_IRQHandler /* FlexRAM ECC fatal interrupt*/
.long CM7_GPIO2_3_IRQHandler /* CM7_GPIO2,CM7_GPIO3 interrupt*/
.long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
.long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
.long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
.long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
.long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
.long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
.long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
.long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
.long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
.long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
.long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/
.long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/
.long WDOG1_IRQHandler /* WDOG1 interrupt*/
.long RTWDOG3_IRQHandler /* RTWDOG3 interrupt*/
.long EWM_IRQHandler /* EWM interrupt*/
.long OCOTP_READ_FUSE_ERROR_IRQHandler /* OCOTP read fuse error interrupt*/
.long OCOTP_READ_DONE_ERROR_IRQHandler /* OCOTP read fuse done interrupt*/
.long GPC_IRQHandler /* GPC interrupt*/
.long MUA_IRQHandler /* MUA interrupt*/
.long GPT1_IRQHandler /* GPT1 interrupt*/
.long GPT2_IRQHandler /* GPT2 interrupt*/
.long GPT3_IRQHandler /* GPT3 interrupt*/
.long GPT4_IRQHandler /* GPT4 interrupt*/
.long GPT5_IRQHandler /* GPT5 interrupt*/
.long GPT6_IRQHandler /* GPT6 interrupt*/
.long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/
.long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/
.long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/
.long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/
.long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/
.long FLEXSPI1_IRQHandler /* FlexSPI1 interrupt*/
.long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/
.long SEMC_IRQHandler /* SEMC interrupt*/
.long USDHC1_IRQHandler /* USDHC1 interrupt*/
.long USDHC2_IRQHandler /* USDHC2 interrupt*/
.long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/
.long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/
.long ENET_IRQHandler /* ENET interrupt*/
.long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/
.long ENET_MAC0_Tx_Rx_Done_0_IRQHandler /* ENET 1G MAC0 transmit/receive done 0*/
.long ENET_MAC0_Tx_Rx_Done_1_IRQHandler /* ENET 1G MAC0 transmit/receive done 1*/
.long ENET_1G_IRQHandler /* ENET 1G interrupt*/
.long ENET_1G_1588_Timer_IRQHandler /* ENET_1G_1588_Timer interrupt*/
.long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/
.long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/
.long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/
.long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/
.long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/
.long ADC_ETC_IRQ3_IRQHandler /* ADCETC IRQ3 interrupt*/
.long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/
.long Reserved166_IRQHandler /* Reserved interrupt*/
.long Reserved167_IRQHandler /* Reserved interrupt*/
.long Reserved168_IRQHandler /* Reserved interrupt*/
.long Reserved169_IRQHandler /* Reserved interrupt*/
.long Reserved170_IRQHandler /* Reserved interrupt*/
.long PIT1_IRQHandler /* PIT1 interrupt*/
.long PIT2_IRQHandler /* PIT2 interrupt*/
.long ACMP1_IRQHandler /* ACMP interrupt*/
.long ACMP2_IRQHandler /* ACMP interrupt*/
.long ACMP3_IRQHandler /* ACMP interrupt*/
.long ACMP4_IRQHandler /* ACMP interrupt*/
.long Reserved177_IRQHandler /* Reserved interrupt*/
.long Reserved178_IRQHandler /* Reserved interrupt*/
.long Reserved179_IRQHandler /* Reserved interrupt*/
.long Reserved180_IRQHandler /* Reserved interrupt*/
.long ENC1_IRQHandler /* ENC1 interrupt*/
.long ENC2_IRQHandler /* ENC2 interrupt*/
.long ENC3_IRQHandler /* ENC3 interrupt*/
.long ENC4_IRQHandler /* ENC4 interrupt*/
.long Reserved185_IRQHandler /* Reserved interrupt*/
.long Reserved186_IRQHandler /* Reserved interrupt*/
.long TMR1_IRQHandler /* TMR1 interrupt*/
.long TMR2_IRQHandler /* TMR2 interrupt*/
.long TMR3_IRQHandler /* TMR3 interrupt*/
.long TMR4_IRQHandler /* TMR4 interrupt*/
.long SEMA4_CP0_IRQHandler /* SEMA4 CP0 interrupt*/
.long SEMA4_CP1_IRQHandler /* SEMA4 CP1 interrupt*/
.long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/
.long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/
.long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/
.long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/
.long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/
.long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/
.long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/
.long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/
.long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/
.long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/
.long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/
.long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/
.long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
.long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
.long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/
.long Reserved208_IRQHandler /* Reserved interrupt*/
.long Reserved209_IRQHandler /* Reserved interrupt*/
.long Reserved210_IRQHandler /* Reserved interrupt*/
.long Reserved211_IRQHandler /* Reserved interrupt*/
.long Reserved212_IRQHandler /* Reserved interrupt*/
.long Reserved213_IRQHandler /* Reserved interrupt*/
.long Reserved214_IRQHandler /* Reserved interrupt*/
.long Reserved215_IRQHandler /* Reserved interrupt*/
.long Reserved216_IRQHandler /* Reserved interrupt*/
.long Reserved217_IRQHandler /* Reserved interrupt*/
.long PDM_EVENT_IRQHandler /* PDM event interrupt*/
.long PDM_ERROR_IRQHandler /* PDM error interrupt*/
.long EMVSIM1_IRQHandler /* EMVSIM1 interrupt*/
.long EMVSIM2_IRQHandler /* EMVSIM2 interrupt*/
.long MECC1_INIT_IRQHandler /* MECC1 init*/
.long MECC1_FATAL_INIT_IRQHandler /* MECC1 fatal init*/
.long MECC2_INIT_IRQHandler /* MECC2 init*/
.long MECC2_FATAL_INIT_IRQHandler /* MECC2 fatal init*/
.long XECC_FLEXSPI1_INIT_IRQHandler /* XECC init*/
.long XECC_FLEXSPI1_FATAL_INIT_IRQHandler /* XECC fatal init*/
.long XECC_FLEXSPI2_INIT_IRQHandler /* XECC init*/
.long XECC_FLEXSPI2_FATAL_INIT_IRQHandler /* XECC fatal init*/
.long XECC_SEMC_INIT_IRQHandler /* XECC init*/
.long XECC_SEMC_FATAL_INIT_IRQHandler /* XECC fatal init*/
.long ENET_QOS_IRQHandler /* ENET_QOS interrupt*/
.long ENET_QOS_PMT_IRQHandler /* ENET_QOS_PMT interrupt*/
.long DefaultISR /* 234*/
.long DefaultISR /* 235*/
.long DefaultISR /* 236*/
.long DefaultISR /* 237*/
.long DefaultISR /* 238*/
.long DefaultISR /* 239*/
.long DefaultISR /* 240*/
.long DefaultISR /* 241*/
.long DefaultISR /* 242*/
.long DefaultISR /* 243*/
.long DefaultISR /* 244*/
.long DefaultISR /* 245*/
.long DefaultISR /* 246*/
.long DefaultISR /* 247*/
.long DefaultISR /* 248*/
.long DefaultISR /* 249*/
.long DefaultISR /* 250*/
.long DefaultISR /* 251*/
.long DefaultISR /* 252*/
.long DefaultISR /* 253*/
.long DefaultISR /* 254*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __Vectors, . - __Vectors
.text
.thumb
.equ BANK_CFG_0_ADDR, 0x400e4044
.equ BANK_CFG_1_ADDR, 0x400e4048
.equ BANK_CFG_0, 0xAAAA
.equ BANK_CFG_1, 0xFAAA
.equ BANK_CFG_SEL, 0x400e4040
.equ CFG_SEL, 1<<2
.thumb_func
.align 2
.type Config_Flexram, %function
Config_Flexram:
/* 64K itcm(32*2), 448K dtcm(32*14) */
/* block1 set */
ldr r0,=BANK_CFG_0_ADDR
ldr r1, [r0]
ldr r2, =BANK_CFG_0
bfi r1, r2, #0, #16 // 11, itcm, 10, dtcm, 01 ocram, 8*dtcm
str r1, [r0]
/* block2 set */
ldr r0,=BANK_CFG_1_ADDR
ldr r1, [r0]
ldr r2, =BANK_CFG_1
bfi r1, r2, #0, #16 // 4*dtcm, 4*dtcm
str r1, [r0]
/* CFG Sel */
ldr r0,=BANK_CFG_SEL
ldr r1, [r0]
orr r1, r1, CFG_SEL // use FLEXRAM_BANK_CFG to configure
str r1, [r0]
dsb
bx lr
.size Config_Flexram, . - Config_Flexram
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
mov r0, pc
cmp r0, 0x30000000
bls l0
bl Config_Flexram
l0:
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__Vectors
str r1, [r0]
ldr r2, [r1]
msr msp, r2
ldr r0,=SystemInit
blx r0
cpsie i /* Unmask interrupts */
ldr r0,=__main
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak DMA0_DMA16_IRQHandler
.type DMA0_DMA16_IRQHandler, %function
DMA0_DMA16_IRQHandler:
ldr r0,=DMA0_DMA16_DriverIRQHandler
bx r0
.size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
.align 1
.thumb_func
.weak DMA1_DMA17_IRQHandler
.type DMA1_DMA17_IRQHandler, %function
DMA1_DMA17_IRQHandler:
ldr r0,=DMA1_DMA17_DriverIRQHandler
bx r0
.size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
.align 1
.thumb_func
.weak DMA2_DMA18_IRQHandler
.type DMA2_DMA18_IRQHandler, %function
DMA2_DMA18_IRQHandler:
ldr r0,=DMA2_DMA18_DriverIRQHandler
bx r0
.size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
.align 1
.thumb_func
.weak DMA3_DMA19_IRQHandler
.type DMA3_DMA19_IRQHandler, %function
DMA3_DMA19_IRQHandler:
ldr r0,=DMA3_DMA19_DriverIRQHandler
bx r0
.size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
.align 1
.thumb_func
.weak DMA4_DMA20_IRQHandler
.type DMA4_DMA20_IRQHandler, %function
DMA4_DMA20_IRQHandler:
ldr r0,=DMA4_DMA20_DriverIRQHandler
bx r0
.size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
.align 1
.thumb_func
.weak DMA5_DMA21_IRQHandler
.type DMA5_DMA21_IRQHandler, %function
DMA5_DMA21_IRQHandler:
ldr r0,=DMA5_DMA21_DriverIRQHandler
bx r0
.size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
.align 1
.thumb_func
.weak DMA6_DMA22_IRQHandler
.type DMA6_DMA22_IRQHandler, %function
DMA6_DMA22_IRQHandler:
ldr r0,=DMA6_DMA22_DriverIRQHandler
bx r0
.size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
.align 1
.thumb_func
.weak DMA7_DMA23_IRQHandler
.type DMA7_DMA23_IRQHandler, %function
DMA7_DMA23_IRQHandler:
ldr r0,=DMA7_DMA23_DriverIRQHandler
bx r0
.size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
.align 1
.thumb_func
.weak DMA8_DMA24_IRQHandler
.type DMA8_DMA24_IRQHandler, %function
DMA8_DMA24_IRQHandler:
ldr r0,=DMA8_DMA24_DriverIRQHandler
bx r0
.size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
.align 1
.thumb_func
.weak DMA9_DMA25_IRQHandler
.type DMA9_DMA25_IRQHandler, %function
DMA9_DMA25_IRQHandler:
ldr r0,=DMA9_DMA25_DriverIRQHandler
bx r0
.size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
.align 1
.thumb_func
.weak DMA10_DMA26_IRQHandler
.type DMA10_DMA26_IRQHandler, %function
DMA10_DMA26_IRQHandler:
ldr r0,=DMA10_DMA26_DriverIRQHandler
bx r0
.size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
.align 1
.thumb_func
.weak DMA11_DMA27_IRQHandler
.type DMA11_DMA27_IRQHandler, %function
DMA11_DMA27_IRQHandler:
ldr r0,=DMA11_DMA27_DriverIRQHandler
bx r0
.size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
.align 1
.thumb_func
.weak DMA12_DMA28_IRQHandler
.type DMA12_DMA28_IRQHandler, %function
DMA12_DMA28_IRQHandler:
ldr r0,=DMA12_DMA28_DriverIRQHandler
bx r0
.size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
.align 1
.thumb_func
.weak DMA13_DMA29_IRQHandler
.type DMA13_DMA29_IRQHandler, %function
DMA13_DMA29_IRQHandler:
ldr r0,=DMA13_DMA29_DriverIRQHandler
bx r0
.size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
.align 1
.thumb_func
.weak DMA14_DMA30_IRQHandler
.type DMA14_DMA30_IRQHandler, %function
DMA14_DMA30_IRQHandler:
ldr r0,=DMA14_DMA30_DriverIRQHandler
bx r0
.size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
.align 1
.thumb_func
.weak DMA15_DMA31_IRQHandler
.type DMA15_DMA31_IRQHandler, %function
DMA15_DMA31_IRQHandler:
ldr r0,=DMA15_DMA31_DriverIRQHandler
bx r0
.size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
.align 1
.thumb_func
.weak DMA_ERROR_IRQHandler
.type DMA_ERROR_IRQHandler, %function
DMA_ERROR_IRQHandler:
ldr r0,=DMA_ERROR_DriverIRQHandler
bx r0
.size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler
.align 1
.thumb_func
.weak LPUART1_IRQHandler
.type LPUART1_IRQHandler, %function
LPUART1_IRQHandler:
ldr r0,=LPUART1_DriverIRQHandler
bx r0
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
.align 1
.thumb_func
.weak LPUART2_IRQHandler
.type LPUART2_IRQHandler, %function
LPUART2_IRQHandler:
ldr r0,=LPUART2_DriverIRQHandler
bx r0
.size LPUART2_IRQHandler, . - LPUART2_IRQHandler
.align 1
.thumb_func
.weak LPUART3_IRQHandler
.type LPUART3_IRQHandler, %function
LPUART3_IRQHandler:
ldr r0,=LPUART3_DriverIRQHandler
bx r0
.size LPUART3_IRQHandler, . - LPUART3_IRQHandler
.align 1
.thumb_func
.weak LPUART4_IRQHandler
.type LPUART4_IRQHandler, %function
LPUART4_IRQHandler:
ldr r0,=LPUART4_DriverIRQHandler
bx r0
.size LPUART4_IRQHandler, . - LPUART4_IRQHandler
.align 1
.thumb_func
.weak LPUART5_IRQHandler
.type LPUART5_IRQHandler, %function
LPUART5_IRQHandler:
ldr r0,=LPUART5_DriverIRQHandler
bx r0
.size LPUART5_IRQHandler, . - LPUART5_IRQHandler
.align 1
.thumb_func
.weak LPUART6_IRQHandler
.type LPUART6_IRQHandler, %function
LPUART6_IRQHandler:
ldr r0,=LPUART6_DriverIRQHandler
bx r0
.size LPUART6_IRQHandler, . - LPUART6_IRQHandler
.align 1
.thumb_func
.weak LPUART7_IRQHandler
.type LPUART7_IRQHandler, %function
LPUART7_IRQHandler:
ldr r0,=LPUART7_DriverIRQHandler
bx r0
.size LPUART7_IRQHandler, . - LPUART7_IRQHandler
.align 1
.thumb_func
.weak LPUART8_IRQHandler
.type LPUART8_IRQHandler, %function
LPUART8_IRQHandler:
ldr r0,=LPUART8_DriverIRQHandler
bx r0
.size LPUART8_IRQHandler, . - LPUART8_IRQHandler
.align 1
.thumb_func
.weak LPUART9_IRQHandler
.type LPUART9_IRQHandler, %function
LPUART9_IRQHandler:
ldr r0,=LPUART9_DriverIRQHandler
bx r0
.size LPUART9_IRQHandler, . - LPUART9_IRQHandler
.align 1
.thumb_func
.weak LPUART10_IRQHandler
.type LPUART10_IRQHandler, %function
LPUART10_IRQHandler:
ldr r0,=LPUART10_DriverIRQHandler
bx r0
.size LPUART10_IRQHandler, . - LPUART10_IRQHandler
.align 1
.thumb_func
.weak LPUART11_IRQHandler
.type LPUART11_IRQHandler, %function
LPUART11_IRQHandler:
ldr r0,=LPUART11_DriverIRQHandler
bx r0
.size LPUART11_IRQHandler, . - LPUART11_IRQHandler
.align 1
.thumb_func
.weak LPUART12_IRQHandler
.type LPUART12_IRQHandler, %function
LPUART12_IRQHandler:
ldr r0,=LPUART12_DriverIRQHandler
bx r0
.size LPUART12_IRQHandler, . - LPUART12_IRQHandler
.align 1
.thumb_func
.weak LPI2C1_IRQHandler
.type LPI2C1_IRQHandler, %function
LPI2C1_IRQHandler:
ldr r0,=LPI2C1_DriverIRQHandler
bx r0
.size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler
.align 1
.thumb_func
.weak LPI2C2_IRQHandler
.type LPI2C2_IRQHandler, %function
LPI2C2_IRQHandler:
ldr r0,=LPI2C2_DriverIRQHandler
bx r0
.size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler
.align 1
.thumb_func
.weak LPI2C3_IRQHandler
.type LPI2C3_IRQHandler, %function
LPI2C3_IRQHandler:
ldr r0,=LPI2C3_DriverIRQHandler
bx r0
.size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler
.align 1
.thumb_func
.weak LPI2C4_IRQHandler
.type LPI2C4_IRQHandler, %function
LPI2C4_IRQHandler:
ldr r0,=LPI2C4_DriverIRQHandler
bx r0
.size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler
.align 1
.thumb_func
.weak LPI2C5_IRQHandler
.type LPI2C5_IRQHandler, %function
LPI2C5_IRQHandler:
ldr r0,=LPI2C5_DriverIRQHandler
bx r0
.size LPI2C5_IRQHandler, . - LPI2C5_IRQHandler
.align 1
.thumb_func
.weak LPI2C6_IRQHandler
.type LPI2C6_IRQHandler, %function
LPI2C6_IRQHandler:
ldr r0,=LPI2C6_DriverIRQHandler
bx r0
.size LPI2C6_IRQHandler, . - LPI2C6_IRQHandler
.align 1
.thumb_func
.weak LPSPI1_IRQHandler
.type LPSPI1_IRQHandler, %function
LPSPI1_IRQHandler:
ldr r0,=LPSPI1_DriverIRQHandler
bx r0
.size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler
.align 1
.thumb_func
.weak LPSPI2_IRQHandler
.type LPSPI2_IRQHandler, %function
LPSPI2_IRQHandler:
ldr r0,=LPSPI2_DriverIRQHandler
bx r0
.size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler
.align 1
.thumb_func
.weak LPSPI3_IRQHandler
.type LPSPI3_IRQHandler, %function
LPSPI3_IRQHandler:
ldr r0,=LPSPI3_DriverIRQHandler
bx r0
.size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler
.align 1
.thumb_func
.weak LPSPI4_IRQHandler
.type LPSPI4_IRQHandler, %function
LPSPI4_IRQHandler:
ldr r0,=LPSPI4_DriverIRQHandler
bx r0
.size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler
.align 1
.thumb_func
.weak LPSPI5_IRQHandler
.type LPSPI5_IRQHandler, %function
LPSPI5_IRQHandler:
ldr r0,=LPSPI5_DriverIRQHandler
bx r0
.size LPSPI5_IRQHandler, . - LPSPI5_IRQHandler
.align 1
.thumb_func
.weak LPSPI6_IRQHandler
.type LPSPI6_IRQHandler, %function
LPSPI6_IRQHandler:
ldr r0,=LPSPI6_DriverIRQHandler
bx r0
.size LPSPI6_IRQHandler, . - LPSPI6_IRQHandler
.align 1
.thumb_func
.weak CAN1_IRQHandler
.type CAN1_IRQHandler, %function
CAN1_IRQHandler:
ldr r0,=CAN1_DriverIRQHandler
bx r0
.size CAN1_IRQHandler, . - CAN1_IRQHandler
.align 1
.thumb_func
.weak CAN1_ERROR_IRQHandler
.type CAN1_ERROR_IRQHandler, %function
CAN1_ERROR_IRQHandler:
ldr r0,=CAN1_ERROR_DriverIRQHandler
bx r0
.size CAN1_ERROR_IRQHandler, . - CAN1_ERROR_IRQHandler
.align 1
.thumb_func
.weak CAN2_IRQHandler
.type CAN2_IRQHandler, %function
CAN2_IRQHandler:
ldr r0,=CAN2_DriverIRQHandler
bx r0
.size CAN2_IRQHandler, . - CAN2_IRQHandler
.align 1
.thumb_func
.weak CAN2_ERROR_IRQHandler
.type CAN2_ERROR_IRQHandler, %function
CAN2_ERROR_IRQHandler:
ldr r0,=CAN2_ERROR_DriverIRQHandler
bx r0
.size CAN2_ERROR_IRQHandler, . - CAN2_ERROR_IRQHandler
.align 1
.thumb_func
.weak CAN3_IRQHandler
.type CAN3_IRQHandler, %function
CAN3_IRQHandler:
ldr r0,=CAN3_DriverIRQHandler
bx r0
.size CAN3_IRQHandler, . - CAN3_IRQHandler
.align 1
.thumb_func
.weak CAN3_ERROR_IRQHandler
.type CAN3_ERROR_IRQHandler, %function
CAN3_ERROR_IRQHandler:
ldr r0,=CAN3_ERROR_DriverIRQHandler
bx r0
.size CAN3_ERROR_IRQHandler, . - CAN3_ERROR_IRQHandler
.align 1
.thumb_func
.weak SAI1_IRQHandler
.type SAI1_IRQHandler, %function
SAI1_IRQHandler:
ldr r0,=SAI1_DriverIRQHandler
bx r0
.size SAI1_IRQHandler, . - SAI1_IRQHandler
.align 1
.thumb_func
.weak SAI2_IRQHandler
.type SAI2_IRQHandler, %function
SAI2_IRQHandler:
ldr r0,=SAI2_DriverIRQHandler
bx r0
.size SAI2_IRQHandler, . - SAI2_IRQHandler
.align 1
.thumb_func
.weak SAI3_RX_IRQHandler
.type SAI3_RX_IRQHandler, %function
SAI3_RX_IRQHandler:
ldr r0,=SAI3_RX_DriverIRQHandler
bx r0
.size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler
.align 1
.thumb_func
.weak SAI3_TX_IRQHandler
.type SAI3_TX_IRQHandler, %function
SAI3_TX_IRQHandler:
ldr r0,=SAI3_TX_DriverIRQHandler
bx r0
.size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler
.align 1
.thumb_func
.weak SAI4_RX_IRQHandler
.type SAI4_RX_IRQHandler, %function
SAI4_RX_IRQHandler:
ldr r0,=SAI4_RX_DriverIRQHandler
bx r0
.size SAI4_RX_IRQHandler, . - SAI4_RX_IRQHandler
.align 1
.thumb_func
.weak SAI4_TX_IRQHandler
.type SAI4_TX_IRQHandler, %function
SAI4_TX_IRQHandler:
ldr r0,=SAI4_TX_DriverIRQHandler
bx r0
.size SAI4_TX_IRQHandler, . - SAI4_TX_IRQHandler
.align 1
.thumb_func
.weak SPDIF_IRQHandler
.type SPDIF_IRQHandler, %function
SPDIF_IRQHandler:
ldr r0,=SPDIF_DriverIRQHandler
bx r0
.size SPDIF_IRQHandler, . - SPDIF_IRQHandler
.align 1
.thumb_func
.weak ASRC_IRQHandler
.type ASRC_IRQHandler, %function
ASRC_IRQHandler:
ldr r0,=ASRC_DriverIRQHandler
bx r0
.size ASRC_IRQHandler, . - ASRC_IRQHandler
.align 1
.thumb_func
.weak FLEXIO1_IRQHandler
.type FLEXIO1_IRQHandler, %function
FLEXIO1_IRQHandler:
ldr r0,=FLEXIO1_DriverIRQHandler
bx r0
.size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler
.align 1
.thumb_func
.weak FLEXIO2_IRQHandler
.type FLEXIO2_IRQHandler, %function
FLEXIO2_IRQHandler:
ldr r0,=FLEXIO2_DriverIRQHandler
bx r0
.size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler
.align 1
.thumb_func
.weak FLEXSPI1_IRQHandler
.type FLEXSPI1_IRQHandler, %function
FLEXSPI1_IRQHandler:
ldr r0,=FLEXSPI1_DriverIRQHandler
bx r0
.size FLEXSPI1_IRQHandler, . - FLEXSPI1_IRQHandler
.align 1
.thumb_func
.weak FLEXSPI2_IRQHandler
.type FLEXSPI2_IRQHandler, %function
FLEXSPI2_IRQHandler:
ldr r0,=FLEXSPI2_DriverIRQHandler
bx r0
.size FLEXSPI2_IRQHandler, . - FLEXSPI2_IRQHandler
.align 1
.thumb_func
.weak USDHC1_IRQHandler
.type USDHC1_IRQHandler, %function
USDHC1_IRQHandler:
ldr r0,=USDHC1_DriverIRQHandler
bx r0
.size USDHC1_IRQHandler, . - USDHC1_IRQHandler
.align 1
.thumb_func
.weak USDHC2_IRQHandler
.type USDHC2_IRQHandler, %function
USDHC2_IRQHandler:
ldr r0,=USDHC2_DriverIRQHandler
bx r0
.size USDHC2_IRQHandler, . - USDHC2_IRQHandler
.align 1
.thumb_func
.weak ENET_IRQHandler
.type ENET_IRQHandler, %function
ENET_IRQHandler:
ldr r0,=ENET_DriverIRQHandler
bx r0
.size ENET_IRQHandler, . - ENET_IRQHandler
.align 1
.thumb_func
.weak ENET_1588_Timer_IRQHandler
.type ENET_1588_Timer_IRQHandler, %function
ENET_1588_Timer_IRQHandler:
ldr r0,=ENET_1588_Timer_DriverIRQHandler
bx r0
.size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler
.align 1
.thumb_func
.weak ENET_MAC0_Tx_Rx_Done_0_IRQHandler
.type ENET_MAC0_Tx_Rx_Done_0_IRQHandler, %function
ENET_MAC0_Tx_Rx_Done_0_IRQHandler:
ldr r0,=ENET_MAC0_Tx_Rx_Done_0_DriverIRQHandler
bx r0
.size ENET_MAC0_Tx_Rx_Done_0_IRQHandler, . - ENET_MAC0_Tx_Rx_Done_0_IRQHandler
.align 1
.thumb_func
.weak ENET_MAC0_Tx_Rx_Done_1_IRQHandler
.type ENET_MAC0_Tx_Rx_Done_1_IRQHandler, %function
ENET_MAC0_Tx_Rx_Done_1_IRQHandler:
ldr r0,=ENET_MAC0_Tx_Rx_Done_1_DriverIRQHandler
bx r0
.size ENET_MAC0_Tx_Rx_Done_1_IRQHandler, . - ENET_MAC0_Tx_Rx_Done_1_IRQHandler
.align 1
.thumb_func
.weak ENET_1G_IRQHandler
.type ENET_1G_IRQHandler, %function
ENET_1G_IRQHandler:
ldr r0,=ENET_1G_DriverIRQHandler
bx r0
.size ENET_1G_IRQHandler, . - ENET_1G_IRQHandler
.align 1
.thumb_func
.weak ENET_1G_1588_Timer_IRQHandler
.type ENET_1G_1588_Timer_IRQHandler, %function
ENET_1G_1588_Timer_IRQHandler:
ldr r0,=ENET_1G_1588_Timer_DriverIRQHandler
bx r0
.size ENET_1G_1588_Timer_IRQHandler, . - ENET_1G_1588_Timer_IRQHandler
.align 1
.thumb_func
.weak PDM_EVENT_IRQHandler
.type PDM_EVENT_IRQHandler, %function
PDM_EVENT_IRQHandler:
ldr r0,=PDM_EVENT_DriverIRQHandler
bx r0
.size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler
.align 1
.thumb_func
.weak PDM_ERROR_IRQHandler
.type PDM_ERROR_IRQHandler, %function
PDM_ERROR_IRQHandler:
ldr r0,=PDM_ERROR_DriverIRQHandler
bx r0
.size PDM_ERROR_IRQHandler, . - PDM_ERROR_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI1_INIT_IRQHandler
.type XECC_FLEXSPI1_INIT_IRQHandler, %function
XECC_FLEXSPI1_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI1_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI1_INIT_IRQHandler, . - XECC_FLEXSPI1_INIT_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI1_FATAL_INIT_IRQHandler
.type XECC_FLEXSPI1_FATAL_INIT_IRQHandler, %function
XECC_FLEXSPI1_FATAL_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI1_FATAL_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI1_FATAL_INIT_IRQHandler, . - XECC_FLEXSPI1_FATAL_INIT_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI2_INIT_IRQHandler
.type XECC_FLEXSPI2_INIT_IRQHandler, %function
XECC_FLEXSPI2_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI2_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI2_INIT_IRQHandler, . - XECC_FLEXSPI2_INIT_IRQHandler
.align 1
.thumb_func
.weak XECC_FLEXSPI2_FATAL_INIT_IRQHandler
.type XECC_FLEXSPI2_FATAL_INIT_IRQHandler, %function
XECC_FLEXSPI2_FATAL_INIT_IRQHandler:
ldr r0,=XECC_FLEXSPI2_FATAL_INIT_DriverIRQHandler
bx r0
.size XECC_FLEXSPI2_FATAL_INIT_IRQHandler, . - XECC_FLEXSPI2_FATAL_INIT_IRQHandler
.align 1
.thumb_func
.weak ENET_QOS_IRQHandler
.type ENET_QOS_IRQHandler, %function
ENET_QOS_IRQHandler:
ldr r0,=ENET_QOS_DriverIRQHandler
bx r0
.size ENET_QOS_IRQHandler, . - ENET_QOS_IRQHandler
.align 1
.thumb_func
.weak ENET_QOS_PMT_IRQHandler
.type ENET_QOS_PMT_IRQHandler, %function
ENET_QOS_PMT_IRQHandler:
ldr r0,=ENET_QOS_PMT_DriverIRQHandler
bx r0
.size ENET_QOS_PMT_IRQHandler, . - ENET_QOS_PMT_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler DMA0_DMA16_DriverIRQHandler
def_irq_handler DMA1_DMA17_DriverIRQHandler
def_irq_handler DMA2_DMA18_DriverIRQHandler
def_irq_handler DMA3_DMA19_DriverIRQHandler
def_irq_handler DMA4_DMA20_DriverIRQHandler
def_irq_handler DMA5_DMA21_DriverIRQHandler
def_irq_handler DMA6_DMA22_DriverIRQHandler
def_irq_handler DMA7_DMA23_DriverIRQHandler
def_irq_handler DMA8_DMA24_DriverIRQHandler
def_irq_handler DMA9_DMA25_DriverIRQHandler
def_irq_handler DMA10_DMA26_DriverIRQHandler
def_irq_handler DMA11_DMA27_DriverIRQHandler
def_irq_handler DMA12_DMA28_DriverIRQHandler
def_irq_handler DMA13_DMA29_DriverIRQHandler
def_irq_handler DMA14_DMA30_DriverIRQHandler
def_irq_handler DMA15_DMA31_DriverIRQHandler
def_irq_handler DMA_ERROR_DriverIRQHandler
def_irq_handler CTI0_ERROR_IRQHandler
def_irq_handler CTI1_ERROR_IRQHandler
def_irq_handler CORE_IRQHandler
def_irq_handler LPUART1_DriverIRQHandler
def_irq_handler LPUART2_DriverIRQHandler
def_irq_handler LPUART3_DriverIRQHandler
def_irq_handler LPUART4_DriverIRQHandler
def_irq_handler LPUART5_DriverIRQHandler
def_irq_handler LPUART6_DriverIRQHandler
def_irq_handler LPUART7_DriverIRQHandler
def_irq_handler LPUART8_DriverIRQHandler
def_irq_handler LPUART9_DriverIRQHandler
def_irq_handler LPUART10_DriverIRQHandler
def_irq_handler LPUART11_DriverIRQHandler
def_irq_handler LPUART12_DriverIRQHandler
def_irq_handler LPI2C1_DriverIRQHandler
def_irq_handler LPI2C2_DriverIRQHandler
def_irq_handler LPI2C3_DriverIRQHandler
def_irq_handler LPI2C4_DriverIRQHandler
def_irq_handler LPI2C5_DriverIRQHandler
def_irq_handler LPI2C6_DriverIRQHandler
def_irq_handler LPSPI1_DriverIRQHandler
def_irq_handler LPSPI2_DriverIRQHandler
def_irq_handler LPSPI3_DriverIRQHandler
def_irq_handler LPSPI4_DriverIRQHandler
def_irq_handler LPSPI5_DriverIRQHandler
def_irq_handler LPSPI6_DriverIRQHandler
def_irq_handler CAN1_DriverIRQHandler
def_irq_handler CAN1_ERROR_DriverIRQHandler
def_irq_handler CAN2_DriverIRQHandler
def_irq_handler CAN2_ERROR_DriverIRQHandler
def_irq_handler CAN3_DriverIRQHandler
def_irq_handler CAN3_ERROR_DriverIRQHandler
def_irq_handler FLEXRAM_IRQHandler
def_irq_handler KPP_IRQHandler
def_irq_handler Reserved68_IRQHandler
def_irq_handler GPR_IRQ_IRQHandler
def_irq_handler LCDIF1_IRQHandler
def_irq_handler LCDIF2_IRQHandler
def_irq_handler CSI_IRQHandler
def_irq_handler PXP_IRQHandler
def_irq_handler MIPI_CSI_IRQHandler
def_irq_handler MIPI_DSI_IRQHandler
def_irq_handler GPU2D_IRQHandler
def_irq_handler GPIO6_Combined_0_15_IRQHandler
def_irq_handler GPIO6_Combined_16_31_IRQHandler
def_irq_handler DAC_IRQHandler
def_irq_handler KEY_MANAGER_IRQHandler
def_irq_handler WDOG2_IRQHandler
def_irq_handler SNVS_HP_WRAPPER_IRQHandler
def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler
def_irq_handler SNVS_LP_WRAPPER_IRQHandler
def_irq_handler CAAM_IRQ0_IRQHandler
def_irq_handler CAAM_IRQ1_IRQHandler
def_irq_handler CAAM_IRQ2_IRQHandler
def_irq_handler CAAM_IRQ3_IRQHandler
def_irq_handler CAAM_RECORVE_ERRPR_IRQHandler
def_irq_handler CAAM_RTC_IRQHandler
def_irq_handler Reserved91_IRQHandler
def_irq_handler SAI1_DriverIRQHandler
def_irq_handler SAI2_DriverIRQHandler
def_irq_handler SAI3_RX_DriverIRQHandler
def_irq_handler SAI3_TX_DriverIRQHandler
def_irq_handler SAI4_RX_DriverIRQHandler
def_irq_handler SAI4_TX_DriverIRQHandler
def_irq_handler SPDIF_DriverIRQHandler
def_irq_handler ANATOP_TEMP_INT_IRQHandler
def_irq_handler ANATOP_TEMP_LOW_HIGH_IRQHandler
def_irq_handler ANATOP_TEMP_PANIC_IRQHandler
def_irq_handler ANATOP_LP8_BROWNOUT_IRQHandler
def_irq_handler ANATOP_LP0_BROWNOUT_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler ADC2_IRQHandler
def_irq_handler USBPHY1_IRQHandler
def_irq_handler USBPHY2_IRQHandler
def_irq_handler RDC_IRQHandler
def_irq_handler GPIO13_Combined_0_31_IRQHandler
def_irq_handler SFA_IRQHandler
def_irq_handler DCIC1_IRQHandler
def_irq_handler DCIC2_IRQHandler
def_irq_handler ASRC_DriverIRQHandler
def_irq_handler FLEXRAM_ECC_IRQHandler
def_irq_handler CM7_GPIO2_3_IRQHandler
def_irq_handler GPIO1_Combined_0_15_IRQHandler
def_irq_handler GPIO1_Combined_16_31_IRQHandler
def_irq_handler GPIO2_Combined_0_15_IRQHandler
def_irq_handler GPIO2_Combined_16_31_IRQHandler
def_irq_handler GPIO3_Combined_0_15_IRQHandler
def_irq_handler GPIO3_Combined_16_31_IRQHandler
def_irq_handler GPIO4_Combined_0_15_IRQHandler
def_irq_handler GPIO4_Combined_16_31_IRQHandler
def_irq_handler GPIO5_Combined_0_15_IRQHandler
def_irq_handler GPIO5_Combined_16_31_IRQHandler
def_irq_handler FLEXIO1_DriverIRQHandler
def_irq_handler FLEXIO2_DriverIRQHandler
def_irq_handler WDOG1_IRQHandler
def_irq_handler RTWDOG3_IRQHandler
def_irq_handler EWM_IRQHandler
def_irq_handler OCOTP_READ_FUSE_ERROR_IRQHandler
def_irq_handler OCOTP_READ_DONE_ERROR_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler MUA_IRQHandler
def_irq_handler GPT1_IRQHandler
def_irq_handler GPT2_IRQHandler
def_irq_handler GPT3_IRQHandler
def_irq_handler GPT4_IRQHandler
def_irq_handler GPT5_IRQHandler
def_irq_handler GPT6_IRQHandler
def_irq_handler PWM1_0_IRQHandler
def_irq_handler PWM1_1_IRQHandler
def_irq_handler PWM1_2_IRQHandler
def_irq_handler PWM1_3_IRQHandler
def_irq_handler PWM1_FAULT_IRQHandler
def_irq_handler FLEXSPI1_DriverIRQHandler
def_irq_handler FLEXSPI2_DriverIRQHandler
def_irq_handler SEMC_IRQHandler
def_irq_handler USDHC1_DriverIRQHandler
def_irq_handler USDHC2_DriverIRQHandler
def_irq_handler USB_OTG2_IRQHandler
def_irq_handler USB_OTG1_IRQHandler
def_irq_handler ENET_DriverIRQHandler
def_irq_handler ENET_1588_Timer_DriverIRQHandler
def_irq_handler ENET_MAC0_Tx_Rx_Done_0_DriverIRQHandler
def_irq_handler ENET_MAC0_Tx_Rx_Done_1_DriverIRQHandler
def_irq_handler ENET_1G_DriverIRQHandler
def_irq_handler ENET_1G_1588_Timer_DriverIRQHandler
def_irq_handler XBAR1_IRQ_0_1_IRQHandler
def_irq_handler XBAR1_IRQ_2_3_IRQHandler
def_irq_handler ADC_ETC_IRQ0_IRQHandler
def_irq_handler ADC_ETC_IRQ1_IRQHandler
def_irq_handler ADC_ETC_IRQ2_IRQHandler
def_irq_handler ADC_ETC_IRQ3_IRQHandler
def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler
def_irq_handler Reserved166_IRQHandler
def_irq_handler Reserved167_IRQHandler
def_irq_handler Reserved168_IRQHandler
def_irq_handler Reserved169_IRQHandler
def_irq_handler Reserved170_IRQHandler
def_irq_handler PIT1_IRQHandler
def_irq_handler PIT2_IRQHandler
def_irq_handler ACMP1_IRQHandler
def_irq_handler ACMP2_IRQHandler
def_irq_handler ACMP3_IRQHandler
def_irq_handler ACMP4_IRQHandler
def_irq_handler Reserved177_IRQHandler
def_irq_handler Reserved178_IRQHandler
def_irq_handler Reserved179_IRQHandler
def_irq_handler Reserved180_IRQHandler
def_irq_handler ENC1_IRQHandler
def_irq_handler ENC2_IRQHandler
def_irq_handler ENC3_IRQHandler
def_irq_handler ENC4_IRQHandler
def_irq_handler Reserved185_IRQHandler
def_irq_handler Reserved186_IRQHandler
def_irq_handler TMR1_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler TMR4_IRQHandler
def_irq_handler SEMA4_CP0_IRQHandler
def_irq_handler SEMA4_CP1_IRQHandler
def_irq_handler PWM2_0_IRQHandler
def_irq_handler PWM2_1_IRQHandler
def_irq_handler PWM2_2_IRQHandler
def_irq_handler PWM2_3_IRQHandler
def_irq_handler PWM2_FAULT_IRQHandler
def_irq_handler PWM3_0_IRQHandler
def_irq_handler PWM3_1_IRQHandler
def_irq_handler PWM3_2_IRQHandler
def_irq_handler PWM3_3_IRQHandler
def_irq_handler PWM3_FAULT_IRQHandler
def_irq_handler PWM4_0_IRQHandler
def_irq_handler PWM4_1_IRQHandler
def_irq_handler PWM4_2_IRQHandler
def_irq_handler PWM4_3_IRQHandler
def_irq_handler PWM4_FAULT_IRQHandler
def_irq_handler Reserved208_IRQHandler
def_irq_handler Reserved209_IRQHandler
def_irq_handler Reserved210_IRQHandler
def_irq_handler Reserved211_IRQHandler
def_irq_handler Reserved212_IRQHandler
def_irq_handler Reserved213_IRQHandler
def_irq_handler Reserved214_IRQHandler
def_irq_handler Reserved215_IRQHandler
def_irq_handler Reserved216_IRQHandler
def_irq_handler Reserved217_IRQHandler
def_irq_handler PDM_EVENT_DriverIRQHandler
def_irq_handler PDM_ERROR_DriverIRQHandler
def_irq_handler EMVSIM1_IRQHandler
def_irq_handler EMVSIM2_IRQHandler
def_irq_handler MECC1_INIT_IRQHandler
def_irq_handler MECC1_FATAL_INIT_IRQHandler
def_irq_handler MECC2_INIT_IRQHandler
def_irq_handler MECC2_FATAL_INIT_IRQHandler
def_irq_handler XECC_FLEXSPI1_INIT_DriverIRQHandler
def_irq_handler XECC_FLEXSPI1_FATAL_INIT_DriverIRQHandler
def_irq_handler XECC_FLEXSPI2_INIT_DriverIRQHandler
def_irq_handler XECC_FLEXSPI2_FATAL_INIT_DriverIRQHandler
def_irq_handler XECC_SEMC_INIT_IRQHandler
def_irq_handler XECC_SEMC_FATAL_INIT_IRQHandler
def_irq_handler ENET_QOS_DriverIRQHandler
def_irq_handler ENET_QOS_PMT_DriverIRQHandler
.end
|
nxp-mcuxpresso/OpenART | 5,313 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S | ;/* ----------------------------------------------------------------------
; * Project: CMSIS DSP Library
; * Title: arm_bitreversal2.S
; * Description: arm_bitreversal_32 function done in assembly for maximum speed.
; * Called after doing an fft to reorder the output.
; * The function is loop unrolled by 2. arm_bitreversal_16 as well.
; *
; * $Date: 18. March 2019
; * $Revision: V1.5.2
; *
; * Target Processor: Cortex-M cores
; * -------------------------------------------------------------------- */
;/*
; * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
#if defined ( __CC_ARM ) /* Keil */
#define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
#define LABEL
#elif defined ( __IASMARM__ ) /* IAR */
#define CODESECT SECTION `.text`:CODE
#define PROC
#define LABEL
#define ENDP
#define EXPORT PUBLIC
#elif defined ( __CSMC__ ) /* Cosmic */
#define CODESECT switch .text
#define THUMB
#define EXPORT xdef
#define PROC :
#define LABEL :
#define ENDP
#define arm_bitreversal_32 _arm_bitreversal_32
#elif defined ( __TI_ARM__ ) /* TI ARM */
#define THUMB .thumb
#define CODESECT .text
#define EXPORT .global
#define PROC : .asmfunc
#define LABEL :
#define ENDP .endasmfunc
#define END
#elif defined ( __GNUC__ ) /* GCC */
#define THUMB .thumb
#define CODESECT .section .text
#define EXPORT .global
#define PROC :
#define LABEL :
#define ENDP
#define END
.syntax unified
#endif
CODESECT
THUMB
;/**
; @brief In-place bit reversal function.
; @param[in,out] pSrc points to the in-place buffer of unknown 32-bit data type
; @param[in] bitRevLen bit reversal table length
; @param[in] pBitRevTab points to bit reversal table
; @return none
; */
EXPORT arm_bitreversal_32
EXPORT arm_bitreversal_16
#if defined ( __CC_ARM ) /* Keil */
#elif defined ( __IASMARM__ ) /* IAR */
#elif defined ( __CSMC__ ) /* Cosmic */
#elif defined ( __TI_ARM__ ) /* TI ARM */
#elif defined ( __GNUC__ ) /* GCC */
.type arm_bitreversal_16, %function
.type arm_bitreversal_32, %function
#endif
#if defined (ARM_MATH_CM0_FAMILY)
arm_bitreversal_32 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_32_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
LDR r5,[r2,#4]
LDR r4,[r6,#4]
STR r5,[r6,#4]
STR r4,[r2,#4]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r6}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_16_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
LSRS r2,r2,#1
LSRS r6,r6,#1
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r6}
BX lr
ENDP
#else
arm_bitreversal_32 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8
ADD r9,r0,r9
ADD r2,r0,r2
ADD r12,r0,r12
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
LDR r7,[r9,#4]
LDR r6,[r8,#4]
LDR r5,[r2,#4]
LDR r4,[r12,#4]
STR r6,[r9,#4]
STR r7,[r8,#4]
STR r5,[r12,#4]
STR r4,[r2,#4]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r9}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8,LSR #1
ADD r9,r0,r9,LSR #1
ADD r2,r0,r2,LSR #1
ADD r12,r0,r12,LSR #1
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r9}
BX lr
ENDP
#endif
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,086 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.s | ;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s | ;/**************************************************************************//**
; * @file startup_ARMCM7.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM7 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s | ;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
nxp-mcuxpresso/OpenART | 6,348 | bsp/imxrt/libraries/MIMXRT1170/CMSIS/DSP_Lib/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s | ;/**************************************************************************//**
; * @file startup_ARMCM3.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM3 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD Interrupt3_Handler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler Interrupt3_Handler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END
|
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