repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
mynameisProjects/pokeemeraldplusplus | 2,066 | sound/songs/se_m_blizzard.s | .include "MPlayDef.s"
.equ se_m_blizzard_grp, voicegroup128
.equ se_m_blizzard_pri, 4
.equ se_m_blizzard_rev, reverb_set+50
.equ se_m_blizzard_mvl, 127
.equ se_m_blizzard_key, 0
.equ se_m_blizzard_tbs, 1
.equ se_m_blizzard_exg, 0
.equ se_m_blizzard_cmp, 1
.section .rodata
.global se_m_blizzard
.align 2
@********************** Track 1 **********************@
se_m_blizzard_1:
.byte KEYSH , se_m_blizzard_key+0
.byte TEMPO , 150*se_m_blizzard_tbs/2
.byte VOICE , 22
.byte BENDR , 12
.byte PAN , c_v+0
.byte VOL , 64*se_m_blizzard_mvl/mxv
.byte BEND , c_v+0
.byte N24 , Gn3 , v108
.byte W03
.byte VOL , 79*se_m_blizzard_mvl/mxv
.byte BEND , c_v+22
.byte W02
.byte c_v+8
.byte W01
.byte VOL , 84*se_m_blizzard_mvl/mxv
.byte PAN , c_v-4
.byte W03
.byte VOL , 91*se_m_blizzard_mvl/mxv
.byte BEND , c_v+0
.byte W03
.byte VOL , 100*se_m_blizzard_mvl/mxv
.byte PAN , c_v-8
.byte W03
.byte VOL , 110*se_m_blizzard_mvl/mxv
.byte W03
.byte PAN , c_v-12
.byte W06
se_m_blizzard_1_B1:
.byte PAN , c_v-17
.byte BEND , c_v+0
.byte N48 , Gn3 , v108
.byte W03
.byte BEND , c_v-7
.byte W03
.byte PAN , c_v-9
.byte BEND , c_v-12
.byte W03
.byte c_v-20
.byte W03
.byte PAN , c_v-3
.byte W03
.byte c_v+6
.byte BEND , c_v-13
.byte W03
.byte PAN , c_v+10
.byte W03
.byte BEND , c_v-6
.byte W03
.byte PAN , c_v+16
.byte W03
.byte BEND , c_v+6
.byte W03
.byte PAN , c_v+13
.byte BEND , c_v+11
.byte W03
.byte c_v+20
.byte W03
.byte PAN , c_v+8
.byte W03
.byte c_v+0
.byte BEND , c_v+12
.byte W03
.byte PAN , c_v-8
.byte BEND , c_v+7
.byte W03
.byte PAN , c_v-11
.byte W03
.byte GOTO
.word se_m_blizzard_1_B1
.byte FINE
@******************************************************@
.align 2
se_m_blizzard:
.byte 1 @ NumTrks
.byte 0 @ NumBlks
.byte se_m_blizzard_pri @ Priority
.byte se_m_blizzard_rev @ Reverb.
.word se_m_blizzard_grp
.word se_m_blizzard_1
.end
|
mynameisProjects/pokeemeraldplusplus | 1,199 | sound/songs/se_m_bubble3.s | .include "MPlayDef.s"
.equ se_m_bubble3_grp, voicegroup128
.equ se_m_bubble3_pri, 4
.equ se_m_bubble3_rev, reverb_set+50
.equ se_m_bubble3_mvl, 127
.equ se_m_bubble3_key, 0
.equ se_m_bubble3_tbs, 1
.equ se_m_bubble3_exg, 0
.equ se_m_bubble3_cmp, 1
.section .rodata
.global se_m_bubble3
.align 2
@********************** Track 1 **********************@
se_m_bubble3_1:
.byte KEYSH , se_m_bubble3_key+0
.byte TEMPO , 220*se_m_bubble3_tbs/2
.byte VOICE , 23
.byte VOL , 95*se_m_bubble3_mvl/mxv
.byte BENDR , 12
.byte PAN , c_v+0
.byte BEND , c_v+0
.byte N12 , Gn2 , v127
.byte W06
.byte PAN , c_v-17
.byte BEND , c_v+6
.byte W01
.byte c_v+16
.byte W02
.byte PAN , c_v+16
.byte BEND , c_v+25
.byte W01
.byte c_v+31
.byte W02
.byte PAN , c_v+0
.byte BEND , c_v-1
.byte W03
.byte N06
.byte W03
.byte BEND , c_v+6
.byte W01
.byte c_v+13
.byte W05
.byte FINE
@******************************************************@
.align 2
se_m_bubble3:
.byte 1 @ NumTrks
.byte 0 @ NumBlks
.byte se_m_bubble3_pri @ Priority
.byte se_m_bubble3_rev @ Reverb.
.word se_m_bubble3_grp
.word se_m_bubble3_1
.end
|
MythTV/packaging | 15,839 | Win32/msvc/external/zlib/contrib/gcc_gvmat64/gvmat64.S | /*
;uInt longest_match_x64(
; deflate_state *s,
; IPos cur_match); // current match
; gvmat64.S -- Asm portion of the optimized longest_match for 32 bits x86_64
; (AMD64 on Athlon 64, Opteron, Phenom
; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
; this file is translation from gvmat64.asm to GCC 4.x (for Linux, Mac XCode)
; Copyright (C) 1995-2010 Jean-loup Gailly, Brian Raiter and Gilles Vollant.
;
; File written by Gilles Vollant, by converting to assembly the longest_match
; from Jean-loup Gailly in deflate.c of zLib and infoZip zip.
; and by taking inspiration on asm686 with masm, optimised assembly code
; from Brian Raiter, written 1998
;
; This software is provided 'as-is', without any express or implied
; warranty. In no event will the authors be held liable for any damages
; arising from the use of this software.
;
; Permission is granted to anyone to use this software for any purpose,
; including commercial applications, and to alter it and redistribute it
; freely, subject to the following restrictions:
;
; 1. The origin of this software must not be misrepresented; you must not
; claim that you wrote the original software. If you use this software
; in a product, an acknowledgment in the product documentation would be
; appreciated but is not required.
; 2. Altered source versions must be plainly marked as such, and must not be
; misrepresented as being the original software
; 3. This notice may not be removed or altered from any source distribution.
;
; http://www.zlib.net
; http://www.winimage.com/zLibDll
; http://www.muppetlabs.com/~breadbox/software/assembly.html
;
; to compile this file for zLib, I use option:
; gcc -c -arch x86_64 gvmat64.S
;uInt longest_match(s, cur_match)
; deflate_state *s;
; IPos cur_match; // current match /
;
; with XCode for Mac, I had strange error with some jump on intel syntax
; this is why BEFORE_JMP and AFTER_JMP are used
*/
#define BEFORE_JMP .att_syntax
#define AFTER_JMP .intel_syntax noprefix
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
.intel_syntax noprefix
.globl match_init, longest_match
.text
longest_match:
#define LocalVarsSize 96
/*
; register used : rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12
; free register : r14,r15
; register can be saved : rsp
*/
#define chainlenwmask (rsp + 8 - LocalVarsSize)
#define nicematch (rsp + 16 - LocalVarsSize)
#define save_rdi (rsp + 24 - LocalVarsSize)
#define save_rsi (rsp + 32 - LocalVarsSize)
#define save_rbx (rsp + 40 - LocalVarsSize)
#define save_rbp (rsp + 48 - LocalVarsSize)
#define save_r12 (rsp + 56 - LocalVarsSize)
#define save_r13 (rsp + 64 - LocalVarsSize)
#define save_r14 (rsp + 72 - LocalVarsSize)
#define save_r15 (rsp + 80 - LocalVarsSize)
/*
; all the +4 offsets are due to the addition of pending_buf_size (in zlib
; in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, remove the +4).
; Note : these value are good with a 8 bytes boundary pack structure
*/
#define MAX_MATCH 258
#define MIN_MATCH 3
#define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1)
/*
;;; Offsets for fields in the deflate_state structure. These numbers
;;; are calculated from the definition of deflate_state, with the
;;; assumption that the compiler will dword-align the fields. (Thus,
;;; changing the definition of deflate_state could easily cause this
;;; program to crash horribly, without so much as a warning at
;;; compile time. Sigh.)
; all the +zlib1222add offsets are due to the addition of fields
; in zlib in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
; (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
; if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize %u\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask %u\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow %u\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev %u\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen %u\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch %u\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart %u\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart %u\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead %u\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen %u\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen %u\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch %u\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch %u\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
#define dsWSize 68
#define dsWMask 76
#define dsWindow 80
#define dsPrev 96
#define dsMatchLen 144
#define dsPrevMatch 148
#define dsStrStart 156
#define dsMatchStart 160
#define dsLookahead 164
#define dsPrevLen 168
#define dsMaxChainLen 172
#define dsGoodMatch 188
#define dsNiceMatch 192
#define window_size [ rcx + dsWSize]
#define WMask [ rcx + dsWMask]
#define window_ad [ rcx + dsWindow]
#define prev_ad [ rcx + dsPrev]
#define strstart [ rcx + dsStrStart]
#define match_start [ rcx + dsMatchStart]
#define Lookahead [ rcx + dsLookahead] //; 0ffffffffh on infozip
#define prev_length [ rcx + dsPrevLen]
#define max_chain_length [ rcx + dsMaxChainLen]
#define good_match [ rcx + dsGoodMatch]
#define nice_match [ rcx + dsNiceMatch]
/*
; windows:
; parameter 1 in rcx(deflate state s), param 2 in rdx (cur match)
; see http://weblogs.asp.net/oldnewthing/archive/2004/01/14/58579.aspx and
; http://msdn.microsoft.com/library/en-us/kmarch/hh/kmarch/64bitAMD_8e951dd2-ee77-4728-8702-55ce4b5dd24a.xml.asp
;
; All registers must be preserved across the call, except for
; rax, rcx, rdx, r8, r9, r10, and r11, which are scratch.
;
; gcc on macosx-linux:
; see http://www.x86-64.org/documentation/abi-0.99.pdf
; param 1 in rdi, param 2 in rsi
; rbx, rsp, rbp, r12 to r15 must be preserved
;;; Save registers that the compiler may be using, and adjust esp to
;;; make room for our stack frame.
;;; Retrieve the function arguments. r8d will hold cur_match
;;; throughout the entire function. edx will hold the pointer to the
;;; deflate_state structure during the function's setup (before
;;; entering the main loop.
; ms: parameter 1 in rcx (deflate_state* s), param 2 in edx -> r8 (cur match)
; mac: param 1 in rdi, param 2 rsi
; this clear high 32 bits of r8, which can be garbage in both r8 and rdx
*/
mov [save_rbx],rbx
mov [save_rbp],rbp
mov rcx,rdi
mov r8d,esi
mov [save_r12],r12
mov [save_r13],r13
mov [save_r14],r14
mov [save_r15],r15
//;;; uInt wmask = s->w_mask;
//;;; unsigned chain_length = s->max_chain_length;
//;;; if (s->prev_length >= s->good_match) {
//;;; chain_length >>= 2;
//;;; }
mov edi, prev_length
mov esi, good_match
mov eax, WMask
mov ebx, max_chain_length
cmp edi, esi
jl LastMatchGood
shr ebx, 2
LastMatchGood:
//;;; chainlen is decremented once beforehand so that the function can
//;;; use the sign flag instead of the zero flag for the exit test.
//;;; It is then shifted into the high word, to make room for the wmask
//;;; value, which it will always accompany.
dec ebx
shl ebx, 16
or ebx, eax
//;;; on zlib only
//;;; if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead;
mov eax, nice_match
mov [chainlenwmask], ebx
mov r10d, Lookahead
cmp r10d, eax
cmovnl r10d, eax
mov [nicematch],r10d
//;;; register Bytef *scan = s->window + s->strstart;
mov r10, window_ad
mov ebp, strstart
lea r13, [r10 + rbp]
//;;; Determine how many bytes the scan ptr is off from being
//;;; dword-aligned.
mov r9,r13
neg r13
and r13,3
//;;; IPos limit = s->strstart > (IPos)MAX_DIST(s) ?
//;;; s->strstart - (IPos)MAX_DIST(s) : NIL;
mov eax, window_size
sub eax, MIN_LOOKAHEAD
xor edi,edi
sub ebp, eax
mov r11d, prev_length
cmovng ebp,edi
//;;; int best_len = s->prev_length;
//;;; Store the sum of s->window + best_len in esi locally, and in esi.
lea rsi,[r10+r11]
//;;; register ush scan_start = *(ushf*)scan;
//;;; register ush scan_end = *(ushf*)(scan+best_len-1);
//;;; Posf *prev = s->prev;
movzx r12d,word ptr [r9]
movzx ebx, word ptr [r9 + r11 - 1]
mov rdi, prev_ad
//;;; Jump into the main loop.
mov edx, [chainlenwmask]
cmp bx,word ptr [rsi + r8 - 1]
jz LookupLoopIsZero
LookupLoop1:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
jbe LeaveNow
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry1:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop2:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry2:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop4:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry4:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
jmp LookupLoopIsZero
AFTER_JMP
/*
;;; do {
;;; match = s->window + cur_match;
;;; if (*(ushf*)(match+best_len-1) != scan_end ||
;;; *(ushf*)match != scan_start) continue;
;;; [...]
;;; } while ((cur_match = prev[cur_match & wmask]) > limit
;;; && --chain_length != 0);
;;;
;;; Here is the inner loop of the function. The function will spend the
;;; majority of its time in this loop, and majority of that time will
;;; be spent in the first ten instructions.
;;;
;;; Within this loop:
;;; ebx = scanend
;;; r8d = curmatch
;;; edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
;;; esi = windowbestlen - i.e., (window + bestlen)
;;; edi = prev
;;; ebp = limit
*/
.balign 16
LookupLoop:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
LookupLoopIsZero:
cmp r12w, word ptr [r10 + r8]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
//;;; Store the current value of chainlen.
mov [chainlenwmask], edx
/*
;;; Point edi to the string under scrutiny, and esi to the string we
;;; are hoping to match it up with. In actuality, esi and edi are
;;; both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and edx is
;;; initialized to -(MAX_MATCH_8 - scanalign).
*/
lea rsi,[r8+r10]
mov rdx, 0xfffffffffffffef8 //; -(MAX_MATCH_8)
lea rsi, [rsi + r13 + 0x0108] //;MAX_MATCH_8]
lea rdi, [r9 + r13 + 0x0108] //;MAX_MATCH_8]
prefetcht1 [rsi+rdx]
prefetcht1 [rdi+rdx]
/*
;;; Test the strings for equality, 8 bytes at a time. At the end,
;;; adjust rdx so that it is offset to the exact byte that mismatched.
;;;
;;; We already know at this point that the first three bytes of the
;;; strings match each other, and they can be safely passed over before
;;; starting the compare loop. So what this code does is skip over 0-3
;;; bytes, as much as necessary in order to dword-align the edi
;;; pointer. (rsi will still be misaligned three times out of four.)
;;;
;;; It should be confessed that this loop usually does not represent
;;; much of the total running time. Replacing it with a more
;;; straightforward "rep cmpsb" would not drastically degrade
;;; performance.
*/
LoopCmps:
mov rax, [rsi + rdx]
xor rax, [rdi + rdx]
jnz LeaveLoopCmps
mov rax, [rsi + rdx + 8]
xor rax, [rdi + rdx + 8]
jnz LeaveLoopCmps8
mov rax, [rsi + rdx + 8+8]
xor rax, [rdi + rdx + 8+8]
jnz LeaveLoopCmps16
add rdx,8+8+8
BEFORE_JMP
jnz LoopCmps
jmp LenMaximum
AFTER_JMP
LeaveLoopCmps16: add rdx,8
LeaveLoopCmps8: add rdx,8
LeaveLoopCmps:
test eax, 0x0000FFFF
jnz LenLower
test eax,0xffffffff
jnz LenLower32
add rdx,4
shr rax,32
or ax,ax
BEFORE_JMP
jnz LenLower
AFTER_JMP
LenLower32:
shr eax,16
add rdx,2
LenLower:
sub al, 1
adc rdx, 0
//;;; Calculate the length of the match. If it is longer than MAX_MATCH,
//;;; then automatically accept it as the best possible match and leave.
lea rax, [rdi + rdx]
sub rax, r9
cmp eax, MAX_MATCH
BEFORE_JMP
jge LenMaximum
AFTER_JMP
/*
;;; If the length of the match is not longer than the best match we
;;; have so far, then forget it and return to the lookup loop.
;///////////////////////////////////
*/
cmp eax, r11d
jg LongerMatch
lea rsi,[r10+r11]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
/*
;;; s->match_start = cur_match;
;;; best_len = len;
;;; if (len >= nice_match) break;
;;; scan_end = *(ushf*)(scan+best_len-1);
*/
LongerMatch:
mov r11d, eax
mov match_start, r8d
cmp eax, [nicematch]
BEFORE_JMP
jge LeaveNow
AFTER_JMP
lea rsi,[r10+rax]
movzx ebx, word ptr [r9 + rax - 1]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
//;;; Accept the current string, with the maximum possible length.
LenMaximum:
mov r11d,MAX_MATCH
mov match_start, r8d
//;;; if ((uInt)best_len <= s->lookahead) return (uInt)best_len;
//;;; return s->lookahead;
LeaveNow:
mov eax, Lookahead
cmp r11d, eax
cmovng eax, r11d
//;;; Restore the stack and return from whence we came.
// mov rsi,[save_rsi]
// mov rdi,[save_rdi]
mov rbx,[save_rbx]
mov rbp,[save_rbp]
mov r12,[save_r12]
mov r13,[save_r13]
mov r14,[save_r14]
mov r15,[save_r15]
ret 0
//; please don't remove this string !
//; Your can freely use gvmat64 in any free or commercial app
//; but it is far better don't remove the string in the binary!
// db 0dh,0ah,"asm686 with masm, optimised assembly code from Brian Raiter, written 1998, converted to amd 64 by Gilles Vollant 2005",0dh,0ah,0
match_init:
ret 0
|
MythTV/packaging | 42,842 | Win32/msvc/external/zlib/contrib/inflate86/inffast.S | /*
* inffast.S is a hand tuned assembler version of:
*
* inffast.c -- fast decoding
* Copyright (C) 1995-2003 Mark Adler
* For conditions of distribution and use, see copyright notice in zlib.h
*
* Copyright (C) 2003 Chris Anderson <christop@charm.net>
* Please use the copyright conditions above.
*
* This version (Jan-23-2003) of inflate_fast was coded and tested under
* GNU/Linux on a pentium 3, using the gcc-3.2 compiler distribution. On that
* machine, I found that gzip style archives decompressed about 20% faster than
* the gcc-3.2 -O3 -fomit-frame-pointer compiled version. Your results will
* depend on how large of a buffer is used for z_stream.next_in & next_out
* (8K-32K worked best for my 256K cpu cache) and how much overhead there is in
* stream processing I/O and crc32/addler32. In my case, this routine used
* 70% of the cpu time and crc32 used 20%.
*
* I am confident that this version will work in the general case, but I have
* not tested a wide variety of datasets or a wide variety of platforms.
*
* Jan-24-2003 -- Added -DUSE_MMX define for slightly faster inflating.
* It should be a runtime flag instead of compile time flag...
*
* Jan-26-2003 -- Added runtime check for MMX support with cpuid instruction.
* With -DUSE_MMX, only MMX code is compiled. With -DNO_MMX, only non-MMX code
* is compiled. Without either option, runtime detection is enabled. Runtime
* detection should work on all modern cpus and the recomended algorithm (flip
* ID bit on eflags and then use the cpuid instruction) is used in many
* multimedia applications. Tested under win2k with gcc-2.95 and gas-2.12
* distributed with cygwin3. Compiling with gcc-2.95 -c inffast.S -o
* inffast.obj generates a COFF object which can then be linked with MSVC++
* compiled code. Tested under FreeBSD 4.7 with gcc-2.95.
*
* Jan-28-2003 -- Tested Athlon XP... MMX mode is slower than no MMX (and
* slower than compiler generated code). Adjusted cpuid check to use the MMX
* code only for Pentiums < P4 until I have more data on the P4. Speed
* improvment is only about 15% on the Athlon when compared with code generated
* with MSVC++. Not sure yet, but I think the P4 will also be slower using the
* MMX mode because many of it's x86 ALU instructions execute in .5 cycles and
* have less latency than MMX ops. Added code to buffer the last 11 bytes of
* the input stream since the MMX code grabs bits in chunks of 32, which
* differs from the inffast.c algorithm. I don't think there would have been
* read overruns where a page boundary was crossed (a segfault), but there
* could have been overruns when next_in ends on unaligned memory (unintialized
* memory read).
*
* Mar-13-2003 -- P4 MMX is slightly slower than P4 NO_MMX. I created a C
* version of the non-MMX code so that it doesn't depend on zstrm and zstate
* structure offsets which are hard coded in this file. This was last tested
* with zlib-1.2.0 which is currently in beta testing, newer versions of this
* and inffas86.c can be found at http://www.eetbeetee.com/zlib/ and
* http://www.charm.net/~christop/zlib/
*/
/*
* if you have underscore linking problems (_inflate_fast undefined), try
* using -DGAS_COFF
*/
#if ! defined( GAS_COFF ) && ! defined( GAS_ELF )
#if defined( WIN32 ) || defined( __CYGWIN__ )
#define GAS_COFF /* windows object format */
#else
#define GAS_ELF
#endif
#endif /* ! GAS_COFF && ! GAS_ELF */
#if defined( GAS_COFF )
/* coff externals have underscores */
#define inflate_fast _inflate_fast
#define inflate_fast_use_mmx _inflate_fast_use_mmx
#endif /* GAS_COFF */
.file "inffast.S"
.globl inflate_fast
.text
.align 4,0
.L_invalid_literal_length_code_msg:
.string "invalid literal/length code"
.align 4,0
.L_invalid_distance_code_msg:
.string "invalid distance code"
.align 4,0
.L_invalid_distance_too_far_msg:
.string "invalid distance too far back"
#if ! defined( NO_MMX )
.align 4,0
.L_mask: /* mask[N] = ( 1 << N ) - 1 */
.long 0
.long 1
.long 3
.long 7
.long 15
.long 31
.long 63
.long 127
.long 255
.long 511
.long 1023
.long 2047
.long 4095
.long 8191
.long 16383
.long 32767
.long 65535
.long 131071
.long 262143
.long 524287
.long 1048575
.long 2097151
.long 4194303
.long 8388607
.long 16777215
.long 33554431
.long 67108863
.long 134217727
.long 268435455
.long 536870911
.long 1073741823
.long 2147483647
.long 4294967295
#endif /* NO_MMX */
.text
/*
* struct z_stream offsets, in zlib.h
*/
#define next_in_strm 0 /* strm->next_in */
#define avail_in_strm 4 /* strm->avail_in */
#define next_out_strm 12 /* strm->next_out */
#define avail_out_strm 16 /* strm->avail_out */
#define msg_strm 24 /* strm->msg */
#define state_strm 28 /* strm->state */
/*
* struct inflate_state offsets, in inflate.h
*/
#define mode_state 0 /* state->mode */
#define wsize_state 32 /* state->wsize */
#define write_state 40 /* state->write */
#define window_state 44 /* state->window */
#define hold_state 48 /* state->hold */
#define bits_state 52 /* state->bits */
#define lencode_state 68 /* state->lencode */
#define distcode_state 72 /* state->distcode */
#define lenbits_state 76 /* state->lenbits */
#define distbits_state 80 /* state->distbits */
/*
* inflate_fast's activation record
*/
#define local_var_size 64 /* how much local space for vars */
#define strm_sp 88 /* first arg: z_stream * (local_var_size + 24) */
#define start_sp 92 /* second arg: unsigned int (local_var_size + 28) */
/*
* offsets for local vars on stack
*/
#define out 60 /* unsigned char* */
#define window 56 /* unsigned char* */
#define wsize 52 /* unsigned int */
#define write 48 /* unsigned int */
#define in 44 /* unsigned char* */
#define beg 40 /* unsigned char* */
#define buf 28 /* char[ 12 ] */
#define len 24 /* unsigned int */
#define last 20 /* unsigned char* */
#define end 16 /* unsigned char* */
#define dcode 12 /* code* */
#define lcode 8 /* code* */
#define dmask 4 /* unsigned int */
#define lmask 0 /* unsigned int */
/*
* typedef enum inflate_mode consts, in inflate.h
*/
#define INFLATE_MODE_TYPE 11 /* state->mode flags enum-ed in inflate.h */
#define INFLATE_MODE_BAD 26
#if ! defined( USE_MMX ) && ! defined( NO_MMX )
#define RUN_TIME_MMX
#define CHECK_MMX 1
#define DO_USE_MMX 2
#define DONT_USE_MMX 3
.globl inflate_fast_use_mmx
.data
.align 4,0
inflate_fast_use_mmx: /* integer flag for run time control 1=check,2=mmx,3=no */
.long CHECK_MMX
#if defined( GAS_ELF )
/* elf info */
.type inflate_fast_use_mmx,@object
.size inflate_fast_use_mmx,4
#endif
#endif /* RUN_TIME_MMX */
#if defined( GAS_COFF )
/* coff info: scl 2 = extern, type 32 = function */
.def inflate_fast; .scl 2; .type 32; .endef
#endif
.text
.align 32,0x90
inflate_fast:
pushl %edi
pushl %esi
pushl %ebp
pushl %ebx
pushf /* save eflags (strm_sp, state_sp assumes this is 32 bits) */
subl $local_var_size, %esp
cld
#define strm_r %esi
#define state_r %edi
movl strm_sp(%esp), strm_r
movl state_strm(strm_r), state_r
/* in = strm->next_in;
* out = strm->next_out;
* last = in + strm->avail_in - 11;
* beg = out - (start - strm->avail_out);
* end = out + (strm->avail_out - 257);
*/
movl avail_in_strm(strm_r), %edx
movl next_in_strm(strm_r), %eax
addl %eax, %edx /* avail_in += next_in */
subl $11, %edx /* avail_in -= 11 */
movl %eax, in(%esp)
movl %edx, last(%esp)
movl start_sp(%esp), %ebp
movl avail_out_strm(strm_r), %ecx
movl next_out_strm(strm_r), %ebx
subl %ecx, %ebp /* start -= avail_out */
negl %ebp /* start = -start */
addl %ebx, %ebp /* start += next_out */
subl $257, %ecx /* avail_out -= 257 */
addl %ebx, %ecx /* avail_out += out */
movl %ebx, out(%esp)
movl %ebp, beg(%esp)
movl %ecx, end(%esp)
/* wsize = state->wsize;
* write = state->write;
* window = state->window;
* hold = state->hold;
* bits = state->bits;
* lcode = state->lencode;
* dcode = state->distcode;
* lmask = ( 1 << state->lenbits ) - 1;
* dmask = ( 1 << state->distbits ) - 1;
*/
movl lencode_state(state_r), %eax
movl distcode_state(state_r), %ecx
movl %eax, lcode(%esp)
movl %ecx, dcode(%esp)
movl $1, %eax
movl lenbits_state(state_r), %ecx
shll %cl, %eax
decl %eax
movl %eax, lmask(%esp)
movl $1, %eax
movl distbits_state(state_r), %ecx
shll %cl, %eax
decl %eax
movl %eax, dmask(%esp)
movl wsize_state(state_r), %eax
movl write_state(state_r), %ecx
movl window_state(state_r), %edx
movl %eax, wsize(%esp)
movl %ecx, write(%esp)
movl %edx, window(%esp)
movl hold_state(state_r), %ebp
movl bits_state(state_r), %ebx
#undef strm_r
#undef state_r
#define in_r %esi
#define from_r %esi
#define out_r %edi
movl in(%esp), in_r
movl last(%esp), %ecx
cmpl in_r, %ecx
ja .L_align_long /* if in < last */
addl $11, %ecx /* ecx = &in[ avail_in ] */
subl in_r, %ecx /* ecx = avail_in */
movl $12, %eax
subl %ecx, %eax /* eax = 12 - avail_in */
leal buf(%esp), %edi
rep movsb /* memcpy( buf, in, avail_in ) */
movl %eax, %ecx
xorl %eax, %eax
rep stosb /* memset( &buf[ avail_in ], 0, 12 - avail_in ) */
leal buf(%esp), in_r /* in = buf */
movl in_r, last(%esp) /* last = in, do just one iteration */
jmp .L_is_aligned
/* align in_r on long boundary */
.L_align_long:
testl $3, in_r
jz .L_is_aligned
xorl %eax, %eax
movb (in_r), %al
incl in_r
movl %ebx, %ecx
addl $8, %ebx
shll %cl, %eax
orl %eax, %ebp
jmp .L_align_long
.L_is_aligned:
movl out(%esp), out_r
#if defined( NO_MMX )
jmp .L_do_loop
#endif
#if defined( USE_MMX )
jmp .L_init_mmx
#endif
/*** Runtime MMX check ***/
#if defined( RUN_TIME_MMX )
.L_check_mmx:
cmpl $DO_USE_MMX, inflate_fast_use_mmx
je .L_init_mmx
ja .L_do_loop /* > 2 */
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
pushf
movl (%esp), %eax /* copy eflags to eax */
xorl $0x200000, (%esp) /* try toggling ID bit of eflags (bit 21)
* to see if cpu supports cpuid...
* ID bit method not supported by NexGen but
* bios may load a cpuid instruction and
* cpuid may be disabled on Cyrix 5-6x86 */
popf
pushf
popl %edx /* copy new eflags to edx */
xorl %eax, %edx /* test if ID bit is flipped */
jz .L_dont_use_mmx /* not flipped if zero */
xorl %eax, %eax
cpuid
cmpl $0x756e6547, %ebx /* check for GenuineIntel in ebx,ecx,edx */
jne .L_dont_use_mmx
cmpl $0x6c65746e, %ecx
jne .L_dont_use_mmx
cmpl $0x49656e69, %edx
jne .L_dont_use_mmx
movl $1, %eax
cpuid /* get cpu features */
shrl $8, %eax
andl $15, %eax
cmpl $6, %eax /* check for Pentium family, is 0xf for P4 */
jne .L_dont_use_mmx
testl $0x800000, %edx /* test if MMX feature is set (bit 23) */
jnz .L_use_mmx
jmp .L_dont_use_mmx
.L_use_mmx:
movl $DO_USE_MMX, inflate_fast_use_mmx
jmp .L_check_mmx_pop
.L_dont_use_mmx:
movl $DONT_USE_MMX, inflate_fast_use_mmx
.L_check_mmx_pop:
popl %edx
popl %ecx
popl %ebx
popl %eax
jmp .L_check_mmx
#endif
/*** Non-MMX code ***/
#if defined ( NO_MMX ) || defined( RUN_TIME_MMX )
#define hold_r %ebp
#define bits_r %bl
#define bitslong_r %ebx
.align 32,0x90
.L_while_test:
/* while (in < last && out < end)
*/
cmpl out_r, end(%esp)
jbe .L_break_loop /* if (out >= end) */
cmpl in_r, last(%esp)
jbe .L_break_loop
.L_do_loop:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out
*
* do {
* if (bits < 15) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* this = lcode[hold & lmask]
*/
cmpb $15, bits_r
ja .L_get_length_code /* if (15 < bits) */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
.L_get_length_code:
movl lmask(%esp), %edx /* edx = lmask */
movl lcode(%esp), %ecx /* ecx = lcode */
andl hold_r, %edx /* edx &= hold */
movl (%ecx,%edx,4), %eax /* eax = lcode[hold & lmask] */
.L_dolen:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out
*
* dolen:
* bits -= this.bits;
* hold >>= this.bits
*/
movb %ah, %cl /* cl = this.bits */
subb %ah, bits_r /* bits -= this.bits */
shrl %cl, hold_r /* hold >>= this.bits */
/* check if op is a literal
* if (op == 0) {
* PUP(out) = this.val;
* }
*/
testb %al, %al
jnz .L_test_for_length_base /* if (op != 0) 45.7% */
shrl $16, %eax /* output this.val char */
stosb
jmp .L_while_test
.L_test_for_length_base:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = len
*
* else if (op & 16) {
* len = this.val
* op &= 15
* if (op) {
* if (op > bits) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* len += hold & mask[op];
* bits -= op;
* hold >>= op;
* }
*/
#define len_r %edx
movl %eax, len_r /* len = this */
shrl $16, len_r /* len = this.val */
movb %al, %cl
testb $16, %al
jz .L_test_for_second_level_length /* if ((op & 16) == 0) 8% */
andb $15, %cl /* op &= 15 */
jz .L_save_len /* if (!op) */
cmpb %cl, bits_r
jae .L_add_bits_to_len /* if (op <= bits) */
movb %cl, %ch /* stash op in ch, freeing cl */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
movb %ch, %cl /* move op back to ecx */
.L_add_bits_to_len:
movl $1, %eax
shll %cl, %eax
decl %eax
subb %cl, bits_r
andl hold_r, %eax /* eax &= hold */
shrl %cl, hold_r
addl %eax, len_r /* len += hold & mask[op] */
.L_save_len:
movl len_r, len(%esp) /* save len */
#undef len_r
.L_decode_distance:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = dist
*
* if (bits < 15) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* this = dcode[hold & dmask];
* dodist:
* bits -= this.bits;
* hold >>= this.bits;
* op = this.op;
*/
cmpb $15, bits_r
ja .L_get_distance_code /* if (15 < bits) */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
.L_get_distance_code:
movl dmask(%esp), %edx /* edx = dmask */
movl dcode(%esp), %ecx /* ecx = dcode */
andl hold_r, %edx /* edx &= hold */
movl (%ecx,%edx,4), %eax /* eax = dcode[hold & dmask] */
#define dist_r %edx
.L_dodist:
movl %eax, dist_r /* dist = this */
shrl $16, dist_r /* dist = this.val */
movb %ah, %cl
subb %ah, bits_r /* bits -= this.bits */
shrl %cl, hold_r /* hold >>= this.bits */
/* if (op & 16) {
* dist = this.val
* op &= 15
* if (op > bits) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* dist += hold & mask[op];
* bits -= op;
* hold >>= op;
*/
movb %al, %cl /* cl = this.op */
testb $16, %al /* if ((op & 16) == 0) */
jz .L_test_for_second_level_dist
andb $15, %cl /* op &= 15 */
jz .L_check_dist_one
cmpb %cl, bits_r
jae .L_add_bits_to_dist /* if (op <= bits) 97.6% */
movb %cl, %ch /* stash op in ch, freeing cl */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
movb %ch, %cl /* move op back to ecx */
.L_add_bits_to_dist:
movl $1, %eax
shll %cl, %eax
decl %eax /* (1 << op) - 1 */
subb %cl, bits_r
andl hold_r, %eax /* eax &= hold */
shrl %cl, hold_r
addl %eax, dist_r /* dist += hold & ((1 << op) - 1) */
jmp .L_check_window
.L_check_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes
*
* nbytes = out - beg;
* if (dist <= nbytes) {
* from = out - dist;
* do {
* PUP(out) = PUP(from);
* } while (--len > 0) {
* }
*/
movl in_r, in(%esp) /* save in so from can use it's reg */
movl out_r, %eax
subl beg(%esp), %eax /* nbytes = out - beg */
cmpl dist_r, %eax
jb .L_clip_window /* if (dist > nbytes) 4.2% */
movl len(%esp), %ecx
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
subl $3, %ecx
movb (from_r), %al
movb %al, (out_r)
movb 1(from_r), %al
movb 2(from_r), %dl
addl $3, from_r
movb %al, 1(out_r)
movb %dl, 2(out_r)
addl $3, out_r
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
jmp .L_while_test
.align 16,0x90
.L_check_dist_one:
cmpl $1, dist_r
jne .L_check_window
cmpl out_r, beg(%esp)
je .L_check_window
decl out_r
movl len(%esp), %ecx
movb (out_r), %al
subl $3, %ecx
movb %al, 1(out_r)
movb %al, 2(out_r)
movb %al, 3(out_r)
addl $4, out_r
rep stosb
jmp .L_while_test
.align 16,0x90
.L_test_for_second_level_length:
/* else if ((op & 64) == 0) {
* this = lcode[this.val + (hold & mask[op])];
* }
*/
testb $64, %al
jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */
movl $1, %eax
shll %cl, %eax
decl %eax
andl hold_r, %eax /* eax &= hold */
addl %edx, %eax /* eax += this.val */
movl lcode(%esp), %edx /* edx = lcode */
movl (%edx,%eax,4), %eax /* eax = lcode[val + (hold&mask[op])] */
jmp .L_dolen
.align 16,0x90
.L_test_for_second_level_dist:
/* else if ((op & 64) == 0) {
* this = dcode[this.val + (hold & mask[op])];
* }
*/
testb $64, %al
jnz .L_invalid_distance_code /* if ((op & 64) != 0) */
movl $1, %eax
shll %cl, %eax
decl %eax
andl hold_r, %eax /* eax &= hold */
addl %edx, %eax /* eax += this.val */
movl dcode(%esp), %edx /* edx = dcode */
movl (%edx,%eax,4), %eax /* eax = dcode[val + (hold&mask[op])] */
jmp .L_dodist
.align 16,0x90
.L_clip_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes
*
* else {
* if (dist > wsize) {
* invalid distance
* }
* from = window;
* nbytes = dist - nbytes;
* if (write == 0) {
* from += wsize - nbytes;
*/
#define nbytes_r %ecx
movl %eax, nbytes_r
movl wsize(%esp), %eax /* prepare for dist compare */
negl nbytes_r /* nbytes = -nbytes */
movl window(%esp), from_r /* from = window */
cmpl dist_r, %eax
jb .L_invalid_distance_too_far /* if (dist > wsize) */
addl dist_r, nbytes_r /* nbytes = dist - nbytes */
cmpl $0, write(%esp)
jne .L_wrap_around_window /* if (write != 0) */
subl nbytes_r, %eax
addl %eax, from_r /* from += wsize - nbytes */
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = len
*
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = out - dist;
* }
* }
*/
#define len_r %eax
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
.L_wrap_around_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = write, %eax = len
*
* else if (write < nbytes) {
* from += wsize + write - nbytes;
* nbytes -= write;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = window;
* nbytes = write;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while(--nbytes);
* from = out - dist;
* }
* }
* }
*/
#define write_r %eax
movl write(%esp), write_r
cmpl write_r, nbytes_r
jbe .L_contiguous_in_window /* if (write >= nbytes) */
addl wsize(%esp), from_r
addl write_r, from_r
subl nbytes_r, from_r /* from += wsize + write - nbytes */
subl write_r, nbytes_r /* nbytes -= write */
#undef write_r
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl window(%esp), from_r /* from = window */
movl write(%esp), nbytes_r /* nbytes = write */
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
.L_contiguous_in_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = write, %eax = len
*
* else {
* from += write - nbytes;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = out - dist;
* }
* }
*/
#define write_r %eax
addl write_r, from_r
subl nbytes_r, from_r /* from += write - nbytes */
#undef write_r
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
.L_do_copy1:
/* regs: %esi = from, %esi = in, %ebp = hold, %bl = bits, %edi = out
* %eax = len
*
* while (len > 0) {
* PUP(out) = PUP(from);
* len--;
* }
* }
* } while (in < last && out < end);
*/
#undef nbytes_r
#define in_r %esi
movl len_r, %ecx
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
jmp .L_while_test
#undef len_r
#undef dist_r
#endif /* NO_MMX || RUN_TIME_MMX */
/*** MMX code ***/
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
.align 32,0x90
.L_init_mmx:
emms
#undef bits_r
#undef bitslong_r
#define bitslong_r %ebp
#define hold_mm %mm0
movd %ebp, hold_mm
movl %ebx, bitslong_r
#define used_mm %mm1
#define dmask2_mm %mm2
#define lmask2_mm %mm3
#define lmask_mm %mm4
#define dmask_mm %mm5
#define tmp_mm %mm6
movd lmask(%esp), lmask_mm
movq lmask_mm, lmask2_mm
movd dmask(%esp), dmask_mm
movq dmask_mm, dmask2_mm
pxor used_mm, used_mm
movl lcode(%esp), %ebx /* ebx = lcode */
jmp .L_do_loop_mmx
.align 32,0x90
.L_while_test_mmx:
/* while (in < last && out < end)
*/
cmpl out_r, end(%esp)
jbe .L_break_loop /* if (out >= end) */
cmpl in_r, last(%esp)
jbe .L_break_loop
.L_do_loop_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
cmpl $32, bitslong_r
ja .L_get_length_code_mmx /* if (32 < bits) */
movd bitslong_r, tmp_mm
movd (in_r), %mm7
addl $4, in_r
psllq tmp_mm, %mm7
addl $32, bitslong_r
por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */
.L_get_length_code_mmx:
pand hold_mm, lmask_mm
movd lmask_mm, %eax
movq lmask2_mm, lmask_mm
movl (%ebx,%eax,4), %eax /* eax = lcode[hold & lmask] */
.L_dolen_mmx:
movzbl %ah, %ecx /* ecx = this.bits */
movd %ecx, used_mm
subl %ecx, bitslong_r /* bits -= this.bits */
testb %al, %al
jnz .L_test_for_length_base_mmx /* if (op != 0) 45.7% */
shrl $16, %eax /* output this.val char */
stosb
jmp .L_while_test_mmx
.L_test_for_length_base_mmx:
#define len_r %edx
movl %eax, len_r /* len = this */
shrl $16, len_r /* len = this.val */
testb $16, %al
jz .L_test_for_second_level_length_mmx /* if ((op & 16) == 0) 8% */
andl $15, %eax /* op &= 15 */
jz .L_decode_distance_mmx /* if (!op) */
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd %eax, used_mm
movd hold_mm, %ecx
subl %eax, bitslong_r
andl .L_mask(,%eax,4), %ecx
addl %ecx, len_r /* len += hold & mask[op] */
.L_decode_distance_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
cmpl $32, bitslong_r
ja .L_get_dist_code_mmx /* if (32 < bits) */
movd bitslong_r, tmp_mm
movd (in_r), %mm7
addl $4, in_r
psllq tmp_mm, %mm7
addl $32, bitslong_r
por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */
.L_get_dist_code_mmx:
movl dcode(%esp), %ebx /* ebx = dcode */
pand hold_mm, dmask_mm
movd dmask_mm, %eax
movq dmask2_mm, dmask_mm
movl (%ebx,%eax,4), %eax /* eax = dcode[hold & lmask] */
.L_dodist_mmx:
#define dist_r %ebx
movzbl %ah, %ecx /* ecx = this.bits */
movl %eax, dist_r
shrl $16, dist_r /* dist = this.val */
subl %ecx, bitslong_r /* bits -= this.bits */
movd %ecx, used_mm
testb $16, %al /* if ((op & 16) == 0) */
jz .L_test_for_second_level_dist_mmx
andl $15, %eax /* op &= 15 */
jz .L_check_dist_one_mmx
.L_add_bits_to_dist_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd %eax, used_mm /* save bit length of current op */
movd hold_mm, %ecx /* get the next bits on input stream */
subl %eax, bitslong_r /* bits -= op bits */
andl .L_mask(,%eax,4), %ecx /* ecx = hold & mask[op] */
addl %ecx, dist_r /* dist += hold & mask[op] */
.L_check_window_mmx:
movl in_r, in(%esp) /* save in so from can use it's reg */
movl out_r, %eax
subl beg(%esp), %eax /* nbytes = out - beg */
cmpl dist_r, %eax
jb .L_clip_window_mmx /* if (dist > nbytes) 4.2% */
movl len_r, %ecx
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
subl $3, %ecx
movb (from_r), %al
movb %al, (out_r)
movb 1(from_r), %al
movb 2(from_r), %dl
addl $3, from_r
movb %al, 1(out_r)
movb %dl, 2(out_r)
addl $3, out_r
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
.align 16,0x90
.L_check_dist_one_mmx:
cmpl $1, dist_r
jne .L_check_window_mmx
cmpl out_r, beg(%esp)
je .L_check_window_mmx
decl out_r
movl len_r, %ecx
movb (out_r), %al
subl $3, %ecx
movb %al, 1(out_r)
movb %al, 2(out_r)
movb %al, 3(out_r)
addl $4, out_r
rep stosb
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
.align 16,0x90
.L_test_for_second_level_length_mmx:
testb $64, %al
jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */
andl $15, %eax
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ecx
andl .L_mask(,%eax,4), %ecx
addl len_r, %ecx
movl (%ebx,%ecx,4), %eax /* eax = lcode[hold & lmask] */
jmp .L_dolen_mmx
.align 16,0x90
.L_test_for_second_level_dist_mmx:
testb $64, %al
jnz .L_invalid_distance_code /* if ((op & 64) != 0) */
andl $15, %eax
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ecx
andl .L_mask(,%eax,4), %ecx
movl dcode(%esp), %eax /* ecx = dcode */
addl dist_r, %ecx
movl (%eax,%ecx,4), %eax /* eax = lcode[hold & lmask] */
jmp .L_dodist_mmx
.align 16,0x90
.L_clip_window_mmx:
#define nbytes_r %ecx
movl %eax, nbytes_r
movl wsize(%esp), %eax /* prepare for dist compare */
negl nbytes_r /* nbytes = -nbytes */
movl window(%esp), from_r /* from = window */
cmpl dist_r, %eax
jb .L_invalid_distance_too_far /* if (dist > wsize) */
addl dist_r, nbytes_r /* nbytes = dist - nbytes */
cmpl $0, write(%esp)
jne .L_wrap_around_window_mmx /* if (write != 0) */
subl nbytes_r, %eax
addl %eax, from_r /* from += wsize - nbytes */
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
.L_wrap_around_window_mmx:
#define write_r %eax
movl write(%esp), write_r
cmpl write_r, nbytes_r
jbe .L_contiguous_in_window_mmx /* if (write >= nbytes) */
addl wsize(%esp), from_r
addl write_r, from_r
subl nbytes_r, from_r /* from += wsize + write - nbytes */
subl write_r, nbytes_r /* nbytes -= write */
#undef write_r
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl window(%esp), from_r /* from = window */
movl write(%esp), nbytes_r /* nbytes = write */
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
.L_contiguous_in_window_mmx:
#define write_r %eax
addl write_r, from_r
subl nbytes_r, from_r /* from += write - nbytes */
#undef write_r
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
.L_do_copy1_mmx:
#undef nbytes_r
#define in_r %esi
movl len_r, %ecx
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
#undef hold_r
#undef bitslong_r
#endif /* USE_MMX || RUN_TIME_MMX */
/*** USE_MMX, NO_MMX, and RUNTIME_MMX from here on ***/
.L_invalid_distance_code:
/* else {
* strm->msg = "invalid distance code";
* state->mode = BAD;
* }
*/
movl $.L_invalid_distance_code_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_test_for_end_of_block:
/* else if (op & 32) {
* state->mode = TYPE;
* break;
* }
*/
testb $32, %al
jz .L_invalid_literal_length_code /* if ((op & 32) == 0) */
movl $0, %ecx
movl $INFLATE_MODE_TYPE, %edx
jmp .L_update_stream_state
.L_invalid_literal_length_code:
/* else {
* strm->msg = "invalid literal/length code";
* state->mode = BAD;
* }
*/
movl $.L_invalid_literal_length_code_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_invalid_distance_too_far:
/* strm->msg = "invalid distance too far back";
* state->mode = BAD;
*/
movl in(%esp), in_r /* from_r has in's reg, put in back */
movl $.L_invalid_distance_too_far_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_update_stream_state:
/* set strm->msg = %ecx, strm->state->mode = %edx */
movl strm_sp(%esp), %eax
testl %ecx, %ecx /* if (msg != NULL) */
jz .L_skip_msg
movl %ecx, msg_strm(%eax) /* strm->msg = msg */
.L_skip_msg:
movl state_strm(%eax), %eax /* state = strm->state */
movl %edx, mode_state(%eax) /* state->mode = edx (BAD | TYPE) */
jmp .L_break_loop
.align 32,0x90
.L_break_loop:
/*
* Regs:
*
* bits = %ebp when mmx, and in %ebx when non-mmx
* hold = %hold_mm when mmx, and in %ebp when non-mmx
* in = %esi
* out = %edi
*/
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
#if defined( RUN_TIME_MMX )
cmpl $DO_USE_MMX, inflate_fast_use_mmx
jne .L_update_next_in
#endif /* RUN_TIME_MMX */
movl %ebp, %ebx
.L_update_next_in:
#endif
#define strm_r %eax
#define state_r %edx
/* len = bits >> 3;
* in -= len;
* bits -= len << 3;
* hold &= (1U << bits) - 1;
* state->hold = hold;
* state->bits = bits;
* strm->next_in = in;
* strm->next_out = out;
*/
movl strm_sp(%esp), strm_r
movl %ebx, %ecx
movl state_strm(strm_r), state_r
shrl $3, %ecx
subl %ecx, in_r
shll $3, %ecx
subl %ecx, %ebx
movl out_r, next_out_strm(strm_r)
movl %ebx, bits_state(state_r)
movl %ebx, %ecx
leal buf(%esp), %ebx
cmpl %ebx, last(%esp)
jne .L_buf_not_used /* if buf != last */
subl %ebx, in_r /* in -= buf */
movl next_in_strm(strm_r), %ebx
movl %ebx, last(%esp) /* last = strm->next_in */
addl %ebx, in_r /* in += strm->next_in */
movl avail_in_strm(strm_r), %ebx
subl $11, %ebx
addl %ebx, last(%esp) /* last = &strm->next_in[ avail_in - 11 ] */
.L_buf_not_used:
movl in_r, next_in_strm(strm_r)
movl $1, %ebx
shll %cl, %ebx
decl %ebx
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
#if defined( RUN_TIME_MMX )
cmpl $DO_USE_MMX, inflate_fast_use_mmx
jne .L_update_hold
#endif /* RUN_TIME_MMX */
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ebp
emms
.L_update_hold:
#endif /* USE_MMX || RUN_TIME_MMX */
andl %ebx, %ebp
movl %ebp, hold_state(state_r)
#define last_r %ebx
/* strm->avail_in = in < last ? 11 + (last - in) : 11 - (in - last) */
movl last(%esp), last_r
cmpl in_r, last_r
jbe .L_last_is_smaller /* if (in >= last) */
subl in_r, last_r /* last -= in */
addl $11, last_r /* last += 11 */
movl last_r, avail_in_strm(strm_r)
jmp .L_fixup_out
.L_last_is_smaller:
subl last_r, in_r /* in -= last */
negl in_r /* in = -in */
addl $11, in_r /* in += 11 */
movl in_r, avail_in_strm(strm_r)
#undef last_r
#define end_r %ebx
.L_fixup_out:
/* strm->avail_out = out < end ? 257 + (end - out) : 257 - (out - end)*/
movl end(%esp), end_r
cmpl out_r, end_r
jbe .L_end_is_smaller /* if (out >= end) */
subl out_r, end_r /* end -= out */
addl $257, end_r /* end += 257 */
movl end_r, avail_out_strm(strm_r)
jmp .L_done
.L_end_is_smaller:
subl end_r, out_r /* out -= end */
negl out_r /* out = -out */
addl $257, out_r /* out += 257 */
movl out_r, avail_out_strm(strm_r)
#undef end_r
#undef strm_r
#undef state_r
.L_done:
addl $local_var_size, %esp
popf
popl %ebx
popl %ebp
popl %esi
popl %edi
ret
#if defined( GAS_ELF )
/* elf info */
.type inflate_fast,@function
.size inflate_fast,.-inflate_fast
#endif
|
MythTV/packaging | 10,365 | Win32/msvc/external/zlib/contrib/asm686/match.S | /* match.S -- x86 assembly version of the zlib longest_match() function.
* Optimized for the Intel 686 chips (PPro and later).
*
* Copyright (C) 1998, 2007 Brian Raiter <breadbox@muppetlabs.com>
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the author be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#ifndef NO_UNDERLINE
#define match_init _match_init
#define longest_match _longest_match
#endif
#define MAX_MATCH (258)
#define MIN_MATCH (3)
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7)
/* stack frame offsets */
#define chainlenwmask 0 /* high word: current chain len */
/* low word: s->wmask */
#define window 4 /* local copy of s->window */
#define windowbestlen 8 /* s->window + bestlen */
#define scanstart 16 /* first two bytes of string */
#define scanend 12 /* last two bytes of string */
#define scanalign 20 /* dword-misalignment of string */
#define nicematch 24 /* a good enough match size */
#define bestlen 28 /* size of best match so far */
#define scan 32 /* ptr to string wanting match */
#define LocalVarsSize (36)
/* saved ebx 36 */
/* saved edi 40 */
/* saved esi 44 */
/* saved ebp 48 */
/* return address 52 */
#define deflatestate 56 /* the function arguments */
#define curmatch 60
/* All the +zlib1222add offsets are due to the addition of fields
* in zlib in the deflate_state structure since the asm code was first written
* (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
* (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
* if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
#define zlib1222add (8)
#define dsWSize (36+zlib1222add)
#define dsWMask (44+zlib1222add)
#define dsWindow (48+zlib1222add)
#define dsPrev (56+zlib1222add)
#define dsMatchLen (88+zlib1222add)
#define dsPrevMatch (92+zlib1222add)
#define dsStrStart (100+zlib1222add)
#define dsMatchStart (104+zlib1222add)
#define dsLookahead (108+zlib1222add)
#define dsPrevLen (112+zlib1222add)
#define dsMaxChainLen (116+zlib1222add)
#define dsGoodMatch (132+zlib1222add)
#define dsNiceMatch (136+zlib1222add)
.file "match.S"
.globl match_init, longest_match
.text
/* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */
.cfi_sections .debug_frame
longest_match:
.cfi_startproc
/* Save registers that the compiler may be using, and adjust %esp to */
/* make room for our stack frame. */
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset ebp, -8
pushl %edi
.cfi_def_cfa_offset 12
pushl %esi
.cfi_def_cfa_offset 16
pushl %ebx
.cfi_def_cfa_offset 20
subl $LocalVarsSize, %esp
.cfi_def_cfa_offset LocalVarsSize+20
/* Retrieve the function arguments. %ecx will hold cur_match */
/* throughout the entire function. %edx will hold the pointer to the */
/* deflate_state structure during the function's setup (before */
/* entering the main loop). */
movl deflatestate(%esp), %edx
movl curmatch(%esp), %ecx
/* uInt wmask = s->w_mask; */
/* unsigned chain_length = s->max_chain_length; */
/* if (s->prev_length >= s->good_match) { */
/* chain_length >>= 2; */
/* } */
movl dsPrevLen(%edx), %eax
movl dsGoodMatch(%edx), %ebx
cmpl %ebx, %eax
movl dsWMask(%edx), %eax
movl dsMaxChainLen(%edx), %ebx
jl LastMatchGood
shrl $2, %ebx
LastMatchGood:
/* chainlen is decremented once beforehand so that the function can */
/* use the sign flag instead of the zero flag for the exit test. */
/* It is then shifted into the high word, to make room for the wmask */
/* value, which it will always accompany. */
decl %ebx
shll $16, %ebx
orl %eax, %ebx
movl %ebx, chainlenwmask(%esp)
/* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */
movl dsNiceMatch(%edx), %eax
movl dsLookahead(%edx), %ebx
cmpl %eax, %ebx
jl LookaheadLess
movl %eax, %ebx
LookaheadLess: movl %ebx, nicematch(%esp)
/* register Bytef *scan = s->window + s->strstart; */
movl dsWindow(%edx), %esi
movl %esi, window(%esp)
movl dsStrStart(%edx), %ebp
lea (%esi,%ebp), %edi
movl %edi, scan(%esp)
/* Determine how many bytes the scan ptr is off from being */
/* dword-aligned. */
movl %edi, %eax
negl %eax
andl $3, %eax
movl %eax, scanalign(%esp)
/* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */
/* s->strstart - (IPos)MAX_DIST(s) : NIL; */
movl dsWSize(%edx), %eax
subl $MIN_LOOKAHEAD, %eax
subl %eax, %ebp
jg LimitPositive
xorl %ebp, %ebp
LimitPositive:
/* int best_len = s->prev_length; */
movl dsPrevLen(%edx), %eax
movl %eax, bestlen(%esp)
/* Store the sum of s->window + best_len in %esi locally, and in %esi. */
addl %eax, %esi
movl %esi, windowbestlen(%esp)
/* register ush scan_start = *(ushf*)scan; */
/* register ush scan_end = *(ushf*)(scan+best_len-1); */
/* Posf *prev = s->prev; */
movzwl (%edi), %ebx
movl %ebx, scanstart(%esp)
movzwl -1(%edi,%eax), %ebx
movl %ebx, scanend(%esp)
movl dsPrev(%edx), %edi
/* Jump into the main loop. */
movl chainlenwmask(%esp), %edx
jmp LoopEntry
.balign 16
/* do {
* match = s->window + cur_match;
* if (*(ushf*)(match+best_len-1) != scan_end ||
* *(ushf*)match != scan_start) continue;
* [...]
* } while ((cur_match = prev[cur_match & wmask]) > limit
* && --chain_length != 0);
*
* Here is the inner loop of the function. The function will spend the
* majority of its time in this loop, and majority of that time will
* be spent in the first ten instructions.
*
* Within this loop:
* %ebx = scanend
* %ecx = curmatch
* %edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
* %esi = windowbestlen - i.e., (window + bestlen)
* %edi = prev
* %ebp = limit
*/
LookupLoop:
andl %edx, %ecx
movzwl (%edi,%ecx,2), %ecx
cmpl %ebp, %ecx
jbe LeaveNow
subl $0x00010000, %edx
js LeaveNow
LoopEntry: movzwl -1(%esi,%ecx), %eax
cmpl %ebx, %eax
jnz LookupLoop
movl window(%esp), %eax
movzwl (%eax,%ecx), %eax
cmpl scanstart(%esp), %eax
jnz LookupLoop
/* Store the current value of chainlen. */
movl %edx, chainlenwmask(%esp)
/* Point %edi to the string under scrutiny, and %esi to the string we */
/* are hoping to match it up with. In actuality, %esi and %edi are */
/* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */
/* initialized to -(MAX_MATCH_8 - scanalign). */
movl window(%esp), %esi
movl scan(%esp), %edi
addl %ecx, %esi
movl scanalign(%esp), %eax
movl $(-MAX_MATCH_8), %edx
lea MAX_MATCH_8(%edi,%eax), %edi
lea MAX_MATCH_8(%esi,%eax), %esi
/* Test the strings for equality, 8 bytes at a time. At the end,
* adjust %edx so that it is offset to the exact byte that mismatched.
*
* We already know at this point that the first three bytes of the
* strings match each other, and they can be safely passed over before
* starting the compare loop. So what this code does is skip over 0-3
* bytes, as much as necessary in order to dword-align the %edi
* pointer. (%esi will still be misaligned three times out of four.)
*
* It should be confessed that this loop usually does not represent
* much of the total running time. Replacing it with a more
* straightforward "rep cmpsb" would not drastically degrade
* performance.
*/
LoopCmps:
movl (%esi,%edx), %eax
xorl (%edi,%edx), %eax
jnz LeaveLoopCmps
movl 4(%esi,%edx), %eax
xorl 4(%edi,%edx), %eax
jnz LeaveLoopCmps4
addl $8, %edx
jnz LoopCmps
jmp LenMaximum
LeaveLoopCmps4: addl $4, %edx
LeaveLoopCmps: testl $0x0000FFFF, %eax
jnz LenLower
addl $2, %edx
shrl $16, %eax
LenLower: subb $1, %al
adcl $0, %edx
/* Calculate the length of the match. If it is longer than MAX_MATCH, */
/* then automatically accept it as the best possible match and leave. */
lea (%edi,%edx), %eax
movl scan(%esp), %edi
subl %edi, %eax
cmpl $MAX_MATCH, %eax
jge LenMaximum
/* If the length of the match is not longer than the best match we */
/* have so far, then forget it and return to the lookup loop. */
movl deflatestate(%esp), %edx
movl bestlen(%esp), %ebx
cmpl %ebx, %eax
jg LongerMatch
movl windowbestlen(%esp), %esi
movl dsPrev(%edx), %edi
movl scanend(%esp), %ebx
movl chainlenwmask(%esp), %edx
jmp LookupLoop
/* s->match_start = cur_match; */
/* best_len = len; */
/* if (len >= nice_match) break; */
/* scan_end = *(ushf*)(scan+best_len-1); */
LongerMatch: movl nicematch(%esp), %ebx
movl %eax, bestlen(%esp)
movl %ecx, dsMatchStart(%edx)
cmpl %ebx, %eax
jge LeaveNow
movl window(%esp), %esi
addl %eax, %esi
movl %esi, windowbestlen(%esp)
movzwl -1(%edi,%eax), %ebx
movl dsPrev(%edx), %edi
movl %ebx, scanend(%esp)
movl chainlenwmask(%esp), %edx
jmp LookupLoop
/* Accept the current string, with the maximum possible length. */
LenMaximum: movl deflatestate(%esp), %edx
movl $MAX_MATCH, bestlen(%esp)
movl %ecx, dsMatchStart(%edx)
/* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */
/* return s->lookahead; */
LeaveNow:
movl deflatestate(%esp), %edx
movl bestlen(%esp), %ebx
movl dsLookahead(%edx), %eax
cmpl %eax, %ebx
jg LookaheadRet
movl %ebx, %eax
LookaheadRet:
/* Restore the stack and return from whence we came. */
addl $LocalVarsSize, %esp
.cfi_def_cfa_offset 20
popl %ebx
.cfi_def_cfa_offset 16
popl %esi
.cfi_def_cfa_offset 12
popl %edi
.cfi_def_cfa_offset 8
popl %ebp
.cfi_def_cfa_offset 4
.cfi_endproc
match_init: ret
|
MythTV/packaging | 12,418 | Win32/msvc/external/zlib/contrib/amd64/amd64-match.S | /*
* match.S -- optimized version of longest_match()
* based on the similar work by Gilles Vollant, and Brian Raiter, written 1998
*
* This is free software; you can redistribute it and/or modify it
* under the terms of the BSD License. Use by owners of Che Guevarra
* parafernalia is prohibited, where possible, and highly discouraged
* elsewhere.
*/
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
#define scanend ebx
#define scanendw bx
#define chainlenwmask edx /* high word: current chain len low word: s->wmask */
#define curmatch rsi
#define curmatchd esi
#define windowbestlen r8
#define scanalign r9
#define scanalignd r9d
#define window r10
#define bestlen r11
#define bestlend r11d
#define scanstart r12d
#define scanstartw r12w
#define scan r13
#define nicematch r14d
#define limit r15
#define limitd r15d
#define prev rcx
/*
* The 258 is a "magic number, not a parameter -- changing it
* breaks the hell loose
*/
#define MAX_MATCH (258)
#define MIN_MATCH (3)
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7)
/* stack frame offsets */
#define LocalVarsSize (112)
#define _chainlenwmask ( 8-LocalVarsSize)(%rsp)
#define _windowbestlen (16-LocalVarsSize)(%rsp)
#define save_r14 (24-LocalVarsSize)(%rsp)
#define save_rsi (32-LocalVarsSize)(%rsp)
#define save_rbx (40-LocalVarsSize)(%rsp)
#define save_r12 (56-LocalVarsSize)(%rsp)
#define save_r13 (64-LocalVarsSize)(%rsp)
#define save_r15 (80-LocalVarsSize)(%rsp)
.globl match_init, longest_match
/*
* On AMD64 the first argument of a function (in our case -- the pointer to
* deflate_state structure) is passed in %rdi, hence our offsets below are
* all off of that.
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize (%3u)(%%rdi)\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask (%3u)(%%rdi)\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow (%3u)(%%rdi)\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev (%3u)(%%rdi)\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen (%3u)(%%rdi)\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart (%3u)(%%rdi)\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart (%3u)(%%rdi)\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead (%3u)(%%rdi)\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen (%3u)(%%rdi)\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
/*
to compile for XCode 3.2 on MacOSX x86_64
- run "gcc -g -c -DXCODE_MAC_X64_STRUCTURE amd64-match.S"
*/
#ifndef CURRENT_LINX_XCODE_MAC_X64_STRUCTURE
#define dsWSize ( 68)(%rdi)
#define dsWMask ( 76)(%rdi)
#define dsWindow ( 80)(%rdi)
#define dsPrev ( 96)(%rdi)
#define dsMatchLen (144)(%rdi)
#define dsPrevMatch (148)(%rdi)
#define dsStrStart (156)(%rdi)
#define dsMatchStart (160)(%rdi)
#define dsLookahead (164)(%rdi)
#define dsPrevLen (168)(%rdi)
#define dsMaxChainLen (172)(%rdi)
#define dsGoodMatch (188)(%rdi)
#define dsNiceMatch (192)(%rdi)
#else
#ifndef STRUCT_OFFSET
# define STRUCT_OFFSET (0)
#endif
#define dsWSize ( 56 + STRUCT_OFFSET)(%rdi)
#define dsWMask ( 64 + STRUCT_OFFSET)(%rdi)
#define dsWindow ( 72 + STRUCT_OFFSET)(%rdi)
#define dsPrev ( 88 + STRUCT_OFFSET)(%rdi)
#define dsMatchLen (136 + STRUCT_OFFSET)(%rdi)
#define dsPrevMatch (140 + STRUCT_OFFSET)(%rdi)
#define dsStrStart (148 + STRUCT_OFFSET)(%rdi)
#define dsMatchStart (152 + STRUCT_OFFSET)(%rdi)
#define dsLookahead (156 + STRUCT_OFFSET)(%rdi)
#define dsPrevLen (160 + STRUCT_OFFSET)(%rdi)
#define dsMaxChainLen (164 + STRUCT_OFFSET)(%rdi)
#define dsGoodMatch (180 + STRUCT_OFFSET)(%rdi)
#define dsNiceMatch (184 + STRUCT_OFFSET)(%rdi)
#endif
.text
/* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */
longest_match:
/*
* Retrieve the function arguments. %curmatch will hold cur_match
* throughout the entire function (passed via rsi on amd64).
* rdi will hold the pointer to the deflate_state (first arg on amd64)
*/
mov %rsi, save_rsi
mov %rbx, save_rbx
mov %r12, save_r12
mov %r13, save_r13
mov %r14, save_r14
mov %r15, save_r15
/* uInt wmask = s->w_mask; */
/* unsigned chain_length = s->max_chain_length; */
/* if (s->prev_length >= s->good_match) { */
/* chain_length >>= 2; */
/* } */
movl dsPrevLen, %eax
movl dsGoodMatch, %ebx
cmpl %ebx, %eax
movl dsWMask, %eax
movl dsMaxChainLen, %chainlenwmask
jl LastMatchGood
shrl $2, %chainlenwmask
LastMatchGood:
/* chainlen is decremented once beforehand so that the function can */
/* use the sign flag instead of the zero flag for the exit test. */
/* It is then shifted into the high word, to make room for the wmask */
/* value, which it will always accompany. */
decl %chainlenwmask
shll $16, %chainlenwmask
orl %eax, %chainlenwmask
/* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */
movl dsNiceMatch, %eax
movl dsLookahead, %ebx
cmpl %eax, %ebx
jl LookaheadLess
movl %eax, %ebx
LookaheadLess: movl %ebx, %nicematch
/* register Bytef *scan = s->window + s->strstart; */
mov dsWindow, %window
movl dsStrStart, %limitd
lea (%limit, %window), %scan
/* Determine how many bytes the scan ptr is off from being */
/* dword-aligned. */
mov %scan, %scanalign
negl %scanalignd
andl $3, %scanalignd
/* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */
/* s->strstart - (IPos)MAX_DIST(s) : NIL; */
movl dsWSize, %eax
subl $MIN_LOOKAHEAD, %eax
xorl %ecx, %ecx
subl %eax, %limitd
cmovng %ecx, %limitd
/* int best_len = s->prev_length; */
movl dsPrevLen, %bestlend
/* Store the sum of s->window + best_len in %windowbestlen locally, and in memory. */
lea (%window, %bestlen), %windowbestlen
mov %windowbestlen, _windowbestlen
/* register ush scan_start = *(ushf*)scan; */
/* register ush scan_end = *(ushf*)(scan+best_len-1); */
/* Posf *prev = s->prev; */
movzwl (%scan), %scanstart
movzwl -1(%scan, %bestlen), %scanend
mov dsPrev, %prev
/* Jump into the main loop. */
movl %chainlenwmask, _chainlenwmask
jmp LoopEntry
.balign 16
/* do {
* match = s->window + cur_match;
* if (*(ushf*)(match+best_len-1) != scan_end ||
* *(ushf*)match != scan_start) continue;
* [...]
* } while ((cur_match = prev[cur_match & wmask]) > limit
* && --chain_length != 0);
*
* Here is the inner loop of the function. The function will spend the
* majority of its time in this loop, and majority of that time will
* be spent in the first ten instructions.
*/
LookupLoop:
andl %chainlenwmask, %curmatchd
movzwl (%prev, %curmatch, 2), %curmatchd
cmpl %limitd, %curmatchd
jbe LeaveNow
subl $0x00010000, %chainlenwmask
js LeaveNow
LoopEntry: cmpw -1(%windowbestlen, %curmatch), %scanendw
jne LookupLoop
cmpw %scanstartw, (%window, %curmatch)
jne LookupLoop
/* Store the current value of chainlen. */
movl %chainlenwmask, _chainlenwmask
/* %scan is the string under scrutiny, and %prev to the string we */
/* are hoping to match it up with. In actuality, %esi and %edi are */
/* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */
/* initialized to -(MAX_MATCH_8 - scanalign). */
mov $(-MAX_MATCH_8), %rdx
lea (%curmatch, %window), %windowbestlen
lea MAX_MATCH_8(%windowbestlen, %scanalign), %windowbestlen
lea MAX_MATCH_8(%scan, %scanalign), %prev
/* the prefetching below makes very little difference... */
prefetcht1 (%windowbestlen, %rdx)
prefetcht1 (%prev, %rdx)
/*
* Test the strings for equality, 8 bytes at a time. At the end,
* adjust %rdx so that it is offset to the exact byte that mismatched.
*
* It should be confessed that this loop usually does not represent
* much of the total running time. Replacing it with a more
* straightforward "rep cmpsb" would not drastically degrade
* performance -- unrolling it, for example, makes no difference.
*/
#undef USE_SSE /* works, but is 6-7% slower, than non-SSE... */
LoopCmps:
#ifdef USE_SSE
/* Preload the SSE registers */
movdqu (%windowbestlen, %rdx), %xmm1
movdqu (%prev, %rdx), %xmm2
pcmpeqb %xmm2, %xmm1
movdqu 16(%windowbestlen, %rdx), %xmm3
movdqu 16(%prev, %rdx), %xmm4
pcmpeqb %xmm4, %xmm3
movdqu 32(%windowbestlen, %rdx), %xmm5
movdqu 32(%prev, %rdx), %xmm6
pcmpeqb %xmm6, %xmm5
movdqu 48(%windowbestlen, %rdx), %xmm7
movdqu 48(%prev, %rdx), %xmm8
pcmpeqb %xmm8, %xmm7
/* Check the comparisions' results */
pmovmskb %xmm1, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
/* this is the only iteration of the loop with a possibility of having
incremented rdx by 0x108 (each loop iteration add 16*4 = 0x40
and (0x40*4)+8=0x108 */
add $8, %rdx
jz LenMaximum
add $8, %rdx
pmovmskb %xmm3, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
pmovmskb %xmm5, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
pmovmskb %xmm7, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
jmp LoopCmps
LeaveLoopCmps: add %rax, %rdx
#else
mov (%windowbestlen, %rdx), %rax
xor (%prev, %rdx), %rax
jnz LeaveLoopCmps
mov 8(%windowbestlen, %rdx), %rax
xor 8(%prev, %rdx), %rax
jnz LeaveLoopCmps8
mov 16(%windowbestlen, %rdx), %rax
xor 16(%prev, %rdx), %rax
jnz LeaveLoopCmps16
add $24, %rdx
jnz LoopCmps
jmp LenMaximum
# if 0
/*
* This three-liner is tantalizingly simple, but bsf is a slow instruction,
* and the complicated alternative down below is quite a bit faster. Sad...
*/
LeaveLoopCmps: bsf %rax, %rax /* find the first non-zero bit */
shrl $3, %eax /* divide by 8 to get the byte */
add %rax, %rdx
# else
LeaveLoopCmps16:
add $8, %rdx
LeaveLoopCmps8:
add $8, %rdx
LeaveLoopCmps: testl $0xFFFFFFFF, %eax /* Check the first 4 bytes */
jnz Check16
add $4, %rdx
shr $32, %rax
Check16: testw $0xFFFF, %ax
jnz LenLower
add $2, %rdx
shrl $16, %eax
LenLower: subb $1, %al
adc $0, %rdx
# endif
#endif
/* Calculate the length of the match. If it is longer than MAX_MATCH, */
/* then automatically accept it as the best possible match and leave. */
lea (%prev, %rdx), %rax
sub %scan, %rax
cmpl $MAX_MATCH, %eax
jge LenMaximum
/* If the length of the match is not longer than the best match we */
/* have so far, then forget it and return to the lookup loop. */
cmpl %bestlend, %eax
jg LongerMatch
mov _windowbestlen, %windowbestlen
mov dsPrev, %prev
movl _chainlenwmask, %edx
jmp LookupLoop
/* s->match_start = cur_match; */
/* best_len = len; */
/* if (len >= nice_match) break; */
/* scan_end = *(ushf*)(scan+best_len-1); */
LongerMatch:
movl %eax, %bestlend
movl %curmatchd, dsMatchStart
cmpl %nicematch, %eax
jge LeaveNow
lea (%window, %bestlen), %windowbestlen
mov %windowbestlen, _windowbestlen
movzwl -1(%scan, %rax), %scanend
mov dsPrev, %prev
movl _chainlenwmask, %chainlenwmask
jmp LookupLoop
/* Accept the current string, with the maximum possible length. */
LenMaximum:
movl $MAX_MATCH, %bestlend
movl %curmatchd, dsMatchStart
/* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */
/* return s->lookahead; */
LeaveNow:
movl dsLookahead, %eax
cmpl %eax, %bestlend
cmovngl %bestlend, %eax
LookaheadRet:
/* Restore the registers and return from whence we came. */
mov save_rsi, %rsi
mov save_rbx, %rbx
mov save_r12, %r12
mov save_r13, %r13
mov save_r14, %r14
mov save_r15, %r15
ret
match_init: ret
|
MZT-srcount/ToyOS | 925 | toyos/src/trap/trap.S | .altmacro
#类似define
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
#位于.text段
.section .text.trampoline
.globl __alltraps
.globl __restore
.align 2
__alltraps:
#从用户栈到用户空间中trapcontext位置，sscratch保存的是trapcontext地址,csrrw可理解为交换寄存器值,sp指向trapcontext
csrrw sp, sscratch, sp
sd x1, 1*8(sp)
sd x3, 3*8(sp)
#循环函数，保存寄存器
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
#保存用户栈栈顶地址
csrr t2, sscratch
sd t2, 2*8(sp)
#传参内核satp、trap_handler地址等
ld t0, 34*8(sp)
ld t1, 36*8(sp)
ld sp, 35*8(sp)
#进入内核虚拟空间，跳转进入trap_handler
csrw satp, t0
sfence.vma
jr t1
__restore:
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
ld sp, 2*8(sp)
sret
|
MZT-srcount/ToyOS | 17,376 | dependency/riscv/asm.S | #include "asm.h"
.section .text.__ebreak
.global __ebreak
__ebreak:
ebreak
ret
.section .text.__wfi
.global __wfi
__wfi:
wfi
ret
.section .text.__sfence_vma_all
.global __sfence_vma_all
__sfence_vma_all:
sfence.vma
ret
.section .text.__sfence_vma
.global __sfence_vma
__sfence_vma:
sfence.vma a0, a1
ret
// RISC-V hypervisor instructions.
// The switch for enabling LLVM support for asm generation.
// #define LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
.section .text.__hfence_gvma
.global __hfence_gvma
__hfence_gvma:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hfence.gvma a0, a1
#else
.word 1656029299
#endif
ret
.section .text.__hfence_vvma
.global __hfence_vvma
__hfence_vvma:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hfence.vvma a0, a1
#else
.word 582287475
#endif
ret
.section .text.__hlv_b
.global __hlv_b
__hlv_b:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.b a0, a0
#else
.word 1610958195
#endif
ret
.section .text.__hlv_bu
.global __hlv_bu
__hlv_bu:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.bu a0, a0
#else
.word 1612006771
#endif
ret
.section .text.__hlv_h
.global __hlv_h
__hlv_h:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.h a0, a0
#else
.word 1678067059
#endif
ret
.section .text.__hlv_hu
.global __hlv_hu
__hlv_hu:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.hu a0, a0
#else
.word 1679115635
#endif
ret
.section .text.__hlvx_hu
.global __hlvx_hu
__hlvx_hu:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlvx.hu a0, a0
#else
.word 1681212787
#endif
ret
.section .text.__hlv_w
.global __hlv_w
__hlv_w:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.w a0, a0
#else
.word 1745175923
#endif
ret
.section .text.__hlvx_wu
.global __hlvx_wu
__hlvx_wu:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlvx.wu a0, a0
#else
.word 1748321651
#endif
ret
.section .text.__hsv_b
.global __hsv_b
__hsv_b:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hsv.b a0, a1
#else
.word 1656045683
#endif
ret
.section .text.__hsv_h
.global __hsv_h
__hsv_h:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hsv.h a0, a1
#else
.word 1723154547
#endif
ret
.section .text.__hsv_w
.global __hsv_w
__hsv_w:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hsv.w a0, a1
#else
.word 1790263411
#endif
ret
.section .text.__hlv_wu
.global __hlv_wu
__hlv_wu:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.wu a0, a0
#else
.word 1746224499
#endif
ret
.section .text.__hlv_d
.global __hlv_d
__hlv_d:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hlv.d a0, a0
#else
.word 1812284787
#endif
ret
.section .text.__hsv_d
.global __hsv_d
__hsv_d:
#ifdef LLVM_RISCV_HYPERVISOR_EXTENSION_SUPPORT
hsv.d a0, a1
#else
.word 1857372275
#endif
ret
// User Trap Setup
RW(0x000, ustatus) // User status register
RW(0x004, uie) // User interrupt-enable register
RW(0x005, utvec) // User trap handler base address
// User Trap Handling
RW(0x040, uscratch) // Scratch register for user trap handlers
RW(0x041, uepc) // User exception program counter
RW(0x042, ucause) // User trap cause
RW(0x043, utval) // User bad address or instruction
RW(0x044, uip) // User interrupt pending
// User Floating-Point CSRs
RW(0x001, fflags) // Floating-Point Accrued Exceptions
RW(0x002, frm) // Floating-Point Dynamic Rounding Mode
RW(0x003, fcsr) // Floating-Point Control and Status Register (frm + fflags)
// User Counter/Timers
RO( 0xC00, cycle) // Cycle counter for RDCYCLE instruction
RO( 0xC01, time) // Timer for RDTIME instruction
RO( 0xC02, instret) // Instructions-retired counter for RDINSTRET instruction
RO( 0xC03, hpmcounter3) // Performance-monitoring counter
RO( 0xC04, hpmcounter4) // Performance-monitoring counter
RO( 0xC05, hpmcounter5) // Performance-monitoring counter
RO( 0xC06, hpmcounter6) // Performance-monitoring counter
RO( 0xC07, hpmcounter7) // Performance-monitoring counter
RO( 0xC08, hpmcounter8) // Performance-monitoring counter
RO( 0xC09, hpmcounter9) // Performance-monitoring counter
RO( 0xC0A, hpmcounter10) // Performance-monitoring counter
RO( 0xC0B, hpmcounter11) // Performance-monitoring counter
RO( 0xC0C, hpmcounter12) // Performance-monitoring counter
RO( 0xC0D, hpmcounter13) // Performance-monitoring counter
RO( 0xC0E, hpmcounter14) // Performance-monitoring counter
RO( 0xC0F, hpmcounter15) // Performance-monitoring counter
RO( 0xC10, hpmcounter16) // Performance-monitoring counter
RO( 0xC11, hpmcounter17) // Performance-monitoring counter
RO( 0xC12, hpmcounter18) // Performance-monitoring counter
RO( 0xC13, hpmcounter19) // Performance-monitoring counter
RO( 0xC14, hpmcounter20) // Performance-monitoring counter
RO( 0xC15, hpmcounter21) // Performance-monitoring counter
RO( 0xC16, hpmcounter22) // Performance-monitoring counter
RO( 0xC17, hpmcounter23) // Performance-monitoring counter
RO( 0xC18, hpmcounter24) // Performance-monitoring counter
RO( 0xC19, hpmcounter25) // Performance-monitoring counter
RO( 0xC1A, hpmcounter26) // Performance-monitoring counter
RO( 0xC1B, hpmcounter27) // Performance-monitoring counter
RO( 0xC1C, hpmcounter28) // Performance-monitoring counter
RO( 0xC1D, hpmcounter29) // Performance-monitoring counter
RO( 0xC1E, hpmcounter30) // Performance-monitoring counter
RO( 0xC1F, hpmcounter31) // Performance-monitoring counter
RO32(0xC80, cycleh) // Upper 32 bits of cycle, RV32I only
RO32(0xC81, timeh) // Upper 32 bits of time, RV32I only
RO32(0xC82, instreth) // Upper 32 bits of instret, RV32I only
RO32(0xC83, hpmcounter3h) // Upper 32 bits of hpmcounter3, RV32I only
RO32(0xC84, hpmcounter4h)
RO32(0xC85, hpmcounter5h)
RO32(0xC86, hpmcounter6h)
RO32(0xC87, hpmcounter7h)
RO32(0xC88, hpmcounter8h)
RO32(0xC89, hpmcounter9h)
RO32(0xC8A, hpmcounter10h)
RO32(0xC8B, hpmcounter11h)
RO32(0xC8C, hpmcounter12h)
RO32(0xC8D, hpmcounter13h)
RO32(0xC8E, hpmcounter14h)
RO32(0xC8F, hpmcounter15h)
RO32(0xC90, hpmcounter16h)
RO32(0xC91, hpmcounter17h)
RO32(0xC92, hpmcounter18h)
RO32(0xC93, hpmcounter19h)
RO32(0xC94, hpmcounter20h)
RO32(0xC95, hpmcounter21h)
RO32(0xC96, hpmcounter22h)
RO32(0xC97, hpmcounter23h)
RO32(0xC98, hpmcounter24h)
RO32(0xC99, hpmcounter25h)
RO32(0xC9A, hpmcounter26h)
RO32(0xC9B, hpmcounter27h)
RO32(0xC9C, hpmcounter28h)
RO32(0xC9D, hpmcounter29h)
RO32(0xC9E, hpmcounter30h)
RO32(0xC9F, hpmcounter31h)
// Supervisor Trap Setup
RW(0x100, sstatus) // Supervisor status register
RW(0x102, sedeleg) // Supervisor exception delegation register
RW(0x103, sideleg) // Supervisor interrupt delegation register
RW(0x104, sie) // Supervisor interrupt-enable register
RW(0x105, stvec) // Supervisor trap handler base address
RW(0x106, scounteren) // Supervisor counter enable
// Supervisor Trap Handling
RW(0x140, sscratch) // Scratch register for supervisor trap handlers
RW(0x141, sepc) // Supervisor exception program counter
RW(0x142, scause) // Supervisor trap cause
RW(0x143, stval) // Supervisor bad address or instruction
RW(0x144, sip) // Supervisor interrupt pending
// Supervisor Protection and Translation
RW(0x180, satp) // Supervisor address translation and protection
// Machine Information Registers
RO(0xF11, mvendorid) // Vendor ID
RO(0xF12, marchid) // Architecture ID
RO(0xF13, mimpid) // Implementation ID
RO(0xF14, mhartid) // Hardware thread ID
// Machine Trap Setup
RW(0x300, mstatus) // Machine status register
RW(0x301, misa) // ISA and extensions
RW(0x302, medeleg) // Machine exception delegation register
RW(0x303, mideleg) // Machine interrupt delegation register
RW(0x304, mie) // Machine interrupt-enable register
RW(0x305, mtvec) // Machine trap handler base address
RW(0x306, mcounteren) // Machine counter enable
// Machine Trap Handling
RW(0x340, mscratch) // Scratch register for machine trap handlers
RW(0x341, mepc) // Machine exception program counter
RW(0x342, mcause) // Machine trap cause
RW(0x343, mtval) // Machine bad address or instruction
RW(0x344, mip) // Machine interrupt pending
// Machine Protection and Translation
RW( 0x3A0, pmpcfg0) // Physical memory protection configuration
RW32(0x3A1, pmpcfg1) // Physical memory protection configuration, RV32 only
RW( 0x3A2, pmpcfg2) // Physical memory protection configuration
RW32(0x3A3, pmpcfg3) // Physical memory protection configuration, RV32 only
RW( 0x3B0, pmpaddr0) // Physical memory protection address register
RW( 0x3B1, pmpaddr1) // Physical memory protection address register
RW( 0x3B2, pmpaddr2) // Physical memory protection address register
RW( 0x3B3, pmpaddr3) // Physical memory protection address register
RW( 0x3B4, pmpaddr4) // Physical memory protection address register
RW( 0x3B5, pmpaddr5) // Physical memory protection address register
RW( 0x3B6, pmpaddr6) // Physical memory protection address register
RW( 0x3B7, pmpaddr7) // Physical memory protection address register
RW( 0x3B8, pmpaddr8) // Physical memory protection address register
RW( 0x3B9, pmpaddr9) // Physical memory protection address register
RW( 0x3BA, pmpaddr10) // Physical memory protection address register
RW( 0x3BB, pmpaddr11) // Physical memory protection address register
RW( 0x3BC, pmpaddr12) // Physical memory protection address register
RW( 0x3BD, pmpaddr13) // Physical memory protection address register
RW( 0x3BE, pmpaddr14) // Physical memory protection address register
RW( 0x3BF, pmpaddr15) // Physical memory protection address register
// Machine Counter/Timers
RO( 0xB00, mcycle) // Machine cycle counter
RO( 0xB02, minstret) // Machine instructions-retired counter
RO( 0xB03, mhpmcounter3) // Machine performance-monitoring counter
RO( 0xB04, mhpmcounter4) // Machine performance-monitoring counter
RO( 0xB05, mhpmcounter5) // Machine performance-monitoring counter
RO( 0xB06, mhpmcounter6) // Machine performance-monitoring counter
RO( 0xB07, mhpmcounter7) // Machine performance-monitoring counter
RO( 0xB08, mhpmcounter8) // Machine performance-monitoring counter
RO( 0xB09, mhpmcounter9) // Machine performance-monitoring counter
RO( 0xB0A, mhpmcounter10) // Machine performance-monitoring counter
RO( 0xB0B, mhpmcounter11) // Machine performance-monitoring counter
RO( 0xB0C, mhpmcounter12) // Machine performance-monitoring counter
RO( 0xB0D, mhpmcounter13) // Machine performance-monitoring counter
RO( 0xB0E, mhpmcounter14) // Machine performance-monitoring counter
RO( 0xB0F, mhpmcounter15) // Machine performance-monitoring counter
RO( 0xB10, mhpmcounter16) // Machine performance-monitoring counter
RO( 0xB11, mhpmcounter17) // Machine performance-monitoring counter
RO( 0xB12, mhpmcounter18) // Machine performance-monitoring counter
RO( 0xB13, mhpmcounter19) // Machine performance-monitoring counter
RO( 0xB14, mhpmcounter20) // Machine performance-monitoring counter
RO( 0xB15, mhpmcounter21) // Machine performance-monitoring counter
RO( 0xB16, mhpmcounter22) // Machine performance-monitoring counter
RO( 0xB17, mhpmcounter23) // Machine performance-monitoring counter
RO( 0xB18, mhpmcounter24) // Machine performance-monitoring counter
RO( 0xB19, mhpmcounter25) // Machine performance-monitoring counter
RO( 0xB1A, mhpmcounter26) // Machine performance-monitoring counter
RO( 0xB1B, mhpmcounter27) // Machine performance-monitoring counter
RO( 0xB1C, mhpmcounter28) // Machine performance-monitoring counter
RO( 0xB1D, mhpmcounter29) // Machine performance-monitoring counter
RO( 0xB1E, mhpmcounter30) // Machine performance-monitoring counter
RO( 0xB1F, mhpmcounter31) // Machine performance-monitoring counter
RO32(0xB80, mcycleh) // Upper 32 bits of mcycle, RV32I only
RO32(0xB82, minstreth) // Upper 32 bits of minstret, RV32I only
RO32(0xB83, mhpmcounter3h) // Upper 32 bits of mhpmcounter3, RV32I only
RO32(0xB84, mhpmcounter4h)
RO32(0xB85, mhpmcounter5h)
RO32(0xB86, mhpmcounter6h)
RO32(0xB87, mhpmcounter7h)
RO32(0xB88, mhpmcounter8h)
RO32(0xB89, mhpmcounter9h)
RO32(0xB8A, mhpmcounter10h)
RO32(0xB8B, mhpmcounter11h)
RO32(0xB8C, mhpmcounter12h)
RO32(0xB8D, mhpmcounter13h)
RO32(0xB8E, mhpmcounter14h)
RO32(0xB8F, mhpmcounter15h)
RO32(0xB90, mhpmcounter16h)
RO32(0xB91, mhpmcounter17h)
RO32(0xB92, mhpmcounter18h)
RO32(0xB93, mhpmcounter19h)
RO32(0xB94, mhpmcounter20h)
RO32(0xB95, mhpmcounter21h)
RO32(0xB96, mhpmcounter22h)
RO32(0xB97, mhpmcounter23h)
RO32(0xB98, mhpmcounter24h)
RO32(0xB99, mhpmcounter25h)
RO32(0xB9A, mhpmcounter26h)
RO32(0xB9B, mhpmcounter27h)
RO32(0xB9C, mhpmcounter28h)
RO32(0xB9D, mhpmcounter29h)
RO32(0xB9E, mhpmcounter30h)
RO32(0xB9F, mhpmcounter31h)
RW(0x323, mhpmevent3) // Machine performance-monitoring event selector
RW(0x324, mhpmevent4) // Machine performance-monitoring event selector
RW(0x325, mhpmevent5) // Machine performance-monitoring event selector
RW(0x326, mhpmevent6) // Machine performance-monitoring event selector
RW(0x327, mhpmevent7) // Machine performance-monitoring event selector
RW(0x328, mhpmevent8) // Machine performance-monitoring event selector
RW(0x329, mhpmevent9) // Machine performance-monitoring event selector
RW(0x32A, mhpmevent10) // Machine performance-monitoring event selector
RW(0x32B, mhpmevent11) // Machine performance-monitoring event selector
RW(0x32C, mhpmevent12) // Machine performance-monitoring event selector
RW(0x32D, mhpmevent13) // Machine performance-monitoring event selector
RW(0x32E, mhpmevent14) // Machine performance-monitoring event selector
RW(0x32F, mhpmevent15) // Machine performance-monitoring event selector
RW(0x330, mhpmevent16) // Machine performance-monitoring event selector
RW(0x331, mhpmevent17) // Machine performance-monitoring event selector
RW(0x332, mhpmevent18) // Machine performance-monitoring event selector
RW(0x333, mhpmevent19) // Machine performance-monitoring event selector
RW(0x334, mhpmevent20) // Machine performance-monitoring event selector
RW(0x335, mhpmevent21) // Machine performance-monitoring event selector
RW(0x336, mhpmevent22) // Machine performance-monitoring event selector
RW(0x337, mhpmevent23) // Machine performance-monitoring event selector
RW(0x338, mhpmevent24) // Machine performance-monitoring event selector
RW(0x339, mhpmevent25) // Machine performance-monitoring event selector
RW(0x33A, mhpmevent26) // Machine performance-monitoring event selector
RW(0x33B, mhpmevent27) // Machine performance-monitoring event selector
RW(0x33C, mhpmevent28) // Machine performance-monitoring event selector
RW(0x33D, mhpmevent29) // Machine performance-monitoring event selector
RW(0x33E, mhpmevent30) // Machine performance-monitoring event selector
RW(0x33F, mhpmevent31) // Machine performance-monitoring event selector
// Debug/Trace Registers (shared with Debug Mode)
RW(0x7A0, tselect) // Debug/Trace trigger register select
RW(0x7A1, tdata1) // First Debug/Trace trigger data register
RW(0x7A2, tdata2) // Second Debug/Trace trigger data register
RW(0x7A3, tdata3) // Third Debug/Trace trigger data register
// Debug Mode Registers
RW(0x7B0, dcsr) // Debug control and status register
RW(0x7B1, dpc) // Debug PC
RW(0x7B2, dscratch) // Debug scratch register
// Hypervisor Trap Setup
RW(0x600, hstatus) // Hypervisor status register
RW(0x602, hedeleg) // Hypervisor exception delegation register
RW(0x603, hideleg) // Hypervisor interrupt delegation register
RW(0x604, hie) // Hypervisor interrupt-enable register
RW(0x606, hcounteren) // Hypervisor counter enable
RW(0x607, hgeie) // Hypervisor guest external interrupt-enable register
// Hypervisor Trap Handling
RW(0x643, htval) // Hypervisor bad guest physical address
RW(0x644, hip) // Hypervisor interrupt pending
RW(0x645, hvip) // Hypervisor virtual interrupt pending
RW(0x64a, htinst) // Hypervisor trap instruction (transformed)
RW(0xe12, hgeip) // Hypervisor guest external interrupt pending
// Hypervisor Protection and Translation
RO(0x680, hgatp) // Hypervisor guest address translation and protection
// Debug/Trace Registers
RW(0x6a8, hcontext) // Hypervisor-mode context register
// Hypervisor Counter/Timer Virtualization Registers
RW(0x605, htimedelta) // Delta for VS/VU-mode timer
RW32(0x615, htimedeltah) // Upper 32 bits of {\tt htimedelta}, RV32 only
// Virtual Supervisor Registers
RW(0x200, vsstatus) // Virtual supervisor status register
RW(0x204, vsie) // Virtual supervisor interrupt-enable register
RW(0x205, vstvec) // Virtual supervisor trap handler base address
RW(0x240, vsscratch) // Virtual supervisor scratch register
RW(0x241, vsepc) // Virtual supervisor exception program counter
RW(0x242, vscause) // Virtual supervisor trap cause
RW(0x243, vstval) // Virtual supervisor bad address or instruction
RW(0x244, vsip) // Virtual supervisor interrupt pending
RW(0x280, vsatp) // Virtual supervisor address translation and protection
|
ncnynl/ros-car-stm32 | 12,079 | Libraries/CMSIS/startup/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 15,346 | Libraries/CMSIS/startup/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 13,758 | Libraries/CMSIS/startup/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 15,597 | Libraries/CMSIS/startup/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 12,458 | Libraries/CMSIS/startup/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 15,145 | Libraries/CMSIS/startup/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 15,398 | Libraries/CMSIS/startup/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
ncnynl/ros-car-stm32 | 13,352 | Libraries/CMSIS/startup/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
NienfengYao/armv8-bare-metal | 5,981 | vector.S | /* -*- mode: asm; coding:utf-8 -*- */
/************************************************************************/
/* OS kernel sample */
/* Copyright 2014 Takeharu KATO */
/* */
/* Exception vector */
/* */
/************************************************************************/
#define ASM_FILE 1
#include "exception.h"
.section ".text.boot"
.macro build_trapframe exc_type
/*
* store generic registers from (x29,x30) pair to (x1,x2) pair.
*/
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
stp x17, x18, [sp, #-16]!
stp x15, x16, [sp, #-16]!
stp x13, x14, [sp, #-16]!
stp x11, x12, [sp, #-16]!
stp x9, x10, [sp, #-16]!
stp x7, x8, [sp, #-16]!
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
/*
* Store (spsr, x0)
*/
mrs x21, spsr_el1
stp x21, x0, [sp, #-16]!
/*
* Allocate a room for sp_el0 and store elr
*/
mrs x21, elr_el1
stp xzr, x21, [sp, #-16]!
/*
* store exception type and esr
*/
mov x21, #(\exc_type)
mrs x22, esr_el1
stp x21, x22, [sp, #-16]!
.endm
.macro store_traped_sp
mrs x21, sp_el0
str x21, [sp, #EXC_EXC_SP_OFFSET]
.endm
.macro call_common_trap_handler
mov x0, sp
bl common_trap_handler
.endm
.macro store_nested_sp
mov x21, sp
add x21, x21, #EXC_FRAME_SIZE
str x21, [sp, #EXC_EXC_SP_OFFSET]
.endm
.macro restore_traped_sp
ldr x21, [sp, #EXC_EXC_SP_OFFSET]
msr sp_el0, x21
.endm
.macro restore_trapframe
/*
* Drop exception type, esr,
*/
add sp, sp, #16
/*
* Drop exception stack pointer and restore elr_el1
*/
ldp x21, x22, [sp], #16
msr elr_el1, x22
/*
* Retore spsr and x0
*/
ldp x21, x0, [sp], #16
msr spsr_el1, x21
/*
* Restore generic registers from (x29,x30) pair to (x1,x2) pair.
*/
ldp x1, x2, [sp], #16
ldp x3, x4, [sp], #16
ldp x5, x6, [sp], #16
ldp x7, x8, [sp], #16
ldp x9, x10, [sp], #16
ldp x11, x12, [sp], #16
ldp x13, x14, [sp], #16
ldp x15, x16, [sp], #16
ldp x17, x18, [sp], #16
ldp x19, x20, [sp], #16
ldp x21, x22, [sp], #16
ldp x23, x24, [sp], #16
ldp x25, x26, [sp], #16
ldp x27, x28, [sp], #16
ldp x29, x30, [sp], #16
eret
.endm
/*
* Exception vectors.
*/
vector_table_align
.globl vectors
vectors:
/*
* Current EL with SP0
*/
vector_entry_align
b _curr_el_sp0_sync /* Synchronous */
vector_entry_align
b _curr_el_sp0_irq /* IRQ/vIRQ */
vector_entry_align
b _curr_el_sp0_fiq /* FIQ/vFIQ */
vector_entry_align
b _curr_el_sp0_serror /* SError/vSError */
/*
* Current EL with SPx
*/
vector_entry_align
b _curr_el_spx_sync /* Synchronous */
vector_entry_align
b _curr_el_spx_irq /* IRQ/vIRQ */
vector_entry_align
b _curr_el_spx_fiq /* FIQ/vFIQ */
vector_entry_align
b _curr_el_spx_serror /* SError/vSError */
/*
* Lower EL using AArch64
*/
vector_entry_align
b _lower_el_aarch64_sync
vector_entry_align
b _lower_el_aarch64_irq
vector_entry_align
b _lower_el_aarch64_fiq
vector_entry_align
b _lower_el_aarch64_serror
/*
* Lower EL using AArch32
*/
vector_entry_align
b _lower_el_aarch32_sync
vector_entry_align
b _lower_el_aarch32_irq
vector_entry_align
b _lower_el_aarch32_fiq
vector_entry_align
b _lower_el_aarch32_serror
text_align
_curr_el_sp0_sync:
build_trapframe AARCH64_EXC_SYNC_SP0
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_curr_el_sp0_irq:
build_trapframe AARCH64_EXC_IRQ_SP0
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_curr_el_sp0_fiq:
build_trapframe AARCH64_EXC_FIQ_SP0
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_curr_el_sp0_serror:
build_trapframe AARCH64_EXC_SERR_SP0
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_curr_el_spx_sync:
build_trapframe AARCH64_EXC_SYNC_SPX
store_nested_sp
call_common_trap_handler
restore_trapframe
text_align
_curr_el_spx_irq:
build_trapframe AARCH64_EXC_IRQ_SPX
store_nested_sp
call_common_trap_handler
restore_trapframe
text_align
_curr_el_spx_fiq:
build_trapframe AARCH64_EXC_FIQ_SPX
store_nested_sp
call_common_trap_handler
restore_trapframe
text_align
_curr_el_spx_serror:
build_trapframe AARCH64_EXC_SERR_SPX
store_nested_sp
call_common_trap_handler
restore_trapframe
text_align
_lower_el_aarch64_sync:
build_trapframe AARCH64_EXC_SYNC_AARCH64
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch64_irq:
build_trapframe AARCH64_EXC_IRQ_AARCH64
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch64_fiq:
build_trapframe AARCH64_EXC_FIQ_AARCH64
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch64_serror:
build_trapframe AARCH64_EXC_SERR_AARCH64
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch32_sync:
build_trapframe AARCH64_EXC_SYNC_AARCH32
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch32_irq:
build_trapframe AARCH64_EXC_IRQ_AARCH32
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch32_fiq:
build_trapframe AARCH64_EXC_FIQ_AARCH32
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
text_align
_lower_el_aarch32_serror:
build_trapframe AARCH64_EXC_SERR_AARCH32
store_traped_sp
call_common_trap_handler
restore_traped_sp
restore_trapframe
|
Night-Traders-Dev/vOS-Kernel | 1,899 | src/Boot/boot.S | /* boot.S */
.section .text
.global _start
/* Start of the bootloader */
_start:
/* Set up the stack pointer */
ldr x0, =stack_top
mov sp, x0
/* Load the base address of the string into x0 */
ldr x0, =boot_msg
/* Write the string to the UART (serial output) */
print_boot_msg:
ldrb w2, [x0], #1 /* Load a byte from the string */
cmp w2, #0 /* Check if null byte */
b.eq boot_kernel /* If null byte, finish and jump to kernel */
/* Print bootloader message */
bl print_string /* Branch Link UART address to x3*/
strb w2, [x3] /* Write the byte to UART */
b print_boot_msg /* Loop until string is printed */
boot_kernel:
/* Print a message before jumping to kernel */
ldr x0, =jump_to_kernel_msg
bl print_string
/* Jump to the kernel entry point */
ldr x0, =kernel_entry /* Address of the kernel entry */
br x0 /* Branch to the kernel */
/* Infinite loop to halt */
end:
b end /* Hang system */
/* Function to print a string to UART */
print_string:
mov x3, #0x09000000 /* UART base address for QEMU virt machine */
print_loop:
ldrb w2, [x0], #1 /* Load a byte from the string */
cmp w2, #0 /* Check if null byte */
b.eq print_done /* If null byte, finish */
strb w2, [x3] /* Write the byte to UART */
b print_loop /* Loop to next character */
print_done:
ret
/* Data section */
.section .data
boot_msg:
.ascii "[bootloader]Boot init completed\n" /* The string to print */
jump_to_kernel_msg:
.ascii "[bootloader]Kernel init starting...\n" /* Message before jumping to kernel */
/* Stack */
.section .bss
.align 16
.stack:
.skip 0x1000 /* 4KB stack */
stack_top:
|
niltsh/mplayer-for-MPlayerX | 1,852 | loader/wrapper.S | #include "config.h"
#define GLUE(a, b) a ## b
#define JOIN(a, b) GLUE(a, b)
#define MANGLE(s) JOIN(EXTERN_ASM, s)
.data
.globl MANGLE(caller_return)
MANGLE(caller_return):
.long 0
.globl MANGLE(report_entry)
MANGLE(report_entry):
.long MANGLE(null_call)
.globl MANGLE(report_ret)
MANGLE(report_ret):
.long MANGLE(null_call)
.global MANGLE(wrapper_target)
MANGLE(wrapper_target):
.long MANGLE(null_call)
.text
.globl MANGLE(null_call)
.type MANGLE(null_call), @function
.balign 16,0x90
MANGLE(null_call):
ret
.globl MANGLE(wrapper)
.type MANGLE(wrapper), @function
.balign 16,0x90
MANGLE(wrapper):
pusha # store registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI)
pushf # store flags
push %ebp # set up a stack frame
movl %esp, %ebp
leal 4(%ebp), %eax # push flags addr
push %eax
leal 8(%ebp), %eax # push registers addr
push %eax
leal 40(%ebp), %edx
movl (%ebp), %eax
subl %edx, %eax
push %eax
push %edx
call *MANGLE(report_entry) # report entry
test %eax, %eax
jnz .Ldone
leave # restore %esp, %ebp
popf # restore flags
popa # restore registers
popl MANGLE(caller_return) # switch return addresses
pushl $.Lwrapper_return
jmp *MANGLE(wrapper_target) # wrapper_target should return at .Lwrapper_return
.balign 16, 0x90
.Lwrapper_return:
pushl MANGLE(caller_return) # restore the original return address
pusha # more for reference sake here
pushf
push %ebp # set up a stack frame
movl %esp, %ebp
leal 4(%ebp), %eax # push flags addr
push %eax
leal 8(%ebp), %eax # push registers addr
push %eax
leal 40(%ebp), %edx # push stack top address (relative to our entry)
movl (%ebp), %eax
subl %edx, %eax # calculate difference between entry and previous frame
push %eax
push %edx
call *MANGLE(report_ret) # report the return information (same args)
.Ldone:
leave
popf
popa
ret
|
niltsh/mplayer-for-MPlayerX | 7,886 | libmpeg2/motion_comp_arm_s.S | @ motion_comp_arm_s.S
@ Copyright (C) 2004 AGAWA Koji <i (AT) atty (DOT) jp>
@
@ This file is part of mpeg2dec, a free MPEG-2 video stream decoder.
@ See http://libmpeg2.sourceforge.net/ for updates.
@
@ mpeg2dec is free software; you can redistribute it and/or modify
@ it under the terms of the GNU General Public License as published by
@ the Free Software Foundation; either version 2 of the License, or
@ (at your option) any later version.
@
@ mpeg2dec is distributed in the hope that it will be useful,
@ but WITHOUT ANY WARRANTY; without even the implied warranty of
@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
@ GNU General Public License for more details.
@
@ You should have received a copy of the GNU General Public License
@ along with mpeg2dec; if not, write to the Free Software
@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
.text
@ ----------------------------------------------------------------
.align
.global MC_put_o_16_arm
MC_put_o_16_arm:
@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
pld [r1]
stmfd sp!, {r4-r11, lr} @ R14 is also called LR
and r4, r1, #3
adr r5, MC_put_o_16_arm_align_jt
add r5, r5, r4, lsl #2
ldr pc, [r5]
MC_put_o_16_arm_align0:
ldmia r1, {r4-r7}
add r1, r1, r2
pld [r1]
stmia r0, {r4-r7}
subs r3, r3, #1
add r0, r0, r2
bne MC_put_o_16_arm_align0
ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
.macro PROC shift
ldmia r1, {r4-r8}
add r1, r1, r2
mov r9, r4, lsr #(\shift)
pld [r1]
mov r10, r5, lsr #(\shift)
orr r9, r9, r5, lsl #(32-\shift)
mov r11, r6, lsr #(\shift)
orr r10, r10, r6, lsl #(32-\shift)
mov r12, r7, lsr #(\shift)
orr r11, r11, r7, lsl #(32-\shift)
orr r12, r12, r8, lsl #(32-\shift)
stmia r0, {r9-r12}
subs r3, r3, #1
add r0, r0, r2
.endm
MC_put_o_16_arm_align1:
and r1, r1, #0xFFFFFFFC
1: PROC(8)
bne 1b
ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
MC_put_o_16_arm_align2:
and r1, r1, #0xFFFFFFFC
1: PROC(16)
bne 1b
ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
MC_put_o_16_arm_align3:
and r1, r1, #0xFFFFFFFC
1: PROC(24)
bne 1b
ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
MC_put_o_16_arm_align_jt:
.word MC_put_o_16_arm_align0
.word MC_put_o_16_arm_align1
.word MC_put_o_16_arm_align2
.word MC_put_o_16_arm_align3
@ ----------------------------------------------------------------
.align
.global MC_put_o_8_arm
MC_put_o_8_arm:
@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
pld [r1]
stmfd sp!, {r4-r10, lr} @ R14 is also called LR
and r4, r1, #3
adr r5, MC_put_o_8_arm_align_jt
add r5, r5, r4, lsl #2
ldr pc, [r5]
MC_put_o_8_arm_align0:
ldmia r1, {r4-r5}
add r1, r1, r2
pld [r1]
stmia r0, {r4-r5}
add r0, r0, r2
subs r3, r3, #1
bne MC_put_o_8_arm_align0
ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
.macro PROC8 shift
ldmia r1, {r4-r6}
add r1, r1, r2
mov r9, r4, lsr #(\shift)
pld [r1]
mov r10, r5, lsr #(\shift)
orr r9, r9, r5, lsl #(32-\shift)
orr r10, r10, r6, lsl #(32-\shift)
stmia r0, {r9-r10}
subs r3, r3, #1
add r0, r0, r2
.endm
MC_put_o_8_arm_align1:
and r1, r1, #0xFFFFFFFC
1: PROC8(8)
bne 1b
ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
MC_put_o_8_arm_align2:
and r1, r1, #0xFFFFFFFC
1: PROC8(16)
bne 1b
ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
MC_put_o_8_arm_align3:
and r1, r1, #0xFFFFFFFC
1: PROC8(24)
bne 1b
ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
MC_put_o_8_arm_align_jt:
.word MC_put_o_8_arm_align0
.word MC_put_o_8_arm_align1
.word MC_put_o_8_arm_align2
.word MC_put_o_8_arm_align3
@ ----------------------------------------------------------------
.macro AVG_PW rW1, rW2
mov \rW2, \rW2, lsl #24
orr \rW2, \rW2, \rW1, lsr #8
eor r9, \rW1, \rW2
and \rW2, \rW1, \rW2
and r10, r9, r12
add \rW2, \rW2, r10, lsr #1
and r10, r9, r11
add \rW2, \rW2, r10
.endm
.align
.global MC_put_x_16_arm
MC_put_x_16_arm:
@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
pld [r1]
stmfd sp!, {r4-r11,lr} @ R14 is also called LR
and r4, r1, #3
adr r5, MC_put_x_16_arm_align_jt
ldr r11, [r5]
mvn r12, r11
add r5, r5, r4, lsl #2
ldr pc, [r5, #4]
.macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
mov \R0, \R0, lsr #(\shift)
orr \R0, \R0, \R1, lsl #(32 - \shift)
mov \R1, \R1, lsr #(\shift)
orr \R1, \R1, \R2, lsl #(32 - \shift)
mov \R2, \R2, lsr #(\shift)
orr \R2, \R2, \R3, lsl #(32 - \shift)
mov \R3, \R3, lsr #(\shift)
orr \R3, \R3, \R4, lsl #(32 - \shift)
mov \R4, \R4, lsr #(\shift)
@ and \R4, \R4, #0xFF
.endm
MC_put_x_16_arm_align0:
ldmia r1, {r4-r8}
add r1, r1, r2
pld [r1]
AVG_PW r7, r8
AVG_PW r6, r7
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r8}
subs r3, r3, #1
add r0, r0, r2
bne MC_put_x_16_arm_align0
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_16_arm_align1:
and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r8}
add r1, r1, r2
pld [r1]
ADJ_ALIGN_QW 8, r4, r5, r6, r7, r8
AVG_PW r7, r8
AVG_PW r6, r7
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r8}
subs r3, r3, #1
add r0, r0, r2
bne 1b
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_16_arm_align2:
and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r8}
add r1, r1, r2
pld [r1]
ADJ_ALIGN_QW 16, r4, r5, r6, r7, r8
AVG_PW r7, r8
AVG_PW r6, r7
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r8}
subs r3, r3, #1
add r0, r0, r2
bne 1b
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_16_arm_align3:
and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r8}
add r1, r1, r2
pld [r1]
ADJ_ALIGN_QW 24, r4, r5, r6, r7, r8
AVG_PW r7, r8
AVG_PW r6, r7
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r8}
subs r3, r3, #1
add r0, r0, r2
bne 1b
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_16_arm_align_jt:
.word 0x01010101
.word MC_put_x_16_arm_align0
.word MC_put_x_16_arm_align1
.word MC_put_x_16_arm_align2
.word MC_put_x_16_arm_align3
@ ----------------------------------------------------------------
.align
.global MC_put_x_8_arm
MC_put_x_8_arm:
@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
pld [r1]
stmfd sp!, {r4-r11,lr} @ R14 is also called LR
and r4, r1, #3
adr r5, MC_put_x_8_arm_align_jt
ldr r11, [r5]
mvn r12, r11
add r5, r5, r4, lsl #2
ldr pc, [r5, #4]
.macro ADJ_ALIGN_DW shift, R0, R1, R2
mov \R0, \R0, lsr #(\shift)
orr \R0, \R0, \R1, lsl #(32 - \shift)
mov \R1, \R1, lsr #(\shift)
orr \R1, \R1, \R2, lsl #(32 - \shift)
mov \R2, \R2, lsr #(\shift)
@ and \R4, \R4, #0xFF
.endm
MC_put_x_8_arm_align0:
ldmia r1, {r4-r6}
add r1, r1, r2
pld [r1]
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r6}
subs r3, r3, #1
add r0, r0, r2
bne MC_put_x_8_arm_align0
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_8_arm_align1:
and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r6}
add r1, r1, r2
pld [r1]
ADJ_ALIGN_DW 8, r4, r5, r6
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r6}
subs r3, r3, #1
add r0, r0, r2
bne 1b
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_8_arm_align2:
and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r6}
add r1, r1, r2
pld [r1]
ADJ_ALIGN_DW 16, r4, r5, r6
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r6}
subs r3, r3, #1
add r0, r0, r2
bne 1b
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_8_arm_align3:
and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r6}
add r1, r1, r2
pld [r1]
ADJ_ALIGN_DW 24, r4, r5, r6
AVG_PW r5, r6
AVG_PW r4, r5
stmia r0, {r5-r6}
subs r3, r3, #1
add r0, r0, r2
bne 1b
ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
MC_put_x_8_arm_align_jt:
.word 0x01010101
.word MC_put_x_8_arm_align0
.word MC_put_x_8_arm_align1
.word MC_put_x_8_arm_align2
.word MC_put_x_8_arm_align3
|
ninjadynamics/MMC3Template | 7,089 | crt0.s | ; Compile
; Startup code for cc65 and Shiru's NES library
; based on code by Groepaz/Hitmen <groepaz@gmx.net>, Ullrich von Bassewitz <uz@cc65.org>
A12_INVERSION = $80 ;must match MMC_MODE in mmc3.h
FT_BASE_ADR = $0300 ;page in RAM, should be $xx00
FT_DPCM_OFF = $c000 ;$c000..$ffc0, 64-byte steps
FT_SFX_STREAMS = 4 ;number of sound effects played at once, 1..4
FT_THREAD = 1 ;undefine if you call sound effects in the same thread as sound update
FT_PAL_SUPPORT = 0 ;undefine to exclude PAL support (either PAL or NTSC - do NOT enable both!)
FT_NTSC_SUPPORT = 1 ;undefine to exclude NTSC support (either PAL or NTSC - do NOT enable both!)
FT_DPCM_ENABLE = 0 ;undefine to exclude all DMC code
FT_SFX_ENABLE = 1 ;undefine to exclude all sound effects code
FT_BANKED_MUSIC = 1 ;undefine if there is no need for music bank switching
FT_BANKED_SFX = 1 ;undefine if there is no need for sound effects bank switching
FT_BANKED_DPCM = 0 ;undefine if there is no need for samples bank switching
;REMOVED initlib
;this called the CONDES function
.export _exit,__STARTUP__:absolute=1
.import push0,popa,popax,_main,zerobss,copydata
; Linker generated symbols
.import __STACK_START__ ,__STACKSIZE__ ;changed
.import __ROM0_START__ ,__ROM0_SIZE__
.import __STARTUP_LOAD__,__STARTUP_RUN__,__STARTUP_SIZE__
.import __CODE_LOAD__ ,__CODE_RUN__ ,__CODE_SIZE__
.import __RODATA_LOAD__ ,__RODATA_RUN__ ,__RODATA_SIZE__
.import NES_MAPPER, NES_PRG_BANKS, NES_CHR_BANKS, NES_MIRRORING, NES_BATTERY
.importzp _PAD_STATE, _PAD_STATET ;added
.include "zeropage.inc"
PPU_CTRL =$2000
PPU_MASK =$2001
PPU_STATUS =$2002
PPU_OAM_ADDR =$2003
PPU_OAM_DATA =$2004
PPU_SCROLL =$2005
PPU_ADDR =$2006
PPU_DATA =$2007
PPU_OAM_DMA =$4014
PPU_FRAMECNT =$4017
DMC_FREQ =$4010
CTRL_PORT1 =$4016
CTRL_PORT2 =$4017
OAM_BUF =$0200
PAL_BUF =$01A0
MMC3_BNKSEL =$8000
MMC3_BNKVAL =$8001
MMC3_MIRROR =$A000
.segment "ZEROPAGE"
NTSC_MODE: .res 1
FRAME_CNT1: .res 1
FRAME_CNT2: .res 1
VRAM_UPDATE: .res 1
NAME_UPD_ADR: .res 2
NAME_UPD_ENABLE: .res 1
PAL_UPDATE: .res 1
PAL_BG_PTR: .res 2
PAL_SPR_PTR: .res 2
SCROLL_X: .res 1
SCROLL_Y: .res 1
SCROLL_X1: .res 1
SCROLL_Y1: .res 1
PAD_STATE: .res 2 ;one byte per controller
PAD_STATEP: .res 2
PAD_STATET: .res 2
PPU_CTRL_VAR: .res 1
PPU_CTRL_VAR1: .res 1
PPU_MASK_VAR: .res 1
RAND_SEED: .res 2
FT_TEMP: .res 3
TEMP: .res 11
SPRID: .res 1
PAD_BUF =TEMP+1
PTR =TEMP ;word
LEN =TEMP+2 ;word
NEXTSPR =TEMP+4
SCRX =TEMP+5
SCRY =TEMP+6
SRC =TEMP+7 ;word
DST =TEMP+9 ;word
RLE_LOW =TEMP
RLE_HIGH =TEMP+1
RLE_TAG =TEMP+2
RLE_BYTE =TEMP+3
NMICallback: .res 3
.exportzp NMICallback
.segment "HEADER"
.byte $4e,$45,$53,$1a
.byte <NES_PRG_BANKS
.byte <NES_CHR_BANKS
.byte <NES_MIRRORING|(<NES_MAPPER<<4)|(<NES_BATTERY<<1)
.byte <NES_MAPPER&$f0
.res 8,0
.segment "STARTUP"
start:
_exit:
sei
cld
ldx #$40
stx CTRL_PORT2
ldx #$ff
txs
inx
stx PPU_MASK
stx DMC_FREQ
stx PPU_CTRL ;no NMI
initMMC:
; MMC3 initialization (NROM-like mapping)
; https://forums.nesdev.com/viewtopic.php?p=209344#p209344
; set mirroring
lda #$00 ; 0->vertical, 1->horizontal
sta MMC3_MIRROR
; disable IRQ
sta $E000
; enable Work RAM
lda #$80
sta $A001
; PRG banking setup (8 kB banks)
lda #6 ; select R6 (used as a swappable data bank)
sta MMC3_BNKSEL
lda #0 ; set R6 to bank 0
sta MMC3_BNKVAL
lda #7 ; select R7 (used as a swappable code bank)
sta MMC3_BNKSEL ; bank select
lda #1 ; set R7 to bank 1 (it doesn't really matter at this point)
sta $8001
; CHR banking setup (1 kB banks)
lda #0 ; select R0
sta MMC3_BNKSEL ; bank select
lda #0 ; R0 -> bank 0 (banks 0 + 1)
sta MMC3_BNKVAL
lda #1 ; select R1
sta MMC3_BNKSEL ; bank select
lda #2 ; R1 -> bank 2 (banks 2 + 3)
sta MMC3_BNKVAL
lda #2 ; select R2
sta MMC3_BNKSEL ; bank select
lda #4 ; R2 -> bank 4
sta MMC3_BNKVAL
lda #4 ; select R3
sta MMC3_BNKSEL ; bank select
lda #5 ; R3 -> bank 5
sta MMC3_BNKVAL
lda #4 ; select R4
sta MMC3_BNKSEL ; bank select
lda #6 ; R4 -> bank 6
sta MMC3_BNKVAL
lda #5 ; select R5
sta MMC3_BNKSEL ; bank select
lda #7 ; R5 -> bank 7
sta MMC3_BNKVAL
initPPU:
bit PPU_STATUS
@1:
bit PPU_STATUS
bpl @1
@2:
bit PPU_STATUS
bpl @2
clearPalette:
lda #$3f
sta PPU_ADDR
stx PPU_ADDR
lda #$0f
ldx #$20
@1:
sta PPU_DATA
dex
bne @1
clearVRAM:
txa
ldy #$20
sty PPU_ADDR
sta PPU_ADDR
ldy #$10
@1:
sta PPU_DATA
inx
bne @1
dey
bne @1
clearRAM:
txa
@1:
sta $000,x
sta $100,x
sta $200,x
sta $300,x
sta $400,x
sta $500,x
sta $600,x
sta $700,x
inx
bne @1
lda #4
jsr _pal_bright
jsr _pal_clear
jsr _oam_clear
jsr zerobss
jsr copydata
lda #<(__STACK_START__+__STACKSIZE__) ;changed
sta sp
lda #>(__STACK_START__+__STACKSIZE__)
sta sp+1 ; Set argument stack ptr
; setup NMICallback trampoline to NOP
;lda #$4C ;JMP xxxx
;sta NMICallback
;lda #<HandyRTS
;sta NMICallback+1
;lda #>HandyRTS
;sta NMICallback+2
jsr _nmi_clear_callback
; N BS
lda #%10001000 ;enable NMI, bg @ bank 0, sprites @ bank 1
sta <PPU_CTRL_VAR
sta PPU_CTRL
lda #%00000110
sta <PPU_MASK_VAR
waitSync3:
lda <FRAME_CNT1
@1:
cmp <FRAME_CNT1
beq @1
detectNTSC:
ldx #52 ;blargg's code
ldy #24
@1:
dex
bne @1
dey
bne @1
lda PPU_STATUS
and #$80
sta <NTSC_MODE
jsr _ppu_off
lda #0
ldx #0
jsr _set_vram_update
ldx #<music_data
ldy #>music_data
lda <NTSC_MODE
jsr FamiToneInit
.if(FT_SFX_ENABLE)
ldx #<sounds_data
ldy #>sounds_data
jsr FamiToneSfxInit
.endif
lda #$fd
sta <RAND_SEED
sta <RAND_SEED+1
lda #0
sta PPU_SCROLL
sta PPU_SCROLL
jmp _main ;no parameters
.include "neslib.s"
.include "famitone2.s"
.segment "RODATA"
music_data:
.include "music.s"
.if(FT_SFX_ENABLE)
sounds_data:
.include "sounds.s"
.endif
.segment "SAMPLES"
; .incbin "music_dpcm.bin"
.segment "VECTORS"
.word nmi ;$fffa vblank nmi
.word start ;$fffc reset
.word irq ;$fffe irq / brk
.segment "CHARS"
.include "chr_default.s" |
ninjadynamics/MMC3Template | 5,476 | sfx.s | ;this file for FamiTone2 libary generated by nsf2data tool
.export _demo_sounds
_demo_sounds:
.word @ntsc
@ntsc:
.word @sfx_ntsc_0
.word @sfx_ntsc_1
.word @sfx_ntsc_2
.word @sfx_ntsc_3
.word @sfx_ntsc_4
.word @sfx_ntsc_5
.word @sfx_ntsc_6
.word @sfx_ntsc_7
.word @sfx_ntsc_8
.word @sfx_ntsc_9
.word @sfx_ntsc_a
.word @sfx_ntsc_b
@sfx_ntsc_0: ;open
.byte $85,$04,$84,$b3,$83,$ff,$8a,$0a,$89,$3f,$01,$84,$f3,$8a,$0b,$01
.byte $85,$05,$84,$32,$89,$f0,$01,$83,$f0,$01,$85,$01,$84,$07,$83,$f8
.byte $8a,$09,$89,$37,$01,$84,$2d,$8a,$08,$89,$3f,$01,$84,$53,$8a,$07
.byte $01,$84,$79,$8a,$06,$01,$84,$9f,$8a,$05,$01,$84,$c5,$8a,$04,$01
.byte $84,$eb,$8a,$03,$01,$85,$02,$84,$11,$8a,$02,$01,$84,$37,$8a,$01
.byte $01,$84,$5c,$8a,$00,$01,$8a,$0f,$01,$83,$f0,$00
@sfx_ntsc_1: ;close
.byte $85,$04,$84,$b3,$83,$ff,$8a,$0a,$89,$3f,$01,$84,$f3,$8a,$0b,$01
.byte $85,$05,$84,$32,$8a,$0c,$01,$83,$f0,$8a,$0d,$01,$85,$06,$84,$ec
.byte $83,$f8,$8a,$0e,$89,$37,$01,$85,$07,$84,$2c,$8a,$0f,$89,$3f,$01
.byte $84,$6b,$01,$84,$ab,$01,$83,$f0,$00
@sfx_ntsc_2: ;kill
.byte $89,$3f,$8a,$0d,$01,$8a,$0b,$01,$8a,$09,$01,$8a,$07,$01,$8a,$05
.byte $01,$8a,$03,$01,$89,$3e,$8a,$01,$01,$8a,$0f,$01,$8a,$0d,$01,$8a
.byte $0b,$01,$89,$3d,$8a,$09,$01,$8a,$07,$01,$8a,$05,$01,$8a,$03,$01
.byte $89,$3c,$8a,$01,$01,$8a,$0f,$01,$8a,$0d,$01,$8a,$0b,$01,$89,$3b
.byte $8a,$09,$01,$8a,$07,$01,$8a,$05,$01,$8a,$03,$01,$89,$3a,$8a,$01
.byte $01,$8a,$0f,$01,$8a,$0d,$01,$8a,$0b,$01,$89,$39,$8a,$09,$01,$8a
.byte $07,$01,$8a,$05,$01,$8a,$03,$01,$89,$38,$8a,$01,$01,$8a,$0f,$01
.byte $8a,$0d,$01,$8a,$0b,$01,$89,$37,$8a,$09,$01,$8a,$07,$01,$8a,$05
.byte $01,$8a,$03,$01,$89,$36,$8a,$01,$01,$8a,$0f,$01,$8a,$0d,$01,$8a
.byte $0b,$01,$89,$35,$8a,$09,$01,$8a,$07,$01,$8a,$05,$01,$8a,$03,$01
.byte $89,$34,$8a,$01,$01,$8a,$0f,$01,$8a,$0d,$01,$8a,$0b,$01,$89,$33
.byte $8a,$09,$01,$8a,$07,$01,$8a,$05,$01,$8a,$03,$01,$89,$32,$8a,$01
.byte $01,$8a,$0f,$01,$8a,$0d,$01,$8a,$0b,$01,$89,$31,$8a,$09,$01,$8a
.byte $07,$01,$8a,$05,$01,$8a,$03,$01,$8a,$01,$01,$8a,$0f,$01,$8a,$0d
.byte $01,$00
@sfx_ntsc_3: ;splash
.byte $8a,$02,$89,$3f,$01,$8a,$08,$89,$3e,$01,$8a,$01,$89,$3f,$01,$8a
.byte $07,$89,$3e,$01,$8a,$0c,$89,$3d,$01,$8a,$01,$89,$3b,$01,$8a,$06
.byte $89,$39,$01,$8a,$07,$89,$3b,$01,$8a,$06,$89,$3e,$01,$8a,$08,$89
.byte $3f,$01,$89,$3e,$01,$89,$3d,$01,$89,$3f,$01,$8a,$07,$89,$3e,$01
.byte $89,$3f,$02,$89,$3e,$01,$8a,$06,$89,$3d,$01,$89,$3c,$01,$89,$3a
.byte $01,$89,$38,$01,$8a,$05,$89,$37,$01,$89,$36,$01,$89,$35,$01,$89
.byte $34,$01,$8a,$04,$89,$33,$01,$89,$32,$01,$89,$31,$02,$8a,$03,$01
.byte $00
@sfx_ntsc_4: ;jump
.byte $82,$02,$81,$3a,$80,$3f,$87,$3a,$88,$02,$86,$8f,$8a,$0f,$89,$3f
.byte $01,$81,$1a,$87,$1a,$8a,$0e,$01,$80,$30,$86,$80,$89,$f0,$01,$82
.byte $01,$81,$c4,$80,$3f,$87,$c4,$88,$01,$86,$8f,$8a,$0b,$89,$3f,$01
.byte $82,$02,$81,$a6,$87,$a6,$88,$02,$8a,$02,$01,$80,$30,$86,$80,$00
@sfx_ntsc_5: ;menu cursor move
.byte $85,$00,$84,$5e,$83,$7f,$89,$f0,$02,$84,$4f,$02,$84,$3b,$02,$84
.byte $4f,$01,$00
@sfx_ntsc_6: ;menu select option
.byte $85,$01,$84,$ab,$83,$3d,$89,$f0,$02,$84,$0c,$83,$7d,$02,$85,$00
.byte $84,$d5,$02,$84,$a9,$02,$00
@sfx_ntsc_7: ;summon attack
.byte $8a,$03,$89,$3f,$01,$8a,$04,$01,$8a,$05,$01,$8a,$06,$01,$8a,$07
.byte $02,$8a,$08,$01,$8a,$09,$01,$8a,$0a,$02,$8a,$0f,$01,$8a,$00,$01
.byte $8a,$01,$01,$8a,$02,$01,$8a,$03,$01,$8a,$04,$01,$8a,$05,$01,$8a
.byte $06,$01,$8a,$07,$01,$8a,$08,$01,$8a,$03,$01,$8a,$04,$01,$8a,$05
.byte $01,$8a,$06,$01,$8a,$07,$01,$8a,$08,$01,$8a,$09,$01,$8a,$0a,$01
.byte $8a,$0c,$02,$8a,$01,$01,$8a,$02,$01,$8a,$03,$01,$8a,$04,$01,$8a
.byte $06,$01,$8a,$07,$01,$8a,$08,$01,$8a,$09,$01,$8a,$0b,$02,$8a,$04
.byte $01,$8a,$05,$01,$8a,$06,$01,$8a,$07,$01,$8a,$09,$01,$8a,$0a,$01
.byte $8a,$0b,$01,$8a,$0c,$01,$8a,$0e,$02,$8a,$01,$01,$8a,$02,$01,$8a
.byte $03,$01,$8a,$04,$01,$8a,$05,$02,$8a,$06,$01,$8a,$07,$01,$8a,$08
.byte $01,$8a,$09,$02,$8a,$0a,$02,$89,$f0,$01,$8a,$03,$89,$3f,$01,$8a
.byte $04,$01,$8a,$05,$02,$8a,$06,$01,$8a,$07,$02,$8a,$08,$01,$8a,$09
.byte $02,$8a,$0a,$01,$8a,$0b,$03,$89,$f0,$01,$8a,$07,$89,$3f,$04,$8a
.byte $08,$04,$8a,$09,$04,$8a,$0a,$04,$8a,$0b,$04,$8a,$0c,$04,$8a,$0d
.byte $04,$8a,$0e,$04,$8a,$0f,$09,$00
@sfx_ntsc_8: ;charge
.byte $8a,$0e,$89,$3f,$03,$8a,$0d,$04,$8a,$0c,$04,$8a,$0b,$04,$8a,$0a
.byte $04,$8a,$09,$04,$8a,$08,$04,$8a,$07,$04,$8a,$06,$04,$8a,$05,$04
.byte $8a,$04,$03,$89,$3e,$01,$8a,$03,$01,$89,$3d,$02,$89,$3c,$01,$8a
.byte $02,$01,$89,$3b,$02,$89,$3a,$01,$8a,$01,$01,$89,$39,$02,$89,$38
.byte $01,$8a,$00,$01,$89,$37,$02,$89,$36,$02,$89,$35,$02,$89,$34,$03
.byte $89,$33,$04,$89,$32,$03,$89,$31,$05,$00
@sfx_ntsc_9: ;bling
.byte $82,$00,$81,$d5,$80,$7f,$89,$f0,$01,$80,$3e,$01,$80,$30,$03,$80
.byte $7f,$01,$80,$3e,$01,$80,$30,$05,$81,$8e,$80,$7f,$01,$80,$3e,$01
.byte $80,$30,$06,$81,$6a,$80,$7f,$01,$80,$3e,$01,$80,$3a,$01,$80,$38
.byte $01,$80,$36,$01,$00
@sfx_ntsc_a: ;exposion
.byte $8a,$06,$89,$3f,$02,$8a,$07,$02,$8a,$08,$02,$8a,$09,$02,$8a,$0a
.byte $02,$8a,$0b,$02,$8a,$0c,$02,$8a,$0d,$02,$8a,$0e,$02,$8a,$0f,$35
.byte $89,$3e,$01,$89,$3d,$01,$89,$3c,$01,$89,$3b,$01,$89,$3a,$01,$89
.byte $38,$01,$89,$36,$01,$89,$34,$01,$89,$31,$01,$00
@sfx_ntsc_b: ;coin
.byte $82,$00,$81,$38,$80,$3f,$89,$f0,$04,$81,$29,$09,$80,$3e,$05,$80
.byte $3d,$03,$80,$3c,$02,$80,$3b,$02,$80,$3a,$01,$80,$39,$01,$80,$38
.byte $01,$80,$37,$01,$80,$35,$01,$00
|
ninjadynamics/MMC3Template | 15,141 | music_shatterhand.s | ; This file for the FamiTone2 library and was generated by FamiStudio
_shatterhand_music_data:
.byte 1
.word @instruments
.word @samples-3
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256
@instruments:
.byte $30 ;instrument 00 (Bass)
.word @env5, @env1, @env1
.byte $00
.byte $30 ;instrument 01 (BassDrum)
.word @env10, @env4, @env1
.byte $00
.byte $30 ;instrument 02 (CymbalHigh)
.word @env3, @env9, @env1
.byte $00
.byte $30 ;instrument 03 (CymbalLow)
.word @env8, @env7, @env1
.byte $00
.byte $30 ;instrument 04 (Lead-Duty0)
.word @env6, @env1, @env0
.byte $00
.byte $70 ;instrument 05 (Lead-Duty1)
.word @env6, @env1, @env0
.byte $00
.byte $b0 ;instrument 06 (Lead-Duty2)
.word @env6, @env1, @env0
.byte $00
.byte $30 ;instrument 07 (Snare)
.word @env2, @env9, @env1
.byte $00
@samples:
@env0:
.byte $c0,$08,$c0,$04,$bd,$03,$bd,$00,$02
@env1:
.byte $c0,$7f,$00,$00
@env2:
.byte $ca,$c6,$c3,$c0,$00,$03
@env3:
.byte $cb,$ca,$09,$c9,$00,$03
@env4:
.byte $c0,$bf,$c1,$00,$02
@env5:
.byte $cf,$7f,$00,$00
@env6:
.byte $c8,$c9,$c5,$00,$02
@env7:
.byte $c0,$c2,$c5,$00,$02
@env8:
.byte $cb,$cb,$c5,$03,$c4,$03,$c3,$03,$c2,$00,$08
@env9:
.byte $c0,$c1,$c2,$00,$02
@env10:
.byte $cf,$ca,$c3,$c2,$c0,$00,$04
@song0ch0:
.byte $fb, $01
@song0ch0loop:
.byte $88
@song0ref5:
.byte $2c, $a1, $32, $8d, $2c, $2c, $a1, $36, $8d, $2c, $2c, $a1, $3c, $8d, $2c, $2c, $a1, $3a, $a1, $36, $8d, $3a, $32, $8d
.byte $36, $28, $8d, $32
.byte $ff, $1c
.word @song0ref5
.byte $00, $32, $8d, $4e, $8d, $28, $4a, $8d, $4e, $40, $8d, $4a, $4e, $8d, $40, $4a, $8d, $4e, $40, $8d, $4a, $36, $8d, $40
.byte $32, $8d, $36, $28, $8d, $32, $3a, $8d, $28, $32, $8d, $3a, $28, $8d, $32, $22, $8d, $28
@song0ref78:
.byte $28, $8d, $22, $2c, $8d, $28, $4e, $8d, $2c, $00, $2c, $8d, $3c, $8d, $4e, $00, $4e
@song0ref95:
.byte $8d, $3c, $8f, $40, $8d, $3c, $00, $3c, $8d, $40, $8f, $3a, $8d, $40, $00, $40, $8d, $3a, $8f, $3c, $8d, $3a, $00, $3a
.byte $8d, $36, $b3, $3a, $8d, $36, $00, $36, $8d, $32, $8d, $3a, $36, $d7, $00, $36, $8d, $22, $8d, $36, $28, $8d, $22, $2c
.byte $8d, $28, $36, $8d, $2c, $32, $8d, $36, $28, $8d, $32, $2c, $8d, $28, $00, $28, $8d, $2c, $8f, $3c, $8d, $2c, $00, $2c
.byte $ff, $43
.word @song0ref95
.byte $8a
@song0ref171:
.byte $46, $b3, $4a, $8d, $46, $4e, $8d, $4a, $52, $8d, $4e, $54, $a1, $58, $8d, $54, $54, $8d, $58, $00, $58, $8d, $4c, $b3
.byte $46, $c5, $52, $93, $46, $4e, $93, $52, $4c, $93, $4e, $4e, $a1, $44, $8d, $4e, $54, $a1, $52, $8d, $54, $4e, $8d, $52
.byte $4a, $8d, $4e, $00, $4e, $8d, $4a, $8f
.byte $ff, $0b
.word @song0ref171
.byte $4a, $a1, $4e, $8d, $4a, $52, $8d, $4e, $00, $4e, $8d, $54, $b3, $58, $c5, $58, $8f, $5c, $8d, $58, $62, $8d, $5c, $58
.byte $8d, $62, $00, $62, $8d, $88, $3c, $8d, $58, $3a, $8d, $3c, $32, $8d, $3a, $24, $8d, $32, $22, $8d, $24
.byte $ff, $59
.word @song0ref78
.byte $ff, $43
.word @song0ref95
.byte $4a, $a1, $4a, $8f, $4e, $8d, $4a, $52, $8d, $4e, $52, $b3, $52, $8f, $4e, $8d, $52, $00, $52, $8d, $4c, $b3, $4e, $c5
.byte $4e, $8f, $52, $8d, $4e, $54, $8d, $52, $58, $b3, $54, $8d, $58, $52, $8d, $54, $00, $54, $8d, $4e, $b3, $00, $4e, $9f
@song0ref329:
.byte $52, $a1, $52, $8f, $54, $8d, $52, $58, $8d, $54, $5c, $b3, $58, $8d, $5c, $54, $8d, $58, $00, $58, $8d, $58, $8d, $54
.byte $54, $8d, $58, $52, $8d, $54, $4c, $c5, $4e, $c5, $52, $8d, $4e, $52, $8f, $00, $52, $8d, $52, $d7, $5c, $8d, $52
@song0ref376:
.byte $4e, $8d, $5c, $44, $8d, $4e, $58, $8d, $44, $4a, $8d, $58, $40, $8d, $4a, $3c, $a1, $00, $3c, $8d, $3c, $8f, $3a, $8d
.byte $3c, $32, $8d, $3a, $3c, $8d, $32, $3a, $8d, $3c, $32, $8d, $3a, $36, $8d, $32, $3c, $8d, $36, $3c, $8f, $00, $3c, $8d
.byte $40, $8d, $3c, $40, $8f, $00, $40, $8d, $3c, $8d, $40, $3c, $8f, $00, $3c, $8d, $40, $89, $41, $3c, $40, $8f, $00, $40
.byte $8d, $4e, $8d, $40, $4a, $8d, $4e, $46, $8d, $4a, $44, $8d, $46, $5c, $8d, $44
.byte $ff, $55
.word @song0ref376
.byte $2e, $a1, $3c, $8d, $2e, $32, $a1, $40, $a1, $36, $a1, $44, $a1, $52, $8d, $44, $54, $8d, $52, $8f, $54, $4e, $8d, $52
.byte $4a, $8d, $4e, $54, $8d, $4a, $54, $8f, $00, $54, $8d, $52, $8d, $54, $52, $8f, $00, $52, $8d, $54, $8d, $52, $54, $8f
.byte $00, $54, $8d, $22, $8d, $54, $2c, $8d, $22, $3a, $8d, $2c, $4a, $8d, $3a, $52, $b3, $fd
.word @song0ch0loop
@song0ch1:
@song0ch1loop:
.byte $8a
@song0ref537:
.byte $36, $a1, $3c, $8d, $36, $36, $a1, $40, $8d, $36, $36, $a1, $44, $8d, $36, $36, $a1, $40, $a1, $3c, $8d, $40, $3a, $8d
.byte $3c, $32, $8d, $3a
.byte $ff, $1c
.word @song0ref537
.byte $00, $3a, $8d, $54, $8d, $32
@song0ref574:
.byte $52, $8d, $54, $4a, $8d, $52, $54, $8d, $4a
@song0ref583:
.byte $52, $8d, $54, $4a, $8d, $52, $3c, $8d, $4a, $3a, $8d, $3c, $32, $8d, $3a, $40, $8d, $32, $3a, $8d, $40, $32, $8d, $3a
.byte $2c, $8d, $32, $32, $8d, $2c
@song0ref613:
.byte $36, $8d, $32, $66, $8d, $36, $00, $36, $8d, $44, $8d, $66, $00, $66
@song0ref627:
.byte $8d, $44, $8f, $46, $8d, $44, $00, $44, $8d, $46, $8f, $40, $8d, $46, $00, $46, $8d, $40, $8f, $44, $8d, $40, $00, $40
.byte $8d, $3c, $b3, $40, $8d, $3c, $00, $3c, $8d, $3a, $8d, $40, $3c, $d7, $00, $3c, $8d, $2c, $8d, $3c, $32, $8d, $2c, $36
.byte $8d, $32, $3c, $8d, $36, $3a, $8d, $3c, $32, $8d, $3a, $36, $8d, $32, $00, $32, $8d, $36, $8f, $44, $8d, $36, $00, $36
.byte $ff, $43
.word @song0ref627
.byte $8c
@song0ref703:
.byte $4e, $b3, $52, $8d, $4e, $54, $8d, $52, $58, $8d, $54, $5c, $a1, $5e, $8d, $5c, $5c, $8d, $5e, $00, $5e, $8d, $52, $b3
.byte $58, $c5, $58, $95, $54, $93, $58, $52, $93, $54, $54, $a1, $4e, $8d, $54, $5c, $d7, $00, $5c, $9f
.byte $ff, $10
.word @song0ref703
.byte $62, $8d, $5e, $00, $5e, $8d, $66, $b3, $6a, $c5, $6a, $8f, $6c, $8d, $6a, $70, $8d, $6c, $6a, $8d, $70, $00, $70, $8d
.byte $8a, $54, $8d, $6a
.byte $ff, $0f
.word @song0ref583
.byte $ff, $56
.word @song0ref613
.byte $ff, $43
.word @song0ref627
.byte $ff, $15
.word @song0ref329
.byte $52, $b3, $54, $c5, $54, $8f, $58, $8d, $54, $5c, $8d, $58, $5e, $b3, $5c, $8d, $5e, $58, $8d, $5c, $00, $5c, $8d, $54
.byte $b3, $00, $54, $9f, $58, $a1, $58, $8f, $5c, $8d, $58, $5e, $8d, $5c, $62, $b3, $5e, $8d, $62, $5c, $8d, $5e, $00, $5e
.byte $8d, $5e, $8d, $5c, $5c, $8d, $5e, $58, $8d, $5c, $5c, $c5, $60, $c5, $62, $8d, $60, $62, $8f, $00, $62, $8d, $64, $d7
.byte $66, $8d, $64
@song0ref865:
.byte $5c, $8d, $66, $4e, $8d, $5c, $62, $8d, $4e, $58, $8d, $62, $4a, $8d, $58, $46, $a1, $00, $46, $8d, $54, $8d, $46
.byte $ff, $0f
.word @song0ref574
@song0ref891:
.byte $4e, $8d, $4a, $46, $8d, $4e, $46, $8f, $00, $46, $8d, $4a, $8d, $46, $4a, $8f, $00, $4a, $8d, $4e, $8d, $4a, $4e, $8f
.byte $00, $4e, $8d, $52, $8d, $4e, $52, $8f, $00, $52, $8d, $54, $8d, $52, $52, $8d, $54, $4e, $8d, $52, $4a, $8d, $4e, $66
.byte $8d, $4a
.byte $ff, $17
.word @song0ref865
.byte $ff, $0f
.word @song0ref574
.byte $ff, $2f
.word @song0ref891
.byte $46, $a1, $54, $8d, $46, $4a, $a1, $58, $a1, $4e, $a1, $5c, $a1, $6a, $8d, $5c, $6c, $8d, $6a, $6a, $8d, $6c, $66, $8d
.byte $6a, $62, $8d, $66, $66, $8d, $62, $66, $8f, $00, $66, $8d, $62, $8d, $66, $62, $8f, $00, $62, $8d, $66, $8d, $62, $66
.byte $8f, $00, $66, $8d, $2c, $8d, $66, $3a, $8d, $2c, $44, $8d, $3a, $52, $8d, $44, $5c, $b3, $fd
.word @song0ch1loop
@song0ch2:
@song0ch2loop:
.byte $80
@song0ref1021:
.byte $36, $8b, $01, $36, $8b, $01, $36, $8b, $01, $36, $8b, $01
.byte $ff, $0c
.word @song0ref1021
@song0ref1036:
.byte $36, $8b, $01, $36, $8b, $01, $36, $8b, $01, $32, $9d, $01, $2c, $8b, $01, $32, $8b, $01, $3a, $8b, $00, $81
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $16
.word @song0ref1036
.byte $32, $f7, $01, $32, $d3, $01, $32, $8b, $01, $2c, $8b, $01, $32, $8b, $01, $36, $8b, $00, $81
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0b
.word @song0ref1021
.byte $00, $81
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
@song0ref1106:
.byte $36
@song0ref1107:
.byte $8b, $01, $2c, $8b, $01, $32, $8b, $01, $36, $8b, $01, $3c, $8b, $01, $3a, $8b, $01, $32, $8b, $01, $36, $8b
@song0ref1129:
.byte $00, $81
@song0ref1131:
.byte $2e
@song0ref1132:
.byte $8b, $01, $2e, $8b, $01, $2e, $8b, $01, $2e, $8b, $01
.byte $ff, $0c
.word @song0ref1131
.byte $ff, $0c
.word @song0ref1131
.byte $ff, $0b
.word @song0ref1131
.byte $ff, $0e
.word @song0ref1129
.byte $ff, $0c
.word @song0ref1131
.byte $2e
.byte $ff, $18
.word @song0ref1107
@song0ref1162:
.byte $28, $8b, $01, $28, $8b, $01, $36, $8b, $01, $3c, $8b, $01
.byte $ff, $0c
.word @song0ref1162
@song0ref1177:
.byte $2c, $8b, $01, $2c, $8b, $01, $3a, $8b, $01, $40, $8b, $01
.byte $ff, $0b
.word @song0ref1177
.byte $00, $81
.byte $ff, $0c
.word @song0ref1162
.byte $ff, $0c
.word @song0ref1177
@song0ref1200:
.byte $36, $8b, $01, $36, $8b, $01, $32, $8b, $01, $32, $8b, $01, $2e, $8b, $01, $2e, $8b, $01, $2c, $8b, $01, $2c, $8b, $00
.byte $81
.byte $ff, $0c
.word @song0ref1162
.byte $ff, $0c
.word @song0ref1162
.byte $ff, $0c
.word @song0ref1177
.byte $ff, $0b
.word @song0ref1177
.byte $00, $81, $2e, $8b, $01, $2e, $8b, $01, $3c, $8b, $01, $46, $8b, $01, $2e, $8b, $01, $3c, $8b, $01, $46, $8b, $01, $32
.byte $8b, $00, $93, $32, $8b, $01, $32, $9d, $01, $32, $8b, $01, $32, $9d, $01, $36, $8b, $00, $81
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0b
.word @song0ref1021
.byte $00, $81
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $25
.word @song0ref1106
.byte $ff, $0c
.word @song0ref1131
.byte $ff, $0c
.word @song0ref1131
.byte $ff, $0b
.word @song0ref1131
.byte $ff, $0e
.word @song0ref1129
.byte $ff, $0c
.word @song0ref1131
.byte $2e
.byte $ff, $18
.word @song0ref1107
@song0ref1322:
.byte $32
@song0ref1323:
.byte $8b, $01, $32, $8b, $01, $32, $8b, $01, $32, $8b, $01
.byte $ff, $0c
.word @song0ref1322
@song0ref1337:
.byte $34, $8b, $01, $34, $8b, $01, $34, $8b, $01, $34, $8b, $01
.byte $ff, $0b
.word @song0ref1337
.byte $00, $81
.byte $ff, $0c
.word @song0ref1021
.byte $ff, $0c
.word @song0ref1021
@song0ref1360:
.byte $38, $8b, $01, $38, $8b, $01, $38, $8b, $01, $38, $8b, $01
.byte $ff, $0b
.word @song0ref1360
.byte $00, $81
@song0ref1377:
.byte $3a, $8b, $01, $3a, $8b, $01, $3a, $8b, $01, $3a, $8b, $01
.byte $ff, $0c
.word @song0ref1377
.byte $ff, $0c
.word @song0ref1322
.byte $ff, $0b
.word @song0ref1322
.byte $00, $81
@song0ref1400:
.byte $2c
@song0ref1401:
.byte $8b, $01, $2c, $8b, $01, $2c, $8b, $01, $2c, $8b, $01
.byte $ff, $0c
.word @song0ref1400
.byte $2c, $8b, $01, $2c, $8b, $01, $3a, $8b, $01, $44, $9d, $01, $44, $8b, $01, $3a, $8b, $01, $2c, $8b, $00, $81, $36, $8b
.byte $01
.byte $ff, $0c
.word @song0ref1200
@song0ref1443:
.byte $32, $8b, $01, $2e, $af, $01, $2e, $8b, $01, $2e, $9d, $01, $2e, $8b, $01, $2e, $9d, $01, $2e, $8b, $00, $81, $28, $8b
.byte $01, $28, $8b, $01, $28
.byte $ff, $0b
.word @song0ref1401
.byte $2e, $8b, $01, $2e, $8b, $01, $2e
.byte $ff, $0b
.word @song0ref1323
@song0ref1485:
.byte $2e, $8b, $01, $2e, $8b, $01, $32, $8b, $01, $32, $8b, $00, $81, $36, $8b, $01
.byte $ff, $0c
.word @song0ref1200
.byte $ff, $1d
.word @song0ref1443
.byte $ff, $0b
.word @song0ref1401
.byte $2e, $8b, $01
.byte $ff, $0b
.word @song0ref1485
.byte $01, $32, $8b, $01
.byte $ff, $0d
.word @song0ref1485
.byte $28, $8b, $01, $28, $8b, $01, $28, $8b, $01, $28
.byte $ff, $0b
.word @song0ref1401
.byte $2c
.byte $ff, $0b
.word @song0ref1132
.byte $2e
.byte $ff, $0b
.word @song0ref1323
.byte $32, $8b, $00, $81, $36, $8b, $01, $36, $8b, $00, $93, $32, $8b, $01, $32, $8b, $00, $93, $36, $8b, $01, $36, $8b, $00
.byte $93
.byte $ff, $0c
.word @song0ref1400
.byte $2c, $8b, $01, $30, $8b, $01, $34, $8b, $00, $81, $fd
.word @song0ch2loop
@song0ch3:
@song0ch3loop:
@song0ref1586:
.byte $84, $5a, $a1, $86, $4e, $a1, $84, $5a, $a1, $86, $4e, $a1, $84, $5a, $a1, $86, $4e, $a1
.byte $ff, $0c
.word @song0ref1586
.byte $84, $5a, $a1, $86, $4e, $a1, $84, $5a, $a1, $86, $4e, $a1, $84, $5a, $a1, $5a, $a1, $5a, $a1, $5a, $a1, $5a, $a1, $5a
.byte $a1, $86, $4e, $8f, $84, $5a, $8f, $86, $4f, $4e, $8b, $84
@song0ref1643:
.byte $5a
@song0ref1644:
.byte $8f, $82, $42, $8f, $8e, $5a, $8f, $86, $4e, $8f, $8e, $5a, $8f, $82, $42, $8f, $42, $8f, $86, $4e, $8f, $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
@song0ref1673:
.byte $8e, $5a, $8f, $82, $42, $8f, $86, $4e, $8f, $4e, $8f, $82, $42, $8f, $86, $4e, $8f, $4e, $8f, $82, $42, $8f, $86, $4e
.byte $ff, $0f
.word @song0ref1644
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $ff, $11
.word @song0ref1673
.byte $ff, $0f
.word @song0ref1644
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e, $5a, $8f, $86, $4e, $8f, $82, $42, $8f
@song0ref1747:
.byte $42, $8f, $86, $4e, $8f, $82, $42, $8f, $86, $4e, $8f, $4e, $8f, $4e
.byte $ff, $0f
.word @song0ref1644
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $ff, $11
.word @song0ref1673
.byte $ff, $0f
.word @song0ref1644
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $ff, $11
.word @song0ref1673
.byte $ff, $0f
.word @song0ref1644
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e
.byte $ff, $10
.word @song0ref1643
.byte $8e, $5a, $8f, $86, $4e, $8f, $4e, $8f, $82
.byte $ff, $0b
.word @song0ref1747
.byte $8f
@song0ref1829:
.byte $4e, $8f, $4e, $a1, $4e, $8f, $4e, $a1, $4e, $8f, $4e, $a1, $82, $42, $8f, $86, $4e, $8f, $82, $42, $8f, $86, $4e, $8f
.byte $82, $42, $8f, $86, $4e, $8f, $4e
@song0ref1860:
.byte $8f, $82, $42, $8f, $42, $8f, $84, $5a, $8f, $82, $42, $8f, $42, $8f, $84, $5a
.byte $ff, $0c
.word @song0ref1860
.byte $8f, $86, $4e, $a1, $4e, $a1
.byte $ff, $25
.word @song0ref1829
.byte $ff, $0c
.word @song0ref1860
.byte $8f, $86, $4e, $a1, $4e, $a1
.byte $ff, $0c
.word @song0ref1586
.byte $84, $5a, $a1, $86, $4e, $a1
.byte $ff, $0c
.word @song0ref1829
.byte $4e, $8f, $4e, $8f, $4e, $8f, $4e, $8f, $4e, $8f, $82, $42, $8f, $42, $8f, $fd
.word @song0ch3loop
@song0ch4:
@song0ch4loop:
@song0ref1928:
.byte $f9, $f9, $ab, $f9, $f9, $ab, $f9, $f9, $ab, $f9, $f9, $ab
.byte $ff, $0c
.word @song0ref1928
.byte $ff, $0c
.word @song0ref1928
.byte $ff, $0c
.word @song0ref1928
.byte $ff, $0c
.word @song0ref1928
.byte $ff, $0c
.word @song0ref1928
.byte $f9, $f9, $ab, $fd
.word @song0ch4loop
|
ninjadynamics/MMC3Template | 11,011 | music_farewell.s | ; This file for the FamiTone2 library and was generated by FamiStudio
_farewell_music_data:
.byte 1
.word @instruments
.word @samples-3
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256
@instruments:
.byte $30 ;instrument 00 (Bass)
.word @env2, @env0, @env0
.byte $00
.byte $70 ;instrument 01 (BeepEcho)
.word @env1, @env0, @env7
.byte $00
.byte $30 ;instrument 02 (HiHat)
.word @env3, @env5, @env0
.byte $00
.byte $30 ;instrument 03 (Lead)
.word @env4, @env0, @env8
.byte $00
.byte $30 ;instrument 04 (LeadLow)
.word @env6, @env0, @env8
.byte $00
@samples:
.byte $00+.lobyte(FT_DPCM_PTR),$0c,$0f ;1 (BassDrum)
.byte $03+.lobyte(FT_DPCM_PTR),$30,$0f ;2 (Snare)
@env0:
.byte $c0,$7f,$00,$00
@env1:
.byte $c8,$c7,$c6,$c5,$00,$03
@env2:
.byte $cf,$7f,$00,$00
@env3:
.byte $ca,$ca,$c7,$c6,$c6,$c5,$04,$c4,$c3,$c2,$c1,$05,$c0,$00,$0c
@env4:
.byte $c4,$c4,$c5,$02,$c4,$03,$c3,$00,$06
@env5:
.byte $c0,$c1,$03,$c2,$c1,$c2,$c1,$c2,$c1,$c2,$00,$09
@env6:
.byte $c4,$c3,$c2,$00,$02
@env7:
.byte $c1,$04,$c0,$00,$02
@env8:
.byte $c0,$11,$c0,$c1,$c2,$c2,$c1,$c0,$bf,$be,$bd,$be,$bf,$00,$02
@song0ch0:
.byte $fb, $01
@song0ch0loop:
@song0ref4:
.byte $82, $36, $8b, $3a, $87, $37, $3c
@song0ref11:
.byte $87, $37
@song0ref13:
.byte $44, $87, $3b, $4e, $87, $3d, $52, $87, $45, $54, $87, $4f, $5c, $87, $53, $36, $87, $55, $3a, $87, $5d, $3c, $87, $37
.byte $44, $87, $3b, $4e, $87, $3d, $52, $87, $45, $54, $87, $4f, $5c, $87, $53, $32, $87, $55, $36, $87, $5d, $3a, $87, $33
.byte $40, $87, $37, $4a, $87, $3b, $4e, $87, $41, $52, $87, $4b, $58, $87, $4f, $32, $87, $53, $36, $87, $59, $3a, $87, $33
.byte $40, $87, $37, $4a, $87, $3b, $4e, $87, $41, $52, $87, $4b, $58, $87, $4e, $81, $30, $87, $53, $32, $87, $59, $36, $87
.byte $31, $3c, $87, $33, $48, $87, $37, $4a, $87, $3d, $4e, $87, $49, $54, $87, $4b, $30, $87, $4f, $32, $87, $55, $36, $87
.byte $31, $3c, $87, $33, $48, $87, $37, $4a, $87, $3d, $4e, $87, $49, $54, $87, $4b, $2e, $87, $4f, $32, $87, $55
@song0ref155:
.byte $36, $87, $2f, $3c, $87, $33, $46, $87, $37, $4a, $87, $3d, $4e, $87, $47, $54, $87, $4b, $2e, $87, $4f, $32, $87, $55
.byte $36, $87, $2f, $3c, $87, $33, $46, $87, $37, $4a, $87, $3d, $4e, $87, $47, $54, $87, $4a, $81, $2c, $87, $4f, $30, $87
.byte $55, $32, $87, $2d, $3a, $87, $31, $44, $87, $33, $48, $87, $3b, $4a, $87, $45, $52, $87, $49, $2c, $87, $4b, $30, $87
.byte $53, $32, $87, $2d, $3a, $87, $31, $44, $87, $33, $48, $87, $3b, $4a, $87, $45, $52, $87, $49, $2e, $87, $4b, $32, $87
.byte $53
.byte $ff, $2b
.word @song0ref155
@song0ref255:
.byte $30, $87, $4f, $32, $87, $55, $36, $87, $31, $40, $87, $33, $48, $87, $37, $4a, $87, $41, $4e, $87, $49, $58, $87, $4b
.byte $30, $87, $4f, $32, $87, $59, $36, $87, $31, $40, $87, $33, $48, $87, $37, $4a, $87, $41, $4e, $87, $49, $58, $87, $4b
.byte $32, $87, $4f, $4a, $87, $59, $4e, $87, $33, $52, $87, $4b, $36, $87, $4f, $4a, $87, $53, $4e, $87, $37, $52, $87, $4b
.byte $3a, $87, $4f, $4a, $87, $53, $4e, $87, $3b, $52, $87, $4b, $44, $87, $4f, $4a, $87, $53, $4e, $87, $45, $52, $87, $4a
.byte $81, $36, $8b, $3a, $87, $37, $3c, $8b
.byte $ff, $d1
.word @song0ref13
.byte $24, $87, $4b, $28, $87, $53, $2c, $87, $25, $32, $87, $29, $3c, $87, $2d, $40, $87, $33, $44, $87, $3d, $4a, $87, $41
.byte $24, $87, $45, $28, $87, $4b, $2a, $87, $25, $32, $87, $29, $3c, $87, $2b, $40, $87, $33, $42, $87, $3d, $4a, $87, $41
.byte $24, $87, $43, $28, $87, $4b, $2a, $87, $25, $32, $87, $29, $28, $87, $2b, $2a, $87, $33, $32, $87, $29, $40, $87, $2a
.byte $81, $28, $87, $33, $2c, $87, $41, $2e, $87, $29, $36, $87, $2d, $2c, $87, $2f, $2e, $87, $37, $36, $87, $2d, $3c, $87
.byte $2f, $2e, $87, $37, $36, $87, $3d, $3c, $87, $2f, $44, $87, $37, $36, $87, $3d, $3c, $87, $45, $44, $87, $37, $4e, $87
.byte $3d, $24, $87, $45, $28, $87, $4f, $32, $87, $25, $3c, $87, $29, $40, $87, $33, $4a, $87, $3d, $54, $87, $41, $58, $87
.byte $4b, $62, $87, $55, $58, $8b, $54, $87, $63, $52, $87, $59, $4a, $87, $55, $40, $87, $53, $3c, $87, $4b, $3a, $87, $40
.byte $81, $86
@song0ref532:
.byte $3c, $ed, $88, $4e, $b5, $5c, $a7, $66, $a7, $66, $ed, $62, $a7, $5c, $a7, $58, $97, $5c, $5c, $f9, $d5, $58, $8b, $56
.byte $f9, $8f, $56, $8b, $58, $8b, $5c, $8b, $58, $8b, $86, $3c, $ed, $88, $4e, $b5, $5c, $a7, $66, $a7, $66, $ed, $62, $a7
.byte $5c, $a7, $58, $97, $5c, $5c, $d1, $86, $56, $9f, $5d, $5c, $a3, $66, $9d, $57, $66, $f9, $ab, $46, $8b, $48, $8b, $4a
.byte $8b, $4c, $8b
.byte $ff, $3b
.word @song0ref532
.byte $56, $56, $66, $f9, $e3
.byte $ff, $f7
.word @song0ref4
.byte $ff, $2b
.word @song0ref155
.byte $ff, $67
.word @song0ref255
.byte $ff, $f1
.word @song0ref11
.byte $ff, $2b
.word @song0ref155
.byte $ff, $61
.word @song0ref255
.byte $86, $54, $ed, $54, $a3, $62, $9f, $55, $62, $9d, $55, $58, $f9, $e1, $00, $fd
.word @song0ch0loop
@song0ch1:
@song0ch1loop:
.byte $86
@song0ref653:
.byte $44, $f9, $99, $4e, $a3, $5c, $f9, $97, $52, $a3, $58, $a3, $62, $a1, $66, $f9, $99, $6a, $a3, $6c, $f9, $97, $54, $a3
.byte $58, $a3, $5c, $a1, $62, $f9, $99, $66, $a3, $6a, $a1, $6a, $ed, $66, $b5, $5c, $b5, $6a, $ed, $66, $a3, $5c, $a3, $62
.byte $f9, $f9, $8d
.byte $ff, $1d
.word @song0ref653
.byte $ed, $54, $a3, $58, $a3, $5c, $a1, $62, $b5, $5e, $b5, $54, $b5, $58, $b5, $5e, $b5, $5c, $b5, $54, $b5, $4e, $b5, $54
.byte $ed, $52, $ed
@song0ref734:
.byte $4e, $f9, $8f, $5c, $a7, $66, $a7, $66, $ed, $62, $a7, $5c, $a7, $58, $99, $5c, $f9, $d5, $58, $8b, $56, $f9, $8f, $56
.byte $8b, $58, $8b, $5c, $8b, $58, $8b, $54, $8b, $52, $8b, $4e, $f9, $8f, $5c, $a7, $66, $a7, $66, $ed, $62, $a7, $5c, $a7
.byte $58, $99, $5c, $ed, $5c, $a3, $66, $a3, $70, $a1, $6e, $f9, $e3
.byte $ff, $3d
.word @song0ref734
.byte $ff, $33
.word @song0ref653
.byte $ff, $33
.word @song0ref653
.byte $62, $ed, $6c, $a3, $70, $a3, $7a, $a1, $02, $f9, $e1, $00, $fd
.word @song0ch1loop
@song0ch2:
@song0ch2loop:
.byte $80
@song0ref821:
.byte $32, $8b, $36, $f9, $d5, $32, $f9, $e3, $30, $f9, $e3, $2e, $f9, $e3, $2c, $a7, $00, $8b, $2c, $a7, $00, $8b, $2c, $a7
.byte $00, $8b, $2c, $a7, $00, $8b
@song0ref851:
.byte $2e, $a7, $00, $8b, $2e, $a7, $00, $8b, $2e, $a7, $00, $8b, $2e, $a7, $00, $8b, $30, $a7, $00, $8b, $30, $a7, $00, $8b
.byte $30, $a7, $00, $8b, $30, $a7, $00, $8b, $32, $a7, $00, $8b, $36, $a7, $00, $8b, $3a, $9d, $3a, $95, $44, $b5, $36, $c1
.byte $36, $a9, $4e, $d1, $4a, $8b, $4e, $8b, $4a, $ed, $3a, $a3, $40, $a3, $4a, $a1, $48, $ed, $30, $ed, $46, $ed, $3c, $a3
.byte $40, $a3, $44, $a1, $2c, $a7, $00, $8b, $2c, $a7, $00, $8b, $2c, $a7, $00, $8b, $2c, $a7, $00, $8b, $2a, $a7, $00, $8b
.byte $2a, $a7, $00, $8b, $2a, $a7, $00, $8b, $2a, $a7, $00, $8b, $28, $a7, $00, $8b, $2c, $a7, $00, $8b, $2e, $a7, $00, $8b
.byte $2e, $a7, $00, $8b, $32, $a7, $00, $8b, $32, $a7, $00, $8b, $32, $a7, $00, $8b, $32, $a7, $00, $8b, $2e, $91, $00, $85
.byte $46, $91, $00, $85, $46, $87, $01, $2e, $91, $00, $85, $2e, $87, $01, $2e, $a7, $00, $8b, $2e, $91, $00, $85
@song0ref1017:
.byte $2e, $87, $01, $30, $87, $01, $32, $91, $00, $85
@song0ref1027:
.byte $4a, $91, $00, $85, $4a, $87, $01, $32, $91, $00, $85, $32, $87, $01, $32, $a7, $00, $8b, $32, $91, $00, $85, $32, $87
.byte $01, $32, $87, $00, $81, $36, $a7, $00, $8b, $36, $a7, $00, $8b, $36, $a7, $00, $8b, $36, $9d, $00, $87, $2c, $87, $01
.byte $36, $91, $00, $85, $4e, $91, $00, $85, $4e, $87, $01, $36, $91, $00, $85, $36, $87, $01, $36, $91, $00, $85
@song0ref1097:
.byte $36, $87, $01, $3a, $87, $01, $3c, $87, $01, $3a, $87, $01, $36, $87, $01, $32, $87, $00, $81, $2e, $91, $00, $85, $46
.byte $91, $00, $85, $46, $87, $01, $2e, $91, $00, $85, $2e, $87, $01, $2e, $a7, $00, $8b, $2e, $93, $00, $83
.byte $ff, $37
.word @song0ref1017
@song0ref1145:
.byte $44, $87, $01, $36, $91, $00, $85, $4e, $91, $00, $85, $4e, $87, $01, $36, $91, $00, $85, $36, $87, $01, $36, $a7, $00
.byte $8b, $36, $89, $36, $a9, $2e, $93, $00, $83, $46, $91, $00, $85, $46, $87, $01, $2e, $91, $00, $85, $2e, $87, $01, $2e
.byte $a7, $00, $8b, $2e, $93, $00, $83
.byte $ff, $46
.word @song0ref1017
.byte $93, $00, $83, $36, $87, $01, $36, $93, $00, $83
.byte $ff, $2d
.word @song0ref1097
.byte $2e, $87, $01, $30, $87, $01, $32, $93, $00, $83
.byte $ff, $2d
.word @song0ref1027
.byte $ff, $1d
.word @song0ref1145
.byte $ff, $7a
.word @song0ref821
.byte $ff, $21
.word @song0ref851
.byte $ad, $00, $85, $36, $ab, $00, $87, $3a, $ab, $00, $87, $32, $ab, $00, $87, $34, $f9, $e3, $32, $f9, $e1, $00, $fd
.word @song0ch2loop
@song0ch3:
@song0ch3loop:
.byte $b7, $84
@song0ref1266:
.byte $5a, $99, $5a, $8b, $5a, $8b, $5a, $b5, $5a, $ed, $5a, $99, $5a, $8b, $5a, $8b, $5a, $b5, $5a, $b5, $b7, $5a, $99, $5a
.byte $8b, $5a, $8b, $5a, $b5, $5a, $ed, $5a, $99, $5a, $8b, $5a, $8b, $5a, $d1, $5a, $99, $a9, $5a, $b5, $5a, $b5, $5a, $b5
.byte $5a, $b5, $5a, $b5, $5a, $b5, $5a, $c3, $a9, $5a, $b5, $5a, $b5, $5a, $ed, $5a, $b5, $5a, $b5, $5a, $c3, $b7
.byte $ff, $45
.word @song0ref1266
@song0ref1339:
.byte $5a, $8b, $5a, $99, $5a, $99, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $99, $5a, $8b, $5a, $8b
.byte $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $99, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $8b, $5a, $99
.byte $5a, $8b, $5a, $8b, $5a, $8b
.byte $ff, $2f
.word @song0ref1339
.byte $c3
.byte $ff, $36
.word @song0ref1339
.byte $ff, $2f
.word @song0ref1339
.byte $c3
.byte $ff, $36
.word @song0ref1339
.byte $ff, $2f
.word @song0ref1339
.byte $c3
.byte $ff, $36
.word @song0ref1339
.byte $ff, $2f
.word @song0ref1339
.byte $c3, $b7
.byte $ff, $46
.word @song0ref1266
.byte $ff, $46
.word @song0ref1266
.byte $5a, $99, $5a, $f9, $91, $5a, $f9, $e1, $fd
.word @song0ch3loop
@song0ch4:
@song0ch4loop:
@song0ref1437:
.byte $02, $f9, $8f, $02, $b5, $02, $99, $02, $f9, $8f, $02, $b5, $02, $99, $02, $f9, $8f, $02, $b5, $02, $99, $02, $f9, $8f
.byte $02, $8b, $02, $8b, $04, $b5, $04, $99, $02, $99, $04, $99, $02, $99, $04, $99, $02, $99, $04, $99, $02, $99, $04, $99
.byte $02, $99, $04, $99, $02, $99, $04, $99, $02, $99, $04, $99, $02, $8b, $02, $8b, $04, $99, $02, $99, $04, $99, $02, $99
.byte $04, $99, $02, $99, $04, $99, $04, $8b, $04, $8b, $04, $99, $02, $99, $04, $99, $02, $99, $04, $99, $02, $99, $04, $83
.byte $04, $85, $02, $8b, $04, $8b, $04, $8b
.byte $ff, $68
.word @song0ref1437
@song0ref1544:
.byte $02, $99, $04, $99, $04, $8b, $02, $a7, $02, $b5, $04, $a7, $02, $8b, $02, $99, $02, $99, $04, $8b, $02, $a7, $02, $b5
.byte $04, $a7, $02, $8b, $02, $99, $04, $99, $04, $8b, $02, $a7, $02, $b5, $04, $a7, $02, $8b, $02, $99, $02, $99, $04, $8b
.byte $02, $a7, $02, $b5, $04, $8b, $04, $8b, $04, $8b, $04, $8b
.byte $ff, $3c
.word @song0ref1544
.byte $ff, $3c
.word @song0ref1544
.byte $ff, $3c
.word @song0ref1544
.byte $ff, $68
.word @song0ref1437
.byte $ff, $68
.word @song0ref1437
.byte $02, $db, $04, $87, $04, $85, $04, $a3, $04, $a3, $04, $a1, $04, $f9, $e3, $fd
.word @song0ch4loop
|
ninjadynamics/MMC3Template | 19,714 | chr_default.s |
;;{w:8,h:8,bpp:1,count:256,brev:1,np:2,pofs:8,remap:[0,1,2,4,5,6,7,8,9,10,11,12]};;
.segment "CHARS"
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $55,$AA,$55,$AA,$55,$AA,$55,$AA
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $55,$AA,$55,$AA,$55,$AA,$55,$AA
.byte $55,$AA,$55,$AA,$55,$AA,$55,$AA
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $55,$AA,$55,$AA,$55,$AA,$55,$AA
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $AA,$55,$AA,$55,$AA,$55,$AA,$55
.byte $AA,$55,$AA,$55,$AA,$55,$AA,$55
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $AA,$55,$AA,$55,$AA,$55,$AA,$55
.byte $55,$AA,$55,$AA,$55,$AA,$55,$AA
.byte $33,$CC,$33,$CC,$33,$CC,$33,$CC
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $33,$CC,$33,$CC,$33,$CC,$33,$CC
.byte $33,$CC,$33,$CC,$33,$CC,$33,$CC
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $33,$CC,$33,$CC,$33,$CC,$33,$CC
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $CC,$33,$CC,$33,$CC,$33,$CC,$33
.byte $CC,$33,$CC,$33,$CC,$33,$CC,$33
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $CC,$33,$CC,$33,$CC,$33,$CC,$33
.byte $33,$CC,$33,$CC,$33,$CC,$33,$CC
.byte $3E,$7F,$7F,$7F,$7F,$7F,$7F,$3E
.byte $3C,$42,$5A,$52,$5A,$42,$3C,$00
.byte $FE,$FF,$7F,$7B,$7B,$00,$00,$00
.byte $F4,$4A,$52,$52,$00,$00,$00,$00
.byte $0F,$0F,$0F,$3F,$7E,$7E,$7E,$3C
.byte $0E,$06,$0A,$38,$6C,$6C,$38,$00
.byte $3C,$7E,$7E,$7E,$3C,$3C,$3C,$18
.byte $38,$6C,$6C,$38,$10,$38,$10,$00
.byte $18,$3C,$7E,$FF,$FF,$FF,$3C,$3C
.byte $10,$38,$7C,$FE,$EE,$10,$38,$00
.byte $7E,$FF,$FF,$FF,$FF,$7E,$3C,$18
.byte $6C,$FE,$FE,$FE,$7C,$38,$10,$00
.byte $18,$3C,$7E,$FF,$FF,$7E,$3C,$18
.byte $10,$38,$7C,$FE,$7C,$38,$10,$00
.byte $3C,$7E,$7E,$FF,$FF,$FF,$3C,$3C
.byte $38,$7C,$38,$FE,$D6,$10,$38,$00
.byte $18,$3C,$FF,$FF,$7E,$7E,$7E,$7E
.byte $10,$38,$FE,$7C,$38,$7C,$6C,$00
.byte $0F,$1F,$7F,$FF,$FC,$FC,$FC,$78
.byte $0A,$14,$72,$F8,$F8,$F8,$70,$00
.byte $00,$00,$FF,$FF,$F6,$F6,$F6,$F6
.byte $00,$00,$EE,$84,$E4,$24,$E4,$00
.byte $00,$00,$FC,$FC,$FC,$FC,$FF,$FF
.byte $00,$00,$E8,$88,$E8,$28,$EE,$00
.byte $18,$3C,$7E,$FF,$FF,$DB,$18,$18
.byte $10,$38,$7C,$D6,$92,$10,$10,$00
.byte $18,$18,$DB,$FF,$FF,$7E,$3C,$18
.byte $10,$10,$92,$D6,$7C,$38,$10,$00
.byte $1C,$3C,$78,$FF,$FF,$78,$3C,$1C
.byte $18,$30,$60,$FE,$60,$30,$18,$00
.byte $38,$3C,$1E,$FF,$FF,$1E,$3C,$38
.byte $30,$18,$0C,$FE,$0C,$18,$30,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $3C,$3C,$3C,$38,$38,$38,$38,$38
.byte $38,$38,$30,$30,$30,$00,$30,$00
.byte $3C,$3C,$3C,$3C,$00,$00,$00,$00
.byte $28,$28,$28,$00,$00,$00,$00,$00
.byte $00,$3C,$7E,$7E,$7E,$7E,$3C,$00
.byte $00,$28,$7C,$28,$7C,$28,$00,$00
.byte $0C,$3F,$3F,$3E,$3E,$7E,$7E,$18
.byte $08,$3E,$28,$3C,$14,$7C,$10,$00
.byte $00,$76,$7E,$7C,$3E,$7E,$6E,$00
.byte $00,$64,$48,$10,$24,$4C,$00,$00
.byte $00,$38,$7C,$7C,$7E,$7E,$7E,$3E
.byte $00,$30,$48,$30,$5C,$48,$34,$00
.byte $30,$30,$70,$60,$00,$00,$00,$00
.byte $20,$20,$40,$00,$00,$00,$00,$00
.byte $0E,$1E,$3C,$38,$38,$3C,$1E,$0E
.byte $0C,$18,$30,$30,$30,$18,$0C,$00
.byte $70,$78,$3C,$1C,$1C,$3C,$78,$70
.byte $60,$30,$18,$18,$18,$30,$60,$00
.byte $00,$00,$3E,$3E,$3E,$3E,$00,$00
.byte $00,$00,$3C,$18,$3C,$00,$00,$00
.byte $00,$18,$18,$7E,$7E,$18,$18,$00
.byte $00,$10,$10,$7C,$10,$10,$00,$00
.byte $00,$00,$00,$00,$38,$38,$78,$70
.byte $00,$00,$00,$00,$30,$30,$60,$00
.byte $00,$00,$00,$3E,$3E,$00,$00,$00
.byte $00,$00,$00,$3C,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$38,$38,$38
.byte $00,$00,$00,$00,$00,$30,$30,$00
.byte $06,$0E,$0E,$1C,$1C,$38,$38,$30
.byte $04,$0C,$08,$18,$10,$30,$20,$00
.byte $3C,$7E,$7E,$7E,$7E,$7E,$7E,$3C
.byte $38,$6C,$6C,$6C,$6C,$6C,$38,$00
.byte $1C,$3C,$3C,$1C,$1C,$1C,$1C,$1C
.byte $18,$38,$18,$18,$18,$18,$18,$00
.byte $3C,$7E,$7E,$3E,$7C,$7E,$7E,$7E
.byte $38,$6C,$0C,$38,$60,$6C,$7C,$00
.byte $3C,$7E,$7E,$3E,$3E,$7E,$7E,$3C
.byte $38,$6C,$0C,$38,$0C,$6C,$38,$00
.byte $7E,$7E,$7E,$7E,$7E,$0E,$0E,$0E
.byte $6C,$6C,$6C,$7C,$0C,$0C,$0C,$00
.byte $7E,$7E,$7E,$7C,$7E,$7E,$7E,$3C
.byte $7C,$6C,$60,$78,$0C,$6C,$38,$00
.byte $3C,$7E,$7E,$7C,$7E,$7E,$7E,$3C
.byte $38,$6C,$60,$78,$6C,$6C,$38,$00
.byte $7E,$7E,$7E,$7E,$0E,$0E,$0E,$0E
.byte $7C,$6C,$6C,$0C,$0C,$0C,$0C,$00
.byte $3C,$7E,$7E,$7E,$7E,$7E,$7E,$3C
.byte $38,$6C,$6C,$38,$6C,$6C,$38,$00
.byte $3C,$7E,$7E,$7E,$3E,$7E,$7E,$3C
.byte $38,$6C,$6C,$3C,$0C,$6C,$38,$00
.byte $00,$38,$38,$38,$38,$38,$38,$00
.byte $00,$30,$30,$00,$30,$30,$00,$00
.byte $00,$38,$38,$38,$38,$38,$78,$70
.byte $00,$30,$30,$00,$30,$30,$60,$00
.byte $0E,$1E,$3C,$78,$78,$3C,$1E,$0E
.byte $0C,$18,$30,$60,$30,$18,$0C,$00
.byte $00,$00,$3E,$3E,$3E,$3E,$00,$00
.byte $00,$00,$3C,$00,$3C,$00,$00,$00
.byte $70,$78,$3C,$1E,$1E,$3C,$78,$70
.byte $60,$30,$18,$0C,$18,$30,$60,$00
.byte $3C,$7E,$7E,$1E,$3C,$38,$38,$38
.byte $38,$6C,$0C,$18,$30,$00,$30,$00
.byte $3C,$7E,$7E,$7E,$7E,$7E,$7E,$3E
.byte $38,$44,$5C,$54,$5C,$40,$3C,$00
.byte $3E,$7F,$77,$7F,$7F,$77,$77,$77
.byte $3C,$66,$66,$7E,$66,$66,$66,$00
.byte $7E,$7F,$77,$7F,$7F,$77,$7F,$7E
.byte $7C,$66,$66,$7C,$66,$66,$7C,$00
.byte $3E,$7F,$77,$70,$70,$77,$7F,$3E
.byte $3C,$66,$60,$60,$60,$66,$3C,$00
.byte $7C,$7E,$7F,$77,$77,$7F,$7E,$7C
.byte $78,$6C,$66,$66,$66,$6C,$78,$00
.byte $7F,$7F,$70,$7F,$7F,$70,$7F,$7F
.byte $7E,$60,$60,$7E,$60,$60,$7E,$00
.byte $7F,$7F,$70,$7C,$7C,$70,$70,$70
.byte $7E,$60,$60,$78,$60,$60,$60,$00
.byte $3E,$7F,$77,$7F,$7F,$77,$7F,$3E
.byte $3C,$66,$60,$6E,$66,$66,$3C,$00
.byte $77,$77,$77,$7F,$7F,$77,$77,$77
.byte $66,$66,$66,$7E,$66,$66,$66,$00
.byte $7F,$7F,$1C,$1C,$1C,$1C,$7F,$7F
.byte $7E,$18,$18,$18,$18,$18,$7E,$00
.byte $07,$07,$07,$07,$77,$77,$7F,$3E
.byte $06,$06,$06,$06,$66,$66,$3C,$00
.byte $77,$7F,$7E,$7C,$7C,$7E,$7F,$77
.byte $66,$6C,$78,$70,$78,$6C,$66,$00
.byte $70,$70,$70,$70,$70,$70,$7F,$7F
.byte $60,$60,$60,$60,$60,$60,$7E,$00
.byte $FE,$FF,$FF,$FF,$FF,$E7,$E7,$E7
.byte $EC,$FE,$D6,$D6,$C6,$C6,$C6,$00
.byte $77,$7F,$7F,$7F,$7F,$7F,$77,$77
.byte $66,$76,$7E,$7E,$6E,$66,$66,$00
.byte $3E,$7F,$77,$77,$77,$77,$7F,$3E
.byte $3C,$66,$66,$66,$66,$66,$3C,$00
.byte $7E,$7F,$77,$7F,$7E,$70,$70,$70
.byte $7C,$66,$66,$7C,$60,$60,$60,$00
.byte $3E,$7F,$77,$77,$77,$7F,$7F,$3F
.byte $3C,$66,$66,$66,$66,$6C,$3E,$00
.byte $7E,$7F,$77,$7F,$7E,$7E,$7F,$77
.byte $7C,$66,$66,$7C,$78,$6C,$66,$00
.byte $3E,$7F,$77,$7E,$3F,$77,$7F,$3E
.byte $3C,$66,$60,$3C,$06,$66,$3C,$00
.byte $7F,$7F,$1C,$1C,$1C,$1C,$1C,$1C
.byte $7E,$18,$18,$18,$18,$18,$18,$00
.byte $77,$77,$77,$77,$77,$77,$7F,$3E
.byte $66,$66,$66,$66,$66,$66,$3C,$00
.byte $77,$77,$77,$77,$7F,$3E,$3E,$1C
.byte $66,$66,$66,$66,$3C,$3C,$18,$00
.byte $E7,$E7,$FF,$FF,$FF,$FF,$FF,$7E
.byte $C6,$C6,$D6,$D6,$D6,$FE,$6C,$00
.byte $77,$77,$7F,$3E,$3E,$7F,$77,$77
.byte $66,$66,$3C,$18,$3C,$66,$66,$00
.byte $77,$77,$77,$7F,$3E,$1C,$1C,$1C
.byte $66,$66,$66,$3C,$18,$18,$18,$00
.byte $7F,$7F,$0F,$1E,$3C,$78,$7F,$7F
.byte $7E,$06,$0C,$18,$30,$60,$7E,$00
.byte $1F,$1F,$1C,$1C,$1C,$1C,$1F,$1F
.byte $1E,$18,$18,$18,$18,$18,$1E,$00
.byte $30,$38,$38,$1C,$1C,$0E,$0E,$06
.byte $20,$30,$10,$18,$08,$0C,$04,$00
.byte $F8,$F8,$38,$38,$38,$38,$F8,$F8
.byte $F0,$30,$30,$30,$30,$30,$F0,$00
.byte $18,$3C,$7E,$7E,$00,$00,$00,$00
.byte $10,$38,$6C,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$7F,$7F
.byte $00,$00,$00,$00,$00,$00,$7E,$00
.byte $30,$30,$38,$18,$00,$00,$00,$00
.byte $20,$20,$10,$00,$00,$00,$00,$00
.byte $00,$00,$3C,$3E,$3E,$7E,$7E,$3E
.byte $00,$00,$38,$0C,$3C,$4C,$34,$00
.byte $70,$70,$7C,$7E,$7E,$7E,$7E,$7C
.byte $60,$60,$78,$6C,$6C,$6C,$78,$00
.byte $00,$00,$3C,$7E,$7E,$7E,$7E,$3C
.byte $00,$00,$38,$6C,$60,$6C,$38,$00
.byte $0E,$0E,$3E,$7E,$7E,$7E,$7E,$3E
.byte $0C,$0C,$3C,$6C,$6C,$6C,$3C,$00
.byte $00,$00,$3C,$7E,$7E,$7E,$7E,$3E
.byte $00,$00,$38,$64,$7C,$60,$3C,$00
.byte $00,$3C,$7E,$7E,$7C,$7C,$70,$70
.byte $00,$38,$6C,$60,$78,$60,$60,$00
.byte $00,$00,$3E,$7E,$7E,$3E,$7E,$7C
.byte $00,$00,$3C,$6C,$3C,$0C,$78,$00
.byte $70,$70,$7C,$7E,$7E,$7E,$7E,$7E
.byte $60,$60,$78,$6C,$6C,$6C,$6C,$00
.byte $00,$1C,$1C,$1C,$1C,$1C,$1C,$1C
.byte $00,$18,$00,$18,$18,$18,$18,$00
.byte $00,$0E,$0E,$0E,$0E,$7E,$7E,$3C
.byte $00,$0C,$00,$0C,$0C,$6C,$38,$00
.byte $70,$70,$7E,$7E,$7C,$7C,$7E,$7E
.byte $60,$60,$6C,$78,$70,$78,$6C,$00
.byte $3C,$3C,$1C,$1C,$1C,$1C,$1C,$1C
.byte $38,$18,$18,$18,$18,$18,$18,$00
.byte $00,$00,$7E,$7F,$7F,$7F,$77,$77
.byte $00,$00,$6C,$7E,$56,$66,$66,$00
.byte $00,$00,$7C,$7E,$7E,$7E,$7E,$7E
.byte $00,$00,$78,$6C,$6C,$6C,$6C,$00
.byte $00,$00,$3C,$7E,$7E,$7E,$7E,$3C
.byte $00,$00,$38,$6C,$6C,$6C,$38,$00
.byte $00,$00,$7C,$7E,$7E,$7C,$70,$70
.byte $00,$00,$78,$6C,$78,$60,$60,$00
.byte $00,$00,$3E,$7E,$7E,$3E,$0E,$0E
.byte $00,$00,$3C,$6C,$3C,$0C,$0C,$00
.byte $00,$00,$7C,$7E,$7E,$70,$70,$70
.byte $00,$00,$78,$6C,$60,$60,$60,$00
.byte $00,$00,$3E,$7E,$7C,$3E,$7E,$7C
.byte $00,$00,$3C,$60,$38,$0C,$78,$00
.byte $00,$1C,$3E,$3E,$1C,$1C,$1E,$0E
.byte $00,$18,$3C,$18,$18,$18,$0C,$00
.byte $00,$00,$7E,$7E,$7E,$7E,$7E,$3E
.byte $00,$00,$6C,$6C,$6C,$6C,$34,$00
.byte $00,$00,$7E,$7E,$7E,$7E,$3E,$1C
.byte $00,$00,$6C,$6C,$6C,$3C,$18,$00
.byte $00,$00,$E7,$E7,$FF,$FF,$7E,$7E
.byte $00,$00,$C6,$C6,$D6,$7C,$6C,$00
.byte $00,$00,$7E,$7E,$3C,$3C,$7E,$7E
.byte $00,$00,$6C,$38,$10,$38,$6C,$00
.byte $00,$00,$7E,$7E,$7E,$3E,$7C,$78
.byte $00,$00,$6C,$6C,$3C,$18,$70,$00
.byte $00,$00,$7E,$7E,$3C,$78,$7E,$7E
.byte $00,$00,$7C,$18,$30,$60,$7C,$00
.byte $0E,$1E,$1C,$3C,$3C,$1C,$1E,$0E
.byte $0C,$18,$18,$30,$18,$18,$0C,$00
.byte $18,$18,$18,$18,$18,$18,$18,$18
.byte $10,$10,$10,$10,$10,$10,$10,$00
.byte $70,$78,$38,$3C,$3C,$38,$78,$70
.byte $60,$30,$30,$18,$30,$30,$60,$00
.byte $00,$00,$7F,$FF,$FE,$00,$00,$00
.byte $00,$00,$76,$DC,$00,$00,$00,$00
.byte $7F,$7F,$7F,$7F,$7F,$7F,$7F,$7F
.byte $7E,$7E,$7E,$7E,$7E,$7E,$7E,$00
.byte $E0,$F8,$FE,$7E,$7E,$3F,$3F,$06
.byte $C0,$F0,$7C,$78,$3C,$2E,$04,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $F0,$F0,$F0,$F0,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $0F,$0F,$0F,$0F,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$F0,$F0,$F0,$F0
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $F0,$F0,$F0,$F0,$F0,$F0,$F0,$F0
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$F0,$F0,$F0,$F0
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$0F,$0F,$0F,$0F
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $F0,$F0,$F0,$F0,$0F,$0F,$0F,$0F
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $0F,$0F,$0F,$0F,$0F,$0F,$0F,$0F
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$0F,$0F,$0F,$0F
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$FF,$FF,$FF,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $F0,$F0,$F0,$F0,$FF,$FF,$FF,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $0F,$0F,$0F,$0F,$FF,$FF,$FF,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $7F,$80,$80,$80,$80,$80,$80,$80
.byte $FF,$00,$00,$00,$00,$00,$00,$00
.byte $3F,$3F,$C0,$C0,$C0,$C0,$C0,$C0
.byte $FF,$FF,$00,$00,$00,$00,$00,$00
.byte $1F,$1F,$1F,$E0,$E0,$E0,$E0,$E0
.byte $FF,$FF,$FF,$00,$00,$00,$00,$00
.byte $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0
.byte $FF,$FF,$FF,$FF,$00,$00,$00,$00
.byte $07,$07,$07,$07,$07,$F8,$F8,$F8
.byte $FF,$FF,$FF,$FF,$FF,$00,$00,$00
.byte $03,$03,$03,$03,$03,$03,$FC,$FC
.byte $FF,$FF,$FF,$FF,$FF,$FF,$00,$00
.byte $01,$01,$01,$01,$01,$01,$01,$FE
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $7F,$80,$80,$80,$80,$80,$80,$80
.byte $00,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $3F,$3F,$C0,$C0,$C0,$C0,$C0,$C0
.byte $00,$00,$FF,$FF,$FF,$FF,$FF,$FF
.byte $1F,$1F,$1F,$E0,$E0,$E0,$E0,$E0
.byte $00,$00,$00,$FF,$FF,$FF,$FF,$FF
.byte $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0
.byte $00,$00,$00,$00,$FF,$FF,$FF,$FF
.byte $07,$07,$07,$07,$07,$F8,$F8,$F8
.byte $00,$00,$00,$00,$00,$FF,$FF,$FF
.byte $03,$03,$03,$03,$03,$03,$FC,$FC
.byte $00,$00,$00,$00,$00,$00,$FF,$FF
.byte $01,$01,$01,$01,$01,$01,$01,$FE
.byte $00,$00,$00,$00,$00,$00,$00,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $FF,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$FF
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $80,$80,$80,$80,$80,$80,$80,$80
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $01,$01,$01,$01,$01,$01,$01,$01
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$03,$0C,$30,$C0
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $03,$0C,$30,$C0,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $C0,$30,$0C,$03,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$C0,$30,$0C,$03
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $10,$10,$20,$20,$40,$40,$80,$80
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $01,$01,$02,$02,$04,$04,$08,$08
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $80,$80,$40,$40,$20,$20,$10,$10
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $08,$08,$04,$04,$02,$02,$01,$01
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $01,$02,$04,$08,$10,$20,$40,$80
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $80,$40,$20,$10,$08,$04,$02,$01
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $81,$42,$24,$18,$18,$24,$42,$81
.byte $00,$00,$00,$00,$00,$00,$00,$00
.byte $3C,$42,$81,$81,$81,$81,$42,$3C
.byte $0C,$00,$10,$00,$00,$00,$04,$00
.byte $0C,$00,$10,$3E,$2E,$2E,$2A,$2E
.byte $00,$3C,$BC,$5A,$00,$20,$24,$7E
.byte $18,$00,$80,$42,$18,$04,$00,$12
.byte $00,$FF,$00,$FF,$00,$FF,$00,$FF
.byte $55,$AA,$55,$AA,$55,$AA,$55,$AA
.byte $24,$00,$5A,$00,$24,$00,$18,$00
.byte $24,$00,$5A,$00,$24,$00,$18,$3C
.byte $4D,$41,$00,$2E,$24,$24,$6A,$6E
.byte $0C,$00,$10,$3E,$2E,$2E,$2A,$2E
.byte $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF
.byte $E7,$C3,$C3,$E7,$E7,$DB,$DB,$93
.byte $24,$24,$C3,$08,$18,$C3,$24,$24
.byte $18,$66,$42,$91,$89,$42,$66,$18
.byte $18,$24,$00,$24,$00,$18,$00,$00
.byte $24,$00,$5A,$00,$24,$00,$18,$3C
.byte $5A,$36,$00,$00,$6C,$3B,$76,$00
.byte $24,$7E,$54,$45,$48,$7E,$3E,$00
.byte $00,$08,$14,$2A,$55,$2A,$14,$08
.byte $80,$49,$36,$3E,$5D,$3E,$36,$49
.byte $0F,$1F,$3F,$3D,$38,$38,$3C,$16
.byte $0F,$1F,$3F,$3F,$3F,$3F,$3F,$17
.byte $F0,$F8,$BC,$14,$A0,$A0,$08,$1C
.byte $F0,$F8,$FC,$FC,$58,$58,$F8,$FC
.byte $F2,$F1,$E1,$0F,$1F,$3B,$11,$00
.byte $0D,$0E,$0E,$00,$00,$04,$0E,$0F
.byte $00,$E0,$F0,$F0,$F8,$DC,$88,$00
.byte $C0,$00,$00,$00,$00,$20,$70,$78
.byte $F2,$F1,$E1,$1F,$3F,$13,$03,$00
.byte $0D,$0E,$0E,$00,$00,$2C,$3C,$20
.byte $00,$E0,$F0,$F8,$E0,$C0,$00,$00
.byte $C0,$00,$00,$04,$1C,$3C,$1C,$00
.byte $FF,$2F,$7F,$FF,$FF,$F2,$F7,$FF
.byte $00,$FE,$FC,$D0,$00,$EF,$CF,$0D
.byte $FF,$F9,$F9,$FF,$FF,$9F,$9F,$FF
.byte $0F,$6F,$6F,$0F,$F0,$F6,$F6,$F0
.byte $FF,$FF,$DF,$FF,$FF,$FF,$FF,$FF
.byte $00,$7E,$7C,$7E,$74,$7C,$50,$00
.byte $05,$67,$4F,$1F,$9D,$3D,$A9,$FF
.byte $FF,$FE,$FF,$FE,$FE,$FF,$FE,$A4
;/* use block comment to map a subset of data to sprite bitmaps */
;/*{w:16,h:16,bpp:1,count:15,brev:1,np:2,pofs:8,remap:[5,0,1,2,4,6,7,8,9,10,11,12]}*/
.byte $00,$0F,$3F,$3F,$7F,$00,$7F,$7F
.byte $0F,$30,$4D,$6D,$AD,$FF,$80,$AD
.byte $7F,$7F,$7F,$00,$7F,$7F,$7F,$00
.byte $AD,$AD,$AD,$FF,$80,$AD,$AD,$FF
.byte $00,$F0,$FC,$FC,$FE,$00,$FE,$FE
.byte $F0,$0C,$B2,$B6,$B7,$FF,$01,$B7
.byte $EA,$E2,$FE,$00,$FE,$FE,$FE,$00
.byte $B5,$BD,$A1,$FF,$01,$B7,$B7,$FF
.byte $00,$22,$4C,$1F,$36,$3F,$5F,$17
.byte $01,$63,$3F,$20,$2D,$29,$60,$EC
.byte $FF,$7F,$36,$3F,$1F,$5C,$22,$00
.byte $68,$20,$0D,$29,$20,$77,$43,$01
.byte $80,$C4,$F2,$FC,$DC,$FC,$FA,$D8
.byte $00,$86,$DC,$04,$B0,$24,$06,$37
.byte $FF,$FE,$DC,$FC,$FC,$FA,$C4,$80
.byte $26,$04,$B0,$20,$04,$CC,$86,$00
.byte $00,$00,$00,$1C,$26,$2F,$3F,$3F
.byte $00,$00,$1C,$3E,$7F,$7F,$7F,$7F
.byte $1F,$0F,$07,$03,$01,$00,$00,$00
.byte $3F,$1F,$0F,$07,$02,$01,$00,$00
.byte $00,$00,$00,$38,$4C,$DC,$F4,$F4
.byte $00,$00,$38,$74,$FA,$FA,$FA,$FA
.byte $E8,$D0,$A0,$40,$80,$00,$00,$00
.byte $F4,$E8,$D0,$A0,$40,$80,$00,$00
.byte $00,$03,$0F,$30,$73,$73,$73,$70
.byte $03,$0F,$3F,$FF,$FC,$FD,$FD,$FF
.byte $73,$73,$3F,$CF,$33,$0C,$03,$00
.byte $FC,$FD,$F1,$3F,$0F,$03,$00,$00
.byte $80,$20,$C8,$72,$3A,$3A,$3A,$7A
.byte $00,$C0,$F0,$BC,$DC,$DC,$DC,$9C
.byte $FA,$FA,$F2,$CE,$38,$E0,$80,$00
.byte $3C,$FC,$FC,$F0,$C0,$00,$00,$00
.byte $B0,$B0,$BF,$B0,$BF,$BF,$B0,$B0
.byte $E0,$E0,$E0,$FF,$EF,$E0,$E0,$E0
.byte $0B,$0B,$FB,$0B,$FB,$FB,$0B,$0B
.byte $0E,$0E,$0E,$FE,$F6,$0E,$0E,$0E
.byte $00,$00,$00,$0C,$3E,$3E,$7B,$FB
.byte $00,$00,$00,$38,$7C,$7C,$FE,$FE
.byte $7B,$F3,$F3,$66,$7E,$3C,$00,$00
.byte $FE,$FE,$7C,$7C,$38,$00,$00,$00
.byte $00,$17,$0F,$1F,$12,$30,$08,$18
.byte $00,$00,$00,$00,$0D,$0F,$07,$07
.byte $0F,$1F,$1F,$13,$03,$0E,$0E,$0F
.byte $0F,$1F,$1F,$1C,$0C,$00,$0E,$0F
.byte $00,$C8,$F8,$F0,$40,$40,$00,$00
.byte $00,$00,$00,$00,$A0,$B0,$E0,$C0
.byte $C0,$E0,$E0,$C0,$C0,$C0,$E0,$70
.byte $C0,$E0,$E0,$20,$20,$00,$E0,$70
.byte $00,$17,$0F,$1F,$12,$30,$08,$18
.byte $00,$00,$00,$00,$0D,$0F,$07,$07
.byte $1F,$1F,$0F,$0F,$3F,$7C,$30,$18
.byte $1F,$3F,$3F,$00,$00,$60,$30,$18
.byte $00,$C8,$F8,$F0,$40,$40,$00,$00
.byte $00,$00,$00,$00,$A0,$B0,$E0,$C0
.byte $C0,$F0,$F8,$E4,$FC,$FC,$7C,$00
.byte $CC,$FC,$F8,$04,$0C,$0C,$0C,$00
.byte $00,$17,$0F,$1F,$12,$30,$08,$18
.byte $00,$00,$00,$00,$0D,$0F,$07,$07
.byte $0F,$1F,$1F,$13,$03,$0E,$0E,$0F
.byte $0F,$1F,$1F,$1C,$0C,$00,$0E,$0F
.byte $00,$C8,$F8,$F0,$40,$40,$00,$00
.byte $00,$00,$00,$00,$A0,$B0,$E0,$C0
.byte $C0,$C0,$C0,$C0,$C0,$C0,$E0,$00
.byte $C0,$C0,$E0,$20,$00,$C0,$E0,$00
.byte $00,$00,$17,$0F,$1F,$12,$30,$08
.byte $00,$00,$00,$00,$00,$0D,$0F,$07
.byte $18,$1F,$0F,$0F,$3F,$7B,$43,$03
.byte $07,$1F,$3F,$37,$20,$60,$43,$03
.byte $00,$00,$C8,$F8,$F0,$40,$40,$00
.byte $00,$00,$00,$00,$00,$A0,$B0,$E0
.byte $00,$E0,$E0,$C0,$C0,$80,$80,$C0
.byte $C0,$F8,$F8,$C0,$00,$00,$80,$C0
.byte $00,$17,$0F,$1F,$12,$30,$08,$18
.byte $00,$00,$00,$00,$0D,$0F,$07,$1F
.byte $3F,$3F,$0F,$7F,$7F,$7E,$40,$00
.byte $3F,$7F,$6F,$60,$60,$60,$40,$00
.byte $00,$C8,$F8,$F0,$40,$40,$00,$00
.byte $00,$00,$00,$00,$A0,$B0,$E0,$CC
.byte $D0,$F8,$F0,$C4,$FC,$FC,$7C,$00
.byte $DC,$F8,$F0,$04,$0C,$0C,$0C,$00
.byte $00,$17,$0F,$1F,$1F,$3F,$0F,$7F
.byte $00,$00,$00,$00,$00,$00,$30,$60
.byte $7F,$3F,$1F,$0F,$0F,$0F,$0F,$0F
.byte $7F,$3F,$1F,$00,$00,$06,$0F,$0F
.byte $00,$E0,$F0,$FC,$FC,$FC,$FC,$FC
.byte $00,$18,$08,$04,$04,$00,$0C,$04
.byte $F8,$F8,$F8,$F8,$F0,$00,$00,$00
.byte $F8,$F8,$C0,$00,$70,$00,$00,$00
.byte $00,$17,$0F,$1F,$1A,$19,$0A,$7C
.byte $00,$00,$00,$00,$05,$66,$65,$63
.byte $7F,$3F,$4F,$7F,$7F,$7E,$00,$00
.byte $7F,$3F,$4F,$60,$60,$60,$00,$00
.byte $00,$E8,$F0,$F8,$58,$9C,$50,$38
.byte $00,$00,$00,$00,$A0,$60,$A0,$C3
.byte $FC,$FE,$F0,$E0,$F0,$F0,$E0,$70
.byte $FF,$FE,$F0,$00,$00,$00,$E0,$70
.byte $FF,$80,$80,$9F,$90,$97,$97,$97
.byte $00,$7F,$7F,$7F,$7F,$7F,$7F,$7F
.byte $97,$97,$97,$97,$9F,$BF,$FF,$00
.byte $7F,$7F,$7F,$78,$7F,$60,$40,$00
.byte $FE,$02,$06,$FE,$0E,$FE,$FE,$FE
.byte $00,$FE,$FC,$F8,$F8,$E8,$E8,$E8
.byte $FE,$FE,$FE,$FE,$FE,$FE,$FE,$00
.byte $E8,$E8,$E8,$08,$F8,$00,$00,$00
.byte $00,$3F,$7F,$60,$6E,$72,$76,$76
.byte $00,$00,$1F,$3F,$31,$2D,$29,$29
.byte $7E,$60,$60,$7F,$7C,$7E,$3F,$00
.byte $21,$3F,$3F,$38,$1B,$01,$00,$00
.byte $00,$FC,$FE,$0E,$7E,$4E,$6E,$6E
.byte $00,$00,$F8,$FC,$8C,$B4,$94,$94
.byte $7E,$0E,$0E,$FE,$3E,$7E,$FC,$00
.byte $84,$FC,$FC,$1C,$D8,$80,$00,$00
.byte $00,$7F,$7F,$60,$7F,$7F,$77,$76
.byte $00,$00,$3F,$3F,$00,$20,$29,$29
.byte $72,$6E,$60,$77,$7E,$3C,$1F,$00
.byte $2D,$31,$3F,$3C,$19,$03,$00,$00
.byte $00,$FE,$FE,$0E,$FE,$FE,$EE,$6E
.byte $00,$00,$FC,$FC,$00,$04,$94,$94
.byte $4E,$7E,$0E,$EE,$7E,$3C,$F8,$00
.byte $B4,$8C,$FC,$3C,$98,$C0,$00,$00
;;
|
ninjadynamics/MMC3Template | 33,911 | famitone2.s | .segment "CODE"
.export _famitone_init,_famitone_update
.export _music_play,_music_stop,_music_pause
;from mmc3.h
.importzp _music_bank,_sfx_bank,_dpcm_bank
.importzp _mmc3_cpu_bank, _mmc3_register
.importzp _mmc3_last_register, _mmc3_last_cpu_bank
.importzp _active_data_bank,_active_data_bank_index
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; Core Functionality
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;void __fastcall__ famitone_init(void* music_data);
_famitone_init=FamiToneInit
;void __fastcall__ famitone_update(void);
_famitone_update=FamiToneUpdate
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; Music
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;void __fastcall__ music_play(unsigned char song);
_music_play=FamiToneMusicPlay
;void __fastcall__ music_stop(void);
_music_stop=FamiToneMusicStop
;void __fastcall__ music_pause(unsigned char pause);
_music_pause=FamiToneMusicPause
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; Sound Effects
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
.if(FT_SFX_ENABLE)
.export _sfx_init
.export _sfx_play
;void __fastcall__ sfx_init(void* sounds_data);
_sfx_init=FamiToneSfxInit
;void __fastcall__ sfx_play(unsigned char sound,unsigned char channel);
_sfx_play:
and #$03
tax
lda @sfxPriority,x
tax
jsr popa
jmp FamiToneSfxPlay
@sfxPriority:
.byte FT_SFX_CH0,FT_SFX_CH1,FT_SFX_CH2,FT_SFX_CH3
.else
rts
.endif
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; Samples
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;void __fastcall__ sample_play(unsigned char sample);
.if(FT_DPCM_ENABLE)
.export _sample_play
;void __fastcall__ sample_play(unsigned char sample);
_sample_play=FamiToneSamplePlay
.else
_sample_play:
rts
.endif
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
; Bank switching macros
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
.macro switch_to_music_bank
.if(FT_BANKED_MUSIC)
lda #$06
sta _mmc3_register
lda _music_bank
sta _mmc3_cpu_bank
lda #($06 | A12_INVERSION)
sta $8000
lda _music_bank
sta $8001
.endif
.endmacro
.macro switch_to_SFX_bank
.if(FT_BANKED_SFX)
lda #$06
sta _mmc3_register
lda _sfx_bank
sta _mmc3_cpu_bank
lda #($06 | A12_INVERSION)
sta $8000
lda _sfx_bank
sta $8001
.endif
.endmacro
.macro switch_to_DPCM_bank
.if(FT_BANKED_DPCM)
lda #$06
sta _mmc3_register
lda _dpcm_bank
sta _mmc3_cpu_bank
lda #($06 | A12_INVERSION)
sta $8000
lda _dpcm_bank
sta $8001
.endif
.endmacro
.macro switch_to_active_data_bank
lda #($06 | A12_INVERSION)
sta $8000
ldy _active_data_bank_index
lda _active_data_bank,y
sta $8001
.endmacro
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
;======================================================================================================
;FamiTone2 v1.12 - Removed FT_PITCH_FIX
;======================================================================================================
;zero page variables
FT_TEMP_PTR = FT_TEMP ;word
FT_TEMP_PTR_L = FT_TEMP_PTR+0
FT_TEMP_PTR_H = FT_TEMP_PTR+1
FT_TEMP_VAR1 = FT_TEMP+2
;envelope structure offsets, 5 bytes per envelope, grouped by variable type
FT_ENVELOPES_ALL = 3+3+3+2 ;3 for the pulse and triangle channels, 2 for the noise channel
FT_ENV_STRUCT_SIZE = 5
FT_ENV_VALUE = FT_BASE_ADR+0*FT_ENVELOPES_ALL
FT_ENV_REPEAT = FT_BASE_ADR+1*FT_ENVELOPES_ALL
FT_ENV_ADR_L = FT_BASE_ADR+2*FT_ENVELOPES_ALL
FT_ENV_ADR_H = FT_BASE_ADR+3*FT_ENVELOPES_ALL
FT_ENV_PTR = FT_BASE_ADR+4*FT_ENVELOPES_ALL
;channel structure offsets, 7 bytes per channel
FT_CHANNELS_ALL = 5
FT_CHN_STRUCT_SIZE = 9
FT_CHN_PTR_L = FT_BASE_ADR+0*FT_CHANNELS_ALL
FT_CHN_PTR_H = FT_BASE_ADR+1*FT_CHANNELS_ALL
FT_CHN_NOTE = FT_BASE_ADR+2*FT_CHANNELS_ALL
FT_CHN_INSTRUMENT = FT_BASE_ADR+3*FT_CHANNELS_ALL
FT_CHN_REPEAT = FT_BASE_ADR+4*FT_CHANNELS_ALL
FT_CHN_RETURN_L = FT_BASE_ADR+5*FT_CHANNELS_ALL
FT_CHN_RETURN_H = FT_BASE_ADR+6*FT_CHANNELS_ALL
FT_CHN_REF_LEN = FT_BASE_ADR+7*FT_CHANNELS_ALL
FT_CHN_DUTY = FT_BASE_ADR+8*FT_CHANNELS_ALL
;variables and aliases
FT_ENVELOPES = FT_BASE_ADR
FT_CH1_ENVS = FT_ENVELOPES+0
FT_CH2_ENVS = FT_ENVELOPES+3
FT_CH3_ENVS = FT_ENVELOPES+6
FT_CH4_ENVS = FT_ENVELOPES+9
FT_CHANNELS = FT_ENVELOPES+FT_ENVELOPES_ALL*FT_ENV_STRUCT_SIZE
FT_CH1_VARS = FT_CHANNELS+0
FT_CH2_VARS = FT_CHANNELS+1
FT_CH3_VARS = FT_CHANNELS+2
FT_CH4_VARS = FT_CHANNELS+3
FT_CH5_VARS = FT_CHANNELS+4
FT_CH1_NOTE = FT_CH1_VARS+.lobyte(FT_CHN_NOTE)
FT_CH2_NOTE = FT_CH2_VARS+.lobyte(FT_CHN_NOTE)
FT_CH3_NOTE = FT_CH3_VARS+.lobyte(FT_CHN_NOTE)
FT_CH4_NOTE = FT_CH4_VARS+.lobyte(FT_CHN_NOTE)
FT_CH5_NOTE = FT_CH5_VARS+.lobyte(FT_CHN_NOTE)
FT_CH1_INSTRUMENT = FT_CH1_VARS+.lobyte(FT_CHN_INSTRUMENT)
FT_CH2_INSTRUMENT = FT_CH2_VARS+.lobyte(FT_CHN_INSTRUMENT)
FT_CH3_INSTRUMENT = FT_CH3_VARS+.lobyte(FT_CHN_INSTRUMENT)
FT_CH4_INSTRUMENT = FT_CH4_VARS+.lobyte(FT_CHN_INSTRUMENT)
FT_CH5_INSTRUMENT = FT_CH5_VARS+.lobyte(FT_CHN_INSTRUMENT)
FT_CH1_DUTY = FT_CH1_VARS+.lobyte(FT_CHN_DUTY)
FT_CH2_DUTY = FT_CH2_VARS+.lobyte(FT_CHN_DUTY)
FT_CH3_DUTY = FT_CH3_VARS+.lobyte(FT_CHN_DUTY)
FT_CH4_DUTY = FT_CH4_VARS+.lobyte(FT_CHN_DUTY)
FT_CH5_DUTY = FT_CH5_VARS+.lobyte(FT_CHN_DUTY)
FT_CH1_VOLUME = FT_CH1_ENVS+.lobyte(FT_ENV_VALUE)+0
FT_CH2_VOLUME = FT_CH2_ENVS+.lobyte(FT_ENV_VALUE)+0
FT_CH3_VOLUME = FT_CH3_ENVS+.lobyte(FT_ENV_VALUE)+0
FT_CH4_VOLUME = FT_CH4_ENVS+.lobyte(FT_ENV_VALUE)+0
FT_CH1_NOTE_OFF = FT_CH1_ENVS+.lobyte(FT_ENV_VALUE)+1
FT_CH2_NOTE_OFF = FT_CH2_ENVS+.lobyte(FT_ENV_VALUE)+1
FT_CH3_NOTE_OFF = FT_CH3_ENVS+.lobyte(FT_ENV_VALUE)+1
FT_CH4_NOTE_OFF = FT_CH4_ENVS+.lobyte(FT_ENV_VALUE)+1
FT_CH1_PITCH_OFF = FT_CH1_ENVS+.lobyte(FT_ENV_VALUE)+2
FT_CH2_PITCH_OFF = FT_CH2_ENVS+.lobyte(FT_ENV_VALUE)+2
FT_CH3_PITCH_OFF = FT_CH3_ENVS+.lobyte(FT_ENV_VALUE)+2
FT_VARS = FT_CHANNELS+FT_CHANNELS_ALL*FT_CHN_STRUCT_SIZE
FT_PAL_ADJUST = FT_VARS+0
FT_SONG_LIST_L = FT_VARS+1
FT_SONG_LIST_H = FT_VARS+2
FT_INSTRUMENT_L = FT_VARS+3
FT_INSTRUMENT_H = FT_VARS+4
FT_TEMPO_STEP_L = FT_VARS+5
FT_TEMPO_STEP_H = FT_VARS+6
FT_TEMPO_ACC_L = FT_VARS+7
FT_TEMPO_ACC_H = FT_VARS+8
FT_SONG_SPEED = FT_CH5_INSTRUMENT
FT_PULSE1_PREV = FT_CH3_DUTY
FT_PULSE2_PREV = FT_CH5_DUTY
FT_DPCM_LIST_L = FT_VARS+9
FT_DPCM_LIST_H = FT_VARS+10
FT_DPCM_EFFECT = FT_VARS+11
FT_OUT_BUF = FT_VARS+12 ;11 bytes
;sound effect stream variables, 2 bytes and 15 bytes per stream
;when sound effects are disabled, this memory is not used
FT_SFX_ADR_L = FT_VARS+23
FT_SFX_ADR_H = FT_VARS+24
FT_SFX_BASE_ADR = FT_VARS+25
FT_SFX_STRUCT_SIZE = 15
FT_SFX_REPEAT = FT_SFX_BASE_ADR+0
FT_SFX_PTR_L = FT_SFX_BASE_ADR+1
FT_SFX_PTR_H = FT_SFX_BASE_ADR+2
FT_SFX_OFF = FT_SFX_BASE_ADR+3
FT_SFX_BUF = FT_SFX_BASE_ADR+4 ;11 bytes
;aliases for sound effect channels to use in user calls
FT_SFX_CH0 = FT_SFX_STRUCT_SIZE*0
FT_SFX_CH1 = FT_SFX_STRUCT_SIZE*1
FT_SFX_CH2 = FT_SFX_STRUCT_SIZE*2
FT_SFX_CH3 = FT_SFX_STRUCT_SIZE*3
;aliases for the APU registers
APU_PL1_VOL = $4000
APU_PL1_SWEEP = $4001
APU_PL1_LO = $4002
APU_PL1_HI = $4003
APU_PL2_VOL = $4004
APU_PL2_SWEEP = $4005
APU_PL2_LO = $4006
APU_PL2_HI = $4007
APU_TRI_LINEAR = $4008
APU_TRI_LO = $400a
APU_TRI_HI = $400b
APU_NOISE_VOL = $400c
APU_NOISE_LO = $400e
APU_NOISE_HI = $400f
APU_DMC_FREQ = $4010
APU_DMC_RAW = $4011
APU_DMC_START = $4012
APU_DMC_LEN = $4013
APU_SND_CHN = $4015
;aliases for the APU registers in the output buffer
.if(!FT_SFX_ENABLE) ;if sound effects are disabled, write to the APU directly
FT_MR_PULSE1_V = APU_PL1_VOL
FT_MR_PULSE1_L = APU_PL1_LO
FT_MR_PULSE1_H = APU_PL1_HI
FT_MR_PULSE2_V = APU_PL2_VOL
FT_MR_PULSE2_L = APU_PL2_LO
FT_MR_PULSE2_H = APU_PL2_HI
FT_MR_TRI_V = APU_TRI_LINEAR
FT_MR_TRI_L = APU_TRI_LO
FT_MR_TRI_H = APU_TRI_HI
FT_MR_NOISE_V = APU_NOISE_VOL
FT_MR_NOISE_F = APU_NOISE_LO
.else ;otherwise write to the output buffer
FT_MR_PULSE1_V = FT_OUT_BUF
FT_MR_PULSE1_L = FT_OUT_BUF+1
FT_MR_PULSE1_H = FT_OUT_BUF+2
FT_MR_PULSE2_V = FT_OUT_BUF+3
FT_MR_PULSE2_L = FT_OUT_BUF+4
FT_MR_PULSE2_H = FT_OUT_BUF+5
FT_MR_TRI_V = FT_OUT_BUF+6
FT_MR_TRI_L = FT_OUT_BUF+7
FT_MR_TRI_H = FT_OUT_BUF+8
FT_MR_NOISE_V = FT_OUT_BUF+9
FT_MR_NOISE_F = FT_OUT_BUF+10
.endif
;------------------------------------------------------------------------------
; reset APU, initialize FamiTone
;------------------------------------------------------------------------------
FamiToneInit:
sta FT_SONG_LIST_L ;store music data pointer for further use
stx FT_SONG_LIST_H
sta <FT_TEMP_PTR_L
stx <FT_TEMP_PTR_H
@pal:
.if(FT_PAL_SUPPORT)
lda #0
.endif
.if(FT_NTSC_SUPPORT)
lda #64
.endif
sta FT_PAL_ADJUST
jsr FamiToneMusicStop ;initialize channels and envelopes
ldy #1
lda (FT_TEMP_PTR),y ;get instrument list address
sta FT_INSTRUMENT_L
iny
lda (FT_TEMP_PTR),y
sta FT_INSTRUMENT_H
iny
lda (FT_TEMP_PTR),y ;get sample list address
sta FT_DPCM_LIST_L
iny
lda (FT_TEMP_PTR),y
sta FT_DPCM_LIST_H
lda #$ff ;previous pulse period MSB, to not write it when not changed
sta FT_PULSE1_PREV
sta FT_PULSE2_PREV
lda #$0f ;enable channels, stop DMC
sta APU_SND_CHN
lda #$80 ;disable triangle length counter
sta APU_TRI_LINEAR
lda #$00 ;load noise length
sta APU_NOISE_HI
lda #$30 ;volumes to 0
sta APU_PL1_VOL
sta APU_PL2_VOL
sta APU_NOISE_VOL
lda #$08 ;no sweep
sta APU_PL1_SWEEP
sta APU_PL2_SWEEP
;jmp FamiToneMusicStop
;------------------------------------------------------------------------------
; stop music that is currently playing, if any
; in: none
;------------------------------------------------------------------------------
FamiToneMusicStop:
lda #0
sta FT_SONG_SPEED ;stop music, reset pause flag
sta FT_DPCM_EFFECT ;no DPCM effect playing
ldx #.lobyte(FT_CHANNELS) ;initialize channel structures
@set_channels:
lda #0
sta FT_CHN_REPEAT,x
sta FT_CHN_INSTRUMENT,x
sta FT_CHN_NOTE,x
sta FT_CHN_REF_LEN,x
lda #$30
sta FT_CHN_DUTY,x
inx ;next channel
cpx #.lobyte(FT_CHANNELS)+FT_CHANNELS_ALL
bne @set_channels
ldx #.lobyte(FT_ENVELOPES) ;initialize all envelopes to the dummy envelope
@set_envelopes:
lda #.lobyte (_FT2DummyEnvelope)
sta FT_ENV_ADR_L,x
lda #.hibyte(_FT2DummyEnvelope)
sta FT_ENV_ADR_H,x
lda #0
sta FT_ENV_REPEAT,x
sta FT_ENV_VALUE,x
inx
cpx #.lobyte(FT_ENVELOPES)+FT_ENVELOPES_ALL
bne @set_envelopes
jmp FamiToneSampleStop
;------------------------------------------------------------------------------
; play music
; in: A number of subsong
;------------------------------------------------------------------------------
FamiToneMusicPlay:
ldx FT_SONG_LIST_L
stx <FT_TEMP_PTR_L
ldx FT_SONG_LIST_H
stx <FT_TEMP_PTR_H
ldy #0
cmp (FT_TEMP_PTR),y ;check if there is such sub song
bcs @skip
asl a ;multiply song number by 14
sta <FT_TEMP_PTR_L ;use pointer LSB as temp variable
asl a
tax
asl a
adc <FT_TEMP_PTR_L
stx <FT_TEMP_PTR_L
adc <FT_TEMP_PTR_L
adc #5 ;add offset
tay
lda FT_SONG_LIST_L ;restore pointer LSB
sta <FT_TEMP_PTR_L
jsr FamiToneMusicStop ;stop music, initialize channels and envelopes
ldx #.lobyte(FT_CHANNELS) ;initialize channel structures
@set_channels:
lda (FT_TEMP_PTR),y ;read channel pointers
sta FT_CHN_PTR_L,x
iny
lda (FT_TEMP_PTR),y
sta FT_CHN_PTR_H,x
iny
lda #0
sta FT_CHN_REPEAT,x
sta FT_CHN_INSTRUMENT,x
sta FT_CHN_NOTE,x
sta FT_CHN_REF_LEN,x
lda #$30
sta FT_CHN_DUTY,x
inx ;next channel
cpx #.lobyte(FT_CHANNELS)+FT_CHANNELS_ALL
bne @set_channels
lda FT_PAL_ADJUST ;read tempo for PAL or NTSC
beq @pal
iny
iny
@pal:
lda (FT_TEMP_PTR),y ;read the tempo step
sta FT_TEMPO_STEP_L
iny
lda (FT_TEMP_PTR),y
sta FT_TEMPO_STEP_H
lda #0 ;reset tempo accumulator
sta FT_TEMPO_ACC_L
lda #6 ;default speed
sta FT_TEMPO_ACC_H
sta FT_SONG_SPEED ;apply default speed, this also enables music
@skip:
rts
;------------------------------------------------------------------------------
; pause and unpause current music
; in: A 0 or not 0 to play or pause
;------------------------------------------------------------------------------
FamiToneMusicPause:
tax ;set SZ flags for A
beq @unpause
@pause:
jsr FamiToneSampleStop
lda #0 ;mute sound
sta FT_CH1_VOLUME
sta FT_CH2_VOLUME
sta FT_CH3_VOLUME
sta FT_CH4_VOLUME
lda FT_SONG_SPEED ;set pause flag
ora #$80
bne @done
@unpause:
lda FT_SONG_SPEED ;reset pause flag
and #$7f
@done:
sta FT_SONG_SPEED
rts
;------------------------------------------------------------------------------
; update FamiTone state, should be called every NMI
; in: none
;------------------------------------------------------------------------------
FamiToneUpdate:
lda _mmc3_register
sta _mmc3_last_register
lda _mmc3_cpu_bank
sta _mmc3_last_cpu_bank
switch_to_music_bank
.if(FT_THREAD)
lda FT_TEMP_PTR_L
pha
lda FT_TEMP_PTR_H
pha
.endif
lda FT_SONG_SPEED ;speed 0 means that no music is playing currently
bmi @pause ;bit 7 set is the pause flag
bne @update
@pause:
jmp @update_sound
@update:
clc ;update frame counter that considers speed, tempo, and PAL/NTSC
lda FT_TEMPO_ACC_L
adc FT_TEMPO_STEP_L
sta FT_TEMPO_ACC_L
lda FT_TEMPO_ACC_H
adc FT_TEMPO_STEP_H
cmp FT_SONG_SPEED
bcs @update_row ;overflow, row update is needed
sta FT_TEMPO_ACC_H ;no row update, skip to the envelopes update
jmp @update_envelopes
@update_row:
sec
sbc FT_SONG_SPEED
sta FT_TEMPO_ACC_H
ldx #.lobyte(FT_CH1_VARS) ;process channel 1
jsr _FT2ChannelUpdate
bcc @no_new_note1
ldx #.lobyte(FT_CH1_ENVS)
lda FT_CH1_INSTRUMENT
jsr _FT2SetInstrument
sta FT_CH1_DUTY
@no_new_note1:
ldx #.lobyte(FT_CH2_VARS) ;process channel 2
jsr _FT2ChannelUpdate
bcc @no_new_note2
ldx #.lobyte(FT_CH2_ENVS)
lda FT_CH2_INSTRUMENT
jsr _FT2SetInstrument
sta FT_CH2_DUTY
@no_new_note2:
ldx #.lobyte(FT_CH3_VARS) ;process channel 3
jsr _FT2ChannelUpdate
bcc @no_new_note3
ldx #.lobyte(FT_CH3_ENVS)
lda FT_CH3_INSTRUMENT
jsr _FT2SetInstrument
@no_new_note3:
ldx #.lobyte(FT_CH4_VARS) ;process channel 4
jsr _FT2ChannelUpdate
bcc @no_new_note4
ldx #.lobyte(FT_CH4_ENVS)
lda FT_CH4_INSTRUMENT
jsr _FT2SetInstrument
sta FT_CH4_DUTY
@no_new_note4:
.if(FT_DPCM_ENABLE)
ldx #.lobyte(FT_CH5_VARS) ;process channel 5
jsr _FT2ChannelUpdate
bcc @no_new_note5
lda FT_CH5_NOTE
bne @play_sample
jsr FamiToneSampleStop
bne @no_new_note5 ;A is non-zero after FamiToneSampleStop
@play_sample:
jsr FamiToneSamplePlayM
@no_new_note5:
.endif
@update_envelopes:
ldx #.lobyte(FT_ENVELOPES) ;process 11 envelopes
@env_process:
lda FT_ENV_REPEAT,x ;check envelope repeat counter
beq @env_read ;if it is zero, process envelope
dec FT_ENV_REPEAT,x ;otherwise decrement the counter
bne @env_next
@env_read:
lda FT_ENV_ADR_L,x ;load envelope data address into temp
sta <FT_TEMP_PTR_L
lda FT_ENV_ADR_H,x
sta <FT_TEMP_PTR_H
ldy FT_ENV_PTR,x ;load envelope pointer
@env_read_value:
lda (FT_TEMP_PTR),y ;read a byte of the envelope data
bpl @env_special ;values below 128 used as a special code, loop or repeat
clc ;values above 128 are output value+192 (output values are signed -63..64)
adc #256-192
sta FT_ENV_VALUE,x ;store the output value
iny ;advance the pointer
bne @env_next_store_ptr ;bra
@env_special:
bne @env_set_repeat ;zero is the loop point, non-zero values used for the repeat counter
iny ;advance the pointer
lda (FT_TEMP_PTR),y ;read loop position
tay ;use loop position
jmp @env_read_value ;read next byte of the envelope
@env_set_repeat:
iny
sta FT_ENV_REPEAT,x ;store the repeat counter value
@env_next_store_ptr:
tya ;store the envelope pointer
sta FT_ENV_PTR,x
@env_next:
inx ;next envelope
cpx #.lobyte(FT_ENVELOPES)+FT_ENVELOPES_ALL
bne @env_process
@update_sound:
;convert envelope and channel output data into APU register values in the output buffer
lda FT_CH1_NOTE
beq @ch1cut
clc
adc FT_CH1_NOTE_OFF
tax
lda FT_CH1_PITCH_OFF
tay
adc _FT2NoteTableLSB,x
sta FT_MR_PULSE1_L
tya ;sign extension for the pitch offset
ora #$7f
bmi @ch1sign
lda #0
@ch1sign:
adc _FT2NoteTableMSB,x
.if(!FT_SFX_ENABLE)
cmp FT_PULSE1_PREV
beq @ch1prev
sta FT_PULSE1_PREV
.endif
sta FT_MR_PULSE1_H
@ch1prev:
lda FT_CH1_VOLUME
@ch1cut:
ora FT_CH1_DUTY
sta FT_MR_PULSE1_V
lda FT_CH2_NOTE
beq @ch2cut
clc
adc FT_CH2_NOTE_OFF
tax
lda FT_CH2_PITCH_OFF
tay
adc _FT2NoteTableLSB,x
sta FT_MR_PULSE2_L
tya
ora #$7f
bmi @ch2sign
lda #0
@ch2sign:
adc _FT2NoteTableMSB,x
.if(!FT_SFX_ENABLE)
cmp FT_PULSE2_PREV
beq @ch2prev
sta FT_PULSE2_PREV
.endif
sta FT_MR_PULSE2_H
@ch2prev:
lda FT_CH2_VOLUME
@ch2cut:
ora FT_CH2_DUTY
sta FT_MR_PULSE2_V
lda FT_CH3_NOTE
beq @ch3cut
clc
adc FT_CH3_NOTE_OFF
tax
lda FT_CH3_PITCH_OFF
tay
adc _FT2NoteTableLSB,x
sta FT_MR_TRI_L
tya
ora #$7f
bmi @ch3sign
lda #0
@ch3sign:
adc _FT2NoteTableMSB,x
sta FT_MR_TRI_H
lda FT_CH3_VOLUME
@ch3cut:
ora #$80
sta FT_MR_TRI_V
lda FT_CH4_NOTE
beq @ch4cut
clc
adc FT_CH4_NOTE_OFF
and #$0f
eor #$0f
sta <FT_TEMP_VAR1
lda FT_CH4_DUTY
asl a
and #$80
ora <FT_TEMP_VAR1
sta FT_MR_NOISE_F
lda FT_CH4_VOLUME
@ch4cut:
ora #$f0
sta FT_MR_NOISE_V
.if(FT_SFX_ENABLE)
switch_to_SFX_bank
;process all sound effect streams
.if FT_SFX_STREAMS>0
ldx #FT_SFX_CH0
jsr _FT2SfxUpdate
.endif
.if FT_SFX_STREAMS>1
ldx #FT_SFX_CH1
jsr _FT2SfxUpdate
.endif
.if FT_SFX_STREAMS>2
ldx #FT_SFX_CH2
jsr _FT2SfxUpdate
.endif
.if FT_SFX_STREAMS>3
ldx #FT_SFX_CH3
jsr _FT2SfxUpdate
.endif
;send data from the output buffer to the APU
lda FT_OUT_BUF ;pulse 1 volume
sta APU_PL1_VOL
lda FT_OUT_BUF+1 ;pulse 1 period LSB
sta APU_PL1_LO
lda FT_OUT_BUF+2 ;pulse 1 period MSB, only applied when changed
cmp FT_PULSE1_PREV
beq @no_pulse1_upd
sta FT_PULSE1_PREV
sta APU_PL1_HI
@no_pulse1_upd:
lda FT_OUT_BUF+3 ;pulse 2 volume
sta APU_PL2_VOL
lda FT_OUT_BUF+4 ;pulse 2 period LSB
sta APU_PL2_LO
lda FT_OUT_BUF+5 ;pulse 2 period MSB, only applied when changed
cmp FT_PULSE2_PREV
beq @no_pulse2_upd
sta FT_PULSE2_PREV
sta APU_PL2_HI
@no_pulse2_upd:
lda FT_OUT_BUF+6 ;triangle volume (plays or not)
sta APU_TRI_LINEAR
lda FT_OUT_BUF+7 ;triangle period LSB
sta APU_TRI_LO
lda FT_OUT_BUF+8 ;triangle period MSB
sta APU_TRI_HI
lda FT_OUT_BUF+9 ;noise volume
sta APU_NOISE_VOL
lda FT_OUT_BUF+10 ;noise period
sta APU_NOISE_LO
.endif
.if(FT_THREAD)
pla
sta FT_TEMP_PTR_H
pla
sta FT_TEMP_PTR_L
.endif
lda _mmc3_last_register
sta _mmc3_register
lda _mmc3_last_cpu_bank
sta _mmc3_cpu_bank
switch_to_active_data_bank
rts
;internal routine, sets up envelopes of a channel according to current instrument
;in X envelope group offset, A instrument number
_FT2SetInstrument:
asl a ;instrument number is pre multiplied by 4
tay
lda FT_INSTRUMENT_H
adc #0 ;use carry to extend range for 64 instruments
sta <FT_TEMP_PTR_H
lda FT_INSTRUMENT_L
sta <FT_TEMP_PTR_L
lda (FT_TEMP_PTR),y ;duty cycle
sta <FT_TEMP_VAR1
iny
lda (FT_TEMP_PTR),y ;instrument pointer LSB
sta FT_ENV_ADR_L,x
iny
lda (FT_TEMP_PTR),y ;instrument pointer MSB
iny
sta FT_ENV_ADR_H,x
inx ;next envelope
lda (FT_TEMP_PTR),y ;instrument pointer LSB
sta FT_ENV_ADR_L,x
iny
lda (FT_TEMP_PTR),y ;instrument pointer MSB
sta FT_ENV_ADR_H,x
lda #0
sta FT_ENV_REPEAT-1,x ;reset env1 repeat counter
sta FT_ENV_PTR-1,x ;reset env1 pointer
sta FT_ENV_REPEAT,x ;reset env2 repeat counter
sta FT_ENV_PTR,x ;reset env2 pointer
cpx #.lobyte(FT_CH4_ENVS) ;noise channel has only two envelopes
bcs @no_pitch
inx ;next envelope
iny
sta FT_ENV_REPEAT,x ;reset env3 repeat counter
sta FT_ENV_PTR,x ;reset env3 pointer
lda (FT_TEMP_PTR),y ;instrument pointer LSB
sta FT_ENV_ADR_L,x
iny
lda (FT_TEMP_PTR),y ;instrument pointer MSB
sta FT_ENV_ADR_H,x
@no_pitch:
lda <FT_TEMP_VAR1
rts
;internal routine, parses channel note data
_FT2ChannelUpdate:
lda FT_CHN_REPEAT,x ;check repeat counter
beq @no_repeat
dec FT_CHN_REPEAT,x ;decrease repeat counter
clc ;no new note
rts
@no_repeat:
lda FT_CHN_PTR_L,x ;load channel pointer into temp
sta <FT_TEMP_PTR_L
lda FT_CHN_PTR_H,x
sta <FT_TEMP_PTR_H
@no_repeat_r:
ldy #0
@read_byte:
lda (FT_TEMP_PTR),y ;read byte of the channel
inc <FT_TEMP_PTR_L ;advance pointer
bne @no_inc_ptr1
inc <FT_TEMP_PTR_H
@no_inc_ptr1:
ora #0
bmi @special_code ;bit 7 0=note 1=special code
lsr a ;bit 0 set means the note is followed by an empty row
bcc @no_empty_row
inc FT_CHN_REPEAT,x ;set repeat counter to 1
@no_empty_row:
sta FT_CHN_NOTE,x ;store note code
sec ;new note flag is set
bcs @done ;bra
@special_code:
and #$7f
lsr a
bcs @set_empty_rows
asl a
asl a
sta FT_CHN_INSTRUMENT,x ;store instrument number*4
bcc @read_byte ;bra
@set_empty_rows:
cmp #$3d
bcc @set_repeat
beq @set_speed
cmp #$3e
beq @set_loop
@set_reference:
clc ;remember return address+3
lda <FT_TEMP_PTR_L
adc #3
sta FT_CHN_RETURN_L,x
lda <FT_TEMP_PTR_H
adc #0
sta FT_CHN_RETURN_H,x
lda (FT_TEMP_PTR),y ;read length of the reference (how many rows)
sta FT_CHN_REF_LEN,x
iny
lda (FT_TEMP_PTR),y ;read 16-bit absolute address of the reference
sta <FT_TEMP_VAR1 ;remember in temp
iny
lda (FT_TEMP_PTR),y
sta <FT_TEMP_PTR_H
lda <FT_TEMP_VAR1
sta <FT_TEMP_PTR_L
ldy #0
jmp @read_byte
@set_speed:
lda (FT_TEMP_PTR),y
sta FT_SONG_SPEED
inc <FT_TEMP_PTR_L ;advance pointer after reading the speed value
bne @read_byte
inc <FT_TEMP_PTR_H
bne @read_byte ;bra
@set_loop:
lda (FT_TEMP_PTR),y
sta <FT_TEMP_VAR1
iny
lda (FT_TEMP_PTR),y
sta <FT_TEMP_PTR_H
lda <FT_TEMP_VAR1
sta <FT_TEMP_PTR_L
dey
jmp @read_byte
@set_repeat:
sta FT_CHN_REPEAT,x ;set up repeat counter, carry is clear, no new note
@done:
lda FT_CHN_REF_LEN,x ;check reference row counter
beq @no_ref ;if it is zero, there is no reference
dec FT_CHN_REF_LEN,x ;decrease row counter
bne @no_ref
lda FT_CHN_RETURN_L,x ;end of a reference, return to previous pointer
sta FT_CHN_PTR_L,x
lda FT_CHN_RETURN_H,x
sta FT_CHN_PTR_H,x
rts
@no_ref:
lda <FT_TEMP_PTR_L
sta FT_CHN_PTR_L,x
lda <FT_TEMP_PTR_H
sta FT_CHN_PTR_H,x
rts
;------------------------------------------------------------------------------
; stop DPCM sample if it plays
;------------------------------------------------------------------------------
FamiToneSampleStop:
lda #%00001111
sta APU_SND_CHN
rts
.if(FT_DPCM_ENABLE)
;------------------------------------------------------------------------------
; play DPCM sample, used by music player, could be used externally
; in: A is number of a sample, 1..63
;------------------------------------------------------------------------------
FamiToneSamplePlayM: ;for music (low priority)
ldx FT_DPCM_EFFECT
beq _FT2SamplePlay
tax
lda APU_SND_CHN
and #16
beq @not_busy
rts
@not_busy:
sta FT_DPCM_EFFECT
txa
jmp _FT2SamplePlay
;------------------------------------------------------------------------------
; play DPCM sample with higher priority, for sound effects
; in: A is number of a sample, 1..63
;------------------------------------------------------------------------------
FamiToneSamplePlay:
ldx #1
stx FT_DPCM_EFFECT
_FT2SamplePlay:
sta <FT_TEMP ;sample number*3, offset in the sample table
asl a
clc
adc <FT_TEMP
adc FT_DPCM_LIST_L
sta <FT_TEMP_PTR_L
lda #0
adc FT_DPCM_LIST_H
sta <FT_TEMP_PTR_H
lda #%00001111 ;stop DPCM
sta APU_SND_CHN
ldy #0
lda (FT_TEMP_PTR),y ;sample offset
sta APU_DMC_START
iny
lda (FT_TEMP_PTR),y ;sample length
sta APU_DMC_LEN
iny
lda (FT_TEMP_PTR),y ;pitch and loop
sta APU_DMC_FREQ
lda #32 ;reset DAC counter
sta APU_DMC_RAW
lda #%00011111 ;start DMC
sta APU_SND_CHN
rts
.endif
.if(FT_SFX_ENABLE)
;------------------------------------------------------------------------------
; init sound effects player, set pointer to data
; in: A,X is address of sound effects data
;------------------------------------------------------------------------------
FamiToneSfxInit:
sta <FT_TEMP_PTR_L
stx <FT_TEMP_PTR_H
ldy #0
@ntsc:
lda (FT_TEMP_PTR),y ;read and store pointer to the effects list
sta FT_SFX_ADR_L
iny
lda (FT_TEMP_PTR),y
sta FT_SFX_ADR_H
ldx #FT_SFX_CH0 ;init all the streams
@set_channels:
jsr _FT2SfxClearChannel
txa
clc
adc #FT_SFX_STRUCT_SIZE
tax
cpx #FT_SFX_STRUCT_SIZE*FT_SFX_STREAMS
bne @set_channels
rts
;internal routine, clears output buffer of a sound effect
;in: A is 0
; X is offset of sound effect stream
_FT2SfxClearChannel:
lda #0
sta FT_SFX_PTR_H,x ;this stops the effect
sta FT_SFX_REPEAT,x
sta FT_SFX_OFF,x
sta FT_SFX_BUF+6,x ;mute triangle
lda #$30
sta FT_SFX_BUF+0,x ;mute pulse1
sta FT_SFX_BUF+3,x ;mute pulse2
sta FT_SFX_BUF+9,x ;mute noise
rts
;------------------------------------------------------------------------------
; play sound effect
; in: A is a number of the sound effect 0..127
; X is offset of sound effect channel, should be FT_SFX_CH0..FT_SFX_CH3
;------------------------------------------------------------------------------
FamiToneSfxPlay:
asl a ;get offset in the effects list
tay
jsr _FT2SfxClearChannel ;stops the effect if it plays
lda FT_SFX_ADR_L
sta <FT_TEMP_PTR_L
lda FT_SFX_ADR_H
sta <FT_TEMP_PTR_H
lda (FT_TEMP_PTR),y ;read effect pointer from the table
sta FT_SFX_PTR_L,x ;store it
iny
lda (FT_TEMP_PTR),y
sta FT_SFX_PTR_H,x ;this write enables the effect
rts
;internal routine, update one sound effect stream
;in: X is offset of sound effect stream
_FT2SfxUpdate:
lda FT_SFX_REPEAT,x ;check if repeat counter is not zero
beq @no_repeat
dec FT_SFX_REPEAT,x ;decrement and return
bne @update_buf ;just mix with output buffer
@no_repeat:
lda FT_SFX_PTR_H,x ;check if MSB of the pointer is not zero
bne @sfx_active
rts ;return otherwise, no active effect
@sfx_active:
sta <FT_TEMP_PTR_H ;load effect pointer into temp
lda FT_SFX_PTR_L,x
sta <FT_TEMP_PTR_L
ldy FT_SFX_OFF,x
clc
@read_byte:
lda (FT_TEMP_PTR),y ;read byte of effect
bmi @get_data ;if bit 7 is set, it is a register write
beq @eof
iny
sta FT_SFX_REPEAT,x ;if bit 7 is reset, it is number of repeats
tya
sta FT_SFX_OFF,x
jmp @update_buf
@get_data:
iny
stx <FT_TEMP_VAR1 ;it is a register write
adc <FT_TEMP_VAR1 ;get offset in the effect output buffer
tax
lda (FT_TEMP_PTR),y ;read value
iny
sta FT_SFX_BUF-128,x ;store into output buffer
ldx <FT_TEMP_VAR1
jmp @read_byte ;and read next byte
@eof:
sta FT_SFX_PTR_H,x ;mark channel as inactive
@update_buf:
lda FT_OUT_BUF ;compare effect output buffer with main output buffer
and #$0f ;if volume of pulse 1 of effect is higher than that of the
sta <FT_TEMP_VAR1 ;main buffer, overwrite the main buffer value with the new one
lda FT_SFX_BUF+0,x
and #$0f
cmp <FT_TEMP_VAR1
bcc @no_pulse1
lda FT_SFX_BUF+0,x
sta FT_OUT_BUF+0
lda FT_SFX_BUF+1,x
sta FT_OUT_BUF+1
lda FT_SFX_BUF+2,x
sta FT_OUT_BUF+2
@no_pulse1:
lda FT_OUT_BUF+3 ;same for pulse 2
and #$0f
sta <FT_TEMP_VAR1
lda FT_SFX_BUF+3,x
and #$0f
cmp <FT_TEMP_VAR1
bcc @no_pulse2
lda FT_SFX_BUF+3,x
sta FT_OUT_BUF+3
lda FT_SFX_BUF+4,x
sta FT_OUT_BUF+4
lda FT_SFX_BUF+5,x
sta FT_OUT_BUF+5
@no_pulse2:
lda FT_SFX_BUF+6,x ;overwrite triangle of main output buffer if it is active
beq @no_triangle
sta FT_OUT_BUF+6
lda FT_SFX_BUF+7,x
sta FT_OUT_BUF+7
lda FT_SFX_BUF+8,x
sta FT_OUT_BUF+8
@no_triangle:
lda FT_OUT_BUF+9 ;same as for pulse 1 and 2, but for noise
and #$0f
sta <FT_TEMP_VAR1
lda FT_SFX_BUF+9,x
and #$0f
cmp <FT_TEMP_VAR1
bcc @no_noise
lda FT_SFX_BUF+9,x
sta FT_OUT_BUF+9
lda FT_SFX_BUF+10,x
sta FT_OUT_BUF+10
@no_noise:
rts
.endif
;dummy envelope used to initialize all channels with silence
_FT2DummyEnvelope:
.byte $c0,$00,$00
;PAL and NTSC, 11-bit dividers
;rest note, then octaves 1-5, then three zeroes
;first 64 bytes are PAL, next 64 bytes are NTSC
_FT2NoteTableLSB:
.if(FT_PAL_SUPPORT)
.byte $00,$33,$da,$86,$36,$eb,$a5,$62,$23,$e7,$af,$7a,$48,$19,$ec,$c2
.byte $9a,$75,$52,$30,$11,$f3,$d7,$bc,$a3,$8c,$75,$60,$4c,$3a,$28,$17
.byte $08,$f9,$eb,$dd,$d1,$c5,$ba,$af,$a5,$9c,$93,$8b,$83,$7c,$75,$6e
.byte $68,$62,$5c,$57,$52,$4d,$49,$45,$41,$3d,$3a,$36,$33,$30,$2d,$2b
.endif
.if(FT_NTSC_SUPPORT)
.byte $00,$ad,$4d,$f2,$9d,$4c,$00,$b8,$74,$34,$f7,$be,$88,$56,$26,$f8
.byte $ce,$a5,$7f,$5b,$39,$19,$fb,$de,$c3,$aa,$92,$7b,$66,$52,$3f,$2d
.byte $1c,$0c,$fd,$ee,$e1,$d4,$c8,$bd,$b2,$a8,$9f,$96,$8d,$85,$7e,$76
.byte $70,$69,$63,$5e,$58,$53,$4f,$4a,$46,$42,$3e,$3a,$37,$34,$31,$2e
.endif
_FT2NoteTableMSB:
.if(FT_PAL_SUPPORT)
.byte $00,$06,$05,$05,$05,$04,$04,$04,$04,$03,$03,$03,$03,$03,$02,$02
.byte $02,$02,$02,$02,$02,$01,$01,$01,$01,$01,$01,$01,$01,$01,$01,$01
.byte $01,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.endif
.if(FT_NTSC_SUPPORT)
.byte $00,$06,$06,$05,$05,$05,$05,$04,$04,$04,$03,$03,$03,$03,$03,$02
.byte $02,$02,$02,$02,$02,$02,$01,$01,$01,$01,$01,$01,$01,$01,$01,$01
.byte $01,$01,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.byte $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
.endif |
ninjadynamics/MMC3Template | 8,950 | music_dedricil.s | ; This file for the FamiTone2 library and was generated by FamiStudio
_dedricil_music_data:
.byte 1
.word @instruments
.word @samples-45
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256 ; 00 : 8. Eerie
@instruments:
.byte $70 ; 00 : Blip 25to12.5
.word @env4, @env2, @env6
.byte $00
.byte $30 ; 01 : Drums
.word @env3, @env2, @env2
.byte $00
.byte $30 ; 02 : Lead Echo
.word @env1, @env2, @env2
.byte $00
.byte $30 ; 03 : Lead Echo 2
.word @env5, @env2, @env2
.byte $00
.byte $30 ; 04 : Snare
.word @env7, @env2, @env2
.byte $00
.byte $30 ; 05 : Tri Lead
.word @env0, @env2, @env6
.byte $00
@samples:
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$01 ;15 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$01 ;16 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$02 ;17 (Gimmick!1.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$03 ;18 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$03 ;19 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$04 ;20 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$04 ;21 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$05 ;22 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$05 ;23 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$06 ;24 (Gimmick!1.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$07 ;25 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$07 ;26 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$08 ;27 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$08 ;28 (Gimmick!4.dmc)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$09 ;29 (Gimmick!3.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$09 ;30 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$09 ;31 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0a ;32 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$0a ;33 (Gimmick!4.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0b ;34 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$0b ;35 (Gimmick!4.dmc)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$0c ;36 (Gimmick!3.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0c ;37 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$0c ;38 (Gimmick!4.dmc)
.byte $30+.lobyte(FT_DPCM_PTR),$3f,$0d ;39 (Gimmick!5.dmc)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$0d ;40 (Gimmick!3.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0d ;41 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$0d ;42 (Gimmick!4.dmc)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$0e ;43 (Gimmick!3.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0e ;44 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$0e ;45 (Gimmick!4.dmc)
.byte $40+.lobyte(FT_DPCM_PTR),$3f,$0e ;46 (Gimmick!2.dmc)
.byte $30+.lobyte(FT_DPCM_PTR),$3f,$0f ;47 (Gimmick!5.dmc)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$0f ;48 (Gimmick!3.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0f ;49 (Gimmick!1.dmc)
.byte $10+.lobyte(FT_DPCM_PTR),$3f,$0f ;50 (Gimmick!4.dmc)
.byte $40+.lobyte(FT_DPCM_PTR),$3f,$0f ;51 (Gimmick!2.dmc)
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;52
.byte $50+.lobyte(FT_DPCM_PTR),$0c,$0f ;53 (BassDrum)
.byte $53+.lobyte(FT_DPCM_PTR),$00,$0f ;54 (Blank)
.byte $53+.lobyte(FT_DPCM_PTR),$30,$0f ;55 (Snare)
@env0:
.byte $cc,$cb,$ca,$c9,$c8,$c8,$c7,$03,$c6,$03,$c5,$0b,$c4,$00,$0c
@env1:
.byte $ca,$c9,$c9,$c8,$c8,$c7,$c7,$c6,$c6,$c5,$05,$c4,$00,$0b
@env2:
.byte $c0,$7f,$00,$01
@env3:
.byte $c6,$c5,$c4,$c3,$c2,$c1,$c0,$00,$06
@env4:
.byte $ce,$cd,$cd,$cc,$cc,$cb,$cb,$ca,$ca,$c9,$05,$c8,$08,$c8,$00,$0b
@env5:
.byte $c7,$c6,$c6,$c5,$c5,$c4,$c4,$c3,$c3,$c2,$05,$c1,$00,$0b
@env6:
.byte $c0,$1c,$bf,$c0,$c1,$c2,$c1,$c0,$bf,$be,$00,$02
@env7:
.byte $cd,$ca,$c8,$c6,$c5,$c4,$c3,$03,$c2,$03,$c1,$04,$c0,$00,$0c
@song0ch0:
.byte $fb, $01
@song0ref3:
.byte $80, $30, $8d, $86, $40, $8b, $80, $3a, $8d, $86, $30, $8b, $80, $40, $8d, $86, $3a, $8b, $80, $48, $8d, $86, $40, $8b
.byte $80, $4a, $8d, $86, $48, $8b, $80, $48, $8d, $86, $4a, $8b, $80, $40, $8d, $86, $48, $8b, $80, $3a, $8d, $86, $40, $8b
.byte $ff, $20
.word @song0ref3
@song0ref54:
.byte $80, $2e, $8d, $86, $3e, $8b, $80, $38, $8d, $86, $2e, $8b, $80, $3e, $8d, $86, $38, $8b, $80, $46, $8d, $86, $3e, $8b
.byte $80, $48, $8d, $86, $46, $8b, $80, $46, $8d, $86, $48, $8b, $80, $3e, $8d, $86, $46, $8b, $80, $38, $8d, $86, $3e, $8b
.byte $ff, $20
.word @song0ref54
@song0ch0loop:
.byte $ff, $20
.word @song0ref3
.byte $ff, $20
.word @song0ref3
.byte $ff, $20
.word @song0ref54
.byte $ff, $20
.word @song0ref54
.byte $ff, $20
.word @song0ref3
.byte $ff, $20
.word @song0ref3
.byte $ff, $20
.word @song0ref54
.byte $ff, $20
.word @song0ref54
@song0ref130:
.byte $80, $52, $8d, $86, $3a, $8b, $80, $50, $8d, $86, $52, $8b, $80, $4a, $8d, $86, $50, $8b, $80, $48, $8d, $86, $4a, $8b
.byte $80, $44, $8d, $86, $48, $8b, $80, $40, $8d, $86, $44, $8b, $80, $3e, $8d, $86, $40, $8b, $80, $3a, $8d, $86, $3e, $8b
.byte $80, $50, $8d, $86, $38, $8b, $80, $4e, $8d, $86, $50, $8b, $80, $48, $8d, $86, $4e, $8b, $80, $46, $8d, $86, $48, $8b
.byte $80, $42, $8d, $86, $46, $8b, $80, $3e, $8d, $86, $42, $8b, $80, $3c, $8d, $86, $3e, $8b, $80, $38, $8d, $86, $3c, $8b
.byte $80, $36, $8d, $86, $4e, $8b, $80, $3a, $8d, $86, $36, $8b, $80, $3c, $8d, $86, $3a, $8b, $80, $40, $8d, $86, $3c, $8b
.byte $80, $44, $8d, $86, $40, $8b, $80, $46, $8d, $86, $44, $8b, $80, $4c, $8d, $86, $46, $8b, $80, $4e, $8d, $86, $4c, $8b
.byte $80, $34, $8d, $86, $4c, $8b, $80, $38, $8d, $86, $34, $8b, $80, $3a, $8d, $86, $38, $8b, $80, $3e, $8d, $86, $3a, $8b
.byte $80, $42, $8d, $86, $3e, $8b, $80, $44, $8d, $86, $42, $8b, $80, $4a, $8d, $86, $44, $8b, $80, $4c, $8d, $86, $4a, $8b
.byte $ff, $80
.word @song0ref130
.byte $fd
.word @song0ch0loop
@song0ch1:
.byte $f9, $f9, $f9, $f1, $f9, $f9, $f9, $f1
@song0ch1loop:
@song0ref337:
.byte $84, $30, $9b, $86, $30, $9b, $84, $30, $9b, $86, $30, $9b, $84, $30, $9b, $86, $30, $9b, $84, $30, $9b, $86, $30, $9b
.byte $84, $0a, $9b, $86, $0a, $9b, $84, $0a, $9b, $86, $0a, $9b, $84, $0a, $9b, $86, $0a, $9b, $84, $0a, $9b, $86, $0a, $9b
@song0ref385:
.byte $84, $2e, $9b, $86, $2e, $9b, $84, $2e, $9b, $86, $2e, $9b, $84, $2e, $9b, $86, $2e, $9b, $84, $2e, $9b, $86, $2e, $9b
.byte $84, $08, $9b, $86, $08, $9b, $84, $08, $9b, $86, $08, $9b, $84, $08, $9b, $86, $08, $9b, $84, $08, $9b, $86, $08, $9b
.byte $ff, $40
.word @song0ref337
.byte $ff, $10
.word @song0ref337
.byte $ff, $10
.word @song0ref385
@song0ref442:
.byte $84, $2c, $9b, $86, $2c, $9b, $84, $2c, $9b, $86, $2c, $9b, $84, $2c, $9b, $86, $2c, $9b, $84, $2c, $9b, $86, $2c, $9b
.byte $84, $2a, $9b, $86, $2a, $9b, $84, $2a, $9b, $86, $2a, $9b, $84, $2a, $9b, $86, $2a, $9b, $84, $2a, $9b, $86, $2a, $9b
.byte $ff, $10
.word @song0ref337
.byte $ff, $10
.word @song0ref385
.byte $ff, $20
.word @song0ref442
.byte $fd
.word @song0ch1loop
@song0ch2:
.byte $f9, $f9, $f9, $f1, $f9, $f9, $f3, $8a, $20, $b9, $50, $b9
@song0ch2loop:
.byte $8a
@song0ref516:
.byte $52, $f9, $f3, $58, $f5, $56, $f5, $50, $f9, $b7, $46, $b9, $50, $f9, $f3
.byte $ff, $0f
.word @song0ref516
@song0ref534:
.byte $6a, $b9, $68, $b9, $52, $b9, $6a, $b9, $68, $b9, $60, $b9, $56, $b9, $50, $b9, $66, $f9, $b7, $6a, $b9, $64, $f9, $b7
.byte $64, $9b, $00, $9b
.byte $ff, $1c
.word @song0ref534
.byte $fd
.word @song0ch2loop
@song0ch3:
@song0ref568:
.byte $88, $76, $9b, $82, $78, $9b, $78, $9b, $78, $9b, $78, $9b, $78, $9b, $78, $9b, $78, $9b
.byte $ff, $10
.word @song0ref568
.byte $ff, $10
.word @song0ref568
.byte $ff, $10
.word @song0ref568
@song0ch3loop:
.byte $82
@song0ref597:
.byte $78, $9b, $78, $9b, $88, $76, $9b, $82, $78, $9b, $78, $9b, $78, $9b, $88, $76, $9b, $82, $78, $9b
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $ff, $10
.word @song0ref597
.byte $fd
.word @song0ch3loop
@song0ch4:
.byte $3a, $f9, $f3, $3a, $f9, $b7, $52, $b9, $50, $f9, $b7, $46, $b9, $50, $f9, $b7, $50, $9b, $38, $9b
@song0ch4loop:
@song0ref686:
.byte $6a, $9b, $3a, $b9, $3a, $9b, $6e, $9b, $3a, $9b, $52, $9b, $3a, $9b, $6a, $9b, $3a, $b9, $3a, $9b, $6e, $9b, $58, $9b
.byte $52, $9b, $58, $9b, $6a, $9b, $38, $b9, $38, $9b, $6e, $9b, $38, $b9, $50, $9b, $6a, $9b, $38, $b9, $38, $9b, $6e, $9b
.byte $56, $9b, $50, $9b, $56, $9b
.byte $ff, $36
.word @song0ref686
.byte $ff, $10
.word @song0ref686
@song0ref746:
.byte $38, $b9, $38, $9b, $6e, $9b, $56, $9b, $50, $9b, $56, $9b, $6a, $9b, $36, $b9, $36, $9b, $6e, $9b, $36, $9b, $4e, $9b
.byte $36, $9b, $6a, $9b, $34, $b9, $34, $9b, $6e, $9b, $52, $9b, $4c, $9b, $52, $9b
.byte $ff, $10
.word @song0ref686
.byte $ff, $28
.word @song0ref746
.byte $fd
.word @song0ch4loop
|
ninjadynamics/MMC3Template | 10,357 | music_dangerstreets.s | ;this file for FamiTone2 library generated by text2data tool
_the_moon_music_data:
.byte 1
.word @instruments
.word @samples-3
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256
@instruments:
.byte $30 ; 00 : Bass
.word @env0, @env4, @env4
.byte $00
.byte $f0 ; 01 : Bleep
.word @env3, @env4, @env4
.byte $00
.byte $70 ; 02 : BleepIntro
.word @env9, @env4, @env4
.byte $00
.byte $30 ; 03 : DrumHi
.word @env10, @env4, @env4
.byte $00
.byte $30 ; 04 : DrumIntro
.word @env8, @env4, @env4
.byte $00
.byte $30 ; 05 : DrumLo
.word @env7, @env4, @env4
.byte $00
.byte $30 ; 06 : DrumMed
.word @env1, @env4, @env4
.byte $00
.byte $30 ; 07 : Lead
.word @env2, @env4, @env4
.byte $00
.byte $f0 ; 08 : LeadIntro
.word @env6, @env4, @env4
.byte $00
.byte $30 ; 09 : LeadLo
.word @env5, @env4, @env4
.byte $00
@env0:
.byte $cf,$7f,$00,$00
@env1:
.byte $ca,$02,$c6,$03,$c2,$00,$04
@env2:
.byte $ca,$7f,$00,$00
@env3:
.byte $c7,$02,$c5,$03,$c1,$00,$04
@env4:
.byte $c0,$7f,$00,$01
@env5:
.byte $c7,$7f,$00,$00
@env6:
.byte $c1,$c2,$c3,$c4,$c5,$c6,$c7,$c8,$c9,$ca,$00,$09
@env7:
.byte $ca,$02,$c2,$00,$02
@env8:
.byte $ca,$02,$c5,$00,$02
@env9:
.byte $c7,$06,$c1,$00,$02
@env10:
.byte $ca,$c4,$00,$01
@samples:
@song0ch0:
.byte $fb, $01, $f9, $f9, $b7, $90, $4c, $f9, $b5, $00, $56, $a3, $00, $5a, $a3, $00, $60, $a3, $00, $60, $b7, $00, $5e, $8f
.byte $00, $5e, $f9, $8d, $00, $5a, $a3, $00, $56, $a3, $00, $64, $f3, $00, $56, $f3, $00, $6e, $b9, $f9, $f3, $00, $72, $a3
.byte $00, $6e, $8f, $00, $7c, $f9, $f9, $c7, $00
@song0ch0loop:
.byte $cf, $8e, $46, $8f, $00, $48, $8f, $00, $4c, $8f, $00, $4c, $b7, $00, $56, $a3, $00, $54, $a3, $00, $56, $a3, $00, $5a
.byte $a3, $00, $5e, $8f, $00, $56, $f9, $dd, $00, $54, $8f, $00, $56, $8f, $00, $64, $b7, $00, $56, $8f, $00, $56, $f9, $dd
.byte $00, $56, $8f, $00, $56, $cb, $00, $93, $5a, $8f, $00, $56, $8f, $00, $54, $f9, $b5, $00, $46, $cb, $00, $93, $42, $8f
.byte $00, $3e, $8f, $00, $4c, $cb, $00, $93, $56, $a3, $00, $5a, $a3, $00, $60, $b7, $00, $5e, $8f, $00, $5e, $f9, $a1, $00
.byte $64, $a3, $00, $60, $a3, $00, $5e, $8f, $00, $60, $8f, $00, $5e, $8f, $00, $56, $a3, $00, $4c, $cb, $00, $5a, $8f, $00
.byte $56, $8f, $00, $54, $8f, $00, $50, $8f, $00, $54, $b7, $00, $56, $8f, $00, $a7, $56, $8f, $00, $a7, $56, $a3, $00, $8d
.byte $2e, $f9, $93, $00
@song0ref207:
.byte $56, $8f, $00, $56, $8f, $00, $a7, $5a, $8f, $00, $5a, $8f, $00, $93, $52, $cb, $00, $4c, $a3, $00, $52, $8f, $00, $48
.byte $83, $4a, $83, $00, $49, $00, $44, $8f, $00, $48, $a3, $00, $44, $8f, $00, $48, $8f, $00, $93, $44, $8f, $00, $93, $4c
.byte $f9, $a1, $00, $93
.byte $ff, $0e
.word @song0ref207
.byte $5c, $a3, $00, $52, $a3, $00, $52, $a3, $00, $52, $8f, $00, $5c, $8f, $00, $60, $91, $f5, $00, $5c, $8f, $00, $64, $f3
.byte $00, $64, $8f, $00, $64, $8f, $00, $64, $91, $f9, $f3, $00, $1e, $a3, $00, $22, $a3, $00, $fd
.word @song0ch0loop
@song0ch1:
.byte $84
@song0ref308:
.byte $56, $8f, $00, $64, $8f, $00, $6e, $8f, $00, $72, $8f, $00, $64, $8f, $00, $6e, $8f, $00, $72
@song0ref327:
.byte $8f, $00, $78, $8f, $00, $64, $8f, $00, $78, $8f, $00, $76, $8f, $00, $64, $8f, $00, $76, $8f, $00, $72, $8f, $00, $6e
.byte $8f, $00
.byte $ff, $2d
.word @song0ref308
.byte $ff, $2d
.word @song0ref308
.byte $ff, $2d
.word @song0ref308
.byte $ff, $2d
.word @song0ref308
.byte $82
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
@song0ch1loop:
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $6e, $8f, $00, $5c, $8f, $00, $66, $8f, $00, $72, $8f, $00, $60, $8f, $00, $72, $8f, $00, $78, $8f, $00, $76, $8f, $00
.byte $6e, $8f, $00, $64, $8f, $00, $60, $8f, $00, $5e, $8f, $00, $56, $8f, $00, $4c, $8f, $00, $48, $8f, $00, $46, $8f, $00
.byte $92, $44, $8f, $00, $44, $8f, $00, $a7, $48, $8f, $00, $48, $8f, $00, $93, $44, $a3, $00, $84, $5a, $8f, $00, $5c, $8f
.byte $00, $6a, $8f, $00, $93, $72, $8f, $00, $74, $8f, $00, $02, $8f, $00, $92, $36, $a3, $00, $36, $8f, $00, $36, $8f, $00
.byte $93, $36, $8f, $00, $93, $3c, $f9, $a1, $00, $93, $4e, $8f, $00, $4e, $8f, $00, $a7, $48, $8f, $00, $48, $8f, $00, $93
.byte $4c, $a3, $00, $4c, $a3, $00, $4c, $a3, $00, $4c, $8f, $00, $52, $8f, $00, $56, $91, $e1, $00, $93, $56, $8f, $00, $54
.byte $f3, $00, $54, $8f, $00, $54, $8f, $00, $56, $8f, $00, $82
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $fd
.word @song0ch1loop
@song0ch2:
.byte $f9, $f9, $b7, $80, $3e, $b7, $00, $4c, $b7, $00, $56, $f9, $a1, $00, $93, $3a, $b7, $00, $48, $b7, $00, $52, $f9, $a1
.byte $00, $93, $38, $b7, $00, $46, $b7, $00, $50, $f9, $a1, $00, $93, $36, $b7, $00, $44, $b7, $00, $4e, $f9, $a1, $00, $93
@song0ref637:
.byte $56, $8f, $00, $56, $8f, $00, $56, $8f, $00, $56, $8f, $00
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
@song0ch2loop:
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
@song0ref665:
.byte $54, $8f, $00, $54, $8f, $00, $54, $8f, $00, $54, $8f, $00
.byte $ff, $0c
.word @song0ref665
@song0ref680:
.byte $50, $8f, $00, $50, $8f, $00, $50, $8f, $00, $50, $8f, $00
.byte $ff, $0c
.word @song0ref680
@song0ref695:
.byte $4c, $8f, $00, $4c, $8f, $00, $4c, $8f, $00, $4c, $8f, $00
.byte $ff, $0c
.word @song0ref695
@song0ref710:
.byte $48, $8f, $00, $48, $8f, $00, $48, $8f, $00, $48, $8f, $00
.byte $ff, $0c
.word @song0ref710
@song0ref725:
.byte $4a, $8f, $00, $4a, $8f, $00, $4a, $8f, $00, $4a, $8f, $00
.byte $ff, $0c
.word @song0ref725
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
@song0ref758:
.byte $52, $8f, $00, $52, $8f, $00, $52, $8f, $00, $52, $8f, $00
.byte $ff, $0c
.word @song0ref758
.byte $ff, $0c
.word @song0ref680
.byte $ff, $0c
.word @song0ref680
@song0ref779:
.byte $4e, $8f, $00, $4e, $8f, $00, $4e, $8f, $00, $4e, $8f, $00
.byte $ff, $0c
.word @song0ref779
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref725
.byte $ff, $0c
.word @song0ref695
.byte $4e, $8f, $00, $a7, $52, $8f, $00, $a7, $56, $b7, $00, $3e, $8f, $00, $3e, $8f, $00, $3e, $8f, $00, $3e, $8f, $00, $3e
.byte $8f, $00, $3e, $8f, $00, $3e, $8f, $00
@song0ref838:
.byte $48, $8f, $00, $48, $8f, $00, $a7, $52, $8f, $00, $52, $8f, $00, $93, $44, $a3, $00, $44, $8f, $00, $44, $8f, $00, $44
.byte $8f, $00, $44, $8f, $00, $44, $8f, $00, $44, $8f, $00, $44, $8f, $00
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $26
.word @song0ref838
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref779
.byte $ff, $0c
.word @song0ref779
.byte $4e, $8f, $00, $bb, $4e, $a3, $00, $52, $a3, $00, $fd
.word @song0ch2loop
@song0ch3:
@song0ref922:
.byte $f9, $f9, $b7, $f9, $f9, $b7, $f9, $f9, $b7, $f9, $f9, $b7, $f9, $e1, $88, $4a, $8b, $00, $83, $40, $8b, $00, $83, $4a
.byte $8b, $00, $83, $40, $8b, $00, $83
@song0ref953:
.byte $8a, $40, $8b, $00, $83, $86, $58, $83, $00, $8b, $8c, $4a, $8f, $00, $86, $58, $83, $00, $8b
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
@song0ref978:
.byte $8a, $40, $8b, $00, $83, $86, $58, $83, $00, $8b, $8c, $4a, $8f, $00, $4a, $8f, $00
@song0ch3loop:
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $fd
.word @song0ch3loop
@song0ch4:
.byte $ff, $0d
.word @song0ref922
.byte $f9, $b7, $f9, $f9, $cb
@song0ch4loop:
@song0ref1164:
.byte $f9, $f9, $cb, $f9, $f9, $cb, $f9, $f9, $cb, $f9, $f9, $cb
.byte $ff, $0c
.word @song0ref1164
.byte $ff, $0c
.word @song0ref1164
.byte $f9, $f9, $cb, $fd
.word @song0ch4loop
|
ninjadynamics/MMC3Template | 15,192 | neslib.s | ;NES hardware-dependent functions by Shiru (shiru@mail.ru)
;with improvements by VEG
;Feel free to do anything you want with this code, consider it Public Domain
;nesdoug version, 2019-09
;minor change %%, added ldx #0 to functions returning char
;removed sprid from c functions to speed them up
;Ninja Dynamics
;added NMI callback functions
;added Convert to bool function
.export _pal_all,_pal_bg,_pal_spr,_pal_col,_pal_clear
.export _pal_bright,_pal_spr_bright,_pal_bg_bright
.export _ppu_off,_ppu_on_all,_ppu_on_bg,_ppu_on_spr,_ppu_mask,_ppu_system
.export _oam_clear,_oam_size,_oam_spr,_oam_meta_spr,_oam_hide_rest
.export _ppu_wait_frame,_ppu_wait_nmi
.export _scroll,_split
.export _bank_spr,_bank_bg
.export _vram_read,_vram_write
.export _pad_poll,_pad_trigger,_pad_state
.export _rand8,_rand16,_set_rand
.export _vram_adr,_vram_put,_vram_fill,_vram_inc,_vram_unrle
.export _set_vram_update,_flush_vram_update
.export _memcpy,_memfill,_delay
.export _get_ppu_ctrl_var,_set_ppu_ctrl_var
.export _flush_vram_update_nmi, _oam_set, _oam_get
.export _nmi_set_callback, _nmi_clear_callback
.export _to_bool
; https://discord.com/channels/352252932953079811/352436568062951427/1252666807798595687
; unsigned char __fastcall__ to_bool(unsigned char x);
_to_bool:
cmp #1 ; Compare A with 1, setting the carry flag if A != 0
lda #0 ; Clear A
rol a ; Rotate left through carry, setting A to 1 if the carry flag is set
rts ; Return from subroutine
;NMI handler
nmi:
pha
txa
pha
tya
pha
lda <PPU_MASK_VAR ;if rendering is disabled, do not access the VRAM at all
and #%00011000
bne @doUpdate
jmp @skipAll
@doUpdate:
lda #>OAM_BUF ;update OAM
sta PPU_OAM_DMA
lda <PAL_UPDATE ;update palette if needed
bne @updPal
jmp @updVRAM
@updPal:
ldx #0
stx <PAL_UPDATE
lda #$3f
sta PPU_ADDR
stx PPU_ADDR
ldy PAL_BUF ;background color, remember it in X
lda (PAL_BG_PTR),y
sta PPU_DATA
tax
.repeat 3,I
ldy PAL_BUF+1+I
lda (PAL_BG_PTR),y
sta PPU_DATA
.endrepeat
.repeat 3,J
stx PPU_DATA ;background color
.repeat 3,I
ldy PAL_BUF+5+(J*4)+I
lda (PAL_BG_PTR),y
sta PPU_DATA
.endrepeat
.endrepeat
.repeat 4,J
stx PPU_DATA ;background color
.repeat 3,I
ldy PAL_BUF+17+(J*4)+I
lda (PAL_SPR_PTR),y
sta PPU_DATA
.endrepeat
.endrepeat
@updVRAM:
lda <VRAM_UPDATE
beq @skipUpd
lda #0
sta <VRAM_UPDATE
lda <NAME_UPD_ENABLE
beq @skipUpd
jsr _flush_vram_update_nmi
@skipUpd:
lda #0
sta PPU_ADDR
sta PPU_ADDR
lda <SCROLL_X
sta PPU_SCROLL
lda <SCROLL_Y
sta PPU_SCROLL
lda <PPU_CTRL_VAR
sta PPU_CTRL
@skipAll:
lda <PPU_MASK_VAR
sta PPU_MASK
inc <FRAME_CNT1
inc <FRAME_CNT2
lda <FRAME_CNT2
cmp #6
bne skipNtsc
lda #0
sta <FRAME_CNT2
skipNtsc:
jsr NMICallback
; jsr FamiToneUpdate
pla
tay
pla
tax
pla
rti
; IRQ: jumps to NMICallback, passing -1 as argument
irq:
pha
txa
pha
tya
pha
lda #$ff
jmp skipNtsc
;void __fastcall__ nmi_set_callback(void (*callback)());
_nmi_set_callback:
sta NMICallback+1
stx NMICallback+2
HandyRTS:
rts
; void __fastcall__ nmi_clear_callback(void);
_nmi_clear_callback:
lda #$4C ;JMP xxxx
sta NMICallback
lda #<HandyRTS
sta NMICallback+1
lda #>HandyRTS
sta NMICallback+2
rts
;void __fastcall__ pal_all(const char *data);
_pal_all:
sta <PTR
stx <PTR+1
ldx #$00
lda #$20
pal_copy:
sta <LEN
ldy #$00
@0:
lda (PTR),y
sta PAL_BUF,x
inx
iny
dec <LEN
bne @0
inc <PAL_UPDATE
rts
;void __fastcall__ pal_bg(const char *data);
_pal_bg:
sta <PTR
stx <PTR+1
ldx #$00
lda #$10
bne pal_copy ;bra
;void __fastcall__ pal_spr(const char *data);
_pal_spr:
sta <PTR
stx <PTR+1
ldx #$10
txa
bne pal_copy ;bra
;void __fastcall__ pal_col(unsigned char index,unsigned char color);
_pal_col:
sta <PTR
jsr popa
and #$1f
tax
lda <PTR
sta PAL_BUF,x
inc <PAL_UPDATE
rts
;void __fastcall__ pal_clear(void);
_pal_clear:
lda #$0f
ldx #0
@1:
sta PAL_BUF,x
inx
cpx #$20
bne @1
stx <PAL_UPDATE
rts
;void __fastcall__ pal_spr_bright(unsigned char bright);
_pal_spr_bright:
tax
lda palBrightTableL,x
sta <PAL_SPR_PTR
lda palBrightTableH,x ;MSB is never zero
sta <PAL_SPR_PTR+1
sta <PAL_UPDATE
rts
;void __fastcall__ pal_bg_bright(unsigned char bright);
_pal_bg_bright:
tax
lda palBrightTableL,x
sta <PAL_BG_PTR
lda palBrightTableH,x ;MSB is never zero
sta <PAL_BG_PTR+1
sta <PAL_UPDATE
rts
;void __fastcall__ pal_bright(unsigned char bright);
_pal_bright:
jsr _pal_spr_bright
txa
jmp _pal_bg_bright
;void __fastcall__ ppu_off(void);
_ppu_off:
lda <PPU_MASK_VAR
and #%11100111
sta <PPU_MASK_VAR
jmp _ppu_wait_nmi
;void __fastcall__ ppu_on_all(void);
_ppu_on_all:
lda <PPU_MASK_VAR
ora #%00011000
ppu_onoff:
sta <PPU_MASK_VAR
jmp _ppu_wait_nmi
;void __fastcall__ ppu_on_bg(void);
_ppu_on_bg:
lda <PPU_MASK_VAR
ora #%00001000
bne ppu_onoff ;bra
;void __fastcall__ ppu_on_spr(void);
_ppu_on_spr:
lda <PPU_MASK_VAR
ora #%00010000
bne ppu_onoff ;bra
;void __fastcall__ ppu_mask(unsigned char mask);
_ppu_mask:
sta <PPU_MASK_VAR
rts
;unsigned char __fastcall__ ppu_system(void);
_ppu_system:
lda <NTSC_MODE
ldx #0
rts
;unsigned char __fastcall__ get_ppu_ctrl_var(void);
_get_ppu_ctrl_var:
lda <PPU_CTRL_VAR
ldx #$00
rts
;void __fastcall__ set_ppu_ctrl_var(unsigned char var);
_set_ppu_ctrl_var:
sta <PPU_CTRL_VAR
rts
;void __fastcall__ oam_clear(void);
_oam_clear:
ldx #0
stx SPRID ; automatically sets sprid to zero
lda #$ff
@1:
sta OAM_BUF,x
inx
inx
inx
inx
bne @1
rts
;void __fastcall__ oam_set(unsigned char index);
;to manually set the position
;a = sprid
_oam_set:
and #$fc ;strip those low 2 bits, just in case
sta SPRID
rts
;unsigned char __fastcall__ oam_get(void);
;returns the sprid
_oam_get:
lda SPRID
ldx #0
rts
;void __fastcall__ oam_size(unsigned char size);
_oam_size:
asl a
asl a
asl a
asl a
asl a
and #$20
sta <TEMP
lda <PPU_CTRL_VAR
and #$df
ora <TEMP
sta <PPU_CTRL_VAR
rts
;void __fastcall__ oam_spr(unsigned char x,unsigned char y,unsigned char chrnum,unsigned char attr);
;sprid removed
_oam_spr:
ldx SPRID
;a = chrnum
sta OAM_BUF+2,x
ldy #0 ;3 popa calls replacement
lda (sp),y
iny
sta OAM_BUF+1,x
lda (sp),y
iny
sta OAM_BUF+0,x
lda (sp),y
sta OAM_BUF+3,x
lda <sp
clc
adc #3 ;4
sta <sp
bcc @1
inc <sp+1
@1:
txa
clc
adc #4
sta SPRID
rts
;void __fastcall__ oam_meta_spr(unsigned char x,unsigned char y,const unsigned char *data);
;sprid removed
_oam_meta_spr:
sta <PTR
stx <PTR+1
ldy #1 ;2 popa calls replacement, performed in reversed order
lda (sp),y
dey
sta <SCRX
lda (sp),y
sta <SCRY
ldx SPRID
@1:
lda (PTR),y ;x offset
cmp #$80
beq @2
iny
clc
adc <SCRX
sta OAM_BUF+3,x
lda (PTR),y ;y offset
iny
clc
adc <SCRY
sta OAM_BUF+0,x
lda (PTR),y ;tile
iny
sta OAM_BUF+1,x
lda (PTR),y ;attribute
iny
sta OAM_BUF+2,x
inx
inx
inx
inx
jmp @1
@2:
lda <sp
adc #1 ;2 ;carry is always set here, so it adds 3
sta <sp
bcc @3
inc <sp+1
@3:
stx SPRID
rts
;void __fastcall__ oam_hide_rest(void);
;sprid removed
_oam_hide_rest:
ldx SPRID
lda #240
@1:
sta OAM_BUF,x
inx
inx
inx
inx
bne @1
;x is zero
stx SPRID
rts
;void __fastcall__ ppu_wait_frame(void);
_ppu_wait_frame:
lda #1
sta <VRAM_UPDATE
lda <FRAME_CNT1
@1:
cmp <FRAME_CNT1
beq @1
lda <NTSC_MODE
beq @3
@2:
lda <FRAME_CNT2
cmp #5
beq @2
@3:
rts
;void __fastcall__ ppu_wait_nmi(void);
_ppu_wait_nmi:
lda #1
sta <VRAM_UPDATE
lda <FRAME_CNT1
@1:
cmp <FRAME_CNT1
beq @1
rts
;void __fastcall__ vram_unrle(const unsigned char *data);
_vram_unrle:
tay
stx <RLE_HIGH
lda #0
sta <RLE_LOW
lda (RLE_LOW),y
sta <RLE_TAG
iny
bne @1
inc <RLE_HIGH
@1:
lda (RLE_LOW),y
iny
bne @11
inc <RLE_HIGH
@11:
cmp <RLE_TAG
beq @2
sta PPU_DATA
sta <RLE_BYTE
bne @1
@2:
lda (RLE_LOW),y
beq @4
iny
bne @21
inc <RLE_HIGH
@21:
tax
lda <RLE_BYTE
@3:
sta PPU_DATA
dex
bne @3
beq @1
@4:
rts
;void __fastcall__ scroll(unsigned int x,unsigned int y);
_scroll:
sta <TEMP
txa
bne @1
lda <TEMP
cmp #240
bcs @1
sta <SCROLL_Y
lda #0
sta <TEMP
beq @2 ;bra
@1:
sec
lda <TEMP
sbc #240
sta <SCROLL_Y
lda #2
sta <TEMP
@2:
jsr popax
sta <SCROLL_X
txa
and #$01
ora <TEMP
sta <TEMP
lda <PPU_CTRL_VAR
and #$fc
ora <TEMP
sta <PPU_CTRL_VAR
rts
;;void __fastcall__ split(unsigned int x);
;minor changes %%
_split:
; jsr popax
sta <SCROLL_X1
txa
and #$01
sta <TEMP
lda <PPU_CTRL_VAR
and #$fc
ora <TEMP
sta <PPU_CTRL_VAR1
@3:
bit PPU_STATUS
bvs @3
@4:
bit PPU_STATUS
bvc @4
lda <SCROLL_X1
sta PPU_SCROLL
lda #0
sta PPU_SCROLL
lda <PPU_CTRL_VAR1
sta PPU_CTRL
rts
;void __fastcall__ bank_spr(unsigned char n);
_bank_spr:
and #$01
asl a
asl a
asl a
sta <TEMP
lda <PPU_CTRL_VAR
and #%11110111
ora <TEMP
sta <PPU_CTRL_VAR
rts
;void __fastcall__ bank_bg(unsigned char n);
_bank_bg:
and #$01
asl a
asl a
asl a
asl a
sta <TEMP
lda <PPU_CTRL_VAR
and #%11101111
ora <TEMP
sta <PPU_CTRL_VAR
rts
;void __fastcall__ vram_read(unsigned char *dst,unsigned int size);
_vram_read:
sta <TEMP
stx <TEMP+1
jsr popax
sta <TEMP+2
stx <TEMP+3
lda PPU_DATA
ldy #0
@1:
lda PPU_DATA
sta (TEMP+2),y
inc <TEMP+2
bne @2
inc <TEMP+3
@2:
lda <TEMP
bne @3
dec <TEMP+1
@3:
dec <TEMP
lda <TEMP
ora <TEMP+1
bne @1
rts
;void __fastcall__ vram_write(unsigned char *src,unsigned int size);
_vram_write:
sta <TEMP
stx <TEMP+1
jsr popax
sta <TEMP+2
stx <TEMP+3
ldy #0
@1:
lda (TEMP+2),y
sta PPU_DATA
inc <TEMP+2
bne @2
inc <TEMP+3
@2:
lda <TEMP
bne @3
dec <TEMP+1
@3:
dec <TEMP
lda <TEMP
ora <TEMP+1
bne @1
rts
;unsigned char __fastcall__ pad_poll(unsigned char pad);
_pad_poll:
tay
ldx #3
@padPollPort:
lda #1
sta CTRL_PORT1
sta <PAD_BUF-1,x
lda #0
sta CTRL_PORT1
lda #8
sta <TEMP
@padPollLoop:
lda CTRL_PORT1,y
lsr a
rol <PAD_BUF-1,x
bcc @padPollLoop
dex
bne @padPollPort
lda <PAD_BUF
cmp <PAD_BUF+1
beq @done
cmp <PAD_BUF+2
beq @done
lda <PAD_BUF+1
@done:
sta <PAD_STATE,y
tax
eor <PAD_STATEP,y
and <PAD_STATE ,y
sta <PAD_STATET,y
txa
sta <PAD_STATEP,y
ldx #0
rts
;unsigned char __fastcall__ pad_trigger(unsigned char pad);
_pad_trigger:
pha
jsr _pad_poll
pla
tax
lda <PAD_STATET,x
ldx #0
rts
;unsigned char __fastcall__ pad_state(unsigned char pad);
_pad_state:
tax
lda <PAD_STATE,x
ldx #0
rts
;unsigned char __fastcall__ rand8(void);
;Galois random generator, found somewhere
;out: A random number 0..255
rand1:
lda <RAND_SEED
asl a
bcc @1
eor #$cf
@1:
sta <RAND_SEED
rts
rand2:
lda <RAND_SEED+1
asl a
bcc @1
eor #$d7
@1:
sta <RAND_SEED+1
rts
_rand8:
jsr rand1
jsr rand2
adc <RAND_SEED
ldx #0
rts
;unsigned int __fastcall__ rand16(void);
_rand16:
jsr rand1
tax
jsr rand2
rts
;void __fastcall__ set_rand(unsigned char seed);
_set_rand:
sta <RAND_SEED
stx <RAND_SEED+1
rts
;void __fastcall__ set_vram_update(unsigned char *buf);
_set_vram_update:
sta <NAME_UPD_ADR+0
stx <NAME_UPD_ADR+1
ora <NAME_UPD_ADR+1
sta <NAME_UPD_ENABLE
rts
;void __fastcall__ flush_vram_update(unsigned char *buf);
_flush_vram_update:
sta <NAME_UPD_ADR+0
stx <NAME_UPD_ADR+1
_flush_vram_update_nmi: ;minor changes %
ldy #0
@updName:
lda (NAME_UPD_ADR),y
iny
cmp #$40 ;is it a non-sequental write?
bcs @updNotSeq
sta PPU_ADDR
lda (NAME_UPD_ADR),y
iny
sta PPU_ADDR
lda (NAME_UPD_ADR),y
iny
sta PPU_DATA
jmp @updName
@updNotSeq:
tax
lda <PPU_CTRL_VAR
cpx #$80 ;is it a horizontal or vertical sequence?
bcc @updHorzSeq
cpx #$ff ;is it end of the update?
beq @updDone
@updVertSeq:
ora #$04
bne @updNameSeq ;bra
@updHorzSeq:
and #$fb
@updNameSeq:
sta PPU_CTRL
txa
and #$3f
sta PPU_ADDR
lda (NAME_UPD_ADR),y
iny
sta PPU_ADDR
lda (NAME_UPD_ADR),y
iny
tax
@updNameLoop:
lda (NAME_UPD_ADR),y
iny
sta PPU_DATA
dex
bne @updNameLoop
lda <PPU_CTRL_VAR
sta PPU_CTRL
jmp @updName
@updDone:
rts
;void __fastcall__ vram_adr(unsigned int adr);
_vram_adr:
stx PPU_ADDR
sta PPU_ADDR
rts
;void __fastcall__ vram_put(unsigned char n);
_vram_put:
sta PPU_DATA
rts
;void __fastcall__ vram_fill(unsigned char n,unsigned int len);
_vram_fill:
sta <LEN
stx <LEN+1
jsr popa
ldx <LEN+1
beq @2
ldx #0
@1:
sta PPU_DATA
dex
bne @1
dec <LEN+1
bne @1
@2:
ldx <LEN
beq @4
@3:
sta PPU_DATA
dex
bne @3
@4:
rts
;void __fastcall__ vram_inc(unsigned char n);
_vram_inc:
ora #0
beq @1
lda #$04
@1:
sta <TEMP
lda <PPU_CTRL_VAR
and #$fb
ora <TEMP
sta <PPU_CTRL_VAR
sta PPU_CTRL
rts
;void __fastcall__ memcpy(void *dst,void *src,unsigned int len);
_memcpy:
sta <LEN
stx <LEN+1
jsr popax
sta <SRC
stx <SRC+1
jsr popax
sta <DST
stx <DST+1
ldx #0
@1:
lda <LEN+1
beq @2
jsr @3
dec <LEN+1
inc <SRC+1
inc <DST+1
jmp @1
@2:
ldx <LEN
beq @5
@3:
ldy #0
@4:
lda (SRC),y
sta (DST),y
iny
dex
bne @4
@5:
rts
;void __fastcall__ memfill(void *dst,unsigned char value,unsigned int len);
_memfill:
sta <LEN
stx <LEN+1
jsr popa
sta <TEMP
jsr popax
sta <DST
stx <DST+1
ldx #0
@1:
lda <LEN+1
beq @2
jsr @3
dec <LEN+1
inc <DST+1
jmp @1
@2:
ldx <LEN
beq @5
@3:
ldy #0
lda <TEMP
@4:
sta (DST),y
iny
dex
bne @4
@5:
rts
;void __fastcall__ delay(unsigned char frames);
_delay:
tax
@1:
jsr _ppu_wait_nmi
dex
bne @1
rts
palBrightTableL:
.byte <palBrightTable0,<palBrightTable1,<palBrightTable2
.byte <palBrightTable3,<palBrightTable4,<palBrightTable5
.byte <palBrightTable6,<palBrightTable7,<palBrightTable8
palBrightTableH:
.byte >palBrightTable0,>palBrightTable1,>palBrightTable2
.byte >palBrightTable3,>palBrightTable4,>palBrightTable5
.byte >palBrightTable6,>palBrightTable7,>palBrightTable8
palBrightTable0:
.byte $0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f ;black
palBrightTable1:
.byte $0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f
palBrightTable2:
.byte $0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f
palBrightTable3:
.byte $0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f,$0f
palBrightTable4:
.byte $00,$01,$02,$03,$04,$05,$06,$07,$08,$09,$0a,$0b,$0c,$0f,$0f,$0f ;normal colors
palBrightTable5:
.byte $10,$11,$12,$13,$14,$15,$16,$17,$18,$19,$1a,$1b,$1c,$00,$00,$00
palBrightTable6:
.byte $10,$21,$22,$23,$24,$25,$26,$27,$28,$29,$2a,$2b,$2c,$10,$10,$10 ;$10 because $20 is the same as $30
palBrightTable7:
.byte $30,$31,$32,$33,$34,$35,$36,$37,$38,$39,$3a,$3b,$3c,$20,$20,$20
palBrightTable8:
.byte $30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30 ;white
.byte $30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30
.byte $30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30
.byte $30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30,$30
;; .include "famitone2.s"
; included in crt0.s
|
ninjadynamics/MMC3Template | 21,794 | music_journey.s | ;this file for FamiTone2 library generated by FamiStudio
_journey_to_silius_music_data:
.byte 1
.word @instruments
.word @samples-3
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256
@instruments:
.byte $70 ;instrument 00 (BackingLead)
.word @env13, @env0, @env0
.byte $00
.byte $30 ;instrument 01 (Lead0)
.word @env10, @env0, @env21
.byte $00
.byte $30 ;instrument 02 (Lead0Alt)
.word @env6, @env0, @env22
.byte $00
.byte $30 ;instrument 03 (Lead0End1)
.word @env1, @env0, @env0
.byte $00
.byte $30 ;instrument 04 (Lead0End2)
.word @env8, @env0, @env3
.byte $00
.byte $30 ;instrument 05 (Lead0Plain)
.word @env12, @env0, @env0
.byte $00
.byte $30 ;instrument 06 (Lead0Release)
.word @env19, @env0, @env21
.byte $00
.byte $30 ;instrument 07 (Lead0Sweep)
.word @env8, @env23, @env9
.byte $00
.byte $30 ;instrument 08 (Lead0SweepLow)
.word @env12, @env23, @env9
.byte $00
.byte $70 ;instrument 09 (Lead1)
.word @env10, @env0, @env21
.byte $00
.byte $70 ;instrument 0a (Lead1Alt)
.word @env2, @env0, @env22
.byte $00
.byte $70 ;instrument 0b (Lead1Release)
.word @env19, @env0, @env0
.byte $00
.byte $70 ;instrument 0c (Lead1TremoloAlt)
.word @env10, @env0, @env20
.byte $00
.byte $b0 ;instrument 0d (Lead2)
.word @env24, @env0, @env4
.byte $00
.byte $b0 ;instrument 0e (Lead2Plain)
.word @env12, @env0, @env0
.byte $00
.byte $b0 ;instrument 0f (Lead2Release)
.word @env7, @env0, @env15
.byte $00
.byte $30 ;instrument 10 (TomNoise1)
.word @env11, @env17, @env0
.byte $00
.byte $30 ;instrument 11 (TomNoise2)
.word @env14, @env18, @env0
.byte $00
.byte $30 ;instrument 12 (TomNoise3)
.word @env11, @env18, @env0
.byte $00
.byte $30 ;instrument 13 (TomTriangle)
.word @env5, @env16, @env0
.byte $00
.byte $30 ;instrument 14 (TomTrianglePlain)
.word @env5, @env0, @env0
.byte $00
@samples:
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;1
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;2
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;3
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;4
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;5
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;6
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;7
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;8
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;9
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;10
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;11
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;12
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;13
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;14
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;15
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;16
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;17
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;18
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;19
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;20
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;21
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;22
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;23
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;24
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0c ;25 (ripped00)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0a ;26 (ripped00)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0e ;27 (ripped00)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$09 ;28 (ripped00)
.byte $10+.lobyte(FT_DPCM_PTR),$3e,$0d ;29 (ripped01)
.byte $10+.lobyte(FT_DPCM_PTR),$3e,$08 ;30 (ripped01)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$0d ;31 (ripped02)
.byte $00+.lobyte(FT_DPCM_PTR),$3f,$0f ;32 (ripped00)
.byte $30+.lobyte(FT_DPCM_PTR),$3e,$0c ;33 (ripped03)
.byte $30+.lobyte(FT_DPCM_PTR),$3e,$0f ;34 (ripped03)
.byte $10+.lobyte(FT_DPCM_PTR),$3e,$0a ;35 (ripped01)
.byte $10+.lobyte(FT_DPCM_PTR),$3e,$0e ;36 (ripped01)
.byte $40+.lobyte(FT_DPCM_PTR),$3f,$0a ;37 (ripped04)
.byte $40+.lobyte(FT_DPCM_PTR),$3f,$0e ;38 (ripped04)
.byte $20+.lobyte(FT_DPCM_PTR),$3f,$0e ;39 (ripped02)
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;40
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;41
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;42
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;43
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;44
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;45
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;46
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;47
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;48
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;49
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;50
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;51
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;52
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;53
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;54
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;55
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;56
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;57
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;58
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;59
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;60
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;61
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;62
.byte $00+.lobyte(FT_DPCM_PTR),$00,$00 ;63
@env0:
.byte $c0,$7f,$00,$00
@env1:
.byte $c5,$c9,$c9,$c8,$00,$03
@env2:
.byte $ce,$cb,$ca,$c9,$00,$03
@env3:
.byte $c0,$bf,$bd,$bb,$bd,$c0,$c1,$c3,$c5,$c3,$c1,$00,$00
@env4:
.byte $c0,$07,$c1,$c3,$c6,$c3,$c1,$bf,$bd,$ba,$bd,$bf,$00,$02
@env5:
.byte $cf,$7d,$cf,$00,$02
@env6:
.byte $c4,$c6,$c9,$c8,$00,$03
@env7:
.byte $c1,$c5,$c4,$c3,$c2,$00,$04
@env8:
.byte $c8,$00,$00
@env9:
.byte $c0,$c2,$bd,$bf,$c1,$bd,$bf,$c1,$c3,$bd,$bf,$c1,$bd,$c1,$bd,$c1,$bc,$c0,$c4,$bf,$c3,$be,$c2,$bc,$c0,$c4,$bd,$c1,$bb,$c1,$bb,$c1,$ba,$c0,$c6,$bf,$c5,$bc,$c2,$ba,$00,$27
@env10:
.byte $c4,$c6,$c9,$c8,$0f,$c7,$0e,$c6,$0e,$c5,$00,$09
@env11:
.byte $cc,$cc,$c9,$c5,$c2,$c0,$00,$05
@env12:
.byte $c4,$00,$00
@env13:
.byte $c3,$00,$00
@env14:
.byte $cd,$ce,$cc,$c8,$c9,$c7,$c6,$c4,$c3,$c1,$c0,$00,$0a
@env15:
.byte $bf,$bd,$ba,$bd,$bf,$c1,$c3,$c6,$c3,$c1,$00,$00
@env16:
.byte $c0,$bf,$be,$bd,$bc,$bb,$ba,$b9,$b8,$b7,$00,$09
@env17:
.byte $c0,$c3,$00,$01
@env18:
.byte $c0,$c6,$00,$01
@env19:
.byte $c1,$c5,$c4,$c2,$00,$03
@env20:
.byte $c0,$08,$c0,$02,$bf,$bd,$ba,$bd,$bf,$00,$02
@env21:
.byte $c0,$07,$bf,$bd,$b9,$bd,$bf,$c1,$c3,$c7,$c3,$c1,$c0,$00,$02
@env22:
.byte $c0,$07,$c2,$c4,$c7,$c4,$c1,$bf,$bd,$bb,$bd,$bf,$00,$02
@env23:
.byte $c0,$c0,$bf,$02,$be,$03,$bd,$02,$bc,$bc,$bb,$bb,$ba,$02,$b9,$b9,$b8,$b8,$b7,$02,$b6,$b6,$b5,$b5,$b4,$b4,$b3,$02,$b2,$b2,$b1,$b1,$b0,$00,$20
@env24:
.byte $c5,$c6,$c6,$ca,$cb,$cc,$cb,$ca,$c9,$c8,$c7,$00,$0a
@song0ch0:
.byte $fb, $01
@ref0:
.byte $d1
@song0ch0loop:
@ref1:
.byte $a7,$80,$32,$91,$38,$91,$32,$91,$3c,$3f,$40,$9f,$3c,$91
@ref2:
.byte $92,$28,$af,$96,$28,$87,$92,$2c,$d7,$96,$2c,$87
.byte $ff,$0d
.word @ref1
@ref3:
.byte $92,$40,$af,$96,$40,$87,$92,$3c,$d7,$96,$3c,$87
.byte $ff,$0d
.word @ref1
.byte $ff,$08
.word @ref2
.byte $ff,$0d
.word @ref1
.byte $ff,$08
.word @ref3
@ref4:
.byte $a7,$82,$2e,$91,$8c,$2e,$91,$82,$2c,$87,$8c,$2c,$87,$82,$2e,$91,$8c,$2e,$91,$82,$2e,$91
@ref5:
.byte $93,$8c,$2e,$91,$82,$2c,$91,$8c,$2c,$91,$82,$2c,$91,$2e,$87,$8c,$2e,$af
.byte $ff,$0f
.word @ref4
.byte $ff,$0d
.word @ref5
.byte $ff,$0f
.word @ref4
.byte $ff,$0d
.word @ref5
@ref6:
.byte $a7,$82,$2e,$91,$8c,$2e,$91,$82,$2c,$87,$8c,$2c,$87,$82,$2e,$91,$8c,$2e,$91,$82,$28,$91
@ref7:
.byte $f9,$9b,$9a,$32,$87
@ref8:
.byte $89,$9e,$32,$87,$9a,$32,$87,$9e,$32,$87,$9a,$38,$87,$9e,$38,$87,$9a,$32,$87,$9e,$32,$87,$9a,$3c,$87,$9e,$3c,$87,$9a,$32,$9b,$9e,$32,$87,$9a,$40,$91
@ref9:
.byte $89,$9e,$40,$87,$9a,$32,$87,$9e,$32,$87,$9a,$3c,$87,$9e,$3c,$87,$9a,$32,$87,$9e,$32,$87,$9a,$38,$87,$9e,$38,$87,$9a,$32,$9b,$9e,$32,$87,$9a,$28,$91
@ref10:
.byte $89,$9e,$28,$87,$9a,$28,$87,$9e,$28,$87,$9a,$2e,$87,$9e,$2e,$87,$9a,$28,$87,$9e,$28,$87,$9a,$2e,$87,$9e,$2e,$87,$9a,$34,$37,$38,$8b,$36,$87,$9e,$36,$87,$9a,$32,$91
@ref11:
.byte $f9,$87,$9e,$32,$87,$9a,$32,$91
@ref12:
.byte $89,$9e,$32,$87,$9a,$32,$87,$9e,$32,$87,$9a,$38,$87,$9e,$38,$87,$9a,$32,$87,$9e,$32,$87,$9a,$3c,$87,$9e,$3c,$87,$9a,$32,$91,$9e,$32,$91,$9a,$3c,$3f,$40,$8b
@ref13:
.byte $93,$32,$87,$9e,$32,$87,$9a,$3c,$87,$9e,$3c,$87,$9a,$32,$87,$9e,$32,$87,$9a,$38,$87,$9e,$38,$87,$9a,$32,$91,$9e,$32,$91,$9a,$28,$91
@ref14:
.byte $89,$9e,$28,$87,$9a,$28,$87,$9e,$28,$87,$9a,$2e,$87,$9e,$2e,$87,$9a,$32,$87,$9e,$32,$87,$9a,$34,$37,$38,$8b,$36,$87,$9e,$36,$87,$9a,$2e,$87,$9e,$2e,$87,$9a,$32,$91
@ref15:
.byte $f9,$9b,$9e,$32,$87
@ref16:
.byte $9a,$3d,$3f,$40,$d9,$3c,$87,$9e,$3c,$87,$9a,$38,$87,$9e,$38,$87,$9a,$36,$91
@ref17:
.byte $c5,$9e,$36,$87,$9a,$38,$91,$9e,$38,$87,$9a,$3c,$91,$9e,$3c,$87,$9a,$3f,$40,$8d
@ref18:
.byte $f9,$91,$84,$3c,$3f,$40,$8b
@ref19:
.byte $93,$3c,$3f,$41,$8c,$40,$87,$84,$44,$91,$8c,$44,$91,$84,$46,$91,$44,$46,$85,$8c,$46,$af
.byte $ff,$0e
.word @ref16
@ref20:
.byte $c5,$9e,$36,$87,$9a,$38,$91,$9e,$38,$87,$9a,$3c,$91,$9e,$3c,$87,$9a,$32,$91
@ref21:
.byte $f9,$91,$94,$32,$87,$96,$32,$87
@ref22:
.byte $94,$32,$87,$96,$32,$87,$94,$32,$87,$96,$32,$87,$94,$32,$87,$96,$32,$eb
@ref23:
.byte $82,$32,$c3,$8c,$32,$87,$82,$32,$c3,$8c,$32,$87
@ref24:
.byte $82,$32,$af,$8c,$32,$87,$82,$32,$cd,$8c,$32,$91
.byte $ff,$08
.word @ref23
.byte $ff,$08
.word @ref24
.byte $ff,$08
.word @ref23
.byte $ff,$08
.word @ref24
@ref25:
.byte $82,$36,$c3,$8c,$36,$87,$82,$36,$c3,$8c,$36,$87
@ref26:
.byte $82,$36,$af,$8c,$36,$87,$82,$36,$cd,$8c,$36,$91
@ref27:
.byte $9d,$32,$87,$84,$32,$9b,$8c,$32,$87,$84,$32,$91,$8c,$32,$87,$84,$32,$91,$8c,$32,$87,$84,$32,$91
@ref28:
.byte $9d,$8c,$32,$87,$84,$32,$9b,$8c,$32,$87,$84,$32,$91,$8c,$32,$87,$84,$32,$91,$8c,$32,$87,$84,$32,$91
.byte $ff,$11
.word @ref28
@ref29:
.byte $b1,$8c,$32,$87,$84,$2e,$c3,$8c,$2e,$87,$84,$32,$91
.byte $ff,$11
.word @ref28
.byte $ff,$11
.word @ref28
@ref30:
.byte $9d,$8c,$32,$87,$84,$32,$9b,$8c,$32,$87,$84,$36,$91,$8c,$36,$87,$84,$40,$91,$8c,$40,$87,$84,$40,$91
@ref31:
.byte $f9,$9b,$8c,$40,$87
@ref32:
.byte $a7,$8a,$32,$91,$36,$91,$38,$91,$3c,$91,$32,$91,$36,$91
@ref33:
.byte $38,$91,$3c,$91,$32,$91,$36,$91,$38,$91,$3c,$91,$32,$91,$36,$91
.byte $ff,$10
.word @ref33
.byte $ff,$10
.word @ref33
.byte $ff,$10
.word @ref33
@ref34:
.byte $38,$91,$3c,$91,$36,$91,$38,$91,$3c,$91,$40,$a5,$40,$91
@ref35:
.byte $46,$91,$4a,$91,$4a,$91,$4e,$91,$50,$91,$54,$91,$4a,$91,$4e,$91
@ref36:
.byte $50,$91,$54,$91,$54,$91,$58,$91,$5a,$91,$5e,$91,$54,$91,$58,$91
@ref37:
.byte $5a,$91,$5e,$91,$62,$f5
@ref38:
.byte $f7,$90,$62,$a5
.byte $fd
.word @song0ch0loop
@song0ch1:
@ref39:
.byte $d1
@song0ch1loop:
@ref40:
.byte $92,$32,$87,$96,$32,$87,$92,$38,$87,$96,$38,$87,$92,$32,$87,$96,$32,$87,$92,$3c,$3f,$40,$9f,$3c,$87,$96,$3c,$87,$92,$38,$9b,$96,$38,$87
@ref41:
.byte $92,$2e,$af,$96,$2e,$87,$92,$32,$d7,$96,$32,$87
@ref42:
.byte $93,$92,$38,$87,$96,$38,$87,$92,$32,$87,$96,$32,$87,$92,$3c,$3f,$40,$9f,$3c,$87,$96,$3c,$87,$92,$38,$9b,$96,$38,$87
@ref43:
.byte $92,$46,$af,$96,$46,$87,$98,$44,$d7,$96,$44,$87
.byte $ff,$18
.word @ref40
.byte $ff,$08
.word @ref41
.byte $ff,$15
.word @ref42
.byte $ff,$08
.word @ref43
@ref44:
.byte $a7,$82,$38,$91,$8c,$38,$91,$82,$36,$87,$8c,$36,$87,$82,$38,$91,$8c,$38,$91,$82,$38,$91
@ref45:
.byte $93,$8c,$38,$91,$82,$36,$91,$8c,$36,$91,$82,$36,$91,$38,$87,$8c,$38,$af
.byte $ff,$0f
.word @ref44
.byte $ff,$0d
.word @ref45
.byte $ff,$0f
.word @ref44
.byte $ff,$0d
.word @ref45
@ref46:
.byte $a7,$82,$38,$91,$8c,$38,$91,$82,$36,$87,$8c,$36,$87,$82,$38,$91,$8c,$38,$91,$82,$36,$91
@ref47:
.byte $f9,$9b,$8c,$36,$87
@ref48:
.byte $93,$9c,$32,$a5,$32,$91,$38,$91,$32,$91,$3c,$91,$32,$91
@ref49:
.byte $93,$40,$a5,$32,$91,$3c,$91,$32,$91,$38,$91,$32,$91
@ref50:
.byte $93,$28,$a5,$28,$91,$2e,$91,$28,$91,$2e,$91,$34,$37,$38,$8b
@ref51:
.byte $36,$91,$32,$f9,$8f
@ref52:
.byte $93,$32,$a5,$32,$91,$38,$91,$32,$91,$3c,$91,$32,$91
@ref53:
.byte $93,$3c,$3f,$40,$9f,$32,$91,$3c,$91,$32,$91,$38,$91,$32,$91
@ref54:
.byte $93,$28,$a5,$28,$91,$2e,$91,$32,$91,$34,$37,$38,$8b,$36,$91
@ref55:
.byte $2e,$91,$32,$f9,$8f
@ref56:
.byte $a7,$3d,$3f,$40,$d9,$3c,$91
@ref57:
.byte $38,$91,$36,$e1,$38,$9b,$3c,$87
@ref58:
.byte $93,$3c,$3f,$40,$ef,$84,$36,$91
@ref59:
.byte $9d,$8c,$36,$87,$84,$3c,$91,$8c,$3c,$91,$84,$40,$9b,$8c,$40,$af
@ref60:
.byte $a7,$9c,$3d,$3f,$40,$d9,$3c,$91
.byte $ff,$08
.word @ref57
@ref61:
.byte $93,$32,$f9,$8f
@ref62:
.byte $93,$84,$28,$87,$8c,$28,$87,$84,$28,$87,$8c,$28,$87,$84,$28,$87,$8c,$28,$87,$84,$28,$87,$8c,$28,$c3
@ref63:
.byte $92,$40,$c3,$96,$40,$87,$92,$3c,$c3,$96,$3c,$87
@ref64:
.byte $92,$38,$af,$96,$38,$87,$92,$3c,$cd,$96,$3c,$91
.byte $ff,$08
.word @ref63
.byte $ff,$08
.word @ref64
.byte $ff,$08
.word @ref63
.byte $ff,$08
.word @ref64
@ref65:
.byte $92,$42,$c3,$96,$42,$87,$92,$40,$c3,$96,$40,$87
@ref66:
.byte $92,$3c,$af,$96,$3c,$87,$92,$40,$cd,$96,$40,$91
@ref67:
.byte $94,$40,$9b,$96,$40,$87,$94,$3c,$9b,$96,$3c,$87,$94,$38,$91,$96,$38,$87,$94,$3c,$91,$96,$3c,$87,$94,$40,$91
@ref68:
.byte $9d,$96,$40,$87,$94,$3c,$9b,$96,$3c,$87,$94,$38,$91,$96,$38,$87,$94,$3c,$91,$96,$3c,$87,$94,$40,$91
@ref69:
.byte $9d,$96,$40,$87,$94,$3c,$9b,$96,$3c,$87,$94,$38,$91,$96,$38,$87,$94,$3c,$91,$96,$3c,$87,$94,$38,$91
@ref70:
.byte $b1,$96,$38,$87,$94,$36,$c3,$96,$36,$87,$94,$40,$91
@ref71:
.byte $40,$9b,$96,$40,$87,$94,$3c,$9b,$96,$3c,$87,$94,$38,$91,$96,$38,$87,$94,$3c,$91,$96,$3c,$87,$94,$40,$91
.byte $ff,$11
.word @ref68
@ref72:
.byte $9d,$96,$40,$87,$94,$3c,$9b,$96,$3c,$87,$94,$40,$91,$96,$40,$87,$94,$46,$91,$96,$46,$87,$94,$4a,$91
@ref73:
.byte $f9,$9b,$96,$4a,$87
@ref74:
.byte $86,$32,$91,$36,$91,$38,$91,$3c,$91,$32,$91,$36,$91,$38,$91,$3c,$91
@ref75:
.byte $32,$91,$36,$91,$38,$91,$3c,$91,$32,$91,$36,$91,$38,$91,$3c,$91
.byte $ff,$10
.word @ref75
.byte $ff,$10
.word @ref75
.byte $ff,$10
.word @ref75
@ref76:
.byte $36,$91,$38,$91,$3c,$91,$40,$b9,$46,$91,$4a,$91
@ref77:
.byte $4a,$91,$4e,$91,$50,$91,$54,$91,$4a,$91,$4e,$91,$50,$91,$54,$91
@ref78:
.byte $54,$91,$58,$91,$5a,$91,$5e,$91,$54,$91,$58,$91,$5a,$91,$5e,$91
@ref79:
.byte $62,$cd,$88,$62,$cd
@ref80:
.byte $cf,$8e,$62,$cd
.byte $fd
.word @song0ch1loop
@song0ch2:
@ref81:
.byte $a6,$4d,$4c,$83,$4d,$4c,$83,$4c,$85,$00,$4c,$85,$00,$3c,$85,$00,$3c,$85,$00,$34,$8f,$00,$81
@song0ch2loop:
@ref82:
.byte $a6,$38,$83,$00,$8b,$38,$83,$00,$8b,$44,$8f,$00,$38,$83,$00,$8b,$38,$83,$00,$8b,$38,$83,$00,$8b,$44,$8f,$00,$38,$83,$00,$8b
@ref83:
.byte $38,$83,$00,$8b,$38,$83,$00,$8b,$44,$8f,$00,$38,$83,$00,$8b,$38,$83,$00,$8b,$38,$83,$00,$8b,$44,$8f,$00,$38,$83,$00,$8b
.byte $ff,$1e
.word @ref83
@ref84:
.byte $4a,$8f,$00,$4a,$8f,$00,$3c,$8f,$00,$34,$8f,$00,$4c,$85,$00,$4c,$85,$00,$89,$4c,$85,$00,$3c,$85,$00,$3c,$85,$00,$38,$8f,$00
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
@ref85:
.byte $4c,$85,$00,$4c,$85,$00,$3c,$85,$00,$34,$85,$00,$4c,$85,$00,$3c,$85,$00,$3c,$85,$00,$34,$85,$00,$4c,$85,$00,$4c,$85,$00,$4a,$85,$00,$4a,$85,$00,$3c,$85,$00,$3c,$85,$00,$34,$85,$00,$34,$85,$00
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1f
.word @ref84
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$30
.word @ref85
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1f
.word @ref84
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$30
.word @ref85
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1f
.word @ref84
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
@ref86:
.byte $38,$83,$00,$8b,$44,$8f,$00,$44,$8f,$00,$44,$8f,$00,$44,$8f,$00,$95,$a8,$44,$83,$00,$9d
@ref87:
.byte $a6,$38,$83,$00,$c7,$38,$83,$00,$c7
@ref88:
.byte $38,$83,$00,$b3,$38,$83,$00,$9f,$a8,$44,$83,$00,$8b,$a6,$38,$83,$00,$9f
@ref89:
.byte $38,$83,$00,$c7,$38,$83,$00,$c7
.byte $ff,$10
.word @ref88
.byte $ff,$08
.word @ref89
.byte $ff,$10
.word @ref88
.byte $ff,$08
.word @ref89
@ref90:
.byte $38,$83,$00,$b3,$38,$83,$00,$9f,$44,$8f,$00,$44,$8f,$00,$44,$8f,$00
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1f
.word @ref84
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$30
.word @ref85
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1f
.word @ref84
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$1e
.word @ref83
.byte $ff,$30
.word @ref85
.byte $ff,$1e
.word @ref83
@ref91:
.byte $4c,$85,$00,$4c,$85,$00,$3e,$85,$00,$34,$85,$00,$4c,$85,$00,$3c,$85,$00,$3c,$85,$00,$34,$85,$00,$4d,$4c,$83,$4c,$83,$4d,$4c,$85,$00,$4c,$85,$00,$3c,$85,$00,$3c,$85,$00,$34,$85,$00,$34,$85,$00
.byte $fd
.word @song0ch2loop
@song0ch3:
@ref92:
.byte $a2,$4c,$83,$4c,$85,$4c,$83,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$89
@song0ch3loop:
@ref93:
.byte $a0,$38,$91,$38,$91,$a2,$4c,$91,$a0,$38,$91,$38,$91,$38,$91,$a2,$4c,$91,$a0,$38,$91
@ref94:
.byte $38,$91,$38,$91,$a2,$4c,$91,$a0,$38,$91,$38,$91,$38,$91,$a2,$4c,$91,$a0,$38,$91
.byte $ff,$10
.word @ref94
@ref95:
.byte $a4,$4c,$91,$4c,$91,$4c,$91,$4c,$91,$4c,$87,$4c,$91,$4c,$87,$4c,$87,$4c,$87,$4c,$91
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
@ref96:
.byte $a4,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87,$4c,$87
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$14
.word @ref95
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$20
.word @ref96
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$14
.word @ref95
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$20
.word @ref96
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$14
.word @ref95
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
@ref97:
.byte $38,$91,$a2,$4c,$91,$4c,$91,$4c,$91,$4c,$a7,$4c,$a3
@ref98:
.byte $a0,$38,$cd,$38,$cd
@ref99:
.byte $38,$b9,$38,$a5,$a2,$4c,$91,$a0,$38,$a5
@ref100:
.byte $38,$cd,$38,$cd
.byte $ff,$08
.word @ref99
@ref101:
.byte $38,$cd,$38,$cd
.byte $ff,$08
.word @ref99
@ref102:
.byte $38,$cd,$38,$cd
@ref103:
.byte $38,$b9,$38,$a5,$a2,$4c,$91,$4c,$91,$4c,$91
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$14
.word @ref95
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$20
.word @ref96
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$14
.word @ref95
.byte $ff,$10
.word @ref93
.byte $ff,$10
.word @ref94
.byte $ff,$10
.word @ref94
.byte $ff,$20
.word @ref96
.byte $ff,$10
.word @ref93
.byte $ff,$20
.word @ref96
.byte $fd
.word @song0ch3loop
@song0ch4:
@ref104:
.byte $d1
@song0ch4loop:
@ref105:
.byte $32,$91,$32,$91,$32,$91,$32,$91,$32,$91,$32,$91,$32,$91,$32,$91
@ref106:
.byte $34,$91,$34,$91,$36,$91,$38,$91,$38,$91,$3a,$91,$38,$91,$3a,$91
.byte $ff,$10
.word @ref105
@ref107:
.byte $3c,$91,$3c,$91,$3e,$91,$38,$91,$38,$91,$3a,$91,$38,$91,$3a,$91
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref106
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref107
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref105
.byte $ff,$10
.word @ref105
@ref108:
.byte $32,$91,$32,$91,$32,$91,$32,$91,$32,$91,$32,$91,$32,$91,$34,$91
@ref109:
.byte $34,$91,$34,$91,$34,$91,$34,$91,$34,$91,$34,$91,$34,$91,$34,$91
@ref110:
.byte $32,$91,$32,$91,$32,$91,$40,$91,$32,$91,$40,$91,$32,$91,$32,$91
@ref111:
.byte $42,$91,$44,$91,$42,$91,$42,$91,$42,$91,$44,$91,$42,$91,$42,$91
@ref112:
.byte $34,$91,$34,$91,$34,$91,$36,$91,$42,$91,$44,$91,$42,$91,$42,$91
@ref113:
.byte $32,$91,$40,$91,$32,$91,$32,$91,$32,$91,$40,$91,$32,$91,$32,$91
.byte $ff,$10
.word @ref110
.byte $ff,$10
.word @ref111
.byte $ff,$10
.word @ref112
.byte $ff,$10
.word @ref113
@ref114:
.byte $38,$91,$38,$91,$3a,$91,$38,$91,$38,$91,$38,$91,$3a,$91,$38,$91
@ref115:
.byte $34,$91,$34,$91,$36,$91,$34,$91,$34,$91,$34,$91,$36,$91,$34,$91
@ref116:
.byte $32,$91,$32,$91,$40,$91,$32,$91,$40,$91,$32,$91,$32,$91,$40,$91
@ref117:
.byte $32,$91,$32,$91,$40,$91,$32,$91,$32,$91,$40,$91,$32,$91,$40,$91
.byte $ff,$10
.word @ref114
.byte $ff,$10
.word @ref115
.byte $ff,$10
.word @ref116
@ref118:
.byte $32,$91,$32,$91,$32,$91,$32,$91,$32,$cd
@ref119:
.byte $32,$cd,$32,$cd
@ref120:
.byte $32,$b9,$32,$a5,$32,$91,$40,$91,$32,$91
@ref121:
.byte $42,$cd,$42,$cd
@ref122:
.byte $42,$b9,$42,$a5,$42,$91,$44,$91,$42,$91
@ref123:
.byte $46,$cd,$46,$cd
@ref124:
.byte $46,$b9,$46,$a5,$46,$91,$44,$91,$46,$91
@ref125:
.byte $42,$cd,$42,$cd
@ref126:
.byte $42,$b9,$42,$a5,$44,$91,$42,$91,$44,$91
.byte $ff,$10
.word @ref117
@ref127:
.byte $42,$91,$42,$91,$44,$91,$42,$91,$42,$91,$44,$91,$42,$91,$44,$91
@ref128:
.byte $46,$91,$46,$91,$48,$91,$46,$91,$46,$91,$48,$91,$46,$91,$48,$91
.byte $ff,$10
.word @ref127
.byte $ff,$10
.word @ref117
.byte $ff,$10
.word @ref127
.byte $ff,$10
.word @ref128
.byte $ff,$10
.word @ref117
@ref129:
.byte $32,$91,$32,$91,$32,$91,$40,$91,$32,$91,$32,$91,$44,$91,$40,$91
@ref130:
.byte $42,$91,$42,$91,$42,$91,$44,$91,$42,$91,$42,$91,$48,$91,$44,$91
@ref131:
.byte $4a,$91,$4a,$91,$4a,$91,$4c,$91,$4a,$91,$4a,$91,$34,$91,$4c,$91
@ref132:
.byte $46,$91,$46,$91,$46,$91,$48,$91,$46,$91,$46,$91,$4e,$91,$48,$91
.byte $ff,$10
.word @ref129
.byte $ff,$10
.word @ref130
.byte $ff,$10
.word @ref131
.byte $ff,$10
.word @ref132
.byte $ff,$10
.word @ref129
.byte $ff,$10
.word @ref117
.byte $fd
.word @song0ch4loop
|
ninjadynamics/MMC3Template | 27,562 | music_rain.s | _rain_music_data:
.byte 1
.word @instruments
.word @samples-3
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256
@instruments:
.byte $30 ;instrument $00
.word @env1,@env15,@env0
.byte $00
.byte $70 ;instrument $01
.word @env2,@env0,@env16
.byte $00
.byte $70 ;instrument $02
.word @env3,@env13,@env0
.byte $00
.byte $70 ;instrument $03
.word @env3,@env14,@env0
.byte $00
.byte $30 ;instrument $04
.word @env4,@env0,@env0
.byte $00
.byte $70 ;instrument $05
.word @env5,@env13,@env0
.byte $00
.byte $70 ;instrument $06
.word @env5,@env14,@env0
.byte $00
.byte $30 ;instrument $07
.word @env6,@env0,@env0
.byte $00
.byte $30 ;instrument $08
.word @env7,@env0,@env0
.byte $00
.byte $b0 ;instrument $09
.word @env9,@env0,@env0
.byte $00
.byte $30 ;instrument $0a
.word @env5,@env0,@env0
.byte $00
.byte $70 ;instrument $0b
.word @env8,@env0,@env16
.byte $00
.byte $30 ;instrument $0c
.word @env1,@env0,@env0
.byte $00
.byte $b0 ;instrument $0d
.word @env2,@env0,@env16
.byte $00
.byte $b0 ;instrument $0e
.word @env8,@env0,@env0
.byte $00
.byte $30 ;instrument $0f
.word @env10,@env15,@env0
.byte $00
.byte $30 ;instrument $10
.word @env11,@env0,@env16
.byte $00
.byte $30 ;instrument $11
.word @env8,@env0,@env0
.byte $00
.byte $70 ;instrument $12
.word @env12,@env0,@env16
.byte $00
@samples:
.byte $00+<(FT_DPCM_PTR),$00,$00 ;1
.byte $00+<(FT_DPCM_PTR),$00,$00 ;2
.byte $00+<(FT_DPCM_PTR),$00,$00 ;3
.byte $00+<(FT_DPCM_PTR),$00,$00 ;4
.byte $00+<(FT_DPCM_PTR),$00,$00 ;5
.byte $00+<(FT_DPCM_PTR),$00,$00 ;6
.byte $00+<(FT_DPCM_PTR),$00,$00 ;7
.byte $00+<(FT_DPCM_PTR),$00,$00 ;8
.byte $00+<(FT_DPCM_PTR),$00,$00 ;9
.byte $00+<(FT_DPCM_PTR),$00,$00 ;10
.byte $00+<(FT_DPCM_PTR),$00,$00 ;11
.byte $00+<(FT_DPCM_PTR),$00,$00 ;12
.byte $00+<(FT_DPCM_PTR),$00,$00 ;13
.byte $00+<(FT_DPCM_PTR),$00,$00 ;14
.byte $00+<(FT_DPCM_PTR),$00,$00 ;15
.byte $00+<(FT_DPCM_PTR),$00,$00 ;16
.byte $00+<(FT_DPCM_PTR),$00,$00 ;17
.byte $00+<(FT_DPCM_PTR),$00,$00 ;18
.byte $00+<(FT_DPCM_PTR),$00,$00 ;19
.byte $00+<(FT_DPCM_PTR),$00,$00 ;20
.byte $00+<(FT_DPCM_PTR),$00,$00 ;21
.byte $00+<(FT_DPCM_PTR),$00,$00 ;22
.byte $00+<(FT_DPCM_PTR),$00,$00 ;23
.byte $00+<(FT_DPCM_PTR),$00,$00 ;24
.byte $00+<(FT_DPCM_PTR),$0c,$0f ;25
.byte $00+<(FT_DPCM_PTR),$00,$00 ;26
.byte $04+<(FT_DPCM_PTR),$1b,$0f ;27
.byte $00+<(FT_DPCM_PTR),$00,$00 ;28
.byte $0b+<(FT_DPCM_PTR),$22,$0f ;29
.byte $14+<(FT_DPCM_PTR),$0d,$0f ;30
.byte $00+<(FT_DPCM_PTR),$00,$00 ;31
.byte $18+<(FT_DPCM_PTR),$0a,$0f ;32
.byte $00+<(FT_DPCM_PTR),$00,$00 ;33
.byte $00+<(FT_DPCM_PTR),$00,$00 ;34
.byte $00+<(FT_DPCM_PTR),$00,$00 ;35
.byte $1b+<(FT_DPCM_PTR),$36,$0f ;36
.byte $00+<(FT_DPCM_PTR),$00,$00 ;37
.byte $00+<(FT_DPCM_PTR),$00,$00 ;38
.byte $00+<(FT_DPCM_PTR),$00,$00 ;39
.byte $00+<(FT_DPCM_PTR),$00,$00 ;40
.byte $00+<(FT_DPCM_PTR),$00,$00 ;41
.byte $00+<(FT_DPCM_PTR),$00,$00 ;42
.byte $00+<(FT_DPCM_PTR),$00,$00 ;43
.byte $00+<(FT_DPCM_PTR),$00,$00 ;44
.byte $00+<(FT_DPCM_PTR),$00,$00 ;45
.byte $00+<(FT_DPCM_PTR),$00,$00 ;46
.byte $00+<(FT_DPCM_PTR),$00,$00 ;47
.byte $00+<(FT_DPCM_PTR),$00,$00 ;48
.byte $00+<(FT_DPCM_PTR),$00,$00 ;49
.byte $00+<(FT_DPCM_PTR),$00,$00 ;50
.byte $00+<(FT_DPCM_PTR),$00,$00 ;51
.byte $00+<(FT_DPCM_PTR),$00,$00 ;52
.byte $00+<(FT_DPCM_PTR),$00,$00 ;53
.byte $00+<(FT_DPCM_PTR),$00,$00 ;54
.byte $00+<(FT_DPCM_PTR),$00,$00 ;55
.byte $00+<(FT_DPCM_PTR),$00,$00 ;56
.byte $00+<(FT_DPCM_PTR),$00,$00 ;57
.byte $00+<(FT_DPCM_PTR),$00,$00 ;58
.byte $00+<(FT_DPCM_PTR),$00,$00 ;59
.byte $00+<(FT_DPCM_PTR),$00,$00 ;60
.byte $00+<(FT_DPCM_PTR),$00,$00 ;61
.byte $00+<(FT_DPCM_PTR),$00,$00 ;62
.byte $00+<(FT_DPCM_PTR),$00,$00 ;63
@env0:
.byte $c0,$00,$00
@env1:
.byte $cf,$00,$00
@env2:
.byte $c5,$c6,$c7,$05,$c6,$0b,$c5,$0f,$c4,$11,$c3,$14,$c2,$15,$c1,$1d
.byte $c0,$00,$10
@env3:
.byte $c5,$c5,$c4,$c4,$c3,$c3,$c2,$c2,$c1,$c1,$c0,$00,$0a
@env4:
.byte $c8,$c4,$c3,$c2,$c2,$c1,$c1,$c0,$00,$07
@env5:
.byte $c3,$02,$c2,$02,$c1,$02,$c0,$00,$06
@env6:
.byte $ca,$c8,$c6,$c5,$c4,$c3,$c3,$c2,$c2,$c1,$03,$c0,$00,$0b
@env7:
.byte $c6,$c6,$c3,$03,$c2,$03,$c1,$c1,$c0,$00,$08
@env8:
.byte $c4,$03,$c3,$03,$c2,$30,$c1,$45,$c0,$00,$08
@env9:
.byte $c8,$c5,$c5,$c4,$c4,$c3,$00,$05
@env10:
.byte $cf,$cf,$c0,$00,$02
@env11:
.byte $c9,$06,$c8,$08,$c7,$08,$c6,$09,$c5,$0a,$c4,$0e,$c3,$11,$c2,$16
.byte $c1,$18,$c0,$00,$12
@env12:
.byte $c5,$03,$c4,$06,$c3,$09,$c2,$23,$c3,$0a,$c4,$11,$c3,$0d,$c2,$0a
.byte $c1,$0f,$c0,$00,$12
@env13:
.byte $c0,$c0,$c3,$c3,$c7,$c7,$00,$00
@env14:
.byte $c0,$c0,$c4,$c4,$c7,$c7,$00,$00
@env15:
.byte $cc,$c0,$00,$01
@env16:
.byte $c0,$0f,$c1,$c1,$c2,$c2,$c1,$c1,$c0,$c0,$00,$02
@song0ch0:
@song0ch0loop:
@ref0:
.byte $84,$41,$41,$41,$8a,$41,$84,$41,$8a,$41,$41,$84,$41,$41,$41,$41
.byte $8a,$41,$84,$41,$8a,$41,$84,$41,$40,$81
@ref1:
.byte $86,$47,$47,$47,$8c,$47,$86,$47,$8c,$47,$47,$86,$47,$47,$47,$47
.byte $8c,$47,$86,$47,$8c,$47,$86,$47,$46,$81
@ref2:
.byte $39,$39,$39,$8c,$39,$86,$39,$8c,$39,$39,$86,$39,$39,$39,$39,$8c
.byte $39,$86,$39,$8c,$39,$86,$39,$38,$81
@ref3:
.byte $3d,$3d,$3d,$8c,$3d,$86,$3d,$8c,$3d,$3d,$86,$3d,$3d,$3d,$3d,$8c
.byte $3d,$86,$3d,$8c,$3d,$3c,$85
.byte $ff,$11
.word @ref0
.byte $ff,$11
.word @ref1
.byte $ff,$11
.word @ref2
@ref7:
.byte $3d,$3d,$3d,$8c,$3d,$86,$3d,$8c,$3d,$86,$3d,$3d,$3d,$3d,$8c,$3d
.byte $3c,$91
@ref8:
.byte $87,$84,$41,$41,$8a,$40,$85,$84,$41,$8a,$41,$96,$24,$28,$83,$84
.byte $41,$41,$8a,$41,$96,$2f,$84,$41,$8a,$40,$81
@ref9:
.byte $96,$2c,$2e,$83,$86,$47,$47,$8c,$47,$96,$2f,$86,$47,$8c,$47,$96
.byte $2c,$85,$86,$47,$47,$8c,$46,$85,$96,$1e,$85
@ref10:
.byte $20,$85,$86,$39,$39,$8c,$39,$96,$21,$86,$39,$8c,$38,$89,$86,$39
.byte $39,$8c,$38,$85,$86,$39,$8c,$38,$81
@ref11:
.byte $96,$36,$85,$86,$3d,$3d,$8c,$3c,$85,$86,$3d,$8c,$3d,$96,$32,$85
.byte $86,$3d,$3d,$8c,$3c,$8d
.byte $ff,$11
.word @ref8
@ref13:
.byte $96,$2c,$2e,$83,$86,$47,$47,$8c,$47,$96,$2f,$86,$47,$8c,$47,$96
.byte $32,$85,$86,$47,$47,$8c,$46,$85,$96,$36,$85
@ref14:
.byte $38,$85,$86,$39,$39,$8c,$38,$85,$86,$39,$8c,$38,$89,$86,$39,$39
.byte $8c,$38,$85,$86,$39,$8c,$38,$81
@ref15:
.byte $96,$3c,$85,$86,$3d,$3d,$8c,$3c,$85,$86,$3d,$8c,$3c,$89,$86,$3d
.byte $3d,$8c,$3c,$85,$86,$3d,$8c,$3c,$81
@ref16:
.byte $96,$21,$86,$39,$39,$8c,$39,$86,$39,$8c,$39,$86,$39,$39,$9c,$3d
.byte $86,$39,$9c,$38,$85,$86,$39,$39,$9c,$36,$85
@ref17:
.byte $96,$33,$86,$3d,$3d,$9c,$25,$86,$3d,$8c,$3d,$86,$3d,$3d,$8c,$3d
.byte $86,$3d,$9c,$32,$85,$86,$3d,$3d,$9c,$2c,$85
@ref18:
.byte $83,$86,$2f,$2f,$9c,$37,$86,$2f,$9c,$37,$86,$2f,$2f,$9c,$37,$86
.byte $2f,$8c,$2e,$85,$86,$2f,$2f,$9c,$2c,$2e,$83
@ref19:
.byte $33,$84,$29,$29,$9c,$33,$84,$29,$8a,$29,$84,$29,$29,$9c,$2f,$84
.byte $29,$9c,$2e,$85,$84,$29,$29,$8a,$28,$85
@ref20:
.byte $83,$86,$39,$39,$8c,$39,$86,$39,$8c,$39,$86,$39,$38,$85,$39,$9c
.byte $2c,$85,$86,$39,$39,$9c,$32,$85
@ref21:
.byte $2c,$2e,$86,$3d,$3d,$9c,$2f,$86,$3d,$8c,$3d,$86,$3d,$3d,$9c,$2d
.byte $86,$3d,$9c,$2c,$85,$86,$3d,$3d,$8c,$3c,$85
@ref22:
.byte $83,$86,$2f,$2f,$9c,$3d,$86,$2f,$9c,$3d,$86,$2f,$2f,$8c,$2f,$86
.byte $2f,$8c,$2e,$85,$86,$2f,$2f,$9c,$46,$85
@ref23:
.byte $4b,$86,$2f,$2f,$9c,$4b,$86,$2f,$8c,$2f,$86,$2f,$2f,$9c,$46,$8d
.byte $96,$2c,$2e,$83,$32,$85
@ref24:
.byte $21,$86,$39,$39,$8c,$39,$86,$39,$8c,$39,$86,$39,$39,$9c,$3d,$86
.byte $39,$9c,$38,$85,$86,$39,$39,$9c,$36,$85
.byte $ff,$10
.word @ref17
.byte $ff,$11
.word @ref18
.byte $ff,$10
.word @ref19
@ref28:
.byte $83,$86,$39,$39,$9c,$21,$86,$39,$9c,$25,$86,$39,$39,$8c,$39,$86
.byte $39,$8c,$38,$85,$86,$39,$38,$9c,$26,$28,$85
@ref29:
.byte $2d,$86,$3d,$3d,$9c,$29,$86,$3d,$9c,$2d,$86,$3d,$3d,$8c,$3d,$86
.byte $3d,$8c,$3c,$85,$86,$3d,$3c,$9c,$2c,$2e,$85
@ref30:
.byte $33,$86,$2f,$2f,$9c,$2f,$86,$2f,$9c,$2f,$86,$2f,$2f,$9c,$2f,$86
.byte $2f,$8c,$2e,$85,$86,$2f,$2f,$8c,$2e,$85
@ref31:
.byte $83,$86,$2f,$2f,$8c,$2f,$86,$2f,$8c,$2f,$86,$2f,$2f,$8c,$2e,$9d
.byte $ff,$11
.word @ref0
.byte $ff,$11
.word @ref1
.byte $ff,$11
.word @ref2
.byte $ff,$10
.word @ref3
.byte $ff,$11
.word @ref0
.byte $ff,$11
.word @ref1
.byte $ff,$11
.word @ref2
.byte $ff,$0d
.word @ref7
@ref40:
.byte $8f,$9a,$36,$85,$3a,$3c,$8b,$3a,$85,$36,$85,$28,$85
@ref41:
.byte $9f,$44,$85,$46,$95
@ref42:
.byte $8f,$36,$85,$3a,$3c,$8b,$3a,$85,$28,$85,$2c,$85
@ref43:
.byte $8f,$2d,$2f,$2c,$a5
@ref44:
.byte $8f,$36,$85,$3a,$3c,$8b,$3a,$85,$32,$85,$36,$85
.byte $ff,$05
.word @ref41
@ref46:
.byte $8f,$4e,$85,$4a,$8d,$46,$85,$44,$85,$40,$44,$83
@ref47:
.byte $8f,$45,$47,$4a,$8d,$46,$85,$44,$8d
@ref48:
.byte $8f,$a0,$10,$14,$83,$16,$8d,$16,$85,$14,$85,$16,$85
@ref49:
.byte $9f,$14,$16,$83,$1a,$85,$1e,$8d
@ref50:
.byte $16,$a5,$10,$14,$83,$16,$85,$14,$85
@ref51:
.byte $87,$28,$2c,$83,$2e,$85,$2c,$8d,$82,$28,$2c,$83,$2e,$85,$2c,$85
@ref52:
.byte $8f,$a0,$28,$2c,$83,$2e,$8d,$2c,$85,$28,$85,$2e,$85
@ref53:
.byte $8f,$82,$2c,$2e,$83,$32,$85,$a0,$2c,$2e,$83,$32,$85,$36,$8d
@ref54:
.byte $38,$ad,$36,$38,$83,$3c,$85
@ref55:
.byte $87,$3a,$3c,$87,$3a,$3c,$83,$a2,$3d,$a0,$3c,$9d
.byte $ff,$10
.word @ref16
.byte $ff,$10
.word @ref17
.byte $ff,$11
.word @ref18
.byte $ff,$10
.word @ref19
.byte $ff,$10
.word @ref20
.byte $ff,$11
.word @ref21
.byte $ff,$10
.word @ref22
.byte $ff,$0f
.word @ref23
.byte $ff,$10
.word @ref24
.byte $ff,$10
.word @ref17
.byte $ff,$11
.word @ref18
.byte $ff,$10
.word @ref19
.byte $ff,$11
.word @ref28
.byte $ff,$11
.word @ref29
.byte $ff,$10
.word @ref30
.byte $ff,$0a
.word @ref31
.byte $fd
.word @song0ch0loop
@song0ch1:
@song0ch1loop:
@ref72:
.byte $92,$11,$11,$11,$94,$11,$92,$29,$11,$94,$29,$92,$0d,$11,$11,$11
.byte $94,$11,$92,$29,$2d,$94,$29,$92,$2e,$81
@ref73:
.byte $94,$2f,$92,$17,$17,$94,$17,$92,$2f,$17,$94,$2f,$92,$11,$17,$17
.byte $17,$94,$17,$92,$2f,$94,$2f,$92,$2c,$2e,$2c,$81
@ref74:
.byte $09,$09,$09,$94,$09,$92,$21,$09,$94,$21,$92,$07,$09,$09,$09,$94
.byte $09,$92,$21,$23,$94,$21,$92,$24,$81
@ref75:
.byte $94,$25,$92,$0d,$0d,$94,$0d,$92,$25,$0d,$94,$25,$92,$0b,$0d,$94
.byte $0b,$92,$25,$2d,$2f,$94,$2d,$92,$2c,$2e,$2c,$81
@ref76:
.byte $11,$11,$11,$94,$11,$92,$29,$11,$94,$29,$92,$0d,$11,$11,$11,$94
.byte $11,$92,$29,$2d,$94,$29,$92,$2e,$81
.byte $ff,$12
.word @ref73
.byte $ff,$11
.word @ref74
@ref79:
.byte $94,$25,$92,$0d,$0d,$94,$0d,$92,$22,$24,$0d,$2c,$2e,$2d,$24,$85
.byte $94,$24,$85,$92,$0d,$94,$0d,$92,$25,$24,$81
@ref80:
.byte $11,$94,$10,$91,$82,$24,$28,$83,$2c,$85,$2e,$85,$32,$85,$2c,$2e
.byte $83
@ref81:
.byte $97,$2c,$95,$1e,$85,$20,$85
@ref82:
.byte $af,$36,$38,$83,$36,$85
@ref83:
.byte $97,$32,$a5
@ref84:
.byte $97,$24,$28,$83,$2c,$85,$2e,$85,$32,$85,$2c,$2e,$83
@ref85:
.byte $97,$32,$95,$36,$85,$38,$85
@ref86:
.byte $af,$36,$38,$83,$3c,$85
@ref87:
.byte $bf
@ref88:
.byte $8f,$9a,$38,$9c,$39,$9a,$38,$3d,$38,$91,$36,$85,$32,$85
@ref89:
.byte $24,$95,$2d,$9c,$2d,$9a,$2e,$32,$83,$2e,$85,$2c,$8d
@ref90:
.byte $36,$a5,$33,$9c,$33,$9a,$2c,$2e,$83,$32,$85
@ref91:
.byte $97,$2e,$a5
@ref92:
.byte $97,$28,$9c,$29,$9a,$28,$2c,$85,$2e,$85,$32,$83,$2c,$2e,$85
@ref93:
.byte $97,$2c,$a5
@ref94:
.byte $3c,$a5,$3c,$85,$46,$85,$4a,$85
@ref95:
.byte $97,$46,$a5
@ref96:
.byte $8f,$38,$9c,$39,$9a,$38,$3d,$38,$91,$36,$85,$32,$85
.byte $ff,$0b
.word @ref89
.byte $ff,$09
.word @ref90
@ref99:
.byte $97,$2e,$a5
@ref100:
.byte $1e,$20,$87,$24,$89,$29,$9c,$29,$9a,$24,$8b,$26,$28,$85,$2c,$85
@ref101:
.byte $28,$89,$2c,$89,$2f,$9c,$2f,$9a,$2c,$8b,$2c,$2e,$85,$32,$85
@ref102:
.byte $2e,$bd
@ref103:
.byte $a4,$14,$16,$bb
.byte $ff,$11
.word @ref72
.byte $ff,$12
.word @ref73
.byte $ff,$11
.word @ref74
.byte $ff,$12
.word @ref75
.byte $ff,$11
.word @ref76
.byte $ff,$12
.word @ref73
.byte $ff,$11
.word @ref74
.byte $ff,$13
.word @ref79
@ref112:
.byte $11,$94,$11,$84,$29,$29,$8a,$28,$85,$84,$29,$8a,$29,$9c,$3a,$3c
.byte $83,$84,$29,$29,$8a,$29,$9c,$3b,$92,$29,$94,$28,$81
@ref113:
.byte $92,$11,$94,$11,$84,$29,$29,$8a,$28,$85,$84,$29,$8a,$28,$89,$92
.byte $11,$94,$11,$92,$29,$94,$29,$92,$2f,$94,$2e,$81
@ref114:
.byte $92,$17,$94,$17,$86,$2f,$2f,$8c,$2e,$85,$86,$2f,$8c,$2f,$9c,$3a
.byte $3c,$83,$86,$2f,$2f,$8c,$2f,$9c,$3b,$92,$2f,$94,$2e,$81
@ref115:
.byte $92,$0d,$94,$0d,$86,$25,$25,$8c,$24,$85,$86,$25,$8c,$25,$9c,$2c
.byte $85,$92,$0d,$94,$0d,$92,$25,$94,$25,$92,$2b,$94,$2a,$81
@ref116:
.byte $92,$11,$94,$11,$84,$29,$29,$8a,$28,$85,$84,$29,$8a,$29,$9c,$3a
.byte $3c,$83,$84,$29,$29,$8a,$29,$9c,$3b,$92,$29,$94,$28,$81
.byte $ff,$10
.word @ref113
@ref118:
.byte $92,$09,$94,$09,$86,$21,$21,$8c,$20,$85,$86,$21,$8c,$21,$9c,$4a
.byte $85,$86,$21,$21,$8c,$21,$9c,$47,$92,$21,$94,$20,$81
@ref119:
.byte $92,$0d,$94,$0d,$86,$25,$25,$8c,$24,$85,$86,$25,$8c,$25,$9c,$4a
.byte $85,$92,$0d,$94,$0d,$92,$25,$94,$25,$92,$2b,$94,$2a,$81
@ref120:
.byte $83,$84,$29,$29,$8a,$29,$84,$29,$8a,$29,$84,$29,$29,$a2,$17,$84
.byte $29,$8a,$28,$85,$84,$29,$29,$a2,$14,$85
@ref121:
.byte $17,$86,$2f,$2f,$a2,$17,$86,$2f,$8c,$2f,$86,$2f,$2f,$8c,$2e,$85
.byte $86,$2f,$2f,$a2,$1a,$85,$1e,$85
@ref122:
.byte $83,$86,$21,$21,$a2,$17,$86,$21,$a2,$17,$86,$21,$21,$8c,$21,$86
.byte $21,$8c,$20,$85,$86,$21,$21,$a2,$16,$85
@ref123:
.byte $15,$86,$25,$25,$8c,$25,$86,$25,$a2,$15,$86,$25,$25,$a2,$14,$85
.byte $86,$25,$25,$96,$28,$2c,$83,$2e,$85
@ref124:
.byte $2d,$84,$29,$29,$8a,$29,$84,$29,$8a,$29,$84,$29,$29,$a2,$2f,$84
.byte $29,$8a,$28,$85,$84,$29,$29,$a2,$28,$85
@ref125:
.byte $2f,$86,$2f,$2f,$8c,$2f,$86,$2f,$8c,$2f,$86,$2f,$2f,$96,$32,$85
.byte $86,$2f,$2f,$a2,$32,$85,$36,$85
@ref126:
.byte $83,$86,$21,$21,$a2,$39,$86,$21,$a2,$39,$86,$21,$21,$8c,$21,$86
.byte $21,$8c,$20,$85,$86,$21,$21,$a2,$36,$38,$83
@ref127:
.byte $3d,$86,$25,$25,$8c,$25,$86,$25,$a2,$3d,$86,$25,$25,$8c,$24,$85
.byte $a2,$3c,$95
.byte $ff,$0b
.word @ref88
.byte $ff,$0b
.word @ref89
.byte $ff,$09
.word @ref90
@ref131:
.byte $97,$2e,$a5
.byte $ff,$0d
.word @ref92
@ref133:
.byte $97,$2c,$a5
.byte $ff,$08
.word @ref94
@ref135:
.byte $97,$46,$a5
.byte $ff,$0b
.word @ref96
.byte $ff,$0b
.word @ref89
.byte $ff,$09
.word @ref90
@ref139:
.byte $97,$2e,$a5
.byte $ff,$0e
.word @ref100
.byte $ff,$0d
.word @ref101
@ref142:
.byte $2e,$bd
@ref143:
.byte $a4,$14,$16,$bb
.byte $fd
.word @song0ch1loop
@song0ch2:
@song0ch2loop:
@ref144:
.byte $80,$28,$00,$28,$00,$29,$01,$41,$29,$01,$24,$00,$28,$00,$28,$00
.byte $29,$01,$41,$98,$44,$85,$46,$81
@ref145:
.byte $80,$2e,$00,$2e,$00,$2f,$01,$47,$2f,$01,$28,$00,$2e,$00,$2e,$00
.byte $2e,$00,$83,$98,$46,$85,$44,$46,$44,$81
@ref146:
.byte $80,$20,$00,$20,$00,$21,$01,$39,$21,$01,$1e,$00,$20,$00,$20,$00
.byte $21,$01,$98,$39,$3a,$85,$3c,$81
@ref147:
.byte $80,$24,$00,$24,$00,$25,$01,$3d,$25,$01,$22,$00,$25,$01,$98,$3d
.byte $45,$46,$85,$44,$46,$44,$81
.byte $ff,$16
.word @ref144
.byte $ff,$18
.word @ref145
@ref150:
.byte $80,$20,$00,$20,$00,$21,$01,$39,$21,$01,$1e,$00,$20,$00,$20,$00
.byte $21,$01,$39,$98,$3a,$85,$3c,$81
@ref151:
.byte $80,$24,$00,$24,$00,$25,$01,$98,$3a,$3c,$83,$44,$46,$45,$3c,$89
.byte $3a,$36,$80,$25,$01,$3c,$00,$3c,$00
@ref152:
.byte $28,$00,$28,$00,$29,$01,$41,$00,$85,$24,$00,$28,$00,$28,$00,$29
.byte $01,$41,$41,$29,$00,$81
@ref153:
.byte $2e,$00,$2e,$00,$2f,$01,$47,$00,$85,$28,$00,$2e,$00,$2e,$00,$2e
.byte $00,$83,$47,$01,$46,$00,$46,$00
@ref154:
.byte $20,$00,$20,$00,$21,$01,$39,$00,$85,$20,$00,$20,$00,$20,$00,$21
.byte $01,$39,$39,$21,$00,$81
@ref155:
.byte $24,$00,$24,$00,$25,$01,$3d,$00,$85,$22,$00,$24,$00,$24,$00,$24
.byte $00,$83,$3c,$83,$00,$25,$3c,$81
.byte $ff,$16
.word @ref152
.byte $ff,$18
.word @ref153
.byte $ff,$16
.word @ref154
@ref159:
.byte $24,$00,$24,$00,$25,$01,$3d,$00,$85,$23,$24,$85,$3d,$3d,$24,$85
.byte $37,$36,$81
@ref160:
.byte $20,$83,$00,$20,$00,$20,$83,$00,$20,$00,$39,$01,$20,$83,$00,$20
.byte $00,$20,$83,$00,$21,$3a,$85
@ref161:
.byte $24,$83,$00,$24,$00,$24,$83,$00,$24,$00,$3d,$01,$24,$83,$00,$24
.byte $00,$24,$83,$00,$24,$00,$44,$85
@ref162:
.byte $2e,$83,$00,$2e,$00,$2e,$83,$00,$2e,$00,$47,$01,$2e,$83,$00,$2e
.byte $00,$2e,$83,$00,$2f,$2c,$85
@ref163:
.byte $28,$83,$00,$28,$00,$28,$83,$00,$28,$00,$41,$01,$28,$83,$00,$28
.byte $00,$28,$83,$00,$41,$3c,$85
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
@ref167:
.byte $2e,$83,$00,$2e,$00,$2e,$83,$00,$2e,$00,$47,$01,$2e,$85,$00,$85
.byte $44,$98,$46,$83,$80,$4a,$85
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
.byte $ff,$17
.word @ref163
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
@ref175:
.byte $2e,$83,$00,$2e,$00,$2e,$83,$00,$2e,$00,$47,$01,$2e,$85,$00,$95
@ref176:
.byte $28,$00,$28,$00,$29,$01,$41,$29,$01,$24,$00,$28,$00,$28,$00,$29
.byte $01,$41,$98,$44,$85,$46,$81
.byte $ff,$18
.word @ref145
.byte $ff,$16
.word @ref146
.byte $ff,$15
.word @ref147
.byte $ff,$16
.word @ref144
.byte $ff,$18
.word @ref145
.byte $ff,$16
.word @ref150
.byte $ff,$16
.word @ref151
@ref184:
.byte $28,$00,$29,$9e,$41,$40,$89,$40,$8d,$41,$40,$89,$80,$41,$00,$81
@ref185:
.byte $28,$00,$29,$9e,$41,$40,$89,$40,$8d,$80,$28,$00,$9e,$29,$80,$40
.byte $00,$9e,$41,$80,$46,$00,$9e,$46,$81
@ref186:
.byte $80,$2e,$00,$2f,$9e,$47,$46,$89,$46,$8d,$47,$46,$89,$80,$47,$00
.byte $81
@ref187:
.byte $24,$00,$25,$9e,$3d,$3c,$89,$3c,$8d,$80,$24,$00,$9e,$25,$80,$3c
.byte $00,$9e,$3d,$80,$42,$00,$9e,$42,$81
@ref188:
.byte $80,$28,$00,$29,$9e,$41,$40,$89,$40,$8d,$41,$40,$89,$80,$41,$00
.byte $81
.byte $ff,$12
.word @ref185
@ref190:
.byte $80,$20,$00,$21,$9e,$39,$38,$89,$38,$8d,$39,$38,$89,$80,$39,$00
.byte $81
@ref191:
.byte $24,$00,$25,$9e,$3d,$3c,$89,$3c,$8d,$80,$24,$00,$24,$89,$00,$85
.byte $ff,$16
.word @ref152
.byte $ff,$18
.word @ref153
.byte $ff,$16
.word @ref154
.byte $ff,$18
.word @ref155
.byte $ff,$16
.word @ref152
.byte $ff,$18
.word @ref153
.byte $ff,$16
.word @ref154
.byte $ff,$13
.word @ref159
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
.byte $ff,$17
.word @ref163
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
.byte $ff,$15
.word @ref167
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
.byte $ff,$17
.word @ref163
.byte $ff,$17
.word @ref160
.byte $ff,$18
.word @ref161
.byte $ff,$17
.word @ref162
.byte $ff,$10
.word @ref175
.byte $fd
.word @song0ch2loop
@song0ch3:
.byte $fb,$06
@song0ch3loop:
@ref216:
.byte $fb,$05,$88,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$90,$1f,$fb,$05
.byte $8e,$1f,$fb,$03,$88,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05
.byte $1f,$fb,$03,$1f,$fb,$05,$8e,$1f,$fb,$03,$90,$1f,$fb,$05,$8e,$1f
.byte $fb,$03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$1e,$81
@ref217:
.byte $fb,$05,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$90,$1f,$fb,$05,$8e
.byte $1f,$fb,$03,$88,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f
.byte $fb,$03,$1f,$fb,$05,$8e,$1f,$fb,$03,$90,$1f,$fb,$05,$8e,$1f,$fb
.byte $03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$1e,$81
.byte $ff,$11
.word @ref217
@ref219:
.byte $fb,$05,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$90,$1f,$fb,$05,$8e
.byte $1f,$fb,$03,$88,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f
.byte $fb,$03,$1f,$fb,$05,$8e,$1f,$fb,$03,$83,$fb,$05,$1f,$fb,$03,$83
.byte $fb,$05,$1f,$fb,$03,$83
.byte $ff,$11
.word @ref216
.byte $ff,$11
.word @ref217
.byte $ff,$11
.word @ref217
.byte $ff,$10
.word @ref219
@ref224:
.byte $fb,$05,$88,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb
.byte $05,$90,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb,$05
.byte $83,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$83,$fb,$05,$90,$1f,$fb
.byte $03,$83,$fb,$05,$8e,$1f,$fb,$03,$83
@ref225:
.byte $fb,$05,$88,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb
.byte $05,$90,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb,$05
.byte $83,$fb,$03,$1f,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb,$05,$90,$1f
.byte $fb,$03,$88,$1f,$fb,$05,$8e,$1f,$fb,$03,$88,$1e,$81
@ref226:
.byte $fb,$05,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb,$05
.byte $90,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb,$05,$83
.byte $fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$83,$fb,$05,$90,$1f,$fb,$03
.byte $83,$fb,$05,$8e,$1f,$fb,$03,$83
.byte $ff,$11
.word @ref225
.byte $ff,$10
.word @ref226
.byte $ff,$11
.word @ref225
.byte $ff,$10
.word @ref226
@ref231:
.byte $fb,$05,$88,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb
.byte $05,$90,$1f,$fb,$03,$83,$fb,$05,$8e,$1f,$fb,$03,$88,$1f,$fb,$05
.byte $8e,$1f,$fb,$03,$83,$fb,$05,$88,$1f,$fb,$03,$83,$fb,$05,$1f,$fb
.byte $03,$83,$fb,$05,$1f,$fb,$03,$83
@ref232:
.byte $fb,$05,$8e,$1d,$fb,$03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$90,$1f
.byte $fb,$05,$88,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$8e,$1f,$fb,$05
.byte $88,$1f,$fb,$03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$90,$1f,$fb,$05
.byte $88,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$8e,$1e,$81
@ref233:
.byte $fb,$05,$1d,$fb,$03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$90,$1f,$fb
.byte $05,$88,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$8e,$1f,$fb,$05,$88
.byte $1f,$fb,$03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$90,$1f,$fb,$05,$88
.byte $1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$8e,$1e,$81
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
@ref239:
.byte $fb,$05,$1d,$fb,$03,$90,$1f,$fb,$05,$88,$1f,$fb,$03,$90,$1f,$fb
.byte $05,$88,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$8e,$1f,$fb,$05,$90
.byte $1f,$fb,$03,$83,$fb,$05,$1f,$fb,$03,$83,$fb,$05,$1b,$fb,$03,$83
.byte $fb,$05,$83,$fb,$03,$83
.byte $ff,$11
.word @ref232
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$10
.word @ref239
.byte $ff,$11
.word @ref216
.byte $ff,$11
.word @ref217
.byte $ff,$11
.word @ref217
.byte $ff,$10
.word @ref219
.byte $ff,$11
.word @ref216
.byte $ff,$11
.word @ref217
.byte $ff,$11
.word @ref217
.byte $ff,$10
.word @ref219
@ref256:
.byte $fb,$05,$90,$1f,$fb,$03,$83,$fb,$05,$83,$fb,$03,$83,$fb,$05,$1f
.byte $fb,$03,$83,$fb,$05,$83,$fb,$03,$83,$fb,$05,$1f,$fb,$03,$83,$fb
.byte $05,$83,$fb,$03,$83,$fb,$05,$1f,$fb,$03,$83,$fb,$05,$83,$fb,$03
.byte $88,$1e,$81
@ref257:
.byte $fb,$05,$90,$1f,$fb,$03,$83,$fb,$05,$83,$fb,$03,$83,$fb,$05,$1f
.byte $fb,$03,$83,$fb,$05,$83,$fb,$03,$83,$fb,$05,$1f,$fb,$03,$83,$fb
.byte $05,$88,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb,$03,$1f,$fb,$05,$1f,$fb
.byte $03,$1e,$81
.byte $ff,$11
.word @ref256
.byte $ff,$11
.word @ref257
.byte $ff,$11
.word @ref256
.byte $ff,$11
.word @ref257
.byte $ff,$11
.word @ref256
.byte $ff,$11
.word @ref257
@ref264:
.byte $fb,$05,$1f,$fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05
.byte $1f,$fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f,$fb
.byte $03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f,$fb,$03,$1f
.byte $fb,$05,$90,$1f,$fb,$03,$8e,$1e,$81
@ref265:
.byte $fb,$05,$88,$1f,$fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb
.byte $05,$1f,$fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f
.byte $fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f,$fb,$03
.byte $1f,$fb,$05,$90,$1f,$fb,$03,$8e,$1e,$81
.byte $ff,$11
.word @ref265
.byte $ff,$11
.word @ref265
.byte $ff,$11
.word @ref265
.byte $ff,$11
.word @ref265
.byte $ff,$11
.word @ref265
@ref271:
.byte $fb,$05,$88,$1f,$fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb
.byte $05,$1f,$fb,$03,$1f,$fb,$05,$90,$1f,$fb,$03,$88,$1f,$fb,$05,$1f
.byte $fb,$03,$83,$fb,$05,$83,$fb,$03,$83,$fb,$05,$1f,$fb,$03,$1f,$fb
.byte $05,$90,$1f,$fb,$03,$8e,$1e,$81
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$10
.word @ref239
.byte $ff,$11
.word @ref232
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$11
.word @ref233
.byte $ff,$10
.word @ref239
.byte $fd
.word @song0ch3loop
@song0ch4:
@song0ch4loop:
@ref288:
.byte $32,$85,$32,$85,$3b,$32,$85,$33,$33,$33,$32,$85,$3b,$33,$36,$85
@ref289:
.byte $32,$85,$32,$85,$3b,$32,$85,$33,$33,$33,$32,$85,$3a,$83,$36,$37
.byte $36,$81
@ref290:
.byte $32,$85,$32,$85,$3b,$32,$85,$33,$33,$33,$32,$85,$3b,$33,$36,$83
.byte $36
@ref291:
.byte $32,$85,$32,$85,$3b,$32,$85,$3b,$32,$83,$36,$3b,$3b,$3a,$83,$36
.byte $3b,$3a,$81
.byte $ff,$10
.word @ref288
.byte $ff,$12
.word @ref289
@ref294:
.byte $32,$85,$32,$85,$3b,$32,$85,$33,$33,$33,$32,$85,$3b,$32,$85,$3a
.byte $81
@ref295:
.byte $32,$85,$32,$85,$3b,$32,$85,$33,$3a,$93,$36,$37,$36,$81
@ref296:
.byte $32,$8d,$36,$89,$32,$89,$32,$85,$37,$32,$89
@ref297:
.byte $32,$85,$32,$85,$36,$89,$32,$89,$32,$85,$36,$85,$33,$32,$81
@ref298:
.byte $32,$8d,$36,$89,$32,$89,$32,$85,$37,$32,$85,$36,$81
@ref299:
.byte $32,$85,$32,$85,$36,$85,$37,$32,$89,$32,$85,$36,$85,$37,$36,$81
.byte $ff,$0b
.word @ref296
.byte $ff,$0f
.word @ref297
.byte $ff,$0d
.word @ref298
@ref303:
.byte $32,$85,$32,$85,$37,$32,$85,$37,$32,$8b,$36,$3a,$85,$3a,$85
@ref304:
.byte $32,$89,$33,$36,$89,$32,$89,$32,$85,$3b,$32,$89
@ref305:
.byte $32,$89,$33,$36,$89,$32,$85,$37,$32,$85,$3a,$85,$33,$32,$81
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
@ref311:
.byte $32,$89,$33,$36,$89,$32,$85,$37,$32,$83,$3a,$3a,$85,$3a,$85
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
@ref319:
.byte $32,$89,$33,$36,$89,$32,$85,$37,$32,$85,$3a,$8d
.byte $ff,$10
.word @ref288
.byte $ff,$12
.word @ref289
.byte $ff,$11
.word @ref290
.byte $ff,$13
.word @ref291
.byte $ff,$10
.word @ref288
.byte $ff,$12
.word @ref289
.byte $ff,$11
.word @ref294
.byte $ff,$0e
.word @ref295
@ref328:
.byte $32,$8d,$3c,$89,$40,$89,$40,$85,$3c,$89,$40,$81
@ref329:
.byte $32,$85,$40,$85,$3d,$40,$85,$40,$89,$32,$85,$3d,$32,$89
.byte $ff,$0c
.word @ref328
@ref331:
.byte $32,$85,$40,$85,$3d,$40,$85,$40,$85,$3d,$40,$85,$3c,$85,$3d,$3c
.byte $81
.byte $ff,$0c
.word @ref328
.byte $ff,$11
.word @ref331
.byte $ff,$0c
.word @ref328
@ref335:
.byte $32,$85,$40,$85,$3d,$40,$85,$32,$8f,$36,$37,$37,$37,$36,$81
@ref336:
.byte $32,$89,$33,$37,$32,$85,$36,$89,$32,$85,$3b,$32,$85,$32,$81
@ref337:
.byte $32,$89,$33,$37,$32,$85,$37,$32,$85,$32,$85,$3b,$33,$32,$85
.byte $ff,$0f
.word @ref336
@ref339:
.byte $32,$89,$33,$37,$32,$85,$37,$32,$85,$32,$85,$3b,$33,$3b,$3a,$81
.byte $ff,$0f
.word @ref336
.byte $ff,$0f
.word @ref337
.byte $ff,$0f
.word @ref336
@ref343:
.byte $32,$89,$33,$3b,$33,$3b,$3b,$3a,$8d,$36,$83,$36,$37,$36,$81
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref311
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0f
.word @ref305
.byte $ff,$0c
.word @ref304
.byte $ff,$0c
.word @ref319
.byte $fd
.word @song0ch4loop
|
ninjadynamics/MMC3Template | 10,357 | music_themoon.s | ;this file for FamiTone2 library generated by text2data tool
_the_moon_music_data:
.byte 1
.word @instruments
.word @samples-3
.word @song0ch0,@song0ch1,@song0ch2,@song0ch3,@song0ch4,307,256
@instruments:
.byte $30 ; 00 : Bass
.word @env0, @env4, @env4
.byte $00
.byte $f0 ; 01 : Bleep
.word @env3, @env4, @env4
.byte $00
.byte $70 ; 02 : BleepIntro
.word @env9, @env4, @env4
.byte $00
.byte $30 ; 03 : DrumHi
.word @env10, @env4, @env4
.byte $00
.byte $30 ; 04 : DrumIntro
.word @env8, @env4, @env4
.byte $00
.byte $30 ; 05 : DrumLo
.word @env7, @env4, @env4
.byte $00
.byte $30 ; 06 : DrumMed
.word @env1, @env4, @env4
.byte $00
.byte $30 ; 07 : Lead
.word @env2, @env4, @env4
.byte $00
.byte $f0 ; 08 : LeadIntro
.word @env6, @env4, @env4
.byte $00
.byte $30 ; 09 : LeadLo
.word @env5, @env4, @env4
.byte $00
@env0:
.byte $cf,$7f,$00,$00
@env1:
.byte $ca,$02,$c6,$03,$c2,$00,$04
@env2:
.byte $ca,$7f,$00,$00
@env3:
.byte $c7,$02,$c5,$03,$c1,$00,$04
@env4:
.byte $c0,$7f,$00,$01
@env5:
.byte $c7,$7f,$00,$00
@env6:
.byte $c1,$c2,$c3,$c4,$c5,$c6,$c7,$c8,$c9,$ca,$00,$09
@env7:
.byte $ca,$02,$c2,$00,$02
@env8:
.byte $ca,$02,$c5,$00,$02
@env9:
.byte $c7,$06,$c1,$00,$02
@env10:
.byte $ca,$c4,$00,$01
@samples:
@song0ch0:
.byte $fb, $01, $f9, $f9, $b7, $90, $4c, $f9, $b5, $00, $56, $a3, $00, $5a, $a3, $00, $60, $a3, $00, $60, $b7, $00, $5e, $8f
.byte $00, $5e, $f9, $8d, $00, $5a, $a3, $00, $56, $a3, $00, $64, $f3, $00, $56, $f3, $00, $6e, $b9, $f9, $f3, $00, $72, $a3
.byte $00, $6e, $8f, $00, $7c, $f9, $f9, $c7, $00
@song0ch0loop:
.byte $cf, $8e, $46, $8f, $00, $48, $8f, $00, $4c, $8f, $00, $4c, $b7, $00, $56, $a3, $00, $54, $a3, $00, $56, $a3, $00, $5a
.byte $a3, $00, $5e, $8f, $00, $56, $f9, $dd, $00, $54, $8f, $00, $56, $8f, $00, $64, $b7, $00, $56, $8f, $00, $56, $f9, $dd
.byte $00, $56, $8f, $00, $56, $cb, $00, $93, $5a, $8f, $00, $56, $8f, $00, $54, $f9, $b5, $00, $46, $cb, $00, $93, $42, $8f
.byte $00, $3e, $8f, $00, $4c, $cb, $00, $93, $56, $a3, $00, $5a, $a3, $00, $60, $b7, $00, $5e, $8f, $00, $5e, $f9, $a1, $00
.byte $64, $a3, $00, $60, $a3, $00, $5e, $8f, $00, $60, $8f, $00, $5e, $8f, $00, $56, $a3, $00, $4c, $cb, $00, $5a, $8f, $00
.byte $56, $8f, $00, $54, $8f, $00, $50, $8f, $00, $54, $b7, $00, $56, $8f, $00, $a7, $56, $8f, $00, $a7, $56, $a3, $00, $8d
.byte $2e, $f9, $93, $00
@song0ref207:
.byte $56, $8f, $00, $56, $8f, $00, $a7, $5a, $8f, $00, $5a, $8f, $00, $93, $52, $cb, $00, $4c, $a3, $00, $52, $8f, $00, $48
.byte $83, $4a, $83, $00, $49, $00, $44, $8f, $00, $48, $a3, $00, $44, $8f, $00, $48, $8f, $00, $93, $44, $8f, $00, $93, $4c
.byte $f9, $a1, $00, $93
.byte $ff, $0e
.word @song0ref207
.byte $5c, $a3, $00, $52, $a3, $00, $52, $a3, $00, $52, $8f, $00, $5c, $8f, $00, $60, $91, $f5, $00, $5c, $8f, $00, $64, $f3
.byte $00, $64, $8f, $00, $64, $8f, $00, $64, $91, $f9, $f3, $00, $1e, $a3, $00, $22, $a3, $00, $fd
.word @song0ch0loop
@song0ch1:
.byte $84
@song0ref308:
.byte $56, $8f, $00, $64, $8f, $00, $6e, $8f, $00, $72, $8f, $00, $64, $8f, $00, $6e, $8f, $00, $72
@song0ref327:
.byte $8f, $00, $78, $8f, $00, $64, $8f, $00, $78, $8f, $00, $76, $8f, $00, $64, $8f, $00, $76, $8f, $00, $72, $8f, $00, $6e
.byte $8f, $00
.byte $ff, $2d
.word @song0ref308
.byte $ff, $2d
.word @song0ref308
.byte $ff, $2d
.word @song0ref308
.byte $ff, $2d
.word @song0ref308
.byte $82
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
@song0ch1loop:
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $6e, $8f, $00, $5c, $8f, $00, $66, $8f, $00, $72, $8f, $00, $60, $8f, $00, $72, $8f, $00, $78, $8f, $00, $76, $8f, $00
.byte $6e, $8f, $00, $64, $8f, $00, $60, $8f, $00, $5e, $8f, $00, $56, $8f, $00, $4c, $8f, $00, $48, $8f, $00, $46, $8f, $00
.byte $92, $44, $8f, $00, $44, $8f, $00, $a7, $48, $8f, $00, $48, $8f, $00, $93, $44, $a3, $00, $84, $5a, $8f, $00, $5c, $8f
.byte $00, $6a, $8f, $00, $93, $72, $8f, $00, $74, $8f, $00, $02, $8f, $00, $92, $36, $a3, $00, $36, $8f, $00, $36, $8f, $00
.byte $93, $36, $8f, $00, $93, $3c, $f9, $a1, $00, $93, $4e, $8f, $00, $4e, $8f, $00, $a7, $48, $8f, $00, $48, $8f, $00, $93
.byte $4c, $a3, $00, $4c, $a3, $00, $4c, $a3, $00, $4c, $8f, $00, $52, $8f, $00, $56, $91, $e1, $00, $93, $56, $8f, $00, $54
.byte $f3, $00, $54, $8f, $00, $54, $8f, $00, $56, $8f, $00, $82
.byte $ff, $15
.word @song0ref308
.byte $64
.byte $ff, $1a
.word @song0ref327
.byte $fd
.word @song0ch1loop
@song0ch2:
.byte $f9, $f9, $b7, $80, $3e, $b7, $00, $4c, $b7, $00, $56, $f9, $a1, $00, $93, $3a, $b7, $00, $48, $b7, $00, $52, $f9, $a1
.byte $00, $93, $38, $b7, $00, $46, $b7, $00, $50, $f9, $a1, $00, $93, $36, $b7, $00, $44, $b7, $00, $4e, $f9, $a1, $00, $93
@song0ref637:
.byte $56, $8f, $00, $56, $8f, $00, $56, $8f, $00, $56, $8f, $00
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
@song0ch2loop:
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
@song0ref665:
.byte $54, $8f, $00, $54, $8f, $00, $54, $8f, $00, $54, $8f, $00
.byte $ff, $0c
.word @song0ref665
@song0ref680:
.byte $50, $8f, $00, $50, $8f, $00, $50, $8f, $00, $50, $8f, $00
.byte $ff, $0c
.word @song0ref680
@song0ref695:
.byte $4c, $8f, $00, $4c, $8f, $00, $4c, $8f, $00, $4c, $8f, $00
.byte $ff, $0c
.word @song0ref695
@song0ref710:
.byte $48, $8f, $00, $48, $8f, $00, $48, $8f, $00, $48, $8f, $00
.byte $ff, $0c
.word @song0ref710
@song0ref725:
.byte $4a, $8f, $00, $4a, $8f, $00, $4a, $8f, $00, $4a, $8f, $00
.byte $ff, $0c
.word @song0ref725
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref637
.byte $ff, $0c
.word @song0ref637
@song0ref758:
.byte $52, $8f, $00, $52, $8f, $00, $52, $8f, $00, $52, $8f, $00
.byte $ff, $0c
.word @song0ref758
.byte $ff, $0c
.word @song0ref680
.byte $ff, $0c
.word @song0ref680
@song0ref779:
.byte $4e, $8f, $00, $4e, $8f, $00, $4e, $8f, $00, $4e, $8f, $00
.byte $ff, $0c
.word @song0ref779
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref725
.byte $ff, $0c
.word @song0ref695
.byte $4e, $8f, $00, $a7, $52, $8f, $00, $a7, $56, $b7, $00, $3e, $8f, $00, $3e, $8f, $00, $3e, $8f, $00, $3e, $8f, $00, $3e
.byte $8f, $00, $3e, $8f, $00, $3e, $8f, $00
@song0ref838:
.byte $48, $8f, $00, $48, $8f, $00, $a7, $52, $8f, $00, $52, $8f, $00, $93, $44, $a3, $00, $44, $8f, $00, $44, $8f, $00, $44
.byte $8f, $00, $44, $8f, $00, $44, $8f, $00, $44, $8f, $00, $44, $8f, $00
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $26
.word @song0ref838
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref710
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref695
.byte $ff, $0c
.word @song0ref779
.byte $ff, $0c
.word @song0ref779
.byte $4e, $8f, $00, $bb, $4e, $a3, $00, $52, $a3, $00, $fd
.word @song0ch2loop
@song0ch3:
@song0ref922:
.byte $f9, $f9, $b7, $f9, $f9, $b7, $f9, $f9, $b7, $f9, $f9, $b7, $f9, $e1, $88, $4a, $8b, $00, $83, $40, $8b, $00, $83, $4a
.byte $8b, $00, $83, $40, $8b, $00, $83
@song0ref953:
.byte $8a, $40, $8b, $00, $83, $86, $58, $83, $00, $8b, $8c, $4a, $8f, $00, $86, $58, $83, $00, $8b
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
@song0ref978:
.byte $8a, $40, $8b, $00, $83, $86, $58, $83, $00, $8b, $8c, $4a, $8f, $00, $4a, $8f, $00
@song0ch3loop:
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0f
.word @song0ref953
.byte $ff, $0e
.word @song0ref978
.byte $fd
.word @song0ch3loop
@song0ch4:
.byte $ff, $0d
.word @song0ref922
.byte $f9, $b7, $f9, $f9, $cb
@song0ch4loop:
@song0ref1164:
.byte $f9, $f9, $cb, $f9, $f9, $cb, $f9, $f9, $cb, $f9, $f9, $cb
.byte $ff, $0c
.word @song0ref1164
.byte $ff, $0c
.word @song0ref1164
.byte $f9, $f9, $cb, $fd
.word @song0ch4loop
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab8/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_practice/lab8/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab6/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_practice/lab6/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab2/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 2,826 | code_practice/lab2/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, sbadaddr
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
.align(2)
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
|
nkgongxl/ucoreonrv | 2,699 | code_practice/riscv-pk/pk/entry.S | // See LICENSE for license details.
#include "encoding.h"
#include "bits.h"
.macro save_tf
# save gprs
STORE x1,1*REGBYTES(x2)
STORE x3,3*REGBYTES(x2)
STORE x4,4*REGBYTES(x2)
STORE x5,5*REGBYTES(x2)
STORE x6,6*REGBYTES(x2)
STORE x7,7*REGBYTES(x2)
STORE x8,8*REGBYTES(x2)
STORE x9,9*REGBYTES(x2)
STORE x10,10*REGBYTES(x2)
STORE x11,11*REGBYTES(x2)
STORE x12,12*REGBYTES(x2)
STORE x13,13*REGBYTES(x2)
STORE x14,14*REGBYTES(x2)
STORE x15,15*REGBYTES(x2)
STORE x16,16*REGBYTES(x2)
STORE x17,17*REGBYTES(x2)
STORE x18,18*REGBYTES(x2)
STORE x19,19*REGBYTES(x2)
STORE x20,20*REGBYTES(x2)
STORE x21,21*REGBYTES(x2)
STORE x22,22*REGBYTES(x2)
STORE x23,23*REGBYTES(x2)
STORE x24,24*REGBYTES(x2)
STORE x25,25*REGBYTES(x2)
STORE x26,26*REGBYTES(x2)
STORE x27,27*REGBYTES(x2)
STORE x28,28*REGBYTES(x2)
STORE x29,29*REGBYTES(x2)
STORE x30,30*REGBYTES(x2)
STORE x31,31*REGBYTES(x2)
# get sr, epc, badvaddr, cause
csrrw t0,sscratch,x0
csrr s0,sstatus
csrr t1,sepc
csrr t2,sbadaddr
csrr t3,scause
STORE t0,2*REGBYTES(x2)
STORE s0,32*REGBYTES(x2)
STORE t1,33*REGBYTES(x2)
STORE t2,34*REGBYTES(x2)
STORE t3,35*REGBYTES(x2)
# get faulting insn, if it wasn't a fetch-related trap
li x5,-1
STORE x5,36*REGBYTES(x2)
1:
.endm
.text
.align 2
.global trap_entry
trap_entry:
csrrw sp, sscratch, sp
bnez sp, 1f
csrr sp, sscratch
1:addi sp,sp,-320
save_tf
move a0,sp
jal handle_trap
mv a0,sp
# don't restore sscratch if trap came from kernel
andi s0,s0,SSTATUS_SPP
bnez s0,start_user
addi sp,sp,320
csrw sscratch,sp
.globl start_user
start_user:
LOAD t0, 32*REGBYTES(a0)
LOAD t1, 33*REGBYTES(a0)
csrw sstatus, t0
csrw sepc, t1
# restore x registers
LOAD x1,1*REGBYTES(a0)
LOAD x2,2*REGBYTES(a0)
LOAD x3,3*REGBYTES(a0)
LOAD x4,4*REGBYTES(a0)
LOAD x5,5*REGBYTES(a0)
LOAD x6,6*REGBYTES(a0)
LOAD x7,7*REGBYTES(a0)
LOAD x8,8*REGBYTES(a0)
LOAD x9,9*REGBYTES(a0)
LOAD x11,11*REGBYTES(a0)
LOAD x12,12*REGBYTES(a0)
LOAD x13,13*REGBYTES(a0)
LOAD x14,14*REGBYTES(a0)
LOAD x15,15*REGBYTES(a0)
LOAD x16,16*REGBYTES(a0)
LOAD x17,17*REGBYTES(a0)
LOAD x18,18*REGBYTES(a0)
LOAD x19,19*REGBYTES(a0)
LOAD x20,20*REGBYTES(a0)
LOAD x21,21*REGBYTES(a0)
LOAD x22,22*REGBYTES(a0)
LOAD x23,23*REGBYTES(a0)
LOAD x24,24*REGBYTES(a0)
LOAD x25,25*REGBYTES(a0)
LOAD x26,26*REGBYTES(a0)
LOAD x27,27*REGBYTES(a0)
LOAD x28,28*REGBYTES(a0)
LOAD x29,29*REGBYTES(a0)
LOAD x30,30*REGBYTES(a0)
LOAD x31,31*REGBYTES(a0)
# restore a0 last
LOAD x10,10*REGBYTES(a0)
# gtfo
sret
|
nkgongxl/ucoreonrv | 2,760 | code_practice/riscv-pk/machine/fp_asm.S | // See LICENSE for license details.
#ifdef __riscv_flen
#define get_f32(which) fmv.x.s a0, which; jr t0
#define put_f32(which) fmv.s.x which, a0; jr t0
#if __riscv_xlen == 64
# define get_f64(which) fmv.x.d a0, which; jr t0
# define put_f64(which) fmv.d.x which, a0; jr t0
#else
# define get_f64(which) fsd which, 0(a0); jr t0
# define put_f64(which) fld which, 0(a0); jr t0
#endif
.text
.option norvc
.globl get_f32_reg
get_f32_reg:
get_f32(f0)
get_f32(f1)
get_f32(f2)
get_f32(f3)
get_f32(f4)
get_f32(f5)
get_f32(f6)
get_f32(f7)
get_f32(f8)
get_f32(f9)
get_f32(f10)
get_f32(f11)
get_f32(f12)
get_f32(f13)
get_f32(f14)
get_f32(f15)
get_f32(f16)
get_f32(f17)
get_f32(f18)
get_f32(f19)
get_f32(f20)
get_f32(f21)
get_f32(f22)
get_f32(f23)
get_f32(f24)
get_f32(f25)
get_f32(f26)
get_f32(f27)
get_f32(f28)
get_f32(f29)
get_f32(f30)
get_f32(f31)
.text
.globl put_f32_reg
put_f32_reg:
put_f32(f0)
put_f32(f1)
put_f32(f2)
put_f32(f3)
put_f32(f4)
put_f32(f5)
put_f32(f6)
put_f32(f7)
put_f32(f8)
put_f32(f9)
put_f32(f10)
put_f32(f11)
put_f32(f12)
put_f32(f13)
put_f32(f14)
put_f32(f15)
put_f32(f16)
put_f32(f17)
put_f32(f18)
put_f32(f19)
put_f32(f20)
put_f32(f21)
put_f32(f22)
put_f32(f23)
put_f32(f24)
put_f32(f25)
put_f32(f26)
put_f32(f27)
put_f32(f28)
put_f32(f29)
put_f32(f30)
put_f32(f31)
#if __riscv_flen > 32
.text
.globl get_f64_reg
get_f64_reg:
get_f64(f0)
get_f64(f1)
get_f64(f2)
get_f64(f3)
get_f64(f4)
get_f64(f5)
get_f64(f6)
get_f64(f7)
get_f64(f8)
get_f64(f9)
get_f64(f10)
get_f64(f11)
get_f64(f12)
get_f64(f13)
get_f64(f14)
get_f64(f15)
get_f64(f16)
get_f64(f17)
get_f64(f18)
get_f64(f19)
get_f64(f20)
get_f64(f21)
get_f64(f22)
get_f64(f23)
get_f64(f24)
get_f64(f25)
get_f64(f26)
get_f64(f27)
get_f64(f28)
get_f64(f29)
get_f64(f30)
get_f64(f31)
.text
.globl put_f64_reg
put_f64_reg:
put_f64(f0)
put_f64(f1)
put_f64(f2)
put_f64(f3)
put_f64(f4)
put_f64(f5)
put_f64(f6)
put_f64(f7)
put_f64(f8)
put_f64(f9)
put_f64(f10)
put_f64(f11)
put_f64(f12)
put_f64(f13)
put_f64(f14)
put_f64(f15)
put_f64(f16)
put_f64(f17)
put_f64(f18)
put_f64(f19)
put_f64(f20)
put_f64(f21)
put_f64(f22)
put_f64(f23)
put_f64(f24)
put_f64(f25)
put_f64(f26)
put_f64(f27)
put_f64(f28)
put_f64(f29)
put_f64(f30)
put_f64(f31)
#endif
#endif
|
nkgongxl/ucoreonrv | 6,591 | code_practice/riscv-pk/machine/mentry.S | // See LICENSE for license details.
#include "mtrap.h"
#include "bits.h"
#include "config.h"
.data
.align 6
trap_table:
#define BAD_TRAP_VECTOR 0
.dc.a bad_trap
.dc.a pmp_trap
.dc.a illegal_insn_trap
.dc.a bad_trap
.dc.a misaligned_load_trap
.dc.a pmp_trap
.dc.a misaligned_store_trap
.dc.a pmp_trap
.dc.a bad_trap
.dc.a mcall_trap
.dc.a bad_trap
#ifdef BBL_BOOT_MACHINE
.dc.a mcall_trap
#else
.dc.a bad_trap
#endif /* BBL_BOOT_MACHINE */
.dc.a bad_trap
#define TRAP_FROM_MACHINE_MODE_VECTOR 13
.dc.a __trap_from_machine_mode
.dc.a bad_trap
.dc.a bad_trap
.option norvc
.section .text.init,"ax",@progbits
.globl reset_vector
reset_vector:
j do_reset
trap_vector:
csrrw sp, mscratch, sp
beqz sp, .Ltrap_from_machine_mode
STORE a0, 10*REGBYTES(sp)
STORE a1, 11*REGBYTES(sp)
csrr a1, mcause
bgez a1, .Lhandle_trap_in_machine_mode
# This is an interrupt. Discard the mcause MSB and decode the rest.
sll a1, a1, 1
# Is it a machine timer interrupt?
li a0, IRQ_M_TIMER * 2
bne a0, a1, 1f
# Yes. Simply clear MTIE and raise STIP.
li a0, MIP_MTIP
csrc mie, a0
li a0, MIP_STIP
csrs mip, a0
.Lmret:
# Go back whence we came.
LOAD a0, 10*REGBYTES(sp)
LOAD a1, 11*REGBYTES(sp)
csrrw sp, mscratch, sp
mret
1:
# Is it an IPI?
li a0, IRQ_M_SOFT * 2
bne a0, a1, .Lbad_trap
# Yes. First, clear the MIPI bit.
LOAD a0, MENTRY_IPI_OFFSET(sp)
sw x0, (a0)
fence
# Now, decode the cause(s).
#ifdef __riscv_atomic
addi a0, sp, MENTRY_IPI_PENDING_OFFSET
amoswap.w a0, x0, (a0)
#else
lw a0, MENTRY_IPI_PENDING_OFFSET(sp)
sw x0, MENTRY_IPI_PENDING_OFFSET(sp)
#endif
and a1, a0, IPI_SOFT
beqz a1, 1f
csrs mip, MIP_SSIP
1:
andi a1, a0, IPI_FENCE_I
beqz a1, 1f
fence.i
1:
andi a1, a0, IPI_SFENCE_VMA
beqz a1, 1f
sfence.vma
1:
andi a1, a0, IPI_HALT
beqz a1, 1f
wfi
j 1b
1:
j .Lmret
.Lhandle_trap_in_machine_mode:
# Preserve the registers. Compute the address of the trap handler.
STORE ra, 1*REGBYTES(sp)
STORE gp, 3*REGBYTES(sp)
STORE tp, 4*REGBYTES(sp)
STORE t0, 5*REGBYTES(sp)
1:auipc t0, %pcrel_hi(trap_table) # t0 <- %hi(trap_table)
STORE t1, 6*REGBYTES(sp)
sll t1, a1, LOG_REGBYTES # t1 <- mcause * ptr size
STORE t2, 7*REGBYTES(sp)
add t1, t0, t1 # t1 <- %hi(trap_table)[mcause]
STORE s0, 8*REGBYTES(sp)
LOAD t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause]
STORE s1, 9*REGBYTES(sp)
mv a0, sp # a0 <- regs
STORE a2,12*REGBYTES(sp)
csrr a2, mepc # a2 <- mepc
STORE a3,13*REGBYTES(sp)
csrrw t0, mscratch, x0 # t0 <- user sp
STORE a4,14*REGBYTES(sp)
STORE a5,15*REGBYTES(sp)
STORE a6,16*REGBYTES(sp)
STORE a7,17*REGBYTES(sp)
STORE s2,18*REGBYTES(sp)
STORE s3,19*REGBYTES(sp)
STORE s4,20*REGBYTES(sp)
STORE s5,21*REGBYTES(sp)
STORE s6,22*REGBYTES(sp)
STORE s7,23*REGBYTES(sp)
STORE s8,24*REGBYTES(sp)
STORE s9,25*REGBYTES(sp)
STORE s10,26*REGBYTES(sp)
STORE s11,27*REGBYTES(sp)
STORE t3,28*REGBYTES(sp)
STORE t4,29*REGBYTES(sp)
STORE t5,30*REGBYTES(sp)
STORE t6,31*REGBYTES(sp)
STORE t0, 2*REGBYTES(sp) # sp
#ifndef __riscv_flen
lw tp, (sp) # Move the emulated FCSR from x0's save slot into tp.
#endif
STORE x0, (sp) # Zero x0's save slot.
# Invoke the handler.
jalr t1
#ifndef __riscv_flen
sw tp, (sp) # Move the emulated FCSR from tp into x0's save slot.
#endif
restore_mscratch:
# Restore mscratch, so future traps will know they didn't come from M-mode.
csrw mscratch, sp
restore_regs:
# Restore all of the registers.
LOAD ra, 1*REGBYTES(sp)
LOAD gp, 3*REGBYTES(sp)
LOAD tp, 4*REGBYTES(sp)
LOAD t0, 5*REGBYTES(sp)
LOAD t1, 6*REGBYTES(sp)
LOAD t2, 7*REGBYTES(sp)
LOAD s0, 8*REGBYTES(sp)
LOAD s1, 9*REGBYTES(sp)
LOAD a0,10*REGBYTES(sp)
LOAD a1,11*REGBYTES(sp)
LOAD a2,12*REGBYTES(sp)
LOAD a3,13*REGBYTES(sp)
LOAD a4,14*REGBYTES(sp)
LOAD a5,15*REGBYTES(sp)
LOAD a6,16*REGBYTES(sp)
LOAD a7,17*REGBYTES(sp)
LOAD s2,18*REGBYTES(sp)
LOAD s3,19*REGBYTES(sp)
LOAD s4,20*REGBYTES(sp)
LOAD s5,21*REGBYTES(sp)
LOAD s6,22*REGBYTES(sp)
LOAD s7,23*REGBYTES(sp)
LOAD s8,24*REGBYTES(sp)
LOAD s9,25*REGBYTES(sp)
LOAD s10,26*REGBYTES(sp)
LOAD s11,27*REGBYTES(sp)
LOAD t3,28*REGBYTES(sp)
LOAD t4,29*REGBYTES(sp)
LOAD t5,30*REGBYTES(sp)
LOAD t6,31*REGBYTES(sp)
LOAD sp, 2*REGBYTES(sp)
mret
.Ltrap_from_machine_mode:
csrr sp, mscratch
addi sp, sp, -INTEGER_CONTEXT_SIZE
STORE a0,10*REGBYTES(sp)
STORE a1,11*REGBYTES(sp)
li a1, TRAP_FROM_MACHINE_MODE_VECTOR
j .Lhandle_trap_in_machine_mode
.Lbad_trap:
li a1, BAD_TRAP_VECTOR
j .Lhandle_trap_in_machine_mode
.globl __redirect_trap
__redirect_trap:
# reset sp to top of M-mode stack
li t0, MACHINE_STACK_SIZE
add sp, sp, t0
neg t0, t0
and sp, sp, t0
addi sp, sp, -MENTRY_FRAME_SIZE
j restore_mscratch
__trap_from_machine_mode:
jal trap_from_machine_mode
j restore_regs
do_reset:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
// save a0 and a1; arguments from previous boot loader stage:
// li x10, 0
// li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
csrw mscratch, x0
# write mtvec and make sure it sticks
la t0, trap_vector
csrw mtvec, t0
csrr t1, mtvec
1:bne t0, t1, 1b
la sp, stacks + RISCV_PGSIZE - MENTRY_FRAME_SIZE
csrr a3, mhartid
slli a2, a3, RISCV_PGSHIFT
add sp, sp, a2
bnez a3, .LmultiHartInit
#ifdef ZERO_BSS
# Zero out BSS; linker script provides alignment and padding
la t0, _fbss
la t1, _end
beq t0, t1, 2f
1:STORE zero, 0(t0)
addi t0, t0, REGBYTES
bne t0, t1, 1b
2:
#endif
# Boot on the first hart
j init_first_hart
.LmultiHartInit:
# set MSIE bit to receive IPI
li a2, MIP_MSIP
csrw mie, a2
.LmultiHart:
#if MAX_HARTS > 1
# wait for an IPI to signal that it's safe to boot
wfi
# masked harts never start
la a4, disabled_hart_mask
LOAD a4, 0(a4)
srl a4, a4, a3
andi a4, a4, 1
bnez a4, .LmultiHart
# only start if mip is set
csrr a2, mip
andi a2, a2, MIP_MSIP
beqz a2, .LmultiHart
# make sure our hart id is within a valid range
fence
li a2, MAX_HARTS
bltu a3, a2, init_other_hart
#endif
wfi
j .LmultiHart
.bss
.align RISCV_PGSHIFT
stacks:
.skip RISCV_PGSIZE * MAX_HARTS
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab7/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_practice/lab7/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab5/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_practice/lab5/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab4/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 2,763 | code_practice/lab4/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
.align 2
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save gprs
STORE x1,1*REGBYTES(sp)
STORE x3,3*REGBYTES(sp)
STORE x4,4*REGBYTES(sp)
STORE x5,5*REGBYTES(sp)
STORE x6,6*REGBYTES(sp)
STORE x7,7*REGBYTES(sp)
STORE x8,8*REGBYTES(sp)
STORE x9,9*REGBYTES(sp)
STORE x10,10*REGBYTES(sp)
STORE x11,11*REGBYTES(sp)
STORE x12,12*REGBYTES(sp)
STORE x13,13*REGBYTES(sp)
STORE x14,14*REGBYTES(sp)
STORE x15,15*REGBYTES(sp)
STORE x16,16*REGBYTES(sp)
STORE x17,17*REGBYTES(sp)
STORE x18,18*REGBYTES(sp)
STORE x19,19*REGBYTES(sp)
STORE x20,20*REGBYTES(sp)
STORE x21,21*REGBYTES(sp)
STORE x22,22*REGBYTES(sp)
STORE x23,23*REGBYTES(sp)
STORE x24,24*REGBYTES(sp)
STORE x25,25*REGBYTES(sp)
STORE x26,26*REGBYTES(sp)
STORE x27,27*REGBYTES(sp)
STORE x28,28*REGBYTES(sp)
STORE x29,29*REGBYTES(sp)
STORE x30,30*REGBYTES(sp)
STORE x31,31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
csrr s0, sscratch
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
// restore x registers
LOAD x1,1*REGBYTES(sp)
LOAD x3,3*REGBYTES(sp)
LOAD x4,4*REGBYTES(sp)
LOAD x5,5*REGBYTES(sp)
LOAD x6,6*REGBYTES(sp)
LOAD x7,7*REGBYTES(sp)
LOAD x8,8*REGBYTES(sp)
LOAD x9,9*REGBYTES(sp)
LOAD x10,10*REGBYTES(sp)
LOAD x11,11*REGBYTES(sp)
LOAD x12,12*REGBYTES(sp)
LOAD x13,13*REGBYTES(sp)
LOAD x14,14*REGBYTES(sp)
LOAD x15,15*REGBYTES(sp)
LOAD x16,16*REGBYTES(sp)
LOAD x17,17*REGBYTES(sp)
LOAD x18,18*REGBYTES(sp)
LOAD x19,19*REGBYTES(sp)
LOAD x20,20*REGBYTES(sp)
LOAD x21,21*REGBYTES(sp)
LOAD x22,22*REGBYTES(sp)
LOAD x23,23*REGBYTES(sp)
LOAD x24,24*REGBYTES(sp)
LOAD x25,25*REGBYTES(sp)
LOAD x26,26*REGBYTES(sp)
LOAD x27,27*REGBYTES(sp)
LOAD x28,28*REGBYTES(sp)
LOAD x29,29*REGBYTES(sp)
LOAD x30,30*REGBYTES(sp)
LOAD x31,31*REGBYTES(sp)
# restore sp last
LOAD x2,2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# go back from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_practice/lab3/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 2,665 | code_practice/lab3/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
.align 2
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save gprs
STORE x1,1*REGBYTES(sp)
STORE x3,3*REGBYTES(sp)
STORE x4,4*REGBYTES(sp)
STORE x5,5*REGBYTES(sp)
STORE x6,6*REGBYTES(sp)
STORE x7,7*REGBYTES(sp)
STORE x8,8*REGBYTES(sp)
STORE x9,9*REGBYTES(sp)
STORE x10,10*REGBYTES(sp)
STORE x11,11*REGBYTES(sp)
STORE x12,12*REGBYTES(sp)
STORE x13,13*REGBYTES(sp)
STORE x14,14*REGBYTES(sp)
STORE x15,15*REGBYTES(sp)
STORE x16,16*REGBYTES(sp)
STORE x17,17*REGBYTES(sp)
STORE x18,18*REGBYTES(sp)
STORE x19,19*REGBYTES(sp)
STORE x20,20*REGBYTES(sp)
STORE x21,21*REGBYTES(sp)
STORE x22,22*REGBYTES(sp)
STORE x23,23*REGBYTES(sp)
STORE x24,24*REGBYTES(sp)
STORE x25,25*REGBYTES(sp)
STORE x26,26*REGBYTES(sp)
STORE x27,27*REGBYTES(sp)
STORE x28,28*REGBYTES(sp)
STORE x29,29*REGBYTES(sp)
STORE x30,30*REGBYTES(sp)
STORE x31,31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
csrr s0, sscratch
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
// restore x registers
LOAD x1,1*REGBYTES(sp)
LOAD x3,3*REGBYTES(sp)
LOAD x4,4*REGBYTES(sp)
LOAD x5,5*REGBYTES(sp)
LOAD x6,6*REGBYTES(sp)
LOAD x7,7*REGBYTES(sp)
LOAD x8,8*REGBYTES(sp)
LOAD x9,9*REGBYTES(sp)
LOAD x10,10*REGBYTES(sp)
LOAD x11,11*REGBYTES(sp)
LOAD x12,12*REGBYTES(sp)
LOAD x13,13*REGBYTES(sp)
LOAD x14,14*REGBYTES(sp)
LOAD x15,15*REGBYTES(sp)
LOAD x16,16*REGBYTES(sp)
LOAD x17,17*REGBYTES(sp)
LOAD x18,18*REGBYTES(sp)
LOAD x19,19*REGBYTES(sp)
LOAD x20,20*REGBYTES(sp)
LOAD x21,21*REGBYTES(sp)
LOAD x22,22*REGBYTES(sp)
LOAD x23,23*REGBYTES(sp)
LOAD x24,24*REGBYTES(sp)
LOAD x25,25*REGBYTES(sp)
LOAD x26,26*REGBYTES(sp)
LOAD x27,27*REGBYTES(sp)
LOAD x28,28*REGBYTES(sp)
LOAD x29,29*REGBYTES(sp)
LOAD x30,30*REGBYTES(sp)
LOAD x31,31*REGBYTES(sp)
# restore sp last
LOAD x2,2*REGBYTES(sp)
.endm
.align 4
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
// sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
// go back from supervisor call
sret
|
nkgongxl/ucoreonrv | 2,854 | code_practice/lab1/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, sbadaddr
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
#addi sp, sp, 36 * REGBYTES
.endm
.globl __alltraps
.align(2)
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab8/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_answer/lab8/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab6/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_answer/lab6/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab2/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 2,826 | code_answer/lab2/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, sbadaddr
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
.align(2)
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
|
nkgongxl/ucoreonrv | 2,699 | code_answer/riscv-pk/pk/entry.S | // See LICENSE for license details.
#include "encoding.h"
#include "bits.h"
.macro save_tf
# save gprs
STORE x1,1*REGBYTES(x2)
STORE x3,3*REGBYTES(x2)
STORE x4,4*REGBYTES(x2)
STORE x5,5*REGBYTES(x2)
STORE x6,6*REGBYTES(x2)
STORE x7,7*REGBYTES(x2)
STORE x8,8*REGBYTES(x2)
STORE x9,9*REGBYTES(x2)
STORE x10,10*REGBYTES(x2)
STORE x11,11*REGBYTES(x2)
STORE x12,12*REGBYTES(x2)
STORE x13,13*REGBYTES(x2)
STORE x14,14*REGBYTES(x2)
STORE x15,15*REGBYTES(x2)
STORE x16,16*REGBYTES(x2)
STORE x17,17*REGBYTES(x2)
STORE x18,18*REGBYTES(x2)
STORE x19,19*REGBYTES(x2)
STORE x20,20*REGBYTES(x2)
STORE x21,21*REGBYTES(x2)
STORE x22,22*REGBYTES(x2)
STORE x23,23*REGBYTES(x2)
STORE x24,24*REGBYTES(x2)
STORE x25,25*REGBYTES(x2)
STORE x26,26*REGBYTES(x2)
STORE x27,27*REGBYTES(x2)
STORE x28,28*REGBYTES(x2)
STORE x29,29*REGBYTES(x2)
STORE x30,30*REGBYTES(x2)
STORE x31,31*REGBYTES(x2)
# get sr, epc, badvaddr, cause
csrrw t0,sscratch,x0
csrr s0,sstatus
csrr t1,sepc
csrr t2,sbadaddr
csrr t3,scause
STORE t0,2*REGBYTES(x2)
STORE s0,32*REGBYTES(x2)
STORE t1,33*REGBYTES(x2)
STORE t2,34*REGBYTES(x2)
STORE t3,35*REGBYTES(x2)
# get faulting insn, if it wasn't a fetch-related trap
li x5,-1
STORE x5,36*REGBYTES(x2)
1:
.endm
.text
.align 2
.global trap_entry
trap_entry:
csrrw sp, sscratch, sp
bnez sp, 1f
csrr sp, sscratch
1:addi sp,sp,-320
save_tf
move a0,sp
jal handle_trap
mv a0,sp
# don't restore sscratch if trap came from kernel
andi s0,s0,SSTATUS_SPP
bnez s0,start_user
addi sp,sp,320
csrw sscratch,sp
.globl start_user
start_user:
LOAD t0, 32*REGBYTES(a0)
LOAD t1, 33*REGBYTES(a0)
csrw sstatus, t0
csrw sepc, t1
# restore x registers
LOAD x1,1*REGBYTES(a0)
LOAD x2,2*REGBYTES(a0)
LOAD x3,3*REGBYTES(a0)
LOAD x4,4*REGBYTES(a0)
LOAD x5,5*REGBYTES(a0)
LOAD x6,6*REGBYTES(a0)
LOAD x7,7*REGBYTES(a0)
LOAD x8,8*REGBYTES(a0)
LOAD x9,9*REGBYTES(a0)
LOAD x11,11*REGBYTES(a0)
LOAD x12,12*REGBYTES(a0)
LOAD x13,13*REGBYTES(a0)
LOAD x14,14*REGBYTES(a0)
LOAD x15,15*REGBYTES(a0)
LOAD x16,16*REGBYTES(a0)
LOAD x17,17*REGBYTES(a0)
LOAD x18,18*REGBYTES(a0)
LOAD x19,19*REGBYTES(a0)
LOAD x20,20*REGBYTES(a0)
LOAD x21,21*REGBYTES(a0)
LOAD x22,22*REGBYTES(a0)
LOAD x23,23*REGBYTES(a0)
LOAD x24,24*REGBYTES(a0)
LOAD x25,25*REGBYTES(a0)
LOAD x26,26*REGBYTES(a0)
LOAD x27,27*REGBYTES(a0)
LOAD x28,28*REGBYTES(a0)
LOAD x29,29*REGBYTES(a0)
LOAD x30,30*REGBYTES(a0)
LOAD x31,31*REGBYTES(a0)
# restore a0 last
LOAD x10,10*REGBYTES(a0)
# gtfo
sret
|
nkgongxl/ucoreonrv | 2,760 | code_answer/riscv-pk/machine/fp_asm.S | // See LICENSE for license details.
#ifdef __riscv_flen
#define get_f32(which) fmv.x.s a0, which; jr t0
#define put_f32(which) fmv.s.x which, a0; jr t0
#if __riscv_xlen == 64
# define get_f64(which) fmv.x.d a0, which; jr t0
# define put_f64(which) fmv.d.x which, a0; jr t0
#else
# define get_f64(which) fsd which, 0(a0); jr t0
# define put_f64(which) fld which, 0(a0); jr t0
#endif
.text
.option norvc
.globl get_f32_reg
get_f32_reg:
get_f32(f0)
get_f32(f1)
get_f32(f2)
get_f32(f3)
get_f32(f4)
get_f32(f5)
get_f32(f6)
get_f32(f7)
get_f32(f8)
get_f32(f9)
get_f32(f10)
get_f32(f11)
get_f32(f12)
get_f32(f13)
get_f32(f14)
get_f32(f15)
get_f32(f16)
get_f32(f17)
get_f32(f18)
get_f32(f19)
get_f32(f20)
get_f32(f21)
get_f32(f22)
get_f32(f23)
get_f32(f24)
get_f32(f25)
get_f32(f26)
get_f32(f27)
get_f32(f28)
get_f32(f29)
get_f32(f30)
get_f32(f31)
.text
.globl put_f32_reg
put_f32_reg:
put_f32(f0)
put_f32(f1)
put_f32(f2)
put_f32(f3)
put_f32(f4)
put_f32(f5)
put_f32(f6)
put_f32(f7)
put_f32(f8)
put_f32(f9)
put_f32(f10)
put_f32(f11)
put_f32(f12)
put_f32(f13)
put_f32(f14)
put_f32(f15)
put_f32(f16)
put_f32(f17)
put_f32(f18)
put_f32(f19)
put_f32(f20)
put_f32(f21)
put_f32(f22)
put_f32(f23)
put_f32(f24)
put_f32(f25)
put_f32(f26)
put_f32(f27)
put_f32(f28)
put_f32(f29)
put_f32(f30)
put_f32(f31)
#if __riscv_flen > 32
.text
.globl get_f64_reg
get_f64_reg:
get_f64(f0)
get_f64(f1)
get_f64(f2)
get_f64(f3)
get_f64(f4)
get_f64(f5)
get_f64(f6)
get_f64(f7)
get_f64(f8)
get_f64(f9)
get_f64(f10)
get_f64(f11)
get_f64(f12)
get_f64(f13)
get_f64(f14)
get_f64(f15)
get_f64(f16)
get_f64(f17)
get_f64(f18)
get_f64(f19)
get_f64(f20)
get_f64(f21)
get_f64(f22)
get_f64(f23)
get_f64(f24)
get_f64(f25)
get_f64(f26)
get_f64(f27)
get_f64(f28)
get_f64(f29)
get_f64(f30)
get_f64(f31)
.text
.globl put_f64_reg
put_f64_reg:
put_f64(f0)
put_f64(f1)
put_f64(f2)
put_f64(f3)
put_f64(f4)
put_f64(f5)
put_f64(f6)
put_f64(f7)
put_f64(f8)
put_f64(f9)
put_f64(f10)
put_f64(f11)
put_f64(f12)
put_f64(f13)
put_f64(f14)
put_f64(f15)
put_f64(f16)
put_f64(f17)
put_f64(f18)
put_f64(f19)
put_f64(f20)
put_f64(f21)
put_f64(f22)
put_f64(f23)
put_f64(f24)
put_f64(f25)
put_f64(f26)
put_f64(f27)
put_f64(f28)
put_f64(f29)
put_f64(f30)
put_f64(f31)
#endif
#endif
|
nkgongxl/ucoreonrv | 6,591 | code_answer/riscv-pk/machine/mentry.S | // See LICENSE for license details.
#include "mtrap.h"
#include "bits.h"
#include "config.h"
.data
.align 6
trap_table:
#define BAD_TRAP_VECTOR 0
.dc.a bad_trap
.dc.a pmp_trap
.dc.a illegal_insn_trap
.dc.a bad_trap
.dc.a misaligned_load_trap
.dc.a pmp_trap
.dc.a misaligned_store_trap
.dc.a pmp_trap
.dc.a bad_trap
.dc.a mcall_trap
.dc.a bad_trap
#ifdef BBL_BOOT_MACHINE
.dc.a mcall_trap
#else
.dc.a bad_trap
#endif /* BBL_BOOT_MACHINE */
.dc.a bad_trap
#define TRAP_FROM_MACHINE_MODE_VECTOR 13
.dc.a __trap_from_machine_mode
.dc.a bad_trap
.dc.a bad_trap
.option norvc
.section .text.init,"ax",@progbits
.globl reset_vector
reset_vector:
j do_reset
trap_vector:
csrrw sp, mscratch, sp
beqz sp, .Ltrap_from_machine_mode
STORE a0, 10*REGBYTES(sp)
STORE a1, 11*REGBYTES(sp)
csrr a1, mcause
bgez a1, .Lhandle_trap_in_machine_mode
# This is an interrupt. Discard the mcause MSB and decode the rest.
sll a1, a1, 1
# Is it a machine timer interrupt?
li a0, IRQ_M_TIMER * 2
bne a0, a1, 1f
# Yes. Simply clear MTIE and raise STIP.
li a0, MIP_MTIP
csrc mie, a0
li a0, MIP_STIP
csrs mip, a0
.Lmret:
# Go back whence we came.
LOAD a0, 10*REGBYTES(sp)
LOAD a1, 11*REGBYTES(sp)
csrrw sp, mscratch, sp
mret
1:
# Is it an IPI?
li a0, IRQ_M_SOFT * 2
bne a0, a1, .Lbad_trap
# Yes. First, clear the MIPI bit.
LOAD a0, MENTRY_IPI_OFFSET(sp)
sw x0, (a0)
fence
# Now, decode the cause(s).
#ifdef __riscv_atomic
addi a0, sp, MENTRY_IPI_PENDING_OFFSET
amoswap.w a0, x0, (a0)
#else
lw a0, MENTRY_IPI_PENDING_OFFSET(sp)
sw x0, MENTRY_IPI_PENDING_OFFSET(sp)
#endif
and a1, a0, IPI_SOFT
beqz a1, 1f
csrs mip, MIP_SSIP
1:
andi a1, a0, IPI_FENCE_I
beqz a1, 1f
fence.i
1:
andi a1, a0, IPI_SFENCE_VMA
beqz a1, 1f
sfence.vma
1:
andi a1, a0, IPI_HALT
beqz a1, 1f
wfi
j 1b
1:
j .Lmret
.Lhandle_trap_in_machine_mode:
# Preserve the registers. Compute the address of the trap handler.
STORE ra, 1*REGBYTES(sp)
STORE gp, 3*REGBYTES(sp)
STORE tp, 4*REGBYTES(sp)
STORE t0, 5*REGBYTES(sp)
1:auipc t0, %pcrel_hi(trap_table) # t0 <- %hi(trap_table)
STORE t1, 6*REGBYTES(sp)
sll t1, a1, LOG_REGBYTES # t1 <- mcause * ptr size
STORE t2, 7*REGBYTES(sp)
add t1, t0, t1 # t1 <- %hi(trap_table)[mcause]
STORE s0, 8*REGBYTES(sp)
LOAD t1, %pcrel_lo(1b)(t1) # t1 <- trap_table[mcause]
STORE s1, 9*REGBYTES(sp)
mv a0, sp # a0 <- regs
STORE a2,12*REGBYTES(sp)
csrr a2, mepc # a2 <- mepc
STORE a3,13*REGBYTES(sp)
csrrw t0, mscratch, x0 # t0 <- user sp
STORE a4,14*REGBYTES(sp)
STORE a5,15*REGBYTES(sp)
STORE a6,16*REGBYTES(sp)
STORE a7,17*REGBYTES(sp)
STORE s2,18*REGBYTES(sp)
STORE s3,19*REGBYTES(sp)
STORE s4,20*REGBYTES(sp)
STORE s5,21*REGBYTES(sp)
STORE s6,22*REGBYTES(sp)
STORE s7,23*REGBYTES(sp)
STORE s8,24*REGBYTES(sp)
STORE s9,25*REGBYTES(sp)
STORE s10,26*REGBYTES(sp)
STORE s11,27*REGBYTES(sp)
STORE t3,28*REGBYTES(sp)
STORE t4,29*REGBYTES(sp)
STORE t5,30*REGBYTES(sp)
STORE t6,31*REGBYTES(sp)
STORE t0, 2*REGBYTES(sp) # sp
#ifndef __riscv_flen
lw tp, (sp) # Move the emulated FCSR from x0's save slot into tp.
#endif
STORE x0, (sp) # Zero x0's save slot.
# Invoke the handler.
jalr t1
#ifndef __riscv_flen
sw tp, (sp) # Move the emulated FCSR from tp into x0's save slot.
#endif
restore_mscratch:
# Restore mscratch, so future traps will know they didn't come from M-mode.
csrw mscratch, sp
restore_regs:
# Restore all of the registers.
LOAD ra, 1*REGBYTES(sp)
LOAD gp, 3*REGBYTES(sp)
LOAD tp, 4*REGBYTES(sp)
LOAD t0, 5*REGBYTES(sp)
LOAD t1, 6*REGBYTES(sp)
LOAD t2, 7*REGBYTES(sp)
LOAD s0, 8*REGBYTES(sp)
LOAD s1, 9*REGBYTES(sp)
LOAD a0,10*REGBYTES(sp)
LOAD a1,11*REGBYTES(sp)
LOAD a2,12*REGBYTES(sp)
LOAD a3,13*REGBYTES(sp)
LOAD a4,14*REGBYTES(sp)
LOAD a5,15*REGBYTES(sp)
LOAD a6,16*REGBYTES(sp)
LOAD a7,17*REGBYTES(sp)
LOAD s2,18*REGBYTES(sp)
LOAD s3,19*REGBYTES(sp)
LOAD s4,20*REGBYTES(sp)
LOAD s5,21*REGBYTES(sp)
LOAD s6,22*REGBYTES(sp)
LOAD s7,23*REGBYTES(sp)
LOAD s8,24*REGBYTES(sp)
LOAD s9,25*REGBYTES(sp)
LOAD s10,26*REGBYTES(sp)
LOAD s11,27*REGBYTES(sp)
LOAD t3,28*REGBYTES(sp)
LOAD t4,29*REGBYTES(sp)
LOAD t5,30*REGBYTES(sp)
LOAD t6,31*REGBYTES(sp)
LOAD sp, 2*REGBYTES(sp)
mret
.Ltrap_from_machine_mode:
csrr sp, mscratch
addi sp, sp, -INTEGER_CONTEXT_SIZE
STORE a0,10*REGBYTES(sp)
STORE a1,11*REGBYTES(sp)
li a1, TRAP_FROM_MACHINE_MODE_VECTOR
j .Lhandle_trap_in_machine_mode
.Lbad_trap:
li a1, BAD_TRAP_VECTOR
j .Lhandle_trap_in_machine_mode
.globl __redirect_trap
__redirect_trap:
# reset sp to top of M-mode stack
li t0, MACHINE_STACK_SIZE
add sp, sp, t0
neg t0, t0
and sp, sp, t0
addi sp, sp, -MENTRY_FRAME_SIZE
j restore_mscratch
__trap_from_machine_mode:
jal trap_from_machine_mode
j restore_regs
do_reset:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
// save a0 and a1; arguments from previous boot loader stage:
// li x10, 0
// li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
csrw mscratch, x0
# write mtvec and make sure it sticks
la t0, trap_vector
csrw mtvec, t0
csrr t1, mtvec
1:bne t0, t1, 1b
la sp, stacks + RISCV_PGSIZE - MENTRY_FRAME_SIZE
csrr a3, mhartid
slli a2, a3, RISCV_PGSHIFT
add sp, sp, a2
bnez a3, .LmultiHartInit
#ifdef ZERO_BSS
# Zero out BSS; linker script provides alignment and padding
la t0, _fbss
la t1, _end
beq t0, t1, 2f
1:STORE zero, 0(t0)
addi t0, t0, REGBYTES
bne t0, t1, 1b
2:
#endif
# Boot on the first hart
j init_first_hart
.LmultiHartInit:
# set MSIE bit to receive IPI
li a2, MIP_MSIP
csrw mie, a2
.LmultiHart:
#if MAX_HARTS > 1
# wait for an IPI to signal that it's safe to boot
wfi
# masked harts never start
la a4, disabled_hart_mask
LOAD a4, 0(a4)
srl a4, a4, a3
andi a4, a4, 1
bnez a4, .LmultiHart
# only start if mip is set
csrr a2, mip
andi a2, a2, MIP_MSIP
beqz a2, .LmultiHart
# make sure our hart id is within a valid range
fence
li a2, MAX_HARTS
bltu a3, a2, init_other_hart
#endif
wfi
j .LmultiHart
.bss
.align RISCV_PGSHIFT
stacks:
.skip RISCV_PGSIZE * MAX_HARTS
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab7/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_answer/lab7/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 4,150 | code_answer/lab5/boot/bootasm.S | #include <asm.h>
# Start the CPU: switch to 32-bit protected mode, jump into C.
# The BIOS loads this code from the first sector of the hard disk into
# memory at physical address 0x7c00 and starts executing in real mode
# with %cs=0 %ip=7c00.
.set PROT_MODE_CSEG, 0x8 # kernel code segment selector
.set PROT_MODE_DSEG, 0x10 # kernel data segment selector
.set CR0_PE_ON, 0x1 # protected mode enable flag
.set SMAP, 0x534d4150
# start address should be 0:7c00, in real mode, the beginning address of the running bootloader
.globl start
start:
.code16 # Assemble for 16-bit mode
cli # Disable interrupts
cld # String operations increment
# Set up the important data segment registers (DS, ES, SS).
xorw %ax, %ax # Segment number zero
movw %ax, %ds # -> Data Segment
movw %ax, %es # -> Extra Segment
movw %ax, %ss # -> Stack Segment
# Enable A20:
# For backwards compatibility with the earliest PCs, physical
# address line 20 is tied low, so that addresses higher than
# 1MB wrap around to zero by default. This code undoes this.
seta20.1:
inb $0x64, %al # Wait for not busy(8042 input buffer empty).
testb $0x2, %al
jnz seta20.1
movb $0xd1, %al # 0xd1 -> port 0x64
outb %al, $0x64 # 0xd1 means: write data to 8042's P2 port
seta20.2:
inb $0x64, %al # Wait for not busy(8042 input buffer empty).
testb $0x2, %al
jnz seta20.2
movb $0xdf, %al # 0xdf -> port 0x60
outb %al, $0x60 # 0xdf = 11011111, means set P2's A20 bit(the 1 bit) to 1
probe_memory:
movl $0, 0x8000
xorl %ebx, %ebx
movw $0x8004, %di
start_probe:
movl $0xE820, %eax
movl $20, %ecx
movl $SMAP, %edx
int $0x15
jnc cont
movw $12345, 0x8000
jmp finish_probe
cont:
addw $20, %di
incl 0x8000
cmpl $0, %ebx
jnz start_probe
finish_probe:
# Switch from real to protected mode, using a bootstrap GDT
# and segment translation that makes virtual addresses
# identical to physical addresses, so that the
# effective memory map does not change during the switch.
lgdt gdtdesc
movl %cr0, %eax
orl $CR0_PE_ON, %eax
movl %eax, %cr0
# Jump to next instruction, but in 32-bit code segment.
# Switches processor into 32-bit mode.
ljmp $PROT_MODE_CSEG, $protcseg
.code32 # Assemble for 32-bit mode
protcseg:
# Set up the protected-mode data segment registers
movw $PROT_MODE_DSEG, %ax # Our data segment selector
movw %ax, %ds # -> DS: Data Segment
movw %ax, %es # -> ES: Extra Segment
movw %ax, %fs # -> FS
movw %ax, %gs # -> GS
movw %ax, %ss # -> SS: Stack Segment
# Set up the stack pointer and call into C. The stack region is from 0--start(0x7c00)
movl $0x0, %ebp
movl $start, %esp
call bootmain
# If bootmain returns (it shouldn't), loop.
spin:
jmp spin
.data
# Bootstrap GDT
.p2align 2 # force 4 byte alignment
gdt:
SEG_NULLASM # null seg
SEG_ASM(STA_X|STA_R, 0x0, 0xffffffff) # code seg for bootloader and kernel
SEG_ASM(STA_W, 0x0, 0xffffffff) # data seg for bootloader and kernel
gdtdesc:
.word 0x17 # sizeof(gdt) - 1
.long gdt # address gdt
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab5/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 3,548 | code_answer/lab5/kern/trap/trapentry.S | #include <riscv.h>
.altmacro
.align 2
.macro SAVE_ALL
LOCAL _restore_kernel_sp
LOCAL _save_context
# If coming from userspace, preserve the user stack pointer and load
# the kernel stack pointer. If we came from the kernel, sscratch
# will contain 0, and we should continue on the current stack.
csrrw sp, sscratch, sp
bnez sp, _save_context
_restore_kernel_sp:
csrr sp, sscratch
_save_context:
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, tval, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOCAL _save_kernel_sp
LOCAL _restore_context
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
andi s0, s1, SSTATUS_SPP
bnez s0, _restore_context
_save_kernel_sp:
# Save unwound kernel stack pointer in sscratch
addi s0, sp, 36 * REGBYTES
csrw sscratch, s0
_restore_context:
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab4/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 2,763 | code_answer/lab4/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
.align 2
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save gprs
STORE x1,1*REGBYTES(sp)
STORE x3,3*REGBYTES(sp)
STORE x4,4*REGBYTES(sp)
STORE x5,5*REGBYTES(sp)
STORE x6,6*REGBYTES(sp)
STORE x7,7*REGBYTES(sp)
STORE x8,8*REGBYTES(sp)
STORE x9,9*REGBYTES(sp)
STORE x10,10*REGBYTES(sp)
STORE x11,11*REGBYTES(sp)
STORE x12,12*REGBYTES(sp)
STORE x13,13*REGBYTES(sp)
STORE x14,14*REGBYTES(sp)
STORE x15,15*REGBYTES(sp)
STORE x16,16*REGBYTES(sp)
STORE x17,17*REGBYTES(sp)
STORE x18,18*REGBYTES(sp)
STORE x19,19*REGBYTES(sp)
STORE x20,20*REGBYTES(sp)
STORE x21,21*REGBYTES(sp)
STORE x22,22*REGBYTES(sp)
STORE x23,23*REGBYTES(sp)
STORE x24,24*REGBYTES(sp)
STORE x25,25*REGBYTES(sp)
STORE x26,26*REGBYTES(sp)
STORE x27,27*REGBYTES(sp)
STORE x28,28*REGBYTES(sp)
STORE x29,29*REGBYTES(sp)
STORE x30,30*REGBYTES(sp)
STORE x31,31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
csrr s0, sscratch
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
// restore x registers
LOAD x1,1*REGBYTES(sp)
LOAD x3,3*REGBYTES(sp)
LOAD x4,4*REGBYTES(sp)
LOAD x5,5*REGBYTES(sp)
LOAD x6,6*REGBYTES(sp)
LOAD x7,7*REGBYTES(sp)
LOAD x8,8*REGBYTES(sp)
LOAD x9,9*REGBYTES(sp)
LOAD x10,10*REGBYTES(sp)
LOAD x11,11*REGBYTES(sp)
LOAD x12,12*REGBYTES(sp)
LOAD x13,13*REGBYTES(sp)
LOAD x14,14*REGBYTES(sp)
LOAD x15,15*REGBYTES(sp)
LOAD x16,16*REGBYTES(sp)
LOAD x17,17*REGBYTES(sp)
LOAD x18,18*REGBYTES(sp)
LOAD x19,19*REGBYTES(sp)
LOAD x20,20*REGBYTES(sp)
LOAD x21,21*REGBYTES(sp)
LOAD x22,22*REGBYTES(sp)
LOAD x23,23*REGBYTES(sp)
LOAD x24,24*REGBYTES(sp)
LOAD x25,25*REGBYTES(sp)
LOAD x26,26*REGBYTES(sp)
LOAD x27,27*REGBYTES(sp)
LOAD x28,28*REGBYTES(sp)
LOAD x29,29*REGBYTES(sp)
LOAD x30,30*REGBYTES(sp)
LOAD x31,31*REGBYTES(sp)
# restore sp last
LOAD x2,2*REGBYTES(sp)
.endm
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# go back from supervisor call
sret
.globl forkrets
forkrets:
# set stack to this new process's trapframe
move sp, a0
j __trapret
|
nkgongxl/ucoreonrv | 1,365 | code_answer/lab3/kern/init/entry.S | #include <mmu.h>
#include <memlayout.h>
.section .text,"ax",%progbits
.globl kern_entry
kern_entry:
# t0 := 三级页表的虚拟地址
lui t0, %hi(boot_page_table_sv39)
# t1 := 0xffffffff40000000 即虚实映射偏移量
li t1, 0xffffffffc0000000 - 0x80000000
# t0 减去虚实映射偏移量 0xffffffff40000000，变为三级页表的物理地址
sub t0, t0, t1
# t0 >>= 12，变为三级页表的物理页号
srli t0, t0, 12
# t1 := 8 << 60，设置 satp 的 MODE 字段为 Sv39
li t1, 8 << 60
# 将刚才计算出的预设三级页表物理页号附加到 satp 中
or t0, t0, t1
# 将算出的 t0(即新的MODE|页表基址物理页号) 覆盖到 satp 中
csrw satp, t0
# 使用 sfence.vma 指令刷新 TLB
sfence.vma
# 从此，我们给内核搭建出了一个完美的虚拟内存空间！
#nop # 可能映射的位置有些bug。。插入一个nop
# 我们在虚拟内存空间中：随意将 sp 设置为虚拟地址！
lui sp, %hi(bootstacktop)
# 我们在虚拟内存空间中：随意跳转到虚拟地址！
# 跳转到 kern_init
lui t0, %hi(kern_init)
addi t0, t0, %lo(kern_init)
jr t0
.section .data
# .align 2^12
.align PGSHIFT
.global bootstack
bootstack:
.space KSTACKSIZE
.global bootstacktop
bootstacktop:
.section .data
# 由于我们要把这个页表放到一个页里面，因此必须 12 位对齐
.align PGSHIFT
.global boot_page_table_sv39
# 分配 4KiB 内存给预设的三级页表
boot_page_table_sv39:
# 0xffffffff_c0000000 map to 0x80000000 (1G)
# 前 511 个页表项均设置为 0 ，因此 V=0 ，意味着是空的(unmapped)
.zero 8 * 511
# 设置最后一个页表项，PPN=0x80000，标志位 VRWXAD 均为 1
.quad (0x80000 << 10) | 0xcf # VRWXAD
|
nkgongxl/ucoreonrv | 2,665 | code_answer/lab3/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
.align 2
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save gprs
STORE x1,1*REGBYTES(sp)
STORE x3,3*REGBYTES(sp)
STORE x4,4*REGBYTES(sp)
STORE x5,5*REGBYTES(sp)
STORE x6,6*REGBYTES(sp)
STORE x7,7*REGBYTES(sp)
STORE x8,8*REGBYTES(sp)
STORE x9,9*REGBYTES(sp)
STORE x10,10*REGBYTES(sp)
STORE x11,11*REGBYTES(sp)
STORE x12,12*REGBYTES(sp)
STORE x13,13*REGBYTES(sp)
STORE x14,14*REGBYTES(sp)
STORE x15,15*REGBYTES(sp)
STORE x16,16*REGBYTES(sp)
STORE x17,17*REGBYTES(sp)
STORE x18,18*REGBYTES(sp)
STORE x19,19*REGBYTES(sp)
STORE x20,20*REGBYTES(sp)
STORE x21,21*REGBYTES(sp)
STORE x22,22*REGBYTES(sp)
STORE x23,23*REGBYTES(sp)
STORE x24,24*REGBYTES(sp)
STORE x25,25*REGBYTES(sp)
STORE x26,26*REGBYTES(sp)
STORE x27,27*REGBYTES(sp)
STORE x28,28*REGBYTES(sp)
STORE x29,29*REGBYTES(sp)
STORE x30,30*REGBYTES(sp)
STORE x31,31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
csrr s0, sscratch
csrr s1, sstatus
csrr s2, sepc
csrr s3, 0x143
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
// restore x registers
LOAD x1,1*REGBYTES(sp)
LOAD x3,3*REGBYTES(sp)
LOAD x4,4*REGBYTES(sp)
LOAD x5,5*REGBYTES(sp)
LOAD x6,6*REGBYTES(sp)
LOAD x7,7*REGBYTES(sp)
LOAD x8,8*REGBYTES(sp)
LOAD x9,9*REGBYTES(sp)
LOAD x10,10*REGBYTES(sp)
LOAD x11,11*REGBYTES(sp)
LOAD x12,12*REGBYTES(sp)
LOAD x13,13*REGBYTES(sp)
LOAD x14,14*REGBYTES(sp)
LOAD x15,15*REGBYTES(sp)
LOAD x16,16*REGBYTES(sp)
LOAD x17,17*REGBYTES(sp)
LOAD x18,18*REGBYTES(sp)
LOAD x19,19*REGBYTES(sp)
LOAD x20,20*REGBYTES(sp)
LOAD x21,21*REGBYTES(sp)
LOAD x22,22*REGBYTES(sp)
LOAD x23,23*REGBYTES(sp)
LOAD x24,24*REGBYTES(sp)
LOAD x25,25*REGBYTES(sp)
LOAD x26,26*REGBYTES(sp)
LOAD x27,27*REGBYTES(sp)
LOAD x28,28*REGBYTES(sp)
LOAD x29,29*REGBYTES(sp)
LOAD x30,30*REGBYTES(sp)
LOAD x31,31*REGBYTES(sp)
# restore sp last
LOAD x2,2*REGBYTES(sp)
.endm
.align 4
.globl __alltraps
__alltraps:
SAVE_ALL
move a0, sp
jal trap
// sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
// go back from supervisor call
sret
|
nkgongxl/ucoreonrv | 2,854 | code_answer/lab1/kern/trap/trapentry.S | #include <riscv.h>
.macro SAVE_ALL
csrw sscratch, sp
addi sp, sp, -36 * REGBYTES
# save x registers
STORE x0, 0*REGBYTES(sp)
STORE x1, 1*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
# get sr, epc, badvaddr, cause
# Set sscratch register to 0, so that if a recursive exception
# occurs, the exception vector knows it came from the kernel
csrrw s0, sscratch, x0
csrr s1, sstatus
csrr s2, sepc
csrr s3, sbadaddr
csrr s4, scause
STORE s0, 2*REGBYTES(sp)
STORE s1, 32*REGBYTES(sp)
STORE s2, 33*REGBYTES(sp)
STORE s3, 34*REGBYTES(sp)
STORE s4, 35*REGBYTES(sp)
.endm
.macro RESTORE_ALL
LOAD s1, 32*REGBYTES(sp)
LOAD s2, 33*REGBYTES(sp)
csrw sstatus, s1
csrw sepc, s2
# restore x registers
LOAD x1, 1*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
# restore sp last
LOAD x2, 2*REGBYTES(sp)
#addi sp, sp, 36 * REGBYTES
.endm
.globl __alltraps
.align(2)
__alltraps:
SAVE_ALL
move a0, sp
jal trap
# sp should be the same as before "jal trap"
.globl __trapret
__trapret:
RESTORE_ALL
# return from supervisor call
sret
|
nopjne/DaisyDrive64 | 3,317 | external/libdragon/tests/rsp_test.S | #include <rsp_queue.inc>
#define ASSERT_GP_BACKWARD 0xF001 // Also defined in test_rspq.c
.set noreorder
.set at
.data
RSPQ_BeginOverlayHeader
RSPQ_DefineCommand command_test, 4 # 0x00
RSPQ_DefineCommand command_test, 8 # 0x01
RSPQ_DefineCommand command_test, 16 # 0x02
RSPQ_DefineCommand command_wait, 8 # 0x03
RSPQ_DefineCommand command_output, 8 # 0x04
RSPQ_DefineCommand command_reset, 4 # 0x05
RSPQ_DefineCommand command_test_high, 4 # 0x06
RSPQ_DefineCommand command_reset_log, 4 # 0x07
RSPQ_DefineCommand command_big, 132 # 0x08
RSPQ_DefineCommand command_big_out, 8 # 0x09
RSPQ_EndOverlayHeader
RSPQ_BeginSavedState
TEST_DATA:
TEST_PADDING: .long 0
TEST_VARIABLE: .long 0
TEST_PADDING2: .long 0
TEST_VARIABLE2: .long 0
RSPQ_EndSavedState
BIG_LOG_PTR: .long 0
.align 10
BIG_LOG: .ds.b 2048
.align 2
TEST_BIG: .ds.b 128
.text
command_test:
lw t0, %lo(TEST_VARIABLE)
and a0, 0xFFFFFF
add t0, a0
jr ra
sw t0, %lo(TEST_VARIABLE)
command_test_high:
# Compare the last entry in the big log with the current command (RDRAM+GP).
# If RDRAM pointer is the same, but GP is less than before, it means that
# GP has moved backward in the same buffer, and this is surely an error.
# It can be caused by many different bug, so we do a RSP assert that can
# be useful while debugging.
lw s0, %lo(BIG_LOG_PTR)
lw t1, %lo(RSPQ_RDRAM_PTR)
lw t2, %lo(BIG_LOG) -16(s0)
bne t1, t2, 1f
lw t2, %lo(BIG_LOG) -12(s0)
bgt rspq_dmem_buf_ptr, t2, 1f
nop
assert ASSERT_GP_BACKWARD
1:
# Save the current command in the big log. This is useful as a trace
# during debugging. The big log contains all command_test_high commands
# that have been executed.
and a0, 0xFFFFFF
sw t1, %lo(BIG_LOG) + 0(s0)
sw rspq_dmem_buf_ptr, %lo(BIG_LOG) + 4(s0)
sw a0, %lo(BIG_LOG) + 8(s0)
lw t0, %lo(TEST_VARIABLE2)
sw t0, %lo(BIG_LOG) + 12(s0)
addi s0, 16
sw s0, %lo(BIG_LOG_PTR)
lw t0, %lo(TEST_VARIABLE2)
add t0, a0
jr ra
sw t0, %lo(TEST_VARIABLE2)
command_wait:
bgtz a1, command_wait
addi a1, -1
jr ra
nop
command_output:
move s0, a1
li s4, %lo(TEST_DATA)
j DMAOut
li t0, DMA_SIZE(16, 1)
command_reset:
# Save the command_reset into the big log.
lw s0, %lo(BIG_LOG_PTR)
lw t1, %lo(RSPQ_RDRAM_PTR)
sw t1, %lo(BIG_LOG) + 0(s0)
sw gp, %lo(BIG_LOG) + 4(s0)
sw zero, %lo(BIG_LOG) + 8(s0)
sw zero, %lo(BIG_LOG) + 12(s0)
addi s0, 16
sw s0, %lo(BIG_LOG_PTR)
sw zero, %lo(TEST_VARIABLE)
jr ra
sw zero, %lo(TEST_VARIABLE2)
command_reset_log:
# Reset the big log pointer to the start
jr ra
sw zero, %lo(BIG_LOG_PTR)
command_big:
addi s1, rspq_dmem_buf_ptr, -128
move s2, zero
command_big_loop:
lw t0, %lo(RSPQ_DMEM_BUFFER)(s1)
lw t1, %lo(TEST_BIG)(s2)
xor t0, t1
sw t0, %lo(TEST_BIG)(s2)
add s1, 0x4
blt s1, rspq_dmem_buf_ptr, command_big_loop
add s2, 0x4
jr ra
nop
command_big_out:
move s0, a1
li s4, %lo(TEST_BIG)
j DMAOut
li t0, DMA_SIZE(128, 1)
|
nopjne/DaisyDrive64 | 2,286 | external/libdragon/src/rsp_crash.S | # RSP ucode that is used as part of the crash handler.
# It extracts the value of all registers into DMEM so that they can be
# shown in the exception screen.
#include <rsp.inc>
.data
EMPTY: .long 0
.text
.globl _start
_start:
.set noat
sw $0, 0*4(zero)
sw $1, 1*4(zero)
sw $2, 2*4(zero)
sw $3, 3*4(zero)
sw $4, 4*4(zero)
sw $5, 5*4(zero)
sw $6, 6*4(zero)
sw $7, 7*4(zero)
sw $8, 8*4(zero)
sw $9, 9*4(zero)
sw $10, 10*4(zero)
sw $11, 11*4(zero)
sw $12, 12*4(zero)
sw $13, 13*4(zero)
sw $14, 14*4(zero)
sw $15, 15*4(zero)
sw $16, 16*4(zero)
sw $17, 17*4(zero)
sw $18, 18*4(zero)
sw $19, 19*4(zero)
sw $20, 20*4(zero)
sw $21, 21*4(zero)
sw $22, 22*4(zero)
sw $23, 23*4(zero)
sw $24, 24*4(zero)
sw $25, 25*4(zero)
sw $26, 26*4(zero)
sw $27, 27*4(zero)
sw $28, 28*4(zero)
sw $29, 29*4(zero)
sw $30, 30*4(zero)
sw $31, 31*4(zero)
li s0, 32*4
sqv $v00, 0*16,s0
sqv $v01, 1*16,s0
sqv $v02, 2*16,s0
sqv $v03, 3*16,s0
sqv $v04, 4*16,s0
sqv $v05, 5*16,s0
sqv $v06, 6*16,s0
sqv $v07, 7*16,s0
sqv $v08, 8*16,s0
sqv $v09, 9*16,s0
sqv $v10, 10*16,s0
sqv $v11, 11*16,s0
sqv $v12, 12*16,s0
sqv $v13, 13*16,s0
sqv $v14, 14*16,s0
sqv $v15, 15*16,s0
sqv $v16, 16*16,s0
sqv $v17, 17*16,s0
sqv $v18, 18*16,s0
sqv $v19, 19*16,s0
sqv $v20, 20*16,s0
sqv $v21, 21*16,s0
sqv $v22, 22*16,s0
sqv $v23, 23*16,s0
sqv $v24, 24*16,s0
sqv $v25, 25*16,s0
sqv $v26, 26*16,s0
sqv $v27, 27*16,s0
sqv $v28, 28*16,s0
sqv $v29, 29*16,s0
sqv $v30, 30*16,s0
sqv $v31, 31*16,s0
vsar $v00, COP2_ACC_HI
vsar $v01, COP2_ACC_MD
vsar $v02, COP2_ACC_LO
sqv $v00, 32*16,s0
sqv $v01, 33*16,s0
sqv $v02, 34*16,s0
add s0, 35*16
mfc0 t0, $0
mfc0 t1, $1
mfc0 t2, $2
mfc0 t3, $3
mfc0 t4, $4
mfc0 t5, $5
mfc0 t6, $6
mfc0 t7, $7
sw t0, 0*4(s0)
sw t1, 1*4(s0)
sw t2, 2*4(s0)
sw t3, 3*4(s0)
sw t4, 4*4(s0)
sw t5, 5*4(s0)
sw t6, 6*4(s0)
sw t7, 7*4(s0)
mfc0 t0, $8
mfc0 t1, $9
mfc0 t2, $10
mfc0 t3, $11
mfc0 t4, $12
mfc0 t5, $13
mfc0 t6, $14
mfc0 t7, $15
sw t0, 8*4(s0)
sw t1, 9*4(s0)
sw t2, 10*4(s0)
sw t3, 11*4(s0)
sw t4, 12*4(s0)
sw t5, 13*4(s0)
sw t6, 14*4(s0)
sw t7, 15*4(s0)
add s0, 16*4
cfc2 t0, $0
cfc2 t1, $1
cfc2 t2, $2
sw t0, 0*4(s0)
sw t1, 1*4(s0)
sw t2, 2*4(s0)
break
|
nopjne/DaisyDrive64 | 6,396 | external/libdragon/src/regs.S | /*
* regs.S -- standard MIPS register names.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* Standard MIPS register names: */
#define zero $0
#define z0 $0
#define v0 $2
#define v1 $3
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define k0 $26 /* kernel private register 0 */
#define k1 $27 /* kernel private register 1 */
#define gp $28 /* global data pointer */
#define sp $29 /* stack-pointer */
#define fp $30 /* frame-pointer */
#define ra $31 /* return address */
#define pc $pc /* pc, used on mips16 */
#define fp0 $f0
#define fp1 $f1
/* Useful memory constants: */
#define K0BASE 0x80000000
#ifndef __mips64
#define K1BASE 0xA0000000
#define K0BASE_ADDR ((char *)K0BASE)
#define K1BASE_ADDR ((char *)K1BASE)
#else
#define K1BASE 0xFFFFFFFFA0000000LL
#define K0BASE_ADDR ((char *)0xFFFFFFFF80000000LL)
#define K1BASE_ADDR ((char *)K1BASE)
#endif
#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
/* Standard Co-Processor 0 registers */
#define C0_COUNT $9 /* Timer Count Register */
#define C0_COMPARE $11 /* Timer Compare Register */
#define C0_SR $12 /* Status Register */
#define C0_CAUSE $13 /* last exception description */
#define C0_EPC $14 /* Exception error address */
#define C0_PRID $15 /* Processor Revision ID */
#define C0_CONFIG $16 /* CPU configuration */
/* Standard Processor Revision ID Register field offsets */
#define PR_IMP 8
/* Standard Config Register field offsets */
#define CR_DB 4
#define CR_IB 5
#define CR_DC 6 /* NOTE v4121 semantics != 43,5xxx semantics */
#define CR_IC 9 /* NOTE v4121 semantics != 43,5xxx semantics */
#define CR_SC 17
#define CR_SS 20
#define CR_SB 22
/* Standard Status Register bitmasks: */
#define SR_CU1 0x20000000 /* Mark CP1 as usable */
#define SR_FR 0x04000000 /* Enable MIPS III FP registers */
#define SR_BEV 0x00400000 /* Controls location of exception vectors */
#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */
#define SR_KX 0x00000080 /* Kernel extended addressing enabled */
#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
#define SR_UX 0x00000020 /* User extended addressing enabled */
#define SR_ERL 0x00000004 /* Error level */
#define SR_EXL 0x00000002 /* Exception level */
#define SR_IE 0x00000001 /* Interrupts enabled */
/* Standard Cause Register bitmasks: */
#define CAUSE_EXC_MASK (0x1F << 2)
#define CAUSE_EXC_SYSCALL (8 << 2)
#define CAUSE_EXC_BREAKPOINT (9 << 2)
#define CAUSE_EXC_COPROCESSOR (11 << 2)
/* Standard (R4000) cache operations. Taken from "MIPS R4000
Microprocessor User's Manual" 2nd edition: */
#define CACHE_I (0) /* primary instruction */
#define CACHE_D (1) /* primary data */
#define CACHE_SI (2) /* secondary instruction */
#define CACHE_SD (3) /* secondary data (or combined instruction/data) */
#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
#define INDEX_LOAD_TAG (1)
#define INDEX_STORE_TAG (2)
#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */
#define HIT_INVALIDATE (4)
#define CACHE_FILL (5) /* CACHE_I only */
#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */
#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */
#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */
#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
/* Individual cache operations: */
#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
/*> EOF regs.S <*/
|
nopjne/DaisyDrive64 | 10,216 | external/libdragon/src/inthandler.S | /*
Simple interrupt handler, hands off MIPS interrupts to higher level processes.
Based on INITS.inc from Neon64.
It is not reentrant, so interrupts are disabled for the duration.
Safe for doing most things, including FPU operations, within handlers.
*/
#include "regs.S"
.align 5
inthandler:
.global inthandler
.set noat
.set noreorder
# The exception stack contains a dump of all GPRs/FPRs. This requires 544 bytes.
# On top of that, we need 32 bytes of empty space at offset 0-31, because
# that is required by MIPS ABI when calling C functions (it's a space called
# "argument slots" -- even if the function takes no arguments, or are only passed in
# registers, the ABI requires reserving that space and called functions might
# use it to store local variables).
# So we keep 0-31 empty, and we start saving GPRs from 32, and then FPR. See
# the other macros to see the actual layout.
#
# *NOTE*: this layout is also exposed in C via regblock_t in exception.h
# Please keep in sync!
#define EXC_STACK_SIZE (544+32)
#define STACK_GPR 32
#define STACK_HI (STACK_GPR+(32*8))
#define STACK_LO (STACK_HI+8)
#define STACK_SR (STACK_LO+8)
#define STACK_CR (STACK_SR+4)
#define STACK_EPC (STACK_CR+4)
#define STACK_FC31 (STACK_EPC+4)
#define STACK_FPR (STACK_FC31+4)
addiu sp, -EXC_STACK_SIZE
# Save caller-saved GPRs only. These are the only
# ones required to call a C function from assembly, as the
# others (callee-saved) would be preserved by the function
# itself, if modified.
sd $1, (STACK_GPR+ 1*8)(sp) # AT
.set at
sd $2, (STACK_GPR+ 2*8)(sp) # V0
sd $3, (STACK_GPR+ 3*8)(sp) # V1
sd $4, (STACK_GPR+ 4*8)(sp) # A0
sd $5, (STACK_GPR+ 5*8)(sp) # A1
sd $6, (STACK_GPR+ 6*8)(sp) # A2
sd $7, (STACK_GPR+ 7*8)(sp) # A3
sd $8, (STACK_GPR+ 8*8)(sp) # T0
sd $9, (STACK_GPR+ 9*8)(sp) # T1
sd $10,(STACK_GPR+10*8)(sp) # T2
sd $11,(STACK_GPR+11*8)(sp) # T3
sd $12,(STACK_GPR+12*8)(sp) # T4
sd $13,(STACK_GPR+13*8)(sp) # T5
sd $14,(STACK_GPR+14*8)(sp) # T6
sd $15,(STACK_GPR+15*8)(sp) # T7
sd $24,(STACK_GPR+24*8)(sp) # T8
sd $25,(STACK_GPR+25*8)(sp) # T9
sd $31,(STACK_GPR+31*8)(sp) # RA
mflo k0
mfhi k1
sd k0,STACK_LO(sp)
sd k1,STACK_HI(sp)
mfc0 k0, C0_EPC
mfc0 k1, C0_SR
sw k0, STACK_EPC(sp)
sw k1, STACK_SR(sp)
# Since all critical information about current exception has been saved,
# we can now turn off EXL. This allows a reentrant exception to save its
# own full context for operating. At the same time, it is better to keep
# interrupts disabled so that we don't risk triggering recursive interrupts,
# so disable IE as well.
and k1, ~(SR_IE | SR_EXL)
mtc0 k1, C0_SR
# WARNING: it is now possible to trigger reentrant exceptions (and not only
# crashing one. Avoid using k0/k1 from now on, as they would get corrupted
# by a reentrant exception.
#define cause t8
mfc0 cause, C0_CAUSE
sw cause, STACK_CR(sp)
andi t0, cause, 0xff
beqz t0, interrupt
nop
exception:
# This is an exception, not an interrupt. We want to save the full processor
# state in the exception frame, so all registers including FPU regs.
# Make sure FPU is activated in this context. It could be deactivated if
# this exception happened within an interrupt (where FPU is disabled by default).
mfc0 t0, C0_SR
or t0, SR_CU1
mtc0 t0, C0_SR
# Save the callee-saved FPU regs
jal save_fpu_regs
move a0, sp
# Save all the CPU+FPU caller-saved regs, which are normally
# not saved for an interrupt.
jal finalize_exception_frame
nop
# Check the exception type
andi t0, cause, CAUSE_EXC_MASK
bne t0, CAUSE_EXC_COPROCESSOR, critical_exception
nop
exception_coprocessor:
# Extract CE bits (28..29) from CR
srl t0, cause, 28
andi t0, 3
# If == 1 (COP1), it is an FPU exception
bne t0, 1, critical_exception
nop
exception_coprocessor_fpu:
# FPU exception. This happened because of the use of FPU in an interrupt handler,
# where it is disabled by default. We must save the full FPU context,
# reactivate the FPU, and then return from exception, so that the FPU instruction
# is executed again and this time it will work.
# Make sure that FPU will also be enabled when we exit this exception
lw t0, STACK_SR(sp)
or t0, SR_CU1
sw t0, STACK_SR(sp)
# Save the FPU registers into the *underlying* interrupt context.
# That is, we want to make sure that they get restored when the
# underlying interrupt exits.
jal save_fpu_regs
lw a0, interrupt_exception_frame
# OK we are done. We can now exit the exception
j end_interrupt
nop
critical_exception:
/* Exception not specially handled. */
addiu a0, sp, 32
jal __onCriticalException
nop
j end_interrupt
nop
interrupt:
# This is an interrupt.
# First of all, disable FPU coprocessor so that we can avoid saving FPU
# registers altogether.
mfc0 t0, C0_SR
and t0, ~SR_CU1
mtc0 t0, C0_SR
# If a FPU instruction is executed during the interrupt handler, a nested
# exception will trigger. The nested handler will enable the FPU and save
# the FPU registers into the interrupt exception frame. To do so, it needs
# to know *where* the interrupt exception frame is. That is, we need
# to store the current stack pointer somewhere.
# Notice that interrupts cannot be reentrant (only exceptions are), so
# a single variable will suffice.
sw sp, interrupt_exception_frame
/* check for "pre-NMI" (reset) */
andi t0, cause, 0x1000
beqz t0, notprenmi
nop
/* handle reset */
jal __onResetException
addiu a0, sp, 32
# There is no way to ack the pre-NMI interrupt, so it will
# stay pending in CR. Let's disable it in SR to avoid
# looping here. If another unrelated interrupt triggers,
# CR will still have 0x1000 set, but __onResetException will
# do nothing after the first call.
li t0, ~0x1000
lw t1, STACK_SR(sp)
and t1, t0
sw t1, STACK_SR(sp)
# Reload cause register (might be reused by C code) and test for other interrupts
lw cause, STACK_CR(sp)
notprenmi:
/* check for count=compare */
and t0, cause, 0x8000
beqz t0,notcount
nop
/* Writing C0_COMPARE acknowledges the timer interrupt (clear the interrupt
bit in C0_CAUSE, otherwise the interrupt would retrigger). We write
the current value so that we don't destroy it in case it's needed. */
mfc0 t0,C0_COMPARE
mtc0 t0,C0_COMPARE
/* handle timer interrupt */
jal __TI_handler
nop
# Reload cause register (might be reused by C code) and test for other interrupts
lw cause, STACK_CR(sp)
notcount:
and t0, cause, 0x800
beqz t0, notcart
nop
/* handle CART interrupt */
jal __CART_handler
nop
# Reload cause register (might be reused by C code) and test for other interrupts
lw cause, STACK_CR(sp)
notcart:
/* pass anything else along to MI (RCP) handler */
jal __MI_handler
addiu a0, sp, 32
# No more interrupts to process, we can exit
# (fallthrough)
end_interrupt:
mfc0 t0, C0_SR
and t0, SR_CU1
beqz t0, end_interrupt_gpr
nop
ldc1 $f0, (STACK_FPR+ 0*8)(sp)
ldc1 $f1, (STACK_FPR+ 1*8)(sp)
ldc1 $f2, (STACK_FPR+ 2*8)(sp)
ldc1 $f3, (STACK_FPR+ 3*8)(sp)
ldc1 $f4, (STACK_FPR+ 4*8)(sp)
ldc1 $f5, (STACK_FPR+ 5*8)(sp)
ldc1 $f6, (STACK_FPR+ 6*8)(sp)
ldc1 $f7, (STACK_FPR+ 7*8)(sp)
ldc1 $f8, (STACK_FPR+ 8*8)(sp)
ldc1 $f9, (STACK_FPR+ 9*8)(sp)
ldc1 $f10,(STACK_FPR+10*8)(sp)
ldc1 $f11,(STACK_FPR+11*8)(sp)
ldc1 $f12,(STACK_FPR+12*8)(sp)
ldc1 $f13,(STACK_FPR+13*8)(sp)
ldc1 $f14,(STACK_FPR+14*8)(sp)
ldc1 $f15,(STACK_FPR+15*8)(sp)
ldc1 $f16,(STACK_FPR+16*8)(sp)
ldc1 $f17,(STACK_FPR+17*8)(sp)
ldc1 $f18,(STACK_FPR+18*8)(sp)
ldc1 $f19,(STACK_FPR+19*8)(sp)
lw t0, STACK_FC31(sp)
ctc1 t0, $f31
end_interrupt_gpr:
# Restore SR. This also disables reentrant exceptions by
# restoring the EXL bit into SR
.set noat
lw t0, STACK_SR(sp)
mtc0 t0, C0_SR
ld t0, STACK_LO(sp)
ld t1, STACK_HI(sp)
lw t2, STACK_EPC(sp)
mtlo t0
mthi t1
mtc0 t2, C0_EPC
/* restore GPRs */
ld $1,(STACK_GPR + 1*8)(sp)
ld $2,(STACK_GPR + 2*8)(sp)
ld $3,(STACK_GPR + 3*8)(sp)
ld $4,(STACK_GPR + 4*8)(sp)
ld $5,(STACK_GPR + 5*8)(sp)
ld $6,(STACK_GPR + 6*8)(sp)
ld $7,(STACK_GPR + 7*8)(sp)
ld $8,(STACK_GPR + 8*8)(sp)
ld $9,(STACK_GPR + 9*8)(sp)
ld $10,(STACK_GPR+10*8)(sp)
ld $11,(STACK_GPR+11*8)(sp)
ld $12,(STACK_GPR+12*8)(sp)
ld $13,(STACK_GPR+13*8)(sp)
ld $14,(STACK_GPR+14*8)(sp)
ld $15,(STACK_GPR+15*8)(sp)
ld $24,(STACK_GPR+24*8)(sp)
ld $25,(STACK_GPR+25*8)(sp)
ld $31,(STACK_GPR+31*8)(sp)
addiu sp, EXC_STACK_SIZE
eret
.align 5
finalize_exception_frame:
sd $16,(STACK_GPR+16*8)(sp) # S0
sd $17,(STACK_GPR+17*8)(sp) # S1
sd $18,(STACK_GPR+18*8)(sp) # S2
sd $19,(STACK_GPR+19*8)(sp) # S3
sd $20,(STACK_GPR+20*8)(sp) # S4
sd $21,(STACK_GPR+21*8)(sp) # S5
sd $22,(STACK_GPR+22*8)(sp) # S6
sd $23,(STACK_GPR+23*8)(sp) # S7
sd $28,(STACK_GPR+28*8)(sp) # GP
# SP has been modified to make space for the exception frame,
# but we want to save the previous value in the exception frame itself.
addiu $1, sp, EXC_STACK_SIZE
sd $1, (STACK_GPR+29*8)(sp) # SP
sd $30,(STACK_GPR+30*8)(sp) # FP
sdc1 $f20,(STACK_FPR+20*8)(sp)
sdc1 $f21,(STACK_FPR+21*8)(sp)
sdc1 $f22,(STACK_FPR+22*8)(sp)
sdc1 $f23,(STACK_FPR+23*8)(sp)
sdc1 $f24,(STACK_FPR+24*8)(sp)
sdc1 $f25,(STACK_FPR+25*8)(sp)
sdc1 $f26,(STACK_FPR+26*8)(sp)
sdc1 $f27,(STACK_FPR+27*8)(sp)
sdc1 $f28,(STACK_FPR+28*8)(sp)
sdc1 $f29,(STACK_FPR+29*8)(sp)
sdc1 $f30,(STACK_FPR+30*8)(sp)
sdc1 $f31,(STACK_FPR+31*8)(sp)
jr ra
nop
.align 5
save_fpu_regs:
cfc1 $1, $f31
sw $1, STACK_FC31(a0)
sdc1 $f0, (STACK_FPR+ 0*8)(a0)
sdc1 $f1, (STACK_FPR+ 1*8)(a0)
sdc1 $f2, (STACK_FPR+ 2*8)(a0)
sdc1 $f3, (STACK_FPR+ 3*8)(a0)
sdc1 $f4, (STACK_FPR+ 4*8)(a0)
sdc1 $f5, (STACK_FPR+ 5*8)(a0)
sdc1 $f6, (STACK_FPR+ 6*8)(a0)
sdc1 $f7, (STACK_FPR+ 7*8)(a0)
sdc1 $f8, (STACK_FPR+ 8*8)(a0)
sdc1 $f9, (STACK_FPR+ 9*8)(a0)
sdc1 $f10,(STACK_FPR+10*8)(a0)
sdc1 $f11,(STACK_FPR+11*8)(a0)
sdc1 $f12,(STACK_FPR+12*8)(a0)
sdc1 $f13,(STACK_FPR+13*8)(a0)
sdc1 $f14,(STACK_FPR+14*8)(a0)
sdc1 $f15,(STACK_FPR+15*8)(a0)
sdc1 $f16,(STACK_FPR+16*8)(a0)
sdc1 $f17,(STACK_FPR+17*8)(a0)
sdc1 $f18,(STACK_FPR+18*8)(a0)
sdc1 $f19,(STACK_FPR+19*8)(a0)
jr ra
nop
.section .bss
.align 8
.lcomm interrupt_exception_frame, 4
|
nopjne/DaisyDrive64 | 2,646 | external/libdragon/src/entrypoint.S | /*
* N64 init code for GNU as
*/
#include "regs.S"
.set noreorder
.section .boot
.global _start
_start:
lw t0, 0x80000318 /* memory size */
/* Check whether we are running on iQue or N64. Use the MI version register
which has LSB set to 0xB0 on iQue. We assume 0xBn was meant for BBPlayer.
Notice that we want this test to be hard for emulators to pass by mistake,
so checking for a specific value while reading seems solid enough. */
lw t1, 0xA4300004
andi t1, 0xF0
bne t1, 0xB0, set_sp
li fp, 0 /* fp=0 -> vanilla N64 */
/* In iQue player, memory allocated to game can be configured and it appears
in 0x80000318. On the other hand, the top 8Mb of RDRAM is reserved to
savegames. So avoid putting the stack there, capping the size to 0x7C0000.
See also get_memory_size. */
li fp, 1 /* fp=1 -> iQue player */
li t1, 0x800000
blt t0, t1, set_sp
nop
li t0, 0x7C0000
set_sp:
li t1, 0x7FFFFFF0
addu sp,t0,t1 /* init stack */
la gp, _gp /* init data pointer */
li v0, 8
sw v0,(0xbfc007fc) /* magic N64 hardware init */
/* a bit from libgloss so we start at a known state */
li v0,SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0,C0_SR
mtc0 $0,C0_CAUSE
/* copy code and data via DMA */
la a0, __text_start
la a1, __data_end
la t0, __libdragon_text_start
subu a2, a0, t0 /* skip over .boot section */
addu a2, 0x10001000 /* address in rom */
/* Start PI DMA transfer */
lui t0, 0xA460
sw a0, 0x00(t0)
sw a2, 0x04(t0)
sub t1, a1, a0
addi t1, -1
sw t1, 0x0C(t0)
/* fill .bss with 0s */
la a0, __bss_start
or a0, 0x20000000
la a1, __bss_end
or a1, 0x20000000
bss_init:
sd $0,(a0)
addiu a0,8
bltu a0,a1, bss_init
nop
/* Wait for DMA transfer to be finished */
lui t0, 0xA460
wait_dma_end:
lw t1, 0x10(t0)
andi t1, 3
bnez t1, wait_dma_end
nop
/* Store the bbplayer flag now that BSS has been cleared */
sw fp, __bbplayer
/* load interrupt vector */
la t0,intvector
la t1,0xa0000000
la t2,4
loadintvectorloop:
lw t3,(t0)
sw t3,0(t1)
sw t3,0x80(t1)
sw t3,0x100(t1)
sw t3,0x180(t1)
/* sync */
cache HIT_INVALIDATE_I,0(t1)
cache HIT_INVALIDATE_I,0x80(t1)
cache HIT_INVALIDATE_I,0x100(t1)
cache HIT_INVALIDATE_I,0x180(t1)
addi t0,4
addi t1,4
addiu t2,-1
bnez t2,loadintvectorloop
nop
la t0, debug_assert_func /* install assert function in system.c */
la t1, __assert_func_ptr
sw t0, 0(t1)
jal __do_global_ctors /* call global constructors */
nop
li a0, 0
jal main /* call main app */
li a1, 0
deadloop:
j deadloop
nop
intvector:
la k1,inthandler
jr k1
nop
.section .code
|
nopjne/DaisyDrive64 | 3,109 | external/libdragon/examples/rspqdemo/rsp_vec.S | #include <rsp_queue.inc>
#define SLOT_SIZE 0x20
#define NUM_SLOTS 0x20
.set noreorder
.set at
.data
RSPQ_BeginOverlayHeader
RSPQ_DefineCommand VecCmd_Load, 8
RSPQ_DefineCommand VecCmd_Store, 8
RSPQ_DefineCommand VecCmd_Transform, 8
RSPQ_EndOverlayHeader
RSPQ_BeginSavedState
.align 4
VEC_SLOTS: .ds.b NUM_SLOTS * SLOT_SIZE
RSPQ_EndSavedState
.text
VecCmd_Load:
j Vec_DMA
li t2, DMA_IN
VecCmd_Store:
li t2, DMA_OUT
Vec_DMA:
andi s4, a1, 0xFFF0
addiu s4, %lo(VEC_SLOTS)
srl t0, a1, 16
j DMAExec
move s0, a0
VecCmd_Transform:
#define trans_mtx t0
#define trans_vec t1
#define trans_out t2
#define m0i $v01
#define m0f $v02
#define m1i $v03
#define m1f $v04
#define m2i $v05
#define m2f $v06
#define m3i $v07
#define m3f $v08
#define v01i $v09
#define v01f $v10
#define o01i $v13
#define o01f $v14
#define vtemp $v17
srl trans_mtx, a1, 16
andi trans_mtx, 0xFF0
andi trans_vec, a1, 0xFF0
andi trans_out, a0, 0xFF0
addiu trans_mtx, %lo(VEC_SLOTS)
addiu trans_vec, %lo(VEC_SLOTS)
addiu trans_out, %lo(VEC_SLOTS)
# Load matrix columns, repeating each column twice in a register
ldv m0i,0x0, 0x00,trans_mtx
ldv m0i,0x8, 0x00,trans_mtx
ldv m0f,0x0, 0x10,trans_mtx
ldv m0f,0x8, 0x10,trans_mtx
ldv m1i,0x0, 0x08,trans_mtx
ldv m1i,0x8, 0x08,trans_mtx
ldv m1f,0x0, 0x18,trans_mtx
ldv m1f,0x8, 0x18,trans_mtx
ldv m2i,0x0, 0x20,trans_mtx
ldv m2i,0x8, 0x20,trans_mtx
ldv m2f,0x0, 0x30,trans_mtx
ldv m2f,0x8, 0x30,trans_mtx
ldv m3i,0x0, 0x28,trans_mtx
ldv m3i,0x8, 0x28,trans_mtx
ldv m3f,0x0, 0x38,trans_mtx
ldv m3f,0x8, 0x38,trans_mtx
# Load vector (a slot always contains two vectors)
lqv v01i,0x0, 0x00,trans_vec
lqv v01f,0x0, 0x10,trans_vec
# Perform transformation by computing the dot products of the matrix rows with the vector.
# We take advantage of the accumulator by letting it perform the addition automatically
# with each multiplication.
vmudl vtemp, m0f, v01f,e(0h) # m(x,0) * v(0)
vmadm vtemp, m0i, v01f,e(0h)
vmadn vtemp, m0f, v01i,e(0h)
vmadh vtemp, m0i, v01i,e(0h)
vmadl vtemp, m1f, v01f,e(1h) # + m(x,1) * v(1)
vmadm vtemp, m1i, v01f,e(1h)
vmadn vtemp, m1f, v01i,e(1h)
vmadh vtemp, m1i, v01i,e(1h)
vmadl vtemp, m2f, v01f,e(2h) # + m(x,2) * v(2)
vmadm vtemp, m2i, v01f,e(2h)
vmadn vtemp, m2f, v01i,e(2h)
vmadh vtemp, m2i, v01i,e(2h)
vmadl vtemp, m3f, v01f,e(3h) # + m(x,3) * v(3)
vmadm vtemp, m3i, v01f,e(3h)
vmadn o01f, m3f, v01i,e(3h)
vmadh o01i, m3i, v01i,e(3h)
# Write result
sqv o01i,0x0, 0x00,trans_out
jr ra
sqv o01f,0x0, 0x10,trans_out
#undef trans_mtx
#undef trans_vec
#undef trans_out
#undef m0i
#undef m0f
#undef m1i
#undef m1f
#undef m2i
#undef m2f
#undef m3i
#undef m3f
#undef v01i
#undef v01f
#undef o01i
#undef o01f
#undef vtemp
|
nopjne/DaisyDrive64 | 33,791 | external/libdragon/src/audio/rsp_mixer.S | ####################################################################
#
# Libdragon RSP ucode for audio mixer
#
####################################################################
##############################################################
#
# This ucode implements a mixer, for 32 channels of digital samples,
# with per-channel resampling (mixing channels of different frequencies),
# per-channel 16-bit volume and 16-bit panning control,
# and full 16-bit stereo output with no loss of precision.
#
# The C code that drives this ucode is in mixer.c (mixer_poll).
# The input for the ucode is the channel parameters, that describe
# the playback configuration and where to find the actual samples
# in RDRAM.
#
# The ucode fetches the samples from RDRAM via DMA, resample them
# (that is, operating a frequency change using a linear interpolation),
# apply volume/panning, and mix them together. The final output
# samples are sent to RDRAM via DMA.
#
# Given the limited space in DMEM, this happens in loops where a small
# amount of samples per each channel is processed (MAX_SAMPLES_PER_LOOP).
#
# RESAMPLING
# **********
#
# Resampling is implemented by the function UpdateAndFetch. As the name
# describes, this functions fetches samples from RDRAM via DMA into a
# temporary buffer in DMEM (DMEM_SAMPLE_CACHE), and then resample them
# into a buffer called CHANNEL_BUFFER, which holds the resampled samples
# for all channels.
#
# Resampling means doing a linear interpolation on the index used to go
# through the input sample, according to the resampling frequency. The
# channel configuration already contains a fixed-point "step" value for
# each channel, that is used as increment in the loop. For instance, if
# the step is 2, it means that every other sample will be skipped, thus
# achieving a 0.5x resampling (= playing a 88Khz sample on a 44Khz output).
#
# Resampling requires thus copying one sample at at time from DMEM_SAMPLE_CACHE
# into CHANNEL_BUFFER, with a fixed-point increment. This is actually
# quite slow and cannot be vectorized; it is by far the slowest part of
# the whole ucode. To achieve reasonable performance, the inner resampling
# loop has been painstakingly optimized by having specific version for 8-bit
# and 16-bit input samples, and with manual loop unrolling to increase
# performance. The final version takes 4,88 cycles/sample for 8-bit channels,
# and 5,88 cycles/samples for 16-bit channels. TODO: handle also stereo
# waveforms spanning 2 channels. This would allow the mixer to support
# interleaved stereo waveforms.
#
# The DMEM_SAMPLE_CACHE area is a temporary 64-byte buffer that is used to
# hold the original samples fetched via DMA (before resampling). Since the
# ucode doesn't know how many samples will be needed (the exact number
# depends on the resampling step and would require a division to be
# calculated), the DMA always fills this area in full, so we define it
# small-ish to avoid wasting too much time fetching useless samples. On
# the other hand, in the rare cases in which there is a high resampling
# step, multiple DMA transfers might be needed.
#
#
# MIXER
# *****
#
# The mixer is actually made of two cores: one that mixes up to 32 channels
# and runs at 16 cycles/sample, and one that mixes up to 8 channels
# and runs at 11 cycles/sample. The 8 channels core is only
# 32% faster because the 32 channels core better exploit vector
# instruction parallelism.
#
# The 8-channel mixer is automatically selected whenever no more than 8
# channels are configured. TODO: this could be improved by actually looking
# at channel status; a channel might be configured but be currently turned
# off or otherwise silent.
#
# The mixer fetches the samples from CHANNEL_BUFFER, apply volume and
# panning, mix them, and write the output stream in a buffer called
# OUTPUT_AREA. The main loop will then DMA this buffer back to RDRAM.
#
# The mixer cores also implement a one-tap volume filter to
# smooth out sudden volume changes to avoid clicks in the output.
# This is common for instance with XM modules, and in fact most
# XM players implement filters to achieve a similar effect.
# To avoid taxing too much the core, the filter runs at 1/8th
# of the output rate. With the filter turned on, the 32-channel
# core runs at 18 cycles/samples, while the 8-channel core
# runs at 11.5 cycles/samples. The filter can be turned off at compile
# time (VOLUME_FILTER). TODO: make this a runtime option.
#
# Even with the filter overhead, the mixer is still very fast.
# For 32 channel mixing at 44100Hz, it uses only the 1.65% of the
# available frame time, while 8-channel mixing takes 1.10%. In
# general, resampling takes much more time than mixing. Because of this,
# the volume filter is on by default.
#
####################################################################
#
# Glossary:
# * Sample: a single 8-bit / 16-bit amplitude value
# * Waveform: a sequence of samples that can be played (eg: a WAV file)
#
####################################################################
#include <rsp_queue.inc>
.set noreorder
.set at
# Maximum number of channels supported by this ucode. You can't really increase
# this without modifying the code.
#define MAX_CHANNELS 32
# Activate one-tap filter on volume changes, to smooth out sudden changes
# that can cause clicks.
#define VOLUME_FILTER 1
# How many sample to process in a mixing loop. This can be tuned to use more/less
# DMEM. Obviously, more samples per loop is better for performance.
#define MAX_SAMPLES_PER_LOOP 32
# Number of fractional bits used in the fixed point numbers that specify
# the waveform position, step, length and loop length.
# NOTE: This must be the same of MIXER_FX32_FRAC in mixer.c.
#define WAVEFORM_POS_FRAC_BITS 12
# Waveform flags. Keep these in sync with mixer.c
#define CH_FLAGS_16BIT (1<<2)
#define CH_FLAGS_STEREO (1<<3)
#define MAX_CHANNELS_VOFF (MAX_CHANNELS*2)
################################
# Global register allocations, valid in the whole ucode
################################
#define v_zero $v00
# Current volume left/right for each channel. This is the volume
# that's being ramped up to the final volume.
#define v_xvol_l_0 $v13
#define v_xvol_r_0 $v14
#define v_xvol_l_1 $v15
#define v_xvol_r_1 $v16
#define v_xvol_l_2 $v17
#define v_xvol_r_2 $v18
#define v_xvol_l_3 $v19
#define v_xvol_r_3 $v20
# Final volume left/right (basic volume * panning * global volume),
# pre-multiplied by 1-alpha.
#define v_chvol_l_0 $v21
#define v_chvol_r_0 $v22
#define v_chvol_l_1 $v23
#define v_chvol_r_1 $v24
#define v_chvol_l_2 $v25
#define v_chvol_r_2 $v26
#define v_chvol_l_3 $v27
#define v_chvol_r_3 $v28
# Shift registers
#define v_shift8 $v29
#define v_shift $v30
# Misc constants
#define v_const1 $v31
#define k_0000 v_zero
#define k_8000 v_shift8.e0
.data
RSPQ_BeginOverlayHeader
RSPQ_DefineCommand command_exec, 16
RSPQ_EndOverlayHeader
############################################################################
# Misc constants
.align 4
VCONST_1:
.half 0x7FFF
.half 0xe076 # (0.9837**8) fixed 0.16
.half 0x1f8a # 1-(0.9837**8) fixed 0.16
#define k_ffff v_const1.e0
#define k_alpha v_const1.e1
#define k_1malpha v_const1.e2
vsll_data
vsll8_data
.align 4
BANNER0: .ascii "Dragon RSP Audio"
BANNER1: .ascii " Coded by Rasky "
RSPQ_BeginSavedState
# Current volume state for each channel. This might differ from CHANNEL_VOLUMES
# when the volume filter is turned on: this is the actual current value that
# is being interpolated to CHANNEL_VOLUMES, which is the requested target
# volume to reach.
.align 4
XVOL_L: .dcb.w MAX_CHANNELS
XVOL_R: .dcb.w MAX_CHANNELS
RSPQ_EndSavedState
.bss
############################################################################
# UCODE INPUT DATA
############################################################################
# Output RDRAM buffer where to store mixed samples (16-bit, stereo)
OUTPUT_RDRAM: .long 0
# Global volume of playback
GLOBAL_VOLUME: .half 0
# Number of samples to resample/mix on each channel
NUM_SAMPLES: .half 0
# Number of configured channels
NUM_CHANNELS: .half 0
# Requested volumes for each channel. If VOLUME_FILTER is on, these are the
# values requested by the user, but the current value for each channel might
# be different (as the filter is running).
.align 4
SETTINGS_START:
CHANNEL_VOLUMES_L: .dcb.w MAX_CHANNELS
CHANNEL_VOLUMES_R: .dcb.w MAX_CHANNELS
# Array of structures rsp_mixer_channel_s. See mixer.c. 6 words for each
# channel with the following content:
#
# 0: pos: absolute waveform position (as fixed point, WAVEFORM_POS_FRAC_BITS)
# 1: step: resampling increment of position for each output sample (fixed point)
# 2: len: length of the waveform (fixed point)
# 3: loop_len: length of the loop from the end of the waveform (or 0 if no loop)
# 4: ptr: pointer to the beginning of the waveform
# 5: flags: channel flags (see CH_FLAGS_ macros in mixer.c)
#
.align 4
WAVEFORM_SETTINGS: .dcb.l (6*MAX_CHANNELS)
SETTINGS_END:
# Temporary cache of samples fetched by DMA. Notice that this must be
# less or equal than MIXER_LOOP_OVERREAD (mixer.c), because the
# RSP will over-read up to this amount of bytes after waveform's end.
.align 3
#define SAMPLE_CACHE_SIZE 64
DMEM_SAMPLE_CACHE: .dcb.b SAMPLE_CACHE_SIZE
# CHANNEL_BUFFER holds the resampled samples for all the channels.
# Samples of different channels are interleaved, so that they can
# be mixed with vector instructions.
.align 4 # for human visual debugging
CHANNEL_BUFFER: .dcb.w (MAX_SAMPLES_PER_LOOP * MAX_CHANNELS)
# OUTPUT_AREA holds the final mixed stereo samples, that will be copied
# to RDRAM via DMA.
.align 4 # for human visual debugging, 3 would be sufficient (for DMA)
OUTPUT_AREA: .dcb.w MAX_SAMPLES_PER_LOOP*2
.text
# Number of samples that will be processed in the current loop.
#define num_samples k1
command_exec:
setup_vsll v_shift
setup_vsll8 v_shift8
#define samples_left t4
#define outptr s8
vxor v_zero, v_zero, v_zero
li t0, %lo(VCONST_1)
lqv v_const1, 0,t0
# Extract command parameters
andi a0, 0xFFFF
sh a0, %lo(GLOBAL_VOLUME)
srl t1, a1, 16
sh t1, %lo(NUM_SAMPLES)
andi a1, 0xFFFF
sh a1, %lo(NUM_CHANNELS)
lw a2, CMD_ADDR(0x8, 0x10)
sw a2, %lo(OUTPUT_RDRAM)
# Load settings
jal DMASettings
li t2, DMA_IN
jal SetupMixer
nop
MainLoop:
lh samples_left, %lo(NUM_SAMPLES)
beqz samples_left, End
# Fetch output RDRAM pointer and set t1=1 if it's not 8-byte aligned.
# We expect the pointer to be 32-bit aligned (since it's a buffer of 16-bit
# stereo samples), but it might not be 64-bit aligned.
lw t1, %lo(OUTPUT_RDRAM)
andi t1, 7
slt t1, zero, t1
# The maximum number of samples that we want to generate
# in a single loop is MAX_SAMPLES_PER_LOOP. Subtract
# 1 from this number if RDRAM buffer is not aligned so
# that after this loop we're 8-byte aligned again.
li num_samples, MAX_SAMPLES_PER_LOOP
sub num_samples, t1
# num_samples = MIN(num_samples, MAX_SAMPLES_PER_LOOP[-1])
bgt samples_left, num_samples, CheckDMAAlignment
nop
move num_samples, samples_left
CheckDMAAlignment:
# If the output buffer is not aligned, fetch one DMA line (8 bytes)
# so that we preserve the 4 bytes that come before the buffer we were
# given (which would be overwritten by the RSP DMA).
beqz t1, DoLoop
li outptr, %lo(OUTPUT_AREA)
lw s0, %lo(OUTPUT_RDRAM)
li s4, %lo(OUTPUT_AREA)
jal DMAIn
li t0, DMA_SIZE(8,1)
addi outptr, 4
DoLoop:
# Update number of samples left, subtracting the number of samples
# that will be calculated in this loop.
sub samples_left, num_samples
sh samples_left, %lo(NUM_SAMPLES)
# Fetch the samples and do resampling
jal UpdateAndFetch
lhu k0, %lo(NUM_CHANNELS)
# Mix the samples
jal Mixer
move s4, outptr
# Update the output pointer in RDRAM for next loop.
sll t0, num_samples, 2
lw s0, %lo(OUTPUT_RDRAM)
add s1, s0, t0
sw s1, %lo(OUTPUT_RDRAM)
# DMA the output buffer into RDRAM (s0 is the output pointer before update).
# We can do the transfer in background because it will surely be finished
# by the time we start filling the output area again.
addi t0, -1
jal DMAOutAsync
li s4, %lo(OUTPUT_AREA)
j MainLoop
nop
End:
# Store the current channel volume in DMEM (permanent state)
jal EndMixer
nop
jal DMASettings
li t2, DMA_OUT_ASYNC
# Wait for the last out transfer to be finished
jal_and_j DMAWaitIdle, RSPQ_Loop
#undef samples_left
#undef outptr
###############################################################
# DMASettings - Load/save the settings via DMA.
#
# Arguments:
# t2: DMA_* flag for DMAExec
###############################################################
.func DMASettings
DMASettings:
# Save settings
lw s0, CMD_ADDR(0xC, 0x10)
li s4, %lo(SETTINGS_START)
j DMAExec
li t0, DMA_SIZE((SETTINGS_END - SETTINGS_START), 1)
.endfunc
###############################################################
# UpdateAndFetch - Resampling loop.
#
# This function goes through all active channels, fetch
# the samples of current waveforms via DMA, and apply the
# required resampling (frequency change) for a specified
# number of ticks (output samples).
#
# All channels parameters are fetched from WAVEFORM_SETTINGS.
#
# Arguments:
#
# k0: number of active channels
#
# Global state:
#
# num_samples: number of ticks to resample
#
###############################################################
#define ticks t3
#define waveform_ptr s1
#define wv_pos t4
#define wv_step t5
#define wv_len t6
#define wv_loop_len t7
#define wv_addr t8
#define wv_dma_addr v0
#define nchan v1
#define dma_cache_end s7
#define out_ptr s5
#define wv_pos_to_dmem s6
#define wv_step_8x t2
#define is_stereo a0
#define is_16bit a1
.func UpdateAndFetch
UpdateAndFetch:
move ra2, ra
li out_ptr, %lo(CHANNEL_BUFFER)
li t0, (MAX_SAMPLES_PER_LOOP * MAX_CHANNELS * 2) / 64 - 1
ClearLoop:
sqv v_zero, 0x00,out_ptr
sqv v_zero, 0x10,out_ptr
sqv v_zero, 0x20,out_ptr
sqv v_zero, 0x30,out_ptr
addi out_ptr, 64
bnez t0, ClearLoop
addi t0, -1
li waveform_ptr, %lo(WAVEFORM_SETTINGS)
li nchan, 0
li dma_cache_end, %lo(DMEM_SAMPLE_CACHE+SAMPLE_CACHE_SIZE)
sll dma_cache_end, WAVEFORM_POS_FRAC_BITS
# main update loop: will be done once per channel.
UpdateLoop:
# Fetch waveform parameters. Notice that if the RDRAM
# address is zero, no waveform was configured in this channel,
# so we can skip directly to next channel.
lw wv_addr, 16(waveform_ptr)
beqz wv_addr, WaveLoopEpilog2
lw wv_pos, 0(waveform_ptr)
lw wv_step, 4(waveform_ptr)
lw wv_len, 8(waveform_ptr)
lw wv_loop_len, 12(waveform_ptr)
# Prepare output pointer
addi out_ptr, nchan, %lo(CHANNEL_BUFFER)
add out_ptr, nchan
move ticks, num_samples
# Flags: isolate 16-bit flag (bit 2) and stereo flags (bit 3)
lw t0, 20(waveform_ptr)
andi is_stereo, t0, CH_FLAGS_STEREO
andi is_16bit, t0, CH_FLAGS_16BIT
WaveStart:
# Check if we reached end of sample.
bltu wv_pos, wv_len, WaveDmaFetch
nop
# End of sample. Check if the waveform loops
beqz wv_loop_len, WaveLoopEpilog
nop
# Apply loop to current position and loop again (until wv_pos < wv_len).
# We need to iterate in case during a single UpdateLoop we moved wv_pos
# more than wv_loop_len bytes, so subtracting just once is not sufficient.
j WaveStart
sub wv_pos, wv_loop_len
WaveDmaFetch:
# Fetch SAMPLE_CACHE_SIZE bytes of the current waveform
# into DMEM_SAMPLE_CACHE, from the current position.
# Notice that DMA is 8-byte aligned, and DMAIn will adjust
# s4 to point to the actual byte in DMEM containing the
# first requested sample.
srl s2, wv_pos, WAVEFORM_POS_FRAC_BITS
add s0, s2, wv_addr
li s4, %lo(DMEM_SAMPLE_CACHE)
jal DMAIn
li t0, DMA_SIZE(SAMPLE_CACHE_SIZE, 1)
# Calculate an offset that converts wv_pos from a (fixed point) RDRAM
# pointer into a (fixed point) DMEM pointer. This will be used because
# the inner loop will use wv_pos adjusted to be a DMEM pointer
# rather than a RDRAM pointer, for performance.
sub wv_pos_to_dmem, s2, s4
sll wv_pos_to_dmem, WAVEFORM_POS_FRAC_BITS
# Compute wv_step_8x
sll wv_step_8x, wv_step, 3
############################################################
# His Royal Majesty The Resampling Loop.
############################################################
# This is where 80% of the RSP time is spent. Any clock
# cycle counts!
#
# We need to go through the samples fetched in DMEM and
# resample them into the output buffer (aka: copying them
# going through with specified step).
#
# For performance, this loop assumes that all samples in
# DMEM are valid (that is, they were not fetched more than
# waveform length). To make sure this is always true,
# the C code has prepared all samples with an overread
# buffer at the end (see XM_WAVEFORM_OVERREAD).
#
# The loop is available in four different versions:
# 8-bit and 16-bits, and 1x and 8x (unrolled). The unrolled
# version automatically fallbacks to the 1x version when
# required.
############################################################
# Adjust wv_pos to become a DMEM pointer, and then
# jump to the 8-bit or 16-bit resampling loop.
bnez is_stereo, WaveLoopStereo
sub wv_pos, wv_pos_to_dmem
############################################################
# Mono
############################################################
bnez is_16bit, WaveLoop16_8x
############################################################
# Mono - 8 bit
############################################################
WaveLoop8_8x:
add t0, wv_pos, wv_step_8x # check if pos+step*8 is still in the DMEM cache
bgt t0, dma_cache_end, WaveLoop8Checks
li t0, 8 # check if we need to process at least 8 samples
blt ticks, t0, WaveLoop8Checks
# Process 8 samples
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS # Get raw DMEM pointer (integer part of wv_pos)
lbu t0, 0(t0) # Fetch the sample
add wv_pos, wv_step # Update wv_pos (load cycle delay)
sb t0, (0*MAX_CHANNELS*2+0)(out_ptr) # Store the sample
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (1*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (2*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (3*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (4*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (5*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (6*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS
lbu t0, 0(t0)
add wv_pos, wv_step
sb t0, (7*MAX_CHANNELS*2+0)(out_ptr)
# Update output pointer and ticks counter, and loop.
add out_ptr, 8*MAX_CHANNELS*2
j WaveLoop8_8x
addi ticks, -8
WaveLoop8:
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS # Get the raw DMEM pointer
lbu t0, 0(t0) # Fetch the 8-bit sample
add wv_pos, wv_step # Update the pointer using the resampling step
sb t0, 0(out_ptr) # Store to output as 16-bit
addi out_ptr, MAX_CHANNELS*2 # Update output pointer
addi ticks, -1
WaveLoop8Checks:
blez ticks, WaveBeforeEpilog # Check if we're finished
slt t0, wv_pos, dma_cache_end # Loop if we've not reached the end of DMEM buffer
bnez t0, WaveLoop8
nop
j WaveStart # End of buffer: fetch some more samples
add wv_pos, wv_pos_to_dmem
############################################################
# Mono - 16 bit
############################################################
WaveLoop16_8x:
add t0, wv_pos, wv_step_8x
bgt t0, dma_cache_end, WaveLoop16Checks
li t0, 8
blt ticks, t0, WaveLoop16Checks
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (0*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (1*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (2*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (3*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (4*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (5*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (6*MAX_CHANNELS*2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, (7*MAX_CHANNELS*2)(out_ptr)
add out_ptr, 8*MAX_CHANNELS*2
j WaveLoop16_8x
addi ticks, -8
WaveLoop16:
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lhu t0, 0(t0)
add wv_pos, wv_step
sh t0, 0(out_ptr)
addi out_ptr, MAX_CHANNELS*2
addi ticks, -1
WaveLoop16Checks:
blez ticks, WaveBeforeEpilog
slt t0, wv_pos, dma_cache_end
bnez t0, WaveLoop16
nop
j WaveStart
add wv_pos, wv_pos_to_dmem
############################################################
# Stereo
############################################################
WaveLoopStereo:
bnez is_16bit, WaveLoop16_Stereo_8x
############################################################
# Stereo - 8 bit
############################################################
WaveLoop8_Stereo_8x:
add t0, wv_pos, wv_step_8x
bgt t0, dma_cache_end, WaveLoop8StereoChecks
li t0, 8
blt ticks, t0, WaveLoop8StereoChecks
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (0*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (0*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (1*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (1*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (2*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (2*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (3*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (3*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (4*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (4*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (5*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (5*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (6*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (6*MAX_CHANNELS*2+2)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, (7*MAX_CHANNELS*2+0)(out_ptr)
sb t0, (7*MAX_CHANNELS*2+2)(out_ptr)
add out_ptr, 8*MAX_CHANNELS*2
j WaveLoop8_Stereo_8x
addi ticks, -8
WaveLoop8Stereo:
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+1
sll t0, 1
lbu t1, 0(t0)
lbu t0, 1(t0)
add wv_pos, wv_step
sb t1, 0(out_ptr)
sb t0, 2(out_ptr)
addi out_ptr, MAX_CHANNELS*2
addi ticks, -1
WaveLoop8StereoChecks:
blez ticks, WaveBeforeEpilog
slt t0, wv_pos, dma_cache_end
bnez t0, WaveLoop8Stereo
nop
j WaveStart
add wv_pos, wv_pos_to_dmem
############################################################
# Stereo - 16 bit
############################################################
WaveLoop16_Stereo_8x:
add t0, wv_pos, wv_step_8x
bgt t0, dma_cache_end, WaveLoop16StereoChecks
li t0, 8
blt ticks, t0, WaveLoop16StereoChecks
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (0*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (1*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (2*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (3*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (4*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (5*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (6*MAX_CHANNELS*2+0)(out_ptr)
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, (7*MAX_CHANNELS*2+0)(out_ptr)
add out_ptr, 8*MAX_CHANNELS*2
j WaveLoop16_Stereo_8x
addi ticks, -8
WaveLoop16Stereo:
srl t0, wv_pos, WAVEFORM_POS_FRAC_BITS+2
sll t0, 2
lw t0, 0(t0)
add wv_pos, wv_step
sw t0, 0(out_ptr)
addi out_ptr, MAX_CHANNELS*2
addi ticks, -1
WaveLoop16StereoChecks:
blez ticks, WaveBeforeEpilog
slt t0, wv_pos, dma_cache_end
bnez t0, WaveLoop16Stereo
nop
j WaveStart
add wv_pos, wv_pos_to_dmem
WaveBeforeEpilog:
add wv_pos, wv_pos_to_dmem
WaveLoopEpilog:
beqz is_stereo, WaveLoopEpilog2
sw wv_pos, 0(waveform_ptr) # store updated wv_pos in DMEM
# For stereo, we need to skip 1 channel
addi nchan, 1
addi waveform_ptr, 6*4
WaveLoopEpilog2:
addi nchan, 1
bne nchan, k0, UpdateLoop
addi waveform_ptr, 6*4
jr ra2
nop
.endfunc
##############################################################
# SetupMixer: load left/right volumes for each channel
# into the global registers (v_chvol_l/r), so that they're
# available for mixing.
##############################################################
#define v_glvol $v01
.func SetupMixer
SetupMixer:
# Load global volume (into all lanes)
lh t0, %lo(GLOBAL_VOLUME)
mtc2 t0, v_glvol.e0
vor v_glvol, v_zero, v_glvol.e0
li s0, %lo(CHANNEL_VOLUMES_L)
li s1, %lo(XVOL_L)
# Load channel volumes (left / right)
lqv v_chvol_l_0, 0*MAX_CHANNELS_VOFF+0x00,s0
lqv v_chvol_l_1, 0*MAX_CHANNELS_VOFF+0x10,s0
lqv v_chvol_l_2, 0*MAX_CHANNELS_VOFF+0x20,s0
lqv v_chvol_l_3, 0*MAX_CHANNELS_VOFF+0x30,s0
lqv v_chvol_r_0, 1*MAX_CHANNELS_VOFF+0x00,s0
lqv v_chvol_r_1, 1*MAX_CHANNELS_VOFF+0x10,s0
lqv v_chvol_r_2, 1*MAX_CHANNELS_VOFF+0x20,s0
lqv v_chvol_r_3, 1*MAX_CHANNELS_VOFF+0x30,s0
# Apply global volume to obtain the final volume for each channel
vmudl v_chvol_l_0, v_chvol_l_0, v_glvol
vmudl v_chvol_r_0, v_chvol_r_0, v_glvol
vmudl v_chvol_l_1, v_chvol_l_1, v_glvol
vmudl v_chvol_r_1, v_chvol_r_1, v_glvol
vmudl v_chvol_l_2, v_chvol_l_2, v_glvol
vmudl v_chvol_r_2, v_chvol_r_2, v_glvol
vmudl v_chvol_l_3, v_chvol_l_3, v_glvol
vmudl v_chvol_r_3, v_chvol_r_3, v_glvol
#if VOLUME_FILTER
# Load actual volumes levels
lqv v_xvol_l_0, 0*MAX_CHANNELS_VOFF+0x00,s1
lqv v_xvol_l_1, 0*MAX_CHANNELS_VOFF+0x10,s1
lqv v_xvol_l_2, 0*MAX_CHANNELS_VOFF+0x20,s1
lqv v_xvol_l_3, 0*MAX_CHANNELS_VOFF+0x30,s1
lqv v_xvol_r_0, 1*MAX_CHANNELS_VOFF+0x00,s1
lqv v_xvol_r_1, 1*MAX_CHANNELS_VOFF+0x10,s1
lqv v_xvol_r_2, 1*MAX_CHANNELS_VOFF+0x20,s1
lqv v_xvol_r_3, 1*MAX_CHANNELS_VOFF+0x30,s1
#else
vor v_xvol_l_0, v_chvol_l_0, v_zero
vor v_xvol_l_1, v_chvol_l_1, v_zero
vor v_xvol_l_2, v_chvol_l_2, v_zero
vor v_xvol_l_3, v_chvol_l_3, v_zero
vor v_xvol_r_0, v_chvol_r_0, v_zero
vor v_xvol_r_1, v_chvol_r_1, v_zero
vor v_xvol_r_2, v_chvol_r_2, v_zero
vor v_xvol_r_3, v_chvol_r_3, v_zero
#endif
jr ra
nop
.endfunc
#undef v_glvol
.func EndMixer
EndMixer:
li s1, %lo(XVOL_L)
sqv v_xvol_l_0, 0*MAX_CHANNELS_VOFF+0x00,s1
sqv v_xvol_l_1, 0*MAX_CHANNELS_VOFF+0x10,s1
sqv v_xvol_l_2, 0*MAX_CHANNELS_VOFF+0x20,s1
sqv v_xvol_l_3, 0*MAX_CHANNELS_VOFF+0x30,s1
sqv v_xvol_r_0, 1*MAX_CHANNELS_VOFF+0x00,s1
sqv v_xvol_r_1, 1*MAX_CHANNELS_VOFF+0x10,s1
sqv v_xvol_r_2, 1*MAX_CHANNELS_VOFF+0x20,s1
sqv v_xvol_r_3, 1*MAX_CHANNELS_VOFF+0x30,s1
jr ra
nop
.endfunc
##############################################################
# Mixer
#
# Arguments:
# s4: buffer into which the mixed samples will be stored
#
# Global state:
# num_samples: number of samples to mix
#
##############################################################
#define v_out_l $v01
#define v_out_r $v02
#define v_sample_0 $v03
#define v_sample_1 $v04
#define v_sample_2 $v05
#define v_sample_3 $v06
#define v_mix_l $v07
#define v_mix_r $v08
.func Mixer
Mixer:
# Load samples
li s0, %lo(CHANNEL_BUFFER)
move t1, num_samples
# Load initial samples
lqv v_sample_0, 0x00,s0
lqv v_sample_1, 0x10,s0
lqv v_sample_2, 0x20,s0
lqv v_sample_3, 0x30,s0
# For optimal pipelining, output is stored at the beginning of the loop. To avoid
# corrupting memory, load the output register with whatever is there now.
lsv v_out_l.e0, -4,s4
ble k0, 8, Mix8Start # Optimized mixing loop for <= 8 channels
lsv v_out_r.e0, -2,s4
Mix32Start:
blt t1, 8, Mix32Loop
move t0, t1
li t0, 8
############################################################################
# VU SU #
############################################################################
.align 3
Mix32Loop:
# Apply volume/panning to each channel sample.
# left channel:
vmulf v_mix_l, v_sample_0, v_xvol_l_0;
vmacf v_mix_l, v_sample_1, v_xvol_l_1; # Store previous loop's output
vmacf v_mix_l, v_sample_2, v_xvol_l_2; ssv v_out_l.e0, -4,s4
vmacf v_mix_l, v_sample_3, v_xvol_l_3; ssv v_out_r.e0, -2,s4
# right channel: # Updated counters
vmulf v_mix_r, v_sample_0, v_xvol_r_0; add s0, 32*2
vmacf v_mix_r, v_sample_1, v_xvol_r_1; addi t0, -1
vmacf v_mix_r, v_sample_2, v_xvol_r_2; addi s4, 4
vmacf v_mix_r, v_sample_3, v_xvol_r_3;
# Mix all lanes together into the first lane # Load next loop's samples
vaddc v_out_l, v_mix_l, v_mix_l.q1; lqv v_sample_0.e0, 0x00,s0
vaddc v_out_r, v_mix_r, v_mix_r.q1; lqv v_sample_1.e0, 0x10,s0
# 1 cycle stall here
vaddc v_out_l, v_out_l, v_out_l.h2; lqv v_sample_2.e0, 0x20,s0
vaddc v_out_r, v_out_r, v_out_r.h2; lqv v_sample_3.e0, 0x30,s0
# 1 cycle stall here
vaddc v_out_l, v_out_l, v_out_l.e4; bnez t0, Mix32Loop
vaddc v_out_r, v_out_r, v_out_r.e4;
#if VOLUME_FILTER
# Apply volume ramp
vmudm v_xvol_l_0, v_xvol_l_0, k_alpha
vmadm v_xvol_l_0, v_chvol_l_0, k_1malpha
vmudm v_xvol_l_1, v_xvol_l_1, k_alpha
vmadm v_xvol_l_1, v_chvol_l_1, k_1malpha
vmudm v_xvol_l_2, v_xvol_l_2, k_alpha
vmadm v_xvol_l_2, v_chvol_l_2, k_1malpha
vmudm v_xvol_l_3, v_xvol_l_3, k_alpha
vmadm v_xvol_l_3, v_chvol_l_3, k_1malpha
vmudm v_xvol_r_0, v_xvol_r_0, k_alpha
vmadm v_xvol_r_0, v_chvol_r_0, k_1malpha
vmudm v_xvol_r_1, v_xvol_r_1, k_alpha
vmadm v_xvol_r_1, v_chvol_r_1, k_1malpha
vmudm v_xvol_r_2, v_xvol_r_2, k_alpha # Next iteration
vmadm v_xvol_r_2, v_chvol_r_2, k_1malpha; addi t1, -8
vmudm v_xvol_r_3, v_xvol_r_3, k_alpha; bgtz t1, Mix32Start
vmadm v_xvol_r_3, v_chvol_r_3, k_1malpha
#else
addi t1, -8
bgtz t1, Mix32Start
nop
#endif
# Store last loop's output and exit
ssv v_out_l.e0, -4,s4
jr ra
ssv v_out_r.e0, -2,s4
Mix8Start:
blt t1, 8, Mix8Loop
move t0, t1
li t0, 8
############################################################################
# VU SU #
############################################################################
.align 3
Mix8Loop:
vmulf v_mix_l, v_sample_0, v_xvol_l_0; ssv v_out_l.e0, -4,s4
vmulf v_mix_r, v_sample_0, v_xvol_r_0; ssv v_out_r.e0, -2,s4
# pipeline stall
vaddc v_out_l, v_mix_l, v_mix_l.q1; addi t0, -1
vaddc v_out_r, v_mix_r, v_mix_r.q1; add s0, 32*2
# pipeline stall
vaddc v_out_l, v_out_l, v_out_l.h2; addi s4, 4
vaddc v_out_r, v_out_r, v_out_r.h2; lqv v_sample_0, 0,s0
# pipeline stall
vaddc v_out_l, v_out_l, v_out_l.e4; bnez t0, Mix8Loop
vaddc v_out_r, v_out_r, v_out_r.e4;
#if VOLUME_FILTER
# Apply volume ramp
vmudm v_xvol_l_0, v_xvol_l_0, k_alpha
vmadm v_xvol_l_0, v_chvol_l_0, k_1malpha; addi t1, -8
vmudm v_xvol_r_0, v_xvol_r_0, k_alpha; bgtz t1, Mix8Start
vmadm v_xvol_r_0, v_chvol_r_0, k_1malpha
#else
addi t1, -8
bgtz t1, Mix8Start
nop
#endif
ssv v_out_l.e0, -4,s4
jr ra
ssv v_out_r.e0, -2,s4
.endfunc
|
nopjne/DaisyDrive64 | 34,329 | external/libdaisy/core/startup_stm32h750xx.s | /**
******************************************************************************
* @file startup_stm32h750xx.s
* @author MCD Application Team
* @brief STM32H750xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word CRYP_IRQHandler /* Crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 5,360 | external/libdaisy/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S | ;/* ----------------------------------------------------------------------
; * Project: CMSIS DSP Library
; * Title: arm_bitreversal2.S
; * Description: arm_bitreversal_32 function done in assembly for maximum speed.
; * Called after doing an fft to reorder the output.
; * The function is loop unrolled by 2. arm_bitreversal_16 as well.
; *
; * $Date: 27. January 2017
; * $Revision: V.1.5.1
; *
; * Target Processor: Cortex-M cores
; * -------------------------------------------------------------------- */
;/*
; * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
#if defined ( __CC_ARM ) /* Keil */
#define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
#define LABEL
#elif defined ( __IASMARM__ ) /* IAR */
#define CODESECT SECTION `.text`:CODE
#define PROC
#define LABEL
#define ENDP
#define EXPORT PUBLIC
#elif defined ( __CSMC__ ) /* Cosmic */
#define CODESECT switch .text
#define THUMB
#define EXPORT xdef
#define PROC :
#define LABEL :
#define ENDP
#define arm_bitreversal_32 _arm_bitreversal_32
#elif defined ( __TI_ARM__ ) /* TI ARM */
#define THUMB .thumb
#define CODESECT .text
#define EXPORT .global
#define PROC : .asmfunc
#define LABEL :
#define ENDP .endasmfunc
#define END
#elif defined ( __GNUC__ ) /* GCC */
#define THUMB .thumb
#define CODESECT .section .text
#define EXPORT .global
#define PROC :
#define LABEL :
#define ENDP
#define END
.syntax unified
#endif
CODESECT
THUMB
;/*
;* @brief In-place bit reversal function.
;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
;* @param[in] bitRevLen bit reversal table length
;* @param[in] *pBitRevTab points to bit reversal table.
;* @return none.
;*/
EXPORT arm_bitreversal_32
EXPORT arm_bitreversal_16
#if defined ( __CC_ARM ) /* Keil */
#elif defined ( __IASMARM__ ) /* IAR */
#elif defined ( __CSMC__ ) /* Cosmic */
#elif defined ( __TI_ARM__ ) /* TI ARM */
#elif defined ( __GNUC__ ) /* GCC */
.type arm_bitreversal_16, %function
.type arm_bitreversal_32, %function
#endif
#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS) || defined(ARM_MATH_ARMV8MBL)
arm_bitreversal_32 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_32_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
LDR r5,[r2,#4]
LDR r4,[r6,#4]
STR r5,[r6,#4]
STR r4,[r2,#4]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r6}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
PUSH {r4-r6}
ADDS r1,r2,#0
LSRS r3,r3,#1
arm_bitreversal_16_0 LABEL
LDRH r2,[r1,#2]
LDRH r6,[r1,#0]
LSRS r2,r2,#1
LSRS r6,r6,#1
ADD r2,r0,r2
ADD r6,r0,r6
LDR r5,[r2,#0]
LDR r4,[r6,#0]
STR r5,[r6,#0]
STR r4,[r2,#0]
ADDS r1,r1,#4
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r6}
BX lr
ENDP
#else
arm_bitreversal_32 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8
ADD r9,r0,r9
ADD r2,r0,r2
ADD r12,r0,r12
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
LDR r7,[r9,#4]
LDR r6,[r8,#4]
LDR r5,[r2,#4]
LDR r4,[r12,#4]
STR r6,[r9,#4]
STR r7,[r8,#4]
STR r5,[r12,#4]
STR r4,[r2,#4]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_32_0
POP {r4-r9}
BX lr
ENDP
arm_bitreversal_16 PROC
ADDS r3,r1,#1
CMP r3,#1
IT LS
BXLS lr
PUSH {r4-r9}
ADDS r1,r2,#2
LSRS r3,r3,#2
arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
LDRH r8,[r1,#4]
LDRH r9,[r1,#2]
LDRH r2,[r1,#0]
LDRH r12,[r1,#-2]
ADD r8,r0,r8,LSR #1
ADD r9,r0,r9,LSR #1
ADD r2,r0,r2,LSR #1
ADD r12,r0,r12,LSR #1
LDR r7,[r9,#0]
LDR r6,[r8,#0]
LDR r5,[r2,#0]
LDR r4,[r12,#0]
STR r6,[r9,#0]
STR r7,[r8,#0]
STR r5,[r12,#0]
STR r4,[r2,#0]
ADDS r1,r1,#8
SUBS r3,r3,#1
BNE arm_bitreversal_16_0
POP {r4-r9}
BX lr
ENDP
#endif
END
|
nopjne/DaisyDrive64 | 45,546 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h755xx.s | ;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h755xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT CM7_SEV_IRQHandler [WEAK]
EXPORT CM4_SEV_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT HSEM2_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT WWDG_RST_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT HOLD_CORE_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
CM7_SEV_IRQHandler
CM4_SEV_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
HSEM2_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
WWDG_RST_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
HOLD_CORE_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 44,410 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s | ;******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
;* File Name : startup_stm32h750xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 45,168 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xx.s | ;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h745xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT CM7_SEV_IRQHandler [WEAK]
EXPORT CM4_SEV_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT HSEM2_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT WWDG_RST_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT HOLD_CORE_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
CM7_SEV_IRQHandler
CM4_SEV_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
HSEM2_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
WWDG_RST_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
HOLD_CORE_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 45,157 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xx.s | ;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h747xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD DSI_IRQHandler ; DSI global Interrupt
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT CM7_SEV_IRQHandler [WEAK]
EXPORT CM4_SEV_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT DSI_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT HSEM2_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT WWDG_RST_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT HOLD_CORE_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
CM7_SEV_IRQHandler
CM4_SEV_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
DSI_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
HSEM2_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
WWDG_RST_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
HOLD_CORE_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 44,410 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s | ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32h753xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 44,144 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s | ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32h743xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 45,642 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h757xx.s | ;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h757xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD DSI_IRQHandler ; DSI global Interrupt
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT CM7_SEV_IRQHandler [WEAK]
EXPORT CM4_SEV_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT LTDC_ER_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT JPEG_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT DSI_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT HSEM2_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT WWDG_RST_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT HOLD_CORE_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
CM7_SEV_IRQHandler
CM4_SEV_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
LTDC_IRQHandler
LTDC_ER_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
JPEG_IRQHandler
MDMA_IRQHandler
DSI_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
HSEM2_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
WWDG_RST_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
HOLD_CORE_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 43,733 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h742xx.s | ;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h742xx.s
;* @author MCD Application Team
;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD 0 ; Reserved
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_AVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT FDCAN1_IT0_IRQHandler [WEAK]
EXPORT FDCAN2_IT0_IRQHandler [WEAK]
EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT FDCAN2_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT FDCAN_CAL_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT UART7_IRQHandler [WEAK]
EXPORT UART8_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT SPI6_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT DMA2D_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
EXPORT SAI3_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT MDIOS_WKUP_IRQHandler [WEAK]
EXPORT MDIOS_IRQHandler [WEAK]
EXPORT MDMA_IRQHandler [WEAK]
EXPORT SDMMC2_IRQHandler [WEAK]
EXPORT HSEM1_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
EXPORT BDMA_Channel0_IRQHandler [WEAK]
EXPORT BDMA_Channel1_IRQHandler [WEAK]
EXPORT BDMA_Channel2_IRQHandler [WEAK]
EXPORT BDMA_Channel3_IRQHandler [WEAK]
EXPORT BDMA_Channel4_IRQHandler [WEAK]
EXPORT BDMA_Channel5_IRQHandler [WEAK]
EXPORT BDMA_Channel6_IRQHandler [WEAK]
EXPORT BDMA_Channel7_IRQHandler [WEAK]
EXPORT COMP1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT LPTIM3_IRQHandler [WEAK]
EXPORT LPTIM4_IRQHandler [WEAK]
EXPORT LPTIM5_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
EXPORT ECC_IRQHandler [WEAK]
EXPORT SAI4_IRQHandler [WEAK]
EXPORT WAKEUP_PIN_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_AVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
FDCAN1_IT0_IRQHandler
FDCAN2_IT0_IRQHandler
FDCAN1_IT1_IRQHandler
FDCAN2_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDMMC1_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
FDCAN_CAL_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
UART7_IRQHandler
UART8_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
SPI6_IRQHandler
SAI1_IRQHandler
DMA2D_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
LPTIM1_IRQHandler
CEC_IRQHandler
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPDIF_RX_IRQHandler
OTG_FS_EP1_OUT_IRQHandler
OTG_FS_EP1_IN_IRQHandler
OTG_FS_WKUP_IRQHandler
OTG_FS_IRQHandler
DMAMUX1_OVR_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
DFSDM1_FLT2_IRQHandler
DFSDM1_FLT3_IRQHandler
SAI3_IRQHandler
SWPMI1_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
MDIOS_WKUP_IRQHandler
MDIOS_IRQHandler
MDMA_IRQHandler
SDMMC2_IRQHandler
HSEM1_IRQHandler
ADC3_IRQHandler
DMAMUX2_OVR_IRQHandler
BDMA_Channel0_IRQHandler
BDMA_Channel1_IRQHandler
BDMA_Channel2_IRQHandler
BDMA_Channel3_IRQHandler
BDMA_Channel4_IRQHandler
BDMA_Channel5_IRQHandler
BDMA_Channel6_IRQHandler
BDMA_Channel7_IRQHandler
COMP1_IRQHandler
LPTIM2_IRQHandler
LPTIM3_IRQHandler
LPTIM4_IRQHandler
LPTIM5_IRQHandler
LPUART1_IRQHandler
CRS_IRQHandler
ECC_IRQHandler
SAI4_IRQHandler
WAKEUP_PIN_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
nopjne/DaisyDrive64 | 34,866 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s | /**
******************************************************************************
* @file startup_stm32h755xx.s
* @author MCD Application Team
* @brief STM32H755xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word CRYP_IRQHandler /* Crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak CM7_SEV_IRQHandler
.thumb_set CM7_SEV_IRQHandler,Default_Handler
.weak CM4_SEV_IRQHandler
.thumb_set CM4_SEV_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak HSEM2_IRQHandler
.thumb_set HSEM2_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak WWDG_RST_IRQHandler
.thumb_set WWDG_RST_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak HOLD_CORE_IRQHandler
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 34,329 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s | /**
******************************************************************************
* @file startup_stm32h750xx.s
* @author MCD Application Team
* @brief STM32H750xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word CRYP_IRQHandler /* Crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 34,766 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s | /**
******************************************************************************
* @file startup_stm32h745xx.s
* @author MCD Application Team
* @brief STM32H745xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak CM7_SEV_IRQHandler
.thumb_set CM7_SEV_IRQHandler,Default_Handler
.weak CM4_SEV_IRQHandler
.thumb_set CM4_SEV_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak HSEM2_IRQHandler
.thumb_set HSEM2_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak WWDG_RST_IRQHandler
.thumb_set WWDG_RST_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak HOLD_CORE_IRQHandler
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 34,854 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s | /**
******************************************************************************
* @file startup_stm32h747xx.s
* @author MCD Application Team
* @brief STM32H747xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word DSI_IRQHandler /* DSI global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak CM7_SEV_IRQHandler
.thumb_set CM7_SEV_IRQHandler,Default_Handler
.weak CM4_SEV_IRQHandler
.thumb_set CM4_SEV_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak HSEM2_IRQHandler
.thumb_set HSEM2_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak WWDG_RST_IRQHandler
.thumb_set WWDG_RST_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak HOLD_CORE_IRQHandler
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 34,329 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s | /**
******************************************************************************
* @file startup_stm32h753xx.s
* @author MCD Application Team
* @brief STM32H753xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word CRYP_IRQHandler /* Crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 34,230 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s | /**
******************************************************************************
* @file startup_stm32h743xx.s
* @author MCD Application Team
* @brief STM32H743xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 34,953 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s | /**
******************************************************************************
* @file startup_stm32h757xx.s
* @author MCD Application Team
* @brief STM32H757xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word CRYP_IRQHandler /* Crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word DSI_IRQHandler /* DSI global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak CM7_SEV_IRQHandler
.thumb_set CM7_SEV_IRQHandler,Default_Handler
.weak CM4_SEV_IRQHandler
.thumb_set CM4_SEV_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP_IRQHandler
.thumb_set CRYP_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak HSEM2_IRQHandler
.thumb_set HSEM2_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak WWDG_RST_IRQHandler
.thumb_set WWDG_RST_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak HOLD_CORE_IRQHandler
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 33,952 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s | /**
******************************************************************************
* @file startup_stm32h742xx.s
* @author MCD Application Team
* @brief STM32H742xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word 0 /* Reserved */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word SAI3_IRQHandler /* SAI3 global Interrupt */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word 0 /* Reserved */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word ADC3_IRQHandler /* ADC3 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
.word COMP1_IRQHandler /* COMP1 global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_FS_EP1_OUT_IRQHandler
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_FS_EP1_IN_IRQHandler
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA_Channel0_IRQHandler
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
.weak BDMA_Channel1_IRQHandler
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
.weak BDMA_Channel2_IRQHandler
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
.weak BDMA_Channel3_IRQHandler
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
.weak BDMA_Channel4_IRQHandler
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
.weak BDMA_Channel5_IRQHandler
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
.weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
.weak BDMA_Channel7_IRQHandler
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
.weak COMP1_IRQHandler
.thumb_set COMP1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 39,060 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h755xx.s | ;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h755xx.s
;* Author : MCD Application Team
;* Description : STM32H755xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK CM7_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM7_SEV_IRQHandler
B CM7_SEV_IRQHandler
PUBWEAK CM4_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM4_SEV_IRQHandler
B CM4_SEV_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK HSEM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM2_IRQHandler
B HSEM2_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK WWDG_RST_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_RST_IRQHandler
B WWDG_RST_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK HOLD_CORE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HOLD_CORE_IRQHandler
B HOLD_CORE_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 38,273 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s | ;/******************** (C) COPYRIGHT 2018 STMicroelectronics ********************
;* File Name : startup_stm32h750xx.s
;* Author : MCD Application Team
;* Description : STM32H750xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 38,924 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xx.s | ;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h745xx.s
;* Author : MCD Application Team
;* Description : STM32H745xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK CM7_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM7_SEV_IRQHandler
B CM7_SEV_IRQHandler
PUBWEAK CM4_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM4_SEV_IRQHandler
B CM4_SEV_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK HSEM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM2_IRQHandler
B HSEM2_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK WWDG_RST_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_RST_IRQHandler
B WWDG_RST_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK HOLD_CORE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HOLD_CORE_IRQHandler
B HOLD_CORE_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 39,063 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xx.s | ;/******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
;* File Name : startup_stm32h747xx.s
;* Author : MCD Application Team
;* Description : STM32H747xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD DSI_IRQHandler ; DSI global Interrupt
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD HOLD_CORE_IRQHandler ; Hold core interrupt
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK CM7_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM7_SEV_IRQHandler
B CM7_SEV_IRQHandler
PUBWEAK CM4_SEV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CM4_SEV_IRQHandler
B CM4_SEV_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK DSI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DSI_IRQHandler
B DSI_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK HSEM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM2_IRQHandler
B HSEM2_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK WWDG_RST_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_RST_IRQHandler
B WWDG_RST_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK HOLD_CORE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HOLD_CORE_IRQHandler
B HOLD_CORE_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 38,273 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s | ;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32h753xx.s
;* Author : MCD Application Team
;* Description : STM32H753xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CRYP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRYP_IRQHandler
B CRYP_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
nopjne/DaisyDrive64 | 38,135 | external/libdaisy/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s | ;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32h743xx.s
;* Author : MCD Application Team
;* Description : STM32H743xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2
DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD RNG_IRQHandler ; Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QUADSPI
DCD LPTIM1_IRQHandler ; LPTIM1
DCD CEC_IRQHandler ; HDMI_CEC
DCD I2C4_EV_IRQHandler ; I2C4 Event
DCD I2C4_ER_IRQHandler ; I2C4 Error
DCD SPDIF_RX_IRQHandler ; SPDIF_RX
DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
DCD SAI3_IRQHandler ; SAI3 global Interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TIM15_IRQHandler ; TIM15 global Interrupt
DCD TIM16_IRQHandler ; TIM16 global Interrupt
DCD TIM17_IRQHandler ; TIM17 global Interrupt
DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
DCD MDIOS_IRQHandler ; MDIOS global Interrupt
DCD JPEG_IRQHandler ; JPEG global Interrupt
DCD MDMA_IRQHandler ; MDMA global Interrupt
DCD 0 ; Reserved
DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
DCD 0 ; Reserved
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
DCD COMP1_IRQHandler ; COMP1 global Interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD 0 ; Reserved
DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
DCD SAI4_IRQHandler ; SAI4 global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_AVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_AVD_IRQHandler
B PVD_AVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK FDCAN1_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT0_IRQHandler
B FDCAN1_IT0_IRQHandler
PUBWEAK FDCAN2_IT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT0_IRQHandler
B FDCAN2_IT0_IRQHandler
PUBWEAK FDCAN1_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN1_IT1_IRQHandler
B FDCAN1_IT1_IRQHandler
PUBWEAK FDCAN2_IT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN2_IT1_IRQHandler
B FDCAN2_IT1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK FDCAN_CAL_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FDCAN_CAL_IRQHandler
B FDCAN_CAL_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK SPDIF_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPDIF_RX_IRQHandler
B SPDIF_RX_IRQHandler
PUBWEAK OTG_FS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_OUT_IRQHandler
B OTG_FS_EP1_OUT_IRQHandler
PUBWEAK OTG_FS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_EP1_IN_IRQHandler
B OTG_FS_EP1_IN_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK SAI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI3_IRQHandler
B SAI3_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK MDIOS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_WKUP_IRQHandler
B MDIOS_WKUP_IRQHandler
PUBWEAK MDIOS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDIOS_IRQHandler
B MDIOS_IRQHandler
PUBWEAK JPEG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
JPEG_IRQHandler
B JPEG_IRQHandler
PUBWEAK MDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MDMA_IRQHandler
B MDMA_IRQHandler
PUBWEAK SDMMC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC2_IRQHandler
B SDMMC2_IRQHandler
PUBWEAK HSEM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM1_IRQHandler
B HSEM1_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK DMAMUX2_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX2_OVR_IRQHandler
B DMAMUX2_OVR_IRQHandler
PUBWEAK BDMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel0_IRQHandler
B BDMA_Channel0_IRQHandler
PUBWEAK BDMA_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel1_IRQHandler
B BDMA_Channel1_IRQHandler
PUBWEAK BDMA_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel2_IRQHandler
B BDMA_Channel2_IRQHandler
PUBWEAK BDMA_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel3_IRQHandler
B BDMA_Channel3_IRQHandler
PUBWEAK BDMA_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel4_IRQHandler
B BDMA_Channel4_IRQHandler
PUBWEAK BDMA_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel5_IRQHandler
B BDMA_Channel5_IRQHandler
PUBWEAK BDMA_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel6_IRQHandler
B BDMA_Channel6_IRQHandler
PUBWEAK BDMA_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
BDMA_Channel7_IRQHandler
B BDMA_Channel7_IRQHandler
PUBWEAK COMP1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP1_IRQHandler
B COMP1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK LPTIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM3_IRQHandler
B LPTIM3_IRQHandler
PUBWEAK LPTIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM4_IRQHandler
B LPTIM4_IRQHandler
PUBWEAK LPTIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM5_IRQHandler
B LPTIM5_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK ECC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ECC_IRQHandler
B ECC_IRQHandler
PUBWEAK SAI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI4_IRQHandler
B SAI4_IRQHandler
PUBWEAK WAKEUP_PIN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WAKEUP_PIN_IRQHandler
B WAKEUP_PIN_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.