repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
abforce/xposed_art_n | 19,721 | runtime/arch/quick_alloc_entrypoints.S | /*
* Copyright (C) 2013 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 5,243 | runtime/interpreter/mterp/mips64/footer.S | /*
* We've detected a condition that will result in an exception, but the exception
* has not yet been thrown. Just bail out to the reference interpreter to deal with it.
* TUNING: for consistency, we may want to just go ahead and handle these here.
*/
.extern MterpLogDivideByZeroException
common_errDivideByZ... |
abforce/xposed_art_n | 1,425 | runtime/interpreter/mterp/mips64/op_aget.S | %default { "load":"lw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* for: aget, aget-boolean, aget-byte, aget-char, aget-short
*
* NOTE: assumes data offset for arrays is the same for all non-wide types.
* If this ch... |
abforce/xposed_art_n | 1,492 | runtime/interpreter/mterp/mips64/binop.S | %default {"preinstr":"", "result":"a0", "chkzero":"0"}
/*
* Generic 32-bit binary operation. Provide an "instr" line that
* specifies an instruction that performs "result = a0 op a1".
* This could be a MIPS instruction or a function call. (If the result
* comes back in a register other than a0... |
abforce/xposed_art_n | 2,346 | runtime/interpreter/mterp/mips64/entry.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,521 | runtime/interpreter/mterp/mips64/binop2addr.S | %default {"preinstr":"", "result":"a0", "chkzero":"0"}
/*
* Generic 32-bit "/2addr" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = a0 op a1".
* This could be a MIPS instruction or a function call. (If the result
* comes back in a register othe... |
abforce/xposed_art_n | 7,784 | runtime/interpreter/mterp/mips64/header.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,431 | runtime/interpreter/mterp/mips64/op_aput.S | %default { "store":"sw", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* for: aput, aput-boolean, aput-byte, aput-char, aput-short
*
* NOTE: this assumes data offset for arrays is the same for all non-wide types.
* If t... |
abforce/xposed_art_n | 1,254 | runtime/interpreter/mterp/mips64/fcmpWide.S | %default {}
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* For: cmpl-double, cmpg-double
*/
/* op vAA, vBB, vCC */
srl a4, rINST, 8 # a4 <- AA
lbu a2, 2(rPC) ... |
abforce/xposed_art_n | 1,363 | runtime/interpreter/mterp/mips64/zcmp.S | /*
* Generic one-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform, e.g. for
* "if-lez" you would use "le".
*
* For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez
*/
/* if-cmp vAA, +BBBB */
.extern MterpProfileBran... |
abforce/xposed_art_n | 1,089 | runtime/interpreter/mterp/mips64/op_goto.S | /*
* Unconditional branch, 8-bit offset.
*
* The branch distance is a signed code-unit offset, which we need to
* double to get a byte offset.
*/
/* goto +AA */
.extern MterpProfileBranch
srl rINST, rINST, 8
seb rINST, rINST # rINST <- offset (sign-ext... |
abforce/xposed_art_n | 1,649 | runtime/interpreter/mterp/mips64/op_packed_switch.S | %default { "func":"MterpDoPackedSwitch" }
/*
* Handle a packed-switch or sparse-switch instruction. In both cases
* we decode it and hand it off to a helper function.
*
* We don't really expect backward branches in a switch statement, but
* they're perfectly legal, so we check for them her... |
abforce/xposed_art_n | 1,252 | runtime/interpreter/mterp/mips64/fcmp.S | %default {}
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* For: cmpl-float, cmpg-float
*/
/* op vAA, vBB, vCC */
srl a4, rINST, 8 # a4 <- AA
lbu a2, 2(rPC) ... |
abforce/xposed_art_n | 1,343 | runtime/interpreter/mterp/mips64/op_goto_32.S | /*
* Unconditional branch, 32-bit offset.
*
* The branch distance is a signed code-unit offset, which we need to
* double to get a byte offset.
*
* Unlike most opcodes, this one is allowed to branch to itself, so
* our "backward branch" test must be "<=0" instead of "<0".
*/
... |
abforce/xposed_art_n | 1,431 | runtime/interpreter/mterp/mips64/binopLit8.S | %default {"preinstr":"", "result":"a0", "chkzero":"0"}
/*
* Generic 32-bit "lit8" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = a0 op a1".
* This could be an MIPS instruction or a function call. (If the result
* comes back in a register other... |
abforce/xposed_art_n | 1,380 | runtime/interpreter/mterp/mips64/binopLit16.S | %default {"preinstr":"", "result":"a0", "chkzero":"0"}
/*
* Generic 32-bit "lit16" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = a0 op a1".
* This could be an MIPS instruction or a function call. (If the result
* comes back in a register othe... |
abforce/xposed_art_n | 1,101 | runtime/interpreter/mterp/mips64/op_aget_wide.S | /*
* Array get, 64 bits. vAA <- vBB[vCC].
*
*/
/* aget-wide vAA, vBB, vCC */
lbu a2, 2(rPC) # a2 <- BB
lbu a3, 3(rPC) # a3 <- CC
srl a4, rINST, 8 # a4 <- AA
GET_VREG_U a0, a2 # a0 <- vBB (array object)... |
abforce/xposed_art_n | 1,533 | runtime/interpreter/mterp/mips64/binopWide2addr.S | %default {"preinstr":"", "result":"a0", "chkzero":"0"}
/*
* Generic 64-bit "/2addr" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = a0 op a1".
* This could be a MIPS instruction or a function call. (If the result
* comes back in a register othe... |
abforce/xposed_art_n | 1,504 | runtime/interpreter/mterp/mips64/binopWide.S | %default {"preinstr":"", "result":"a0", "chkzero":"0"}
/*
* Generic 64-bit binary operation. Provide an "instr" line that
* specifies an instruction that performs "result = a0 op a1".
* This could be a MIPS instruction or a function call. (If the result
* comes back in a register other than a0... |
abforce/xposed_art_n | 1,461 | runtime/interpreter/mterp/mips64/bincmp.S | /*
* Generic two-operand compare-and-branch operation. Provide a "condition"
* fragment that specifies the comparison to perform, e.g. for
* "if-le" you would use "le".
*
* For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le
*/
/* if-cmp vA, vB, +CCCC */
.extern MterpProfileBranch
... |
abforce/xposed_art_n | 1,084 | runtime/interpreter/mterp/mips64/op_aput_wide.S | /*
* Array put, 64 bits. vBB[vCC] <- vAA.
*
*/
/* aput-wide vAA, vBB, vCC */
lbu a2, 2(rPC) # a2 <- BB
lbu a3, 3(rPC) # a3 <- CC
srl a4, rINST, 8 # a4 <- AA
GET_VREG_U a0, a2 # a0 <- vBB (array object)... |
abforce/xposed_art_n | 1,069 | runtime/interpreter/mterp/mips64/op_goto_16.S | /*
* Unconditional branch, 16-bit offset.
*
* The branch distance is a signed code-unit offset, which we need to
* double to get a byte offset.
*/
/* goto/16 +AAAA */
.extern MterpProfileBranch
lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA)
#if MTERP_... |
abforce/xposed_art_n | 1,404 | runtime/interpreter/mterp/arm/op_cmpg_double.S | /*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* int compare(x, y) {
* if (x == y) {
* return 0;
* } else if (x < y) {
* return -1;
* } else if (x > y) {
... |
abforce/xposed_art_n | 1,408 | runtime/interpreter/mterp/arm/op_cmpl_float.S | /*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* int compare(x, y) {
* if (x == y) {
* return 0;
* } else if (x > y) {
* return 1;
* } else if (x < y) {
... |
abforce/xposed_art_n | 1,474 | runtime/interpreter/mterp/arm/op_shr_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance.
*/
/* shr-long vAA, vBB, vCC */
FETCH r0, 1 ... |
abforce/xposed_art_n | 10,103 | runtime/interpreter/mterp/arm/footer.S | /*
* ===========================================================================
* Common subroutines and data
* ===========================================================================
*/
.text
.align 2
/*
* We've detected a condition that will result in an exception, but the exception
* has not y... |
abforce/xposed_art_n | 1,151 | runtime/interpreter/mterp/arm/op_cmp_long.S | /*
* Compare two 64-bit values. Puts 0, 1, or -1 into the destination
* register based on the results of the comparison.
*/
/* cmp-long vAA, vBB, vCC */
FETCH r0, 1 @ r0<- CCBB
mov r9, rINST, lsr #8 @ r9<- AA
and r2, r0, #255 @... |
abforce/xposed_art_n | 1,505 | runtime/interpreter/mterp/arm/op_aget.S | %default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boole... |
abforce/xposed_art_n | 1,703 | runtime/interpreter/mterp/arm/binop.S | %default {"preinstr":"", "result":"r0", "chkzero":"0"}
/*
* Generic 32-bit binary operation. Provide an "instr" line that
* specifies an instruction that performs "result = r0 op r1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register other than r0... |
abforce/xposed_art_n | 1,267 | runtime/interpreter/mterp/arm/op_rem_int_lit8.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* NOTE: idivmod ret... |
abforce/xposed_art_n | 1,475 | runtime/interpreter/mterp/arm/op_shl_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance.
*/
/* shl-long vAA, vBB, vCC */
FETCH r0, 1 ... |
abforce/xposed_art_n | 2,340 | runtime/interpreter/mterp/arm/entry.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,599 | runtime/interpreter/mterp/arm/binop2addr.S | %default {"preinstr":"", "result":"r0", "chkzero":"0"}
/*
* Generic 32-bit "/2addr" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = r0 op r1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register othe... |
abforce/xposed_art_n | 9,370 | runtime/interpreter/mterp/arm/header.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,512 | runtime/interpreter/mterp/arm/op_aput.S | %default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-bool... |
abforce/xposed_art_n | 1,279 | runtime/interpreter/mterp/arm/op_rem_int.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* NOTE: idivmod ret... |
abforce/xposed_art_n | 1,037 | runtime/interpreter/mterp/arm/op_instance_of.S | /*
* Check to see if an object reference is an instance of a class.
*
* Most common situation is a non-null object, being compared against
* an already-resolved class.
*/
/* instance-of vA, vB, class@CCCC */
EXPORT_PC
FETCH r0, 1 @ r0<- CCCC
mov ... |
abforce/xposed_art_n | 1,186 | runtime/interpreter/mterp/arm/op_rem_int_lit16.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* NOTE: idivmod ret... |
abforce/xposed_art_n | 1,163 | runtime/interpreter/mterp/arm/op_shr_long_2addr.S | /*
* Long integer shift, 2addr version. vA is 64-bit value/result, vB is
* 32-bit shift distance.
*/
/* shr-long/2addr vA, vB */
mov r3, rINST, lsr #12 @ r3<- B
ubfx r9, rINST, #8, #4 @ r9<- A
GET_VREG r2, r3 @ r2<- vB
CLEAR_SHADOW_PA... |
abforce/xposed_art_n | 1,046 | runtime/interpreter/mterp/arm/op_iget.S | %default { "is_object":"0", "helper":"artGet32InstanceFromCode"}
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH r0, 1 @ r0<- field ref CCCC
mov r1, rINST, lsr #12 ... |
abforce/xposed_art_n | 1,065 | runtime/interpreter/mterp/arm/op_div_int_2addr.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* div-int/2addr
*
... |
abforce/xposed_art_n | 1,166 | runtime/interpreter/mterp/arm/op_ushr_long_2addr.S | /*
* Long integer shift, 2addr version. vA is 64-bit value/result, vB is
* 32-bit shift distance.
*/
/* ushr-long/2addr vA, vB */
mov r3, rINST, lsr #12 @ r3<- B
ubfx r9, rINST, #8, #4 @ r9<- A
GET_VREG r2, r3 @ r2<- vB
CLEAR_SHADOW_P... |
abforce/xposed_art_n | 1,093 | runtime/interpreter/mterp/arm/unopWide.S | %default {"preinstr":""}
/*
* Generic 64-bit unary operation. Provide an "instr" line that
* specifies an instruction that performs "result = op r0/r1".
* This could be an ARM instruction or a function call.
*
* For: neg-long, not-long, neg-double, long-to-double, double-to-long
*/
... |
abforce/xposed_art_n | 1,404 | runtime/interpreter/mterp/arm/op_cmpg_float.S | /*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* int compare(x, y) {
* if (x == y) {
* return 0;
* } else if (x < y) {
* return -1;
* } else if (x > y) {
... |
abforce/xposed_art_n | 1,071 | runtime/interpreter/mterp/arm/unopNarrower.S | %default {"preinstr":""}
/*
* Generic 64bit-to-32bit unary operation. Provide an "instr" line
* that specifies an instruction that performs "result = op r0/r1", where
* "result" is a 32-bit quantity in r0.
*
* For: long-to-float, double-to-int, double-to-float
*
* (This would wor... |
abforce/xposed_art_n | 1,029 | runtime/interpreter/mterp/arm/unopWider.S | %default {"preinstr":""}
/*
* Generic 32bit-to-64bit unary operation. Provide an "instr" line
* that specifies an instruction that performs "result = op r0", where
* "result" is a 64-bit quantity in r0/r1.
*
* For: int-to-long, int-to-double, float-to-long, float-to-double
*/
/* u... |
abforce/xposed_art_n | 1,601 | runtime/interpreter/mterp/arm/binopLit8.S | %default {"preinstr":"", "result":"r0", "chkzero":"0"}
/*
* Generic 32-bit "lit8" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = r0 op r1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register other ... |
abforce/xposed_art_n | 1,104 | runtime/interpreter/mterp/arm/fbinop.S | /*
* Generic 32-bit floating-point operation. Provide an "instr" line that
* specifies an instruction that performs "s2 = s0 op s1". Because we
* use the "softfp" ABI, this must be an instruction, not a function call.
*
* For: add-float, sub-float, mul-float, div-float
*/
/* floa... |
abforce/xposed_art_n | 1,165 | runtime/interpreter/mterp/arm/op_rem_int_2addr.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* NOTE: idivmod ret... |
abforce/xposed_art_n | 1,374 | runtime/interpreter/mterp/arm/binopLit16.S | %default {"result":"r0", "chkzero":"0"}
/*
* Generic 32-bit "lit16" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = r0 op r1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register other than r0, you c... |
abforce/xposed_art_n | 1,164 | runtime/interpreter/mterp/arm/op_shl_long_2addr.S | /*
* Long integer shift, 2addr version. vA is 64-bit value/result, vB is
* 32-bit shift distance.
*/
/* shl-long/2addr vA, vB */
mov r3, rINST, lsr #12 @ r3<- B
ubfx r9, rINST, #8, #4 @ r9<- A
GET_VREG r2, r3 @ r2<- vB
CLEAR_SHADOW_PA... |
abforce/xposed_art_n | 1,086 | runtime/interpreter/mterp/arm/op_div_int_lit16.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* div-int/lit16
*
... |
abforce/xposed_art_n | 1,106 | runtime/interpreter/mterp/arm/fbinopWide.S | /*
* Generic 64-bit double-precision floating point binary operation.
* Provide an "instr" line that specifies an instruction that performs
* "d2 = d0 op d1".
*
* for: add-double, sub-double, mul-double, div-double
*/
/* doubleop vAA, vBB, vCC */
FETCH r0, 1 ... |
abforce/xposed_art_n | 1,366 | runtime/interpreter/mterp/arm/op_aget_wide.S | /*
* Array get, 64 bits. vAA <- vBB[vCC].
*
* Arrays of long/double are 64-bit aligned, so it's okay to use LDRD.
*/
/* aget-wide vAA, vBB, vCC */
FETCH r0, 1 @ r0<- CCBB
mov r9, rINST, lsr #8 @ r9<- AA
and r2, r0, #255 @ ... |
abforce/xposed_art_n | 2,125 | runtime/interpreter/mterp/arm/op_double_to_long.S | @include "arm/unopWide.S" {"instr":"bl __aeabi_d2lz"}
%include "arm/unopWide.S" {"instr":"bl d2l_doconv"}
%break
/*
* Convert the double in r0/r1 to a long in r0/r1.
*
* We have to clip values to long min/max per the specification. The
* expected common case is a "reasonable" value that converts directl... |
abforce/xposed_art_n | 1,166 | runtime/interpreter/mterp/arm/op_div_int_lit8.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* div-int/lit8
*
... |
abforce/xposed_art_n | 1,781 | runtime/interpreter/mterp/arm/binopWide2addr.S | %default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"}
/*
* Generic 64-bit "/2addr" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = r0-r1 op r2-r3".
* This could be an ARM instruction or a function call. (If the result
* comes ... |
abforce/xposed_art_n | 1,937 | runtime/interpreter/mterp/arm/binopWide.S | %default {"preinstr":"", "result0":"r0", "result1":"r1", "chkzero":"0"}
/*
* Generic 64-bit binary operation. Provide an "instr" line that
* specifies an instruction that performs "result = r0-r1 op r2-r3".
* This could be an ARM instruction or a function call. (If the result
* comes back in a... |
abforce/xposed_art_n | 1,507 | runtime/interpreter/mterp/arm/op_float_to_long.S | @include "arm/unopWider.S" {"instr":"bl __aeabi_f2lz"}
%include "arm/unopWider.S" {"instr":"bl f2l_doconv"}
%break
/*
* Convert the float in r0 to a long in r0/r1.
*
* We have to clip values to long min/max per the specification. The
* expected common case is a "reasonable" value that converts directly
... |
abforce/xposed_art_n | 1,408 | runtime/interpreter/mterp/arm/op_cmpl_double.S | /*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* int compare(x, y) {
* if (x == y) {
* return 0;
* } else if (x > y) {
* return 1;
* } else if (x < y) {
... |
abforce/xposed_art_n | 1,299 | runtime/interpreter/mterp/arm/op_aput_wide.S | /*
* Array put, 64 bits. vBB[vCC] <- vAA.
*
* Arrays of long/double are 64-bit aligned, so it's okay to use STRD.
*/
/* aput-wide vAA, vBB, vCC */
FETCH r0, 1 @ r0<- CCBB
mov r9, rINST, lsr #8 @ r9<- AA
and r2, r0, #255 @ ... |
abforce/xposed_art_n | 1,577 | runtime/interpreter/mterp/arm/op_mul_long.S | /*
* Signed 64-bit integer multiply.
*
* Consider WXxYZ (r1r0 x r3r2) with a long multiply:
* WX
* x YZ
* --------
* ZW ZX
* YW YX
*
* The low word of the result holds ZX, the high word holds
* (ZW+YX) + (the high overflow from ZX). YW doesn'... |
abforce/xposed_art_n | 1,165 | runtime/interpreter/mterp/arm/op_mul_long_2addr.S | /*
* Signed 64-bit integer multiply, "/2addr" version.
*
* See op_mul_long for an explanation.
*
* We get a little tight on registers, so to avoid looking up &fp[A]
* again we stuff it into rINST.
*/
/* mul-long/2addr vA, vB */
mov r1, rINST, lsr #12 @ r1<- B
... |
abforce/xposed_art_n | 1,164 | runtime/interpreter/mterp/arm/op_div_int.S | %default {}
/*
* Specialized 32-bit binary operation
*
* Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper
* depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for
* ARMv7 CPUs that have hardware division support).
*
* div-int
*
*/
... |
abforce/xposed_art_n | 1,477 | runtime/interpreter/mterp/arm/op_ushr_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance.
*/
/* ushr-long vAA, vBB, vCC */
FETCH r0, 1 ... |
abforce/xposed_art_n | 10,769 | runtime/interpreter/mterp/arm64/footer.S | /*
* ===========================================================================
* Common subroutines and data
* ===========================================================================
*/
/*
* We've detected a condition that will result in an exception, but the exception
* has not yet been thrown. Just ba... |
abforce/xposed_art_n | 1,476 | runtime/interpreter/mterp/arm64/op_aget.S | %default { "load":"ldr", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
/*
* Array get, 32 bits or less. vAA <- vBB[vCC].
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aget, aget-boole... |
abforce/xposed_art_n | 1,680 | runtime/interpreter/mterp/arm64/binop.S | %default {"preinstr":"", "result":"w0", "chkzero":"0"}
/*
* Generic 32-bit binary operation. Provide an "instr" line that
* specifies an instruction that performs "result = w0 op w1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register other than w0... |
abforce/xposed_art_n | 2,444 | runtime/interpreter/mterp/arm64/entry.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,546 | runtime/interpreter/mterp/arm64/binop2addr.S | %default {"preinstr":"", "result":"w0", "chkzero":"0"}
/*
* Generic 32-bit "/2addr" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = w0 op w1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register othe... |
abforce/xposed_art_n | 9,129 | runtime/interpreter/mterp/arm64/header.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,469 | runtime/interpreter/mterp/arm64/op_aput.S | %default { "store":"str", "shift":"2", "data_offset":"MIRROR_INT_ARRAY_DATA_OFFSET" }
/*
* Array put, 32 bits or less. vBB[vCC] <- vAA.
*
* Note: using the usual FETCH/and/shift stuff, this fits in exactly 17
* instructions. We use a pair of FETCH_Bs instead.
*
* for: aput, aput-bool... |
abforce/xposed_art_n | 1,043 | runtime/interpreter/mterp/arm64/op_instance_of.S | /*
* Check to see if an object reference is an instance of a class.
*
* Most common situation is a non-null object, being compared against
* an already-resolved class.
*/
/* instance-of vA, vB, class//CCCC */
EXPORT_PC
FETCH w0, 1 // w0<- CCCC
lsr ... |
abforce/xposed_art_n | 1,062 | runtime/interpreter/mterp/arm64/op_iget.S | %default { "extend":"", "is_object":"0", "helper":"artGet32InstanceFromCode"}
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
FETCH w0, 1 // w0<- field ref CCCC
lsr w1, wINST, #12... |
abforce/xposed_art_n | 1,548 | runtime/interpreter/mterp/arm64/binopLit8.S | %default {"preinstr":"", "result":"w0", "chkzero":"0"}
/*
* Generic 32-bit "lit8" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = w0 op w1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register other ... |
abforce/xposed_art_n | 1,349 | runtime/interpreter/mterp/arm64/binopLit16.S | %default {"preinstr":"", "result":"w0", "chkzero":"0"}
/*
* Generic 32-bit "lit16" binary operation. Provide an "instr" line
* that specifies an instruction that performs "result = w0 op w1".
* This could be an ARM instruction or a function call. (If the result
* comes back in a register other... |
abforce/xposed_art_n | 1,089 | runtime/interpreter/mterp/arm64/op_aget_wide.S | /*
* Array get, 64 bits. vAA <- vBB[vCC].
*
*/
/* aget-wide vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG ... |
abforce/xposed_art_n | 1,413 | runtime/interpreter/mterp/arm64/binopWide2addr.S | %default {"preinstr":"", "instr":"add x0, x0, x1", "r0":"x0", "r1":"x1", "chkzero":"0"}
/*
* Generic 64-bit "/2addr" binary operation. Provide an "instr" line
* that specifies an instruction that performs "x0 = x0 op x1".
* This must not be a function call, as we keep w2 live across it.
*
... |
abforce/xposed_art_n | 1,522 | runtime/interpreter/mterp/arm64/binopWide.S | %default {"preinstr":"", "instr":"add x0, x1, x2", "result":"x0", "r1":"x1", "r2":"x2", "chkzero":"0"}
/*
* Generic 64-bit binary operation. Provide an "instr" line that
* specifies an instruction that performs "result = x1 op x2".
* This could be an ARM instruction or a function call. (If the resu... |
abforce/xposed_art_n | 1,070 | runtime/interpreter/mterp/arm64/op_aput_wide.S | /*
* Array put, 64 bits. vBB[vCC] <- vAA.
*
*/
/* aput-wide vAA, vBB, vCC */
FETCH w0, 1 // w0<- CCBB
lsr w4, wINST, #8 // w4<- AA
and w2, w0, #255 // w2<- BB
lsr w3, w0, #8 // w3<- CC
GET_VREG ... |
abforce/xposed_art_n | 1,149 | runtime/interpreter/mterp/x86/op_shr_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance. x86 shifts automatically mask off
* the low 5 bits of %cl, so have to handle... |
abforce/xposed_art_n | 10,012 | runtime/interpreter/mterp/x86/footer.S | /*
* ===========================================================================
* Common subroutines and data
* ===========================================================================
*/
.text
.align 2
/*
* We've detected a condition that will result in an exception, but the exception
* has not y... |
abforce/xposed_art_n | 1,142 | runtime/interpreter/mterp/x86/op_shl_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance. x86 shifts automatically mask off
* the low 5 bits of %cl, so have to handle... |
abforce/xposed_art_n | 2,156 | runtime/interpreter/mterp/x86/entry.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 9,367 | runtime/interpreter/mterp/x86/header.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,125 | runtime/interpreter/mterp/x86/op_iget.S | %default { "is_object":"0", "helper":"artGet32InstanceFromCode"}
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short
*/
EXPORT_PC
movzwl 2(rPC), %eax # eax <- 0000CCCC
movl %eax, OUT_ARG0(%esp) # field ref CCCC
... |
abforce/xposed_art_n | 2,083 | runtime/interpreter/mterp/x86/cvtfp_int.S | %default {"srcdouble":"1","tgtlong":"1"}
/* On fp to int conversions, Java requires that
* if the result > maxint, it should be clamped to maxint. If it is less
* than minint, it should be clamped to minint. If it is a nan, the result
* should be zero. Further, the rounding mode is to truncate. This model
* dif... |
abforce/xposed_art_n | 1,709 | runtime/interpreter/mterp/x86/bindiv.S | %default {"result":"","special":"","rem":""}
/*
* 32-bit binary div/rem operation. Handles special case of op0=minint and
* op1=-1.
*/
/* div/rem vAA, vBB, vCC */
movzbl 2(rPC), %eax # eax <- BB
movzbl 3(rPC), %ecx # ecx <- CC
GET_VREG %eax, %eax ... |
abforce/xposed_art_n | 1,625 | runtime/interpreter/mterp/x86/op_mul_long.S | /*
* Signed 64-bit integer multiply.
*
* We could definately use more free registers for
* this code. We spill rINSTw (ebx),
* giving us eax, ebc, ecx and edx as computational
* temps. On top of that, we'll spill edi (rFP)
* for use as the vB pointer and esi (rPC) for use
* as the vC pointer. Yuck.
*
*/
... |
abforce/xposed_art_n | 1,831 | runtime/interpreter/mterp/x86/op_mul_long_2addr.S | /*
* Signed 64-bit integer multiply, 2-addr version
*
* We could definately use more free registers for
* this code. We must spill %edx (rIBASE) because it
* is used by imul. We'll also spill rINST (ebx),
* giving us eax, ebc, ecx and rIBASE as computational
* temps. On top of that, we'll spill %esi (edi)
* ... |
abforce/xposed_art_n | 1,152 | runtime/interpreter/mterp/x86/op_ushr_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance. x86 shifts automatically mask off
* the low 5 bits of %cl, so have to handle... |
abforce/xposed_art_n | 9,212 | runtime/interpreter/mterp/x86_64/footer.S | /*
* ===========================================================================
* Common subroutines and data
* ===========================================================================
*/
.text
.align 2
/*
* We've detected a condition that will result in an exception, but the exception
* has not y... |
abforce/xposed_art_n | 2,059 | runtime/interpreter/mterp/x86_64/entry.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 8,676 | runtime/interpreter/mterp/x86_64/header.S | /*
* Copyright (C) 2016 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
abforce/xposed_art_n | 1,047 | runtime/interpreter/mterp/x86_64/op_iget.S | %default { "is_object":"0", "helper":"artGet32InstanceFromCode", "wide":"0"}
/*
* General instance field get.
*
* for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short, iget-wide
*/
EXPORT_PC
movzbq rINSTbl, %rcx # rcx <- BA
movzwl 2(rPC), OUT_32_ARG0 # e... |
abforce/xposed_art_n | 1,142 | runtime/interpreter/mterp/x86_64/bindiv2addr.S | %default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"}
/*
* 32-bit binary div/rem operation. Handles special case of op1=-1.
*/
/* div/rem/2addr vA, vB */
movl rINST, %ecx # rcx <- BA
sarl $$4, %ecx # rcx <- B
andb $$0xf, rINS... |
abforce/xposed_art_n | 1,052 | runtime/interpreter/mterp/x86_64/cvtfp_int.S | %default {"fp_suffix":"","i_suffix":"","max_const":"","result_reg":"","wide":""}
/* On fp to int conversions, Java requires that
* if the result > maxint, it should be clamped to maxint. If it is less
* than minint, it should be clamped to minint. If it is a nan, the result
* should be zero. Further, the rounding... |
abforce/xposed_art_n | 1,087 | runtime/interpreter/mterp/x86_64/bindiv.S | %default {"result":"","second":"","wide":"","suffix":"","rem":"0","ext":"cdq"}
/*
* 32-bit binary div/rem operation. Handles special case of op1=-1.
*/
/* div/rem vAA, vBB, vCC */
movzbq 2(rPC), %rax # rax <- BB
movzbq 3(rPC), %rcx # rcx <- CC
.if $wide
GET... |
abforce/xposed_art_n | 1,866 | runtime/interpreter/mterp/mips/op_cmpl_float.S | %default { "naninst":"li rTEMP, -1" }
/*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register rTEMP based on the results of the comparison.
*
* Provide a "naninst" instruction that puts 1 or -1 into rTEMP depending
* on what value we'd like to return when o... |
abforce/xposed_art_n | 1,533 | runtime/interpreter/mterp/mips/op_shr_long.S | /*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to mask off the low
* 6 bits of the shift distance.
*/
/* shr-long vAA, vBB, vCC */
FETCH(a0, 1) ... |
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