repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 6,264 | sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s | //Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp
// Spec Reference: c_dspldst st_drhi_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
i... |
tactcomplabs/xbgas-binutils-gdb | 2,869 | sim/testsuite/bfin/m5.s | // Test result extraction of mac instructions.
// Test basic edge values
// SIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym... |
tactcomplabs/xbgas-binutils-gdb | 5,457 | sim/testsuite/bfin/c_ldst_ld_p_p_pp.s | //Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp
// Spec Reference: c_ldst ld p [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ++ ];
P1 +=... |
tactcomplabs/xbgas-binutils-gdb | 1,158 | sim/testsuite/bfin/c_dsp32shiftim_lf.s | //Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
i... |
tactcomplabs/xbgas-binutils-gdb | 23,178 | sim/testsuite/bfin/random_0025.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x10cfffff;
imm32 R6, 0x06a1ea20;
R0.H = R6.H >>> 0x1b;
checkreg R0, 0xd420ffff;
checkreg ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);... |
tactcomplabs/xbgas-binutils-gdb | 1,725 | sim/testsuite/bfin/brcc.s | # mach: bfin
.include "testutils.inc"
start
/* Stall tests */
r0 = 0;
r1 = 1;
loadsym p0, foo;
p1 = p0;
pass_1:
cc = r0;
nop;
nop;
if cc jump _fail_1;
[p0++] = p0;
[p0++] = p0;
r7 = p0;
r5 = CC;
P1 += 8;
r6 = p1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if !cc jump over;
_fail_1:
[p0++... |
tactcomplabs/xbgas-binutils-gdb | 5,030 | sim/testsuite/bfin/s13.s | // Test rl3 = ashift (rh0 by r5;
// Test rl3 = lshift (rh0 by r5);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
R0 = 0;
ASTAT = R0;
R0.L = 0x1;
R0.H = 0x1;
R5.L = 4;
R7.L = ASHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0010 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = A... |
tactcomplabs/xbgas-binutils-gdb | 4,844 | sim/testsuite/bfin/c_dsp32mult_dr_m_i.s | //Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp
// Spec Reference: dsp32mult single dr munop i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
tactcomplabs/xbgas-binutils-gdb | 8,283 | sim/testsuite/bfin/c_interr_timer.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp
// Spec Reference: interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL ... |
tactcomplabs/xbgas-binutils-gdb | 9,178 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00100a00;
imm32 r1, 0x00100a01;
imm32 r2, 0x00100a02;
imm32 r3, 0x00100a03;
imm32 r4, 0x0010... |
tactcomplabs/xbgas-binutils-gdb | 4,524 | sim/testsuite/bfin/c_dsp32mult_pair_u.s | //Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp
// Spec Reference: dsp32mult pair u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2... |
tactcomplabs/xbgas-binutils-gdb | 6,095 | sim/testsuite/bfin/c_interr_nmi.S | //Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); ... |
tactcomplabs/xbgas-binutils-gdb | 6,338 | sim/testsuite/bfin/c_progctrl_clisti_interr.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp
// Spec Reference: CLI STI interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifnd... |
tactcomplabs/xbgas-binutils-gdb | 7,454 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp
// Spec Reference: dsp32mac pair a1a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645... |
tactcomplabs/xbgas-binutils-gdb | 1,885 | sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s | //Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp
// Spec Reference: c_cactrl iflush_pr [p++]
# mach: bfin
.include "testutils.inc"
start
loadsym p2, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0... |
tactcomplabs/xbgas-binutils-gdb | 2,422 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s | //Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x0730... |
tactcomplabs/xbgas-binutils-gdb | 6,193 | sim/testsuite/bfin/c_ldst_ld_d_p.s | //Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp
// Spec Reference: c_ldst ld d [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ];
R1 = [ P2 ];
R3... |
tactcomplabs/xbgas-binutils-gdb | 2,559 | sim/testsuite/bfin/random_0010.S | # Test logical left shift (vector) insns with larger shift values
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN);
imm32 R5, 0xb0b40000;
imm32 R6, 0xf43a5d3c;
R6 = R5 << 0x19 (V, S);
checkreg R6, 0xff610000;
checkreg ASTAT, (0x30400e90 | ... |
tactcomplabs/xbgas-binutils-gdb | 5,635 | sim/testsuite/bfin/se_misaligned_fetch.S | //Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp
// Description: attempt to fetch code from misaligned address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
incl... |
tactcomplabs/xbgas-binutils-gdb | 2,751 | sim/testsuite/bfin/abs_acc.s | // ACP 5.7 ABS(A1) sets AV0
# mach: bfin
.include "testutils.inc"
start
r1=0x80 (z);
A0=0;
A0.x=r1;
A0=abs A0;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x3);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
db... |
tactcomplabs/xbgas-binutils-gdb | 2,492 | sim/testsuite/bfin/c_logi2op_bitclr.s | //Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp
// Spec Reference: Logi2op functions: bitclr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xffffffff;
imm32 r1, 0xffffffff;
imm32 r2, 0xffffffff;
imm32 r3, 0xffffffff;
imm32 r4, 0xffffffff;
imm32 r5, 0xffffffff;
imm32 r6, 0xffffffff;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 1,057 | sim/testsuite/bfin/c_brcc_bp2.s | //Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT =... |
tactcomplabs/xbgas-binutils-gdb | 3,798 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp
// Spec Reference: dsp32mac pair a1a0 M MNOP
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0... |
tactcomplabs/xbgas-binutils-gdb | 4,167 | sim/testsuite/bfin/c_regmv_dr_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp
// Spec Reference: regmv dr-dep no stall
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00110001;
imm32 r2, 0x00220002;
imm32 r3, 0x00330003;
imm32 r4, 0x00440004;
imm32 r5, 0x00550005;
imm... |
tactcomplabs/xbgas-binutils-gdb | 11,110 | sim/testsuite/bfin/se_loop_kill_01.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 4,049 | sim/testsuite/bfin/random_0034.S | # Verify sign extension behavior with simultaneous acc additions, and
# verify that no ASTAT bits get changed as a result
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
dmm32 A0.w, 0x589145b7;
dmm32 A0.x, 0xffffffee;
dmm32 A1.w, 0x0b247b05;
dm... |
tactcomplabs/xbgas-binutils-gdb | 6,164 | sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp
// Spec Reference: dsp32mac pair a1 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa894567... |
tactcomplabs/xbgas-binutils-gdb | 12,214 | sim/testsuite/bfin/se_cc2stat_haz.S | //Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp
// Description:
// Verify CC hazards under the following condition:
//
// (1a) cc2stat (that modifies CC) followed by that uses CC
// (1b) same as (1a) but kill cc2stat instruction in WB
//
// (2a) cc2stat (that modifies CC) foll... |
tactcomplabs/xbgas-binutils-gdb | 1,775 | sim/testsuite/bfin/c_regmv_pr_pr.s | //Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp
// Spec Reference: regmv preg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
imm32 p1, 0x20021003;
imm32 p... |
tactcomplabs/xbgas-binutils-gdb | 11,635 | sim/testsuite/bfin/se_popkill.S | //Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp
// Description: Kill pops to sysregs in WB
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files... |
tactcomplabs/xbgas-binutils-gdb | 8,524 | sim/testsuite/bfin/c_regmv_dr_imlb.s | //Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp
// Spec Reference: regmv dreg-to-imlb
# mach: bfin
.include "testutils.inc"
start
// check DR-reg to imlb-reg move
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 7,518 | sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
in... |
tactcomplabs/xbgas-binutils-gdb | 2,470 | sim/testsuite/bfin/dsp_a4.s | /* ALU test program.
* Test instructions
* r3= + (r0,r0);
* r3= + (r0,r0) s;
* r3= - (r0,r0);
* r3= - (r0,r0) s;
*/
# mach: bfin
.include "testutils.inc"
start
// overflow positive
R0.L = 0xffff;
R0.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0xffff )... |
tactcomplabs/xbgas-binutils-gdb | 1,470 | sim/testsuite/bfin/m9.s | // Test extraction from accumulators:
// ROUND/TRUNCATE in SIGNED FRACTIONAL mode
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffef000
// load r1=0x7ffff000
// load r2=0x00008000
// load r3=0x00018000
// load r4=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 =... |
tactcomplabs/xbgas-binutils-gdb | 7,235 | sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
IN... |
tactcomplabs/xbgas-binutils-gdb | 4,171 | sim/testsuite/bfin/c_alu2op_log_l_sft.s | //Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp
// Spec Reference: alu2op logical left
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x9... |
tactcomplabs/xbgas-binutils-gdb | 2,118 | sim/testsuite/bfin/cir1.s | # Blackfin testcase for circular buffers
# mach: bfin
.include "testutils.inc"
.macro daginit i:req, b:req, l:req, m:req
imm32 I0, \i
imm32 B0, \b
imm32 L0, \l
imm32 M0, \m
.endm
.macro dagcheck newi:req
DBGA ( I0.L, \newi & 0xFFFF );
DBGA ( I0.H, \newi >> 16 );
.endm
.macro dagadd i:req, b:req, l:req, m... |
tactcomplabs/xbgas-binutils-gdb | 4,503 | sim/testsuite/bfin/c_dsp32mult_dr_m.s | //Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp
// Spec Reference: dsp32mult single dr (mix) MUNOP
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm... |
tactcomplabs/xbgas-binutils-gdb | 6,139 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_b.s | //Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp
// Spec Reference: c_ldst ld d [p--] b
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2... |
tactcomplabs/xbgas-binutils-gdb | 2,772 | sim/testsuite/bfin/c_dspldst_st_drlo_i.s | //Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp
// Spec Reference: c_dspldst st_drlo_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
i... |
tactcomplabs/xbgas-binutils-gdb | 1,068 | sim/testsuite/bfin/c_brcc_bp4.s | //Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT ... |
tactcomplabs/xbgas-binutils-gdb | 1,417 | sim/testsuite/bfin/m15.s | // Test extraction from accumulators:
// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0ffffff0
// load r1=0x7ffffff0
// load r2=0x0fffffff
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ... |
tactcomplabs/xbgas-binutils-gdb | 2,424 | sim/testsuite/bfin/cc-astat-bits.s | # Blackfin testcase for setting all ASTAT bits via CC
# mach: bfin
# We encode the opcodes directly since we test reserved bits
# which lack an insn in the ISA for it. It's a 16bit insn;
# the low 8 bits are always 0x03 while the encoding for the
# high 8 bits are:
# bit 7 - direction
# 0: CC=...;
# ... |
tactcomplabs/xbgas-binutils-gdb | 10,645 | sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s | //Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp
// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1... |
tactcomplabs/xbgas-binutils-gdb | 5,502 | sim/testsuite/bfin/c_logi2op_arith_shft.s | //Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp
// Spec Reference: Logi2op >>>=
# mach: bfin
.include "testutils.inc"
start
// Arithmetic >>>= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5... |
tactcomplabs/xbgas-binutils-gdb | 6,609 | sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s | //Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp
// Spec Reference: c_dspldst ld_drhi_i++/--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
// initial values
//i0=0x3000;
//i1=0x4000;
//i2=0x5000;
//i3=0x6000;
loadsym I0, DATA_ADDR_3;
loadsym I1, DATA_ADDR_4... |
tactcomplabs/xbgas-binutils-gdb | 2,844 | sim/testsuite/bfin/conv_enc_gen.s | # mach: bfin
// GENERIC CONVOLUTIONAL ENCODER
// This a generic rate 1/n convolutional encoder. It computes n output
// bits for each input bit, based on n generic polynomials.
// It uses the set of BXOR_CC instructions to compute bit XOR
// reduction from a state masked by a polynomial. For an alternate
// solution ... |
tactcomplabs/xbgas-binutils-gdb | 4,017 | sim/testsuite/bfin/c_cc2stat_cc_an.s | //Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp
// Spec Reference: cc2stat cc an
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;... |
tactcomplabs/xbgas-binutils-gdb | 9,359 | sim/testsuite/bfin/se_loop_disable.S | //Original:/proj/frio/dv/testcases/seq/se_loop_disable/se_loop_disable.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 1,898 | sim/testsuite/bfin/c_cactrl_iflush_pr.s | //Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp
// Spec Reference: c_cactrl iflush_pr
# mach: bfin
.include "testutils.inc"
start
// initial values
//p1=0x448;
//imm32 p1, CODE_ADDR_1;
loadsym p1, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1... |
tactcomplabs/xbgas-binutils-gdb | 1,667 | sim/testsuite/bfin/c_br_preg_killed_ac.s | //Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000... |
tactcomplabs/xbgas-binutils-gdb | 1,458 | sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s | //Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp
// Spec Reference: dsp32alu r(lh) = ( a0 += a1)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x0125ab2d;
imm32 r2, 0x04445535;
imm32 r3, 0x00567747;
imm32 r4, 0x0566895b;
imm32 r5, 0x07897b6d;
imm32 r6, 0x044... |
tactcomplabs/xbgas-binutils-gdb | 3,498 | sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s | //Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp
// Spec Reference: dsp32mac dr_a1 iu (unsigned integer)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x7890afc7;
imm32 r2, 0x52248679;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 4,386 | sim/testsuite/bfin/a10.s | // ALU test program.
// Test dual 16 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0002;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0002 ... |
tactcomplabs/xbgas-binutils-gdb | 2,744 | sim/testsuite/bfin/c_ldimmhalf_l_ibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp
// Spec Reference: ldimmhalf l ibml
# mach: bfin
.include "testutils.inc"
start
INIT_I_REGS -1;
INIT_L_REGS -1;
INIT_M_REGS -1;
INIT_B_REGS -1;
I0.L = 0x2001;
I1.L = 0x2003;
I2.L = 0x2005;
I3.L = 0x2007;
L0.L = 0x2009;
L1.L ... |
tactcomplabs/xbgas-binutils-gdb | 9,978 | sim/testsuite/bfin/se_loop_nest_ppm.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 2,538 | sim/testsuite/bfin/s30.s | // Test signbits40
# mach: bfin
.include "testutils.inc"
start
// positive value in accum, smaller than 1.0
A1 = A0 = 0;
R0.L = 0xffff;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA... |
tactcomplabs/xbgas-binutils-gdb | 1,827 | sim/testsuite/bfin/dsp_d1.s | /* DAG test program.
* Test circular buffers
*/
# mach: bfin
.include "testutils.inc"
start
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x10 (X);
M1 = 8 (X);
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 )... |
tactcomplabs/xbgas-binutils-gdb | 3,002 | sim/testsuite/bfin/c_dsp32shift_bxor.s | //Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp
// Spec Reference: dsp32shift bxor
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
R1 = 58;
A0 = R1;
ASTAT = R0;
imm32 r0, 0x12345678;
imm32 r1, 0x22334455;
imm32 r2, 0x66778890;
imm32 r3, 0xaabbccdd;
imm32 r4, 0x34567890;
imm32 r5, 0xa2d3d5f6;... |
tactcomplabs/xbgas-binutils-gdb | 9,103 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0... |
tactcomplabs/xbgas-binutils-gdb | 1,056 | sim/testsuite/bfin/c_dsp32alu_sgn.s | //Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L;
R5.H = R5.L = SIGN(... |
tactcomplabs/xbgas-binutils-gdb | 3,544 | sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s | //Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp
// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679... |
tactcomplabs/xbgas-binutils-gdb | 4,640 | sim/testsuite/bfin/c_alu2op_shadd_1.s | //Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp
// Spec Reference: alu2op shadd 1
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bc... |
tactcomplabs/xbgas-binutils-gdb | 4,134 | sim/testsuite/bfin/c_alu2op_conv_xh.s | //Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp
// Spec Reference: alu2op convert xh
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8... |
tactcomplabs/xbgas-binutils-gdb | 10,753 | sim/testsuite/bfin/lmu_excpt_illaddr.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp
// Description: LMU illegal address exceptions
// Illegal core MMR: addr[19:16] != 0
// Illegal core MMR: Illegal peripheral
// Illegal core MMR: Illegal addr in peripheral
# mach: bfin
# sim: --environment operating
#include "test.h"
.incl... |
tactcomplabs/xbgas-binutils-gdb | 1,462 | sim/testsuite/bfin/stk3.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 =... |
tactcomplabs/xbgas-binutils-gdb | 6,835 | sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp
// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
I... |
tactcomplabs/xbgas-binutils-gdb | 54,870 | sim/testsuite/bfin/se_undefinedinstruction2.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction2/se_undefinedinstruction2.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
... |
tactcomplabs/xbgas-binutils-gdb | 6,307 | sim/testsuite/bfin/c_ldst_ld_d_p_pp.s | //Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp
// Spec Reference: c_ldst ld d [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P5 ++ ];
R1 = ... |
tactcomplabs/xbgas-binutils-gdb | 4,737 | sim/testsuite/bfin/c_dspldst_st_dr_ippm.s | //Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp
// Spec Reference: c_dspldst st_dr_ippm
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;... |
tactcomplabs/xbgas-binutils-gdb | 17,518 | sim/testsuite/bfin/se_loop_kill_dcr.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 11,801 | sim/testsuite/bfin/se_loop_mv2lb_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lb_stall/se_loop_mv2lb_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
tactcomplabs/xbgas-binutils-gdb | 3,329 | sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp
// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1)
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4, 0xa00a1089;
imm32 p5, 0x... |
tactcomplabs/xbgas-binutils-gdb | 11,276 | sim/testsuite/bfin/c_dsp32shift_bitmux.s | //Original:/testcases/core/c_dsp32shift_bitmux/c_dsp32shift_bitmux.dsp
// Spec Reference: dsp32shift bitmux
# mach: bfin
.include "testutils.inc"
start
A0 = 0;
imm32 r0, 0x01230000;
imm32 r1, 0x12340678;
imm32 r2, 0x23450089;
imm32 r3, 0x3456089a;
imm32 r4, 0x456709ab;
imm32 r5, 0x56780abc;
imm32 r6, 0x678... |
tactcomplabs/xbgas-binutils-gdb | 10,162 | sim/testsuite/bfin/lmu_excpt_align.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp
// Description: LMU data alignment exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
CHECK_INIT(p5, 0xE0000000);
// test addres... |
tactcomplabs/xbgas-binutils-gdb | 10,840 | sim/testsuite/bfin/c_ldstii_st_dreg.s | //Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp
// Spec Reference: c_ldstii store dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 6,227 | sim/testsuite/bfin/se_bug_ui.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include... |
tactcomplabs/xbgas-binutils-gdb | 1,131 | sim/testsuite/bfin/se_all64bitg2opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 2)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach:... |
tactcomplabs/xbgas-binutils-gdb | 5,570 | sim/testsuite/bfin/a9.s | // ALU test program.
// Test 32 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R... |
tactcomplabs/xbgas-binutils-gdb | 9,487 | sim/testsuite/bfin/se_loop_ppm_int.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 2,919 | sim/testsuite/bfin/random_0023.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0xf41fbf3f;
dmm32 A1.x, 0x00000000;
imm32 R5, 0xd8d95310;
imm32 R6, 0xd0457fff;
R5.H = (A1 -= R6.L * R6.H) (M, FU);
checkreg R5, 0x7fff5310;
checkreg A1.... |
tactcomplabs/xbgas-binutils-gdb | 5,914 | sim/testsuite/bfin/c_dsp32alu_rl_m.s | //Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x55678911;
imm32 r1, 0x2759ab1d;
imm32 r2, 0x34455515;
imm32 r3, 0x46665717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789a51d;
imm32 r6, 0x74445515;
imm32 r7, 0x8... |
tactcomplabs/xbgas-binutils-gdb | 9,699 | sim/testsuite/bfin/c_dsp32shift_rot_mix.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp
// Spec Reference: dsp32shift rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x83456789;
imm32 r3, 0x9456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb... |
tactcomplabs/xbgas-binutils-gdb | 6,197 | sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s | //Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp
// Spec Reference: c_dspldst ld_dr_i++/--
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 ... |
tactcomplabs/xbgas-binutils-gdb | 1,066 | sim/testsuite/bfin/c_brcc_brf_bp.s | //Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp
// Spec Reference: brcc brf bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
beg... |
tactcomplabs/xbgas-binutils-gdb | 2,632 | sim/testsuite/bfin/a7.s | # mach: bfin
.include "testutils.inc"
start
R1 = 0;
R0 = 0;
R0 = R1 ^ R0;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 1 );
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
... |
tactcomplabs/xbgas-binutils-gdb | 1,744 | sim/testsuite/bfin/double_prec_mult.s | # mach: bfin
.include "testutils.inc"
start
// This function computes an integer 32x32 multiply,
// and returns the upper 32 bits of the result.
// If the complete 64 bit result is required, one must
// write the partial results as they are computed.
// To change this code for a fractional 32x32, one needs
// to adj... |
tactcomplabs/xbgas-binutils-gdb | 8,708 | sim/testsuite/bfin/c_ldstiifp_ld_preg.s | //Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp
// Spec Reference: c_ldstiifp load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
... |
tactcomplabs/xbgas-binutils-gdb | 2,474 | sim/testsuite/bfin/c_logi2op_bitset.s | //Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp
// Spec Reference: Logi2op
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
//... |
tactcomplabs/xbgas-binutils-gdb | 7,512 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp
// Spec Reference: dsp32mac pair a1a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8... |
tactcomplabs/xbgas-binutils-gdb | 1,700 | sim/testsuite/bfin/c_dsp32mac_pair_mix.s | //Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp
// Spec Reference: dsp32mac pair mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00060007;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7,... |
tactcomplabs/xbgas-binutils-gdb | 1,452 | sim/testsuite/bfin/c_ldimmhalf_drhi.s | //Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp
// Spec Reference: ldimmhalf dreg hi
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.H = 0x0001;
R1.H = 0x0003;
R2.H = 0x0005;
R3.H = 0x0007;
R4.H = 0x0009;
R5.H = 0x000b;
R6.H = 0x000d;
R7.H = 0x000f;
CHECKREG r0, 0x0001... |
tactcomplabs/xbgas-binutils-gdb | 4,199 | sim/testsuite/bfin/c_logi2op_log_l_shft.s | //Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp
// Spec Reference: Logi2op <<=
# mach: bfin
.include "testutils.inc"
start
// Logical <<= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81... |
tactcomplabs/xbgas-binutils-gdb | 4,760 | sim/testsuite/bfin/c_dsp32shift_fdepx.s | //Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp
// Spec Reference: dsp32shift fdep x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x0... |
tactcomplabs/xbgas-binutils-gdb | 4,621 | sim/testsuite/bfin/c_dsp32mult_pair_s.s | //Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp
// Spec Reference: dsp32mult pair s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2... |
tactcomplabs/xbgas-binutils-gdb | 2,626 | sim/testsuite/bfin/m3.s | // MAC test program.
// Test basic edge values
// UNSIGNED FRACTIONAL mode U
// test ops: "+=" "-="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
// load r5=0xffffffff
loadsym P0, data0;
R0 = [ P0 ++ ];... |
tactcomplabs/xbgas-binutils-gdb | 1,555 | sim/testsuite/bfin/x1.s | # mach: bfin
.include "testutils.inc"
start
// 0.5
imm32 r0, 0x40004000;
imm32 r1, 0x40004000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x40004000;
checkreg r3, 0;
imm32 r1, 0x10001000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x28002800;
checkreg r3, 0x18001800;
R0 = R2 +|+... |
tactcomplabs/xbgas-binutils-gdb | 14,785 | sim/testsuite/bfin/se_lsetup_kill.S | //Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 4,520 | sim/testsuite/bfin/c_comp3op_dr_mix.s | //Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp
// Spec Reference: comp3op dregs mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12... |
tactcomplabs/xbgas-binutils-gdb | 5,243 | sim/testsuite/bfin/c_dsp32shift_expexp_r.s | //Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp
// Spec Reference: dsp32shift expadj / expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0800d001;
imm32 r1, 0x08000001;
imm32 r2, 0x0800d002;
imm32 r3, 0x0800d003;
imm32 r4, 0x0800d004;
imm32 r5, 0x0800d005;
imm32 r6, 0x080... |
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