repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 103,044 | sim/testsuite/bfin/se_undefinedinstruction3.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp
// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
# xfail: "missing checks in A0/A1 macfunc" *-*
#include "test.h"
.include "testutils.inc"
start
//
// ... |
tactcomplabs/xbgas-binutils-gdb | 6,382 | sim/testsuite/bfin/random_0026.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x4c60c810 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x7fffffff;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R5, 0x00007fff;
imm32 R7, 0x00000000;
R7.L = (A0 += R0.L * R5.L) (IH);
checkreg R7, 0x00007fff;
c... |
tactcomplabs/xbgas-binutils-gdb | 10,134 | sim/testsuite/bfin/random_0036.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x3ce04490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x7d8d8272;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe0004138;
dmm32 A1.x, 0x0000007f;
imm32 R0, 0x7d8e7fff;
imm32 R2, 0xffff8001;
A1 -= R2.L * R0.L (M), A0 ... |
tactcomplabs/xbgas-binutils-gdb | 4,524 | sim/testsuite/bfin/c_dsp32mult_pair_i.s | //Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp
// Spec Reference: dsp32mult pair i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2... |
tactcomplabs/xbgas-binutils-gdb | 5,429 | sim/testsuite/bfin/c_dsp32alu_rmm.s | //Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp
// Spec Reference: dsp32alu dreg = -/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm... |
tactcomplabs/xbgas-binutils-gdb | 1,045 | sim/testsuite/bfin/stk.s | # mach: bfin
.include "testutils.inc"
start
// load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
R0 = 1;
R1 = 2;
R2 = 3;
R3 ... |
tactcomplabs/xbgas-binutils-gdb | 1,313 | sim/testsuite/bfin/c_dsp32alu_a0a1s.s | //Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp
// Spec Reference: dsp32alu a0a1s
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0xf6667717;
imm32 r4, 0xe567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xb4445515;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 1,806 | sim/testsuite/bfin/se_all64bitg1opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 1)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach:... |
tactcomplabs/xbgas-binutils-gdb | 17,730 | sim/testsuite/bfin/se_loop_kill_dcr_01.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////... |
tactcomplabs/xbgas-binutils-gdb | 1,128 | sim/testsuite/bfin/lsetup.s | # Blackfin testcase for playing with LSETUP
# mach: bfin
.include "testutils.inc"
start
R0 = 0x123;
P0 = R0;
LSETUP (.L1, .L1) LC0 = P0;
.L1:
R0 += -1;
R1 = 0;
CC = R1 == R0;
IF CC JUMP 1f;
fail
1:
p0=10;
loadsym i0, _buf
imm32 r0, 0x12345678
LSETUP(.L2, .L3) lc0 = p0;
.L2:
[i0++] = r0;
.L3:
[i0++]... |
tactcomplabs/xbgas-binutils-gdb | 5,957 | sim/testsuite/bfin/c_dsp32alu_rl_rnd20_m.s | //Original:/testcases/core/c_dsp32alu_rl_rnd20_m/c_dsp32alu_rl_rnd20_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0xa789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x4b677717;
imm32 r4, 0x5678791b;
imm32 r5, 0xc789a71d;
imm32 r6, 0x74445515;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 3,646 | sim/testsuite/bfin/c_dsp32shift_amix.s | //Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp
// Spec Reference: dsp32shift ashift mix
# mach: bfin
.include "testutils.inc"
start
// Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1)
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Ashift : posi... |
tactcomplabs/xbgas-binutils-gdb | 8,456 | sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmrj_mvp/c_seq_ex3_ls_mmrj_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_... |
tactcomplabs/xbgas-binutils-gdb | 6,415 | sim/testsuite/bfin/c_interr_pending.S | //Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
... |
tactcomplabs/xbgas-binutils-gdb | 8,487 | sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
tactcomplabs/xbgas-binutils-gdb | 5,517 | sim/testsuite/bfin/c_interr_excpt.S | //Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp
// Spec Reference: interr excpt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // ini... |
tactcomplabs/xbgas-binutils-gdb | 7,980 | sim/testsuite/bfin/s14.s | // reg-based SHIFT test program.
// Test r4 = ASHIFT (r2 by rl3);
// Test r4 = LSHIFT (r2 by rl3);
# mach: bfin
.include "testutils.inc"
start
R0.L = 0x0001;
R0.H = 0x8000;
// arithmetic
// left by 31
// 8000 0001 -> 8000 0000
R7 = 0;
ASTAT = R7;
R3.L = 31;
R3.H = 0;
R6 = ASHIFT R0 BY R3.L;
DBGA ( R... |
tactcomplabs/xbgas-binutils-gdb | 5,833 | sim/testsuite/bfin/random_0029.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2030ca00 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0xdf7ce5c7;
dmm32 A1.x, 0xffffff9c;
imm32 R0, 0x098ecb70;
imm32 R1, 0x80000000;
R1.H = (A1 += R0.L * R1.H) (M, ISS2);
checkreg R1, 0x80000000;... |
tactcomplabs/xbgas-binutils-gdb | 2,651 | sim/testsuite/bfin/c_ccflag_a0a1.S | //Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp
// Spec Reference: ccflag a0-a1 (==, <, <=)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x12345778;
imm32 r1, 0x12345678;
imm32 r2, 0x056789ab;
imm32 r3, 0x80231345;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x... |
tactcomplabs/xbgas-binutils-gdb | 6,250 | sim/testsuite/bfin/c_dsp32mac_pair_a0_i.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp
// Spec Reference: dsp32mac pair a0 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
... |
tactcomplabs/xbgas-binutils-gdb | 6,888 | sim/testsuite/bfin/random_0019.S | # Test a few (W32) corner cases
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x68b0ca90 | _VS | _AV1S | _AV0S | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x70da33ff;
dmm32 A1.x, 0x0000000f;
imm32 R0, 0x5e29f819;
imm32 R1, 0x3f59520b;
A1 += R0.L * R1.L (M, W32);
checkreg A1.w, 0x... |
tactcomplabs/xbgas-binutils-gdb | 3,816 | sim/testsuite/bfin/c_ldimmhalf_pibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp
// Spec Reference: ldimmhalf p i b m l
# mach: bfin
.include "testutils.inc"
start
// set all reg=-1
//p0 =0x0123;
P1 = 0x1234 (X);
P2 = 0x2345 (X);
P3 = 0x3456 (X);
P4 = 0x4567 (X);
P5 = 0x5678 (X);
FP = 0x6789 (X);
SP = 0x789a... |
tactcomplabs/xbgas-binutils-gdb | 6,235 | sim/testsuite/bfin/se_bug_ui2.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
inclu... |
tactcomplabs/xbgas-binutils-gdb | 3,885 | sim/testsuite/bfin/c_alu2op_conv_toggle.s | //Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp
// Spec Reference: alu2op (~) toggle
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 5,142 | sim/testsuite/bfin/c_dsp32mac_dr_a1.s | //Original:/testcases/core/c_dsp32mac_dr_a1/c_dsp32mac_dr_a1.dsp
// Spec Reference: dsp32mac dr_a1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0... |
tactcomplabs/xbgas-binutils-gdb | 4,864 | sim/testsuite/bfin/c_interr_timer_tcount.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp
// Spec Reference: interrupt on HW TIMER tcount
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNT... |
tactcomplabs/xbgas-binutils-gdb | 6,107 | sim/testsuite/bfin/c_mmr_ppopm_illegal_adr.S | //Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp
// Spec Reference: mmr ppopm illegal address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef ... |
tactcomplabs/xbgas-binutils-gdb | 4,358 | sim/testsuite/bfin/c_dsp32mult_pair.s | //Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp
// Spec Reference: dsp32mult pair
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029... |
tactcomplabs/xbgas-binutils-gdb | 8,487 | sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
I... |
tactcomplabs/xbgas-binutils-gdb | 1,232 | sim/testsuite/bfin/stk6.s | // setup a dummy stack and put values in memory 0,1,2,3...n
// then restore registers with pop instruction.
# mach: bfin
.include "testutils.inc"
start
SP += -12;
P1 = SP;
R1 = 0;
P5.L = 0xdead;
SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5
P4 = (8+6); // 8 data re... |
tactcomplabs/xbgas-binutils-gdb | 3,770 | sim/testsuite/bfin/c_regmv_dr_dr.s | //Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp
// Spec Reference: regmv dreg-to-dreg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to R-reg move
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000... |
tactcomplabs/xbgas-binutils-gdb | 4,591 | sim/testsuite/bfin/c_dsp32mult_pair_is.s | //Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp
// Spec Reference: dsp32mult pair is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0... |
tactcomplabs/xbgas-binutils-gdb | 6,542 | sim/testsuite/bfin/c_interr_timer_tscale.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp
// Spec Reference: interrupt on HW TIMER tscale
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNT... |
tactcomplabs/xbgas-binutils-gdb | 3,011 | sim/testsuite/bfin/c_dsp32mac_pair_a1_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp
// Spec Reference: dsp32mac pair a1 M MNOP
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x63547abd;
imm32 r1, 0x86bc8ec7;
imm32 r2, 0xa86956... |
tactcomplabs/xbgas-binutils-gdb | 4,425 | sim/testsuite/bfin/c_alu2op_divq.s | //Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp
// Spec Reference: alu2op divide q
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R... |
tactcomplabs/xbgas-binutils-gdb | 1,500 | sim/testsuite/bfin/random_0003.S | # Test for ASTAT AN setting when overflows occur
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x18204a80 | _AV1S | _AV0 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x1098e30b;
dmm32 A1.x, 0x0000001f;
imm32 R0, 0x440ed6ae;
imm32 R5, 0x3272c296;
R0.H = (A1 += R0.L * R5.H);
... |
tactcomplabs/xbgas-binutils-gdb | 1,211 | sim/testsuite/bfin/c_dsp32alu_absabs.s | //Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp
// Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6,... |
tactcomplabs/xbgas-binutils-gdb | 9,511 | sim/testsuite/bfin/c_dsp32shift_rot.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp
// Spec Reference: dsp32shift rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x01230001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;... |
tactcomplabs/xbgas-binutils-gdb | 8,707 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6... |
tactcomplabs/xbgas-binutils-gdb | 11,608 | sim/testsuite/bfin/c_ldstidxl_ld_preg.s | //Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp
// Spec Reference: c_ldstidxl load dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
... |
tactcomplabs/xbgas-binutils-gdb | 3,526 | sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s | //Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp
// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc12486... |
tactcomplabs/xbgas-binutils-gdb | 5,343 | sim/testsuite/bfin/c_ldst_st_p_d.s | //Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp
// Spec Reference: c_ldst st_p_d
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7... |
tactcomplabs/xbgas-binutils-gdb | 8,907 | sim/testsuite/bfin/se_cc_kill.S | //Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp
// Description:
// Verify CC kill under the following condition:
//
// (1) CC = AZ killed in WB
// (2) CC = AN killed in WB
// (3) CC = AC killed in WB
// (4) CC = AV0 killed in WB
// (5) CC = AV1 killed in WB
... |
tactcomplabs/xbgas-binutils-gdb | 1,470 | sim/testsuite/bfin/c_ldimmhalf_h_dr.s | //Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp
// Spec Reference: ldimmhalf h dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.H = 0x0000;
R1.H = 0x0002;
R2.H = 0x0004;
R3.H = 0x0006;
R4.H = 0x0008;
R5.H = 0x000a;
R6.H = 0x000c;
R7.H = 0x000e;
CHECKREG r0, 0x0000... |
tactcomplabs/xbgas-binutils-gdb | 5,448 | sim/testsuite/bfin/c_ldst_st_p_d_b.s | //Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp
// Spec Reference: c_ldst st_p d b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6... |
tactcomplabs/xbgas-binutils-gdb | 2,790 | sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s | //Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp
// Spec Reference: compi2opd dregs += imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += -1;
R2 += -2;
R3 += -3;
R4 += -4;
R5 += -5;
R6 += -6;
R7 += -7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFF... |
tactcomplabs/xbgas-binutils-gdb | 8,716 | sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_rti_lsmmrj_mvp/c_seq_wb_rti_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( rti ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
tactcomplabs/xbgas-binutils-gdb | 1,478 | sim/testsuite/bfin/c_pushpopmultiple_preg.s | //Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp
// Spec Reference: pushpopmultiple preg
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
P1 = 0xa1 (X);
P2 = 0xa2 (X);
P3 = 0xa3 (X);
P4 = 0xa4 (X);
P5 = 0xa5 (X);
[ -- SP ] = ( P5:1 );
P1 =... |
tactcomplabs/xbgas-binutils-gdb | 3,385 | sim/testsuite/bfin/c_dsp32shiftim_amix.s | //Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: mix
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// Ashift : positive data, count (+)=left (half reg)
imm32 r0, 0... |
tactcomplabs/xbgas-binutils-gdb | 5,459 | sim/testsuite/bfin/c_ldst_ld_d_p_xb.s | //Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp
// Spec Reference: c_ldst ld d [p] xb
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 8 bits from me... |
tactcomplabs/xbgas-binutils-gdb | 3,054 | sim/testsuite/bfin/c_pushpopmultiple_dreg.s | //Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp
// Spec Reference: pushpopmultiple dreg
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
[ -- SP ] =... |
tactcomplabs/xbgas-binutils-gdb | 11,958 | sim/testsuite/bfin/dbg_brprd_ntkn_src_kill.S | //Original:/proj/frio/dv/testcases/debug/dbg_brprd_ntkn_src_kill/dbg_brprd_ntkn_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a
// branch source instruction that is predicted but not taken getting killed
// at each stage in the pipe. The test consists of 8 instances of an EXCPT
// ... |
tactcomplabs/xbgas-binutils-gdb | 4,740 | sim/testsuite/bfin/s21.s | // Test A0 = ROT (A0 by imm6);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
// rot
// left by 1
// 00 8000 0001 -> 01 0000 0002 cc=0
R0.L = 0x0001;
R0.H = 0x8000;
R7 = 0;
CC = R7;
A1 = A0 = 0;
A0.w = R0;
A0 = ROT A0 BY 1;
R1 = A0.w;
DBGA ( R1.L , 0x0002 );
D... |
tactcomplabs/xbgas-binutils-gdb | 1,157 | sim/testsuite/bfin/m11.s | // Test extraction from accumulators:
// SCALE in SIGNED FRACTIONAL mode
# mach: bfin
.include "testutils.inc"
start
// load r0=0x3fff0000
// load r1=0x0fffc000
// load r2=0x7ff00000
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];... |
tactcomplabs/xbgas-binutils-gdb | 1,050 | sim/testsuite/bfin/c_brcc_brf_nbp.s | //Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp
// Spec Reference: brcc brf no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
... |
tactcomplabs/xbgas-binutils-gdb | 4,780 | sim/testsuite/bfin/c_dsp32mult_dr_m_t.s | //Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp
// Spec Reference: dsp32mult single dr munop t
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm... |
tactcomplabs/xbgas-binutils-gdb | 1,626 | sim/testsuite/bfin/c_cc_flag_ccmv_depend.S | //Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp
// Spec Reference: ccflag followed by ccmv (# stalls)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;... |
tactcomplabs/xbgas-binutils-gdb | 5,467 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_b.s | //Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp
// Spec Reference: c_ldst ld d [p++] b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = B [ P5 ++ ... |
tactcomplabs/xbgas-binutils-gdb | 9,410 | sim/testsuite/bfin/lmu_excpt_default.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp
// Description: Default protection checks (CPLB disabled)
// - MMR access in User mode
// - DAG1 Access MMRs (supv/user mode, read/write)
// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write)
# mach: bfin
# sim: --environmen... |
tactcomplabs/xbgas-binutils-gdb | 8,468 | sim/testsuite/bfin/random_0024.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ);
imm32 R2, 0x00000000;
imm32 R4, 0x00000000;
imm32 R7, 0x00000000;
R2 = ASHIFT R7 BY R4.L (S);
checkreg ASTAT, (0x3ce00800 | _VS | _AV1S | _AV0S | _AQ | _AZ);
checkreg R2, 0x00000000;
che... |
tactcomplabs/xbgas-binutils-gdb | 7,027 | sim/testsuite/bfin/c_ldst_ld_p_p_mm.s | //Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp
// Spec Reference: c_ldst ld p [p--]
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
load... |
tactcomplabs/xbgas-binutils-gdb | 3,485 | sim/testsuite/bfin/dotproduct2.s | /* Vector Dot Product
* This program computes a simple vector dot product using hard
* wired input buffers of 128 samples each. These values are in
* 1.15 signed .
*/
# mach: bfin
.include "testutils.inc"
start
// load buffer addresses into pointer regs
loadsym I0, data0;
loadsym I1, data1;
// loop contro... |
tactcomplabs/xbgas-binutils-gdb | 1,212 | sim/testsuite/bfin/c_dsp32shiftim_af_s.s | //Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift saturated
imm32 r0, 0x81230001;
imm32 r1, 0x19345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x3ed6789a;
imm32 r4, 0x85d789ab;
imm32 r5, 0x967f9abc;
imm32 r6,... |
tactcomplabs/xbgas-binutils-gdb | 6,034 | sim/testsuite/bfin/c_dsp32alu_minmin.s | //Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp
// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x2a445345;
imm32 r3, 0x46657717;
imm32 r4, 0xd567e91b;
imm32 r5, 0x6789af1d;
imm32 r6,... |
tactcomplabs/xbgas-binutils-gdb | 6,034 | sim/testsuite/bfin/c_dsp32alu_maxmax.s | //Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp
// Spec Reference: dsp32alu dregs = max / max ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xe6657717;
imm32 r4, 0x5a67891b;
imm32 r5, 0x67b9ab1d;
imm32 r6,... |
tactcomplabs/xbgas-binutils-gdb | 2,263 | sim/testsuite/bfin/se_kills2.S | //Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp
// Description: Test se_kill for all supported types of RTL1 instructions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(symtable... |
tactcomplabs/xbgas-binutils-gdb | 8,703 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x... |
tactcomplabs/xbgas-binutils-gdb | 4,307 | sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s | //Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp
// Spec Reference: dagmodik l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000100e;
imm32 b1, 0x0000110c;... |
tactcomplabs/xbgas-binutils-gdb | 5,107 | sim/testsuite/bfin/c_dsp32shift_expadj_l.s | //Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp
// Spec Reference: dsp32shift expadj rl
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
i... |
tactcomplabs/xbgas-binutils-gdb | 2,963 | sim/testsuite/bfin/c_loopsetup_nested_prelc.s | //Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp
// Spec Reference: loopsetup nested preload lc0 lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x12;
R3 = 0x14;... |
tactcomplabs/xbgas-binutils-gdb | 3,313 | sim/testsuite/bfin/a2.s | # mach: bfin
.include "testutils.inc"
start
loadsym P0, middle;
R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 );
R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 );
R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 );
R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 );
R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 );
R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 );
R0 = [ P0 + 24 ]; D... |
tactcomplabs/xbgas-binutils-gdb | 4,342 | sim/testsuite/bfin/c_dsp32shift_a0alr.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp
// Spec Reference: dsp32shift a0 ashift, lshift, rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x11140000;
imm32 r1, 0x012C003E;
imm32 r2, 0x81359E24;
imm32 r3, 0x81459E24;
imm32 r4, 0xD159E268;
... |
tactcomplabs/xbgas-binutils-gdb | 9,721 | sim/testsuite/bfin/c_ldstii_ld_preg.s | //Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp
// Spec Reference: c_ldstii load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loads... |
tactcomplabs/xbgas-binutils-gdb | 2,025 | sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s | //Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp
// Spec Reference: ldimmhalf lz & hi dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0001 (Z);
R0.H = 0x0000;
R1 = 0x0003 (Z);
R1.H = 0x0002;
R2 = 0x0005 (Z);
R2.H = 0x0004;
R3 = 0x0007 (Z);
R3.H = 0x0006;
... |
tactcomplabs/xbgas-binutils-gdb | 3,795 | sim/testsuite/bfin/c_ccflag_dr_imm3.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp
// Spec Reference: ccflag dr-imm3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00000002;
imm32 r2, 0x00000003;
imm32 r3, 0x00000004;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32... |
tactcomplabs/xbgas-binutils-gdb | 6,094 | sim/testsuite/bfin/c_dsp32mult_dr_u.s | //Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp
// Spec Reference: dsp32mult single dr u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd... |
tactcomplabs/xbgas-binutils-gdb | 1,469 | sim/testsuite/bfin/c_ldimmhalf_l_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp
// Spec Reference: ldimmhalf l preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
INIT_P_REGS -1;
imm32 sp, 0xffffffff;
imm32 fp, 0xffffffff;
// test Preg
P1.L = 0x0003;
P2.L = 0x0005;
P3.L = 0x0007;
P4.L = 0x0009;
... |
tactcomplabs/xbgas-binutils-gdb | 7,255 | sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp
// Spec Reference: sequencer stage ex2 ( brcc (mis-pred)+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include... |
tactcomplabs/xbgas-binutils-gdb | 1,209 | sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp
// Spec Reference: ccmv !cc dpreg = dpreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x138d2301;
imm32 r1, 0x20421053;
imm32 r2, 0x3f051405;
imm32 r3, 0x40b66507;
imm32 r4, 0x50487709;
imm32 r5, 0x60... |
tactcomplabs/xbgas-binutils-gdb | 4,824 | sim/testsuite/bfin/random_0032.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x74308400 | _VS | _AV1S | _AV0S | _CC | _AN);
dmm32 A0.w, 0x5d4cf98c;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0xba16ffff;
imm32 R4, 0x8000109d;
imm32 R6, 0x8000b212;
R6.L = (A0 -= R4.L * R0.L) (IH);
checkreg R6, 0x80008000;
checkreg A0.w... |
tactcomplabs/xbgas-binutils-gdb | 2,286 | sim/testsuite/bfin/c_loopsetup_prelc.s | //Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp
// Spec Reference: loopsetup preload lc0 lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = ... |
tactcomplabs/xbgas-binutils-gdb | 9,518 | sim/testsuite/bfin/lmu_excpt_prot0.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp
// Description: LMU protection exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test ... |
tactcomplabs/xbgas-binutils-gdb | 5,431 | sim/testsuite/bfin/c_dsp32alu_rpp.s | //Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp
// Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm... |
tactcomplabs/xbgas-binutils-gdb | 5,667 | sim/testsuite/bfin/c_mode_supervisor.S | //Original:/proj/frio/dv/testcases/core/c_mode_supervisor/c_mode_supervisor.dsp
// Spec Reference: mode_supervisor
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); ... |
tactcomplabs/xbgas-binutils-gdb | 2,387 | sim/testsuite/bfin/m4.s | // MAC test program.
// Test basic edge values
// SIGNED INTEGER mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
... |
tactcomplabs/xbgas-binutils-gdb | 10,985 | sim/testsuite/bfin/ashift.s | # Blackfin testcase for ashift
# mach: bfin
.include "testutils.inc"
.macro ashift_test in:req, shift:req, out:req, opt
r0 = \in (Z);
r2.L = \shift;
r2.h = ASHIFT R0.L BY R2.L \opt;
DBGA (r2.h, \out);
.endm
start
/*
* 16-bit ashift and lshift uses a 6-bit signed magnitude, which
* gives a range from -... |
tactcomplabs/xbgas-binutils-gdb | 5,875 | sim/testsuite/bfin/c_interr_timer_reload.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp
// Spec Reference: interrupt on HW TIMER auto-reload
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef... |
tactcomplabs/xbgas-binutils-gdb | 3,232 | sim/testsuite/bfin/s18.s | // Immediate dual 16b SHIFT test program.
// Test r4 = ASHIFT/ASHIFT (r2 by 10);
// Test r4 = ASHIFT/ASHIFT (r2 by 10) S;
// Test r4 = LSHIFT/LSHIFT (r2 by 10);
# mach: bfin
.include "testutils.inc"
start
// arithmetic
// left by largest positive magnitude of 15 (0xf)
// 8001 -> 8000
R7 = 0;
ASTAT = R7;
... |
tactcomplabs/xbgas-binutils-gdb | 6,606 | sim/testsuite/bfin/c_dsp32alu_rrppmm.s | //Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5597891b;
imm32 r5, 0x6989ab1d;
... |
tactcomplabs/xbgas-binutils-gdb | 2,885 | sim/testsuite/bfin/c_loopsetup_nested_top.s | //Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp
// Spec Reference: loopsetup nested top
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 3;
P2 = 4;
P3 = 5;
P4 = 6;
P5 = 7;
SP = 8;
FP = 9;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
... |
tactcomplabs/xbgas-binutils-gdb | 3,122 | sim/testsuite/bfin/c_dsp32mac_pair_a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp
// Spec Reference: dsp32mac pair a0 m (M, MNOP)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa... |
tactcomplabs/xbgas-binutils-gdb | 4,507 | sim/testsuite/bfin/c_dsp32shift_af_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// ashift : mix data, count (+)= (half reg)
// d_reg = ashift (d BY d_lo)
// R... |
tactcomplabs/xbgas-binutils-gdb | 2,290 | sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s | //Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp
// Spec Reference: ccmv !cc dreg = dreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x808d2301;
imm32 r1, 0x90021053;
imm32 r2, 0x21041405;
imm32 r3, 0x60261507;
imm32 r4, 0x50447609;
imm32 r5, 0xdfe5500b;
imm32 r6, 0x2a0... |
tactcomplabs/xbgas-binutils-gdb | 5,681 | sim/testsuite/bfin/iir.s | # mach: bfin
// GENERIC BIQUAD:
// ---------------
// x ---------+---------|---------+-------y
// | |t1 |
// | D |
// | a1 | b1 |
// +---<-----|---->----+
// | | |
// | D | ... |
tactcomplabs/xbgas-binutils-gdb | 4,334 | sim/testsuite/bfin/c_interr_loopsetup_stld.S | //Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp
// Spec Reference: interrupt loopsetup_ldst
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
A0 = 0; // reset accumulators
A1 = 0;
P1 = 3;
P2 = 4;
LD32(r0, 0x00200005);
LD32(r1, 0x00300010);
LD32... |
tactcomplabs/xbgas-binutils-gdb | 7,522 | sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc... |
tactcomplabs/xbgas-binutils-gdb | 3,017 | sim/testsuite/bfin/s11.s | # mach: bfin
// Shift test program.
// Test instructions
// RL0 = CC = BXOR (A0 AND R1) << 1;
// RL0 = CC = BXOR A0 AND R1;
// A0 <<=1 (BXOR A0 AND A1 CC);
// RL3 = CC = BXOR A0 AND A1 CC;
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// RL0 = CC = BXOR (A0 AND R1) << 1;
R0.L = 0x1000;
R0.H... |
tactcomplabs/xbgas-binutils-gdb | 1,426 | sim/testsuite/bfin/c_br_preg_stall_ac.s | //Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
/* This test likes to assume the current [SP] is valid */
SP += -12;
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x0000... |
tactcomplabs/xbgas-binutils-gdb | 3,933 | sim/testsuite/bfin/c_dsp32mult_pair_m_i.s | //Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp
// Spec Reference: dsp32mult pair MUNOP i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 14,295 | sim/testsuite/bfin/c_ldst_st_p_d_pp.s | //Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp
// Spec Reference: c_ldst st_p++ d
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r... |
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