repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 3,226 | sim/testsuite/bfin/c_dsp32mac_pair_a0.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0/c_dsp32mac_pair_a0.dsp
// Spec Reference: dsp32mac pair a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 ... |
tactcomplabs/xbgas-binutils-gdb | 4,925 | sim/testsuite/bfin/c_progctrl_excpt.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_excpt/c_progctrl_excpt.dsp
// Spec Reference: progctrl excpt uimm4
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0)... |
tactcomplabs/xbgas-binutils-gdb | 2,077 | sim/testsuite/bfin/PN_generator.s | # mach: bfin
// GENERIC PN SEQUENCE GENERATOR
// Linear Feedback Shift Register
// -------------------------------
// This solution implements an LFSR by applying an XOR reduction
// function to the 40 bit accumulator, XORing the contents of the
// CC bit, shifting by one the accumulator, and inserting the
// resultin... |
tactcomplabs/xbgas-binutils-gdb | 6,260 | sim/testsuite/bfin/c_dspldst_st_drlo_ipp.s | //Original:testcases/core/c_dspldst_st_drlo_ipp/c_dspldst_st_drlo_ipp.dsp
// Spec Reference: c_dspldst st_drlo_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
im... |
tactcomplabs/xbgas-binutils-gdb | 5,190 | sim/testsuite/bfin/c_interr_pending_2.S | //Original:/proj/frio/dv/testcases/core/c_interr_pending_2/c_interr_pending_2.dsp
// Spec Reference: interr pending (raise)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
#ifnde... |
tactcomplabs/xbgas-binutils-gdb | 4,916 | sim/testsuite/bfin/c_dsp32mult_dr_m_iutsh.s | //Original:/testcases/core/c_dsp32mult_dr_m_iutsh/c_dsp32mult_dr_m_iutsh.dsp
// Spec Reference: dsp32mult single dr munop iu tu is ih
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 6,388 | sim/testsuite/bfin/random_0031.S | # Check that VS in ASTAT is set with add/sub insns (and not just V)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x27f3a149;
imm32 R3, 0x3cae7c58;
imm32 R4, 0x33c97634;
R3.H = R0.L - R4.H (NS);
checkre... |
tactcomplabs/xbgas-binutils-gdb | 3,142 | sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft_sn.S | //Original:/proj/frio/dv/testcases/core/c_cc_regmvlogi_mvbrsft_sn/c_cc_regmvlogi_mvbrsft_sn.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
INIT_I_REGS 0;
INIT_M_REGS 0;
INIT_L_REGS 0;
INIT_B_REGS 0;
INIT_R_REGS 0;
INI... |
tactcomplabs/xbgas-binutils-gdb | 1,202 | sim/testsuite/bfin/m17.s | // Test various moves to single register
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7fffffff
// load r1=0x00ffffff
// load r2=0xf0000000
// load r3=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
// extract only to high register
R5 = 0;
R4 = 0;
A... |
tactcomplabs/xbgas-binutils-gdb | 1,709 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft.s | //Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5,... |
tactcomplabs/xbgas-binutils-gdb | 8,846 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_rp.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_rp/c_dsp32shiftim_ahalf_rp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;... |
tactcomplabs/xbgas-binutils-gdb | 10,449 | sim/testsuite/bfin/se_stall_if2.S | //Original:/proj/frio/dv/testcases/seq/se_stall_if2/se_stall_if2.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
... |
tactcomplabs/xbgas-binutils-gdb | 9,974 | sim/testsuite/bfin/a3.s | # mach: bfin
.include "testutils.inc"
start
loadsym P1, middle;
R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 );
R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 );
R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 );
R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 );
R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 );
R0 = W [ P1 + -12 ] ... |
tactcomplabs/xbgas-binutils-gdb | 9,934 | sim/testsuite/bfin/c_dsp32shift_lhalf_rn.s | //Original:/testcases/core/c_dsp32shift_lhalf_rn/c_dsp32shift_lhalf_rn.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 1,598 | sim/testsuite/bfin/c_br_preg_killed_ex1.s | //Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x000... |
tactcomplabs/xbgas-binutils-gdb | 6,439 | sim/testsuite/bfin/a11.S | // Test ALU RND RND12 RND20
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R7 = 0;
ASTAT = R7;
// 7ffffff0
// + 00008000
// -> 7fff0000
R0 = 0xfff0 (Z);
R0.H = 0x7fff;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff;
CHECKREG R0, (_VS|_V|_V_COPY);
// 7ffffff0
// + 00008000
// ->... |
tactcomplabs/xbgas-binutils-gdb | 4,815 | sim/testsuite/bfin/c_dsp32mac_dr_a1_m.s | //Original:/testcases/core/c_dsp32mac_dr_a1_m/c_dsp32mac_dr_a1_m.dsp
// Spec Reference: dsp32mac dr a1 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0... |
tactcomplabs/xbgas-binutils-gdb | 3,933 | sim/testsuite/bfin/c_dsp32mult_pair_m_u.s | //Original:/testcases/core/c_dsp32mult_pair_m_u/c_dsp32mult_pair_m_u.dsp
// Spec Reference: dsp32mult pair MUNOP u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 2,857 | sim/testsuite/bfin/c_dsp32mac_dr_a0.s | //Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp
// Spec Reference: dsp32mac dr_a0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcaba5127;
imm32 r2, 0x13a46705;
imm32 r3, 0x000a0007;
imm32 r4, 0x90abad09;
imm32 r5, 0x10aceadb;
imm32 r6, 0x000c00ad;
imm32 r7, 0x12467... |
tactcomplabs/xbgas-binutils-gdb | 4,973 | sim/testsuite/bfin/dbg_tr_tbuf0.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
// This test embeds .text offsets, s... |
tactcomplabs/xbgas-binutils-gdb | 2,063 | sim/testsuite/bfin/c_compi2opp_pr_add_i7_p.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_p/c_compi2opp_pr_add_i7_p.dsp
// Spec Reference: compi2opp pregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 fp, 0x00000000;
P1 += 1;
P2 += 2;
P3 += 3;
P4 += 4;
P5 += 5;
FP += 7;
CHECKREG p1, 0x00000001;
... |
tactcomplabs/xbgas-binutils-gdb | 1,280 | sim/testsuite/bfin/c_br_preg_stall_ex1.s | //Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000... |
tactcomplabs/xbgas-binutils-gdb | 9,135 | sim/testsuite/bfin/se_all16bitopcodes.S | /*
* Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace
* we track all instructions which cause some sort of exception when run from
* userspace, this is normally EXCAUSE :
* - 0x21 : illegal instruction
* - 0x22 : illegal instruction combination
* - 0x2e : use of supervisor resource fro... |
tactcomplabs/xbgas-binutils-gdb | 1,412 | sim/testsuite/bfin/cc5.S | // ALU test program.
// Test instructions reg = (A0+=A1)
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// add accums and transfer result
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R6 =... |
tactcomplabs/xbgas-binutils-gdb | 10,413 | sim/testsuite/bfin/se_loop_ppm.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm/se_loop_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
//... |
tactcomplabs/xbgas-binutils-gdb | 4,133 | sim/testsuite/bfin/c_alu2op_conv_xb.s | //Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp
// Spec Reference: alu2op convert xb
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89... |
tactcomplabs/xbgas-binutils-gdb | 2,901 | sim/testsuite/bfin/c_dsp32mac_dr_a0_is.s | //Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp
// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 6,378 | sim/testsuite/bfin/c_interr_disable.S | //Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
... |
tactcomplabs/xbgas-binutils-gdb | 4,804 | sim/testsuite/bfin/c_ccflag_pr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr/c_ccflag_pr_pr.dsp
// Spec Reference: ccflag pr-pr
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
INIT_R_REGS 0;
//imm32 p0, 0x00110022;
imm32 p1, 0x00110022;
imm32 p2, 0x00330044;
imm32 p3, 0x00550066;
imm32 p4, 0x00770088;
imm32 p5, 0x009900aa;
... |
tactcomplabs/xbgas-binutils-gdb | 6,096 | sim/testsuite/bfin/c_dsp32mac_pair_a1_i.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp
// Spec Reference: dsp32mac pair a1 I
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
... |
tactcomplabs/xbgas-binutils-gdb | 4,130 | sim/testsuite/bfin/c_alu2op_conv_b.s | //Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp
// Spec Reference: alu2op convert b
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abc... |
tactcomplabs/xbgas-binutils-gdb | 6,340 | sim/testsuite/bfin/se_usermode_protviol.S | //Original:/proj/frio/dv/testcases/seq/se_usermode_protviol/se_usermode_protviol.dsp
// Description: User mode "Illegal Use Supervsor Resource" Exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck... |
tactcomplabs/xbgas-binutils-gdb | 1,549 | sim/testsuite/bfin/s12.s | // Shifter test program.
// Test instructions
// RL5 = EXPADJ R4 BY RL2;
# mach: bfin
.include "testutils.inc"
start
R0.L = 30; // large norm of small value
R0.H = 1; // make sure high half is not used
R1.L = 0x0000;
R1.H = 0x1000; // small norm (2) of large value
R7.L = EXPADJ( R1 , R0.L );
DBGA ( R7.L , ... |
tactcomplabs/xbgas-binutils-gdb | 5,504 | sim/testsuite/bfin/saatest.s | # mach: bfin
.include "testutils.inc"
start
I0 = 0 (X);
I1 = 0 (X);
A0 = A1 = 0;
init_r_regs 0;
ASTAT = R0;
// This section of code will test the SAA instructions and sum of accumulators;
loadsym I0, tstvecI;
R0 = [ I0 ++ ];
R2 = [ I0 ++ ];
// +++++++++++++++ TG11.001 +++++++++++++ //
// ... |
tactcomplabs/xbgas-binutils-gdb | 1,536 | sim/testsuite/bfin/c_ldimmhalf_lz_dr.s | //Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp
// Spec Reference: ldimmhalf lz dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0001 (Z);
R1 = 0x0003 (Z);
R2 = 0x0005 (Z);
R3 = 0x0007 (Z);
R4 = 0x0009 (Z);
R5 = 0x000b (Z);
R6 = 0x000d (Z);
R7 = 0x000f (Z);
C... |
tactcomplabs/xbgas-binutils-gdb | 3,115 | sim/testsuite/bfin/s9.s | // Test rl3 = ashift (rh0 by 7);
// Test rl3 = lshift (rh0 by 7);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
R0 = 0;
ASTAT = R0;
R0.L = 0x1;
R0.H = 0x1;
R7.L = R0.L << 4;
DBGA ( R7.L , 0x0010 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.... |
tactcomplabs/xbgas-binutils-gdb | 1,310 | sim/testsuite/bfin/c_dsp32shiftim_ahh_s.s | //Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789ab... |
tactcomplabs/xbgas-binutils-gdb | 4,653 | sim/testsuite/bfin/c_logi2op_bittgl.s | //Original:/testcases/core/c_logi2op_bittgl/c_logi2op_bittgl.dsp
// Spec Reference: Logi2op functions: bittgl
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 1,464 | sim/testsuite/bfin/c_ldimmhalf_lz_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lz_pr/c_ldimmhalf_lz_pr.dsp
// Spec Reference: ldimmhalf lz preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Preg
P1 = 0x0003 (Z);
P2 = 0x0005 (Z);
P3 = 0x0007 (Z);
P4 = 0x0009 (Z);
P5 = 0x000b (Z);
FP = 0x000d (Z);
SP = 0x000f (Z);... |
tactcomplabs/xbgas-binutils-gdb | 2,078 | sim/testsuite/bfin/c_dagmodik_lz_inc_dec.s | //Original:/testcases/core/c_dagmodik_lz_inc_dec/c_dagmodik_lz_inc_dec.dsp
// Spec Reference: dagmodik L=0, I incremented & decremented
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001200;
imm32 i3, 0x00001300;
imm32 m0, 0x00000000;
imm32 m1, ... |
tactcomplabs/xbgas-binutils-gdb | 1,967 | sim/testsuite/bfin/c_dsp32alu_byteop2.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop2/c_dsp32alu_byteop2.dsp
// Spec Reference: dsp32alu byteop2
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444... |
tactcomplabs/xbgas-binutils-gdb | 5,109 | sim/testsuite/bfin/c_dsp32shift_expadj_h.s | //Original:/testcases/core/c_dsp32shift_expadj_h/c_dsp32shift_expadj_h.dsp
// Spec Reference: dsp32shift expadj rh
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x80000008;
imm32 r1, 0x80010008;
imm32 r2, 0x80020008;
imm32 r3, 0x80030008;
imm32 r4, 0x80040008;
imm32 r5, 0x80050008;
imm32 r6, 0x80060008;
i... |
tactcomplabs/xbgas-binutils-gdb | 2,210 | sim/testsuite/bfin/c_ccmv_ncc_pr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_pr_pr/c_ccmv_ncc_pr_pr.dsp
// Spec Reference: ccmv !cc preg = preg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 p1, 0xd0021053;
imm32 p2, 0x2f041405;
imm32 p3, 0x60b61507;
imm32 p4, 0x50487609;
imm32 p5, 0x3005900b;
imm32 sp, 0x2a0c... |
tactcomplabs/xbgas-binutils-gdb | 3,322 | sim/testsuite/bfin/s15.s | // reg-based SHIFT test program.
# mach: bfin
.include "testutils.inc"
start
// Test FEXT with no sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0810; // pos=8 len=16
R7 = EXTRACT( R0, R1.L ) (Z);
DBGA ( R7.L , 0x34de );
DBGA ( R7.H , 0 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0814; // pos=8 le... |
tactcomplabs/xbgas-binutils-gdb | 9,027 | sim/testsuite/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_wb_rtx_lsmmrj_mvp/c_seq_wb_rtx_lsmmrj_mvp.dsp
// Spec Reference: sequencer:wb ( rtx ldst mmr jump regmv pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.in... |
tactcomplabs/xbgas-binutils-gdb | 7,160 | sim/testsuite/bfin/c_ldstpmod_ld_dr_hi.s | //Original:testcases/core/c_ldstpmod_ld_dr_hi/c_ldstpmod_ld_dr_hi.dsp
// Spec Reference: c_ldstpmod load dr hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = ... |
tactcomplabs/xbgas-binutils-gdb | 5,431 | sim/testsuite/bfin/c_logi2op_log_r_shft.s | //Original:/testcases/core/c_logi2op_log_r_shft/c_logi2op_log_r_shft.dsp
// Spec Reference: Logi2op >>=
# mach: bfin
.include "testutils.inc"
start
// Logical >>= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81... |
tactcomplabs/xbgas-binutils-gdb | 4,311 | sim/testsuite/bfin/c_dagmodik_lnz_imgebl.s | //Original:/testcases/core/c_dagmodik_lnz_imgebl/c_dagmodik_lnz_imgebl.dsp
// Spec Reference: dagmodik l not zero & i+m >= b+l
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x00001000;
imm32 b1, 0x000010... |
tactcomplabs/xbgas-binutils-gdb | 3,031 | sim/testsuite/bfin/dotproduct.s | # Blackfin testcase for a simple vector dot product using hard
# wired input buffers of 128 samples each. These values are in
# 1.15 signed .
# mach: bfin
.include "testutils.inc"
start
loadsym P0, _buf0
loadsym P1, _buf1
/* loop control
* number of loop iterations is 2^N with r4|=1<<N
* to process 128 sa... |
tactcomplabs/xbgas-binutils-gdb | 6,180 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_xh.s | //Original:testcases/core/c_ldst_ld_d_p_mm_xh/c_ldst_ld_d_p_mm_xh.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 ... |
tactcomplabs/xbgas-binutils-gdb | 5,771 | sim/testsuite/bfin/se_excpt_dagprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp
// Description: EXCPT instruction combined with DAG Misaligned Access
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(m... |
tactcomplabs/xbgas-binutils-gdb | 7,367 | sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x4666771... |
tactcomplabs/xbgas-binutils-gdb | 1,711 | sim/testsuite/bfin/c_loopsetup_preg_div2_lc1.s | //Original:/testcases/core/c_loopsetup_preg_div2_lc1/c_loopsetup_preg_div2_lc1.dsp
// Spec Reference: loopsetup preg lc1 / 2
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40... |
tactcomplabs/xbgas-binutils-gdb | 5,247 | sim/testsuite/bfin/acc-rot.s | # Blackfin testcase for Accumulator Rotates (ROT)
# mach: bfin
.include "testutils.inc"
.macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req
imm32 R0, \val_w
imm32 R1, \val_x
R2 = \cc;
R3 = \shift
\acc\().W = R0;
\acc\().X = R1;
CC = R2;
.endm
.macro atest_check acc:req, exp_x:req, exp_w:re... |
tactcomplabs/xbgas-binutils-gdb | 1,668 | sim/testsuite/bfin/c_loopsetup_topbotcntr.s | //Original:/proj/frio/dv/testcases/core/c_loopsetup_topbotcntr/c_loopsetup_topbotcntr.dsp
// Spec Reference: loopsetup top bot counter
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x08;
loadsym R6, start1;
loadsym R7, end1;
... |
tactcomplabs/xbgas-binutils-gdb | 6,219 | sim/testsuite/bfin/se_bug_ui3.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui3/se_bug_ui3.dsp
// Description: 32 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
inclu... |
tactcomplabs/xbgas-binutils-gdb | 2,356 | sim/testsuite/bfin/c_regmv_pr_dr.s | //Original:/testcases/core/c_regmv_pr_dr/c_regmv_pr_dr.dsp
// Spec Reference: regmv preg to dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e00... |
tactcomplabs/xbgas-binutils-gdb | 5,916 | sim/testsuite/bfin/c_ldst_ld_d_p_h.s | //Original:/testcases/core/c_ldst_ld_d_p_h/c_ldst_ld_d_p_h.dsp
// Spec Reference: c_ldst ld d [p] h
# mach: bfin
.include "testutils.inc"
start
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_... |
tactcomplabs/xbgas-binutils-gdb | 1,107 | sim/testsuite/bfin/c_ldimmhalf_dreg.s | //Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp
// Spec Reference: ldimmhalf dreg imm16
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0 = 0x0123 (X);
R1 = 0x1234 (X);
R2 = 0x2345 (X);
R3 = 0x3456 (X);
R4 = 0x4567 (X);
R5 = 0x5678 (X);
R6 = 0x6789 (X);
R7 = 0x789a (X);
... |
tactcomplabs/xbgas-binutils-gdb | 1,470 | sim/testsuite/bfin/c_ldimmhalf_l_dr.s | //Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp
// Spec Reference: ldimmhalf l dreg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xffff... |
tactcomplabs/xbgas-binutils-gdb | 5,233 | sim/testsuite/bfin/byteop3p.s | # Blackfin testcase for BYTEOP3P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP3P (R1:0, R3:2) (LO);
check_it \re... |
tactcomplabs/xbgas-binutils-gdb | 5,625 | sim/testsuite/bfin/c_regmv_imlb_dep_stall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp
// Spec Reference: regmv imlb-depepency stall
# mach: bfin
.include "testutils.inc"
start
// R-reg to I,M-reg to R-reg: stall
imm32 r0, 0x00001110;
imm32 r1, 0x00213330;
imm32 r2, 0x04015550;
imm32 r3, 0x06607770;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 1,081 | sim/testsuite/bfin/c_logi2op_log_r_shft_astat.S | # Test ASTAT bits with logical right shift (>>=)
# mach: bfin
.include "testutils.inc"
#include "test.h"
start
.macro __do val:req, shift:req, exp:req
# First test when ASTAT starts with all bits cleared
imm32 R2, \val;
ASTAT = R0;
R2 >>= \shift;
R3 = ASTAT;
CHECKREG R2, (\val >> \shift);
CHECKREG R3, \exp;
... |
tactcomplabs/xbgas-binutils-gdb | 5,702 | sim/testsuite/bfin/c_dsp32alu_max.s | //Original:/testcases/core/c_dsp32alu_max/c_dsp32alu_max.dsp
// Spec Reference: dsp32alu dregs = max ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x85678911;
imm32 r1, 0x9789ab1d;
imm32 r2, 0xa4445b15;
imm32 r3, 0x46667717;
imm32 r4, 0xd567f91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;... |
tactcomplabs/xbgas-binutils-gdb | 4,303 | sim/testsuite/bfin/c_cc2stat_cc_av1.S | //Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp
// Spec Reference: cc2stat cc av1
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000... |
tactcomplabs/xbgas-binutils-gdb | 3,633 | sim/testsuite/bfin/c_dsp32alu_byteop1ew.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop1ew/c_dsp32alu_byteop1ew.dsp
// Spec Reference: dsp32alu byteop1ew
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, ... |
tactcomplabs/xbgas-binutils-gdb | 4,030 | sim/testsuite/bfin/c_regmv_pr_dep_stall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_stall/c_regmv_pr_dep_stall.dsp
// Spec Reference: regmv pr-dependency stall
# mach: bfin
.include "testutils.inc"
start
INIT_M_REGS 0;
// R-reg to P-reg to R reg: stall
imm32 r0, 0x00001110;
imm32 r1, 0x00213330;
imm32 r2, 0x04015550;
imm32 r3, 0x06607770... |
tactcomplabs/xbgas-binutils-gdb | 1,660 | sim/testsuite/bfin/m13.s | // Test extraction from accumulators:
// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffffff0
// load r1=0xfffffff0
// load r2=0x0fffffff
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ ... |
tactcomplabs/xbgas-binutils-gdb | 4,000 | sim/testsuite/bfin/c_dsp32mult_pair_m_is.s | //Original:/testcases/core/c_dsp32mult_pair_m_is/c_dsp32mult_pair_m_is.dsp
// Spec Reference: dsp32mult pair MUNOP is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
i... |
tactcomplabs/xbgas-binutils-gdb | 1,468 | sim/testsuite/bfin/dsp_s1.s | /* SHIFT test program.
* Test r0, r1, A0 >>= BITMUX;
*/
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = r0;
// load r0=0x80000009
// load r1=0x10000009
// load r2=0x0000000f
// load r3=0x00000000
// load r4=0x80000008
// load r5=0x00000000
loadsym P0, data0;
loadsym P1, data0;
R0 = [ P0 ... |
tactcomplabs/xbgas-binutils-gdb | 11,605 | sim/testsuite/bfin/dbg_jmp_src_kill.S | //Original:/proj/frio/dv/testcases/debug/dbg_jmp_src_kill/dbg_jmp_src_kill.dsp
// Description: This test checks that the trace buffer keeps track of a JUMP
// source instruction getting killed at each stage in the pipe. The test
// consists of 8 instances of an EXCPT instruction followed by 0 to 7 NOPs
// and a JUMP, ... |
tactcomplabs/xbgas-binutils-gdb | 7,686 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_s/c_dsp32mac_pair_a1a0_s.dsp
// Spec Reference: dsp32mac pair a1a0 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645... |
tactcomplabs/xbgas-binutils-gdb | 5,622 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_xh.s | //Original:testcases/core/c_ldst_ld_d_p_pp_xh/c_ldst_ld_d_p_pp_xh.dsp
// Spec Reference: c_ldst ld d [p++] xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// initial values
loadsym p5, DATA_ADDR_1, 0x08;
loadsym p1, DATA... |
tactcomplabs/xbgas-binutils-gdb | 7,512 | sim/testsuite/bfin/c_seq_ex2_mmr_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmr_mvpop/c_seq_ex2_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_R... |
tactcomplabs/xbgas-binutils-gdb | 3,835 | sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s | //Original:/testcases/core/c_pushpopmultiple_dp_pair/c_pushpopmultiple_dp_pair.dsp
// Spec Reference: pushpopmultiple dreg preg in group pair
# mach: bfin
.include "testutils.inc"
start
FP = SP;
imm32 r0, 0x00000000;
ASTAT = r0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;... |
tactcomplabs/xbgas-binutils-gdb | 9,363 | sim/testsuite/bfin/se_kill_wbbr.S | //Original:/proj/frio/dv/testcases/seq/se_kill_wbbr/se_kill_wbbr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
... |
tactcomplabs/xbgas-binutils-gdb | 9,932 | sim/testsuite/bfin/c_dsp32shift_lhalf_rp.s | //Original:/testcases/core/c_dsp32shift_lhalf_rp/c_dsp32shift_lhalf_rp.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00000001;
imm32... |
tactcomplabs/xbgas-binutils-gdb | 3,380 | sim/testsuite/bfin/c_regmv_dr_acc_acc.s | //Original:/testcases/core/c_regmv_dr_acc_acc/c_regmv_dr_acc_acc.dsp
// Spec Reference: regmv dreg-acc-acc
# mach: bfin
.include "testutils.inc"
start
// check R-reg to ACC
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x91234567;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm... |
tactcomplabs/xbgas-binutils-gdb | 2,911 | sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s | //Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp
// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x83545abd;
imm32 r1, 0x98bcfec7;
imm32 r... |
tactcomplabs/xbgas-binutils-gdb | 1,533,086 | sim/testsuite/bfin/se_all64bitg0opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 0)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0xC0000000 to 0xffffffff
* (... |
tactcomplabs/xbgas-binutils-gdb | 10,670 | sim/testsuite/bfin/se_brtarget_stall.S | //Original:/proj/frio/dv/testcases/seq/se_brtarget_stall/se_brtarget_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files ////////////////////... |
tactcomplabs/xbgas-binutils-gdb | 10,526 | sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0... |
tactcomplabs/xbgas-binutils-gdb | 19,424 | sim/testsuite/bfin/se_undefinedinstruction1.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction1/se_undefinedinstruction1.dsp
// Description: 16 bit "holes" Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
includ... |
tactcomplabs/xbgas-binutils-gdb | 7,770 | sim/testsuite/bfin/c_dsp32alu_rrpmmp_sft_x.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x4666... |
tactcomplabs/xbgas-binutils-gdb | 2,204 | sim/testsuite/bfin/c_compi2opd_dr_eq_i7_n.s | //Original:/testcases/core/c_compi2opd_dr_eq_i7_n/c_compi2opd_dr_eq_i7_n.dsp
// Spec Reference: compi2opd dregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = -0;
R1 = -1;
R2 = -2;
R3 = -3;
R4 = -4;
R5 = -5;
R6 = -6;
R7 = -7;
CHECKREG r0, -0;
CHECKREG r1, -1;
CHECKREG r2, -2;
CHEC... |
tactcomplabs/xbgas-binutils-gdb | 4,200 | sim/testsuite/bfin/c_dsp32shift_ones.s | //Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp
// Spec Reference: dsp32shift ones
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x88880000;
imm32 r1, 0x34560001;
imm32 r2, 0x08000002;
imm32 r3, 0x08000003;
imm32 r4, 0x08000004;
imm32 r5, 0x08000005;
imm32 r6, 0x08000006;
imm32 r7, 0x08... |
tactcomplabs/xbgas-binutils-gdb | 2,315 | sim/testsuite/bfin/dsp_a7.s | /* ALU test program.
* Test instructions
* r7 = +/- (r0,r1);
* r7 = -/+ (r0,r1);
* r7 = -/- (r0,r1);
*/
# mach: bfin
.include "testutils.inc"
start
// test subtraction
R0.L = 0x000f;
R0.H = 0x0010;
R1.L = 0x000f;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|- R1;
DBGA ( R7.L , 0x0000 );
DBGA ( R7... |
tactcomplabs/xbgas-binutils-gdb | 2,414 | sim/testsuite/bfin/c_dsp32alu_alhwx.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp
// Spec Reference: dsp32alu alhwx
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
A1 = A0 = 0;
imm32 r0, 0xa5678911;
imm32 r1, 0xaa89ab1d;
imm32 r2, 0xd4b45515;
imm32 r3, 0xf66e7717;
imm32 r4, 0xe567f91b;
imm32 r5... |
tactcomplabs/xbgas-binutils-gdb | 4,586 | sim/testsuite/bfin/c_dsp32shift_signbits_rl.s | //Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp
// Spec Reference: dsp32shift signbits dregs_lo
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, ... |
tactcomplabs/xbgas-binutils-gdb | 4,735 | sim/testsuite/bfin/c_except_sys_sstep.S | //Original:/proj/frio/dv/testcases/core/c_except_sys_sstep/c_except_sys_sstep.dsp
// Spec Reference: Single Step Supervisor Exception Test (NO REGTRACE!)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
#ifndef S... |
tactcomplabs/xbgas-binutils-gdb | 77,422 | sim/testsuite/bfin/divq.s | # Blackfin testcase for divide instructions
# mach: bfin
.include "testutils.inc"
start
/*
* Evaluate given a signed integer dividend and signed interger divisor
* input is:
* r0 = dividend, or numerator
* r1 = divisor, or denominator
* output is:
* r0 = quotient (16-bits)
*/
.macro divide num:... |
tactcomplabs/xbgas-binutils-gdb | 4,845 | sim/testsuite/bfin/c_dsp32shift_align24.s | //Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp
// Spec Reference: dsp32shift align24
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7... |
tactcomplabs/xbgas-binutils-gdb | 1,346 | sim/testsuite/bfin/mc_s2.s | /* SHIFT test program.
* Test r0, r1, A0 <<= BITMUX;
*/
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// load r0=0x90000001
// load r1=0x90000002
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x20000002
// load r5=0x00000000
loadsym P1, data0;
// insert two bits, both equal... |
tactcomplabs/xbgas-binutils-gdb | 7,286 | sim/testsuite/bfin/c_dsp32alu_rrppmm_sft.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, <<
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717... |
tactcomplabs/xbgas-binutils-gdb | 1,817 | sim/testsuite/bfin/c_regmv_dr_pr.s | //Original:/testcases/core/c_regmv_dr_pr/c_regmv_dr_pr.dsp
// Spec Reference: regmv dreg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check R-reg to R-reg move
imm32 r0, 0x20001001;
imm32 r1, 0x20021003;
imm32 r2, 0x20041005;
imm32 r3, 0x20061007;
imm32 r4, 0x20081009;
imm32 r5, 0x200a100b;
imm32 r6... |
tactcomplabs/xbgas-binutils-gdb | 5,914 | sim/testsuite/bfin/c_dsp32alu_rh_m.s | //Original:/testcases/core/c_dsp32alu_rh_m/c_dsp32alu_rh_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x89678911;
imm32 r1, 0x2189ab1d;
imm32 r2, 0x34145515;
imm32 r3, 0x46617717;
imm32 r4, 0x5678191b;
imm32 r5, 0x6789a11d;
imm32 r6, 0x74445515;
imm32 r7, 0x8... |
tactcomplabs/xbgas-binutils-gdb | 2,860 | sim/testsuite/bfin/c_dsp32mac_dr_a0_u.s | //Original:/testcases/core/c_dsp32mac_dr_a0_u/c_dsp32mac_dr_a0_u.dsp
// Spec Reference: dsp32mac dr a0 u (unsigned fraction and unsigned int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0x9abcfec7;
imm32 r2, 0x... |
tactcomplabs/xbgas-binutils-gdb | 6,193 | sim/testsuite/bfin/c_dsp32mac_pair_a1_s.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_s/c_dsp32mac_pair_a1_s.dsp
// Spec Reference: dsp32mac pair a1 S
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
... |
tactcomplabs/xbgas-binutils-gdb | 5,417 | sim/testsuite/bfin/c_dsp32alu_rp.s | //Original:/testcases/core/c_dsp32alu_rp/c_dsp32alu_rp.dsp
// Spec Reference: dsp32alu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0 = R0... |
tactcomplabs/xbgas-binutils-gdb | 9,487 | sim/testsuite/bfin/c_ldstii_ld_dr_xh.s | //Original:testcases/core/c_ldstii_ld_dr_xh/c_ldstii_ld_dr_xh.dsp
// Spec Reference: c_ldstii load dreg xh
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
... |
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