repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
taciclei/PrismChrono | 4,800 | benchmarks/prismchrono/trit_operations.s | # Benchmark: Trit Operations
# Implémentation d'opérations spécialisées trit par trit (TMIN, TMAX, TSUM, TCMP3)
# Ce benchmark démontre l'efficacité des instructions ternaires spécialisées
# Définition des constantes
.equ ARRAY_SIZE, 50 # Taille du tableau
.equ ARRAY_ADDR, 0x1000 # Adresse du premier tableau
.eq... |
taciclei/PrismChrono | 3,112 | benchmarks/prismchrono/compact_format.s | # Benchmark: Compact Format
# Comparaison entre format standard et format compact
# Ce benchmark démontre les avantages du format d'instruction compact en termes de densité de code
# Définition des constantes
.equ ITERATIONS, 50 # Nombre d'itérations
.equ DATA_ADDR, 0x1000 # Adresse des données d'entrée
.equ ... |
tactcomplabs/xbgas-binutils-gdb | 2,867 | binutils/testsuite/binutils-all/dwo.s | /* Assembler source used to create an object file for testing readelf's
and objdump's ability to process separate dwarf object files.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public Lic... |
tactcomplabs/xbgas-binutils-gdb | 5,206 | binutils/testsuite/binutils-all/dw2-2.S | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2008-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
tactcomplabs/xbgas-binutils-gdb | 1,642 | binutils/testsuite/binutils-all/retain1.s | .global discard0
.section .bss.discard0,"aw"
.type discard0, %object
discard0:
.zero 2
.global discard1
.section .bss.discard1,"aw"
.type discard1, %object
discard1:
.zero 2
.global discard2
.section .data.discard2,"aw"
.type discard2, %object
discard2:
.word 1
.section .bss.sdiscard0,"aw"
.type sdisca... |
tactcomplabs/xbgas-binutils-gdb | 8,459 | binutils/testsuite/binutils-all/locview-1.s | .text
.Ltext0:
.LFB0:
/* locview.c:1 */
.LM1:
/* view -0 */
/* locview.c:2 */
.LM2:
/* view 1 */
.LVL0:
/* DEBUG i => 0 */
/* locview.c:3 */
.LM3:
/* view 2 */
/* DEBUG j => 0x1 */
/* locview.c:4 */
.LM4:
/* view 3 */
/* DEBUG i => 0x2 */
/* locview.c:5 */
.LM5:
/* view 4 */
/* DEBUG j => 0x3 */
/* locv... |
tactcomplabs/xbgas-binutils-gdb | 3,119 | binutils/testsuite/binutils-all/pr18374.s | .section .debug_info,"",%progbits
.4byte 0x77
.2byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x4
.uleb128 0x1
.4byte .LASF3
.byte 0xc
.ascii "x.c\000"
.4byte .LASF4
.4byte .Ltext0
.4byte .Letext0
.4byte .Ldebug_line0
.uleb128 0x2
.ascii "foo\000"
.byte 0x1
.byte 0x2
.4byte .LFB0
.4byte .LFE0
.uleb128 0x1
... |
tactcomplabs/xbgas-binutils-gdb | 2,386 | binutils/testsuite/binutils-all/debuglink.s | /* Assembler source used to create an object file for testing readelf's
and objdump's ability to process separate debug information files.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Publi... |
tactcomplabs/xbgas-binutils-gdb | 21,697 | binutils/testsuite/binutils-all/dw5.S | /* Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This ... |
tactcomplabs/xbgas-binutils-gdb | 5,436 | binutils/testsuite/binutils-all/dw5-op.S | /* Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This ... |
tactcomplabs/xbgas-binutils-gdb | 1,451 | binutils/testsuite/binutils-all/pr25662-pdp11.s | /* PR 25662: objcopy sets invalid sh_offset for the first section in a
no_contents segment containing program headers.
Several conditions are required for the bug to manifest:
- The first loadable segment (which contains the program headers) must only
contain SHT_NOBITS sections. .bss is the SHT_NOBITS s... |
tactcomplabs/xbgas-binutils-gdb | 1,450 | binutils/testsuite/binutils-all/testranges-ia64.s | # Test .debug_info can reference .debug_ranges entries without ordering the
# offsets strictly as increasing.
.text
start:
.byte 1
sub:
.byte 2
end:
.section .debug_ranges,"",@progbits
range:
range_sub:
data4.ua @secrel(sub), @secrel(end)
data4.ua 0, 0 /* range terminator */
range_cu:
data4.ua @secrel(start... |
tactcomplabs/xbgas-binutils-gdb | 1,363 | binutils/testsuite/binutils-all/pr25662.s | /* PR 25662: objcopy sets invalid sh_offset for the first section in a
no_contents segment containing program headers.
Several conditions are required for the bug to manifest:
- The first loadable segment (which contains the program headers) must only
contain SHT_NOBITS sections. .bss is the SHT_NOBITS s... |
tactcomplabs/xbgas-binutils-gdb | 5,276 | binutils/testsuite/binutils-all/dw2-1.S | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2008-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
tactcomplabs/xbgas-binutils-gdb | 2,212 | binutils/testsuite/binutils-all/linkdebug.s | /* Assembler source used to create an object file for testing readelf's
and objdump's ability to process separate debug information files.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Publi... |
tactcomplabs/xbgas-binutils-gdb | 9,143 | binutils/testsuite/binutils-all/dw2-3.S | /* This testcase is part of GDB, the GNU debugger.
Copyright (C) 2004-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License,... |
tactcomplabs/xbgas-binutils-gdb | 1,400 | binutils/testsuite/binutils-all/testranges.s | # Test .debug_info can reference .debug_ranges entries without ordering the
# offsets strictly as increasing.
.text
start:
.byte 1
sub:
.byte 2
end:
.section .debug_ranges,"",%progbits
range:
range_sub:
.4byte sub, end
.4byte 0, 0 ;# range terminator
range_cu:
.4byte start, end
.4byte 0, 0 ;# range terminat... |
tactcomplabs/xbgas-binutils-gdb | 4,450 | binutils/testsuite/binutils-all/dwarf-attributes.S | /* Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This ... |
tactcomplabs/xbgas-binutils-gdb | 11,323 | binutils/testsuite/binutils-all/locview-2.s | .text
.Ltext0:
.LFB0:
/* locview.c:1 */
.LM1:
/* view -0 */
/* locview.c:2 */
.LM2:
/* view 1 */
.LVL0:
/* DEBUG i => 0 */
/* locview.c:3 */
.LM3:
/* view 2 */
/* DEBUG j => 0x1 */
/* locview.c:4 */
.LM4:
/* view 3 */
/* DEBUG i => 0x2 */
/* locview.c:5 */
.LM5:
/* view 4 */
/* DEBUG j => 0x3 */
/* locv... |
tactcomplabs/xbgas-binutils-gdb | 4,519 | binutils/testsuite/binutils-all/dw2-compressed.S | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2008-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
tactcomplabs/xbgas-binutils-gdb | 1,086 | binutils/testsuite/binutils-all/readelf.s | There are .* section headers, starting at offset .*:
Section Headers:
+\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0
# On the normal MIPS systems, sections must be aligned to 16 byte
# boundaries. On IA64, text sections are aligned to 16 byte boundaries.
+\[ ... |
tactcomplabs/xbgas-binutils-gdb | 35,389 | binutils/testsuite/binutils-all/dw4.s | .file "main.c"
.text
.Ltext0:
.text
.globl main
.type main, %function
main:
.LFB0:
.file 1 "main.c"
.loc 1 6 1 view -0
.word 1234
.word 5678
.LFE0:
.size main, . - main
.globl g_my_private_global
.data
.align 4
.type g_my_private_global, %object
.size g_my_private_global, 4
g_my_private_global:
.zero 4
... |
tactcomplabs/xbgas-binutils-gdb | 4,440 | binutils/testsuite/binutils-all/dw2-ranges.S | /* Copyright (C) 2015-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This ... |
tactcomplabs/xbgas-binutils-gdb | 1,299 | binutils/testsuite/binutils-all/riscv/unknown.s | /* Copyright (C) 2021-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This ... |
tactcomplabs/xbgas-binutils-gdb | 2,178 | binutils/testsuite/binutils-all/i386/compressed-1.s | .file "compressed-1.c"
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.cfi_sections .debug_frame
.p2align 4,,15
.globl foo2
.type foo2, @function
foo2:
.LFB1:
.file 1 "compressed-1.c"
.loc 1 ... |
tactcomplabs/xbgas-binutils-gdb | 9,273 | binutils/testsuite/binutils-all/mips/mips16-extend-insn.s | .set mips16
.set noreorder
foo:
extend 0x123 # ADDIUSP
addiu $16, $29, 0
extend 0x123
addiu $16, $29, 128
extend 0x123
addiu $16, $29, 256
extend 0x123
addiu $16, $29, 384
extend 0x123
addiu $16, $29, 512
extend 0x123
addiu $16, $29, 640
extend 0x123
addiu $16, $29, 768
extend 0x123
addiu $16, $29, 8... |
tactcomplabs/xbgas-binutils-gdb | 3,702 | binutils/testsuite/binutils-all/mips/mips16-undecoded.s | .text
.set mips16
.globl foo
.ent foo
foo:
# Individual major opcodes.
addiu $2, $sp, 0x4011
.half 0xf008, 0x0211
.half 0xf008, 0x0231
.half 0xf008, 0x0251
.half 0xf008, 0x0291
addiu $2, $pc, 0x4011
.half 0xf008, 0x0a11
.half 0xf008, 0x0a31
.half 0xf008, 0x0a51
.half 0xf008, 0x0a91
b . + 0x8026
.half... |
tactcomplabs/xbgas-binutils-gdb | 2,182 | binutils/testsuite/binutils-all/mips/mips16-pcrel.s | .module mips64
.set mips16
.set noreorder
.set noautoextend
.align 12, 0
foo0:
nop
nop
addiu $2, $pc, 0x3fc
nop
nop
nop
lw $3, 0x3fc($pc)
nop
nop
nop
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
nop
ld $5, 0xf8($pc)
.align 12, 0
foo1:
jal bar0
addiu $2, $pc, 0x3fc
nop
jal bar0
lw $3, 0x3fc($pc)
... |
tactcomplabs/xbgas-binutils-gdb | 2,087 | binutils/testsuite/binutils-all/x86-64/compressed-1.s | .file "compressed-1.c"
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.cfi_sections .debug_frame
.p2align 4,,15
.globl foo2
.type foo2, @function
foo2:
.LFB1:
.file 1 "compressed-1.c"
.loc 1 ... |
tactcomplabs/xbgas-binutils-gdb | 1,494 | binutils/testsuite/binutils-all/x86-64/pr23494a.s | .section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/... |
tactcomplabs/xbgas-binutils-gdb | 1,979 | binutils/testsuite/binutils-all/x86-64/pr23494c.s | .section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/... |
tactcomplabs/xbgas-binutils-gdb | 1,478 | binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s | .text
func:
//scale 1, size<0> check for H.
#st1 {v30.h}[0], [x30]
.inst 0x0d0043de | (1 << 10)
#st2 {v29.h, v30.h}[0], [x30]
.inst 0x0d2043dd | (1 << 10)
#st3 {v28.h, v29.h, v30.h}[0], [x30]
.inst 0x0d0063dc | (1 << 10)
#st4 {v27.h, v28.h, v29.h, v30.h}[0], [x30]
.inst 0x0d2063db | (1 << 10)
//scale 2, siz... |
tactcomplabs/xbgas-binutils-gdb | 1,568 | sim/bfin/linux-fixed-code.s | /* Linux fixed code userspace ABI
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the... |
tactcomplabs/xbgas-binutils-gdb | 32,830 | sim/testsuite/sh/movxy.s | # sh testcase for movxy
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
src1: .word 1
src2: .word 2
src3: .word 3
src4: .word 4
src5: .word 5
src6: .word 6
src7: .word 7
src8: .word 8
src9: .word 9
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dst1: .word 0... |
tactcomplabs/xbgas-binutils-gdb | 1,647 | sim/testsuite/sh/bxor.s | # sh testcase for bxor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bxor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bxor.b #0, @(3, r1)
bt8k mfail
bxor.b #1, @(3, r1)
bt8k ... |
tactcomplabs/xbgas-binutils-gdb | 4,699 | sim/testsuite/sh/fmov.s | # sh testcase for all fmov instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fldi1 fr3
.endm
start
fmov1: # Test fr -> fr.
set_grs_a5a5
set_fprs_a5a5
init
single_prec
sz_32
fmov fr0, fr1
# Ensure fr0 and fr1 are now equal.
fcmp/eq ... |
tactcomplabs/xbgas-binutils-gdb | 1,619 | sim/testsuite/sh/fcmpeq.s | # sh testcase for fcmpeq
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpeq_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 == 1.0.
fldi1 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# 0.0 != 1.0.
fldi0 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L1
fail
.L1:
# 1.0 != 0.0.
fldi1 fr0
... |
tactcomplabs/xbgas-binutils-gdb | 1,361 | sim/testsuite/sh/clip.s | # sh testcase for clips, clipu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
clips_b:
set_grs_a5a5
clips.b r1
test_gr0_a5a5
assertreg 0xffffff80 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r... |
tactcomplabs/xbgas-binutils-gdb | 1,247 | sim/testsuite/sh/add.s | # sh testcase for add
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 1
_y: .long 1
start
add_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
add r1, r2
test_gr0_a5a5
assertreg 2 r1
assertreg 4 r2
test_gr_a5a5 r3
test_gr_a5a... |
tactcomplabs/xbgas-binutils-gdb | 1,326 | sim/testsuite/sh/fmac.s | # sh testcase for fmac
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fmac_:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * x + y = y.
fldi0 fr0
fldi1 fr1
fldi1 fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fcmp/eq fr0, fr2
bt .L0
fail
.L0:
# x * y + 0.0 = x * y.
fldi1 fr0
fldi1 fr1
... |
tactcomplabs/xbgas-binutils-gdb | 1,643 | sim/testsuite/sh/fcmpgt.s | # sh testcase for fcmpgt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpgt_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L0
fail
.L0:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt .L1
fail
.L1:
# 1.0 > 0.0.
fldi1 fr0
fl... |
tactcomplabs/xbgas-binutils-gdb | 2,387 | sim/testsuite/sh/bclr.s | # sh testcase for bclr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xffffffff
_y: .long 0x55555555
start
bclr_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bclr.b #0, @(3, r1)
assertmem _x, 0xfffffffe
bclr.b #1, @(3, r1)
assertmem ... |
tactcomplabs/xbgas-binutils-gdb | 4,107 | sim/testsuite/sh/resbank.s | # sh testcase for ldbank stbank resbank
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.macro SEND reg bankno regno
set_greg ((\bankno << 7) + (\regno << 2)), \reg
.endm
start
stbank_1:
set_grs_a5a5
mov #0, r0
SEND r1, 0, 0
stbank r0, @r1
mov #1, r0
... |
tactcomplabs/xbgas-binutils-gdb | 1,318 | sim/testsuite/sh/shll.s | # sh testcase for shll
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll:
set_grs_a5a5
mov #1, r1
shll r1
assertreg 2, r1
shll r1
assertreg 4, r1
shll r1
assertreg 8, r1
shll r1
assertreg 16, r1
shll r1
assertreg 32, r1
shll r1
assertreg... |
tactcomplabs/xbgas-binutils-gdb | 1,730 | sim/testsuite/sh/fsca.s | # sh testcase for fsca
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsca:
set_grs_a5a5
set_fprs_a5a5
# Start with angle zero
mov.l zero, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
mov.l plus_90, r0
lds... |
tactcomplabs/xbgas-binutils-gdb | 2,256 | sim/testsuite/sh/bst.s | # sh testcase for bst
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bst_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bst.b #0, @(3, r1)
assertmem _x, 0x1
bst.b #1, ... |
tactcomplabs/xbgas-binutils-gdb | 1,609 | sim/testsuite/sh/fabs.s | # sh testcase for fabs
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fabs_freg_b0:
single_prec
bank0
set_grs_a5a5
set_fprs_a5a5
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
... |
tactcomplabs/xbgas-binutils-gdb | 1,325 | sim/testsuite/sh/and.s | # sh testcase for and
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
and_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
and r1, r2
test_gr0_a5a5
assertreg 0xa5a5a5a5 r1
assertreg 0xa0a0a... |
tactcomplabs/xbgas-binutils-gdb | 1,715 | sim/testsuite/sh/fsqrt.s | # sh testcase for fsqrt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsqrt_single:
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
fsqrt fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# sqrt(1.0) = 1.0.
fldi1 fr0
fsqrt fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1... |
tactcomplabs/xbgas-binutils-gdb | 2,169 | sim/testsuite/sh/float.s | # sh testcase for float
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
float_pos:
set_grs_a5a5
set_fprs_a5a5
single_prec
mov #3, r0
lds r0, fpul
float fpul, fr2
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fcmp/eq fr1, fr2
bt float_neg
fail
float_neg: ... |
tactcomplabs/xbgas-binutils-gdb | 2,323 | sim/testsuite/sh/ftrc.s | # sh testcase for ftrc
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
ftrc_single:
set_grs_a5a5
set_fprs_a5a5
# ftrc(0.0) = 0.
fldi0 fr0
ftrc fr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L0
fail
.L0:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr1
fldi1 fr2
# dou... |
tactcomplabs/xbgas-binutils-gdb | 1,896 | sim/testsuite/sh/pshli.s | # sh testcase for pshl <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_imm: ! shift logical, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, a0
pshl #0, a0
asse... |
tactcomplabs/xbgas-binutils-gdb | 1,142 | sim/testsuite/sh/movi.s | # sh testcase for all mov <#imm> instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
mov_i_reg: # Test <imm8>
set_grs_a5a5
mov #-0x55, r1
assertreg 0xffffffab, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 ... |
tactcomplabs/xbgas-binutils-gdb | 1,484 | sim/testsuite/sh/bldnot.s | # sh testcase for bldnot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bldnot_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bldnot.b #0, @(0, r1)
bt8k mfail
bldnot.b #1, @(0, r1)
bf8k mfail
bldn... |
tactcomplabs/xbgas-binutils-gdb | 2,717 | sim/testsuite/sh/movua.s | # sh testcase for movua
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movua_1:
set_grs_a5a5
mov.l srcp, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg... |
tactcomplabs/xbgas-binutils-gdb | 1,585 | sim/testsuite/sh/fneg.s | # sh testcase for fneg
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fneg_single:
set_grs_a5a5
set_fprs_a5a5
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr1
fneg fr0
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# neg(1.0) = fsub(0,1)
fldi1 fr0
fneg fr0
fldi0 fr1
fldi1 fr2
fsub fr2, fr1
fcmp/eq f... |
tactcomplabs/xbgas-binutils-gdb | 2,619 | sim/testsuite/sh/mulr.s | # sh testcase for mulr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
mulr_1: ! multiply by one
set_grs_a5a5
mov #1, r0
mulr r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
... |
tactcomplabs/xbgas-binutils-gdb | 1,665 | sim/testsuite/sh/fmul.s | # sh testcase for fmul
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
.endm
start
fmul_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * 0.0 = 0.0.
init
fmul fr0, fr0
assert_fpreg_i 0, fr0
# 0.0 * 1.0 = 0.0.
init
fmul fr1, fr0
asse... |
tactcomplabs/xbgas-binutils-gdb | 2,985 | sim/testsuite/sh/pswap.s | # sh testcase for pswap
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pswapx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
pswap x0, y0
assert_sreg 0x7777a5a5, y0
set... |
tactcomplabs/xbgas-binutils-gdb | 6,051 | sim/testsuite/sh/loop.s | # sh testcase for loop control
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
loop1:
set_grs_a5a5
ldrs Loop1_start0+8
ldre Loop1_start0+4
setrc #5
Loop1_start0:
add #1, r1 ! Before loop
# Loop should execute one instruction five times.
Loop1_begin:
add #1, r1 ! Within loo... |
tactcomplabs/xbgas-binutils-gdb | 1,589 | sim/testsuite/sh/bld.s | # sh testcase for bld
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bld_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bld.b #0, @(0, r1)
bf8k mfail
bld.b #1, @(0, r1)
bt8k mfail
bld.b #2, @(0, r... |
tactcomplabs/xbgas-binutils-gdb | 1,557 | sim/testsuite/sh/fdiv.s | # sh testcase for fdiv
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fdiv_single:
# Single test
set_grs_a5a5
set_fprs_a5a5
single_prec
# 1.0 / 0.0 should be INF
# (and not crash the sim).
fldi0 fr0
fldi1 fr1
fdiv fr0, fr1
assert_fpreg_x 0x7f800000, fr1
# 0.0 / 1.0 == 0.0.
fldi0... |
tactcomplabs/xbgas-binutils-gdb | 1,167 | sim/testsuite/sh/fadd.s | # sh testcase for fadd
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fadd_freg_freg_b0:
set_grs_a5a5
set_fprs_a5a5
bank0
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 2 fr1
fldi0 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
fldi1 fr0
fldi0 fr1
fadd fr0, fr1
assert_fp... |
tactcomplabs/xbgas-binutils-gdb | 3,257 | sim/testsuite/sh/div.s | # sh testcase for divs and divu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
divs_1: ! divide by one
set_grs_a5a5
mov #1, r0
divs r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a... |
tactcomplabs/xbgas-binutils-gdb | 1,911 | sim/testsuite/sh/fsub.s | # sh testcase for fsub
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsub_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr1
fsub fr0, fr1
fldi1 fr2
fcmp/eq... |
tactcomplabs/xbgas-binutils-gdb | 1,433 | sim/testsuite/sh/prnd.s | # sh testcase for prnd
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
# FIXME: opcode table ambiguity in ignored bits 4-7.
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
# prnd(0xa5a5a5a5) = 0xa5a60000
prnd ... |
tactcomplabs/xbgas-binutils-gdb | 2,568 | sim/testsuite/sh/pshlr.s | # sh testcase for pshl <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, x0
set_sreg 0x0, y... |
tactcomplabs/xbgas-binutils-gdb | 1,805 | sim/testsuite/sh/pinc.s | # sh testcase for pinc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pincx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pinc x0, y0
assert_sreg 0xa5a60000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
... |
tactcomplabs/xbgas-binutils-gdb | 1,911 | sim/testsuite/sh/mov.s | # sh testcase for all mov.[bwl] instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.align 2
_lsrc: .long 0x55555555
_wsrc: .long 0x55550000
_bsrc: .long 0x55000000
.align 2
_ldst: .long 0
_wdst: .long 0
_bdst: .long 0
start
movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr
set_grs_a5... |
tactcomplabs/xbgas-binutils-gdb | 2,500 | sim/testsuite/sh/pushpop.s | # sh testcase for push/pop (mov,movml,movmu...) insns.
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movml_1:
set_greg 0, r0
set_greg 1, r1
set_greg 2, r2
set_greg 3, r3
set_greg 4, r4
set_greg 5, r5
set_greg 6, r6
set_greg 7, r7
set_greg 8, r8... |
tactcomplabs/xbgas-binutils-gdb | 1,029 | sim/testsuite/sh/fsrra.s | # sh testcase for fsrra
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsrra_single:
set_grs_a5a5
set_fprs_a5a5
# 1/sqrt(0.0) = +infinity.
fldi0 fr0
fsrra fr0
assert_fpreg_x 0x7f800000, fr0
# 1/sqrt(1.0) = 1.0.
fldi1 fr0
fsrra fr0
asser... |
tactcomplabs/xbgas-binutils-gdb | 4,383 | sim/testsuite/sh/pshar.s | # sh testcase for psha <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, x0
set_sreg 0x0, y0
p... |
tactcomplabs/xbgas-binutils-gdb | 2,259 | sim/testsuite/sh/bset.s | # sh testcase for bset
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bset_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bset.b #0, @(3, r1)
assertmem _x, 0x1
bset.b #1, @(3, r1)
assertmem _x, 0x3
bset.b ... |
tactcomplabs/xbgas-binutils-gdb | 1,807 | sim/testsuite/sh/pdec.s | # sh testcase for pdec
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pdecx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pdec x0, y0
assert_sreg 0xa5a40000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
... |
tactcomplabs/xbgas-binutils-gdb | 3,058 | sim/testsuite/sh/pshai.s | # sh testcase for psha <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_imm: ! shift arithmetic, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, a0
psha #0, a0
asser... |
tactcomplabs/xbgas-binutils-gdb | 1,593 | sim/testsuite/sh/ldrc.s | # sh testcase for ldrc, strc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
setrc_imm:
set_grs_a5a5
# Test setrc
#
ldrs lstart
ldre lend
setrc #0xff
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xff, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc... |
tactcomplabs/xbgas-binutils-gdb | 1,638 | sim/testsuite/sh/bandor.s | # sh testcase for band, bor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
band.b #0, @(3, r1)
bf8k mfail
bor.b #1, @(3, r1)
... |
tactcomplabs/xbgas-binutils-gdb | 4,646 | sim/testsuite/sh/pdmsb.s | # sh testcase for pdmsb
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x0, x0
L0: pdmsb x0, x1
# assert_sreg 31<<16, x1
set_sreg 0x1, x0
L1: pdmsb x0, x... |
tactcomplabs/xbgas-binutils-gdb | 2,333 | sim/testsuite/sh/fipr.s | # sh testcase for fipr $fvm, $fvn
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
initv0:
set_grs_a5a5
set_fprs_a5a5
# Load 1 into fr0.
fldi1 fr0
# Load 2 into fr1.
fldi1 fr1
fadd fr1, fr1
# Load 4 into fr2.
fldi1 fr2
fadd fr2, fr2
fadd fr2, fr2
# Load 8 into fr3.
fmov fr2, fr3
f... |
tactcomplabs/xbgas-binutils-gdb | 1,740 | sim/testsuite/sh/bandornot.s | # sh testcase for bandnot, bornot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bandnot.b #0, @(3, r1)
bt8k mfail
bornot.b #... |
tactcomplabs/xbgas-binutils-gdb | 17,132 | sim/testsuite/ft32/basic.s | # check that basic insns work.
# mach: ft32
.include "testutils.inc"
start
ldk $r0,__PMSIZE
EXPECT $r0,0x00040000
ldk $r0,__RAMSIZE
EXPECT $r0,0x00010000
ldk $r4,10
add $r4,$r4,23
EXPECT $r4,33
# lda, sta
.data
tmp: .long 0
.text
xor.l $r0,$r0,$r0
EXPECT $r0,0x0000... |
tactcomplabs/xbgas-binutils-gdb | 2,888 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s | //Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, ... |
tactcomplabs/xbgas-binutils-gdb | 3,576 | sim/testsuite/bfin/c_dsp32mac_dr_a1_s.s | //Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp
// Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbabcfec7;
imm32 r2... |
tactcomplabs/xbgas-binutils-gdb | 1,135 | sim/testsuite/bfin/cec-syscfg-ssstep.S | # Blackfin testcase for hardware single stepping
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set up exception handler
imm32 P4, EVT3;
loadsym R1, _evx;
[P4] = R1;
# Enable single stepping
R0 = 1;
SYSCFG = R0;
# Lower to the code we want to single step th... |
tactcomplabs/xbgas-binutils-gdb | 2,946 | sim/testsuite/bfin/c_dspldst_ld_drhi_i.s | //Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp
// Spec Reference: c_dspldst ld_drhi_i
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load upper half of Dr... |
tactcomplabs/xbgas-binutils-gdb | 2,045 | sim/testsuite/bfin/random_0033.S | # Verify registers saturate and ASTAT bits are updated correctly
# with the RND12 subtract insn
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN);
imm32 R5, 0x0fb35119;
imm32 R6, 0xffffffff;
imm32 R7, 0x80000000;
R6.H = R5 - R7 ... |
tactcomplabs/xbgas-binutils-gdb | 5,857 | sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s | //Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm3... |
tactcomplabs/xbgas-binutils-gdb | 10,881 | sim/testsuite/bfin/se_loop_nest_ppm_2.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_2/se_loop_nest_ppm_2.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files //////////////////... |
tactcomplabs/xbgas-binutils-gdb | 2,927 | sim/testsuite/bfin/c_dspldst_ld_drlo_i.s | //Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp
// Spec Reference: c_dspldst ld_drlo_i
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.L = W [ I... |
tactcomplabs/xbgas-binutils-gdb | 5,591 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_h.s | //Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp
// Spec Reference: c_ldst ld d [p--] h
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// initial values
loadsym p5, DATA_ADDR_1, 0x10;
loadsym p1, DATA_AD... |
tactcomplabs/xbgas-binutils-gdb | 1,691 | sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s | //Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp
// Spec Reference: dagmodim l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000110e;
imm32 b1, 0x0000110c;... |
tactcomplabs/xbgas-binutils-gdb | 1,701 | sim/testsuite/bfin/c_dsp32alu_bytepack.s | //Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp
// Spec Reference: dsp32alu bytepack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0... |
tactcomplabs/xbgas-binutils-gdb | 1,638 | sim/testsuite/bfin/random_0012.S | # test VIT_MAX behavior when high Acc bits are set
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0xd81562e8;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x15c2d815;
imm32 R5, 0xc9bd3a6b;
R4.L = VIT_MAX (R5) (ASR);
checkr... |
tactcomplabs/xbgas-binutils-gdb | 4,235 | sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s | //Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp
// Spec Reference: dsp32mac and 2 loads
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0
loadsym I1, DATA1
loadsym P1, DATA0
loadsym P2, DATA1
// t... |
tactcomplabs/xbgas-binutils-gdb | 5,561 | sim/testsuite/bfin/dbg_tr_simplejp.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp
// Description: This test performs simple jumps and verifies the trace buffer
// recording for simple jumps.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.in... |
tactcomplabs/xbgas-binutils-gdb | 4,081 | sim/testsuite/bfin/c_cc2stat_cc_aq.s | //Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp
// Spec Reference: cc2stat cc aq
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;... |
tactcomplabs/xbgas-binutils-gdb | 6,851 | sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp
// Spec Reference: sequencer stage AC (regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_RE... |
tactcomplabs/xbgas-binutils-gdb | 9,304 | sim/testsuite/bfin/c_dsp32shift_lf.s | //Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : mix data, count (+)= (half reg)
// d_reg = lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01210001;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x345178... |
tactcomplabs/xbgas-binutils-gdb | 2,891 | sim/testsuite/bfin/c_loopsetup_nested_bot.s | //Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp
// Spec Reference: loopsetup nested same bottom
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 2;
P2 = 4;
P3 = 6;
P4 = 8;
P5 = 10;
SP = 12;
FP = 14;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x32;
R4 = ... |
tactcomplabs/xbgas-binutils-gdb | 94,871 | sim/testsuite/bfin/lmu_cplb_multiple0.S | //Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp
// Description: Multiple CPLB Hit exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
... |
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