repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
lizhirui/DreamCore | 2,680 | model/tests/riscv-tests/isa/rv64ui/sw.S | # See LICENSE for license details.
#*****************************************************************************
# sw.S
#-----------------------------------------------------------------------------
#
# Test sw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 3,184 | model/tests/riscv-tests/isa/rv64ui/addw.S | # See LICENSE for license details.
#*****************************************************************************
# addw.S
#-----------------------------------------------------------------------------
#
# Test addw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 4,022 | model/tests/riscv-tests/isa/rv64ui/sra.S | # See LICENSE for license details.
#*****************************************************************************
# sra.S
#-----------------------------------------------------------------------------
#
# Test sra instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 3,114 | model/tests/riscv-tests/isa/rv64ui/sraiw.S | # See LICENSE for license details.
#*****************************************************************************
# sraiw.S
#-----------------------------------------------------------------------------
#
# Test sraiw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 2,623 | model/tests/riscv-tests/isa/rv64ui/or.S | # See LICENSE for license details.
#*****************************************************************************
# or.S
#-----------------------------------------------------------------------------
#
# Test or instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 2,597 | model/tests/riscv-tests/isa/rv64ui/srai.S | # See LICENSE for license details.
#*****************************************************************************
# srai.S
#-----------------------------------------------------------------------------
#
# Test srai instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,013 | model/tests/riscv-tests/isa/rv64ui/bne.S | # See LICENSE for license details.
#*****************************************************************************
# bne.S
#-----------------------------------------------------------------------------
#
# Test bne instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,201 | model/tests/riscv-tests/isa/rv64ui/sltiu.S | # See LICENSE for license details.
#*****************************************************************************
# sltiu.S
#-----------------------------------------------------------------------------
#
# Test sltiu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 1,087 | model/tests/riscv-tests/isa/rv64ui/jal.S | # See LICENSE for license details.
#*****************************************************************************
# jal.S
#-----------------------------------------------------------------------------
#
# Test jal instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 1,735 | model/tests/riscv-tests/isa/rv64ui/jalr.S | # See LICENSE for license details.
#*****************************************************************************
# jalr.S
#-----------------------------------------------------------------------------
#
# Test jalr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,176 | model/tests/riscv-tests/isa/rv64ui/srli.S | # See LICENSE for license details.
#*****************************************************************************
# srli.S
#-----------------------------------------------------------------------------
#
# Test srli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,827 | model/tests/riscv-tests/isa/rv64ui/slli.S | # See LICENSE for license details.
#*****************************************************************************
# slli.S
#-----------------------------------------------------------------------------
#
# Test slli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,290 | model/tests/riscv-tests/isa/rv64ui/lh.S | # See LICENSE for license details.
#*****************************************************************************
# lh.S
#-----------------------------------------------------------------------------
#
# Test lh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 3,145 | model/tests/riscv-tests/isa/rv64ui/add.S | # See LICENSE for license details.
#*****************************************************************************
# add.S
#-----------------------------------------------------------------------------
#
# Test add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,282 | model/tests/riscv-tests/isa/rv64ui/lb.S | # See LICENSE for license details.
#*****************************************************************************
# lb.S
#-----------------------------------------------------------------------------
#
# Test lb instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 1,861 | model/tests/riscv-tests/isa/rv64ui/xori.S | # See LICENSE for license details.
#*****************************************************************************
# xori.S
#-----------------------------------------------------------------------------
#
# Test xori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,949 | model/tests/riscv-tests/isa/rv64ui/slt.S | # See LICENSE for license details.
#*****************************************************************************
# slt.S
#-----------------------------------------------------------------------------
#
# Test slt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,149 | model/tests/riscv-tests/isa/rv64ui/bge.S | # See LICENSE for license details.
#*****************************************************************************
# bge.S
#-----------------------------------------------------------------------------
#
# Test bge instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,028 | model/tests/riscv-tests/isa/rv64ui/blt.S | # See LICENSE for license details.
#*****************************************************************************
# blt.S
#-----------------------------------------------------------------------------
#
# Test blt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,371 | model/tests/riscv-tests/isa/rv64ui/addiw.S | # See LICENSE for license details.
#*****************************************************************************
# addiw.S
#-----------------------------------------------------------------------------
#
# Test addiw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 2,975 | model/tests/riscv-tests/isa/rv64ui/srliw.S | # See LICENSE for license details.
#*****************************************************************************
# srliw.S
#-----------------------------------------------------------------------------
#
# Test srliw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 1,143 | model/tests/riscv-tests/isa/rv32ud/ldst.S | # See LICENSE for license details.
#*****************************************************************************
# ldst.S
#-----------------------------------------------------------------------------
#
# This test verifies that flw, fld, fsw, and fsd work properly.
#
#include "riscv_test.h"
#include "test_macros.h"... |
lizhirui/DreamCore | 2,781 | model/tests/riscv-tests/isa/rv64um/mulhu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhu.S
#-----------------------------------------------------------------------------
#
# Test mulhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 2,576 | model/tests/riscv-tests/isa/rv64um/mulh.S | # See LICENSE for license details.
#*****************************************************************************
# mulh.S
#-----------------------------------------------------------------------------
#
# Test mulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,420 | model/tests/riscv-tests/isa/rv64um/mulw.S | # See LICENSE for license details.
#*****************************************************************************
# mulw.S
#-----------------------------------------------------------------------------
#
# Test mulw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,636 | model/tests/riscv-tests/isa/rv64um/mulhsu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhsu.S
#-----------------------------------------------------------------------------
#
# Test mulhsu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
... |
lizhirui/DreamCore | 2,732 | model/tests/riscv-tests/isa/rv64um/mul.S | # See LICENSE for license details.
#*****************************************************************************
# mul.S
#-----------------------------------------------------------------------------
#
# Test mul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 1,872 | model/tests/riscv-tests/isa/rv64uzfh/fmin.S | # See LICENSE for license details.
#*****************************************************************************
# fmin.S
#-----------------------------------------------------------------------------
#
# Test f{min|max}.h instructinos.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BE... |
lizhirui/DreamCore | 1,629 | model/tests/riscv-tests/isa/rv64uzfh/fmadd.S | # See LICENSE for license details.
#*****************************************************************************
# fmadd.S
#-----------------------------------------------------------------------------
#
# Test f[n]m{add|sub}.h and f[n]m{add|sub}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RV... |
lizhirui/DreamCore | 1,496 | model/tests/riscv-tests/isa/rv64uzfh/move.S | # See LICENSE for license details.
#*****************************************************************************
# move.S
#-----------------------------------------------------------------------------
#
# This test verifies that the fmv.h.x, fmv.x.h, and fsgnj[x|n].d instructions
# and the fcsr work properly.
#
#inc... |
lizhirui/DreamCore | 1,055 | model/tests/riscv-tests/isa/rv64uzfh/fdiv.S | # See LICENSE for license details.
#*****************************************************************************
# fdiv.S
#-----------------------------------------------------------------------------
#
# Test f{div|sqrt}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_B... |
lizhirui/DreamCore | 1,122 | model/tests/riscv-tests/isa/rv64uzfh/recoding.S | # See LICENSE for license details.
#*****************************************************************************
# recoding.S
#-----------------------------------------------------------------------------
#
# Test corner cases of John Hauser's microarchitectural recoding scheme.
# There are twice as many recoded valu... |
lizhirui/DreamCore | 1,111 | model/tests/riscv-tests/isa/rv64uzfh/fclass.S | # See LICENSE for license details.
#*****************************************************************************
# fclass.S
#-----------------------------------------------------------------------------
#
# Test fclass.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGI... |
lizhirui/DreamCore | 1,229 | model/tests/riscv-tests/isa/rv64uzfh/fcvt.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt.S
#-----------------------------------------------------------------------------
#
# Test fcvt.h.{wu|w|lu|l}, fcvt.h.d, and fcvt.d.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"... |
lizhirui/DreamCore | 4,416 | model/tests/riscv-tests/isa/rv64uzfh/fcvt_w.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt_w.S
#-----------------------------------------------------------------------------
#
# Test fcvt{wu|w|lu|l}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_C... |
lizhirui/DreamCore | 1,380 | model/tests/riscv-tests/isa/rv64uzfh/fadd.S | # See LICENSE for license details.
#*****************************************************************************
# fadd.S
#-----------------------------------------------------------------------------
#
# Test f{add|sub|mul}.h instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_COD... |
lizhirui/DreamCore | 1,157 | model/tests/riscv-tests/isa/rv64mi/access.S | # See LICENSE for license details.
#*****************************************************************************
# access.S
#-----------------------------------------------------------------------------
#
# Test access-exception behavior.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_B... |
lizhirui/DreamCore | 3,404 | model/tests/riscv-tests/isa/rv64mi/illegal.S | # See LICENSE for license details.
#*****************************************************************************
# illegal.S
#-----------------------------------------------------------------------------
#
# Test illegal instruction trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_B... |
lizhirui/DreamCore | 2,449 | model/tests/riscv-tests/isa/rv64mi/breakpoint.S | # See LICENSE for license details.
#*****************************************************************************
# breakpoint.S
#-----------------------------------------------------------------------------
#
# Test breakpoints, if they are implemented.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64... |
lizhirui/DreamCore | 3,189 | model/tests/riscv-tests/isa/rv64mi/ma_addr.S | # See LICENSE for license details.
#*****************************************************************************
# ma_addr.S
#-----------------------------------------------------------------------------
#
# Test misaligned ld/st trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64M
RVTEST_CODE_BEGI... |
lizhirui/DreamCore | 1,872 | model/tests/riscv-tests/isa/rv64uf/fmin.S | # See LICENSE for license details.
#*****************************************************************************
# fmin.S
#-----------------------------------------------------------------------------
#
# Test f{min|max}.s instructinos.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BE... |
lizhirui/DreamCore | 1,629 | model/tests/riscv-tests/isa/rv64uf/fmadd.S | # See LICENSE for license details.
#*****************************************************************************
# fmadd.S
#-----------------------------------------------------------------------------
#
# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RV... |
lizhirui/DreamCore | 1,504 | model/tests/riscv-tests/isa/rv64uf/move.S | # See LICENSE for license details.
#*****************************************************************************
# move.S
#-----------------------------------------------------------------------------
#
# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions
# and the fcsr work properly.
#
#inc... |
lizhirui/DreamCore | 1,054 | model/tests/riscv-tests/isa/rv64uf/fdiv.S | # See LICENSE for license details.
#*****************************************************************************
# fdiv.S
#-----------------------------------------------------------------------------
#
# Test f{div|sqrt}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_B... |
lizhirui/DreamCore | 1,122 | model/tests/riscv-tests/isa/rv64uf/recoding.S | # See LICENSE for license details.
#*****************************************************************************
# recoding.S
#-----------------------------------------------------------------------------
#
# Test corner cases of John Hauser's microarchitectural recoding scheme.
# There are twice as many recoded valu... |
lizhirui/DreamCore | 1,414 | model/tests/riscv-tests/isa/rv64uf/fcmp.S | # See LICENSE for license details.
#*****************************************************************************
# fcmp.S
#-----------------------------------------------------------------------------
#
# Test f{eq|lt|le}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_B... |
lizhirui/DreamCore | 1,127 | model/tests/riscv-tests/isa/rv64uf/fcvt.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt.S
#-----------------------------------------------------------------------------
#
# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"... |
lizhirui/DreamCore | 4,360 | model/tests/riscv-tests/isa/rv64uf/fcvt_w.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt_w.S
#-----------------------------------------------------------------------------
#
# Test fcvt{wu|w|lu|l}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_... |
lizhirui/DreamCore | 1,380 | model/tests/riscv-tests/isa/rv64uf/fadd.S | # See LICENSE for license details.
#*****************************************************************************
# fadd.S
#-----------------------------------------------------------------------------
#
# Test f{add|sub|mul}.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_COD... |
lizhirui/DreamCore | 2,017 | model/tests/riscv-tests/isa/rv64ua/lrsc.S | # See LICENSE for license details.
#*****************************************************************************
# lrsr.S
#-----------------------------------------------------------------------------
#
# Test LR/SC instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
# g... |
lizhirui/DreamCore | 2,627 | model/tests/riscv-tests/isa/rv64si/dirty.S | # See LICENSE for license details.
#*****************************************************************************
# dirty.S
#-----------------------------------------------------------------------------
#
# Test VM referenced and dirty bits.
#
#include "riscv_test.h"
#include "test_macros.h"
#if (DRAM_BASE >> 30 << ... |
lizhirui/DreamCore | 2,003 | model/tests/riscv-tests/isa/rv64si/scall.S | # See LICENSE for license details.
#*****************************************************************************
# scall.S
#-----------------------------------------------------------------------------
#
# Test syscall trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_BEGIN
#ifdef _... |
lizhirui/DreamCore | 2,494 | model/tests/riscv-tests/isa/rv64si/icache-alias.S | # See LICENSE for license details.
#*****************************************************************************
# icache-alias.S
#-----------------------------------------------------------------------------
#
# Test that instruction memory appears to be physically addressed, i.e.,
# that disagreements in the low-or... |
lizhirui/DreamCore | 3,380 | model/tests/riscv-tests/isa/rv64si/ma_fetch.S | # See LICENSE for license details.
#*****************************************************************************
# ma_fetch.S
#-----------------------------------------------------------------------------
#
# Test misaligned fetch trap.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_BEG... |
lizhirui/DreamCore | 4,918 | model/tests/riscv-tests/isa/rv64si/csr.S | # See LICENSE for license details.
#*****************************************************************************
# csr.S
#-----------------------------------------------------------------------------
#
# Test CSRRx and CSRRxI instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64S
RVTEST_CODE_... |
lizhirui/DreamCore | 2,960 | model/tests/riscv-tests/isa/rv32um/mulhu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhu.S
#-----------------------------------------------------------------------------
#
# Test mulhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 2,923 | model/tests/riscv-tests/isa/rv32um/mulh.S | # See LICENSE for license details.
#*****************************************************************************
# mulh.S
#-----------------------------------------------------------------------------
#
# Test mulh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,997 | model/tests/riscv-tests/isa/rv32um/mulhsu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhsu.S
#-----------------------------------------------------------------------------
#
# Test mulhsu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
... |
lizhirui/DreamCore | 2,818 | model/tests/riscv-tests/isa/rv32um/mul.S | # See LICENSE for license details.
#*****************************************************************************
# mul.S
#-----------------------------------------------------------------------------
#
# Test mul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 1,794 | model/testcode/coremark/startup.S | # SPDX-License-Identifier: Apache-2.0
# Copyright 2019 Western Digital Corporation or its affiliates.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICE... |
lizhirui/DreamCore | 1,794 | model/testcode/dhrystone/startup.S | # SPDX-License-Identifier: Apache-2.0
# Copyright 2019 Western Digital Corporation or its affiliates.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICE... |
lizhirui/DreamCore | 1,984 | model/testcode/rt-thread/bsp/MyRISCVCore/MyRISCVCore/board/startup.S | /*
* Copyright (c) 2020-2020, AnnikaChip Development Team
*
* Change Logs:
* Date Author Notes
* 2020-11-08 lizhirui first version
*
*/
#include "riscv_encoding.h"
.section .init
.globl _start
.type _start,@function
/**
* Reset Handler called on controller reset
*/
_start... |
lizhirui/DreamCore | 6,553 | model/testcode/rt-thread/bsp/MyRISCVCore/MyRISCVCore/board/intexc.S | /*
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE... |
lizhirui/DreamCore | 5,089 | model/testcode/rt-thread/libcpu/common/context_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting implementation
* 2018/12/27 Jesven Add SMP support
*/
#include "cpuport.h"
#ifdef RT_USING_SMP... |
lizhirui/DreamCore | 5,319 | model/testcode/rt-thread/libcpu/risc-v/myriscvcore/context_gcc.S | /*
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/03/26 Huaqi First Nuclei RISC-V porting implementation
*/
#include "riscv_encoding.h"
#ifndef __riscv_32e
#define RT_SAVED_REGNUM ... |
lizhirui/DreamCore | 4,618 | model/testcode/rt-thread/libcpu/risc-v/myriscvcore/interrupt_gcc.S | /*
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/03/26 hqfang First Nuclei RISC-V porting implementation
*/
#include "riscv_encoding.h"
.section .text.entry
.align 8
/**
* \br... |
lizhirui/DreamCore | 3,020 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m7/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m7
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_... |
lizhirui/DreamCore | 2,972 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m7/lwp_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint3... |
lizhirui/DreamCore | 3,071 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m7/lwp_rvds.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys... |
lizhirui/DreamCore | 1,381 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-a/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x1... |
lizhirui/DreamCore | 1,545 | model/testcode/rt-thread/components/lwp/arch/arm/arm926/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x1... |
lizhirui/DreamCore | 3,020 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m3/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m3
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_... |
lizhirui/DreamCore | 2,972 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m3/lwp_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint3... |
lizhirui/DreamCore | 3,071 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m3/lwp_rvds.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys... |
lizhirui/DreamCore | 3,020 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m4/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m4
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_... |
lizhirui/DreamCore | 2,972 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m4/lwp_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint3... |
lizhirui/DreamCore | 3,071 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-m4/lwp_rvds.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys... |
lizhirui/DreamCore | 1,380 | model/testcode/rt-thread/components/lwp/arch/arm/cortex-a9/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x1... |
LoCryptEn/Key-security | 84,351 | Cache-bound/GMIn_Cache/Nortm/Kernel/sm4_dec_master.S | .section .data
sbox:
.byte 0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05,0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99,0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62,0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x... |
LoCryptEn/Key-security | 55,142 | Cache-bound/GMIn_Cache/Nortm/Kernel/sm4_enc.S | .section .data
sbox:
.byte 0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05,0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99,0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62,0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x... |
LoCryptEn/Key-security | 86,021 | Cache-bound/GMIn_Cache/Nortm/Kernel/sm4_dec.S | .section .data
sbox:
.byte 0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05,0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99,0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62,0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x... |
LoCryptEn/Key-security | 54,545 | Cache-bound/GMIn_Cache/Nortm/Kernel/sm4_enc_master.S | .section .data
sbox:
.byte 0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05,0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99,0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62,0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x... |
LoCryptEn/Key-security | 4,561 | Cache-bound/DilithiumIn_Cache/Nortm/Kernel/aesni.S | .section .text
.type aes_enc, @function
.type aes_dec, @function
.type aes_enc_master, @function
.type aes_dec_master, @function
.globl aes_enc
.globl aes_dec
.globl aes_enc_master
.globl aes_dec_master
.macro key_expand RCON DEST INV=0
aeskeygenassist \RCON, %xmm0, %xmm1
call key_combine
.if \INV
aesimc... |
LoCryptEn/Key-security | 4,561 | Cache-bound/ECDSA_Cache/Nortm/Kernel/aesni.S | .section .text
.type aes_enc, @function
.type aes_dec, @function
.type aes_enc_master, @function
.type aes_dec_master, @function
.globl aes_enc
.globl aes_dec
.globl aes_enc_master
.globl aes_dec_master
.macro key_expand RCON DEST INV=0
aeskeygenassist \RCON, %xmm0, %xmm1
call key_combine
.if \INV
aesimc... |
LoCryptEn/Key-security | 106,919 | Register-bound/RSAIn_Register/Kernel/RSA_function.S |
#include "montexp_AES.S"
.file "RSA_function.S"
.text
##################################################################################################
### ###
### mul1024(A,B): ###
### ###
### R=A*B ###
### ###
### ###
#############################################... |
LoCryptEn/Key-security | 137,966 | Register-bound/RSAIn_Register/Kernel/montmul.S | #include "rsa_head.S"
.file "montmul.S"
.text
##################################################################################################
### ###
### montmul(A,B,M,n0): ###
### ###
### R=A*B*R^(-1) mod M ###
### ###
### ###
#######################################... |
LoCryptEn/Key-security | 7,059 | Register-bound/RSAIn_Register/Kernel/rsa_head.S | .file "rsa_head.S"
.text
##################################################################################################
### ###
### montmul_1st montsqu_1st ###
### ###
##################################################################################################
/* 16 256bi... |
LoCryptEn/Key-security | 139,044 | Register-bound/RSAIn_Register/Kernel/montsqu.S | #include "rsa_head.S"
.file "montsqu.S"
.text
##################################################################################################
### ###
### montsqu(A,M,n0): ###
### ###
### R=A*A*R^(-1) mod M ###
### ###
### ###
#########################################... |
LoCryptEn/Key-security | 17,343 | Register-bound/RSAIn_Register/Kernel/montexp_AES.S | #include "montexp.S"
#include "aesni.S"
.file "montexp_AES.S"
.text
##################################################################################################
### ###
### montexp1024_AES_p: load exp argument ###
### Dec argument ###
### Call montexp ###
### E... |
LoCryptEn/Key-security | 63,351 | Register-bound/RSAIn_Register/Kernel/call_rrmontmul.S | .file "call_rrmontmul.s"
.text
# A0-A31
.set A0, %zmm0
.set B0, %zmm1
.set R0, %zmm3
.set T, %zmm4
#TT for temp register
.set TT, %zmm9
.set A1, %zmm5
.set A2, %zmm6
.set A3, %zmm7
.set A4, %zmm8
.set B1, %zmm11
.set B2, %zmm12
.set B3, %zmm13
.set B4, %zmm14
.set R5, %zmm... |
LoCryptEn/Key-security | 6,461 | Register-bound/RSAIn_Register/Kernel/VIRSA.S |
//#include "kernel.h"
#include "RSA_function.S"
.file "VIRSA.S"
.text
##################################################################################################
### ###
### montmul2014_test ###
### ###
### ###
### ###
##############################################... |
LoCryptEn/Key-security | 16,395 | Register-bound/RSAIn_Register/Kernel/montexp.S | #include "montmul.S"
#include "montsqu.S"
#include "aesni.S"
//#include "montmul_raw.S"
//#include "montsqu_raw.S"
.file "montexp.S"
.data
my_var: .quad 0x123344
.text
##################################################################################################
### ###
### montexp(A,Ex... |
LoCryptEn/Key-security | 5,765 | Register-bound/RSAIn_Register/Kernel/aesni.S | .file "aes.S"
.text
#ifndef AES_NI
#define AES_NI
.set rstate, %xmm0 //AES state
.set rhelp, %xmm1 //helping reg 1
.set round_key_i, %xmm2 //round key i
.set round_key_j, %xmm3 //round key j
.set mes, %xmm15 //message
.macro key_shedule r0 r1 rcon
pxor ... |
LoCryptEn/Key-security | 165,226 | Register-bound/RSAIn_Register/Kernel/Comcq.S | #include "aesni.S"
#include "rsa_head.S"
.file "Comcq.S"
.text
.macro store_B
##################################################################################################
#### store B ####
vshufpd $0x05, A0, A0, T3 #imm=0101
vmovq T3xmm, %rax #q0=B[0] s0=B[8]
movq %rax, q0
vperm2i128 $0x01, ... |
LoCryptEn/Key-security | 3,064 | Register-bound/ECCIn_Register/User/aes.S | .file "aes.S"
.text
// Register assignments
.set rstate, %xmm0 // AES state (message)
.set rk0, %xmm1 // Round key 0 (initial key)
.set rk1, %xmm2 // Round key 1
.set rk2, %xmm3 // Round key 2
.set rk3, %xmm4 // Round key 3
.set rk4, %xmm5 // Round key 4
.set rk5, ... |
LoCryptEn/Key-security | 5,552 | Register-bound/ECCIn_Register/Kernel/montmul_n256_xmm.S | // Montmul n256
// n256: 0xffffffff00000000ffffffffffffffffbce6faada7179e84f3b9cac2fc632551
// Input: x(256 bits in [xmm28 | xmm29]), y(256 bits in [xmm30 | xmm31])
// Output: x * y * R^-1 store in [xmm26 | xmm27]
// Macro "mulpadd i x" adds %rdx * x to the (i,i+1) position of
// the rotating register window %r15,.... |
LoCryptEn/Key-security | 3,064 | Register-bound/ECCIn_Register/Kernel/aes.S | .file "aes.S"
.text
// Register assignments
.set rstate, %xmm0 // AES state (message)
.set rk0, %xmm1 // Round key 0 (initial key)
.set rk1, %xmm2 // Round key 1
.set rk2, %xmm3 // Round key 2
.set rk3, %xmm4 // Round key 3
.set rk4, %xmm5 // Round key 4
.set rk5, ... |
LoCryptEn/Key-security | 5,146 | Register-bound/ECCIn_Register/Kernel/SecSig.S | .file "SecSig.S"
.section .data
.align 16
SHUFFLE_MASK:
.quad 0x08090a0b0c0d0e0f
.quad 0x0001020304050607
.section .text
// [r8 | r9 | r10 | r11] + [r12 | r13 | r14 | r15] mod n256 & save to [xmm30 | xmm31]
.macro addmod
add %r11, %r15
adc %r10, %r14
adc %r9, %r13
... |
lucadentella/esp32-tutorial | 10,220 | 18_u8g2/components/u8g2/sys/arm/stm32l031x6/stm32l0xx/src/startup_stm32l031xx.s | /*
Source: en.stm32cubel0.zip
STM32Cube_FW_L0_V1.8.0/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc
*/
/**
******************************************************************************
* @file startup_stm32l031xx.s
* @author MCD Application Team
* @version V1.7.1
* @date 25-November-20... |
lucadentella/esp32-tutorial | 10,220 | 22_deep_sleep/components/u8g2/sys/arm/stm32l031x6/stm32l0xx/src/startup_stm32l031xx.s | /*
Source: en.stm32cubel0.zip
STM32Cube_FW_L0_V1.8.0/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc
*/
/**
******************************************************************************
* @file startup_stm32l031xx.s
* @author MCD Application Team
* @version V1.7.1
* @date 25-November-20... |
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