repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
liva/minimal-linux | 2,662 | arch/x86/lib/getuser.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* __get_user functions.
*
* (C) Copyright 1998 Linus Torvalds
* (C) Copyright 2005 Andi Kleen
* (C) Copyright 2008 Glauber Costa
*
* These functions have a non-standard call interface
* to make them more efficient, especially as they
* return an error value in addition... |
liva/minimal-linux | 10,392 | arch/x86/lib/checksum_32.S | /*
* INET An implementation of the TCP/IP protocol suite for the LINUX
* operating system. INET is implemented using the BSD Socket
* interface as the means of communication with the user level.
*
* IP/TCP/UDP checksumming routines
*
* Authors: Jorge Cwik, <jorge@laser.satlink.net>
* Arnt Gulbrandsen, <a... |
liva/minimal-linux | 2,036 | arch/x86/lib/putuser.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* __put_user functions.
*
* (C) Copyright 2005 Linus Torvalds
* (C) Copyright 2005 Andi Kleen
* (C) Copyright 2008 Glauber Costa
*
* These functions have a non-standard call interface
* to make them more efficient, especially as they
* return an error value in addition... |
liva/minimal-linux | 2,553 | arch/x86/lib/atomic64_386_32.S | /*
* atomic64_t for 386/486
*
* Copyright © 2010 Luca Barbieri
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version... |
liva/minimal-linux | 6,329 | arch/x86/lib/memcpy_64.S | /* Copyright 2002 Andi Kleen */
#include <linux/linkage.h>
#include <asm/errno.h>
#include <asm/cpufeatures.h>
#include <asm/alternative-asm.h>
#include <asm/export.h>
/*
* We build a jump to memcpy_orig by default which gets NOPped out on
* the majority of x86 CPUs which set REP_GOOD. In addition, CPUs which
* ha... |
liva/minimal-linux | 1,837 | arch/x86/lib/copy_page_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/* Written 2003 by Andi Kleen, based on a kernel by Evandro Menezes */
#include <linux/linkage.h>
#include <asm/cpufeatures.h>
#include <asm/alternative-asm.h>
#include <asm/export.h>
/*
* Some CPUs run faster using the string copy instructions (sane microcode).
* It is also a... |
liva/minimal-linux | 1,165 | arch/x86/lib/cmpxchg16b_emu.S | /*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*
*/
#include <linux/linkage.h>
#include <asm/percpu.h>
.text
/*
* Inputs:
* %rsi : memory location to co... |
liva/minimal-linux | 4,376 | arch/x86/mm/mem_encrypt_boot.S | /*
* AMD Memory Encryption Support
*
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* Author: Tom Lendacky <thomas.lendacky@amd.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software... |
liva/minimal-linux | 1,605 | arch/x86/entry/thunk_64.S | /*
* Save registers before calling assembly functions. This avoids
* disturbance of register allocation in some inline assembly constructs.
* Copyright 2001,2002 by Andi Kleen, SuSE Labs.
* Added trace_hardirqs callers - Copyright 2007 Steven Rostedt, Red Hat, Inc.
* Subject to the GNU public license, v.2. No warr... |
liva/minimal-linux | 50,457 | arch/x86/entry/entry_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/x86_64/entry.S
*
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
*
* entry.S contains the system-call and fault low-level handling routines.
*
* Some o... |
liva/minimal-linux | 12,289 | arch/x86/entry/entry_64_compat.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Compatibility mode system call entry point for x86-64.
*
* Copyright 2000-2002 Andi Kleen, SuSE Labs.
*/
#include "calling.h"
#include <asm/asm-offsets.h>
#include <asm/current.h>
#include <asm/errno.h>
#include <asm/ia32_unistd.h>
#include <asm/thread_info.h>
#include <a... |
liva/minimal-linux | 26,805 | arch/x86/entry/entry_32.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 1991,1992 Linus Torvalds
*
* entry_32.S contains the system-call and low-level fault and trap handling routines.
*
* Stack layout while running C code:
* ptrace needs to have all registers on the stack.
* If the order here is changed, it needs to be
* ... |
liva/minimal-linux | 9,990 | arch/x86/kernel/vmlinux.lds.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* ld script for the x86 kernel
*
* Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>
*
* Modernisation, unification and other changes and fixes:
* Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org>
*
*
* Don't define absolute symbols... |
liva/minimal-linux | 5,131 | arch/x86/kernel/ftrace_32.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 Steven Rostedt, VMware Inc.
*/
#include <linux/linkage.h>
#include <asm/page_types.h>
#include <asm/segment.h>
#include <asm/export.h>
#include <asm/ftrace.h>
#include <asm/nospec-branch.h>
#ifdef CC_USING_FENTRY
# define function_hook __fentry__
EXPO... |
liva/minimal-linux | 12,830 | arch/x86/kernel/head_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
*
* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
* Copyright (C) 2001,2002 Andi Kl... |
liva/minimal-linux | 14,663 | arch/x86/kernel/head_32.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
*
* Copyright (C) 1991, 1992 Linus Torvalds
*
* Enhanced CPU detection and feature setting code by Mike Jagdis
* and Martin Mares, November 1997.
*/
.text
#include <linux/threads.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/segment.h>
#include ... |
liva/minimal-linux | 8,198 | arch/x86/kernel/ftrace_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014 Steven Rostedt, Red Hat Inc
*/
#include <linux/linkage.h>
#include <asm/ptrace.h>
#include <asm/ftrace.h>
#include <asm/export.h>
#include <asm/nospec-branch.h>
#include <asm/unwind_hints.h>
.code64
.section .entry.text, "ax"
#ifdef CC_USING_FENTRY... |
liva/minimal-linux | 5,697 | arch/x86/kernel/relocate_kernel_32.S | /*
* relocate_kernel.S - put the kernel image in place to boot
* Copyright (C) 2002-2004 Eric Biederman <ebiederm@xmission.com>
*
* This source code is licensed under the GNU General Public License,
* Version 2. See the file COPYING for more details.
*/
#include <linux/linkage.h>
#include <asm/page_types.h>
#i... |
liva/minimal-linux | 5,653 | arch/x86/kernel/relocate_kernel_64.S | /*
* relocate_kernel.S - put the kernel image in place to boot
* Copyright (C) 2002-2005 Eric Biederman <ebiederm@xmission.com>
*
* This source code is licensed under the GNU General Public License,
* Version 2. See the file COPYING for more details.
*/
#include <linux/linkage.h>
#include <asm/page_types.h>
#i... |
liva/minimal-linux | 3,810 | arch/x86/kernel/verify_cpu.S | /*
*
* verify_cpu.S - Code for cpu long mode and SSE verification. This
* code has been borrowed from boot/setup.S and was introduced by
* Andi Kleen.
*
* Copyright (c) 2007 Andi Kleen (ak@suse.de)
* Copyright (c) 2007 Eric Biederman (ebiederm@xmission.com)
* Copyright (c) 2007 Vivek Goyal (vgoyal@in.ibm.co... |
liva/minimal-linux | 2,407 | arch/x86/boot/compressed/mem_encrypt.S | /*
* AMD Memory Encryption Support
*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* Author: Tom Lendacky <thomas.lendacky@amd.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software... |
liva/minimal-linux | 1,216 | arch/x86/boot/compressed/vmlinux.lds.S | /* SPDX-License-Identifier: GPL-2.0 */
#include <asm-generic/vmlinux.lds.h>
OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT, CONFIG_OUTPUT_FORMAT)
#undef i386
#include <asm/cache.h>
#include <asm/page_types.h>
#ifdef CONFIG_X86_64
OUTPUT_ARCH(i386:x86-64)
ENTRY(startup_64)
#else
OUTPUT_ARCH(i386)
ENTRY(sta... |
liva/minimal-linux | 12,648 | arch/x86/boot/compressed/head_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/boot/head.S
*
* Copyright (C) 1991, 1992, 1993 Linus Torvalds
*/
/*
* head.S contains the 32-bit startup code.
*
* NOTE!!! Startup happens at absolute address 0x00001000, which is also where
* the page directory will exist. The startup code will be overwrit... |
liva/minimal-linux | 6,277 | arch/x86/boot/compressed/head_32.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/boot/head.S
*
* Copyright (C) 1991, 1992, 1993 Linus Torvalds
*/
/*
* head.S contains the 32-bit startup code.
*
* NOTE!!! Startup happens at absolute address 0x00001000, which is also where
* the page directory will exist. The startup code will be overwrit... |
liva/minimal-linux | 3,694 | arch/x86/boot/compressed/efi_thunk_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2014, 2015 Intel Corporation; author Matt Fleming
*
* Early support for invoking 32-bit EFI services from a 64-bit kernel.
*
* Because this thunking occurs before ExitBootServices() we have to
* restore the firmware's 32-bit GDT before we make EFI serivce ... |
liva/minimal-linux | 2,348 | arch/x86/boot/compressed/efi_stub_32.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* EFI call stub for IA32.
*
* This stub allows us to make EFI calls in physical mode with interrupts
* turned off. Note that this implementation is different from the one in
* arch/x86/platform/efi/efi_stub_32.S because we're _already_ in physical
* mode at this point.
*... |
liva/minimal-linux | 2,905 | arch/x86/entry/vdso/vdso-layout.lds.S | /* SPDX-License-Identifier: GPL-2.0 */
#include <asm/vdso.h>
/*
* Linker script for vDSO. This is an ELF shared object prelinked to
* its virtual address, and with only one read-only segment.
* This script controls its layout.
*/
#if defined(BUILD_VDSO64)
# define SHDR_SIZE 64
#elif defined(BUILD_VDSO32) || defi... |
liva/minimal-linux | 4,861 | arch/x86/entry/vdso/vdso32/sigreturn.S | /* SPDX-License-Identifier: GPL-2.0 */
#include <linux/linkage.h>
#include <asm/unistd_32.h>
#include <asm/asm-offsets.h>
#ifndef SYSCALL_ENTER_KERNEL
#define SYSCALL_ENTER_KERNEL int $0x80
#endif
.text
.globl __kernel_sigreturn
.type __kernel_sigreturn,@function
nop /* this guy is needed for .LSTARTFDEDLSI1 belo... |
liva/minimal-linux | 2,410 | arch/x86/entry/vdso/vdso32/system_call.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* AT_SYSINFO entry point
*/
#include <linux/linkage.h>
#include <asm/dwarf2.h>
#include <asm/cpufeatures.h>
#include <asm/alternative-asm.h>
.text
.globl __kernel_vsyscall
.type __kernel_vsyscall,@function
ALIGN
__kernel_vsyscall:
CFI_STARTPROC
/*
* Reshuffle regs so... |
liva/minimal-linux | 1,715 | arch/x86/entry/vdso/vdso32/note.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* This supplies .note.* sections to go into the PT_NOTE inside the vDSO text.
* Here we can supply some information useful to userland.
*/
#include <linux/version.h>
#include <linux/elfnote.h>
/* Ideally this would use UTS_NAME, but using a quoted string here
doesn't wo... |
liva/minimal-linux | 2,974 | arch/x86/kernel/acpi/wakeup_64.S | .text
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/pgtable_types.h>
#include <asm/page_types.h>
#include <asm/msr.h>
#include <asm/asm-offsets.h>
#include <asm/frame.h>
# Copyright 2003 Pavel Machek <pavel@suse.cz>, distribute under GPLv2
.code64
/*
* Hooray, we are in Long 64-bit mode (but st... |
liva/minimal-linux | 1,717 | arch/x86/kernel/acpi/wakeup_32.S | .text
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/page_types.h>
# Copyright 2003, 2008 Pavel Machek <pavel@suse.cz>, distribute under GPLv2
.code32
ALIGN
ENTRY(wakeup_pmode_return)
wakeup_pmode_return:
movw $__KERNEL_DS, %ax
movw %ax, %ss
movw %ax, %fs
movw %ax, %gs
movw $__USER_DS, %a... |
liva/minimal-linux | 4,185 | arch/x86/realmode/rm/reboot.S | /* SPDX-License-Identifier: GPL-2.0 */
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/page_types.h>
#include <asm/processor-flags.h>
#include <asm/msr-index.h>
#include "realmode.h"
/*
* The following code and data reboots the machine by switching to real
* mode and jumping to the BIOS reset entry... |
liva/minimal-linux | 1,871 | arch/x86/realmode/rm/trampoline_32.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
*
* Trampoline.S Derived from Setup.S by Linus Torvalds
*
* 4 Jan 1997 Michael Chastain: changed to gnu as.
*
* This is only used for booting secondary CPUs in SMP machine
*
* Entry: CS:IP point to the start of our code, we are
* in real mode with no stack, but the res... |
liva/minimal-linux | 4,454 | arch/x86/realmode/rm/trampoline_64.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
*
* Trampoline.S Derived from Setup.S by Linus Torvalds
*
* 4 Jan 1997 Michael Chastain: changed to gnu as.
* 15 Sept 2005 Eric Biederman: 64bit PIC support
*
* Entry: CS:IP point to the start of our code, we are
* in real mode with no stack, but the rest of the
* tram... |
liva/minimal-linux | 3,765 | arch/x86/realmode/rm/wakeup_asm.S | /* SPDX-License-Identifier: GPL-2.0 */
/*
* ACPI wakeup real mode startup stub
*/
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/msr-index.h>
#include <asm/page_types.h>
#include <asm/pgtable_types.h>
#include <asm/processor-flags.h>
#include "realmode.h"
#include "wakeup.h"
.code16
/* This shou... |
lizhirui/DreamCore | 1,879 | software/coremark_app/startup.S | # SPDX-License-Identifier: Apache-2.0
# Copyright 2019 Western Digital Corporation or its affiliates.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICE... |
lizhirui/DreamCore | 1,879 | software/dhrystone_app/startup.S | # SPDX-License-Identifier: Apache-2.0
# Copyright 2019 Western Digital Corporation or its affiliates.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICE... |
lizhirui/DreamCore | 1,481 | software/bootloader/main/src/startup.S | //#define USE_MODEL
.section .text.entry
.global _start
_start:
csrw minstret, zero
csrw minstreth, zero
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15... |
lizhirui/DreamCore | 1,048 | software/hello_world_app/main/src/startup.S | //#define USE_MODEL
.section .text.entry
.global _start
_start:
csrw minstret, zero
csrw minstreth, zero
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15... |
lizhirui/DreamCore | 2,077 | software/ext_int_test_app/main/src/startup.S | //#define USE_MODEL
.section .text.entry
.global _start
_start:
csrw minstret, zero
csrw minstreth, zero
la t0, trap_entry
csrw mtvec, t0
li t0, 0x800
csrw mie, t0
li t0, 0x00000008
csrw mstatus, t0
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
... |
lizhirui/DreamCore | 1,984 | software/rtthread_app/bsp/MyRISCVCore/MyRISCVCore/board/startup.S | /*
* Copyright (c) 2020-2020, AnnikaChip Development Team
*
* Change Logs:
* Date Author Notes
* 2020-11-08 lizhirui first version
*
*/
#include "riscv_encoding.h"
.section .init
.globl _start
.type _start,@function
/**
* Reset Handler called on controller reset
*/
_start... |
lizhirui/DreamCore | 6,553 | software/rtthread_app/bsp/MyRISCVCore/MyRISCVCore/board/intexc.S | /*
* Copyright (c) 2019 Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE... |
lizhirui/DreamCore | 5,089 | software/rtthread_app/libcpu/common/context_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting implementation
* 2018/12/27 Jesven Add SMP support
*/
#include "cpuport.h"
#ifdef RT_USING_SMP... |
lizhirui/DreamCore | 5,319 | software/rtthread_app/libcpu/risc-v/myriscvcore/context_gcc.S | /*
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/03/26 Huaqi First Nuclei RISC-V porting implementation
*/
#include "riscv_encoding.h"
#ifndef __riscv_32e
#define RT_SAVED_REGNUM ... |
lizhirui/DreamCore | 4,618 | software/rtthread_app/libcpu/risc-v/myriscvcore/interrupt_gcc.S | /*
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/03/26 hqfang First Nuclei RISC-V porting implementation
*/
#include "riscv_encoding.h"
.section .text.entry
.align 8
/**
* \br... |
ljessendk/CanFestival | 7,288 | examples/gene_SYNC_HCS12/vectors.s | ;;/* M68HC11 Interrupt vectors table
;; Copyright (C) 1999 Free Software Foundation, Inc.
;; Written by Stephane Carrez (stcarrez@worldnet.fr)
;;
;;This file is free software; you can redistribute it and/or modify it
;;under the terms of the GNU General Public License as published by the
;;Free Software Foundation... |
lizhirui/DreamCore | 3,020 | software/rtthread_app/components/lwp/arch/arm/cortex-m7/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m7
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_... |
lizhirui/DreamCore | 2,972 | software/rtthread_app/components/lwp/arch/arm/cortex-m7/lwp_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint3... |
lizhirui/DreamCore | 3,071 | software/rtthread_app/components/lwp/arch/arm/cortex-m7/lwp_rvds.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys... |
lizhirui/DreamCore | 1,381 | software/rtthread_app/components/lwp/arch/arm/cortex-a/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x1... |
lizhirui/DreamCore | 1,545 | software/rtthread_app/components/lwp/arch/arm/arm926/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x1... |
lizhirui/DreamCore | 3,020 | software/rtthread_app/components/lwp/arch/arm/cortex-m3/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m3
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_... |
lizhirui/DreamCore | 2,972 | software/rtthread_app/components/lwp/arch/arm/cortex-m3/lwp_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint3... |
lizhirui/DreamCore | 3,071 | software/rtthread_app/components/lwp/arch/arm/cortex-m3/lwp_rvds.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys... |
lizhirui/DreamCore | 3,020 | software/rtthread_app/components/lwp/arch/arm/cortex-m4/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m4
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_... |
lizhirui/DreamCore | 2,972 | software/rtthread_app/components/lwp/arch/arm/cortex-m4/lwp_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint3... |
lizhirui/DreamCore | 3,071 | software/rtthread_app/components/lwp/arch/arm/cortex-m4/lwp_rvds.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys... |
lizhirui/DreamCore | 1,380 | software/rtthread_app/components/lwp/arch/arm/cortex-a9/lwp_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x1... |
lizhirui/DreamCore | 4,073 | model/tests/riscv-tests/benchmarks/common/crt.S | # See LICENSE for license details.
#include "encoding.h"
#if __riscv_xlen == 64
# define LREG ld
# define SREG sd
# define REGBYTES 8
#else
# define LREG lw
# define SREG sw
# define REGBYTES 4
#endif
.section ".text.init"
.globl _start
_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6... |
lizhirui/DreamCore | 1,159 | model/tests/riscv-tests/isa/rv64ud/structural.S | # See LICENSE for license details.
#*****************************************************************************
# structural.S
#-----------------------------------------------------------------------------
#
# This test verifies that the FPU correctly obviates structural hazards on its
# writeback port (e.g. fadd fo... |
lizhirui/DreamCore | 2,044 | model/tests/riscv-tests/isa/rv64ud/fmin.S | # See LICENSE for license details.
#*****************************************************************************
# fmin.S
#-----------------------------------------------------------------------------
#
# Test f{min|max}.d instructinos.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BE... |
lizhirui/DreamCore | 1,803 | model/tests/riscv-tests/isa/rv64ud/fmadd.S | # See LICENSE for license details.
#*****************************************************************************
# fmadd.S
#-----------------------------------------------------------------------------
#
# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RV... |
lizhirui/DreamCore | 3,659 | model/tests/riscv-tests/isa/rv64ud/move.S | # See LICENSE for license details.
#*****************************************************************************
# move.S
#-----------------------------------------------------------------------------
#
# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly.
#
#include "riscv_test.h"
#include "te... |
lizhirui/DreamCore | 1,028 | model/tests/riscv-tests/isa/rv64ud/ldst.S | # See LICENSE for license details.
#*****************************************************************************
# ldst.S
#-----------------------------------------------------------------------------
#
# This test verifies that flw, fld, fsw, and fsd work properly.
#
#include "riscv_test.h"
#include "test_macros.h"... |
lizhirui/DreamCore | 1,521 | model/tests/riscv-tests/isa/rv64ud/fdiv.S | # See LICENSE for license details.
#*****************************************************************************
# fdiv.S
#-----------------------------------------------------------------------------
#
# Test f{div|sqrt}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_B... |
lizhirui/DreamCore | 1,686 | model/tests/riscv-tests/isa/rv64ud/recoding.S | # See LICENSE for license details.
#*****************************************************************************
# recoding.S
#-----------------------------------------------------------------------------
#
# Test corner cases of John Hauser's microarchitectural recoding scheme.
# There are twice as many recoded valu... |
lizhirui/DreamCore | 1,594 | model/tests/riscv-tests/isa/rv64ud/fcmp.S | # See LICENSE for license details.
#*****************************************************************************
# fcmp.S
#-----------------------------------------------------------------------------
#
# Test f{eq|lt|le}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_B... |
lizhirui/DreamCore | 1,229 | model/tests/riscv-tests/isa/rv64ud/fclass.S | # See LICENSE for license details.
#*****************************************************************************
# fclass.S
#-----------------------------------------------------------------------------
#
# Test fclass.d instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_CODE_BEGIN... |
lizhirui/DreamCore | 1,876 | model/tests/riscv-tests/isa/rv64ud/fcvt.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt.S
#-----------------------------------------------------------------------------
#
# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
#
#include "riscv_test.h"
#include "test_macros.h"... |
lizhirui/DreamCore | 4,731 | model/tests/riscv-tests/isa/rv64ud/fcvt_w.S | # See LICENSE for license details.
#*****************************************************************************
# fcvt_w.S
#-----------------------------------------------------------------------------
#
# Test fcvt{wu|w|lu|l}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_... |
lizhirui/DreamCore | 1,553 | model/tests/riscv-tests/isa/rv64ud/fadd.S | # See LICENSE for license details.
#*****************************************************************************
# fadd.S
#-----------------------------------------------------------------------------
#
# Test f{add|sub|mul}.d instructions.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UF
RVTEST_COD... |
lizhirui/DreamCore | 2,953 | model/tests/riscv-tests/isa/rv64ssvnapot/napot.S | # See LICENSE for license details.
#*****************************************************************************
# napot.S
#-----------------------------------------------------------------------------
#
# Test Svnapot
#
#include "riscv_test.h"
#include "test_macros.h"
#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
# err... |
lizhirui/DreamCore | 3,981 | model/tests/riscv-tests/isa/rv64uc/rvc.S | # See LICENSE for license details.
#*****************************************************************************
# rvc.S
#-----------------------------------------------------------------------------
#
# Test RVC corner cases.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
.ali... |
lizhirui/DreamCore | 2,651 | model/tests/riscv-tests/isa/rv64ui/xor.S | # See LICENSE for license details.
#*****************************************************************************
# xor.S
#-----------------------------------------------------------------------------
#
# Test xor instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 3,122 | model/tests/riscv-tests/isa/rv64ui/sub.S | # See LICENSE for license details.
#*****************************************************************************
# sub.S
#-----------------------------------------------------------------------------
#
# Test sub instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,308 | model/tests/riscv-tests/isa/rv64ui/lw.S | # See LICENSE for license details.
#*****************************************************************************
# lw.S
#-----------------------------------------------------------------------------
#
# Test lw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 2,748 | model/tests/riscv-tests/isa/rv64ui/sltu.S | # See LICENSE for license details.
#*****************************************************************************
# sltu.S
#-----------------------------------------------------------------------------
#
# Test sltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,538 | model/tests/riscv-tests/isa/rv64ui/bgeu.S | # See LICENSE for license details.
#*****************************************************************************
# bgeu.S
#-----------------------------------------------------------------------------
#
# Test bgeu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,175 | model/tests/riscv-tests/isa/rv64ui/slti.S | # See LICENSE for license details.
#*****************************************************************************
# slti.S
#-----------------------------------------------------------------------------
#
# Test slti instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 4,229 | model/tests/riscv-tests/isa/rv64ui/sll.S | # See LICENSE for license details.
#*****************************************************************************
# sll.S
#-----------------------------------------------------------------------------
#
# Test sll instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 4,389 | model/tests/riscv-tests/isa/rv64ui/sraw.S | # See LICENSE for license details.
#*****************************************************************************
# sraw.S
#-----------------------------------------------------------------------------
#
# Test sraw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,345 | model/tests/riscv-tests/isa/rv64ui/addi.S | # See LICENSE for license details.
#*****************************************************************************
# addi.S
#-----------------------------------------------------------------------------
#
# Test addi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 4,358 | model/tests/riscv-tests/isa/rv64ui/sllw.S | # See LICENSE for license details.
#*****************************************************************************
# sllw.S
#-----------------------------------------------------------------------------
#
# Test sllw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,345 | model/tests/riscv-tests/isa/rv64ui/ld.S | # See LICENSE for license details.
#*****************************************************************************
# ld.S
#-----------------------------------------------------------------------------
#
# Test ld instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 1,680 | model/tests/riscv-tests/isa/rv64ui/andi.S | # See LICENSE for license details.
#*****************************************************************************
# andi.S
#-----------------------------------------------------------------------------
#
# Test andi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 4,389 | model/tests/riscv-tests/isa/rv64ui/srlw.S | # See LICENSE for license details.
#*****************************************************************************
# srlw.S
#-----------------------------------------------------------------------------
#
# Test srlw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,310 | model/tests/riscv-tests/isa/rv64ui/lhu.S | # See LICENSE for license details.
#*****************************************************************************
# lhu.S
#-----------------------------------------------------------------------------
#
# Test lhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,633 | model/tests/riscv-tests/isa/rv64ui/and.S | # See LICENSE for license details.
#*****************************************************************************
# and.S
#-----------------------------------------------------------------------------
#
# Test and instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,366 | model/tests/riscv-tests/isa/rv64ui/bltu.S | # See LICENSE for license details.
#*****************************************************************************
# bltu.S
#-----------------------------------------------------------------------------
#
# Test bltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 2,959 | model/tests/riscv-tests/isa/rv64ui/slliw.S | # See LICENSE for license details.
#*****************************************************************************
# slliw.S
#-----------------------------------------------------------------------------
#
# Test slliw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#... |
lizhirui/DreamCore | 2,642 | model/tests/riscv-tests/isa/rv64ui/sh.S | # See LICENSE for license details.
#*****************************************************************************
# sh.S
#-----------------------------------------------------------------------------
#
# Test sh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 3,452 | model/tests/riscv-tests/isa/rv64ui/srl.S | # See LICENSE for license details.
#*****************************************************************************
# srl.S
#-----------------------------------------------------------------------------
#
# Test srl instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,610 | model/tests/riscv-tests/isa/rv64ui/sb.S | # See LICENSE for license details.
#*****************************************************************************
# sb.S
#-----------------------------------------------------------------------------
#
# Test sb instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 2,028 | model/tests/riscv-tests/isa/rv64ui/beq.S | # See LICENSE for license details.
#*****************************************************************************
# beq.S
#-----------------------------------------------------------------------------
#
# Test beq instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,750 | model/tests/riscv-tests/isa/rv64ui/sd.S | # See LICENSE for license details.
#*****************************************************************************
# sd.S
#-----------------------------------------------------------------------------
#
# Test sd instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#------... |
lizhirui/DreamCore | 3,160 | model/tests/riscv-tests/isa/rv64ui/subw.S | # See LICENSE for license details.
#*****************************************************************************
# subw.S
#-----------------------------------------------------------------------------
#
# Test subw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#--... |
lizhirui/DreamCore | 1,829 | model/tests/riscv-tests/isa/rv64ui/ori.S | # See LICENSE for license details.
#*****************************************************************************
# ori.S
#-----------------------------------------------------------------------------
#
# Test ori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,302 | model/tests/riscv-tests/isa/rv64ui/lbu.S | # See LICENSE for license details.
#*****************************************************************************
# lbu.S
#-----------------------------------------------------------------------------
#
# Test lbu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
lizhirui/DreamCore | 2,326 | model/tests/riscv-tests/isa/rv64ui/lwu.S | # See LICENSE for license details.
#*****************************************************************************
# lwu.S
#-----------------------------------------------------------------------------
#
# Test lwu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#----... |
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