code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TLB_entry (
//时钟信号
input wire clk,
input wire rst,
//VA-PA通道
//命令通道
input wire read,
input wire write,
input wire execute,
input wire access_rdy, //cache准备好，表示一次访问结束，TLB计数器加1
//地址通道
input wire [63:0] addr_va,
//反馈通道
//output wire load_page_fault,
//output wire store_page_fault,
//output wire ins_page_fault,
//到下一级(Cache)的信号
//output wire read,
//output wire write,
//output wire C, //该页面在分页方案中允许缓存
//TLB_ctrl控制信号
output reg valid, //该TLB entry有效
output reg [11:0] acc_count, //访问计数
output wire PTE_G, //全局有效
output reg [63:0] PTE_out, //该页表的页表项
output reg [63:0] PTE_pa_out, //该页表的物理地址
output reg [43:0] PPN_out, //物理页号输出
input wire [26:0] VPN_in, //该页表对应的VPN
input wire [43:0] PPN_in,
input wire [63:0] PTE_in, //新的页表
input wire [63:0] PTE_pa_in, //新的页表的物理地址
output wire TLB_hit, //命中
input wire TLB_write, //写页表项
input wire TLB_clear, //页表清零（清除valid位）
input wire TLB_D_set //置位脏标志（已经写穿完成）
);
//pte位
//Sv39CT分页方案
parameter V = 0;
parameter R = 1;
parameter W = 2;
parameter X = 3;
parameter U = 4;
parameter G = 5;
parameter A = 6;
parameter D = 7;
parameter C = 63;
parameter T = 62;
reg [26:0] VPN; //页表VPN
//访问计数
always @(posedge clk) begin //页表更新时候，访问计数清零
if (rst | TLB_clear | TLB_write) begin
acc_count <= 12'b0;
end //访问计数达到最高时候，不再增加
else if(acc_count == 12'b111111111111)begin
acc_count <= acc_count;
end //当一次访问完全成功之后，访问计数+1
else if(TLB_hit & access_rdy)begin
acc_count <= acc_count + 12'b1;
end
end
assign TLB_hit = (read|write|execute)&(addr_va[38:12]==VPN)&valid; //该TLB项有效时 VPN相等即命中
//缓存有效
always @(posedge clk) begin
if (rst | TLB_clear) begin
valid <= 1'b0;
end //TLB更新完成后 valid为1
else if(TLB_write)begin
valid <= 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
PTE_out <= 64'b0;
PTE_pa_out <= 64'b0;
PPN_out <= 43'b0;
VPN <= 27'b0;
end else if (TLB_write) begin
PTE_out <= PTE_in;
PTE_pa_out <= PTE_pa_in;
PPN_out <= PPN_in;
VPN <= VPN_in;
end else if (TLB_D_set) begin //Dset时， PTE进行D位更新
PTE_out <= PTE_out | 64'b10000000;
end
end
assign PTE_G = PTE_out[G];
endmodule
| 7.412594 |
module TLB_line_select (
//entry0
input wire entry0_valid, //该TLB entry有效
input wire [11:0] entry0_acc_count, //访问计数
input wire entry0_PTE_G, //全局有效
//entry1
input wire entry1_valid, //该TLB entry有效
input wire [11:0] entry1_acc_count, //访问计数
input wire entry1_PTE_G, //全局有效
//entry2
input wire entry2_valid, //该TLB entry有效
input wire [11:0] entry2_acc_count, //访问计数
input wire entry2_PTE_G, //全局有效
//entry3
input wire entry3_valid, //该TLB entry有效
input wire [11:0] entry3_acc_count, //访问计数
input wire entry3_PTE_G, //全局有效
//选出的替换页
output wire [3:0] entry_select
);
//第一次比较选出的值
wire [1:0] id0;
wire compare_0and1_valid;
wire [11:0] compare_0and1_acc_count;
wire compare_0and1_PTE_G;
wire [1:0] id1;
wire compare_2and3_valid;
wire [11:0] compare_2and3_acc_count;
wire compare_2and3_PTE_G;
//第二次比较
wire [1:0] id_sel;
//0和1进行比较
TLB_select_cell TLB_select_0and1 (
//entry0
.id0 (2'b00),
.entry0_valid (entry0_valid), //该TLB entry有效
.entry0_acc_count(entry0_acc_count), //访问计数
.entry0_PTE_G (entry0_PTE_G), //全局有效
//entry1
.id1 (2'b01),
.entry1_valid (entry1_valid), //该TLB entry有效
.entry1_acc_count(entry1_acc_count), //访问计数
.entry1_PTE_G (entry1_PTE_G), //全局有效
//选出的
.id_out (id0),
.valid_out (compare_0and1_valid), //该TLB entry有效
.acc_count_out (compare_0and1_acc_count), //访问计数
.PTE_G_out (compare_0and1_PTE_G) //全局有效
);
//2和3比较
TLB_select_cell TLB_select_2and3 (
//entry0
.id0 (2'b10),
.entry0_valid (entry2_valid), //该TLB entry有效
.entry0_acc_count(entry2_acc_count), //访问计数
.entry0_PTE_G (entry2_PTE_G), //全局有效
//entry1
.id1 (2'b11),
.entry1_valid (entry3_valid), //该TLB entry有效
.entry1_acc_count(entry3_acc_count), //访问计数
.entry1_PTE_G (entry3_PTE_G), //全局有效
//选出的
.id_out (id1),
.valid_out (compare_2and3_valid), //该TLB entry有效
.acc_count_out (compare_2and3_acc_count), //访问计数
.PTE_G_out (compare_2and3_PTE_G) //全局有效
);
//第二次比较
//使用第一次选出来的值进行比较
TLB_select_cell TLB_select_final (
//entry0
.id0 (id0),
.entry0_valid (compare_0and1_valid), //该TLB entry有效
.entry0_acc_count(compare_0and1_acc_count), //访问计数
.entry0_PTE_G (compare_0and1_PTE_G), //全局有效
//entry1
.id1 (id1),
.entry1_valid (compare_2and3_valid), //该TLB entry有效
.entry1_acc_count(compare_2and3_acc_count), //访问计数
.entry1_PTE_G (compare_2and3_PTE_G), //全局有效
//选出的
.id_out (id_sel),
.valid_out (), //该TLB entry有效
.acc_count_out (), //访问计数
.PTE_G_out () //全局有效
);
assign entry_select[0] = (id_sel == 2'b00);
assign entry_select[1] = (id_sel == 2'b01);
assign entry_select[2] = (id_sel == 2'b10);
assign entry_select[3] = (id_sel == 2'b11);
endmodule
| 7.755038 |
module tlb_lookup (
input [6:0] io_ptw_ptbr_asid,
input [26:0] io_req_bits_vpn,
input [33:0] tags_0,
input [33:0] tags_1,
input [33:0] tags_2,
input [33:0] tags_3,
input [33:0] tags_4,
input [33:0] tags_5,
input [33:0] tags_6,
input [33:0] tags_7,
input [7:0] valid,
input [8:0] dirty_hit_check,
input vm_enabled,
input bad_va,
output [33:0] lookup_tag,
output [8:0] hitsVec,
output [8:0] hits,
output tlb_miss
);
wire [8:0] tlb_hits;
wire tlb_hit;
assign lookup_tag = {io_ptw_ptbr_asid, io_req_bits_vpn[26:0]};
assign hitsVec[0] = (valid[0] & vm_enabled) & (tags_0 == lookup_tag);
assign hitsVec[1] = (valid[1] & vm_enabled) & (tags_1 == lookup_tag);
assign hitsVec[2] = (valid[2] & vm_enabled) & (tags_2 == lookup_tag);
assign hitsVec[3] = (valid[3] & vm_enabled) & (tags_3 == lookup_tag);
assign hitsVec[4] = (valid[4] & vm_enabled) & (tags_4 == lookup_tag);
assign hitsVec[5] = (valid[5] & vm_enabled) & (tags_5 == lookup_tag);
assign hitsVec[6] = (valid[6] & vm_enabled) & (tags_6 == lookup_tag);
assign hitsVec[7] = (valid[7] & vm_enabled) & (tags_7 == lookup_tag);
assign hitsVec[8] = vm_enabled == 1'h0;
assign hits = {
hitsVec[8],
hitsVec[7],
hitsVec[6],
hitsVec[5],
hitsVec[4],
hitsVec[3],
hitsVec[2],
hitsVec[1],
hitsVec[0]
};
assign tlb_hits = ({1'd0, hits[7:0]}) & dirty_hit_check;//dirty_hit_check is for dirty limits judge
assign tlb_hit = tlb_hits != 9'h0;
assign tlb_miss = (vm_enabled & (bad_va == 1'h0)) & (tlb_hit == 1'h0);
endmodule
| 6.552112 |
module tlb_req_trans (
input [1:0] state,
input io_ptw_resp_valid,
input tlb_miss,
input [33:0] r_refill_tag,
input r_req_instruction,
input r_req_store,
input io_ptw_status_pum,
input io_ptw_status_mxr,
input [1:0] io_ptw_status_prv,
output io_req_ready,
output io_ptw_req_valid,
output io_resp_miss,
output [26:0] io_ptw_req_bits_addr,
output io_ptw_req_bits_fetch,
output io_ptw_req_bits_store,
output io_ptw_req_bits_pum,
output io_ptw_req_bits_mxr,
output [1:0] io_ptw_req_bits_prv
);
assign io_req_ready = state == 2'h0;
assign io_ptw_req_valid = state == 2'h1;
assign io_resp_miss = io_ptw_resp_valid | tlb_miss;
assign io_ptw_req_bits_addr = r_refill_tag[26:0];
assign io_ptw_req_bits_fetch = r_req_instruction;
assign io_ptw_req_bits_store = r_req_store;
assign io_ptw_req_bits_prv = io_ptw_status_prv;
assign io_ptw_req_bits_pum = io_ptw_status_pum;
assign io_ptw_req_bits_mxr = io_ptw_status_mxr;
endmodule
| 7.405594 |
module TLB_select_cell (
//entry0
input wire [1:0] id0,
input wire entry0_valid, //该TLB entry有效
input wire [11:0] entry0_acc_count, //访问计数
input wire entry0_PTE_G, //全局有效
//entry1
input wire [1:0] id1,
input wire entry1_valid, //该TLB entry有效
input wire [11:0] entry1_acc_count, //访问计数
input wire entry1_PTE_G, //全局有效
//选出的
output wire [1:0] id_out,
output wire valid_out, //该TLB entry有效
output wire [11:0] acc_count_out, //访问计数
output wire PTE_G_out //全局有效
);
wire sel; //选择
wire both_valid; //二者都是有效项
wire both_global; //二者都是全局表
assign both_valid = entry0_valid & entry1_valid;
assign both_global = entry0_PTE_G & entry1_PTE_G;
assign sel = !both_valid ? (entry0_valid) : //若两个有一个不是有效页面，选出这个非有效页面
!both_global ? (entry0_PTE_G) : //如果有一个不是全局页面，选出这个非全局页面
(entry0_acc_count >=entry1_acc_count) ? 1'b1 : 1'b0; //如果有访问次数较大，选出访问次数小的
assign id_out = sel ? id1 : id0;
assign valid_out = sel ? entry1_valid : entry0_valid;
assign acc_count_out = sel ? entry1_acc_count : entry0_acc_count;
assign PTE_G_out = sel ? entry1_PTE_G : entry0_PTE_G;
endmodule
| 6.707642 |
module tlb_way_testbench;
`include "../sync_clk_gen_template.vh"
`include "armleocpu_defines.vh"
initial begin
#500 $finish;
end
reg [1:0] command;
// invalidate
reg [ENTRIES_W-1:0] invalidate_set_index;
// write
reg [7:0] accesstag_w;
reg [21:0] phys_w;
reg [19:0] virtual_address_w;
// read
reg [19:0] virtual_address;
wire hit;
wire [7:0] accesstag_r;
wire [21:0] phys_r;
localparam ENTRIES_W = 1;
armleocpu_tlb #(ENTRIES_W, 1, 0) tlb (.*);
/*
Test cases:
invalidate all
resolve w/ invalid -> miss
write valid entry
to 0 entry
to 1 entry
to 2 entry
resolve
from 1, 2, 3 entry (8,9, 10,11, 12,13)
write valid entry
to 0 entry with different tag
to 1 entry with different tag
to 2 entry with different tag
resolve
from 0, 1, 2 entry
resolve to other entry -> miss
invalidate
resolve -> miss
write valid entry
to 0 entry
resolve -> hit
resolve to other entry -> miss
*/
initial begin
@(posedge rst_n)
// invalidate all
@(negedge clk)
command <= `TLB_CMD_INVALIDATE;
invalidate_set_index <= 0;
@(posedge clk) @(negedge clk) invalidate_set_index <= 1;
@(posedge clk)
// tlb invalidate done
// tlb write 100 -> F5
@(negedge clk)
command <= `TLB_CMD_WRITE;
accesstag_w = 8'hFF;
phys_w <= 22'hF5;
virtual_address_w <= 20'h100;
@(negedge clk)
// tlb write 101 -> F5
command <= `TLB_CMD_WRITE;
accesstag_w = 8'hFF;
phys_w <= 22'hF5;
virtual_address_w <= 20'h101;
@(negedge clk)
// tlb write 55 -> FE
command <= `TLB_CMD_WRITE;
accesstag_w = 8'hFF;
phys_w <= 22'hFE;
virtual_address_w <= 20'h55;
@(negedge clk)
// tlb write 56 -> F5
command <= `TLB_CMD_WRITE;
accesstag_w = 8'hFF;
phys_w <= 22'hF5;
virtual_address_w <= 20'h56;
@(negedge clk)
// resolve test 55 -> FE
command <= `TLB_CMD_RESOLVE;
virtual_address <= 20'h55;
@(negedge clk) `assert(hit, 1'b1);
`assert(accesstag_r, 8'hFF);
`assert(phys_r, 22'hFE);
// resolve test 56 -> F5
virtual_address <= 20'h56;
@(negedge clk) `assert(hit, 1'b1);
`assert(accesstag_r, 8'hFF);
`assert(phys_r, 22'hF5);
// resolve test 100 -> F5
virtual_address <= 20'h100;
@(negedge clk) `assert(hit, 1'b1);
`assert(accesstag_r, 8'hFF);
`assert(phys_r, 22'hF5);
// resolve test 101 -> F5
virtual_address <= 20'h101;
@(negedge clk) `assert(hit, 1'b1);
`assert(accesstag_r, 8'hFF);
`assert(phys_r, 22'hF5);
// invalidate requests
command <= `TLB_CMD_INVALIDATE;
invalidate_set_index <= 0;
@(posedge clk) @(negedge clk) invalidate_set_index <= 1;
@(posedge clk) @(negedge clk) command <= `TLB_CMD_RESOLVE;
virtual_address <= 20'h55;
// test invalidation
@(negedge clk) `assert(hit, 1'b0);
virtual_address <= 20'h56;
@(negedge clk) `assert(hit, 1'b0);
virtual_address <= 20'h100;
@(negedge clk) `assert(hit, 1'b0);
virtual_address <= 20'h101;
@(negedge clk) `assert(hit, 1'b0);
$finish;
end
endmodule
| 6.70855 |
module TLB_exp_handler (
input s0_found,
input s0_en,
input [1:0] s0_mem_type,
input s0_dmw_hit,
input found_v0,
input found_d0,
input [1:0] s0_plv,
input [1:0] found_plv0,
output [6:0] s0_exception,
input [31:0] s0_vaddr,
input s1_found,
input s1_en,
input [1:0] s1_mem_type,
input s1_dmw_hit,
input found_v1,
input found_d1,
input [1:0] s1_plv,
input [1:0] found_plv1,
output [6:0] s1_exception,
input [31:0] s1_vaddr
);
parameter FETCH = 2'd2;
parameter LOAD = 2'd0;
parameter STORE = 2'd1;
reg [6:0] s0_exception_temp, s1_exception_temp;
/* exeption coping */
always @(*) begin
s0_exception_temp = 0;
if (s0_plv == 2'd3 && s0_vaddr[31]) s0_exception_temp = `EXP_ADEF;
// TLBR
else if (!s0_found) s0_exception_temp = `EXP_TLBR;
// PIF, PIL, PIS
else if (!found_v0) begin
case (s0_mem_type)
FETCH: s0_exception_temp = `EXP_PIF;
LOAD: s0_exception_temp = `EXP_PIL;
STORE: s0_exception_temp = `EXP_PIS;
default: s0_exception_temp = 0;
endcase
end //PPI
else if (s0_plv > found_plv0) s0_exception_temp = `EXP_PPI;
//PME
else if (s0_mem_type == STORE && !found_d0) s0_exception_temp = `EXP_PME;
end
always @(*) begin
s1_exception_temp = 0;
// TLBR
if (s1_plv == 2'd3 && s1_vaddr[31]) s1_exception_temp = `EXP_ADEM;
else if (!s1_found) s1_exception_temp = `EXP_TLBR;
// PIF, PIL, PIS
else if (!found_v1) begin
case (s1_mem_type)
FETCH: s1_exception_temp = `EXP_PIF;
LOAD: s1_exception_temp = `EXP_PIL;
STORE: s1_exception_temp = `EXP_PIS;
default: s1_exception_temp = 0;
endcase
end //PPI
else if (s1_plv > found_plv1) s1_exception_temp = `EXP_PPI;
//PME
else if (s1_mem_type == STORE && !found_d1) s1_exception_temp = `EXP_PME;
end
assign s0_exception = s0_exception_temp & {7{~s0_dmw_hit}} & {7{s0_en}};
assign s1_exception = s1_exception_temp & {7{~s1_dmw_hit}} & {7{s1_en}};
endmodule
| 6.76263 |
module tlc_test;
reg a, b;
reg clock;
reg reset;
wire [2:0] st;
wire RA, RB, YA, YB, GA, GB;
tlc uut (
clock,
reset,
a,
b,
RA,
YA,
GA,
RB,
YB,
GB,
st
);
initial begin
$dumpfile("tlc.vcd");
$dumpvars(0, tlc_test);
clock = 0;
reset = 1;
a = 1;
b = 0;
end
always begin
#5 reset = 0;
#2 a = 0;
#2 b = 1;
#12 b = 0;
#1 a = 1;
#5 a = 0;
#10 reset = 1;
end
always begin
#2 clock <= ~clock;
end
endmodule
| 6.936445 |
module tlc5615b (
input wire clk, //50M
input wire rst_n,
output reg sclk, //1M
output wire cs,
output wire din,
input wire [9:0] datain
);
parameter D_N = 50 - 1;
reg [5:0] div_cnt;
reg [3:0] shift_cnt;
reg shift_en;
reg shift_flag;
reg shift_end;
reg [9:0] shift_buf;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) div_cnt <= 6'd0;
else if (div_cnt == D_N) div_cnt <= 6'd0;
else div_cnt <= div_cnt + 6'd1;
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) shift_flag <= 1'b0;
else if ((div_cnt == D_N) && (shift_end == 1'b0)) shift_flag <= 1'b1;
else shift_flag <= 1'b0;
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) shift_cnt <= 4'b0000;
else if (shift_flag == 1'b1) shift_cnt <= shift_cnt + 4'b0001;
else shift_cnt <= shift_cnt;
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) shift_en <= 1'b0;
else if ((shift_cnt == 4'b1001) && (shift_flag == 1'b1)) shift_en <= 1'b0;
else if (shift_cnt == 4'b0000) shift_en <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) shift_buf <= 10'd0;
else if ((shift_flag == 1'b1) && (shift_en == 1'b1)) shift_buf <= {shift_buf[8:0], 1'b0};
else if ((shift_cnt == 4'b0000) && (shift_en == 1'b1)) shift_buf <= datain;
end
assign din = shift_buf[9];
assign cs = ~shift_en;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) sclk <= 1'b1;
else if ((shift_en == 1'b1) && (div_cnt == 6'd2)) sclk <= 1'b0;
else if ((shift_en == 1'b1) && (div_cnt == 6'd27)) sclk <= 1'b1;
end
endmodule
| 7.361991 |
module TLDA_master_interface (
// clock and reset
input clk,
input resetn,
// avalon master signals
input master_waitrequest,
output reg [31:0] master_address,
output reg master_write,
output reg [15:0] master_writedata,
output [1:0] master_byteenable,
// signals for LDA circuit
input Draw_from_LDA,
input [31:0] Pixel_Address_from_LDA,
input [15:0] Color_from_LDA,
output reg Write_Finish_to_LDA
);
/*****************************************************************************
* Please write your code below *
*****************************************************************************/
assign master_byteenable = 2'b11;
`define IDLE_STATE 0
`define WRITING_STATE 1
`define WAITING_STATE 2
`define DONE_WRITING_STATE 3
reg [1:0] next_state;
wire [1:0] state;
always @(*) begin
case (state)
`IDLE_STATE: begin
master_write = 0;
master_address = 0;
master_writedata = 0;
Write_Finish_to_LDA = 0;
next_state = Draw_from_LDA ? `WRITING_STATE : `IDLE_STATE;
end
`WRITING_STATE: begin
master_write = 1;
master_address = Pixel_Address_from_LDA;
master_writedata = Color_from_LDA;
Write_Finish_to_LDA = 0;
next_state = master_waitrequest ? `WAITING_STATE : `DONE_WRITING_STATE;
end
`WAITING_STATE: begin
master_write = 1;
master_address = Pixel_Address_from_LDA;
master_writedata = Color_from_LDA;
Write_Finish_to_LDA = 0;
if (master_waitrequest) begin
next_state = `WAITING_STATE;
end else begin
next_state = `DONE_WRITING_STATE;
end
end
`DONE_WRITING_STATE: begin
master_write = 0;
master_address = 0;
master_writedata = 0;
Write_Finish_to_LDA = 1;
next_state = Draw_from_LDA ? `WRITING_STATE : `IDLE_STATE;
end
default: begin
master_write = 0;
master_address = 0;
master_writedata = 0;
Write_Finish_to_LDA = 0;
next_state = `IDLE_STATE;
end
endcase
end
dffre #(2) state_ff (
.clk (clk),
.reset (~resetn),
.en (1),
.d (next_state),
.q (state)
);
endmodule
| 8.957208 |
module TLDA_peripheral (
// clock and reset signals
input csi_clockreset_clk,
input csi_clockreset_resetn,
// avalon slave signals
input avs_slave_chipselect,
input [2:0] avs_slave_address,
input avs_slave_read,
input avs_slave_write,
input [31:0] avs_slave_writedata,
output [31:0] avs_slave_readdata,
// avalon master signals
input avm_master_waitrequest,
output [31:0] avm_master_address,
output avm_master_write,
output [15:0] avm_master_writedata,
output [1:0] avm_master_byteenable
);
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
wire Go, Draw, Done, Write_Finish;
wire [8:0] X0, X1, Thickness;
wire [7:0] Y0, Y1;
wire [15:0] Color;
wire [31:0] Pixel_Address, Base_Addr;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// memory-mapped avalon slave interface
TLDA_slave_interface ASI (
// clock and reset
.clk (csi_clockreset_clk),
.resetn(csi_clockreset_resetn),
// avalon slave signals
.slave_chipselect (avs_slave_chipselect),
.slave_address (avs_slave_address),
.slave_read (avs_slave_read),
.slave_write (avs_slave_write),
.slave_writedata (avs_slave_writedata),
.slave_readdata (avs_slave_readdata),
// signals for LDA circuit
.Done_from_LDA (Done),
.Thickness (Thickness),
.Go_to_LDA (Go),
.X0_to_LDA (X0),
.Y0_to_LDA (Y0),
.X1_to_LDA (X1),
.Y1_to_LDA (Y1),
.Color_to_LDA (Color),
.Base_Addr_to_LDA (Base_Addr)
);
//line_drawing_algorithm circuit
TLDA_circuit TLDA_C (
// clock and reset signals
.clk (csi_clockreset_clk),
.resetn(csi_clockreset_resetn),
// signals communicate with ASC
.Go (Go),
.X0 (X0),
.Y0 (Y0),
.X1 (X1),
.Y1 (Y1),
.Thickness(Thickness),
.Done (Done),
// signals communicate with AMC
.Write_Finish (Write_Finish),
.Draw (Draw),
.Pixel_Address(Pixel_Address),
// inout signal, its value is unchanged in this module
.Color (Color),
.Base_Addr(Base_Addr)
);
//avalon master interface
TLDA_master_interface AMI (
// clock and reset
.clk (csi_clockreset_clk),
.resetn(csi_clockreset_resetn),
// avalon master signals
.master_waitrequest(avm_master_waitrequest),
.master_address (avm_master_address),
.master_write (avm_master_write),
.master_writedata (avm_master_writedata),
.master_byteenable (avm_master_byteenable),
// signals for LDA circuit
.Draw_from_LDA (Draw),
.Pixel_Address_from_LDA(Pixel_Address),
.Color_from_LDA (Color),
.Write_Finish_to_LDA (Write_Finish)
);
endmodule
| 8.561742 |
module TLDA_slave_interface (
// clock and reset
input clk,
input resetn,
// avalon slave signals
input slave_chipselect,
input [ 2:0] slave_address,
input slave_read,
input slave_write,
input [31:0] slave_writedata,
output reg [31:0] slave_readdata,
// signals for LDA circuit
input Done_from_LDA,
output Go_to_LDA,
output [ 8:0] X0_to_LDA,
output [ 8:0] X1_to_LDA,
output [ 7:0] Y0_to_LDA,
output [ 7:0] Y1_to_LDA,
output [ 8:0] Thickness,
output [15:0] Color_to_LDA,
output [31:0] Base_Addr_to_LDA
);
// ENABLE THE THICKNESS COMPONENT
/*****************************************************************************
* Please write your code below *
*****************************************************************************/
// Slave addresses
`define STATUS_REGISTER 0
`define GO_REGISTER 1
`define LINE_START 2
`define LINE_END 3
`define LINE_COLOR 4
`define LINE_THICKNESS 5
`define BASE_ADDR 6
reg [8:0] next_X0, next_X1;
reg [7:0] next_Y0, next_Y1;
// Determine what readdata to provide to master
always @(*) begin
if (slave_chipselect) begin
if (slave_write) begin
slave_readdata = 0;
end else if (slave_read) begin
case (slave_address)
`STATUS_REGISTER: begin
slave_readdata = Done_from_LDA;
end
`LINE_START: begin
slave_readdata = {Y0_to_LDA, X0_to_LDA};
end
`LINE_END: begin
slave_readdata = {Y1_to_LDA, X1_to_LDA};
end
`LINE_COLOR: begin
slave_readdata = Color_to_LDA;
end
`LINE_THICKNESS: begin
slave_readdata = Thickness;
end
`BASE_ADDR: begin
slave_readdata = Base_Addr_to_LDA;
end
default: begin
slave_readdata = 0;
end
endcase
end else begin
slave_readdata = 0;
end
end else begin // if not slave_chipselect
slave_readdata = 0;
end
end
wire write_line_start, write_line_end, write_color, write_go, write_thickness, write_base_addr;
assign write_line_start = slave_write & slave_chipselect & (slave_address == `LINE_START);
assign write_line_end = slave_write & slave_chipselect & (slave_address == `LINE_END);
assign write_color = slave_write & slave_chipselect & (slave_address == `LINE_COLOR);
assign write_go = slave_write & slave_chipselect & (slave_address == `GO_REGISTER);
assign write_thickness = slave_write & slave_chipselect & (slave_address == `LINE_THICKNESS);
assign write_base_addr = slave_write & slave_chipselect & (slave_address == `BASE_ADDR);
assign Go_to_LDA = write_go & slave_writedata[0];
dffre #(32) base_addr_ff (
.clk (clk),
.reset(~resetn),
.en (write_base_addr),
.d (slave_writedata),
.q (Base_Addr_to_LDA)
);
falling_dffre #(9) x0_ff (
.clk (clk),
.reset (~resetn),
.en (write_line_start),
.d (slave_writedata[8:0]),
.q (X0_to_LDA)
);
falling_dffre #(8) y0_ff (
.clk (clk),
.reset (~resetn),
.en (write_line_start),
.d (slave_writedata[16:9]),
.q (Y0_to_LDA)
);
falling_dffre #(9) x1_ff (
.clk (clk),
.reset (~resetn),
.en (write_line_end),
.d (slave_writedata[8:0]),
.q (X1_to_LDA)
);
falling_dffre #(9) y1_ff (
.clk (clk),
.reset (~resetn),
.en (write_line_end),
.d (slave_writedata[16:9]),
.q (Y1_to_LDA)
);
falling_dffre #(16) color_ff (
.clk (clk),
.reset (~resetn),
.en (write_color),
.d (slave_writedata[15:0]),
.q (Color_to_LDA)
);
falling_dffre #(9) thickness_ff (
.clk (clk),
.reset (~resetn),
.en (write_thickness),
.d (slave_writedata[8:0]),
.q (Thickness)
);
endmodule
| 7.502948 |
module greenscreen (
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
output wire [2:0] ro,
output wire [2:0] go,
output wire [2:0] bo,
input wire mono
);
reg [2:0] r;
reg [2:0] g;
reg [2:0] b;
assign go = mono ? r + g + b : gi;
assign ro = mono ? {1'b0, g[2:1]} : ri;
assign bo = mono ? {2'b00, g[2]} : bi;
always @* begin // a LUT
case (ri[2:0])
3'd0: r[2:0] = 3'd0;
3'd1: r[2:0] = 3'd0;
3'd2: r[2:0] = 3'd1;
3'd3: r[2:0] = 3'd1;
3'd4: r[2:0] = 3'd1;
3'd5: r[2:0] = 3'd1;
3'd6: r[2:0] = 3'd2;
3'd7: r[2:0] = 3'd2;
default: r[2:0] = 3'd0;
endcase
end
always @* begin // a LUT
case (gi[2:0])
3'd0: g[2:0] = 3'd0;
3'd1: g[2:0] = 3'd1;
3'd2: g[2:0] = 3'd1;
3'd3: g[2:0] = 3'd2;
3'd4: g[2:0] = 3'd2;
3'd5: g[2:0] = 3'd3;
3'd6: g[2:0] = 3'd4;
3'd7: g[2:0] = 3'd4;
default: g[2:0] = 3'd0;
endcase
end
always @* begin // a LUT
case (bi[2:0])
3'd0: b[2:0] = 3'd0;
3'd1: b[2:0] = 3'd0;
3'd2: b[2:0] = 3'd0;
3'd3: b[2:0] = 3'd0;
3'd4: b[2:0] = 3'd0;
3'd5: b[2:0] = 3'd1;
3'd6: b[2:0] = 3'd1;
3'd7: b[2:0] = 3'd1;
default: b[2:0] = 3'd0;
endcase
end
endmodule
| 6.849634 |
module tld_pano_g2 (
input wire SYSCLK,
input wire PANO_BUTTON, // nivel bajo al pulsarlo
output wire LED_RED,
output wire LED_GREEN,
output wire LED_BLUE,
output wire GMII_RST_N // reset de la Marvell a nivel bajo
);
assign GMII_RST_N = ~PANO_BUTTON;
// con el boton pulsado, se desactiva el reset de la Marvell y
// el reloj que "ve" la FPGA pasa de 25 a 125 MHz
// Con el boton soltado, la Marvell est reseteada y su mux
// interno ruta el reloj de 25 MHz en lugar del de 125 MHz
rgb_leds_pwm las_lucecitas (
.clk(SYSCLK), // 25 MHz
.red(LED_RED),
.green(LED_GREEN),
.blue(LED_BLUE)
);
endmodule
| 7.450759 |
module tld_sockit (
input wire clk50mhz, // cristal de 50 MHz
output wire [7:0] r, // Salidas R,G,B
output wire [7:0] g, // de 6 bits
output wire [7:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync, // y vertical
output wire VGA_CLK,
output wire VGA_SYNC_N,
output wire VGA_BLANK_N
);
wire [7:0] r8b, g8b, b8b;
assign r = r8b[7:0]; // como solo tenemos 6 bits por componente de color, asignamos de los 8 bits
assign g = g8b[7:0]; // originales de cada color solo los 6 bits mas significativos
assign b = b8b[7:0]; // (esto en ZX-UNO cambiaria a los 3 bits mas significativos)
wire clkvga;
// cambiar el contenido de este modulo (reloj_cyclone) si hay que cambiar la frecuencia del reloj
// si es que hemos cambiado el ModeLine en videosyncs.v para generar otra frecuencia distinta
reloj_cyclone reloj (
.inclk0(clk50mhz),
.c0(clkvga)
);
fantasma_rebotando el_ejemplo (
.clk(clkvga),
.r(r8b),
.g(g8b),
.b(b8b),
.hsync(hsync),
.vsync(vsync)
);
assign VGA_BLANK_N = hsync && vsync; //VGA DAC additional required pin
assign VGA_SYNC_N = 0; //VGA DAC additional required pin
assign VGA_CLK = clkvga; //has to define a clock to VGA DAC clock otherwise the picture is noisy
endmodule
| 7.971645 |
module tld_unamiga (
input wire clk50mhz, // cristal de 50 MHz
output wire [5:0] r, // Salidas R,G,B
output wire [5:0] g, // de 6 bits
output wire [5:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync // y vertical
);
wire [7:0] r8b, g8b, b8b;
assign r = r8b[7:2]; // como solo tenemos 6 bits por componente de color, asignamos de los 8 bits
assign g = g8b[7:2]; // originales de cada color solo los 6 bits mas significativos
assign b = b8b[7:2]; // (esto en ZX-UNO cambiaria a los 3 bits mas significativos)
wire clkvga;
// cambiar el contenido de este modulo (reloj_cyclone) si hay que cambiar la frecuencia del reloj
// si es que hemos cambiado el ModeLine en videosyncs.v para generar otra frecuencia distinta
reloj_cyclone reloj (
.inclk0(clk50mhz),
.c0(clkvga)
);
fantasma_rebotando el_ejemplo (
.clk(clkvga),
.r(r8b),
.g(g8b),
.b(b8b),
.hsync(hsync),
.vsync(vsync)
);
endmodule
| 7.970068 |
module tld_fantasma_zxdos (
input wire clk50mhz, // cristal de 50 MHz
output wire [5:0] r, // Salidas R,G,B
output wire [5:0] g, // de 6 bits
output wire [5:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync // y vertical
);
wire [7:0] r8b, g8b, b8b;
assign r = r8b[7:2]; // como solo tenemos 6 bits por componente de color, asignamos de los 8 bits
assign g = g8b[7:2]; // originales de cada color slo los 6 bits ms significativos
assign b = b8b[7:2]; // (esto en ZX-UNO cambiara a los 3 bits ms significativos)
wire clkvga;
// cambiar el contenido de este mdulo (relojes.v) si hay que cambiar la frecuencia del reloj
// si es que hemos cambiado el ModeLine en videosyncs.v para generar otra frecuencia distinta
reloj relojvga (
.CLKIN_IN(clk50mhz),
.CLKFX_OUT(clkvga),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
fantasma_rebotando el_ejemplo (
.clk(clkvga),
.r(r8b),
.g(g8b),
.b(b8b),
.hsync(hsync),
.vsync(vsync)
);
endmodule
| 7.222478 |
module tld_fantasma_zxuno (
input wire clk50mhz, // cristal de 50 MHz
output wire [2:0] r, // Salidas R,G,B
output wire [2:0] g, // de 3 bits
output wire [2:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync, // y vertical
output wire stdn, // control del
output wire stdnb // AD724
);
assign stdn = 1'b0;
assign stdnb = 1'b1;
wire [7:0] r8b, g8b, b8b;
assign r = r8b[7:5]; // como solo tenemos 3 bits por componente de color, asignamos de los 8 bits
assign g = g8b[7:5]; // originales de cada color slo los 3 bits ms significativos
assign b = b8b[7:5]; // (esto en ZX-DOS cambiara a los 6 bits ms significativos)
wire clkvga;
// cambiar el contenido de este mdulo (relojes.v) si hay que cambiar la frecuencia del reloj
// si es que hemos cambiado el ModeLine en videosyncs.v para generar otra frecuencia distinta
reloj relojvga (
.CLKIN_IN(clk50mhz),
.CLKFX_OUT(clkvga),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
fantasma_rebotando el_ejemplo (
.clk(clkvga),
.r(r8b),
.g(g8b),
.b(b8b),
.hsync(hsync),
.vsync(vsync)
);
endmodule
| 7.222478 |
module tld_zxuno_v2 (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
output wire audio_out_right,
output wire stdn,
output wire stdnb,
output wire [18:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
output wire flash_cs_n,
output wire flash_clk,
output wire flash_mosi,
input wire flash_miso,
output wire sd_cs_n,
output wire sd_clk,
output wire sd_mosi,
input wire sd_miso,
output wire testled, // nos servir como testigo de uso de la SPI
input wire joyup,
input wire joydown,
input wire joyleft,
input wire joyright,
input wire joyfire
);
wire wssclk, sysclk, clk14, clk7, clk3d5, cpuclk, cpuclkplain;
wire CPUContention;
wire [1:0] turbo_enable;
wire [2:0] pll_frequency_option;
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
clock_generator relojes_maestros ( // Clock in ports
.CLK_IN1 (clk50mhz),
.CPUContention(CPUContention),
.pll_option (pll_frequency_option),
.turbo_enable (turbo_enable),
// Clock out ports
.CLK_OUT1 (sysclk),
.CLK_OUT2 (clk14),
.CLK_OUT3 (clk7),
.CLK_OUT4 (clk3d5),
.cpuclk (cpuclk),
.cpuclkplain (cpuclkplain)
);
wire audio_out;
assign audio_out_left = audio_out;
assign audio_out_right = audio_out;
wire [2:0] ri, gi, bi;
wire hsync_pal, vsync_pal, csync_pal;
wire vga_enable, scanlines_enable;
zxuno la_maquina (
.clk28(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ah, para el resto del circuito
.clk14(clk14),
.clk7(clk7),
.clk3d5(clk3d5),
.cpuclk(cpuclk),
.cpuclkplain(cpuclkplain),
.CPUContention(CPUContention),
.power_on_reset_n(1'b1), // slo para simulacin. Para implementacion, dejar a 1
.r(ri),
.g(gi),
.b(bi),
.hsync(hsync_pal),
.vsync(vsync_pal),
.csync(csync_pal),
.clkps2(clkps2),
.dataps2(dataps2),
.ear(~ear), // negada porque el hardware tiene un transistor inversor
.audio_out(audio_out),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n),
.flash_cs_n(flash_cs_n),
.flash_clk (flash_clk),
.flash_di (flash_mosi),
.flash_do (flash_miso),
.sd_cs_n(sd_cs_n),
.sd_clk (sd_clk),
.sd_mosi(sd_mosi),
.sd_miso(sd_miso),
.joyup(joyup),
.joydown(joydown),
.joyleft(joyleft),
.joyright(joyright),
.joyfire(joyfire),
.mouseclk (mouseclk),
.mousedata(mousedata),
.vga_enable(vga_enable),
.scanlines_enable(scanlines_enable),
.freq_option(pll_frequency_option),
.turbo_enable(turbo_enable)
);
vga_scandoubler #(
.CLKVIDEO(14000)
) salida_vga (
.clkvideo(clk14),
.clkvga(sysclk),
.enable_scandoubling(vga_enable),
.disable_scaneffect(~scanlines_enable),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.csync_ext_n(csync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
assign testled = (!flash_cs_n || !sd_cs_n);
// reg [21:0] monoestable = 22'hFFFFFF;
// always @(posedge sysclk) begin
// if (!flash_cs_n || !sd_cs_n)
// monoestable <= 0;
// else if (monoestable[21] == 1'b0)
// monoestable <= monoestable + 1;
// end
// assign testled = ~monoestable[21];
endmodule
| 7.672643 |
module tld_zxuno_v3 (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
output wire audio_out_right,
output wire stdn,
output wire stdnb,
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
output wire flash_cs_n,
output wire flash_clk,
output wire flash_mosi,
input wire flash_miso,
output wire sd_cs_n,
output wire sd_clk,
output wire sd_mosi,
input wire sd_miso,
output wire testled, // nos servir como testigo de uso de la SPI
input wire joyup,
input wire joydown,
input wire joyleft,
input wire joyright,
input wire joyfire
);
wire wssclk, sysclk, clk14, clk7, clk3d5, cpuclk;
wire CPUContention;
wire [1:0] turbo_enable;
wire [2:0] pll_frequency_option;
assign wssclk = 1'b0; // de momento, sin WSS
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
assign sram_addr[19] = 1'b0;
assign sram_addr[20] = 1'b0;
clock_generator relojes_maestros ( // Clock in ports
.CLK_IN1 (clk50mhz),
.CPUContention(CPUContention),
.pll_option (pll_frequency_option),
.turbo_enable (turbo_enable),
// Clock out ports
.CLK_OUT1 (sysclk),
.CLK_OUT2 (clk14),
.CLK_OUT3 (clk7),
.CLK_OUT4 (clk3d5),
.cpuclk (cpuclk)
);
wire audio_out;
assign audio_out_left = audio_out;
assign audio_out_right = audio_out;
wire [2:0] ri, gi, bi;
wire hsync_pal, vsync_pal;
wire vga_enable, scanlines_enable;
zxuno la_maquina (
.clk(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ah, para el resto del circuito
.wssclk(wssclk), // 5MHz, reloj para el WSS
.clk14(clk14),
.clk7(clk7),
.clk3d5(clk3d5),
.cpuclk(cpuclk),
.CPUContention(CPUContention),
.power_on_reset_n(1'b1), // slo para simulacin. Para implementacion, dejar a 1
.r(ri),
.g(gi),
.b(bi),
.hsync(hsync_pal),
.vsync(vsync_pal),
.clkps2(clkps2),
.dataps2(dataps2),
.ear(~ear), // negada porque el hardware tiene un transistor inversor
.audio_out(audio_out),
.sram_addr(sram_addr[18:0]),
.sram_data(sram_data),
.sram_we_n(sram_we_n),
.flash_cs_n(flash_cs_n),
.flash_clk (flash_clk),
.flash_di (flash_mosi),
.flash_do (flash_miso),
.sd_cs_n(sd_cs_n),
.sd_clk (sd_clk),
.sd_mosi(sd_mosi),
.sd_miso(sd_miso),
.joyup(joyup),
.joydown(joydown),
.joyleft(joyleft),
.joyright(joyright),
.joyfire(joyfire),
.mouseclk (mouseclk),
.mousedata(mousedata),
.vga_enable(vga_enable),
.scanlines_enable(scanlines_enable),
.freq_option(pll_frequency_option),
.turbo_enable(turbo_enable)
);
vga_scandoubler #(
.CLKVIDEO(14000)
) salida_vga (
.clkvideo(clk14),
.clkvga(sysclk),
.enable_scandoubling(vga_enable),
.disable_scaneffect(~scanlines_enable),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
assign testled = (!flash_cs_n || !sd_cs_n);
// reg [21:0] monoestable = 22'hFFFFFF;
// always @(posedge sysclk) begin
// if (!flash_cs_n || !sd_cs_n)
// monoestable <= 0;
// else if (monoestable[21] == 1'b0)
// monoestable <= monoestable + 1;
// end
// assign testled = ~monoestable[21];
endmodule
| 7.855313 |
module tld_zxuno_v4 (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
output wire audio_out_right,
output wire stdn,
output wire stdnb,
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n,
output wire flash_cs_n,
output wire flash_clk,
output wire flash_mosi,
input wire flash_miso,
output wire sd_cs_n,
output wire sd_clk,
output wire sd_mosi,
input wire sd_miso,
output wire testled, // nos servir como testigo de uso de la SPI
input wire joyup,
input wire joydown,
input wire joyleft,
input wire joyright,
input wire joyfire
);
wire wssclk, sysclk, clk14, clk7, clk3d5, cpuclk, cpuclkplain;
wire CPUContention;
wire [1:0] turbo_enable;
wire [2:0] pll_frequency_option;
assign stdn = 1'b0; // fijar norma PAL
assign stdnb = 1'b1; // y conectamos reloj PAL
assign sram_addr[19] = 1'b0;
assign sram_addr[20] = 1'b0;
clock_generator relojes_maestros ( // Clock in ports
.CLK_IN1 (clk50mhz),
.CPUContention(CPUContention),
.pll_option (pll_frequency_option),
.turbo_enable (turbo_enable),
// Clock out ports
.CLK_OUT1 (sysclk),
.CLK_OUT2 (clk14),
.CLK_OUT3 (clk7),
.CLK_OUT4 (clk3d5),
.cpuclk (cpuclk),
.cpuclkplain (cpuclkplain)
);
wire [2:0] ri, gi, bi;
wire hsync_pal, vsync_pal, csync_pal;
wire vga_enable, scanlines_enable;
zxuno la_maquina (
.clk28(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ah, para el resto del circuito
.clk14(clk14),
.clk7(clk7),
.clk3d5(clk3d5),
.cpuclk(cpuclk),
.cpuclkplain(cpuclkplain),
.CPUContention(CPUContention),
.power_on_reset_n(1'b1), // slo para simulacin. Para implementacion, dejar a 1
.r(ri),
.g(gi),
.b(bi),
.hsync(hsync_pal),
.vsync(vsync_pal),
.csync(csync_pal),
.clkps2(clkps2),
.dataps2(dataps2),
.ear(~ear), // negada porque el hardware tiene un transistor inversor
.audio_out_left(audio_out_left),
.audio_out_right(audio_out_right),
.sram_addr(sram_addr[18:0]),
.sram_data(sram_data),
.sram_we_n(sram_we_n),
.flash_cs_n(flash_cs_n),
.flash_clk (flash_clk),
.flash_di (flash_mosi),
.flash_do (flash_miso),
.sd_cs_n(sd_cs_n),
.sd_clk (sd_clk),
.sd_mosi(sd_mosi),
.sd_miso(sd_miso),
.joyup(joyup),
.joydown(joydown),
.joyleft(joyleft),
.joyright(joyright),
.joyfire(joyfire),
.mouseclk (mouseclk),
.mousedata(mousedata),
.vga_enable(vga_enable),
.scanlines_enable(scanlines_enable),
.freq_option(pll_frequency_option),
.turbo_enable(turbo_enable)
);
vga_scandoubler #(
.CLKVIDEO(14000)
) salida_vga (
.clkvideo(clk14),
.clkvga(sysclk),
.enable_scandoubling(vga_enable),
.disable_scaneffect(~scanlines_enable),
.ri(ri),
.gi(gi),
.bi(bi),
.hsync_ext_n(hsync_pal),
.vsync_ext_n(vsync_pal),
.csync_ext_n(csync_pal),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync)
);
assign testled = (!flash_cs_n || !sd_cs_n);
// reg [21:0] monoestable = 22'hFFFFFF;
// always @(posedge sysclk) begin
// if (!flash_cs_n || !sd_cs_n)
// monoestable <= 0;
// else if (monoestable[21] == 1'b0)
// monoestable <= monoestable + 1;
// end
// assign testled = ~monoestable[21];
endmodule
| 7.538829 |
module TLI4970 (
input clk,
input reset,
input read,
input address,
output signed [31:0] readdata,
output waitrequest,
input spi_miso,
output [NUMBER_OF_SENSORS-1:0] spi_cs,
output spi_clk
);
assign readdata = current[address];
parameter NUMBER_OF_SENSORS = 2;
parameter CLOCK_FREQ = 50_000_000;
parameter CLOCK_DIVIDER = 13;
parameter UPDATE_FREQ = 100;
reg clk_slow;
reg [7:0] counter;
always @(posedge clk) begin : CLK_GENERATOR
counter <= counter + 1;
if (counter > CLOCK_DIVIDER) begin
clk_slow <= !clk_slow;
counter <= 0;
end
end
reg clk_out;
reg slave_select;
assign spi_clk = (slave_select ? 1 : clk_slow) & clk_out;
genvar j;
generate
for (j = 0; j < NUMBER_OF_SENSORS; j = j + 1) begin : connect_slave_selects
assign spi_cs[j] = (current_sensor == j ? slave_select : 1);
end
endgenerate
reg [7:0] bit_counter;
reg [15:0] data;
reg [15:0] delay_counter;
reg [7:0] state;
reg [7:0] current_sensor;
reg signed [15:0] current[NUMBER_OF_SENSORS-1:0];
wire signed [12:0] current_raw;
assign current_raw = data[12:0];
localparam IDLE = 0, SLAVE_SELECT = 1, CLOCK_DATA = 2, STOP = 3;
always @(negedge clk_slow) begin : TLI4970_READOUT_LOGIC
if (delay_counter > (CLOCK_FREQ / CLOCK_DIVIDER / UPDATE_FREQ / NUMBER_OF_SENSORS)) begin
state <= SLAVE_SELECT;
delay_counter <= 0;
end else begin
delay_counter <= delay_counter + 1;
end
case (state)
IDLE: begin
slave_select <= 1;
end
SLAVE_SELECT: begin
if (current_sensor < (NUMBER_OF_SENSORS - 1)) begin
current_sensor <= current_sensor + 1;
end else begin
current_sensor <= 0;
end
slave_select <= 0;
clk_out <= 1;
state <= CLOCK_DATA;
bit_counter <= 15;
end
CLOCK_DATA: begin
data[bit_counter] <= spi_miso;
bit_counter <= bit_counter - 1;
if (bit_counter == 0) begin
state <= STOP;
clk_out <= 0;
end
end
STOP: begin
if (data[15] == 0) begin
current[current_sensor] <= current_raw - 16'd4096;
end
state <= IDLE;
end
endcase
end
endmodule
| 7.419307 |
module: uart_tlm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tlm_tb;
// Inputs
reg fpgaClk_i;
reg clk_fb;
// Outputs
wire [2:0] chan_io;
wire clk_en;
wire sd_clk;
wire cs;
wire we;
wire ras;
wire cas;
wire dml;
wire dmh;
wire [1:0] bs;
wire [12:0] sdAddr_o;
//inouts
wire [15:0] sdData_io;
// Instantiate the Unit Under Test (UUT)
uart_tlm uut (
.fpgaClk_i(fpgaClk_i),
.chan_io(chan_io),
.clk_en(clk_en),
.sd_clk(sd_clk),
.clk_fb(clk_fb),
.cs(cs),
.we(we),
.ras(ras),
.cas(cas),
.dml(dml),
.dmh(dmh),
.bs(bs),
.sdAddr_o(sdAddr_o),
.sdData_io(sdData_io)
);
mt48lc16m16a2 instance_name (
.Dq(sdData_io),
.Addr(sdAddr_o),
.Ba(bs),
.Clk(fpgaClk_i),
.Cke(clk_en),
.Cs_n(cs),
.Ras_n(ras),
.Cas_n(cas),
.We_n(we),
.Dqm({dml, dmh})
);
initial begin
// Initialize Inputs
fpgaClk_i = 0;
clk_fb = 0;
// Add stimulus here
end
always #41 fpgaClk_i = ~fpgaClk_i;
endmodule
| 7.112422 |
module tlp_s_axi_cntrl ( /*AUTOARG*/
// Outputs
AWVALID,
AWADDR,
AWPROT,
AWREGION,
AWLEN,
AWSIZE,
AWBURST,
AWLOCK,
AWCACHE,
AWQOS,
AWID,
AWUSER,
WVALID,
WDATA,
WSTRB,
WLAST,
WUSER,
BREADY,
ARVALID,
ARADDR,
ARPROT,
ARREGION,
ARLEN,
ARSIZE,
ARBURST,
ARLOCK,
ARCACHE,
ARQOS,
ARID,
ARUSER,
RREADY,
// Inputs
ACLK,
ARESETn,
AWREADY,
WREADY,
BVALID,
BRESP,
BID,
BUSER,
ARREADY,
RVALID,
RDATA,
RRESP,
RLAST,
RID,
RUSER
);
parameter AXI4_ADDRESS_WIDTH = 64;
parameter AXI4_RDATA_WIDTH = 128;
parameter AXI4_WDATA_WIDTH = 128;
parameter AXI4_ID_WIDTH = 3;
input ACLK;
input ARESETn;
output M_AWVALID;
output [((AXI4_ADDRESS_WIDTH) - 1):0] M_AWADDR;
output [2:0] M_AWPROT;
output [3:0] M_AWREGION;
output [7:0] M_AWLEN;
output [2:0] M_AWSIZE;
output [1:0] M_AWBURST;
output M_AWLOCK;
output [3:0] M_AWCACHE;
output [3:0] M_AWQOS;
output [((AXI4_ID_WIDTH) - 1):0] M_AWID;
output [((AXI4_USER_WIDTH) - 1):0] M_AWUSER;
input M_AWREADY;
output M_WVALID;
output [((AXI4_WDATA_WIDTH) - 1):0] M_WDATA;
output [(((AXI4_WDATA_WIDTH / 8)) - 1):0] M_WSTRB;
output M_WLAST;
output [((AXI4_USER_WIDTH) - 1):0] M_WUSER;
input M_WREADY;
input M_BVALID;
input [1:0] M_BRESP;
input [((AXI4_ID_WIDTH) - 1):0] M_BID;
input [((AXI4_USER_WIDTH) - 1):0] M_BUSER;
output M_BREADY;
output M_ARVALID;
output [((AXI4_ADDRESS_WIDTH) - 1):0] M_ARADDR;
output [2:0] M_ARPROT;
output [3:0] M_ARREGION;
output [7:0] M_ARLEN;
output [2:0] M_ARSIZE;
output [1:0] M_ARBURST;
output M_ARLOCK;
output [3:0] M_ARCACHE;
output [3:0] M_ARQOS;
output [((AXI4_ID_WIDTH) - 1):0] M_ARID;
output [((AXI4_USER_WIDTH) - 1):0] M_ARUSER;
input M_ARREADY;
input M_RVALID;
input [((AXI4_RDATA_WIDTH) - 1):0] M_RDATA;
input [1:0] M_RRESP;
input M_RLAST;
input [((AXI4_ID_WIDTH) - 1):0] M_RID;
input [((AXI4_USER_WIDTH) - 1):0] M_RUSER;
output M_RREADY;
endmodule
| 7.080645 |
module tlp_tx #(
DOUBLE_WORD = 32, // 双字，32位
HEADER_SIZE = 4 * DOUBLE_WORD, // Header4个双字，取决于host内存空间是否大于4GB
TLP_DATA_WIDTH = 8 * DOUBLE_WORD // 数据荷载8个双字
) (
input clk,
input rst_n,
input in_ready,
output reg [TLP_DATA_WIDTH-1:0] in_data,
output reg [ HEADER_SIZE-1:0] in_hdr,
output reg in_sop,
output reg in_eop,
output reg in_valid
);
reg [TLP_DATA_WIDTH-1:0] in_data_nxt;
reg [ HEADER_SIZE-1:0] in_hdr_nxt;
reg in_sop_nxt;
reg in_eop_nxt;
reg in_valid_nxt;
reg [9:0] cnt, cnt_nxt;
wire [9:0] cnt_minus1;
assign cnt_minus1 = cnt - 1'b1;
reg finish, finish_nxt;
reg [2:0] r_w_cnt, r_w_cnt_nxt;
parameter [9:0] TLP_NUM = 16; // 正常传输
// parameter [9:0] TLP_NUM = 1; // 单次传输
always @* begin
in_hdr_nxt = in_hdr;
in_hdr_nxt[127:125] = 3'b011; // fmt wr TLP
// in_hdr_nxt[126] = r_w_cnt[2] ? 1 : 0; // 随机读写
r_w_cnt_nxt = r_w_cnt;
in_hdr_nxt[105:96] = TLP_NUM << 3; // length
in_data_nxt = in_data;
in_valid_nxt = in_valid;
cnt_nxt = cnt;
in_sop_nxt = in_sop;
in_eop_nxt = in_eop;
finish_nxt = finish;
if (cnt == TLP_NUM) begin
in_sop_nxt = 1'b1;
end
if (cnt == 1) begin
in_eop_nxt = 1'b1;
end
if (!in_valid) begin
in_valid_nxt = 1'b1;
in_data_nxt = in_data + 1'b1;
r_w_cnt_nxt = r_w_cnt - 1'b1;
end
if (in_valid & in_ready) begin
cnt_nxt = cnt_minus1;
in_valid_nxt = 0;
in_sop_nxt = 0;
in_eop_nxt = 0;
if (in_eop) begin
finish_nxt = 0;
end
end
end
always @(posedge clk) begin
if (!rst_n) begin
in_hdr <= 0; // 对齐地址测试
// in_hdr <= {0,3'b100}; // 非对齐地址测试
in_data <= 0;
in_sop <= 0;
in_eop <= 0;
in_valid <= 0;
cnt <= TLP_NUM;
finish <= 1'b1;
r_w_cnt <= 0;
end else begin
in_hdr <= in_hdr_nxt;
in_data <= in_data_nxt & {TLP_DATA_WIDTH{finish}};
in_sop <= in_sop_nxt;
in_eop <= in_eop_nxt;
in_valid <= in_valid_nxt & finish;
cnt <= cnt_nxt;
r_w_cnt <= r_w_cnt_nxt;
finish <= finish_nxt;
end
end
endmodule
| 7.102726 |
module tlu_incr64 (
in,
out
);
input [63:0] in;
output [63:0] out; // result of increment
assign out = in + 64'h01;
endmodule
| 7.099215 |
module TLV320 (
input clock,
output reg nCS,
output reg MOSI,
output reg SCLK,
output CMODE
);
reg [ 2:0] load;
reg [ 3:0] TLV;
reg [15:0] TLV_data;
reg [ 3:0] bit_cnt;
// Set up TLV320 data to send
always @* begin
case (load)
//3'd0: TLV_data = 16'h8889; // simulation test case
3'd0: TLV_data = 16'h1E00; // data to load into TLV320
3'd1: TLV_data = 16'h1201;
3'd2: TLV_data = 16'h0814; // D/A on
3'd3: TLV_data = 16'h0C00;
3'd4: TLV_data = 16'h0E02;
3'd5: TLV_data = 16'h1000;
3'd6: TLV_data = 16'h0A00;
default: TLV_data = 0;
endcase
end
// State machine to send data to TLV320 via SPI interface
assign CMODE = 1'b1; // Set to 1 for SPI mode
reg [23:0] tlv_timeout;
always @ (posedge clock) // use 12.288MHz BCLK for SPI
begin
if (tlv_timeout != (200 * 12288)) // 200mS @BCLK = 12.288Mhz
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0: begin
nCS <= 1'b1; // set TLV320 CS high
bit_cnt <= 4'd15; // set starting bit count to 15
if (tlv_timeout == (200 * 12288)) // wait for 200mS timeout
TLV <= 4'd1;
else TLV <= 4'd0;
end
4'd1: begin
nCS <= 1'b0; // start data transfer with nCS low
MOSI <= TLV_data[bit_cnt]; // set data up
TLV <= 4'd2;
end
4'd2: begin
SCLK <= 1'b1; // clock data into TLV320
TLV <= 4'd3;
end
4'd3: begin
SCLK <= 1'b0; // reset clock
TLV <= 4'd4;
end
4'd4: begin
if (bit_cnt == 0) // word transfer is complete, check for any more
TLV <= 4'd5;
else begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1; // go round again
end
end
4'd5: begin
if (load == 6) begin // stop when all data sent
TLV <= 4'd5; // hang out here forever
nCS <= 1'b1; // set CS high
end else begin // else get next data
TLV <= 4'd0;
load <= load + 3'b1; // select next data word to send
end
end
default: TLV <= 4'd0;
endcase
end
endmodule
| 8.13493 |
module TLV320_SPI (
clk,
CMODE,
nCS,
MOSI,
SSCK,
boost,
line,
line_in_gain
);
input wire clk;
output wire CMODE;
output reg nCS;
output reg MOSI;
output reg SSCK;
input wire boost;
input wire line; // set when using line rather than mic input
input wire [4:0] line_in_gain;
reg [ 3:0] load;
reg [ 3:0] TLV;
reg [15:0] TLV_data;
reg [15:0] latch_TLV_data;
reg [ 3:0] bit_cnt;
reg prev_boost;
reg prev_line;
reg [ 4:0] prev_line_in_gain;
// Set up TLV320 data to send
always @* begin
case (load)
4'd0: TLV_data = 16'h1E00; // data to load into TLV320
4'd1: TLV_data = 16'h1201;
4'd2: TLV_data = line ? 16'h0810 : (16'h0814 + boost); // D/A on
4'd3: TLV_data = 16'h0C00;
4'd4: TLV_data = 16'h0E02;
4'd5: TLV_data = 16'h1000;
4'd6: TLV_data = 16'h0A00;
4'd7: TLV_data = {11'b0, line_in_gain}; // set line in gain
//4'd8: TLV_data = 16'h0000;
default: TLV_data = 0;
endcase
end
// State machine to send data to TLV320 via SPI interface
assign CMODE = 1'b1; // Set to 1 for SPI mode
reg [23:0] tlv_timeout;
always @(posedge clk) begin
if (tlv_timeout != (200 * 12288)) // 200mS @CMCLK= 12.288Mhz
tlv_timeout <= tlv_timeout + 1'd1;
case (TLV)
4'd0: begin
nCS <= 1'b1; // set TLV320 CS high
bit_cnt <= 4'd15; // set starting bit count to 15
if (tlv_timeout == (200 * 12288)) begin // wait for 200mS timeout
latch_TLV_data <= TLV_data; // save the current settings
TLV <= 4'd1;
end else TLV <= 4'd0;
end
4'd1: begin
nCS <= 1'b0; // start data transfer with nCS low
MOSI <= latch_TLV_data[bit_cnt]; // set data up
TLV <= 4'd2;
end
4'd2: begin
SSCK <= 1'b1; // clock data into TLV320
TLV <= 4'd3;
end
4'd3: begin
SSCK <= 1'b0; // reset clock
TLV <= 4'd4;
end
4'd4: begin
if (bit_cnt == 0) // word transfer is complete, check for any more
TLV <= 4'd5;
else begin
bit_cnt <= bit_cnt - 1'b1;
TLV <= 4'd1; // go round again
end
begin
prev_boost <= boost; // save the current boost setting
prev_line <= line; // save the current line in setting
prev_line_in_gain <= line_in_gain; // save the current line-in gain setting
end
end
4'd5: begin
if (load == 7) begin // stop when all data sent, and wait for boost to change
nCS <= 1'b1; // set CS high
if (boost != prev_boost || line != prev_line || line_in_gain != prev_line_in_gain) begin // has boost or line in or line-in gain changed?
load <= 0;
TLV <= 4'd0;
end else TLV <= 4'd5; // hang out here forever
end else begin // else get next data
TLV <= 4'd0;
load <= load + 3'b1; // select next data word to send
end
end
default: TLV <= 4'd0;
endcase
end
endmodule
| 7.81941 |
module top (
input clk,
output tlvds_p,
output tlvds_n,
input key_i
);
wire key = key_i ^ `INV_BTN;
reg [24:0] ctr_q;
wire [24:0] ctr_d;
wire i_tick;
// Sequential code (flip-flop)
always @(posedge clk) ctr_q <= ctr_d;
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign i_tick = |ctr_q[24:23];
TLVDS_TBUF diff_buf (
.OEN(~key),
.O (tlvds_p),
.OB (tlvds_n),
.I (i_tick)
);
endmodule
| 7.233807 |
module tl_cntr_w_left (
clk,
reset_n,
Ta,
Tb,
Tal,
Tbl,
La,
Lb
);
input clk, reset_n, Ta, Tb, Tal, Tbl; // 6 inputs
output [1:0] La, Lb; // 2bits 2 outputs
wire [2:0] next_state; // 3bits wire
wire [2:0] state; // 3bits wire
_register3_r U0_register3_r (
.clk(clk),
.reset_n(reset_n),
.d(next_state),
.q(state)
); // instance by using _register3_r, ns_logic and o_logic
ns_logic U1_ns_logic (
.Ta(Ta),
.Tb(Tb),
.Tal(Tal),
.Tbl(Tbl),
.state(state),
.nextstate(next_state)
);
o_logic U2_o_logic (
.state(state),
.La(La),
.Lb(Lb)
);
endmodule
| 6.967823 |
module tl_cntr_w_left_be (
clk,
reset_n,
Ta,
Tb,
Tal,
Tbl,
La,
Lb
);
input clk, reset_n, Ta, Tb, Tal, Tbl; // 6 inputs
output [1:0] La, Lb; // 2 bits 2 output
wire [2:0] next_state; // 3bits wire
wire [2:0] state; // 3bits wire
_register3_r U0_register3_r (
.clk(clk),
.reset_n(reset_n),
.d(next_state),
.q(state)
); //instance by using _register3_r,ns_logic and o_logic
ns_logic U1_ns_logic (
.Ta(Ta),
.Tb(Tb),
.Tal(Tal),
.Tbl(Tbl),
.state(state),
.nextstate(next_state)
);
o_logic U2_o_logic (
.state(state),
.La(La),
.Lb(Lb)
);
endmodule
| 6.967823 |
module TL_Math2 (
clock,
reset,
start,
addIn,
subIn,
L_subIn,
T_op,
PIT_MIN,
PIT_MAX,
addOutA,
addOutB,
subOutA,
subOutB,
L_subOutA,
L_subOutB,
T0_min,
T0_max,
done
);
`include "paramList.v"
//inputs
input clock;
input reset;
input start;
input [15:0] addIn;
input [15:0] subIn;
input [31:0] L_subIn;
input [15:0] T_op;
input [15:0] PIT_MIN;
input [15:0] PIT_MAX;
//outputs
output reg [15:0] addOutA;
output reg [15:0] addOutB;
output reg [15:0] subOutA;
output reg [15:0] subOutB;
output reg [31:0] L_subOutA;
output reg [31:0] L_subOutB;
output [15:0] T0_min;
output [15:0] T0_max;
output reg done;
//wires/regs
reg [1:0] currentstate, nextstate;
reg [15:0] nextT0_min, nextT0_max;
reg [15:0] T0_min, T0_max;
reg LDT0_min, LDT0_max;
reg resetT0_min, resetT0_max;
//parameters
parameter INIT = 3'd0;
parameter S1 = 3'd1;
parameter S2 = 3'd2;
parameter DONE = 3'd3;
//flip flops
always @(posedge clock) begin
if (reset) currentstate <= INIT;
else currentstate <= nextstate;
end
always @(posedge clock) begin
if (reset) T0_min <= 0;
else if (resetT0_min) T0_min <= 0;
else if (LDT0_min) T0_min <= nextT0_min;
end
always @(posedge clock) begin
if (reset) T0_max <= 0;
else if (resetT0_max) T0_max <= 0;
else if (LDT0_max) T0_max <= nextT0_max;
end
always @(*) begin
addOutA = 0;
addOutB = 0;
subOutA = 0;
subOutB = 0;
L_subOutA = 0;
L_subOutB = 0;
done = 0;
nextstate = currentstate;
nextT0_min = T0_min;
nextT0_max = T0_max;
LDT0_min = 0;
LDT0_max = 0;
resetT0_min = 0;
resetT0_max = 0;
case (currentstate)
INIT: begin
resetT0_min = 1;
resetT0_max = 1;
if (start == 1) nextstate = S1;
else nextstate = INIT;
end
//T0_min = sub(T_op, 3);
// if (sub(T0_min,PIT_MIN)<0) {
// T0_min = PIT_MIN;
// }
S1: begin
subOutA = T_op;
subOutB = 16'd3;
if (subIn[15] == 1) L_subOutA = {16'hffff, subIn};
else L_subOutA = {16'h0000, subIn};
L_subOutB = PIT_MIN;
if (L_subIn[31] == 1) nextT0_min = PIT_MIN;
else nextT0_min = subIn;
LDT0_min = 1;
nextstate = S2;
end
// T0_max = add(T0_min, 6);
// if (sub(T0_max ,PIT_MAX)>0)
// {
// T0_max = PIT_MAX;
// T0_min = sub(T0_max, 6);
// }
S2: begin
addOutA = T0_min;
addOutB = 16'd6;
if (addIn[15] == 1) L_subOutA = {16'hffff, addIn};
else L_subOutA = {16'h0000, addIn};
L_subOutB = PIT_MAX;
if ((L_subIn[31] == 0) && (L_subIn != 0)) begin
nextT0_max = PIT_MAX;
subOutA = PIT_MAX;
subOutB = 16'd6;
nextT0_min = subIn;
LDT0_min = 1;
end else nextT0_max = addIn;
LDT0_max = 1;
nextstate = DONE;
end
DONE: begin
done = 1;
nextstate = INIT;
end
default: nextstate = INIT;
endcase
end
endmodule
| 6.871475 |
module LFSR (
out,
clk,
rst
);
output reg [4:0] out;
input clk, rst;
wire feedback;
assign feedback = ~(out[2] ^ out[4]);
always @(posedge clk, posedge rst) begin
if (rst) out = 5'b0;
else out = {out[3:0], feedback};
end
endmodule
| 7.001839 |
module tm1637_tb;
reg clk, rst;
reg [7:0] data_byte;
reg data_latch, data_stop_bit;
wire busy, scl_en, scl_out, sda_en, sda_out;
reg sda_in;
tm1637 u_tm1637 (
.clk (clk),
.rst (rst),
.data_latch (data_latch),
.data_byte (data_byte),
.data_stop_bit(data_stop_bit),
.busy (busy),
.scl_en (scl_en),
.scl_out (scl_out),
.sda_en (sda_en),
.sda_out (sda_out),
.sda_in (sda_in)
);
initial begin
$dumpfile("src/tm1637/tm1637_tb.vcd");
$dumpvars;
clk = 0;
rst = 0;
data_byte = 0;
data_latch = 0;
data_stop_bit = 0;
sda_in = 0;
#10000
// trigger reset
rst = 1;
#50 rst = 0;
#10000
// send data command
data_byte = 8'b01000000;
data_stop_bit = 1;
data_latch = 1;
#10 data_latch = 0;
#80000
// send location command
data_byte = 8'b11000000;
data_stop_bit = 0;
data_latch = 1;
#10 data_latch = 0;
#80000
// send '1'
data_byte = 8'b00000110;
data_latch = 1;
#10 data_latch = 0;
#80000
// send '2'
data_byte = 8'b01011011;
data_latch = 1;
#10 data_latch = 0;
#80000
// send '3'
data_byte = 8'b01001111;
data_latch = 1;
#10 data_latch = 0;
#80000
// send '4'
data_byte = 8'b01100110;
data_stop_bit = 1;
data_latch = 1;
#10 data_latch = 0;
#80000
// send display command
data_byte = 8'b10001111;
data_stop_bit = 1;
data_latch = 1;
#10 data_latch = 0;
#300000 $finish;
end
always @(posedge clk) begin
;
end
always #5 clk = !clk;
endmodule
| 7.15832 |
module TM1638 (
reset,
clock,
data_in,
data_io,
strobe
);
input reset;
input clock;
input [7:0] data_in;
tri0 reset;
tri0 [7:0] data_in;
output data_io;
output strobe;
reg data_io;
reg reg_data_io;
reg strobe;
reg [8:0] fstate;
reg [8:0] reg_fstate;
parameter state1=0,state2=1,state3=2,state4=3,state5=4,state6=5,state7=6,state8=7,state9=8;
initial begin
reg_data_io <= 1'b0;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
fstate <= state1;
end else begin
fstate <= reg_fstate;
end
end
always @(fstate or data_in or reg_data_io) begin
reg_data_io <= 1'b0;
strobe <= 1'b0;
data_io <= 1'b0;
case (fstate)
state1: begin
reg_fstate <= state2;
strobe <= 1'b0;
reg_data_io <= data_in[0];
end
state2: begin
reg_fstate <= state3;
reg_data_io <= data_in[1];
end
state3: begin
reg_fstate <= state4;
reg_data_io <= data_in[2];
end
state4: begin
reg_fstate <= state5;
reg_data_io <= data_in[3];
end
state5: begin
reg_fstate <= state6;
reg_data_io <= data_in[4];
end
state6: begin
reg_fstate <= state7;
reg_data_io <= data_in[5];
end
state7: begin
reg_fstate <= state8;
reg_data_io <= data_in[6];
end
state8: begin
reg_fstate <= state9;
strobe <= 1'b1;
reg_data_io <= data_in[7];
end
state9: begin
reg_fstate <= state9;
reg_data_io <= 1'b0;
end
default: begin
reg_data_io <= 1'bx;
strobe <= 1'bx;
$display("Reach undefined state");
end
endcase
data_io <= reg_data_io;
end
endmodule
| 6.742421 |
module tm1638BtmDisp (
input wire CLK_IN,
input wire RST_IN,
output wire TM1638_STB,
output wire TM1638_CLK,
inout wire TM1638_DIO
);
parameter CLOCK_SLOW = 6; // Work in reel: drive1=[2-15] openDrain=[6-15]
parameter WRITE_SLOW = 0; // Nice with 20 for humain reading
parameter READ_SLOW = 0; // TODO
reg [CLOCK_SLOW:0] clkSlowCpt;
reg [WRITE_SLOW:0] writeSlowCpt;
reg [READ_SLOW:0] readSlowCpt;
reg [23:0] data;
reg [2:0] hexaIndex;
wire tm1638Ready;
wire [3:0] hexTo7SegDataIn;
wire [7:0] tm1638DataIn;
wire [7:0] tm1638DataOut;
wire tm1638ClkIn;
reg [3:0] tm1638Addr;
reg tm1638W;
reg tm1638R;
assign tm1638ClkIn = clkSlowCpt[CLOCK_SLOW];
always @(posedge CLK_IN) begin
if (RST_IN == 0) begin
clkSlowCpt <= 0;
writeSlowCpt <= 1;
readSlowCpt <= 1;
data <= 0;
hexaIndex <= 0;
tm1638W <= 1'b0;
tm1638R <= 1'b0;
end else begin
clkSlowCpt <= clkSlowCpt + 1'b1;
// If ready
if (tm1638Ready == 1) begin
// If time to read
if (readSlowCpt == 0) begin
// Ask to read
tm1638R <= 1'b1;
end // If time to write
else if (writeSlowCpt == 0) begin
// Ask to write
tm1638W <= 1'b1;
// Prepare to write
tm1638Addr <= {hexaIndex, 1'b0};
end else begin
// Wait time to write
writeSlowCpt <= writeSlowCpt + 1'b1;
// Wait time to read
readSlowCpt <= readSlowCpt + 1'b1;
end
end // If write
else if (tm1638W == 1'b1) begin
// Stop asking to write
tm1638W <= 1'b0;
// Prepare next data to write
hexaIndex <= hexaIndex + 1'b1;
if (hexaIndex == 3'b111) data <= data + 1'b1;
// Reset write slow compter
writeSlowCpt <= 1;
end // If read
else if (tm1638R == 1'b1) begin
// Stop asking to read
tm1638R <= 1'b0;
// Reset read slow compter
readSlowCpt <= 1;
end
end
end
function [3:0] computeHexTo7SegDataIn(input [2:0] index, input [31:0] data);
case (index)
3'h0: computeHexTo7SegDataIn = data[3:0];
3'h1: computeHexTo7SegDataIn = data[7:4];
3'h2: computeHexTo7SegDataIn = data[11:8];
3'h3: computeHexTo7SegDataIn = data[15:12];
3'h4: computeHexTo7SegDataIn = data[19:16];
3'h5: computeHexTo7SegDataIn = data[23:20];
3'h6: computeHexTo7SegDataIn = data[27:24];
3'h7: computeHexTo7SegDataIn = data[31:28];
endcase
endfunction
assign hexTo7SegDataIn = computeHexTo7SegDataIn(hexaIndex, {tm1638DataOut, data});
hexTo7Seg hexTo7Seg_1 (
.HEX(hexTo7SegDataIn),
.DOT(1'b0),
.SEG(tm1638DataIn)
);
tm1638 tm1638_1 (
.RST_IN(RST_IN),
.DATA_IN(tm1638DataIn),
.DATA_OUT(tm1638DataOut),
.ADDR(tm1638Addr),
.WRITE(tm1638W),
.READ(tm1638R),
.CLK_IN(tm1638ClkIn),
.STB(TM1638_STB),
.DIO(TM1638_DIO),
.CLK_OUT(TM1638_CLK),
.READY(tm1638Ready)
);
endmodule
| 6.686042 |
module tm1638BtmDisp_tb();
reg CLK_IN;
reg RST_IN;
wire TM1638_STB;
wire TM1638_CLK;
tri1 TM1638_DIO;
reg [7:0] byte;
reg dio;
reg [2:0] hexaIndex;
glbl glbl();
defparam uut.CLOCK_SLOW = 0;
defparam uut.WRITE_SLOW = 0;
defparam uut.READ_SLOW = 0;
tm1638BtmDisp uut(
.CLK_IN(CLK_IN),
.RST_IN(RST_IN),
.TM1638_STB(TM1638_STB),
.TM1638_CLK(TM1638_CLK),
.TM1638_DIO(TM1638_DIO)
);
assign TM1638_DIO = dio;
initial begin
CLK_IN = 1;
forever #41 CLK_IN = ~CLK_IN; // generate a clock arround 24Mhz
end
task assert(input integer value, input integer expected, input [1024*8-1:0] name, input integer line);
begin
if (expected !== value)
begin
$display("ERROR: with '%0s' on %0d expected %0b get %0b", name, line, expected, value);
#1000
$stop;
end
end
endtask
task readByte(output [7:0] byte);
reg [3:0] bitCpt;
begin
bitCpt = 0;
repeat (8)
begin
@(negedge TM1638_CLK);
assert(TM1638_STB, 0, "TM1638_STB", `__LINE__);
@(posedge TM1638_CLK);
assert(TM1638_STB, 0, "TM1638_STB", `__LINE__);
byte[bitCpt] = TM1638_DIO;
bitCpt = bitCpt + 1;
end
end
endtask
task writeByte(input [7:0] byte);
reg [3:0] bitCpt;
begin
bitCpt = 0;
repeat (8)
begin
@(negedge TM1638_CLK);
assert(TM1638_STB, 0, "TM1638_STB", `__LINE__);
dio = byte[bitCpt];
bitCpt = bitCpt + 1;
@(posedge TM1638_CLK);
assert(TM1638_STB, 0, "TM1638_STB", `__LINE__);
end
#41
dio = 1'bz;
end
endtask
initial begin
dio = 1'bz;
hexaIndex = 0;
// Reset
RST_IN = 1;
#500
RST_IN = 0;
#500
RST_IN = 1;
// Send to TM1638: Init
@(negedge TM1638_STB);
readByte(byte);
@(posedge TM1638_STB);
assert(byte, 8'b10001111, "byte", `__LINE__);
repeat (8)
begin
// Send to TM1638: command read
@(negedge TM1638_STB);
readByte(byte);
assert(byte, 8'b01000010, "byte", `__LINE__);
assert(TM1638_CLK, 1'b1, "TM1638_CLK", `__LINE__);
// Read from TM1638: button state (only bit 0 and 4 of each byte)
writeByte(8'b00000001);
writeByte(8'b00000000);
writeByte(8'b00000000);
writeByte(8'b00010000);
@(posedge TM1638_STB);
// Send to TM1638: command write
@(negedge TM1638_STB);
readByte(byte);
@(posedge TM1638_STB);
assert(byte, 8'b01000100, "byte", `__LINE__);
// Send to TM1638: addr hexaIndex
@(negedge TM1638_STB);
readByte(byte);
assert(byte, {4'b1100, hexaIndex, 1'b0}, "byte", `__LINE__);
// Send to TM1638: data display X
readByte(byte);
@(posedge TM1638_STB);
if (hexaIndex == 6)
// Display 1
assert(byte, 8'b00000110, "byte", `__LINE__);
else if (hexaIndex == 7)
// Display 8
assert(byte, 8'b01111111, "byte", `__LINE__);
else
// Display 0
assert(byte, 8'b00111111, "byte", `__LINE__);
hexaIndex = hexaIndex + 1;
end
#500
$display("SUCCESS");
$stop;
end
endmodule
| 6.686042 |
module tm1638Cpt (
input wire CLK_IN,
input wire RST_IN,
output wire TM1638_STB,
output wire TM1638_CLK,
output wire TM1638_DIO
);
parameter CLOCK_SLOW = 5; // Work in reel between 2 and 15
parameter WRITE_SLOW = 20; // Nice with 20 for humain reading
wire tm1638Ready;
wire [7:0] tm1638DataIn;
reg [CLOCK_SLOW:0] clkSlowCpt;
reg [WRITE_SLOW:0] writeSlowCpt;
reg [3:0] data;
reg [3:0] tm1638Addr;
reg tm1638W;
always @(posedge CLK_IN) begin
if (RST_IN == 0) begin
clkSlowCpt <= 0;
writeSlowCpt <= 1;
data <= 4'b1111;
tm1638Addr <= 4'b1110;
tm1638W <= 1'b0;
end else begin
clkSlowCpt <= clkSlowCpt + 1'b1;
// If ready
if (tm1638Ready == 1) begin
// Wait time to write
if (writeSlowCpt != 0) writeSlowCpt <= writeSlowCpt + 1'b1;
// If time to write
else begin
// Ask to write
tm1638W <= 1'b1;
// Prepare to write
tm1638Addr <= {tm1638Addr[3:1] + 1'b1, 1'b0};
data <= data + 1'b1;
end
end // If write
else if (tm1638W == 1'b1) begin
// Stop asking to write
tm1638W <= 1'b0;
// Reset write slow compter
writeSlowCpt <= 1;
end
end
end
hexTo7Seg hexTo7Seg_1 (
.HEX(data),
.DOT(1'b0),
.SEG(tm1638DataIn)
);
tm1638 tm1638_1 (
.RST_IN(RST_IN),
.DATA_IN(tm1638DataIn),
.ADDR(tm1638Addr),
.WRITE(tm1638W),
.CLK_IN(clkSlowCpt[CLOCK_SLOW]),
.STB(TM1638_STB),
.DIO(TM1638_DIO),
.CLK_OUT(TM1638_CLK),
.READY(tm1638Ready)
);
endmodule
| 6.778358 |
module tm1638Cpt_tb();
reg CLK_IN;
reg RST_IN;
wire TM1638_STB;
wire TM1638_CLK;
tri1 TM1638_DIO;
reg [7:0] byte;
glbl glbl();
defparam uut.CLOCK_SLOW = 0;
defparam uut.WRITE_SLOW = 0;
tm1638Cpt uut(
.CLK_IN(CLK_IN),
.RST_IN(RST_IN),
.TM1638_STB(TM1638_STB),
.TM1638_CLK(TM1638_CLK),
.TM1638_DIO(TM1638_DIO)
);
initial begin
CLK_IN = 0;
forever #41 CLK_IN = ~CLK_IN; // generate a clock arround 24Mhz
end
task assert(input integer value, input integer expected, input [1024*8-1:0] name, input integer line);
begin
if (expected !== value)
begin
$display("ERROR: with '%0s' on %0d expected %0b get %0b", name, line, expected, value);
#1000
$stop;
end
end
endtask
task readByte(output [7:0] byte);
reg [3:0] bitCpt;
begin
bitCpt = 0;
repeat (8)
begin
@(negedge TM1638_CLK);
assert(TM1638_STB, 0, "TM1638_STB", `__LINE__);
@(posedge TM1638_CLK);
assert(TM1638_STB, 0, "TM1638_STB", `__LINE__);
byte[bitCpt] = TM1638_DIO;
bitCpt = bitCpt + 1;
end
end
endtask
initial begin
// Reset
RST_IN = 1;
#500
RST_IN = 0;
#500
RST_IN = 1;
// Send to TM1638: Init
@(negedge TM1638_STB);
readByte(byte);
assert(byte, 8'b10001111, "byte", `__LINE__);
@(posedge TM1638_STB);
// Send to TM1638: Write data
@(negedge TM1638_STB);
readByte(byte);
assert(byte, 8'b01000100, "byte", `__LINE__);
@(posedge TM1638_STB);
// Send to TM1638: addr 0
@(negedge TM1638_STB);
readByte(byte);
assert(byte, 8'b11000000, "byte", `__LINE__);
// Send to TM1638: data display 0
readByte(byte);
assert(byte, 8'b00111111, "byte", `__LINE__);
@(posedge TM1638_STB);
// Send to TM1638: Write data
@(negedge TM1638_STB);
readByte(byte);
assert(byte, 8'b01000100, "byte", `__LINE__);
@(posedge TM1638_STB);
// Send to TM1638: addr 2
@(negedge TM1638_STB);
readByte(byte);
assert(byte, 8'b11000010, "byte", `__LINE__);
// Send to TM1638: data display 1
readByte(byte);
assert(byte, 8'b00000110, "byte", `__LINE__);
@(posedge TM1638_STB);
#10
$display("SUCCESS");
$stop;
end
endmodule
| 6.526589 |
module tm1638SegHex4 (
input wire CLK_IN,
input wire RST_IN,
input wire READY,
output reg READ_BUTTON,
output reg WRITE_SEG,
output reg [2:0] SEG_INDEX,
output wire [3:0] SEG_DATA,
input wire [31:0] SEG_HEX_ALL
);
localparam WRITE_SLOW = 5; // Nice with 20 for humain reading
localparam READ_SLOW = 0; // TODO
reg [WRITE_SLOW:0] writeSlowCpt;
reg [ READ_SLOW:0] readSlowCpt;
always @(posedge CLK_IN) begin
if (RST_IN == 0) begin
writeSlowCpt <= 1;
readSlowCpt <= 1;
SEG_INDEX <= 0;
WRITE_SEG <= 1'b0;
READ_BUTTON <= 1'b0;
end else begin
// If ready
if (READY == 1) begin
// If time to read
if (readSlowCpt == 0) begin
// Ask to read
READ_BUTTON <= 1'b1;
end // If time to write
else if (writeSlowCpt == 0) begin
// Ask to write
WRITE_SEG <= 1'b1;
end else begin
// Wait time to write
writeSlowCpt <= writeSlowCpt + 1'b1;
// Wait time to read
readSlowCpt <= readSlowCpt + 1'b1;
end
end // If write
else if (WRITE_SEG == 1'b1) begin
// Stop asking to write
WRITE_SEG <= 1'b0;
// Prepare next data to write
SEG_INDEX <= SEG_INDEX + 1'b1;
// Reset write slow compter
writeSlowCpt <= 1;
end // If read
else if (READ_BUTTON == 1'b1) begin
// Stop asking to read
READ_BUTTON <= 1'b0;
// Reset read slow compter
readSlowCpt <= 1;
end
end
end
function [3:0] computeHexTo7SegDataIn(input [2:0] index, input [31:0] data);
case (index)
3'h7: computeHexTo7SegDataIn = data[3:0];
3'h6: computeHexTo7SegDataIn = data[7:4];
3'h5: computeHexTo7SegDataIn = data[11:8];
3'h4: computeHexTo7SegDataIn = data[15:12];
3'h3: computeHexTo7SegDataIn = data[19:16];
3'h2: computeHexTo7SegDataIn = data[23:20];
3'h1: computeHexTo7SegDataIn = data[27:24];
3'h0: computeHexTo7SegDataIn = data[31:28];
endcase
endfunction
assign SEG_DATA = computeHexTo7SegDataIn(SEG_INDEX, SEG_HEX_ALL);
endmodule
| 6.815954 |
module TB_TM1638_LED_KEY_DRV #(
parameter C_C = 10.0
)(
) ;
reg CK ;
initial begin
CK <= 1'b1 ;
forever begin
#( C_C /2) ;
CK <= ~ CK ;
end
end
reg XARST ;
initial begin
XARST <= 1'b1 ;
#( 0.1 * C_C) ;
XARST <= 1'b0 ;
#( 2.1 * C_C) ;
XARST <= 1'b1 ;
end
wire FRAME_REQ_o ;
wire EN_CK_o ;
reg BIN2BCD_ON_i ;
wire ENCBIN_XDIRECT_i;
wire MISO_i ;
wire MOSI ;
wire MOSI_OE ;
wire SCLK_o ;
wire SS_o ;
wire [ 7:0] KEYS ;
assign ENCBIN_XDIRECT_i = 1'b1 ; //
TM1638_LED_KEY_DRV #(
.C_FCK ( 4096 )// Hz
, .C_FSCLK ( 1024 )// Hz
, .C_FPS ( 1 )// cycle(Hz)
) TM1638_LED_KEY_DRV (
.CK_i ( CK )
, .XARST_i ( XARST )
, .DIRECT7SEG0_i ( 7'b0111111 )
, .DIRECT7SEG1_i ( 7'b0000110 )
, .DIRECT7SEG2_i ( 7'b1011011 )
, .DIRECT7SEG3_i ( 7'b1001111 )
, .DIRECT7SEG4_i ( 7'b1100110 )
, .DIRECT7SEG5_i ( 7'b1101101 )
, .DIRECT7SEG6_i ( 7'b1111101 )
, .DIRECT7SEG7_i ( 7'b0100111 )
, .DOTS_i ( KEYS )
, .LEDS_i ( 8'hFF )
, .BIN_DAT_i ( {
4'h0
, 4'h5
, 4'hE
, 4'h3
, 4'h0
, 4'hA
, 4'h7
, 4'h8
})
, .SUP_DIGITS_i ()
, .ENCBIN_XDIRECT_i ( ENCBIN_XDIRECT_i)
, .BIN2BCD_ON_i ( BIN2BCD_ON_i )
, .FRAME_REQ_o ( FRAME_REQ_o )
, .EN_CK_o ( EN_CK_o )
, .MISO_i ( MISO_i )
, .MOSI_o ( MOSI )
, .MOSI_OE_o ( MOSI_OE )
, .SCLK_o ( SCLK_o )
, .SS_o ( SS_o )
, .KEYS_o ( KEYS )
) ;
integer TB_CTR ;
initial begin
TB_CTR <= 'd0 ;
BIN2BCD_ON_i <= 1'b1 ;
repeat ( 100 ) begin
repeat ( 100 )
@(posedge CK) ;
TB_CTR <= TB_CTR +1 ;
end
$stop ;
end
endmodule
| 7.122013 |
module TM1638_shifter (
reset,
clock,
data_in,
data_io,
strobe
);
input reset;
input clock;
input [7:0] data_in;
tri0 reset;
tri0 [7:0] data_in;
output data_io;
output strobe;
reg data_io;
reg reg_data_io;
reg strobe;
reg [8:0] fstate;
reg [8:0] reg_fstate;
parameter state1=0,state2=1,state3=2,state4=3,state5=4,state6=5,state7=6,state8=7,state9=8;
initial begin
reg_data_io <= 1'b0;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
fstate <= state1;
end else begin
fstate <= reg_fstate;
end
end
always @(fstate or data_in or reg_data_io) begin
reg_data_io <= 1'b0;
strobe <= 1'b0;
data_io <= 1'b0;
case (fstate)
state1: begin
reg_fstate <= state2;
strobe <= 1'b0;
reg_data_io <= data_in[0];
end
state2: begin
reg_fstate <= state3;
reg_data_io <= data_in[1];
end
state3: begin
reg_fstate <= state4;
reg_data_io <= data_in[2];
end
state4: begin
reg_fstate <= state5;
reg_data_io <= data_in[3];
end
state5: begin
reg_fstate <= state6;
reg_data_io <= data_in[4];
end
state6: begin
reg_fstate <= state7;
reg_data_io <= data_in[5];
end
state7: begin
reg_fstate <= state8;
reg_data_io <= data_in[6];
end
state8: begin
reg_fstate <= state9;
strobe <= 1'b1;
reg_data_io <= data_in[7];
end
state9: begin
reg_fstate <= state9;
reg_data_io <= 1'b0;
end
default: begin
reg_data_io <= 1'bx;
strobe <= 1'bx;
$display("Reach undefined state");
end
endcase
data_io <= reg_data_io;
end
endmodule
| 6.612541 |
module tMDR;
wire [15:0] bus;
reg rOutEn, readEn, writeEn, reset;
wire [15:0] dToWriteOut;
reg [15:0] dReadIn;
MDR mdr (
bus,
dReadIn,
dToWriteOut,
readEn,
writeEn,
rOutEn,
reset
);
initial begin
rOutEn = 0;
#5 dReadIn = 16'd5;
readEn = 1;
#5 readEn = 0;
rOutEn = 1;
#5 rOutEn = 0;
end
endmodule
| 6.739352 |
module tmds_decode (
input clk,
input [9:0] in,
output data_valid,
output sync_valid,
output ctrl_valid,
output [7:0] data,
output [1:0] sync, // hsync/vsync
output [3:0] ctrl // audio header?
);
// the sync control bits are encoded with four specific patterns
parameter CTRL_00 = 10'b1101010100; // 354
parameter CTRL_01 = 10'b0010101011; // 0AB
parameter CTRL_10 = 10'b0101010100; // 154
parameter CTRL_11 = 10'b1010101011; // 2AB
// the control channel data
parameter TERC4_0 = 10'b1010011100;
parameter TERC4_1 = 10'b1001100011;
parameter TERC4_2 = 10'b1011100100;
parameter TERC4_3 = 10'b1011100010;
parameter TERC4_4 = 10'b0101110001;
parameter TERC4_5 = 10'b0100011110;
parameter TERC4_6 = 10'b0110001110;
parameter TERC4_7 = 10'b0100111100;
parameter TERC4_8 = 10'b1011001100;
parameter TERC4_9 = 10'b0100111001;
parameter TERC4_A = 10'b0110011100;
parameter TERC4_B = 10'b1011000110;
parameter TERC4_C = 10'b1010001110;
parameter TERC4_D = 10'b1001110001;
parameter TERC4_E = 10'b0101100011;
parameter TERC4_F = 10'b1011000011;
// first two of the 10 bits encodes the how the other bits
// are encoded (either inverted and either xor or xnor)
// see page 83 of HDMI 1.3 spec
wire invert = in[9];
wire use_xor = in[8];
wire [7:0] in_bits = invert ? ~in[7:0] : in;
wire [7:0] in_xor = {in_bits[6:0] ^ in_bits[7:1], in_bits[0]};
wire [7:0] in_xnor = {in_bits[6:0] ^~ in_bits[7:1], in_bits[0]};
wire [7:0] data_out = use_xor ? in_xor : in_xnor;
reg data_valid;
reg sync_valid;
reg ctrl_valid;
reg [7:0] data;
reg [1:0] sync;
reg [3:0] ctrl;
always @(posedge clk) begin
sync_valid <= 0;
ctrl_valid <= 0;
data_valid <= 0;
data <= data_out;
case (in)
CTRL_00: {sync_valid, sync} = {1'b1, 2'b00};
CTRL_01: {sync_valid, sync} = {1'b1, 2'b01};
CTRL_10: {sync_valid, sync} = {1'b1, 2'b10};
CTRL_11: {sync_valid, sync} = {1'b1, 2'b11};
TERC4_0: {ctrl_valid, ctrl} = {1'b1, 4'h0};
TERC4_1: {ctrl_valid, ctrl} = {1'b1, 4'h1};
TERC4_2: {ctrl_valid, ctrl} = {1'b1, 4'h2};
TERC4_3: {ctrl_valid, ctrl} = {1'b1, 4'h3};
TERC4_4: {ctrl_valid, ctrl} = {1'b1, 4'h4};
TERC4_5: {ctrl_valid, ctrl} = {1'b1, 4'h5};
TERC4_6: {ctrl_valid, ctrl} = {1'b1, 4'h6};
TERC4_7: {ctrl_valid, ctrl} = {1'b1, 4'h7};
TERC4_8: {ctrl_valid, ctrl} = {1'b1, 4'h8};
TERC4_9: {ctrl_valid, ctrl} = {1'b1, 4'h9};
TERC4_A: {ctrl_valid, ctrl} = {1'b1, 4'hA};
TERC4_B: {ctrl_valid, ctrl} = {1'b1, 4'hB};
TERC4_C: {ctrl_valid, ctrl} = {1'b1, 4'hC};
TERC4_D: {ctrl_valid, ctrl} = {1'b1, 4'hD};
TERC4_E: {ctrl_valid, ctrl} = {1'b1, 4'hE};
TERC4_F: {ctrl_valid, ctrl} = {1'b1, 4'hF};
default: data_valid <= 1;
endcase
/*
if (in == CTRL_00) { sync_valid, sync } = { 1'b1, 2'b00 }; else
if (in == CTRL_01) { sync_valid, sync } = { 1'b1, 2'b01 }; else
if (in == CTRL_10) { sync_valid, sync } = { 1'b1, 2'b10 }; else
if (in == CTRL_11) { sync_valid, sync } = { 1'b1, 2'b11 }; else
data_valid <= 1;
*/
end
endmodule
| 7.591102 |
module tmdstest (
// {{{
// (i_clk, i_dtype, i_ctl, i_color, o_ctl, o_color);
input wire i_clk,
input wire [1:0] i_dtype,
input wire [1:0] i_ctl,
input wire [7:0] i_color,
//
output reg [1:0] o_ctl,
output reg [7:0] o_color
// }}}
);
// Local declarations
// {{{
reg [9:0] tmds_word;
reg [1:0] dec_ctl;
reg [6:0] dec_aux;
reg [7:0] dec_pix;
reg [2:0] runup;
reg valid_test;
// }}}
tmdsencode encoder (
i_clk,
i_dtype,
i_ctl,
i_color[3:0],
i_color,
tmds_word
);
tmdsdecode decoder (
i_clk,
tmds_word,
dec_ctl,
dec_aux,
dec_pix
);
// o_color
// {{{
always @(*) o_color = dec_pix;
// }}}
// o_ctl
// {{{
always @(*) o_ctl = dec_ctl;
// }}}
// runup
// {{{
initial runup = 0;
always @(posedge i_clk) if (runup != 3'h7) runup <= runup + 1'b1;
// }}}
// valid_test
// {{{
initial valid_test = 1'b0;
always @(posedge i_clk) if (runup == 3'h7) valid_test <= 1'b1;
// }}}
// Make verilator happy
// {{{
// Verilator lint_off UNUSED
wire unused;
assign unused = &{1'b0, valid_test, dec_aux, dec_pix};
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal property checks
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
always @(posedge i_clk)
if (valid_test) begin
case ($past(
i_dtype, 4
))
2'b00: // Guard period
assert (dec_aux[6] && dec_ctl == 2'b0);
2'b01: // Control period
assert (dec_aux[4] && (dec_ctl == $past(i_ctl, 4)));
2'b10: // Data Island
assert (dec_aux[5] && (dec_aux[3:0] == $past(i_color[3:0], 4)));
2'b11: // Video data
assert ((!dec_aux[4]) && (o_color == $past(i_color, 4)));
endcase
end
always @(posedge i_clk) if (runup != 0) assume (i_dtype == $past(i_dtype));
`endif
// }}}
endmodule
| 7.028243 |
module TMDS_8b10b_enc (
input rst,
input [7:0] d,
input [1:0] c,
input den,
input clk,
output [9:0] q
);
// I. fázis: q_m kiszámítása invert_d_m alapján
reg [7:0] d_m;
wire [8:0] q_m;
wire invert_d_m;
assign q_m = {~invert_d_m, d_m[7:0]};
always @(*) begin
if (rst) d_m <= 8'b0;
else begin
d_m[0] <= d[0];
d_m[1] <= d_m[0] ^ d[1] ^ invert_d_m;
d_m[2] <= d_m[1] ^ d[2] ^ invert_d_m;
d_m[3] <= d_m[2] ^ d[3] ^ invert_d_m;
d_m[4] <= d_m[3] ^ d[4] ^ invert_d_m;
d_m[5] <= d_m[4] ^ d[5] ^ invert_d_m;
d_m[6] <= d_m[5] ^ d[6] ^ invert_d_m;
d_m[7] <= d_m[6] ^ d[7] ^ invert_d_m;
end
end
// bitszámlálók
wire [3:0] d_1s;
wire [3:0] q_m_1s;
wire [3:0] q_m_0s = 8 - q_m_1s;
BITADD8 d_bitadd (
.d(d),
.q(d_1s)
);
BITADD8 q_m_bitadd (
.d(q_m[7:0]),
.q(q_m_1s)
);
//BITADD8 q_m_n_bitadd(.d(~q_m), .q(q_m_0s));
// invert_d_m kiszámolása
assign invert_d_m = d_1s > 4 || (d_1s == 4 & ~d[0]);
// Stream disparity számláló
reg [9:0] cnt;
// kimenet előállítása
// q[9] = invertálva van-e q[7:0]
// q[8] = invert_d_m
reg [9:0] q_out;
assign q = q_out;
always @(posedge clk) begin
if (rst) begin
cnt <= 10'b0;
q_out <= 10'b0;
end else if (den)
if ((~&cnt) || (q_m_1s == q_m_0s)) begin
// ki van súlyozva
q_out[9] <= ~q_m[8];
q_out[8] <= q_m[8];
if (q_m[8]) begin
q_out[7:0] <= q_m[7:0];
cnt <= cnt + q_m_1s - q_m_0s;
end else begin
q_out[7:0] <= ~q_m[7:0];
cnt <= cnt + q_m_0s - q_m_1s;
end
end else begin
if (
// túl sok egyes, invertálandó
(cnt > 0 && q_m_1s > q_m_0s) ||
// túl sok nullás, invertálandó
(cnt < 0 && q_m_1s < q_m_0s)) begin
q_out[9] <= 1'b1;
q_out[8] <= q_m[8];
q_out[7:0] <= ~q_m[7:0];
cnt <= cnt + (q_m[8] << 1) + q_m_0s - q_m_1s;
end else begin
q_out[9] <= 1'b0;
q_out[8] <= q_m[8];
q_out[7:0] <= q_m[7:0];
cnt <= cnt + (~q_m[8] << 1) + q_m_1s - q_m_0s;
end
end
else
case (c)
2'b00: q_out <= 10'b1101010100;
2'b01: q_out <= 10'b0010101011;
2'b10: q_out <= 10'b0101010100;
2'b11: q_out <= 10'b1010101011;
endcase
end
endmodule
| 6.722801 |
module used for simulation to test the encoder
// By Liam Davey (3/3/2011)
`timescale 1ns / 1ps
module tmds_decode (
input clk, input rst,
input [9:0] q_in,
output reg [7:0] d,
output reg c0,
output reg c1,
output reg de,
output reg signed [7:0] cnt);
reg [9:0] s1_q_in;
wire [7:0] d_q;
reg c0_1, c1_1, de_1;
genvar i;
wire signed [7:0] n1_q_in = q_in[9] + q_in[8] + q_in[7] + q_in[6] + q_in[5] + q_in[4] + q_in[3] + q_in[2] + q_in[1] + q_in[0];
reg signed [7:0] q_in_disparity;
// decode stage 2, XNOR or XOR depending on bit 8
assign d_q[0] = s1_q_in[0];
for (i = 1; i < 8; i = i + 1) begin : decode_loop
assign d_q[i] = (s1_q_in[8]) ? (s1_q_in[i] ^ s1_q_in[i - 1]) : ~(s1_q_in[i] ^ s1_q_in[i - 1]);
end
always @ (posedge clk) begin
if (rst) begin
cnt <= 0;
end else begin
case(q_in)
10'b1101010100 : {de_1, c0_1, c1_1} <= 3'b000;
10'b0010101011 : {de_1, c0_1, c1_1} <= 3'b001;
10'b0101010100 : {de_1, c0_1, c1_1} <= 3'b010;
10'b1010101011 : {de_1, c0_1, c1_1} <= 3'b011;
default : {de_1, c0_1, c1_1} <= 3'b100;
endcase
// decode stage 1, invert data bits if bit 9 set
s1_q_in[9:8] <= q_in[9:8];
s1_q_in[7:0] <= (q_in[9]) ? (~q_in[7:0]) : (q_in[7:0]);
// output results from stage 2
d <= d_q;
de <= de_1;
c0 <= c0_1;
c1 <= c1_1;
// update cnt, the disparity count
q_in_disparity = {n1_q_in, 1'b0} - 8'd10;
cnt <= cnt + q_in_disparity;
end
end
endmodule
| 7.055139 |
module tmds_encoder_dvi (
input wire i_clk, // clock
input wire i_rst, // reset (active high)
input wire [7:0] i_data, // colour data
input wire [1:0] i_ctrl, // control data
input wire i_de, // display enable (active high)
output reg [9:0] o_tmds // encoded TMDS data
);
// select basic encoding based on the ones in the input data
wire [3:0] d_ones = {3'b0,i_data[0]} + {3'b0,i_data[1]} + {3'b0,i_data[2]}
+ {3'b0,i_data[3]} + {3'b0,i_data[4]} + {3'b0,i_data[5]}
+ {3'b0,i_data[6]} + {3'b0,i_data[7]};
wire use_xnor = (d_ones > 4'd4) || ((d_ones == 4'd4) && (i_data[0] == 0));
// encode colour data with xor/xnor
/* verilator lint_off UNOPTFLAT */
wire [8:0] enc_qm;
assign enc_qm[0] = i_data[0];
assign enc_qm[1] = (use_xnor) ? (enc_qm[0] ~^ i_data[1]) : (enc_qm[0] ^ i_data[1]);
assign enc_qm[2] = (use_xnor) ? (enc_qm[1] ~^ i_data[2]) : (enc_qm[1] ^ i_data[2]);
assign enc_qm[3] = (use_xnor) ? (enc_qm[2] ~^ i_data[3]) : (enc_qm[2] ^ i_data[3]);
assign enc_qm[4] = (use_xnor) ? (enc_qm[3] ~^ i_data[4]) : (enc_qm[3] ^ i_data[4]);
assign enc_qm[5] = (use_xnor) ? (enc_qm[4] ~^ i_data[5]) : (enc_qm[4] ^ i_data[5]);
assign enc_qm[6] = (use_xnor) ? (enc_qm[5] ~^ i_data[6]) : (enc_qm[5] ^ i_data[6]);
assign enc_qm[7] = (use_xnor) ? (enc_qm[6] ~^ i_data[7]) : (enc_qm[6] ^ i_data[7]);
assign enc_qm[8] = (use_xnor) ? 0 : 1;
/* verilator lint_on UNOPTFLAT */
// disparity in encoded data for DC balancing: needs to cover -8 to +8
wire signed [4:0] ones = {4'b0,enc_qm[0]} + {4'b0,enc_qm[1]}
+ {4'b0,enc_qm[2]} + {4'b0,enc_qm[3]} + {4'b0,enc_qm[4]}
+ {4'b0,enc_qm[5]} + {4'b0,enc_qm[6]} + {4'b0,enc_qm[7]};
wire signed [4:0] zeros = 5'b01000 - ones;
wire signed [4:0] balance = ones - zeros;
// record ongoing DC bias
reg signed [4:0] bias;
always @(posedge i_clk) begin
if (i_rst) begin
o_tmds <= 10'b1101010100; // equivalent to ctrl 2'b00
bias <= 5'sb00000;
end
else if (i_de == 0) // send control data in blanking interval
begin
case (i_ctrl) // ctrl sequences (always have 7 transitions)
2'b00: o_tmds <= 10'b1101010100;
2'b01: o_tmds <= 10'b0010101011;
2'b10: o_tmds <= 10'b0101010100;
default: o_tmds <= 10'b1010101011;
endcase
bias <= 5'sb00000;
end else // send pixel colour data (at most 5 transitions)
begin
if (bias == 0 || balance == 0) // no prior bias or disparity
begin
if (enc_qm[8] == 0) begin
$display("\t%d %b %d, %d, A1", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {2'b10, ~enc_qm[7:0]};
bias <= bias - balance;
end else begin
$display("\t%d %b %d, %d, A0", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {2'b01, enc_qm[7:0]};
bias <= bias + balance;
end
end else if ((bias > 0 && balance > 0) || (bias < 0 && balance < 0)) begin
$display("\t%d %b %d, %d, B1", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {1'b1, enc_qm[8], ~enc_qm[7:0]};
bias <= bias + {3'b0, enc_qm[8], 1'b0} - balance;
end else begin
$display("\t%d %b %d, %d, B0", i_data, enc_qm, ones, bias);
o_tmds[9:0] <= {1'b0, enc_qm[8], enc_qm[7:0]};
bias <= bias - {3'b0, ~enc_qm[8], 1'b0} + balance;
end
end
end
endmodule
| 6.697413 |
module tmds_encode_dvi_tb ();
reg rst;
reg clk;
reg [7:0] data;
reg [1:0] ctrl;
reg de;
wire [9:0] tmds;
reg [8:0] cycle;
// encoded TMDS data $display(...) is within tmds_encoder_dvi.v
initial begin
$display("\t 1s B O");
clk = 1;
rst = 1;
de = 0;
ctrl = 2'b00;
#10 rst = 0;
#10 de = 1;
end
tmds_encoder_dvi tmds_test (
.i_clk (clk),
.i_rst (rst),
.i_data(data),
.i_ctrl(ctrl),
.i_de (de),
.o_tmds(tmds)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
cycle <= 0;
data <= 0;
end else begin
cycle <= cycle + 1;
data <= cycle[7:0];
end
end
always #5 clk = ~clk;
endmodule
| 7.516153 |
module tmds_encoder_tb ();
parameter CLOCKPERIOD = 10;
reg reset;
reg clock;
reg disp_en;
reg [1:0] ctrl;
reg [7:0] data;
wire [9:0] tmds;
// for counting the cycles
reg [15:0] cycle;
// module, parameters, instance, ports
tmds_encoder #() tmds_encoder (
.clk(clock),
.reset(reset),
.disp_en(disp_en),
.ctrl(ctrl),
.data(data),
.tmds(tmds)
);
// Initial conditions; setup
initial begin
$timeformat(-9, 1, "ns", 12);
$monitor("%t, CYCLE: %d, DISP_EN: %b, CTRL: %b, DATA: %b, TMDS: %b", $realtime, cycle, disp_en,
ctrl, data, tmds);
$display("Initializing");
cycle <= 0;
reset <= 1'b0;
disp_en <= 1'b0;
ctrl <= 2'b00;
data <= 8'b00000000;
#1 reset <= 1'b1;
// Initial clock setting
#10 clock <= 1'b0;
#10 ctrl <= 2'b00;
#10 ctrl <= 2'b01;
#10 ctrl <= 2'b10;
#10 ctrl <= 2'b11;
#10 ctrl <= 2'b00;
#10 disp_en <= 1'b1;
#100 $finish;
end
/**************************************************************/
/* The following can be left as-is unless necessary to change */
/**************************************************************/
// Cycle Counter
always @(posedge clock) cycle <= cycle + 1;
// Clock generation
always #(CLOCKPERIOD / 2) clock <= ~clock;
/*
Conditional Environment Settings for the following:
- Icarus Verilog
- VCS
- Altera Modelsim
- Xilinx ISIM
*/
// Icarus Verilog
`ifdef IVERILOG
initial $dumpfile("vcdbasic.vcd");
initial $dumpvars();
`endif
// VCS
`ifdef VCS
initial $vcdpluson;
`endif
// Altera Modelsim
`ifdef MODEL_TECH
`endif
// Xilinx ISIM
`ifdef XILINX_ISIM
`endif
endmodule
| 6.697413 |
module tmds_encode_tb;
// Inputs
reg clk;
reg rst;
reg [7:0] d;
reg de;
reg c0;
reg c1;
// Outputs
wire [9:0] q_out;
wire [7:0] d_out;
wire de_out, c0_out, c1_out;
wire signed [7:0] count_out;
// Instantiate the Unit Under Test (UUT)
tmds_encode uut (
.clk(clk),
.rst(rst),
.d(d),
.de(de),
.c0(c0),
.c1(c1),
.q_out(q_out)
);
// inputs of decode module
tmds_decode u_tmds_decode (
.clk(clk),
.rst(rst),
.q_in(q_out),
.d(d_out),
.de(de_out),
.c0(c0_out),
.c1(c1_out),
.cnt(count_out)
);
always begin
#5 clk = ~clk;
end
reg rand_in_enable;
reg [7:0] delay_count, delay_length, delayed_d_in;
reg [7:0] d_delay[7:0];
always @(posedge clk) begin
if (de) begin
if (rand_in_enable) begin
d <= $random % 256;
case (delay_length)
8'd2: delayed_d_in = d_delay[0];
8'd3: delayed_d_in = d_delay[1];
8'd4: delayed_d_in = d_delay[2];
8'd5: delayed_d_in = d_delay[3];
8'd6: delayed_d_in = d_delay[4];
8'd7: delayed_d_in = d_delay[5];
8'd8: delayed_d_in = d_delay[6];
8'd9: delayed_d_in = d_delay[7];
default: delayed_d_in = 8'hxx;
endcase
if (d_out != delayed_d_in) begin
$display("error: dout (%x) != din (%x)", d_out, delayed_d_in);
end
end else begin
d <= (delay_count == 8'd0) ? 8'h5a : 8'h00;
delay_count <= delay_count + 1;
if (d_out == 8'h5a) begin
$display("received sync byte after delay of %d", delay_count);
delay_length <= delay_count;
rand_in_enable <= 1'b1;
end
end
d_delay[0] <= d;
d_delay[1] <= d_delay[0];
d_delay[2] <= d_delay[1];
d_delay[3] <= d_delay[2];
d_delay[4] <= d_delay[3];
d_delay[5] <= d_delay[4];
d_delay[6] <= d_delay[5];
d_delay[7] <= d_delay[6];
if (count_out < -10 || count_out > 10) begin
$display("warning: large disparity on differential line detected (%d)", count_out);
end
end
end
initial begin
$monitor("d_in=%x, d_out=%x, q_out=%x, count_out=%d", d, d_out, q_out, count_out);
$dumpfile("tmds_encode_tb.vcd");
$dumpvars;
// Initialize Inputs
clk = 0;
rst = 0;
d = 0;
de = 0;
c0 = 0;
c1 = 0;
rand_in_enable = 1'b0;
delay_count = 0;
delay_length = 0;
// reset pulse
#40 rst = 1'b1;
#80 rst = 1'b0;
// Add stimulus here
#120 de = 1'b1;
#1000 $finish;
end
endmodule
| 6.69946 |
module TMDS_Serializer (
input [9:0] RedEncoded,
input [9:0] BlueEncoded,
input [9:0] GreenEncoded,
input PixClk,
input PixClk5,
output [3:0] TMDS /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */
);
wire Sync;
ClockSync CS (
.PixClk(PixClk),
.PixClk5(PixClk5),
.Sync(Sync)
);
ComponentShift CSB (
.Data(BlueEncoded),
.PixClk5(PixClk5),
.Sync(Sync),
.SerOut(TMDS[0])
);
ComponentShift CSG (
.Data(GreenEncoded),
.PixClk5(PixClk5),
.Sync(Sync),
.SerOut(TMDS[1])
);
ComponentShift CSR (
.Data(RedEncoded),
.PixClk5(PixClk5),
.Sync(Sync),
.SerOut(TMDS[2])
);
ComponentShift CSC (
.Data(10'b0000011111),
.PixClk5(PixClk5),
.Sync(Sync),
.SerOut(TMDS[3])
);
endmodule
| 6.570039 |
module tmds_test (
input clk,
input enable,
output [3:0] tmds_p,
output [3:0] tmds_n
);
reg enable_r = 0;
reg test_a = 0, test_b = 0, test_c = 0, test_d = 0;
always @(posedge clk) begin
enable_r <= enable; // cross clock domains
test_a <= ~test_b & enable_r;
test_b <= test_a;
test_c <= test_a & ~test_b;
test_d <= test_c;
end
wire [3:0] tmds_d1 = {test_c, test_b, test_d, ~test_a};
wire [3:0] tmds_d2 = {test_a, test_c, test_b, test_d};
wire [3:0] tmds_q;
// Hardware-specific primitives, use unisims or unisims_lrd.
// No need for a generate loop, just use instance arrays.
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE")
) ddr[0:3] (
.Q (tmds_q),
.C (clk),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D1(tmds_d1),
.D2(tmds_d2)
);
OBUFDS obuf[0:3] (
.I (tmds_q),
.O (tmds_p),
.OB(tmds_n)
);
endmodule
| 7.55116 |
module tmds_test_tb;
integer cc;
reg clk, fail = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("tmds_test.vcd");
$dumpvars(5, tmds_test_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 100; cc = cc + 1) begin
clk = 0;
#2;
clk = 1;
#2;
end
if (fail) begin
$display("FAIL");
$stop(0);
end else begin
$display("PASS");
$finish(0);
end
end
tmds_test dut (
.clk(clk),
.enable(1'b1)
);
endmodule
| 7.288587 |
module tmds_top (
input wire pix_clk,
input wire sys_rst,
output wire [9:0] tmds_0,
output wire [9:0] tmds_1,
output wire [9:0] tmds_2,
output wire [9:0] tmds_3
);
//1920x1080@60Hz
parameter HPIXELS_HDTV1080P = 12'd1920; //Horizontal Live Pixels
parameter VLINES_HDTV1080P = 12'd1080; //Vertical Live ines
parameter HFNPRCH_HDTV1080P = 12'd88; //Horizontal Front Portch
parameter HSYNCPW_HDTV1080P = 12'd44; //HSYNC Pulse Width
parameter HBKPRCH_HDTV1080P = 12'd148; //Horizontal Back Portch
parameter VFNPRCH_HDTV1080P = 12'd4; //Vertical Front Portch
parameter VSYNCPW_HDTV1080P = 12'd5; //VSYNC Pulse Width
parameter VBKPRCH_HDTV1080P = 12'd36; //Vertical Back Portch
wire [11:0] tc_hsblnk = HPIXELS_HDTV1080P - 12'd1;
wire [11:0] tc_hssync = HPIXELS_HDTV1080P - 12'd1 + HFNPRCH_HDTV1080P;
wire [11:0] tc_hesync = HPIXELS_HDTV1080P - 12'd1 + HFNPRCH_HDTV1080P + HSYNCPW_HDTV1080P;
wire [11:0] tc_heblnk = HPIXELS_HDTV1080P - 12'd1 + HFNPRCH_HDTV1080P + HSYNCPW_HDTV1080P + HBKPRCH_HDTV1080P;
wire [11:0] tc_vsblnk = VLINES_HDTV1080P - 12'd1;
wire [11:0] tc_vssync = VLINES_HDTV1080P - 12'd1 + VFNPRCH_HDTV1080P;
wire [11:0] tc_vesync = VLINES_HDTV1080P - 12'd1 + VFNPRCH_HDTV1080P + VSYNCPW_HDTV1080P;
wire [11:0] tc_veblnk = VLINES_HDTV1080P - 12'd1 + VFNPRCH_HDTV1080P + VSYNCPW_HDTV1080P + VBKPRCH_HDTV1080P;
wire hvsync_polarity = 1'b0;
wire hdmi_hsync_int, hdmi_vsync_int;
wire [11:0] bgnd_hcount;
wire bgnd_hsync;
wire bgnd_hblnk;
wire [11:0] bgnd_vcount;
wire bgnd_vsync;
wire bgnd_vblnk;
timing timing_inst (
.tc_hsblnk(tc_hsblnk), //input
.tc_hssync(tc_hssync), //input
.tc_hesync(tc_hesync), //input
.tc_heblnk(tc_heblnk), //input
.hcount(bgnd_hcount), //output
.hsync(hdmi_hsync_int), //output
.hblnk(bgnd_hblnk), //output
.tc_vsblnk(tc_vsblnk), //input
.tc_vssync(tc_vssync), //input
.tc_vesync(tc_vesync), //input
.tc_veblnk(tc_veblnk), //input
.vcount(bgnd_vcount), //output
.vsync(hdmi_vsync_int), //output
.vblnk(bgnd_vblnk), //output
.restart(sys_rst),
.clk(pix_clk)
);
/* ------ V/H SYNC and DE generator ------ */
wire active;
assign active = !bgnd_hblnk && !bgnd_vblnk;
reg active_q;
reg vsync, hsync;
reg hdmi_hsync, hdmi_vsync;
reg vde;
wire [7:0] red_data, green_data, blue_data;
always @(posedge pix_clk) begin
hsync <= hdmi_hsync_int ^ hvsync_polarity;
vsync <= hdmi_vsync_int ^ hvsync_polarity;
hdmi_hsync <= hsync;
hdmi_vsync <= vsync;
active_q <= active;
vde <= active_q;
end
/* ------------- TMDS Encoder ---------------- */
hdmi_encoder_top enc0 (
.pclk (pix_clk),
.rstin (sys_rst),
.blue_din (blue_data),
.green_din(green_data),
.red_din (red_data),
.aux0_din (4'd0),
.aux1_din (4'd0),
.aux2_din (4'd0),
.hsync (hdmi_hsync),
.vsync (hdmi_vsync),
.vde (vde),
.ade (1'b0),
.sdata_r (tmds_2), // 10bit Red Channel
.sdata_g (tmds_1), // 10bit Green Channel
.sdata_b (tmds_0) // 10bit Blue Channel
);
assign tmds_3 = 10'b1111100000;
hdcolorbar clrbar (
.i_clk_74M(pix_clk),
.i_rst (sys_rst),
.i_hcnt (bgnd_hcount),
.i_vcnt (bgnd_vcount),
.baronly (1'b0),
.i_format (2'b00),
.o_r (red_data),
.o_g (green_data),
.o_b (blue_data)
);
endmodule
| 7.76149 |
module tmec_decode #(
parameter N = 15,
parameter K = 5,
parameter T = 3, /* Correctable errors */
parameter OPTION = "SERIAL"
) (
input clk,
input start,
input data_in,
output reg ready = 1,
output reg output_valid = 0,
output reg data_out = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = n2m(N);
localparam BUF_SIZE = OPTION == "SERIAL" ? (N + T * (M + 2) + 0) : (N + T * 2 + 1);
if (BUF_SIZE > 2 * N) begin
wire [log2(BUF_SIZE - N + 3)-1:0] wait_count;
counter #(BUF_SIZE - N + 2) u_wait (
.clk(clk),
.reset(start),
.ce(!ready),
.count(wait_count)
);
always @(posedge clk) begin
if (start) ready <= #TCQ 0;
else if (wait_count == BUF_SIZE - N + 2) ready <= #TCQ 1;
end
end
reg [BUF_SIZE-1:0] buf_ = 0;
wire [M*(2*T-1)-1:0] syn_shuffled;
wire [2*T*M-1:M] synN;
wire [M*(T+1)-1:0] sigma;
wire bsel;
wire ch_start;
wire next_l;
wire d_r_nonzero;
wire err;
wire syn_done;
wire syn_shuffle;
reg next_output_valid = 0;
wire ch_done;
reg ch_ready = 0;
wire [log2(T)-1:0] bch_n;
if (OPTION == "PARALLEL") begin
tmec_decode_parallel #(M, T) u_decode_parallel (
.clk(clk),
.syn_done(syn_done),
.bsel(bsel),
.bch_n(bch_n),
.syn1(synN[1*M+:M]),
.syn_shuffled(syn_shuffled),
.syn_shuffle(syn_shuffle),
.next_l(next_l),
.ch_start(ch_start),
.d_r_nonzero(d_r_nonzero),
.sigma(sigma)
);
end else if (OPTION == "SERIAL") begin
tmec_decode_serial #(M, T) u_decode_serial (
.clk(clk),
.syn_done(syn_done),
.bsel(bsel),
.bch_n(bch_n),
.syn1(synN[1*M+:M]),
.syn_shuffled(syn_shuffled),
.syn_shuffle(syn_shuffle),
.next_l(next_l),
.ch_start(ch_start),
.d_r_nonzero(d_r_nonzero),
.sigma(sigma)
);
end else illegal_option_value u_iov ();
reg [log2(T+1)-1:0] l = 0;
wire syn1_nonzero = |synN[1*M+:M];
counter #(T) u_bch_n_counter (
.clk(clk),
.reset(syn_done),
.ce(next_l),
.count(bch_n)
);
assign bsel = d_r_nonzero && bch_n >= l;
always @(posedge clk)
if (syn_done) l <= #TCQ{{log2(T + 1) - 1{1'b0}}, syn1_nonzero};
else if (next_l) if (bsel) l <= #TCQ 2 * bch_n - l + 1;
bch_syndrome #(M, T) u_bch_syndrome (
.clk(clk),
.ce(1'b1),
.start(start),
.done(syn_done),
.data_in(data_in),
.out(synN)
);
bch_syndrome_shuffle #(M, T) u_bch_syndrome_shuffle (
.clk(clk),
.start(syn_done),
.ce(syn_shuffle),
.synN(synN),
.syn_shuffled(syn_shuffled)
);
chien #(M, K, T) u_chien (
.clk(clk),
.ce(1'b1),
.start(ch_start),
.sigma(sigma),
.done(ch_done),
.err(err)
);
always @(posedge clk) begin
if (ch_ready) next_output_valid <= #TCQ 1;
else if (ch_done) next_output_valid <= #TCQ 0;
output_valid <= #TCQ next_output_valid;
ch_ready <= #TCQ ch_start;
buf_ <= #TCQ{buf_[BUF_SIZE-2:0], data_in};
data_out <= #TCQ(buf_[BUF_SIZE-1] ^ err) && next_output_valid;
end
endmodule
| 7.797956 |
module tmec_decode_serial #(
parameter M = 4,
parameter T = 3 /* Correctable errors */
) (
input clk,
input syn_done,
input bsel,
input [log2(T)-1:0] bch_n,
input [M-1:0] syn1,
input [M*(2*T-1)-1:0] syn_shuffled,
output syn_shuffle,
output next_l,
output ch_start,
output reg d_r_nonzero = 0,
output [M*(T+1)-1:0] sigma
);
`include "bch.vh"
localparam TCQ = 1;
wire [M-1:0] d_r;
wire [M-1:0] d_rp_dual;
wire [T:0] cin;
wire [T:0] sigma_serial; /* 0 bits of each sigma */
reg [M*(T+1)-1:0] beta = 0;
reg [M*(T-1)-1:0] sigma_last = 0; /* Last sigma values */
reg adder_ce = 0;
reg busy = 0;
wire [M*4-1:0] beta0; /* Initial beta */
wire [M*(T+1)-1:0] d_r0; /* Initial dr */
wire last_cycle;
wire first_cycle;
wire second_cycle;
wire penult1_cycle;
wire penult2_cycle;
/* beta(1)(x) = syn1 ? x^2 : x^3 */
assign beta0 = {{{M - 1{1'b0}}, !syn1}, {{M - 1{1'b0}}, |syn1}, {(M * 2) {1'b0}}};
/* d_r(0) = 1 + S_1 * x */
assign d_r0 = {syn1, {(M - 1) {1'b0}}, 1'b1};
always @(posedge clk) begin
if (syn_done) busy <= #TCQ 1;
else if (ch_start) busy <= #TCQ 0;
if (last_cycle || syn_done) adder_ce <= #TCQ 1;
else if (!busy || penult2_cycle) adder_ce <= #TCQ 0;
if (syn_done) begin
beta <= #TCQ beta0;
sigma_last <= #TCQ beta0[2*M+:2*M]; /* beta(1) */
end else if (last_cycle) begin
d_r_nonzero <= #TCQ |d_r;
sigma_last <= #TCQ sigma[0*M+:M*T];
/* b^(r+1)(x) = x^2 * (bsel ? sigmal^(r-1)(x) : b_(r)(x)) */
beta[2*M+:(T-1)*M] <= #TCQ(!bch_n || bsel) ? sigma_last[0*M+:(T-1)*M] : beta[0*M+:(T-1)*M];
end
end
wire [M-1:0] denom;
assign denom = syn_done ? syn1 : d_r; /* syn1 is d_p initial value */
/* d_rp = d_p^-1 * d_r */
finite_divider #(M) u_dinv (
.clk(clk),
.start(syn_done || (first_cycle && bsel)),
.standard_numer(d_r),
/* d_p = S_1 ? S_1 : 1 */
.standard_denom(denom ? denom : {1'b1}),
.dual_out(d_rp_dual)
);
/* mbN SDBM d_rp * beta_i(r) */
serial_mixed_multiplier #(M, T + 1) u_serial_mixed_multiplier (
.clk(clk),
.start(last_cycle),
.dual_in(d_rp_dual),
.standard_in(beta),
.standard_out(cin)
);
/* Add Beta * drp to sigma (Summation) */
/* simga_i^(r-1) + d_rp * beta_i^(r) */
finite_serial_adder #(M) u_cN[T:0] (
.clk(clk),
.start(syn_done),
.ce(adder_ce),
.parallel_in(d_r0),
.serial_in({(T + 1) {bch_n ? 1'b1 : 1'b0}} & cin),
.parallel_out(sigma),
.serial_out(sigma_serial)
);
/* d_r = summation (simga_i^(r-1) + d_rp * beta_i^(r)) * S_(2 * r - i + 1) from i = 0 to t */
serial_standard_multiplier #(M, T + 1) msm_serial_standard_multiplier (
.clk(clk),
.run(!last_cycle),
.start(second_cycle),
.parallel_in(syn_shuffled[0+:M*(T+1)]),
.serial_in(sigma_serial),
.out(d_r)
);
wire [log2(M+2)-1:0] count;
assign last_cycle = busy && count == M;
assign first_cycle = busy && count == M + 1;
assign second_cycle = busy && count == 0;
assign penult2_cycle = busy && count == M - 2;
assign penult1_cycle = busy && count == M - 1;
assign syn_shuffle = last_cycle;
assign ch_start = penult1_cycle && bch_n == T - 1;
assign next_l = last_cycle;
counter #(M + 2) u_counter (
.clk(clk),
.reset(syn_done || first_cycle),
.ce(busy),
.count(count)
);
endmodule
| 6.724826 |
module Brightness_Adjustor (
input_pixel,
output_pixel
);
input [15:0] input_pixel;
output reg [15:0] output_pixel;
always @(*) begin
if (input_pixel[15]) output_pixel = {1'b1, input_pixel[15:1]} + 16'd50;
else output_pixel = {1'b0, input_pixel[15:1]} + 16'd50;
end
endmodule
| 7.196841 |
module TMM2064P #(
parameter FILE_NAME = "",
// CY6264 timing and naming conventions (or thereabouts)
parameter tAA = "0:100:100", // address access time
parameter tOHA = "10", // output data hold time from address change
parameter tACE = "0:100:100", // CE access time
parameter tLZCE = "10", // CE to output low-Z
parameter tHZCE = "0:40:40", // CE to output high-Z
parameter tDOE = "0:40:40", // OE access time
parameter tLZOE = "5", // OE to output low-Z
parameter tHZOE = "0:35:35" // OE to output high-Z
) (
input wire CE1,
input wire CE2,
input wire OE,
input wire WE,
input wire [12:0] A,
inout wire [7:0] D
);
GENERIC_SRAM #(13, 8, FILE_NAME, tAA, tOHA, tACE, tLZCE, tHZCE, tDOE, tLZOE, tHZOE) sram (
.OE(OE),
.CE(CE1 && CE2),
.WE(WE),
.A (A),
.D (D)
);
endmodule
| 8.638044 |
module tmm_c (
input clk,
input rst_n,
input [19:0] m,
output reg clk_out
);
reg [19:0] count;
always @(posedge clk) begin
if (!rst_n) begin
count <= 0;
clk_out <= 0;
end else if (count == m - 1) begin
clk_out <= ~clk_out;
count <= 0;
end else if (count == m / 2 - 1) begin
clk_out <= ~clk_out;
count <= count + 1;
end else count <= count + 1;
end
endmodule
| 6.544512 |
module tmm_c1 (
input clk,
input rst_n,
input [19:0] m,
output reg clk_out
);
reg [19:0] count;
always @(posedge clk) begin
if (!rst_n) begin
count <= 0;
clk_out <= 0;
end else if (count == m - 1) begin
clk_out <= ~clk_out;
count <= 0;
end else if (count == m / 2 - 1) begin
clk_out <= ~clk_out;
count <= count + 1;
end else count <= count + 1;
end
endmodule
| 6.511921 |
module tmm_c2 (
input clk,
input rst_n,
input [19:0] m,
output reg clk_out
);
reg [19:0] count;
always @(posedge clk) begin
if (!rst_n) begin
count <= 0;
clk_out <= 0;
end else if (count == m - 1) begin
clk_out <= ~clk_out;
count <= 0;
end else if (count == m / 2 - 1) begin
clk_out <= ~clk_out;
count <= count + 1;
end else count <= count + 1;
end
endmodule
| 6.502182 |
module TMON(
//inputs
RSTN,
ECLK,
TCLK,
//outputs
TSTOP,
TVAL,
);
//inputs
input RSTN;
input ECLK;
input TCLK;
//ouputs
output TSTOP;
output [15:0] TVAL;
//regs
reg TSTOP;
reg [15:0] TVAL;
reg PCLKA;
reg PCLKB;
reg PCLKC;
reg PCLKD;
reg NCLKA;
reg NCLKB;
reg NCLKC;
reg NCLKD;
reg TENBA;
reg TENBB;
//wires
wire TRST;
wire TEN;
//****************************************//
always @(negedge ECLK or negedge RSTN)
begin
if(!RSTN)
NCLKA<=`UDLY 1'b0;
else
NCLKA<=`UDLY ~NCLKA;
end
always @(negedge NCLKA or negedge RSTN)
begin
if(!RSTN)
NCLKB<=`UDLY 1'b0;
else
NCLKB<=`UDLY ~NCLKB;
end
always @(negedge NCLKB or negedge RSTN)
begin
if(!RSTN)
NCLKC<=`UDLY 1'b0;
else
NCLKC<=`UDLY ~NCLKC;
end
always @(negedge NCLKC or negedge RSTN)
begin
if(!RSTN)
NCLKD<=`UDLY 1'b0;
else
NCLKD<=`UDLY ~NCLKD;
end
always @(posedge NCLKD or negedge RSTN)
begin
if(!RSTN)
PCLKA<=`UDLY 1'b0;
else
PCLKA<=`UDLY ~PCLKA;
end
always @(posedge PCLKA or negedge RSTN)
begin
if(!RSTN)
PCLKB<=`UDLY 1'b0;
else
PCLKB<=`UDLY ~PCLKB;
end
always @(posedge PCLKB or negedge RSTN)
begin
if(!RSTN)
PCLKC<=`UDLY 1'b0;
else
PCLKC<=`UDLY ~PCLKC;
end
always @(posedge PCLKC or negedge RSTN)
begin
if(!RSTN)
PCLKD<=`UDLY 1'b0;
else
PCLKD<=`UDLY ~PCLKD;
end
//****************************************//
always @(posedge TCLK or negedge RSTN)
begin
if(!RSTN)
TENBA<=`UDLY 1'b0;
else
TENBA<=`UDLY PCLKD;
end
always @(negedge TCLK or negedge RSTN)
begin
if(!RSTN)
TENBB<=`UDLY 1'b0;
else
TENBB<=`UDLY TENBA;
end
assign TRST=RSTN&~(TENBA&~TENBB);
always @(negedge PCLKD or negedge RSTN)
begin
if(!RSTN)
TSTOP<=`UDLY 1'b0;
else
TSTOP<=`UDLY ~TSTOP;
end
assign TEN=PCLKD;
always @(posedge TCLK or negedge TRST)
begin
if(!TRST)
TVAL<=`UDLY 1'b0;
else if(TEN)
TVAL<=`UDLY TVAL+1'b1;
else
TVAL<=`UDLY TVAL;
end
endmodule
| 7.206186 |
module branching_mechanism(
input [31:0] pc_in,
input [31:0] dest_addr,
input [31:0] reg1,
input [1:0] branch_control_signal,
input [5:0] ins_func_code,
input [2:0] alu_flag,
input rst,
input clk,
output reg [31:0] pc_out,
output reg [31:0] ref
);
/*
name ins_func_code branch_control alu_flag(ZNC) pc_out ref
br 000000 01 xxx reg1 pc_in+1
bltz 000001 01 x1x dest_addr pc_in+1
bz 000010 01 1xx dest_addr pc_in+1
bnz 000011 01 0xx dest_addr pc_in+1
b 000000 10 xxx dest_addr pc_in+1
bcy 000001 10 xx1 dest_addr pc_in+1
bncy 000010 10 xx0 dest_addr pc_in+1
bl 000000 11 xxx dest_addr pc_in+1
none xxxxxx 00 xxx pc_in+1 pc_in+1
*/
reg [2:0] old_flag;
always @(posedge clk) begin
if(rst)
old_flag <= 3'b000;
else
old_flag <= alu_flag;
end
always @(*) begin
ref <= pc_in+32'd1;
if(rst)
pc_out <= 32'd0;
else begin
case(branch_control_signal)
2'b01: begin
case(ins_func_code)
6'b000000: begin
pc_out<=reg1;
end
6'b000001:begin
if(alu_flag[1]==1'b1)
pc_out<=dest_addr;
else
pc_out<=pc_in+32'd1;
end
6'b000010:begin
if(alu_flag[0]==1'b1)
pc_out<=dest_addr;
else
pc_out<=pc_in+32'd1;
end
6'b000011:begin
if(alu_flag[0]==1'b0)
pc_out<=dest_addr;
else
pc_out<=pc_in+32'd1;
end
default: begin
pc_out<=pc_in+32'd1;
end
endcase
end
2'b10: begin
case(ins_func_code)
6'b000000: begin
pc_out<=dest_addr;
end
6'b000001:begin
if(old_flag[2]==1'b1)
pc_out<=dest_addr;
else
pc_out<=pc_in+32'd1;
end
6'b000010:begin
if(old_flag[2]==1'b0)
pc_out<=dest_addr;
else
pc_out<=pc_in+32'd1;
end
default: begin
pc_out<=pc_in+32'd1;
end
endcase
end
2'b11: begin
pc_out<=dest_addr;
end
default: begin
pc_out<=pc_in+32'd1;
end
endcase
end
end
endmodule
| 8.68257 |
module TmpImage_Test_bench ();
reg clk;
wire clkout;
wire [7:0] scaler;
reg rst;
TempImgCreator uut (
.CLK(clk),
.CLKOUT(clkout),
.dataOut(scaler),
.reset(rst)
);
initial begin
clk = 0;
forever begin
#1 clk = ~clk;
end
end
initial begin
$display("Testing data creator");
rst = 1;
#10;
rst = 0;
#1000 $finish;
end
endmodule
| 6.536572 |
module tmp_FakeMouse (
input clk,
input upBtn,
input downBtn,
input leftBtn,
input rightBtn,
output reg [9:0] xPos,
output reg [9:0] yPos
);
initial begin
xPos = 320;
yPos = 240;
end
///////////////////////////////////////////////////////////////
//Flags for the control of the input signals
//Usado para el control del Boton_Up
reg cambio_SolicitadoUp = 0, cambio_RealizadoUp = 0;
wire cambio_FinalizadoUp;
assign cambio_FinalizadoUp = ((cambio_RealizadoUp & cambio_SolicitadoUp) | ((!cambio_RealizadoUp) & (!cambio_SolicitadoUp)));
//Usado para el control del Boton_Down
reg cambio_SolicitadoDown = 0, cambio_RealizadoDown = 0;
wire cambio_FinalizadoDown;
assign cambio_FinalizadoDown = ((cambio_RealizadoDown & cambio_SolicitadoDown) | ((!cambio_RealizadoDown) & (!cambio_SolicitadoDown)));
//Usado para el control del Boton_derecha
reg cambio_SolicitadoRIGHT = 0, cambio_RealizadoRIGHT = 0;
wire cambio_FinalizadoRIGHT;
assign cambio_FinalizadoRIGHT = ((cambio_RealizadoRIGHT & cambio_SolicitadoRIGHT) | ((!cambio_RealizadoRIGHT) & (!cambio_SolicitadoRIGHT)));
//Usado para el control del Boton_Izquierda
reg cambio_SolicitadoLEFT = 0, cambio_RealizadoLEFT = 0;
wire cambio_FinalizadoLEFT;
assign cambio_FinalizadoLEFT = ((cambio_RealizadoLEFT & cambio_SolicitadoLEFT) | ((!cambio_RealizadoLEFT) & (!cambio_SolicitadoLEFT)));
//Logs a request for the use of the buttons
always @(posedge downBtn) cambio_SolicitadoDown = ~cambio_SolicitadoDown;
always @(posedge rightBtn) cambio_SolicitadoRIGHT = ~cambio_SolicitadoRIGHT;
always @(posedge leftBtn) cambio_SolicitadoLEFT = ~cambio_SolicitadoLEFT;
always @(posedge upBtn) cambio_SolicitadoUp = ~cambio_SolicitadoUp;
always @(posedge clk) begin
if (!cambio_FinalizadoUp) begin
yPos = yPos - 35;
if (yPos > 640) yPos = 320;
cambio_RealizadoUp = cambio_SolicitadoUp; //Marque la bandera de que se realiz el cambio
end
if (!cambio_FinalizadoDown) begin
yPos = yPos + 35;
if (yPos > 640) yPos = 320;
cambio_RealizadoDown = cambio_SolicitadoDown; //Marque la bandera de que se realiz el cambio
end
if (!cambio_FinalizadoLEFT) begin
xPos = xPos - 35;
if (xPos > 480) xPos = 240;
cambio_RealizadoLEFT = cambio_SolicitadoLEFT; //Marque la bandera de que se realiz el cambio
end
if (!cambio_FinalizadoRIGHT) begin
xPos = xPos + 35;
if (xPos > 480) xPos = 240;
cambio_RealizadoRIGHT = cambio_SolicitadoRIGHT;//Marque la bandera de que se realiz el cambio
end
end
endmodule
| 6.997715 |
module mealyFSM (
output reg o_d,
input i_d,
input clk,
input reset_n
);
parameter IDLE = 2'b00;
parameter S0 = 2'b01;
// inner state/next_state
reg [1:0] state, next_state;
reg o_d_next;
//state
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
//output
always @(*) begin
o_d_next = 1'b0;
case (state)
IDLE: begin
if (i_d == 1'b1) begin
o_d_next = 1'b1;
end
end
endcase
end
//next_state
always @(*) begin
next_state = IDLE;
case (state)
IDLE: begin
if (i_d == 1'b1) begin
next_state = S0;
end
end
S0: begin
if (i_d == 1'b1) begin
next_state = S0;
end
end
endcase
end
// D-FF stores output
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
o_d <= 1'b0;
end else begin
o_d <= o_d_next;
end
end
endmodule
| 9.012849 |
module timer_controller #(
parameter DIV = `TMR_DIV // 0<DIV<=65536
) (
input wire clk,
input wire rstn, // sync
output wire interrupt,
// user interface
input wire [$clog2(`TMR_SIZE)-1:0] addr,
input wire w_rb,
input wire [ `BUS_ACC_WIDTH-1:0] acc,
output reg [ `BUS_WIDTH-1:0] rdata,
input wire [ `BUS_WIDTH-1:0] wdata,
input wire req,
output reg resp,
output wire fault
);
/*
* Register map
* Name | Address | Size | Access | Note
* TR | 0 | 4 | R/W | -
* INTCSR | 4 | 4 | R/W | -
*
* INTCSR
* (31:8) | INTEN(7) | (6:0)
*/
// fault generation
wire invld_addr = (addr[1:0] != 0);
wire invld_acc = (acc != `BUS_ACC_4B);
wire invld_wr = 0;
wire invld = |{invld_addr, invld_acc, invld_wr};
assign fault = req & invld;
// resp generation
always @(posedge clk) begin
if (~rstn) begin
resp <= 0;
end else begin
resp <= req & ~invld;
end
end
// register operation
reg [31:0] tr;
reg inten;
always @(posedge clk) if (req & ~invld & ~w_rb) rdata <= addr[2] ? {24'd0, inten, 7'd0} : tr;
reg [15:0] div;
always @(posedge clk) begin
if (~rstn) div <= 0;
else if (req & ~invld & w_rb) div <= DIV - 1;
else if (tr) begin
if (div == 0) div <= DIV - 1;
else div <= div - 1;
end
/* // Resetting div is unnecessary but keep the code
else
div <= 0;
*/
end
always @(posedge clk) begin
if (~rstn) begin
tr <= 0;
inten <= 1'b0;
end else if (req & ~invld & w_rb) begin
if (addr[2]) inten <= wdata[7];
else tr <= wdata;
end else if (tr && !div) begin
tr <= tr - 1;
end
end
assign interrupt = inten && (tr == 1) && (div == 0);
endmodule
| 6.879247 |
module timer0_tb;
//---------------------------------------------------------------------------//
//--------------------Constant Parameter-------------------------------------//
//---------------------------------------------------------------------------//
localparam integer PERIOD = 50; // 20 MHz clock frequency
//---------------------------------------------------------------------------//
//--------------------Testbench Connections----------------------------------//
//---------------------------------------------------------------------------//
reg clock; // Clock Input
reg reset; // Synchronous Reset Input
reg int0;
reg tmod_gate_t0;
reg tmod_m0t0;
reg tmod_m1t0;
reg tcon_tr0;
reg [7:0] th0_i;
reg [7:0] tm0_i;
reg [7:0] tl0_i;
wire tcon_tf0;
wire [7:0] th0_o; // Timer 0 Counter Registers
wire [7:0] tm0_o;
wire [7:0] tl0_o;
reg int1;
reg tmod_gate_t1;
reg tmod_m0t1;
reg tmod_m1t1;
reg tcon_tr1;
reg [7:0] th1_i;
reg [7:0] tm1_i;
reg [7:0] tl1_i;
wire tcon_tf1;
wire [7:0] th1_o; // Timer 0 Counter Registers
wire [7:0] tm1_o;
wire [7:0] tl1_o;
//---------------------------------------------------------------------------//
//--------------------Module Instance----------------------------------------//
//---------------------------------------------------------------------------//
top_timers UUT (
.top_timers_machine_cycle_i (clock),
.top_timers_reset_i (reset),
// /*
.top_timers_int0_i (int0),
.top_timers_sfr_tmod_gate_t0_i(tmod_gate_t0),
.top_timers_sfr_tmod_m0_t0_i (tmod_m0t0),
.top_timers_sfr_tmod_m1_t0_i (tmod_m1t0),
.top_timers_sfr_tcon_tr0_i (tcon_tr0),
.top_timers_sfr_th0_i (th0_i),
.top_timers_sfr_tm0_i (tm0_i),
.top_timers_sfr_tl0_i (tl0_i),
.top_timers_sfr_tcon_tf0_i (tcon_tf0_i),
.top_timers_sfr_tcon_tf0_o (tcon_tf0_o),
.top_timers_sfr_th0_o (th0_o),
.top_timers_sfr_tm0_o (tm0_o),
.top_timers_sfr_tl0_o (tl0_o)
// */
/*
.top_timers_int1_i (int0) ,
.top_timers_sfr_tmod_gate_t1_i (tmod_gate_t0) ,
.top_timers_sfr_tmod_m0_t1_i (tmod_m0t0) ,
.top_timers_sfr_tmod_m1_t1_i (tmod_m1t0) ,
.top_timers_sfr_tcon_tr1_i (tcon_tr0) ,
.top_timers_sfr_th1_i (th0_i) ,
.top_timers_sfr_tm1_i (tm0_i) ,
.top_timers_sfr_tl1_i (tl0_i) ,
.top_timers_sfr_tcon_tf1_i (tcon_tf0_i) ,
.top_timers_sfr_tcon_tf1_o (tcon_tf0_o) ,
.top_timers_sfr_th1_o (th0_o) ,
.top_timers_sfr_tm1_o (tm0_o) ,
.top_timers_sfr_tl1_o (tl0_o)
*/
);
//---------------------------------------------------------------------------//
//--------------------Clock Generation---------------------------------------//
//---------------------------------------------------------------------------//
always begin
clock <= 1;
#(PERIOD / 2);
clock <= 0;
#(PERIOD / 2);
end
endmodule
| 6.856016 |
module timer0_tb;
//---------------------------------------------------------------------------//
//--------------------Constant Parameter-------------------------------------//
//---------------------------------------------------------------------------//
localparam integer PERIOD = 50; // 20 MHz clock frequency
//---------------------------------------------------------------------------//
//--------------------Testbench Connections----------------------------------//
//---------------------------------------------------------------------------//
reg clock; // Clock Input
reg reset; // Synchronous Reset Input
reg int0;
reg tmod_gate_t0;
reg tmod_m0t0;
reg tmod_m1t0;
reg tcon_tr0;
reg [7:0] th0_i;
reg [7:0] tm0_i;
reg [7:0] tl0_i;
wire tcon_tf0;
wire [7:0] th0_o; // Timer 0 Counter Registers
wire [7:0] tm0_o;
wire [7:0] tl0_o;
reg int1;
reg tmod_gate_t1;
reg tmod_m0t1;
reg tmod_m1t1;
reg tcon_tr1;
reg [7:0] th1_i;
reg [7:0] tm1_i;
reg [7:0] tl1_i;
wire tcon_tf1;
wire [7:0] th1_o; // Timer 0 Counter Registers
wire [7:0] tm1_o;
wire [7:0] tl1_o;
//---------------------------------------------------------------------------//
//--------------------Module Instance----------------------------------------//
//---------------------------------------------------------------------------//
top_timers UUT (
.top_timers_machine_cycle_i (clock),
.top_timers_reset_i (reset),
/*
.top_timers_int0_i (int0) ,
.top_timers_sfr_tmod_gate_t0_i (tmod_gate_t0) ,
.top_timers_sfr_tmod_m0_t0_i (tmod_m0t0) ,
.top_timers_sfr_tmod_m1_t0_i (tmod_m1t0) ,
.top_timers_sfr_tcon_tr0_i (tcon_tr0) ,
.top_timers_sfr_th0_i (th0_i) ,
.top_timers_sfr_tm0_i (tm0_i) ,
.top_timers_sfr_tl0_i (tl0_i) ,
.top_timers_sfr_tcon_tf0_i (tcon_tf0_i) ,
.top_timers_sfr_tcon_tf0_o (tcon_tf0_o) ,
.top_timers_sfr_th0_o (th0_o) ,
.top_timers_sfr_tm0_o (tm0_o) ,
.top_timers_sfr_tl0_o (tl0_o)
*/
// /*
.top_timers_int1_i (int0),
.top_timers_sfr_tmod_gate_t1_i(tmod_gate_t0),
.top_timers_sfr_tmod_m0_t1_i (tmod_m0t0),
.top_timers_sfr_tmod_m1_t1_i (tmod_m1t0),
.top_timers_sfr_tcon_tr1_i (tcon_tr0),
.top_timers_sfr_th1_i (th0_i),
.top_timers_sfr_tm1_i (tm0_i),
.top_timers_sfr_tl1_i (tl0_i),
.top_timers_sfr_tcon_tf1_i (tcon_tf0_i),
.top_timers_sfr_tcon_tf1_o (tcon_tf0_o),
.top_timers_sfr_th1_o (th0_o),
.top_timers_sfr_tm1_o (tm0_o),
.top_timers_sfr_tl1_o (tl0_o)
//*/
);
//---------------------------------------------------------------------------//
//--------------------Clock Generation---------------------------------------//
//---------------------------------------------------------------------------//
always begin
clock <= 1;
#(PERIOD / 2);
clock <= 0;
#(PERIOD / 2);
end
endmodule
| 6.856016 |
module TMR32_tb;
reg clk;
reg rst_n;
wire [31:0] TMR;
wire [31:0] CAPTURE;
reg [15:0] PRE;
reg [31:0] CMP;
reg [31:0] LOAD;
wire OVF;
wire CMPF;
wire EEVF; // Trigger event flag for Capture mode.
reg OVF_CLR;
reg CMPF_CLR;
reg EEVF_CLR;
reg EN;
reg MODE; // Perioid or One-shot
reg UD; // Up or Down
reg TC; // Timer or Counter
reg CP; // Enable Capture Mode
reg PNE; // Posedge or Negede - Counter/Capture
reg BE; // Both Edges
reg PWMEN;
reg EXTPIN;
wire PWMPIN;
TMR32 MUV (
.clk (clk),
.rst_n (rst_n),
.TMR (TMR),
.CAPTURE (CAPTURE),
.PRE (PRE),
.CMP (CMP),
.LOAD (LOAD),
.OVF (OVF),
.CMPF (CMPF),
.EEVF (EEVF), // Trigger event flag for Capture mode.
.OVF_CLR (),
.CMPF_CLR(),
.EEVF_CLR(),
.EN (EN),
.MODE (MODE), // Perioid or One-shot
.UD (UD), // Up or Down
.TC (TC), // Timer/Counter
.CP (CP), // Enable Capture Mode
.PNE (PNE), // Posedge or Negede - Counter/Capture
.BE (BE), // Both Edges
.PWMEN (PWMEN),
.EXTPIN (EXTPIN),
.PWMPIN (PWMPIN)
);
initial begin
$dumpfile("tmr.vcd");
$dumpvars(0, MUV);
end
initial begin
clk = 0;
rst_n = 0;
PRE = 3;
CMP = 5;
LOAD = 10;
OVF_CLR = 0;
CMPF_CLR = 0;
EEVF_CLR = 0;
EN = 0;
MODE = 1; // Perioid or One-shot
UD = 0; // Up or Down
TC = 1; // Timer / Counter
CP = 0; // Enable Capture Mode
PNE = 0; // Posedge or Negede - Counter/Capture
BE = 0; // Both Edges
EXTPIN = 0;
PWMEN = 0;
#10_000 $finish;
end
always #5 clk = !clk;
always #157 EXTPIN = ~EXTPIN;
initial begin
#342;
@(posedge clk);
rst_n = 1;
#333;
@(posedge clk);
EN = 1;
#1111;
@(posedge clk);
UD = 1;
#321;
@(posedge clk);
EN = 0;
#611;
@(posedge clk);
EN = 1;
#199;
@(posedge clk);
EN = 0;
#333;
@(posedge clk);
TC = 0;
EN = 1;
#977;
@(posedge clk);
EN = 0;
CP = 1;
#100;
@(posedge clk);
EN = 1;
#555;
@(posedge clk);
CP = 0;
EN = 0;
TC = 1;
PWMEN = 1;
#777;
@(posedge clk);
EN = 1;
#1500;
@(posedge clk);
EN = 0;
CMP = 3;
#111;
@(posedge clk);
EN = 1;
end
endmodule
| 6.777026 |
module tmr_wrapper (
input wire clk,
input wire rstn,
input wire [ `XLEN-1:0] p_addr, // byte addr
input wire p_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] p_acc,
output wire [ `BUS_WIDTH-1:0] p_rdata,
input wire [ `BUS_WIDTH-1:0] p_wdata,
input wire p_req,
output wire p_resp,
output wire tmr_fault,
output wire interrupt
);
timer_controller timer_controller (
.clk (clk),
.rstn(rstn),
.interrupt(interrupt),
.addr (p_addr[$clog2(`TMR_SIZE)-1:0]),
.w_rb (p_w_rb),
.acc (p_acc),
.wdata(p_wdata),
.rdata(p_rdata),
.req (p_req),
.resp (p_resp),
.fault(tmr_fault)
);
endmodule
| 7.586999 |
module tmu2_adrgen #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [10:0] dx_c,
input [10:0] dy_c,
input [16:0] tx_c,
input [16:0] ty_c,
input [fml_depth-1-1:0] dst_fbuf, /* in 16-bit words */
input [10:0] dst_hres,
input [fml_depth-1-1:0] tex_fbuf, /* in 16-bit words */
input [10:0] tex_hres,
output pipe_stb_o,
input pipe_ack_i,
output [fml_depth-1-1:0] dadr, /* in 16-bit words */
output [fml_depth-1-1:0] tadra,
output [fml_depth-1-1:0] tadrb,
output [fml_depth-1-1:0] tadrc,
output [fml_depth-1-1:0] tadrd,
output [5:0] x_frac,
output [5:0] y_frac
);
/* Arithmetic pipeline. Enable signal is shared to ease usage of hard macros. */
wire pipe_en;
reg valid_1;
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] tadra_1;
reg [5:0] x_frac_1;
reg [5:0] y_frac_1;
reg valid_2;
reg [fml_depth-1-1:0] dadr_2;
reg [fml_depth-1-1:0] tadra_2;
reg [5:0] x_frac_2;
reg [5:0] y_frac_2;
reg valid_3;
reg [fml_depth-1-1:0] dadr_3;
reg [fml_depth-1-1:0] tadra_3;
reg [fml_depth-1-1:0] tadrb_3;
reg [fml_depth-1-1:0] tadrc_3;
reg [fml_depth-1-1:0] tadrd_3;
reg [5:0] x_frac_3;
reg [5:0] y_frac_3;
always @(posedge sys_clk) begin
if (sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
end else if (pipe_en) begin
valid_1 <= pipe_stb_i;
dadr_1 <= dst_fbuf + dst_hres * dy_c + dx_c;
tadra_1 <= tex_fbuf + tex_hres * ty_c[16:6] + tx_c[16:6];
x_frac_1 <= tx_c[5:0];
y_frac_1 <= ty_c[5:0];
valid_2 <= valid_1;
dadr_2 <= dadr_1;
tadra_2 <= tadra_1;
x_frac_2 <= x_frac_1;
y_frac_2 <= y_frac_1;
valid_3 <= valid_2;
dadr_3 <= dadr_2;
tadra_3 <= tadra_2;
tadrb_3 <= tadra_2 + 1'd1;
tadrc_3 <= tadra_2 + tex_hres;
tadrd_3 <= tadra_2 + tex_hres + 1'd1;
x_frac_3 <= x_frac_2;
y_frac_3 <= y_frac_2;
end
end
/* Glue logic */
assign pipe_stb_o = valid_3;
assign dadr = dadr_3;
assign tadra = tadra_3;
assign tadrb = tadrb_3;
assign tadrc = tadrc_3;
assign tadrd = tadrd_3;
assign x_frac = x_frac_3;
assign y_frac = y_frac_3;
assign pipe_en = ~valid_3 | pipe_ack_i;
assign pipe_ack_o = ~valid_3 | pipe_ack_i;
assign busy = valid_1 | valid_2 | valid_3;
endmodule
| 7.249982 |
module tmu2_alpha #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input [5:0] alpha,
input additive,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [15:0] dcolor,
output pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-1-1:0] dadr_f,
output [15:0] acolor
);
wire en;
reg valid_1;
reg valid_2;
reg valid_3;
reg valid_4;
always @(posedge sys_clk) begin
if (sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
valid_3 <= 1'b0;
valid_4 <= 1'b0;
end else if (en) begin
valid_1 <= pipe_stb_i;
valid_2 <= valid_1;
valid_3 <= valid_2;
valid_4 <= valid_3;
end
end
/* Pipeline operation on four stages. */
reg [fml_depth-1-1:0] dadr_1;
reg [fml_depth-1-1:0] dadr_2;
reg [fml_depth-1-1:0] dadr_3;
wire [4:0] r = color[15:11];
wire [5:0] g = color[10:5];
wire [4:0] b = color[4:0];
wire [4:0] dr = dcolor[15:11];
wire [5:0] dg = dcolor[10:5];
wire [4:0] db = dcolor[4:0];
reg [10:0] r_1;
reg [11:0] g_1;
reg [10:0] b_1;
reg [10:0] dr_1;
reg [11:0] dg_1;
reg [10:0] db_1;
reg [10:0] r_2;
reg [11:0] g_2;
reg [10:0] b_2;
reg [10:0] dr_2;
reg [11:0] dg_2;
reg [10:0] db_2;
reg [11:0] r_3;
reg [12:0] g_3;
reg [11:0] b_3;
reg [5:0] r_4;
reg [6:0] g_4;
reg [5:0] b_4;
always @(posedge sys_clk) begin
if (en) begin
dadr_1 <= dadr;
dadr_2 <= dadr_1;
dadr_3 <= dadr_2;
dadr_f <= dadr_3;
r_1 <= ({1'b0, alpha} + 7'd1) * r;
g_1 <= ({1'b0, alpha} + 7'd1) * g;
b_1 <= ({1'b0, alpha} + 7'd1) * b;
dr_1 <= (additive ? 7'd64 : (7'd63 - alpha)) * dr;
dg_1 <= (additive ? 7'd64 : (7'd63 - alpha)) * dg;
db_1 <= (additive ? 7'd64 : (7'd63 - alpha)) * db;
r_2 <= r_1;
g_2 <= g_1;
b_2 <= b_1;
dr_2 <= dr_1;
dg_2 <= dg_1;
db_2 <= db_1;
r_3 <= r_2 + dr_2;
g_3 <= g_2 + dg_2;
b_3 <= b_2 + db_2;
r_4 <= r_3[11:6] + (r_3[5] & (|r_3[4:0] | r_3[6]));
g_4 <= g_3[12:6] + (g_3[5] & (|g_3[4:0] | g_3[6]));
b_4 <= b_3[11:6] + (b_3[5] & (|b_3[4:0] | b_3[6]));
end
end
assign acolor = {{5{r_4[5]}} | r_4[4:0], {6{g_4[6]}} | g_4[5:0], {5{b_4[5]}} | b_4[4:0]};
/* Pipeline management */
assign busy = valid_1 | valid_2 | valid_3 | valid_4;
assign pipe_ack_o = ~valid_4 | pipe_ack_i;
assign en = ~valid_4 | pipe_ack_i;
assign pipe_stb_o = valid_4;
endmodule
| 7.513079 |
module tmu2_buffer #(
parameter width = 8,
parameter depth = 1 /* < log2 of the storage size, in words */
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [width-1:0] dat_i,
output pipe_stb_o,
input pipe_ack_i,
output [width-1:0] dat_o
);
reg [width-1:0] storage[0:(1 << depth)-1];
reg [depth-1:0] produce;
reg [depth-1:0] consume;
reg [depth:0] level;
wire inc = pipe_stb_i & pipe_ack_o;
wire dec = pipe_stb_o & pipe_ack_i;
always @(posedge sys_clk) begin
if (sys_rst) begin
produce <= 0;
consume <= 0;
end else begin
if (inc) produce <= produce + 1;
if (dec) consume <= consume + 1;
end
end
always @(posedge sys_clk) begin
if (sys_rst) level <= 0;
else begin
case ({
inc, dec
})
2'b10: level <= level + 1;
2'b01: level <= level - 1;
default: ;
endcase
end
end
always @(posedge sys_clk) begin
if (inc) storage[produce] <= dat_i;
end
assign dat_o = storage[consume];
assign busy = |level;
assign pipe_ack_o = ~level[depth];
assign pipe_stb_o = |level;
endmodule
| 8.264058 |
module tmu2_burst #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
input flush,
output reg busy,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output reg pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-5-1:0] burst_addr, /* in 256-bit words */
/* 16-bit granularity selection that needs to be expanded
* to 8-bit granularity selection to drive the FML lines.
*/
output reg [15:0] burst_sel,
output reg [255:0] burst_do
);
wire burst_hit = dadr[fml_depth-1-1:4] == burst_addr;
/* Always memorize input in case we have to ack a cycle we cannot immediately handle */
reg [15:0] color_r;
reg [fml_depth-1-1:0] dadr_r;
always @(posedge sys_clk) begin
if (pipe_stb_i & pipe_ack_o) begin
color_r <= color;
dadr_r <= dadr;
end
end
/* Write to the burst storage registers */
reg clear_en;
reg write_en;
reg use_memorized;
wire [15:0] color_mux = use_memorized ? color_r : color;
wire [fml_depth-1-1:0] dadr_mux = use_memorized ? dadr_r : dadr;
always @(posedge sys_clk) begin
if (sys_rst) burst_sel = 16'd0;
else begin
if (clear_en) burst_sel = 16'd0;
if (write_en) begin
burst_addr = dadr_mux[fml_depth-1-1:4]; /* update tag */
case (dadr_mux[3:0]) /* unmask */
4'd00: burst_sel = burst_sel | 16'h8000;
4'd01: burst_sel = burst_sel | 16'h4000;
4'd02: burst_sel = burst_sel | 16'h2000;
4'd03: burst_sel = burst_sel | 16'h1000;
4'd04: burst_sel = burst_sel | 16'h0800;
4'd05: burst_sel = burst_sel | 16'h0400;
4'd06: burst_sel = burst_sel | 16'h0200;
4'd07: burst_sel = burst_sel | 16'h0100;
4'd08: burst_sel = burst_sel | 16'h0080;
4'd09: burst_sel = burst_sel | 16'h0040;
4'd10: burst_sel = burst_sel | 16'h0020;
4'd11: burst_sel = burst_sel | 16'h0010;
4'd12: burst_sel = burst_sel | 16'h0008;
4'd13: burst_sel = burst_sel | 16'h0004;
4'd14: burst_sel = burst_sel | 16'h0002;
4'd15: burst_sel = burst_sel | 16'h0001;
endcase
case (dadr_mux[3:0]) /* register data */
4'd00: burst_do[255:240] = color_mux;
4'd01: burst_do[239:224] = color_mux;
4'd02: burst_do[223:208] = color_mux;
4'd03: burst_do[207:192] = color_mux;
4'd04: burst_do[191:176] = color_mux;
4'd05: burst_do[175:160] = color_mux;
4'd06: burst_do[159:144] = color_mux;
4'd07: burst_do[143:128] = color_mux;
4'd08: burst_do[127:112] = color_mux;
4'd09: burst_do[111:96] = color_mux;
4'd10: burst_do[95:80] = color_mux;
4'd11: burst_do[79:64] = color_mux;
4'd12: burst_do[63:48] = color_mux;
4'd13: burst_do[47:32] = color_mux;
4'd14: burst_do[31:16] = color_mux;
4'd15: burst_do[15:0] = color_mux;
endcase
end
end
end
wire empty = (burst_sel == 16'd0);
reg state;
reg next_state;
parameter RUNNING = 1'b0;
parameter DOWNSTREAM = 1'b1;
always @(posedge sys_clk) begin
if (sys_rst) state <= RUNNING;
else state <= next_state;
end
/*
* generate pipe_ack_o using an assign statement to work around a bug in CVER
*/
assign pipe_ack_o = (state == RUNNING) & (~flush | empty);
always @(*) begin
next_state = state;
busy = 1'b1;
// CVER WA (see above) pipe_ack_o = 1'b0;
pipe_stb_o = 1'b0;
write_en = 1'b0;
clear_en = 1'b0;
use_memorized = 1'b0;
case (state)
RUNNING: begin
busy = 1'b0;
if (flush & ~empty) next_state = DOWNSTREAM;
else begin
// CVER WA (see above) pipe_ack_o = 1'b1;
if (pipe_stb_i) begin
if (burst_hit | empty) write_en = 1'b1;
else next_state = DOWNSTREAM;
end
end
end
DOWNSTREAM: begin
pipe_stb_o = 1'b1;
use_memorized = 1'b1;
if (pipe_ack_i) begin
clear_en = 1'b1;
write_en = 1'b1;
next_state = RUNNING;
end
end
endcase
end
endmodule
| 7.408583 |
module tmu2_clamp (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [10:0] tex_hres,
input [10:0] tex_vres,
input [10:0] dst_hres,
input [10:0] dst_vres,
output reg pipe_stb_o,
input pipe_ack_i,
output reg [10:0] dx_c,
output reg [10:0] dy_c,
output reg [16:0] tx_c,
output reg [16:0] ty_c
);
always @(posedge sys_clk) begin
if (sys_rst) pipe_stb_o <= 1'b0;
else begin
if (pipe_ack_i) pipe_stb_o <= 1'b0;
if (pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= (~dx[11]) && (dx[10:0] < dst_hres) && (~dy[11]) && (dy[10:0] < dst_vres);
dx_c <= dx[10:0];
dy_c <= dy[10:0];
if (tx[17]) tx_c <= 17'd0;
else if (tx[16:0] > {tex_hres - 11'd1, 6'd0}) tx_c <= {tex_hres - 11'd1, 6'd0};
else tx_c <= tx[16:0];
if (ty[17]) ty_c <= 17'd0;
else if (ty[16:0] > {tex_vres - 11'd1, 6'd0}) ty_c <= {tex_vres - 11'd1, 6'd0};
else ty_c <= ty[16:0];
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
| 8.12267 |
module tmu2_decay #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input [5:0] brightness,
input chroma_key_en,
input [15:0] chroma_key,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr,
output pipe_stb_o,
input pipe_ack_i,
output [15:0] color_d,
output reg [fml_depth-1-1:0] dadr_f
);
wire en;
reg valid_1;
reg valid_2;
always @(posedge sys_clk) begin
if (sys_rst) begin
valid_1 <= 1'b0;
valid_2 <= 1'b0;
end else if (en) begin
valid_1 <= pipe_stb_i & ((color != chroma_key) | ~chroma_key_en);
valid_2 <= valid_1;
end
end
/* Pipeline operation on two stages. */
reg [fml_depth-1-1:0] dadr_1;
wire [4:0] r = color[15:11];
wire [5:0] g = color[10:5];
wire [4:0] b = color[4:0];
reg [10:0] r_1;
reg [11:0] g_1;
reg [10:0] b_1;
reg [10:0] r_2;
reg [11:0] g_2;
reg [10:0] b_2;
always @(posedge sys_clk) begin
if (en) begin
dadr_1 <= dadr;
dadr_f <= dadr_1;
r_1 <= ({1'b0, brightness} + 7'd1) * r;
g_1 <= ({1'b0, brightness} + 7'd1) * g;
b_1 <= ({1'b0, brightness} + 7'd1) * b;
r_2 <= r_1;
g_2 <= g_1;
b_2 <= b_1;
end
end
assign color_d = {r_2[10:6], g_2[11:6], b_2[10:6]};
/* Pipeline management */
assign busy = valid_1 | valid_2;
assign pipe_ack_o = ~valid_2 | pipe_ack_i;
assign en = ~valid_2 | pipe_ack_i;
assign pipe_stb_o = valid_2;
endmodule
| 7.460965 |
module tmu2_divider17 (
input sys_clk,
input sys_rst,
input start,
input [16:0] dividend,
input [16:0] divisor,
output ready,
output [16:0] quotient,
output [16:0] remainder
);
reg [33:0] qr;
assign remainder = qr[33:17];
assign quotient = qr[16:0];
reg [4:0] counter;
assign ready = (counter == 5'd0);
reg [16:0] divisor_r;
wire [17:0] diff = qr[33:16] - {1'b0, divisor_r};
always @(posedge sys_clk) begin
if (sys_rst) counter = 5'd0;
else begin
if (start) begin
counter = 5'd17;
qr = {17'd0, dividend};
divisor_r = divisor;
end else begin
if (~ready) begin
if (diff[17]) qr = {qr[32:0], 1'b0};
else qr = {diff[16:0], qr[15:0], 1'b1};
counter = counter - 5'd1;
end
end
end
end
endmodule
| 6.992145 |
module tmu2_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32
) (
input sys_clk,
input [depth-1:0] ra,
input re,
output [width-1:0] rd,
input [depth-1:0] wa,
input we,
input [width-1:0] wd
);
reg [width-1:0] ram [0:(1 << depth)-1];
reg [depth-1:0] rar;
always @(posedge sys_clk) begin
if (re) rar <= ra;
if (we) ram[wa] <= wd;
end
assign rd = ram[rar];
// synthesis translate_off
integer i;
initial begin
for (i = 0; i < (1 << depth); i = i + 1) ram[i] = 0;
end
// synthesis translate_on
endmodule
| 6.711363 |
module tmu2_fdest #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input fetch_en,
input pipe_stb_i,
output reg pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output pipe_stb_o,
input pipe_ack_i,
output reg [15:0] color_f,
output [fml_depth-1-1:0] dadr_f, /* in 16-bit words */
output reg [15:0] dcolor
);
/* Hit detection */
reg valid;
reg [fml_depth-1-1-4:0] tag;
reg [fml_depth-1-1:0] dadr_r;
reg hit;
reg tag_we;
always @(posedge sys_clk) begin
if (sys_rst) begin
valid <= 1'b0;
hit <= 1'b0;
dadr_r <= {fml_depth - 1{1'b0}};
end else begin
if (tag_we) valid <= 1'b1;
if (flush) valid <= 1'b0;
if (pipe_stb_i & pipe_ack_o) begin
hit <= valid & (tag == dadr[fml_depth-1-1:4]);
dadr_r <= dadr;
end
end
end
always @(posedge sys_clk) begin
if (sys_rst) tag <= {fml_depth - 1 - 4{1'b0}};
else if (tag_we) tag <= dadr_r[fml_depth-1-1:4];
end
/* Forward */
always @(posedge sys_clk) begin
if (sys_rst) color_f <= 16'd0;
else if (pipe_stb_i & pipe_ack_o) color_f <= color;
end
assign dadr_f = dadr_r;
/* Storage */
reg [63:0] storage[0:3];
// synthesis translate_off
initial begin
storage[0] = 64'd0;
storage[1] = 64'd0;
storage[2] = 64'd0;
storage[3] = 64'd0;
end
// synthesis translate_on
wire [63:0] storage_do = storage[dadr_r[3:2]];
always @(*) begin
case (dadr_r[1:0])
2'd0: dcolor = storage_do[63:48];
2'd1: dcolor = storage_do[47:32];
2'd2: dcolor = storage_do[31:16];
2'd3: dcolor = storage_do[15:0];
endcase
end
reg [1:0] storage_wa;
reg storage_we;
always @(posedge sys_clk) begin
if (storage_we) storage[storage_wa] = fml_di;
end
/* Control & bus master */
assign fml_adr = {dadr_r[fml_depth-1-1:4], 5'd0};
reg wanted;
always @(posedge sys_clk) begin
if (sys_rst) wanted <= 1'b0;
else if (pipe_ack_o) wanted <= pipe_stb_i;
end
reg stb_after_fetch;
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter FETCH1 = 3'd1;
parameter FETCH2 = 3'd2;
parameter FETCH3 = 3'd3;
parameter FETCH4 = 3'd4;
parameter OUT = 3'd5;
always @(posedge sys_clk) begin
if (sys_rst) state <= IDLE;
else state <= next_state;
end
always @(*) begin
next_state = state;
tag_we = 1'b0;
storage_we = 1'b0;
storage_wa = 2'bx;
fml_stb = 1'b0;
pipe_ack_o = 1'b0;
stb_after_fetch = 1'b0;
case (state)
IDLE: begin
pipe_ack_o = pipe_ack_i | ~wanted;
if (wanted & ~hit & fetch_en) begin
pipe_ack_o = 1'b0;
next_state = FETCH1;
end
end
FETCH1: begin
fml_stb = 1'b1;
storage_we = 1'b1;
storage_wa = 2'd0;
if (fml_ack) next_state = FETCH2;
end
FETCH2: begin
storage_we = 1'b1;
storage_wa = 2'd1;
next_state = FETCH3;
end
FETCH3: begin
storage_we = 1'b1;
storage_wa = 2'd2;
next_state = FETCH4;
end
FETCH4: begin
storage_we = 1'b1;
storage_wa = 2'd3;
tag_we = 1'b1;
next_state = OUT;
end
OUT: begin
stb_after_fetch = 1'b1;
pipe_ack_o = pipe_ack_i;
if (pipe_ack_i) next_state = IDLE;
end
endcase
end
assign pipe_stb_o = stb_after_fetch | (wanted & (hit | ~fetch_en));
assign busy = wanted;
endmodule
| 7.72567 |
module tmu2_fetchtexel #(
parameter depth = 2,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-5-1:0] fetch_adr,
output pipe_stb_o,
input pipe_ack_i,
output [255:0] fetch_dat,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di
);
/* Generate FML requests */
wire fetch_en;
always @(posedge sys_clk) begin
if (sys_rst) fml_stb <= 1'b0;
else begin
if (fml_ack) fml_stb <= 1'b0;
if (pipe_ack_o) begin
fml_stb <= pipe_stb_i;
fml_adr <= {fetch_adr, 5'd0};
end
end
end
assign pipe_ack_o = fetch_en & (~fml_stb | fml_ack);
/* Gather received data */
wire fifo_we;
tmu2_fifo64to256 #(
.depth(depth)
) fifo64to256 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.w8avail(fetch_en),
.we(fifo_we),
.wd(fml_di),
.ravail(pipe_stb_o),
.re(pipe_ack_i),
.rd(fetch_dat)
);
reg [1:0] bcount;
assign fifo_we = fml_ack | (|bcount);
always @(posedge sys_clk) begin
if (sys_rst) bcount <= 2'd0;
else if (fml_ack) bcount <= 2'd3;
else if (|bcount) bcount <= bcount - 2'd1;
end
assign busy = pipe_stb_o | fml_stb | fifo_we;
endmodule
| 7.942828 |
module tmu2_fifo64to256 #(
parameter depth = 2 /* < log2 of the capacity, in 256-bit words */
) (
input sys_clk,
input sys_rst,
output w8avail,
input we,
input [63:0] wd,
output ravail,
input re,
output [255:0] rd
);
reg [63:0] storage1[0:(1 << depth)-1];
reg [63:0] storage2[0:(1 << depth)-1];
reg [63:0] storage3[0:(1 << depth)-1];
reg [63:0] storage4[0:(1 << depth)-1];
reg [depth+2:0] level;
reg [depth+1:0] produce;
reg [depth-1:0] consume;
wire wavail = ~level[depth+2];
assign w8avail = level < ((1 << (depth + 2)) - 8);
assign ravail = |(level[depth+2:2]);
wire read = re & ravail;
wire write = we & wavail;
always @(posedge sys_clk) begin
if (sys_rst) begin
level <= 0;
produce <= 0;
consume <= 0;
end else begin
if (read) consume <= consume + 1;
if (write) begin
produce <= produce + 1;
case (produce[1:0])
2'd0: storage1[produce[depth+1:2]] <= wd;
2'd1: storage2[produce[depth+1:2]] <= wd;
2'd2: storage3[produce[depth+1:2]] <= wd;
2'd3: storage4[produce[depth+1:2]] <= wd;
endcase
end
case ({
read, write
})
2'b10: level <= level - 4;
2'b01: level <= level + 1;
2'b11: level <= level - 3;
endcase
end
end
assign rd = {storage1[consume], storage2[consume], storage3[consume], storage4[consume]};
endmodule
| 7.024547 |
module tmu2_hdiv (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x,
input diff_y_positive,
input [16:0] diff_y,
input [10:0] dst_squarew,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x_f,
output reg signed [11:0] y_f,
output reg signed [17:0] tsx_f,
output reg signed [17:0] tsy_f,
output reg diff_x_positive_f,
output [16:0] diff_x_q,
output [16:0] diff_x_r,
output reg diff_y_positive_f,
output [16:0] diff_y_q,
output [16:0] diff_y_r
);
/* Divider bank */
reg start;
wire ready;
tmu2_divider17 d_x (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_x),
.divisor({6'd0, dst_squarew}),
.ready(ready),
.quotient(diff_x_q),
.remainder(diff_x_r)
);
tmu2_divider17 d_y (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_y),
.divisor({6'd0, dst_squarew}),
.ready(),
.quotient(diff_y_q),
.remainder(diff_y_r)
);
/* Forward */
always @(posedge sys_clk) begin
if (start) begin
x_f <= x;
y_f <= y;
tsx_f <= tsx;
tsy_f <= tsy;
diff_x_positive_f <= diff_x_positive;
diff_y_positive_f <= diff_y_positive;
end
end
/* Glue logic */
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter WAIT = 1'b1;
always @(posedge sys_clk) begin
if (sys_rst) state = IDLE;
else state = next_state;
end
assign busy = state;
always @(*) begin
next_state = state;
start = 1'b0;
pipe_stb_o = 1'b0;
pipe_ack_o = 1'b0;
case (state)
IDLE: begin
pipe_ack_o = 1'b1;
if (pipe_stb_i) begin
start = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if (ready) begin
pipe_stb_o = 1'b1;
if (pipe_ack_i) next_state = IDLE;
end
end
endcase
end
endmodule
| 8.417747 |
module tmu2_hdivops (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input signed [17:0] tex,
input signed [17:0] tey,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x_f,
output reg signed [11:0] y_f,
output reg signed [17:0] tsx_f,
output reg signed [17:0] tsy_f,
output reg diff_x_positive,
output reg [16:0] diff_x,
output reg diff_y_positive,
output reg [16:0] diff_y
);
always @(posedge sys_clk) begin
if (sys_rst) pipe_stb_o <= 1'b0;
else begin
if (pipe_ack_i) pipe_stb_o <= 1'b0;
if (pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= 1'b1;
if (tex > tsx) begin
diff_x_positive <= 1'b1;
diff_x <= tex - tsx;
end else begin
diff_x_positive <= 1'b0;
diff_x <= tsx - tex;
end
if (tey > tsy) begin
diff_y_positive <= 1'b1;
diff_y <= tey - tsy;
end else begin
diff_y_positive <= 1'b0;
diff_y <= tsy - tey;
end
x_f <= x;
y_f <= y;
tsx_f <= tsx;
tsy_f <= tsy;
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
| 7.083673 |
module tmu2_hinterp (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x_q,
input [16:0] diff_x_r,
input diff_y_positive,
input [16:0] diff_y_q,
input [16:0] diff_y_r,
input [10:0] dst_squarew,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] dx,
output reg signed [11:0] dy,
output signed [17:0] tx,
output signed [17:0] ty
);
reg load;
reg next_point;
/* Interpolators */
tmu2_geninterp18 i_tx (
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(tsx),
.positive(diff_x_positive),
.q(diff_x_q),
.r(diff_x_r),
.divisor({6'd0, dst_squarew}),
.o(tx)
);
tmu2_geninterp18 i_ty (
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(tsy),
.positive(diff_y_positive),
.q(diff_y_q),
.r(diff_y_r),
.divisor({6'd0, dst_squarew}),
.o(ty)
);
always @(posedge sys_clk) begin
if (load) begin
dx <= x;
dy <= y;
end else if (next_point) dx <= dx + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if (load) remaining_points <= dst_squarew - 11'd1;
else if (next_point) remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if (sys_rst) state <= IDLE;
else state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case (state)
IDLE: begin
if (pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if (pipe_ack_i) begin
if (last_point) next_state = IDLE;
else next_point = 1'b1;
end
end
endcase
end
endmodule
| 7.460486 |
module tmu2_mask (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [17:0] tex_hmask,
input [17:0] tex_vmask,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] dx_f,
output reg signed [11:0] dy_f,
output reg signed [17:0] tx_m,
output reg signed [17:0] ty_m
);
always @(posedge sys_clk) begin
if (sys_rst) pipe_stb_o <= 1'b0;
else begin
if (pipe_ack_i) pipe_stb_o <= 1'b0;
if (pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= 1'b1;
dx_f <= dx;
dy_f <= dy;
tx_m <= tx & tex_hmask;
ty_m <= ty & tex_vmask;
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
| 7.815317 |
module tmu2_mult2 (
input sys_clk,
input ce,
input [12:0] a,
input [12:0] b,
output reg [25:0] p
);
reg [25:0] temp;
always @(posedge sys_clk) begin
if (ce) begin
temp <= a * b;
p <= temp;
end
end
endmodule
| 6.532892 |
module tmu2_mult2 (
input sys_clk,
input ce,
input [12:0] a,
input [12:0] b,
output [25:0] p
);
DSP48 #(
.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2
.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2
.B_INPUT("DIRECT"), // B input DIRECT from fabric or CASCADE from another DSP48
.CARRYINREG(0), // Number of pipeline registers for the CARRYIN input, 0 or 1
.CARRYINSELREG(0), // Number of pipeline registers for the CARRYINSEL, 0 or 1
.CREG(0), // Number of pipeline registers on the C input, 0 or 1
.LEGACY_MODE("MULT18X18"), // Backward compatibility, NONE, MULT18X18 or MULT18X18S
.MREG(0), // Number of multiplier pipeline registers, 0 or 1
.OPMODEREG(0), // Number of pipeline regsiters on OPMODE input, 0 or 1
.PREG(1), // Number of pipeline registers on the P output, 0 or 1
.SUBTRACTREG(0) // Number of pipeline registers on the SUBTRACT input, 0 or 1
) DSP48_inst (
.BCOUT(), // 18-bit B cascade output
.P(p), // 48-bit product output
.PCOUT(), // 48-bit cascade output
.A(a), // 18-bit A data input
.B(b), // 18-bit B data input
.BCIN(18'd0), // 18-bit B cascade input
.C(48'd0), // 48-bit cascade input
.CARRYIN(1'b0), // Carry input signal
.CARRYINSEL(2'd0), // 2-bit carry input select
.CEA(ce), // A data clock enable input
.CEB(ce), // B data clock enable input
.CEC(1'b1), // C data clock enable input
.CECARRYIN(1'b1), // CARRYIN clock enable input
.CECINSUB(1'b1), // CINSUB clock enable input
.CECTRL(1'b1), // Clock Enable input for CTRL regsiters
.CEM(1'b1), // Clock Enable input for multiplier regsiters
.CEP(ce), // Clock Enable input for P regsiters
.CLK(sys_clk), // Clock input
.OPMODE(7'h35), // 7-bit operation mode input
.PCIN(48'd0), // 48-bit PCIN input
.RSTA(1'b0), // Reset input for A pipeline registers
.RSTB(1'b0), // Reset input for B pipeline registers
.RSTC(1'b0), // Reset input for C pipeline registers
.RSTCARRYIN(1'b0), // Reset input for CARRYIN registers
.RSTCTRL(1'b0), // Reset input for CTRL registers
.RSTM(1'b0), // Reset input for multiplier registers
.RSTP(1'b0), // Reset input for P pipeline registers
.SUBTRACT(1'b0) // SUBTRACT input
);
endmodule
| 6.532892 |
module tmu2_pixout #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
input pipe_stb_i,
output reg pipe_ack_o,
input [fml_depth-5-1:0] burst_addr,
input [15:0] burst_sel,
input [255:0] burst_do,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
output reg [7:0] fml_sel,
output reg [63:0] fml_do
);
reg [15:0] burst_sel_r;
reg [255:0] burst_do_r;
reg load;
always @(posedge sys_clk) begin
if (load) begin
fml_adr = {burst_addr, 5'd0};
burst_sel_r = burst_sel;
burst_do_r = burst_do;
end
end
reg [1:0] bcounter;
always @(posedge sys_clk) begin
case (bcounter)
2'd0: begin
fml_sel <= {
burst_sel_r[15],
burst_sel_r[15],
burst_sel_r[14],
burst_sel_r[14],
burst_sel_r[13],
burst_sel_r[13],
burst_sel_r[12],
burst_sel_r[12]
};
fml_do <= burst_do_r[255:192];
end
2'd1: begin
fml_sel <= {
burst_sel_r[11],
burst_sel_r[11],
burst_sel_r[10],
burst_sel_r[10],
burst_sel_r[9],
burst_sel_r[9],
burst_sel_r[8],
burst_sel_r[8]
};
fml_do <= burst_do_r[191:128];
end
2'd2: begin
fml_sel <= {
burst_sel_r[7],
burst_sel_r[7],
burst_sel_r[6],
burst_sel_r[6],
burst_sel_r[5],
burst_sel_r[5],
burst_sel_r[4],
burst_sel_r[4]
};
fml_do <= burst_do_r[127:64];
end
2'd3: begin
fml_sel <= {
burst_sel_r[3],
burst_sel_r[3],
burst_sel_r[2],
burst_sel_r[2],
burst_sel_r[1],
burst_sel_r[1],
burst_sel_r[0],
burst_sel_r[0]
};
fml_do <= burst_do_r[63:0];
end
endcase
end
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE = 2'd0;
parameter WAIT = 2'd1;
parameter XFER2 = 2'd2;
parameter XFER3 = 2'd3;
always @(posedge sys_clk) begin
if (sys_rst) state <= IDLE;
else state <= next_state;
end
always @(*) begin
next_state = state;
busy = 1'b1;
pipe_ack_o = 1'b0;
fml_stb = 1'b0;
load = 1'b0;
bcounter = 2'bxx;
case (state)
IDLE: begin
busy = 1'b0;
pipe_ack_o = 1'b1;
bcounter = 2'd0;
if (pipe_stb_i) begin
load = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
fml_stb = 1'b1;
bcounter = 2'd0;
if (fml_ack) begin
bcounter = 2'd1;
next_state = XFER2;
end
end
XFER2: begin
bcounter = 2'd2;
next_state = XFER3;
end
XFER3: begin
bcounter = 2'd3;
next_state = IDLE;
end
endcase
end
endmodule
| 7.094597 |
module tmu2_qpram #(
parameter depth = 11 /* < log2 of the capacity in bytes */
) (
input sys_clk,
input [depth-1:0] raa, /* < in bytes, 16-bit aligned */
output reg [15:0] rda,
input [depth-1:0] rab,
output reg [15:0] rdb,
input [depth-1:0] rac,
output reg [15:0] rdc,
input [depth-1:0] rad,
output reg [15:0] rdd,
input we,
input [depth-1:0] wa, /* < in bytes, 256-bit aligned */
input [255:0] wd
);
wire [127:0] rd128a;
wire [127:0] rd128b;
wire [127:0] rd128c;
wire [127:0] rd128d;
reg [ 2:0] rala;
reg [ 2:0] ralb;
reg [ 2:0] ralc;
reg [ 2:0] rald;
always @(posedge sys_clk) begin
rala <= raa[3:1];
ralb <= rab[3:1];
ralc <= rac[3:1];
rald <= rad[3:1];
end
always @(*) begin
case (rala)
3'd0: rda = rd128a[127:112];
3'd1: rda = rd128a[111:96];
3'd2: rda = rd128a[95:80];
3'd3: rda = rd128a[79:64];
3'd4: rda = rd128a[63:48];
3'd5: rda = rd128a[47:32];
3'd6: rda = rd128a[31:16];
default: rda = rd128a[15:0];
endcase
case (ralb)
3'd0: rdb = rd128b[127:112];
3'd1: rdb = rd128b[111:96];
3'd2: rdb = rd128b[95:80];
3'd3: rdb = rd128b[79:64];
3'd4: rdb = rd128b[63:48];
3'd5: rdb = rd128b[47:32];
3'd6: rdb = rd128b[31:16];
default: rdb = rd128b[15:0];
endcase
case (ralc)
3'd0: rdc = rd128c[127:112];
3'd1: rdc = rd128c[111:96];
3'd2: rdc = rd128c[95:80];
3'd3: rdc = rd128c[79:64];
3'd4: rdc = rd128c[63:48];
3'd5: rdc = rd128c[47:32];
3'd6: rdc = rd128c[31:16];
default: rdc = rd128c[15:0];
endcase
case (rald)
3'd0: rdd = rd128d[127:112];
3'd1: rdd = rd128d[111:96];
3'd2: rdd = rd128d[95:80];
3'd3: rdd = rd128d[79:64];
3'd4: rdd = rd128d[63:48];
3'd5: rdd = rd128d[47:32];
3'd6: rdd = rd128d[31:16];
default: rdd = rd128d[15:0];
endcase
end
tmu2_tdpram #(
.depth(depth - 4),
.width(128)
) ram0 (
.sys_clk(sys_clk),
.a (we ? {wa[depth-1:5], 1'b0} : raa[depth-1:4]),
.we(we),
.di(wd[255:128]),
.do(rd128a),
.a2 (we ? {wa[depth-1:5], 1'b1} : rab[depth-1:4]),
.we2(we),
.di2(wd[127:0]),
.do2(rd128b)
);
tmu2_tdpram #(
.depth(depth - 4),
.width(128)
) ram1 (
.sys_clk(sys_clk),
.a (we ? {wa[depth-1:5], 1'b0} : rac[depth-1:4]),
.we(we),
.di(wd[255:128]),
.do(rd128c),
.a2 (we ? {wa[depth-1:5], 1'b1} : rad[depth-1:4]),
.we2(we),
.di2(wd[127:0]),
.do2(rd128d)
);
endmodule
| 8.471702 |
module tmu2_qpram32 #(
parameter depth = 11 /* < log2 of the capacity in 32-bit words */
) (
input sys_clk,
/* 32-bit read port 1 */
input [depth-1:0] a1,
output [31:0] d1,
/* 32-bit read port 2 */
input [depth-1:0] a2,
output [31:0] d2,
/* 32-bit read port 3 */
input [depth-1:0] a3,
output [31:0] d3,
/* 32-bit read port 4 */
input [depth-1:0] a4,
output [31:0] d4,
/* 64-bit write port - we=1 disables read ports */
input we,
input [depth-1-1:0] aw,
input [63:0] dw
);
tmu2_dpram #(
.depth(depth),
.width(32)
) ram1 (
.sys_clk(sys_clk),
.a (we ? {aw, 1'b0} : a1),
.we(we),
.di(dw[63:32]),
.do(d1),
.a2 (we ? {aw, 1'b1} : a2),
.we2(we),
.di2(dw[31:0]),
.do2(d2)
);
tmu2_dpram #(
.depth(depth),
.width(32)
) ram2 (
.sys_clk(sys_clk),
.a (we ? {aw, 1'b0} : a3),
.we(we),
.di(dw[63:32]),
.do(d3),
.a2 (we ? {aw, 1'b1} : a4),
.we2(we),
.di2(dw[31:0]),
.do2(d4)
);
endmodule
| 7.824017 |
module tmu2_qpram32 #(
parameter depth = 11 /* < log2 of the capacity in 32-bit words */
) (
input sys_clk,
/* 32-bit read port 1 */
input [depth-1:0] a1,
output [31:0] d1,
/* 32-bit read port 2 */
input [depth-1:0] a2,
output [31:0] d2,
/* 32-bit read port 3 */
input [depth-1:0] a3,
output [31:0] d3,
/* 32-bit read port 4 */
input [depth-1:0] a4,
output [31:0] d4,
/* 64-bit write port - we=1 disables read ports */
input we,
input [depth-1-1:0] aw,
input [63:0] dw
);
wire [63:0] mem_d1;
wire [63:0] mem_d2;
wire [63:0] mem_d3;
wire [63:0] mem_d4;
reg r1, r2, r3, r4;
always @(posedge sys_clk) begin
r1 <= a1[0];
r2 <= a2[0];
r3 <= a3[0];
r4 <= a4[0];
end
tmu2_qpram #(
.depth(depth - 1),
.width(64)
) workaround (
.sys_clk(sys_clk),
.a1(a1[depth-1:1]),
.d1(mem_d1),
.a2(a2[depth-1:1]),
.d2(mem_d2),
.a3(a3[depth-1:1]),
.d3(mem_d3),
.a4(a4[depth-1:1]),
.d4(mem_d4),
.we(we),
.aw(aw),
.dw(dw)
);
assign d1 = r1 ? mem_d1[31:0] : mem_d1[63:32];
assign d2 = r2 ? mem_d2[31:0] : mem_d2[63:32];
assign d3 = r3 ? mem_d3[31:0] : mem_d3[63:32];
assign d4 = r4 ? mem_d4[31:0] : mem_d4[63:32];
endmodule
| 7.824017 |
module tmu2_serialize #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
input pipe_stb_i,
output reg pipe_ack_o,
input [fml_depth-5-1:0] tadra,
input [fml_depth-5-1:0] tadrb,
input [fml_depth-5-1:0] tadrc,
input [fml_depth-5-1:0] tadrd,
input miss_a,
input miss_b,
input miss_c,
input miss_d,
output reg pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-5-1:0] adr
);
/* Input registers */
reg load_en;
reg [fml_depth-5-1:0] r_tadra;
reg [fml_depth-5-1:0] r_tadrb;
reg [fml_depth-5-1:0] r_tadrc;
reg [fml_depth-5-1:0] r_tadrd;
reg r_miss_a;
reg r_miss_b;
reg r_miss_c;
reg r_miss_d;
always @(posedge sys_clk) begin
if (load_en) begin
r_tadra <= tadra;
r_tadrb <= tadrb;
r_tadrc <= tadrc;
r_tadrd <= tadrd;
r_miss_a <= miss_a;
r_miss_b <= miss_b;
r_miss_c <= miss_c;
r_miss_d <= miss_d;
end
end
/* Output multiplexer */
reg [1:0] adr_sel;
always @(*) begin
case (adr_sel)
2'd0: adr = r_tadra;
2'd1: adr = r_tadrb;
2'd2: adr = r_tadrc;
default: adr = r_tadrd;
endcase
end
/* Miss mask */
reg [3:0] missmask;
reg missmask_init;
reg missmask_we;
always @(posedge sys_clk) begin
if (missmask_init) missmask <= 4'b1111;
if (missmask_we) begin
case (adr_sel)
2'd0: missmask <= missmask & 4'b1110;
2'd1: missmask <= missmask & 4'b1101;
2'd2: missmask <= missmask & 4'b1011;
default: missmask <= missmask & 4'b0111;
endcase
end
end
/* Control logic */
reg state;
reg next_state;
parameter LOAD = 1'b0;
parameter SERIALIZE = 1'b1;
always @(posedge sys_clk) begin
if (sys_rst) state <= LOAD;
else state <= next_state;
end
always @(*) begin
next_state = state;
busy = 1'b0;
pipe_ack_o = 1'b0;
pipe_stb_o = 1'b0;
load_en = 1'b0;
adr_sel = 2'd0;
missmask_init = 1'b0;
missmask_we = 1'b0;
case (state)
LOAD: begin
pipe_ack_o = 1'b1;
load_en = 1'b1;
missmask_init = 1'b1;
if (pipe_stb_i) next_state = SERIALIZE;
end
SERIALIZE: begin
pipe_stb_o = 1'b1;
missmask_we = 1'b1;
if (r_miss_a & missmask[0]) adr_sel = 2'd0;
else if (r_miss_b & missmask[1]) adr_sel = 2'd1;
else if (r_miss_c & missmask[2]) adr_sel = 2'd2;
else if (r_miss_d & missmask[3]) adr_sel = 2'd3;
else begin
pipe_stb_o = 1'b0;
next_state = LOAD;
end
if (~pipe_ack_i) missmask_we = 1'b0;
end
endcase
end
endmodule
| 7.010921 |
module tmu2_split #(
parameter cache_depth = 13,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-1-1:0] dadr,
input [fml_depth-1:0] tadra,
input [fml_depth-1:0] tadrb,
input [fml_depth-1:0] tadrc,
input [fml_depth-1:0] tadrd,
input [5:0] x_frac,
input [5:0] y_frac,
input miss_a,
input miss_b,
input miss_c,
input miss_d,
/* to fragment FIFO */
output reg frag_pipe_stb_o,
input frag_pipe_ack_i,
output reg [fml_depth-1-1:0] frag_dadr,
output [cache_depth-1:0] frag_tadra, /* < texel cache addresses (in bytes) */
output [cache_depth-1:0] frag_tadrb,
output [cache_depth-1:0] frag_tadrc,
output [cache_depth-1:0] frag_tadrd,
output reg [5:0] frag_x_frac,
output reg [5:0] frag_y_frac,
output frag_miss_a,
output frag_miss_b,
output frag_miss_c,
output frag_miss_d,
/* to texel fetch unit */
output reg fetch_pipe_stb_o,
input fetch_pipe_ack_i,
output [fml_depth-5-1:0] fetch_tadra, /* < texel burst addresses (in 4*64 bit units) */
output [fml_depth-5-1:0] fetch_tadrb,
output [fml_depth-5-1:0] fetch_tadrc,
output [fml_depth-5-1:0] fetch_tadrd,
output fetch_miss_a,
output fetch_miss_b,
output fetch_miss_c,
output fetch_miss_d
);
/* shared data */
reg [fml_depth-1:0] r_tadra;
reg [fml_depth-1:0] r_tadrb;
reg [fml_depth-1:0] r_tadrc;
reg [fml_depth-1:0] r_tadrd;
reg r_miss_a;
reg r_miss_b;
reg r_miss_c;
reg r_miss_d;
assign frag_tadra = r_tadra[cache_depth-1:0];
assign frag_tadrb = r_tadrb[cache_depth-1:0];
assign frag_tadrc = r_tadrc[cache_depth-1:0];
assign frag_tadrd = r_tadrd[cache_depth-1:0];
assign frag_miss_a = r_miss_a;
assign frag_miss_b = r_miss_b;
assign frag_miss_c = r_miss_c;
assign frag_miss_d = r_miss_d;
assign fetch_tadra = r_tadra[fml_depth-1:5];
assign fetch_tadrb = r_tadrb[fml_depth-1:5];
assign fetch_tadrc = r_tadrc[fml_depth-1:5];
assign fetch_tadrd = r_tadrd[fml_depth-1:5];
assign fetch_miss_a = r_miss_a;
assign fetch_miss_b = r_miss_b;
assign fetch_miss_c = r_miss_c;
assign fetch_miss_d = r_miss_d;
reg data_valid;
always @(posedge sys_clk) begin
if (sys_rst) begin
frag_pipe_stb_o <= 1'b0;
fetch_pipe_stb_o <= 1'b0;
end else begin
if (frag_pipe_ack_i) frag_pipe_stb_o <= 1'b0;
if (fetch_pipe_ack_i) fetch_pipe_stb_o <= 1'b0;
if (pipe_ack_o) begin
frag_pipe_stb_o <= pipe_stb_i;
fetch_pipe_stb_o <= pipe_stb_i & (miss_a | miss_b | miss_c | miss_d);
frag_dadr <= dadr;
r_tadra <= tadra;
r_tadrb <= tadrb;
r_tadrc <= tadrc;
r_tadrd <= tadrd;
frag_x_frac <= x_frac;
frag_y_frac <= y_frac;
r_miss_a <= miss_a;
r_miss_b <= miss_b;
r_miss_c <= miss_c;
r_miss_d <= miss_d;
end
end
end
assign busy = frag_pipe_stb_o | fetch_pipe_stb_o;
assign pipe_ack_o = (~frag_pipe_stb_o & ~fetch_pipe_stb_o) | (frag_pipe_ack_i & fetch_pipe_ack_i);
endmodule
| 6.689224 |
module tmu2_vdiv (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx,
input diff_cy_positive,
input [16:0] diff_cy,
input diff_dx_positive,
input [16:0] diff_dx,
input diff_dy_positive,
input [16:0] diff_dy,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [17:0] ax_f,
output reg signed [17:0] ay_f,
output reg signed [17:0] bx_f,
output reg signed [17:0] by_f,
output reg diff_cx_positive_f,
output [16:0] diff_cx_q,
output [16:0] diff_cx_r,
output reg diff_cy_positive_f,
output [16:0] diff_cy_q,
output [16:0] diff_cy_r,
output reg diff_dx_positive_f,
output [16:0] diff_dx_q,
output [16:0] diff_dx_r,
output reg diff_dy_positive_f,
output [16:0] diff_dy_q,
output [16:0] diff_dy_r,
output reg signed [11:0] drx_f,
output reg signed [11:0] dry_f
);
/* Divider bank */
reg start;
wire ready;
tmu2_divider17 d_cx (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_cx),
.divisor({6'd0, dst_squareh}),
.ready(ready),
.quotient(diff_cx_q),
.remainder(diff_cx_r)
);
tmu2_divider17 d_cy (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_cy),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_cy_q),
.remainder(diff_cy_r)
);
tmu2_divider17 d_dx (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_dx),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_dx_q),
.remainder(diff_dx_r)
);
tmu2_divider17 d_dy (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_dy),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_dy_q),
.remainder(diff_dy_r)
);
/* Forward */
always @(posedge sys_clk) begin
if (start) begin
ax_f <= ax;
ay_f <= ay;
bx_f <= bx;
by_f <= by;
diff_cx_positive_f <= diff_cx_positive;
diff_cy_positive_f <= diff_cy_positive;
diff_dx_positive_f <= diff_dx_positive;
diff_dy_positive_f <= diff_dy_positive;
drx_f <= drx;
dry_f <= dry;
end
end
/* Glue logic */
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter WAIT = 1'b1;
always @(posedge sys_clk) begin
if (sys_rst) state = IDLE;
else state = next_state;
end
assign busy = state;
always @(*) begin
next_state = state;
start = 1'b0;
pipe_stb_o = 1'b0;
pipe_ack_o = 1'b0;
case (state)
IDLE: begin
pipe_ack_o = 1'b1;
if (pipe_stb_i) begin
start = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if (ready) begin
pipe_stb_o = 1'b1;
if (pipe_ack_i) next_state = IDLE;
end
end
endcase
end
endmodule
| 8.552412 |
module tmu2_vdivops (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input signed [17:0] cx,
input signed [17:0] cy,
input signed [17:0] dx,
input signed [17:0] dy,
input signed [11:0] drx,
input signed [11:0] dry,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [17:0] ax_f,
output reg signed [17:0] ay_f,
output reg signed [17:0] bx_f,
output reg signed [17:0] by_f,
output reg diff_cx_positive,
output reg [16:0] diff_cx,
output reg diff_cy_positive,
output reg [16:0] diff_cy,
output reg diff_dx_positive,
output reg [16:0] diff_dx,
output reg diff_dy_positive,
output reg [16:0] diff_dy,
output reg signed [11:0] drx_f,
output reg signed [11:0] dry_f
);
always @(posedge sys_clk) begin
if (sys_rst) pipe_stb_o <= 1'b0;
else begin
if (pipe_ack_i) pipe_stb_o <= 1'b0;
if (pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= 1'b1;
if (cx > ax) begin
diff_cx_positive <= 1'b1;
diff_cx <= cx - ax;
end else begin
diff_cx_positive <= 1'b0;
diff_cx <= ax - cx;
end
if (cy > ay) begin
diff_cy_positive <= 1'b1;
diff_cy <= cy - ay;
end else begin
diff_cy_positive <= 1'b0;
diff_cy <= ay - cy;
end
if (dx > bx) begin
diff_dx_positive <= 1'b1;
diff_dx <= dx - bx;
end else begin
diff_dx_positive <= 1'b0;
diff_dx <= bx - dx;
end
if (dy > by) begin
diff_dy_positive <= 1'b1;
diff_dy <= dy - by;
end else begin
diff_dy_positive <= 1'b0;
diff_dy <= by - dy;
end
ax_f <= ax;
ay_f <= ay;
bx_f <= bx;
by_f <= by;
drx_f <= drx;
dry_f <= dry;
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
| 6.960093 |
module tmu2_vinterp (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx_q,
input [16:0] diff_cx_r,
input diff_cy_positive,
input [16:0] diff_cy_q,
input [16:0] diff_cy_r,
input diff_dx_positive,
input [16:0] diff_dx_q,
input [16:0] diff_dx_r,
input diff_dy_positive,
input [16:0] diff_dy_q,
input [16:0] diff_dy_r,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x,
output reg signed [11:0] y,
output signed [17:0] tsx,
output signed [17:0] tsy,
output signed [17:0] tex,
output signed [17:0] tey
);
reg load;
reg next_point;
always @(posedge sys_clk) begin
if (load) x <= drx;
end
/* Interpolators */
tmu2_geninterp18 i_cx (
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ax),
.positive(diff_cx_positive),
.q(diff_cx_q),
.r(diff_cx_r),
.divisor({6'd0, dst_squareh}),
.o(tsx)
);
tmu2_geninterp18 i_cy (
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ay),
.positive(diff_cy_positive),
.q(diff_cy_q),
.r(diff_cy_r),
.divisor({6'd0, dst_squareh}),
.o(tsy)
);
tmu2_geninterp18 i_bx (
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(bx),
.positive(diff_dx_positive),
.q(diff_dx_q),
.r(diff_dx_r),
.divisor({6'd0, dst_squareh}),
.o(tex)
);
tmu2_geninterp18 i_by (
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(by),
.positive(diff_dy_positive),
.q(diff_dy_q),
.r(diff_dy_r),
.divisor({6'd0, dst_squareh}),
.o(tey)
);
/* y datapath */
always @(posedge sys_clk) begin
if (load) y <= dry;
else if (next_point) y <= y + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if (load) remaining_points <= dst_squareh - 11'd1;
else if (next_point) remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if (sys_rst) state <= IDLE;
else state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case (state)
IDLE: begin
if (pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if (pipe_ack_i) begin
if (last_point) next_state = IDLE;
else next_point = 1'b1;
end
end
endcase
end
endmodule
| 6.968315 |
module TM_ALU (
clk,
reset,
AvgTxLen, // 8-bit input
InstExed, // 8-bit input
CurTxLen, // 8-bit input
AvgTxLen_new, // 8-bit output
InstExed_new // 8-bit output
);
parameter WIDTH = 8; // Width of inputs
input clk, reset;
input [WIDTH - 1:0] AvgTxLen, CurTxLen;
input [WIDTH - 1:0] InstExed;
output [WIDTH - 1:0] AvgTxLen_new;
output [WIDTH - 1:0] InstExed_new;
// four stage registers
reg [3 * WIDTH - 1:0] stage_0;
reg [4 * WIDTH - 1:0] stage_1;
reg [4 * WIDTH - 1:0] stage_2;
reg [2 * WIDTH - 1:0] stage_3;
// Generates the output
assign {AvgTxLen_new, InstExed_new} = stage_3;
// Stage 1
always @(posedge clk, posedge reset) begin
if (reset) {stage_0, stage_1} <= 0;
else begin
//stage 0: launch the input into stage_0 register
stage_0 <= {AvgTxLen, InstExed, CurTxLen};
//stage 1: Multiplication
stage_1[4*WIDTH-1:2*WIDTH] <= stage_0[3*WIDTH-1:2*WIDTH] * stage_0[2*WIDTH-1:WIDTH];
stage_1[2*WIDTH-1:0] <= {stage_0[WIDTH-1:0], stage_0[2*WIDTH-1:WIDTH]};
end
end
// Stage 2
always @(posedge clk, posedge reset) begin
if (reset) stage_2 <= 0;
else begin
stage_2[4*WIDTH-1:2*WIDTH] <= stage_1[4*WIDTH-1:2*WIDTH] + stage_1[2*WIDTH-1:WIDTH];
stage_2[2*WIDTH-1:WIDTH] <= stage_1[WIDTH-1:0] + 1;
stage_2[WIDTH-1:0] <= stage_1[WIDTH-1:0] + 1;
end
end
// Stage 3
always @(posedge clk, posedge reset) begin
if (reset) stage_3 <= 0;
else begin
stage_3[2*WIDTH-1:WIDTH] <= (stage_2[4*WIDTH-1:2*WIDTH]) / (stage_2[2*WIDTH-1:WIDTH]);
stage_3[WIDTH-1:0] <= stage_2[WIDTH-1:0];
end
end
endmodule
| 7.460141 |
module TM_IF_ID_Stage;
reg clk, rst;
reg [31:0] PC_in, Ins_in;
wire [31:0] PC_out, Ins_out;
IF_ID_Stage stage1 (
PC_in,
Ins_in,
PC_out,
Ins_out,
clk,
rst
);
parameter t = 100;
always #(t / 2) clk = ~clk;
initial begin
$dumpfile("wave.vcd");
$dumpvars;
rst = 1;
clk = 0;
PC_in = 32'b0;
Ins_in = 32'b0;
#(2 * t) rst = 0;
#t PC_in = 32'b10;
Ins_in = 32'b10;
#t PC_in = 32'b100;
Ins_in = 32'b100;
#t PC_in = 32'b1000;
Ins_in = 32'b1000;
#t $finish;
end
endmodule
| 6.543354 |
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