code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module td_fused_top_fifo_w11_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w11_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w11_d2_S_shiftReg U_td_fused_top_fifo_w11_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w11_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w11_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd11;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w11_d7_S_shiftReg U_td_fused_top_fifo_w11_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w12_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w12_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w12_d7_S_shiftReg U_td_fused_top_fifo_w12_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w12_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w12_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w12_d8_S_shiftReg U_td_fused_top_fifo_w12_d8_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w12_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w12_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w12_d8_S_x_shiftReg U_td_fused_top_fifo_w12_d8_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w13_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd13;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w13_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd13;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w13_d2_S_shiftReg U_td_fused_top_fifo_w13_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w13_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd13;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w13_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd13;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w13_d7_S_shiftReg U_td_fused_top_fifo_w13_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w14_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd14;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
sr_8 <= sr_7;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin
case (a)
4'd0: q = sr_0;
4'd1: q = sr_1;
4'd2: q = sr_2;
4'd3: q = sr_3;
4'd4: q = sr_4;
4'd5: q = sr_5;
4'd6: q = sr_6;
4'd7: q = sr_7;
4'd8: q = sr_8;
default: q = sr_8;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w14_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd14;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 5'd1;
if (mOutPtr == 5'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 5'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 5'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w14_d9_S_shiftReg U_td_fused_top_fifo_w14_d9_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w15_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd15;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w15_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd15;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w15_d2_S_shiftReg U_td_fused_top_fifo_w15_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w15_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd15;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w15_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd15;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w15_d7_S_shiftReg U_td_fused_top_fifo_w15_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_shiftReg U_td_fused_top_fifo_w16_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x0_shiftReg U_td_fused_top_fifo_w16_d2_S_x0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x1_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x1_shiftReg U_td_fused_top_fifo_w16_d2_S_x1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x2_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x2 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x2_shiftReg U_td_fused_top_fifo_w16_d2_S_x2_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x3_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x3 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x3_shiftReg U_td_fused_top_fifo_w16_d2_S_x3_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x4_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x4 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x4_shiftReg U_td_fused_top_fifo_w16_d2_S_x4_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x5_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x5 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x5_shiftReg U_td_fused_top_fifo_w16_d2_S_x5_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x6_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x6 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x6_shiftReg U_td_fused_top_fifo_w16_d2_S_x6_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x7_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x7 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x7_shiftReg U_td_fused_top_fifo_w16_d2_S_x7_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x8_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x8 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x8_shiftReg U_td_fused_top_fifo_w16_d2_S_x8_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x9_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x9 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x9_shiftReg U_td_fused_top_fifo_w16_d2_S_x9_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w16_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w16_d2_S_x_shiftReg U_td_fused_top_fifo_w16_d2_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d8_S_shiftReg U_td_fused_top_fifo_w1_d8_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d8_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d8_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d8_S_x0_shiftReg U_td_fused_top_fifo_w1_d8_S_x0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d8_S_x_shiftReg U_td_fused_top_fifo_w1_d8_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
sr_8 <= sr_7;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin
case (a)
4'd0: q = sr_0;
4'd1: q = sr_1;
4'd2: q = sr_2;
4'd3: q = sr_3;
4'd4: q = sr_4;
4'd5: q = sr_5;
4'd6: q = sr_6;
4'd7: q = sr_7;
4'd8: q = sr_8;
default: q = sr_8;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 5'd1;
if (mOutPtr == 5'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 5'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 5'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d9_S_shiftReg U_td_fused_top_fifo_w1_d9_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
sr_8 <= sr_7;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin
case (a)
4'd0: q = sr_0;
4'd1: q = sr_1;
4'd2: q = sr_2;
4'd3: q = sr_3;
4'd4: q = sr_4;
4'd5: q = sr_5;
4'd6: q = sr_6;
4'd7: q = sr_7;
4'd8: q = sr_8;
default: q = sr_8;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 5'd1;
if (mOutPtr == 5'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 5'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 5'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d9_S_x0_shiftReg U_td_fused_top_fifo_w1_d9_S_x0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x1_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
sr_8 <= sr_7;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin
case (a)
4'd0: q = sr_0;
4'd1: q = sr_1;
4'd2: q = sr_2;
4'd3: q = sr_3;
4'd4: q = sr_4;
4'd5: q = sr_5;
4'd6: q = sr_6;
4'd7: q = sr_7;
4'd8: q = sr_8;
default: q = sr_8;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 5'd1;
if (mOutPtr == 5'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 5'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 5'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d9_S_x1_shiftReg U_td_fused_top_fifo_w1_d9_S_x1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x2_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
sr_8 <= sr_7;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin
case (a)
4'd0: q = sr_0;
4'd1: q = sr_1;
4'd2: q = sr_2;
4'd3: q = sr_3;
4'd4: q = sr_4;
4'd5: q = sr_5;
4'd6: q = sr_6;
4'd7: q = sr_7;
4'd8: q = sr_8;
default: q = sr_8;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x2 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 5'd1;
if (mOutPtr == 5'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 5'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 5'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d9_S_x2_shiftReg U_td_fused_top_fifo_w1_d9_S_x2_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
sr_8 <= sr_7;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, sr_8, a) begin
case (a)
4'd0: q = sr_0;
4'd1: q = sr_1;
4'd2: q = sr_2;
4'd3: q = sr_3;
4'd4: q = sr_4;
4'd5: q = sr_5;
4'd6: q = sr_6;
4'd7: q = sr_7;
4'd8: q = sr_8;
default: q = sr_8;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w1_d9_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd4;
parameter DEPTH = 5'd9;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 5'd1;
if (mOutPtr == 5'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 5'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 5'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w1_d9_S_x_shiftReg U_td_fused_top_fifo_w1_d9_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d2_S_shiftReg U_td_fused_top_fifo_w4_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d2_S_x_shiftReg U_td_fused_top_fifo_w4_d2_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d7_S_shiftReg U_td_fused_top_fifo_w4_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d7_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d7_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d7_S_x0_shiftReg U_td_fused_top_fifo_w4_d7_S_x0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d7_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d7_S_x_shiftReg U_td_fused_top_fifo_w4_d7_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d8_S_shiftReg U_td_fused_top_fifo_w4_d8_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d8_S_x0_shiftReg U_td_fused_top_fifo_w4_d8_S_x0_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_x1_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_x1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d8_S_x1_shiftReg U_td_fused_top_fifo_w4_d8_S_x1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d8_S_x_shiftReg U_td_fused_top_fifo_w4_d8_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w5_d2_S_shiftReg U_td_fused_top_fifo_w5_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w5_d2_S_x_shiftReg U_td_fused_top_fifo_w5_d2_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w5_d7_S_shiftReg U_td_fused_top_fifo_w5_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d7_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w5_d7_S_x_shiftReg U_td_fused_top_fifo_w5_d7_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w5_d8_S_shiftReg U_td_fused_top_fifo_w5_d8_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w5_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd5;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w5_d8_S_x_shiftReg U_td_fused_top_fifo_w5_d8_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w6_d2_S_shiftReg U_td_fused_top_fifo_w6_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d7_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d7_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w6_d7_S_shiftReg U_td_fused_top_fifo_w6_d7_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d7_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
default: q = sr_6;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d7_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd7;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w6_d7_S_x_shiftReg U_td_fused_top_fifo_w6_d7_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w6_d8_S_shiftReg U_td_fused_top_fifo_w6_d8_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d8_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w6_d8_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w6_d8_S_x_shiftReg U_td_fused_top_fifo_w6_d8_S_x_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
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